Repository: cliffordwolf/riscv-formal Branch: main Commit: a5443540f965 Files: 282 Total size: 3.0 MB Directory structure: gitextract_1qfjctmx/ ├── .github/ │ └── workflows/ │ └── ci.yml ├── .gitignore ├── COPYING ├── CodeOfConduct ├── README.md ├── bus/ │ ├── rvfi_bus_axi4.sv │ └── rvfi_bus_util.sv ├── checks/ │ ├── genchecks.py │ ├── rvfi_bus_dmem_check.sv │ ├── rvfi_bus_dmem_fault_check.sv │ ├── rvfi_bus_dmem_io_order_check.sv │ ├── rvfi_bus_dmem_io_read_check.sv │ ├── rvfi_bus_dmem_io_read_fault_check.sv │ ├── rvfi_bus_dmem_io_write_check.sv │ ├── rvfi_bus_dmem_io_write_fault_check.sv │ ├── rvfi_bus_imem_check.sv │ ├── rvfi_bus_imem_fault_check.sv │ ├── rvfi_causal_check.sv │ ├── rvfi_causal_io_check.sv │ ├── rvfi_causal_mem_check.sv │ ├── rvfi_channel.sv │ ├── rvfi_cover_check.sv │ ├── rvfi_csr_ill_check.sv │ ├── rvfi_csrc_any_check.sv │ ├── rvfi_csrc_const_check.sv │ ├── rvfi_csrc_hpm_check.sv │ ├── rvfi_csrc_inc_check.sv │ ├── rvfi_csrc_upcnt_check.sv │ ├── rvfi_csrc_zero_check.sv │ ├── rvfi_csrw_check.sv │ ├── rvfi_dmem_check.sv │ ├── rvfi_fault_check.sv │ ├── rvfi_hang_check.sv │ ├── rvfi_ill_check.sv │ ├── rvfi_imem_check.sv │ ├── rvfi_insn_check.sv │ ├── rvfi_liveness_check.sv │ ├── rvfi_macros.py │ ├── rvfi_macros.vh │ ├── rvfi_pc_bwd_check.sv │ ├── rvfi_pc_fwd_check.sv │ ├── rvfi_reg_check.sv │ ├── rvfi_testbench.sv │ └── rvfi_unique_check.sv ├── cores/ │ ├── VexRiscv/ │ │ ├── .gitignore │ │ ├── README.md │ │ ├── VexRiscv.v │ │ ├── checks.cfg │ │ ├── disasm.py │ │ ├── dmemcheck.sby │ │ ├── dmemcheck.sv │ │ ├── imemcheck.sby │ │ ├── imemcheck.sv │ │ └── wrapper.sv │ ├── nerv/ │ │ ├── .gitignore │ │ ├── COPYING │ │ ├── Makefile │ │ ├── README.md │ │ ├── axi_cache/ │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── axi_ram.v │ │ │ ├── checks_axi.cfg │ │ │ ├── checks_internal.cfg │ │ │ ├── firmware.c │ │ │ ├── nerv_axi_cache.sv │ │ │ ├── nerv_axi_cache_dcache.sv │ │ │ ├── nerv_axi_cache_icache.sv │ │ │ ├── testbench_axi.sv │ │ │ ├── testbench_internal.sv │ │ │ ├── verify_axi.sby │ │ │ ├── verify_axi.sv │ │ │ ├── wrapper_axi.sv │ │ │ └── wrapper_internal.sv │ │ ├── cexdata.sh │ │ ├── checks.cfg │ │ ├── disasm.py │ │ ├── examples/ │ │ │ └── icebreaker/ │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── firmware.c │ │ │ ├── firmware.s │ │ │ ├── icebreaker.pcf │ │ │ ├── sections.lds │ │ │ ├── testbench.gtkw │ │ │ ├── testbench.sv │ │ │ └── top.v │ │ ├── firmware.c │ │ ├── firmware.s │ │ ├── imemcheck.sby │ │ ├── imemcheck.sv │ │ ├── nerv.sv │ │ ├── nervsoc.sv │ │ ├── sections.lds │ │ ├── testbench.gtkw │ │ ├── testbench.sv │ │ ├── trace.gtkw │ │ ├── vectors.s │ │ └── wrapper.sv │ ├── picorv32/ │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── README.md │ │ ├── cexdata.sh │ │ ├── checks.cfg │ │ ├── checks.gtkw │ │ ├── complete.sby │ │ ├── complete.sv │ │ ├── cover.sby │ │ ├── cover.sv │ │ ├── disasm.py │ │ ├── dmemcheck.sv │ │ ├── equiv.sh │ │ ├── honest.sby │ │ ├── honest.sv │ │ ├── imemcheck.sv │ │ ├── testbugs.sh │ │ └── wrapper.sv │ ├── rocket/ │ │ ├── .gitignore │ │ ├── README.md │ │ ├── cexdata.sh │ │ ├── checks.gtkw │ │ ├── cover.gtkw │ │ ├── cover.sby │ │ ├── cover.sv │ │ ├── coverage.sby │ │ ├── coverage.sv │ │ ├── decode.sh │ │ ├── disasm.py │ │ ├── generate.sh │ │ ├── muldivlen.py │ │ ├── muldivlen.sby │ │ ├── muldivlen.sv │ │ ├── rocketrvfi.sv │ │ ├── testbench.cc │ │ ├── testbench.sh │ │ └── wrapper.sv │ └── serv/ │ ├── .gitignore │ ├── README.md │ ├── cexdata.sh │ ├── checks.cfg │ ├── cover.gtkw │ ├── cover.sby │ ├── cover.sv │ ├── disasm.py │ ├── generate.sh │ ├── sbram.sv │ └── wrapper.sv ├── docs/ │ ├── config.md │ ├── csrs.md │ ├── examplebugs.md │ ├── procedure.md │ ├── quickstart.md │ ├── references.md │ └── rvfi.md ├── insns/ │ ├── generate.py │ ├── insn_add.v │ ├── insn_addi.v │ ├── insn_addiw.v │ ├── insn_addw.v │ ├── insn_and.v │ ├── insn_andi.v │ ├── insn_auipc.v │ ├── insn_beq.v │ ├── insn_bge.v │ ├── insn_bgeu.v │ ├── insn_blt.v │ ├── insn_bltu.v │ ├── insn_bne.v │ ├── insn_c_add.v │ ├── insn_c_addi.v │ ├── insn_c_addi16sp.v │ ├── insn_c_addi4spn.v │ ├── insn_c_addiw.v │ ├── insn_c_addw.v │ ├── insn_c_and.v │ ├── insn_c_andi.v │ ├── insn_c_beqz.v │ ├── insn_c_bnez.v │ ├── insn_c_j.v │ ├── insn_c_jal.v │ ├── insn_c_jalr.v │ ├── insn_c_jr.v │ ├── insn_c_ld.v │ ├── insn_c_ldsp.v │ ├── insn_c_li.v │ ├── insn_c_lui.v │ ├── insn_c_lw.v │ ├── insn_c_lwsp.v │ ├── insn_c_mv.v │ ├── insn_c_or.v │ ├── insn_c_sd.v │ ├── insn_c_sdsp.v │ ├── insn_c_slli.v │ ├── insn_c_srai.v │ ├── insn_c_srli.v │ ├── insn_c_sub.v │ ├── insn_c_subw.v │ ├── insn_c_sw.v │ ├── insn_c_swsp.v │ ├── insn_c_xor.v │ ├── insn_div.v │ ├── insn_divu.v │ ├── insn_divuw.v │ ├── insn_divw.v │ ├── insn_jal.v │ ├── insn_jalr.v │ ├── insn_lb.v │ ├── insn_lbu.v │ ├── insn_ld.v │ ├── insn_lh.v │ ├── insn_lhu.v │ ├── insn_lui.v │ ├── insn_lw.v │ ├── insn_lwu.v │ ├── insn_mul.v │ ├── insn_mulh.v │ ├── insn_mulhsu.v │ ├── insn_mulhu.v │ ├── insn_mulw.v │ ├── insn_or.v │ ├── insn_ori.v │ ├── insn_rem.v │ ├── insn_remu.v │ ├── insn_remuw.v │ ├── insn_remw.v │ ├── insn_sb.v │ ├── insn_sd.v │ ├── insn_sh.v │ ├── insn_sll.v │ ├── insn_slli.v │ ├── insn_slliw.v │ ├── insn_sllw.v │ ├── insn_slt.v │ ├── insn_slti.v │ ├── insn_sltiu.v │ ├── insn_sltu.v │ ├── insn_sra.v │ ├── insn_srai.v │ ├── insn_sraiw.v │ ├── insn_sraw.v │ ├── insn_srl.v │ ├── insn_srli.v │ ├── insn_srliw.v │ ├── insn_srlw.v │ ├── insn_sub.v │ ├── insn_subw.v │ ├── insn_sw.v │ ├── insn_xor.v │ ├── insn_xori.v │ ├── isa_rv32i.txt │ ├── isa_rv32i.v │ ├── isa_rv32ic.txt │ ├── isa_rv32ic.v │ ├── isa_rv32im.txt │ ├── isa_rv32im.v │ ├── isa_rv32imc.txt │ ├── isa_rv32imc.v │ ├── isa_rv64i.txt │ ├── isa_rv64i.v │ ├── isa_rv64ic.txt │ ├── isa_rv64ic.v │ ├── isa_rv64im.txt │ ├── isa_rv64im.v │ ├── isa_rv64imc.txt │ └── isa_rv64imc.v ├── monitor/ │ └── generate.py └── tests/ ├── coverage/ │ ├── .gitignore │ ├── coverage.sby │ ├── coverage.sv │ ├── generate.py │ ├── riscv_rv32i_insn.v │ ├── riscv_rv32ic_insn.v │ ├── riscv_rv64i_insn.v │ └── riscv_rv64ic_insn.v ├── semantics/ │ ├── .gitignore │ ├── Makefile │ ├── cexformat.py │ ├── makejob.py │ └── top.sv └── spike/ ├── .gitignore ├── common.h └── generate.py ================================================ FILE CONTENTS ================================================ ================================================ FILE: .github/workflows/ci.yml ================================================ name: ci on: push: pull_request: workflow_dispatch: schedule: - cron: '30 1 * * *' jobs: build: runs-on: ubuntu-latest steps: - uses: actions/checkout@v3 - uses: YosysHQ/setup-oss-cad-suite@v2 with: github-token: ${{ secrets.GITHUB_TOKEN }} - name: Run checks run: | cd cores/nerv make check -j$(nproc) cd ../picorv32 wget -O picorv32.v https://raw.githubusercontent.com/YosysHQ/picorv32/master/picorv32.v python3 ../../checks/genchecks.py make -C checks -j$(nproc) ================================================ FILE: .gitignore ================================================ /cores/.gitignore ================================================ FILE: COPYING ================================================ Copyright (C) 2017 Claire Xenia Wolf Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ================================================ FILE: CodeOfConduct ================================================ Contributor Covenant Code of Conduct Our Pledge In the interest of fostering an open and welcoming environment, we as contributors and maintainers pledge to making participation in our project and our community a harassment-free experience for everyone, regardless of age, body size, disability, ethnicity, gender identity and expression, level of experience, nationality, personal appearance, race, religion, or sexual identity and orientation. Our Standards Examples of behavior that contributes to creating a positive environment include: * Using welcoming and inclusive language * Being respectful of differing viewpoints and experiences * Gracefully accepting constructive criticism * Focusing on what is best for the community * Showing empathy towards other community members Examples of unacceptable behavior by participants include: * The use of sexualized language or imagery and unwelcome sexual attention or advances * Trolling, insulting/derogatory comments, and personal or political attacks * Public or private harassment * Publishing others' private information, such as a physical or electronic address, without explicit permission * Other conduct which could reasonably be considered inappropriate in a professional setting Our Responsibilities Project maintainers are responsible for clarifying the standards of acceptable behavior and are expected to take appropriate and fair corrective action in response to any instances of unacceptable behavior. Project maintainers have the right and responsibility to remove, edit, or reject comments, commits, code, wiki edits, issues, and other contributions that are not aligned to this Code of Conduct, or to ban temporarily or permanently any contributor for other behaviors that they deem inappropriate, threatening, offensive, or harmful. Scope This Code of Conduct applies both within project spaces and in public spaces when an individual is representing the project or its community. Examples of representing a project or community include using an official project e-mail address, posting via an official social media account, or acting as an appointed representative at an online or offline event. Representation of a project may be further defined and clarified by project maintainers. Enforcement Instances of abusive, harassing, or otherwise unacceptable behavior may be reported by contacting the project team at contact@yosyshq.com. All complaints will be reviewed and investigated and will result in a response that is deemed necessary and appropriate to the circumstances. The project team is obligated to maintain confidentiality with regard to the reporter of an incident. Further details of specific enforcement policies may be posted separately. Project maintainers who do not follow or enforce the Code of Conduct in good faith may face temporary or permanent repercussions as determined by other members of the project's leadership. Attribution This Code of Conduct is adapted from the Contributor Covenant, version 1.4, available at http://contributor-covenant.org/version/1/4/ ================================================ FILE: README.md ================================================ RISC-V Formal Verification Framework ==================================== **This is work in progress. The interfaces described here are likely to change as the project matures.** About ----- `riscv-formal` is a framework for formal verification of RISC-V processors. It consists of the following components: - A processor-independent formal description of the RISC-V ISA - A set of formal testbenches for each processor supported by the framework - The specification for the [RISC-V Formal Interface (RVFI)](docs/rvfi.md) that must be implemented by a processor core to interface with `riscv-formal`. - Some auxiliary proofs and scripts, for example to prove correctness of the ISA spec agains riscv-isa-sim. See [cores/picorv32/](cores/picorv32/) for example bindings for the PicoRV32 processor core. A processor core usually will implement RVFI as an optional feature that is only enabled for verification. Sequential equivalence check can be used to prove equivalence of the processor versions with and without RVFI. The current focus is on implementing formal models of all instructions from the RISC-V RV32I and RV64I ISAs, and formally verifying those models against the models used in the RISC-V "Spike" ISA simulator. `riscv-formal` uses the FOSS SymbiYosys formal verification flow. All properties are expressed using immediate assertions/assumptions for maximal compatibility with other tools. Table of contents ----------------- - [Quickstart Guide](docs/quickstart.md) - [The RVFI Interface Specification](docs/rvfi.md) - [RISC-V Formal CSR Sematics](docs/csrs.md) - [Configuration macros used by riscv-formal](docs/config.md) - [The riscv-formal Verification Procedure](docs/procedure.md) - [Examples of bugs found with riscv-formal](docs/examplebugs.md) - [References and related work](docs/references.md) Configuring a new RISC-V processor ---------------------------------- 1. Create a `riscv-formal/cores//` directory 2. Write a wrapper module that instantiates the core under test and abstracts models of necessary peripherals (usually just memory) - Use the [RVFI helper macros](docs/config.md#rvfi_wires-rvfi_outputs-rvfi_inputs-rvfi_conn) `RVFI_OUTPUTS` and `RVFI_CONN` for quickly defining wrapper connections - See [picorv32/wrapper.sv](cores/picorv32/wrapper.sv) for a simple example wrapper 3. Write a `checks.cfg` config file for the new core - See [nerv/checks.cfg](cores/nerv/checks.cfg) for an example utilising most of the checks - Refer to [The riscv-formal Verification Procedure](docs/procedure.md) for a complete guide on available checks, and a more detailed view of using `genchecks.py` 4. Generate checks with `python3 ../../checks/genchecks.py` from the `` directory - Checks are generated in `riscv-formal/cores//checks` 5. Run checks with `make -C checks j$(nproc)` ### Notes - The [quickstart guide](docs/quickstart.md) goes through the process of running riscv-formal with some of the included cores. It is recommended to follow this guide before adding a new core. - See [picorv32/Makefile](cores/picorv32/Makefile) for an example makefile to manage generation and execution of checks. - Out of tree generation with `genchecks.py` is not currently supported. - Refer to [docs/config.md](docs/config.md) and [docs/procedure.md](docs/procedure.md) for a breakdown of how to use riscv-formal checks without using `genchecks.py`. - The [cover check](docs/procedure.md#cover) can be used to help determine the depth needed for the core to reach certain states as needed for other checks. ================================================ FILE: bus/rvfi_bus_axi4.sv ================================================ // RVFI_BUS observer for AXI4 interfaces // // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. // NOTE: When a W transfer happens before the corresponding AW transfer, the // data appears on the RVFI_BUS signals starting with the cycle of that AW // transfer, processing at most one W transfer per cycle. This can cause the // whole burst to be delayed, potentially also delaying the processing of a // following burst's W transfers even when that burst's AW transfer arrived for // the first W transfer. // // An alternative that could process the W transfers before the AW transfers // would have to let the solver guess the write addresses. This could cause // spurious writes to appear that cause an assertion violation in a cycle // before the actual AW transfer arrives that would constrain the guessed write // address to be correctly guessed, as the AW transfer cycle is never // considered by the solver due to the assertion being violated prior to // reaching that. // // Hence, delaying the processing of W transfers until the corresponding AW // transfer happens is less likely to cause false positives for most reasonable // properties to check. In any case, writes appear on the RVFI_BUS signals in // the exact same order as they appear on the AXI bus. When all AW transfers // are guaranteed to arrive in time for their their first W transfer, the // writes also appear on the same cycle as the W transfers carrying the data. module rvfi_bus_axi4_observer_write #( parameter AXI_DATA_WIDTH = 32, parameter AXI_ADDRESS_WIDTH = 32, parameter AXI_ID_WIDTH = 1, parameter AXI_AWUSER_WIDTH = 1, parameter AXI_WUSER_WIDTH = 1, parameter AXI_BUSER_WIDTH = 1, parameter AXI_ID_MASK = 0, parameter AXI_ID = 0, parameter IGNORE_PROT_DATA_INSN = 0, parameter DEPTH = 2, localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8 ) ( input clock, input reset, // Write Address Channel (AW) input [AXI_ID_WIDTH-1:0] axi_awid, input [AXI_ADDRESS_WIDTH-1:0] axi_awaddr, input [3:0] axi_awregion, input [7:0] axi_awlen, input [2:0] axi_awsize, input [1:0] axi_awburst, input axi_awlock, input [3:0] axi_awcache, input [2:0] axi_awprot, input [3:0] axi_awqos, input [AXI_AWUSER_WIDTH-1:0] axi_awuser, input axi_awvalid, input axi_awready, // Write Data Channel (W) input [AXI_DATA_WIDTH-1:0] axi_wdata, input [AXI_STRB_WIDTH-1:0] axi_wstrb, input axi_wlast, input [AXI_WUSER_WIDTH-1:0] axi_wuser, input axi_wvalid, input axi_wready, // Write Response Channel (B) input [AXI_ID_WIDTH-1:0] axi_bid, input [1:0] axi_bresp, input [AXI_BUSER_WIDTH-1:0] axi_buser, input axi_bvalid, input axi_bready `RVFI_BUS_CHANNEL_OUTPUTS ); wire aw_transfer = axi_awvalid && axi_awready; wire w_transfer = axi_wvalid && axi_wready; wire b_transfer = axi_bvalid && axi_bready; wire [AXI_ID_WIDTH-1:0] out_awid; wire [AXI_ADDRESS_WIDTH-1:0] out_awaddr; wire [7:0] out_awlen; wire [2:0] out_awsize; wire [1:0] out_awburst; wire [2:0] out_awprot; wire [AXI_DATA_WIDTH-1:0] out_wdata; wire [AXI_STRB_WIDTH-1:0] out_wstrb; wire out_wlast; wire aw_fifo_in_ready, aw_fifo_out_valid; wire w_fifo_in_ready, w_fifo_out_valid; wire fut_b_fifo_in_ready, fut_b_fifo_out_valid; `rvformal_rand_reg [1:0] rand_bresp; wire [1:0] out_aw_bresp; wire [1:0] out_bresp; rvfi_bus_util_fifo #( .DEPTH(DEPTH), .WIDTH(AXI_ID_WIDTH + AXI_ADDRESS_WIDTH + 8 + 3 + 2 + 3 + 2) ) aw_fifo ( .clock(clock), .reset(reset), .in_data( {axi_awid, axi_awaddr, axi_awlen, axi_awsize, axi_awburst, axi_awprot, rand_bresp}), .out_data({out_awid, out_awaddr, out_awlen, out_awsize, out_awburst, out_awprot, out_aw_bresp}), .in_valid(aw_transfer), .in_ready(aw_fifo_in_ready), .out_ready(w_fifo_out_valid && out_wlast), .out_valid(aw_fifo_out_valid) ); rvfi_bus_util_fifo #( .DEPTH(DEPTH), .WIDTH(AXI_DATA_WIDTH + AXI_STRB_WIDTH + 1) ) w_fifo ( .clock(clock), .reset(reset), .in_data( {axi_wdata, axi_wstrb, axi_wlast}), .out_data({out_wdata, out_wstrb, out_wlast}), .in_valid(w_transfer), .in_ready(w_fifo_in_ready), .out_ready(aw_fifo_out_valid), .out_valid(w_fifo_out_valid) ); // We enqueue a guessed bresp value when we see an AW transfer and dequeue // it when we see a B transfer, then assuming we made a correct guess. // This doesn't have the same problem described in the note above, as the B // channel is read by the AXI manager and any reasonable property of the // AXI manager regarding the B response cannot fail before the AXI manager // actually reads that response. rvfi_bus_util_fifo #( .DEPTH(DEPTH), .WIDTH(2) ) fut_b_fifo ( .clock(clock), .reset(reset), .in_data( {rand_bresp}), .out_data({out_bresp}), .in_valid(aw_transfer), .in_ready(fut_b_fifo_in_ready), .out_ready(b_transfer), .out_valid(fut_b_fifo_out_valid) ); always @(posedge clock) begin if (!reset) begin if (aw_transfer) DEPTH_too_small_AW: assert (aw_fifo_in_ready); if (aw_transfer) DEPTH_too_small_B: assert (fut_b_fifo_in_ready); if (w_transfer) DEPTH_too_small_W: assert (w_fifo_in_ready); end end reg [7:0] burst_counter; reg [AXI_ADDRESS_WIDTH-1:0] burst_offset; always @(posedge clock) begin if (w_fifo_out_valid && aw_fifo_out_valid) begin if (!reset) assert (out_wlast == (burst_counter == out_awlen)); if (out_wlast) begin burst_counter <= 0; burst_offset <= 0; end else begin burst_counter <= burst_counter + 1'b1; burst_offset <= burst_offset + (1'b1 << out_awsize); end end if (reset) begin burst_counter <= 0; burst_offset <= 0; end end // Mask of address bits that can change between transfers of the same burst // given the current burst type. This is used to compute the unaligned // transfer address. reg [AXI_ADDRESS_WIDTH-1:0] burst_mask; // Log2 of the burst length, used to compute the burst mask for the WRAP // burst type. reg [2:0] burst_len_log2; // Current transfer address, not aligned. // // When unaligned, it stays unaligned for the entire burst and always // increments by the burst size. This means that transfers past the initial // can include bytes below this address down to the next size aligned // address. wire [AXI_ADDRESS_WIDTH-1:0] unaligned_addr = ( burst_mask & (out_awaddr + burst_offset)) | (~burst_mask & out_awaddr); // Current transfer address, aligned to the burst size. wire [AXI_ADDRESS_WIDTH-1:0] size_aligned_addr = unaligned_addr & ('1 << out_awsize); // Current transfer address, aligned to the bus width. wire [AXI_ADDRESS_WIDTH-1:0] bus_aligned_addr = unaligned_addr & ~(AXI_DATA_WIDTH/8 - 1); // Mask of data bytes/strobe bits that are active given the current // transfer address and burst size. wire [AXI_DATA_WIDTH/8-1:0] size_mask = (~('1 << (1 << out_awsize))) << (size_aligned_addr ^ bus_aligned_addr); // Mask of data bytes/strobe bits that are active given the current // misalignment (subset of size_mask). After the initial transfer in a // burst, this is always the same as size_mask, as the transfer includes // the remaining bytes that did not fit into the previous transfer. wire [AXI_DATA_WIDTH/8-1:0] alignment_mask = burst_counter ? size_mask : size_mask & (size_mask << (unaligned_addr ^ size_aligned_addr)); always @* begin case (out_awlen) 8'h00: burst_len_log2 = 0; 8'h01: burst_len_log2 = 1; 8'h03: burst_len_log2 = 2; 8'h07: burst_len_log2 = 3; 8'h0f: burst_len_log2 = 4; default: begin burst_len_log2 = 0; AWLEN_invalid_for_AWBURST: assert (reset || !aw_fifo_out_valid || out_awburst != 2'b10); end endcase case (out_awburst) // FIXED 2'b00: burst_mask = '0; // INCR 2'b01: burst_mask = '1; // WRAP 2'b10: burst_mask = ~('1 << (out_awsize + burst_len_log2)); // reserved default: begin burst_mask = '0; AWBURST_invalid: assert (reset || !aw_fifo_out_valid); end endcase end // The AXI spec says that the wstrb bits are restricted by the burst size // and alignment. // // Choosing to pass on invalid wstrb bits or to implicitly clear them could // hide bugs in designs that do produce such invalid strobe bits, so we are // checking this here. always @(posedge clock) begin if (!reset && rvfi_bus_valid) WSTRB_invalid: assert (!(out_wstrb & ~alignment_mask)); end always @(posedge clock) begin if (!reset) begin if (b_transfer) begin unexpected_B_transfer: assert (fut_b_fifo_out_valid); // Only assume this when we can actually pull a not-yet // constrained value from the FIFO, so that this assumption // cannot hide any AXI signalling errors. assume ((out_bresp == axi_bresp) || !fut_b_fifo_out_valid); end end end `ifdef RISCV_FORMAL_BUS initial begin BUSLEN_too_small: assert (AXI_DATA_WIDTH <= `RISCV_FORMAL_BUSLEN); XLEN_too_small: assert (AXI_ADDRESS_WIDTH <= `RISCV_FORMAL_XLEN); end `endif assign rvfi_bus_rdata = '0; assign rvfi_bus_wdata = out_wdata; assign rvfi_bus_wmask = out_wstrb; assign rvfi_bus_addr = bus_aligned_addr; assign rvfi_bus_insn = !IGNORE_PROT_DATA_INSN && out_awprot[2]; assign rvfi_bus_data = IGNORE_PROT_DATA_INSN || !out_awprot[2]; assign rvfi_bus_rmask = 0; assign rvfi_bus_fault = out_aw_bresp[1]; assign rvfi_bus_valid = w_fifo_out_valid && aw_fifo_out_valid && ((out_awid & AXI_ID_MASK) == AXI_ID); endmodule module rvfi_bus_axi4_observer_read #( parameter AXI_DATA_WIDTH = 32, parameter AXI_ADDRESS_WIDTH = 32, parameter AXI_ID_WIDTH = 1, parameter AXI_ARUSER_WIDTH = 1, parameter AXI_RUSER_WIDTH = 1, parameter AXI_ID_MASK = 0, parameter AXI_ID = 0, parameter DEPTH = 2, parameter IGNORE_PROT_DATA_INSN = 0 ) ( input clock, input reset, // Read Address Channel (AR) input [AXI_ID_WIDTH-1:0] axi_arid, input [AXI_ADDRESS_WIDTH-1:0] axi_araddr, input [3:0] axi_arregion, input [7:0] axi_arlen, input [2:0] axi_arsize, input [1:0] axi_arburst, input axi_arlock, input [3:0] axi_arcache, input [2:0] axi_arprot, input [3:0] axi_arqos, input [AXI_ARUSER_WIDTH-1:0] axi_aruser, input axi_arvalid, input axi_arready, // Read Data Channel (R) input [AXI_ID_WIDTH-1:0] axi_rid, input [AXI_DATA_WIDTH-1:0] axi_rdata, input [1:0] axi_rresp, input axi_rlast, input [AXI_RUSER_WIDTH-1:0] axi_ruser, input axi_rvalid, input axi_rready `RVFI_BUS_CHANNEL_OUTPUTS ); wire ar_transfer = axi_arvalid && axi_arready; wire r_transfer = axi_rvalid && axi_rready; wire ar_transfer_match = ar_transfer && ((axi_arid & AXI_ID_MASK) == AXI_ID); wire r_transfer_match = r_transfer && ((axi_rid & AXI_ID_MASK) == AXI_ID); wire [AXI_ADDRESS_WIDTH-1:0] out_araddr; wire [7:0] out_arlen; wire [2:0] out_arsize; wire [1:0] out_arburst; wire [2:0] out_arprot; wire fifo_in_ready, fifo_out_valid; rvfi_bus_util_fifo #( .DEPTH(DEPTH), .WIDTH(AXI_ADDRESS_WIDTH + 8 + 3 + 2 + 3) ) aw_fifo ( .clock(clock), .reset(reset), .in_data( {axi_araddr, axi_arlen, axi_arsize, axi_arburst, axi_arprot}), .out_data({out_araddr, out_arlen, out_arsize, out_arburst, out_arprot}), .in_valid(ar_transfer_match), .in_ready(fifo_in_ready), .out_ready(r_transfer_match && axi_rlast), .out_valid(fifo_out_valid) ); always @(posedge clock) begin if (!reset) begin if (ar_transfer_match) DEPTH_too_small: assert (fifo_in_ready); if (r_transfer_match) unexpected_R_transfer: assert (fifo_out_valid); end end reg [7:0] burst_counter; reg [AXI_ADDRESS_WIDTH-1:0] burst_offset; always @(posedge clock) begin if (r_transfer_match) begin if (!reset) RLAST_invalid: assert (axi_rlast == (burst_counter == out_arlen)); if (axi_rlast) begin burst_counter <= 0; burst_offset <= 0; end else begin burst_counter <= burst_counter + 1'b1; burst_offset <= burst_offset + (1 << out_arsize); end end if (reset) begin burst_counter <= 0; burst_offset <= 0; end end // Mask of address bits that can change between transfers of the same burst // given the current burst type. This is used to compute the unaligned // transfer address. reg [AXI_ADDRESS_WIDTH-1:0] burst_mask; // Log2 of the burst length, used to compute the burst mask for the WRAP // burst type. reg [2:0] burst_len_log2; // Current transfer address, not aligned. // // When unaligned, it stays unaligned for the entire burst and always // increments by the burst size. This means that transfers past the initial // can include bytes below this address down to the next size aligned // address. wire [AXI_ADDRESS_WIDTH-1:0] unaligned_addr = ( burst_mask & (out_araddr + burst_offset)) | (~burst_mask & out_araddr); // Current transfer address, aligned to the burst size. wire [AXI_ADDRESS_WIDTH-1:0] size_aligned_addr = unaligned_addr & ('1 << out_arsize); // Current transfer address, aligned to the bus width. wire [AXI_ADDRESS_WIDTH-1:0] bus_aligned_addr = unaligned_addr & ~(AXI_DATA_WIDTH/8 - 1); // Mask of data bytes/strobe bits that are active given the current // transfer address and burst size. wire [AXI_DATA_WIDTH/8-1:0] size_mask = (~('1 << (1 << out_arsize))) << (size_aligned_addr ^ bus_aligned_addr); // Mask of data bytes/strobe bits that are active given the current // misalignment (subset of size_mask). After the initial transfer in a // burst, this is always the same as size_mask, as the transfer includes // the remaining bytes that did not fit into the previous transfer. wire [AXI_DATA_WIDTH/8-1:0] alignment_mask = burst_counter ? size_mask : size_mask & (size_mask << (unaligned_addr ^ size_aligned_addr)); always @* begin case (out_arlen) 8'h00: burst_len_log2 = 0; 8'h01: burst_len_log2 = 1; 8'h03: burst_len_log2 = 2; 8'h07: burst_len_log2 = 3; 8'h0f: burst_len_log2 = 4; default: begin burst_len_log2 = 0; ARLEN_invalid_for_ARBURST: assert (reset || !fifo_out_valid || out_arburst != 2'b10); end endcase case (out_arburst) // FIXED 2'b00: burst_mask = '0; // INCR 2'b01: burst_mask = '1; // WRAP 2'b10: burst_mask = ~('1 << (out_arsize + burst_len_log2)); // reserved default: begin burst_mask = '0; ARBURST_invalid: assert (reset || !fifo_out_valid); end endcase end `ifdef RISCV_FORMAL_BUS initial begin BUSLEN_too_small: assert (AXI_DATA_WIDTH <= `RISCV_FORMAL_BUSLEN); XLEN_too_small: assert (AXI_ADDRESS_WIDTH <= `RISCV_FORMAL_XLEN); end `endif assign rvfi_bus_rdata = axi_rdata; assign rvfi_bus_wdata = '0; assign rvfi_bus_addr = bus_aligned_addr; assign rvfi_bus_rmask = alignment_mask; assign rvfi_bus_insn = IGNORE_PROT_DATA_INSN || out_arprot[2]; assign rvfi_bus_data = IGNORE_PROT_DATA_INSN || !out_arprot[2]; assign rvfi_bus_wmask = 0; assign rvfi_bus_fault = axi_rresp[1]; assign rvfi_bus_valid = r_transfer_match; endmodule module rvfi_bus_axi4_abstract_read #( parameter AXI_ADDRESS_WIDTH = 32, parameter AXI_DATA_WIDTH = 32, parameter AXI_ID_WIDTH = 1, parameter AXI_ARUSER_WIDTH = 1, parameter AXI_RUSER_WIDTH = 1, parameter DEPTH = 2 ) ( input wire clock, input wire reset, // Read Address Channel (AR) input wire [AXI_ID_WIDTH-1:0] axi_arid, input wire [AXI_ADDRESS_WIDTH-1:0] axi_araddr, input wire [3:0] axi_arregion, input wire [7:0] axi_arlen, input wire [2:0] axi_arsize, input wire [1:0] axi_arburst, input wire axi_arlock, input wire [3:0] axi_arcache, input wire [2:0] axi_arprot, input wire [3:0] axi_arqos, input wire [AXI_ARUSER_WIDTH-1:0] axi_aruser, input wire axi_arvalid, output var axi_arready, // Read Data Channel (R) output var [AXI_ID_WIDTH-1:0] axi_rid, output var [AXI_DATA_WIDTH-1:0] axi_rdata, output var [1:0] axi_rresp, output var axi_rlast, output var [AXI_RUSER_WIDTH-1:0] axi_ruser, output var axi_rvalid, input wire axi_rready ); `rvformal_rand_reg rand_arready; `rvformal_rand_reg [AXI_ID_WIDTH-1:0] rand_rid; `rvformal_rand_reg [AXI_DATA_WIDTH-1:0] rand_rdata; `rvformal_rand_reg [1:0] rand_rresp; `rvformal_rand_reg rand_rlast; `rvformal_rand_reg [AXI_RUSER_WIDTH-1:0] rand_ruser; `rvformal_rand_reg rand_rvalid; logic reset_q; // Read Address Channel (AR) logic [AXI_ID_WIDTH-1:0] axi_arid_q; logic [AXI_ADDRESS_WIDTH-1:0] axi_araddr_q; logic [3:0] axi_arregion_q; logic [7:0] axi_arlen_q; logic [2:0] axi_arsize_q; logic [1:0] axi_arburst_q; logic axi_arlock_q; logic [3:0] axi_arcache_q; logic [2:0] axi_arprot_q; logic [3:0] axi_arqos_q; logic [AXI_ARUSER_WIDTH-1:0] axi_aruser_q; logic axi_arvalid_q; logic axi_arready_q; // Read Data Channel (R) logic [AXI_ID_WIDTH-1:0] axi_rid_q; logic [AXI_DATA_WIDTH-1:0] axi_rdata_q; logic [1:0] axi_rresp_q; logic axi_rlast_q; logic [AXI_RUSER_WIDTH-1:0] axi_ruser_q; logic axi_rvalid_q; logic axi_rready_q; always @(posedge clock) begin reset_q <= reset; axi_arid_q <= axi_arid; axi_araddr_q <= axi_araddr; axi_arregion_q <= axi_arregion; axi_arlen_q <= axi_arlen; axi_arsize_q <= axi_arsize; axi_arburst_q <= axi_arburst; axi_arlock_q <= axi_arlock; axi_arcache_q <= axi_arcache; axi_arprot_q <= axi_arprot; axi_arqos_q <= axi_arqos; axi_aruser_q <= axi_aruser; axi_arvalid_q <= axi_arvalid; axi_arready_q <= axi_arready; axi_rid_q <= axi_rid; axi_rdata_q <= axi_rdata; axi_rresp_q <= axi_rresp; axi_rlast_q <= axi_rlast; axi_ruser_q <= axi_ruser; axi_rvalid_q <= axi_rvalid; axi_rready_q <= axi_rready; end wire logic ar_transfer = axi_arvalid && axi_arready; wire logic ar_transfer_q = axi_arvalid_q && axi_arready_q; wire logic r_transfer = axi_rvalid && axi_rready; wire logic r_transfer_q = axi_rvalid_q && axi_rready_q; wire logic r_new = axi_rvalid && (!axi_rvalid_q || axi_rready_q); wire logic r_stable = axi_rvalid_q && !axi_rvalid_q; assign axi_arready = rand_arready; assign axi_rid = r_stable ? axi_rid_q : rand_rid; assign axi_rdata = r_stable ? axi_rdata_q : rand_rdata; assign axi_rresp = r_stable ? axi_rresp_q : rand_rresp; assign axi_rlast = r_stable ? axi_rlast_q : rand_rlast; assign axi_ruser = r_stable ? axi_ruser_q : rand_ruser; assign axi_rvalid = r_stable ? axi_rvalid_q : rand_rvalid; logic [AXI_ID_WIDTH-1:0] read_id [0:DEPTH]; logic [AXI_ID_WIDTH-1:0] read_id_q [0:DEPTH]; logic [7:0] read_len [0:DEPTH]; logic [7:0] read_len_q [0:DEPTH]; logic [DEPTH:0] ar_mask; logic [DEPTH:0] ar_mask_q; logic matched; logic last_read; always @* begin for (int i = 0; i <= DEPTH; i++) begin read_id[i] = read_id_q[i]; read_len[i] = read_len_q[i]; end matched = 0; last_read = 0; ar_mask = 0; if (!reset) begin ar_mask = ar_mask_q; if (ar_transfer_q) begin // insert new read burst assume(!ar_mask[0]); for (int i = 0; i <= DEPTH; i++) begin if (!ar_mask[i]) begin read_id[i] = axi_arid_q; read_len[i] = axi_arlen_q; end end ar_mask = (ar_mask << 1) | 1'b1; end if (r_new) begin // update oldest read burst with a matching id, removing it // when it is completed for (int i = DEPTH; i >= 0; i--) begin if (!matched && ar_mask[i] && read_id[i] == axi_rid) begin matched = 1; if (read_len[i] > 0) begin read_len[i] -= 1; end else begin last_read = 1; end end if (last_read) begin if (i > 0) begin read_len[i] = read_len[i - 1]; end end end assume (matched); assume (axi_rlast == last_read); if (last_read) begin ar_mask >>= 1; end end end end always @(posedge clock) begin for (int i = 0; i <= DEPTH; i++) begin read_id_q[i] <= read_id[i]; read_len_q[i] <= read_len[i]; end ar_mask_q <= ar_mask; end endmodule module rvfi_bus_axi4_abstract_write #( parameter AXI_ADDRESS_WIDTH = 32, parameter AXI_DATA_WIDTH = 32, parameter AXI_ID_WIDTH = 1, parameter AXI_AWUSER_WIDTH = 1, parameter AXI_WUSER_WIDTH = 1, parameter AXI_BUSER_WIDTH = 1, parameter DEPTH = 2, localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8 ) ( input wire clock, input wire reset, // Write Address Channel (AW) input wire [AXI_ID_WIDTH-1:0] axi_awid, input wire [AXI_ADDRESS_WIDTH-1:0] axi_awaddr, input wire [3:0] axi_awregion, input wire [7:0] axi_awlen, input wire [2:0] axi_awsize, input wire [1:0] axi_awburst, input wire axi_awlock, input wire [3:0] axi_awcache, input wire [2:0] axi_awprot, input wire [3:0] axi_awqos, input wire [AXI_AWUSER_WIDTH-1:0] axi_awuser, input wire axi_awvalid, output var axi_awready, // Write Data Channel (W) input wire [AXI_DATA_WIDTH-1:0] axi_wdata, input wire [AXI_STRB_WIDTH-1:0] axi_wstrb, input wire axi_wlast, input wire [AXI_WUSER_WIDTH-1:0] axi_wuser, input wire axi_wvalid, output var axi_wready, // Write Response Channel (B) output var [AXI_ID_WIDTH-1:0] axi_bid, output var [1:0] axi_bresp, output var [AXI_BUSER_WIDTH-1:0] axi_buser, output var axi_bvalid, input wire axi_bready ); `rvformal_rand_reg rand_awready; `rvformal_rand_reg rand_wready; `rvformal_rand_reg [AXI_ID_WIDTH-1:0] rand_bid; `rvformal_rand_reg [1:0] rand_bresp; `rvformal_rand_reg [AXI_BUSER_WIDTH-1:0] rand_buser; `rvformal_rand_reg rand_bvalid; logic reset_q; // Write Address Channel (AW) logic [AXI_ID_WIDTH-1:0] axi_awid_q; logic [AXI_ADDRESS_WIDTH-1:0] axi_awaddr_q; logic [3:0] axi_awregion_q; logic [7:0] axi_awlen_q; logic [2:0] axi_awsize_q; logic [1:0] axi_awburst_q; logic axi_awlock_q; logic [3:0] axi_awcache_q; logic [2:0] axi_awprot_q; logic [3:0] axi_awqos_q; logic [AXI_AWUSER_WIDTH-1:0] axi_awuser_q; logic axi_awvalid_q; logic axi_awready_q; // Write Data Channel (W) logic [AXI_DATA_WIDTH-1:0] axi_wdata_q; logic [AXI_STRB_WIDTH-1:0] axi_wstrb_q; logic axi_wlast_q; logic [AXI_WUSER_WIDTH-1:0] axi_wuser_q; logic axi_wvalid_q; logic axi_wready_q; // Write Response Channel (B) logic [AXI_ID_WIDTH-1:0] axi_bid_q; logic [1:0] axi_bresp_q; logic [AXI_BUSER_WIDTH-1:0] axi_buser_q; logic axi_bvalid_q; logic axi_bready_q; always @(posedge clock) begin reset_q <= reset; axi_awid_q <= axi_awid; axi_awaddr_q <= axi_awaddr; axi_awregion_q <= axi_awregion; axi_awlen_q <= axi_awlen; axi_awsize_q <= axi_awsize; axi_awburst_q <= axi_awburst; axi_awlock_q <= axi_awlock; axi_awcache_q <= axi_awcache; axi_awprot_q <= axi_awprot; axi_awqos_q <= axi_awqos; axi_awuser_q <= axi_awuser; axi_awvalid_q <= axi_awvalid; axi_awready_q <= axi_awready; axi_wdata_q <= axi_wdata; axi_wstrb_q <= axi_wstrb; axi_wlast_q <= axi_wlast; axi_wuser_q <= axi_wuser; axi_wvalid_q <= axi_wvalid; axi_wready_q <= axi_wready; axi_bid_q <= axi_bid; axi_bresp_q <= axi_bresp; axi_buser_q <= axi_buser; axi_bvalid_q <= axi_bvalid; axi_bready_q <= axi_bready; end wire logic aw_transfer = axi_awvalid && axi_awready; wire logic aw_transfer_q = axi_awvalid_q && axi_awready_q; wire logic w_transfer = axi_wvalid && axi_wready; wire logic w_transfer_q = axi_wvalid_q && axi_wready_q; wire logic b_transfer = axi_bvalid && axi_bready; wire logic b_transfer_q = axi_bvalid_q && axi_bready_q; wire logic b_stable = axi_bvalid_q && !axi_bready_q; wire logic b_new = axi_bvalid && (!axi_bvalid_q || axi_bready_q); assign axi_awready = rand_awready; assign axi_wready = rand_wready; assign axi_bid = b_stable ? axi_bid_q : rand_bid; assign axi_bresp = b_stable ? axi_bresp_q : rand_bresp; assign axi_buser = b_stable ? axi_buser_q : rand_buser; assign axi_bvalid = b_stable ? axi_bvalid_q : rand_bvalid; logic [AXI_ID_WIDTH-1:0] write_id [0:DEPTH]; logic [AXI_ID_WIDTH-1:0] write_id_q [0:DEPTH]; logic [DEPTH:0] aw_mask; logic [DEPTH:0] aw_mask_q; logic [DEPTH:0] wlast_mask; logic [DEPTH:0] wlast_mask_q; logic matched; always @* begin for (int i = 0; i <= DEPTH; i++) begin write_id[i] = write_id_q[i]; end aw_mask = 0; wlast_mask = 0; matched = 0; if (!reset) begin aw_mask = aw_mask_q; wlast_mask = wlast_mask_q; if (aw_transfer_q) begin assume (!aw_mask[0]); for (int i = 0; i <= DEPTH; i++) begin if (!aw_mask[i]) begin write_id[i] = axi_awid_q; end end aw_mask = (aw_mask << 1) | 1'b1; end if (w_transfer_q && axi_wlast_q) begin assume (wlast_mask[0] == 0); wlast_mask = (wlast_mask << 1) | 1'b1; end if (b_new) begin for (int i = DEPTH; i >= 0; i--) begin if (!matched && aw_mask[i] && wlast_mask[i] && write_id[i] == axi_bid) begin matched = 1; end if (matched) begin if (i > 0) begin write_id[i] = write_id[i-1]; end end end assume (matched); aw_mask = aw_mask >> 1; wlast_mask = wlast_mask >> 1; end end end always @(posedge clock) begin aw_mask_q <= aw_mask; wlast_mask_q <= wlast_mask; for (int i = 0; i <= DEPTH; i++) begin write_id_q[i] <= write_id[i]; end end endmodule ================================================ FILE: bus/rvfi_bus_util.sv ================================================ // Utility code for RVFI_BUS observers // // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_bus_util_fifo_stage #( parameter WIDTH = 8 ) ( input clock, input reset, input in_valid, output in_ready, input [WIDTH-1:0] in_data, output out_valid, input out_ready, output [WIDTH-1:0] out_data ); reg [WIDTH-1:0] buffered; reg buffer_valid; wire in_txn = in_valid && in_ready; wire out_txn = out_valid && out_ready; assign out_data = buffer_valid ? buffered : in_data; assign in_ready = out_ready || !buffer_valid; assign out_valid = in_valid || buffer_valid; always @(posedge clock) begin if (reset) begin buffer_valid <= 0; end else begin if (in_txn != out_txn) buffer_valid <= in_txn; end if (in_txn) buffered <= in_data; end endmodule module rvfi_bus_util_fifo #( parameter WIDTH = 8, parameter DEPTH = 3 ) ( input clock, input reset, input in_valid, output in_ready, input [WIDTH-1:0] in_data, output out_valid, input out_ready, output [WIDTH-1:0] out_data ); wire [WIDTH-1:0] stage_data [0:DEPTH]; wire [DEPTH:0] stage_valid; wire [DEPTH:0] stage_ready; genvar i; generate for (i = 0; i < DEPTH; i = i + 1) begin rvfi_bus_util_fifo_stage #(.WIDTH(WIDTH)) stage ( .clock(clock), .reset(reset), .in_data(stage_data[i]), .out_data(stage_data[i+1]), .in_valid(stage_valid[i]), .out_valid(stage_valid[i+1]), .in_ready(stage_ready[i]), .out_ready(stage_ready[i+1]) ); end endgenerate assign stage_valid[0] = in_valid; assign stage_data[0] = in_data; assign in_ready = stage_ready[0]; assign out_valid = stage_valid[DEPTH]; assign stage_ready[DEPTH] = out_ready; assign out_data = stage_data[DEPTH]; endmodule ================================================ FILE: checks/genchecks.py ================================================ #!/usr/bin/env python3 # # Copyright (C) 2017 Claire Xenia Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. import os, sys, shutil, re from functools import reduce nret = 1 isa = "rv32i" ilen = 32 xlen = 32 buslen = 32 nbus = 1 csrs = set() custom_csrs = set() illegal_csrs = set() csr_tests = {} csr_spec = None compr = False depths = list() groups = [None] blackbox = False cfgname = "checks" basedir = f"{os.getcwd()}/../.." corename = os.getcwd().split("/")[-1] solver = "boolector" dumpsmt2 = False abspath = False sbycmd = "sby" config = dict() mode = "bmc" if len(sys.argv) > 1: assert len(sys.argv) == 2 cfgname = sys.argv[1] print(f"Reading {cfgname}.cfg.") with open(f"{cfgname}.cfg", "r") as f: cfgsection = None cfgsubsection = None for line in f: line = line.strip() if line.startswith("#"): continue if line.startswith("[") and line.endswith("]"): cfgsection = line.lstrip("[").rstrip("]") cfgsubsection = None if cfgsection.startswith("assume ") or cfgsection == "assume": cfgsubsection = cfgsection.split()[1:] cfgsection = "assume" continue if cfgsection is not None: if cfgsubsection is None: if cfgsection not in config: config[cfgsection] = "" config[cfgsection] += f"{line}\n" else: if cfgsection not in config: config[cfgsection] = [] config[cfgsection].append((cfgsubsection, line)) if "options" in config: for line in config["options"].split("\n"): line = line.split() if len(line) == 0: continue elif line[0] == "nret": assert len(line) == 2 nret = int(line[1]) elif line[0] == "isa": assert len(line) == 2 isa = line[1] elif line[0] == "blackbox": assert len(line) == 1 blackbox = True elif line[0] == "solver": assert len(line) == 2 solver = line[1] elif line[0] == "dumpsmt2": assert len(line) == 1 dumpsmt2 = True elif line[0] == "abspath": assert len(line) == 1 abspath = True elif line[0] == "mode": assert len(line) == 2 assert(line[1] in ("bmc", "prove", "cover")) mode = line[1] elif line[0] == "buslen": assert len(line) == 2 buslen = int(line[1]) elif line[0] == "nbus": assert len(line) == 2 nbus = int(line[1]) elif line[0] == "csr_spec": assert len(line) == 2 csr_spec = line[1] else: print(line) assert 0 if "64" in isa: xlen = 64 if "c" in isa: compr = True def add_csr_tests(name, test_str): # use regex to split by spaces, unless those spaces are inside quotation marks # e.g. const="32'h dead_beef" is one match not two # const="32'h 0"_mask="32'h dead_beef" is also one match tests = re.findall("((?:\S*?\"[^\"]*\")+|\S+)", test_str) csr_tests[name] = tests def add_csr(csr_str): try: (name, tests) = csr_str.split(maxsplit=1) add_csr_tests(name, tests) except ValueError: # no tests name = csr_str.strip() csrs.add(name) return name def mask_bits(test: str, bits: "list[int]", mask_len: int, invert=False): mask = reduce(lambda x, y: x | 1<= 0: try: csr_mask = str(csr_test[mask_idx:]).split('=', maxsplit=1)[1].strip('"') except IndexError: # no value provided print(csr_test) assert 0 csr_test = csr_test[:mask_idx] if csr_test.startswith("const"): try: constval = str(csr_test).split('=', maxsplit=1)[1].strip('"') except IndexError: # no value provided constval = "rdata_shadow" check = f"{pf}csrc_const_{csr_name}" check_name = f"csrc_const" elif csr_test.startswith("hpm"): try: hpmevent = str(csr_test).split('=', maxsplit=1)[1].strip('"') except IndexError: # no value provided pass hpmcounter = str(csr_name).replace("event", "counter") if hpmcounter not in csrs: csrs.add(hpmcounter) check = f"{pf}csrc_hpm_{csr_name}" check_name = f"csrc_hpm" else: check = f"{pf}csrc_{csr_test}_{csr_name}" check_name =f"csrc_{csr_test}" else: check = f"{pf}csrc_{csr_name}" check_name = "csrc" hargs["check"] = check_name if chanidx is not None: depth_cfg = get_depth_cfg([f"{pf}{check_name}", check, f"{pf}{check_name}_ch{chanidx:d}", f"{check}_ch{chanidx:d}"]) hargs["channel"] = f"{chanidx:d}" check = f"{check}_ch{chanidx:d}" else: depth_cfg = get_depth_cfg([f"{check_name}", check]) else: hargs["check"] = check check = pf + check if chanidx is not None: depth_cfg = get_depth_cfg([check, f"{check}_ch{chanidx:d}"]) hargs["channel"] = f"{chanidx:d}" check = f"{check}_ch{chanidx:d}" else: depth_cfg = get_depth_cfg([check]) if depth_cfg is None: return if start is not None: start = depth_cfg[start] else: start = 1 if trig is not None: trig = depth_cfg[trig] if depth is not None: depth = depth_cfg[depth] hargs["start"] = start hargs["depth"] = depth hargs["depth_plus"] = depth + 1 hargs["skip"] = depth hargs["checkch"] = check hargs["xmode"] = hargs["mode"] if check == "cover" or "csrc_hpm" in check: hargs["xmode"] = "cover" if test_disabled(check): return consistency_checks.add(check) with open(f"{cfgname}/{check}.sby", "w") as sby_file: print_hfmt(sby_file, """ : [options] : mode @xmode@ : expect pass,fail : append @append@ : depth @depth_plus@ : skip @skip@ : : [engines] : @engine@ : : [script] """, **hargs) if "script-defines" in config: print_hfmt(sby_file, config["script-defines"], **hargs) if (f"script-defines {hargs['check']}") in config: print_hfmt(sby_file, config[f"script-defines {hargs['check']}"], **hargs) sv_files = [f"{check}.sv"] if "verilog-files" in config: sv_files += hfmt(config["verilog-files"], **hargs) vhdl_files = [] if "vhdl-files" in config: vhdl_files += hfmt(config["vhdl-files"], **hargs) if len(sv_files): print(f"read -sv {' '.join(sv_files)}", file=sby_file) if len(vhdl_files): print(f"read -vhdl {' '.join(vhdl_files)}", file=sby_file) if "script-sources" in config: print_hfmt(sby_file, config["script-sources"], **hargs) print_hfmt(sby_file, """ : prep -flatten -nordff -top rvfi_testbench """, **hargs) if "script-link" in config: print_hfmt(sby_file, config["script-link"], **hargs) print_hfmt(sby_file, """ : chformal -early : : [files] : @basedir@/checks/rvfi_macros.vh : @basedir@/checks/rvfi_channel.sv : @basedir@/checks/rvfi_testbench.sv : @basedir@/checks/rvfi_@check@_check.sv : : [file defines.sv] """, **hargs) print_hfmt(sby_file, """ : `define RISCV_FORMAL : `define RISCV_FORMAL_NRET @nret@ : `define RISCV_FORMAL_XLEN @xlen@ : `define RISCV_FORMAL_ILEN @ilen@ : `define RISCV_FORMAL_CHECKER rvfi_@check@_check : `define RISCV_FORMAL_RESET_CYCLES @start@ : `define RISCV_FORMAL_CHECK_CYCLE @depth@ """, **hargs) if "assume" in config: print("`define RISCV_FORMAL_ASSUME", file=sby_file) if mode == "prove": print("`define RISCV_FORMAL_UNBOUNDED", file=sby_file) for csr in sorted(csrs): print(f"`define RISCV_FORMAL_CSR_{csr.upper()}", file=sby_file) if csr_mode: localdict = locals() if "constval" in localdict: print(f"`define RISCV_FORMAL_CSRC_CONSTVAL {constval}", file=sby_file) if "hpmevent" in localdict: print(f"`define RISCV_FORMAL_CSRC_HPMEVENT {hpmevent}", file=sby_file) if "hpmcounter" in localdict: print(f"`define RISCV_FORMAL_CSRC_HPMCOUNTER {hpmcounter}", file=sby_file) if "csr_mask" in localdict: print(f"`define RISCV_FORMAL_CSRC_MASK {csr_mask}", file=sby_file) print(f"`define RISCV_FORMAL_CSRC_NAME {csr_name}", file=sby_file) if custom_csrs: print_custom_csrs(sby_file) if blackbox and hargs["check"] != "liveness": print("`define RISCV_FORMAL_BLACKBOX_ALU", file=sby_file) if blackbox and hargs["check"] != "reg": print("`define RISCV_FORMAL_BLACKBOX_REGS", file=sby_file) if chanidx is not None: print(f"`define RISCV_FORMAL_CHANNEL_IDX {chanidx:d}", file=sby_file) if trig is not None: print(f"`define RISCV_FORMAL_TRIG_CYCLE {trig:d}", file=sby_file) if bus_mode: print_hfmt(sby_file, """ : `define RISCV_FORMAL_BUS : `define RISCV_FORMAL_NBUS @nbus@ : `define RISCV_FORMAL_BUSLEN @buslen@ """, **hargs) if hargs["check"] in ("liveness", "hang"): print("`define RISCV_FORMAL_FAIRNESS", file=sby_file) if "defines" in config: print_hfmt(sby_file, config["defines"], **hargs) if (f"defines {hargs['check']}") in config: print_hfmt(sby_file, config[f"defines {hargs['check']}"], **hargs) print_hfmt(sby_file, """ : `include "rvfi_macros.vh" : : [file @checkch@.sv] : `include "defines.sv" : `include "rvfi_channel.sv" : `include "rvfi_testbench.sv" : `include "rvfi_@check@_check.sv" """, **hargs) if check == pf+"cover": print_hfmt(sby_file, """ : : [file cover_stmts.vh] : @cover@ """, **hargs) if "assume" in config: print("", file=sby_file) print("[file assume_stmts.vh]", file=sby_file) for pat, line in config["assume"]: enabled = True for p in pat: if p.startswith("!"): p = p[1:] enabled = False else: enabled = True if re.match(p, check): enabled = not enabled break if enabled: print(line, file=sby_file) for grp in groups: for i in range(nret): check_cons(grp, "reg", chanidx=i, start=0, depth=1) check_cons(grp, "pc_fwd", chanidx=i, start=0, depth=1) check_cons(grp, "pc_bwd", chanidx=i, start=0, depth=1) check_cons(grp, "liveness", chanidx=i, start=0, trig=1, depth=2) check_cons(grp, "unique", chanidx=i, start=0, trig=1, depth=2) check_cons(grp, "causal", chanidx=i, start=0, depth=1) check_cons(grp, "causal_mem", chanidx=i, start=0, depth=1) check_cons(grp, "causal_io", chanidx=i, start=0, depth=1) check_cons(grp, "ill", chanidx=i, depth=0) check_cons(grp, "fault", chanidx=i, depth=0) check_cons(grp, "bus_imem", chanidx=i, start=0, depth=1, bus_mode=True) check_cons(grp, "bus_imem_fault", chanidx=i, start=0, depth=1, bus_mode=True) check_cons(grp, "bus_dmem", chanidx=i, start=0, depth=1, bus_mode=True) check_cons(grp, "bus_dmem_fault", chanidx=i, start=0, depth=1, bus_mode=True) check_cons(grp, "bus_dmem_io_read", chanidx=i, start=0, depth=1, bus_mode=True) check_cons(grp, "bus_dmem_io_read_fault", chanidx=i, start=0, depth=1, bus_mode=True) check_cons(grp, "bus_dmem_io_write", chanidx=i, start=0, depth=1, bus_mode=True) check_cons(grp, "bus_dmem_io_write_fault", chanidx=i, start=0, depth=1, bus_mode=True) check_cons(grp, "bus_dmem_io_order", chanidx=i, start=0, depth=1, bus_mode=True) check_cons(grp, "hang", start=0, depth=1) check_cons(grp, "cover", start=0, depth=1) for csr in sorted(csrs): for chanidx in range(nret): for csr_test in csr_tests.get(csr, [None]): check_cons(grp, csr, chanidx, start=0, depth=1, csr_mode=True, csr_test=csr_test) # ------------------------------ Makefile ------------------------------ def checks_key(check): if "sort" in config: for index, line in enumerate(config["sort"].split("\n")): if re.fullmatch(line.strip(), check): return f"{index:04d}-{check}" if check.startswith("insn_"): return f"9999-{check}" return f"9998-{check}" with open(f"{cfgname}/makefile", "w") as mkfile: print("all:", end="", file=mkfile) checks = list(sorted(consistency_checks | instruction_checks, key=checks_key)) for check in checks: print(f" {check}", end="", file=mkfile) print(file=mkfile) for check in checks: print(f"{check}: {check}/status", file=mkfile) print(f"{check}/status:", file=mkfile) if abspath: print(f"\t{sbycmd} $(shell pwd)/{check}.sby", file=mkfile) else: print(f"\t{sbycmd} {check}.sby", file=mkfile) print(f".PHONY: {check}", file=mkfile) print(f"Generated {len(consistency_checks) + len(instruction_checks)} checks.") ================================================ FILE: checks/rvfi_bus_dmem_check.sv ================================================ // external bus: check data reads // // Note: This only checks the data on the core side, so it is valid even with // caches between the checked bus and core. It also checks that the first bus // read of the checked data makes it to the core, but does not check that any // writes make it to the bus nor that any other bus-side data makes it to the // core. // // Copyright (C) 2017 Claire Xenia Wolf // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. `ifndef RISCV_FORMAL_FAULT_WIDTH `define RISCV_FORMAL_FAULT_WIDTH 1 `endif module rvfi_bus_dmem_check ( input clock, reset, check, `RVFI_INPUTS `RVFI_BUS_INPUTS ); `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] dmem_addr; `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] dmem_data; reg [ `RISCV_FORMAL_XLEN-1:0] dmem_shadow; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] bus_addr; (* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_rmask; (* keep *) reg [`RISCV_FORMAL_BUSLEN - 1:0] bus_rdata; (* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_wmask; (* keep *) reg [`RISCV_FORMAL_BUSLEN - 1:0] bus_wdata; reg [`RISCV_FORMAL_XLEN-1:0] bus_shadow; integer channel_idx, i, j; always @(posedge clock) begin if (reset) begin dmem_shadow <= dmem_data; bus_shadow <= dmem_data; end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin if (rvfi_bus_valid[channel_idx] && rvfi_bus_data[channel_idx]) begin bus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; bus_rmask = rvfi_bus_rmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8]; bus_rdata = rvfi_bus_rdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN]; bus_wmask = rvfi_bus_wmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8]; bus_wdata = rvfi_bus_wdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN]; for (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin for (j = 0; j < `RISCV_FORMAL_XLEN/8; j=j+1) begin if (bus_addr + i == dmem_addr + j) begin if (bus_rmask[i]) begin assume (bus_rdata[i*8 +: 8] == bus_shadow[j*8 +: 8]); end if (bus_wmask[i]) begin bus_shadow[j*8 +: 8] = bus_wdata[i*8 +: 8]; end end if (((bus_addr + i) | (`RISCV_FORMAL_FAULT_WIDTH - 1)) == ((dmem_addr + j) | (`RISCV_FORMAL_FAULT_WIDTH - 1))) begin if (bus_rmask[i] || bus_wmask[i]) begin assume (!rvfi_bus_fault[channel_idx]); end end end end end end for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin if (rvfi_valid[channel_idx] && rvfi_mem_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN] == dmem_addr && `rvformal_addr_valid(dmem_addr)) begin for (i = 0; i < `RISCV_FORMAL_XLEN/8; i = i+1) begin if (channel_idx == `RISCV_FORMAL_CHANNEL_IDX && check && rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 + i] ) begin cover (1); assert (dmem_shadow[i*8 +: 8] == rvfi_mem_rdata[i*8 +: 8]); end if (rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 + i]) begin dmem_shadow[i*8 +: 8] = rvfi_mem_wdata[i*8 +: 8]; end end end end end end endmodule ================================================ FILE: checks/rvfi_bus_dmem_fault_check.sv ================================================ // external bus: check faulting data reads // // Note: This only checks the data on the core side, so it is valid even with // caches between the checked bus and core. It also checks that the first bus // read of the checked data makes it to the core, but does not check that any // writes make it to the bus nor that any other bus-side data makes it to the // core. // // Copyright (C) 2017 Claire Xenia Wolf // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_bus_dmem_fault_check ( input clock, reset, check, `RVFI_INPUTS `RVFI_BUS_INPUTS ); `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] dmem_addr; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] bus_addr; (* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_rmask; (* keep *) reg [`RISCV_FORMAL_BUSLEN - 1:0] bus_rdata; (* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_wmask; (* keep *) reg [`RISCV_FORMAL_BUSLEN - 1:0] bus_wdata; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_addr; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_rdata; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] mem_rmask; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_wdata; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] mem_wmask; `ifdef RISCV_FORMAL_MEM_FAULT (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] mem_fault_rmask; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] mem_fault_wmask; `endif integer channel_idx, i, j; always @(posedge clock) begin if (!reset) begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin if (rvfi_bus_valid[channel_idx] && rvfi_bus_data[channel_idx]) begin bus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; bus_rmask = rvfi_bus_rmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8]; bus_rdata = rvfi_bus_rdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN]; bus_wmask = rvfi_bus_wmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8]; bus_wdata = rvfi_bus_wdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN]; for (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin for (j = 0; j < `RISCV_FORMAL_XLEN/8; j=j+1) begin if (bus_addr + i == dmem_addr + j) begin if (bus_rmask[i]) begin assume (rvfi_bus_fault[channel_idx]); end if (bus_wmask[i]) begin assume (rvfi_bus_fault[channel_idx]); end end end end cover (rvfi_bus_fault[channel_idx]); end end for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin mem_addr = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_rdata = rvfi_mem_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; mem_wdata = rvfi_mem_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; `ifdef RISCV_FORMAL_MEM_FAULT mem_fault_rmask = rvfi_mem_fault_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; mem_fault_wmask = rvfi_mem_fault_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; `endif if (rvfi_valid[channel_idx] && mem_addr == dmem_addr && `rvformal_addr_valid(dmem_addr)) begin for (i = 0; i < `RISCV_FORMAL_XLEN/8; i = i+1) begin if (check && channel_idx == `RISCV_FORMAL_CHANNEL_IDX) begin `ifndef RISCV_FORMAL_MEM_FAULT cover (1); `endif assert (!mem_rmask[i]); assert (!mem_wmask[i]); `ifdef RISCV_FORMAL_MEM_FAULT cover (mem_fault_rmask[i]); cover (mem_fault_wmask[i]); if (mem_fault_rmask[i] || mem_fault_wmask[i]) begin assert (rvfi_mem_fault[channel_idx]); end `endif end end end end end end endmodule ================================================ FILE: checks/rvfi_bus_dmem_io_order_check.sv ================================================ // external bus: check i/o access ordering // // Copyright (C) 2017 Claire Xenia Wolf // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_bus_dmem_io_order_check ( input clock, reset, check, `RVFI_INPUTS `RVFI_BUS_INPUTS ); `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN - 1:0] check_addr_0; `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN - 1:0] check_addr_1; `rvformal_rand_const_reg check_write_0; `rvformal_rand_const_reg check_fault_0; `rvformal_rand_const_reg check_write_1; `rvformal_rand_const_reg check_fault_1; (* keep *) reg bus_0_prev, bus_0_current, bus_1_current, bus_seq_seen; (* keep *) reg [`RISCV_FORMAL_NBUS-1:0] bus_is_io; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] bus_addr; (* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_rmask; (* keep *) reg [`RISCV_FORMAL_BUSLEN - 1:0] bus_rdata; (* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_wmask; (* keep *) reg [`RISCV_FORMAL_BUSLEN - 1:0] bus_wdata; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_addr; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_rdata; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] mem_rmask; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_wdata; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] mem_wmask; (* keep *) reg fault; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] prev_addr; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] prev_rdata; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] prev_rmask; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] prev_wdata; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] prev_wmask; (* keep *) reg prev_fault; (* keep *) reg core_has_prev; (* keep *) reg core_0_match; (* keep *) reg core_1_match; reg [ `RISCV_FORMAL_XLEN - 1:0] bus_byte_addr; integer channel_idx, i, j; always @(posedge clock) begin if (reset) begin bus_0_current = 0; bus_0_prev = 0; bus_1_current = 0; bus_seq_seen = 0; core_has_prev = 0; end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin if (rvfi_bus_valid[channel_idx] && rvfi_bus_data[channel_idx]) begin bus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; bus_rmask = rvfi_bus_rmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8]; bus_rdata = rvfi_bus_rdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN]; bus_wmask = rvfi_bus_wmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8]; bus_wdata = rvfi_bus_wdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN]; bus_is_io[channel_idx] = 0; for (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin bus_byte_addr = bus_addr + i; if (`rvformal_addr_io(bus_byte_addr) && (bus_rmask[i] || bus_wmask[i])) begin bus_is_io[channel_idx] = 1; end end if (bus_is_io[channel_idx]) begin bus_1_current = 0; bus_0_prev = bus_0_current; bus_0_current = 0; for (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin if ((bus_addr + i == check_addr_0) && (check_fault_0 == rvfi_bus_fault[channel_idx]) && (check_write_0 ? bus_wmask[i] : bus_rmask[i])) begin bus_0_current = 1; end if ((bus_addr + i == check_addr_1) && (check_fault_1 == rvfi_bus_fault[channel_idx]) && (check_write_1 ? bus_wmask[i] : bus_rmask[i])) begin bus_1_current = 1; end end if (bus_1_current && bus_0_prev) begin bus_seq_seen = 1; cover (1); end end end end for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin mem_addr = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_rdata = rvfi_mem_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; mem_wdata = rvfi_mem_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; `ifdef RISCV_FORMAL_MEM_FAULT fault = rvfi_mem_fault[channel_idx]; if (fault) begin mem_rmask = rvfi_mem_fault_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; mem_wmask = rvfi_mem_fault_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; end `else fault = 0; `endif core_0_match = 0; core_1_match = 0; for (i = 0; i < `RISCV_FORMAL_XLEN/8; i=i+1) begin if ((prev_addr + i == check_addr_0) && (check_fault_0 == prev_fault) && (check_write_0 ? prev_wmask[i] : prev_rmask[i])) begin core_0_match = core_has_prev; end if ((mem_addr + i == check_addr_1) && (check_fault_1 == fault) && (check_write_1 ? mem_wmask[i] : mem_rmask[i])) begin core_1_match = 1; end end if ( check && rvfi_valid[channel_idx] && channel_idx == `RISCV_FORMAL_CHANNEL_IDX && `rvformal_addr_io(mem_addr) && core_0_match && core_1_match ) begin cover (1); assert (bus_seq_seen); end if (rvfi_valid[channel_idx] && `rvformal_addr_io(mem_addr) && (mem_rmask || mem_wmask)) begin // This check would need to be extended to handle potential instructions that // simultaneously read and write. This assertion makes sure this check doesn't // silently miss any issues should such instructions be added. assert (!(mem_rmask && mem_wmask)); core_has_prev = 1; prev_addr = mem_addr; prev_rdata = mem_rdata; prev_rmask = mem_rmask; prev_wdata = mem_wdata; prev_wmask = mem_wmask; prev_fault = fault; end end end end endmodule ================================================ FILE: checks/rvfi_bus_dmem_io_read_check.sv ================================================ // external bus: check i/o reads // // This checks that a retired non-faulting load is contained in a single read // transaction on the external bus. It doesn't check any relationships bitween // multiple instructions or bus transactions. See the inline comment for // details on loads that are not as wide as the bus. // // Copyright (C) 2017 Claire Xenia Wolf // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_bus_dmem_io_read_check ( input clock, reset, check, `RVFI_INPUTS `RVFI_BUS_INPUTS ); `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN - 1:0] check_addr; `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN - 1:0] check_rdata; `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN/8 - 1:0] check_rmask; reg bus_read_seen, bus_read_matches; reg core_read_matches; reg [`RISCV_FORMAL_XLEN/8 - 1:0] check_match_mask; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] bus_addr; (* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_rmask; (* keep *) reg [`RISCV_FORMAL_BUSLEN - 1:0] bus_rdata; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_addr; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_rdata; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] mem_rmask; integer channel_idx, i, j; always @(posedge clock) begin if (reset) begin bus_read_seen <= 0; end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin if (rvfi_bus_valid[channel_idx] && rvfi_bus_data[channel_idx]) begin bus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; bus_rmask = rvfi_bus_rmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8]; bus_rdata = rvfi_bus_rdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN]; // This allows the read to appear anywhere in the bus data as long as it fits // into a single transaction. It also allows reading adjacent bytes in the same // transaction. Different busses handle narrow reads differently, so as a // generic check we don't prescribe any particular behavior. check_match_mask = 0; bus_read_matches = 1; for (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin for (j = 0; j < `RISCV_FORMAL_XLEN/8; j=j+1) begin if (bus_addr + i == check_addr + j && check_rmask[i]) begin if (bus_rmask[i] && bus_rdata[i*8 +: 8] == check_rdata[j*8 +: 8]) begin check_match_mask[j] = 1; end else begin bus_read_matches = 0; end end end end if (bus_read_matches && check_match_mask == check_rmask && !rvfi_bus_fault[channel_idx]) begin bus_read_seen = 1; end end end for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin mem_addr = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_rdata = rvfi_mem_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; core_read_matches = check_rmask && mem_addr == check_addr && mem_rmask == check_rmask `ifdef RISCV_FORMAL_MEM_FAULT && !rvfi_mem_fault[channel_idx] `endif ; for (i = 0; i < `RISCV_FORMAL_XLEN/8; i=i+1) begin if (mem_rmask[i] && mem_rdata[i*8 +: 8] != check_rdata[i*8 +: 8]) begin core_read_matches = 0; end end if (check && rvfi_valid[channel_idx] && core_read_matches && `rvformal_addr_io(check_addr)) begin cover (1); assert (bus_read_seen); end end end end endmodule ================================================ FILE: checks/rvfi_bus_dmem_io_read_fault_check.sv ================================================ // external bus: check i/o read faults // // This checks that a retired faulting load is contained in a single read // transaction on the external bus. It doesn't check any relationships bitween // multiple instructions or bus transactions. See the inline comment for // details on loads that are not as wide as the bus. // // Copyright (C) 2017 Claire Xenia Wolf // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_bus_dmem_io_read_fault_check ( input clock, reset, check, `RVFI_INPUTS `RVFI_BUS_INPUTS ); `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN - 1:0] check_addr; `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN/8 - 1:0] check_rmask; reg bus_read_seen, bus_read_matches; reg core_read_matches; reg [`RISCV_FORMAL_XLEN/8 - 1:0] check_match_mask; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] bus_addr; (* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_rmask; (* keep *) reg [`RISCV_FORMAL_BUSLEN - 1:0] bus_rdata; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_addr; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_rdata; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] mem_rmask; integer channel_idx, i, j; always @(posedge clock) begin if (reset) begin bus_read_seen <= 0; end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin if (rvfi_bus_valid[channel_idx] && rvfi_bus_data[channel_idx]) begin bus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; bus_rmask = rvfi_bus_rmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8]; bus_rdata = rvfi_bus_rdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN]; // This allows the read to appear anywhere in the bus data as long as it fits // into a single transaction. It also allows reading adjacent bytes in the same // transaction. Different busses handle narrow reads differently, so as a // generic check we don't prescribe any particular behavior. check_match_mask = 0; bus_read_matches = 1; for (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin for (j = 0; j < `RISCV_FORMAL_XLEN/8; j=j+1) begin if (bus_addr + i == check_addr + j && check_rmask[i]) begin if (bus_rmask[i]) begin check_match_mask[j] = 1; end else begin bus_read_matches = 0; end end end end if (bus_read_matches && check_match_mask == check_rmask && rvfi_bus_fault[channel_idx]) begin bus_read_seen = 1; end end end for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin mem_addr = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_rdata = rvfi_mem_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_rmask = rvfi_mem_fault_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; core_read_matches = check_rmask && mem_addr == check_addr && mem_rmask == check_rmask && rvfi_mem_fault[channel_idx]; if (check && rvfi_valid[channel_idx] && core_read_matches && `rvformal_addr_io(check_addr)) begin cover (1); assert (bus_read_seen); end end end end endmodule ================================================ FILE: checks/rvfi_bus_dmem_io_write_check.sv ================================================ // external bus: check i/o writes // // This checks that a retired non-faulting store is contained in a single read // transaction on the external bus. It doesn't check any relationships bitween // multiple instructions or bus transactions. See the inline comment for // details on stores that are not as wide as the bus. // // Copyright (C) 2017 Claire Xenia Wolf // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_bus_dmem_io_write_check ( input clock, reset, check, `RVFI_INPUTS `RVFI_BUS_INPUTS ); `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN - 1:0] check_addr; `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN - 1:0] check_wdata; `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN/8 - 1:0] check_wmask; reg bus_write_seen, bus_write_matches; reg core_write_matches; reg [`RISCV_FORMAL_XLEN/8 - 1:0] check_match_mask; reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_match_mask; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] bus_addr; (* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_wmask; (* keep *) reg [`RISCV_FORMAL_BUSLEN - 1:0] bus_wdata; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_addr; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_wdata; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] mem_wmask; integer channel_idx, i, j; always @(posedge clock) begin if (reset) begin bus_write_seen <= 0; end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin if (rvfi_bus_valid[channel_idx] && rvfi_bus_data[channel_idx]) begin bus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; bus_wmask = rvfi_bus_wmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8]; bus_wdata = rvfi_bus_wdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN]; // This allows the write to appear anywhere in the bus data as long as it fits // into a single transaction. Unlike for reads, we don't allow writing // additional adjacent bytes. check_match_mask = 0; bus_match_mask = 0; bus_write_matches = 1; for (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin for (j = 0; j < `RISCV_FORMAL_XLEN/8; j=j+1) begin if (bus_addr + i == check_addr + j && check_wmask[i]) begin if (bus_wmask[i] && bus_wdata[i*8 +: 8] == check_wdata[j*8 +: 8]) begin check_match_mask[j] = 1; bus_match_mask[i] = 1; end else begin bus_write_matches = 0; end end end end if (bus_write_matches && bus_match_mask == bus_wmask && check_match_mask == check_wmask && !rvfi_bus_fault[channel_idx]) begin bus_write_seen = 1; end end end for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin mem_addr = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_wdata = rvfi_mem_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; core_write_matches = check_wmask && mem_addr == check_addr && mem_wmask == check_wmask `ifdef RISCV_FORMAL_MEM_FAULT && !rvfi_mem_fault[channel_idx] `endif ; for (i = 0; i < `RISCV_FORMAL_XLEN/8; i=i+1) begin if (mem_wmask[i] && mem_wdata[i*8 +: 8] != check_wdata[i*8 +: 8]) begin core_write_matches = 0; end end if (check && rvfi_valid[channel_idx] && core_write_matches && `rvformal_addr_io(check_addr)) begin cover (1); assert (bus_write_seen); end end end end endmodule ================================================ FILE: checks/rvfi_bus_dmem_io_write_fault_check.sv ================================================ // external bus: check i/o write faults // // This checks that a retired faulting store is contained in a single read // transaction on the external bus. It doesn't check any relationships bitween // multiple instructions or bus transactions. See the inline comment for // details on stores that are not as wide as the bus. // // Copyright (C) 2017 Claire Xenia Wolf // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_bus_dmem_io_write_fault_check ( input clock, reset, check, `RVFI_INPUTS `RVFI_BUS_INPUTS ); `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN - 1:0] check_addr; `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN - 1:0] check_wdata; `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN/8 - 1:0] check_wmask; reg bus_write_seen, bus_write_matches; reg core_write_matches; reg [`RISCV_FORMAL_XLEN/8 - 1:0] check_match_mask; reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_match_mask; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] bus_addr; (* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_wmask; (* keep *) reg [`RISCV_FORMAL_BUSLEN - 1:0] bus_wdata; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_addr; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_wdata; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] mem_wmask; integer channel_idx, i, j; always @(posedge clock) begin if (reset) begin bus_write_seen <= 0; end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin if (rvfi_bus_valid[channel_idx] && rvfi_bus_data[channel_idx]) begin bus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; bus_wmask = rvfi_bus_wmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8]; bus_wdata = rvfi_bus_wdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN]; // This allows the write to appear anywhere in the bus data as long as it fits // into a single transaction. Unlike for reads, we don't allow writing // additional adjacent bytes. check_match_mask = 0; bus_match_mask = 0; bus_write_matches = 1; for (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin for (j = 0; j < `RISCV_FORMAL_XLEN/8; j=j+1) begin if (bus_addr + i == check_addr + j && check_wmask[i]) begin if (bus_wmask[i] && bus_wdata[i*8 +: 8] == check_wdata[j*8 +: 8]) begin check_match_mask[j] = 1; bus_match_mask[i] = 1; end else begin bus_write_matches = 0; end end end end if (bus_write_matches && bus_match_mask == bus_wmask && check_match_mask == check_wmask && rvfi_bus_fault[channel_idx]) begin bus_write_seen = 1; end end end for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin mem_addr = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_wdata = rvfi_mem_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_wmask = rvfi_mem_fault_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; core_write_matches = check_wmask && mem_addr == check_addr && mem_wmask == check_wmask && rvfi_mem_fault[channel_idx]; for (i = 0; i < `RISCV_FORMAL_XLEN/8; i=i+1) begin if (mem_wmask[i] && mem_wdata[i*8 +: 8] != check_wdata[i*8 +: 8]) begin core_write_matches = 0; end end if (check && rvfi_valid[channel_idx] && core_write_matches && `rvformal_addr_io(check_addr)) begin cover (1); assert (bus_write_seen); end end end end endmodule ================================================ FILE: checks/rvfi_bus_imem_check.sv ================================================ // external bus: check instruction memory reads // // Copyright (C) 2017 Claire Xenia Wolf // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. `ifndef RISCV_FORMAL_FAULT_WIDTH `define RISCV_FORMAL_FAULT_WIDTH 1 `endif module rvfi_bus_imem_check ( input clock, reset, check, `RVFI_INPUTS `RVFI_BUS_INPUTS ); `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] imem_addr; `rvformal_rand_const_reg [15:0] imem_data; reg [`RISCV_FORMAL_XLEN-1:0] pc; reg [`RISCV_FORMAL_ILEN-1:0] insn; reg [ `RISCV_FORMAL_XLEN - 1:0] bus_addr; reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_rmask; reg [`RISCV_FORMAL_BUSLEN - 1:0] bus_rdata; integer channel_idx, i, j; always @(posedge clock) begin if (reset) begin end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin if (rvfi_bus_valid[channel_idx] && rvfi_bus_insn[channel_idx]) begin bus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; bus_rmask = rvfi_bus_rmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8]; bus_rdata = rvfi_bus_rdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN]; for (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) for (j = 0; j < 2; j=j+1) begin if (bus_rmask[i] && bus_addr + i == imem_addr + j) begin assume (imem_data[j*8 +: 8] == bus_rdata[i*8 +: 8]); end if (bus_rmask[i] && ((bus_addr + i) | (`RISCV_FORMAL_FAULT_WIDTH - 1)) == ((imem_addr + j) | (`RISCV_FORMAL_FAULT_WIDTH - 1))) begin assume (!rvfi_bus_fault[channel_idx]); end end end end if (check) begin if (rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]) begin pc = rvfi_pc_rdata[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; insn = rvfi_insn[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_ILEN +: `RISCV_FORMAL_ILEN]; if (`rvformal_addr_valid(pc) && pc == imem_addr) begin cover (1); assert (insn[15:0] == imem_data); end; if (insn[1:0] == 2'b11 && `rvformal_addr_valid(pc+2) && pc+2 == imem_addr) begin cover (1); assert (insn[31:16] == imem_data); end; end end end end endmodule ================================================ FILE: checks/rvfi_bus_imem_fault_check.sv ================================================ // external bus: check faulting instruction memory reads // // Copyright (C) 2017 Claire Xenia Wolf // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_bus_imem_fault_check ( input clock, reset, check, `RVFI_INPUTS `RVFI_BUS_INPUTS ); `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] imem_addr; reg [`RISCV_FORMAL_XLEN-1:0] pc; reg [`RISCV_FORMAL_ILEN-1:0] insn; reg [ `RISCV_FORMAL_XLEN - 1:0] bus_addr; reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_rmask; reg [`RISCV_FORMAL_BUSLEN - 1:0] bus_rdata; integer channel_idx, i, j; always @(posedge clock) begin if (reset) begin end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin if (rvfi_bus_valid[channel_idx] && rvfi_bus_insn[channel_idx]) begin bus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; bus_rmask = rvfi_bus_rmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8]; bus_rdata = rvfi_bus_rdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN]; for (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) for (j = 0; j < 2; j=j+1) begin if (bus_rmask[i] && bus_addr + i == imem_addr + j) begin assume (rvfi_bus_fault[channel_idx]); end end cover (rvfi_bus_fault[channel_idx]); end end if (check) begin if (rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]) begin pc = rvfi_pc_rdata[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; insn = rvfi_insn[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_ILEN +: `RISCV_FORMAL_ILEN]; if (`rvformal_addr_valid(pc) && pc == imem_addr) begin cover (1); assert (rvfi_trap[`RISCV_FORMAL_CHANNEL_IDX]); assert (insn == 0); `ifdef RISCV_FORMAL_MEM_FAULT assert (rvfi_mem_fault[`RISCV_FORMAL_CHANNEL_IDX]); `endif end; if (`rvformal_addr_valid(pc+2) && pc+2 == imem_addr) begin cover (1); assert (rvfi_trap[`RISCV_FORMAL_CHANNEL_IDX]); assert (insn == 0); `ifdef RISCV_FORMAL_MEM_FAULT assert (rvfi_mem_fault[`RISCV_FORMAL_CHANNEL_IDX]); `endif end; end end end end endmodule ================================================ FILE: checks/rvfi_causal_check.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_causal_check ( input clock, reset, check, `RVFI_INPUTS ); `rvformal_rand_const_reg [63:0] insn_order; `rvformal_rand_const_reg [4:0] register_index; reg found_non_causal = 0; integer channel_idx; always @(posedge clock) begin if (reset) begin found_non_causal = 0; end else begin if (check) begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_CHANNEL_IDX; channel_idx=channel_idx+1) begin if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] > insn_order && (register_index == rvfi_rs1_addr[channel_idx*5 +: 5] || register_index == rvfi_rs2_addr[channel_idx*5 +: 5])) begin found_non_causal = 1; end end assume(register_index != 0); assume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]); assume((register_index == rvfi_rd_addr[`RISCV_FORMAL_CHANNEL_IDX*5 +: 5])); assume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]); assert(!found_non_causal); end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] > insn_order && (register_index == rvfi_rs1_addr[channel_idx*5 +: 5] || register_index == rvfi_rs2_addr[channel_idx*5 +: 5])) begin found_non_causal = 1; end end end end end endmodule ================================================ FILE: checks/rvfi_causal_io_check.sv ================================================ // check that no i/o memory accesses are retired in a non-causal order // // This checks that no i/o memory accesses are retired out of order. It uses // the RISCV_FORMAL_IOADDR(addr) macro to determine whether a memory location // is considered to be an i/o address. // // Copyright (C) 2017 Claire Xenia Wolf // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_causal_io_check ( input clock, reset, check, `RVFI_INPUTS ); `rvformal_rand_const_reg [63:0] insn_order; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_addr; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] mem_rmask; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] mem_wmask; reg found_non_causal = 0; reg performs_io = 0; reg [ `RISCV_FORMAL_XLEN - 1:0] byte_addr; integer channel_idx; integer i; always @(posedge clock) begin if (reset) begin found_non_causal = 0; end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin mem_addr = rvfi_mem_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; mem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; `ifdef RISCV_FORMAL_MEM_FAULT if (rvfi_mem_fault[channel_idx]) begin mem_rmask = rvfi_mem_fault_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; mem_wmask = rvfi_mem_fault_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; end `endif performs_io = 0; for (i = 0; i < `RISCV_FORMAL_XLEN/8; i = i+1) begin byte_addr = mem_addr + i; if (`rvformal_addr_io(byte_addr)) begin performs_io |= mem_rmask[i] | mem_wmask[i]; end end if (check && channel_idx == `RISCV_FORMAL_CHANNEL_IDX) begin assume (rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]); assume (performs_io); assume (insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]); cover (1); assert (!found_non_causal); end if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] > insn_order && performs_io) begin found_non_causal = 1; end end end end endmodule ================================================ FILE: checks/rvfi_causal_mem_check.sv ================================================ // check that no memory accesses are retired in a non-causal order // // This checks that no read of a memory location is retired before the write of // the to-be-read value. // // Copyright (C) 2017 Claire Xenia Wolf // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_causal_mem_check ( input clock, reset, check, `RVFI_INPUTS ); `rvformal_rand_const_reg [63:0] insn_order; `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] check_addr; (* keep *) reg [ `RISCV_FORMAL_XLEN - 1:0] mem_addr; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] mem_rmask; (* keep *) reg [ `RISCV_FORMAL_XLEN/8 - 1:0] mem_wmask; reg found_non_causal = 0; reg reads_check_addr; reg writes_check_addr; integer channel_idx; integer i; always @(posedge clock) begin if (reset) begin found_non_causal = 0; end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin mem_addr = rvfi_mem_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; mem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; mem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; `ifdef RISCV_FORMAL_MEM_FAULT if (rvfi_mem_fault[channel_idx]) begin mem_rmask = rvfi_mem_fault_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; mem_wmask = rvfi_mem_fault_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; end `endif reads_check_addr = 0; writes_check_addr = 0; for (i = 0; i < `RISCV_FORMAL_XLEN/8; i = i+1) begin if (mem_addr + i == check_addr) begin reads_check_addr |= mem_rmask[i]; writes_check_addr |= mem_wmask[i]; end end if (check && channel_idx == `RISCV_FORMAL_CHANNEL_IDX) begin assume (rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]); assume (writes_check_addr); assume (insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]); cover (1); assert (!found_non_causal); end if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] > insn_order && reads_check_addr) begin found_non_causal = 1; end end end end endmodule ================================================ FILE: checks/rvfi_channel.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_channel ( `RVFI_INPUTS ); parameter CHANNEL_IDX = 0; (* keep *) wire valid = rvfi_valid [CHANNEL_IDX]; (* keep *) wire [ 63 : 0] order = rvfi_order [CHANNEL_IDX*64 +: 64]; (* keep *) wire [`RISCV_FORMAL_ILEN - 1 : 0] insn = rvfi_insn [CHANNEL_IDX*`RISCV_FORMAL_ILEN +: `RISCV_FORMAL_ILEN]; (* keep *) wire trap = rvfi_trap [CHANNEL_IDX]; (* keep *) wire halt = rvfi_halt [CHANNEL_IDX]; (* keep *) wire intr = rvfi_intr [CHANNEL_IDX]; (* keep *) wire [ 1 : 0] mode = rvfi_mode [CHANNEL_IDX*2 +: 2]; (* keep *) wire [ 1 : 0] ixl = rvfi_ixl [CHANNEL_IDX*2 +: 2]; (* keep *) wire [ 4 : 0] rs1_addr = rvfi_rs1_addr [CHANNEL_IDX*5 +: 5]; (* keep *) wire [ 4 : 0] rs2_addr = rvfi_rs2_addr [CHANNEL_IDX*5 +: 5]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] rs1_rdata = rvfi_rs1_rdata[CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] rs2_rdata = rvfi_rs2_rdata[CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [ 4 : 0] rd_addr = rvfi_rd_addr [CHANNEL_IDX*5 +: 5]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] rd_wdata = rvfi_rd_wdata [CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] pc_rdata = rvfi_pc_rdata [CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] pc_wdata = rvfi_pc_wdata [CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_addr = rvfi_mem_addr [CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_rmask = rvfi_mem_rmask[CHANNEL_IDX*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_wmask = rvfi_mem_wmask[CHANNEL_IDX*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_rdata = rvfi_mem_rdata[CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_wdata = rvfi_mem_wdata[CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; endmodule ================================================ FILE: checks/rvfi_cover_check.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_cover_check ( input clock, reset, check, `RVFI_INPUTS ); `ifdef RISCV_FORMAL_ROLLBACK (* keep *) integer cnt_rollback; integer cnt_rollback_q; always @(posedge clock) begin cnt_rollback_q <= cnt_rollback; end always @* begin if (reset) cnt_rollback = 0; else cnt_rollback = cnt_rollback_q + rvfi_rollback_valid; end `endif genvar channel_idx; generate for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin:channel `RVFI_GETCHANNEL(channel_idx) (* keep *) integer cnt_insns; (* keep *) integer cnt_trap_insns; (* keep *) integer cnt_intr_insns; (* keep *) integer cnt_norm_insns; `ifdef RISCV_FORMAL_ROLLBACK // "arb" = after rollback (* keep *) integer arb_cnt_insns; (* keep *) integer arb_cnt_trap_insns; (* keep *) integer arb_cnt_intr_insns; (* keep *) integer arb_cnt_norm_insns; `endif integer cnt_insns_q; integer cnt_trap_insns_q; integer cnt_intr_insns_q; integer cnt_norm_insns_q; `ifdef RISCV_FORMAL_ROLLBACK integer arb_cnt_insns_q; integer arb_cnt_trap_insns_q; integer arb_cnt_intr_insns_q; integer arb_cnt_norm_insns_q; `endif always @(posedge clock) begin cnt_insns_q <= cnt_insns; cnt_trap_insns_q <= cnt_trap_insns; cnt_intr_insns_q <= cnt_intr_insns; cnt_norm_insns_q <= cnt_norm_insns; `ifdef RISCV_FORMAL_ROLLBACK arb_cnt_insns_q <= arb_cnt_insns; arb_cnt_trap_insns_q <= arb_cnt_trap_insns; arb_cnt_intr_insns_q <= arb_cnt_intr_insns; arb_cnt_norm_insns_q <= arb_cnt_norm_insns; `endif end always @* begin if (reset) begin cnt_insns = 0; cnt_trap_insns = 0; cnt_intr_insns = 0; cnt_norm_insns = 0; `ifdef RISCV_FORMAL_ROLLBACK arb_cnt_insns = 0; arb_cnt_trap_insns = 0; arb_cnt_intr_insns = 0; arb_cnt_norm_insns = 0; `endif end else begin cnt_insns = cnt_insns_q + valid; cnt_trap_insns = cnt_trap_insns_q + (valid && trap); cnt_intr_insns = cnt_intr_insns_q + (valid && intr); cnt_norm_insns = cnt_norm_insns_q + (valid && !{trap,intr}); `ifdef RISCV_FORMAL_ROLLBACK arb_cnt_insns = arb_cnt_insns_q + (valid && cnt_rollback); arb_cnt_trap_insns = arb_cnt_trap_insns_q + (valid && cnt_rollback && trap); arb_cnt_intr_insns = arb_cnt_intr_insns_q + (valid && cnt_rollback && intr); arb_cnt_norm_insns = arb_cnt_norm_insns_q + (valid && cnt_rollback && !{trap,intr}); `endif end end end endgenerate `include "cover_stmts.vh" endmodule ================================================ FILE: checks/rvfi_csr_ill_check.sv ================================================ // Copyright (C) 2023 Krystine Dawn Sherwin // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_csr_ill_check ( input clock, reset, check, `RVFI_INPUTS ); `RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX) wire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0); wire [11:0] csr_insn_addr = rvfi.insn[31:20]; wire csr_write = !rvfi.insn[13] || rvfi.insn[19:15]; wire csr_read = rvfi.insn[11:7] != 0; always @* begin if (!reset && check) begin assume (csr_insn_valid); assume (csr_insn_addr == `RISCV_FORMAL_ILL_CSR_ADDR); if ( (0 `ifdef RISCV_FORMAL_ILL_MMODE || rvfi.mode == 3 `endif `ifdef RISCV_FORMAL_ILL_SMODE || rvfi.mode == 1 `endif `ifdef RISCV_FORMAL_ILL_UMODE || rvfi.mode == 0 `endif ) && (0 `ifdef RISCV_FORMAL_ILL_WRITE || csr_write `endif `ifdef RISCV_FORMAL_ILL_READ || csr_read `endif ) ) begin assert (rvfi.trap); end end end endmodule ================================================ FILE: checks/rvfi_csrc_any_check.sv ================================================ // Copyright (C) 2023 Krystine Dawn Sherwin // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_csrc_any_check ( input clock, reset, check, `RVFI_INPUTS ); // Setup for csrs `RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX) localparam [11:0] csr_none = 12'hFFF; `RVFI_INDICES `define quoted(txt) txt `define csrget(_name, _type) rvfi.csr_``_name```quoted(_``_type) `define csr_mindex(_name) csr_mindex_``_name `define csr_sindex(_name) csr_sindex_``_name `define csr_uindex(_name) csr_uindex_``_name `define csr_mindexh(_name) csr_mindex_``_name```quoted(h) `define csr_sindexh(_name) csr_sindex_``_name```quoted(h) `define csr_uindexh(_name) csr_uindex_``_name```quoted(h) wire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0); wire [11:0] csr_insn_addr = rvfi.insn[31:20]; wire csr_insn_under_test = (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRC_NAME) `ifdef RISCV_FORMAL_SMODE || csr_insn_addr == `csr_sindex(`RISCV_FORMAL_CSRC_NAME) `endif `ifdef RISCV_FORMAL_UMODE || csr_insn_addr == `csr_uindex(`RISCV_FORMAL_CSRC_NAME) `endif ); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = `csrget(`RISCV_FORMAL_CSRC_NAME, rmask); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = `csrget(`RISCV_FORMAL_CSRC_NAME, wmask); `ifdef RISCV_FORMAL_CSRC_MASK wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata) & `RISCV_FORMAL_CSRC_MASK; wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRC_NAME, wdata) & `RISCV_FORMAL_CSRC_MASK; `else wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRC_NAME, wdata); `endif //RISCV_FORMAL_CSRC_MASK wire csr_write = !rvfi.insn[13] || rvfi.insn[19:15]; wire csr_read = rvfi.insn[11:7] != 0; wire csr_write_valid = csr_write && csr_insn_valid; wire csr_read_valid = csr_read && csr_insn_valid; wire [1:0] csr_mode = rvfi.insn[13:12]; wire [31:0] csr_rsval = rvfi.insn[14] ? rvfi.insn[19:15] : rvfi.rs1_rdata; // Setup for reg testing `rvformal_rand_const_reg [63:0] insn_order; reg [`RISCV_FORMAL_XLEN-1:0] rsval_shadow = 0; reg [`RISCV_FORMAL_XLEN-1:0] wdata_shadow = 0; reg csr_written = 0; reg [1:0] csr_mode_shadow = 0; always @(posedge clock) begin if (reset) begin rsval_shadow = 0; wdata_shadow = 0; csr_written = 0; csr_mode_shadow = 0; end else begin if (check) begin `ifdef RISCV_FORMAL_CSRC_MASK assume ((rsval_shadow & `RISCV_FORMAL_CSRC_MASK) == rsval_shadow); `endif if (csr_written && csr_read_valid && csr_insn_under_test) begin case (csr_mode_shadow) 2'b 00 /* None */, 2'b 01 /* RW */: begin assert(rsval_shadow == csr_insn_rdata || csr_insn_rdata == wdata_shadow); assert(rsval_shadow == wdata_shadow); end // Currently not testing set/clear from rsval 2'b 10 /* RS */, 2'b 11 /* RC */: begin assert(csr_insn_rdata == wdata_shadow); end endcase end end else begin if (csr_write_valid && csr_insn_under_test) begin rsval_shadow = csr_rsval; wdata_shadow = csr_insn_wdata; csr_written = 1; csr_mode_shadow = csr_mode; end end end end endmodule ================================================ FILE: checks/rvfi_csrc_const_check.sv ================================================ // Copyright (C) 2023 Krystine Dawn Sherwin // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_csrc_const_check ( input clock, reset, check, `RVFI_INPUTS ); // Setup for csrs `RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX) localparam [11:0] csr_none = 12'hFFF; `RVFI_INDICES `define quoted(txt) txt `define csrget(_name, _type) rvfi.csr_``_name```quoted(_``_type) `define csr_mindex(_name) csr_mindex_``_name `define csr_sindex(_name) csr_sindex_``_name `define csr_uindex(_name) csr_uindex_``_name `define csr_mindexh(_name) csr_mindex_``_name```quoted(h) `define csr_sindexh(_name) csr_sindex_``_name```quoted(h) `define csr_uindexh(_name) csr_uindex_``_name```quoted(h) wire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0); wire [11:0] csr_insn_addr = rvfi.insn[31:20]; wire csr_insn_under_test = (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRC_NAME) `ifdef RISCV_FORMAL_SMODE || csr_insn_addr == `csr_sindex(`RISCV_FORMAL_CSRC_NAME) `endif `ifdef RISCV_FORMAL_UMODE || csr_insn_addr == `csr_uindex(`RISCV_FORMAL_CSRC_NAME) `endif ); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = `csrget(`RISCV_FORMAL_CSRC_NAME, rmask); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = `csrget(`RISCV_FORMAL_CSRC_NAME, wmask); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRC_NAME, wdata); `ifdef RISCV_FORMAL_CSRC_MASK wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata) & `RISCV_FORMAL_CSRC_MASK; `else wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata); `endif //RISCV_FORMAL_CSRC_MASK wire csr_write = !rvfi.insn[13] || rvfi.insn[19:15]; wire csr_read = rvfi.insn[11:7] != 0; wire csr_write_valid = csr_write && csr_insn_valid; wire csr_read_valid = csr_read && csr_insn_valid; wire [1:0] csr_mode = rvfi.insn[13:12]; // Setup for reg testing reg [`RISCV_FORMAL_XLEN-1:0] wdata_shadow = 0; reg [`RISCV_FORMAL_XLEN-1:0] rdata_shadow = 0; reg csr_written = 0; always @(posedge clock) begin if (reset) begin wdata_shadow = 0; csr_written = 0; end else begin if (check) begin if (csr_written && csr_read_valid && csr_insn_under_test) begin assert(csr_insn_rdata == `RISCV_FORMAL_CSRC_CONSTVAL); end end else begin if (csr_write_valid && csr_insn_under_test) begin rdata_shadow = csr_insn_rdata; wdata_shadow = csr_insn_wdata; csr_written = 1; end end end end endmodule ================================================ FILE: checks/rvfi_csrc_hpm_check.sv ================================================ // Copyright (C) 2023 Krystine Dawn Sherwin // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_csrc_hpm_check ( input clock, reset, check, `RVFI_INPUTS ); // Setup for csrs `RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX) localparam [11:0] csr_none = 12'hFFF; `RVFI_INDICES `define quoted(txt) txt `define csrget(_name, _type) rvfi.csr_``_name```quoted(_``_type) `define csr_mindex(_name) csr_mindex_``_name `define csr_sindex(_name) csr_sindex_``_name `define csr_uindex(_name) csr_uindex_``_name `define csr_mindexh(_name) csr_mindex_``_name```quoted(h) `define csr_sindexh(_name) csr_sindex_``_name```quoted(h) `define csr_uindexh(_name) csr_uindex_``_name```quoted(h) wire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0); wire [11:0] csr_insn_addr = rvfi.insn[31:20]; wire csr_hpmcounter_under_test = (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRC_HPMCOUNTER) || csr_insn_addr == `csr_mindexh(`RISCV_FORMAL_CSRC_HPMCOUNTER)); wire csr_hpmevent_under_test = (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRC_NAME)); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = `csrget(`RISCV_FORMAL_CSRC_NAME, rmask); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = `csrget(`RISCV_FORMAL_CSRC_NAME, wmask); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRC_NAME, wdata); wire [`RISCV_FORMAL_XLEN-1:0] hpmcounter_rdata = `csrget(`RISCV_FORMAL_CSRC_HPMCOUNTER, rdata); wire csr_write = !rvfi.insn[13] || rvfi.insn[19:15]; wire csr_read = rvfi.insn[11:7] != 0; wire csr_write_valid = csr_write && csr_insn_valid; wire csr_read_valid = csr_read && csr_insn_valid; wire [1:0] csr_mode = rvfi.insn[13:12]; wire [31:0] csr_rsval = rvfi.insn[14] ? rvfi.insn[19:15] : rvfi.rs1_rdata; // Setup for reg testing `rvformal_rand_const_reg [63:0] insn_order; reg [31:0] csr_hpmcounter_shadow = 0; reg csr_hpmevent_written; always @(posedge clock) begin if (reset) begin csr_hpmcounter_shadow = 0; csr_hpmevent_written = 0; end else begin // No writes of CSR under test allowed assume (!(csr_write_valid && csr_hpmcounter_under_test)); if (csr_hpmevent_written) begin // event CSR should hold the desired event assume (csr_insn_rdata == `RISCV_FORMAL_CSRC_HPMEVENT); // counter CSR should eventually increase cover (hpmcounter_rdata > csr_hpmcounter_shadow); end if (csr_write_valid && csr_hpmevent_under_test) begin csr_hpmcounter_shadow = hpmcounter_rdata; csr_hpmevent_written = 1; end end end endmodule ================================================ FILE: checks/rvfi_csrc_inc_check.sv ================================================ // Copyright (C) 2023 Krystine Dawn Sherwin // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_csrc_inc_check ( input clock, reset, check, `RVFI_INPUTS ); // Setup for csrs `RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX) localparam [11:0] csr_none = 12'hFFF; `RVFI_INDICES `define quoted(txt) txt `define csrget(_name, _type) rvfi.csr_``_name```quoted(_``_type) `define csr_mindex(_name) csr_mindex_``_name `define csr_sindex(_name) csr_sindex_``_name `define csr_uindex(_name) csr_uindex_``_name `define csr_mindexh(_name) csr_mindex_``_name```quoted(h) `define csr_sindexh(_name) csr_sindex_``_name```quoted(h) `define csr_uindexh(_name) csr_uindex_``_name```quoted(h) wire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0); wire [11:0] csr_insn_addr = rvfi.insn[31:20]; wire csr_insn_under_test = (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRC_NAME) `ifdef RISCV_FORMAL_SMODE || csr_insn_addr == `csr_sindex(`RISCV_FORMAL_CSRC_NAME) `endif `ifdef RISCV_FORMAL_UMODE || csr_insn_addr == `csr_uindex(`RISCV_FORMAL_CSRC_NAME) `endif ); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = `csrget(`RISCV_FORMAL_CSRC_NAME, rmask); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = `csrget(`RISCV_FORMAL_CSRC_NAME, wmask); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRC_NAME, wdata); wire csr_write = !rvfi.insn[13] || rvfi.insn[19:15]; wire csr_read = rvfi.insn[11:7] != 0; wire csr_write_valid = csr_write && csr_insn_valid; wire csr_read_valid = csr_read && csr_insn_valid; wire [1:0] csr_mode = rvfi.insn[13:12]; wire [31:0] csr_rsval = rvfi.insn[14] ? rvfi.insn[19:15] : rvfi.rs1_rdata; // Setup for reg testing `rvformal_rand_const_reg [63:0] insn_order; reg [`RISCV_FORMAL_XLEN-1:0] wdata_shadow = 0; reg [`RISCV_FORMAL_XLEN-1:0] rdata_shadow = 0; reg csr_written = 0; reg csr_read_shadowed = 0; always @(posedge clock) begin if (reset) begin wdata_shadow = 0; rdata_shadow = 0; csr_written = 0; csr_read_shadowed = 0; end else begin // no writes without read that could decrease the value manually if (csr_write_valid) assume(csr_read_valid); if (check) begin assume(csr_read_shadowed); if (csr_read_shadowed && csr_read_valid && csr_insn_under_test) begin assert(csr_insn_rdata >= rdata_shadow || (csr_written && csr_insn_rdata >= wdata_shadow)); end end else begin csr_written = 0; if (csr_read_valid && csr_insn_under_test) begin if (csr_write_valid) begin assume(csr_insn_wdata[`RISCV_FORMAL_XLEN-1] == 0); wdata_shadow = csr_insn_wdata; csr_written = 1; end rdata_shadow = csr_insn_rdata; csr_read_shadowed = 1; end end end end endmodule ================================================ FILE: checks/rvfi_csrc_upcnt_check.sv ================================================ // Copyright (C) 2023 Krystine Dawn Sherwin // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_csrc_upcnt_check ( input clock, reset, check, `RVFI_INPUTS ); // Setup for csrs `RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX) localparam [11:0] csr_none = 12'hFFF; `RVFI_INDICES `define quoted(txt) txt `define csrget(_name, _type) rvfi.csr_``_name```quoted(_``_type) `define csr_mindex(_name) csr_mindex_``_name `define csr_sindex(_name) csr_sindex_``_name `define csr_uindex(_name) csr_uindex_``_name `define csr_mindexh(_name) csr_mindex_``_name```quoted(h) `define csr_sindexh(_name) csr_sindex_``_name```quoted(h) `define csr_uindexh(_name) csr_uindex_``_name```quoted(h) wire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0); wire [11:0] csr_insn_addr = rvfi.insn[31:20]; wire csr_insn_under_test = (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRC_NAME) `ifdef RISCV_FORMAL_SMODE || csr_insn_addr == `csr_sindex(`RISCV_FORMAL_CSRC_NAME) `endif `ifdef RISCV_FORMAL_UMODE || csr_insn_addr == `csr_uindex(`RISCV_FORMAL_CSRC_NAME) `endif ); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = `csrget(`RISCV_FORMAL_CSRC_NAME, rmask); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = `csrget(`RISCV_FORMAL_CSRC_NAME, wmask); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRC_NAME, wdata); wire csr_write = !rvfi.insn[13] || rvfi.insn[19:15]; wire csr_read = rvfi.insn[11:7] != 0; wire csr_write_valid = csr_write && csr_insn_valid; wire csr_read_valid = csr_read && csr_insn_valid; wire [1:0] csr_mode = rvfi.insn[13:12]; wire [31:0] csr_rsval = rvfi.insn[14] ? rvfi.insn[19:15] : rvfi.rs1_rdata; // Setup for reg testing `rvformal_rand_const_reg [63:0] insn_order; reg [`RISCV_FORMAL_XLEN-1:0] rdata_shadow = 0; reg csr_event_written = 0; reg csr_read_shadowed = 0; always @(posedge clock) begin if (reset) begin rdata_shadow = 0; csr_event_written = 0; csr_read_shadowed = 0; end else begin // No writes of CSR under test allowed assume (!(csr_write_valid && csr_insn_under_test)); if (check) begin assume(csr_read_shadowed); if (csr_read_valid && csr_insn_under_test) begin assert(csr_insn_rdata > rdata_shadow); end end else begin if (csr_read_valid && csr_insn_under_test) begin assume(csr_insn_rdata[31:0] < 'h F000_0000); // no overflow rdata_shadow = csr_insn_rdata; csr_read_shadowed = 1; end end end end endmodule ================================================ FILE: checks/rvfi_csrc_zero_check.sv ================================================ // Copyright (C) 2023 Krystine Dawn Sherwin // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_csrc_zero_check ( input clock, reset, check, `RVFI_INPUTS ); // Setup for csrs `RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX) localparam [11:0] csr_none = 12'hFFF; `RVFI_INDICES `define quoted(txt) txt `define csrget(_name, _type) rvfi.csr_``_name```quoted(_``_type) `define csr_mindex(_name) csr_mindex_``_name `define csr_sindex(_name) csr_sindex_``_name `define csr_uindex(_name) csr_uindex_``_name `define csr_mindexh(_name) csr_mindex_``_name```quoted(h) `define csr_sindexh(_name) csr_sindex_``_name```quoted(h) `define csr_uindexh(_name) csr_uindex_``_name```quoted(h) wire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0); wire [11:0] csr_insn_addr = rvfi.insn[31:20]; wire csr_insn_under_test = (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRC_NAME) `ifdef RISCV_FORMAL_SMODE || csr_insn_addr == `csr_sindex(`RISCV_FORMAL_CSRC_NAME) `endif `ifdef RISCV_FORMAL_UMODE || csr_insn_addr == `csr_uindex(`RISCV_FORMAL_CSRC_NAME) `endif ); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = `csrget(`RISCV_FORMAL_CSRC_NAME, rmask); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = `csrget(`RISCV_FORMAL_CSRC_NAME, wmask); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRC_NAME, wdata); `ifdef RISCV_FORMAL_CSRC_MASK wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata) & `RISCV_FORMAL_CSRC_MASK; `else wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata); `endif //RISCV_FORMAL_CSRC_MASK wire csr_write = !rvfi.insn[13] || rvfi.insn[19:15]; wire csr_read = rvfi.insn[11:7] != 0; wire csr_write_valid = csr_write && csr_insn_valid; wire csr_read_valid = csr_read && csr_insn_valid; wire [1:0] csr_mode = rvfi.insn[13:12]; wire [31:0] csr_rsval = rvfi.insn[14] ? rvfi.insn[19:15] : rvfi.rs1_rdata; // Setup for reg testing `rvformal_rand_const_reg [63:0] insn_order; reg [`RISCV_FORMAL_XLEN-1:0] wdata_shadow = 0; reg csr_written = 0; always @(posedge clock) begin if (reset) begin wdata_shadow = 0; csr_written = 0; end else begin if (check) begin if (csr_written && csr_read_valid && csr_insn_under_test) begin assert(csr_insn_rdata == 0); assume(wdata_shadow != 0); end end else begin if (csr_write_valid && csr_insn_under_test) begin // simplify things by only testing reg write, and not set/clear assume(csr_mode == 0 || csr_mode == 1); wdata_shadow = csr_insn_wdata; csr_written = 1; end end end end endmodule ================================================ FILE: checks/rvfi_csrw_check.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_csrw_check ( input clock, reset, check, `RVFI_INPUTS ); `RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX) localparam [11:0] csr_none = 12'hFFF; `RVFI_INDICES `define quoted(txt) txt `define csrget(_name, _type) rvfi.csr_``_name```quoted(_``_type) `define csr_mindex(_name) csr_mindex_``_name `define csr_sindex(_name) csr_sindex_``_name `define csr_uindex(_name) csr_uindex_``_name `define csr_mindexh(_name) csr_mindex_``_name```quoted(h) `define csr_sindexh(_name) csr_sindex_``_name```quoted(h) `define csr_uindexh(_name) csr_uindex_``_name```quoted(h) wire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0); wire [11:0] csr_insn_addr = rvfi.insn[31:20]; wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_arg = rvfi.insn[14] ? rvfi.insn[19:15] : rvfi.rs1_rdata; `ifdef RISCV_FORMAL_CSRWH wire csr_hi = rvfi.ixl == 1 && (csr_insn_addr == `csr_mindexh(`RISCV_FORMAL_CSRW_NAME) `ifdef RISCV_FORMAL_SMODE || csr_insn_addr == `csr_sindexh(`RISCV_FORMAL_CSRW_NAME) `endif `ifdef RISCV_FORMAL_UMODE || csr_insn_addr == `csr_uindexh(`RISCV_FORMAL_CSRW_NAME) `endif ); wire [63:0] csr_insn_rmask_full = `csrget(`RISCV_FORMAL_CSRW_NAME, rmask); wire [63:0] csr_insn_wmask_full = `csrget(`RISCV_FORMAL_CSRW_NAME, wmask); wire [63:0] csr_insn_rdata_full = `csrget(`RISCV_FORMAL_CSRW_NAME, rdata); wire [63:0] csr_insn_wdata_full = `csrget(`RISCV_FORMAL_CSRW_NAME, wdata); wire [63:0] csr_insn_changed_full = csr_insn_wmask_full & (~csr_insn_rmask_full | (csr_insn_rmask_full & (csr_insn_rdata_full ^ csr_insn_wdata_full))); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = (csr_hi ? csr_insn_rmask_full >> 32 : csr_insn_rmask_full) & (rvfi.ixl == 1 ? 'h FFFF_FFFF : -1); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = (csr_hi ? csr_insn_wmask_full >> 32 : csr_insn_wmask_full) & (rvfi.ixl == 1 ? 'h FFFF_FFFF : -1); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = (csr_hi ? csr_insn_rdata_full >> 32 : csr_insn_rdata_full) & (rvfi.ixl == 1 ? 'h FFFF_FFFF : -1); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = (csr_hi ? csr_insn_wdata_full >> 32 : csr_insn_wdata_full) & (rvfi.ixl == 1 ? 'h FFFF_FFFF : -1); `else wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = `csrget(`RISCV_FORMAL_CSRW_NAME, rmask); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = `csrget(`RISCV_FORMAL_CSRW_NAME, wmask); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRW_NAME, rdata); wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRW_NAME, wdata); `endif wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_smask = /* CSRRW, CSRRWI */ (rvfi.insn[13:12] == 1) ? csr_insn_arg : /* CSRRS, CSRRSI */ (rvfi.insn[13:12] == 2) ? csr_insn_arg : 0; wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_cmask = /* CSRRW, CSRRWI */ (rvfi.insn[13:12] == 1) ? ~csr_insn_arg : /* CSRCS, CSRRCI */ (rvfi.insn[13:12] == 3) ? csr_insn_arg : 0; wire csr_write = !rvfi.insn[13] || rvfi.insn[19:15]; wire csr_read = rvfi.insn[11:7] != 0; reg csr_illacc; always @* begin csr_illacc = 0; case (csr_insn_addr[11:8]) /* User CSRs */ 4'b 00_00, 4'b 01_00, 4'b 10_00: begin // read/write end 4'b 11_00: begin // read-only if (csr_write) csr_illacc = 1; end /* Supervisor CSRs */ 4'b 00_01, 4'b 01_01, 4'b 10_01: begin // read/write if (rvfi.mode < 1) csr_illacc = 1; end 4'b 11_01: begin // read-only if (rvfi.mode < 1) csr_illacc = 1; if (csr_write) csr_illacc = 1; end /* Reserved CSRs */ 4'b 00_10, 4'b 01_10, 4'b 10_10, 4'b 11_10: begin end /* Machine CSRs */ 4'b 00_11, 4'b 01_11, 4'b 10_11: begin // read/write if (rvfi.mode < 3) csr_illacc = 1; end 4'b 11_11: begin // read-only if (rvfi.mode < 3) csr_illacc = 1; if (csr_write) csr_illacc = 1; end endcase end wire [`RISCV_FORMAL_XLEN-1:0] effective_csr_insn_wmask = csr_insn_rmask | csr_insn_wmask; wire [`RISCV_FORMAL_XLEN-1:0] effective_csr_insn_wdata = (csr_insn_wdata & csr_insn_wmask) | (csr_insn_rdata & ~csr_insn_wmask); wire [`RISCV_FORMAL_XLEN-1:0] spec_pc_wdata = rvfi.pc_rdata + 4; wire insn_pma_x; `ifdef RISCV_FORMAL_PMA_MAP `RISCV_FORMAL_PMA_MAP insn_pma ( .address(rvfi.pc_rdata), .log2len(rvfi.insn[1:0] == 2'b11 ? 2'd2 : 2'd1), .X(insn_pma_x) ); `else assign insn_pma_x = 1; `endif integer i; always @* begin if (!reset && check) begin assume (csr_insn_valid); assume (csr_insn_addr != csr_none); assume (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRW_NAME) `ifdef RISCV_FORMAL_SMODE || csr_insn_addr == `csr_sindex(`RISCV_FORMAL_CSRW_NAME) `endif `ifdef RISCV_FORMAL_UMODE || csr_insn_addr == `csr_uindex(`RISCV_FORMAL_CSRW_NAME) `endif `ifdef RISCV_FORMAL_CSRWH || csr_hi `endif ); if (!`rvformal_addr_valid(rvfi.pc_rdata) || !insn_pma_x || csr_illacc) begin assert (rvfi.trap); assert (rvfi.rd_addr == 0); assert (rvfi.rd_wdata == 0); end else begin assert (!rvfi.trap); assert (rvfi.rd_addr == rvfi.insn[11:7]); assert (`rvformal_addr_eq(rvfi.pc_wdata, spec_pc_wdata)); if (rvfi.rd_addr == 0) begin assert (rvfi.rd_wdata == 0); end else begin assert (csr_insn_rmask == {`RISCV_FORMAL_XLEN{1'b1}}); assert (csr_insn_rdata == rvfi.rd_wdata); end assert (((csr_insn_smask | csr_insn_cmask) & ~effective_csr_insn_wmask) == 0); assert ((csr_insn_smask & ~effective_csr_insn_wdata) == 0); assert ((csr_insn_cmask & effective_csr_insn_wdata) == 0); `ifdef RISCV_FORMAL_CSRWH if (csr_hi) begin assert (csr_insn_changed_full[31:0] == 0); end else if (rvfi.ixl == 1) begin assert (csr_insn_changed_full[63:32] == 0); end `endif end assert (rvfi.mem_wmask == 0); end end endmodule ================================================ FILE: checks/rvfi_dmem_check.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_dmem_check ( input clock, reset, enable, output [`RISCV_FORMAL_XLEN-1:0] dmem_addr, `RVFI_INPUTS ); `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] dmem_addr_randval; assign dmem_addr = dmem_addr_randval; reg [`RISCV_FORMAL_XLEN-1:0] dmem_shadow; reg [`RISCV_FORMAL_XLEN/8-1:0] dmem_written = 0; integer channel_idx; integer i; always @(posedge clock) begin if (reset) begin dmem_written <= 0; end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin if (rvfi_valid[channel_idx] && rvfi_mem_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN] == dmem_addr && `rvformal_addr_valid(dmem_addr)) begin for (i = 0; i < `RISCV_FORMAL_XLEN/8; i = i+1) begin if (enable && rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 + i] && dmem_written[i]) assert(dmem_shadow[i*8 +: 8] == rvfi_mem_rdata[i*8 +: 8]); if (rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 + i]) begin dmem_shadow[i*8 +: 8] = rvfi_mem_wdata[i*8 +: 8]; dmem_written[i] = 1; end end end end end end endmodule ================================================ FILE: checks/rvfi_fault_check.sv ================================================ // check handling of memory faults // // This checks that a dynamically occuring memory fault causes a trap and that // the mcause csr correctly reports the cause of the trap. // // Copyright (C) 2017 Claire Xenia Wolf // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_fault_check ( input clock, reset, check, `RVFI_INPUTS ); `ifdef RISCV_FORMAL_CHANNEL_IDX localparam integer channel_idx = `RISCV_FORMAL_CHANNEL_IDX; `else genvar channel_idx; generate for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin:channel `endif (* keep *) wire valid = !reset && rvfi_valid[channel_idx]; (* keep *) wire [`RISCV_FORMAL_ILEN - 1 : 0] insn = rvfi_insn [channel_idx*`RISCV_FORMAL_ILEN +: `RISCV_FORMAL_ILEN]; (* keep *) wire trap = rvfi_trap [channel_idx]; (* keep *) wire mem_fault = rvfi_mem_fault[channel_idx]; (* keep *) wire halt = rvfi_halt [channel_idx]; (* keep *) wire intr = rvfi_intr [channel_idx]; (* keep *) wire [ 4 : 0] rs1_addr = rvfi_rs1_addr [channel_idx*5 +: 5]; (* keep *) wire [ 4 : 0] rs2_addr = rvfi_rs2_addr [channel_idx*5 +: 5]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] rs1_rdata = rvfi_rs1_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] rs2_rdata = rvfi_rs2_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [ 4 : 0] rd_addr = rvfi_rd_addr [channel_idx*5 +: 5]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] rd_wdata = rvfi_rd_wdata [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] pc_rdata = rvfi_pc_rdata [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] pc_wdata = rvfi_pc_wdata [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_addr = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_rdata = rvfi_mem_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_wdata = rvfi_mem_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_fault_rmask = rvfi_mem_fault_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_fault_wmask = rvfi_mem_fault_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; `ifdef RISCV_FORMAL_CSR_MCAUSE (* keep *) wire [`RISCV_FORMAL_XLEN-1:0] csr_mcause_wmask = rvfi_csr_mcause_wmask[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN-1:0] csr_mcause_wdata = rvfi_csr_mcause_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; `endif wire rfault = |mem_fault_rmask; wire wfault = |mem_fault_wmask; wire ifault = !(rfault || wfault); always @* begin if (!reset && check) begin assume(valid); if (mem_fault) begin assert (trap); assert (rd_addr == 0); assert (rd_wdata == 0); assert (mem_wmask == 0); cover (rfault); cover (wfault); cover (ifault); if (ifault) begin assert (insn == 0); end else begin assert (insn != 0); end `ifdef RISCV_FORMAL_CSR_MCAUSE if (wfault) begin assert (&csr_mcause_wmask); assert (csr_mcause_wdata == 7); end else if (rfault) begin assert (&csr_mcause_wmask); assert (csr_mcause_wdata == 5); end else if (ifault) begin assert (&csr_mcause_wmask); assert (csr_mcause_wdata == 1); end `endif else begin end end else begin assert (mem_fault_rmask == 0); assert (mem_fault_wmask == 0); end end end `ifndef RISCV_FORMAL_CHANNEL_IDX end endgenerate `endif endmodule ================================================ FILE: checks/rvfi_hang_check.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_hang_check ( input clock, reset, trig, check, `RVFI_INPUTS ); reg okay = 0; integer channel_idx; always @(posedge clock) begin if (reset) begin okay <= 0; end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin if (rvfi_valid[channel_idx]) okay <= 1; end if (check) begin assert(okay); end end for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin if (rvfi_valid[channel_idx]) begin assume(!rvfi_halt[channel_idx]); assume(rvfi_insn[(channel_idx+1)*`RISCV_FORMAL_ILEN-1 : channel_idx*`RISCV_FORMAL_ILEN] != 32'b 0001000_00101_00000_000_00000_1110011); // WFI `ifdef RISCV_FORMAL_WAITINSN assume(!(`RISCV_FORMAL_WAITINSN(rvfi_insn[(channel_idx+1)*`RISCV_FORMAL_ILEN-1 : channel_idx*`RISCV_FORMAL_ILEN]))); `endif end end end endmodule ================================================ FILE: checks/rvfi_ill_check.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_ill_check ( input clock, reset, check, `RVFI_INPUTS ); `ifdef RISCV_FORMAL_CHANNEL_IDX localparam integer channel_idx = `RISCV_FORMAL_CHANNEL_IDX; `else genvar channel_idx; generate for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin:channel `endif (* keep *) wire valid = !reset && rvfi_valid[channel_idx]; (* keep *) wire [`RISCV_FORMAL_ILEN - 1 : 0] insn = rvfi_insn [channel_idx*`RISCV_FORMAL_ILEN +: `RISCV_FORMAL_ILEN]; (* keep *) wire trap = rvfi_trap [channel_idx]; (* keep *) wire halt = rvfi_halt [channel_idx]; (* keep *) wire intr = rvfi_intr [channel_idx]; (* keep *) wire [ 4 : 0] rs1_addr = rvfi_rs1_addr [channel_idx*5 +: 5]; (* keep *) wire [ 4 : 0] rs2_addr = rvfi_rs2_addr [channel_idx*5 +: 5]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] rs1_rdata = rvfi_rs1_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] rs2_rdata = rvfi_rs2_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [ 4 : 0] rd_addr = rvfi_rd_addr [channel_idx*5 +: 5]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] rd_wdata = rvfi_rd_wdata [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] pc_rdata = rvfi_pc_rdata [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] pc_wdata = rvfi_pc_wdata [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_addr = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_rdata = rvfi_mem_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_wdata = rvfi_mem_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; always @* begin cover(!reset && check && valid && insn == 0); if (!reset && check) begin assume(valid); assume(insn == 0); assert(trap); assert(rd_addr == 0); assert(rd_wdata == 0); assert(mem_wmask == 0); end end `ifndef RISCV_FORMAL_CHANNEL_IDX end endgenerate `endif endmodule ================================================ FILE: checks/rvfi_imem_check.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_imem_check ( input clock, reset, enable, output [`RISCV_FORMAL_XLEN-1:0] imem_addr, output [15:0] imem_data, `RVFI_INPUTS ); `rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] imem_addr_randval; `rvformal_rand_const_reg [15:0] imem_data_randval; assign imem_addr = imem_addr_randval; assign imem_data = imem_data_randval; reg [`RISCV_FORMAL_XLEN-1:0] pc; reg [`RISCV_FORMAL_ILEN-1:0] insn; integer channel_idx; integer i; always @(posedge clock) begin if (reset) begin end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin if (enable && rvfi_valid[channel_idx]) begin pc = rvfi_pc_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; insn = rvfi_insn[channel_idx*`RISCV_FORMAL_ILEN +: `RISCV_FORMAL_ILEN]; if (`rvformal_addr_valid(pc) && pc == imem_addr) assert(insn[15:0] == imem_data); if (insn[1:0] == 2'b11 && `rvformal_addr_valid(pc+2) && pc+2 == imem_addr) assert(insn[31:16] == imem_data); end end end end endmodule ================================================ FILE: checks/rvfi_insn_check.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_insn_check ( input clock, reset, check, `RVFI_INPUTS ); `ifdef RISCV_FORMAL_CHANNEL_IDX localparam integer channel_idx = `RISCV_FORMAL_CHANNEL_IDX; `else genvar channel_idx; generate for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin:channel `endif (* keep *) wire valid = !reset && rvfi_valid[channel_idx]; (* keep *) wire [`RISCV_FORMAL_ILEN - 1 : 0] insn = rvfi_insn [channel_idx*`RISCV_FORMAL_ILEN +: `RISCV_FORMAL_ILEN]; (* keep *) wire trap = rvfi_trap [channel_idx]; (* keep *) wire halt = rvfi_halt [channel_idx]; (* keep *) wire intr = rvfi_intr [channel_idx]; (* keep *) wire [ 4 : 0] rs1_addr = rvfi_rs1_addr [channel_idx*5 +: 5]; (* keep *) wire [ 4 : 0] rs2_addr = rvfi_rs2_addr [channel_idx*5 +: 5]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] rs1_rdata = rvfi_rs1_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] rs2_rdata = rvfi_rs2_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [ 4 : 0] rd_addr = rvfi_rd_addr [channel_idx*5 +: 5]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] rd_wdata = rvfi_rd_wdata [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] pc_rdata = rvfi_pc_rdata [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] pc_wdata = rvfi_pc_wdata [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_addr = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_rdata = rvfi_mem_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_wdata = rvfi_mem_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; `ifdef RISCV_FORMAL_MEM_FAULT (* keep *) wire mem_fault = rvfi_mem_fault[channel_idx]; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_fault_rmask = rvfi_mem_fault_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_fault_wmask = rvfi_mem_fault_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8]; `endif `ifdef RISCV_FORMAL_CSR_MISA (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_misa_rdata = rvfi_csr_misa_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_misa_rmask = rvfi_csr_misa_rmask[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask; `endif (* keep *) wire spec_valid; (* keep *) wire spec_trap; (* keep *) wire [ 4 : 0] spec_rs1_addr; (* keep *) wire [ 4 : 0] spec_rs2_addr; (* keep *) wire [ 4 : 0] spec_rd_addr; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] rs1_rdata_or_zero = spec_rs1_addr != 0 ? rs1_rdata : 0; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] rs2_rdata_or_zero = spec_rs2_addr != 0 ? rs2_rdata : 0; `RISCV_FORMAL_INSN_MODEL insn_spec ( .rvfi_valid (valid ), .rvfi_insn (insn ), .rvfi_pc_rdata (pc_rdata ), .rvfi_rs1_rdata (rs1_rdata_or_zero ), .rvfi_rs2_rdata (rs2_rdata_or_zero ), .rvfi_mem_rdata (mem_rdata ), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata (csr_misa_rdata ), .spec_csr_misa_rmask (spec_csr_misa_rmask), `endif .spec_valid (spec_valid ), .spec_trap (spec_trap ), .spec_rs1_addr (spec_rs1_addr ), .spec_rs2_addr (spec_rs2_addr ), .spec_rd_addr (spec_rd_addr ), .spec_rd_wdata (spec_rd_wdata ), .spec_pc_wdata (spec_pc_wdata ), .spec_mem_addr (spec_mem_addr ), .spec_mem_rmask (spec_mem_rmask ), .spec_mem_wmask (spec_mem_wmask ), .spec_mem_wdata (spec_mem_wdata ) ); wire insn_pma_x, mem_pma_r, mem_pma_w; wire [1:0] mem_log2len = ((spec_mem_rmask | spec_mem_wmask) & 8'b 1111_0000) ? 3 : ((spec_mem_rmask | spec_mem_wmask) & 8'b 0000_1100) ? 2 : ((spec_mem_rmask | spec_mem_wmask) & 8'b 0000_0010) ? 1 : 0; `ifdef RISCV_FORMAL_PMA_MAP `RISCV_FORMAL_PMA_MAP insn_pma ( .address(pc_rdata), .log2len(insn[1:0] == 2'b11 ? 2'd2 : 2'd1), .X(insn_pma_x) ); `RISCV_FORMAL_PMA_MAP mem_pma ( .address(spec_mem_addr), .log2len(mem_log2len), .R(mem_pma_r), .W(mem_pma_w) ); `else assign insn_pma_x = 1; assign mem_pma_r = 1; assign mem_pma_w = 1; `endif `ifdef RISCV_FORMAL_MEM_FAULT wire mem_access_fault = mem_fault || `else wire mem_access_fault = `endif (spec_mem_rmask && !mem_pma_r) || (spec_mem_wmask && !mem_pma_w) || ((spec_mem_rmask || spec_mem_wmask) && !`rvformal_addr_valid(spec_mem_addr)); integer i; always @* begin if (!reset) begin cover(spec_valid); cover(spec_valid && !trap); cover(check && spec_valid); cover(check && spec_valid && !trap); end if (!reset && check) begin assume(spec_valid); if (!`rvformal_addr_valid(pc_rdata) || !insn_pma_x || mem_access_fault) begin assert(trap); assert(rd_addr == 0); assert(rd_wdata == 0); assert(mem_wmask == 0); `ifdef RISCV_FORMAL_MEM_FAULT if (mem_fault) begin assert(mem_rmask == 0); assert(spec_mem_wmask || spec_mem_rmask); assert(`rvformal_addr_eq(spec_mem_addr, mem_addr)); assert(mem_fault_wmask == spec_mem_wmask); assert((mem_fault_rmask & spec_mem_rmask) == spec_mem_rmask); end `endif end else begin `ifdef RISCV_FORMAL_CSR_MISA assert((spec_csr_misa_rmask & csr_misa_rmask) == spec_csr_misa_rmask); `endif if (rs1_addr == 0) assert(rs1_rdata == 0); if (rs2_addr == 0) assert(rs2_rdata == 0); if (!spec_trap) begin if (spec_rs1_addr != 0) assert(spec_rs1_addr == rs1_addr); if (spec_rs2_addr != 0) assert(spec_rs2_addr == rs2_addr); assert(spec_rd_addr == rd_addr); assert(spec_rd_wdata == rd_wdata); assert(`rvformal_addr_eq(spec_pc_wdata, pc_wdata)); if (spec_mem_wmask || spec_mem_rmask) begin assert(`rvformal_addr_eq(spec_mem_addr, mem_addr)); end for (i = 0; i < `RISCV_FORMAL_XLEN/8; i = i+1) begin if (spec_mem_wmask[i]) begin assert(mem_wmask[i]); assert(spec_mem_wdata[i*8 +: 8] == mem_wdata[i*8 +: 8]); end else if (mem_wmask[i]) begin assert(mem_rmask[i]); assert(mem_rdata[i*8 +: 8] == mem_wdata[i*8 +: 8]); end if (spec_mem_rmask[i]) begin assert(mem_rmask[i]); end end end assert(spec_trap == trap); end end end `ifndef RISCV_FORMAL_CHANNEL_IDX end endgenerate `endif endmodule ================================================ FILE: checks/rvfi_liveness_check.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_liveness_check ( input clock, reset, trig, check, `RVFI_INPUTS ); `rvformal_rand_const_reg [63:0] insn_order; reg found_next_insn = 0; integer channel_idx; always @(posedge clock) begin if (reset) begin found_next_insn = 0; end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order+1) begin found_next_insn = 1; end end if (trig) begin assume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]); assume(!rvfi_halt[`RISCV_FORMAL_CHANNEL_IDX]); assume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]); end if (check) begin assert(found_next_insn); end end end endmodule ================================================ FILE: checks/rvfi_macros.py ================================================ #!/usr/bin/env python3 # # Copyright (C) 2017 Claire Xenia Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. from dataclasses import dataclass, field from typing import Optional, List, Tuple @dataclass class Group: name: str signals: List[Tuple[str, str]] channels: Optional[str] = None condition: Optional[str] = None nosep: bool = False csr_conn32: bool = False append: List['Group'] = field(default_factory=list) def __post_init__(self): self._cw = max((len(width) for width, name in self.signals), default=0) self._cn = max((len(name) for width, name in self.signals), default=0) self._has_conn32 = self.csr_conn32 or any(g._has_conn32 for g in self.append) def bitrange(self, width, no_channel=False): if no_channel or self.channels is None: if str(width).strip() == '1': return f"[{'':>{self._cw}} 0 : 0]" else: return f"[{width:>{self._cw}} - 1 : 0]" elif str(width).strip() == '1': return f"[{self.channels} {'':>{self._cw}} - 1 : 0]" else: return f"[{self.channels} * {width:>{self._cw}} - 1 : 0]" def channel_idx(self, width): if str(width).strip() == '1': return f"[ _idx {'':>{self._cw}} +: {width:>{self._cw}}]" else: return f"[(_idx)*({width:>{self._cw}}) +: {width:>{self._cw}}]" def macro_name(self, s, extra=""): if self.name.upper() == self.name: if s == "channel": return f"{self.name}_GETCHANNEL{extra.upper()}(_idx)" elif s == "channel_conn": return f"{self.name}_CHANNEL_CONN{extra.upper()}(_idx)" else: return f"{self.name}_{s.upper()}{extra.upper()}" else: if s == "channel": return f"{self.name}_channel{extra}(_idx)" elif s == "channel_conn": return f"{self.name}_channel_conn{extra}(_idx)" else: return f"{self.name}_{s}{extra}" def macro_name_nosep(self, s): if self.nosep: return self.macro_name(s, extra="_nosep") else: return self.macro_name(s) def commas(self, parts, suffix=()): if (self.condition and not self.nosep) or len(parts) < 2: return " \\\n ".join([", \\\n ".join(parts), *suffix]) else: first, *parts = parts return " \\\n ".join([first, ", \\\n ".join(parts), *suffix]) def high_name(self, name): parts = name.split('_') parts[-2] += 'h' return '_'.join(parts) def print_macros(self): if self.condition: print(f"`ifdef {self.condition}") print(self.commas([f"`define {self.macro_name('wires')}"], [ f"(* keep *) wire {self.bitrange(width)} rvfi_{name:<{self._cn}};" for width, name in self.signals ] + [ "`" + group.macro_name('wires') for group in self.append ])) print(self.commas([f"`define {self.macro_name_nosep('outputs')}"] + [ f"output {self.bitrange(width)} rvfi_{name:<{self._cn}}" for width, name in self.signals ], [ "`" + group.macro_name('outputs') for group in self.append ])) print(self.commas([f"`define {self.macro_name_nosep('channel_outputs')}"] + [ f"output {self.bitrange(width, no_channel=True)} rvfi_{name:<{self._cn}}" for width, name in self.signals ], [ "`" + group.macro_name('channel_outputs') for group in self.append ])) print(self.commas([f"`define {self.macro_name_nosep('inputs')}"] + [ f"input {self.bitrange(width)} rvfi_{name:<{self._cn}}" for width, name in self.signals ], [ "`" + group.macro_name('inputs') for group in self.append ])) print(self.commas([f"`define {self.macro_name_nosep('channel_inputs')}"] + [ f"input {self.bitrange(width, no_channel=True)} rvfi_{name:<{self._cn}}" for width, name in self.signals ], [ "`" + group.macro_name('channel_inputs') for group in self.append ])) print(self.commas([f"`define {self.macro_name_nosep('conn')}"] + [ f".rvfi_{name:<{self._cn}} (rvfi_{name:<{self._cn}})" for width, name in self.signals ], [ "`" + group.macro_name('conn') for group in self.append ])) print(self.commas([f"`define {self.macro_name_nosep('channel_conn')}"] + [ f".rvfi_{name:<{self._cn}} (rvfi_{name:<{self._cn}} {self.channel_idx(width)})" for width, name in self.signals ], [ "`" + group.macro_name('channel_conn') for group in self.append ])) if self.csr_conn32: cn = self._cn + self.csr_conn32 print(self.commas([f"`define {self.macro_name_nosep('conn32')}"] + [ f".rvfi_{name:<{cn}} (rvfi_{name:<{self._cn}}[31: 0])" for width, name in self.signals ] + [ f".rvfi_{self.high_name(name):<{cn}} (rvfi_{name:<{self._cn}}[63:32])" for width, name in self.signals ], [ "`" + group.macro_name('conn32') for group in self.append ])) elif self._has_conn32: print(self.commas([f"`define {self.macro_name_nosep('conn32')}"] + [ f".rvfi_{name:<{self._cn}} (rvfi_{name:<{self._cn}})" for width, name in self.signals ], [ "`" + group.macro_name('conn32' if group._has_conn32 else 'conn') for group in self.append ])) if self.channels: print(self.commas([f"`define {self.macro_name('channel')}"], [ f"wire {self.bitrange(width, True)} {name:<{self._cn}} = " f"rvfi_{name:<{self._cn}} {self.channel_idx(width)};" for width, name in self.signals ] + [ "`" + group.macro_name('channel') for group in self.append if group.channels ])) print(self.commas([f"`define {self.macro_name('signals')}"], [ f"`RISCV_FORMAL_CHANNEL_SIGNAL({self.channels}, {width:>{self._cw}}, {name:<{self._cn}})" for width, name in self.signals ] + [ "`" + group.macro_name('signals') for group in self.append if group.channels ])) if self.nosep: print(f"`define {self.macro_name('outputs')} , `{self.macro_name_nosep('outputs')}") print(f"`define {self.macro_name('inputs')} , `{self.macro_name_nosep('inputs')}") print(f"`define {self.macro_name('conn')} , `{self.macro_name_nosep('conn')}") print(f"`define {self.macro_name('channel_outputs')} , `{self.macro_name_nosep('channel_outputs')}") print(f"`define {self.macro_name('channel_inputs')} , `{self.macro_name_nosep('channel_inputs')}") print(f"`define {self.macro_name('channel_conn')} , `{self.macro_name_nosep('channel_conn')}") if self._has_conn32: print(f"`define {self.macro_name('conn32')}") if self.condition: print("`else") print(f"`define {self.macro_name('wires')}") print(f"`define {self.macro_name('outputs')}") print(f"`define {self.macro_name('inputs')}") print(f"`define {self.macro_name('conn')}") if self._has_conn32: print(f"`define {self.macro_name('conn32')}") if self.channels: print(f"`define {self.macro_name('channel')}") print("`endif") if self.name.upper() == self.name: print("") print(f"`define {self.name}_CHANNEL(_name, _idx) \\") print("generate if(1) begin:_name \\") print(f" `{self.name}_GETCHANNEL(_idx) \\") print("end endgenerate") return self @dataclass class Csr: len: str name: str mindex: Optional[int] = None sindex: Optional[int] = None uindex: Optional[int] = None hmindex: Optional[int] = None hsindex: Optional[int] = None huindex: Optional[int] = None csrs = [ Csr("xlen", "fflags", None, None, None), Csr("xlen", "frm", None, None, None), Csr("xlen", "fcsr", None, None, None), Csr("xlen", "mvendorid", 0xF11, None, None), Csr("xlen", "marchid", 0xF12, None, None), Csr("xlen", "mimpid", 0xF13, None, None), Csr("xlen", "mhartid", 0xF14, None, None), Csr("xlen", "mconfigptr", 0xF15, None, None), Csr("xlen", "mstatus", 0x300, None, None), Csr("xlen", "mstatush", 0x310, None, None), Csr("xlen", "misa", 0x301, None, None), Csr("xlen", "medeleg", 0x302, None, None), Csr("xlen", "mideleg", 0x303, None, None), Csr("xlen", "mie", 0x304, None, None), Csr("xlen", "mtvec", 0x305, None, None), Csr("xlen", "mcounteren", 0x306, None, None), Csr("xlen", "mscratch", 0x340, None, None), Csr("xlen", "mepc", 0x341, None, None), Csr("xlen", "mcause", 0x342, None, None), Csr("xlen", "mtval", 0x343, None, None), Csr("xlen", "mip", 0x344, None, None), Csr("xlen", "mtinst", 0x34A, None, None), Csr("xlen", "mtval2", 0x34B, None, None), Csr("xlen", "mcountinhibit", 0x320, None, None), Csr("xlen", "menvcfg", 0x30A, None, None), Csr("xlen", "menvcfgh", 0x31A, None, None), *( Csr("xlen", f"pmpcfg{i}", 0x3A0 + i, None, None) for i in range(16) ), *( Csr("xlen", f"pmpaddr{i}", 0x3B0 + i, None, None) for i in range(64) ), *( Csr("xlen", f"mhpmevent{i}", 0x320 + i, None, None) for i in range(3, 32) ), Csr("64", "mcycle", 0xB00, None, 0xC00, 0xB80, None, 0xC80), Csr("64", "time", None, None, 0xC01, None, None, 0xC01), Csr("64", "minstret", 0xB02, None, 0xC02, 0xB82, None, 0xC82), *( Csr("64", f"mhpmcounter{i}", 0xB00 + i, None, 0xC00 + i, 0xB80 + i, None, 0xC80 + i) for i in range(3, 32) ), ] print("// Generated by rvfi_macros.py") print("") print("`ifdef YOSYS") print("`define rvformal_rand_reg rand reg") print("`define rvformal_rand_const_reg rand const reg") print("`else") print("`ifdef SIMULATION") print("`define rvformal_rand_reg reg") print("`define rvformal_rand_const_reg reg") print("`else") print("`define rvformal_rand_reg wire") print("`define rvformal_rand_const_reg reg") print("`endif") print("`endif") print("") print("`ifndef RISCV_FORMAL_VALIDADDR") print("`define RISCV_FORMAL_VALIDADDR(addr) 1") print("`endif") print("") print("`ifndef RISCV_FORMAL_IOADDR") print("`define RISCV_FORMAL_IOADDR(addr) 1") print("`endif") print("") print("`define rvformal_addr_valid(a) (`RISCV_FORMAL_VALIDADDR(a))") print("`define rvformal_addr_io(a) (`rvformal_addr_valid(a) && (`RISCV_FORMAL_IOADDR(a)))") print("`define rvformal_addr_eq(a, b) ((`rvformal_addr_valid(a) == `rvformal_addr_valid(b)) && (!`rvformal_addr_valid(a) || (a == b)))") print("`define rvformal_addr_eq_io(a, b) (`rvformal_addr_io(a) ? `rvformal_addr_io(b) : `rvformal_addr_eq(a, b))") print("") csr_groups = [] def csr_index(index): if index is None: return "12'hFFF" else: return f"12'h{index:03X}" for csr in csrs: width = {"64": "64", "xlen": "`RISCV_FORMAL_XLEN"}[csr.len] csr_groups.append(Group( condition=f"RISCV_FORMAL_CSR_{csr.name.upper()}", name=f"rvformal_csr_{csr.name}", channels="`RISCV_FORMAL_NRET", csr_conn32=csr.len == "64", signals=[ (width, f"csr_{csr.name}_rmask"), (width, f"csr_{csr.name}_wmask"), (width, f"csr_{csr.name}_rdata"), (width, f"csr_{csr.name}_wdata"), ] ).print_macros()) print(f"`define rvformal_csr_{csr.name}_indices \\") print(f"localparam [11:0] csr_mindex_{csr.name} = {csr_index(csr.mindex)}; \\") print(f"localparam [11:0] csr_sindex_{csr.name} = {csr_index(csr.sindex)}; \\") print(f"localparam [11:0] csr_uindex_{csr.name} = {csr_index(csr.uindex)}; \\") if csr.len == "64": print(f"localparam [11:0] csr_mindex_{csr.name}h = {csr_index(csr.hmindex)}; \\") print(f"localparam [11:0] csr_sindex_{csr.name}h = {csr_index(csr.hsindex)}; \\") print(f"localparam [11:0] csr_uindex_{csr.name}h = {csr_index(csr.huindex)}; \\") print() print("`define RVFI_INDICES \\") for csr in csrs: print(f"`rvformal_csr_{csr.name}_indices \\") print("`rvformal_custom_csr_indices") print() # Do not print this group, we'll use user macros when defined instead custom_csr = Group(name="rvformal_custom_csr", signals=[], channels="`RISCV_FORMAL_NRET",) for macro in ["inputs", "wires", "conn", "channel", "signals", "outputs", "indices"]: print(f"`ifdef RISCV_FORMAL_CUSTOM_CSR_{macro.upper()}") if (macro == "channel"): print(f"`define rvformal_custom_csr_{macro}(_idx) `RISCV_FORMAL_CUSTOM_CSR_{macro.upper()}(_idx)") print(f"`else") print(f"`define rvformal_custom_csr_{macro}(_idx)") else: print(f"`define rvformal_custom_csr_{macro} `RISCV_FORMAL_CUSTOM_CSR_{macro.upper()}") print(f"`else") print(f"`define rvformal_custom_csr_{macro}") print(f"`endif") group_rollback = Group( condition="RISCV_FORMAL_ROLLBACK", name="rvformal_rollback", signals=[ (" 1", "rollback_valid"), ("64", "rollback_order"), ] ).print_macros() group_extamo = Group( condition="RISCV_FORMAL_EXTAMO", name="rvformal_extamo", channels="`RISCV_FORMAL_NRET", signals=[ ("1", "mem_extamo"), ] ).print_macros() group_fault = Group( condition="RISCV_FORMAL_MEM_FAULT", name="rvformal_mem_fault", channels="`RISCV_FORMAL_NRET", signals=[ (" 1 ", "mem_fault"), ("`RISCV_FORMAL_XLEN/8", "mem_fault_rmask"), ("`RISCV_FORMAL_XLEN/8", "mem_fault_wmask"), ] ).print_macros() rvfi = Group( name="RVFI", channels="`RISCV_FORMAL_NRET", signals=[ (" 1 ", "valid "), (" 64 ", "order "), ("`RISCV_FORMAL_ILEN ", "insn "), (" 1 ", "trap "), (" 1 ", "halt "), (" 1 ", "intr "), (" 2 ", "mode "), (" 2 ", "ixl "), (" 5 ", "rs1_addr "), (" 5 ", "rs2_addr "), ("`RISCV_FORMAL_XLEN ", "rs1_rdata"), ("`RISCV_FORMAL_XLEN ", "rs2_rdata"), (" 5 ", "rd_addr "), ("`RISCV_FORMAL_XLEN ", "rd_wdata "), ("`RISCV_FORMAL_XLEN ", "pc_rdata "), ("`RISCV_FORMAL_XLEN ", "pc_wdata "), ("`RISCV_FORMAL_XLEN ", "mem_addr "), ("`RISCV_FORMAL_XLEN/8", "mem_rmask"), ("`RISCV_FORMAL_XLEN/8", "mem_wmask"), ("`RISCV_FORMAL_XLEN ", "mem_rdata"), ("`RISCV_FORMAL_XLEN ", "mem_wdata"), ], append = [group_extamo, group_rollback, group_fault, *csr_groups, custom_csr] ).print_macros() rvfi = Group( condition="RISCV_FORMAL_BUS", name="RVFI_BUS", channels="`RISCV_FORMAL_NBUS", nosep=True, signals=[ (" 1 ", "bus_valid"), (" 1 ", "bus_insn "), (" 1 ", "bus_data "), (" 1 ", "bus_fault"), (" `RISCV_FORMAL_XLEN ", "bus_addr "), ("`RISCV_FORMAL_BUSLEN/8", "bus_rmask"), ("`RISCV_FORMAL_BUSLEN/8", "bus_wmask"), ("`RISCV_FORMAL_BUSLEN ", "bus_rdata"), ("`RISCV_FORMAL_BUSLEN ", "bus_wdata"), ], ).print_macros() ================================================ FILE: checks/rvfi_macros.vh ================================================ // Generated by rvfi_macros.py `ifdef YOSYS `define rvformal_rand_reg rand reg `define rvformal_rand_const_reg rand const reg `else `ifdef SIMULATION `define rvformal_rand_reg reg `define rvformal_rand_const_reg reg `else `define rvformal_rand_reg wire `define rvformal_rand_const_reg reg `endif `endif `ifndef RISCV_FORMAL_VALIDADDR `define RISCV_FORMAL_VALIDADDR(addr) 1 `endif `ifndef RISCV_FORMAL_IOADDR `define RISCV_FORMAL_IOADDR(addr) 1 `endif `define rvformal_addr_valid(a) (`RISCV_FORMAL_VALIDADDR(a)) `define rvformal_addr_io(a) (`rvformal_addr_valid(a) && (`RISCV_FORMAL_IOADDR(a))) `define rvformal_addr_eq(a, b) ((`rvformal_addr_valid(a) == `rvformal_addr_valid(b)) && (!`rvformal_addr_valid(a) || (a == b))) `define rvformal_addr_eq_io(a, b) (`rvformal_addr_io(a) ? `rvformal_addr_io(b) : `rvformal_addr_eq(a, b)) `ifdef RISCV_FORMAL_CSR_FFLAGS `define rvformal_csr_fflags_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wdata; `define rvformal_csr_fflags_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wdata `define rvformal_csr_fflags_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wdata `define rvformal_csr_fflags_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wdata `define rvformal_csr_fflags_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wdata `define rvformal_csr_fflags_conn, \ .rvfi_csr_fflags_rmask (rvfi_csr_fflags_rmask), \ .rvfi_csr_fflags_wmask (rvfi_csr_fflags_wmask), \ .rvfi_csr_fflags_rdata (rvfi_csr_fflags_rdata), \ .rvfi_csr_fflags_wdata (rvfi_csr_fflags_wdata) `define rvformal_csr_fflags_channel_conn(_idx), \ .rvfi_csr_fflags_rmask (rvfi_csr_fflags_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_fflags_wmask (rvfi_csr_fflags_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_fflags_rdata (rvfi_csr_fflags_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_fflags_wdata (rvfi_csr_fflags_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_fflags_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fflags_rmask = rvfi_csr_fflags_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fflags_wmask = rvfi_csr_fflags_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fflags_rdata = rvfi_csr_fflags_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fflags_wdata = rvfi_csr_fflags_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_fflags_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fflags_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fflags_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fflags_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fflags_wdata) `else `define rvformal_csr_fflags_wires `define rvformal_csr_fflags_outputs `define rvformal_csr_fflags_inputs `define rvformal_csr_fflags_conn `define rvformal_csr_fflags_channel(_idx) `endif `define rvformal_csr_fflags_indices \ localparam [11:0] csr_mindex_fflags = 12'hFFF; \ localparam [11:0] csr_sindex_fflags = 12'hFFF; \ localparam [11:0] csr_uindex_fflags = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_FRM `define rvformal_csr_frm_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wdata; `define rvformal_csr_frm_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wdata `define rvformal_csr_frm_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wdata `define rvformal_csr_frm_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wdata `define rvformal_csr_frm_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wdata `define rvformal_csr_frm_conn, \ .rvfi_csr_frm_rmask (rvfi_csr_frm_rmask), \ .rvfi_csr_frm_wmask (rvfi_csr_frm_wmask), \ .rvfi_csr_frm_rdata (rvfi_csr_frm_rdata), \ .rvfi_csr_frm_wdata (rvfi_csr_frm_wdata) `define rvformal_csr_frm_channel_conn(_idx), \ .rvfi_csr_frm_rmask (rvfi_csr_frm_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_frm_wmask (rvfi_csr_frm_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_frm_rdata (rvfi_csr_frm_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_frm_wdata (rvfi_csr_frm_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_frm_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_frm_rmask = rvfi_csr_frm_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_frm_wmask = rvfi_csr_frm_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_frm_rdata = rvfi_csr_frm_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_frm_wdata = rvfi_csr_frm_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_frm_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_frm_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_frm_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_frm_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_frm_wdata) `else `define rvformal_csr_frm_wires `define rvformal_csr_frm_outputs `define rvformal_csr_frm_inputs `define rvformal_csr_frm_conn `define rvformal_csr_frm_channel(_idx) `endif `define rvformal_csr_frm_indices \ localparam [11:0] csr_mindex_frm = 12'hFFF; \ localparam [11:0] csr_sindex_frm = 12'hFFF; \ localparam [11:0] csr_uindex_frm = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_FCSR `define rvformal_csr_fcsr_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wdata; `define rvformal_csr_fcsr_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wdata `define rvformal_csr_fcsr_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wdata `define rvformal_csr_fcsr_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wdata `define rvformal_csr_fcsr_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wdata `define rvformal_csr_fcsr_conn, \ .rvfi_csr_fcsr_rmask (rvfi_csr_fcsr_rmask), \ .rvfi_csr_fcsr_wmask (rvfi_csr_fcsr_wmask), \ .rvfi_csr_fcsr_rdata (rvfi_csr_fcsr_rdata), \ .rvfi_csr_fcsr_wdata (rvfi_csr_fcsr_wdata) `define rvformal_csr_fcsr_channel_conn(_idx), \ .rvfi_csr_fcsr_rmask (rvfi_csr_fcsr_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_fcsr_wmask (rvfi_csr_fcsr_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_fcsr_rdata (rvfi_csr_fcsr_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_fcsr_wdata (rvfi_csr_fcsr_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_fcsr_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fcsr_rmask = rvfi_csr_fcsr_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fcsr_wmask = rvfi_csr_fcsr_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fcsr_rdata = rvfi_csr_fcsr_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fcsr_wdata = rvfi_csr_fcsr_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_fcsr_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fcsr_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fcsr_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fcsr_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fcsr_wdata) `else `define rvformal_csr_fcsr_wires `define rvformal_csr_fcsr_outputs `define rvformal_csr_fcsr_inputs `define rvformal_csr_fcsr_conn `define rvformal_csr_fcsr_channel(_idx) `endif `define rvformal_csr_fcsr_indices \ localparam [11:0] csr_mindex_fcsr = 12'hFFF; \ localparam [11:0] csr_sindex_fcsr = 12'hFFF; \ localparam [11:0] csr_uindex_fcsr = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MVENDORID `define rvformal_csr_mvendorid_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wdata; `define rvformal_csr_mvendorid_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wdata `define rvformal_csr_mvendorid_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wdata `define rvformal_csr_mvendorid_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wdata `define rvformal_csr_mvendorid_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wdata `define rvformal_csr_mvendorid_conn, \ .rvfi_csr_mvendorid_rmask (rvfi_csr_mvendorid_rmask), \ .rvfi_csr_mvendorid_wmask (rvfi_csr_mvendorid_wmask), \ .rvfi_csr_mvendorid_rdata (rvfi_csr_mvendorid_rdata), \ .rvfi_csr_mvendorid_wdata (rvfi_csr_mvendorid_wdata) `define rvformal_csr_mvendorid_channel_conn(_idx), \ .rvfi_csr_mvendorid_rmask (rvfi_csr_mvendorid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mvendorid_wmask (rvfi_csr_mvendorid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mvendorid_rdata (rvfi_csr_mvendorid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mvendorid_wdata (rvfi_csr_mvendorid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mvendorid_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mvendorid_rmask = rvfi_csr_mvendorid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mvendorid_wmask = rvfi_csr_mvendorid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mvendorid_rdata = rvfi_csr_mvendorid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mvendorid_wdata = rvfi_csr_mvendorid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mvendorid_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mvendorid_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mvendorid_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mvendorid_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mvendorid_wdata) `else `define rvformal_csr_mvendorid_wires `define rvformal_csr_mvendorid_outputs `define rvformal_csr_mvendorid_inputs `define rvformal_csr_mvendorid_conn `define rvformal_csr_mvendorid_channel(_idx) `endif `define rvformal_csr_mvendorid_indices \ localparam [11:0] csr_mindex_mvendorid = 12'hF11; \ localparam [11:0] csr_sindex_mvendorid = 12'hFFF; \ localparam [11:0] csr_uindex_mvendorid = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MARCHID `define rvformal_csr_marchid_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wdata; `define rvformal_csr_marchid_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wdata `define rvformal_csr_marchid_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wdata `define rvformal_csr_marchid_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wdata `define rvformal_csr_marchid_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wdata `define rvformal_csr_marchid_conn, \ .rvfi_csr_marchid_rmask (rvfi_csr_marchid_rmask), \ .rvfi_csr_marchid_wmask (rvfi_csr_marchid_wmask), \ .rvfi_csr_marchid_rdata (rvfi_csr_marchid_rdata), \ .rvfi_csr_marchid_wdata (rvfi_csr_marchid_wdata) `define rvformal_csr_marchid_channel_conn(_idx), \ .rvfi_csr_marchid_rmask (rvfi_csr_marchid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_marchid_wmask (rvfi_csr_marchid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_marchid_rdata (rvfi_csr_marchid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_marchid_wdata (rvfi_csr_marchid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_marchid_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_marchid_rmask = rvfi_csr_marchid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_marchid_wmask = rvfi_csr_marchid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_marchid_rdata = rvfi_csr_marchid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_marchid_wdata = rvfi_csr_marchid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_marchid_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_marchid_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_marchid_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_marchid_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_marchid_wdata) `else `define rvformal_csr_marchid_wires `define rvformal_csr_marchid_outputs `define rvformal_csr_marchid_inputs `define rvformal_csr_marchid_conn `define rvformal_csr_marchid_channel(_idx) `endif `define rvformal_csr_marchid_indices \ localparam [11:0] csr_mindex_marchid = 12'hF12; \ localparam [11:0] csr_sindex_marchid = 12'hFFF; \ localparam [11:0] csr_uindex_marchid = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MIMPID `define rvformal_csr_mimpid_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wdata; `define rvformal_csr_mimpid_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wdata `define rvformal_csr_mimpid_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wdata `define rvformal_csr_mimpid_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wdata `define rvformal_csr_mimpid_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wdata `define rvformal_csr_mimpid_conn, \ .rvfi_csr_mimpid_rmask (rvfi_csr_mimpid_rmask), \ .rvfi_csr_mimpid_wmask (rvfi_csr_mimpid_wmask), \ .rvfi_csr_mimpid_rdata (rvfi_csr_mimpid_rdata), \ .rvfi_csr_mimpid_wdata (rvfi_csr_mimpid_wdata) `define rvformal_csr_mimpid_channel_conn(_idx), \ .rvfi_csr_mimpid_rmask (rvfi_csr_mimpid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mimpid_wmask (rvfi_csr_mimpid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mimpid_rdata (rvfi_csr_mimpid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mimpid_wdata (rvfi_csr_mimpid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mimpid_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mimpid_rmask = rvfi_csr_mimpid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mimpid_wmask = rvfi_csr_mimpid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mimpid_rdata = rvfi_csr_mimpid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mimpid_wdata = rvfi_csr_mimpid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mimpid_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mimpid_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mimpid_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mimpid_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mimpid_wdata) `else `define rvformal_csr_mimpid_wires `define rvformal_csr_mimpid_outputs `define rvformal_csr_mimpid_inputs `define rvformal_csr_mimpid_conn `define rvformal_csr_mimpid_channel(_idx) `endif `define rvformal_csr_mimpid_indices \ localparam [11:0] csr_mindex_mimpid = 12'hF13; \ localparam [11:0] csr_sindex_mimpid = 12'hFFF; \ localparam [11:0] csr_uindex_mimpid = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHARTID `define rvformal_csr_mhartid_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wdata; `define rvformal_csr_mhartid_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wdata `define rvformal_csr_mhartid_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wdata `define rvformal_csr_mhartid_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wdata `define rvformal_csr_mhartid_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wdata `define rvformal_csr_mhartid_conn, \ .rvfi_csr_mhartid_rmask (rvfi_csr_mhartid_rmask), \ .rvfi_csr_mhartid_wmask (rvfi_csr_mhartid_wmask), \ .rvfi_csr_mhartid_rdata (rvfi_csr_mhartid_rdata), \ .rvfi_csr_mhartid_wdata (rvfi_csr_mhartid_wdata) `define rvformal_csr_mhartid_channel_conn(_idx), \ .rvfi_csr_mhartid_rmask (rvfi_csr_mhartid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhartid_wmask (rvfi_csr_mhartid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhartid_rdata (rvfi_csr_mhartid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhartid_wdata (rvfi_csr_mhartid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhartid_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhartid_rmask = rvfi_csr_mhartid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhartid_wmask = rvfi_csr_mhartid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhartid_rdata = rvfi_csr_mhartid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhartid_wdata = rvfi_csr_mhartid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhartid_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhartid_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhartid_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhartid_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhartid_wdata) `else `define rvformal_csr_mhartid_wires `define rvformal_csr_mhartid_outputs `define rvformal_csr_mhartid_inputs `define rvformal_csr_mhartid_conn `define rvformal_csr_mhartid_channel(_idx) `endif `define rvformal_csr_mhartid_indices \ localparam [11:0] csr_mindex_mhartid = 12'hF14; \ localparam [11:0] csr_sindex_mhartid = 12'hFFF; \ localparam [11:0] csr_uindex_mhartid = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MCONFIGPTR `define rvformal_csr_mconfigptr_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wdata; `define rvformal_csr_mconfigptr_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wdata `define rvformal_csr_mconfigptr_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wdata `define rvformal_csr_mconfigptr_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wdata `define rvformal_csr_mconfigptr_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wdata `define rvformal_csr_mconfigptr_conn, \ .rvfi_csr_mconfigptr_rmask (rvfi_csr_mconfigptr_rmask), \ .rvfi_csr_mconfigptr_wmask (rvfi_csr_mconfigptr_wmask), \ .rvfi_csr_mconfigptr_rdata (rvfi_csr_mconfigptr_rdata), \ .rvfi_csr_mconfigptr_wdata (rvfi_csr_mconfigptr_wdata) `define rvformal_csr_mconfigptr_channel_conn(_idx), \ .rvfi_csr_mconfigptr_rmask (rvfi_csr_mconfigptr_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mconfigptr_wmask (rvfi_csr_mconfigptr_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mconfigptr_rdata (rvfi_csr_mconfigptr_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mconfigptr_wdata (rvfi_csr_mconfigptr_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mconfigptr_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mconfigptr_rmask = rvfi_csr_mconfigptr_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mconfigptr_wmask = rvfi_csr_mconfigptr_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mconfigptr_rdata = rvfi_csr_mconfigptr_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mconfigptr_wdata = rvfi_csr_mconfigptr_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mconfigptr_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mconfigptr_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mconfigptr_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mconfigptr_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mconfigptr_wdata) `else `define rvformal_csr_mconfigptr_wires `define rvformal_csr_mconfigptr_outputs `define rvformal_csr_mconfigptr_inputs `define rvformal_csr_mconfigptr_conn `define rvformal_csr_mconfigptr_channel(_idx) `endif `define rvformal_csr_mconfigptr_indices \ localparam [11:0] csr_mindex_mconfigptr = 12'hF15; \ localparam [11:0] csr_sindex_mconfigptr = 12'hFFF; \ localparam [11:0] csr_uindex_mconfigptr = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MSTATUS `define rvformal_csr_mstatus_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wdata; `define rvformal_csr_mstatus_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wdata `define rvformal_csr_mstatus_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wdata `define rvformal_csr_mstatus_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wdata `define rvformal_csr_mstatus_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wdata `define rvformal_csr_mstatus_conn, \ .rvfi_csr_mstatus_rmask (rvfi_csr_mstatus_rmask), \ .rvfi_csr_mstatus_wmask (rvfi_csr_mstatus_wmask), \ .rvfi_csr_mstatus_rdata (rvfi_csr_mstatus_rdata), \ .rvfi_csr_mstatus_wdata (rvfi_csr_mstatus_wdata) `define rvformal_csr_mstatus_channel_conn(_idx), \ .rvfi_csr_mstatus_rmask (rvfi_csr_mstatus_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mstatus_wmask (rvfi_csr_mstatus_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mstatus_rdata (rvfi_csr_mstatus_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mstatus_wdata (rvfi_csr_mstatus_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mstatus_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatus_rmask = rvfi_csr_mstatus_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatus_wmask = rvfi_csr_mstatus_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatus_rdata = rvfi_csr_mstatus_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatus_wdata = rvfi_csr_mstatus_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mstatus_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatus_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatus_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatus_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatus_wdata) `else `define rvformal_csr_mstatus_wires `define rvformal_csr_mstatus_outputs `define rvformal_csr_mstatus_inputs `define rvformal_csr_mstatus_conn `define rvformal_csr_mstatus_channel(_idx) `endif `define rvformal_csr_mstatus_indices \ localparam [11:0] csr_mindex_mstatus = 12'h300; \ localparam [11:0] csr_sindex_mstatus = 12'hFFF; \ localparam [11:0] csr_uindex_mstatus = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MSTATUSH `define rvformal_csr_mstatush_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wdata; `define rvformal_csr_mstatush_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wdata `define rvformal_csr_mstatush_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wdata `define rvformal_csr_mstatush_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wdata `define rvformal_csr_mstatush_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wdata `define rvformal_csr_mstatush_conn, \ .rvfi_csr_mstatush_rmask (rvfi_csr_mstatush_rmask), \ .rvfi_csr_mstatush_wmask (rvfi_csr_mstatush_wmask), \ .rvfi_csr_mstatush_rdata (rvfi_csr_mstatush_rdata), \ .rvfi_csr_mstatush_wdata (rvfi_csr_mstatush_wdata) `define rvformal_csr_mstatush_channel_conn(_idx), \ .rvfi_csr_mstatush_rmask (rvfi_csr_mstatush_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mstatush_wmask (rvfi_csr_mstatush_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mstatush_rdata (rvfi_csr_mstatush_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mstatush_wdata (rvfi_csr_mstatush_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mstatush_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatush_rmask = rvfi_csr_mstatush_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatush_wmask = rvfi_csr_mstatush_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatush_rdata = rvfi_csr_mstatush_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatush_wdata = rvfi_csr_mstatush_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mstatush_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatush_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatush_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatush_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatush_wdata) `else `define rvformal_csr_mstatush_wires `define rvformal_csr_mstatush_outputs `define rvformal_csr_mstatush_inputs `define rvformal_csr_mstatush_conn `define rvformal_csr_mstatush_channel(_idx) `endif `define rvformal_csr_mstatush_indices \ localparam [11:0] csr_mindex_mstatush = 12'h310; \ localparam [11:0] csr_sindex_mstatush = 12'hFFF; \ localparam [11:0] csr_uindex_mstatush = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MISA `define rvformal_csr_misa_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wdata; `define rvformal_csr_misa_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wdata `define rvformal_csr_misa_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wdata `define rvformal_csr_misa_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wdata `define rvformal_csr_misa_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wdata `define rvformal_csr_misa_conn, \ .rvfi_csr_misa_rmask (rvfi_csr_misa_rmask), \ .rvfi_csr_misa_wmask (rvfi_csr_misa_wmask), \ .rvfi_csr_misa_rdata (rvfi_csr_misa_rdata), \ .rvfi_csr_misa_wdata (rvfi_csr_misa_wdata) `define rvformal_csr_misa_channel_conn(_idx), \ .rvfi_csr_misa_rmask (rvfi_csr_misa_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_misa_wmask (rvfi_csr_misa_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_misa_rdata (rvfi_csr_misa_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_misa_wdata (rvfi_csr_misa_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_misa_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_misa_rmask = rvfi_csr_misa_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_misa_wmask = rvfi_csr_misa_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_misa_rdata = rvfi_csr_misa_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_misa_wdata = rvfi_csr_misa_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_misa_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_misa_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_misa_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_misa_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_misa_wdata) `else `define rvformal_csr_misa_wires `define rvformal_csr_misa_outputs `define rvformal_csr_misa_inputs `define rvformal_csr_misa_conn `define rvformal_csr_misa_channel(_idx) `endif `define rvformal_csr_misa_indices \ localparam [11:0] csr_mindex_misa = 12'h301; \ localparam [11:0] csr_sindex_misa = 12'hFFF; \ localparam [11:0] csr_uindex_misa = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MEDELEG `define rvformal_csr_medeleg_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wdata; `define rvformal_csr_medeleg_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wdata `define rvformal_csr_medeleg_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wdata `define rvformal_csr_medeleg_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wdata `define rvformal_csr_medeleg_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wdata `define rvformal_csr_medeleg_conn, \ .rvfi_csr_medeleg_rmask (rvfi_csr_medeleg_rmask), \ .rvfi_csr_medeleg_wmask (rvfi_csr_medeleg_wmask), \ .rvfi_csr_medeleg_rdata (rvfi_csr_medeleg_rdata), \ .rvfi_csr_medeleg_wdata (rvfi_csr_medeleg_wdata) `define rvformal_csr_medeleg_channel_conn(_idx), \ .rvfi_csr_medeleg_rmask (rvfi_csr_medeleg_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_medeleg_wmask (rvfi_csr_medeleg_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_medeleg_rdata (rvfi_csr_medeleg_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_medeleg_wdata (rvfi_csr_medeleg_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_medeleg_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_medeleg_rmask = rvfi_csr_medeleg_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_medeleg_wmask = rvfi_csr_medeleg_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_medeleg_rdata = rvfi_csr_medeleg_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_medeleg_wdata = rvfi_csr_medeleg_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_medeleg_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_medeleg_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_medeleg_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_medeleg_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_medeleg_wdata) `else `define rvformal_csr_medeleg_wires `define rvformal_csr_medeleg_outputs `define rvformal_csr_medeleg_inputs `define rvformal_csr_medeleg_conn `define rvformal_csr_medeleg_channel(_idx) `endif `define rvformal_csr_medeleg_indices \ localparam [11:0] csr_mindex_medeleg = 12'h302; \ localparam [11:0] csr_sindex_medeleg = 12'hFFF; \ localparam [11:0] csr_uindex_medeleg = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MIDELEG `define rvformal_csr_mideleg_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wdata; `define rvformal_csr_mideleg_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wdata `define rvformal_csr_mideleg_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wdata `define rvformal_csr_mideleg_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wdata `define rvformal_csr_mideleg_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wdata `define rvformal_csr_mideleg_conn, \ .rvfi_csr_mideleg_rmask (rvfi_csr_mideleg_rmask), \ .rvfi_csr_mideleg_wmask (rvfi_csr_mideleg_wmask), \ .rvfi_csr_mideleg_rdata (rvfi_csr_mideleg_rdata), \ .rvfi_csr_mideleg_wdata (rvfi_csr_mideleg_wdata) `define rvformal_csr_mideleg_channel_conn(_idx), \ .rvfi_csr_mideleg_rmask (rvfi_csr_mideleg_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mideleg_wmask (rvfi_csr_mideleg_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mideleg_rdata (rvfi_csr_mideleg_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mideleg_wdata (rvfi_csr_mideleg_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mideleg_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mideleg_rmask = rvfi_csr_mideleg_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mideleg_wmask = rvfi_csr_mideleg_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mideleg_rdata = rvfi_csr_mideleg_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mideleg_wdata = rvfi_csr_mideleg_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mideleg_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mideleg_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mideleg_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mideleg_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mideleg_wdata) `else `define rvformal_csr_mideleg_wires `define rvformal_csr_mideleg_outputs `define rvformal_csr_mideleg_inputs `define rvformal_csr_mideleg_conn `define rvformal_csr_mideleg_channel(_idx) `endif `define rvformal_csr_mideleg_indices \ localparam [11:0] csr_mindex_mideleg = 12'h303; \ localparam [11:0] csr_sindex_mideleg = 12'hFFF; \ localparam [11:0] csr_uindex_mideleg = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MIE `define rvformal_csr_mie_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wdata; `define rvformal_csr_mie_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wdata `define rvformal_csr_mie_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wdata `define rvformal_csr_mie_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wdata `define rvformal_csr_mie_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wdata `define rvformal_csr_mie_conn, \ .rvfi_csr_mie_rmask (rvfi_csr_mie_rmask), \ .rvfi_csr_mie_wmask (rvfi_csr_mie_wmask), \ .rvfi_csr_mie_rdata (rvfi_csr_mie_rdata), \ .rvfi_csr_mie_wdata (rvfi_csr_mie_wdata) `define rvformal_csr_mie_channel_conn(_idx), \ .rvfi_csr_mie_rmask (rvfi_csr_mie_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mie_wmask (rvfi_csr_mie_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mie_rdata (rvfi_csr_mie_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mie_wdata (rvfi_csr_mie_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mie_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mie_rmask = rvfi_csr_mie_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mie_wmask = rvfi_csr_mie_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mie_rdata = rvfi_csr_mie_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mie_wdata = rvfi_csr_mie_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mie_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mie_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mie_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mie_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mie_wdata) `else `define rvformal_csr_mie_wires `define rvformal_csr_mie_outputs `define rvformal_csr_mie_inputs `define rvformal_csr_mie_conn `define rvformal_csr_mie_channel(_idx) `endif `define rvformal_csr_mie_indices \ localparam [11:0] csr_mindex_mie = 12'h304; \ localparam [11:0] csr_sindex_mie = 12'hFFF; \ localparam [11:0] csr_uindex_mie = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MTVEC `define rvformal_csr_mtvec_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wdata; `define rvformal_csr_mtvec_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wdata `define rvformal_csr_mtvec_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wdata `define rvformal_csr_mtvec_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wdata `define rvformal_csr_mtvec_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wdata `define rvformal_csr_mtvec_conn, \ .rvfi_csr_mtvec_rmask (rvfi_csr_mtvec_rmask), \ .rvfi_csr_mtvec_wmask (rvfi_csr_mtvec_wmask), \ .rvfi_csr_mtvec_rdata (rvfi_csr_mtvec_rdata), \ .rvfi_csr_mtvec_wdata (rvfi_csr_mtvec_wdata) `define rvformal_csr_mtvec_channel_conn(_idx), \ .rvfi_csr_mtvec_rmask (rvfi_csr_mtvec_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mtvec_wmask (rvfi_csr_mtvec_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mtvec_rdata (rvfi_csr_mtvec_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mtvec_wdata (rvfi_csr_mtvec_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mtvec_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtvec_rmask = rvfi_csr_mtvec_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtvec_wmask = rvfi_csr_mtvec_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtvec_rdata = rvfi_csr_mtvec_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtvec_wdata = rvfi_csr_mtvec_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mtvec_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtvec_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtvec_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtvec_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtvec_wdata) `else `define rvformal_csr_mtvec_wires `define rvformal_csr_mtvec_outputs `define rvformal_csr_mtvec_inputs `define rvformal_csr_mtvec_conn `define rvformal_csr_mtvec_channel(_idx) `endif `define rvformal_csr_mtvec_indices \ localparam [11:0] csr_mindex_mtvec = 12'h305; \ localparam [11:0] csr_sindex_mtvec = 12'hFFF; \ localparam [11:0] csr_uindex_mtvec = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MCOUNTEREN `define rvformal_csr_mcounteren_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wdata; `define rvformal_csr_mcounteren_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wdata `define rvformal_csr_mcounteren_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wdata `define rvformal_csr_mcounteren_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wdata `define rvformal_csr_mcounteren_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wdata `define rvformal_csr_mcounteren_conn, \ .rvfi_csr_mcounteren_rmask (rvfi_csr_mcounteren_rmask), \ .rvfi_csr_mcounteren_wmask (rvfi_csr_mcounteren_wmask), \ .rvfi_csr_mcounteren_rdata (rvfi_csr_mcounteren_rdata), \ .rvfi_csr_mcounteren_wdata (rvfi_csr_mcounteren_wdata) `define rvformal_csr_mcounteren_channel_conn(_idx), \ .rvfi_csr_mcounteren_rmask (rvfi_csr_mcounteren_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mcounteren_wmask (rvfi_csr_mcounteren_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mcounteren_rdata (rvfi_csr_mcounteren_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mcounteren_wdata (rvfi_csr_mcounteren_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mcounteren_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcounteren_rmask = rvfi_csr_mcounteren_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcounteren_wmask = rvfi_csr_mcounteren_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcounteren_rdata = rvfi_csr_mcounteren_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcounteren_wdata = rvfi_csr_mcounteren_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mcounteren_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcounteren_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcounteren_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcounteren_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcounteren_wdata) `else `define rvformal_csr_mcounteren_wires `define rvformal_csr_mcounteren_outputs `define rvformal_csr_mcounteren_inputs `define rvformal_csr_mcounteren_conn `define rvformal_csr_mcounteren_channel(_idx) `endif `define rvformal_csr_mcounteren_indices \ localparam [11:0] csr_mindex_mcounteren = 12'h306; \ localparam [11:0] csr_sindex_mcounteren = 12'hFFF; \ localparam [11:0] csr_uindex_mcounteren = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MSCRATCH `define rvformal_csr_mscratch_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wdata; `define rvformal_csr_mscratch_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wdata `define rvformal_csr_mscratch_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wdata `define rvformal_csr_mscratch_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wdata `define rvformal_csr_mscratch_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wdata `define rvformal_csr_mscratch_conn, \ .rvfi_csr_mscratch_rmask (rvfi_csr_mscratch_rmask), \ .rvfi_csr_mscratch_wmask (rvfi_csr_mscratch_wmask), \ .rvfi_csr_mscratch_rdata (rvfi_csr_mscratch_rdata), \ .rvfi_csr_mscratch_wdata (rvfi_csr_mscratch_wdata) `define rvformal_csr_mscratch_channel_conn(_idx), \ .rvfi_csr_mscratch_rmask (rvfi_csr_mscratch_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mscratch_wmask (rvfi_csr_mscratch_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mscratch_rdata (rvfi_csr_mscratch_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mscratch_wdata (rvfi_csr_mscratch_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mscratch_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mscratch_rmask = rvfi_csr_mscratch_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mscratch_wmask = rvfi_csr_mscratch_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mscratch_rdata = rvfi_csr_mscratch_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mscratch_wdata = rvfi_csr_mscratch_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mscratch_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mscratch_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mscratch_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mscratch_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mscratch_wdata) `else `define rvformal_csr_mscratch_wires `define rvformal_csr_mscratch_outputs `define rvformal_csr_mscratch_inputs `define rvformal_csr_mscratch_conn `define rvformal_csr_mscratch_channel(_idx) `endif `define rvformal_csr_mscratch_indices \ localparam [11:0] csr_mindex_mscratch = 12'h340; \ localparam [11:0] csr_sindex_mscratch = 12'hFFF; \ localparam [11:0] csr_uindex_mscratch = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MEPC `define rvformal_csr_mepc_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wdata; `define rvformal_csr_mepc_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wdata `define rvformal_csr_mepc_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wdata `define rvformal_csr_mepc_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wdata `define rvformal_csr_mepc_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wdata `define rvformal_csr_mepc_conn, \ .rvfi_csr_mepc_rmask (rvfi_csr_mepc_rmask), \ .rvfi_csr_mepc_wmask (rvfi_csr_mepc_wmask), \ .rvfi_csr_mepc_rdata (rvfi_csr_mepc_rdata), \ .rvfi_csr_mepc_wdata (rvfi_csr_mepc_wdata) `define rvformal_csr_mepc_channel_conn(_idx), \ .rvfi_csr_mepc_rmask (rvfi_csr_mepc_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mepc_wmask (rvfi_csr_mepc_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mepc_rdata (rvfi_csr_mepc_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mepc_wdata (rvfi_csr_mepc_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mepc_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mepc_rmask = rvfi_csr_mepc_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mepc_wmask = rvfi_csr_mepc_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mepc_rdata = rvfi_csr_mepc_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mepc_wdata = rvfi_csr_mepc_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mepc_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mepc_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mepc_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mepc_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mepc_wdata) `else `define rvformal_csr_mepc_wires `define rvformal_csr_mepc_outputs `define rvformal_csr_mepc_inputs `define rvformal_csr_mepc_conn `define rvformal_csr_mepc_channel(_idx) `endif `define rvformal_csr_mepc_indices \ localparam [11:0] csr_mindex_mepc = 12'h341; \ localparam [11:0] csr_sindex_mepc = 12'hFFF; \ localparam [11:0] csr_uindex_mepc = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MCAUSE `define rvformal_csr_mcause_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wdata; `define rvformal_csr_mcause_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wdata `define rvformal_csr_mcause_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wdata `define rvformal_csr_mcause_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wdata `define rvformal_csr_mcause_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wdata `define rvformal_csr_mcause_conn, \ .rvfi_csr_mcause_rmask (rvfi_csr_mcause_rmask), \ .rvfi_csr_mcause_wmask (rvfi_csr_mcause_wmask), \ .rvfi_csr_mcause_rdata (rvfi_csr_mcause_rdata), \ .rvfi_csr_mcause_wdata (rvfi_csr_mcause_wdata) `define rvformal_csr_mcause_channel_conn(_idx), \ .rvfi_csr_mcause_rmask (rvfi_csr_mcause_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mcause_wmask (rvfi_csr_mcause_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mcause_rdata (rvfi_csr_mcause_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mcause_wdata (rvfi_csr_mcause_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mcause_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcause_rmask = rvfi_csr_mcause_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcause_wmask = rvfi_csr_mcause_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcause_rdata = rvfi_csr_mcause_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcause_wdata = rvfi_csr_mcause_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mcause_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcause_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcause_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcause_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcause_wdata) `else `define rvformal_csr_mcause_wires `define rvformal_csr_mcause_outputs `define rvformal_csr_mcause_inputs `define rvformal_csr_mcause_conn `define rvformal_csr_mcause_channel(_idx) `endif `define rvformal_csr_mcause_indices \ localparam [11:0] csr_mindex_mcause = 12'h342; \ localparam [11:0] csr_sindex_mcause = 12'hFFF; \ localparam [11:0] csr_uindex_mcause = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MTVAL `define rvformal_csr_mtval_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wdata; `define rvformal_csr_mtval_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wdata `define rvformal_csr_mtval_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wdata `define rvformal_csr_mtval_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wdata `define rvformal_csr_mtval_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wdata `define rvformal_csr_mtval_conn, \ .rvfi_csr_mtval_rmask (rvfi_csr_mtval_rmask), \ .rvfi_csr_mtval_wmask (rvfi_csr_mtval_wmask), \ .rvfi_csr_mtval_rdata (rvfi_csr_mtval_rdata), \ .rvfi_csr_mtval_wdata (rvfi_csr_mtval_wdata) `define rvformal_csr_mtval_channel_conn(_idx), \ .rvfi_csr_mtval_rmask (rvfi_csr_mtval_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mtval_wmask (rvfi_csr_mtval_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mtval_rdata (rvfi_csr_mtval_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mtval_wdata (rvfi_csr_mtval_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mtval_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval_rmask = rvfi_csr_mtval_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval_wmask = rvfi_csr_mtval_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval_rdata = rvfi_csr_mtval_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval_wdata = rvfi_csr_mtval_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mtval_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval_wdata) `else `define rvformal_csr_mtval_wires `define rvformal_csr_mtval_outputs `define rvformal_csr_mtval_inputs `define rvformal_csr_mtval_conn `define rvformal_csr_mtval_channel(_idx) `endif `define rvformal_csr_mtval_indices \ localparam [11:0] csr_mindex_mtval = 12'h343; \ localparam [11:0] csr_sindex_mtval = 12'hFFF; \ localparam [11:0] csr_uindex_mtval = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MIP `define rvformal_csr_mip_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wdata; `define rvformal_csr_mip_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wdata `define rvformal_csr_mip_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wdata `define rvformal_csr_mip_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wdata `define rvformal_csr_mip_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wdata `define rvformal_csr_mip_conn, \ .rvfi_csr_mip_rmask (rvfi_csr_mip_rmask), \ .rvfi_csr_mip_wmask (rvfi_csr_mip_wmask), \ .rvfi_csr_mip_rdata (rvfi_csr_mip_rdata), \ .rvfi_csr_mip_wdata (rvfi_csr_mip_wdata) `define rvformal_csr_mip_channel_conn(_idx), \ .rvfi_csr_mip_rmask (rvfi_csr_mip_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mip_wmask (rvfi_csr_mip_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mip_rdata (rvfi_csr_mip_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mip_wdata (rvfi_csr_mip_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mip_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mip_rmask = rvfi_csr_mip_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mip_wmask = rvfi_csr_mip_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mip_rdata = rvfi_csr_mip_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mip_wdata = rvfi_csr_mip_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mip_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mip_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mip_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mip_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mip_wdata) `else `define rvformal_csr_mip_wires `define rvformal_csr_mip_outputs `define rvformal_csr_mip_inputs `define rvformal_csr_mip_conn `define rvformal_csr_mip_channel(_idx) `endif `define rvformal_csr_mip_indices \ localparam [11:0] csr_mindex_mip = 12'h344; \ localparam [11:0] csr_sindex_mip = 12'hFFF; \ localparam [11:0] csr_uindex_mip = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MTINST `define rvformal_csr_mtinst_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wdata; `define rvformal_csr_mtinst_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wdata `define rvformal_csr_mtinst_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wdata `define rvformal_csr_mtinst_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wdata `define rvformal_csr_mtinst_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wdata `define rvformal_csr_mtinst_conn, \ .rvfi_csr_mtinst_rmask (rvfi_csr_mtinst_rmask), \ .rvfi_csr_mtinst_wmask (rvfi_csr_mtinst_wmask), \ .rvfi_csr_mtinst_rdata (rvfi_csr_mtinst_rdata), \ .rvfi_csr_mtinst_wdata (rvfi_csr_mtinst_wdata) `define rvformal_csr_mtinst_channel_conn(_idx), \ .rvfi_csr_mtinst_rmask (rvfi_csr_mtinst_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mtinst_wmask (rvfi_csr_mtinst_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mtinst_rdata (rvfi_csr_mtinst_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mtinst_wdata (rvfi_csr_mtinst_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mtinst_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtinst_rmask = rvfi_csr_mtinst_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtinst_wmask = rvfi_csr_mtinst_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtinst_rdata = rvfi_csr_mtinst_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtinst_wdata = rvfi_csr_mtinst_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mtinst_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtinst_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtinst_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtinst_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtinst_wdata) `else `define rvformal_csr_mtinst_wires `define rvformal_csr_mtinst_outputs `define rvformal_csr_mtinst_inputs `define rvformal_csr_mtinst_conn `define rvformal_csr_mtinst_channel(_idx) `endif `define rvformal_csr_mtinst_indices \ localparam [11:0] csr_mindex_mtinst = 12'h34A; \ localparam [11:0] csr_sindex_mtinst = 12'hFFF; \ localparam [11:0] csr_uindex_mtinst = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MTVAL2 `define rvformal_csr_mtval2_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wdata; `define rvformal_csr_mtval2_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wdata `define rvformal_csr_mtval2_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wdata `define rvformal_csr_mtval2_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wdata `define rvformal_csr_mtval2_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wdata `define rvformal_csr_mtval2_conn, \ .rvfi_csr_mtval2_rmask (rvfi_csr_mtval2_rmask), \ .rvfi_csr_mtval2_wmask (rvfi_csr_mtval2_wmask), \ .rvfi_csr_mtval2_rdata (rvfi_csr_mtval2_rdata), \ .rvfi_csr_mtval2_wdata (rvfi_csr_mtval2_wdata) `define rvformal_csr_mtval2_channel_conn(_idx), \ .rvfi_csr_mtval2_rmask (rvfi_csr_mtval2_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mtval2_wmask (rvfi_csr_mtval2_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mtval2_rdata (rvfi_csr_mtval2_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mtval2_wdata (rvfi_csr_mtval2_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mtval2_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval2_rmask = rvfi_csr_mtval2_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval2_wmask = rvfi_csr_mtval2_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval2_rdata = rvfi_csr_mtval2_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval2_wdata = rvfi_csr_mtval2_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mtval2_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval2_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval2_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval2_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval2_wdata) `else `define rvformal_csr_mtval2_wires `define rvformal_csr_mtval2_outputs `define rvformal_csr_mtval2_inputs `define rvformal_csr_mtval2_conn `define rvformal_csr_mtval2_channel(_idx) `endif `define rvformal_csr_mtval2_indices \ localparam [11:0] csr_mindex_mtval2 = 12'h34B; \ localparam [11:0] csr_sindex_mtval2 = 12'hFFF; \ localparam [11:0] csr_uindex_mtval2 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MCOUNTINHIBIT `define rvformal_csr_mcountinhibit_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wdata; `define rvformal_csr_mcountinhibit_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wdata `define rvformal_csr_mcountinhibit_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wdata `define rvformal_csr_mcountinhibit_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wdata `define rvformal_csr_mcountinhibit_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wdata `define rvformal_csr_mcountinhibit_conn, \ .rvfi_csr_mcountinhibit_rmask (rvfi_csr_mcountinhibit_rmask), \ .rvfi_csr_mcountinhibit_wmask (rvfi_csr_mcountinhibit_wmask), \ .rvfi_csr_mcountinhibit_rdata (rvfi_csr_mcountinhibit_rdata), \ .rvfi_csr_mcountinhibit_wdata (rvfi_csr_mcountinhibit_wdata) `define rvformal_csr_mcountinhibit_channel_conn(_idx), \ .rvfi_csr_mcountinhibit_rmask (rvfi_csr_mcountinhibit_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mcountinhibit_wmask (rvfi_csr_mcountinhibit_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mcountinhibit_rdata (rvfi_csr_mcountinhibit_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mcountinhibit_wdata (rvfi_csr_mcountinhibit_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mcountinhibit_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcountinhibit_rmask = rvfi_csr_mcountinhibit_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcountinhibit_wmask = rvfi_csr_mcountinhibit_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcountinhibit_rdata = rvfi_csr_mcountinhibit_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcountinhibit_wdata = rvfi_csr_mcountinhibit_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mcountinhibit_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcountinhibit_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcountinhibit_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcountinhibit_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcountinhibit_wdata) `else `define rvformal_csr_mcountinhibit_wires `define rvformal_csr_mcountinhibit_outputs `define rvformal_csr_mcountinhibit_inputs `define rvformal_csr_mcountinhibit_conn `define rvformal_csr_mcountinhibit_channel(_idx) `endif `define rvformal_csr_mcountinhibit_indices \ localparam [11:0] csr_mindex_mcountinhibit = 12'h320; \ localparam [11:0] csr_sindex_mcountinhibit = 12'hFFF; \ localparam [11:0] csr_uindex_mcountinhibit = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MENVCFG `define rvformal_csr_menvcfg_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wdata; `define rvformal_csr_menvcfg_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wdata `define rvformal_csr_menvcfg_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wdata `define rvformal_csr_menvcfg_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wdata `define rvformal_csr_menvcfg_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wdata `define rvformal_csr_menvcfg_conn, \ .rvfi_csr_menvcfg_rmask (rvfi_csr_menvcfg_rmask), \ .rvfi_csr_menvcfg_wmask (rvfi_csr_menvcfg_wmask), \ .rvfi_csr_menvcfg_rdata (rvfi_csr_menvcfg_rdata), \ .rvfi_csr_menvcfg_wdata (rvfi_csr_menvcfg_wdata) `define rvformal_csr_menvcfg_channel_conn(_idx), \ .rvfi_csr_menvcfg_rmask (rvfi_csr_menvcfg_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_menvcfg_wmask (rvfi_csr_menvcfg_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_menvcfg_rdata (rvfi_csr_menvcfg_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_menvcfg_wdata (rvfi_csr_menvcfg_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_menvcfg_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfg_rmask = rvfi_csr_menvcfg_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfg_wmask = rvfi_csr_menvcfg_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfg_rdata = rvfi_csr_menvcfg_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfg_wdata = rvfi_csr_menvcfg_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_menvcfg_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfg_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfg_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfg_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfg_wdata) `else `define rvformal_csr_menvcfg_wires `define rvformal_csr_menvcfg_outputs `define rvformal_csr_menvcfg_inputs `define rvformal_csr_menvcfg_conn `define rvformal_csr_menvcfg_channel(_idx) `endif `define rvformal_csr_menvcfg_indices \ localparam [11:0] csr_mindex_menvcfg = 12'h30A; \ localparam [11:0] csr_sindex_menvcfg = 12'hFFF; \ localparam [11:0] csr_uindex_menvcfg = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MENVCFGH `define rvformal_csr_menvcfgh_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wdata; `define rvformal_csr_menvcfgh_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wdata `define rvformal_csr_menvcfgh_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wdata `define rvformal_csr_menvcfgh_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wdata `define rvformal_csr_menvcfgh_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wdata `define rvformal_csr_menvcfgh_conn, \ .rvfi_csr_menvcfgh_rmask (rvfi_csr_menvcfgh_rmask), \ .rvfi_csr_menvcfgh_wmask (rvfi_csr_menvcfgh_wmask), \ .rvfi_csr_menvcfgh_rdata (rvfi_csr_menvcfgh_rdata), \ .rvfi_csr_menvcfgh_wdata (rvfi_csr_menvcfgh_wdata) `define rvformal_csr_menvcfgh_channel_conn(_idx), \ .rvfi_csr_menvcfgh_rmask (rvfi_csr_menvcfgh_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_menvcfgh_wmask (rvfi_csr_menvcfgh_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_menvcfgh_rdata (rvfi_csr_menvcfgh_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_menvcfgh_wdata (rvfi_csr_menvcfgh_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_menvcfgh_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfgh_rmask = rvfi_csr_menvcfgh_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfgh_wmask = rvfi_csr_menvcfgh_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfgh_rdata = rvfi_csr_menvcfgh_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfgh_wdata = rvfi_csr_menvcfgh_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_menvcfgh_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfgh_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfgh_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfgh_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfgh_wdata) `else `define rvformal_csr_menvcfgh_wires `define rvformal_csr_menvcfgh_outputs `define rvformal_csr_menvcfgh_inputs `define rvformal_csr_menvcfgh_conn `define rvformal_csr_menvcfgh_channel(_idx) `endif `define rvformal_csr_menvcfgh_indices \ localparam [11:0] csr_mindex_menvcfgh = 12'h31A; \ localparam [11:0] csr_sindex_menvcfgh = 12'hFFF; \ localparam [11:0] csr_uindex_menvcfgh = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG0 `define rvformal_csr_pmpcfg0_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wdata; `define rvformal_csr_pmpcfg0_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wdata `define rvformal_csr_pmpcfg0_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wdata `define rvformal_csr_pmpcfg0_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wdata `define rvformal_csr_pmpcfg0_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wdata `define rvformal_csr_pmpcfg0_conn, \ .rvfi_csr_pmpcfg0_rmask (rvfi_csr_pmpcfg0_rmask), \ .rvfi_csr_pmpcfg0_wmask (rvfi_csr_pmpcfg0_wmask), \ .rvfi_csr_pmpcfg0_rdata (rvfi_csr_pmpcfg0_rdata), \ .rvfi_csr_pmpcfg0_wdata (rvfi_csr_pmpcfg0_wdata) `define rvformal_csr_pmpcfg0_channel_conn(_idx), \ .rvfi_csr_pmpcfg0_rmask (rvfi_csr_pmpcfg0_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg0_wmask (rvfi_csr_pmpcfg0_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg0_rdata (rvfi_csr_pmpcfg0_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg0_wdata (rvfi_csr_pmpcfg0_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg0_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg0_rmask = rvfi_csr_pmpcfg0_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg0_wmask = rvfi_csr_pmpcfg0_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg0_rdata = rvfi_csr_pmpcfg0_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg0_wdata = rvfi_csr_pmpcfg0_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg0_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg0_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg0_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg0_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg0_wdata) `else `define rvformal_csr_pmpcfg0_wires `define rvformal_csr_pmpcfg0_outputs `define rvformal_csr_pmpcfg0_inputs `define rvformal_csr_pmpcfg0_conn `define rvformal_csr_pmpcfg0_channel(_idx) `endif `define rvformal_csr_pmpcfg0_indices \ localparam [11:0] csr_mindex_pmpcfg0 = 12'h3A0; \ localparam [11:0] csr_sindex_pmpcfg0 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg0 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG1 `define rvformal_csr_pmpcfg1_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wdata; `define rvformal_csr_pmpcfg1_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wdata `define rvformal_csr_pmpcfg1_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wdata `define rvformal_csr_pmpcfg1_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wdata `define rvformal_csr_pmpcfg1_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wdata `define rvformal_csr_pmpcfg1_conn, \ .rvfi_csr_pmpcfg1_rmask (rvfi_csr_pmpcfg1_rmask), \ .rvfi_csr_pmpcfg1_wmask (rvfi_csr_pmpcfg1_wmask), \ .rvfi_csr_pmpcfg1_rdata (rvfi_csr_pmpcfg1_rdata), \ .rvfi_csr_pmpcfg1_wdata (rvfi_csr_pmpcfg1_wdata) `define rvformal_csr_pmpcfg1_channel_conn(_idx), \ .rvfi_csr_pmpcfg1_rmask (rvfi_csr_pmpcfg1_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg1_wmask (rvfi_csr_pmpcfg1_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg1_rdata (rvfi_csr_pmpcfg1_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg1_wdata (rvfi_csr_pmpcfg1_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg1_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg1_rmask = rvfi_csr_pmpcfg1_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg1_wmask = rvfi_csr_pmpcfg1_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg1_rdata = rvfi_csr_pmpcfg1_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg1_wdata = rvfi_csr_pmpcfg1_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg1_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg1_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg1_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg1_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg1_wdata) `else `define rvformal_csr_pmpcfg1_wires `define rvformal_csr_pmpcfg1_outputs `define rvformal_csr_pmpcfg1_inputs `define rvformal_csr_pmpcfg1_conn `define rvformal_csr_pmpcfg1_channel(_idx) `endif `define rvformal_csr_pmpcfg1_indices \ localparam [11:0] csr_mindex_pmpcfg1 = 12'h3A1; \ localparam [11:0] csr_sindex_pmpcfg1 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg1 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG2 `define rvformal_csr_pmpcfg2_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wdata; `define rvformal_csr_pmpcfg2_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wdata `define rvformal_csr_pmpcfg2_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wdata `define rvformal_csr_pmpcfg2_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wdata `define rvformal_csr_pmpcfg2_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wdata `define rvformal_csr_pmpcfg2_conn, \ .rvfi_csr_pmpcfg2_rmask (rvfi_csr_pmpcfg2_rmask), \ .rvfi_csr_pmpcfg2_wmask (rvfi_csr_pmpcfg2_wmask), \ .rvfi_csr_pmpcfg2_rdata (rvfi_csr_pmpcfg2_rdata), \ .rvfi_csr_pmpcfg2_wdata (rvfi_csr_pmpcfg2_wdata) `define rvformal_csr_pmpcfg2_channel_conn(_idx), \ .rvfi_csr_pmpcfg2_rmask (rvfi_csr_pmpcfg2_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg2_wmask (rvfi_csr_pmpcfg2_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg2_rdata (rvfi_csr_pmpcfg2_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg2_wdata (rvfi_csr_pmpcfg2_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg2_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg2_rmask = rvfi_csr_pmpcfg2_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg2_wmask = rvfi_csr_pmpcfg2_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg2_rdata = rvfi_csr_pmpcfg2_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg2_wdata = rvfi_csr_pmpcfg2_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg2_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg2_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg2_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg2_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg2_wdata) `else `define rvformal_csr_pmpcfg2_wires `define rvformal_csr_pmpcfg2_outputs `define rvformal_csr_pmpcfg2_inputs `define rvformal_csr_pmpcfg2_conn `define rvformal_csr_pmpcfg2_channel(_idx) `endif `define rvformal_csr_pmpcfg2_indices \ localparam [11:0] csr_mindex_pmpcfg2 = 12'h3A2; \ localparam [11:0] csr_sindex_pmpcfg2 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg2 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG3 `define rvformal_csr_pmpcfg3_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wdata; `define rvformal_csr_pmpcfg3_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wdata `define rvformal_csr_pmpcfg3_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wdata `define rvformal_csr_pmpcfg3_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wdata `define rvformal_csr_pmpcfg3_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wdata `define rvformal_csr_pmpcfg3_conn, \ .rvfi_csr_pmpcfg3_rmask (rvfi_csr_pmpcfg3_rmask), \ .rvfi_csr_pmpcfg3_wmask (rvfi_csr_pmpcfg3_wmask), \ .rvfi_csr_pmpcfg3_rdata (rvfi_csr_pmpcfg3_rdata), \ .rvfi_csr_pmpcfg3_wdata (rvfi_csr_pmpcfg3_wdata) `define rvformal_csr_pmpcfg3_channel_conn(_idx), \ .rvfi_csr_pmpcfg3_rmask (rvfi_csr_pmpcfg3_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg3_wmask (rvfi_csr_pmpcfg3_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg3_rdata (rvfi_csr_pmpcfg3_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg3_wdata (rvfi_csr_pmpcfg3_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg3_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg3_rmask = rvfi_csr_pmpcfg3_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg3_wmask = rvfi_csr_pmpcfg3_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg3_rdata = rvfi_csr_pmpcfg3_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg3_wdata = rvfi_csr_pmpcfg3_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg3_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg3_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg3_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg3_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg3_wdata) `else `define rvformal_csr_pmpcfg3_wires `define rvformal_csr_pmpcfg3_outputs `define rvformal_csr_pmpcfg3_inputs `define rvformal_csr_pmpcfg3_conn `define rvformal_csr_pmpcfg3_channel(_idx) `endif `define rvformal_csr_pmpcfg3_indices \ localparam [11:0] csr_mindex_pmpcfg3 = 12'h3A3; \ localparam [11:0] csr_sindex_pmpcfg3 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg3 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG4 `define rvformal_csr_pmpcfg4_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wdata; `define rvformal_csr_pmpcfg4_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wdata `define rvformal_csr_pmpcfg4_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wdata `define rvformal_csr_pmpcfg4_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wdata `define rvformal_csr_pmpcfg4_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wdata `define rvformal_csr_pmpcfg4_conn, \ .rvfi_csr_pmpcfg4_rmask (rvfi_csr_pmpcfg4_rmask), \ .rvfi_csr_pmpcfg4_wmask (rvfi_csr_pmpcfg4_wmask), \ .rvfi_csr_pmpcfg4_rdata (rvfi_csr_pmpcfg4_rdata), \ .rvfi_csr_pmpcfg4_wdata (rvfi_csr_pmpcfg4_wdata) `define rvformal_csr_pmpcfg4_channel_conn(_idx), \ .rvfi_csr_pmpcfg4_rmask (rvfi_csr_pmpcfg4_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg4_wmask (rvfi_csr_pmpcfg4_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg4_rdata (rvfi_csr_pmpcfg4_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg4_wdata (rvfi_csr_pmpcfg4_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg4_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg4_rmask = rvfi_csr_pmpcfg4_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg4_wmask = rvfi_csr_pmpcfg4_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg4_rdata = rvfi_csr_pmpcfg4_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg4_wdata = rvfi_csr_pmpcfg4_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg4_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg4_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg4_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg4_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg4_wdata) `else `define rvformal_csr_pmpcfg4_wires `define rvformal_csr_pmpcfg4_outputs `define rvformal_csr_pmpcfg4_inputs `define rvformal_csr_pmpcfg4_conn `define rvformal_csr_pmpcfg4_channel(_idx) `endif `define rvformal_csr_pmpcfg4_indices \ localparam [11:0] csr_mindex_pmpcfg4 = 12'h3A4; \ localparam [11:0] csr_sindex_pmpcfg4 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg4 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG5 `define rvformal_csr_pmpcfg5_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wdata; `define rvformal_csr_pmpcfg5_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wdata `define rvformal_csr_pmpcfg5_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wdata `define rvformal_csr_pmpcfg5_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wdata `define rvformal_csr_pmpcfg5_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wdata `define rvformal_csr_pmpcfg5_conn, \ .rvfi_csr_pmpcfg5_rmask (rvfi_csr_pmpcfg5_rmask), \ .rvfi_csr_pmpcfg5_wmask (rvfi_csr_pmpcfg5_wmask), \ .rvfi_csr_pmpcfg5_rdata (rvfi_csr_pmpcfg5_rdata), \ .rvfi_csr_pmpcfg5_wdata (rvfi_csr_pmpcfg5_wdata) `define rvformal_csr_pmpcfg5_channel_conn(_idx), \ .rvfi_csr_pmpcfg5_rmask (rvfi_csr_pmpcfg5_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg5_wmask (rvfi_csr_pmpcfg5_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg5_rdata (rvfi_csr_pmpcfg5_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg5_wdata (rvfi_csr_pmpcfg5_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg5_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg5_rmask = rvfi_csr_pmpcfg5_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg5_wmask = rvfi_csr_pmpcfg5_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg5_rdata = rvfi_csr_pmpcfg5_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg5_wdata = rvfi_csr_pmpcfg5_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg5_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg5_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg5_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg5_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg5_wdata) `else `define rvformal_csr_pmpcfg5_wires `define rvformal_csr_pmpcfg5_outputs `define rvformal_csr_pmpcfg5_inputs `define rvformal_csr_pmpcfg5_conn `define rvformal_csr_pmpcfg5_channel(_idx) `endif `define rvformal_csr_pmpcfg5_indices \ localparam [11:0] csr_mindex_pmpcfg5 = 12'h3A5; \ localparam [11:0] csr_sindex_pmpcfg5 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg5 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG6 `define rvformal_csr_pmpcfg6_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wdata; `define rvformal_csr_pmpcfg6_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wdata `define rvformal_csr_pmpcfg6_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wdata `define rvformal_csr_pmpcfg6_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wdata `define rvformal_csr_pmpcfg6_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wdata `define rvformal_csr_pmpcfg6_conn, \ .rvfi_csr_pmpcfg6_rmask (rvfi_csr_pmpcfg6_rmask), \ .rvfi_csr_pmpcfg6_wmask (rvfi_csr_pmpcfg6_wmask), \ .rvfi_csr_pmpcfg6_rdata (rvfi_csr_pmpcfg6_rdata), \ .rvfi_csr_pmpcfg6_wdata (rvfi_csr_pmpcfg6_wdata) `define rvformal_csr_pmpcfg6_channel_conn(_idx), \ .rvfi_csr_pmpcfg6_rmask (rvfi_csr_pmpcfg6_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg6_wmask (rvfi_csr_pmpcfg6_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg6_rdata (rvfi_csr_pmpcfg6_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg6_wdata (rvfi_csr_pmpcfg6_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg6_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg6_rmask = rvfi_csr_pmpcfg6_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg6_wmask = rvfi_csr_pmpcfg6_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg6_rdata = rvfi_csr_pmpcfg6_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg6_wdata = rvfi_csr_pmpcfg6_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg6_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg6_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg6_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg6_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg6_wdata) `else `define rvformal_csr_pmpcfg6_wires `define rvformal_csr_pmpcfg6_outputs `define rvformal_csr_pmpcfg6_inputs `define rvformal_csr_pmpcfg6_conn `define rvformal_csr_pmpcfg6_channel(_idx) `endif `define rvformal_csr_pmpcfg6_indices \ localparam [11:0] csr_mindex_pmpcfg6 = 12'h3A6; \ localparam [11:0] csr_sindex_pmpcfg6 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg6 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG7 `define rvformal_csr_pmpcfg7_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wdata; `define rvformal_csr_pmpcfg7_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wdata `define rvformal_csr_pmpcfg7_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wdata `define rvformal_csr_pmpcfg7_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wdata `define rvformal_csr_pmpcfg7_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wdata `define rvformal_csr_pmpcfg7_conn, \ .rvfi_csr_pmpcfg7_rmask (rvfi_csr_pmpcfg7_rmask), \ .rvfi_csr_pmpcfg7_wmask (rvfi_csr_pmpcfg7_wmask), \ .rvfi_csr_pmpcfg7_rdata (rvfi_csr_pmpcfg7_rdata), \ .rvfi_csr_pmpcfg7_wdata (rvfi_csr_pmpcfg7_wdata) `define rvformal_csr_pmpcfg7_channel_conn(_idx), \ .rvfi_csr_pmpcfg7_rmask (rvfi_csr_pmpcfg7_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg7_wmask (rvfi_csr_pmpcfg7_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg7_rdata (rvfi_csr_pmpcfg7_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg7_wdata (rvfi_csr_pmpcfg7_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg7_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg7_rmask = rvfi_csr_pmpcfg7_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg7_wmask = rvfi_csr_pmpcfg7_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg7_rdata = rvfi_csr_pmpcfg7_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg7_wdata = rvfi_csr_pmpcfg7_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg7_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg7_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg7_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg7_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg7_wdata) `else `define rvformal_csr_pmpcfg7_wires `define rvformal_csr_pmpcfg7_outputs `define rvformal_csr_pmpcfg7_inputs `define rvformal_csr_pmpcfg7_conn `define rvformal_csr_pmpcfg7_channel(_idx) `endif `define rvformal_csr_pmpcfg7_indices \ localparam [11:0] csr_mindex_pmpcfg7 = 12'h3A7; \ localparam [11:0] csr_sindex_pmpcfg7 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg7 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG8 `define rvformal_csr_pmpcfg8_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wdata; `define rvformal_csr_pmpcfg8_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wdata `define rvformal_csr_pmpcfg8_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wdata `define rvformal_csr_pmpcfg8_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wdata `define rvformal_csr_pmpcfg8_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wdata `define rvformal_csr_pmpcfg8_conn, \ .rvfi_csr_pmpcfg8_rmask (rvfi_csr_pmpcfg8_rmask), \ .rvfi_csr_pmpcfg8_wmask (rvfi_csr_pmpcfg8_wmask), \ .rvfi_csr_pmpcfg8_rdata (rvfi_csr_pmpcfg8_rdata), \ .rvfi_csr_pmpcfg8_wdata (rvfi_csr_pmpcfg8_wdata) `define rvformal_csr_pmpcfg8_channel_conn(_idx), \ .rvfi_csr_pmpcfg8_rmask (rvfi_csr_pmpcfg8_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg8_wmask (rvfi_csr_pmpcfg8_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg8_rdata (rvfi_csr_pmpcfg8_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg8_wdata (rvfi_csr_pmpcfg8_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg8_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg8_rmask = rvfi_csr_pmpcfg8_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg8_wmask = rvfi_csr_pmpcfg8_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg8_rdata = rvfi_csr_pmpcfg8_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg8_wdata = rvfi_csr_pmpcfg8_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg8_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg8_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg8_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg8_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg8_wdata) `else `define rvformal_csr_pmpcfg8_wires `define rvformal_csr_pmpcfg8_outputs `define rvformal_csr_pmpcfg8_inputs `define rvformal_csr_pmpcfg8_conn `define rvformal_csr_pmpcfg8_channel(_idx) `endif `define rvformal_csr_pmpcfg8_indices \ localparam [11:0] csr_mindex_pmpcfg8 = 12'h3A8; \ localparam [11:0] csr_sindex_pmpcfg8 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg8 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG9 `define rvformal_csr_pmpcfg9_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wdata; `define rvformal_csr_pmpcfg9_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wdata `define rvformal_csr_pmpcfg9_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wdata `define rvformal_csr_pmpcfg9_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wdata `define rvformal_csr_pmpcfg9_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wdata `define rvformal_csr_pmpcfg9_conn, \ .rvfi_csr_pmpcfg9_rmask (rvfi_csr_pmpcfg9_rmask), \ .rvfi_csr_pmpcfg9_wmask (rvfi_csr_pmpcfg9_wmask), \ .rvfi_csr_pmpcfg9_rdata (rvfi_csr_pmpcfg9_rdata), \ .rvfi_csr_pmpcfg9_wdata (rvfi_csr_pmpcfg9_wdata) `define rvformal_csr_pmpcfg9_channel_conn(_idx), \ .rvfi_csr_pmpcfg9_rmask (rvfi_csr_pmpcfg9_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg9_wmask (rvfi_csr_pmpcfg9_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg9_rdata (rvfi_csr_pmpcfg9_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg9_wdata (rvfi_csr_pmpcfg9_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg9_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg9_rmask = rvfi_csr_pmpcfg9_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg9_wmask = rvfi_csr_pmpcfg9_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg9_rdata = rvfi_csr_pmpcfg9_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg9_wdata = rvfi_csr_pmpcfg9_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg9_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg9_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg9_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg9_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg9_wdata) `else `define rvformal_csr_pmpcfg9_wires `define rvformal_csr_pmpcfg9_outputs `define rvformal_csr_pmpcfg9_inputs `define rvformal_csr_pmpcfg9_conn `define rvformal_csr_pmpcfg9_channel(_idx) `endif `define rvformal_csr_pmpcfg9_indices \ localparam [11:0] csr_mindex_pmpcfg9 = 12'h3A9; \ localparam [11:0] csr_sindex_pmpcfg9 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg9 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG10 `define rvformal_csr_pmpcfg10_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wdata; `define rvformal_csr_pmpcfg10_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wdata `define rvformal_csr_pmpcfg10_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wdata `define rvformal_csr_pmpcfg10_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wdata `define rvformal_csr_pmpcfg10_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wdata `define rvformal_csr_pmpcfg10_conn, \ .rvfi_csr_pmpcfg10_rmask (rvfi_csr_pmpcfg10_rmask), \ .rvfi_csr_pmpcfg10_wmask (rvfi_csr_pmpcfg10_wmask), \ .rvfi_csr_pmpcfg10_rdata (rvfi_csr_pmpcfg10_rdata), \ .rvfi_csr_pmpcfg10_wdata (rvfi_csr_pmpcfg10_wdata) `define rvformal_csr_pmpcfg10_channel_conn(_idx), \ .rvfi_csr_pmpcfg10_rmask (rvfi_csr_pmpcfg10_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg10_wmask (rvfi_csr_pmpcfg10_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg10_rdata (rvfi_csr_pmpcfg10_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg10_wdata (rvfi_csr_pmpcfg10_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg10_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg10_rmask = rvfi_csr_pmpcfg10_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg10_wmask = rvfi_csr_pmpcfg10_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg10_rdata = rvfi_csr_pmpcfg10_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg10_wdata = rvfi_csr_pmpcfg10_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg10_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg10_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg10_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg10_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg10_wdata) `else `define rvformal_csr_pmpcfg10_wires `define rvformal_csr_pmpcfg10_outputs `define rvformal_csr_pmpcfg10_inputs `define rvformal_csr_pmpcfg10_conn `define rvformal_csr_pmpcfg10_channel(_idx) `endif `define rvformal_csr_pmpcfg10_indices \ localparam [11:0] csr_mindex_pmpcfg10 = 12'h3AA; \ localparam [11:0] csr_sindex_pmpcfg10 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg10 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG11 `define rvformal_csr_pmpcfg11_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wdata; `define rvformal_csr_pmpcfg11_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wdata `define rvformal_csr_pmpcfg11_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wdata `define rvformal_csr_pmpcfg11_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wdata `define rvformal_csr_pmpcfg11_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wdata `define rvformal_csr_pmpcfg11_conn, \ .rvfi_csr_pmpcfg11_rmask (rvfi_csr_pmpcfg11_rmask), \ .rvfi_csr_pmpcfg11_wmask (rvfi_csr_pmpcfg11_wmask), \ .rvfi_csr_pmpcfg11_rdata (rvfi_csr_pmpcfg11_rdata), \ .rvfi_csr_pmpcfg11_wdata (rvfi_csr_pmpcfg11_wdata) `define rvformal_csr_pmpcfg11_channel_conn(_idx), \ .rvfi_csr_pmpcfg11_rmask (rvfi_csr_pmpcfg11_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg11_wmask (rvfi_csr_pmpcfg11_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg11_rdata (rvfi_csr_pmpcfg11_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg11_wdata (rvfi_csr_pmpcfg11_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg11_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg11_rmask = rvfi_csr_pmpcfg11_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg11_wmask = rvfi_csr_pmpcfg11_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg11_rdata = rvfi_csr_pmpcfg11_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg11_wdata = rvfi_csr_pmpcfg11_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg11_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg11_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg11_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg11_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg11_wdata) `else `define rvformal_csr_pmpcfg11_wires `define rvformal_csr_pmpcfg11_outputs `define rvformal_csr_pmpcfg11_inputs `define rvformal_csr_pmpcfg11_conn `define rvformal_csr_pmpcfg11_channel(_idx) `endif `define rvformal_csr_pmpcfg11_indices \ localparam [11:0] csr_mindex_pmpcfg11 = 12'h3AB; \ localparam [11:0] csr_sindex_pmpcfg11 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg11 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG12 `define rvformal_csr_pmpcfg12_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wdata; `define rvformal_csr_pmpcfg12_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wdata `define rvformal_csr_pmpcfg12_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wdata `define rvformal_csr_pmpcfg12_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wdata `define rvformal_csr_pmpcfg12_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wdata `define rvformal_csr_pmpcfg12_conn, \ .rvfi_csr_pmpcfg12_rmask (rvfi_csr_pmpcfg12_rmask), \ .rvfi_csr_pmpcfg12_wmask (rvfi_csr_pmpcfg12_wmask), \ .rvfi_csr_pmpcfg12_rdata (rvfi_csr_pmpcfg12_rdata), \ .rvfi_csr_pmpcfg12_wdata (rvfi_csr_pmpcfg12_wdata) `define rvformal_csr_pmpcfg12_channel_conn(_idx), \ .rvfi_csr_pmpcfg12_rmask (rvfi_csr_pmpcfg12_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg12_wmask (rvfi_csr_pmpcfg12_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg12_rdata (rvfi_csr_pmpcfg12_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg12_wdata (rvfi_csr_pmpcfg12_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg12_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg12_rmask = rvfi_csr_pmpcfg12_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg12_wmask = rvfi_csr_pmpcfg12_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg12_rdata = rvfi_csr_pmpcfg12_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg12_wdata = rvfi_csr_pmpcfg12_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg12_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg12_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg12_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg12_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg12_wdata) `else `define rvformal_csr_pmpcfg12_wires `define rvformal_csr_pmpcfg12_outputs `define rvformal_csr_pmpcfg12_inputs `define rvformal_csr_pmpcfg12_conn `define rvformal_csr_pmpcfg12_channel(_idx) `endif `define rvformal_csr_pmpcfg12_indices \ localparam [11:0] csr_mindex_pmpcfg12 = 12'h3AC; \ localparam [11:0] csr_sindex_pmpcfg12 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg12 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG13 `define rvformal_csr_pmpcfg13_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wdata; `define rvformal_csr_pmpcfg13_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wdata `define rvformal_csr_pmpcfg13_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wdata `define rvformal_csr_pmpcfg13_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wdata `define rvformal_csr_pmpcfg13_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wdata `define rvformal_csr_pmpcfg13_conn, \ .rvfi_csr_pmpcfg13_rmask (rvfi_csr_pmpcfg13_rmask), \ .rvfi_csr_pmpcfg13_wmask (rvfi_csr_pmpcfg13_wmask), \ .rvfi_csr_pmpcfg13_rdata (rvfi_csr_pmpcfg13_rdata), \ .rvfi_csr_pmpcfg13_wdata (rvfi_csr_pmpcfg13_wdata) `define rvformal_csr_pmpcfg13_channel_conn(_idx), \ .rvfi_csr_pmpcfg13_rmask (rvfi_csr_pmpcfg13_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg13_wmask (rvfi_csr_pmpcfg13_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg13_rdata (rvfi_csr_pmpcfg13_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg13_wdata (rvfi_csr_pmpcfg13_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg13_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg13_rmask = rvfi_csr_pmpcfg13_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg13_wmask = rvfi_csr_pmpcfg13_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg13_rdata = rvfi_csr_pmpcfg13_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg13_wdata = rvfi_csr_pmpcfg13_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg13_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg13_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg13_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg13_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg13_wdata) `else `define rvformal_csr_pmpcfg13_wires `define rvformal_csr_pmpcfg13_outputs `define rvformal_csr_pmpcfg13_inputs `define rvformal_csr_pmpcfg13_conn `define rvformal_csr_pmpcfg13_channel(_idx) `endif `define rvformal_csr_pmpcfg13_indices \ localparam [11:0] csr_mindex_pmpcfg13 = 12'h3AD; \ localparam [11:0] csr_sindex_pmpcfg13 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg13 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG14 `define rvformal_csr_pmpcfg14_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wdata; `define rvformal_csr_pmpcfg14_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wdata `define rvformal_csr_pmpcfg14_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wdata `define rvformal_csr_pmpcfg14_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wdata `define rvformal_csr_pmpcfg14_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wdata `define rvformal_csr_pmpcfg14_conn, \ .rvfi_csr_pmpcfg14_rmask (rvfi_csr_pmpcfg14_rmask), \ .rvfi_csr_pmpcfg14_wmask (rvfi_csr_pmpcfg14_wmask), \ .rvfi_csr_pmpcfg14_rdata (rvfi_csr_pmpcfg14_rdata), \ .rvfi_csr_pmpcfg14_wdata (rvfi_csr_pmpcfg14_wdata) `define rvformal_csr_pmpcfg14_channel_conn(_idx), \ .rvfi_csr_pmpcfg14_rmask (rvfi_csr_pmpcfg14_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg14_wmask (rvfi_csr_pmpcfg14_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg14_rdata (rvfi_csr_pmpcfg14_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg14_wdata (rvfi_csr_pmpcfg14_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg14_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg14_rmask = rvfi_csr_pmpcfg14_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg14_wmask = rvfi_csr_pmpcfg14_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg14_rdata = rvfi_csr_pmpcfg14_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg14_wdata = rvfi_csr_pmpcfg14_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg14_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg14_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg14_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg14_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg14_wdata) `else `define rvformal_csr_pmpcfg14_wires `define rvformal_csr_pmpcfg14_outputs `define rvformal_csr_pmpcfg14_inputs `define rvformal_csr_pmpcfg14_conn `define rvformal_csr_pmpcfg14_channel(_idx) `endif `define rvformal_csr_pmpcfg14_indices \ localparam [11:0] csr_mindex_pmpcfg14 = 12'h3AE; \ localparam [11:0] csr_sindex_pmpcfg14 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg14 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPCFG15 `define rvformal_csr_pmpcfg15_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wdata; `define rvformal_csr_pmpcfg15_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wdata `define rvformal_csr_pmpcfg15_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wdata `define rvformal_csr_pmpcfg15_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wdata `define rvformal_csr_pmpcfg15_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wdata `define rvformal_csr_pmpcfg15_conn, \ .rvfi_csr_pmpcfg15_rmask (rvfi_csr_pmpcfg15_rmask), \ .rvfi_csr_pmpcfg15_wmask (rvfi_csr_pmpcfg15_wmask), \ .rvfi_csr_pmpcfg15_rdata (rvfi_csr_pmpcfg15_rdata), \ .rvfi_csr_pmpcfg15_wdata (rvfi_csr_pmpcfg15_wdata) `define rvformal_csr_pmpcfg15_channel_conn(_idx), \ .rvfi_csr_pmpcfg15_rmask (rvfi_csr_pmpcfg15_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg15_wmask (rvfi_csr_pmpcfg15_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg15_rdata (rvfi_csr_pmpcfg15_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpcfg15_wdata (rvfi_csr_pmpcfg15_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpcfg15_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg15_rmask = rvfi_csr_pmpcfg15_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg15_wmask = rvfi_csr_pmpcfg15_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg15_rdata = rvfi_csr_pmpcfg15_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg15_wdata = rvfi_csr_pmpcfg15_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpcfg15_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg15_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg15_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg15_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg15_wdata) `else `define rvformal_csr_pmpcfg15_wires `define rvformal_csr_pmpcfg15_outputs `define rvformal_csr_pmpcfg15_inputs `define rvformal_csr_pmpcfg15_conn `define rvformal_csr_pmpcfg15_channel(_idx) `endif `define rvformal_csr_pmpcfg15_indices \ localparam [11:0] csr_mindex_pmpcfg15 = 12'h3AF; \ localparam [11:0] csr_sindex_pmpcfg15 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpcfg15 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR0 `define rvformal_csr_pmpaddr0_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wdata; `define rvformal_csr_pmpaddr0_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wdata `define rvformal_csr_pmpaddr0_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wdata `define rvformal_csr_pmpaddr0_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wdata `define rvformal_csr_pmpaddr0_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wdata `define rvformal_csr_pmpaddr0_conn, \ .rvfi_csr_pmpaddr0_rmask (rvfi_csr_pmpaddr0_rmask), \ .rvfi_csr_pmpaddr0_wmask (rvfi_csr_pmpaddr0_wmask), \ .rvfi_csr_pmpaddr0_rdata (rvfi_csr_pmpaddr0_rdata), \ .rvfi_csr_pmpaddr0_wdata (rvfi_csr_pmpaddr0_wdata) `define rvformal_csr_pmpaddr0_channel_conn(_idx), \ .rvfi_csr_pmpaddr0_rmask (rvfi_csr_pmpaddr0_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr0_wmask (rvfi_csr_pmpaddr0_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr0_rdata (rvfi_csr_pmpaddr0_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr0_wdata (rvfi_csr_pmpaddr0_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr0_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr0_rmask = rvfi_csr_pmpaddr0_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr0_wmask = rvfi_csr_pmpaddr0_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr0_rdata = rvfi_csr_pmpaddr0_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr0_wdata = rvfi_csr_pmpaddr0_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr0_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr0_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr0_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr0_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr0_wdata) `else `define rvformal_csr_pmpaddr0_wires `define rvformal_csr_pmpaddr0_outputs `define rvformal_csr_pmpaddr0_inputs `define rvformal_csr_pmpaddr0_conn `define rvformal_csr_pmpaddr0_channel(_idx) `endif `define rvformal_csr_pmpaddr0_indices \ localparam [11:0] csr_mindex_pmpaddr0 = 12'h3B0; \ localparam [11:0] csr_sindex_pmpaddr0 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr0 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR1 `define rvformal_csr_pmpaddr1_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wdata; `define rvformal_csr_pmpaddr1_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wdata `define rvformal_csr_pmpaddr1_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wdata `define rvformal_csr_pmpaddr1_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wdata `define rvformal_csr_pmpaddr1_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wdata `define rvformal_csr_pmpaddr1_conn, \ .rvfi_csr_pmpaddr1_rmask (rvfi_csr_pmpaddr1_rmask), \ .rvfi_csr_pmpaddr1_wmask (rvfi_csr_pmpaddr1_wmask), \ .rvfi_csr_pmpaddr1_rdata (rvfi_csr_pmpaddr1_rdata), \ .rvfi_csr_pmpaddr1_wdata (rvfi_csr_pmpaddr1_wdata) `define rvformal_csr_pmpaddr1_channel_conn(_idx), \ .rvfi_csr_pmpaddr1_rmask (rvfi_csr_pmpaddr1_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr1_wmask (rvfi_csr_pmpaddr1_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr1_rdata (rvfi_csr_pmpaddr1_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr1_wdata (rvfi_csr_pmpaddr1_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr1_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr1_rmask = rvfi_csr_pmpaddr1_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr1_wmask = rvfi_csr_pmpaddr1_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr1_rdata = rvfi_csr_pmpaddr1_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr1_wdata = rvfi_csr_pmpaddr1_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr1_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr1_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr1_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr1_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr1_wdata) `else `define rvformal_csr_pmpaddr1_wires `define rvformal_csr_pmpaddr1_outputs `define rvformal_csr_pmpaddr1_inputs `define rvformal_csr_pmpaddr1_conn `define rvformal_csr_pmpaddr1_channel(_idx) `endif `define rvformal_csr_pmpaddr1_indices \ localparam [11:0] csr_mindex_pmpaddr1 = 12'h3B1; \ localparam [11:0] csr_sindex_pmpaddr1 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr1 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR2 `define rvformal_csr_pmpaddr2_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wdata; `define rvformal_csr_pmpaddr2_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wdata `define rvformal_csr_pmpaddr2_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wdata `define rvformal_csr_pmpaddr2_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wdata `define rvformal_csr_pmpaddr2_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wdata `define rvformal_csr_pmpaddr2_conn, \ .rvfi_csr_pmpaddr2_rmask (rvfi_csr_pmpaddr2_rmask), \ .rvfi_csr_pmpaddr2_wmask (rvfi_csr_pmpaddr2_wmask), \ .rvfi_csr_pmpaddr2_rdata (rvfi_csr_pmpaddr2_rdata), \ .rvfi_csr_pmpaddr2_wdata (rvfi_csr_pmpaddr2_wdata) `define rvformal_csr_pmpaddr2_channel_conn(_idx), \ .rvfi_csr_pmpaddr2_rmask (rvfi_csr_pmpaddr2_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr2_wmask (rvfi_csr_pmpaddr2_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr2_rdata (rvfi_csr_pmpaddr2_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr2_wdata (rvfi_csr_pmpaddr2_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr2_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr2_rmask = rvfi_csr_pmpaddr2_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr2_wmask = rvfi_csr_pmpaddr2_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr2_rdata = rvfi_csr_pmpaddr2_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr2_wdata = rvfi_csr_pmpaddr2_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr2_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr2_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr2_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr2_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr2_wdata) `else `define rvformal_csr_pmpaddr2_wires `define rvformal_csr_pmpaddr2_outputs `define rvformal_csr_pmpaddr2_inputs `define rvformal_csr_pmpaddr2_conn `define rvformal_csr_pmpaddr2_channel(_idx) `endif `define rvformal_csr_pmpaddr2_indices \ localparam [11:0] csr_mindex_pmpaddr2 = 12'h3B2; \ localparam [11:0] csr_sindex_pmpaddr2 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr2 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR3 `define rvformal_csr_pmpaddr3_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wdata; `define rvformal_csr_pmpaddr3_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wdata `define rvformal_csr_pmpaddr3_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wdata `define rvformal_csr_pmpaddr3_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wdata `define rvformal_csr_pmpaddr3_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wdata `define rvformal_csr_pmpaddr3_conn, \ .rvfi_csr_pmpaddr3_rmask (rvfi_csr_pmpaddr3_rmask), \ .rvfi_csr_pmpaddr3_wmask (rvfi_csr_pmpaddr3_wmask), \ .rvfi_csr_pmpaddr3_rdata (rvfi_csr_pmpaddr3_rdata), \ .rvfi_csr_pmpaddr3_wdata (rvfi_csr_pmpaddr3_wdata) `define rvformal_csr_pmpaddr3_channel_conn(_idx), \ .rvfi_csr_pmpaddr3_rmask (rvfi_csr_pmpaddr3_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr3_wmask (rvfi_csr_pmpaddr3_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr3_rdata (rvfi_csr_pmpaddr3_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr3_wdata (rvfi_csr_pmpaddr3_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr3_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr3_rmask = rvfi_csr_pmpaddr3_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr3_wmask = rvfi_csr_pmpaddr3_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr3_rdata = rvfi_csr_pmpaddr3_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr3_wdata = rvfi_csr_pmpaddr3_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr3_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr3_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr3_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr3_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr3_wdata) `else `define rvformal_csr_pmpaddr3_wires `define rvformal_csr_pmpaddr3_outputs `define rvformal_csr_pmpaddr3_inputs `define rvformal_csr_pmpaddr3_conn `define rvformal_csr_pmpaddr3_channel(_idx) `endif `define rvformal_csr_pmpaddr3_indices \ localparam [11:0] csr_mindex_pmpaddr3 = 12'h3B3; \ localparam [11:0] csr_sindex_pmpaddr3 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr3 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR4 `define rvformal_csr_pmpaddr4_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wdata; `define rvformal_csr_pmpaddr4_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wdata `define rvformal_csr_pmpaddr4_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wdata `define rvformal_csr_pmpaddr4_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wdata `define rvformal_csr_pmpaddr4_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wdata `define rvformal_csr_pmpaddr4_conn, \ .rvfi_csr_pmpaddr4_rmask (rvfi_csr_pmpaddr4_rmask), \ .rvfi_csr_pmpaddr4_wmask (rvfi_csr_pmpaddr4_wmask), \ .rvfi_csr_pmpaddr4_rdata (rvfi_csr_pmpaddr4_rdata), \ .rvfi_csr_pmpaddr4_wdata (rvfi_csr_pmpaddr4_wdata) `define rvformal_csr_pmpaddr4_channel_conn(_idx), \ .rvfi_csr_pmpaddr4_rmask (rvfi_csr_pmpaddr4_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr4_wmask (rvfi_csr_pmpaddr4_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr4_rdata (rvfi_csr_pmpaddr4_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr4_wdata (rvfi_csr_pmpaddr4_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr4_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr4_rmask = rvfi_csr_pmpaddr4_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr4_wmask = rvfi_csr_pmpaddr4_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr4_rdata = rvfi_csr_pmpaddr4_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr4_wdata = rvfi_csr_pmpaddr4_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr4_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr4_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr4_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr4_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr4_wdata) `else `define rvformal_csr_pmpaddr4_wires `define rvformal_csr_pmpaddr4_outputs `define rvformal_csr_pmpaddr4_inputs `define rvformal_csr_pmpaddr4_conn `define rvformal_csr_pmpaddr4_channel(_idx) `endif `define rvformal_csr_pmpaddr4_indices \ localparam [11:0] csr_mindex_pmpaddr4 = 12'h3B4; \ localparam [11:0] csr_sindex_pmpaddr4 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr4 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR5 `define rvformal_csr_pmpaddr5_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wdata; `define rvformal_csr_pmpaddr5_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wdata `define rvformal_csr_pmpaddr5_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wdata `define rvformal_csr_pmpaddr5_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wdata `define rvformal_csr_pmpaddr5_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wdata `define rvformal_csr_pmpaddr5_conn, \ .rvfi_csr_pmpaddr5_rmask (rvfi_csr_pmpaddr5_rmask), \ .rvfi_csr_pmpaddr5_wmask (rvfi_csr_pmpaddr5_wmask), \ .rvfi_csr_pmpaddr5_rdata (rvfi_csr_pmpaddr5_rdata), \ .rvfi_csr_pmpaddr5_wdata (rvfi_csr_pmpaddr5_wdata) `define rvformal_csr_pmpaddr5_channel_conn(_idx), \ .rvfi_csr_pmpaddr5_rmask (rvfi_csr_pmpaddr5_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr5_wmask (rvfi_csr_pmpaddr5_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr5_rdata (rvfi_csr_pmpaddr5_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr5_wdata (rvfi_csr_pmpaddr5_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr5_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr5_rmask = rvfi_csr_pmpaddr5_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr5_wmask = rvfi_csr_pmpaddr5_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr5_rdata = rvfi_csr_pmpaddr5_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr5_wdata = rvfi_csr_pmpaddr5_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr5_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr5_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr5_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr5_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr5_wdata) `else `define rvformal_csr_pmpaddr5_wires `define rvformal_csr_pmpaddr5_outputs `define rvformal_csr_pmpaddr5_inputs `define rvformal_csr_pmpaddr5_conn `define rvformal_csr_pmpaddr5_channel(_idx) `endif `define rvformal_csr_pmpaddr5_indices \ localparam [11:0] csr_mindex_pmpaddr5 = 12'h3B5; \ localparam [11:0] csr_sindex_pmpaddr5 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr5 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR6 `define rvformal_csr_pmpaddr6_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wdata; `define rvformal_csr_pmpaddr6_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wdata `define rvformal_csr_pmpaddr6_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wdata `define rvformal_csr_pmpaddr6_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wdata `define rvformal_csr_pmpaddr6_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wdata `define rvformal_csr_pmpaddr6_conn, \ .rvfi_csr_pmpaddr6_rmask (rvfi_csr_pmpaddr6_rmask), \ .rvfi_csr_pmpaddr6_wmask (rvfi_csr_pmpaddr6_wmask), \ .rvfi_csr_pmpaddr6_rdata (rvfi_csr_pmpaddr6_rdata), \ .rvfi_csr_pmpaddr6_wdata (rvfi_csr_pmpaddr6_wdata) `define rvformal_csr_pmpaddr6_channel_conn(_idx), \ .rvfi_csr_pmpaddr6_rmask (rvfi_csr_pmpaddr6_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr6_wmask (rvfi_csr_pmpaddr6_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr6_rdata (rvfi_csr_pmpaddr6_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr6_wdata (rvfi_csr_pmpaddr6_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr6_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr6_rmask = rvfi_csr_pmpaddr6_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr6_wmask = rvfi_csr_pmpaddr6_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr6_rdata = rvfi_csr_pmpaddr6_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr6_wdata = rvfi_csr_pmpaddr6_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr6_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr6_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr6_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr6_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr6_wdata) `else `define rvformal_csr_pmpaddr6_wires `define rvformal_csr_pmpaddr6_outputs `define rvformal_csr_pmpaddr6_inputs `define rvformal_csr_pmpaddr6_conn `define rvformal_csr_pmpaddr6_channel(_idx) `endif `define rvformal_csr_pmpaddr6_indices \ localparam [11:0] csr_mindex_pmpaddr6 = 12'h3B6; \ localparam [11:0] csr_sindex_pmpaddr6 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr6 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR7 `define rvformal_csr_pmpaddr7_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wdata; `define rvformal_csr_pmpaddr7_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wdata `define rvformal_csr_pmpaddr7_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wdata `define rvformal_csr_pmpaddr7_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wdata `define rvformal_csr_pmpaddr7_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wdata `define rvformal_csr_pmpaddr7_conn, \ .rvfi_csr_pmpaddr7_rmask (rvfi_csr_pmpaddr7_rmask), \ .rvfi_csr_pmpaddr7_wmask (rvfi_csr_pmpaddr7_wmask), \ .rvfi_csr_pmpaddr7_rdata (rvfi_csr_pmpaddr7_rdata), \ .rvfi_csr_pmpaddr7_wdata (rvfi_csr_pmpaddr7_wdata) `define rvformal_csr_pmpaddr7_channel_conn(_idx), \ .rvfi_csr_pmpaddr7_rmask (rvfi_csr_pmpaddr7_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr7_wmask (rvfi_csr_pmpaddr7_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr7_rdata (rvfi_csr_pmpaddr7_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr7_wdata (rvfi_csr_pmpaddr7_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr7_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr7_rmask = rvfi_csr_pmpaddr7_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr7_wmask = rvfi_csr_pmpaddr7_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr7_rdata = rvfi_csr_pmpaddr7_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr7_wdata = rvfi_csr_pmpaddr7_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr7_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr7_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr7_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr7_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr7_wdata) `else `define rvformal_csr_pmpaddr7_wires `define rvformal_csr_pmpaddr7_outputs `define rvformal_csr_pmpaddr7_inputs `define rvformal_csr_pmpaddr7_conn `define rvformal_csr_pmpaddr7_channel(_idx) `endif `define rvformal_csr_pmpaddr7_indices \ localparam [11:0] csr_mindex_pmpaddr7 = 12'h3B7; \ localparam [11:0] csr_sindex_pmpaddr7 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr7 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR8 `define rvformal_csr_pmpaddr8_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wdata; `define rvformal_csr_pmpaddr8_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wdata `define rvformal_csr_pmpaddr8_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wdata `define rvformal_csr_pmpaddr8_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wdata `define rvformal_csr_pmpaddr8_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wdata `define rvformal_csr_pmpaddr8_conn, \ .rvfi_csr_pmpaddr8_rmask (rvfi_csr_pmpaddr8_rmask), \ .rvfi_csr_pmpaddr8_wmask (rvfi_csr_pmpaddr8_wmask), \ .rvfi_csr_pmpaddr8_rdata (rvfi_csr_pmpaddr8_rdata), \ .rvfi_csr_pmpaddr8_wdata (rvfi_csr_pmpaddr8_wdata) `define rvformal_csr_pmpaddr8_channel_conn(_idx), \ .rvfi_csr_pmpaddr8_rmask (rvfi_csr_pmpaddr8_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr8_wmask (rvfi_csr_pmpaddr8_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr8_rdata (rvfi_csr_pmpaddr8_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr8_wdata (rvfi_csr_pmpaddr8_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr8_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr8_rmask = rvfi_csr_pmpaddr8_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr8_wmask = rvfi_csr_pmpaddr8_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr8_rdata = rvfi_csr_pmpaddr8_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr8_wdata = rvfi_csr_pmpaddr8_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr8_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr8_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr8_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr8_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr8_wdata) `else `define rvformal_csr_pmpaddr8_wires `define rvformal_csr_pmpaddr8_outputs `define rvformal_csr_pmpaddr8_inputs `define rvformal_csr_pmpaddr8_conn `define rvformal_csr_pmpaddr8_channel(_idx) `endif `define rvformal_csr_pmpaddr8_indices \ localparam [11:0] csr_mindex_pmpaddr8 = 12'h3B8; \ localparam [11:0] csr_sindex_pmpaddr8 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr8 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR9 `define rvformal_csr_pmpaddr9_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wdata; `define rvformal_csr_pmpaddr9_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wdata `define rvformal_csr_pmpaddr9_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wdata `define rvformal_csr_pmpaddr9_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wdata `define rvformal_csr_pmpaddr9_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wdata `define rvformal_csr_pmpaddr9_conn, \ .rvfi_csr_pmpaddr9_rmask (rvfi_csr_pmpaddr9_rmask), \ .rvfi_csr_pmpaddr9_wmask (rvfi_csr_pmpaddr9_wmask), \ .rvfi_csr_pmpaddr9_rdata (rvfi_csr_pmpaddr9_rdata), \ .rvfi_csr_pmpaddr9_wdata (rvfi_csr_pmpaddr9_wdata) `define rvformal_csr_pmpaddr9_channel_conn(_idx), \ .rvfi_csr_pmpaddr9_rmask (rvfi_csr_pmpaddr9_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr9_wmask (rvfi_csr_pmpaddr9_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr9_rdata (rvfi_csr_pmpaddr9_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr9_wdata (rvfi_csr_pmpaddr9_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr9_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr9_rmask = rvfi_csr_pmpaddr9_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr9_wmask = rvfi_csr_pmpaddr9_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr9_rdata = rvfi_csr_pmpaddr9_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr9_wdata = rvfi_csr_pmpaddr9_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr9_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr9_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr9_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr9_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr9_wdata) `else `define rvformal_csr_pmpaddr9_wires `define rvformal_csr_pmpaddr9_outputs `define rvformal_csr_pmpaddr9_inputs `define rvformal_csr_pmpaddr9_conn `define rvformal_csr_pmpaddr9_channel(_idx) `endif `define rvformal_csr_pmpaddr9_indices \ localparam [11:0] csr_mindex_pmpaddr9 = 12'h3B9; \ localparam [11:0] csr_sindex_pmpaddr9 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr9 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR10 `define rvformal_csr_pmpaddr10_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wdata; `define rvformal_csr_pmpaddr10_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wdata `define rvformal_csr_pmpaddr10_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wdata `define rvformal_csr_pmpaddr10_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wdata `define rvformal_csr_pmpaddr10_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wdata `define rvformal_csr_pmpaddr10_conn, \ .rvfi_csr_pmpaddr10_rmask (rvfi_csr_pmpaddr10_rmask), \ .rvfi_csr_pmpaddr10_wmask (rvfi_csr_pmpaddr10_wmask), \ .rvfi_csr_pmpaddr10_rdata (rvfi_csr_pmpaddr10_rdata), \ .rvfi_csr_pmpaddr10_wdata (rvfi_csr_pmpaddr10_wdata) `define rvformal_csr_pmpaddr10_channel_conn(_idx), \ .rvfi_csr_pmpaddr10_rmask (rvfi_csr_pmpaddr10_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr10_wmask (rvfi_csr_pmpaddr10_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr10_rdata (rvfi_csr_pmpaddr10_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr10_wdata (rvfi_csr_pmpaddr10_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr10_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr10_rmask = rvfi_csr_pmpaddr10_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr10_wmask = rvfi_csr_pmpaddr10_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr10_rdata = rvfi_csr_pmpaddr10_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr10_wdata = rvfi_csr_pmpaddr10_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr10_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr10_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr10_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr10_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr10_wdata) `else `define rvformal_csr_pmpaddr10_wires `define rvformal_csr_pmpaddr10_outputs `define rvformal_csr_pmpaddr10_inputs `define rvformal_csr_pmpaddr10_conn `define rvformal_csr_pmpaddr10_channel(_idx) `endif `define rvformal_csr_pmpaddr10_indices \ localparam [11:0] csr_mindex_pmpaddr10 = 12'h3BA; \ localparam [11:0] csr_sindex_pmpaddr10 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr10 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR11 `define rvformal_csr_pmpaddr11_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wdata; `define rvformal_csr_pmpaddr11_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wdata `define rvformal_csr_pmpaddr11_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wdata `define rvformal_csr_pmpaddr11_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wdata `define rvformal_csr_pmpaddr11_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wdata `define rvformal_csr_pmpaddr11_conn, \ .rvfi_csr_pmpaddr11_rmask (rvfi_csr_pmpaddr11_rmask), \ .rvfi_csr_pmpaddr11_wmask (rvfi_csr_pmpaddr11_wmask), \ .rvfi_csr_pmpaddr11_rdata (rvfi_csr_pmpaddr11_rdata), \ .rvfi_csr_pmpaddr11_wdata (rvfi_csr_pmpaddr11_wdata) `define rvformal_csr_pmpaddr11_channel_conn(_idx), \ .rvfi_csr_pmpaddr11_rmask (rvfi_csr_pmpaddr11_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr11_wmask (rvfi_csr_pmpaddr11_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr11_rdata (rvfi_csr_pmpaddr11_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr11_wdata (rvfi_csr_pmpaddr11_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr11_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr11_rmask = rvfi_csr_pmpaddr11_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr11_wmask = rvfi_csr_pmpaddr11_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr11_rdata = rvfi_csr_pmpaddr11_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr11_wdata = rvfi_csr_pmpaddr11_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr11_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr11_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr11_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr11_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr11_wdata) `else `define rvformal_csr_pmpaddr11_wires `define rvformal_csr_pmpaddr11_outputs `define rvformal_csr_pmpaddr11_inputs `define rvformal_csr_pmpaddr11_conn `define rvformal_csr_pmpaddr11_channel(_idx) `endif `define rvformal_csr_pmpaddr11_indices \ localparam [11:0] csr_mindex_pmpaddr11 = 12'h3BB; \ localparam [11:0] csr_sindex_pmpaddr11 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr11 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR12 `define rvformal_csr_pmpaddr12_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wdata; `define rvformal_csr_pmpaddr12_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wdata `define rvformal_csr_pmpaddr12_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wdata `define rvformal_csr_pmpaddr12_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wdata `define rvformal_csr_pmpaddr12_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wdata `define rvformal_csr_pmpaddr12_conn, \ .rvfi_csr_pmpaddr12_rmask (rvfi_csr_pmpaddr12_rmask), \ .rvfi_csr_pmpaddr12_wmask (rvfi_csr_pmpaddr12_wmask), \ .rvfi_csr_pmpaddr12_rdata (rvfi_csr_pmpaddr12_rdata), \ .rvfi_csr_pmpaddr12_wdata (rvfi_csr_pmpaddr12_wdata) `define rvformal_csr_pmpaddr12_channel_conn(_idx), \ .rvfi_csr_pmpaddr12_rmask (rvfi_csr_pmpaddr12_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr12_wmask (rvfi_csr_pmpaddr12_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr12_rdata (rvfi_csr_pmpaddr12_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr12_wdata (rvfi_csr_pmpaddr12_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr12_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr12_rmask = rvfi_csr_pmpaddr12_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr12_wmask = rvfi_csr_pmpaddr12_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr12_rdata = rvfi_csr_pmpaddr12_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr12_wdata = rvfi_csr_pmpaddr12_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr12_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr12_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr12_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr12_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr12_wdata) `else `define rvformal_csr_pmpaddr12_wires `define rvformal_csr_pmpaddr12_outputs `define rvformal_csr_pmpaddr12_inputs `define rvformal_csr_pmpaddr12_conn `define rvformal_csr_pmpaddr12_channel(_idx) `endif `define rvformal_csr_pmpaddr12_indices \ localparam [11:0] csr_mindex_pmpaddr12 = 12'h3BC; \ localparam [11:0] csr_sindex_pmpaddr12 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr12 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR13 `define rvformal_csr_pmpaddr13_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wdata; `define rvformal_csr_pmpaddr13_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wdata `define rvformal_csr_pmpaddr13_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wdata `define rvformal_csr_pmpaddr13_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wdata `define rvformal_csr_pmpaddr13_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wdata `define rvformal_csr_pmpaddr13_conn, \ .rvfi_csr_pmpaddr13_rmask (rvfi_csr_pmpaddr13_rmask), \ .rvfi_csr_pmpaddr13_wmask (rvfi_csr_pmpaddr13_wmask), \ .rvfi_csr_pmpaddr13_rdata (rvfi_csr_pmpaddr13_rdata), \ .rvfi_csr_pmpaddr13_wdata (rvfi_csr_pmpaddr13_wdata) `define rvformal_csr_pmpaddr13_channel_conn(_idx), \ .rvfi_csr_pmpaddr13_rmask (rvfi_csr_pmpaddr13_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr13_wmask (rvfi_csr_pmpaddr13_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr13_rdata (rvfi_csr_pmpaddr13_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr13_wdata (rvfi_csr_pmpaddr13_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr13_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr13_rmask = rvfi_csr_pmpaddr13_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr13_wmask = rvfi_csr_pmpaddr13_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr13_rdata = rvfi_csr_pmpaddr13_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr13_wdata = rvfi_csr_pmpaddr13_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr13_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr13_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr13_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr13_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr13_wdata) `else `define rvformal_csr_pmpaddr13_wires `define rvformal_csr_pmpaddr13_outputs `define rvformal_csr_pmpaddr13_inputs `define rvformal_csr_pmpaddr13_conn `define rvformal_csr_pmpaddr13_channel(_idx) `endif `define rvformal_csr_pmpaddr13_indices \ localparam [11:0] csr_mindex_pmpaddr13 = 12'h3BD; \ localparam [11:0] csr_sindex_pmpaddr13 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr13 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR14 `define rvformal_csr_pmpaddr14_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wdata; `define rvformal_csr_pmpaddr14_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wdata `define rvformal_csr_pmpaddr14_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wdata `define rvformal_csr_pmpaddr14_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wdata `define rvformal_csr_pmpaddr14_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wdata `define rvformal_csr_pmpaddr14_conn, \ .rvfi_csr_pmpaddr14_rmask (rvfi_csr_pmpaddr14_rmask), \ .rvfi_csr_pmpaddr14_wmask (rvfi_csr_pmpaddr14_wmask), \ .rvfi_csr_pmpaddr14_rdata (rvfi_csr_pmpaddr14_rdata), \ .rvfi_csr_pmpaddr14_wdata (rvfi_csr_pmpaddr14_wdata) `define rvformal_csr_pmpaddr14_channel_conn(_idx), \ .rvfi_csr_pmpaddr14_rmask (rvfi_csr_pmpaddr14_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr14_wmask (rvfi_csr_pmpaddr14_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr14_rdata (rvfi_csr_pmpaddr14_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr14_wdata (rvfi_csr_pmpaddr14_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr14_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr14_rmask = rvfi_csr_pmpaddr14_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr14_wmask = rvfi_csr_pmpaddr14_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr14_rdata = rvfi_csr_pmpaddr14_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr14_wdata = rvfi_csr_pmpaddr14_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr14_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr14_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr14_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr14_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr14_wdata) `else `define rvformal_csr_pmpaddr14_wires `define rvformal_csr_pmpaddr14_outputs `define rvformal_csr_pmpaddr14_inputs `define rvformal_csr_pmpaddr14_conn `define rvformal_csr_pmpaddr14_channel(_idx) `endif `define rvformal_csr_pmpaddr14_indices \ localparam [11:0] csr_mindex_pmpaddr14 = 12'h3BE; \ localparam [11:0] csr_sindex_pmpaddr14 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr14 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR15 `define rvformal_csr_pmpaddr15_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wdata; `define rvformal_csr_pmpaddr15_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wdata `define rvformal_csr_pmpaddr15_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wdata `define rvformal_csr_pmpaddr15_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wdata `define rvformal_csr_pmpaddr15_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wdata `define rvformal_csr_pmpaddr15_conn, \ .rvfi_csr_pmpaddr15_rmask (rvfi_csr_pmpaddr15_rmask), \ .rvfi_csr_pmpaddr15_wmask (rvfi_csr_pmpaddr15_wmask), \ .rvfi_csr_pmpaddr15_rdata (rvfi_csr_pmpaddr15_rdata), \ .rvfi_csr_pmpaddr15_wdata (rvfi_csr_pmpaddr15_wdata) `define rvformal_csr_pmpaddr15_channel_conn(_idx), \ .rvfi_csr_pmpaddr15_rmask (rvfi_csr_pmpaddr15_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr15_wmask (rvfi_csr_pmpaddr15_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr15_rdata (rvfi_csr_pmpaddr15_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr15_wdata (rvfi_csr_pmpaddr15_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr15_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr15_rmask = rvfi_csr_pmpaddr15_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr15_wmask = rvfi_csr_pmpaddr15_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr15_rdata = rvfi_csr_pmpaddr15_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr15_wdata = rvfi_csr_pmpaddr15_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr15_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr15_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr15_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr15_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr15_wdata) `else `define rvformal_csr_pmpaddr15_wires `define rvformal_csr_pmpaddr15_outputs `define rvformal_csr_pmpaddr15_inputs `define rvformal_csr_pmpaddr15_conn `define rvformal_csr_pmpaddr15_channel(_idx) `endif `define rvformal_csr_pmpaddr15_indices \ localparam [11:0] csr_mindex_pmpaddr15 = 12'h3BF; \ localparam [11:0] csr_sindex_pmpaddr15 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr15 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR16 `define rvformal_csr_pmpaddr16_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wdata; `define rvformal_csr_pmpaddr16_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wdata `define rvformal_csr_pmpaddr16_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wdata `define rvformal_csr_pmpaddr16_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wdata `define rvformal_csr_pmpaddr16_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wdata `define rvformal_csr_pmpaddr16_conn, \ .rvfi_csr_pmpaddr16_rmask (rvfi_csr_pmpaddr16_rmask), \ .rvfi_csr_pmpaddr16_wmask (rvfi_csr_pmpaddr16_wmask), \ .rvfi_csr_pmpaddr16_rdata (rvfi_csr_pmpaddr16_rdata), \ .rvfi_csr_pmpaddr16_wdata (rvfi_csr_pmpaddr16_wdata) `define rvformal_csr_pmpaddr16_channel_conn(_idx), \ .rvfi_csr_pmpaddr16_rmask (rvfi_csr_pmpaddr16_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr16_wmask (rvfi_csr_pmpaddr16_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr16_rdata (rvfi_csr_pmpaddr16_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr16_wdata (rvfi_csr_pmpaddr16_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr16_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr16_rmask = rvfi_csr_pmpaddr16_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr16_wmask = rvfi_csr_pmpaddr16_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr16_rdata = rvfi_csr_pmpaddr16_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr16_wdata = rvfi_csr_pmpaddr16_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr16_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr16_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr16_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr16_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr16_wdata) `else `define rvformal_csr_pmpaddr16_wires `define rvformal_csr_pmpaddr16_outputs `define rvformal_csr_pmpaddr16_inputs `define rvformal_csr_pmpaddr16_conn `define rvformal_csr_pmpaddr16_channel(_idx) `endif `define rvformal_csr_pmpaddr16_indices \ localparam [11:0] csr_mindex_pmpaddr16 = 12'h3C0; \ localparam [11:0] csr_sindex_pmpaddr16 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr16 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR17 `define rvformal_csr_pmpaddr17_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wdata; `define rvformal_csr_pmpaddr17_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wdata `define rvformal_csr_pmpaddr17_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wdata `define rvformal_csr_pmpaddr17_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wdata `define rvformal_csr_pmpaddr17_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wdata `define rvformal_csr_pmpaddr17_conn, \ .rvfi_csr_pmpaddr17_rmask (rvfi_csr_pmpaddr17_rmask), \ .rvfi_csr_pmpaddr17_wmask (rvfi_csr_pmpaddr17_wmask), \ .rvfi_csr_pmpaddr17_rdata (rvfi_csr_pmpaddr17_rdata), \ .rvfi_csr_pmpaddr17_wdata (rvfi_csr_pmpaddr17_wdata) `define rvformal_csr_pmpaddr17_channel_conn(_idx), \ .rvfi_csr_pmpaddr17_rmask (rvfi_csr_pmpaddr17_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr17_wmask (rvfi_csr_pmpaddr17_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr17_rdata (rvfi_csr_pmpaddr17_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr17_wdata (rvfi_csr_pmpaddr17_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr17_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr17_rmask = rvfi_csr_pmpaddr17_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr17_wmask = rvfi_csr_pmpaddr17_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr17_rdata = rvfi_csr_pmpaddr17_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr17_wdata = rvfi_csr_pmpaddr17_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr17_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr17_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr17_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr17_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr17_wdata) `else `define rvformal_csr_pmpaddr17_wires `define rvformal_csr_pmpaddr17_outputs `define rvformal_csr_pmpaddr17_inputs `define rvformal_csr_pmpaddr17_conn `define rvformal_csr_pmpaddr17_channel(_idx) `endif `define rvformal_csr_pmpaddr17_indices \ localparam [11:0] csr_mindex_pmpaddr17 = 12'h3C1; \ localparam [11:0] csr_sindex_pmpaddr17 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr17 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR18 `define rvformal_csr_pmpaddr18_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wdata; `define rvformal_csr_pmpaddr18_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wdata `define rvformal_csr_pmpaddr18_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wdata `define rvformal_csr_pmpaddr18_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wdata `define rvformal_csr_pmpaddr18_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wdata `define rvformal_csr_pmpaddr18_conn, \ .rvfi_csr_pmpaddr18_rmask (rvfi_csr_pmpaddr18_rmask), \ .rvfi_csr_pmpaddr18_wmask (rvfi_csr_pmpaddr18_wmask), \ .rvfi_csr_pmpaddr18_rdata (rvfi_csr_pmpaddr18_rdata), \ .rvfi_csr_pmpaddr18_wdata (rvfi_csr_pmpaddr18_wdata) `define rvformal_csr_pmpaddr18_channel_conn(_idx), \ .rvfi_csr_pmpaddr18_rmask (rvfi_csr_pmpaddr18_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr18_wmask (rvfi_csr_pmpaddr18_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr18_rdata (rvfi_csr_pmpaddr18_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr18_wdata (rvfi_csr_pmpaddr18_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr18_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr18_rmask = rvfi_csr_pmpaddr18_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr18_wmask = rvfi_csr_pmpaddr18_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr18_rdata = rvfi_csr_pmpaddr18_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr18_wdata = rvfi_csr_pmpaddr18_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr18_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr18_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr18_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr18_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr18_wdata) `else `define rvformal_csr_pmpaddr18_wires `define rvformal_csr_pmpaddr18_outputs `define rvformal_csr_pmpaddr18_inputs `define rvformal_csr_pmpaddr18_conn `define rvformal_csr_pmpaddr18_channel(_idx) `endif `define rvformal_csr_pmpaddr18_indices \ localparam [11:0] csr_mindex_pmpaddr18 = 12'h3C2; \ localparam [11:0] csr_sindex_pmpaddr18 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr18 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR19 `define rvformal_csr_pmpaddr19_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wdata; `define rvformal_csr_pmpaddr19_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wdata `define rvformal_csr_pmpaddr19_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wdata `define rvformal_csr_pmpaddr19_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wdata `define rvformal_csr_pmpaddr19_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wdata `define rvformal_csr_pmpaddr19_conn, \ .rvfi_csr_pmpaddr19_rmask (rvfi_csr_pmpaddr19_rmask), \ .rvfi_csr_pmpaddr19_wmask (rvfi_csr_pmpaddr19_wmask), \ .rvfi_csr_pmpaddr19_rdata (rvfi_csr_pmpaddr19_rdata), \ .rvfi_csr_pmpaddr19_wdata (rvfi_csr_pmpaddr19_wdata) `define rvformal_csr_pmpaddr19_channel_conn(_idx), \ .rvfi_csr_pmpaddr19_rmask (rvfi_csr_pmpaddr19_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr19_wmask (rvfi_csr_pmpaddr19_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr19_rdata (rvfi_csr_pmpaddr19_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr19_wdata (rvfi_csr_pmpaddr19_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr19_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr19_rmask = rvfi_csr_pmpaddr19_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr19_wmask = rvfi_csr_pmpaddr19_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr19_rdata = rvfi_csr_pmpaddr19_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr19_wdata = rvfi_csr_pmpaddr19_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr19_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr19_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr19_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr19_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr19_wdata) `else `define rvformal_csr_pmpaddr19_wires `define rvformal_csr_pmpaddr19_outputs `define rvformal_csr_pmpaddr19_inputs `define rvformal_csr_pmpaddr19_conn `define rvformal_csr_pmpaddr19_channel(_idx) `endif `define rvformal_csr_pmpaddr19_indices \ localparam [11:0] csr_mindex_pmpaddr19 = 12'h3C3; \ localparam [11:0] csr_sindex_pmpaddr19 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr19 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR20 `define rvformal_csr_pmpaddr20_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wdata; `define rvformal_csr_pmpaddr20_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wdata `define rvformal_csr_pmpaddr20_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wdata `define rvformal_csr_pmpaddr20_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wdata `define rvformal_csr_pmpaddr20_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wdata `define rvformal_csr_pmpaddr20_conn, \ .rvfi_csr_pmpaddr20_rmask (rvfi_csr_pmpaddr20_rmask), \ .rvfi_csr_pmpaddr20_wmask (rvfi_csr_pmpaddr20_wmask), \ .rvfi_csr_pmpaddr20_rdata (rvfi_csr_pmpaddr20_rdata), \ .rvfi_csr_pmpaddr20_wdata (rvfi_csr_pmpaddr20_wdata) `define rvformal_csr_pmpaddr20_channel_conn(_idx), \ .rvfi_csr_pmpaddr20_rmask (rvfi_csr_pmpaddr20_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr20_wmask (rvfi_csr_pmpaddr20_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr20_rdata (rvfi_csr_pmpaddr20_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr20_wdata (rvfi_csr_pmpaddr20_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr20_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr20_rmask = rvfi_csr_pmpaddr20_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr20_wmask = rvfi_csr_pmpaddr20_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr20_rdata = rvfi_csr_pmpaddr20_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr20_wdata = rvfi_csr_pmpaddr20_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr20_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr20_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr20_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr20_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr20_wdata) `else `define rvformal_csr_pmpaddr20_wires `define rvformal_csr_pmpaddr20_outputs `define rvformal_csr_pmpaddr20_inputs `define rvformal_csr_pmpaddr20_conn `define rvformal_csr_pmpaddr20_channel(_idx) `endif `define rvformal_csr_pmpaddr20_indices \ localparam [11:0] csr_mindex_pmpaddr20 = 12'h3C4; \ localparam [11:0] csr_sindex_pmpaddr20 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr20 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR21 `define rvformal_csr_pmpaddr21_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wdata; `define rvformal_csr_pmpaddr21_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wdata `define rvformal_csr_pmpaddr21_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wdata `define rvformal_csr_pmpaddr21_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wdata `define rvformal_csr_pmpaddr21_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wdata `define rvformal_csr_pmpaddr21_conn, \ .rvfi_csr_pmpaddr21_rmask (rvfi_csr_pmpaddr21_rmask), \ .rvfi_csr_pmpaddr21_wmask (rvfi_csr_pmpaddr21_wmask), \ .rvfi_csr_pmpaddr21_rdata (rvfi_csr_pmpaddr21_rdata), \ .rvfi_csr_pmpaddr21_wdata (rvfi_csr_pmpaddr21_wdata) `define rvformal_csr_pmpaddr21_channel_conn(_idx), \ .rvfi_csr_pmpaddr21_rmask (rvfi_csr_pmpaddr21_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr21_wmask (rvfi_csr_pmpaddr21_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr21_rdata (rvfi_csr_pmpaddr21_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr21_wdata (rvfi_csr_pmpaddr21_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr21_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr21_rmask = rvfi_csr_pmpaddr21_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr21_wmask = rvfi_csr_pmpaddr21_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr21_rdata = rvfi_csr_pmpaddr21_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr21_wdata = rvfi_csr_pmpaddr21_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr21_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr21_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr21_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr21_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr21_wdata) `else `define rvformal_csr_pmpaddr21_wires `define rvformal_csr_pmpaddr21_outputs `define rvformal_csr_pmpaddr21_inputs `define rvformal_csr_pmpaddr21_conn `define rvformal_csr_pmpaddr21_channel(_idx) `endif `define rvformal_csr_pmpaddr21_indices \ localparam [11:0] csr_mindex_pmpaddr21 = 12'h3C5; \ localparam [11:0] csr_sindex_pmpaddr21 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr21 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR22 `define rvformal_csr_pmpaddr22_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wdata; `define rvformal_csr_pmpaddr22_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wdata `define rvformal_csr_pmpaddr22_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wdata `define rvformal_csr_pmpaddr22_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wdata `define rvformal_csr_pmpaddr22_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wdata `define rvformal_csr_pmpaddr22_conn, \ .rvfi_csr_pmpaddr22_rmask (rvfi_csr_pmpaddr22_rmask), \ .rvfi_csr_pmpaddr22_wmask (rvfi_csr_pmpaddr22_wmask), \ .rvfi_csr_pmpaddr22_rdata (rvfi_csr_pmpaddr22_rdata), \ .rvfi_csr_pmpaddr22_wdata (rvfi_csr_pmpaddr22_wdata) `define rvformal_csr_pmpaddr22_channel_conn(_idx), \ .rvfi_csr_pmpaddr22_rmask (rvfi_csr_pmpaddr22_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr22_wmask (rvfi_csr_pmpaddr22_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr22_rdata (rvfi_csr_pmpaddr22_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr22_wdata (rvfi_csr_pmpaddr22_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr22_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr22_rmask = rvfi_csr_pmpaddr22_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr22_wmask = rvfi_csr_pmpaddr22_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr22_rdata = rvfi_csr_pmpaddr22_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr22_wdata = rvfi_csr_pmpaddr22_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr22_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr22_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr22_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr22_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr22_wdata) `else `define rvformal_csr_pmpaddr22_wires `define rvformal_csr_pmpaddr22_outputs `define rvformal_csr_pmpaddr22_inputs `define rvformal_csr_pmpaddr22_conn `define rvformal_csr_pmpaddr22_channel(_idx) `endif `define rvformal_csr_pmpaddr22_indices \ localparam [11:0] csr_mindex_pmpaddr22 = 12'h3C6; \ localparam [11:0] csr_sindex_pmpaddr22 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr22 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR23 `define rvformal_csr_pmpaddr23_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wdata; `define rvformal_csr_pmpaddr23_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wdata `define rvformal_csr_pmpaddr23_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wdata `define rvformal_csr_pmpaddr23_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wdata `define rvformal_csr_pmpaddr23_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wdata `define rvformal_csr_pmpaddr23_conn, \ .rvfi_csr_pmpaddr23_rmask (rvfi_csr_pmpaddr23_rmask), \ .rvfi_csr_pmpaddr23_wmask (rvfi_csr_pmpaddr23_wmask), \ .rvfi_csr_pmpaddr23_rdata (rvfi_csr_pmpaddr23_rdata), \ .rvfi_csr_pmpaddr23_wdata (rvfi_csr_pmpaddr23_wdata) `define rvformal_csr_pmpaddr23_channel_conn(_idx), \ .rvfi_csr_pmpaddr23_rmask (rvfi_csr_pmpaddr23_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr23_wmask (rvfi_csr_pmpaddr23_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr23_rdata (rvfi_csr_pmpaddr23_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr23_wdata (rvfi_csr_pmpaddr23_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr23_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr23_rmask = rvfi_csr_pmpaddr23_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr23_wmask = rvfi_csr_pmpaddr23_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr23_rdata = rvfi_csr_pmpaddr23_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr23_wdata = rvfi_csr_pmpaddr23_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr23_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr23_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr23_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr23_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr23_wdata) `else `define rvformal_csr_pmpaddr23_wires `define rvformal_csr_pmpaddr23_outputs `define rvformal_csr_pmpaddr23_inputs `define rvformal_csr_pmpaddr23_conn `define rvformal_csr_pmpaddr23_channel(_idx) `endif `define rvformal_csr_pmpaddr23_indices \ localparam [11:0] csr_mindex_pmpaddr23 = 12'h3C7; \ localparam [11:0] csr_sindex_pmpaddr23 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr23 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR24 `define rvformal_csr_pmpaddr24_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wdata; `define rvformal_csr_pmpaddr24_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wdata `define rvformal_csr_pmpaddr24_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wdata `define rvformal_csr_pmpaddr24_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wdata `define rvformal_csr_pmpaddr24_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wdata `define rvformal_csr_pmpaddr24_conn, \ .rvfi_csr_pmpaddr24_rmask (rvfi_csr_pmpaddr24_rmask), \ .rvfi_csr_pmpaddr24_wmask (rvfi_csr_pmpaddr24_wmask), \ .rvfi_csr_pmpaddr24_rdata (rvfi_csr_pmpaddr24_rdata), \ .rvfi_csr_pmpaddr24_wdata (rvfi_csr_pmpaddr24_wdata) `define rvformal_csr_pmpaddr24_channel_conn(_idx), \ .rvfi_csr_pmpaddr24_rmask (rvfi_csr_pmpaddr24_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr24_wmask (rvfi_csr_pmpaddr24_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr24_rdata (rvfi_csr_pmpaddr24_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr24_wdata (rvfi_csr_pmpaddr24_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr24_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr24_rmask = rvfi_csr_pmpaddr24_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr24_wmask = rvfi_csr_pmpaddr24_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr24_rdata = rvfi_csr_pmpaddr24_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr24_wdata = rvfi_csr_pmpaddr24_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr24_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr24_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr24_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr24_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr24_wdata) `else `define rvformal_csr_pmpaddr24_wires `define rvformal_csr_pmpaddr24_outputs `define rvformal_csr_pmpaddr24_inputs `define rvformal_csr_pmpaddr24_conn `define rvformal_csr_pmpaddr24_channel(_idx) `endif `define rvformal_csr_pmpaddr24_indices \ localparam [11:0] csr_mindex_pmpaddr24 = 12'h3C8; \ localparam [11:0] csr_sindex_pmpaddr24 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr24 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR25 `define rvformal_csr_pmpaddr25_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wdata; `define rvformal_csr_pmpaddr25_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wdata `define rvformal_csr_pmpaddr25_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wdata `define rvformal_csr_pmpaddr25_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wdata `define rvformal_csr_pmpaddr25_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wdata `define rvformal_csr_pmpaddr25_conn, \ .rvfi_csr_pmpaddr25_rmask (rvfi_csr_pmpaddr25_rmask), \ .rvfi_csr_pmpaddr25_wmask (rvfi_csr_pmpaddr25_wmask), \ .rvfi_csr_pmpaddr25_rdata (rvfi_csr_pmpaddr25_rdata), \ .rvfi_csr_pmpaddr25_wdata (rvfi_csr_pmpaddr25_wdata) `define rvformal_csr_pmpaddr25_channel_conn(_idx), \ .rvfi_csr_pmpaddr25_rmask (rvfi_csr_pmpaddr25_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr25_wmask (rvfi_csr_pmpaddr25_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr25_rdata (rvfi_csr_pmpaddr25_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr25_wdata (rvfi_csr_pmpaddr25_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr25_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr25_rmask = rvfi_csr_pmpaddr25_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr25_wmask = rvfi_csr_pmpaddr25_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr25_rdata = rvfi_csr_pmpaddr25_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr25_wdata = rvfi_csr_pmpaddr25_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr25_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr25_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr25_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr25_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr25_wdata) `else `define rvformal_csr_pmpaddr25_wires `define rvformal_csr_pmpaddr25_outputs `define rvformal_csr_pmpaddr25_inputs `define rvformal_csr_pmpaddr25_conn `define rvformal_csr_pmpaddr25_channel(_idx) `endif `define rvformal_csr_pmpaddr25_indices \ localparam [11:0] csr_mindex_pmpaddr25 = 12'h3C9; \ localparam [11:0] csr_sindex_pmpaddr25 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr25 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR26 `define rvformal_csr_pmpaddr26_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wdata; `define rvformal_csr_pmpaddr26_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wdata `define rvformal_csr_pmpaddr26_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wdata `define rvformal_csr_pmpaddr26_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wdata `define rvformal_csr_pmpaddr26_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wdata `define rvformal_csr_pmpaddr26_conn, \ .rvfi_csr_pmpaddr26_rmask (rvfi_csr_pmpaddr26_rmask), \ .rvfi_csr_pmpaddr26_wmask (rvfi_csr_pmpaddr26_wmask), \ .rvfi_csr_pmpaddr26_rdata (rvfi_csr_pmpaddr26_rdata), \ .rvfi_csr_pmpaddr26_wdata (rvfi_csr_pmpaddr26_wdata) `define rvformal_csr_pmpaddr26_channel_conn(_idx), \ .rvfi_csr_pmpaddr26_rmask (rvfi_csr_pmpaddr26_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr26_wmask (rvfi_csr_pmpaddr26_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr26_rdata (rvfi_csr_pmpaddr26_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr26_wdata (rvfi_csr_pmpaddr26_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr26_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr26_rmask = rvfi_csr_pmpaddr26_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr26_wmask = rvfi_csr_pmpaddr26_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr26_rdata = rvfi_csr_pmpaddr26_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr26_wdata = rvfi_csr_pmpaddr26_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr26_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr26_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr26_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr26_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr26_wdata) `else `define rvformal_csr_pmpaddr26_wires `define rvformal_csr_pmpaddr26_outputs `define rvformal_csr_pmpaddr26_inputs `define rvformal_csr_pmpaddr26_conn `define rvformal_csr_pmpaddr26_channel(_idx) `endif `define rvformal_csr_pmpaddr26_indices \ localparam [11:0] csr_mindex_pmpaddr26 = 12'h3CA; \ localparam [11:0] csr_sindex_pmpaddr26 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr26 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR27 `define rvformal_csr_pmpaddr27_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wdata; `define rvformal_csr_pmpaddr27_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wdata `define rvformal_csr_pmpaddr27_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wdata `define rvformal_csr_pmpaddr27_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wdata `define rvformal_csr_pmpaddr27_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wdata `define rvformal_csr_pmpaddr27_conn, \ .rvfi_csr_pmpaddr27_rmask (rvfi_csr_pmpaddr27_rmask), \ .rvfi_csr_pmpaddr27_wmask (rvfi_csr_pmpaddr27_wmask), \ .rvfi_csr_pmpaddr27_rdata (rvfi_csr_pmpaddr27_rdata), \ .rvfi_csr_pmpaddr27_wdata (rvfi_csr_pmpaddr27_wdata) `define rvformal_csr_pmpaddr27_channel_conn(_idx), \ .rvfi_csr_pmpaddr27_rmask (rvfi_csr_pmpaddr27_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr27_wmask (rvfi_csr_pmpaddr27_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr27_rdata (rvfi_csr_pmpaddr27_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr27_wdata (rvfi_csr_pmpaddr27_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr27_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr27_rmask = rvfi_csr_pmpaddr27_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr27_wmask = rvfi_csr_pmpaddr27_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr27_rdata = rvfi_csr_pmpaddr27_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr27_wdata = rvfi_csr_pmpaddr27_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr27_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr27_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr27_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr27_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr27_wdata) `else `define rvformal_csr_pmpaddr27_wires `define rvformal_csr_pmpaddr27_outputs `define rvformal_csr_pmpaddr27_inputs `define rvformal_csr_pmpaddr27_conn `define rvformal_csr_pmpaddr27_channel(_idx) `endif `define rvformal_csr_pmpaddr27_indices \ localparam [11:0] csr_mindex_pmpaddr27 = 12'h3CB; \ localparam [11:0] csr_sindex_pmpaddr27 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr27 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR28 `define rvformal_csr_pmpaddr28_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wdata; `define rvformal_csr_pmpaddr28_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wdata `define rvformal_csr_pmpaddr28_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wdata `define rvformal_csr_pmpaddr28_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wdata `define rvformal_csr_pmpaddr28_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wdata `define rvformal_csr_pmpaddr28_conn, \ .rvfi_csr_pmpaddr28_rmask (rvfi_csr_pmpaddr28_rmask), \ .rvfi_csr_pmpaddr28_wmask (rvfi_csr_pmpaddr28_wmask), \ .rvfi_csr_pmpaddr28_rdata (rvfi_csr_pmpaddr28_rdata), \ .rvfi_csr_pmpaddr28_wdata (rvfi_csr_pmpaddr28_wdata) `define rvformal_csr_pmpaddr28_channel_conn(_idx), \ .rvfi_csr_pmpaddr28_rmask (rvfi_csr_pmpaddr28_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr28_wmask (rvfi_csr_pmpaddr28_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr28_rdata (rvfi_csr_pmpaddr28_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr28_wdata (rvfi_csr_pmpaddr28_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr28_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr28_rmask = rvfi_csr_pmpaddr28_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr28_wmask = rvfi_csr_pmpaddr28_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr28_rdata = rvfi_csr_pmpaddr28_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr28_wdata = rvfi_csr_pmpaddr28_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr28_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr28_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr28_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr28_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr28_wdata) `else `define rvformal_csr_pmpaddr28_wires `define rvformal_csr_pmpaddr28_outputs `define rvformal_csr_pmpaddr28_inputs `define rvformal_csr_pmpaddr28_conn `define rvformal_csr_pmpaddr28_channel(_idx) `endif `define rvformal_csr_pmpaddr28_indices \ localparam [11:0] csr_mindex_pmpaddr28 = 12'h3CC; \ localparam [11:0] csr_sindex_pmpaddr28 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr28 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR29 `define rvformal_csr_pmpaddr29_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wdata; `define rvformal_csr_pmpaddr29_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wdata `define rvformal_csr_pmpaddr29_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wdata `define rvformal_csr_pmpaddr29_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wdata `define rvformal_csr_pmpaddr29_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wdata `define rvformal_csr_pmpaddr29_conn, \ .rvfi_csr_pmpaddr29_rmask (rvfi_csr_pmpaddr29_rmask), \ .rvfi_csr_pmpaddr29_wmask (rvfi_csr_pmpaddr29_wmask), \ .rvfi_csr_pmpaddr29_rdata (rvfi_csr_pmpaddr29_rdata), \ .rvfi_csr_pmpaddr29_wdata (rvfi_csr_pmpaddr29_wdata) `define rvformal_csr_pmpaddr29_channel_conn(_idx), \ .rvfi_csr_pmpaddr29_rmask (rvfi_csr_pmpaddr29_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr29_wmask (rvfi_csr_pmpaddr29_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr29_rdata (rvfi_csr_pmpaddr29_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr29_wdata (rvfi_csr_pmpaddr29_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr29_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr29_rmask = rvfi_csr_pmpaddr29_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr29_wmask = rvfi_csr_pmpaddr29_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr29_rdata = rvfi_csr_pmpaddr29_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr29_wdata = rvfi_csr_pmpaddr29_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr29_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr29_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr29_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr29_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr29_wdata) `else `define rvformal_csr_pmpaddr29_wires `define rvformal_csr_pmpaddr29_outputs `define rvformal_csr_pmpaddr29_inputs `define rvformal_csr_pmpaddr29_conn `define rvformal_csr_pmpaddr29_channel(_idx) `endif `define rvformal_csr_pmpaddr29_indices \ localparam [11:0] csr_mindex_pmpaddr29 = 12'h3CD; \ localparam [11:0] csr_sindex_pmpaddr29 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr29 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR30 `define rvformal_csr_pmpaddr30_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wdata; `define rvformal_csr_pmpaddr30_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wdata `define rvformal_csr_pmpaddr30_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wdata `define rvformal_csr_pmpaddr30_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wdata `define rvformal_csr_pmpaddr30_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wdata `define rvformal_csr_pmpaddr30_conn, \ .rvfi_csr_pmpaddr30_rmask (rvfi_csr_pmpaddr30_rmask), \ .rvfi_csr_pmpaddr30_wmask (rvfi_csr_pmpaddr30_wmask), \ .rvfi_csr_pmpaddr30_rdata (rvfi_csr_pmpaddr30_rdata), \ .rvfi_csr_pmpaddr30_wdata (rvfi_csr_pmpaddr30_wdata) `define rvformal_csr_pmpaddr30_channel_conn(_idx), \ .rvfi_csr_pmpaddr30_rmask (rvfi_csr_pmpaddr30_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr30_wmask (rvfi_csr_pmpaddr30_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr30_rdata (rvfi_csr_pmpaddr30_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr30_wdata (rvfi_csr_pmpaddr30_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr30_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr30_rmask = rvfi_csr_pmpaddr30_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr30_wmask = rvfi_csr_pmpaddr30_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr30_rdata = rvfi_csr_pmpaddr30_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr30_wdata = rvfi_csr_pmpaddr30_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr30_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr30_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr30_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr30_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr30_wdata) `else `define rvformal_csr_pmpaddr30_wires `define rvformal_csr_pmpaddr30_outputs `define rvformal_csr_pmpaddr30_inputs `define rvformal_csr_pmpaddr30_conn `define rvformal_csr_pmpaddr30_channel(_idx) `endif `define rvformal_csr_pmpaddr30_indices \ localparam [11:0] csr_mindex_pmpaddr30 = 12'h3CE; \ localparam [11:0] csr_sindex_pmpaddr30 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr30 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR31 `define rvformal_csr_pmpaddr31_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wdata; `define rvformal_csr_pmpaddr31_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wdata `define rvformal_csr_pmpaddr31_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wdata `define rvformal_csr_pmpaddr31_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wdata `define rvformal_csr_pmpaddr31_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wdata `define rvformal_csr_pmpaddr31_conn, \ .rvfi_csr_pmpaddr31_rmask (rvfi_csr_pmpaddr31_rmask), \ .rvfi_csr_pmpaddr31_wmask (rvfi_csr_pmpaddr31_wmask), \ .rvfi_csr_pmpaddr31_rdata (rvfi_csr_pmpaddr31_rdata), \ .rvfi_csr_pmpaddr31_wdata (rvfi_csr_pmpaddr31_wdata) `define rvformal_csr_pmpaddr31_channel_conn(_idx), \ .rvfi_csr_pmpaddr31_rmask (rvfi_csr_pmpaddr31_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr31_wmask (rvfi_csr_pmpaddr31_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr31_rdata (rvfi_csr_pmpaddr31_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr31_wdata (rvfi_csr_pmpaddr31_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr31_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr31_rmask = rvfi_csr_pmpaddr31_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr31_wmask = rvfi_csr_pmpaddr31_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr31_rdata = rvfi_csr_pmpaddr31_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr31_wdata = rvfi_csr_pmpaddr31_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr31_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr31_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr31_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr31_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr31_wdata) `else `define rvformal_csr_pmpaddr31_wires `define rvformal_csr_pmpaddr31_outputs `define rvformal_csr_pmpaddr31_inputs `define rvformal_csr_pmpaddr31_conn `define rvformal_csr_pmpaddr31_channel(_idx) `endif `define rvformal_csr_pmpaddr31_indices \ localparam [11:0] csr_mindex_pmpaddr31 = 12'h3CF; \ localparam [11:0] csr_sindex_pmpaddr31 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr31 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR32 `define rvformal_csr_pmpaddr32_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wdata; `define rvformal_csr_pmpaddr32_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wdata `define rvformal_csr_pmpaddr32_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wdata `define rvformal_csr_pmpaddr32_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wdata `define rvformal_csr_pmpaddr32_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wdata `define rvformal_csr_pmpaddr32_conn, \ .rvfi_csr_pmpaddr32_rmask (rvfi_csr_pmpaddr32_rmask), \ .rvfi_csr_pmpaddr32_wmask (rvfi_csr_pmpaddr32_wmask), \ .rvfi_csr_pmpaddr32_rdata (rvfi_csr_pmpaddr32_rdata), \ .rvfi_csr_pmpaddr32_wdata (rvfi_csr_pmpaddr32_wdata) `define rvformal_csr_pmpaddr32_channel_conn(_idx), \ .rvfi_csr_pmpaddr32_rmask (rvfi_csr_pmpaddr32_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr32_wmask (rvfi_csr_pmpaddr32_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr32_rdata (rvfi_csr_pmpaddr32_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr32_wdata (rvfi_csr_pmpaddr32_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr32_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr32_rmask = rvfi_csr_pmpaddr32_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr32_wmask = rvfi_csr_pmpaddr32_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr32_rdata = rvfi_csr_pmpaddr32_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr32_wdata = rvfi_csr_pmpaddr32_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr32_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr32_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr32_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr32_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr32_wdata) `else `define rvformal_csr_pmpaddr32_wires `define rvformal_csr_pmpaddr32_outputs `define rvformal_csr_pmpaddr32_inputs `define rvformal_csr_pmpaddr32_conn `define rvformal_csr_pmpaddr32_channel(_idx) `endif `define rvformal_csr_pmpaddr32_indices \ localparam [11:0] csr_mindex_pmpaddr32 = 12'h3D0; \ localparam [11:0] csr_sindex_pmpaddr32 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr32 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR33 `define rvformal_csr_pmpaddr33_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wdata; `define rvformal_csr_pmpaddr33_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wdata `define rvformal_csr_pmpaddr33_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wdata `define rvformal_csr_pmpaddr33_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wdata `define rvformal_csr_pmpaddr33_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wdata `define rvformal_csr_pmpaddr33_conn, \ .rvfi_csr_pmpaddr33_rmask (rvfi_csr_pmpaddr33_rmask), \ .rvfi_csr_pmpaddr33_wmask (rvfi_csr_pmpaddr33_wmask), \ .rvfi_csr_pmpaddr33_rdata (rvfi_csr_pmpaddr33_rdata), \ .rvfi_csr_pmpaddr33_wdata (rvfi_csr_pmpaddr33_wdata) `define rvformal_csr_pmpaddr33_channel_conn(_idx), \ .rvfi_csr_pmpaddr33_rmask (rvfi_csr_pmpaddr33_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr33_wmask (rvfi_csr_pmpaddr33_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr33_rdata (rvfi_csr_pmpaddr33_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr33_wdata (rvfi_csr_pmpaddr33_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr33_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr33_rmask = rvfi_csr_pmpaddr33_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr33_wmask = rvfi_csr_pmpaddr33_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr33_rdata = rvfi_csr_pmpaddr33_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr33_wdata = rvfi_csr_pmpaddr33_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr33_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr33_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr33_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr33_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr33_wdata) `else `define rvformal_csr_pmpaddr33_wires `define rvformal_csr_pmpaddr33_outputs `define rvformal_csr_pmpaddr33_inputs `define rvformal_csr_pmpaddr33_conn `define rvformal_csr_pmpaddr33_channel(_idx) `endif `define rvformal_csr_pmpaddr33_indices \ localparam [11:0] csr_mindex_pmpaddr33 = 12'h3D1; \ localparam [11:0] csr_sindex_pmpaddr33 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr33 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR34 `define rvformal_csr_pmpaddr34_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wdata; `define rvformal_csr_pmpaddr34_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wdata `define rvformal_csr_pmpaddr34_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wdata `define rvformal_csr_pmpaddr34_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wdata `define rvformal_csr_pmpaddr34_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wdata `define rvformal_csr_pmpaddr34_conn, \ .rvfi_csr_pmpaddr34_rmask (rvfi_csr_pmpaddr34_rmask), \ .rvfi_csr_pmpaddr34_wmask (rvfi_csr_pmpaddr34_wmask), \ .rvfi_csr_pmpaddr34_rdata (rvfi_csr_pmpaddr34_rdata), \ .rvfi_csr_pmpaddr34_wdata (rvfi_csr_pmpaddr34_wdata) `define rvformal_csr_pmpaddr34_channel_conn(_idx), \ .rvfi_csr_pmpaddr34_rmask (rvfi_csr_pmpaddr34_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr34_wmask (rvfi_csr_pmpaddr34_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr34_rdata (rvfi_csr_pmpaddr34_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr34_wdata (rvfi_csr_pmpaddr34_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr34_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr34_rmask = rvfi_csr_pmpaddr34_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr34_wmask = rvfi_csr_pmpaddr34_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr34_rdata = rvfi_csr_pmpaddr34_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr34_wdata = rvfi_csr_pmpaddr34_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr34_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr34_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr34_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr34_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr34_wdata) `else `define rvformal_csr_pmpaddr34_wires `define rvformal_csr_pmpaddr34_outputs `define rvformal_csr_pmpaddr34_inputs `define rvformal_csr_pmpaddr34_conn `define rvformal_csr_pmpaddr34_channel(_idx) `endif `define rvformal_csr_pmpaddr34_indices \ localparam [11:0] csr_mindex_pmpaddr34 = 12'h3D2; \ localparam [11:0] csr_sindex_pmpaddr34 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr34 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR35 `define rvformal_csr_pmpaddr35_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wdata; `define rvformal_csr_pmpaddr35_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wdata `define rvformal_csr_pmpaddr35_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wdata `define rvformal_csr_pmpaddr35_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wdata `define rvformal_csr_pmpaddr35_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wdata `define rvformal_csr_pmpaddr35_conn, \ .rvfi_csr_pmpaddr35_rmask (rvfi_csr_pmpaddr35_rmask), \ .rvfi_csr_pmpaddr35_wmask (rvfi_csr_pmpaddr35_wmask), \ .rvfi_csr_pmpaddr35_rdata (rvfi_csr_pmpaddr35_rdata), \ .rvfi_csr_pmpaddr35_wdata (rvfi_csr_pmpaddr35_wdata) `define rvformal_csr_pmpaddr35_channel_conn(_idx), \ .rvfi_csr_pmpaddr35_rmask (rvfi_csr_pmpaddr35_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr35_wmask (rvfi_csr_pmpaddr35_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr35_rdata (rvfi_csr_pmpaddr35_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr35_wdata (rvfi_csr_pmpaddr35_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr35_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr35_rmask = rvfi_csr_pmpaddr35_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr35_wmask = rvfi_csr_pmpaddr35_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr35_rdata = rvfi_csr_pmpaddr35_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr35_wdata = rvfi_csr_pmpaddr35_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr35_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr35_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr35_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr35_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr35_wdata) `else `define rvformal_csr_pmpaddr35_wires `define rvformal_csr_pmpaddr35_outputs `define rvformal_csr_pmpaddr35_inputs `define rvformal_csr_pmpaddr35_conn `define rvformal_csr_pmpaddr35_channel(_idx) `endif `define rvformal_csr_pmpaddr35_indices \ localparam [11:0] csr_mindex_pmpaddr35 = 12'h3D3; \ localparam [11:0] csr_sindex_pmpaddr35 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr35 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR36 `define rvformal_csr_pmpaddr36_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wdata; `define rvformal_csr_pmpaddr36_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wdata `define rvformal_csr_pmpaddr36_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wdata `define rvformal_csr_pmpaddr36_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wdata `define rvformal_csr_pmpaddr36_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wdata `define rvformal_csr_pmpaddr36_conn, \ .rvfi_csr_pmpaddr36_rmask (rvfi_csr_pmpaddr36_rmask), \ .rvfi_csr_pmpaddr36_wmask (rvfi_csr_pmpaddr36_wmask), \ .rvfi_csr_pmpaddr36_rdata (rvfi_csr_pmpaddr36_rdata), \ .rvfi_csr_pmpaddr36_wdata (rvfi_csr_pmpaddr36_wdata) `define rvformal_csr_pmpaddr36_channel_conn(_idx), \ .rvfi_csr_pmpaddr36_rmask (rvfi_csr_pmpaddr36_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr36_wmask (rvfi_csr_pmpaddr36_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr36_rdata (rvfi_csr_pmpaddr36_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr36_wdata (rvfi_csr_pmpaddr36_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr36_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr36_rmask = rvfi_csr_pmpaddr36_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr36_wmask = rvfi_csr_pmpaddr36_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr36_rdata = rvfi_csr_pmpaddr36_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr36_wdata = rvfi_csr_pmpaddr36_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr36_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr36_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr36_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr36_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr36_wdata) `else `define rvformal_csr_pmpaddr36_wires `define rvformal_csr_pmpaddr36_outputs `define rvformal_csr_pmpaddr36_inputs `define rvformal_csr_pmpaddr36_conn `define rvformal_csr_pmpaddr36_channel(_idx) `endif `define rvformal_csr_pmpaddr36_indices \ localparam [11:0] csr_mindex_pmpaddr36 = 12'h3D4; \ localparam [11:0] csr_sindex_pmpaddr36 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr36 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR37 `define rvformal_csr_pmpaddr37_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wdata; `define rvformal_csr_pmpaddr37_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wdata `define rvformal_csr_pmpaddr37_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wdata `define rvformal_csr_pmpaddr37_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wdata `define rvformal_csr_pmpaddr37_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wdata `define rvformal_csr_pmpaddr37_conn, \ .rvfi_csr_pmpaddr37_rmask (rvfi_csr_pmpaddr37_rmask), \ .rvfi_csr_pmpaddr37_wmask (rvfi_csr_pmpaddr37_wmask), \ .rvfi_csr_pmpaddr37_rdata (rvfi_csr_pmpaddr37_rdata), \ .rvfi_csr_pmpaddr37_wdata (rvfi_csr_pmpaddr37_wdata) `define rvformal_csr_pmpaddr37_channel_conn(_idx), \ .rvfi_csr_pmpaddr37_rmask (rvfi_csr_pmpaddr37_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr37_wmask (rvfi_csr_pmpaddr37_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr37_rdata (rvfi_csr_pmpaddr37_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr37_wdata (rvfi_csr_pmpaddr37_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr37_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr37_rmask = rvfi_csr_pmpaddr37_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr37_wmask = rvfi_csr_pmpaddr37_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr37_rdata = rvfi_csr_pmpaddr37_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr37_wdata = rvfi_csr_pmpaddr37_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr37_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr37_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr37_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr37_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr37_wdata) `else `define rvformal_csr_pmpaddr37_wires `define rvformal_csr_pmpaddr37_outputs `define rvformal_csr_pmpaddr37_inputs `define rvformal_csr_pmpaddr37_conn `define rvformal_csr_pmpaddr37_channel(_idx) `endif `define rvformal_csr_pmpaddr37_indices \ localparam [11:0] csr_mindex_pmpaddr37 = 12'h3D5; \ localparam [11:0] csr_sindex_pmpaddr37 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr37 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR38 `define rvformal_csr_pmpaddr38_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wdata; `define rvformal_csr_pmpaddr38_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wdata `define rvformal_csr_pmpaddr38_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wdata `define rvformal_csr_pmpaddr38_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wdata `define rvformal_csr_pmpaddr38_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wdata `define rvformal_csr_pmpaddr38_conn, \ .rvfi_csr_pmpaddr38_rmask (rvfi_csr_pmpaddr38_rmask), \ .rvfi_csr_pmpaddr38_wmask (rvfi_csr_pmpaddr38_wmask), \ .rvfi_csr_pmpaddr38_rdata (rvfi_csr_pmpaddr38_rdata), \ .rvfi_csr_pmpaddr38_wdata (rvfi_csr_pmpaddr38_wdata) `define rvformal_csr_pmpaddr38_channel_conn(_idx), \ .rvfi_csr_pmpaddr38_rmask (rvfi_csr_pmpaddr38_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr38_wmask (rvfi_csr_pmpaddr38_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr38_rdata (rvfi_csr_pmpaddr38_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr38_wdata (rvfi_csr_pmpaddr38_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr38_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr38_rmask = rvfi_csr_pmpaddr38_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr38_wmask = rvfi_csr_pmpaddr38_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr38_rdata = rvfi_csr_pmpaddr38_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr38_wdata = rvfi_csr_pmpaddr38_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr38_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr38_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr38_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr38_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr38_wdata) `else `define rvformal_csr_pmpaddr38_wires `define rvformal_csr_pmpaddr38_outputs `define rvformal_csr_pmpaddr38_inputs `define rvformal_csr_pmpaddr38_conn `define rvformal_csr_pmpaddr38_channel(_idx) `endif `define rvformal_csr_pmpaddr38_indices \ localparam [11:0] csr_mindex_pmpaddr38 = 12'h3D6; \ localparam [11:0] csr_sindex_pmpaddr38 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr38 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR39 `define rvformal_csr_pmpaddr39_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wdata; `define rvformal_csr_pmpaddr39_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wdata `define rvformal_csr_pmpaddr39_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wdata `define rvformal_csr_pmpaddr39_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wdata `define rvformal_csr_pmpaddr39_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wdata `define rvformal_csr_pmpaddr39_conn, \ .rvfi_csr_pmpaddr39_rmask (rvfi_csr_pmpaddr39_rmask), \ .rvfi_csr_pmpaddr39_wmask (rvfi_csr_pmpaddr39_wmask), \ .rvfi_csr_pmpaddr39_rdata (rvfi_csr_pmpaddr39_rdata), \ .rvfi_csr_pmpaddr39_wdata (rvfi_csr_pmpaddr39_wdata) `define rvformal_csr_pmpaddr39_channel_conn(_idx), \ .rvfi_csr_pmpaddr39_rmask (rvfi_csr_pmpaddr39_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr39_wmask (rvfi_csr_pmpaddr39_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr39_rdata (rvfi_csr_pmpaddr39_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr39_wdata (rvfi_csr_pmpaddr39_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr39_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr39_rmask = rvfi_csr_pmpaddr39_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr39_wmask = rvfi_csr_pmpaddr39_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr39_rdata = rvfi_csr_pmpaddr39_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr39_wdata = rvfi_csr_pmpaddr39_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr39_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr39_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr39_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr39_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr39_wdata) `else `define rvformal_csr_pmpaddr39_wires `define rvformal_csr_pmpaddr39_outputs `define rvformal_csr_pmpaddr39_inputs `define rvformal_csr_pmpaddr39_conn `define rvformal_csr_pmpaddr39_channel(_idx) `endif `define rvformal_csr_pmpaddr39_indices \ localparam [11:0] csr_mindex_pmpaddr39 = 12'h3D7; \ localparam [11:0] csr_sindex_pmpaddr39 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr39 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR40 `define rvformal_csr_pmpaddr40_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wdata; `define rvformal_csr_pmpaddr40_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wdata `define rvformal_csr_pmpaddr40_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wdata `define rvformal_csr_pmpaddr40_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wdata `define rvformal_csr_pmpaddr40_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wdata `define rvformal_csr_pmpaddr40_conn, \ .rvfi_csr_pmpaddr40_rmask (rvfi_csr_pmpaddr40_rmask), \ .rvfi_csr_pmpaddr40_wmask (rvfi_csr_pmpaddr40_wmask), \ .rvfi_csr_pmpaddr40_rdata (rvfi_csr_pmpaddr40_rdata), \ .rvfi_csr_pmpaddr40_wdata (rvfi_csr_pmpaddr40_wdata) `define rvformal_csr_pmpaddr40_channel_conn(_idx), \ .rvfi_csr_pmpaddr40_rmask (rvfi_csr_pmpaddr40_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr40_wmask (rvfi_csr_pmpaddr40_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr40_rdata (rvfi_csr_pmpaddr40_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr40_wdata (rvfi_csr_pmpaddr40_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr40_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr40_rmask = rvfi_csr_pmpaddr40_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr40_wmask = rvfi_csr_pmpaddr40_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr40_rdata = rvfi_csr_pmpaddr40_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr40_wdata = rvfi_csr_pmpaddr40_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr40_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr40_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr40_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr40_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr40_wdata) `else `define rvformal_csr_pmpaddr40_wires `define rvformal_csr_pmpaddr40_outputs `define rvformal_csr_pmpaddr40_inputs `define rvformal_csr_pmpaddr40_conn `define rvformal_csr_pmpaddr40_channel(_idx) `endif `define rvformal_csr_pmpaddr40_indices \ localparam [11:0] csr_mindex_pmpaddr40 = 12'h3D8; \ localparam [11:0] csr_sindex_pmpaddr40 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr40 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR41 `define rvformal_csr_pmpaddr41_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wdata; `define rvformal_csr_pmpaddr41_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wdata `define rvformal_csr_pmpaddr41_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wdata `define rvformal_csr_pmpaddr41_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wdata `define rvformal_csr_pmpaddr41_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wdata `define rvformal_csr_pmpaddr41_conn, \ .rvfi_csr_pmpaddr41_rmask (rvfi_csr_pmpaddr41_rmask), \ .rvfi_csr_pmpaddr41_wmask (rvfi_csr_pmpaddr41_wmask), \ .rvfi_csr_pmpaddr41_rdata (rvfi_csr_pmpaddr41_rdata), \ .rvfi_csr_pmpaddr41_wdata (rvfi_csr_pmpaddr41_wdata) `define rvformal_csr_pmpaddr41_channel_conn(_idx), \ .rvfi_csr_pmpaddr41_rmask (rvfi_csr_pmpaddr41_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr41_wmask (rvfi_csr_pmpaddr41_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr41_rdata (rvfi_csr_pmpaddr41_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr41_wdata (rvfi_csr_pmpaddr41_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr41_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr41_rmask = rvfi_csr_pmpaddr41_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr41_wmask = rvfi_csr_pmpaddr41_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr41_rdata = rvfi_csr_pmpaddr41_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr41_wdata = rvfi_csr_pmpaddr41_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr41_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr41_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr41_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr41_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr41_wdata) `else `define rvformal_csr_pmpaddr41_wires `define rvformal_csr_pmpaddr41_outputs `define rvformal_csr_pmpaddr41_inputs `define rvformal_csr_pmpaddr41_conn `define rvformal_csr_pmpaddr41_channel(_idx) `endif `define rvformal_csr_pmpaddr41_indices \ localparam [11:0] csr_mindex_pmpaddr41 = 12'h3D9; \ localparam [11:0] csr_sindex_pmpaddr41 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr41 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR42 `define rvformal_csr_pmpaddr42_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wdata; `define rvformal_csr_pmpaddr42_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wdata `define rvformal_csr_pmpaddr42_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wdata `define rvformal_csr_pmpaddr42_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wdata `define rvformal_csr_pmpaddr42_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wdata `define rvformal_csr_pmpaddr42_conn, \ .rvfi_csr_pmpaddr42_rmask (rvfi_csr_pmpaddr42_rmask), \ .rvfi_csr_pmpaddr42_wmask (rvfi_csr_pmpaddr42_wmask), \ .rvfi_csr_pmpaddr42_rdata (rvfi_csr_pmpaddr42_rdata), \ .rvfi_csr_pmpaddr42_wdata (rvfi_csr_pmpaddr42_wdata) `define rvformal_csr_pmpaddr42_channel_conn(_idx), \ .rvfi_csr_pmpaddr42_rmask (rvfi_csr_pmpaddr42_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr42_wmask (rvfi_csr_pmpaddr42_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr42_rdata (rvfi_csr_pmpaddr42_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr42_wdata (rvfi_csr_pmpaddr42_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr42_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr42_rmask = rvfi_csr_pmpaddr42_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr42_wmask = rvfi_csr_pmpaddr42_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr42_rdata = rvfi_csr_pmpaddr42_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr42_wdata = rvfi_csr_pmpaddr42_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr42_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr42_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr42_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr42_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr42_wdata) `else `define rvformal_csr_pmpaddr42_wires `define rvformal_csr_pmpaddr42_outputs `define rvformal_csr_pmpaddr42_inputs `define rvformal_csr_pmpaddr42_conn `define rvformal_csr_pmpaddr42_channel(_idx) `endif `define rvformal_csr_pmpaddr42_indices \ localparam [11:0] csr_mindex_pmpaddr42 = 12'h3DA; \ localparam [11:0] csr_sindex_pmpaddr42 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr42 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR43 `define rvformal_csr_pmpaddr43_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wdata; `define rvformal_csr_pmpaddr43_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wdata `define rvformal_csr_pmpaddr43_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wdata `define rvformal_csr_pmpaddr43_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wdata `define rvformal_csr_pmpaddr43_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wdata `define rvformal_csr_pmpaddr43_conn, \ .rvfi_csr_pmpaddr43_rmask (rvfi_csr_pmpaddr43_rmask), \ .rvfi_csr_pmpaddr43_wmask (rvfi_csr_pmpaddr43_wmask), \ .rvfi_csr_pmpaddr43_rdata (rvfi_csr_pmpaddr43_rdata), \ .rvfi_csr_pmpaddr43_wdata (rvfi_csr_pmpaddr43_wdata) `define rvformal_csr_pmpaddr43_channel_conn(_idx), \ .rvfi_csr_pmpaddr43_rmask (rvfi_csr_pmpaddr43_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr43_wmask (rvfi_csr_pmpaddr43_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr43_rdata (rvfi_csr_pmpaddr43_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr43_wdata (rvfi_csr_pmpaddr43_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr43_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr43_rmask = rvfi_csr_pmpaddr43_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr43_wmask = rvfi_csr_pmpaddr43_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr43_rdata = rvfi_csr_pmpaddr43_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr43_wdata = rvfi_csr_pmpaddr43_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr43_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr43_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr43_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr43_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr43_wdata) `else `define rvformal_csr_pmpaddr43_wires `define rvformal_csr_pmpaddr43_outputs `define rvformal_csr_pmpaddr43_inputs `define rvformal_csr_pmpaddr43_conn `define rvformal_csr_pmpaddr43_channel(_idx) `endif `define rvformal_csr_pmpaddr43_indices \ localparam [11:0] csr_mindex_pmpaddr43 = 12'h3DB; \ localparam [11:0] csr_sindex_pmpaddr43 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr43 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR44 `define rvformal_csr_pmpaddr44_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wdata; `define rvformal_csr_pmpaddr44_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wdata `define rvformal_csr_pmpaddr44_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wdata `define rvformal_csr_pmpaddr44_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wdata `define rvformal_csr_pmpaddr44_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wdata `define rvformal_csr_pmpaddr44_conn, \ .rvfi_csr_pmpaddr44_rmask (rvfi_csr_pmpaddr44_rmask), \ .rvfi_csr_pmpaddr44_wmask (rvfi_csr_pmpaddr44_wmask), \ .rvfi_csr_pmpaddr44_rdata (rvfi_csr_pmpaddr44_rdata), \ .rvfi_csr_pmpaddr44_wdata (rvfi_csr_pmpaddr44_wdata) `define rvformal_csr_pmpaddr44_channel_conn(_idx), \ .rvfi_csr_pmpaddr44_rmask (rvfi_csr_pmpaddr44_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr44_wmask (rvfi_csr_pmpaddr44_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr44_rdata (rvfi_csr_pmpaddr44_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr44_wdata (rvfi_csr_pmpaddr44_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr44_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr44_rmask = rvfi_csr_pmpaddr44_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr44_wmask = rvfi_csr_pmpaddr44_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr44_rdata = rvfi_csr_pmpaddr44_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr44_wdata = rvfi_csr_pmpaddr44_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr44_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr44_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr44_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr44_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr44_wdata) `else `define rvformal_csr_pmpaddr44_wires `define rvformal_csr_pmpaddr44_outputs `define rvformal_csr_pmpaddr44_inputs `define rvformal_csr_pmpaddr44_conn `define rvformal_csr_pmpaddr44_channel(_idx) `endif `define rvformal_csr_pmpaddr44_indices \ localparam [11:0] csr_mindex_pmpaddr44 = 12'h3DC; \ localparam [11:0] csr_sindex_pmpaddr44 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr44 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR45 `define rvformal_csr_pmpaddr45_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wdata; `define rvformal_csr_pmpaddr45_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wdata `define rvformal_csr_pmpaddr45_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wdata `define rvformal_csr_pmpaddr45_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wdata `define rvformal_csr_pmpaddr45_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wdata `define rvformal_csr_pmpaddr45_conn, \ .rvfi_csr_pmpaddr45_rmask (rvfi_csr_pmpaddr45_rmask), \ .rvfi_csr_pmpaddr45_wmask (rvfi_csr_pmpaddr45_wmask), \ .rvfi_csr_pmpaddr45_rdata (rvfi_csr_pmpaddr45_rdata), \ .rvfi_csr_pmpaddr45_wdata (rvfi_csr_pmpaddr45_wdata) `define rvformal_csr_pmpaddr45_channel_conn(_idx), \ .rvfi_csr_pmpaddr45_rmask (rvfi_csr_pmpaddr45_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr45_wmask (rvfi_csr_pmpaddr45_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr45_rdata (rvfi_csr_pmpaddr45_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr45_wdata (rvfi_csr_pmpaddr45_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr45_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr45_rmask = rvfi_csr_pmpaddr45_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr45_wmask = rvfi_csr_pmpaddr45_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr45_rdata = rvfi_csr_pmpaddr45_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr45_wdata = rvfi_csr_pmpaddr45_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr45_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr45_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr45_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr45_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr45_wdata) `else `define rvformal_csr_pmpaddr45_wires `define rvformal_csr_pmpaddr45_outputs `define rvformal_csr_pmpaddr45_inputs `define rvformal_csr_pmpaddr45_conn `define rvformal_csr_pmpaddr45_channel(_idx) `endif `define rvformal_csr_pmpaddr45_indices \ localparam [11:0] csr_mindex_pmpaddr45 = 12'h3DD; \ localparam [11:0] csr_sindex_pmpaddr45 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr45 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR46 `define rvformal_csr_pmpaddr46_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wdata; `define rvformal_csr_pmpaddr46_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wdata `define rvformal_csr_pmpaddr46_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wdata `define rvformal_csr_pmpaddr46_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wdata `define rvformal_csr_pmpaddr46_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wdata `define rvformal_csr_pmpaddr46_conn, \ .rvfi_csr_pmpaddr46_rmask (rvfi_csr_pmpaddr46_rmask), \ .rvfi_csr_pmpaddr46_wmask (rvfi_csr_pmpaddr46_wmask), \ .rvfi_csr_pmpaddr46_rdata (rvfi_csr_pmpaddr46_rdata), \ .rvfi_csr_pmpaddr46_wdata (rvfi_csr_pmpaddr46_wdata) `define rvformal_csr_pmpaddr46_channel_conn(_idx), \ .rvfi_csr_pmpaddr46_rmask (rvfi_csr_pmpaddr46_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr46_wmask (rvfi_csr_pmpaddr46_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr46_rdata (rvfi_csr_pmpaddr46_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr46_wdata (rvfi_csr_pmpaddr46_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr46_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr46_rmask = rvfi_csr_pmpaddr46_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr46_wmask = rvfi_csr_pmpaddr46_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr46_rdata = rvfi_csr_pmpaddr46_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr46_wdata = rvfi_csr_pmpaddr46_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr46_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr46_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr46_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr46_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr46_wdata) `else `define rvformal_csr_pmpaddr46_wires `define rvformal_csr_pmpaddr46_outputs `define rvformal_csr_pmpaddr46_inputs `define rvformal_csr_pmpaddr46_conn `define rvformal_csr_pmpaddr46_channel(_idx) `endif `define rvformal_csr_pmpaddr46_indices \ localparam [11:0] csr_mindex_pmpaddr46 = 12'h3DE; \ localparam [11:0] csr_sindex_pmpaddr46 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr46 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR47 `define rvformal_csr_pmpaddr47_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wdata; `define rvformal_csr_pmpaddr47_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wdata `define rvformal_csr_pmpaddr47_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wdata `define rvformal_csr_pmpaddr47_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wdata `define rvformal_csr_pmpaddr47_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wdata `define rvformal_csr_pmpaddr47_conn, \ .rvfi_csr_pmpaddr47_rmask (rvfi_csr_pmpaddr47_rmask), \ .rvfi_csr_pmpaddr47_wmask (rvfi_csr_pmpaddr47_wmask), \ .rvfi_csr_pmpaddr47_rdata (rvfi_csr_pmpaddr47_rdata), \ .rvfi_csr_pmpaddr47_wdata (rvfi_csr_pmpaddr47_wdata) `define rvformal_csr_pmpaddr47_channel_conn(_idx), \ .rvfi_csr_pmpaddr47_rmask (rvfi_csr_pmpaddr47_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr47_wmask (rvfi_csr_pmpaddr47_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr47_rdata (rvfi_csr_pmpaddr47_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr47_wdata (rvfi_csr_pmpaddr47_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr47_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr47_rmask = rvfi_csr_pmpaddr47_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr47_wmask = rvfi_csr_pmpaddr47_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr47_rdata = rvfi_csr_pmpaddr47_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr47_wdata = rvfi_csr_pmpaddr47_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr47_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr47_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr47_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr47_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr47_wdata) `else `define rvformal_csr_pmpaddr47_wires `define rvformal_csr_pmpaddr47_outputs `define rvformal_csr_pmpaddr47_inputs `define rvformal_csr_pmpaddr47_conn `define rvformal_csr_pmpaddr47_channel(_idx) `endif `define rvformal_csr_pmpaddr47_indices \ localparam [11:0] csr_mindex_pmpaddr47 = 12'h3DF; \ localparam [11:0] csr_sindex_pmpaddr47 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr47 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR48 `define rvformal_csr_pmpaddr48_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wdata; `define rvformal_csr_pmpaddr48_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wdata `define rvformal_csr_pmpaddr48_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wdata `define rvformal_csr_pmpaddr48_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wdata `define rvformal_csr_pmpaddr48_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wdata `define rvformal_csr_pmpaddr48_conn, \ .rvfi_csr_pmpaddr48_rmask (rvfi_csr_pmpaddr48_rmask), \ .rvfi_csr_pmpaddr48_wmask (rvfi_csr_pmpaddr48_wmask), \ .rvfi_csr_pmpaddr48_rdata (rvfi_csr_pmpaddr48_rdata), \ .rvfi_csr_pmpaddr48_wdata (rvfi_csr_pmpaddr48_wdata) `define rvformal_csr_pmpaddr48_channel_conn(_idx), \ .rvfi_csr_pmpaddr48_rmask (rvfi_csr_pmpaddr48_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr48_wmask (rvfi_csr_pmpaddr48_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr48_rdata (rvfi_csr_pmpaddr48_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr48_wdata (rvfi_csr_pmpaddr48_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr48_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr48_rmask = rvfi_csr_pmpaddr48_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr48_wmask = rvfi_csr_pmpaddr48_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr48_rdata = rvfi_csr_pmpaddr48_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr48_wdata = rvfi_csr_pmpaddr48_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr48_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr48_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr48_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr48_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr48_wdata) `else `define rvformal_csr_pmpaddr48_wires `define rvformal_csr_pmpaddr48_outputs `define rvformal_csr_pmpaddr48_inputs `define rvformal_csr_pmpaddr48_conn `define rvformal_csr_pmpaddr48_channel(_idx) `endif `define rvformal_csr_pmpaddr48_indices \ localparam [11:0] csr_mindex_pmpaddr48 = 12'h3E0; \ localparam [11:0] csr_sindex_pmpaddr48 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr48 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR49 `define rvformal_csr_pmpaddr49_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wdata; `define rvformal_csr_pmpaddr49_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wdata `define rvformal_csr_pmpaddr49_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wdata `define rvformal_csr_pmpaddr49_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wdata `define rvformal_csr_pmpaddr49_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wdata `define rvformal_csr_pmpaddr49_conn, \ .rvfi_csr_pmpaddr49_rmask (rvfi_csr_pmpaddr49_rmask), \ .rvfi_csr_pmpaddr49_wmask (rvfi_csr_pmpaddr49_wmask), \ .rvfi_csr_pmpaddr49_rdata (rvfi_csr_pmpaddr49_rdata), \ .rvfi_csr_pmpaddr49_wdata (rvfi_csr_pmpaddr49_wdata) `define rvformal_csr_pmpaddr49_channel_conn(_idx), \ .rvfi_csr_pmpaddr49_rmask (rvfi_csr_pmpaddr49_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr49_wmask (rvfi_csr_pmpaddr49_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr49_rdata (rvfi_csr_pmpaddr49_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr49_wdata (rvfi_csr_pmpaddr49_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr49_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr49_rmask = rvfi_csr_pmpaddr49_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr49_wmask = rvfi_csr_pmpaddr49_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr49_rdata = rvfi_csr_pmpaddr49_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr49_wdata = rvfi_csr_pmpaddr49_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr49_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr49_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr49_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr49_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr49_wdata) `else `define rvformal_csr_pmpaddr49_wires `define rvformal_csr_pmpaddr49_outputs `define rvformal_csr_pmpaddr49_inputs `define rvformal_csr_pmpaddr49_conn `define rvformal_csr_pmpaddr49_channel(_idx) `endif `define rvformal_csr_pmpaddr49_indices \ localparam [11:0] csr_mindex_pmpaddr49 = 12'h3E1; \ localparam [11:0] csr_sindex_pmpaddr49 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr49 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR50 `define rvformal_csr_pmpaddr50_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wdata; `define rvformal_csr_pmpaddr50_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wdata `define rvformal_csr_pmpaddr50_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wdata `define rvformal_csr_pmpaddr50_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wdata `define rvformal_csr_pmpaddr50_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wdata `define rvformal_csr_pmpaddr50_conn, \ .rvfi_csr_pmpaddr50_rmask (rvfi_csr_pmpaddr50_rmask), \ .rvfi_csr_pmpaddr50_wmask (rvfi_csr_pmpaddr50_wmask), \ .rvfi_csr_pmpaddr50_rdata (rvfi_csr_pmpaddr50_rdata), \ .rvfi_csr_pmpaddr50_wdata (rvfi_csr_pmpaddr50_wdata) `define rvformal_csr_pmpaddr50_channel_conn(_idx), \ .rvfi_csr_pmpaddr50_rmask (rvfi_csr_pmpaddr50_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr50_wmask (rvfi_csr_pmpaddr50_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr50_rdata (rvfi_csr_pmpaddr50_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr50_wdata (rvfi_csr_pmpaddr50_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr50_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr50_rmask = rvfi_csr_pmpaddr50_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr50_wmask = rvfi_csr_pmpaddr50_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr50_rdata = rvfi_csr_pmpaddr50_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr50_wdata = rvfi_csr_pmpaddr50_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr50_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr50_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr50_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr50_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr50_wdata) `else `define rvformal_csr_pmpaddr50_wires `define rvformal_csr_pmpaddr50_outputs `define rvformal_csr_pmpaddr50_inputs `define rvformal_csr_pmpaddr50_conn `define rvformal_csr_pmpaddr50_channel(_idx) `endif `define rvformal_csr_pmpaddr50_indices \ localparam [11:0] csr_mindex_pmpaddr50 = 12'h3E2; \ localparam [11:0] csr_sindex_pmpaddr50 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr50 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR51 `define rvformal_csr_pmpaddr51_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wdata; `define rvformal_csr_pmpaddr51_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wdata `define rvformal_csr_pmpaddr51_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wdata `define rvformal_csr_pmpaddr51_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wdata `define rvformal_csr_pmpaddr51_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wdata `define rvformal_csr_pmpaddr51_conn, \ .rvfi_csr_pmpaddr51_rmask (rvfi_csr_pmpaddr51_rmask), \ .rvfi_csr_pmpaddr51_wmask (rvfi_csr_pmpaddr51_wmask), \ .rvfi_csr_pmpaddr51_rdata (rvfi_csr_pmpaddr51_rdata), \ .rvfi_csr_pmpaddr51_wdata (rvfi_csr_pmpaddr51_wdata) `define rvformal_csr_pmpaddr51_channel_conn(_idx), \ .rvfi_csr_pmpaddr51_rmask (rvfi_csr_pmpaddr51_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr51_wmask (rvfi_csr_pmpaddr51_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr51_rdata (rvfi_csr_pmpaddr51_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr51_wdata (rvfi_csr_pmpaddr51_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr51_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr51_rmask = rvfi_csr_pmpaddr51_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr51_wmask = rvfi_csr_pmpaddr51_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr51_rdata = rvfi_csr_pmpaddr51_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr51_wdata = rvfi_csr_pmpaddr51_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr51_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr51_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr51_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr51_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr51_wdata) `else `define rvformal_csr_pmpaddr51_wires `define rvformal_csr_pmpaddr51_outputs `define rvformal_csr_pmpaddr51_inputs `define rvformal_csr_pmpaddr51_conn `define rvformal_csr_pmpaddr51_channel(_idx) `endif `define rvformal_csr_pmpaddr51_indices \ localparam [11:0] csr_mindex_pmpaddr51 = 12'h3E3; \ localparam [11:0] csr_sindex_pmpaddr51 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr51 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR52 `define rvformal_csr_pmpaddr52_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wdata; `define rvformal_csr_pmpaddr52_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wdata `define rvformal_csr_pmpaddr52_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wdata `define rvformal_csr_pmpaddr52_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wdata `define rvformal_csr_pmpaddr52_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wdata `define rvformal_csr_pmpaddr52_conn, \ .rvfi_csr_pmpaddr52_rmask (rvfi_csr_pmpaddr52_rmask), \ .rvfi_csr_pmpaddr52_wmask (rvfi_csr_pmpaddr52_wmask), \ .rvfi_csr_pmpaddr52_rdata (rvfi_csr_pmpaddr52_rdata), \ .rvfi_csr_pmpaddr52_wdata (rvfi_csr_pmpaddr52_wdata) `define rvformal_csr_pmpaddr52_channel_conn(_idx), \ .rvfi_csr_pmpaddr52_rmask (rvfi_csr_pmpaddr52_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr52_wmask (rvfi_csr_pmpaddr52_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr52_rdata (rvfi_csr_pmpaddr52_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr52_wdata (rvfi_csr_pmpaddr52_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr52_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr52_rmask = rvfi_csr_pmpaddr52_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr52_wmask = rvfi_csr_pmpaddr52_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr52_rdata = rvfi_csr_pmpaddr52_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr52_wdata = rvfi_csr_pmpaddr52_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr52_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr52_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr52_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr52_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr52_wdata) `else `define rvformal_csr_pmpaddr52_wires `define rvformal_csr_pmpaddr52_outputs `define rvformal_csr_pmpaddr52_inputs `define rvformal_csr_pmpaddr52_conn `define rvformal_csr_pmpaddr52_channel(_idx) `endif `define rvformal_csr_pmpaddr52_indices \ localparam [11:0] csr_mindex_pmpaddr52 = 12'h3E4; \ localparam [11:0] csr_sindex_pmpaddr52 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr52 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR53 `define rvformal_csr_pmpaddr53_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wdata; `define rvformal_csr_pmpaddr53_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wdata `define rvformal_csr_pmpaddr53_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wdata `define rvformal_csr_pmpaddr53_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wdata `define rvformal_csr_pmpaddr53_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wdata `define rvformal_csr_pmpaddr53_conn, \ .rvfi_csr_pmpaddr53_rmask (rvfi_csr_pmpaddr53_rmask), \ .rvfi_csr_pmpaddr53_wmask (rvfi_csr_pmpaddr53_wmask), \ .rvfi_csr_pmpaddr53_rdata (rvfi_csr_pmpaddr53_rdata), \ .rvfi_csr_pmpaddr53_wdata (rvfi_csr_pmpaddr53_wdata) `define rvformal_csr_pmpaddr53_channel_conn(_idx), \ .rvfi_csr_pmpaddr53_rmask (rvfi_csr_pmpaddr53_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr53_wmask (rvfi_csr_pmpaddr53_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr53_rdata (rvfi_csr_pmpaddr53_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr53_wdata (rvfi_csr_pmpaddr53_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr53_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr53_rmask = rvfi_csr_pmpaddr53_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr53_wmask = rvfi_csr_pmpaddr53_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr53_rdata = rvfi_csr_pmpaddr53_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr53_wdata = rvfi_csr_pmpaddr53_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr53_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr53_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr53_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr53_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr53_wdata) `else `define rvformal_csr_pmpaddr53_wires `define rvformal_csr_pmpaddr53_outputs `define rvformal_csr_pmpaddr53_inputs `define rvformal_csr_pmpaddr53_conn `define rvformal_csr_pmpaddr53_channel(_idx) `endif `define rvformal_csr_pmpaddr53_indices \ localparam [11:0] csr_mindex_pmpaddr53 = 12'h3E5; \ localparam [11:0] csr_sindex_pmpaddr53 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr53 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR54 `define rvformal_csr_pmpaddr54_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wdata; `define rvformal_csr_pmpaddr54_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wdata `define rvformal_csr_pmpaddr54_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wdata `define rvformal_csr_pmpaddr54_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wdata `define rvformal_csr_pmpaddr54_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wdata `define rvformal_csr_pmpaddr54_conn, \ .rvfi_csr_pmpaddr54_rmask (rvfi_csr_pmpaddr54_rmask), \ .rvfi_csr_pmpaddr54_wmask (rvfi_csr_pmpaddr54_wmask), \ .rvfi_csr_pmpaddr54_rdata (rvfi_csr_pmpaddr54_rdata), \ .rvfi_csr_pmpaddr54_wdata (rvfi_csr_pmpaddr54_wdata) `define rvformal_csr_pmpaddr54_channel_conn(_idx), \ .rvfi_csr_pmpaddr54_rmask (rvfi_csr_pmpaddr54_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr54_wmask (rvfi_csr_pmpaddr54_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr54_rdata (rvfi_csr_pmpaddr54_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr54_wdata (rvfi_csr_pmpaddr54_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr54_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr54_rmask = rvfi_csr_pmpaddr54_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr54_wmask = rvfi_csr_pmpaddr54_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr54_rdata = rvfi_csr_pmpaddr54_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr54_wdata = rvfi_csr_pmpaddr54_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr54_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr54_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr54_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr54_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr54_wdata) `else `define rvformal_csr_pmpaddr54_wires `define rvformal_csr_pmpaddr54_outputs `define rvformal_csr_pmpaddr54_inputs `define rvformal_csr_pmpaddr54_conn `define rvformal_csr_pmpaddr54_channel(_idx) `endif `define rvformal_csr_pmpaddr54_indices \ localparam [11:0] csr_mindex_pmpaddr54 = 12'h3E6; \ localparam [11:0] csr_sindex_pmpaddr54 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr54 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR55 `define rvformal_csr_pmpaddr55_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wdata; `define rvformal_csr_pmpaddr55_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wdata `define rvformal_csr_pmpaddr55_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wdata `define rvformal_csr_pmpaddr55_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wdata `define rvformal_csr_pmpaddr55_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wdata `define rvformal_csr_pmpaddr55_conn, \ .rvfi_csr_pmpaddr55_rmask (rvfi_csr_pmpaddr55_rmask), \ .rvfi_csr_pmpaddr55_wmask (rvfi_csr_pmpaddr55_wmask), \ .rvfi_csr_pmpaddr55_rdata (rvfi_csr_pmpaddr55_rdata), \ .rvfi_csr_pmpaddr55_wdata (rvfi_csr_pmpaddr55_wdata) `define rvformal_csr_pmpaddr55_channel_conn(_idx), \ .rvfi_csr_pmpaddr55_rmask (rvfi_csr_pmpaddr55_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr55_wmask (rvfi_csr_pmpaddr55_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr55_rdata (rvfi_csr_pmpaddr55_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr55_wdata (rvfi_csr_pmpaddr55_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr55_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr55_rmask = rvfi_csr_pmpaddr55_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr55_wmask = rvfi_csr_pmpaddr55_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr55_rdata = rvfi_csr_pmpaddr55_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr55_wdata = rvfi_csr_pmpaddr55_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr55_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr55_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr55_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr55_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr55_wdata) `else `define rvformal_csr_pmpaddr55_wires `define rvformal_csr_pmpaddr55_outputs `define rvformal_csr_pmpaddr55_inputs `define rvformal_csr_pmpaddr55_conn `define rvformal_csr_pmpaddr55_channel(_idx) `endif `define rvformal_csr_pmpaddr55_indices \ localparam [11:0] csr_mindex_pmpaddr55 = 12'h3E7; \ localparam [11:0] csr_sindex_pmpaddr55 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr55 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR56 `define rvformal_csr_pmpaddr56_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wdata; `define rvformal_csr_pmpaddr56_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wdata `define rvformal_csr_pmpaddr56_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wdata `define rvformal_csr_pmpaddr56_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wdata `define rvformal_csr_pmpaddr56_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wdata `define rvformal_csr_pmpaddr56_conn, \ .rvfi_csr_pmpaddr56_rmask (rvfi_csr_pmpaddr56_rmask), \ .rvfi_csr_pmpaddr56_wmask (rvfi_csr_pmpaddr56_wmask), \ .rvfi_csr_pmpaddr56_rdata (rvfi_csr_pmpaddr56_rdata), \ .rvfi_csr_pmpaddr56_wdata (rvfi_csr_pmpaddr56_wdata) `define rvformal_csr_pmpaddr56_channel_conn(_idx), \ .rvfi_csr_pmpaddr56_rmask (rvfi_csr_pmpaddr56_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr56_wmask (rvfi_csr_pmpaddr56_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr56_rdata (rvfi_csr_pmpaddr56_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr56_wdata (rvfi_csr_pmpaddr56_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr56_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr56_rmask = rvfi_csr_pmpaddr56_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr56_wmask = rvfi_csr_pmpaddr56_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr56_rdata = rvfi_csr_pmpaddr56_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr56_wdata = rvfi_csr_pmpaddr56_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr56_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr56_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr56_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr56_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr56_wdata) `else `define rvformal_csr_pmpaddr56_wires `define rvformal_csr_pmpaddr56_outputs `define rvformal_csr_pmpaddr56_inputs `define rvformal_csr_pmpaddr56_conn `define rvformal_csr_pmpaddr56_channel(_idx) `endif `define rvformal_csr_pmpaddr56_indices \ localparam [11:0] csr_mindex_pmpaddr56 = 12'h3E8; \ localparam [11:0] csr_sindex_pmpaddr56 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr56 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR57 `define rvformal_csr_pmpaddr57_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wdata; `define rvformal_csr_pmpaddr57_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wdata `define rvformal_csr_pmpaddr57_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wdata `define rvformal_csr_pmpaddr57_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wdata `define rvformal_csr_pmpaddr57_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wdata `define rvformal_csr_pmpaddr57_conn, \ .rvfi_csr_pmpaddr57_rmask (rvfi_csr_pmpaddr57_rmask), \ .rvfi_csr_pmpaddr57_wmask (rvfi_csr_pmpaddr57_wmask), \ .rvfi_csr_pmpaddr57_rdata (rvfi_csr_pmpaddr57_rdata), \ .rvfi_csr_pmpaddr57_wdata (rvfi_csr_pmpaddr57_wdata) `define rvformal_csr_pmpaddr57_channel_conn(_idx), \ .rvfi_csr_pmpaddr57_rmask (rvfi_csr_pmpaddr57_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr57_wmask (rvfi_csr_pmpaddr57_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr57_rdata (rvfi_csr_pmpaddr57_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr57_wdata (rvfi_csr_pmpaddr57_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr57_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr57_rmask = rvfi_csr_pmpaddr57_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr57_wmask = rvfi_csr_pmpaddr57_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr57_rdata = rvfi_csr_pmpaddr57_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr57_wdata = rvfi_csr_pmpaddr57_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr57_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr57_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr57_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr57_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr57_wdata) `else `define rvformal_csr_pmpaddr57_wires `define rvformal_csr_pmpaddr57_outputs `define rvformal_csr_pmpaddr57_inputs `define rvformal_csr_pmpaddr57_conn `define rvformal_csr_pmpaddr57_channel(_idx) `endif `define rvformal_csr_pmpaddr57_indices \ localparam [11:0] csr_mindex_pmpaddr57 = 12'h3E9; \ localparam [11:0] csr_sindex_pmpaddr57 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr57 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR58 `define rvformal_csr_pmpaddr58_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wdata; `define rvformal_csr_pmpaddr58_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wdata `define rvformal_csr_pmpaddr58_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wdata `define rvformal_csr_pmpaddr58_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wdata `define rvformal_csr_pmpaddr58_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wdata `define rvformal_csr_pmpaddr58_conn, \ .rvfi_csr_pmpaddr58_rmask (rvfi_csr_pmpaddr58_rmask), \ .rvfi_csr_pmpaddr58_wmask (rvfi_csr_pmpaddr58_wmask), \ .rvfi_csr_pmpaddr58_rdata (rvfi_csr_pmpaddr58_rdata), \ .rvfi_csr_pmpaddr58_wdata (rvfi_csr_pmpaddr58_wdata) `define rvformal_csr_pmpaddr58_channel_conn(_idx), \ .rvfi_csr_pmpaddr58_rmask (rvfi_csr_pmpaddr58_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr58_wmask (rvfi_csr_pmpaddr58_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr58_rdata (rvfi_csr_pmpaddr58_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr58_wdata (rvfi_csr_pmpaddr58_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr58_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr58_rmask = rvfi_csr_pmpaddr58_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr58_wmask = rvfi_csr_pmpaddr58_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr58_rdata = rvfi_csr_pmpaddr58_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr58_wdata = rvfi_csr_pmpaddr58_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr58_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr58_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr58_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr58_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr58_wdata) `else `define rvformal_csr_pmpaddr58_wires `define rvformal_csr_pmpaddr58_outputs `define rvformal_csr_pmpaddr58_inputs `define rvformal_csr_pmpaddr58_conn `define rvformal_csr_pmpaddr58_channel(_idx) `endif `define rvformal_csr_pmpaddr58_indices \ localparam [11:0] csr_mindex_pmpaddr58 = 12'h3EA; \ localparam [11:0] csr_sindex_pmpaddr58 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr58 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR59 `define rvformal_csr_pmpaddr59_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wdata; `define rvformal_csr_pmpaddr59_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wdata `define rvformal_csr_pmpaddr59_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wdata `define rvformal_csr_pmpaddr59_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wdata `define rvformal_csr_pmpaddr59_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wdata `define rvformal_csr_pmpaddr59_conn, \ .rvfi_csr_pmpaddr59_rmask (rvfi_csr_pmpaddr59_rmask), \ .rvfi_csr_pmpaddr59_wmask (rvfi_csr_pmpaddr59_wmask), \ .rvfi_csr_pmpaddr59_rdata (rvfi_csr_pmpaddr59_rdata), \ .rvfi_csr_pmpaddr59_wdata (rvfi_csr_pmpaddr59_wdata) `define rvformal_csr_pmpaddr59_channel_conn(_idx), \ .rvfi_csr_pmpaddr59_rmask (rvfi_csr_pmpaddr59_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr59_wmask (rvfi_csr_pmpaddr59_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr59_rdata (rvfi_csr_pmpaddr59_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr59_wdata (rvfi_csr_pmpaddr59_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr59_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr59_rmask = rvfi_csr_pmpaddr59_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr59_wmask = rvfi_csr_pmpaddr59_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr59_rdata = rvfi_csr_pmpaddr59_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr59_wdata = rvfi_csr_pmpaddr59_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr59_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr59_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr59_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr59_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr59_wdata) `else `define rvformal_csr_pmpaddr59_wires `define rvformal_csr_pmpaddr59_outputs `define rvformal_csr_pmpaddr59_inputs `define rvformal_csr_pmpaddr59_conn `define rvformal_csr_pmpaddr59_channel(_idx) `endif `define rvformal_csr_pmpaddr59_indices \ localparam [11:0] csr_mindex_pmpaddr59 = 12'h3EB; \ localparam [11:0] csr_sindex_pmpaddr59 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr59 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR60 `define rvformal_csr_pmpaddr60_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wdata; `define rvformal_csr_pmpaddr60_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wdata `define rvformal_csr_pmpaddr60_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wdata `define rvformal_csr_pmpaddr60_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wdata `define rvformal_csr_pmpaddr60_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wdata `define rvformal_csr_pmpaddr60_conn, \ .rvfi_csr_pmpaddr60_rmask (rvfi_csr_pmpaddr60_rmask), \ .rvfi_csr_pmpaddr60_wmask (rvfi_csr_pmpaddr60_wmask), \ .rvfi_csr_pmpaddr60_rdata (rvfi_csr_pmpaddr60_rdata), \ .rvfi_csr_pmpaddr60_wdata (rvfi_csr_pmpaddr60_wdata) `define rvformal_csr_pmpaddr60_channel_conn(_idx), \ .rvfi_csr_pmpaddr60_rmask (rvfi_csr_pmpaddr60_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr60_wmask (rvfi_csr_pmpaddr60_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr60_rdata (rvfi_csr_pmpaddr60_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr60_wdata (rvfi_csr_pmpaddr60_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr60_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr60_rmask = rvfi_csr_pmpaddr60_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr60_wmask = rvfi_csr_pmpaddr60_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr60_rdata = rvfi_csr_pmpaddr60_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr60_wdata = rvfi_csr_pmpaddr60_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr60_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr60_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr60_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr60_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr60_wdata) `else `define rvformal_csr_pmpaddr60_wires `define rvformal_csr_pmpaddr60_outputs `define rvformal_csr_pmpaddr60_inputs `define rvformal_csr_pmpaddr60_conn `define rvformal_csr_pmpaddr60_channel(_idx) `endif `define rvformal_csr_pmpaddr60_indices \ localparam [11:0] csr_mindex_pmpaddr60 = 12'h3EC; \ localparam [11:0] csr_sindex_pmpaddr60 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr60 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR61 `define rvformal_csr_pmpaddr61_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wdata; `define rvformal_csr_pmpaddr61_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wdata `define rvformal_csr_pmpaddr61_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wdata `define rvformal_csr_pmpaddr61_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wdata `define rvformal_csr_pmpaddr61_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wdata `define rvformal_csr_pmpaddr61_conn, \ .rvfi_csr_pmpaddr61_rmask (rvfi_csr_pmpaddr61_rmask), \ .rvfi_csr_pmpaddr61_wmask (rvfi_csr_pmpaddr61_wmask), \ .rvfi_csr_pmpaddr61_rdata (rvfi_csr_pmpaddr61_rdata), \ .rvfi_csr_pmpaddr61_wdata (rvfi_csr_pmpaddr61_wdata) `define rvformal_csr_pmpaddr61_channel_conn(_idx), \ .rvfi_csr_pmpaddr61_rmask (rvfi_csr_pmpaddr61_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr61_wmask (rvfi_csr_pmpaddr61_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr61_rdata (rvfi_csr_pmpaddr61_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr61_wdata (rvfi_csr_pmpaddr61_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr61_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr61_rmask = rvfi_csr_pmpaddr61_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr61_wmask = rvfi_csr_pmpaddr61_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr61_rdata = rvfi_csr_pmpaddr61_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr61_wdata = rvfi_csr_pmpaddr61_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr61_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr61_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr61_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr61_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr61_wdata) `else `define rvformal_csr_pmpaddr61_wires `define rvformal_csr_pmpaddr61_outputs `define rvformal_csr_pmpaddr61_inputs `define rvformal_csr_pmpaddr61_conn `define rvformal_csr_pmpaddr61_channel(_idx) `endif `define rvformal_csr_pmpaddr61_indices \ localparam [11:0] csr_mindex_pmpaddr61 = 12'h3ED; \ localparam [11:0] csr_sindex_pmpaddr61 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr61 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR62 `define rvformal_csr_pmpaddr62_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wdata; `define rvformal_csr_pmpaddr62_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wdata `define rvformal_csr_pmpaddr62_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wdata `define rvformal_csr_pmpaddr62_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wdata `define rvformal_csr_pmpaddr62_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wdata `define rvformal_csr_pmpaddr62_conn, \ .rvfi_csr_pmpaddr62_rmask (rvfi_csr_pmpaddr62_rmask), \ .rvfi_csr_pmpaddr62_wmask (rvfi_csr_pmpaddr62_wmask), \ .rvfi_csr_pmpaddr62_rdata (rvfi_csr_pmpaddr62_rdata), \ .rvfi_csr_pmpaddr62_wdata (rvfi_csr_pmpaddr62_wdata) `define rvformal_csr_pmpaddr62_channel_conn(_idx), \ .rvfi_csr_pmpaddr62_rmask (rvfi_csr_pmpaddr62_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr62_wmask (rvfi_csr_pmpaddr62_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr62_rdata (rvfi_csr_pmpaddr62_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr62_wdata (rvfi_csr_pmpaddr62_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr62_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr62_rmask = rvfi_csr_pmpaddr62_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr62_wmask = rvfi_csr_pmpaddr62_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr62_rdata = rvfi_csr_pmpaddr62_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr62_wdata = rvfi_csr_pmpaddr62_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr62_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr62_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr62_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr62_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr62_wdata) `else `define rvformal_csr_pmpaddr62_wires `define rvformal_csr_pmpaddr62_outputs `define rvformal_csr_pmpaddr62_inputs `define rvformal_csr_pmpaddr62_conn `define rvformal_csr_pmpaddr62_channel(_idx) `endif `define rvformal_csr_pmpaddr62_indices \ localparam [11:0] csr_mindex_pmpaddr62 = 12'h3EE; \ localparam [11:0] csr_sindex_pmpaddr62 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr62 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_PMPADDR63 `define rvformal_csr_pmpaddr63_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wdata; `define rvformal_csr_pmpaddr63_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wdata `define rvformal_csr_pmpaddr63_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wdata `define rvformal_csr_pmpaddr63_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wdata `define rvformal_csr_pmpaddr63_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wdata `define rvformal_csr_pmpaddr63_conn, \ .rvfi_csr_pmpaddr63_rmask (rvfi_csr_pmpaddr63_rmask), \ .rvfi_csr_pmpaddr63_wmask (rvfi_csr_pmpaddr63_wmask), \ .rvfi_csr_pmpaddr63_rdata (rvfi_csr_pmpaddr63_rdata), \ .rvfi_csr_pmpaddr63_wdata (rvfi_csr_pmpaddr63_wdata) `define rvformal_csr_pmpaddr63_channel_conn(_idx), \ .rvfi_csr_pmpaddr63_rmask (rvfi_csr_pmpaddr63_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr63_wmask (rvfi_csr_pmpaddr63_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr63_rdata (rvfi_csr_pmpaddr63_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_pmpaddr63_wdata (rvfi_csr_pmpaddr63_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_pmpaddr63_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr63_rmask = rvfi_csr_pmpaddr63_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr63_wmask = rvfi_csr_pmpaddr63_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr63_rdata = rvfi_csr_pmpaddr63_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr63_wdata = rvfi_csr_pmpaddr63_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_pmpaddr63_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr63_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr63_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr63_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr63_wdata) `else `define rvformal_csr_pmpaddr63_wires `define rvformal_csr_pmpaddr63_outputs `define rvformal_csr_pmpaddr63_inputs `define rvformal_csr_pmpaddr63_conn `define rvformal_csr_pmpaddr63_channel(_idx) `endif `define rvformal_csr_pmpaddr63_indices \ localparam [11:0] csr_mindex_pmpaddr63 = 12'h3EF; \ localparam [11:0] csr_sindex_pmpaddr63 = 12'hFFF; \ localparam [11:0] csr_uindex_pmpaddr63 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT3 `define rvformal_csr_mhpmevent3_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wdata; `define rvformal_csr_mhpmevent3_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wdata `define rvformal_csr_mhpmevent3_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wdata `define rvformal_csr_mhpmevent3_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wdata `define rvformal_csr_mhpmevent3_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wdata `define rvformal_csr_mhpmevent3_conn, \ .rvfi_csr_mhpmevent3_rmask (rvfi_csr_mhpmevent3_rmask), \ .rvfi_csr_mhpmevent3_wmask (rvfi_csr_mhpmevent3_wmask), \ .rvfi_csr_mhpmevent3_rdata (rvfi_csr_mhpmevent3_rdata), \ .rvfi_csr_mhpmevent3_wdata (rvfi_csr_mhpmevent3_wdata) `define rvformal_csr_mhpmevent3_channel_conn(_idx), \ .rvfi_csr_mhpmevent3_rmask (rvfi_csr_mhpmevent3_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent3_wmask (rvfi_csr_mhpmevent3_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent3_rdata (rvfi_csr_mhpmevent3_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent3_wdata (rvfi_csr_mhpmevent3_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent3_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent3_rmask = rvfi_csr_mhpmevent3_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent3_wmask = rvfi_csr_mhpmevent3_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent3_rdata = rvfi_csr_mhpmevent3_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent3_wdata = rvfi_csr_mhpmevent3_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent3_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent3_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent3_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent3_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent3_wdata) `else `define rvformal_csr_mhpmevent3_wires `define rvformal_csr_mhpmevent3_outputs `define rvformal_csr_mhpmevent3_inputs `define rvformal_csr_mhpmevent3_conn `define rvformal_csr_mhpmevent3_channel(_idx) `endif `define rvformal_csr_mhpmevent3_indices \ localparam [11:0] csr_mindex_mhpmevent3 = 12'h323; \ localparam [11:0] csr_sindex_mhpmevent3 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent3 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT4 `define rvformal_csr_mhpmevent4_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wdata; `define rvformal_csr_mhpmevent4_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wdata `define rvformal_csr_mhpmevent4_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wdata `define rvformal_csr_mhpmevent4_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wdata `define rvformal_csr_mhpmevent4_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wdata `define rvformal_csr_mhpmevent4_conn, \ .rvfi_csr_mhpmevent4_rmask (rvfi_csr_mhpmevent4_rmask), \ .rvfi_csr_mhpmevent4_wmask (rvfi_csr_mhpmevent4_wmask), \ .rvfi_csr_mhpmevent4_rdata (rvfi_csr_mhpmevent4_rdata), \ .rvfi_csr_mhpmevent4_wdata (rvfi_csr_mhpmevent4_wdata) `define rvformal_csr_mhpmevent4_channel_conn(_idx), \ .rvfi_csr_mhpmevent4_rmask (rvfi_csr_mhpmevent4_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent4_wmask (rvfi_csr_mhpmevent4_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent4_rdata (rvfi_csr_mhpmevent4_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent4_wdata (rvfi_csr_mhpmevent4_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent4_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent4_rmask = rvfi_csr_mhpmevent4_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent4_wmask = rvfi_csr_mhpmevent4_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent4_rdata = rvfi_csr_mhpmevent4_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent4_wdata = rvfi_csr_mhpmevent4_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent4_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent4_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent4_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent4_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent4_wdata) `else `define rvformal_csr_mhpmevent4_wires `define rvformal_csr_mhpmevent4_outputs `define rvformal_csr_mhpmevent4_inputs `define rvformal_csr_mhpmevent4_conn `define rvformal_csr_mhpmevent4_channel(_idx) `endif `define rvformal_csr_mhpmevent4_indices \ localparam [11:0] csr_mindex_mhpmevent4 = 12'h324; \ localparam [11:0] csr_sindex_mhpmevent4 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent4 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT5 `define rvformal_csr_mhpmevent5_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wdata; `define rvformal_csr_mhpmevent5_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wdata `define rvformal_csr_mhpmevent5_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wdata `define rvformal_csr_mhpmevent5_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wdata `define rvformal_csr_mhpmevent5_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wdata `define rvformal_csr_mhpmevent5_conn, \ .rvfi_csr_mhpmevent5_rmask (rvfi_csr_mhpmevent5_rmask), \ .rvfi_csr_mhpmevent5_wmask (rvfi_csr_mhpmevent5_wmask), \ .rvfi_csr_mhpmevent5_rdata (rvfi_csr_mhpmevent5_rdata), \ .rvfi_csr_mhpmevent5_wdata (rvfi_csr_mhpmevent5_wdata) `define rvformal_csr_mhpmevent5_channel_conn(_idx), \ .rvfi_csr_mhpmevent5_rmask (rvfi_csr_mhpmevent5_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent5_wmask (rvfi_csr_mhpmevent5_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent5_rdata (rvfi_csr_mhpmevent5_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent5_wdata (rvfi_csr_mhpmevent5_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent5_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent5_rmask = rvfi_csr_mhpmevent5_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent5_wmask = rvfi_csr_mhpmevent5_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent5_rdata = rvfi_csr_mhpmevent5_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent5_wdata = rvfi_csr_mhpmevent5_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent5_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent5_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent5_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent5_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent5_wdata) `else `define rvformal_csr_mhpmevent5_wires `define rvformal_csr_mhpmevent5_outputs `define rvformal_csr_mhpmevent5_inputs `define rvformal_csr_mhpmevent5_conn `define rvformal_csr_mhpmevent5_channel(_idx) `endif `define rvformal_csr_mhpmevent5_indices \ localparam [11:0] csr_mindex_mhpmevent5 = 12'h325; \ localparam [11:0] csr_sindex_mhpmevent5 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent5 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT6 `define rvformal_csr_mhpmevent6_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wdata; `define rvformal_csr_mhpmevent6_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wdata `define rvformal_csr_mhpmevent6_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wdata `define rvformal_csr_mhpmevent6_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wdata `define rvformal_csr_mhpmevent6_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wdata `define rvformal_csr_mhpmevent6_conn, \ .rvfi_csr_mhpmevent6_rmask (rvfi_csr_mhpmevent6_rmask), \ .rvfi_csr_mhpmevent6_wmask (rvfi_csr_mhpmevent6_wmask), \ .rvfi_csr_mhpmevent6_rdata (rvfi_csr_mhpmevent6_rdata), \ .rvfi_csr_mhpmevent6_wdata (rvfi_csr_mhpmevent6_wdata) `define rvformal_csr_mhpmevent6_channel_conn(_idx), \ .rvfi_csr_mhpmevent6_rmask (rvfi_csr_mhpmevent6_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent6_wmask (rvfi_csr_mhpmevent6_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent6_rdata (rvfi_csr_mhpmevent6_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent6_wdata (rvfi_csr_mhpmevent6_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent6_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent6_rmask = rvfi_csr_mhpmevent6_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent6_wmask = rvfi_csr_mhpmevent6_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent6_rdata = rvfi_csr_mhpmevent6_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent6_wdata = rvfi_csr_mhpmevent6_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent6_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent6_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent6_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent6_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent6_wdata) `else `define rvformal_csr_mhpmevent6_wires `define rvformal_csr_mhpmevent6_outputs `define rvformal_csr_mhpmevent6_inputs `define rvformal_csr_mhpmevent6_conn `define rvformal_csr_mhpmevent6_channel(_idx) `endif `define rvformal_csr_mhpmevent6_indices \ localparam [11:0] csr_mindex_mhpmevent6 = 12'h326; \ localparam [11:0] csr_sindex_mhpmevent6 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent6 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT7 `define rvformal_csr_mhpmevent7_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wdata; `define rvformal_csr_mhpmevent7_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wdata `define rvformal_csr_mhpmevent7_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wdata `define rvformal_csr_mhpmevent7_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wdata `define rvformal_csr_mhpmevent7_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wdata `define rvformal_csr_mhpmevent7_conn, \ .rvfi_csr_mhpmevent7_rmask (rvfi_csr_mhpmevent7_rmask), \ .rvfi_csr_mhpmevent7_wmask (rvfi_csr_mhpmevent7_wmask), \ .rvfi_csr_mhpmevent7_rdata (rvfi_csr_mhpmevent7_rdata), \ .rvfi_csr_mhpmevent7_wdata (rvfi_csr_mhpmevent7_wdata) `define rvformal_csr_mhpmevent7_channel_conn(_idx), \ .rvfi_csr_mhpmevent7_rmask (rvfi_csr_mhpmevent7_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent7_wmask (rvfi_csr_mhpmevent7_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent7_rdata (rvfi_csr_mhpmevent7_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent7_wdata (rvfi_csr_mhpmevent7_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent7_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent7_rmask = rvfi_csr_mhpmevent7_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent7_wmask = rvfi_csr_mhpmevent7_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent7_rdata = rvfi_csr_mhpmevent7_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent7_wdata = rvfi_csr_mhpmevent7_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent7_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent7_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent7_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent7_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent7_wdata) `else `define rvformal_csr_mhpmevent7_wires `define rvformal_csr_mhpmevent7_outputs `define rvformal_csr_mhpmevent7_inputs `define rvformal_csr_mhpmevent7_conn `define rvformal_csr_mhpmevent7_channel(_idx) `endif `define rvformal_csr_mhpmevent7_indices \ localparam [11:0] csr_mindex_mhpmevent7 = 12'h327; \ localparam [11:0] csr_sindex_mhpmevent7 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent7 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT8 `define rvformal_csr_mhpmevent8_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wdata; `define rvformal_csr_mhpmevent8_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wdata `define rvformal_csr_mhpmevent8_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wdata `define rvformal_csr_mhpmevent8_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wdata `define rvformal_csr_mhpmevent8_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wdata `define rvformal_csr_mhpmevent8_conn, \ .rvfi_csr_mhpmevent8_rmask (rvfi_csr_mhpmevent8_rmask), \ .rvfi_csr_mhpmevent8_wmask (rvfi_csr_mhpmevent8_wmask), \ .rvfi_csr_mhpmevent8_rdata (rvfi_csr_mhpmevent8_rdata), \ .rvfi_csr_mhpmevent8_wdata (rvfi_csr_mhpmevent8_wdata) `define rvformal_csr_mhpmevent8_channel_conn(_idx), \ .rvfi_csr_mhpmevent8_rmask (rvfi_csr_mhpmevent8_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent8_wmask (rvfi_csr_mhpmevent8_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent8_rdata (rvfi_csr_mhpmevent8_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent8_wdata (rvfi_csr_mhpmevent8_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent8_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent8_rmask = rvfi_csr_mhpmevent8_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent8_wmask = rvfi_csr_mhpmevent8_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent8_rdata = rvfi_csr_mhpmevent8_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent8_wdata = rvfi_csr_mhpmevent8_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent8_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent8_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent8_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent8_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent8_wdata) `else `define rvformal_csr_mhpmevent8_wires `define rvformal_csr_mhpmevent8_outputs `define rvformal_csr_mhpmevent8_inputs `define rvformal_csr_mhpmevent8_conn `define rvformal_csr_mhpmevent8_channel(_idx) `endif `define rvformal_csr_mhpmevent8_indices \ localparam [11:0] csr_mindex_mhpmevent8 = 12'h328; \ localparam [11:0] csr_sindex_mhpmevent8 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent8 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT9 `define rvformal_csr_mhpmevent9_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wdata; `define rvformal_csr_mhpmevent9_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wdata `define rvformal_csr_mhpmevent9_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wdata `define rvformal_csr_mhpmevent9_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wdata `define rvformal_csr_mhpmevent9_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wdata `define rvformal_csr_mhpmevent9_conn, \ .rvfi_csr_mhpmevent9_rmask (rvfi_csr_mhpmevent9_rmask), \ .rvfi_csr_mhpmevent9_wmask (rvfi_csr_mhpmevent9_wmask), \ .rvfi_csr_mhpmevent9_rdata (rvfi_csr_mhpmevent9_rdata), \ .rvfi_csr_mhpmevent9_wdata (rvfi_csr_mhpmevent9_wdata) `define rvformal_csr_mhpmevent9_channel_conn(_idx), \ .rvfi_csr_mhpmevent9_rmask (rvfi_csr_mhpmevent9_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent9_wmask (rvfi_csr_mhpmevent9_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent9_rdata (rvfi_csr_mhpmevent9_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent9_wdata (rvfi_csr_mhpmevent9_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent9_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent9_rmask = rvfi_csr_mhpmevent9_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent9_wmask = rvfi_csr_mhpmevent9_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent9_rdata = rvfi_csr_mhpmevent9_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent9_wdata = rvfi_csr_mhpmevent9_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent9_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent9_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent9_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent9_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent9_wdata) `else `define rvformal_csr_mhpmevent9_wires `define rvformal_csr_mhpmevent9_outputs `define rvformal_csr_mhpmevent9_inputs `define rvformal_csr_mhpmevent9_conn `define rvformal_csr_mhpmevent9_channel(_idx) `endif `define rvformal_csr_mhpmevent9_indices \ localparam [11:0] csr_mindex_mhpmevent9 = 12'h329; \ localparam [11:0] csr_sindex_mhpmevent9 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent9 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT10 `define rvformal_csr_mhpmevent10_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wdata; `define rvformal_csr_mhpmevent10_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wdata `define rvformal_csr_mhpmevent10_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wdata `define rvformal_csr_mhpmevent10_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wdata `define rvformal_csr_mhpmevent10_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wdata `define rvformal_csr_mhpmevent10_conn, \ .rvfi_csr_mhpmevent10_rmask (rvfi_csr_mhpmevent10_rmask), \ .rvfi_csr_mhpmevent10_wmask (rvfi_csr_mhpmevent10_wmask), \ .rvfi_csr_mhpmevent10_rdata (rvfi_csr_mhpmevent10_rdata), \ .rvfi_csr_mhpmevent10_wdata (rvfi_csr_mhpmevent10_wdata) `define rvformal_csr_mhpmevent10_channel_conn(_idx), \ .rvfi_csr_mhpmevent10_rmask (rvfi_csr_mhpmevent10_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent10_wmask (rvfi_csr_mhpmevent10_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent10_rdata (rvfi_csr_mhpmevent10_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent10_wdata (rvfi_csr_mhpmevent10_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent10_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent10_rmask = rvfi_csr_mhpmevent10_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent10_wmask = rvfi_csr_mhpmevent10_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent10_rdata = rvfi_csr_mhpmevent10_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent10_wdata = rvfi_csr_mhpmevent10_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent10_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent10_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent10_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent10_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent10_wdata) `else `define rvformal_csr_mhpmevent10_wires `define rvformal_csr_mhpmevent10_outputs `define rvformal_csr_mhpmevent10_inputs `define rvformal_csr_mhpmevent10_conn `define rvformal_csr_mhpmevent10_channel(_idx) `endif `define rvformal_csr_mhpmevent10_indices \ localparam [11:0] csr_mindex_mhpmevent10 = 12'h32A; \ localparam [11:0] csr_sindex_mhpmevent10 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent10 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT11 `define rvformal_csr_mhpmevent11_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wdata; `define rvformal_csr_mhpmevent11_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wdata `define rvformal_csr_mhpmevent11_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wdata `define rvformal_csr_mhpmevent11_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wdata `define rvformal_csr_mhpmevent11_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wdata `define rvformal_csr_mhpmevent11_conn, \ .rvfi_csr_mhpmevent11_rmask (rvfi_csr_mhpmevent11_rmask), \ .rvfi_csr_mhpmevent11_wmask (rvfi_csr_mhpmevent11_wmask), \ .rvfi_csr_mhpmevent11_rdata (rvfi_csr_mhpmevent11_rdata), \ .rvfi_csr_mhpmevent11_wdata (rvfi_csr_mhpmevent11_wdata) `define rvformal_csr_mhpmevent11_channel_conn(_idx), \ .rvfi_csr_mhpmevent11_rmask (rvfi_csr_mhpmevent11_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent11_wmask (rvfi_csr_mhpmevent11_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent11_rdata (rvfi_csr_mhpmevent11_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent11_wdata (rvfi_csr_mhpmevent11_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent11_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent11_rmask = rvfi_csr_mhpmevent11_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent11_wmask = rvfi_csr_mhpmevent11_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent11_rdata = rvfi_csr_mhpmevent11_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent11_wdata = rvfi_csr_mhpmevent11_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent11_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent11_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent11_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent11_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent11_wdata) `else `define rvformal_csr_mhpmevent11_wires `define rvformal_csr_mhpmevent11_outputs `define rvformal_csr_mhpmevent11_inputs `define rvformal_csr_mhpmevent11_conn `define rvformal_csr_mhpmevent11_channel(_idx) `endif `define rvformal_csr_mhpmevent11_indices \ localparam [11:0] csr_mindex_mhpmevent11 = 12'h32B; \ localparam [11:0] csr_sindex_mhpmevent11 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent11 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT12 `define rvformal_csr_mhpmevent12_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wdata; `define rvformal_csr_mhpmevent12_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wdata `define rvformal_csr_mhpmevent12_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wdata `define rvformal_csr_mhpmevent12_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wdata `define rvformal_csr_mhpmevent12_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wdata `define rvformal_csr_mhpmevent12_conn, \ .rvfi_csr_mhpmevent12_rmask (rvfi_csr_mhpmevent12_rmask), \ .rvfi_csr_mhpmevent12_wmask (rvfi_csr_mhpmevent12_wmask), \ .rvfi_csr_mhpmevent12_rdata (rvfi_csr_mhpmevent12_rdata), \ .rvfi_csr_mhpmevent12_wdata (rvfi_csr_mhpmevent12_wdata) `define rvformal_csr_mhpmevent12_channel_conn(_idx), \ .rvfi_csr_mhpmevent12_rmask (rvfi_csr_mhpmevent12_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent12_wmask (rvfi_csr_mhpmevent12_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent12_rdata (rvfi_csr_mhpmevent12_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent12_wdata (rvfi_csr_mhpmevent12_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent12_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent12_rmask = rvfi_csr_mhpmevent12_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent12_wmask = rvfi_csr_mhpmevent12_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent12_rdata = rvfi_csr_mhpmevent12_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent12_wdata = rvfi_csr_mhpmevent12_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent12_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent12_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent12_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent12_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent12_wdata) `else `define rvformal_csr_mhpmevent12_wires `define rvformal_csr_mhpmevent12_outputs `define rvformal_csr_mhpmevent12_inputs `define rvformal_csr_mhpmevent12_conn `define rvformal_csr_mhpmevent12_channel(_idx) `endif `define rvformal_csr_mhpmevent12_indices \ localparam [11:0] csr_mindex_mhpmevent12 = 12'h32C; \ localparam [11:0] csr_sindex_mhpmevent12 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent12 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT13 `define rvformal_csr_mhpmevent13_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wdata; `define rvformal_csr_mhpmevent13_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wdata `define rvformal_csr_mhpmevent13_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wdata `define rvformal_csr_mhpmevent13_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wdata `define rvformal_csr_mhpmevent13_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wdata `define rvformal_csr_mhpmevent13_conn, \ .rvfi_csr_mhpmevent13_rmask (rvfi_csr_mhpmevent13_rmask), \ .rvfi_csr_mhpmevent13_wmask (rvfi_csr_mhpmevent13_wmask), \ .rvfi_csr_mhpmevent13_rdata (rvfi_csr_mhpmevent13_rdata), \ .rvfi_csr_mhpmevent13_wdata (rvfi_csr_mhpmevent13_wdata) `define rvformal_csr_mhpmevent13_channel_conn(_idx), \ .rvfi_csr_mhpmevent13_rmask (rvfi_csr_mhpmevent13_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent13_wmask (rvfi_csr_mhpmevent13_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent13_rdata (rvfi_csr_mhpmevent13_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent13_wdata (rvfi_csr_mhpmevent13_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent13_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent13_rmask = rvfi_csr_mhpmevent13_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent13_wmask = rvfi_csr_mhpmevent13_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent13_rdata = rvfi_csr_mhpmevent13_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent13_wdata = rvfi_csr_mhpmevent13_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent13_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent13_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent13_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent13_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent13_wdata) `else `define rvformal_csr_mhpmevent13_wires `define rvformal_csr_mhpmevent13_outputs `define rvformal_csr_mhpmevent13_inputs `define rvformal_csr_mhpmevent13_conn `define rvformal_csr_mhpmevent13_channel(_idx) `endif `define rvformal_csr_mhpmevent13_indices \ localparam [11:0] csr_mindex_mhpmevent13 = 12'h32D; \ localparam [11:0] csr_sindex_mhpmevent13 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent13 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT14 `define rvformal_csr_mhpmevent14_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wdata; `define rvformal_csr_mhpmevent14_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wdata `define rvformal_csr_mhpmevent14_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wdata `define rvformal_csr_mhpmevent14_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wdata `define rvformal_csr_mhpmevent14_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wdata `define rvformal_csr_mhpmevent14_conn, \ .rvfi_csr_mhpmevent14_rmask (rvfi_csr_mhpmevent14_rmask), \ .rvfi_csr_mhpmevent14_wmask (rvfi_csr_mhpmevent14_wmask), \ .rvfi_csr_mhpmevent14_rdata (rvfi_csr_mhpmevent14_rdata), \ .rvfi_csr_mhpmevent14_wdata (rvfi_csr_mhpmevent14_wdata) `define rvformal_csr_mhpmevent14_channel_conn(_idx), \ .rvfi_csr_mhpmevent14_rmask (rvfi_csr_mhpmevent14_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent14_wmask (rvfi_csr_mhpmevent14_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent14_rdata (rvfi_csr_mhpmevent14_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent14_wdata (rvfi_csr_mhpmevent14_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent14_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent14_rmask = rvfi_csr_mhpmevent14_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent14_wmask = rvfi_csr_mhpmevent14_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent14_rdata = rvfi_csr_mhpmevent14_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent14_wdata = rvfi_csr_mhpmevent14_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent14_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent14_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent14_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent14_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent14_wdata) `else `define rvformal_csr_mhpmevent14_wires `define rvformal_csr_mhpmevent14_outputs `define rvformal_csr_mhpmevent14_inputs `define rvformal_csr_mhpmevent14_conn `define rvformal_csr_mhpmevent14_channel(_idx) `endif `define rvformal_csr_mhpmevent14_indices \ localparam [11:0] csr_mindex_mhpmevent14 = 12'h32E; \ localparam [11:0] csr_sindex_mhpmevent14 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent14 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT15 `define rvformal_csr_mhpmevent15_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wdata; `define rvformal_csr_mhpmevent15_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wdata `define rvformal_csr_mhpmevent15_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wdata `define rvformal_csr_mhpmevent15_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wdata `define rvformal_csr_mhpmevent15_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wdata `define rvformal_csr_mhpmevent15_conn, \ .rvfi_csr_mhpmevent15_rmask (rvfi_csr_mhpmevent15_rmask), \ .rvfi_csr_mhpmevent15_wmask (rvfi_csr_mhpmevent15_wmask), \ .rvfi_csr_mhpmevent15_rdata (rvfi_csr_mhpmevent15_rdata), \ .rvfi_csr_mhpmevent15_wdata (rvfi_csr_mhpmevent15_wdata) `define rvformal_csr_mhpmevent15_channel_conn(_idx), \ .rvfi_csr_mhpmevent15_rmask (rvfi_csr_mhpmevent15_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent15_wmask (rvfi_csr_mhpmevent15_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent15_rdata (rvfi_csr_mhpmevent15_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent15_wdata (rvfi_csr_mhpmevent15_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent15_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent15_rmask = rvfi_csr_mhpmevent15_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent15_wmask = rvfi_csr_mhpmevent15_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent15_rdata = rvfi_csr_mhpmevent15_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent15_wdata = rvfi_csr_mhpmevent15_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent15_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent15_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent15_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent15_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent15_wdata) `else `define rvformal_csr_mhpmevent15_wires `define rvformal_csr_mhpmevent15_outputs `define rvformal_csr_mhpmevent15_inputs `define rvformal_csr_mhpmevent15_conn `define rvformal_csr_mhpmevent15_channel(_idx) `endif `define rvformal_csr_mhpmevent15_indices \ localparam [11:0] csr_mindex_mhpmevent15 = 12'h32F; \ localparam [11:0] csr_sindex_mhpmevent15 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent15 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT16 `define rvformal_csr_mhpmevent16_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wdata; `define rvformal_csr_mhpmevent16_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wdata `define rvformal_csr_mhpmevent16_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wdata `define rvformal_csr_mhpmevent16_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wdata `define rvformal_csr_mhpmevent16_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wdata `define rvformal_csr_mhpmevent16_conn, \ .rvfi_csr_mhpmevent16_rmask (rvfi_csr_mhpmevent16_rmask), \ .rvfi_csr_mhpmevent16_wmask (rvfi_csr_mhpmevent16_wmask), \ .rvfi_csr_mhpmevent16_rdata (rvfi_csr_mhpmevent16_rdata), \ .rvfi_csr_mhpmevent16_wdata (rvfi_csr_mhpmevent16_wdata) `define rvformal_csr_mhpmevent16_channel_conn(_idx), \ .rvfi_csr_mhpmevent16_rmask (rvfi_csr_mhpmevent16_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent16_wmask (rvfi_csr_mhpmevent16_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent16_rdata (rvfi_csr_mhpmevent16_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent16_wdata (rvfi_csr_mhpmevent16_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent16_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent16_rmask = rvfi_csr_mhpmevent16_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent16_wmask = rvfi_csr_mhpmevent16_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent16_rdata = rvfi_csr_mhpmevent16_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent16_wdata = rvfi_csr_mhpmevent16_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent16_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent16_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent16_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent16_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent16_wdata) `else `define rvformal_csr_mhpmevent16_wires `define rvformal_csr_mhpmevent16_outputs `define rvformal_csr_mhpmevent16_inputs `define rvformal_csr_mhpmevent16_conn `define rvformal_csr_mhpmevent16_channel(_idx) `endif `define rvformal_csr_mhpmevent16_indices \ localparam [11:0] csr_mindex_mhpmevent16 = 12'h330; \ localparam [11:0] csr_sindex_mhpmevent16 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent16 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT17 `define rvformal_csr_mhpmevent17_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wdata; `define rvformal_csr_mhpmevent17_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wdata `define rvformal_csr_mhpmevent17_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wdata `define rvformal_csr_mhpmevent17_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wdata `define rvformal_csr_mhpmevent17_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wdata `define rvformal_csr_mhpmevent17_conn, \ .rvfi_csr_mhpmevent17_rmask (rvfi_csr_mhpmevent17_rmask), \ .rvfi_csr_mhpmevent17_wmask (rvfi_csr_mhpmevent17_wmask), \ .rvfi_csr_mhpmevent17_rdata (rvfi_csr_mhpmevent17_rdata), \ .rvfi_csr_mhpmevent17_wdata (rvfi_csr_mhpmevent17_wdata) `define rvformal_csr_mhpmevent17_channel_conn(_idx), \ .rvfi_csr_mhpmevent17_rmask (rvfi_csr_mhpmevent17_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent17_wmask (rvfi_csr_mhpmevent17_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent17_rdata (rvfi_csr_mhpmevent17_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent17_wdata (rvfi_csr_mhpmevent17_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent17_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent17_rmask = rvfi_csr_mhpmevent17_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent17_wmask = rvfi_csr_mhpmevent17_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent17_rdata = rvfi_csr_mhpmevent17_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent17_wdata = rvfi_csr_mhpmevent17_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent17_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent17_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent17_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent17_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent17_wdata) `else `define rvformal_csr_mhpmevent17_wires `define rvformal_csr_mhpmevent17_outputs `define rvformal_csr_mhpmevent17_inputs `define rvformal_csr_mhpmevent17_conn `define rvformal_csr_mhpmevent17_channel(_idx) `endif `define rvformal_csr_mhpmevent17_indices \ localparam [11:0] csr_mindex_mhpmevent17 = 12'h331; \ localparam [11:0] csr_sindex_mhpmevent17 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent17 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT18 `define rvformal_csr_mhpmevent18_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wdata; `define rvformal_csr_mhpmevent18_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wdata `define rvformal_csr_mhpmevent18_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wdata `define rvformal_csr_mhpmevent18_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wdata `define rvformal_csr_mhpmevent18_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wdata `define rvformal_csr_mhpmevent18_conn, \ .rvfi_csr_mhpmevent18_rmask (rvfi_csr_mhpmevent18_rmask), \ .rvfi_csr_mhpmevent18_wmask (rvfi_csr_mhpmevent18_wmask), \ .rvfi_csr_mhpmevent18_rdata (rvfi_csr_mhpmevent18_rdata), \ .rvfi_csr_mhpmevent18_wdata (rvfi_csr_mhpmevent18_wdata) `define rvformal_csr_mhpmevent18_channel_conn(_idx), \ .rvfi_csr_mhpmevent18_rmask (rvfi_csr_mhpmevent18_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent18_wmask (rvfi_csr_mhpmevent18_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent18_rdata (rvfi_csr_mhpmevent18_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent18_wdata (rvfi_csr_mhpmevent18_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent18_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent18_rmask = rvfi_csr_mhpmevent18_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent18_wmask = rvfi_csr_mhpmevent18_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent18_rdata = rvfi_csr_mhpmevent18_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent18_wdata = rvfi_csr_mhpmevent18_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent18_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent18_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent18_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent18_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent18_wdata) `else `define rvformal_csr_mhpmevent18_wires `define rvformal_csr_mhpmevent18_outputs `define rvformal_csr_mhpmevent18_inputs `define rvformal_csr_mhpmevent18_conn `define rvformal_csr_mhpmevent18_channel(_idx) `endif `define rvformal_csr_mhpmevent18_indices \ localparam [11:0] csr_mindex_mhpmevent18 = 12'h332; \ localparam [11:0] csr_sindex_mhpmevent18 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent18 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT19 `define rvformal_csr_mhpmevent19_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wdata; `define rvformal_csr_mhpmevent19_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wdata `define rvformal_csr_mhpmevent19_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wdata `define rvformal_csr_mhpmevent19_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wdata `define rvformal_csr_mhpmevent19_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wdata `define rvformal_csr_mhpmevent19_conn, \ .rvfi_csr_mhpmevent19_rmask (rvfi_csr_mhpmevent19_rmask), \ .rvfi_csr_mhpmevent19_wmask (rvfi_csr_mhpmevent19_wmask), \ .rvfi_csr_mhpmevent19_rdata (rvfi_csr_mhpmevent19_rdata), \ .rvfi_csr_mhpmevent19_wdata (rvfi_csr_mhpmevent19_wdata) `define rvformal_csr_mhpmevent19_channel_conn(_idx), \ .rvfi_csr_mhpmevent19_rmask (rvfi_csr_mhpmevent19_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent19_wmask (rvfi_csr_mhpmevent19_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent19_rdata (rvfi_csr_mhpmevent19_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent19_wdata (rvfi_csr_mhpmevent19_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent19_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent19_rmask = rvfi_csr_mhpmevent19_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent19_wmask = rvfi_csr_mhpmevent19_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent19_rdata = rvfi_csr_mhpmevent19_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent19_wdata = rvfi_csr_mhpmevent19_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent19_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent19_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent19_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent19_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent19_wdata) `else `define rvformal_csr_mhpmevent19_wires `define rvformal_csr_mhpmevent19_outputs `define rvformal_csr_mhpmevent19_inputs `define rvformal_csr_mhpmevent19_conn `define rvformal_csr_mhpmevent19_channel(_idx) `endif `define rvformal_csr_mhpmevent19_indices \ localparam [11:0] csr_mindex_mhpmevent19 = 12'h333; \ localparam [11:0] csr_sindex_mhpmevent19 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent19 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT20 `define rvformal_csr_mhpmevent20_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wdata; `define rvformal_csr_mhpmevent20_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wdata `define rvformal_csr_mhpmevent20_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wdata `define rvformal_csr_mhpmevent20_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wdata `define rvformal_csr_mhpmevent20_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wdata `define rvformal_csr_mhpmevent20_conn, \ .rvfi_csr_mhpmevent20_rmask (rvfi_csr_mhpmevent20_rmask), \ .rvfi_csr_mhpmevent20_wmask (rvfi_csr_mhpmevent20_wmask), \ .rvfi_csr_mhpmevent20_rdata (rvfi_csr_mhpmevent20_rdata), \ .rvfi_csr_mhpmevent20_wdata (rvfi_csr_mhpmevent20_wdata) `define rvformal_csr_mhpmevent20_channel_conn(_idx), \ .rvfi_csr_mhpmevent20_rmask (rvfi_csr_mhpmevent20_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent20_wmask (rvfi_csr_mhpmevent20_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent20_rdata (rvfi_csr_mhpmevent20_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent20_wdata (rvfi_csr_mhpmevent20_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent20_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent20_rmask = rvfi_csr_mhpmevent20_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent20_wmask = rvfi_csr_mhpmevent20_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent20_rdata = rvfi_csr_mhpmevent20_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent20_wdata = rvfi_csr_mhpmevent20_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent20_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent20_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent20_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent20_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent20_wdata) `else `define rvformal_csr_mhpmevent20_wires `define rvformal_csr_mhpmevent20_outputs `define rvformal_csr_mhpmevent20_inputs `define rvformal_csr_mhpmevent20_conn `define rvformal_csr_mhpmevent20_channel(_idx) `endif `define rvformal_csr_mhpmevent20_indices \ localparam [11:0] csr_mindex_mhpmevent20 = 12'h334; \ localparam [11:0] csr_sindex_mhpmevent20 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent20 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT21 `define rvformal_csr_mhpmevent21_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wdata; `define rvformal_csr_mhpmevent21_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wdata `define rvformal_csr_mhpmevent21_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wdata `define rvformal_csr_mhpmevent21_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wdata `define rvformal_csr_mhpmevent21_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wdata `define rvformal_csr_mhpmevent21_conn, \ .rvfi_csr_mhpmevent21_rmask (rvfi_csr_mhpmevent21_rmask), \ .rvfi_csr_mhpmevent21_wmask (rvfi_csr_mhpmevent21_wmask), \ .rvfi_csr_mhpmevent21_rdata (rvfi_csr_mhpmevent21_rdata), \ .rvfi_csr_mhpmevent21_wdata (rvfi_csr_mhpmevent21_wdata) `define rvformal_csr_mhpmevent21_channel_conn(_idx), \ .rvfi_csr_mhpmevent21_rmask (rvfi_csr_mhpmevent21_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent21_wmask (rvfi_csr_mhpmevent21_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent21_rdata (rvfi_csr_mhpmevent21_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent21_wdata (rvfi_csr_mhpmevent21_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent21_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent21_rmask = rvfi_csr_mhpmevent21_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent21_wmask = rvfi_csr_mhpmevent21_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent21_rdata = rvfi_csr_mhpmevent21_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent21_wdata = rvfi_csr_mhpmevent21_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent21_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent21_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent21_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent21_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent21_wdata) `else `define rvformal_csr_mhpmevent21_wires `define rvformal_csr_mhpmevent21_outputs `define rvformal_csr_mhpmevent21_inputs `define rvformal_csr_mhpmevent21_conn `define rvformal_csr_mhpmevent21_channel(_idx) `endif `define rvformal_csr_mhpmevent21_indices \ localparam [11:0] csr_mindex_mhpmevent21 = 12'h335; \ localparam [11:0] csr_sindex_mhpmevent21 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent21 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT22 `define rvformal_csr_mhpmevent22_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wdata; `define rvformal_csr_mhpmevent22_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wdata `define rvformal_csr_mhpmevent22_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wdata `define rvformal_csr_mhpmevent22_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wdata `define rvformal_csr_mhpmevent22_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wdata `define rvformal_csr_mhpmevent22_conn, \ .rvfi_csr_mhpmevent22_rmask (rvfi_csr_mhpmevent22_rmask), \ .rvfi_csr_mhpmevent22_wmask (rvfi_csr_mhpmevent22_wmask), \ .rvfi_csr_mhpmevent22_rdata (rvfi_csr_mhpmevent22_rdata), \ .rvfi_csr_mhpmevent22_wdata (rvfi_csr_mhpmevent22_wdata) `define rvformal_csr_mhpmevent22_channel_conn(_idx), \ .rvfi_csr_mhpmevent22_rmask (rvfi_csr_mhpmevent22_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent22_wmask (rvfi_csr_mhpmevent22_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent22_rdata (rvfi_csr_mhpmevent22_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent22_wdata (rvfi_csr_mhpmevent22_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent22_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent22_rmask = rvfi_csr_mhpmevent22_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent22_wmask = rvfi_csr_mhpmevent22_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent22_rdata = rvfi_csr_mhpmevent22_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent22_wdata = rvfi_csr_mhpmevent22_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent22_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent22_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent22_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent22_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent22_wdata) `else `define rvformal_csr_mhpmevent22_wires `define rvformal_csr_mhpmevent22_outputs `define rvformal_csr_mhpmevent22_inputs `define rvformal_csr_mhpmevent22_conn `define rvformal_csr_mhpmevent22_channel(_idx) `endif `define rvformal_csr_mhpmevent22_indices \ localparam [11:0] csr_mindex_mhpmevent22 = 12'h336; \ localparam [11:0] csr_sindex_mhpmevent22 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent22 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT23 `define rvformal_csr_mhpmevent23_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wdata; `define rvformal_csr_mhpmevent23_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wdata `define rvformal_csr_mhpmevent23_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wdata `define rvformal_csr_mhpmevent23_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wdata `define rvformal_csr_mhpmevent23_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wdata `define rvformal_csr_mhpmevent23_conn, \ .rvfi_csr_mhpmevent23_rmask (rvfi_csr_mhpmevent23_rmask), \ .rvfi_csr_mhpmevent23_wmask (rvfi_csr_mhpmevent23_wmask), \ .rvfi_csr_mhpmevent23_rdata (rvfi_csr_mhpmevent23_rdata), \ .rvfi_csr_mhpmevent23_wdata (rvfi_csr_mhpmevent23_wdata) `define rvformal_csr_mhpmevent23_channel_conn(_idx), \ .rvfi_csr_mhpmevent23_rmask (rvfi_csr_mhpmevent23_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent23_wmask (rvfi_csr_mhpmevent23_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent23_rdata (rvfi_csr_mhpmevent23_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent23_wdata (rvfi_csr_mhpmevent23_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent23_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent23_rmask = rvfi_csr_mhpmevent23_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent23_wmask = rvfi_csr_mhpmevent23_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent23_rdata = rvfi_csr_mhpmevent23_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent23_wdata = rvfi_csr_mhpmevent23_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent23_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent23_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent23_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent23_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent23_wdata) `else `define rvformal_csr_mhpmevent23_wires `define rvformal_csr_mhpmevent23_outputs `define rvformal_csr_mhpmevent23_inputs `define rvformal_csr_mhpmevent23_conn `define rvformal_csr_mhpmevent23_channel(_idx) `endif `define rvformal_csr_mhpmevent23_indices \ localparam [11:0] csr_mindex_mhpmevent23 = 12'h337; \ localparam [11:0] csr_sindex_mhpmevent23 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent23 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT24 `define rvformal_csr_mhpmevent24_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wdata; `define rvformal_csr_mhpmevent24_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wdata `define rvformal_csr_mhpmevent24_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wdata `define rvformal_csr_mhpmevent24_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wdata `define rvformal_csr_mhpmevent24_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wdata `define rvformal_csr_mhpmevent24_conn, \ .rvfi_csr_mhpmevent24_rmask (rvfi_csr_mhpmevent24_rmask), \ .rvfi_csr_mhpmevent24_wmask (rvfi_csr_mhpmevent24_wmask), \ .rvfi_csr_mhpmevent24_rdata (rvfi_csr_mhpmevent24_rdata), \ .rvfi_csr_mhpmevent24_wdata (rvfi_csr_mhpmevent24_wdata) `define rvformal_csr_mhpmevent24_channel_conn(_idx), \ .rvfi_csr_mhpmevent24_rmask (rvfi_csr_mhpmevent24_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent24_wmask (rvfi_csr_mhpmevent24_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent24_rdata (rvfi_csr_mhpmevent24_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent24_wdata (rvfi_csr_mhpmevent24_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent24_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent24_rmask = rvfi_csr_mhpmevent24_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent24_wmask = rvfi_csr_mhpmevent24_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent24_rdata = rvfi_csr_mhpmevent24_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent24_wdata = rvfi_csr_mhpmevent24_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent24_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent24_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent24_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent24_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent24_wdata) `else `define rvformal_csr_mhpmevent24_wires `define rvformal_csr_mhpmevent24_outputs `define rvformal_csr_mhpmevent24_inputs `define rvformal_csr_mhpmevent24_conn `define rvformal_csr_mhpmevent24_channel(_idx) `endif `define rvformal_csr_mhpmevent24_indices \ localparam [11:0] csr_mindex_mhpmevent24 = 12'h338; \ localparam [11:0] csr_sindex_mhpmevent24 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent24 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT25 `define rvformal_csr_mhpmevent25_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wdata; `define rvformal_csr_mhpmevent25_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wdata `define rvformal_csr_mhpmevent25_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wdata `define rvformal_csr_mhpmevent25_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wdata `define rvformal_csr_mhpmevent25_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wdata `define rvformal_csr_mhpmevent25_conn, \ .rvfi_csr_mhpmevent25_rmask (rvfi_csr_mhpmevent25_rmask), \ .rvfi_csr_mhpmevent25_wmask (rvfi_csr_mhpmevent25_wmask), \ .rvfi_csr_mhpmevent25_rdata (rvfi_csr_mhpmevent25_rdata), \ .rvfi_csr_mhpmevent25_wdata (rvfi_csr_mhpmevent25_wdata) `define rvformal_csr_mhpmevent25_channel_conn(_idx), \ .rvfi_csr_mhpmevent25_rmask (rvfi_csr_mhpmevent25_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent25_wmask (rvfi_csr_mhpmevent25_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent25_rdata (rvfi_csr_mhpmevent25_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent25_wdata (rvfi_csr_mhpmevent25_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent25_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent25_rmask = rvfi_csr_mhpmevent25_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent25_wmask = rvfi_csr_mhpmevent25_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent25_rdata = rvfi_csr_mhpmevent25_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent25_wdata = rvfi_csr_mhpmevent25_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent25_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent25_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent25_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent25_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent25_wdata) `else `define rvformal_csr_mhpmevent25_wires `define rvformal_csr_mhpmevent25_outputs `define rvformal_csr_mhpmevent25_inputs `define rvformal_csr_mhpmevent25_conn `define rvformal_csr_mhpmevent25_channel(_idx) `endif `define rvformal_csr_mhpmevent25_indices \ localparam [11:0] csr_mindex_mhpmevent25 = 12'h339; \ localparam [11:0] csr_sindex_mhpmevent25 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent25 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT26 `define rvformal_csr_mhpmevent26_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wdata; `define rvformal_csr_mhpmevent26_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wdata `define rvformal_csr_mhpmevent26_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wdata `define rvformal_csr_mhpmevent26_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wdata `define rvformal_csr_mhpmevent26_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wdata `define rvformal_csr_mhpmevent26_conn, \ .rvfi_csr_mhpmevent26_rmask (rvfi_csr_mhpmevent26_rmask), \ .rvfi_csr_mhpmevent26_wmask (rvfi_csr_mhpmevent26_wmask), \ .rvfi_csr_mhpmevent26_rdata (rvfi_csr_mhpmevent26_rdata), \ .rvfi_csr_mhpmevent26_wdata (rvfi_csr_mhpmevent26_wdata) `define rvformal_csr_mhpmevent26_channel_conn(_idx), \ .rvfi_csr_mhpmevent26_rmask (rvfi_csr_mhpmevent26_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent26_wmask (rvfi_csr_mhpmevent26_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent26_rdata (rvfi_csr_mhpmevent26_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent26_wdata (rvfi_csr_mhpmevent26_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent26_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent26_rmask = rvfi_csr_mhpmevent26_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent26_wmask = rvfi_csr_mhpmevent26_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent26_rdata = rvfi_csr_mhpmevent26_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent26_wdata = rvfi_csr_mhpmevent26_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent26_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent26_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent26_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent26_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent26_wdata) `else `define rvformal_csr_mhpmevent26_wires `define rvformal_csr_mhpmevent26_outputs `define rvformal_csr_mhpmevent26_inputs `define rvformal_csr_mhpmevent26_conn `define rvformal_csr_mhpmevent26_channel(_idx) `endif `define rvformal_csr_mhpmevent26_indices \ localparam [11:0] csr_mindex_mhpmevent26 = 12'h33A; \ localparam [11:0] csr_sindex_mhpmevent26 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent26 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT27 `define rvformal_csr_mhpmevent27_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wdata; `define rvformal_csr_mhpmevent27_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wdata `define rvformal_csr_mhpmevent27_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wdata `define rvformal_csr_mhpmevent27_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wdata `define rvformal_csr_mhpmevent27_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wdata `define rvformal_csr_mhpmevent27_conn, \ .rvfi_csr_mhpmevent27_rmask (rvfi_csr_mhpmevent27_rmask), \ .rvfi_csr_mhpmevent27_wmask (rvfi_csr_mhpmevent27_wmask), \ .rvfi_csr_mhpmevent27_rdata (rvfi_csr_mhpmevent27_rdata), \ .rvfi_csr_mhpmevent27_wdata (rvfi_csr_mhpmevent27_wdata) `define rvformal_csr_mhpmevent27_channel_conn(_idx), \ .rvfi_csr_mhpmevent27_rmask (rvfi_csr_mhpmevent27_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent27_wmask (rvfi_csr_mhpmevent27_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent27_rdata (rvfi_csr_mhpmevent27_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent27_wdata (rvfi_csr_mhpmevent27_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent27_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent27_rmask = rvfi_csr_mhpmevent27_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent27_wmask = rvfi_csr_mhpmevent27_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent27_rdata = rvfi_csr_mhpmevent27_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent27_wdata = rvfi_csr_mhpmevent27_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent27_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent27_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent27_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent27_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent27_wdata) `else `define rvformal_csr_mhpmevent27_wires `define rvformal_csr_mhpmevent27_outputs `define rvformal_csr_mhpmevent27_inputs `define rvformal_csr_mhpmevent27_conn `define rvformal_csr_mhpmevent27_channel(_idx) `endif `define rvformal_csr_mhpmevent27_indices \ localparam [11:0] csr_mindex_mhpmevent27 = 12'h33B; \ localparam [11:0] csr_sindex_mhpmevent27 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent27 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT28 `define rvformal_csr_mhpmevent28_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wdata; `define rvformal_csr_mhpmevent28_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wdata `define rvformal_csr_mhpmevent28_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wdata `define rvformal_csr_mhpmevent28_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wdata `define rvformal_csr_mhpmevent28_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wdata `define rvformal_csr_mhpmevent28_conn, \ .rvfi_csr_mhpmevent28_rmask (rvfi_csr_mhpmevent28_rmask), \ .rvfi_csr_mhpmevent28_wmask (rvfi_csr_mhpmevent28_wmask), \ .rvfi_csr_mhpmevent28_rdata (rvfi_csr_mhpmevent28_rdata), \ .rvfi_csr_mhpmevent28_wdata (rvfi_csr_mhpmevent28_wdata) `define rvformal_csr_mhpmevent28_channel_conn(_idx), \ .rvfi_csr_mhpmevent28_rmask (rvfi_csr_mhpmevent28_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent28_wmask (rvfi_csr_mhpmevent28_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent28_rdata (rvfi_csr_mhpmevent28_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent28_wdata (rvfi_csr_mhpmevent28_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent28_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent28_rmask = rvfi_csr_mhpmevent28_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent28_wmask = rvfi_csr_mhpmevent28_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent28_rdata = rvfi_csr_mhpmevent28_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent28_wdata = rvfi_csr_mhpmevent28_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent28_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent28_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent28_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent28_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent28_wdata) `else `define rvformal_csr_mhpmevent28_wires `define rvformal_csr_mhpmevent28_outputs `define rvformal_csr_mhpmevent28_inputs `define rvformal_csr_mhpmevent28_conn `define rvformal_csr_mhpmevent28_channel(_idx) `endif `define rvformal_csr_mhpmevent28_indices \ localparam [11:0] csr_mindex_mhpmevent28 = 12'h33C; \ localparam [11:0] csr_sindex_mhpmevent28 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent28 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT29 `define rvformal_csr_mhpmevent29_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wdata; `define rvformal_csr_mhpmevent29_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wdata `define rvformal_csr_mhpmevent29_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wdata `define rvformal_csr_mhpmevent29_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wdata `define rvformal_csr_mhpmevent29_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wdata `define rvformal_csr_mhpmevent29_conn, \ .rvfi_csr_mhpmevent29_rmask (rvfi_csr_mhpmevent29_rmask), \ .rvfi_csr_mhpmevent29_wmask (rvfi_csr_mhpmevent29_wmask), \ .rvfi_csr_mhpmevent29_rdata (rvfi_csr_mhpmevent29_rdata), \ .rvfi_csr_mhpmevent29_wdata (rvfi_csr_mhpmevent29_wdata) `define rvformal_csr_mhpmevent29_channel_conn(_idx), \ .rvfi_csr_mhpmevent29_rmask (rvfi_csr_mhpmevent29_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent29_wmask (rvfi_csr_mhpmevent29_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent29_rdata (rvfi_csr_mhpmevent29_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent29_wdata (rvfi_csr_mhpmevent29_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent29_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent29_rmask = rvfi_csr_mhpmevent29_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent29_wmask = rvfi_csr_mhpmevent29_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent29_rdata = rvfi_csr_mhpmevent29_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent29_wdata = rvfi_csr_mhpmevent29_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent29_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent29_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent29_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent29_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent29_wdata) `else `define rvformal_csr_mhpmevent29_wires `define rvformal_csr_mhpmevent29_outputs `define rvformal_csr_mhpmevent29_inputs `define rvformal_csr_mhpmevent29_conn `define rvformal_csr_mhpmevent29_channel(_idx) `endif `define rvformal_csr_mhpmevent29_indices \ localparam [11:0] csr_mindex_mhpmevent29 = 12'h33D; \ localparam [11:0] csr_sindex_mhpmevent29 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent29 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT30 `define rvformal_csr_mhpmevent30_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wdata; `define rvformal_csr_mhpmevent30_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wdata `define rvformal_csr_mhpmevent30_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wdata `define rvformal_csr_mhpmevent30_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wdata `define rvformal_csr_mhpmevent30_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wdata `define rvformal_csr_mhpmevent30_conn, \ .rvfi_csr_mhpmevent30_rmask (rvfi_csr_mhpmevent30_rmask), \ .rvfi_csr_mhpmevent30_wmask (rvfi_csr_mhpmevent30_wmask), \ .rvfi_csr_mhpmevent30_rdata (rvfi_csr_mhpmevent30_rdata), \ .rvfi_csr_mhpmevent30_wdata (rvfi_csr_mhpmevent30_wdata) `define rvformal_csr_mhpmevent30_channel_conn(_idx), \ .rvfi_csr_mhpmevent30_rmask (rvfi_csr_mhpmevent30_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent30_wmask (rvfi_csr_mhpmevent30_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent30_rdata (rvfi_csr_mhpmevent30_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent30_wdata (rvfi_csr_mhpmevent30_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent30_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent30_rmask = rvfi_csr_mhpmevent30_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent30_wmask = rvfi_csr_mhpmevent30_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent30_rdata = rvfi_csr_mhpmevent30_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent30_wdata = rvfi_csr_mhpmevent30_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent30_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent30_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent30_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent30_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent30_wdata) `else `define rvformal_csr_mhpmevent30_wires `define rvformal_csr_mhpmevent30_outputs `define rvformal_csr_mhpmevent30_inputs `define rvformal_csr_mhpmevent30_conn `define rvformal_csr_mhpmevent30_channel(_idx) `endif `define rvformal_csr_mhpmevent30_indices \ localparam [11:0] csr_mindex_mhpmevent30 = 12'h33E; \ localparam [11:0] csr_sindex_mhpmevent30 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent30 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MHPMEVENT31 `define rvformal_csr_mhpmevent31_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wdata; `define rvformal_csr_mhpmevent31_outputs, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wdata `define rvformal_csr_mhpmevent31_channel_outputs, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wdata `define rvformal_csr_mhpmevent31_inputs, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wdata `define rvformal_csr_mhpmevent31_channel_inputs, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wdata `define rvformal_csr_mhpmevent31_conn, \ .rvfi_csr_mhpmevent31_rmask (rvfi_csr_mhpmevent31_rmask), \ .rvfi_csr_mhpmevent31_wmask (rvfi_csr_mhpmevent31_wmask), \ .rvfi_csr_mhpmevent31_rdata (rvfi_csr_mhpmevent31_rdata), \ .rvfi_csr_mhpmevent31_wdata (rvfi_csr_mhpmevent31_wdata) `define rvformal_csr_mhpmevent31_channel_conn(_idx), \ .rvfi_csr_mhpmevent31_rmask (rvfi_csr_mhpmevent31_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent31_wmask (rvfi_csr_mhpmevent31_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent31_rdata (rvfi_csr_mhpmevent31_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \ .rvfi_csr_mhpmevent31_wdata (rvfi_csr_mhpmevent31_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]) `define rvformal_csr_mhpmevent31_channel(_idx) \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent31_rmask = rvfi_csr_mhpmevent31_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent31_wmask = rvfi_csr_mhpmevent31_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent31_rdata = rvfi_csr_mhpmevent31_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent31_wdata = rvfi_csr_mhpmevent31_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; `define rvformal_csr_mhpmevent31_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent31_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent31_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent31_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent31_wdata) `else `define rvformal_csr_mhpmevent31_wires `define rvformal_csr_mhpmevent31_outputs `define rvformal_csr_mhpmevent31_inputs `define rvformal_csr_mhpmevent31_conn `define rvformal_csr_mhpmevent31_channel(_idx) `endif `define rvformal_csr_mhpmevent31_indices \ localparam [11:0] csr_mindex_mhpmevent31 = 12'h33F; \ localparam [11:0] csr_sindex_mhpmevent31 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmevent31 = 12'hFFF; \ `ifdef RISCV_FORMAL_CSR_MCYCLE `define rvformal_csr_mcycle_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_wdata; `define rvformal_csr_mcycle_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_wdata `define rvformal_csr_mcycle_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mcycle_rmask, \ output [64 - 1 : 0] rvfi_csr_mcycle_wmask, \ output [64 - 1 : 0] rvfi_csr_mcycle_rdata, \ output [64 - 1 : 0] rvfi_csr_mcycle_wdata `define rvformal_csr_mcycle_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_wdata `define rvformal_csr_mcycle_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mcycle_rmask, \ input [64 - 1 : 0] rvfi_csr_mcycle_wmask, \ input [64 - 1 : 0] rvfi_csr_mcycle_rdata, \ input [64 - 1 : 0] rvfi_csr_mcycle_wdata `define rvformal_csr_mcycle_conn, \ .rvfi_csr_mcycle_rmask (rvfi_csr_mcycle_rmask), \ .rvfi_csr_mcycle_wmask (rvfi_csr_mcycle_wmask), \ .rvfi_csr_mcycle_rdata (rvfi_csr_mcycle_rdata), \ .rvfi_csr_mcycle_wdata (rvfi_csr_mcycle_wdata) `define rvformal_csr_mcycle_channel_conn(_idx), \ .rvfi_csr_mcycle_rmask (rvfi_csr_mcycle_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mcycle_wmask (rvfi_csr_mcycle_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mcycle_rdata (rvfi_csr_mcycle_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mcycle_wdata (rvfi_csr_mcycle_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mcycle_conn32, \ .rvfi_csr_mcycle_rmask (rvfi_csr_mcycle_rmask[31: 0]), \ .rvfi_csr_mcycle_wmask (rvfi_csr_mcycle_wmask[31: 0]), \ .rvfi_csr_mcycle_rdata (rvfi_csr_mcycle_rdata[31: 0]), \ .rvfi_csr_mcycle_wdata (rvfi_csr_mcycle_wdata[31: 0]), \ .rvfi_csr_mcycleh_rmask (rvfi_csr_mcycle_rmask[63:32]), \ .rvfi_csr_mcycleh_wmask (rvfi_csr_mcycle_wmask[63:32]), \ .rvfi_csr_mcycleh_rdata (rvfi_csr_mcycle_rdata[63:32]), \ .rvfi_csr_mcycleh_wdata (rvfi_csr_mcycle_wdata[63:32]) `define rvformal_csr_mcycle_channel(_idx) \ wire [64 - 1 : 0] csr_mcycle_rmask = rvfi_csr_mcycle_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mcycle_wmask = rvfi_csr_mcycle_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mcycle_rdata = rvfi_csr_mcycle_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mcycle_wdata = rvfi_csr_mcycle_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mcycle_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mcycle_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mcycle_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mcycle_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mcycle_wdata) `else `define rvformal_csr_mcycle_wires `define rvformal_csr_mcycle_outputs `define rvformal_csr_mcycle_inputs `define rvformal_csr_mcycle_conn `define rvformal_csr_mcycle_conn32 `define rvformal_csr_mcycle_channel(_idx) `endif `define rvformal_csr_mcycle_indices \ localparam [11:0] csr_mindex_mcycle = 12'hB00; \ localparam [11:0] csr_sindex_mcycle = 12'hFFF; \ localparam [11:0] csr_uindex_mcycle = 12'hC00; \ localparam [11:0] csr_mindex_mcycleh = 12'hB80; \ localparam [11:0] csr_sindex_mcycleh = 12'hFFF; \ localparam [11:0] csr_uindex_mcycleh = 12'hC80; \ `ifdef RISCV_FORMAL_CSR_TIME `define rvformal_csr_time_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_wdata; `define rvformal_csr_time_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_wdata `define rvformal_csr_time_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_time_rmask, \ output [64 - 1 : 0] rvfi_csr_time_wmask, \ output [64 - 1 : 0] rvfi_csr_time_rdata, \ output [64 - 1 : 0] rvfi_csr_time_wdata `define rvformal_csr_time_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_wdata `define rvformal_csr_time_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_time_rmask, \ input [64 - 1 : 0] rvfi_csr_time_wmask, \ input [64 - 1 : 0] rvfi_csr_time_rdata, \ input [64 - 1 : 0] rvfi_csr_time_wdata `define rvformal_csr_time_conn, \ .rvfi_csr_time_rmask (rvfi_csr_time_rmask), \ .rvfi_csr_time_wmask (rvfi_csr_time_wmask), \ .rvfi_csr_time_rdata (rvfi_csr_time_rdata), \ .rvfi_csr_time_wdata (rvfi_csr_time_wdata) `define rvformal_csr_time_channel_conn(_idx), \ .rvfi_csr_time_rmask (rvfi_csr_time_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_time_wmask (rvfi_csr_time_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_time_rdata (rvfi_csr_time_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_time_wdata (rvfi_csr_time_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_time_conn32, \ .rvfi_csr_time_rmask (rvfi_csr_time_rmask[31: 0]), \ .rvfi_csr_time_wmask (rvfi_csr_time_wmask[31: 0]), \ .rvfi_csr_time_rdata (rvfi_csr_time_rdata[31: 0]), \ .rvfi_csr_time_wdata (rvfi_csr_time_wdata[31: 0]), \ .rvfi_csr_timeh_rmask (rvfi_csr_time_rmask[63:32]), \ .rvfi_csr_timeh_wmask (rvfi_csr_time_wmask[63:32]), \ .rvfi_csr_timeh_rdata (rvfi_csr_time_rdata[63:32]), \ .rvfi_csr_timeh_wdata (rvfi_csr_time_wdata[63:32]) `define rvformal_csr_time_channel(_idx) \ wire [64 - 1 : 0] csr_time_rmask = rvfi_csr_time_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_time_wmask = rvfi_csr_time_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_time_rdata = rvfi_csr_time_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_time_wdata = rvfi_csr_time_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_time_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_time_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_time_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_time_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_time_wdata) `else `define rvformal_csr_time_wires `define rvformal_csr_time_outputs `define rvformal_csr_time_inputs `define rvformal_csr_time_conn `define rvformal_csr_time_conn32 `define rvformal_csr_time_channel(_idx) `endif `define rvformal_csr_time_indices \ localparam [11:0] csr_mindex_time = 12'hFFF; \ localparam [11:0] csr_sindex_time = 12'hFFF; \ localparam [11:0] csr_uindex_time = 12'hC01; \ localparam [11:0] csr_mindex_timeh = 12'hFFF; \ localparam [11:0] csr_sindex_timeh = 12'hFFF; \ localparam [11:0] csr_uindex_timeh = 12'hC01; \ `ifdef RISCV_FORMAL_CSR_MINSTRET `define rvformal_csr_minstret_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_wdata; `define rvformal_csr_minstret_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_wdata `define rvformal_csr_minstret_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_minstret_rmask, \ output [64 - 1 : 0] rvfi_csr_minstret_wmask, \ output [64 - 1 : 0] rvfi_csr_minstret_rdata, \ output [64 - 1 : 0] rvfi_csr_minstret_wdata `define rvformal_csr_minstret_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_wdata `define rvformal_csr_minstret_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_minstret_rmask, \ input [64 - 1 : 0] rvfi_csr_minstret_wmask, \ input [64 - 1 : 0] rvfi_csr_minstret_rdata, \ input [64 - 1 : 0] rvfi_csr_minstret_wdata `define rvformal_csr_minstret_conn, \ .rvfi_csr_minstret_rmask (rvfi_csr_minstret_rmask), \ .rvfi_csr_minstret_wmask (rvfi_csr_minstret_wmask), \ .rvfi_csr_minstret_rdata (rvfi_csr_minstret_rdata), \ .rvfi_csr_minstret_wdata (rvfi_csr_minstret_wdata) `define rvformal_csr_minstret_channel_conn(_idx), \ .rvfi_csr_minstret_rmask (rvfi_csr_minstret_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_minstret_wmask (rvfi_csr_minstret_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_minstret_rdata (rvfi_csr_minstret_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_minstret_wdata (rvfi_csr_minstret_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_minstret_conn32, \ .rvfi_csr_minstret_rmask (rvfi_csr_minstret_rmask[31: 0]), \ .rvfi_csr_minstret_wmask (rvfi_csr_minstret_wmask[31: 0]), \ .rvfi_csr_minstret_rdata (rvfi_csr_minstret_rdata[31: 0]), \ .rvfi_csr_minstret_wdata (rvfi_csr_minstret_wdata[31: 0]), \ .rvfi_csr_minstreth_rmask (rvfi_csr_minstret_rmask[63:32]), \ .rvfi_csr_minstreth_wmask (rvfi_csr_minstret_wmask[63:32]), \ .rvfi_csr_minstreth_rdata (rvfi_csr_minstret_rdata[63:32]), \ .rvfi_csr_minstreth_wdata (rvfi_csr_minstret_wdata[63:32]) `define rvformal_csr_minstret_channel(_idx) \ wire [64 - 1 : 0] csr_minstret_rmask = rvfi_csr_minstret_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_minstret_wmask = rvfi_csr_minstret_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_minstret_rdata = rvfi_csr_minstret_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_minstret_wdata = rvfi_csr_minstret_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_minstret_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_minstret_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_minstret_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_minstret_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_minstret_wdata) `else `define rvformal_csr_minstret_wires `define rvformal_csr_minstret_outputs `define rvformal_csr_minstret_inputs `define rvformal_csr_minstret_conn `define rvformal_csr_minstret_conn32 `define rvformal_csr_minstret_channel(_idx) `endif `define rvformal_csr_minstret_indices \ localparam [11:0] csr_mindex_minstret = 12'hB02; \ localparam [11:0] csr_sindex_minstret = 12'hFFF; \ localparam [11:0] csr_uindex_minstret = 12'hC02; \ localparam [11:0] csr_mindex_minstreth = 12'hB82; \ localparam [11:0] csr_sindex_minstreth = 12'hFFF; \ localparam [11:0] csr_uindex_minstreth = 12'hC82; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER3 `define rvformal_csr_mhpmcounter3_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_wdata; `define rvformal_csr_mhpmcounter3_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_wdata `define rvformal_csr_mhpmcounter3_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter3_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter3_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter3_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter3_wdata `define rvformal_csr_mhpmcounter3_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_wdata `define rvformal_csr_mhpmcounter3_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter3_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter3_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter3_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter3_wdata `define rvformal_csr_mhpmcounter3_conn, \ .rvfi_csr_mhpmcounter3_rmask (rvfi_csr_mhpmcounter3_rmask), \ .rvfi_csr_mhpmcounter3_wmask (rvfi_csr_mhpmcounter3_wmask), \ .rvfi_csr_mhpmcounter3_rdata (rvfi_csr_mhpmcounter3_rdata), \ .rvfi_csr_mhpmcounter3_wdata (rvfi_csr_mhpmcounter3_wdata) `define rvformal_csr_mhpmcounter3_channel_conn(_idx), \ .rvfi_csr_mhpmcounter3_rmask (rvfi_csr_mhpmcounter3_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter3_wmask (rvfi_csr_mhpmcounter3_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter3_rdata (rvfi_csr_mhpmcounter3_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter3_wdata (rvfi_csr_mhpmcounter3_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter3_conn32, \ .rvfi_csr_mhpmcounter3_rmask (rvfi_csr_mhpmcounter3_rmask[31: 0]), \ .rvfi_csr_mhpmcounter3_wmask (rvfi_csr_mhpmcounter3_wmask[31: 0]), \ .rvfi_csr_mhpmcounter3_rdata (rvfi_csr_mhpmcounter3_rdata[31: 0]), \ .rvfi_csr_mhpmcounter3_wdata (rvfi_csr_mhpmcounter3_wdata[31: 0]), \ .rvfi_csr_mhpmcounter3h_rmask (rvfi_csr_mhpmcounter3_rmask[63:32]), \ .rvfi_csr_mhpmcounter3h_wmask (rvfi_csr_mhpmcounter3_wmask[63:32]), \ .rvfi_csr_mhpmcounter3h_rdata (rvfi_csr_mhpmcounter3_rdata[63:32]), \ .rvfi_csr_mhpmcounter3h_wdata (rvfi_csr_mhpmcounter3_wdata[63:32]) `define rvformal_csr_mhpmcounter3_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter3_rmask = rvfi_csr_mhpmcounter3_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter3_wmask = rvfi_csr_mhpmcounter3_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter3_rdata = rvfi_csr_mhpmcounter3_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter3_wdata = rvfi_csr_mhpmcounter3_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter3_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter3_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter3_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter3_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter3_wdata) `else `define rvformal_csr_mhpmcounter3_wires `define rvformal_csr_mhpmcounter3_outputs `define rvformal_csr_mhpmcounter3_inputs `define rvformal_csr_mhpmcounter3_conn `define rvformal_csr_mhpmcounter3_conn32 `define rvformal_csr_mhpmcounter3_channel(_idx) `endif `define rvformal_csr_mhpmcounter3_indices \ localparam [11:0] csr_mindex_mhpmcounter3 = 12'hB03; \ localparam [11:0] csr_sindex_mhpmcounter3 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter3 = 12'hC03; \ localparam [11:0] csr_mindex_mhpmcounter3h = 12'hB83; \ localparam [11:0] csr_sindex_mhpmcounter3h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter3h = 12'hC83; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER4 `define rvformal_csr_mhpmcounter4_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_wdata; `define rvformal_csr_mhpmcounter4_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_wdata `define rvformal_csr_mhpmcounter4_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter4_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter4_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter4_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter4_wdata `define rvformal_csr_mhpmcounter4_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_wdata `define rvformal_csr_mhpmcounter4_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter4_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter4_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter4_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter4_wdata `define rvformal_csr_mhpmcounter4_conn, \ .rvfi_csr_mhpmcounter4_rmask (rvfi_csr_mhpmcounter4_rmask), \ .rvfi_csr_mhpmcounter4_wmask (rvfi_csr_mhpmcounter4_wmask), \ .rvfi_csr_mhpmcounter4_rdata (rvfi_csr_mhpmcounter4_rdata), \ .rvfi_csr_mhpmcounter4_wdata (rvfi_csr_mhpmcounter4_wdata) `define rvformal_csr_mhpmcounter4_channel_conn(_idx), \ .rvfi_csr_mhpmcounter4_rmask (rvfi_csr_mhpmcounter4_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter4_wmask (rvfi_csr_mhpmcounter4_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter4_rdata (rvfi_csr_mhpmcounter4_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter4_wdata (rvfi_csr_mhpmcounter4_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter4_conn32, \ .rvfi_csr_mhpmcounter4_rmask (rvfi_csr_mhpmcounter4_rmask[31: 0]), \ .rvfi_csr_mhpmcounter4_wmask (rvfi_csr_mhpmcounter4_wmask[31: 0]), \ .rvfi_csr_mhpmcounter4_rdata (rvfi_csr_mhpmcounter4_rdata[31: 0]), \ .rvfi_csr_mhpmcounter4_wdata (rvfi_csr_mhpmcounter4_wdata[31: 0]), \ .rvfi_csr_mhpmcounter4h_rmask (rvfi_csr_mhpmcounter4_rmask[63:32]), \ .rvfi_csr_mhpmcounter4h_wmask (rvfi_csr_mhpmcounter4_wmask[63:32]), \ .rvfi_csr_mhpmcounter4h_rdata (rvfi_csr_mhpmcounter4_rdata[63:32]), \ .rvfi_csr_mhpmcounter4h_wdata (rvfi_csr_mhpmcounter4_wdata[63:32]) `define rvformal_csr_mhpmcounter4_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter4_rmask = rvfi_csr_mhpmcounter4_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter4_wmask = rvfi_csr_mhpmcounter4_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter4_rdata = rvfi_csr_mhpmcounter4_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter4_wdata = rvfi_csr_mhpmcounter4_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter4_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter4_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter4_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter4_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter4_wdata) `else `define rvformal_csr_mhpmcounter4_wires `define rvformal_csr_mhpmcounter4_outputs `define rvformal_csr_mhpmcounter4_inputs `define rvformal_csr_mhpmcounter4_conn `define rvformal_csr_mhpmcounter4_conn32 `define rvformal_csr_mhpmcounter4_channel(_idx) `endif `define rvformal_csr_mhpmcounter4_indices \ localparam [11:0] csr_mindex_mhpmcounter4 = 12'hB04; \ localparam [11:0] csr_sindex_mhpmcounter4 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter4 = 12'hC04; \ localparam [11:0] csr_mindex_mhpmcounter4h = 12'hB84; \ localparam [11:0] csr_sindex_mhpmcounter4h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter4h = 12'hC84; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER5 `define rvformal_csr_mhpmcounter5_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_wdata; `define rvformal_csr_mhpmcounter5_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_wdata `define rvformal_csr_mhpmcounter5_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter5_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter5_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter5_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter5_wdata `define rvformal_csr_mhpmcounter5_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_wdata `define rvformal_csr_mhpmcounter5_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter5_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter5_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter5_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter5_wdata `define rvformal_csr_mhpmcounter5_conn, \ .rvfi_csr_mhpmcounter5_rmask (rvfi_csr_mhpmcounter5_rmask), \ .rvfi_csr_mhpmcounter5_wmask (rvfi_csr_mhpmcounter5_wmask), \ .rvfi_csr_mhpmcounter5_rdata (rvfi_csr_mhpmcounter5_rdata), \ .rvfi_csr_mhpmcounter5_wdata (rvfi_csr_mhpmcounter5_wdata) `define rvformal_csr_mhpmcounter5_channel_conn(_idx), \ .rvfi_csr_mhpmcounter5_rmask (rvfi_csr_mhpmcounter5_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter5_wmask (rvfi_csr_mhpmcounter5_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter5_rdata (rvfi_csr_mhpmcounter5_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter5_wdata (rvfi_csr_mhpmcounter5_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter5_conn32, \ .rvfi_csr_mhpmcounter5_rmask (rvfi_csr_mhpmcounter5_rmask[31: 0]), \ .rvfi_csr_mhpmcounter5_wmask (rvfi_csr_mhpmcounter5_wmask[31: 0]), \ .rvfi_csr_mhpmcounter5_rdata (rvfi_csr_mhpmcounter5_rdata[31: 0]), \ .rvfi_csr_mhpmcounter5_wdata (rvfi_csr_mhpmcounter5_wdata[31: 0]), \ .rvfi_csr_mhpmcounter5h_rmask (rvfi_csr_mhpmcounter5_rmask[63:32]), \ .rvfi_csr_mhpmcounter5h_wmask (rvfi_csr_mhpmcounter5_wmask[63:32]), \ .rvfi_csr_mhpmcounter5h_rdata (rvfi_csr_mhpmcounter5_rdata[63:32]), \ .rvfi_csr_mhpmcounter5h_wdata (rvfi_csr_mhpmcounter5_wdata[63:32]) `define rvformal_csr_mhpmcounter5_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter5_rmask = rvfi_csr_mhpmcounter5_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter5_wmask = rvfi_csr_mhpmcounter5_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter5_rdata = rvfi_csr_mhpmcounter5_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter5_wdata = rvfi_csr_mhpmcounter5_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter5_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter5_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter5_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter5_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter5_wdata) `else `define rvformal_csr_mhpmcounter5_wires `define rvformal_csr_mhpmcounter5_outputs `define rvformal_csr_mhpmcounter5_inputs `define rvformal_csr_mhpmcounter5_conn `define rvformal_csr_mhpmcounter5_conn32 `define rvformal_csr_mhpmcounter5_channel(_idx) `endif `define rvformal_csr_mhpmcounter5_indices \ localparam [11:0] csr_mindex_mhpmcounter5 = 12'hB05; \ localparam [11:0] csr_sindex_mhpmcounter5 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter5 = 12'hC05; \ localparam [11:0] csr_mindex_mhpmcounter5h = 12'hB85; \ localparam [11:0] csr_sindex_mhpmcounter5h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter5h = 12'hC85; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER6 `define rvformal_csr_mhpmcounter6_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_wdata; `define rvformal_csr_mhpmcounter6_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_wdata `define rvformal_csr_mhpmcounter6_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter6_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter6_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter6_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter6_wdata `define rvformal_csr_mhpmcounter6_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_wdata `define rvformal_csr_mhpmcounter6_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter6_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter6_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter6_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter6_wdata `define rvformal_csr_mhpmcounter6_conn, \ .rvfi_csr_mhpmcounter6_rmask (rvfi_csr_mhpmcounter6_rmask), \ .rvfi_csr_mhpmcounter6_wmask (rvfi_csr_mhpmcounter6_wmask), \ .rvfi_csr_mhpmcounter6_rdata (rvfi_csr_mhpmcounter6_rdata), \ .rvfi_csr_mhpmcounter6_wdata (rvfi_csr_mhpmcounter6_wdata) `define rvformal_csr_mhpmcounter6_channel_conn(_idx), \ .rvfi_csr_mhpmcounter6_rmask (rvfi_csr_mhpmcounter6_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter6_wmask (rvfi_csr_mhpmcounter6_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter6_rdata (rvfi_csr_mhpmcounter6_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter6_wdata (rvfi_csr_mhpmcounter6_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter6_conn32, \ .rvfi_csr_mhpmcounter6_rmask (rvfi_csr_mhpmcounter6_rmask[31: 0]), \ .rvfi_csr_mhpmcounter6_wmask (rvfi_csr_mhpmcounter6_wmask[31: 0]), \ .rvfi_csr_mhpmcounter6_rdata (rvfi_csr_mhpmcounter6_rdata[31: 0]), \ .rvfi_csr_mhpmcounter6_wdata (rvfi_csr_mhpmcounter6_wdata[31: 0]), \ .rvfi_csr_mhpmcounter6h_rmask (rvfi_csr_mhpmcounter6_rmask[63:32]), \ .rvfi_csr_mhpmcounter6h_wmask (rvfi_csr_mhpmcounter6_wmask[63:32]), \ .rvfi_csr_mhpmcounter6h_rdata (rvfi_csr_mhpmcounter6_rdata[63:32]), \ .rvfi_csr_mhpmcounter6h_wdata (rvfi_csr_mhpmcounter6_wdata[63:32]) `define rvformal_csr_mhpmcounter6_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter6_rmask = rvfi_csr_mhpmcounter6_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter6_wmask = rvfi_csr_mhpmcounter6_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter6_rdata = rvfi_csr_mhpmcounter6_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter6_wdata = rvfi_csr_mhpmcounter6_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter6_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter6_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter6_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter6_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter6_wdata) `else `define rvformal_csr_mhpmcounter6_wires `define rvformal_csr_mhpmcounter6_outputs `define rvformal_csr_mhpmcounter6_inputs `define rvformal_csr_mhpmcounter6_conn `define rvformal_csr_mhpmcounter6_conn32 `define rvformal_csr_mhpmcounter6_channel(_idx) `endif `define rvformal_csr_mhpmcounter6_indices \ localparam [11:0] csr_mindex_mhpmcounter6 = 12'hB06; \ localparam [11:0] csr_sindex_mhpmcounter6 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter6 = 12'hC06; \ localparam [11:0] csr_mindex_mhpmcounter6h = 12'hB86; \ localparam [11:0] csr_sindex_mhpmcounter6h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter6h = 12'hC86; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER7 `define rvformal_csr_mhpmcounter7_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_wdata; `define rvformal_csr_mhpmcounter7_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_wdata `define rvformal_csr_mhpmcounter7_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter7_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter7_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter7_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter7_wdata `define rvformal_csr_mhpmcounter7_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_wdata `define rvformal_csr_mhpmcounter7_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter7_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter7_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter7_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter7_wdata `define rvformal_csr_mhpmcounter7_conn, \ .rvfi_csr_mhpmcounter7_rmask (rvfi_csr_mhpmcounter7_rmask), \ .rvfi_csr_mhpmcounter7_wmask (rvfi_csr_mhpmcounter7_wmask), \ .rvfi_csr_mhpmcounter7_rdata (rvfi_csr_mhpmcounter7_rdata), \ .rvfi_csr_mhpmcounter7_wdata (rvfi_csr_mhpmcounter7_wdata) `define rvformal_csr_mhpmcounter7_channel_conn(_idx), \ .rvfi_csr_mhpmcounter7_rmask (rvfi_csr_mhpmcounter7_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter7_wmask (rvfi_csr_mhpmcounter7_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter7_rdata (rvfi_csr_mhpmcounter7_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter7_wdata (rvfi_csr_mhpmcounter7_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter7_conn32, \ .rvfi_csr_mhpmcounter7_rmask (rvfi_csr_mhpmcounter7_rmask[31: 0]), \ .rvfi_csr_mhpmcounter7_wmask (rvfi_csr_mhpmcounter7_wmask[31: 0]), \ .rvfi_csr_mhpmcounter7_rdata (rvfi_csr_mhpmcounter7_rdata[31: 0]), \ .rvfi_csr_mhpmcounter7_wdata (rvfi_csr_mhpmcounter7_wdata[31: 0]), \ .rvfi_csr_mhpmcounter7h_rmask (rvfi_csr_mhpmcounter7_rmask[63:32]), \ .rvfi_csr_mhpmcounter7h_wmask (rvfi_csr_mhpmcounter7_wmask[63:32]), \ .rvfi_csr_mhpmcounter7h_rdata (rvfi_csr_mhpmcounter7_rdata[63:32]), \ .rvfi_csr_mhpmcounter7h_wdata (rvfi_csr_mhpmcounter7_wdata[63:32]) `define rvformal_csr_mhpmcounter7_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter7_rmask = rvfi_csr_mhpmcounter7_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter7_wmask = rvfi_csr_mhpmcounter7_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter7_rdata = rvfi_csr_mhpmcounter7_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter7_wdata = rvfi_csr_mhpmcounter7_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter7_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter7_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter7_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter7_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter7_wdata) `else `define rvformal_csr_mhpmcounter7_wires `define rvformal_csr_mhpmcounter7_outputs `define rvformal_csr_mhpmcounter7_inputs `define rvformal_csr_mhpmcounter7_conn `define rvformal_csr_mhpmcounter7_conn32 `define rvformal_csr_mhpmcounter7_channel(_idx) `endif `define rvformal_csr_mhpmcounter7_indices \ localparam [11:0] csr_mindex_mhpmcounter7 = 12'hB07; \ localparam [11:0] csr_sindex_mhpmcounter7 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter7 = 12'hC07; \ localparam [11:0] csr_mindex_mhpmcounter7h = 12'hB87; \ localparam [11:0] csr_sindex_mhpmcounter7h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter7h = 12'hC87; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER8 `define rvformal_csr_mhpmcounter8_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_wdata; `define rvformal_csr_mhpmcounter8_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_wdata `define rvformal_csr_mhpmcounter8_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter8_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter8_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter8_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter8_wdata `define rvformal_csr_mhpmcounter8_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_wdata `define rvformal_csr_mhpmcounter8_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter8_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter8_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter8_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter8_wdata `define rvformal_csr_mhpmcounter8_conn, \ .rvfi_csr_mhpmcounter8_rmask (rvfi_csr_mhpmcounter8_rmask), \ .rvfi_csr_mhpmcounter8_wmask (rvfi_csr_mhpmcounter8_wmask), \ .rvfi_csr_mhpmcounter8_rdata (rvfi_csr_mhpmcounter8_rdata), \ .rvfi_csr_mhpmcounter8_wdata (rvfi_csr_mhpmcounter8_wdata) `define rvformal_csr_mhpmcounter8_channel_conn(_idx), \ .rvfi_csr_mhpmcounter8_rmask (rvfi_csr_mhpmcounter8_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter8_wmask (rvfi_csr_mhpmcounter8_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter8_rdata (rvfi_csr_mhpmcounter8_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter8_wdata (rvfi_csr_mhpmcounter8_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter8_conn32, \ .rvfi_csr_mhpmcounter8_rmask (rvfi_csr_mhpmcounter8_rmask[31: 0]), \ .rvfi_csr_mhpmcounter8_wmask (rvfi_csr_mhpmcounter8_wmask[31: 0]), \ .rvfi_csr_mhpmcounter8_rdata (rvfi_csr_mhpmcounter8_rdata[31: 0]), \ .rvfi_csr_mhpmcounter8_wdata (rvfi_csr_mhpmcounter8_wdata[31: 0]), \ .rvfi_csr_mhpmcounter8h_rmask (rvfi_csr_mhpmcounter8_rmask[63:32]), \ .rvfi_csr_mhpmcounter8h_wmask (rvfi_csr_mhpmcounter8_wmask[63:32]), \ .rvfi_csr_mhpmcounter8h_rdata (rvfi_csr_mhpmcounter8_rdata[63:32]), \ .rvfi_csr_mhpmcounter8h_wdata (rvfi_csr_mhpmcounter8_wdata[63:32]) `define rvformal_csr_mhpmcounter8_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter8_rmask = rvfi_csr_mhpmcounter8_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter8_wmask = rvfi_csr_mhpmcounter8_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter8_rdata = rvfi_csr_mhpmcounter8_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter8_wdata = rvfi_csr_mhpmcounter8_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter8_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter8_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter8_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter8_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter8_wdata) `else `define rvformal_csr_mhpmcounter8_wires `define rvformal_csr_mhpmcounter8_outputs `define rvformal_csr_mhpmcounter8_inputs `define rvformal_csr_mhpmcounter8_conn `define rvformal_csr_mhpmcounter8_conn32 `define rvformal_csr_mhpmcounter8_channel(_idx) `endif `define rvformal_csr_mhpmcounter8_indices \ localparam [11:0] csr_mindex_mhpmcounter8 = 12'hB08; \ localparam [11:0] csr_sindex_mhpmcounter8 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter8 = 12'hC08; \ localparam [11:0] csr_mindex_mhpmcounter8h = 12'hB88; \ localparam [11:0] csr_sindex_mhpmcounter8h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter8h = 12'hC88; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER9 `define rvformal_csr_mhpmcounter9_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_wdata; `define rvformal_csr_mhpmcounter9_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_wdata `define rvformal_csr_mhpmcounter9_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter9_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter9_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter9_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter9_wdata `define rvformal_csr_mhpmcounter9_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_wdata `define rvformal_csr_mhpmcounter9_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter9_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter9_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter9_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter9_wdata `define rvformal_csr_mhpmcounter9_conn, \ .rvfi_csr_mhpmcounter9_rmask (rvfi_csr_mhpmcounter9_rmask), \ .rvfi_csr_mhpmcounter9_wmask (rvfi_csr_mhpmcounter9_wmask), \ .rvfi_csr_mhpmcounter9_rdata (rvfi_csr_mhpmcounter9_rdata), \ .rvfi_csr_mhpmcounter9_wdata (rvfi_csr_mhpmcounter9_wdata) `define rvformal_csr_mhpmcounter9_channel_conn(_idx), \ .rvfi_csr_mhpmcounter9_rmask (rvfi_csr_mhpmcounter9_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter9_wmask (rvfi_csr_mhpmcounter9_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter9_rdata (rvfi_csr_mhpmcounter9_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter9_wdata (rvfi_csr_mhpmcounter9_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter9_conn32, \ .rvfi_csr_mhpmcounter9_rmask (rvfi_csr_mhpmcounter9_rmask[31: 0]), \ .rvfi_csr_mhpmcounter9_wmask (rvfi_csr_mhpmcounter9_wmask[31: 0]), \ .rvfi_csr_mhpmcounter9_rdata (rvfi_csr_mhpmcounter9_rdata[31: 0]), \ .rvfi_csr_mhpmcounter9_wdata (rvfi_csr_mhpmcounter9_wdata[31: 0]), \ .rvfi_csr_mhpmcounter9h_rmask (rvfi_csr_mhpmcounter9_rmask[63:32]), \ .rvfi_csr_mhpmcounter9h_wmask (rvfi_csr_mhpmcounter9_wmask[63:32]), \ .rvfi_csr_mhpmcounter9h_rdata (rvfi_csr_mhpmcounter9_rdata[63:32]), \ .rvfi_csr_mhpmcounter9h_wdata (rvfi_csr_mhpmcounter9_wdata[63:32]) `define rvformal_csr_mhpmcounter9_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter9_rmask = rvfi_csr_mhpmcounter9_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter9_wmask = rvfi_csr_mhpmcounter9_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter9_rdata = rvfi_csr_mhpmcounter9_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter9_wdata = rvfi_csr_mhpmcounter9_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter9_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter9_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter9_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter9_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter9_wdata) `else `define rvformal_csr_mhpmcounter9_wires `define rvformal_csr_mhpmcounter9_outputs `define rvformal_csr_mhpmcounter9_inputs `define rvformal_csr_mhpmcounter9_conn `define rvformal_csr_mhpmcounter9_conn32 `define rvformal_csr_mhpmcounter9_channel(_idx) `endif `define rvformal_csr_mhpmcounter9_indices \ localparam [11:0] csr_mindex_mhpmcounter9 = 12'hB09; \ localparam [11:0] csr_sindex_mhpmcounter9 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter9 = 12'hC09; \ localparam [11:0] csr_mindex_mhpmcounter9h = 12'hB89; \ localparam [11:0] csr_sindex_mhpmcounter9h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter9h = 12'hC89; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER10 `define rvformal_csr_mhpmcounter10_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_wdata; `define rvformal_csr_mhpmcounter10_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_wdata `define rvformal_csr_mhpmcounter10_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter10_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter10_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter10_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter10_wdata `define rvformal_csr_mhpmcounter10_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_wdata `define rvformal_csr_mhpmcounter10_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter10_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter10_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter10_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter10_wdata `define rvformal_csr_mhpmcounter10_conn, \ .rvfi_csr_mhpmcounter10_rmask (rvfi_csr_mhpmcounter10_rmask), \ .rvfi_csr_mhpmcounter10_wmask (rvfi_csr_mhpmcounter10_wmask), \ .rvfi_csr_mhpmcounter10_rdata (rvfi_csr_mhpmcounter10_rdata), \ .rvfi_csr_mhpmcounter10_wdata (rvfi_csr_mhpmcounter10_wdata) `define rvformal_csr_mhpmcounter10_channel_conn(_idx), \ .rvfi_csr_mhpmcounter10_rmask (rvfi_csr_mhpmcounter10_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter10_wmask (rvfi_csr_mhpmcounter10_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter10_rdata (rvfi_csr_mhpmcounter10_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter10_wdata (rvfi_csr_mhpmcounter10_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter10_conn32, \ .rvfi_csr_mhpmcounter10_rmask (rvfi_csr_mhpmcounter10_rmask[31: 0]), \ .rvfi_csr_mhpmcounter10_wmask (rvfi_csr_mhpmcounter10_wmask[31: 0]), \ .rvfi_csr_mhpmcounter10_rdata (rvfi_csr_mhpmcounter10_rdata[31: 0]), \ .rvfi_csr_mhpmcounter10_wdata (rvfi_csr_mhpmcounter10_wdata[31: 0]), \ .rvfi_csr_mhpmcounter10h_rmask (rvfi_csr_mhpmcounter10_rmask[63:32]), \ .rvfi_csr_mhpmcounter10h_wmask (rvfi_csr_mhpmcounter10_wmask[63:32]), \ .rvfi_csr_mhpmcounter10h_rdata (rvfi_csr_mhpmcounter10_rdata[63:32]), \ .rvfi_csr_mhpmcounter10h_wdata (rvfi_csr_mhpmcounter10_wdata[63:32]) `define rvformal_csr_mhpmcounter10_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter10_rmask = rvfi_csr_mhpmcounter10_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter10_wmask = rvfi_csr_mhpmcounter10_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter10_rdata = rvfi_csr_mhpmcounter10_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter10_wdata = rvfi_csr_mhpmcounter10_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter10_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter10_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter10_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter10_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter10_wdata) `else `define rvformal_csr_mhpmcounter10_wires `define rvformal_csr_mhpmcounter10_outputs `define rvformal_csr_mhpmcounter10_inputs `define rvformal_csr_mhpmcounter10_conn `define rvformal_csr_mhpmcounter10_conn32 `define rvformal_csr_mhpmcounter10_channel(_idx) `endif `define rvformal_csr_mhpmcounter10_indices \ localparam [11:0] csr_mindex_mhpmcounter10 = 12'hB0A; \ localparam [11:0] csr_sindex_mhpmcounter10 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter10 = 12'hC0A; \ localparam [11:0] csr_mindex_mhpmcounter10h = 12'hB8A; \ localparam [11:0] csr_sindex_mhpmcounter10h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter10h = 12'hC8A; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER11 `define rvformal_csr_mhpmcounter11_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_wdata; `define rvformal_csr_mhpmcounter11_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_wdata `define rvformal_csr_mhpmcounter11_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter11_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter11_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter11_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter11_wdata `define rvformal_csr_mhpmcounter11_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_wdata `define rvformal_csr_mhpmcounter11_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter11_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter11_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter11_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter11_wdata `define rvformal_csr_mhpmcounter11_conn, \ .rvfi_csr_mhpmcounter11_rmask (rvfi_csr_mhpmcounter11_rmask), \ .rvfi_csr_mhpmcounter11_wmask (rvfi_csr_mhpmcounter11_wmask), \ .rvfi_csr_mhpmcounter11_rdata (rvfi_csr_mhpmcounter11_rdata), \ .rvfi_csr_mhpmcounter11_wdata (rvfi_csr_mhpmcounter11_wdata) `define rvformal_csr_mhpmcounter11_channel_conn(_idx), \ .rvfi_csr_mhpmcounter11_rmask (rvfi_csr_mhpmcounter11_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter11_wmask (rvfi_csr_mhpmcounter11_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter11_rdata (rvfi_csr_mhpmcounter11_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter11_wdata (rvfi_csr_mhpmcounter11_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter11_conn32, \ .rvfi_csr_mhpmcounter11_rmask (rvfi_csr_mhpmcounter11_rmask[31: 0]), \ .rvfi_csr_mhpmcounter11_wmask (rvfi_csr_mhpmcounter11_wmask[31: 0]), \ .rvfi_csr_mhpmcounter11_rdata (rvfi_csr_mhpmcounter11_rdata[31: 0]), \ .rvfi_csr_mhpmcounter11_wdata (rvfi_csr_mhpmcounter11_wdata[31: 0]), \ .rvfi_csr_mhpmcounter11h_rmask (rvfi_csr_mhpmcounter11_rmask[63:32]), \ .rvfi_csr_mhpmcounter11h_wmask (rvfi_csr_mhpmcounter11_wmask[63:32]), \ .rvfi_csr_mhpmcounter11h_rdata (rvfi_csr_mhpmcounter11_rdata[63:32]), \ .rvfi_csr_mhpmcounter11h_wdata (rvfi_csr_mhpmcounter11_wdata[63:32]) `define rvformal_csr_mhpmcounter11_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter11_rmask = rvfi_csr_mhpmcounter11_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter11_wmask = rvfi_csr_mhpmcounter11_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter11_rdata = rvfi_csr_mhpmcounter11_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter11_wdata = rvfi_csr_mhpmcounter11_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter11_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter11_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter11_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter11_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter11_wdata) `else `define rvformal_csr_mhpmcounter11_wires `define rvformal_csr_mhpmcounter11_outputs `define rvformal_csr_mhpmcounter11_inputs `define rvformal_csr_mhpmcounter11_conn `define rvformal_csr_mhpmcounter11_conn32 `define rvformal_csr_mhpmcounter11_channel(_idx) `endif `define rvformal_csr_mhpmcounter11_indices \ localparam [11:0] csr_mindex_mhpmcounter11 = 12'hB0B; \ localparam [11:0] csr_sindex_mhpmcounter11 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter11 = 12'hC0B; \ localparam [11:0] csr_mindex_mhpmcounter11h = 12'hB8B; \ localparam [11:0] csr_sindex_mhpmcounter11h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter11h = 12'hC8B; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER12 `define rvformal_csr_mhpmcounter12_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_wdata; `define rvformal_csr_mhpmcounter12_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_wdata `define rvformal_csr_mhpmcounter12_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter12_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter12_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter12_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter12_wdata `define rvformal_csr_mhpmcounter12_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_wdata `define rvformal_csr_mhpmcounter12_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter12_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter12_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter12_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter12_wdata `define rvformal_csr_mhpmcounter12_conn, \ .rvfi_csr_mhpmcounter12_rmask (rvfi_csr_mhpmcounter12_rmask), \ .rvfi_csr_mhpmcounter12_wmask (rvfi_csr_mhpmcounter12_wmask), \ .rvfi_csr_mhpmcounter12_rdata (rvfi_csr_mhpmcounter12_rdata), \ .rvfi_csr_mhpmcounter12_wdata (rvfi_csr_mhpmcounter12_wdata) `define rvformal_csr_mhpmcounter12_channel_conn(_idx), \ .rvfi_csr_mhpmcounter12_rmask (rvfi_csr_mhpmcounter12_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter12_wmask (rvfi_csr_mhpmcounter12_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter12_rdata (rvfi_csr_mhpmcounter12_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter12_wdata (rvfi_csr_mhpmcounter12_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter12_conn32, \ .rvfi_csr_mhpmcounter12_rmask (rvfi_csr_mhpmcounter12_rmask[31: 0]), \ .rvfi_csr_mhpmcounter12_wmask (rvfi_csr_mhpmcounter12_wmask[31: 0]), \ .rvfi_csr_mhpmcounter12_rdata (rvfi_csr_mhpmcounter12_rdata[31: 0]), \ .rvfi_csr_mhpmcounter12_wdata (rvfi_csr_mhpmcounter12_wdata[31: 0]), \ .rvfi_csr_mhpmcounter12h_rmask (rvfi_csr_mhpmcounter12_rmask[63:32]), \ .rvfi_csr_mhpmcounter12h_wmask (rvfi_csr_mhpmcounter12_wmask[63:32]), \ .rvfi_csr_mhpmcounter12h_rdata (rvfi_csr_mhpmcounter12_rdata[63:32]), \ .rvfi_csr_mhpmcounter12h_wdata (rvfi_csr_mhpmcounter12_wdata[63:32]) `define rvformal_csr_mhpmcounter12_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter12_rmask = rvfi_csr_mhpmcounter12_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter12_wmask = rvfi_csr_mhpmcounter12_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter12_rdata = rvfi_csr_mhpmcounter12_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter12_wdata = rvfi_csr_mhpmcounter12_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter12_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter12_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter12_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter12_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter12_wdata) `else `define rvformal_csr_mhpmcounter12_wires `define rvformal_csr_mhpmcounter12_outputs `define rvformal_csr_mhpmcounter12_inputs `define rvformal_csr_mhpmcounter12_conn `define rvformal_csr_mhpmcounter12_conn32 `define rvformal_csr_mhpmcounter12_channel(_idx) `endif `define rvformal_csr_mhpmcounter12_indices \ localparam [11:0] csr_mindex_mhpmcounter12 = 12'hB0C; \ localparam [11:0] csr_sindex_mhpmcounter12 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter12 = 12'hC0C; \ localparam [11:0] csr_mindex_mhpmcounter12h = 12'hB8C; \ localparam [11:0] csr_sindex_mhpmcounter12h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter12h = 12'hC8C; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER13 `define rvformal_csr_mhpmcounter13_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_wdata; `define rvformal_csr_mhpmcounter13_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_wdata `define rvformal_csr_mhpmcounter13_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter13_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter13_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter13_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter13_wdata `define rvformal_csr_mhpmcounter13_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_wdata `define rvformal_csr_mhpmcounter13_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter13_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter13_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter13_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter13_wdata `define rvformal_csr_mhpmcounter13_conn, \ .rvfi_csr_mhpmcounter13_rmask (rvfi_csr_mhpmcounter13_rmask), \ .rvfi_csr_mhpmcounter13_wmask (rvfi_csr_mhpmcounter13_wmask), \ .rvfi_csr_mhpmcounter13_rdata (rvfi_csr_mhpmcounter13_rdata), \ .rvfi_csr_mhpmcounter13_wdata (rvfi_csr_mhpmcounter13_wdata) `define rvformal_csr_mhpmcounter13_channel_conn(_idx), \ .rvfi_csr_mhpmcounter13_rmask (rvfi_csr_mhpmcounter13_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter13_wmask (rvfi_csr_mhpmcounter13_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter13_rdata (rvfi_csr_mhpmcounter13_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter13_wdata (rvfi_csr_mhpmcounter13_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter13_conn32, \ .rvfi_csr_mhpmcounter13_rmask (rvfi_csr_mhpmcounter13_rmask[31: 0]), \ .rvfi_csr_mhpmcounter13_wmask (rvfi_csr_mhpmcounter13_wmask[31: 0]), \ .rvfi_csr_mhpmcounter13_rdata (rvfi_csr_mhpmcounter13_rdata[31: 0]), \ .rvfi_csr_mhpmcounter13_wdata (rvfi_csr_mhpmcounter13_wdata[31: 0]), \ .rvfi_csr_mhpmcounter13h_rmask (rvfi_csr_mhpmcounter13_rmask[63:32]), \ .rvfi_csr_mhpmcounter13h_wmask (rvfi_csr_mhpmcounter13_wmask[63:32]), \ .rvfi_csr_mhpmcounter13h_rdata (rvfi_csr_mhpmcounter13_rdata[63:32]), \ .rvfi_csr_mhpmcounter13h_wdata (rvfi_csr_mhpmcounter13_wdata[63:32]) `define rvformal_csr_mhpmcounter13_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter13_rmask = rvfi_csr_mhpmcounter13_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter13_wmask = rvfi_csr_mhpmcounter13_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter13_rdata = rvfi_csr_mhpmcounter13_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter13_wdata = rvfi_csr_mhpmcounter13_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter13_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter13_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter13_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter13_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter13_wdata) `else `define rvformal_csr_mhpmcounter13_wires `define rvformal_csr_mhpmcounter13_outputs `define rvformal_csr_mhpmcounter13_inputs `define rvformal_csr_mhpmcounter13_conn `define rvformal_csr_mhpmcounter13_conn32 `define rvformal_csr_mhpmcounter13_channel(_idx) `endif `define rvformal_csr_mhpmcounter13_indices \ localparam [11:0] csr_mindex_mhpmcounter13 = 12'hB0D; \ localparam [11:0] csr_sindex_mhpmcounter13 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter13 = 12'hC0D; \ localparam [11:0] csr_mindex_mhpmcounter13h = 12'hB8D; \ localparam [11:0] csr_sindex_mhpmcounter13h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter13h = 12'hC8D; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER14 `define rvformal_csr_mhpmcounter14_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_wdata; `define rvformal_csr_mhpmcounter14_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_wdata `define rvformal_csr_mhpmcounter14_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter14_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter14_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter14_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter14_wdata `define rvformal_csr_mhpmcounter14_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_wdata `define rvformal_csr_mhpmcounter14_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter14_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter14_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter14_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter14_wdata `define rvformal_csr_mhpmcounter14_conn, \ .rvfi_csr_mhpmcounter14_rmask (rvfi_csr_mhpmcounter14_rmask), \ .rvfi_csr_mhpmcounter14_wmask (rvfi_csr_mhpmcounter14_wmask), \ .rvfi_csr_mhpmcounter14_rdata (rvfi_csr_mhpmcounter14_rdata), \ .rvfi_csr_mhpmcounter14_wdata (rvfi_csr_mhpmcounter14_wdata) `define rvformal_csr_mhpmcounter14_channel_conn(_idx), \ .rvfi_csr_mhpmcounter14_rmask (rvfi_csr_mhpmcounter14_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter14_wmask (rvfi_csr_mhpmcounter14_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter14_rdata (rvfi_csr_mhpmcounter14_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter14_wdata (rvfi_csr_mhpmcounter14_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter14_conn32, \ .rvfi_csr_mhpmcounter14_rmask (rvfi_csr_mhpmcounter14_rmask[31: 0]), \ .rvfi_csr_mhpmcounter14_wmask (rvfi_csr_mhpmcounter14_wmask[31: 0]), \ .rvfi_csr_mhpmcounter14_rdata (rvfi_csr_mhpmcounter14_rdata[31: 0]), \ .rvfi_csr_mhpmcounter14_wdata (rvfi_csr_mhpmcounter14_wdata[31: 0]), \ .rvfi_csr_mhpmcounter14h_rmask (rvfi_csr_mhpmcounter14_rmask[63:32]), \ .rvfi_csr_mhpmcounter14h_wmask (rvfi_csr_mhpmcounter14_wmask[63:32]), \ .rvfi_csr_mhpmcounter14h_rdata (rvfi_csr_mhpmcounter14_rdata[63:32]), \ .rvfi_csr_mhpmcounter14h_wdata (rvfi_csr_mhpmcounter14_wdata[63:32]) `define rvformal_csr_mhpmcounter14_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter14_rmask = rvfi_csr_mhpmcounter14_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter14_wmask = rvfi_csr_mhpmcounter14_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter14_rdata = rvfi_csr_mhpmcounter14_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter14_wdata = rvfi_csr_mhpmcounter14_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter14_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter14_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter14_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter14_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter14_wdata) `else `define rvformal_csr_mhpmcounter14_wires `define rvformal_csr_mhpmcounter14_outputs `define rvformal_csr_mhpmcounter14_inputs `define rvformal_csr_mhpmcounter14_conn `define rvformal_csr_mhpmcounter14_conn32 `define rvformal_csr_mhpmcounter14_channel(_idx) `endif `define rvformal_csr_mhpmcounter14_indices \ localparam [11:0] csr_mindex_mhpmcounter14 = 12'hB0E; \ localparam [11:0] csr_sindex_mhpmcounter14 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter14 = 12'hC0E; \ localparam [11:0] csr_mindex_mhpmcounter14h = 12'hB8E; \ localparam [11:0] csr_sindex_mhpmcounter14h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter14h = 12'hC8E; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER15 `define rvformal_csr_mhpmcounter15_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_wdata; `define rvformal_csr_mhpmcounter15_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_wdata `define rvformal_csr_mhpmcounter15_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter15_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter15_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter15_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter15_wdata `define rvformal_csr_mhpmcounter15_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_wdata `define rvformal_csr_mhpmcounter15_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter15_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter15_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter15_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter15_wdata `define rvformal_csr_mhpmcounter15_conn, \ .rvfi_csr_mhpmcounter15_rmask (rvfi_csr_mhpmcounter15_rmask), \ .rvfi_csr_mhpmcounter15_wmask (rvfi_csr_mhpmcounter15_wmask), \ .rvfi_csr_mhpmcounter15_rdata (rvfi_csr_mhpmcounter15_rdata), \ .rvfi_csr_mhpmcounter15_wdata (rvfi_csr_mhpmcounter15_wdata) `define rvformal_csr_mhpmcounter15_channel_conn(_idx), \ .rvfi_csr_mhpmcounter15_rmask (rvfi_csr_mhpmcounter15_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter15_wmask (rvfi_csr_mhpmcounter15_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter15_rdata (rvfi_csr_mhpmcounter15_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter15_wdata (rvfi_csr_mhpmcounter15_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter15_conn32, \ .rvfi_csr_mhpmcounter15_rmask (rvfi_csr_mhpmcounter15_rmask[31: 0]), \ .rvfi_csr_mhpmcounter15_wmask (rvfi_csr_mhpmcounter15_wmask[31: 0]), \ .rvfi_csr_mhpmcounter15_rdata (rvfi_csr_mhpmcounter15_rdata[31: 0]), \ .rvfi_csr_mhpmcounter15_wdata (rvfi_csr_mhpmcounter15_wdata[31: 0]), \ .rvfi_csr_mhpmcounter15h_rmask (rvfi_csr_mhpmcounter15_rmask[63:32]), \ .rvfi_csr_mhpmcounter15h_wmask (rvfi_csr_mhpmcounter15_wmask[63:32]), \ .rvfi_csr_mhpmcounter15h_rdata (rvfi_csr_mhpmcounter15_rdata[63:32]), \ .rvfi_csr_mhpmcounter15h_wdata (rvfi_csr_mhpmcounter15_wdata[63:32]) `define rvformal_csr_mhpmcounter15_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter15_rmask = rvfi_csr_mhpmcounter15_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter15_wmask = rvfi_csr_mhpmcounter15_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter15_rdata = rvfi_csr_mhpmcounter15_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter15_wdata = rvfi_csr_mhpmcounter15_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter15_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter15_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter15_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter15_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter15_wdata) `else `define rvformal_csr_mhpmcounter15_wires `define rvformal_csr_mhpmcounter15_outputs `define rvformal_csr_mhpmcounter15_inputs `define rvformal_csr_mhpmcounter15_conn `define rvformal_csr_mhpmcounter15_conn32 `define rvformal_csr_mhpmcounter15_channel(_idx) `endif `define rvformal_csr_mhpmcounter15_indices \ localparam [11:0] csr_mindex_mhpmcounter15 = 12'hB0F; \ localparam [11:0] csr_sindex_mhpmcounter15 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter15 = 12'hC0F; \ localparam [11:0] csr_mindex_mhpmcounter15h = 12'hB8F; \ localparam [11:0] csr_sindex_mhpmcounter15h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter15h = 12'hC8F; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER16 `define rvformal_csr_mhpmcounter16_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_wdata; `define rvformal_csr_mhpmcounter16_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_wdata `define rvformal_csr_mhpmcounter16_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter16_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter16_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter16_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter16_wdata `define rvformal_csr_mhpmcounter16_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_wdata `define rvformal_csr_mhpmcounter16_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter16_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter16_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter16_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter16_wdata `define rvformal_csr_mhpmcounter16_conn, \ .rvfi_csr_mhpmcounter16_rmask (rvfi_csr_mhpmcounter16_rmask), \ .rvfi_csr_mhpmcounter16_wmask (rvfi_csr_mhpmcounter16_wmask), \ .rvfi_csr_mhpmcounter16_rdata (rvfi_csr_mhpmcounter16_rdata), \ .rvfi_csr_mhpmcounter16_wdata (rvfi_csr_mhpmcounter16_wdata) `define rvformal_csr_mhpmcounter16_channel_conn(_idx), \ .rvfi_csr_mhpmcounter16_rmask (rvfi_csr_mhpmcounter16_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter16_wmask (rvfi_csr_mhpmcounter16_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter16_rdata (rvfi_csr_mhpmcounter16_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter16_wdata (rvfi_csr_mhpmcounter16_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter16_conn32, \ .rvfi_csr_mhpmcounter16_rmask (rvfi_csr_mhpmcounter16_rmask[31: 0]), \ .rvfi_csr_mhpmcounter16_wmask (rvfi_csr_mhpmcounter16_wmask[31: 0]), \ .rvfi_csr_mhpmcounter16_rdata (rvfi_csr_mhpmcounter16_rdata[31: 0]), \ .rvfi_csr_mhpmcounter16_wdata (rvfi_csr_mhpmcounter16_wdata[31: 0]), \ .rvfi_csr_mhpmcounter16h_rmask (rvfi_csr_mhpmcounter16_rmask[63:32]), \ .rvfi_csr_mhpmcounter16h_wmask (rvfi_csr_mhpmcounter16_wmask[63:32]), \ .rvfi_csr_mhpmcounter16h_rdata (rvfi_csr_mhpmcounter16_rdata[63:32]), \ .rvfi_csr_mhpmcounter16h_wdata (rvfi_csr_mhpmcounter16_wdata[63:32]) `define rvformal_csr_mhpmcounter16_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter16_rmask = rvfi_csr_mhpmcounter16_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter16_wmask = rvfi_csr_mhpmcounter16_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter16_rdata = rvfi_csr_mhpmcounter16_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter16_wdata = rvfi_csr_mhpmcounter16_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter16_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter16_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter16_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter16_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter16_wdata) `else `define rvformal_csr_mhpmcounter16_wires `define rvformal_csr_mhpmcounter16_outputs `define rvformal_csr_mhpmcounter16_inputs `define rvformal_csr_mhpmcounter16_conn `define rvformal_csr_mhpmcounter16_conn32 `define rvformal_csr_mhpmcounter16_channel(_idx) `endif `define rvformal_csr_mhpmcounter16_indices \ localparam [11:0] csr_mindex_mhpmcounter16 = 12'hB10; \ localparam [11:0] csr_sindex_mhpmcounter16 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter16 = 12'hC10; \ localparam [11:0] csr_mindex_mhpmcounter16h = 12'hB90; \ localparam [11:0] csr_sindex_mhpmcounter16h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter16h = 12'hC90; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER17 `define rvformal_csr_mhpmcounter17_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_wdata; `define rvformal_csr_mhpmcounter17_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_wdata `define rvformal_csr_mhpmcounter17_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter17_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter17_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter17_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter17_wdata `define rvformal_csr_mhpmcounter17_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_wdata `define rvformal_csr_mhpmcounter17_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter17_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter17_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter17_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter17_wdata `define rvformal_csr_mhpmcounter17_conn, \ .rvfi_csr_mhpmcounter17_rmask (rvfi_csr_mhpmcounter17_rmask), \ .rvfi_csr_mhpmcounter17_wmask (rvfi_csr_mhpmcounter17_wmask), \ .rvfi_csr_mhpmcounter17_rdata (rvfi_csr_mhpmcounter17_rdata), \ .rvfi_csr_mhpmcounter17_wdata (rvfi_csr_mhpmcounter17_wdata) `define rvformal_csr_mhpmcounter17_channel_conn(_idx), \ .rvfi_csr_mhpmcounter17_rmask (rvfi_csr_mhpmcounter17_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter17_wmask (rvfi_csr_mhpmcounter17_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter17_rdata (rvfi_csr_mhpmcounter17_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter17_wdata (rvfi_csr_mhpmcounter17_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter17_conn32, \ .rvfi_csr_mhpmcounter17_rmask (rvfi_csr_mhpmcounter17_rmask[31: 0]), \ .rvfi_csr_mhpmcounter17_wmask (rvfi_csr_mhpmcounter17_wmask[31: 0]), \ .rvfi_csr_mhpmcounter17_rdata (rvfi_csr_mhpmcounter17_rdata[31: 0]), \ .rvfi_csr_mhpmcounter17_wdata (rvfi_csr_mhpmcounter17_wdata[31: 0]), \ .rvfi_csr_mhpmcounter17h_rmask (rvfi_csr_mhpmcounter17_rmask[63:32]), \ .rvfi_csr_mhpmcounter17h_wmask (rvfi_csr_mhpmcounter17_wmask[63:32]), \ .rvfi_csr_mhpmcounter17h_rdata (rvfi_csr_mhpmcounter17_rdata[63:32]), \ .rvfi_csr_mhpmcounter17h_wdata (rvfi_csr_mhpmcounter17_wdata[63:32]) `define rvformal_csr_mhpmcounter17_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter17_rmask = rvfi_csr_mhpmcounter17_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter17_wmask = rvfi_csr_mhpmcounter17_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter17_rdata = rvfi_csr_mhpmcounter17_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter17_wdata = rvfi_csr_mhpmcounter17_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter17_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter17_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter17_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter17_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter17_wdata) `else `define rvformal_csr_mhpmcounter17_wires `define rvformal_csr_mhpmcounter17_outputs `define rvformal_csr_mhpmcounter17_inputs `define rvformal_csr_mhpmcounter17_conn `define rvformal_csr_mhpmcounter17_conn32 `define rvformal_csr_mhpmcounter17_channel(_idx) `endif `define rvformal_csr_mhpmcounter17_indices \ localparam [11:0] csr_mindex_mhpmcounter17 = 12'hB11; \ localparam [11:0] csr_sindex_mhpmcounter17 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter17 = 12'hC11; \ localparam [11:0] csr_mindex_mhpmcounter17h = 12'hB91; \ localparam [11:0] csr_sindex_mhpmcounter17h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter17h = 12'hC91; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER18 `define rvformal_csr_mhpmcounter18_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_wdata; `define rvformal_csr_mhpmcounter18_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_wdata `define rvformal_csr_mhpmcounter18_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter18_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter18_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter18_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter18_wdata `define rvformal_csr_mhpmcounter18_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_wdata `define rvformal_csr_mhpmcounter18_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter18_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter18_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter18_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter18_wdata `define rvformal_csr_mhpmcounter18_conn, \ .rvfi_csr_mhpmcounter18_rmask (rvfi_csr_mhpmcounter18_rmask), \ .rvfi_csr_mhpmcounter18_wmask (rvfi_csr_mhpmcounter18_wmask), \ .rvfi_csr_mhpmcounter18_rdata (rvfi_csr_mhpmcounter18_rdata), \ .rvfi_csr_mhpmcounter18_wdata (rvfi_csr_mhpmcounter18_wdata) `define rvformal_csr_mhpmcounter18_channel_conn(_idx), \ .rvfi_csr_mhpmcounter18_rmask (rvfi_csr_mhpmcounter18_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter18_wmask (rvfi_csr_mhpmcounter18_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter18_rdata (rvfi_csr_mhpmcounter18_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter18_wdata (rvfi_csr_mhpmcounter18_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter18_conn32, \ .rvfi_csr_mhpmcounter18_rmask (rvfi_csr_mhpmcounter18_rmask[31: 0]), \ .rvfi_csr_mhpmcounter18_wmask (rvfi_csr_mhpmcounter18_wmask[31: 0]), \ .rvfi_csr_mhpmcounter18_rdata (rvfi_csr_mhpmcounter18_rdata[31: 0]), \ .rvfi_csr_mhpmcounter18_wdata (rvfi_csr_mhpmcounter18_wdata[31: 0]), \ .rvfi_csr_mhpmcounter18h_rmask (rvfi_csr_mhpmcounter18_rmask[63:32]), \ .rvfi_csr_mhpmcounter18h_wmask (rvfi_csr_mhpmcounter18_wmask[63:32]), \ .rvfi_csr_mhpmcounter18h_rdata (rvfi_csr_mhpmcounter18_rdata[63:32]), \ .rvfi_csr_mhpmcounter18h_wdata (rvfi_csr_mhpmcounter18_wdata[63:32]) `define rvformal_csr_mhpmcounter18_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter18_rmask = rvfi_csr_mhpmcounter18_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter18_wmask = rvfi_csr_mhpmcounter18_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter18_rdata = rvfi_csr_mhpmcounter18_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter18_wdata = rvfi_csr_mhpmcounter18_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter18_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter18_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter18_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter18_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter18_wdata) `else `define rvformal_csr_mhpmcounter18_wires `define rvformal_csr_mhpmcounter18_outputs `define rvformal_csr_mhpmcounter18_inputs `define rvformal_csr_mhpmcounter18_conn `define rvformal_csr_mhpmcounter18_conn32 `define rvformal_csr_mhpmcounter18_channel(_idx) `endif `define rvformal_csr_mhpmcounter18_indices \ localparam [11:0] csr_mindex_mhpmcounter18 = 12'hB12; \ localparam [11:0] csr_sindex_mhpmcounter18 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter18 = 12'hC12; \ localparam [11:0] csr_mindex_mhpmcounter18h = 12'hB92; \ localparam [11:0] csr_sindex_mhpmcounter18h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter18h = 12'hC92; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER19 `define rvformal_csr_mhpmcounter19_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_wdata; `define rvformal_csr_mhpmcounter19_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_wdata `define rvformal_csr_mhpmcounter19_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter19_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter19_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter19_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter19_wdata `define rvformal_csr_mhpmcounter19_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_wdata `define rvformal_csr_mhpmcounter19_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter19_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter19_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter19_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter19_wdata `define rvformal_csr_mhpmcounter19_conn, \ .rvfi_csr_mhpmcounter19_rmask (rvfi_csr_mhpmcounter19_rmask), \ .rvfi_csr_mhpmcounter19_wmask (rvfi_csr_mhpmcounter19_wmask), \ .rvfi_csr_mhpmcounter19_rdata (rvfi_csr_mhpmcounter19_rdata), \ .rvfi_csr_mhpmcounter19_wdata (rvfi_csr_mhpmcounter19_wdata) `define rvformal_csr_mhpmcounter19_channel_conn(_idx), \ .rvfi_csr_mhpmcounter19_rmask (rvfi_csr_mhpmcounter19_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter19_wmask (rvfi_csr_mhpmcounter19_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter19_rdata (rvfi_csr_mhpmcounter19_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter19_wdata (rvfi_csr_mhpmcounter19_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter19_conn32, \ .rvfi_csr_mhpmcounter19_rmask (rvfi_csr_mhpmcounter19_rmask[31: 0]), \ .rvfi_csr_mhpmcounter19_wmask (rvfi_csr_mhpmcounter19_wmask[31: 0]), \ .rvfi_csr_mhpmcounter19_rdata (rvfi_csr_mhpmcounter19_rdata[31: 0]), \ .rvfi_csr_mhpmcounter19_wdata (rvfi_csr_mhpmcounter19_wdata[31: 0]), \ .rvfi_csr_mhpmcounter19h_rmask (rvfi_csr_mhpmcounter19_rmask[63:32]), \ .rvfi_csr_mhpmcounter19h_wmask (rvfi_csr_mhpmcounter19_wmask[63:32]), \ .rvfi_csr_mhpmcounter19h_rdata (rvfi_csr_mhpmcounter19_rdata[63:32]), \ .rvfi_csr_mhpmcounter19h_wdata (rvfi_csr_mhpmcounter19_wdata[63:32]) `define rvformal_csr_mhpmcounter19_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter19_rmask = rvfi_csr_mhpmcounter19_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter19_wmask = rvfi_csr_mhpmcounter19_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter19_rdata = rvfi_csr_mhpmcounter19_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter19_wdata = rvfi_csr_mhpmcounter19_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter19_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter19_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter19_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter19_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter19_wdata) `else `define rvformal_csr_mhpmcounter19_wires `define rvformal_csr_mhpmcounter19_outputs `define rvformal_csr_mhpmcounter19_inputs `define rvformal_csr_mhpmcounter19_conn `define rvformal_csr_mhpmcounter19_conn32 `define rvformal_csr_mhpmcounter19_channel(_idx) `endif `define rvformal_csr_mhpmcounter19_indices \ localparam [11:0] csr_mindex_mhpmcounter19 = 12'hB13; \ localparam [11:0] csr_sindex_mhpmcounter19 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter19 = 12'hC13; \ localparam [11:0] csr_mindex_mhpmcounter19h = 12'hB93; \ localparam [11:0] csr_sindex_mhpmcounter19h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter19h = 12'hC93; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER20 `define rvformal_csr_mhpmcounter20_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_wdata; `define rvformal_csr_mhpmcounter20_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_wdata `define rvformal_csr_mhpmcounter20_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter20_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter20_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter20_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter20_wdata `define rvformal_csr_mhpmcounter20_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_wdata `define rvformal_csr_mhpmcounter20_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter20_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter20_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter20_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter20_wdata `define rvformal_csr_mhpmcounter20_conn, \ .rvfi_csr_mhpmcounter20_rmask (rvfi_csr_mhpmcounter20_rmask), \ .rvfi_csr_mhpmcounter20_wmask (rvfi_csr_mhpmcounter20_wmask), \ .rvfi_csr_mhpmcounter20_rdata (rvfi_csr_mhpmcounter20_rdata), \ .rvfi_csr_mhpmcounter20_wdata (rvfi_csr_mhpmcounter20_wdata) `define rvformal_csr_mhpmcounter20_channel_conn(_idx), \ .rvfi_csr_mhpmcounter20_rmask (rvfi_csr_mhpmcounter20_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter20_wmask (rvfi_csr_mhpmcounter20_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter20_rdata (rvfi_csr_mhpmcounter20_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter20_wdata (rvfi_csr_mhpmcounter20_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter20_conn32, \ .rvfi_csr_mhpmcounter20_rmask (rvfi_csr_mhpmcounter20_rmask[31: 0]), \ .rvfi_csr_mhpmcounter20_wmask (rvfi_csr_mhpmcounter20_wmask[31: 0]), \ .rvfi_csr_mhpmcounter20_rdata (rvfi_csr_mhpmcounter20_rdata[31: 0]), \ .rvfi_csr_mhpmcounter20_wdata (rvfi_csr_mhpmcounter20_wdata[31: 0]), \ .rvfi_csr_mhpmcounter20h_rmask (rvfi_csr_mhpmcounter20_rmask[63:32]), \ .rvfi_csr_mhpmcounter20h_wmask (rvfi_csr_mhpmcounter20_wmask[63:32]), \ .rvfi_csr_mhpmcounter20h_rdata (rvfi_csr_mhpmcounter20_rdata[63:32]), \ .rvfi_csr_mhpmcounter20h_wdata (rvfi_csr_mhpmcounter20_wdata[63:32]) `define rvformal_csr_mhpmcounter20_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter20_rmask = rvfi_csr_mhpmcounter20_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter20_wmask = rvfi_csr_mhpmcounter20_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter20_rdata = rvfi_csr_mhpmcounter20_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter20_wdata = rvfi_csr_mhpmcounter20_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter20_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter20_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter20_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter20_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter20_wdata) `else `define rvformal_csr_mhpmcounter20_wires `define rvformal_csr_mhpmcounter20_outputs `define rvformal_csr_mhpmcounter20_inputs `define rvformal_csr_mhpmcounter20_conn `define rvformal_csr_mhpmcounter20_conn32 `define rvformal_csr_mhpmcounter20_channel(_idx) `endif `define rvformal_csr_mhpmcounter20_indices \ localparam [11:0] csr_mindex_mhpmcounter20 = 12'hB14; \ localparam [11:0] csr_sindex_mhpmcounter20 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter20 = 12'hC14; \ localparam [11:0] csr_mindex_mhpmcounter20h = 12'hB94; \ localparam [11:0] csr_sindex_mhpmcounter20h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter20h = 12'hC94; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER21 `define rvformal_csr_mhpmcounter21_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_wdata; `define rvformal_csr_mhpmcounter21_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_wdata `define rvformal_csr_mhpmcounter21_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter21_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter21_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter21_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter21_wdata `define rvformal_csr_mhpmcounter21_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_wdata `define rvformal_csr_mhpmcounter21_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter21_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter21_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter21_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter21_wdata `define rvformal_csr_mhpmcounter21_conn, \ .rvfi_csr_mhpmcounter21_rmask (rvfi_csr_mhpmcounter21_rmask), \ .rvfi_csr_mhpmcounter21_wmask (rvfi_csr_mhpmcounter21_wmask), \ .rvfi_csr_mhpmcounter21_rdata (rvfi_csr_mhpmcounter21_rdata), \ .rvfi_csr_mhpmcounter21_wdata (rvfi_csr_mhpmcounter21_wdata) `define rvformal_csr_mhpmcounter21_channel_conn(_idx), \ .rvfi_csr_mhpmcounter21_rmask (rvfi_csr_mhpmcounter21_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter21_wmask (rvfi_csr_mhpmcounter21_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter21_rdata (rvfi_csr_mhpmcounter21_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter21_wdata (rvfi_csr_mhpmcounter21_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter21_conn32, \ .rvfi_csr_mhpmcounter21_rmask (rvfi_csr_mhpmcounter21_rmask[31: 0]), \ .rvfi_csr_mhpmcounter21_wmask (rvfi_csr_mhpmcounter21_wmask[31: 0]), \ .rvfi_csr_mhpmcounter21_rdata (rvfi_csr_mhpmcounter21_rdata[31: 0]), \ .rvfi_csr_mhpmcounter21_wdata (rvfi_csr_mhpmcounter21_wdata[31: 0]), \ .rvfi_csr_mhpmcounter21h_rmask (rvfi_csr_mhpmcounter21_rmask[63:32]), \ .rvfi_csr_mhpmcounter21h_wmask (rvfi_csr_mhpmcounter21_wmask[63:32]), \ .rvfi_csr_mhpmcounter21h_rdata (rvfi_csr_mhpmcounter21_rdata[63:32]), \ .rvfi_csr_mhpmcounter21h_wdata (rvfi_csr_mhpmcounter21_wdata[63:32]) `define rvformal_csr_mhpmcounter21_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter21_rmask = rvfi_csr_mhpmcounter21_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter21_wmask = rvfi_csr_mhpmcounter21_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter21_rdata = rvfi_csr_mhpmcounter21_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter21_wdata = rvfi_csr_mhpmcounter21_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter21_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter21_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter21_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter21_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter21_wdata) `else `define rvformal_csr_mhpmcounter21_wires `define rvformal_csr_mhpmcounter21_outputs `define rvformal_csr_mhpmcounter21_inputs `define rvformal_csr_mhpmcounter21_conn `define rvformal_csr_mhpmcounter21_conn32 `define rvformal_csr_mhpmcounter21_channel(_idx) `endif `define rvformal_csr_mhpmcounter21_indices \ localparam [11:0] csr_mindex_mhpmcounter21 = 12'hB15; \ localparam [11:0] csr_sindex_mhpmcounter21 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter21 = 12'hC15; \ localparam [11:0] csr_mindex_mhpmcounter21h = 12'hB95; \ localparam [11:0] csr_sindex_mhpmcounter21h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter21h = 12'hC95; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER22 `define rvformal_csr_mhpmcounter22_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_wdata; `define rvformal_csr_mhpmcounter22_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_wdata `define rvformal_csr_mhpmcounter22_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter22_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter22_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter22_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter22_wdata `define rvformal_csr_mhpmcounter22_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_wdata `define rvformal_csr_mhpmcounter22_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter22_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter22_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter22_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter22_wdata `define rvformal_csr_mhpmcounter22_conn, \ .rvfi_csr_mhpmcounter22_rmask (rvfi_csr_mhpmcounter22_rmask), \ .rvfi_csr_mhpmcounter22_wmask (rvfi_csr_mhpmcounter22_wmask), \ .rvfi_csr_mhpmcounter22_rdata (rvfi_csr_mhpmcounter22_rdata), \ .rvfi_csr_mhpmcounter22_wdata (rvfi_csr_mhpmcounter22_wdata) `define rvformal_csr_mhpmcounter22_channel_conn(_idx), \ .rvfi_csr_mhpmcounter22_rmask (rvfi_csr_mhpmcounter22_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter22_wmask (rvfi_csr_mhpmcounter22_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter22_rdata (rvfi_csr_mhpmcounter22_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter22_wdata (rvfi_csr_mhpmcounter22_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter22_conn32, \ .rvfi_csr_mhpmcounter22_rmask (rvfi_csr_mhpmcounter22_rmask[31: 0]), \ .rvfi_csr_mhpmcounter22_wmask (rvfi_csr_mhpmcounter22_wmask[31: 0]), \ .rvfi_csr_mhpmcounter22_rdata (rvfi_csr_mhpmcounter22_rdata[31: 0]), \ .rvfi_csr_mhpmcounter22_wdata (rvfi_csr_mhpmcounter22_wdata[31: 0]), \ .rvfi_csr_mhpmcounter22h_rmask (rvfi_csr_mhpmcounter22_rmask[63:32]), \ .rvfi_csr_mhpmcounter22h_wmask (rvfi_csr_mhpmcounter22_wmask[63:32]), \ .rvfi_csr_mhpmcounter22h_rdata (rvfi_csr_mhpmcounter22_rdata[63:32]), \ .rvfi_csr_mhpmcounter22h_wdata (rvfi_csr_mhpmcounter22_wdata[63:32]) `define rvformal_csr_mhpmcounter22_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter22_rmask = rvfi_csr_mhpmcounter22_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter22_wmask = rvfi_csr_mhpmcounter22_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter22_rdata = rvfi_csr_mhpmcounter22_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter22_wdata = rvfi_csr_mhpmcounter22_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter22_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter22_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter22_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter22_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter22_wdata) `else `define rvformal_csr_mhpmcounter22_wires `define rvformal_csr_mhpmcounter22_outputs `define rvformal_csr_mhpmcounter22_inputs `define rvformal_csr_mhpmcounter22_conn `define rvformal_csr_mhpmcounter22_conn32 `define rvformal_csr_mhpmcounter22_channel(_idx) `endif `define rvformal_csr_mhpmcounter22_indices \ localparam [11:0] csr_mindex_mhpmcounter22 = 12'hB16; \ localparam [11:0] csr_sindex_mhpmcounter22 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter22 = 12'hC16; \ localparam [11:0] csr_mindex_mhpmcounter22h = 12'hB96; \ localparam [11:0] csr_sindex_mhpmcounter22h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter22h = 12'hC96; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER23 `define rvformal_csr_mhpmcounter23_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_wdata; `define rvformal_csr_mhpmcounter23_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_wdata `define rvformal_csr_mhpmcounter23_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter23_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter23_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter23_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter23_wdata `define rvformal_csr_mhpmcounter23_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_wdata `define rvformal_csr_mhpmcounter23_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter23_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter23_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter23_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter23_wdata `define rvformal_csr_mhpmcounter23_conn, \ .rvfi_csr_mhpmcounter23_rmask (rvfi_csr_mhpmcounter23_rmask), \ .rvfi_csr_mhpmcounter23_wmask (rvfi_csr_mhpmcounter23_wmask), \ .rvfi_csr_mhpmcounter23_rdata (rvfi_csr_mhpmcounter23_rdata), \ .rvfi_csr_mhpmcounter23_wdata (rvfi_csr_mhpmcounter23_wdata) `define rvformal_csr_mhpmcounter23_channel_conn(_idx), \ .rvfi_csr_mhpmcounter23_rmask (rvfi_csr_mhpmcounter23_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter23_wmask (rvfi_csr_mhpmcounter23_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter23_rdata (rvfi_csr_mhpmcounter23_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter23_wdata (rvfi_csr_mhpmcounter23_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter23_conn32, \ .rvfi_csr_mhpmcounter23_rmask (rvfi_csr_mhpmcounter23_rmask[31: 0]), \ .rvfi_csr_mhpmcounter23_wmask (rvfi_csr_mhpmcounter23_wmask[31: 0]), \ .rvfi_csr_mhpmcounter23_rdata (rvfi_csr_mhpmcounter23_rdata[31: 0]), \ .rvfi_csr_mhpmcounter23_wdata (rvfi_csr_mhpmcounter23_wdata[31: 0]), \ .rvfi_csr_mhpmcounter23h_rmask (rvfi_csr_mhpmcounter23_rmask[63:32]), \ .rvfi_csr_mhpmcounter23h_wmask (rvfi_csr_mhpmcounter23_wmask[63:32]), \ .rvfi_csr_mhpmcounter23h_rdata (rvfi_csr_mhpmcounter23_rdata[63:32]), \ .rvfi_csr_mhpmcounter23h_wdata (rvfi_csr_mhpmcounter23_wdata[63:32]) `define rvformal_csr_mhpmcounter23_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter23_rmask = rvfi_csr_mhpmcounter23_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter23_wmask = rvfi_csr_mhpmcounter23_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter23_rdata = rvfi_csr_mhpmcounter23_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter23_wdata = rvfi_csr_mhpmcounter23_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter23_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter23_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter23_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter23_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter23_wdata) `else `define rvformal_csr_mhpmcounter23_wires `define rvformal_csr_mhpmcounter23_outputs `define rvformal_csr_mhpmcounter23_inputs `define rvformal_csr_mhpmcounter23_conn `define rvformal_csr_mhpmcounter23_conn32 `define rvformal_csr_mhpmcounter23_channel(_idx) `endif `define rvformal_csr_mhpmcounter23_indices \ localparam [11:0] csr_mindex_mhpmcounter23 = 12'hB17; \ localparam [11:0] csr_sindex_mhpmcounter23 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter23 = 12'hC17; \ localparam [11:0] csr_mindex_mhpmcounter23h = 12'hB97; \ localparam [11:0] csr_sindex_mhpmcounter23h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter23h = 12'hC97; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER24 `define rvformal_csr_mhpmcounter24_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_wdata; `define rvformal_csr_mhpmcounter24_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_wdata `define rvformal_csr_mhpmcounter24_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter24_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter24_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter24_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter24_wdata `define rvformal_csr_mhpmcounter24_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_wdata `define rvformal_csr_mhpmcounter24_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter24_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter24_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter24_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter24_wdata `define rvformal_csr_mhpmcounter24_conn, \ .rvfi_csr_mhpmcounter24_rmask (rvfi_csr_mhpmcounter24_rmask), \ .rvfi_csr_mhpmcounter24_wmask (rvfi_csr_mhpmcounter24_wmask), \ .rvfi_csr_mhpmcounter24_rdata (rvfi_csr_mhpmcounter24_rdata), \ .rvfi_csr_mhpmcounter24_wdata (rvfi_csr_mhpmcounter24_wdata) `define rvformal_csr_mhpmcounter24_channel_conn(_idx), \ .rvfi_csr_mhpmcounter24_rmask (rvfi_csr_mhpmcounter24_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter24_wmask (rvfi_csr_mhpmcounter24_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter24_rdata (rvfi_csr_mhpmcounter24_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter24_wdata (rvfi_csr_mhpmcounter24_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter24_conn32, \ .rvfi_csr_mhpmcounter24_rmask (rvfi_csr_mhpmcounter24_rmask[31: 0]), \ .rvfi_csr_mhpmcounter24_wmask (rvfi_csr_mhpmcounter24_wmask[31: 0]), \ .rvfi_csr_mhpmcounter24_rdata (rvfi_csr_mhpmcounter24_rdata[31: 0]), \ .rvfi_csr_mhpmcounter24_wdata (rvfi_csr_mhpmcounter24_wdata[31: 0]), \ .rvfi_csr_mhpmcounter24h_rmask (rvfi_csr_mhpmcounter24_rmask[63:32]), \ .rvfi_csr_mhpmcounter24h_wmask (rvfi_csr_mhpmcounter24_wmask[63:32]), \ .rvfi_csr_mhpmcounter24h_rdata (rvfi_csr_mhpmcounter24_rdata[63:32]), \ .rvfi_csr_mhpmcounter24h_wdata (rvfi_csr_mhpmcounter24_wdata[63:32]) `define rvformal_csr_mhpmcounter24_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter24_rmask = rvfi_csr_mhpmcounter24_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter24_wmask = rvfi_csr_mhpmcounter24_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter24_rdata = rvfi_csr_mhpmcounter24_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter24_wdata = rvfi_csr_mhpmcounter24_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter24_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter24_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter24_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter24_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter24_wdata) `else `define rvformal_csr_mhpmcounter24_wires `define rvformal_csr_mhpmcounter24_outputs `define rvformal_csr_mhpmcounter24_inputs `define rvformal_csr_mhpmcounter24_conn `define rvformal_csr_mhpmcounter24_conn32 `define rvformal_csr_mhpmcounter24_channel(_idx) `endif `define rvformal_csr_mhpmcounter24_indices \ localparam [11:0] csr_mindex_mhpmcounter24 = 12'hB18; \ localparam [11:0] csr_sindex_mhpmcounter24 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter24 = 12'hC18; \ localparam [11:0] csr_mindex_mhpmcounter24h = 12'hB98; \ localparam [11:0] csr_sindex_mhpmcounter24h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter24h = 12'hC98; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER25 `define rvformal_csr_mhpmcounter25_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_wdata; `define rvformal_csr_mhpmcounter25_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_wdata `define rvformal_csr_mhpmcounter25_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter25_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter25_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter25_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter25_wdata `define rvformal_csr_mhpmcounter25_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_wdata `define rvformal_csr_mhpmcounter25_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter25_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter25_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter25_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter25_wdata `define rvformal_csr_mhpmcounter25_conn, \ .rvfi_csr_mhpmcounter25_rmask (rvfi_csr_mhpmcounter25_rmask), \ .rvfi_csr_mhpmcounter25_wmask (rvfi_csr_mhpmcounter25_wmask), \ .rvfi_csr_mhpmcounter25_rdata (rvfi_csr_mhpmcounter25_rdata), \ .rvfi_csr_mhpmcounter25_wdata (rvfi_csr_mhpmcounter25_wdata) `define rvformal_csr_mhpmcounter25_channel_conn(_idx), \ .rvfi_csr_mhpmcounter25_rmask (rvfi_csr_mhpmcounter25_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter25_wmask (rvfi_csr_mhpmcounter25_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter25_rdata (rvfi_csr_mhpmcounter25_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter25_wdata (rvfi_csr_mhpmcounter25_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter25_conn32, \ .rvfi_csr_mhpmcounter25_rmask (rvfi_csr_mhpmcounter25_rmask[31: 0]), \ .rvfi_csr_mhpmcounter25_wmask (rvfi_csr_mhpmcounter25_wmask[31: 0]), \ .rvfi_csr_mhpmcounter25_rdata (rvfi_csr_mhpmcounter25_rdata[31: 0]), \ .rvfi_csr_mhpmcounter25_wdata (rvfi_csr_mhpmcounter25_wdata[31: 0]), \ .rvfi_csr_mhpmcounter25h_rmask (rvfi_csr_mhpmcounter25_rmask[63:32]), \ .rvfi_csr_mhpmcounter25h_wmask (rvfi_csr_mhpmcounter25_wmask[63:32]), \ .rvfi_csr_mhpmcounter25h_rdata (rvfi_csr_mhpmcounter25_rdata[63:32]), \ .rvfi_csr_mhpmcounter25h_wdata (rvfi_csr_mhpmcounter25_wdata[63:32]) `define rvformal_csr_mhpmcounter25_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter25_rmask = rvfi_csr_mhpmcounter25_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter25_wmask = rvfi_csr_mhpmcounter25_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter25_rdata = rvfi_csr_mhpmcounter25_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter25_wdata = rvfi_csr_mhpmcounter25_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter25_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter25_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter25_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter25_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter25_wdata) `else `define rvformal_csr_mhpmcounter25_wires `define rvformal_csr_mhpmcounter25_outputs `define rvformal_csr_mhpmcounter25_inputs `define rvformal_csr_mhpmcounter25_conn `define rvformal_csr_mhpmcounter25_conn32 `define rvformal_csr_mhpmcounter25_channel(_idx) `endif `define rvformal_csr_mhpmcounter25_indices \ localparam [11:0] csr_mindex_mhpmcounter25 = 12'hB19; \ localparam [11:0] csr_sindex_mhpmcounter25 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter25 = 12'hC19; \ localparam [11:0] csr_mindex_mhpmcounter25h = 12'hB99; \ localparam [11:0] csr_sindex_mhpmcounter25h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter25h = 12'hC99; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER26 `define rvformal_csr_mhpmcounter26_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_wdata; `define rvformal_csr_mhpmcounter26_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_wdata `define rvformal_csr_mhpmcounter26_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter26_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter26_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter26_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter26_wdata `define rvformal_csr_mhpmcounter26_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_wdata `define rvformal_csr_mhpmcounter26_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter26_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter26_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter26_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter26_wdata `define rvformal_csr_mhpmcounter26_conn, \ .rvfi_csr_mhpmcounter26_rmask (rvfi_csr_mhpmcounter26_rmask), \ .rvfi_csr_mhpmcounter26_wmask (rvfi_csr_mhpmcounter26_wmask), \ .rvfi_csr_mhpmcounter26_rdata (rvfi_csr_mhpmcounter26_rdata), \ .rvfi_csr_mhpmcounter26_wdata (rvfi_csr_mhpmcounter26_wdata) `define rvformal_csr_mhpmcounter26_channel_conn(_idx), \ .rvfi_csr_mhpmcounter26_rmask (rvfi_csr_mhpmcounter26_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter26_wmask (rvfi_csr_mhpmcounter26_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter26_rdata (rvfi_csr_mhpmcounter26_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter26_wdata (rvfi_csr_mhpmcounter26_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter26_conn32, \ .rvfi_csr_mhpmcounter26_rmask (rvfi_csr_mhpmcounter26_rmask[31: 0]), \ .rvfi_csr_mhpmcounter26_wmask (rvfi_csr_mhpmcounter26_wmask[31: 0]), \ .rvfi_csr_mhpmcounter26_rdata (rvfi_csr_mhpmcounter26_rdata[31: 0]), \ .rvfi_csr_mhpmcounter26_wdata (rvfi_csr_mhpmcounter26_wdata[31: 0]), \ .rvfi_csr_mhpmcounter26h_rmask (rvfi_csr_mhpmcounter26_rmask[63:32]), \ .rvfi_csr_mhpmcounter26h_wmask (rvfi_csr_mhpmcounter26_wmask[63:32]), \ .rvfi_csr_mhpmcounter26h_rdata (rvfi_csr_mhpmcounter26_rdata[63:32]), \ .rvfi_csr_mhpmcounter26h_wdata (rvfi_csr_mhpmcounter26_wdata[63:32]) `define rvformal_csr_mhpmcounter26_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter26_rmask = rvfi_csr_mhpmcounter26_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter26_wmask = rvfi_csr_mhpmcounter26_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter26_rdata = rvfi_csr_mhpmcounter26_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter26_wdata = rvfi_csr_mhpmcounter26_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter26_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter26_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter26_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter26_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter26_wdata) `else `define rvformal_csr_mhpmcounter26_wires `define rvformal_csr_mhpmcounter26_outputs `define rvformal_csr_mhpmcounter26_inputs `define rvformal_csr_mhpmcounter26_conn `define rvformal_csr_mhpmcounter26_conn32 `define rvformal_csr_mhpmcounter26_channel(_idx) `endif `define rvformal_csr_mhpmcounter26_indices \ localparam [11:0] csr_mindex_mhpmcounter26 = 12'hB1A; \ localparam [11:0] csr_sindex_mhpmcounter26 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter26 = 12'hC1A; \ localparam [11:0] csr_mindex_mhpmcounter26h = 12'hB9A; \ localparam [11:0] csr_sindex_mhpmcounter26h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter26h = 12'hC9A; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER27 `define rvformal_csr_mhpmcounter27_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_wdata; `define rvformal_csr_mhpmcounter27_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_wdata `define rvformal_csr_mhpmcounter27_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter27_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter27_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter27_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter27_wdata `define rvformal_csr_mhpmcounter27_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_wdata `define rvformal_csr_mhpmcounter27_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter27_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter27_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter27_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter27_wdata `define rvformal_csr_mhpmcounter27_conn, \ .rvfi_csr_mhpmcounter27_rmask (rvfi_csr_mhpmcounter27_rmask), \ .rvfi_csr_mhpmcounter27_wmask (rvfi_csr_mhpmcounter27_wmask), \ .rvfi_csr_mhpmcounter27_rdata (rvfi_csr_mhpmcounter27_rdata), \ .rvfi_csr_mhpmcounter27_wdata (rvfi_csr_mhpmcounter27_wdata) `define rvformal_csr_mhpmcounter27_channel_conn(_idx), \ .rvfi_csr_mhpmcounter27_rmask (rvfi_csr_mhpmcounter27_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter27_wmask (rvfi_csr_mhpmcounter27_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter27_rdata (rvfi_csr_mhpmcounter27_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter27_wdata (rvfi_csr_mhpmcounter27_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter27_conn32, \ .rvfi_csr_mhpmcounter27_rmask (rvfi_csr_mhpmcounter27_rmask[31: 0]), \ .rvfi_csr_mhpmcounter27_wmask (rvfi_csr_mhpmcounter27_wmask[31: 0]), \ .rvfi_csr_mhpmcounter27_rdata (rvfi_csr_mhpmcounter27_rdata[31: 0]), \ .rvfi_csr_mhpmcounter27_wdata (rvfi_csr_mhpmcounter27_wdata[31: 0]), \ .rvfi_csr_mhpmcounter27h_rmask (rvfi_csr_mhpmcounter27_rmask[63:32]), \ .rvfi_csr_mhpmcounter27h_wmask (rvfi_csr_mhpmcounter27_wmask[63:32]), \ .rvfi_csr_mhpmcounter27h_rdata (rvfi_csr_mhpmcounter27_rdata[63:32]), \ .rvfi_csr_mhpmcounter27h_wdata (rvfi_csr_mhpmcounter27_wdata[63:32]) `define rvformal_csr_mhpmcounter27_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter27_rmask = rvfi_csr_mhpmcounter27_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter27_wmask = rvfi_csr_mhpmcounter27_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter27_rdata = rvfi_csr_mhpmcounter27_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter27_wdata = rvfi_csr_mhpmcounter27_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter27_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter27_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter27_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter27_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter27_wdata) `else `define rvformal_csr_mhpmcounter27_wires `define rvformal_csr_mhpmcounter27_outputs `define rvformal_csr_mhpmcounter27_inputs `define rvformal_csr_mhpmcounter27_conn `define rvformal_csr_mhpmcounter27_conn32 `define rvformal_csr_mhpmcounter27_channel(_idx) `endif `define rvformal_csr_mhpmcounter27_indices \ localparam [11:0] csr_mindex_mhpmcounter27 = 12'hB1B; \ localparam [11:0] csr_sindex_mhpmcounter27 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter27 = 12'hC1B; \ localparam [11:0] csr_mindex_mhpmcounter27h = 12'hB9B; \ localparam [11:0] csr_sindex_mhpmcounter27h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter27h = 12'hC9B; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER28 `define rvformal_csr_mhpmcounter28_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_wdata; `define rvformal_csr_mhpmcounter28_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_wdata `define rvformal_csr_mhpmcounter28_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter28_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter28_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter28_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter28_wdata `define rvformal_csr_mhpmcounter28_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_wdata `define rvformal_csr_mhpmcounter28_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter28_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter28_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter28_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter28_wdata `define rvformal_csr_mhpmcounter28_conn, \ .rvfi_csr_mhpmcounter28_rmask (rvfi_csr_mhpmcounter28_rmask), \ .rvfi_csr_mhpmcounter28_wmask (rvfi_csr_mhpmcounter28_wmask), \ .rvfi_csr_mhpmcounter28_rdata (rvfi_csr_mhpmcounter28_rdata), \ .rvfi_csr_mhpmcounter28_wdata (rvfi_csr_mhpmcounter28_wdata) `define rvformal_csr_mhpmcounter28_channel_conn(_idx), \ .rvfi_csr_mhpmcounter28_rmask (rvfi_csr_mhpmcounter28_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter28_wmask (rvfi_csr_mhpmcounter28_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter28_rdata (rvfi_csr_mhpmcounter28_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter28_wdata (rvfi_csr_mhpmcounter28_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter28_conn32, \ .rvfi_csr_mhpmcounter28_rmask (rvfi_csr_mhpmcounter28_rmask[31: 0]), \ .rvfi_csr_mhpmcounter28_wmask (rvfi_csr_mhpmcounter28_wmask[31: 0]), \ .rvfi_csr_mhpmcounter28_rdata (rvfi_csr_mhpmcounter28_rdata[31: 0]), \ .rvfi_csr_mhpmcounter28_wdata (rvfi_csr_mhpmcounter28_wdata[31: 0]), \ .rvfi_csr_mhpmcounter28h_rmask (rvfi_csr_mhpmcounter28_rmask[63:32]), \ .rvfi_csr_mhpmcounter28h_wmask (rvfi_csr_mhpmcounter28_wmask[63:32]), \ .rvfi_csr_mhpmcounter28h_rdata (rvfi_csr_mhpmcounter28_rdata[63:32]), \ .rvfi_csr_mhpmcounter28h_wdata (rvfi_csr_mhpmcounter28_wdata[63:32]) `define rvformal_csr_mhpmcounter28_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter28_rmask = rvfi_csr_mhpmcounter28_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter28_wmask = rvfi_csr_mhpmcounter28_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter28_rdata = rvfi_csr_mhpmcounter28_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter28_wdata = rvfi_csr_mhpmcounter28_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter28_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter28_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter28_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter28_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter28_wdata) `else `define rvformal_csr_mhpmcounter28_wires `define rvformal_csr_mhpmcounter28_outputs `define rvformal_csr_mhpmcounter28_inputs `define rvformal_csr_mhpmcounter28_conn `define rvformal_csr_mhpmcounter28_conn32 `define rvformal_csr_mhpmcounter28_channel(_idx) `endif `define rvformal_csr_mhpmcounter28_indices \ localparam [11:0] csr_mindex_mhpmcounter28 = 12'hB1C; \ localparam [11:0] csr_sindex_mhpmcounter28 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter28 = 12'hC1C; \ localparam [11:0] csr_mindex_mhpmcounter28h = 12'hB9C; \ localparam [11:0] csr_sindex_mhpmcounter28h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter28h = 12'hC9C; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER29 `define rvformal_csr_mhpmcounter29_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_wdata; `define rvformal_csr_mhpmcounter29_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_wdata `define rvformal_csr_mhpmcounter29_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter29_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter29_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter29_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter29_wdata `define rvformal_csr_mhpmcounter29_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_wdata `define rvformal_csr_mhpmcounter29_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter29_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter29_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter29_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter29_wdata `define rvformal_csr_mhpmcounter29_conn, \ .rvfi_csr_mhpmcounter29_rmask (rvfi_csr_mhpmcounter29_rmask), \ .rvfi_csr_mhpmcounter29_wmask (rvfi_csr_mhpmcounter29_wmask), \ .rvfi_csr_mhpmcounter29_rdata (rvfi_csr_mhpmcounter29_rdata), \ .rvfi_csr_mhpmcounter29_wdata (rvfi_csr_mhpmcounter29_wdata) `define rvformal_csr_mhpmcounter29_channel_conn(_idx), \ .rvfi_csr_mhpmcounter29_rmask (rvfi_csr_mhpmcounter29_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter29_wmask (rvfi_csr_mhpmcounter29_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter29_rdata (rvfi_csr_mhpmcounter29_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter29_wdata (rvfi_csr_mhpmcounter29_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter29_conn32, \ .rvfi_csr_mhpmcounter29_rmask (rvfi_csr_mhpmcounter29_rmask[31: 0]), \ .rvfi_csr_mhpmcounter29_wmask (rvfi_csr_mhpmcounter29_wmask[31: 0]), \ .rvfi_csr_mhpmcounter29_rdata (rvfi_csr_mhpmcounter29_rdata[31: 0]), \ .rvfi_csr_mhpmcounter29_wdata (rvfi_csr_mhpmcounter29_wdata[31: 0]), \ .rvfi_csr_mhpmcounter29h_rmask (rvfi_csr_mhpmcounter29_rmask[63:32]), \ .rvfi_csr_mhpmcounter29h_wmask (rvfi_csr_mhpmcounter29_wmask[63:32]), \ .rvfi_csr_mhpmcounter29h_rdata (rvfi_csr_mhpmcounter29_rdata[63:32]), \ .rvfi_csr_mhpmcounter29h_wdata (rvfi_csr_mhpmcounter29_wdata[63:32]) `define rvformal_csr_mhpmcounter29_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter29_rmask = rvfi_csr_mhpmcounter29_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter29_wmask = rvfi_csr_mhpmcounter29_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter29_rdata = rvfi_csr_mhpmcounter29_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter29_wdata = rvfi_csr_mhpmcounter29_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter29_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter29_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter29_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter29_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter29_wdata) `else `define rvformal_csr_mhpmcounter29_wires `define rvformal_csr_mhpmcounter29_outputs `define rvformal_csr_mhpmcounter29_inputs `define rvformal_csr_mhpmcounter29_conn `define rvformal_csr_mhpmcounter29_conn32 `define rvformal_csr_mhpmcounter29_channel(_idx) `endif `define rvformal_csr_mhpmcounter29_indices \ localparam [11:0] csr_mindex_mhpmcounter29 = 12'hB1D; \ localparam [11:0] csr_sindex_mhpmcounter29 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter29 = 12'hC1D; \ localparam [11:0] csr_mindex_mhpmcounter29h = 12'hB9D; \ localparam [11:0] csr_sindex_mhpmcounter29h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter29h = 12'hC9D; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER30 `define rvformal_csr_mhpmcounter30_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_wdata; `define rvformal_csr_mhpmcounter30_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_wdata `define rvformal_csr_mhpmcounter30_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter30_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter30_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter30_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter30_wdata `define rvformal_csr_mhpmcounter30_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_wdata `define rvformal_csr_mhpmcounter30_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter30_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter30_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter30_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter30_wdata `define rvformal_csr_mhpmcounter30_conn, \ .rvfi_csr_mhpmcounter30_rmask (rvfi_csr_mhpmcounter30_rmask), \ .rvfi_csr_mhpmcounter30_wmask (rvfi_csr_mhpmcounter30_wmask), \ .rvfi_csr_mhpmcounter30_rdata (rvfi_csr_mhpmcounter30_rdata), \ .rvfi_csr_mhpmcounter30_wdata (rvfi_csr_mhpmcounter30_wdata) `define rvformal_csr_mhpmcounter30_channel_conn(_idx), \ .rvfi_csr_mhpmcounter30_rmask (rvfi_csr_mhpmcounter30_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter30_wmask (rvfi_csr_mhpmcounter30_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter30_rdata (rvfi_csr_mhpmcounter30_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter30_wdata (rvfi_csr_mhpmcounter30_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter30_conn32, \ .rvfi_csr_mhpmcounter30_rmask (rvfi_csr_mhpmcounter30_rmask[31: 0]), \ .rvfi_csr_mhpmcounter30_wmask (rvfi_csr_mhpmcounter30_wmask[31: 0]), \ .rvfi_csr_mhpmcounter30_rdata (rvfi_csr_mhpmcounter30_rdata[31: 0]), \ .rvfi_csr_mhpmcounter30_wdata (rvfi_csr_mhpmcounter30_wdata[31: 0]), \ .rvfi_csr_mhpmcounter30h_rmask (rvfi_csr_mhpmcounter30_rmask[63:32]), \ .rvfi_csr_mhpmcounter30h_wmask (rvfi_csr_mhpmcounter30_wmask[63:32]), \ .rvfi_csr_mhpmcounter30h_rdata (rvfi_csr_mhpmcounter30_rdata[63:32]), \ .rvfi_csr_mhpmcounter30h_wdata (rvfi_csr_mhpmcounter30_wdata[63:32]) `define rvformal_csr_mhpmcounter30_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter30_rmask = rvfi_csr_mhpmcounter30_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter30_wmask = rvfi_csr_mhpmcounter30_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter30_rdata = rvfi_csr_mhpmcounter30_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter30_wdata = rvfi_csr_mhpmcounter30_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter30_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter30_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter30_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter30_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter30_wdata) `else `define rvformal_csr_mhpmcounter30_wires `define rvformal_csr_mhpmcounter30_outputs `define rvformal_csr_mhpmcounter30_inputs `define rvformal_csr_mhpmcounter30_conn `define rvformal_csr_mhpmcounter30_conn32 `define rvformal_csr_mhpmcounter30_channel(_idx) `endif `define rvformal_csr_mhpmcounter30_indices \ localparam [11:0] csr_mindex_mhpmcounter30 = 12'hB1E; \ localparam [11:0] csr_sindex_mhpmcounter30 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter30 = 12'hC1E; \ localparam [11:0] csr_mindex_mhpmcounter30h = 12'hB9E; \ localparam [11:0] csr_sindex_mhpmcounter30h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter30h = 12'hC9E; \ `ifdef RISCV_FORMAL_CSR_MHPMCOUNTER31 `define rvformal_csr_mhpmcounter31_wires \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_wdata; `define rvformal_csr_mhpmcounter31_outputs, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_rmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_wmask, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_rdata, \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_wdata `define rvformal_csr_mhpmcounter31_channel_outputs, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter31_rmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter31_wmask, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter31_rdata, \ output [64 - 1 : 0] rvfi_csr_mhpmcounter31_wdata `define rvformal_csr_mhpmcounter31_inputs, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_rmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_wmask, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_rdata, \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_wdata `define rvformal_csr_mhpmcounter31_channel_inputs, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter31_rmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter31_wmask, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter31_rdata, \ input [64 - 1 : 0] rvfi_csr_mhpmcounter31_wdata `define rvformal_csr_mhpmcounter31_conn, \ .rvfi_csr_mhpmcounter31_rmask (rvfi_csr_mhpmcounter31_rmask), \ .rvfi_csr_mhpmcounter31_wmask (rvfi_csr_mhpmcounter31_wmask), \ .rvfi_csr_mhpmcounter31_rdata (rvfi_csr_mhpmcounter31_rdata), \ .rvfi_csr_mhpmcounter31_wdata (rvfi_csr_mhpmcounter31_wdata) `define rvformal_csr_mhpmcounter31_channel_conn(_idx), \ .rvfi_csr_mhpmcounter31_rmask (rvfi_csr_mhpmcounter31_rmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter31_wmask (rvfi_csr_mhpmcounter31_wmask [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter31_rdata (rvfi_csr_mhpmcounter31_rdata [(_idx)*(64) +: 64]), \ .rvfi_csr_mhpmcounter31_wdata (rvfi_csr_mhpmcounter31_wdata [(_idx)*(64) +: 64]) `define rvformal_csr_mhpmcounter31_conn32, \ .rvfi_csr_mhpmcounter31_rmask (rvfi_csr_mhpmcounter31_rmask[31: 0]), \ .rvfi_csr_mhpmcounter31_wmask (rvfi_csr_mhpmcounter31_wmask[31: 0]), \ .rvfi_csr_mhpmcounter31_rdata (rvfi_csr_mhpmcounter31_rdata[31: 0]), \ .rvfi_csr_mhpmcounter31_wdata (rvfi_csr_mhpmcounter31_wdata[31: 0]), \ .rvfi_csr_mhpmcounter31h_rmask (rvfi_csr_mhpmcounter31_rmask[63:32]), \ .rvfi_csr_mhpmcounter31h_wmask (rvfi_csr_mhpmcounter31_wmask[63:32]), \ .rvfi_csr_mhpmcounter31h_rdata (rvfi_csr_mhpmcounter31_rdata[63:32]), \ .rvfi_csr_mhpmcounter31h_wdata (rvfi_csr_mhpmcounter31_wdata[63:32]) `define rvformal_csr_mhpmcounter31_channel(_idx) \ wire [64 - 1 : 0] csr_mhpmcounter31_rmask = rvfi_csr_mhpmcounter31_rmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter31_wmask = rvfi_csr_mhpmcounter31_wmask [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter31_rdata = rvfi_csr_mhpmcounter31_rdata [(_idx)*(64) +: 64]; \ wire [64 - 1 : 0] csr_mhpmcounter31_wdata = rvfi_csr_mhpmcounter31_wdata [(_idx)*(64) +: 64]; `define rvformal_csr_mhpmcounter31_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter31_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter31_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter31_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter31_wdata) `else `define rvformal_csr_mhpmcounter31_wires `define rvformal_csr_mhpmcounter31_outputs `define rvformal_csr_mhpmcounter31_inputs `define rvformal_csr_mhpmcounter31_conn `define rvformal_csr_mhpmcounter31_conn32 `define rvformal_csr_mhpmcounter31_channel(_idx) `endif `define rvformal_csr_mhpmcounter31_indices \ localparam [11:0] csr_mindex_mhpmcounter31 = 12'hB1F; \ localparam [11:0] csr_sindex_mhpmcounter31 = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter31 = 12'hC1F; \ localparam [11:0] csr_mindex_mhpmcounter31h = 12'hB9F; \ localparam [11:0] csr_sindex_mhpmcounter31h = 12'hFFF; \ localparam [11:0] csr_uindex_mhpmcounter31h = 12'hC9F; \ `define RVFI_INDICES \ `rvformal_csr_fflags_indices \ `rvformal_csr_frm_indices \ `rvformal_csr_fcsr_indices \ `rvformal_csr_mvendorid_indices \ `rvformal_csr_marchid_indices \ `rvformal_csr_mimpid_indices \ `rvformal_csr_mhartid_indices \ `rvformal_csr_mconfigptr_indices \ `rvformal_csr_mstatus_indices \ `rvformal_csr_mstatush_indices \ `rvformal_csr_misa_indices \ `rvformal_csr_medeleg_indices \ `rvformal_csr_mideleg_indices \ `rvformal_csr_mie_indices \ `rvformal_csr_mtvec_indices \ `rvformal_csr_mcounteren_indices \ `rvformal_csr_mscratch_indices \ `rvformal_csr_mepc_indices \ `rvformal_csr_mcause_indices \ `rvformal_csr_mtval_indices \ `rvformal_csr_mip_indices \ `rvformal_csr_mtinst_indices \ `rvformal_csr_mtval2_indices \ `rvformal_csr_mcountinhibit_indices \ `rvformal_csr_menvcfg_indices \ `rvformal_csr_menvcfgh_indices \ `rvformal_csr_pmpcfg0_indices \ `rvformal_csr_pmpcfg1_indices \ `rvformal_csr_pmpcfg2_indices \ `rvformal_csr_pmpcfg3_indices \ `rvformal_csr_pmpcfg4_indices \ `rvformal_csr_pmpcfg5_indices \ `rvformal_csr_pmpcfg6_indices \ `rvformal_csr_pmpcfg7_indices \ `rvformal_csr_pmpcfg8_indices \ `rvformal_csr_pmpcfg9_indices \ `rvformal_csr_pmpcfg10_indices \ `rvformal_csr_pmpcfg11_indices \ `rvformal_csr_pmpcfg12_indices \ `rvformal_csr_pmpcfg13_indices \ `rvformal_csr_pmpcfg14_indices \ `rvformal_csr_pmpcfg15_indices \ `rvformal_csr_pmpaddr0_indices \ `rvformal_csr_pmpaddr1_indices \ `rvformal_csr_pmpaddr2_indices \ `rvformal_csr_pmpaddr3_indices \ `rvformal_csr_pmpaddr4_indices \ `rvformal_csr_pmpaddr5_indices \ `rvformal_csr_pmpaddr6_indices \ `rvformal_csr_pmpaddr7_indices \ `rvformal_csr_pmpaddr8_indices \ `rvformal_csr_pmpaddr9_indices \ `rvformal_csr_pmpaddr10_indices \ `rvformal_csr_pmpaddr11_indices \ `rvformal_csr_pmpaddr12_indices \ `rvformal_csr_pmpaddr13_indices \ `rvformal_csr_pmpaddr14_indices \ `rvformal_csr_pmpaddr15_indices \ `rvformal_csr_pmpaddr16_indices \ `rvformal_csr_pmpaddr17_indices \ `rvformal_csr_pmpaddr18_indices \ `rvformal_csr_pmpaddr19_indices \ `rvformal_csr_pmpaddr20_indices \ `rvformal_csr_pmpaddr21_indices \ `rvformal_csr_pmpaddr22_indices \ `rvformal_csr_pmpaddr23_indices \ `rvformal_csr_pmpaddr24_indices \ `rvformal_csr_pmpaddr25_indices \ `rvformal_csr_pmpaddr26_indices \ `rvformal_csr_pmpaddr27_indices \ `rvformal_csr_pmpaddr28_indices \ `rvformal_csr_pmpaddr29_indices \ `rvformal_csr_pmpaddr30_indices \ `rvformal_csr_pmpaddr31_indices \ `rvformal_csr_pmpaddr32_indices \ `rvformal_csr_pmpaddr33_indices \ `rvformal_csr_pmpaddr34_indices \ `rvformal_csr_pmpaddr35_indices \ `rvformal_csr_pmpaddr36_indices \ `rvformal_csr_pmpaddr37_indices \ `rvformal_csr_pmpaddr38_indices \ `rvformal_csr_pmpaddr39_indices \ `rvformal_csr_pmpaddr40_indices \ `rvformal_csr_pmpaddr41_indices \ `rvformal_csr_pmpaddr42_indices \ `rvformal_csr_pmpaddr43_indices \ `rvformal_csr_pmpaddr44_indices \ `rvformal_csr_pmpaddr45_indices \ `rvformal_csr_pmpaddr46_indices \ `rvformal_csr_pmpaddr47_indices \ `rvformal_csr_pmpaddr48_indices \ `rvformal_csr_pmpaddr49_indices \ `rvformal_csr_pmpaddr50_indices \ `rvformal_csr_pmpaddr51_indices \ `rvformal_csr_pmpaddr52_indices \ `rvformal_csr_pmpaddr53_indices \ `rvformal_csr_pmpaddr54_indices \ `rvformal_csr_pmpaddr55_indices \ `rvformal_csr_pmpaddr56_indices \ `rvformal_csr_pmpaddr57_indices \ `rvformal_csr_pmpaddr58_indices \ `rvformal_csr_pmpaddr59_indices \ `rvformal_csr_pmpaddr60_indices \ `rvformal_csr_pmpaddr61_indices \ `rvformal_csr_pmpaddr62_indices \ `rvformal_csr_pmpaddr63_indices \ `rvformal_csr_mhpmevent3_indices \ `rvformal_csr_mhpmevent4_indices \ `rvformal_csr_mhpmevent5_indices \ `rvformal_csr_mhpmevent6_indices \ `rvformal_csr_mhpmevent7_indices \ `rvformal_csr_mhpmevent8_indices \ `rvformal_csr_mhpmevent9_indices \ `rvformal_csr_mhpmevent10_indices \ `rvformal_csr_mhpmevent11_indices \ `rvformal_csr_mhpmevent12_indices \ `rvformal_csr_mhpmevent13_indices \ `rvformal_csr_mhpmevent14_indices \ `rvformal_csr_mhpmevent15_indices \ `rvformal_csr_mhpmevent16_indices \ `rvformal_csr_mhpmevent17_indices \ `rvformal_csr_mhpmevent18_indices \ `rvformal_csr_mhpmevent19_indices \ `rvformal_csr_mhpmevent20_indices \ `rvformal_csr_mhpmevent21_indices \ `rvformal_csr_mhpmevent22_indices \ `rvformal_csr_mhpmevent23_indices \ `rvformal_csr_mhpmevent24_indices \ `rvformal_csr_mhpmevent25_indices \ `rvformal_csr_mhpmevent26_indices \ `rvformal_csr_mhpmevent27_indices \ `rvformal_csr_mhpmevent28_indices \ `rvformal_csr_mhpmevent29_indices \ `rvformal_csr_mhpmevent30_indices \ `rvformal_csr_mhpmevent31_indices \ `rvformal_csr_mcycle_indices \ `rvformal_csr_time_indices \ `rvformal_csr_minstret_indices \ `rvformal_csr_mhpmcounter3_indices \ `rvformal_csr_mhpmcounter4_indices \ `rvformal_csr_mhpmcounter5_indices \ `rvformal_csr_mhpmcounter6_indices \ `rvformal_csr_mhpmcounter7_indices \ `rvformal_csr_mhpmcounter8_indices \ `rvformal_csr_mhpmcounter9_indices \ `rvformal_csr_mhpmcounter10_indices \ `rvformal_csr_mhpmcounter11_indices \ `rvformal_csr_mhpmcounter12_indices \ `rvformal_csr_mhpmcounter13_indices \ `rvformal_csr_mhpmcounter14_indices \ `rvformal_csr_mhpmcounter15_indices \ `rvformal_csr_mhpmcounter16_indices \ `rvformal_csr_mhpmcounter17_indices \ `rvformal_csr_mhpmcounter18_indices \ `rvformal_csr_mhpmcounter19_indices \ `rvformal_csr_mhpmcounter20_indices \ `rvformal_csr_mhpmcounter21_indices \ `rvformal_csr_mhpmcounter22_indices \ `rvformal_csr_mhpmcounter23_indices \ `rvformal_csr_mhpmcounter24_indices \ `rvformal_csr_mhpmcounter25_indices \ `rvformal_csr_mhpmcounter26_indices \ `rvformal_csr_mhpmcounter27_indices \ `rvformal_csr_mhpmcounter28_indices \ `rvformal_csr_mhpmcounter29_indices \ `rvformal_csr_mhpmcounter30_indices \ `rvformal_csr_mhpmcounter31_indices \ `rvformal_custom_csr_indices `ifdef RISCV_FORMAL_CUSTOM_CSR_INPUTS `define rvformal_custom_csr_inputs `RISCV_FORMAL_CUSTOM_CSR_INPUTS `else `define rvformal_custom_csr_inputs `endif `ifdef RISCV_FORMAL_CUSTOM_CSR_WIRES `define rvformal_custom_csr_wires `RISCV_FORMAL_CUSTOM_CSR_WIRES `else `define rvformal_custom_csr_wires `endif `ifdef RISCV_FORMAL_CUSTOM_CSR_CONN `define rvformal_custom_csr_conn `RISCV_FORMAL_CUSTOM_CSR_CONN `else `define rvformal_custom_csr_conn `endif `ifdef RISCV_FORMAL_CUSTOM_CSR_CHANNEL `define rvformal_custom_csr_channel(_idx) `RISCV_FORMAL_CUSTOM_CSR_CHANNEL(_idx) `else `define rvformal_custom_csr_channel(_idx) `endif `ifdef RISCV_FORMAL_CUSTOM_CSR_SIGNALS `define rvformal_custom_csr_signals `RISCV_FORMAL_CUSTOM_CSR_SIGNALS `else `define rvformal_custom_csr_signals `endif `ifdef RISCV_FORMAL_CUSTOM_CSR_OUTPUTS `define rvformal_custom_csr_outputs `RISCV_FORMAL_CUSTOM_CSR_OUTPUTS `else `define rvformal_custom_csr_outputs `endif `ifdef RISCV_FORMAL_CUSTOM_CSR_INDICES `define rvformal_custom_csr_indices `RISCV_FORMAL_CUSTOM_CSR_INDICES `else `define rvformal_custom_csr_indices `endif `ifdef RISCV_FORMAL_ROLLBACK `define rvformal_rollback_wires \ (* keep *) wire [ 0 : 0] rvfi_rollback_valid; \ (* keep *) wire [64 - 1 : 0] rvfi_rollback_order; `define rvformal_rollback_outputs, \ output [ 0 : 0] rvfi_rollback_valid, \ output [64 - 1 : 0] rvfi_rollback_order `define rvformal_rollback_channel_outputs, \ output [ 0 : 0] rvfi_rollback_valid, \ output [64 - 1 : 0] rvfi_rollback_order `define rvformal_rollback_inputs, \ input [ 0 : 0] rvfi_rollback_valid, \ input [64 - 1 : 0] rvfi_rollback_order `define rvformal_rollback_channel_inputs, \ input [ 0 : 0] rvfi_rollback_valid, \ input [64 - 1 : 0] rvfi_rollback_order `define rvformal_rollback_conn, \ .rvfi_rollback_valid (rvfi_rollback_valid), \ .rvfi_rollback_order (rvfi_rollback_order) `define rvformal_rollback_channel_conn(_idx), \ .rvfi_rollback_valid (rvfi_rollback_valid [ _idx +: 1]), \ .rvfi_rollback_order (rvfi_rollback_order [(_idx)*(64) +: 64]) `else `define rvformal_rollback_wires `define rvformal_rollback_outputs `define rvformal_rollback_inputs `define rvformal_rollback_conn `endif `ifdef RISCV_FORMAL_EXTAMO `define rvformal_extamo_wires \ (* keep *) wire [`RISCV_FORMAL_NRET - 1 : 0] rvfi_mem_extamo; `define rvformal_extamo_outputs, \ output [`RISCV_FORMAL_NRET - 1 : 0] rvfi_mem_extamo `define rvformal_extamo_channel_outputs, \ output [ 0 : 0] rvfi_mem_extamo `define rvformal_extamo_inputs, \ input [`RISCV_FORMAL_NRET - 1 : 0] rvfi_mem_extamo `define rvformal_extamo_channel_inputs, \ input [ 0 : 0] rvfi_mem_extamo `define rvformal_extamo_conn, \ .rvfi_mem_extamo (rvfi_mem_extamo) `define rvformal_extamo_channel_conn(_idx), \ .rvfi_mem_extamo (rvfi_mem_extamo [ _idx +: 1]) `define rvformal_extamo_channel(_idx) \ wire [ 0 : 0] mem_extamo = rvfi_mem_extamo [ _idx +: 1]; `define rvformal_extamo_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 1, mem_extamo) `else `define rvformal_extamo_wires `define rvformal_extamo_outputs `define rvformal_extamo_inputs `define rvformal_extamo_conn `define rvformal_extamo_channel(_idx) `endif `ifdef RISCV_FORMAL_MEM_FAULT `define rvformal_mem_fault_wires \ (* keep *) wire [`RISCV_FORMAL_NRET - 1 : 0] rvfi_mem_fault ; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_wmask; `define rvformal_mem_fault_outputs, \ output [`RISCV_FORMAL_NRET - 1 : 0] rvfi_mem_fault , \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_wmask `define rvformal_mem_fault_channel_outputs, \ output [ 0 : 0] rvfi_mem_fault , \ output [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_rmask, \ output [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_wmask `define rvformal_mem_fault_inputs, \ input [`RISCV_FORMAL_NRET - 1 : 0] rvfi_mem_fault , \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_wmask `define rvformal_mem_fault_channel_inputs, \ input [ 0 : 0] rvfi_mem_fault , \ input [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_rmask, \ input [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_wmask `define rvformal_mem_fault_conn, \ .rvfi_mem_fault (rvfi_mem_fault ), \ .rvfi_mem_fault_rmask (rvfi_mem_fault_rmask), \ .rvfi_mem_fault_wmask (rvfi_mem_fault_wmask) `define rvformal_mem_fault_channel_conn(_idx), \ .rvfi_mem_fault (rvfi_mem_fault [ _idx +: 1 ]), \ .rvfi_mem_fault_rmask (rvfi_mem_fault_rmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8]), \ .rvfi_mem_fault_wmask (rvfi_mem_fault_wmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8]) `define rvformal_mem_fault_channel(_idx) \ wire [ 0 : 0] mem_fault = rvfi_mem_fault [ _idx +: 1 ]; \ wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_fault_rmask = rvfi_mem_fault_rmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8]; \ wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_fault_wmask = rvfi_mem_fault_wmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8]; `define rvformal_mem_fault_signals \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 1 , mem_fault ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN/8, mem_fault_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN/8, mem_fault_wmask) `else `define rvformal_mem_fault_wires `define rvformal_mem_fault_outputs `define rvformal_mem_fault_inputs `define rvformal_mem_fault_conn `define rvformal_mem_fault_channel(_idx) `endif `define RVFI_WIRES \ (* keep *) wire [`RISCV_FORMAL_NRET - 1 : 0] rvfi_valid ; \ (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_order ; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn ; \ (* keep *) wire [`RISCV_FORMAL_NRET - 1 : 0] rvfi_trap ; \ (* keep *) wire [`RISCV_FORMAL_NRET - 1 : 0] rvfi_halt ; \ (* keep *) wire [`RISCV_FORMAL_NRET - 1 : 0] rvfi_intr ; \ (* keep *) wire [`RISCV_FORMAL_NRET * 2 - 1 : 0] rvfi_mode ; \ (* keep *) wire [`RISCV_FORMAL_NRET * 2 - 1 : 0] rvfi_ixl ; \ (* keep *) wire [`RISCV_FORMAL_NRET * 5 - 1 : 0] rvfi_rs1_addr ; \ (* keep *) wire [`RISCV_FORMAL_NRET * 5 - 1 : 0] rvfi_rs2_addr ; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * 5 - 1 : 0] rvfi_rd_addr ; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_rd_wdata ; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata ; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_wdata ; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_addr ; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_rmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_wmask; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata; \ (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_wdata; \ `rvformal_extamo_wires \ `rvformal_rollback_wires \ `rvformal_mem_fault_wires \ `rvformal_csr_fflags_wires \ `rvformal_csr_frm_wires \ `rvformal_csr_fcsr_wires \ `rvformal_csr_mvendorid_wires \ `rvformal_csr_marchid_wires \ `rvformal_csr_mimpid_wires \ `rvformal_csr_mhartid_wires \ `rvformal_csr_mconfigptr_wires \ `rvformal_csr_mstatus_wires \ `rvformal_csr_mstatush_wires \ `rvformal_csr_misa_wires \ `rvformal_csr_medeleg_wires \ `rvformal_csr_mideleg_wires \ `rvformal_csr_mie_wires \ `rvformal_csr_mtvec_wires \ `rvformal_csr_mcounteren_wires \ `rvformal_csr_mscratch_wires \ `rvformal_csr_mepc_wires \ `rvformal_csr_mcause_wires \ `rvformal_csr_mtval_wires \ `rvformal_csr_mip_wires \ `rvformal_csr_mtinst_wires \ `rvformal_csr_mtval2_wires \ `rvformal_csr_mcountinhibit_wires \ `rvformal_csr_menvcfg_wires \ `rvformal_csr_menvcfgh_wires \ `rvformal_csr_pmpcfg0_wires \ `rvformal_csr_pmpcfg1_wires \ `rvformal_csr_pmpcfg2_wires \ `rvformal_csr_pmpcfg3_wires \ `rvformal_csr_pmpcfg4_wires \ `rvformal_csr_pmpcfg5_wires \ `rvformal_csr_pmpcfg6_wires \ `rvformal_csr_pmpcfg7_wires \ `rvformal_csr_pmpcfg8_wires \ `rvformal_csr_pmpcfg9_wires \ `rvformal_csr_pmpcfg10_wires \ `rvformal_csr_pmpcfg11_wires \ `rvformal_csr_pmpcfg12_wires \ `rvformal_csr_pmpcfg13_wires \ `rvformal_csr_pmpcfg14_wires \ `rvformal_csr_pmpcfg15_wires \ `rvformal_csr_pmpaddr0_wires \ `rvformal_csr_pmpaddr1_wires \ `rvformal_csr_pmpaddr2_wires \ `rvformal_csr_pmpaddr3_wires \ `rvformal_csr_pmpaddr4_wires \ `rvformal_csr_pmpaddr5_wires \ `rvformal_csr_pmpaddr6_wires \ `rvformal_csr_pmpaddr7_wires \ `rvformal_csr_pmpaddr8_wires \ `rvformal_csr_pmpaddr9_wires \ `rvformal_csr_pmpaddr10_wires \ `rvformal_csr_pmpaddr11_wires \ `rvformal_csr_pmpaddr12_wires \ `rvformal_csr_pmpaddr13_wires \ `rvformal_csr_pmpaddr14_wires \ `rvformal_csr_pmpaddr15_wires \ `rvformal_csr_pmpaddr16_wires \ `rvformal_csr_pmpaddr17_wires \ `rvformal_csr_pmpaddr18_wires \ `rvformal_csr_pmpaddr19_wires \ `rvformal_csr_pmpaddr20_wires \ `rvformal_csr_pmpaddr21_wires \ `rvformal_csr_pmpaddr22_wires \ `rvformal_csr_pmpaddr23_wires \ `rvformal_csr_pmpaddr24_wires \ `rvformal_csr_pmpaddr25_wires \ `rvformal_csr_pmpaddr26_wires \ `rvformal_csr_pmpaddr27_wires \ `rvformal_csr_pmpaddr28_wires \ `rvformal_csr_pmpaddr29_wires \ `rvformal_csr_pmpaddr30_wires \ `rvformal_csr_pmpaddr31_wires \ `rvformal_csr_pmpaddr32_wires \ `rvformal_csr_pmpaddr33_wires \ `rvformal_csr_pmpaddr34_wires \ `rvformal_csr_pmpaddr35_wires \ `rvformal_csr_pmpaddr36_wires \ `rvformal_csr_pmpaddr37_wires \ `rvformal_csr_pmpaddr38_wires \ `rvformal_csr_pmpaddr39_wires \ `rvformal_csr_pmpaddr40_wires \ `rvformal_csr_pmpaddr41_wires \ `rvformal_csr_pmpaddr42_wires \ `rvformal_csr_pmpaddr43_wires \ `rvformal_csr_pmpaddr44_wires \ `rvformal_csr_pmpaddr45_wires \ `rvformal_csr_pmpaddr46_wires \ `rvformal_csr_pmpaddr47_wires \ `rvformal_csr_pmpaddr48_wires \ `rvformal_csr_pmpaddr49_wires \ `rvformal_csr_pmpaddr50_wires \ `rvformal_csr_pmpaddr51_wires \ `rvformal_csr_pmpaddr52_wires \ `rvformal_csr_pmpaddr53_wires \ `rvformal_csr_pmpaddr54_wires \ `rvformal_csr_pmpaddr55_wires \ `rvformal_csr_pmpaddr56_wires \ `rvformal_csr_pmpaddr57_wires \ `rvformal_csr_pmpaddr58_wires \ `rvformal_csr_pmpaddr59_wires \ `rvformal_csr_pmpaddr60_wires \ `rvformal_csr_pmpaddr61_wires \ `rvformal_csr_pmpaddr62_wires \ `rvformal_csr_pmpaddr63_wires \ `rvformal_csr_mhpmevent3_wires \ `rvformal_csr_mhpmevent4_wires \ `rvformal_csr_mhpmevent5_wires \ `rvformal_csr_mhpmevent6_wires \ `rvformal_csr_mhpmevent7_wires \ `rvformal_csr_mhpmevent8_wires \ `rvformal_csr_mhpmevent9_wires \ `rvformal_csr_mhpmevent10_wires \ `rvformal_csr_mhpmevent11_wires \ `rvformal_csr_mhpmevent12_wires \ `rvformal_csr_mhpmevent13_wires \ `rvformal_csr_mhpmevent14_wires \ `rvformal_csr_mhpmevent15_wires \ `rvformal_csr_mhpmevent16_wires \ `rvformal_csr_mhpmevent17_wires \ `rvformal_csr_mhpmevent18_wires \ `rvformal_csr_mhpmevent19_wires \ `rvformal_csr_mhpmevent20_wires \ `rvformal_csr_mhpmevent21_wires \ `rvformal_csr_mhpmevent22_wires \ `rvformal_csr_mhpmevent23_wires \ `rvformal_csr_mhpmevent24_wires \ `rvformal_csr_mhpmevent25_wires \ `rvformal_csr_mhpmevent26_wires \ `rvformal_csr_mhpmevent27_wires \ `rvformal_csr_mhpmevent28_wires \ `rvformal_csr_mhpmevent29_wires \ `rvformal_csr_mhpmevent30_wires \ `rvformal_csr_mhpmevent31_wires \ `rvformal_csr_mcycle_wires \ `rvformal_csr_time_wires \ `rvformal_csr_minstret_wires \ `rvformal_csr_mhpmcounter3_wires \ `rvformal_csr_mhpmcounter4_wires \ `rvformal_csr_mhpmcounter5_wires \ `rvformal_csr_mhpmcounter6_wires \ `rvformal_csr_mhpmcounter7_wires \ `rvformal_csr_mhpmcounter8_wires \ `rvformal_csr_mhpmcounter9_wires \ `rvformal_csr_mhpmcounter10_wires \ `rvformal_csr_mhpmcounter11_wires \ `rvformal_csr_mhpmcounter12_wires \ `rvformal_csr_mhpmcounter13_wires \ `rvformal_csr_mhpmcounter14_wires \ `rvformal_csr_mhpmcounter15_wires \ `rvformal_csr_mhpmcounter16_wires \ `rvformal_csr_mhpmcounter17_wires \ `rvformal_csr_mhpmcounter18_wires \ `rvformal_csr_mhpmcounter19_wires \ `rvformal_csr_mhpmcounter20_wires \ `rvformal_csr_mhpmcounter21_wires \ `rvformal_csr_mhpmcounter22_wires \ `rvformal_csr_mhpmcounter23_wires \ `rvformal_csr_mhpmcounter24_wires \ `rvformal_csr_mhpmcounter25_wires \ `rvformal_csr_mhpmcounter26_wires \ `rvformal_csr_mhpmcounter27_wires \ `rvformal_csr_mhpmcounter28_wires \ `rvformal_csr_mhpmcounter29_wires \ `rvformal_csr_mhpmcounter30_wires \ `rvformal_csr_mhpmcounter31_wires \ `rvformal_custom_csr_wires `define RVFI_OUTPUTS \ output [`RISCV_FORMAL_NRET - 1 : 0] rvfi_valid , \ output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_order , \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn , \ output [`RISCV_FORMAL_NRET - 1 : 0] rvfi_trap , \ output [`RISCV_FORMAL_NRET - 1 : 0] rvfi_halt , \ output [`RISCV_FORMAL_NRET - 1 : 0] rvfi_intr , \ output [`RISCV_FORMAL_NRET * 2 - 1 : 0] rvfi_mode , \ output [`RISCV_FORMAL_NRET * 2 - 1 : 0] rvfi_ixl , \ output [`RISCV_FORMAL_NRET * 5 - 1 : 0] rvfi_rs1_addr , \ output [`RISCV_FORMAL_NRET * 5 - 1 : 0] rvfi_rs2_addr , \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, \ output [`RISCV_FORMAL_NRET * 5 - 1 : 0] rvfi_rd_addr , \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_rd_wdata , \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata , \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_wdata , \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_addr , \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_rmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_wmask, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, \ output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_wdata \ `rvformal_extamo_outputs \ `rvformal_rollback_outputs \ `rvformal_mem_fault_outputs \ `rvformal_csr_fflags_outputs \ `rvformal_csr_frm_outputs \ `rvformal_csr_fcsr_outputs \ `rvformal_csr_mvendorid_outputs \ `rvformal_csr_marchid_outputs \ `rvformal_csr_mimpid_outputs \ `rvformal_csr_mhartid_outputs \ `rvformal_csr_mconfigptr_outputs \ `rvformal_csr_mstatus_outputs \ `rvformal_csr_mstatush_outputs \ `rvformal_csr_misa_outputs \ `rvformal_csr_medeleg_outputs \ `rvformal_csr_mideleg_outputs \ `rvformal_csr_mie_outputs \ `rvformal_csr_mtvec_outputs \ `rvformal_csr_mcounteren_outputs \ `rvformal_csr_mscratch_outputs \ `rvformal_csr_mepc_outputs \ `rvformal_csr_mcause_outputs \ `rvformal_csr_mtval_outputs \ `rvformal_csr_mip_outputs \ `rvformal_csr_mtinst_outputs \ `rvformal_csr_mtval2_outputs \ `rvformal_csr_mcountinhibit_outputs \ `rvformal_csr_menvcfg_outputs \ `rvformal_csr_menvcfgh_outputs \ `rvformal_csr_pmpcfg0_outputs \ `rvformal_csr_pmpcfg1_outputs \ `rvformal_csr_pmpcfg2_outputs \ `rvformal_csr_pmpcfg3_outputs \ `rvformal_csr_pmpcfg4_outputs \ `rvformal_csr_pmpcfg5_outputs \ `rvformal_csr_pmpcfg6_outputs \ `rvformal_csr_pmpcfg7_outputs \ `rvformal_csr_pmpcfg8_outputs \ `rvformal_csr_pmpcfg9_outputs \ `rvformal_csr_pmpcfg10_outputs \ `rvformal_csr_pmpcfg11_outputs \ `rvformal_csr_pmpcfg12_outputs \ `rvformal_csr_pmpcfg13_outputs \ `rvformal_csr_pmpcfg14_outputs \ `rvformal_csr_pmpcfg15_outputs \ `rvformal_csr_pmpaddr0_outputs \ `rvformal_csr_pmpaddr1_outputs \ `rvformal_csr_pmpaddr2_outputs \ `rvformal_csr_pmpaddr3_outputs \ `rvformal_csr_pmpaddr4_outputs \ `rvformal_csr_pmpaddr5_outputs \ `rvformal_csr_pmpaddr6_outputs \ `rvformal_csr_pmpaddr7_outputs \ `rvformal_csr_pmpaddr8_outputs \ `rvformal_csr_pmpaddr9_outputs \ `rvformal_csr_pmpaddr10_outputs \ `rvformal_csr_pmpaddr11_outputs \ `rvformal_csr_pmpaddr12_outputs \ `rvformal_csr_pmpaddr13_outputs \ `rvformal_csr_pmpaddr14_outputs \ `rvformal_csr_pmpaddr15_outputs \ `rvformal_csr_pmpaddr16_outputs \ `rvformal_csr_pmpaddr17_outputs \ `rvformal_csr_pmpaddr18_outputs \ `rvformal_csr_pmpaddr19_outputs \ `rvformal_csr_pmpaddr20_outputs \ `rvformal_csr_pmpaddr21_outputs \ `rvformal_csr_pmpaddr22_outputs \ `rvformal_csr_pmpaddr23_outputs \ `rvformal_csr_pmpaddr24_outputs \ `rvformal_csr_pmpaddr25_outputs \ `rvformal_csr_pmpaddr26_outputs \ `rvformal_csr_pmpaddr27_outputs \ `rvformal_csr_pmpaddr28_outputs \ `rvformal_csr_pmpaddr29_outputs \ `rvformal_csr_pmpaddr30_outputs \ `rvformal_csr_pmpaddr31_outputs \ `rvformal_csr_pmpaddr32_outputs \ `rvformal_csr_pmpaddr33_outputs \ `rvformal_csr_pmpaddr34_outputs \ `rvformal_csr_pmpaddr35_outputs \ `rvformal_csr_pmpaddr36_outputs \ `rvformal_csr_pmpaddr37_outputs \ `rvformal_csr_pmpaddr38_outputs \ `rvformal_csr_pmpaddr39_outputs \ `rvformal_csr_pmpaddr40_outputs \ `rvformal_csr_pmpaddr41_outputs \ `rvformal_csr_pmpaddr42_outputs \ `rvformal_csr_pmpaddr43_outputs \ `rvformal_csr_pmpaddr44_outputs \ `rvformal_csr_pmpaddr45_outputs \ `rvformal_csr_pmpaddr46_outputs \ `rvformal_csr_pmpaddr47_outputs \ `rvformal_csr_pmpaddr48_outputs \ `rvformal_csr_pmpaddr49_outputs \ `rvformal_csr_pmpaddr50_outputs \ `rvformal_csr_pmpaddr51_outputs \ `rvformal_csr_pmpaddr52_outputs \ `rvformal_csr_pmpaddr53_outputs \ `rvformal_csr_pmpaddr54_outputs \ `rvformal_csr_pmpaddr55_outputs \ `rvformal_csr_pmpaddr56_outputs \ `rvformal_csr_pmpaddr57_outputs \ `rvformal_csr_pmpaddr58_outputs \ `rvformal_csr_pmpaddr59_outputs \ `rvformal_csr_pmpaddr60_outputs \ `rvformal_csr_pmpaddr61_outputs \ `rvformal_csr_pmpaddr62_outputs \ `rvformal_csr_pmpaddr63_outputs \ `rvformal_csr_mhpmevent3_outputs \ `rvformal_csr_mhpmevent4_outputs \ `rvformal_csr_mhpmevent5_outputs \ `rvformal_csr_mhpmevent6_outputs \ `rvformal_csr_mhpmevent7_outputs \ `rvformal_csr_mhpmevent8_outputs \ `rvformal_csr_mhpmevent9_outputs \ `rvformal_csr_mhpmevent10_outputs \ `rvformal_csr_mhpmevent11_outputs \ `rvformal_csr_mhpmevent12_outputs \ `rvformal_csr_mhpmevent13_outputs \ `rvformal_csr_mhpmevent14_outputs \ `rvformal_csr_mhpmevent15_outputs \ `rvformal_csr_mhpmevent16_outputs \ `rvformal_csr_mhpmevent17_outputs \ `rvformal_csr_mhpmevent18_outputs \ `rvformal_csr_mhpmevent19_outputs \ `rvformal_csr_mhpmevent20_outputs \ `rvformal_csr_mhpmevent21_outputs \ `rvformal_csr_mhpmevent22_outputs \ `rvformal_csr_mhpmevent23_outputs \ `rvformal_csr_mhpmevent24_outputs \ `rvformal_csr_mhpmevent25_outputs \ `rvformal_csr_mhpmevent26_outputs \ `rvformal_csr_mhpmevent27_outputs \ `rvformal_csr_mhpmevent28_outputs \ `rvformal_csr_mhpmevent29_outputs \ `rvformal_csr_mhpmevent30_outputs \ `rvformal_csr_mhpmevent31_outputs \ `rvformal_csr_mcycle_outputs \ `rvformal_csr_time_outputs \ `rvformal_csr_minstret_outputs \ `rvformal_csr_mhpmcounter3_outputs \ `rvformal_csr_mhpmcounter4_outputs \ `rvformal_csr_mhpmcounter5_outputs \ `rvformal_csr_mhpmcounter6_outputs \ `rvformal_csr_mhpmcounter7_outputs \ `rvformal_csr_mhpmcounter8_outputs \ `rvformal_csr_mhpmcounter9_outputs \ `rvformal_csr_mhpmcounter10_outputs \ `rvformal_csr_mhpmcounter11_outputs \ `rvformal_csr_mhpmcounter12_outputs \ `rvformal_csr_mhpmcounter13_outputs \ `rvformal_csr_mhpmcounter14_outputs \ `rvformal_csr_mhpmcounter15_outputs \ `rvformal_csr_mhpmcounter16_outputs \ `rvformal_csr_mhpmcounter17_outputs \ `rvformal_csr_mhpmcounter18_outputs \ `rvformal_csr_mhpmcounter19_outputs \ `rvformal_csr_mhpmcounter20_outputs \ `rvformal_csr_mhpmcounter21_outputs \ `rvformal_csr_mhpmcounter22_outputs \ `rvformal_csr_mhpmcounter23_outputs \ `rvformal_csr_mhpmcounter24_outputs \ `rvformal_csr_mhpmcounter25_outputs \ `rvformal_csr_mhpmcounter26_outputs \ `rvformal_csr_mhpmcounter27_outputs \ `rvformal_csr_mhpmcounter28_outputs \ `rvformal_csr_mhpmcounter29_outputs \ `rvformal_csr_mhpmcounter30_outputs \ `rvformal_csr_mhpmcounter31_outputs \ `rvformal_custom_csr_outputs `define RVFI_CHANNEL_OUTPUTS \ output [ 0 : 0] rvfi_valid , \ output [ 64 - 1 : 0] rvfi_order , \ output [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn , \ output [ 0 : 0] rvfi_trap , \ output [ 0 : 0] rvfi_halt , \ output [ 0 : 0] rvfi_intr , \ output [ 2 - 1 : 0] rvfi_mode , \ output [ 2 - 1 : 0] rvfi_ixl , \ output [ 5 - 1 : 0] rvfi_rs1_addr , \ output [ 5 - 1 : 0] rvfi_rs2_addr , \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, \ output [ 5 - 1 : 0] rvfi_rd_addr , \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rd_wdata , \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata , \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_wdata , \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_addr , \ output [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_rmask, \ output [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_wmask, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, \ output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_wdata \ `rvformal_extamo_channel_outputs \ `rvformal_rollback_channel_outputs \ `rvformal_mem_fault_channel_outputs \ `rvformal_csr_fflags_channel_outputs \ `rvformal_csr_frm_channel_outputs \ `rvformal_csr_fcsr_channel_outputs \ `rvformal_csr_mvendorid_channel_outputs \ `rvformal_csr_marchid_channel_outputs \ `rvformal_csr_mimpid_channel_outputs \ `rvformal_csr_mhartid_channel_outputs \ `rvformal_csr_mconfigptr_channel_outputs \ `rvformal_csr_mstatus_channel_outputs \ `rvformal_csr_mstatush_channel_outputs \ `rvformal_csr_misa_channel_outputs \ `rvformal_csr_medeleg_channel_outputs \ `rvformal_csr_mideleg_channel_outputs \ `rvformal_csr_mie_channel_outputs \ `rvformal_csr_mtvec_channel_outputs \ `rvformal_csr_mcounteren_channel_outputs \ `rvformal_csr_mscratch_channel_outputs \ `rvformal_csr_mepc_channel_outputs \ `rvformal_csr_mcause_channel_outputs \ `rvformal_csr_mtval_channel_outputs \ `rvformal_csr_mip_channel_outputs \ `rvformal_csr_mtinst_channel_outputs \ `rvformal_csr_mtval2_channel_outputs \ `rvformal_csr_mcountinhibit_channel_outputs \ `rvformal_csr_menvcfg_channel_outputs \ `rvformal_csr_menvcfgh_channel_outputs \ `rvformal_csr_pmpcfg0_channel_outputs \ `rvformal_csr_pmpcfg1_channel_outputs \ `rvformal_csr_pmpcfg2_channel_outputs \ `rvformal_csr_pmpcfg3_channel_outputs \ `rvformal_csr_pmpcfg4_channel_outputs \ `rvformal_csr_pmpcfg5_channel_outputs \ `rvformal_csr_pmpcfg6_channel_outputs \ `rvformal_csr_pmpcfg7_channel_outputs \ `rvformal_csr_pmpcfg8_channel_outputs \ `rvformal_csr_pmpcfg9_channel_outputs \ `rvformal_csr_pmpcfg10_channel_outputs \ `rvformal_csr_pmpcfg11_channel_outputs \ `rvformal_csr_pmpcfg12_channel_outputs \ `rvformal_csr_pmpcfg13_channel_outputs \ `rvformal_csr_pmpcfg14_channel_outputs \ `rvformal_csr_pmpcfg15_channel_outputs \ `rvformal_csr_pmpaddr0_channel_outputs \ `rvformal_csr_pmpaddr1_channel_outputs \ `rvformal_csr_pmpaddr2_channel_outputs \ `rvformal_csr_pmpaddr3_channel_outputs \ `rvformal_csr_pmpaddr4_channel_outputs \ `rvformal_csr_pmpaddr5_channel_outputs \ `rvformal_csr_pmpaddr6_channel_outputs \ `rvformal_csr_pmpaddr7_channel_outputs \ `rvformal_csr_pmpaddr8_channel_outputs \ `rvformal_csr_pmpaddr9_channel_outputs \ `rvformal_csr_pmpaddr10_channel_outputs \ `rvformal_csr_pmpaddr11_channel_outputs \ `rvformal_csr_pmpaddr12_channel_outputs \ `rvformal_csr_pmpaddr13_channel_outputs \ `rvformal_csr_pmpaddr14_channel_outputs \ `rvformal_csr_pmpaddr15_channel_outputs \ `rvformal_csr_pmpaddr16_channel_outputs \ `rvformal_csr_pmpaddr17_channel_outputs \ `rvformal_csr_pmpaddr18_channel_outputs \ `rvformal_csr_pmpaddr19_channel_outputs \ `rvformal_csr_pmpaddr20_channel_outputs \ `rvformal_csr_pmpaddr21_channel_outputs \ `rvformal_csr_pmpaddr22_channel_outputs \ `rvformal_csr_pmpaddr23_channel_outputs \ `rvformal_csr_pmpaddr24_channel_outputs \ `rvformal_csr_pmpaddr25_channel_outputs \ `rvformal_csr_pmpaddr26_channel_outputs \ `rvformal_csr_pmpaddr27_channel_outputs \ `rvformal_csr_pmpaddr28_channel_outputs \ `rvformal_csr_pmpaddr29_channel_outputs \ `rvformal_csr_pmpaddr30_channel_outputs \ `rvformal_csr_pmpaddr31_channel_outputs \ `rvformal_csr_pmpaddr32_channel_outputs \ `rvformal_csr_pmpaddr33_channel_outputs \ `rvformal_csr_pmpaddr34_channel_outputs \ `rvformal_csr_pmpaddr35_channel_outputs \ `rvformal_csr_pmpaddr36_channel_outputs \ `rvformal_csr_pmpaddr37_channel_outputs \ `rvformal_csr_pmpaddr38_channel_outputs \ `rvformal_csr_pmpaddr39_channel_outputs \ `rvformal_csr_pmpaddr40_channel_outputs \ `rvformal_csr_pmpaddr41_channel_outputs \ `rvformal_csr_pmpaddr42_channel_outputs \ `rvformal_csr_pmpaddr43_channel_outputs \ `rvformal_csr_pmpaddr44_channel_outputs \ `rvformal_csr_pmpaddr45_channel_outputs \ `rvformal_csr_pmpaddr46_channel_outputs \ `rvformal_csr_pmpaddr47_channel_outputs \ `rvformal_csr_pmpaddr48_channel_outputs \ `rvformal_csr_pmpaddr49_channel_outputs \ `rvformal_csr_pmpaddr50_channel_outputs \ `rvformal_csr_pmpaddr51_channel_outputs \ `rvformal_csr_pmpaddr52_channel_outputs \ `rvformal_csr_pmpaddr53_channel_outputs \ `rvformal_csr_pmpaddr54_channel_outputs \ `rvformal_csr_pmpaddr55_channel_outputs \ `rvformal_csr_pmpaddr56_channel_outputs \ `rvformal_csr_pmpaddr57_channel_outputs \ `rvformal_csr_pmpaddr58_channel_outputs \ `rvformal_csr_pmpaddr59_channel_outputs \ `rvformal_csr_pmpaddr60_channel_outputs \ `rvformal_csr_pmpaddr61_channel_outputs \ `rvformal_csr_pmpaddr62_channel_outputs \ `rvformal_csr_pmpaddr63_channel_outputs \ `rvformal_csr_mhpmevent3_channel_outputs \ `rvformal_csr_mhpmevent4_channel_outputs \ `rvformal_csr_mhpmevent5_channel_outputs \ `rvformal_csr_mhpmevent6_channel_outputs \ `rvformal_csr_mhpmevent7_channel_outputs \ `rvformal_csr_mhpmevent8_channel_outputs \ `rvformal_csr_mhpmevent9_channel_outputs \ `rvformal_csr_mhpmevent10_channel_outputs \ `rvformal_csr_mhpmevent11_channel_outputs \ `rvformal_csr_mhpmevent12_channel_outputs \ `rvformal_csr_mhpmevent13_channel_outputs \ `rvformal_csr_mhpmevent14_channel_outputs \ `rvformal_csr_mhpmevent15_channel_outputs \ `rvformal_csr_mhpmevent16_channel_outputs \ `rvformal_csr_mhpmevent17_channel_outputs \ `rvformal_csr_mhpmevent18_channel_outputs \ `rvformal_csr_mhpmevent19_channel_outputs \ `rvformal_csr_mhpmevent20_channel_outputs \ `rvformal_csr_mhpmevent21_channel_outputs \ `rvformal_csr_mhpmevent22_channel_outputs \ `rvformal_csr_mhpmevent23_channel_outputs \ `rvformal_csr_mhpmevent24_channel_outputs \ `rvformal_csr_mhpmevent25_channel_outputs \ `rvformal_csr_mhpmevent26_channel_outputs \ `rvformal_csr_mhpmevent27_channel_outputs \ `rvformal_csr_mhpmevent28_channel_outputs \ `rvformal_csr_mhpmevent29_channel_outputs \ `rvformal_csr_mhpmevent30_channel_outputs \ `rvformal_csr_mhpmevent31_channel_outputs \ `rvformal_csr_mcycle_channel_outputs \ `rvformal_csr_time_channel_outputs \ `rvformal_csr_minstret_channel_outputs \ `rvformal_csr_mhpmcounter3_channel_outputs \ `rvformal_csr_mhpmcounter4_channel_outputs \ `rvformal_csr_mhpmcounter5_channel_outputs \ `rvformal_csr_mhpmcounter6_channel_outputs \ `rvformal_csr_mhpmcounter7_channel_outputs \ `rvformal_csr_mhpmcounter8_channel_outputs \ `rvformal_csr_mhpmcounter9_channel_outputs \ `rvformal_csr_mhpmcounter10_channel_outputs \ `rvformal_csr_mhpmcounter11_channel_outputs \ `rvformal_csr_mhpmcounter12_channel_outputs \ `rvformal_csr_mhpmcounter13_channel_outputs \ `rvformal_csr_mhpmcounter14_channel_outputs \ `rvformal_csr_mhpmcounter15_channel_outputs \ `rvformal_csr_mhpmcounter16_channel_outputs \ `rvformal_csr_mhpmcounter17_channel_outputs \ `rvformal_csr_mhpmcounter18_channel_outputs \ `rvformal_csr_mhpmcounter19_channel_outputs \ `rvformal_csr_mhpmcounter20_channel_outputs \ `rvformal_csr_mhpmcounter21_channel_outputs \ `rvformal_csr_mhpmcounter22_channel_outputs \ `rvformal_csr_mhpmcounter23_channel_outputs \ `rvformal_csr_mhpmcounter24_channel_outputs \ `rvformal_csr_mhpmcounter25_channel_outputs \ `rvformal_csr_mhpmcounter26_channel_outputs \ `rvformal_csr_mhpmcounter27_channel_outputs \ `rvformal_csr_mhpmcounter28_channel_outputs \ `rvformal_csr_mhpmcounter29_channel_outputs \ `rvformal_csr_mhpmcounter30_channel_outputs \ `rvformal_csr_mhpmcounter31_channel_outputs \ `rvformal_custom_csr_channel_outputs `define RVFI_INPUTS \ input [`RISCV_FORMAL_NRET - 1 : 0] rvfi_valid , \ input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_order , \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn , \ input [`RISCV_FORMAL_NRET - 1 : 0] rvfi_trap , \ input [`RISCV_FORMAL_NRET - 1 : 0] rvfi_halt , \ input [`RISCV_FORMAL_NRET - 1 : 0] rvfi_intr , \ input [`RISCV_FORMAL_NRET * 2 - 1 : 0] rvfi_mode , \ input [`RISCV_FORMAL_NRET * 2 - 1 : 0] rvfi_ixl , \ input [`RISCV_FORMAL_NRET * 5 - 1 : 0] rvfi_rs1_addr , \ input [`RISCV_FORMAL_NRET * 5 - 1 : 0] rvfi_rs2_addr , \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, \ input [`RISCV_FORMAL_NRET * 5 - 1 : 0] rvfi_rd_addr , \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_rd_wdata , \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata , \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_wdata , \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_addr , \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_rmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_wmask, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, \ input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_wdata \ `rvformal_extamo_inputs \ `rvformal_rollback_inputs \ `rvformal_mem_fault_inputs \ `rvformal_csr_fflags_inputs \ `rvformal_csr_frm_inputs \ `rvformal_csr_fcsr_inputs \ `rvformal_csr_mvendorid_inputs \ `rvformal_csr_marchid_inputs \ `rvformal_csr_mimpid_inputs \ `rvformal_csr_mhartid_inputs \ `rvformal_csr_mconfigptr_inputs \ `rvformal_csr_mstatus_inputs \ `rvformal_csr_mstatush_inputs \ `rvformal_csr_misa_inputs \ `rvformal_csr_medeleg_inputs \ `rvformal_csr_mideleg_inputs \ `rvformal_csr_mie_inputs \ `rvformal_csr_mtvec_inputs \ `rvformal_csr_mcounteren_inputs \ `rvformal_csr_mscratch_inputs \ `rvformal_csr_mepc_inputs \ `rvformal_csr_mcause_inputs \ `rvformal_csr_mtval_inputs \ `rvformal_csr_mip_inputs \ `rvformal_csr_mtinst_inputs \ `rvformal_csr_mtval2_inputs \ `rvformal_csr_mcountinhibit_inputs \ `rvformal_csr_menvcfg_inputs \ `rvformal_csr_menvcfgh_inputs \ `rvformal_csr_pmpcfg0_inputs \ `rvformal_csr_pmpcfg1_inputs \ `rvformal_csr_pmpcfg2_inputs \ `rvformal_csr_pmpcfg3_inputs \ `rvformal_csr_pmpcfg4_inputs \ `rvformal_csr_pmpcfg5_inputs \ `rvformal_csr_pmpcfg6_inputs \ `rvformal_csr_pmpcfg7_inputs \ `rvformal_csr_pmpcfg8_inputs \ `rvformal_csr_pmpcfg9_inputs \ `rvformal_csr_pmpcfg10_inputs \ `rvformal_csr_pmpcfg11_inputs \ `rvformal_csr_pmpcfg12_inputs \ `rvformal_csr_pmpcfg13_inputs \ `rvformal_csr_pmpcfg14_inputs \ `rvformal_csr_pmpcfg15_inputs \ `rvformal_csr_pmpaddr0_inputs \ `rvformal_csr_pmpaddr1_inputs \ `rvformal_csr_pmpaddr2_inputs \ `rvformal_csr_pmpaddr3_inputs \ `rvformal_csr_pmpaddr4_inputs \ `rvformal_csr_pmpaddr5_inputs \ `rvformal_csr_pmpaddr6_inputs \ `rvformal_csr_pmpaddr7_inputs \ `rvformal_csr_pmpaddr8_inputs \ `rvformal_csr_pmpaddr9_inputs \ `rvformal_csr_pmpaddr10_inputs \ `rvformal_csr_pmpaddr11_inputs \ `rvformal_csr_pmpaddr12_inputs \ `rvformal_csr_pmpaddr13_inputs \ `rvformal_csr_pmpaddr14_inputs \ `rvformal_csr_pmpaddr15_inputs \ `rvformal_csr_pmpaddr16_inputs \ `rvformal_csr_pmpaddr17_inputs \ `rvformal_csr_pmpaddr18_inputs \ `rvformal_csr_pmpaddr19_inputs \ `rvformal_csr_pmpaddr20_inputs \ `rvformal_csr_pmpaddr21_inputs \ `rvformal_csr_pmpaddr22_inputs \ `rvformal_csr_pmpaddr23_inputs \ `rvformal_csr_pmpaddr24_inputs \ `rvformal_csr_pmpaddr25_inputs \ `rvformal_csr_pmpaddr26_inputs \ `rvformal_csr_pmpaddr27_inputs \ `rvformal_csr_pmpaddr28_inputs \ `rvformal_csr_pmpaddr29_inputs \ `rvformal_csr_pmpaddr30_inputs \ `rvformal_csr_pmpaddr31_inputs \ `rvformal_csr_pmpaddr32_inputs \ `rvformal_csr_pmpaddr33_inputs \ `rvformal_csr_pmpaddr34_inputs \ `rvformal_csr_pmpaddr35_inputs \ `rvformal_csr_pmpaddr36_inputs \ `rvformal_csr_pmpaddr37_inputs \ `rvformal_csr_pmpaddr38_inputs \ `rvformal_csr_pmpaddr39_inputs \ `rvformal_csr_pmpaddr40_inputs \ `rvformal_csr_pmpaddr41_inputs \ `rvformal_csr_pmpaddr42_inputs \ `rvformal_csr_pmpaddr43_inputs \ `rvformal_csr_pmpaddr44_inputs \ `rvformal_csr_pmpaddr45_inputs \ `rvformal_csr_pmpaddr46_inputs \ `rvformal_csr_pmpaddr47_inputs \ `rvformal_csr_pmpaddr48_inputs \ `rvformal_csr_pmpaddr49_inputs \ `rvformal_csr_pmpaddr50_inputs \ `rvformal_csr_pmpaddr51_inputs \ `rvformal_csr_pmpaddr52_inputs \ `rvformal_csr_pmpaddr53_inputs \ `rvformal_csr_pmpaddr54_inputs \ `rvformal_csr_pmpaddr55_inputs \ `rvformal_csr_pmpaddr56_inputs \ `rvformal_csr_pmpaddr57_inputs \ `rvformal_csr_pmpaddr58_inputs \ `rvformal_csr_pmpaddr59_inputs \ `rvformal_csr_pmpaddr60_inputs \ `rvformal_csr_pmpaddr61_inputs \ `rvformal_csr_pmpaddr62_inputs \ `rvformal_csr_pmpaddr63_inputs \ `rvformal_csr_mhpmevent3_inputs \ `rvformal_csr_mhpmevent4_inputs \ `rvformal_csr_mhpmevent5_inputs \ `rvformal_csr_mhpmevent6_inputs \ `rvformal_csr_mhpmevent7_inputs \ `rvformal_csr_mhpmevent8_inputs \ `rvformal_csr_mhpmevent9_inputs \ `rvformal_csr_mhpmevent10_inputs \ `rvformal_csr_mhpmevent11_inputs \ `rvformal_csr_mhpmevent12_inputs \ `rvformal_csr_mhpmevent13_inputs \ `rvformal_csr_mhpmevent14_inputs \ `rvformal_csr_mhpmevent15_inputs \ `rvformal_csr_mhpmevent16_inputs \ `rvformal_csr_mhpmevent17_inputs \ `rvformal_csr_mhpmevent18_inputs \ `rvformal_csr_mhpmevent19_inputs \ `rvformal_csr_mhpmevent20_inputs \ `rvformal_csr_mhpmevent21_inputs \ `rvformal_csr_mhpmevent22_inputs \ `rvformal_csr_mhpmevent23_inputs \ `rvformal_csr_mhpmevent24_inputs \ `rvformal_csr_mhpmevent25_inputs \ `rvformal_csr_mhpmevent26_inputs \ `rvformal_csr_mhpmevent27_inputs \ `rvformal_csr_mhpmevent28_inputs \ `rvformal_csr_mhpmevent29_inputs \ `rvformal_csr_mhpmevent30_inputs \ `rvformal_csr_mhpmevent31_inputs \ `rvformal_csr_mcycle_inputs \ `rvformal_csr_time_inputs \ `rvformal_csr_minstret_inputs \ `rvformal_csr_mhpmcounter3_inputs \ `rvformal_csr_mhpmcounter4_inputs \ `rvformal_csr_mhpmcounter5_inputs \ `rvformal_csr_mhpmcounter6_inputs \ `rvformal_csr_mhpmcounter7_inputs \ `rvformal_csr_mhpmcounter8_inputs \ `rvformal_csr_mhpmcounter9_inputs \ `rvformal_csr_mhpmcounter10_inputs \ `rvformal_csr_mhpmcounter11_inputs \ `rvformal_csr_mhpmcounter12_inputs \ `rvformal_csr_mhpmcounter13_inputs \ `rvformal_csr_mhpmcounter14_inputs \ `rvformal_csr_mhpmcounter15_inputs \ `rvformal_csr_mhpmcounter16_inputs \ `rvformal_csr_mhpmcounter17_inputs \ `rvformal_csr_mhpmcounter18_inputs \ `rvformal_csr_mhpmcounter19_inputs \ `rvformal_csr_mhpmcounter20_inputs \ `rvformal_csr_mhpmcounter21_inputs \ `rvformal_csr_mhpmcounter22_inputs \ `rvformal_csr_mhpmcounter23_inputs \ `rvformal_csr_mhpmcounter24_inputs \ `rvformal_csr_mhpmcounter25_inputs \ `rvformal_csr_mhpmcounter26_inputs \ `rvformal_csr_mhpmcounter27_inputs \ `rvformal_csr_mhpmcounter28_inputs \ `rvformal_csr_mhpmcounter29_inputs \ `rvformal_csr_mhpmcounter30_inputs \ `rvformal_csr_mhpmcounter31_inputs \ `rvformal_custom_csr_inputs `define RVFI_CHANNEL_INPUTS \ input [ 0 : 0] rvfi_valid , \ input [ 64 - 1 : 0] rvfi_order , \ input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn , \ input [ 0 : 0] rvfi_trap , \ input [ 0 : 0] rvfi_halt , \ input [ 0 : 0] rvfi_intr , \ input [ 2 - 1 : 0] rvfi_mode , \ input [ 2 - 1 : 0] rvfi_ixl , \ input [ 5 - 1 : 0] rvfi_rs1_addr , \ input [ 5 - 1 : 0] rvfi_rs2_addr , \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, \ input [ 5 - 1 : 0] rvfi_rd_addr , \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rd_wdata , \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata , \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_wdata , \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_addr , \ input [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_rmask, \ input [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_wmask, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, \ input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_wdata \ `rvformal_extamo_channel_inputs \ `rvformal_rollback_channel_inputs \ `rvformal_mem_fault_channel_inputs \ `rvformal_csr_fflags_channel_inputs \ `rvformal_csr_frm_channel_inputs \ `rvformal_csr_fcsr_channel_inputs \ `rvformal_csr_mvendorid_channel_inputs \ `rvformal_csr_marchid_channel_inputs \ `rvformal_csr_mimpid_channel_inputs \ `rvformal_csr_mhartid_channel_inputs \ `rvformal_csr_mconfigptr_channel_inputs \ `rvformal_csr_mstatus_channel_inputs \ `rvformal_csr_mstatush_channel_inputs \ `rvformal_csr_misa_channel_inputs \ `rvformal_csr_medeleg_channel_inputs \ `rvformal_csr_mideleg_channel_inputs \ `rvformal_csr_mie_channel_inputs \ `rvformal_csr_mtvec_channel_inputs \ `rvformal_csr_mcounteren_channel_inputs \ `rvformal_csr_mscratch_channel_inputs \ `rvformal_csr_mepc_channel_inputs \ `rvformal_csr_mcause_channel_inputs \ `rvformal_csr_mtval_channel_inputs \ `rvformal_csr_mip_channel_inputs \ `rvformal_csr_mtinst_channel_inputs \ `rvformal_csr_mtval2_channel_inputs \ `rvformal_csr_mcountinhibit_channel_inputs \ `rvformal_csr_menvcfg_channel_inputs \ `rvformal_csr_menvcfgh_channel_inputs \ `rvformal_csr_pmpcfg0_channel_inputs \ `rvformal_csr_pmpcfg1_channel_inputs \ `rvformal_csr_pmpcfg2_channel_inputs \ `rvformal_csr_pmpcfg3_channel_inputs \ `rvformal_csr_pmpcfg4_channel_inputs \ `rvformal_csr_pmpcfg5_channel_inputs \ `rvformal_csr_pmpcfg6_channel_inputs \ `rvformal_csr_pmpcfg7_channel_inputs \ `rvformal_csr_pmpcfg8_channel_inputs \ `rvformal_csr_pmpcfg9_channel_inputs \ `rvformal_csr_pmpcfg10_channel_inputs \ `rvformal_csr_pmpcfg11_channel_inputs \ `rvformal_csr_pmpcfg12_channel_inputs \ `rvformal_csr_pmpcfg13_channel_inputs \ `rvformal_csr_pmpcfg14_channel_inputs \ `rvformal_csr_pmpcfg15_channel_inputs \ `rvformal_csr_pmpaddr0_channel_inputs \ `rvformal_csr_pmpaddr1_channel_inputs \ `rvformal_csr_pmpaddr2_channel_inputs \ `rvformal_csr_pmpaddr3_channel_inputs \ `rvformal_csr_pmpaddr4_channel_inputs \ `rvformal_csr_pmpaddr5_channel_inputs \ `rvformal_csr_pmpaddr6_channel_inputs \ `rvformal_csr_pmpaddr7_channel_inputs \ `rvformal_csr_pmpaddr8_channel_inputs \ `rvformal_csr_pmpaddr9_channel_inputs \ `rvformal_csr_pmpaddr10_channel_inputs \ `rvformal_csr_pmpaddr11_channel_inputs \ `rvformal_csr_pmpaddr12_channel_inputs \ `rvformal_csr_pmpaddr13_channel_inputs \ `rvformal_csr_pmpaddr14_channel_inputs \ `rvformal_csr_pmpaddr15_channel_inputs \ `rvformal_csr_pmpaddr16_channel_inputs \ `rvformal_csr_pmpaddr17_channel_inputs \ `rvformal_csr_pmpaddr18_channel_inputs \ `rvformal_csr_pmpaddr19_channel_inputs \ `rvformal_csr_pmpaddr20_channel_inputs \ `rvformal_csr_pmpaddr21_channel_inputs \ `rvformal_csr_pmpaddr22_channel_inputs \ `rvformal_csr_pmpaddr23_channel_inputs \ `rvformal_csr_pmpaddr24_channel_inputs \ `rvformal_csr_pmpaddr25_channel_inputs \ `rvformal_csr_pmpaddr26_channel_inputs \ `rvformal_csr_pmpaddr27_channel_inputs \ `rvformal_csr_pmpaddr28_channel_inputs \ `rvformal_csr_pmpaddr29_channel_inputs \ `rvformal_csr_pmpaddr30_channel_inputs \ `rvformal_csr_pmpaddr31_channel_inputs \ `rvformal_csr_pmpaddr32_channel_inputs \ `rvformal_csr_pmpaddr33_channel_inputs \ `rvformal_csr_pmpaddr34_channel_inputs \ `rvformal_csr_pmpaddr35_channel_inputs \ `rvformal_csr_pmpaddr36_channel_inputs \ `rvformal_csr_pmpaddr37_channel_inputs \ `rvformal_csr_pmpaddr38_channel_inputs \ `rvformal_csr_pmpaddr39_channel_inputs \ `rvformal_csr_pmpaddr40_channel_inputs \ `rvformal_csr_pmpaddr41_channel_inputs \ `rvformal_csr_pmpaddr42_channel_inputs \ `rvformal_csr_pmpaddr43_channel_inputs \ `rvformal_csr_pmpaddr44_channel_inputs \ `rvformal_csr_pmpaddr45_channel_inputs \ `rvformal_csr_pmpaddr46_channel_inputs \ `rvformal_csr_pmpaddr47_channel_inputs \ `rvformal_csr_pmpaddr48_channel_inputs \ `rvformal_csr_pmpaddr49_channel_inputs \ `rvformal_csr_pmpaddr50_channel_inputs \ `rvformal_csr_pmpaddr51_channel_inputs \ `rvformal_csr_pmpaddr52_channel_inputs \ `rvformal_csr_pmpaddr53_channel_inputs \ `rvformal_csr_pmpaddr54_channel_inputs \ `rvformal_csr_pmpaddr55_channel_inputs \ `rvformal_csr_pmpaddr56_channel_inputs \ `rvformal_csr_pmpaddr57_channel_inputs \ `rvformal_csr_pmpaddr58_channel_inputs \ `rvformal_csr_pmpaddr59_channel_inputs \ `rvformal_csr_pmpaddr60_channel_inputs \ `rvformal_csr_pmpaddr61_channel_inputs \ `rvformal_csr_pmpaddr62_channel_inputs \ `rvformal_csr_pmpaddr63_channel_inputs \ `rvformal_csr_mhpmevent3_channel_inputs \ `rvformal_csr_mhpmevent4_channel_inputs \ `rvformal_csr_mhpmevent5_channel_inputs \ `rvformal_csr_mhpmevent6_channel_inputs \ `rvformal_csr_mhpmevent7_channel_inputs \ `rvformal_csr_mhpmevent8_channel_inputs \ `rvformal_csr_mhpmevent9_channel_inputs \ `rvformal_csr_mhpmevent10_channel_inputs \ `rvformal_csr_mhpmevent11_channel_inputs \ `rvformal_csr_mhpmevent12_channel_inputs \ `rvformal_csr_mhpmevent13_channel_inputs \ `rvformal_csr_mhpmevent14_channel_inputs \ `rvformal_csr_mhpmevent15_channel_inputs \ `rvformal_csr_mhpmevent16_channel_inputs \ `rvformal_csr_mhpmevent17_channel_inputs \ `rvformal_csr_mhpmevent18_channel_inputs \ `rvformal_csr_mhpmevent19_channel_inputs \ `rvformal_csr_mhpmevent20_channel_inputs \ `rvformal_csr_mhpmevent21_channel_inputs \ `rvformal_csr_mhpmevent22_channel_inputs \ `rvformal_csr_mhpmevent23_channel_inputs \ `rvformal_csr_mhpmevent24_channel_inputs \ `rvformal_csr_mhpmevent25_channel_inputs \ `rvformal_csr_mhpmevent26_channel_inputs \ `rvformal_csr_mhpmevent27_channel_inputs \ `rvformal_csr_mhpmevent28_channel_inputs \ `rvformal_csr_mhpmevent29_channel_inputs \ `rvformal_csr_mhpmevent30_channel_inputs \ `rvformal_csr_mhpmevent31_channel_inputs \ `rvformal_csr_mcycle_channel_inputs \ `rvformal_csr_time_channel_inputs \ `rvformal_csr_minstret_channel_inputs \ `rvformal_csr_mhpmcounter3_channel_inputs \ `rvformal_csr_mhpmcounter4_channel_inputs \ `rvformal_csr_mhpmcounter5_channel_inputs \ `rvformal_csr_mhpmcounter6_channel_inputs \ `rvformal_csr_mhpmcounter7_channel_inputs \ `rvformal_csr_mhpmcounter8_channel_inputs \ `rvformal_csr_mhpmcounter9_channel_inputs \ `rvformal_csr_mhpmcounter10_channel_inputs \ `rvformal_csr_mhpmcounter11_channel_inputs \ `rvformal_csr_mhpmcounter12_channel_inputs \ `rvformal_csr_mhpmcounter13_channel_inputs \ `rvformal_csr_mhpmcounter14_channel_inputs \ `rvformal_csr_mhpmcounter15_channel_inputs \ `rvformal_csr_mhpmcounter16_channel_inputs \ `rvformal_csr_mhpmcounter17_channel_inputs \ `rvformal_csr_mhpmcounter18_channel_inputs \ `rvformal_csr_mhpmcounter19_channel_inputs \ `rvformal_csr_mhpmcounter20_channel_inputs \ `rvformal_csr_mhpmcounter21_channel_inputs \ `rvformal_csr_mhpmcounter22_channel_inputs \ `rvformal_csr_mhpmcounter23_channel_inputs \ `rvformal_csr_mhpmcounter24_channel_inputs \ `rvformal_csr_mhpmcounter25_channel_inputs \ `rvformal_csr_mhpmcounter26_channel_inputs \ `rvformal_csr_mhpmcounter27_channel_inputs \ `rvformal_csr_mhpmcounter28_channel_inputs \ `rvformal_csr_mhpmcounter29_channel_inputs \ `rvformal_csr_mhpmcounter30_channel_inputs \ `rvformal_csr_mhpmcounter31_channel_inputs \ `rvformal_custom_csr_channel_inputs `define RVFI_CONN \ .rvfi_valid (rvfi_valid ), \ .rvfi_order (rvfi_order ), \ .rvfi_insn (rvfi_insn ), \ .rvfi_trap (rvfi_trap ), \ .rvfi_halt (rvfi_halt ), \ .rvfi_intr (rvfi_intr ), \ .rvfi_mode (rvfi_mode ), \ .rvfi_ixl (rvfi_ixl ), \ .rvfi_rs1_addr (rvfi_rs1_addr ), \ .rvfi_rs2_addr (rvfi_rs2_addr ), \ .rvfi_rs1_rdata (rvfi_rs1_rdata), \ .rvfi_rs2_rdata (rvfi_rs2_rdata), \ .rvfi_rd_addr (rvfi_rd_addr ), \ .rvfi_rd_wdata (rvfi_rd_wdata ), \ .rvfi_pc_rdata (rvfi_pc_rdata ), \ .rvfi_pc_wdata (rvfi_pc_wdata ), \ .rvfi_mem_addr (rvfi_mem_addr ), \ .rvfi_mem_rmask (rvfi_mem_rmask), \ .rvfi_mem_wmask (rvfi_mem_wmask), \ .rvfi_mem_rdata (rvfi_mem_rdata), \ .rvfi_mem_wdata (rvfi_mem_wdata) \ `rvformal_extamo_conn \ `rvformal_rollback_conn \ `rvformal_mem_fault_conn \ `rvformal_csr_fflags_conn \ `rvformal_csr_frm_conn \ `rvformal_csr_fcsr_conn \ `rvformal_csr_mvendorid_conn \ `rvformal_csr_marchid_conn \ `rvformal_csr_mimpid_conn \ `rvformal_csr_mhartid_conn \ `rvformal_csr_mconfigptr_conn \ `rvformal_csr_mstatus_conn \ `rvformal_csr_mstatush_conn \ `rvformal_csr_misa_conn \ `rvformal_csr_medeleg_conn \ `rvformal_csr_mideleg_conn \ `rvformal_csr_mie_conn \ `rvformal_csr_mtvec_conn \ `rvformal_csr_mcounteren_conn \ `rvformal_csr_mscratch_conn \ `rvformal_csr_mepc_conn \ `rvformal_csr_mcause_conn \ `rvformal_csr_mtval_conn \ `rvformal_csr_mip_conn \ `rvformal_csr_mtinst_conn \ `rvformal_csr_mtval2_conn \ `rvformal_csr_mcountinhibit_conn \ `rvformal_csr_menvcfg_conn \ `rvformal_csr_menvcfgh_conn \ `rvformal_csr_pmpcfg0_conn \ `rvformal_csr_pmpcfg1_conn \ `rvformal_csr_pmpcfg2_conn \ `rvformal_csr_pmpcfg3_conn \ `rvformal_csr_pmpcfg4_conn \ `rvformal_csr_pmpcfg5_conn \ `rvformal_csr_pmpcfg6_conn \ `rvformal_csr_pmpcfg7_conn \ `rvformal_csr_pmpcfg8_conn \ `rvformal_csr_pmpcfg9_conn \ `rvformal_csr_pmpcfg10_conn \ `rvformal_csr_pmpcfg11_conn \ `rvformal_csr_pmpcfg12_conn \ `rvformal_csr_pmpcfg13_conn \ `rvformal_csr_pmpcfg14_conn \ `rvformal_csr_pmpcfg15_conn \ `rvformal_csr_pmpaddr0_conn \ `rvformal_csr_pmpaddr1_conn \ `rvformal_csr_pmpaddr2_conn \ `rvformal_csr_pmpaddr3_conn \ `rvformal_csr_pmpaddr4_conn \ `rvformal_csr_pmpaddr5_conn \ `rvformal_csr_pmpaddr6_conn \ `rvformal_csr_pmpaddr7_conn \ `rvformal_csr_pmpaddr8_conn \ `rvformal_csr_pmpaddr9_conn \ `rvformal_csr_pmpaddr10_conn \ `rvformal_csr_pmpaddr11_conn \ `rvformal_csr_pmpaddr12_conn \ `rvformal_csr_pmpaddr13_conn \ `rvformal_csr_pmpaddr14_conn \ `rvformal_csr_pmpaddr15_conn \ `rvformal_csr_pmpaddr16_conn \ `rvformal_csr_pmpaddr17_conn \ `rvformal_csr_pmpaddr18_conn \ `rvformal_csr_pmpaddr19_conn \ `rvformal_csr_pmpaddr20_conn \ `rvformal_csr_pmpaddr21_conn \ `rvformal_csr_pmpaddr22_conn \ `rvformal_csr_pmpaddr23_conn \ `rvformal_csr_pmpaddr24_conn \ `rvformal_csr_pmpaddr25_conn \ `rvformal_csr_pmpaddr26_conn \ `rvformal_csr_pmpaddr27_conn \ `rvformal_csr_pmpaddr28_conn \ `rvformal_csr_pmpaddr29_conn \ `rvformal_csr_pmpaddr30_conn \ `rvformal_csr_pmpaddr31_conn \ `rvformal_csr_pmpaddr32_conn \ `rvformal_csr_pmpaddr33_conn \ `rvformal_csr_pmpaddr34_conn \ `rvformal_csr_pmpaddr35_conn \ `rvformal_csr_pmpaddr36_conn \ `rvformal_csr_pmpaddr37_conn \ `rvformal_csr_pmpaddr38_conn \ `rvformal_csr_pmpaddr39_conn \ `rvformal_csr_pmpaddr40_conn \ `rvformal_csr_pmpaddr41_conn \ `rvformal_csr_pmpaddr42_conn \ `rvformal_csr_pmpaddr43_conn \ `rvformal_csr_pmpaddr44_conn \ `rvformal_csr_pmpaddr45_conn \ `rvformal_csr_pmpaddr46_conn \ `rvformal_csr_pmpaddr47_conn \ `rvformal_csr_pmpaddr48_conn \ `rvformal_csr_pmpaddr49_conn \ `rvformal_csr_pmpaddr50_conn \ `rvformal_csr_pmpaddr51_conn \ `rvformal_csr_pmpaddr52_conn \ `rvformal_csr_pmpaddr53_conn \ `rvformal_csr_pmpaddr54_conn \ `rvformal_csr_pmpaddr55_conn \ `rvformal_csr_pmpaddr56_conn \ `rvformal_csr_pmpaddr57_conn \ `rvformal_csr_pmpaddr58_conn \ `rvformal_csr_pmpaddr59_conn \ `rvformal_csr_pmpaddr60_conn \ `rvformal_csr_pmpaddr61_conn \ `rvformal_csr_pmpaddr62_conn \ `rvformal_csr_pmpaddr63_conn \ `rvformal_csr_mhpmevent3_conn \ `rvformal_csr_mhpmevent4_conn \ `rvformal_csr_mhpmevent5_conn \ `rvformal_csr_mhpmevent6_conn \ `rvformal_csr_mhpmevent7_conn \ `rvformal_csr_mhpmevent8_conn \ `rvformal_csr_mhpmevent9_conn \ `rvformal_csr_mhpmevent10_conn \ `rvformal_csr_mhpmevent11_conn \ `rvformal_csr_mhpmevent12_conn \ `rvformal_csr_mhpmevent13_conn \ `rvformal_csr_mhpmevent14_conn \ `rvformal_csr_mhpmevent15_conn \ `rvformal_csr_mhpmevent16_conn \ `rvformal_csr_mhpmevent17_conn \ `rvformal_csr_mhpmevent18_conn \ `rvformal_csr_mhpmevent19_conn \ `rvformal_csr_mhpmevent20_conn \ `rvformal_csr_mhpmevent21_conn \ `rvformal_csr_mhpmevent22_conn \ `rvformal_csr_mhpmevent23_conn \ `rvformal_csr_mhpmevent24_conn \ `rvformal_csr_mhpmevent25_conn \ `rvformal_csr_mhpmevent26_conn \ `rvformal_csr_mhpmevent27_conn \ `rvformal_csr_mhpmevent28_conn \ `rvformal_csr_mhpmevent29_conn \ `rvformal_csr_mhpmevent30_conn \ `rvformal_csr_mhpmevent31_conn \ `rvformal_csr_mcycle_conn \ `rvformal_csr_time_conn \ `rvformal_csr_minstret_conn \ `rvformal_csr_mhpmcounter3_conn \ `rvformal_csr_mhpmcounter4_conn \ `rvformal_csr_mhpmcounter5_conn \ `rvformal_csr_mhpmcounter6_conn \ `rvformal_csr_mhpmcounter7_conn \ `rvformal_csr_mhpmcounter8_conn \ `rvformal_csr_mhpmcounter9_conn \ `rvformal_csr_mhpmcounter10_conn \ `rvformal_csr_mhpmcounter11_conn \ `rvformal_csr_mhpmcounter12_conn \ `rvformal_csr_mhpmcounter13_conn \ `rvformal_csr_mhpmcounter14_conn \ `rvformal_csr_mhpmcounter15_conn \ `rvformal_csr_mhpmcounter16_conn \ `rvformal_csr_mhpmcounter17_conn \ `rvformal_csr_mhpmcounter18_conn \ `rvformal_csr_mhpmcounter19_conn \ `rvformal_csr_mhpmcounter20_conn \ `rvformal_csr_mhpmcounter21_conn \ `rvformal_csr_mhpmcounter22_conn \ `rvformal_csr_mhpmcounter23_conn \ `rvformal_csr_mhpmcounter24_conn \ `rvformal_csr_mhpmcounter25_conn \ `rvformal_csr_mhpmcounter26_conn \ `rvformal_csr_mhpmcounter27_conn \ `rvformal_csr_mhpmcounter28_conn \ `rvformal_csr_mhpmcounter29_conn \ `rvformal_csr_mhpmcounter30_conn \ `rvformal_csr_mhpmcounter31_conn \ `rvformal_custom_csr_conn `define RVFI_CHANNEL_CONN(_idx) \ .rvfi_valid (rvfi_valid [ _idx +: 1 ]), \ .rvfi_order (rvfi_order [(_idx)*( 64 ) +: 64 ]), \ .rvfi_insn (rvfi_insn [(_idx)*(`RISCV_FORMAL_ILEN ) +: `RISCV_FORMAL_ILEN ]), \ .rvfi_trap (rvfi_trap [ _idx +: 1 ]), \ .rvfi_halt (rvfi_halt [ _idx +: 1 ]), \ .rvfi_intr (rvfi_intr [ _idx +: 1 ]), \ .rvfi_mode (rvfi_mode [(_idx)*( 2 ) +: 2 ]), \ .rvfi_ixl (rvfi_ixl [(_idx)*( 2 ) +: 2 ]), \ .rvfi_rs1_addr (rvfi_rs1_addr [(_idx)*( 5 ) +: 5 ]), \ .rvfi_rs2_addr (rvfi_rs2_addr [(_idx)*( 5 ) +: 5 ]), \ .rvfi_rs1_rdata (rvfi_rs1_rdata [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]), \ .rvfi_rs2_rdata (rvfi_rs2_rdata [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]), \ .rvfi_rd_addr (rvfi_rd_addr [(_idx)*( 5 ) +: 5 ]), \ .rvfi_rd_wdata (rvfi_rd_wdata [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]), \ .rvfi_pc_rdata (rvfi_pc_rdata [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]), \ .rvfi_pc_wdata (rvfi_pc_wdata [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]), \ .rvfi_mem_addr (rvfi_mem_addr [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]), \ .rvfi_mem_rmask (rvfi_mem_rmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8]), \ .rvfi_mem_wmask (rvfi_mem_wmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8]), \ .rvfi_mem_rdata (rvfi_mem_rdata [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]), \ .rvfi_mem_wdata (rvfi_mem_wdata [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]) \ `rvformal_extamo_channel_conn(_idx) \ `rvformal_rollback_channel_conn(_idx) \ `rvformal_mem_fault_channel_conn(_idx) \ `rvformal_csr_fflags_channel_conn(_idx) \ `rvformal_csr_frm_channel_conn(_idx) \ `rvformal_csr_fcsr_channel_conn(_idx) \ `rvformal_csr_mvendorid_channel_conn(_idx) \ `rvformal_csr_marchid_channel_conn(_idx) \ `rvformal_csr_mimpid_channel_conn(_idx) \ `rvformal_csr_mhartid_channel_conn(_idx) \ `rvformal_csr_mconfigptr_channel_conn(_idx) \ `rvformal_csr_mstatus_channel_conn(_idx) \ `rvformal_csr_mstatush_channel_conn(_idx) \ `rvformal_csr_misa_channel_conn(_idx) \ `rvformal_csr_medeleg_channel_conn(_idx) \ `rvformal_csr_mideleg_channel_conn(_idx) \ `rvformal_csr_mie_channel_conn(_idx) \ `rvformal_csr_mtvec_channel_conn(_idx) \ `rvformal_csr_mcounteren_channel_conn(_idx) \ `rvformal_csr_mscratch_channel_conn(_idx) \ `rvformal_csr_mepc_channel_conn(_idx) \ `rvformal_csr_mcause_channel_conn(_idx) \ `rvformal_csr_mtval_channel_conn(_idx) \ `rvformal_csr_mip_channel_conn(_idx) \ `rvformal_csr_mtinst_channel_conn(_idx) \ `rvformal_csr_mtval2_channel_conn(_idx) \ `rvformal_csr_mcountinhibit_channel_conn(_idx) \ `rvformal_csr_menvcfg_channel_conn(_idx) \ `rvformal_csr_menvcfgh_channel_conn(_idx) \ `rvformal_csr_pmpcfg0_channel_conn(_idx) \ `rvformal_csr_pmpcfg1_channel_conn(_idx) \ `rvformal_csr_pmpcfg2_channel_conn(_idx) \ `rvformal_csr_pmpcfg3_channel_conn(_idx) \ `rvformal_csr_pmpcfg4_channel_conn(_idx) \ `rvformal_csr_pmpcfg5_channel_conn(_idx) \ `rvformal_csr_pmpcfg6_channel_conn(_idx) \ `rvformal_csr_pmpcfg7_channel_conn(_idx) \ `rvformal_csr_pmpcfg8_channel_conn(_idx) \ `rvformal_csr_pmpcfg9_channel_conn(_idx) \ `rvformal_csr_pmpcfg10_channel_conn(_idx) \ `rvformal_csr_pmpcfg11_channel_conn(_idx) \ `rvformal_csr_pmpcfg12_channel_conn(_idx) \ `rvformal_csr_pmpcfg13_channel_conn(_idx) \ `rvformal_csr_pmpcfg14_channel_conn(_idx) \ `rvformal_csr_pmpcfg15_channel_conn(_idx) \ `rvformal_csr_pmpaddr0_channel_conn(_idx) \ `rvformal_csr_pmpaddr1_channel_conn(_idx) \ `rvformal_csr_pmpaddr2_channel_conn(_idx) \ `rvformal_csr_pmpaddr3_channel_conn(_idx) \ `rvformal_csr_pmpaddr4_channel_conn(_idx) \ `rvformal_csr_pmpaddr5_channel_conn(_idx) \ `rvformal_csr_pmpaddr6_channel_conn(_idx) \ `rvformal_csr_pmpaddr7_channel_conn(_idx) \ `rvformal_csr_pmpaddr8_channel_conn(_idx) \ `rvformal_csr_pmpaddr9_channel_conn(_idx) \ `rvformal_csr_pmpaddr10_channel_conn(_idx) \ `rvformal_csr_pmpaddr11_channel_conn(_idx) \ `rvformal_csr_pmpaddr12_channel_conn(_idx) \ `rvformal_csr_pmpaddr13_channel_conn(_idx) \ `rvformal_csr_pmpaddr14_channel_conn(_idx) \ `rvformal_csr_pmpaddr15_channel_conn(_idx) \ `rvformal_csr_pmpaddr16_channel_conn(_idx) \ `rvformal_csr_pmpaddr17_channel_conn(_idx) \ `rvformal_csr_pmpaddr18_channel_conn(_idx) \ `rvformal_csr_pmpaddr19_channel_conn(_idx) \ `rvformal_csr_pmpaddr20_channel_conn(_idx) \ `rvformal_csr_pmpaddr21_channel_conn(_idx) \ `rvformal_csr_pmpaddr22_channel_conn(_idx) \ `rvformal_csr_pmpaddr23_channel_conn(_idx) \ `rvformal_csr_pmpaddr24_channel_conn(_idx) \ `rvformal_csr_pmpaddr25_channel_conn(_idx) \ `rvformal_csr_pmpaddr26_channel_conn(_idx) \ `rvformal_csr_pmpaddr27_channel_conn(_idx) \ `rvformal_csr_pmpaddr28_channel_conn(_idx) \ `rvformal_csr_pmpaddr29_channel_conn(_idx) \ `rvformal_csr_pmpaddr30_channel_conn(_idx) \ `rvformal_csr_pmpaddr31_channel_conn(_idx) \ `rvformal_csr_pmpaddr32_channel_conn(_idx) \ `rvformal_csr_pmpaddr33_channel_conn(_idx) \ `rvformal_csr_pmpaddr34_channel_conn(_idx) \ `rvformal_csr_pmpaddr35_channel_conn(_idx) \ `rvformal_csr_pmpaddr36_channel_conn(_idx) \ `rvformal_csr_pmpaddr37_channel_conn(_idx) \ `rvformal_csr_pmpaddr38_channel_conn(_idx) \ `rvformal_csr_pmpaddr39_channel_conn(_idx) \ `rvformal_csr_pmpaddr40_channel_conn(_idx) \ `rvformal_csr_pmpaddr41_channel_conn(_idx) \ `rvformal_csr_pmpaddr42_channel_conn(_idx) \ `rvformal_csr_pmpaddr43_channel_conn(_idx) \ `rvformal_csr_pmpaddr44_channel_conn(_idx) \ `rvformal_csr_pmpaddr45_channel_conn(_idx) \ `rvformal_csr_pmpaddr46_channel_conn(_idx) \ `rvformal_csr_pmpaddr47_channel_conn(_idx) \ `rvformal_csr_pmpaddr48_channel_conn(_idx) \ `rvformal_csr_pmpaddr49_channel_conn(_idx) \ `rvformal_csr_pmpaddr50_channel_conn(_idx) \ `rvformal_csr_pmpaddr51_channel_conn(_idx) \ `rvformal_csr_pmpaddr52_channel_conn(_idx) \ `rvformal_csr_pmpaddr53_channel_conn(_idx) \ `rvformal_csr_pmpaddr54_channel_conn(_idx) \ `rvformal_csr_pmpaddr55_channel_conn(_idx) \ `rvformal_csr_pmpaddr56_channel_conn(_idx) \ `rvformal_csr_pmpaddr57_channel_conn(_idx) \ `rvformal_csr_pmpaddr58_channel_conn(_idx) \ `rvformal_csr_pmpaddr59_channel_conn(_idx) \ `rvformal_csr_pmpaddr60_channel_conn(_idx) \ `rvformal_csr_pmpaddr61_channel_conn(_idx) \ `rvformal_csr_pmpaddr62_channel_conn(_idx) \ `rvformal_csr_pmpaddr63_channel_conn(_idx) \ `rvformal_csr_mhpmevent3_channel_conn(_idx) \ `rvformal_csr_mhpmevent4_channel_conn(_idx) \ `rvformal_csr_mhpmevent5_channel_conn(_idx) \ `rvformal_csr_mhpmevent6_channel_conn(_idx) \ `rvformal_csr_mhpmevent7_channel_conn(_idx) \ `rvformal_csr_mhpmevent8_channel_conn(_idx) \ `rvformal_csr_mhpmevent9_channel_conn(_idx) \ `rvformal_csr_mhpmevent10_channel_conn(_idx) \ `rvformal_csr_mhpmevent11_channel_conn(_idx) \ `rvformal_csr_mhpmevent12_channel_conn(_idx) \ `rvformal_csr_mhpmevent13_channel_conn(_idx) \ `rvformal_csr_mhpmevent14_channel_conn(_idx) \ `rvformal_csr_mhpmevent15_channel_conn(_idx) \ `rvformal_csr_mhpmevent16_channel_conn(_idx) \ `rvformal_csr_mhpmevent17_channel_conn(_idx) \ `rvformal_csr_mhpmevent18_channel_conn(_idx) \ `rvformal_csr_mhpmevent19_channel_conn(_idx) \ `rvformal_csr_mhpmevent20_channel_conn(_idx) \ `rvformal_csr_mhpmevent21_channel_conn(_idx) \ `rvformal_csr_mhpmevent22_channel_conn(_idx) \ `rvformal_csr_mhpmevent23_channel_conn(_idx) \ `rvformal_csr_mhpmevent24_channel_conn(_idx) \ `rvformal_csr_mhpmevent25_channel_conn(_idx) \ `rvformal_csr_mhpmevent26_channel_conn(_idx) \ `rvformal_csr_mhpmevent27_channel_conn(_idx) \ `rvformal_csr_mhpmevent28_channel_conn(_idx) \ `rvformal_csr_mhpmevent29_channel_conn(_idx) \ `rvformal_csr_mhpmevent30_channel_conn(_idx) \ `rvformal_csr_mhpmevent31_channel_conn(_idx) \ `rvformal_csr_mcycle_channel_conn(_idx) \ `rvformal_csr_time_channel_conn(_idx) \ `rvformal_csr_minstret_channel_conn(_idx) \ `rvformal_csr_mhpmcounter3_channel_conn(_idx) \ `rvformal_csr_mhpmcounter4_channel_conn(_idx) \ `rvformal_csr_mhpmcounter5_channel_conn(_idx) \ `rvformal_csr_mhpmcounter6_channel_conn(_idx) \ `rvformal_csr_mhpmcounter7_channel_conn(_idx) \ `rvformal_csr_mhpmcounter8_channel_conn(_idx) \ `rvformal_csr_mhpmcounter9_channel_conn(_idx) \ `rvformal_csr_mhpmcounter10_channel_conn(_idx) \ `rvformal_csr_mhpmcounter11_channel_conn(_idx) \ `rvformal_csr_mhpmcounter12_channel_conn(_idx) \ `rvformal_csr_mhpmcounter13_channel_conn(_idx) \ `rvformal_csr_mhpmcounter14_channel_conn(_idx) \ `rvformal_csr_mhpmcounter15_channel_conn(_idx) \ `rvformal_csr_mhpmcounter16_channel_conn(_idx) \ `rvformal_csr_mhpmcounter17_channel_conn(_idx) \ `rvformal_csr_mhpmcounter18_channel_conn(_idx) \ `rvformal_csr_mhpmcounter19_channel_conn(_idx) \ `rvformal_csr_mhpmcounter20_channel_conn(_idx) \ `rvformal_csr_mhpmcounter21_channel_conn(_idx) \ `rvformal_csr_mhpmcounter22_channel_conn(_idx) \ `rvformal_csr_mhpmcounter23_channel_conn(_idx) \ `rvformal_csr_mhpmcounter24_channel_conn(_idx) \ `rvformal_csr_mhpmcounter25_channel_conn(_idx) \ `rvformal_csr_mhpmcounter26_channel_conn(_idx) \ `rvformal_csr_mhpmcounter27_channel_conn(_idx) \ `rvformal_csr_mhpmcounter28_channel_conn(_idx) \ `rvformal_csr_mhpmcounter29_channel_conn(_idx) \ `rvformal_csr_mhpmcounter30_channel_conn(_idx) \ `rvformal_csr_mhpmcounter31_channel_conn(_idx) \ `rvformal_custom_csr_channel_conn(_idx) `define RVFI_CONN32 \ .rvfi_valid (rvfi_valid ), \ .rvfi_order (rvfi_order ), \ .rvfi_insn (rvfi_insn ), \ .rvfi_trap (rvfi_trap ), \ .rvfi_halt (rvfi_halt ), \ .rvfi_intr (rvfi_intr ), \ .rvfi_mode (rvfi_mode ), \ .rvfi_ixl (rvfi_ixl ), \ .rvfi_rs1_addr (rvfi_rs1_addr ), \ .rvfi_rs2_addr (rvfi_rs2_addr ), \ .rvfi_rs1_rdata (rvfi_rs1_rdata), \ .rvfi_rs2_rdata (rvfi_rs2_rdata), \ .rvfi_rd_addr (rvfi_rd_addr ), \ .rvfi_rd_wdata (rvfi_rd_wdata ), \ .rvfi_pc_rdata (rvfi_pc_rdata ), \ .rvfi_pc_wdata (rvfi_pc_wdata ), \ .rvfi_mem_addr (rvfi_mem_addr ), \ .rvfi_mem_rmask (rvfi_mem_rmask), \ .rvfi_mem_wmask (rvfi_mem_wmask), \ .rvfi_mem_rdata (rvfi_mem_rdata), \ .rvfi_mem_wdata (rvfi_mem_wdata) \ `rvformal_extamo_conn \ `rvformal_rollback_conn \ `rvformal_mem_fault_conn \ `rvformal_csr_fflags_conn \ `rvformal_csr_frm_conn \ `rvformal_csr_fcsr_conn \ `rvformal_csr_mvendorid_conn \ `rvformal_csr_marchid_conn \ `rvformal_csr_mimpid_conn \ `rvformal_csr_mhartid_conn \ `rvformal_csr_mconfigptr_conn \ `rvformal_csr_mstatus_conn \ `rvformal_csr_mstatush_conn \ `rvformal_csr_misa_conn \ `rvformal_csr_medeleg_conn \ `rvformal_csr_mideleg_conn \ `rvformal_csr_mie_conn \ `rvformal_csr_mtvec_conn \ `rvformal_csr_mcounteren_conn \ `rvformal_csr_mscratch_conn \ `rvformal_csr_mepc_conn \ `rvformal_csr_mcause_conn \ `rvformal_csr_mtval_conn \ `rvformal_csr_mip_conn \ `rvformal_csr_mtinst_conn \ `rvformal_csr_mtval2_conn \ `rvformal_csr_mcountinhibit_conn \ `rvformal_csr_menvcfg_conn \ `rvformal_csr_menvcfgh_conn \ `rvformal_csr_pmpcfg0_conn \ `rvformal_csr_pmpcfg1_conn \ `rvformal_csr_pmpcfg2_conn \ `rvformal_csr_pmpcfg3_conn \ `rvformal_csr_pmpcfg4_conn \ `rvformal_csr_pmpcfg5_conn \ `rvformal_csr_pmpcfg6_conn \ `rvformal_csr_pmpcfg7_conn \ `rvformal_csr_pmpcfg8_conn \ `rvformal_csr_pmpcfg9_conn \ `rvformal_csr_pmpcfg10_conn \ `rvformal_csr_pmpcfg11_conn \ `rvformal_csr_pmpcfg12_conn \ `rvformal_csr_pmpcfg13_conn \ `rvformal_csr_pmpcfg14_conn \ `rvformal_csr_pmpcfg15_conn \ `rvformal_csr_pmpaddr0_conn \ `rvformal_csr_pmpaddr1_conn \ `rvformal_csr_pmpaddr2_conn \ `rvformal_csr_pmpaddr3_conn \ `rvformal_csr_pmpaddr4_conn \ `rvformal_csr_pmpaddr5_conn \ `rvformal_csr_pmpaddr6_conn \ `rvformal_csr_pmpaddr7_conn \ `rvformal_csr_pmpaddr8_conn \ `rvformal_csr_pmpaddr9_conn \ `rvformal_csr_pmpaddr10_conn \ `rvformal_csr_pmpaddr11_conn \ `rvformal_csr_pmpaddr12_conn \ `rvformal_csr_pmpaddr13_conn \ `rvformal_csr_pmpaddr14_conn \ `rvformal_csr_pmpaddr15_conn \ `rvformal_csr_pmpaddr16_conn \ `rvformal_csr_pmpaddr17_conn \ `rvformal_csr_pmpaddr18_conn \ `rvformal_csr_pmpaddr19_conn \ `rvformal_csr_pmpaddr20_conn \ `rvformal_csr_pmpaddr21_conn \ `rvformal_csr_pmpaddr22_conn \ `rvformal_csr_pmpaddr23_conn \ `rvformal_csr_pmpaddr24_conn \ `rvformal_csr_pmpaddr25_conn \ `rvformal_csr_pmpaddr26_conn \ `rvformal_csr_pmpaddr27_conn \ `rvformal_csr_pmpaddr28_conn \ `rvformal_csr_pmpaddr29_conn \ `rvformal_csr_pmpaddr30_conn \ `rvformal_csr_pmpaddr31_conn \ `rvformal_csr_pmpaddr32_conn \ `rvformal_csr_pmpaddr33_conn \ `rvformal_csr_pmpaddr34_conn \ `rvformal_csr_pmpaddr35_conn \ `rvformal_csr_pmpaddr36_conn \ `rvformal_csr_pmpaddr37_conn \ `rvformal_csr_pmpaddr38_conn \ `rvformal_csr_pmpaddr39_conn \ `rvformal_csr_pmpaddr40_conn \ `rvformal_csr_pmpaddr41_conn \ `rvformal_csr_pmpaddr42_conn \ `rvformal_csr_pmpaddr43_conn \ `rvformal_csr_pmpaddr44_conn \ `rvformal_csr_pmpaddr45_conn \ `rvformal_csr_pmpaddr46_conn \ `rvformal_csr_pmpaddr47_conn \ `rvformal_csr_pmpaddr48_conn \ `rvformal_csr_pmpaddr49_conn \ `rvformal_csr_pmpaddr50_conn \ `rvformal_csr_pmpaddr51_conn \ `rvformal_csr_pmpaddr52_conn \ `rvformal_csr_pmpaddr53_conn \ `rvformal_csr_pmpaddr54_conn \ `rvformal_csr_pmpaddr55_conn \ `rvformal_csr_pmpaddr56_conn \ `rvformal_csr_pmpaddr57_conn \ `rvformal_csr_pmpaddr58_conn \ `rvformal_csr_pmpaddr59_conn \ `rvformal_csr_pmpaddr60_conn \ `rvformal_csr_pmpaddr61_conn \ `rvformal_csr_pmpaddr62_conn \ `rvformal_csr_pmpaddr63_conn \ `rvformal_csr_mhpmevent3_conn \ `rvformal_csr_mhpmevent4_conn \ `rvformal_csr_mhpmevent5_conn \ `rvformal_csr_mhpmevent6_conn \ `rvformal_csr_mhpmevent7_conn \ `rvformal_csr_mhpmevent8_conn \ `rvformal_csr_mhpmevent9_conn \ `rvformal_csr_mhpmevent10_conn \ `rvformal_csr_mhpmevent11_conn \ `rvformal_csr_mhpmevent12_conn \ `rvformal_csr_mhpmevent13_conn \ `rvformal_csr_mhpmevent14_conn \ `rvformal_csr_mhpmevent15_conn \ `rvformal_csr_mhpmevent16_conn \ `rvformal_csr_mhpmevent17_conn \ `rvformal_csr_mhpmevent18_conn \ `rvformal_csr_mhpmevent19_conn \ `rvformal_csr_mhpmevent20_conn \ `rvformal_csr_mhpmevent21_conn \ `rvformal_csr_mhpmevent22_conn \ `rvformal_csr_mhpmevent23_conn \ `rvformal_csr_mhpmevent24_conn \ `rvformal_csr_mhpmevent25_conn \ `rvformal_csr_mhpmevent26_conn \ `rvformal_csr_mhpmevent27_conn \ `rvformal_csr_mhpmevent28_conn \ `rvformal_csr_mhpmevent29_conn \ `rvformal_csr_mhpmevent30_conn \ `rvformal_csr_mhpmevent31_conn \ `rvformal_csr_mcycle_conn32 \ `rvformal_csr_time_conn32 \ `rvformal_csr_minstret_conn32 \ `rvformal_csr_mhpmcounter3_conn32 \ `rvformal_csr_mhpmcounter4_conn32 \ `rvformal_csr_mhpmcounter5_conn32 \ `rvformal_csr_mhpmcounter6_conn32 \ `rvformal_csr_mhpmcounter7_conn32 \ `rvformal_csr_mhpmcounter8_conn32 \ `rvformal_csr_mhpmcounter9_conn32 \ `rvformal_csr_mhpmcounter10_conn32 \ `rvformal_csr_mhpmcounter11_conn32 \ `rvformal_csr_mhpmcounter12_conn32 \ `rvformal_csr_mhpmcounter13_conn32 \ `rvformal_csr_mhpmcounter14_conn32 \ `rvformal_csr_mhpmcounter15_conn32 \ `rvformal_csr_mhpmcounter16_conn32 \ `rvformal_csr_mhpmcounter17_conn32 \ `rvformal_csr_mhpmcounter18_conn32 \ `rvformal_csr_mhpmcounter19_conn32 \ `rvformal_csr_mhpmcounter20_conn32 \ `rvformal_csr_mhpmcounter21_conn32 \ `rvformal_csr_mhpmcounter22_conn32 \ `rvformal_csr_mhpmcounter23_conn32 \ `rvformal_csr_mhpmcounter24_conn32 \ `rvformal_csr_mhpmcounter25_conn32 \ `rvformal_csr_mhpmcounter26_conn32 \ `rvformal_csr_mhpmcounter27_conn32 \ `rvformal_csr_mhpmcounter28_conn32 \ `rvformal_csr_mhpmcounter29_conn32 \ `rvformal_csr_mhpmcounter30_conn32 \ `rvformal_csr_mhpmcounter31_conn32 \ `rvformal_custom_csr_conn `define RVFI_GETCHANNEL(_idx) \ wire [ 0 : 0] valid = rvfi_valid [ _idx +: 1 ]; \ wire [ 64 - 1 : 0] order = rvfi_order [(_idx)*( 64 ) +: 64 ]; \ wire [`RISCV_FORMAL_ILEN - 1 : 0] insn = rvfi_insn [(_idx)*(`RISCV_FORMAL_ILEN ) +: `RISCV_FORMAL_ILEN ]; \ wire [ 0 : 0] trap = rvfi_trap [ _idx +: 1 ]; \ wire [ 0 : 0] halt = rvfi_halt [ _idx +: 1 ]; \ wire [ 0 : 0] intr = rvfi_intr [ _idx +: 1 ]; \ wire [ 2 - 1 : 0] mode = rvfi_mode [(_idx)*( 2 ) +: 2 ]; \ wire [ 2 - 1 : 0] ixl = rvfi_ixl [(_idx)*( 2 ) +: 2 ]; \ wire [ 5 - 1 : 0] rs1_addr = rvfi_rs1_addr [(_idx)*( 5 ) +: 5 ]; \ wire [ 5 - 1 : 0] rs2_addr = rvfi_rs2_addr [(_idx)*( 5 ) +: 5 ]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] rs1_rdata = rvfi_rs1_rdata [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] rs2_rdata = rvfi_rs2_rdata [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]; \ wire [ 5 - 1 : 0] rd_addr = rvfi_rd_addr [(_idx)*( 5 ) +: 5 ]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] rd_wdata = rvfi_rd_wdata [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] pc_rdata = rvfi_pc_rdata [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] pc_wdata = rvfi_pc_wdata [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_addr = rvfi_mem_addr [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]; \ wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_rmask = rvfi_mem_rmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8]; \ wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_wmask = rvfi_mem_wmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_rdata = rvfi_mem_rdata [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]; \ wire [`RISCV_FORMAL_XLEN - 1 : 0] mem_wdata = rvfi_mem_wdata [(_idx)*(`RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]; \ `rvformal_extamo_channel(_idx) \ `rvformal_mem_fault_channel(_idx) \ `rvformal_csr_fflags_channel(_idx) \ `rvformal_csr_frm_channel(_idx) \ `rvformal_csr_fcsr_channel(_idx) \ `rvformal_csr_mvendorid_channel(_idx) \ `rvformal_csr_marchid_channel(_idx) \ `rvformal_csr_mimpid_channel(_idx) \ `rvformal_csr_mhartid_channel(_idx) \ `rvformal_csr_mconfigptr_channel(_idx) \ `rvformal_csr_mstatus_channel(_idx) \ `rvformal_csr_mstatush_channel(_idx) \ `rvformal_csr_misa_channel(_idx) \ `rvformal_csr_medeleg_channel(_idx) \ `rvformal_csr_mideleg_channel(_idx) \ `rvformal_csr_mie_channel(_idx) \ `rvformal_csr_mtvec_channel(_idx) \ `rvformal_csr_mcounteren_channel(_idx) \ `rvformal_csr_mscratch_channel(_idx) \ `rvformal_csr_mepc_channel(_idx) \ `rvformal_csr_mcause_channel(_idx) \ `rvformal_csr_mtval_channel(_idx) \ `rvformal_csr_mip_channel(_idx) \ `rvformal_csr_mtinst_channel(_idx) \ `rvformal_csr_mtval2_channel(_idx) \ `rvformal_csr_mcountinhibit_channel(_idx) \ `rvformal_csr_menvcfg_channel(_idx) \ `rvformal_csr_menvcfgh_channel(_idx) \ `rvformal_csr_pmpcfg0_channel(_idx) \ `rvformal_csr_pmpcfg1_channel(_idx) \ `rvformal_csr_pmpcfg2_channel(_idx) \ `rvformal_csr_pmpcfg3_channel(_idx) \ `rvformal_csr_pmpcfg4_channel(_idx) \ `rvformal_csr_pmpcfg5_channel(_idx) \ `rvformal_csr_pmpcfg6_channel(_idx) \ `rvformal_csr_pmpcfg7_channel(_idx) \ `rvformal_csr_pmpcfg8_channel(_idx) \ `rvformal_csr_pmpcfg9_channel(_idx) \ `rvformal_csr_pmpcfg10_channel(_idx) \ `rvformal_csr_pmpcfg11_channel(_idx) \ `rvformal_csr_pmpcfg12_channel(_idx) \ `rvformal_csr_pmpcfg13_channel(_idx) \ `rvformal_csr_pmpcfg14_channel(_idx) \ `rvformal_csr_pmpcfg15_channel(_idx) \ `rvformal_csr_pmpaddr0_channel(_idx) \ `rvformal_csr_pmpaddr1_channel(_idx) \ `rvformal_csr_pmpaddr2_channel(_idx) \ `rvformal_csr_pmpaddr3_channel(_idx) \ `rvformal_csr_pmpaddr4_channel(_idx) \ `rvformal_csr_pmpaddr5_channel(_idx) \ `rvformal_csr_pmpaddr6_channel(_idx) \ `rvformal_csr_pmpaddr7_channel(_idx) \ `rvformal_csr_pmpaddr8_channel(_idx) \ `rvformal_csr_pmpaddr9_channel(_idx) \ `rvformal_csr_pmpaddr10_channel(_idx) \ `rvformal_csr_pmpaddr11_channel(_idx) \ `rvformal_csr_pmpaddr12_channel(_idx) \ `rvformal_csr_pmpaddr13_channel(_idx) \ `rvformal_csr_pmpaddr14_channel(_idx) \ `rvformal_csr_pmpaddr15_channel(_idx) \ `rvformal_csr_pmpaddr16_channel(_idx) \ `rvformal_csr_pmpaddr17_channel(_idx) \ `rvformal_csr_pmpaddr18_channel(_idx) \ `rvformal_csr_pmpaddr19_channel(_idx) \ `rvformal_csr_pmpaddr20_channel(_idx) \ `rvformal_csr_pmpaddr21_channel(_idx) \ `rvformal_csr_pmpaddr22_channel(_idx) \ `rvformal_csr_pmpaddr23_channel(_idx) \ `rvformal_csr_pmpaddr24_channel(_idx) \ `rvformal_csr_pmpaddr25_channel(_idx) \ `rvformal_csr_pmpaddr26_channel(_idx) \ `rvformal_csr_pmpaddr27_channel(_idx) \ `rvformal_csr_pmpaddr28_channel(_idx) \ `rvformal_csr_pmpaddr29_channel(_idx) \ `rvformal_csr_pmpaddr30_channel(_idx) \ `rvformal_csr_pmpaddr31_channel(_idx) \ `rvformal_csr_pmpaddr32_channel(_idx) \ `rvformal_csr_pmpaddr33_channel(_idx) \ `rvformal_csr_pmpaddr34_channel(_idx) \ `rvformal_csr_pmpaddr35_channel(_idx) \ `rvformal_csr_pmpaddr36_channel(_idx) \ `rvformal_csr_pmpaddr37_channel(_idx) \ `rvformal_csr_pmpaddr38_channel(_idx) \ `rvformal_csr_pmpaddr39_channel(_idx) \ `rvformal_csr_pmpaddr40_channel(_idx) \ `rvformal_csr_pmpaddr41_channel(_idx) \ `rvformal_csr_pmpaddr42_channel(_idx) \ `rvformal_csr_pmpaddr43_channel(_idx) \ `rvformal_csr_pmpaddr44_channel(_idx) \ `rvformal_csr_pmpaddr45_channel(_idx) \ `rvformal_csr_pmpaddr46_channel(_idx) \ `rvformal_csr_pmpaddr47_channel(_idx) \ `rvformal_csr_pmpaddr48_channel(_idx) \ `rvformal_csr_pmpaddr49_channel(_idx) \ `rvformal_csr_pmpaddr50_channel(_idx) \ `rvformal_csr_pmpaddr51_channel(_idx) \ `rvformal_csr_pmpaddr52_channel(_idx) \ `rvformal_csr_pmpaddr53_channel(_idx) \ `rvformal_csr_pmpaddr54_channel(_idx) \ `rvformal_csr_pmpaddr55_channel(_idx) \ `rvformal_csr_pmpaddr56_channel(_idx) \ `rvformal_csr_pmpaddr57_channel(_idx) \ `rvformal_csr_pmpaddr58_channel(_idx) \ `rvformal_csr_pmpaddr59_channel(_idx) \ `rvformal_csr_pmpaddr60_channel(_idx) \ `rvformal_csr_pmpaddr61_channel(_idx) \ `rvformal_csr_pmpaddr62_channel(_idx) \ `rvformal_csr_pmpaddr63_channel(_idx) \ `rvformal_csr_mhpmevent3_channel(_idx) \ `rvformal_csr_mhpmevent4_channel(_idx) \ `rvformal_csr_mhpmevent5_channel(_idx) \ `rvformal_csr_mhpmevent6_channel(_idx) \ `rvformal_csr_mhpmevent7_channel(_idx) \ `rvformal_csr_mhpmevent8_channel(_idx) \ `rvformal_csr_mhpmevent9_channel(_idx) \ `rvformal_csr_mhpmevent10_channel(_idx) \ `rvformal_csr_mhpmevent11_channel(_idx) \ `rvformal_csr_mhpmevent12_channel(_idx) \ `rvformal_csr_mhpmevent13_channel(_idx) \ `rvformal_csr_mhpmevent14_channel(_idx) \ `rvformal_csr_mhpmevent15_channel(_idx) \ `rvformal_csr_mhpmevent16_channel(_idx) \ `rvformal_csr_mhpmevent17_channel(_idx) \ `rvformal_csr_mhpmevent18_channel(_idx) \ `rvformal_csr_mhpmevent19_channel(_idx) \ `rvformal_csr_mhpmevent20_channel(_idx) \ `rvformal_csr_mhpmevent21_channel(_idx) \ `rvformal_csr_mhpmevent22_channel(_idx) \ `rvformal_csr_mhpmevent23_channel(_idx) \ `rvformal_csr_mhpmevent24_channel(_idx) \ `rvformal_csr_mhpmevent25_channel(_idx) \ `rvformal_csr_mhpmevent26_channel(_idx) \ `rvformal_csr_mhpmevent27_channel(_idx) \ `rvformal_csr_mhpmevent28_channel(_idx) \ `rvformal_csr_mhpmevent29_channel(_idx) \ `rvformal_csr_mhpmevent30_channel(_idx) \ `rvformal_csr_mhpmevent31_channel(_idx) \ `rvformal_csr_mcycle_channel(_idx) \ `rvformal_csr_time_channel(_idx) \ `rvformal_csr_minstret_channel(_idx) \ `rvformal_csr_mhpmcounter3_channel(_idx) \ `rvformal_csr_mhpmcounter4_channel(_idx) \ `rvformal_csr_mhpmcounter5_channel(_idx) \ `rvformal_csr_mhpmcounter6_channel(_idx) \ `rvformal_csr_mhpmcounter7_channel(_idx) \ `rvformal_csr_mhpmcounter8_channel(_idx) \ `rvformal_csr_mhpmcounter9_channel(_idx) \ `rvformal_csr_mhpmcounter10_channel(_idx) \ `rvformal_csr_mhpmcounter11_channel(_idx) \ `rvformal_csr_mhpmcounter12_channel(_idx) \ `rvformal_csr_mhpmcounter13_channel(_idx) \ `rvformal_csr_mhpmcounter14_channel(_idx) \ `rvformal_csr_mhpmcounter15_channel(_idx) \ `rvformal_csr_mhpmcounter16_channel(_idx) \ `rvformal_csr_mhpmcounter17_channel(_idx) \ `rvformal_csr_mhpmcounter18_channel(_idx) \ `rvformal_csr_mhpmcounter19_channel(_idx) \ `rvformal_csr_mhpmcounter20_channel(_idx) \ `rvformal_csr_mhpmcounter21_channel(_idx) \ `rvformal_csr_mhpmcounter22_channel(_idx) \ `rvformal_csr_mhpmcounter23_channel(_idx) \ `rvformal_csr_mhpmcounter24_channel(_idx) \ `rvformal_csr_mhpmcounter25_channel(_idx) \ `rvformal_csr_mhpmcounter26_channel(_idx) \ `rvformal_csr_mhpmcounter27_channel(_idx) \ `rvformal_csr_mhpmcounter28_channel(_idx) \ `rvformal_csr_mhpmcounter29_channel(_idx) \ `rvformal_csr_mhpmcounter30_channel(_idx) \ `rvformal_csr_mhpmcounter31_channel(_idx) \ `rvformal_custom_csr_channel(_idx) `define RVFI_SIGNALS \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 1 , valid ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64 , order ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_ILEN , insn ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 1 , trap ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 1 , halt ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 1 , intr ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 2 , mode ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 2 , ixl ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 5 , rs1_addr ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 5 , rs2_addr ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN , rs1_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN , rs2_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 5 , rd_addr ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN , rd_wdata ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN , pc_rdata ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN , pc_wdata ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN , mem_addr ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN/8, mem_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN/8, mem_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN , mem_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN , mem_wdata) \ `rvformal_extamo_signals \ `rvformal_mem_fault_signals \ `rvformal_csr_fflags_signals \ `rvformal_csr_frm_signals \ `rvformal_csr_fcsr_signals \ `rvformal_csr_mvendorid_signals \ `rvformal_csr_marchid_signals \ `rvformal_csr_mimpid_signals \ `rvformal_csr_mhartid_signals \ `rvformal_csr_mconfigptr_signals \ `rvformal_csr_mstatus_signals \ `rvformal_csr_mstatush_signals \ `rvformal_csr_misa_signals \ `rvformal_csr_medeleg_signals \ `rvformal_csr_mideleg_signals \ `rvformal_csr_mie_signals \ `rvformal_csr_mtvec_signals \ `rvformal_csr_mcounteren_signals \ `rvformal_csr_mscratch_signals \ `rvformal_csr_mepc_signals \ `rvformal_csr_mcause_signals \ `rvformal_csr_mtval_signals \ `rvformal_csr_mip_signals \ `rvformal_csr_mtinst_signals \ `rvformal_csr_mtval2_signals \ `rvformal_csr_mcountinhibit_signals \ `rvformal_csr_menvcfg_signals \ `rvformal_csr_menvcfgh_signals \ `rvformal_csr_pmpcfg0_signals \ `rvformal_csr_pmpcfg1_signals \ `rvformal_csr_pmpcfg2_signals \ `rvformal_csr_pmpcfg3_signals \ `rvformal_csr_pmpcfg4_signals \ `rvformal_csr_pmpcfg5_signals \ `rvformal_csr_pmpcfg6_signals \ `rvformal_csr_pmpcfg7_signals \ `rvformal_csr_pmpcfg8_signals \ `rvformal_csr_pmpcfg9_signals \ `rvformal_csr_pmpcfg10_signals \ `rvformal_csr_pmpcfg11_signals \ `rvformal_csr_pmpcfg12_signals \ `rvformal_csr_pmpcfg13_signals \ `rvformal_csr_pmpcfg14_signals \ `rvformal_csr_pmpcfg15_signals \ `rvformal_csr_pmpaddr0_signals \ `rvformal_csr_pmpaddr1_signals \ `rvformal_csr_pmpaddr2_signals \ `rvformal_csr_pmpaddr3_signals \ `rvformal_csr_pmpaddr4_signals \ `rvformal_csr_pmpaddr5_signals \ `rvformal_csr_pmpaddr6_signals \ `rvformal_csr_pmpaddr7_signals \ `rvformal_csr_pmpaddr8_signals \ `rvformal_csr_pmpaddr9_signals \ `rvformal_csr_pmpaddr10_signals \ `rvformal_csr_pmpaddr11_signals \ `rvformal_csr_pmpaddr12_signals \ `rvformal_csr_pmpaddr13_signals \ `rvformal_csr_pmpaddr14_signals \ `rvformal_csr_pmpaddr15_signals \ `rvformal_csr_pmpaddr16_signals \ `rvformal_csr_pmpaddr17_signals \ `rvformal_csr_pmpaddr18_signals \ `rvformal_csr_pmpaddr19_signals \ `rvformal_csr_pmpaddr20_signals \ `rvformal_csr_pmpaddr21_signals \ `rvformal_csr_pmpaddr22_signals \ `rvformal_csr_pmpaddr23_signals \ `rvformal_csr_pmpaddr24_signals \ `rvformal_csr_pmpaddr25_signals \ `rvformal_csr_pmpaddr26_signals \ `rvformal_csr_pmpaddr27_signals \ `rvformal_csr_pmpaddr28_signals \ `rvformal_csr_pmpaddr29_signals \ `rvformal_csr_pmpaddr30_signals \ `rvformal_csr_pmpaddr31_signals \ `rvformal_csr_pmpaddr32_signals \ `rvformal_csr_pmpaddr33_signals \ `rvformal_csr_pmpaddr34_signals \ `rvformal_csr_pmpaddr35_signals \ `rvformal_csr_pmpaddr36_signals \ `rvformal_csr_pmpaddr37_signals \ `rvformal_csr_pmpaddr38_signals \ `rvformal_csr_pmpaddr39_signals \ `rvformal_csr_pmpaddr40_signals \ `rvformal_csr_pmpaddr41_signals \ `rvformal_csr_pmpaddr42_signals \ `rvformal_csr_pmpaddr43_signals \ `rvformal_csr_pmpaddr44_signals \ `rvformal_csr_pmpaddr45_signals \ `rvformal_csr_pmpaddr46_signals \ `rvformal_csr_pmpaddr47_signals \ `rvformal_csr_pmpaddr48_signals \ `rvformal_csr_pmpaddr49_signals \ `rvformal_csr_pmpaddr50_signals \ `rvformal_csr_pmpaddr51_signals \ `rvformal_csr_pmpaddr52_signals \ `rvformal_csr_pmpaddr53_signals \ `rvformal_csr_pmpaddr54_signals \ `rvformal_csr_pmpaddr55_signals \ `rvformal_csr_pmpaddr56_signals \ `rvformal_csr_pmpaddr57_signals \ `rvformal_csr_pmpaddr58_signals \ `rvformal_csr_pmpaddr59_signals \ `rvformal_csr_pmpaddr60_signals \ `rvformal_csr_pmpaddr61_signals \ `rvformal_csr_pmpaddr62_signals \ `rvformal_csr_pmpaddr63_signals \ `rvformal_csr_mhpmevent3_signals \ `rvformal_csr_mhpmevent4_signals \ `rvformal_csr_mhpmevent5_signals \ `rvformal_csr_mhpmevent6_signals \ `rvformal_csr_mhpmevent7_signals \ `rvformal_csr_mhpmevent8_signals \ `rvformal_csr_mhpmevent9_signals \ `rvformal_csr_mhpmevent10_signals \ `rvformal_csr_mhpmevent11_signals \ `rvformal_csr_mhpmevent12_signals \ `rvformal_csr_mhpmevent13_signals \ `rvformal_csr_mhpmevent14_signals \ `rvformal_csr_mhpmevent15_signals \ `rvformal_csr_mhpmevent16_signals \ `rvformal_csr_mhpmevent17_signals \ `rvformal_csr_mhpmevent18_signals \ `rvformal_csr_mhpmevent19_signals \ `rvformal_csr_mhpmevent20_signals \ `rvformal_csr_mhpmevent21_signals \ `rvformal_csr_mhpmevent22_signals \ `rvformal_csr_mhpmevent23_signals \ `rvformal_csr_mhpmevent24_signals \ `rvformal_csr_mhpmevent25_signals \ `rvformal_csr_mhpmevent26_signals \ `rvformal_csr_mhpmevent27_signals \ `rvformal_csr_mhpmevent28_signals \ `rvformal_csr_mhpmevent29_signals \ `rvformal_csr_mhpmevent30_signals \ `rvformal_csr_mhpmevent31_signals \ `rvformal_csr_mcycle_signals \ `rvformal_csr_time_signals \ `rvformal_csr_minstret_signals \ `rvformal_csr_mhpmcounter3_signals \ `rvformal_csr_mhpmcounter4_signals \ `rvformal_csr_mhpmcounter5_signals \ `rvformal_csr_mhpmcounter6_signals \ `rvformal_csr_mhpmcounter7_signals \ `rvformal_csr_mhpmcounter8_signals \ `rvformal_csr_mhpmcounter9_signals \ `rvformal_csr_mhpmcounter10_signals \ `rvformal_csr_mhpmcounter11_signals \ `rvformal_csr_mhpmcounter12_signals \ `rvformal_csr_mhpmcounter13_signals \ `rvformal_csr_mhpmcounter14_signals \ `rvformal_csr_mhpmcounter15_signals \ `rvformal_csr_mhpmcounter16_signals \ `rvformal_csr_mhpmcounter17_signals \ `rvformal_csr_mhpmcounter18_signals \ `rvformal_csr_mhpmcounter19_signals \ `rvformal_csr_mhpmcounter20_signals \ `rvformal_csr_mhpmcounter21_signals \ `rvformal_csr_mhpmcounter22_signals \ `rvformal_csr_mhpmcounter23_signals \ `rvformal_csr_mhpmcounter24_signals \ `rvformal_csr_mhpmcounter25_signals \ `rvformal_csr_mhpmcounter26_signals \ `rvformal_csr_mhpmcounter27_signals \ `rvformal_csr_mhpmcounter28_signals \ `rvformal_csr_mhpmcounter29_signals \ `rvformal_csr_mhpmcounter30_signals \ `rvformal_csr_mhpmcounter31_signals \ `rvformal_custom_csr_signals `define RVFI_CHANNEL(_name, _idx) \ generate if(1) begin:_name \ `RVFI_GETCHANNEL(_idx) \ end endgenerate `ifdef RISCV_FORMAL_BUS `define RVFI_BUS_WIRES \ (* keep *) wire [`RISCV_FORMAL_NBUS - 1 : 0] rvfi_bus_valid; \ (* keep *) wire [`RISCV_FORMAL_NBUS - 1 : 0] rvfi_bus_insn ; \ (* keep *) wire [`RISCV_FORMAL_NBUS - 1 : 0] rvfi_bus_data ; \ (* keep *) wire [`RISCV_FORMAL_NBUS - 1 : 0] rvfi_bus_fault; \ (* keep *) wire [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_bus_addr ; \ (* keep *) wire [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_rmask; \ (* keep *) wire [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_wmask; \ (* keep *) wire [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN - 1 : 0] rvfi_bus_rdata; \ (* keep *) wire [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN - 1 : 0] rvfi_bus_wdata; `define RVFI_BUS_OUTPUTS_NOSEP \ output [`RISCV_FORMAL_NBUS - 1 : 0] rvfi_bus_valid, \ output [`RISCV_FORMAL_NBUS - 1 : 0] rvfi_bus_insn , \ output [`RISCV_FORMAL_NBUS - 1 : 0] rvfi_bus_data , \ output [`RISCV_FORMAL_NBUS - 1 : 0] rvfi_bus_fault, \ output [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_bus_addr , \ output [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_rmask, \ output [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_wmask, \ output [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN - 1 : 0] rvfi_bus_rdata, \ output [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN - 1 : 0] rvfi_bus_wdata `define RVFI_BUS_CHANNEL_OUTPUTS_NOSEP \ output [ 0 : 0] rvfi_bus_valid, \ output [ 0 : 0] rvfi_bus_insn , \ output [ 0 : 0] rvfi_bus_data , \ output [ 0 : 0] rvfi_bus_fault, \ output [ `RISCV_FORMAL_XLEN - 1 : 0] rvfi_bus_addr , \ output [`RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_rmask, \ output [`RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_wmask, \ output [`RISCV_FORMAL_BUSLEN - 1 : 0] rvfi_bus_rdata, \ output [`RISCV_FORMAL_BUSLEN - 1 : 0] rvfi_bus_wdata `define RVFI_BUS_INPUTS_NOSEP \ input [`RISCV_FORMAL_NBUS - 1 : 0] rvfi_bus_valid, \ input [`RISCV_FORMAL_NBUS - 1 : 0] rvfi_bus_insn , \ input [`RISCV_FORMAL_NBUS - 1 : 0] rvfi_bus_data , \ input [`RISCV_FORMAL_NBUS - 1 : 0] rvfi_bus_fault, \ input [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_bus_addr , \ input [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_rmask, \ input [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_wmask, \ input [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN - 1 : 0] rvfi_bus_rdata, \ input [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN - 1 : 0] rvfi_bus_wdata `define RVFI_BUS_CHANNEL_INPUTS_NOSEP \ input [ 0 : 0] rvfi_bus_valid, \ input [ 0 : 0] rvfi_bus_insn , \ input [ 0 : 0] rvfi_bus_data , \ input [ 0 : 0] rvfi_bus_fault, \ input [ `RISCV_FORMAL_XLEN - 1 : 0] rvfi_bus_addr , \ input [`RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_rmask, \ input [`RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_wmask, \ input [`RISCV_FORMAL_BUSLEN - 1 : 0] rvfi_bus_rdata, \ input [`RISCV_FORMAL_BUSLEN - 1 : 0] rvfi_bus_wdata `define RVFI_BUS_CONN_NOSEP \ .rvfi_bus_valid (rvfi_bus_valid), \ .rvfi_bus_insn (rvfi_bus_insn ), \ .rvfi_bus_data (rvfi_bus_data ), \ .rvfi_bus_fault (rvfi_bus_fault), \ .rvfi_bus_addr (rvfi_bus_addr ), \ .rvfi_bus_rmask (rvfi_bus_rmask), \ .rvfi_bus_wmask (rvfi_bus_wmask), \ .rvfi_bus_rdata (rvfi_bus_rdata), \ .rvfi_bus_wdata (rvfi_bus_wdata) `define RVFI_BUS_CHANNEL_CONN_NOSEP(_idx) \ .rvfi_bus_valid (rvfi_bus_valid [ _idx +: 1 ]), \ .rvfi_bus_insn (rvfi_bus_insn [ _idx +: 1 ]), \ .rvfi_bus_data (rvfi_bus_data [ _idx +: 1 ]), \ .rvfi_bus_fault (rvfi_bus_fault [ _idx +: 1 ]), \ .rvfi_bus_addr (rvfi_bus_addr [(_idx)*( `RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]), \ .rvfi_bus_rmask (rvfi_bus_rmask [(_idx)*(`RISCV_FORMAL_BUSLEN/8) +: `RISCV_FORMAL_BUSLEN/8]), \ .rvfi_bus_wmask (rvfi_bus_wmask [(_idx)*(`RISCV_FORMAL_BUSLEN/8) +: `RISCV_FORMAL_BUSLEN/8]), \ .rvfi_bus_rdata (rvfi_bus_rdata [(_idx)*(`RISCV_FORMAL_BUSLEN ) +: `RISCV_FORMAL_BUSLEN ]), \ .rvfi_bus_wdata (rvfi_bus_wdata [(_idx)*(`RISCV_FORMAL_BUSLEN ) +: `RISCV_FORMAL_BUSLEN ]) `define RVFI_BUS_GETCHANNEL(_idx) \ wire [ 0 : 0] bus_valid = rvfi_bus_valid [ _idx +: 1 ]; \ wire [ 0 : 0] bus_insn = rvfi_bus_insn [ _idx +: 1 ]; \ wire [ 0 : 0] bus_data = rvfi_bus_data [ _idx +: 1 ]; \ wire [ 0 : 0] bus_fault = rvfi_bus_fault [ _idx +: 1 ]; \ wire [ `RISCV_FORMAL_XLEN - 1 : 0] bus_addr = rvfi_bus_addr [(_idx)*( `RISCV_FORMAL_XLEN ) +: `RISCV_FORMAL_XLEN ]; \ wire [`RISCV_FORMAL_BUSLEN/8 - 1 : 0] bus_rmask = rvfi_bus_rmask [(_idx)*(`RISCV_FORMAL_BUSLEN/8) +: `RISCV_FORMAL_BUSLEN/8]; \ wire [`RISCV_FORMAL_BUSLEN/8 - 1 : 0] bus_wmask = rvfi_bus_wmask [(_idx)*(`RISCV_FORMAL_BUSLEN/8) +: `RISCV_FORMAL_BUSLEN/8]; \ wire [`RISCV_FORMAL_BUSLEN - 1 : 0] bus_rdata = rvfi_bus_rdata [(_idx)*(`RISCV_FORMAL_BUSLEN ) +: `RISCV_FORMAL_BUSLEN ]; \ wire [`RISCV_FORMAL_BUSLEN - 1 : 0] bus_wdata = rvfi_bus_wdata [(_idx)*(`RISCV_FORMAL_BUSLEN ) +: `RISCV_FORMAL_BUSLEN ]; `define RVFI_BUS_SIGNALS \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS, 1 , bus_valid) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS, 1 , bus_insn ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS, 1 , bus_data ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS, 1 , bus_fault) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS, `RISCV_FORMAL_XLEN , bus_addr ) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS, `RISCV_FORMAL_BUSLEN/8, bus_rmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS, `RISCV_FORMAL_BUSLEN/8, bus_wmask) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS, `RISCV_FORMAL_BUSLEN , bus_rdata) \ `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS, `RISCV_FORMAL_BUSLEN , bus_wdata) `define RVFI_BUS_OUTPUTS , `RVFI_BUS_OUTPUTS_NOSEP `define RVFI_BUS_INPUTS , `RVFI_BUS_INPUTS_NOSEP `define RVFI_BUS_CONN , `RVFI_BUS_CONN_NOSEP `define RVFI_BUS_CHANNEL_OUTPUTS , `RVFI_BUS_CHANNEL_OUTPUTS_NOSEP `define RVFI_BUS_CHANNEL_INPUTS , `RVFI_BUS_CHANNEL_INPUTS_NOSEP `define RVFI_BUS_CHANNEL_CONN(_idx) , `RVFI_BUS_CHANNEL_CONN_NOSEP(_idx) `else `define RVFI_BUS_WIRES `define RVFI_BUS_OUTPUTS `define RVFI_BUS_INPUTS `define RVFI_BUS_CONN `define RVFI_BUS_GETCHANNEL(_idx) `endif `define RVFI_BUS_CHANNEL(_name, _idx) \ generate if(1) begin:_name \ `RVFI_BUS_GETCHANNEL(_idx) \ end endgenerate ================================================ FILE: checks/rvfi_pc_bwd_check.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_pc_bwd_check ( input clock, reset, check, `RVFI_INPUTS ); `rvformal_rand_const_reg [63:0] insn_order; reg [`RISCV_FORMAL_XLEN-1:0] expect_pc; reg expect_pc_valid = 0; wire [`RISCV_FORMAL_XLEN-1:0] pc_wdata = rvfi_pc_wdata[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; integer channel_idx; always @(posedge clock) begin if (reset) begin expect_pc_valid = 0; end else begin if (check) begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_CHANNEL_IDX; channel_idx=channel_idx+1) begin if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order+1) begin expect_pc = rvfi_pc_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; expect_pc_valid = !rvfi_intr[`RISCV_FORMAL_CHANNEL_IDX]; end end assume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]); assume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]); if (expect_pc_valid) begin assert(`rvformal_addr_eq(expect_pc, pc_wdata)); end end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order+1) begin expect_pc = rvfi_pc_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; expect_pc_valid = !rvfi_intr[`RISCV_FORMAL_CHANNEL_IDX]; end end end end end endmodule ================================================ FILE: checks/rvfi_pc_fwd_check.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_pc_fwd_check ( input clock, reset, check, `RVFI_INPUTS ); `rvformal_rand_const_reg [63:0] insn_order; reg [`RISCV_FORMAL_XLEN-1:0] expect_pc; reg expect_pc_valid = 0; wire [`RISCV_FORMAL_XLEN-1:0] pc_rdata = rvfi_pc_rdata[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; integer channel_idx; always @(posedge clock) begin if (reset) begin expect_pc_valid = 0; end else begin if (check) begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_CHANNEL_IDX; channel_idx=channel_idx+1) begin if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order-1) begin expect_pc = rvfi_pc_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; expect_pc_valid = 1; end end assume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]); assume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]); if (expect_pc_valid && !rvfi_intr[`RISCV_FORMAL_CHANNEL_IDX]) begin assert(`rvformal_addr_eq(expect_pc, pc_rdata)); end end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order-1) begin expect_pc = rvfi_pc_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; expect_pc_valid = 1; end end end end end endmodule ================================================ FILE: checks/rvfi_reg_check.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_reg_check ( input clock, reset, check, `RVFI_INPUTS ); `rvformal_rand_const_reg [63:0] insn_order; `rvformal_rand_const_reg [4:0] register_index; reg [`RISCV_FORMAL_XLEN-1:0] register_shadow = 0; reg register_written = 0; integer channel_idx; always @(posedge clock) begin if (reset) begin register_shadow = 0; register_written = 0; end else begin if (check) begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_CHANNEL_IDX; channel_idx=channel_idx+1) begin if (rvfi_valid[channel_idx] && !rvfi_trap[channel_idx] && rvfi_order[64*channel_idx +: 64] < insn_order && register_index == rvfi_rd_addr[channel_idx*5 +: 5]) begin register_shadow = rvfi_rd_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; register_written = 1; end end assume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]); assume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]); if (register_written && register_index == rvfi_rs1_addr[`RISCV_FORMAL_CHANNEL_IDX*5 +: 5]) assert(register_shadow == rvfi_rs1_rdata[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]); if (register_written && register_index == rvfi_rs2_addr[`RISCV_FORMAL_CHANNEL_IDX*5 +: 5]) assert(register_shadow == rvfi_rs2_rdata[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]); end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin if (rvfi_valid[channel_idx] && !rvfi_trap[channel_idx] && rvfi_order[64*channel_idx +: 64] < insn_order && register_index == rvfi_rd_addr[channel_idx*5 +: 5]) begin register_shadow = rvfi_rd_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; register_written = 1; end end end end end endmodule ================================================ FILE: checks/rvfi_testbench.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_testbench ( `ifdef RISCV_FORMAL_UNBOUNDED `ifdef RISCV_FORMAL_TRIG_CYCLE input trig, `endif `ifdef RISCV_FORMAL_CHECK_CYCLE input check, `endif `endif input clock, reset ); `RVFI_WIRES `RVFI_BUS_WIRES `ifdef YOSYS always_comb assume (reset == $initstate); `endif reg [7:0] cycle_reg = 0; wire [7:0] cycle = reset ? 8'd 0 : cycle_reg; always @(posedge clock) begin cycle_reg <= reset ? 8'd 1 : cycle_reg + (cycle_reg != 8'h ff); end `RISCV_FORMAL_CHECKER checker_inst ( .clock (clock), .reset (cycle < `RISCV_FORMAL_RESET_CYCLES), `ifdef RISCV_FORMAL_TRIG_CYCLE `ifdef RISCV_FORMAL_UNBOUNDED .trig (trig), `else .trig (cycle == `RISCV_FORMAL_TRIG_CYCLE), `endif `endif `ifdef RISCV_FORMAL_CHECK_CYCLE `ifdef RISCV_FORMAL_UNBOUNDED .check (check), `else .check (cycle == `RISCV_FORMAL_CHECK_CYCLE), `endif `endif `RVFI_CONN `RVFI_BUS_CONN ); rvfi_wrapper wrapper ( .clock (clock), .reset (reset), `RVFI_CONN `RVFI_BUS_CONN ); `ifdef RISCV_FORMAL_ASSUME `include "assume_stmts.vh" `endif endmodule module rvfi_seq #( parameter [1023:0] seq = "", parameter integer N = 1 ) ( input clock, output reg [N-1:0] dout, output reg en ); localparam seqlen = $clog2(seq) / 8; integer cycle = 0; wire [31:0] position = seqlen - cycle; wire [7:0] ch = seq >> (8*position); always @(posedge clock) begin cycle <= cycle + 1; end always @* begin en = |ch; dout = 4'b xxxx; case (ch) "0", "_": dout = 0; "1": dout = 1; "2": dout = 2; "3": dout = 3; "4": dout = 4; "5": dout = 5; "6": dout = 6; "7": dout = 7; "8": dout = 8; "9": dout = 9; "A", "a": dout = 10; "B", "b": dout = 11; "C", "c": dout = 12; "D", "d": dout = 13; "E", "e": dout = 14; "F", "f", "-": dout = 15; "X", "x", " ": begin dout = 4'b xxxx; en = 0; end endcase end endmodule module rvfi_assume_seq #( parameter [1023:0] seq = "", parameter integer N = 1 ) ( input clock, input [N-1:0] din ); wire en; wire [N-1:0] dout; rvfi_seq #(seq, N) seq_inst (clock, dout, en); always @* if (en) assume (din == dout); endmodule ================================================ FILE: checks/rvfi_unique_check.sv ================================================ // Copyright (C) 2017 Claire Xenia Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. module rvfi_unique_check ( input clock, reset, trig, check, `RVFI_INPUTS ); `rvformal_rand_const_reg [63:0] insn_order; reg found_other_insn = 0; integer channel_idx; always @(posedge clock) begin if (reset) begin found_other_insn = 0; end else begin for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order && (!trig || channel_idx != `RISCV_FORMAL_CHANNEL_IDX)) begin found_other_insn = 1; end end if (trig) begin assume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]); assume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]); end if (check) begin assert(!found_other_insn); end end end endmodule ================================================ FILE: cores/VexRiscv/.gitignore ================================================ cover complete /checks/ /dmemcheck/ /imemcheck/ /picorv32.v /disasm.s /disasm.o ================================================ FILE: cores/VexRiscv/README.md ================================================ riscv-formal proofs for VexRiscv ================================ ### Current state: Test a simple VexRiscv configuration (https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/demo/FormalSimple.scala) All standards checks are passing - Instruction Checks - PC Checks - Register Checks - Causality - Liveness Others tests passing : - Instruction Memory check - Data Memory check ### Quickstart guide: First install Yosys, SymbiYosys, and the solvers. See [here](http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing) for instructions. To run all standards checks: ``` python3 ../../checks/genchecks.py make -C checks -j$(nproc) ``` To run again a single check which had failed: ``` #A single time python3 ../../checks/genchecks.py #Each time export test=insn_beq_ch0; rm -r checks/$test; make -C checks -j$(nproc) $test/PASS; python3 disasm.py checks/$test/engine_0/trace.vcd ``` To run imem/dmem checks checks : ``` sby -f imemcheck.sby sby -f dmemcheck.sby ``` ### Todo: - Integrate others VexRiscv configurations into the framework - Add Checking for equivalence of core with and without RVFI check - Add Complete check - Add Cover check ================================================ FILE: cores/VexRiscv/VexRiscv.v ================================================ // Generator : SpinalHDL v1.6.4 git head : 598c18959149eb18e5eee5b0aa3eef01ecaa41a1 // Component : VexRiscv // Git hash : e1620c68b2bfcff7ad1bc8ce665cf4ce29452141 `timescale 1ns/1ps module VexRiscv ( output reg rvfi_valid, output [63:0] rvfi_order, output [31:0] rvfi_insn, output reg rvfi_trap, output reg rvfi_halt, output rvfi_intr, output [1:0] rvfi_mode, output [1:0] rvfi_ixl, output [4:0] rvfi_rs1_addr, output [31:0] rvfi_rs1_rdata, output [4:0] rvfi_rs2_addr, output [31:0] rvfi_rs2_rdata, output [4:0] rvfi_rd_addr, output [31:0] rvfi_rd_wdata, output [31:0] rvfi_pc_rdata, output [31:0] rvfi_pc_wdata, output [31:0] rvfi_mem_addr, output [3:0] rvfi_mem_rmask, output [3:0] rvfi_mem_wmask, output [31:0] rvfi_mem_rdata, output [31:0] rvfi_mem_wdata, output iBus_cmd_valid, input iBus_cmd_ready, output [31:0] iBus_cmd_payload_pc, input iBus_rsp_valid, input iBus_rsp_payload_error, input [31:0] iBus_rsp_payload_inst, output dBus_cmd_valid, input dBus_cmd_ready, output dBus_cmd_payload_wr, output [31:0] dBus_cmd_payload_address, output [31:0] dBus_cmd_payload_data, output [1:0] dBus_cmd_payload_size, input dBus_rsp_ready, input dBus_rsp_error, input [31:0] dBus_rsp_data, input clk, input reset ); localparam ShiftCtrlEnum_DISABLE_1 = 2'd0; localparam ShiftCtrlEnum_SLL_1 = 2'd1; localparam ShiftCtrlEnum_SRL_1 = 2'd2; localparam ShiftCtrlEnum_SRA_1 = 2'd3; localparam BranchCtrlEnum_INC = 2'd0; localparam BranchCtrlEnum_B = 2'd1; localparam BranchCtrlEnum_JAL = 2'd2; localparam BranchCtrlEnum_JALR = 2'd3; localparam AluBitwiseCtrlEnum_XOR_1 = 2'd0; localparam AluBitwiseCtrlEnum_OR_1 = 2'd1; localparam AluBitwiseCtrlEnum_AND_1 = 2'd2; localparam AluCtrlEnum_ADD_SUB = 2'd0; localparam AluCtrlEnum_SLT_SLTU = 2'd1; localparam AluCtrlEnum_BITWISE = 2'd2; localparam Src2CtrlEnum_RS = 2'd0; localparam Src2CtrlEnum_IMI = 2'd1; localparam Src2CtrlEnum_IMS = 2'd2; localparam Src2CtrlEnum_PC = 2'd3; localparam Src1CtrlEnum_RS = 2'd0; localparam Src1CtrlEnum_IMU = 2'd1; localparam Src1CtrlEnum_PC_INCREMENT = 2'd2; localparam Src1CtrlEnum_URS1 = 2'd3; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready; reg [54:0] _zz_IBusSimplePlugin_predictor_history_port1; reg [31:0] _zz_RegFilePlugin_regFile_port0; reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; wire [31:0] _zz_execute_NEXT_PC2; wire [2:0] _zz_execute_NEXT_PC2_1; wire [31:0] _zz_execute_SHIFT_RIGHT; wire [32:0] _zz_execute_SHIFT_RIGHT_1; wire [32:0] _zz_execute_SHIFT_RIGHT_2; wire [31:0] _zz_decode_LEGAL_INSTRUCTION; wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; wire _zz_decode_LEGAL_INSTRUCTION_3; wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; wire [7:0] _zz_decode_LEGAL_INSTRUCTION_5; wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; wire _zz_decode_LEGAL_INSTRUCTION_9; wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; wire [1:0] _zz_decode_LEGAL_INSTRUCTION_11; wire [31:0] _zz_IBusSimplePlugin_fetchPc_pc; wire [2:0] _zz_IBusSimplePlugin_fetchPc_pc_1; wire [31:0] _zz_IBusSimplePlugin_decodePc_pcPlus; wire [2:0] _zz_IBusSimplePlugin_decodePc_pcPlus_1; wire [31:0] _zz_IBusSimplePlugin_decompressor_decompressed_27; wire _zz_IBusSimplePlugin_decompressor_decompressed_28; wire _zz_IBusSimplePlugin_decompressor_decompressed_29; wire [6:0] _zz_IBusSimplePlugin_decompressor_decompressed_30; wire [4:0] _zz_IBusSimplePlugin_decompressor_decompressed_31; wire _zz_IBusSimplePlugin_decompressor_decompressed_32; wire [4:0] _zz_IBusSimplePlugin_decompressor_decompressed_33; wire [11:0] _zz_IBusSimplePlugin_decompressor_decompressed_34; wire [11:0] _zz_IBusSimplePlugin_decompressor_decompressed_35; wire [31:0] _zz__zz_decode_FORMAL_PC_NEXT; wire [2:0] _zz__zz_decode_FORMAL_PC_NEXT_1; wire [54:0] _zz_IBusSimplePlugin_predictor_history_port; wire [9:0] _zz_IBusSimplePlugin_predictor_history_port_1; wire [9:0] _zz__zz_IBusSimplePlugin_predictor_buffer_line_source_1; wire [9:0] _zz_IBusSimplePlugin_predictor_buffer_hazard; wire [29:0] _zz_IBusSimplePlugin_predictor_buffer_hazard_1; wire [19:0] _zz_IBusSimplePlugin_predictor_hit; wire [1:0] _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish; wire [1:0] _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_1; wire [0:0] _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_2; wire [1:0] _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_3; wire [0:0] _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_4; wire [1:0] _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_5; wire [1:0] _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_6; wire [0:0] _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_7; wire [1:0] _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_8; wire [0:0] _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_9; wire [29:0] _zz_IBusSimplePlugin_predictor_historyWrite_payload_address; wire [2:0] _zz_IBusSimplePlugin_pending_next; wire [2:0] _zz_IBusSimplePlugin_pending_next_1; wire [0:0] _zz_IBusSimplePlugin_pending_next_2; wire [2:0] _zz_IBusSimplePlugin_pending_next_3; wire [0:0] _zz_IBusSimplePlugin_pending_next_4; wire [2:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; wire [0:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1; wire [2:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2; wire [0:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3; wire [2:0] _zz_DBusSimplePlugin_memoryExceptionPort_payload_code; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_1; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_2; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_3; wire _zz__zz_decode_BRANCH_CTRL_2_4; wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_5; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_6; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_7; wire _zz__zz_decode_BRANCH_CTRL_2_8; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_9; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_10; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_11; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_12; wire [16:0] _zz__zz_decode_BRANCH_CTRL_2_13; wire _zz__zz_decode_BRANCH_CTRL_2_14; wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_15; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_16; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_17; wire _zz__zz_decode_BRANCH_CTRL_2_18; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_19; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_20; wire _zz__zz_decode_BRANCH_CTRL_2_21; wire [12:0] _zz__zz_decode_BRANCH_CTRL_2_22; wire _zz__zz_decode_BRANCH_CTRL_2_23; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_24; wire _zz__zz_decode_BRANCH_CTRL_2_25; wire _zz__zz_decode_BRANCH_CTRL_2_26; wire _zz__zz_decode_BRANCH_CTRL_2_27; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_28; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_29; wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_30; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_31; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_32; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_33; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_34; wire [8:0] _zz__zz_decode_BRANCH_CTRL_2_35; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_36; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_37; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_38; wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_39; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_40; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_41; wire _zz__zz_decode_BRANCH_CTRL_2_42; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_43; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_44; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_45; wire _zz__zz_decode_BRANCH_CTRL_2_46; wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_47; wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_48; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_49; wire _zz__zz_decode_BRANCH_CTRL_2_50; wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_51; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_52; wire _zz__zz_decode_BRANCH_CTRL_2_53; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_54; wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_55; wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_56; wire _zz__zz_decode_BRANCH_CTRL_2_57; wire _zz__zz_decode_BRANCH_CTRL_2_58; wire _zz_RegFilePlugin_regFile_port; wire _zz_decode_RegFilePlugin_rs1Data; wire _zz_RegFilePlugin_regFile_port_1; wire _zz_decode_RegFilePlugin_rs2Data; wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; wire [2:0] _zz__zz_decode_SRC1_1; wire [4:0] _zz__zz_decode_SRC1_1_1; wire [11:0] _zz__zz_decode_SRC2_4; wire [31:0] _zz_execute_SrcPlugin_addSub; wire [31:0] _zz_execute_SrcPlugin_addSub_1; wire [31:0] _zz_execute_SrcPlugin_addSub_2; wire [31:0] _zz_execute_SrcPlugin_addSub_3; wire [31:0] _zz_execute_SrcPlugin_addSub_4; wire [31:0] _zz_execute_SrcPlugin_addSub_5; wire [31:0] _zz_execute_SrcPlugin_addSub_6; wire [19:0] _zz__zz_execute_BRANCH_SRC22; wire [11:0] _zz__zz_execute_BRANCH_SRC22_4; wire [31:0] writeBack_FORMAL_MEM_RDATA; wire [31:0] memory_MEMORY_READ_DATA; wire execute_TARGET_MISSMATCH2; wire [31:0] execute_NEXT_PC2; wire execute_BRANCH_DO; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire [31:0] execute_REGFILE_WRITE_DATA; wire [31:0] writeBack_FORMAL_MEM_WDATA; wire [31:0] memory_FORMAL_MEM_WDATA; wire [31:0] execute_FORMAL_MEM_WDATA; wire [3:0] writeBack_FORMAL_MEM_RMASK; wire [3:0] memory_FORMAL_MEM_RMASK; wire [3:0] execute_FORMAL_MEM_RMASK; wire [3:0] writeBack_FORMAL_MEM_WMASK; wire [3:0] memory_FORMAL_MEM_WMASK; wire [3:0] execute_FORMAL_MEM_WMASK; wire [31:0] writeBack_FORMAL_MEM_ADDR; wire [31:0] memory_FORMAL_MEM_ADDR; wire [31:0] execute_FORMAL_MEM_ADDR; wire [1:0] memory_MEMORY_ADDRESS_LOW; wire [1:0] execute_MEMORY_ADDRESS_LOW; wire [31:0] decode_SRC2; wire [31:0] decode_SRC1; wire decode_SRC2_FORCE_ZERO; wire [31:0] writeBack_RS2; wire [31:0] memory_RS2; wire [31:0] decode_RS2; wire [31:0] writeBack_RS1; wire [31:0] memory_RS1; wire [31:0] decode_RS1; wire [1:0] decode_BRANCH_CTRL; wire [1:0] _zz_decode_BRANCH_CTRL; wire [1:0] _zz_decode_to_execute_BRANCH_CTRL; wire [1:0] _zz_decode_to_execute_BRANCH_CTRL_1; wire [1:0] _zz_execute_to_memory_SHIFT_CTRL; wire [1:0] _zz_execute_to_memory_SHIFT_CTRL_1; wire [1:0] decode_SHIFT_CTRL; wire [1:0] _zz_decode_SHIFT_CTRL; wire [1:0] _zz_decode_to_execute_SHIFT_CTRL; wire [1:0] _zz_decode_to_execute_SHIFT_CTRL_1; wire [1:0] decode_ALU_BITWISE_CTRL; wire [1:0] _zz_decode_ALU_BITWISE_CTRL; wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL; wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire writeBack_RS2_USE; wire memory_RS2_USE; wire execute_RS2_USE; wire decode_MEMORY_STORE; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; wire [1:0] decode_ALU_CTRL; wire [1:0] _zz_decode_ALU_CTRL; wire [1:0] _zz_decode_to_execute_ALU_CTRL; wire [1:0] _zz_decode_to_execute_ALU_CTRL_1; wire writeBack_RS1_USE; wire memory_RS1_USE; wire execute_RS1_USE; wire decode_MEMORY_ENABLE; wire execute_PREDICTION_CONTEXT_hazard; wire execute_PREDICTION_CONTEXT_hit; wire [19:0] execute_PREDICTION_CONTEXT_line_source; wire [1:0] execute_PREDICTION_CONTEXT_line_branchWish; wire execute_PREDICTION_CONTEXT_line_last2Bytes; wire [31:0] execute_PREDICTION_CONTEXT_line_target; wire decode_PREDICTION_CONTEXT_hazard; wire decode_PREDICTION_CONTEXT_hit; wire [19:0] decode_PREDICTION_CONTEXT_line_source; wire [1:0] decode_PREDICTION_CONTEXT_line_branchWish; wire decode_PREDICTION_CONTEXT_line_last2Bytes; wire [31:0] decode_PREDICTION_CONTEXT_line_target; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire [31:0] writeBack_FORMAL_INSTRUCTION; wire [31:0] memory_FORMAL_INSTRUCTION; wire [31:0] execute_FORMAL_INSTRUCTION; wire [31:0] decode_FORMAL_INSTRUCTION; wire writeBack_FORMAL_HALT; wire memory_FORMAL_HALT; wire execute_FORMAL_HALT; wire decode_FORMAL_HALT; wire [31:0] memory_NEXT_PC2; wire [31:0] memory_BRANCH_CALC; wire memory_TARGET_MISSMATCH2; wire memory_BRANCH_DO; wire [31:0] execute_BRANCH_CALC; wire execute_IS_RVC; wire [31:0] execute_BRANCH_SRC22; wire [31:0] execute_PC; wire [31:0] execute_RS1; wire [1:0] execute_BRANCH_CTRL; wire [1:0] _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; wire [31:0] memory_INSTRUCTION; wire memory_BYPASSABLE_MEMORY_STAGE; wire writeBack_REGFILE_WRITE_VALID; wire [31:0] memory_SHIFT_RIGHT; reg [31:0] _zz_memory_to_writeBack_REGFILE_WRITE_DATA; wire [1:0] memory_SHIFT_CTRL; wire [1:0] _zz_memory_SHIFT_CTRL; wire [1:0] execute_SHIFT_CTRL; wire [1:0] _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; wire [31:0] _zz_decode_SRC2; wire [31:0] _zz_decode_SRC2_1; wire [1:0] decode_SRC2_CTRL; wire [1:0] _zz_decode_SRC2_CTRL; wire [31:0] _zz_decode_SRC1; wire [1:0] decode_SRC1_CTRL; wire [1:0] _zz_decode_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; wire [1:0] execute_ALU_CTRL; wire [1:0] _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; wire [1:0] execute_ALU_BITWISE_CTRL; wire [1:0] _zz_execute_ALU_BITWISE_CTRL; reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; wire [1:0] _zz_decode_BRANCH_CTRL_1; wire [1:0] _zz_decode_SHIFT_CTRL_1; wire [1:0] _zz_decode_ALU_BITWISE_CTRL_1; wire [1:0] _zz_decode_SRC2_CTRL_1; wire [1:0] _zz_decode_ALU_CTRL_1; wire [1:0] _zz_decode_SRC1_CTRL_1; wire writeBack_MEMORY_ENABLE; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; wire [31:0] writeBack_MEMORY_READ_DATA; wire memory_ALIGNEMENT_FAULT; wire [31:0] memory_REGFILE_WRITE_DATA; wire memory_MEMORY_STORE; wire memory_MEMORY_ENABLE; wire [31:0] execute_SRC_ADD; wire [31:0] execute_RS2; wire [31:0] execute_INSTRUCTION; wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; wire execute_ALIGNEMENT_FAULT; wire memory_IS_RVC; wire [31:0] memory_PC; wire memory_PREDICTION_CONTEXT_hazard; wire memory_PREDICTION_CONTEXT_hit; wire [19:0] memory_PREDICTION_CONTEXT_line_source; wire [1:0] memory_PREDICTION_CONTEXT_line_branchWish; wire memory_PREDICTION_CONTEXT_line_last2Bytes; wire [31:0] memory_PREDICTION_CONTEXT_line_target; reg _zz_2; reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; wire [31:0] decode_PC; reg [31:0] _zz_decode_FORMAL_PC_NEXT; wire [31:0] decode_INSTRUCTION; wire decode_IS_RVC; reg _zz_when_FormalPlugin_l114; reg _zz_when_FormalPlugin_l114_1; reg _zz_when_FormalPlugin_l114_2; reg _zz_when_FormalPlugin_l114_3; reg [31:0] _zz_rvfi_rd_wdata; wire _zz_rvfi_rd_addr; wire _zz_rvfi_rs2_addr; wire [31:0] _zz_rvfi_rs1_addr; wire _zz_rvfi_rs1_addr_1; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; reg decode_arbitration_haltItself; reg decode_arbitration_haltByOther; reg decode_arbitration_removeIt; wire decode_arbitration_flushIt; wire decode_arbitration_flushNext; wire decode_arbitration_isValid; wire decode_arbitration_isStuck; wire decode_arbitration_isStuckByOthers; wire decode_arbitration_isFlushed; wire decode_arbitration_isMoving; wire decode_arbitration_isFiring; reg execute_arbitration_haltItself; wire execute_arbitration_haltByOther; reg execute_arbitration_removeIt; wire execute_arbitration_flushIt; wire execute_arbitration_flushNext; reg execute_arbitration_isValid; wire execute_arbitration_isStuck; wire execute_arbitration_isStuckByOthers; wire execute_arbitration_isFlushed; wire execute_arbitration_isMoving; wire execute_arbitration_isFiring; reg memory_arbitration_haltItself; wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; wire memory_arbitration_flushIt; reg memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; wire memory_arbitration_isStuckByOthers; wire memory_arbitration_isFlushed; wire memory_arbitration_isMoving; wire memory_arbitration_isFiring; wire writeBack_arbitration_haltItself; wire writeBack_arbitration_haltByOther; reg writeBack_arbitration_removeIt; wire writeBack_arbitration_flushIt; wire writeBack_arbitration_flushNext; reg writeBack_arbitration_isValid; wire writeBack_arbitration_isStuck; wire writeBack_arbitration_isStuckByOthers; wire writeBack_arbitration_isFlushed; wire writeBack_arbitration_isMoving; wire writeBack_arbitration_isFiring; wire [31:0] lastStageInstruction /* verilator public */ ; wire [31:0] lastStagePc /* verilator public */ ; wire lastStageIsValid /* verilator public */ ; wire lastStageIsFiring /* verilator public */ ; wire IBusSimplePlugin_fetcherHalt; reg IBusSimplePlugin_incomingInstruction; wire IBusSimplePlugin_fetchPrediction_cmd_hadBranch; wire [31:0] IBusSimplePlugin_fetchPrediction_cmd_targetPc; wire IBusSimplePlugin_fetchPrediction_rsp_wasRight; wire [31:0] IBusSimplePlugin_fetchPrediction_rsp_finalPc; wire [31:0] IBusSimplePlugin_fetchPrediction_rsp_sourceLastWord; wire IBusSimplePlugin_pcValids_0; wire IBusSimplePlugin_pcValids_1; wire IBusSimplePlugin_pcValids_2; wire IBusSimplePlugin_pcValids_3; reg DBusSimplePlugin_memoryExceptionPort_valid; reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; wire BranchPlugin_jumpInterface_valid; wire [31:0] BranchPlugin_jumpInterface_payload; reg [63:0] writeBack_FormalPlugin_order; reg writeBack_FormalPlugin_haltRequest; wire when_FormalPlugin_l114; wire when_FormalPlugin_l115; wire when_FormalPlugin_l114_1; wire when_FormalPlugin_l115_1; wire when_FormalPlugin_l114_2; wire when_FormalPlugin_l115_2; wire when_FormalPlugin_l114_3; wire when_FormalPlugin_l115_3; reg writeBack_FormalPlugin_haltRequest_delay_1; reg writeBack_FormalPlugin_haltRequest_delay_2; reg writeBack_FormalPlugin_haltRequest_delay_3; reg writeBack_FormalPlugin_haltRequest_delay_4; reg writeBack_FormalPlugin_haltRequest_delay_5; reg writeBack_FormalPlugin_haltFired; wire when_FormalPlugin_l127; wire when_HaltOnExceptionPlugin_l34; wire when_HaltOnExceptionPlugin_l34_1; wire IBusSimplePlugin_externalFlush; wire IBusSimplePlugin_jump_pcLoad_valid; wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; wire IBusSimplePlugin_fetchPc_output_valid; wire IBusSimplePlugin_fetchPc_output_ready; wire [31:0] IBusSimplePlugin_fetchPc_output_payload; reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; reg IBusSimplePlugin_fetchPc_correction; reg IBusSimplePlugin_fetchPc_correctionReg; wire IBusSimplePlugin_fetchPc_output_fire; wire IBusSimplePlugin_fetchPc_corrected; wire IBusSimplePlugin_fetchPc_pcRegPropagate; reg IBusSimplePlugin_fetchPc_booted; reg IBusSimplePlugin_fetchPc_inc; wire when_Fetcher_l131; wire IBusSimplePlugin_fetchPc_output_fire_1; wire when_Fetcher_l131_1; reg [31:0] IBusSimplePlugin_fetchPc_pc; wire IBusSimplePlugin_fetchPc_predictionPcLoad_valid; wire [31:0] IBusSimplePlugin_fetchPc_predictionPcLoad_payload; wire IBusSimplePlugin_fetchPc_redo_valid; reg [31:0] IBusSimplePlugin_fetchPc_redo_payload; reg IBusSimplePlugin_fetchPc_flushed; wire when_Fetcher_l158; reg IBusSimplePlugin_decodePc_flushed; reg [31:0] IBusSimplePlugin_decodePc_pcReg /* verilator public */ ; wire [31:0] IBusSimplePlugin_decodePc_pcPlus; wire IBusSimplePlugin_decodePc_injectedDecode; wire when_Fetcher_l180; wire IBusSimplePlugin_decodePc_predictionPcLoad_valid; wire [31:0] IBusSimplePlugin_decodePc_predictionPcLoad_payload; wire when_Fetcher_l192; reg IBusSimplePlugin_iBusRsp_redoFetch; wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; reg IBusSimplePlugin_iBusRsp_stages_0_halt; wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; wire IBusSimplePlugin_iBusRsp_stages_1_halt; wire _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready; wire _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready; wire IBusSimplePlugin_iBusRsp_flush; wire IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid; wire IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_ready; wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_payload; reg _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid; reg [31:0] _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_payload; reg IBusSimplePlugin_iBusRsp_readyForError; wire IBusSimplePlugin_iBusRsp_output_valid; wire IBusSimplePlugin_iBusRsp_output_ready; wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc; wire IBusSimplePlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; wire IBusSimplePlugin_iBusRsp_output_payload_isRvc; wire IBusSimplePlugin_decompressor_input_valid; reg IBusSimplePlugin_decompressor_input_ready; wire [31:0] IBusSimplePlugin_decompressor_input_payload_pc; wire IBusSimplePlugin_decompressor_input_payload_rsp_error; wire [31:0] IBusSimplePlugin_decompressor_input_payload_rsp_inst; wire IBusSimplePlugin_decompressor_input_payload_isRvc; wire IBusSimplePlugin_decompressor_output_valid; wire IBusSimplePlugin_decompressor_output_ready; wire [31:0] IBusSimplePlugin_decompressor_output_payload_pc; wire IBusSimplePlugin_decompressor_output_payload_rsp_error; wire [31:0] IBusSimplePlugin_decompressor_output_payload_rsp_inst; wire IBusSimplePlugin_decompressor_output_payload_isRvc; wire IBusSimplePlugin_decompressor_flushNext; wire IBusSimplePlugin_decompressor_consumeCurrent; reg IBusSimplePlugin_decompressor_bufferValid; reg [15:0] IBusSimplePlugin_decompressor_bufferData; wire IBusSimplePlugin_decompressor_isInputLowRvc; wire IBusSimplePlugin_decompressor_isInputHighRvc; reg IBusSimplePlugin_decompressor_throw2BytesReg; wire IBusSimplePlugin_decompressor_throw2Bytes; wire IBusSimplePlugin_decompressor_unaligned; reg IBusSimplePlugin_decompressor_bufferValidLatch; reg IBusSimplePlugin_decompressor_throw2BytesLatch; wire IBusSimplePlugin_decompressor_bufferValidPatched; wire IBusSimplePlugin_decompressor_throw2BytesPatched; wire [31:0] IBusSimplePlugin_decompressor_raw; wire IBusSimplePlugin_decompressor_isRvc; wire [15:0] _zz_IBusSimplePlugin_decompressor_decompressed; reg [31:0] IBusSimplePlugin_decompressor_decompressed; wire [4:0] _zz_IBusSimplePlugin_decompressor_decompressed_1; wire [4:0] _zz_IBusSimplePlugin_decompressor_decompressed_2; wire [11:0] _zz_IBusSimplePlugin_decompressor_decompressed_3; wire _zz_IBusSimplePlugin_decompressor_decompressed_4; reg [11:0] _zz_IBusSimplePlugin_decompressor_decompressed_5; wire _zz_IBusSimplePlugin_decompressor_decompressed_6; reg [9:0] _zz_IBusSimplePlugin_decompressor_decompressed_7; wire [20:0] _zz_IBusSimplePlugin_decompressor_decompressed_8; wire _zz_IBusSimplePlugin_decompressor_decompressed_9; reg [14:0] _zz_IBusSimplePlugin_decompressor_decompressed_10; wire _zz_IBusSimplePlugin_decompressor_decompressed_11; reg [2:0] _zz_IBusSimplePlugin_decompressor_decompressed_12; wire _zz_IBusSimplePlugin_decompressor_decompressed_13; reg [9:0] _zz_IBusSimplePlugin_decompressor_decompressed_14; wire [20:0] _zz_IBusSimplePlugin_decompressor_decompressed_15; wire _zz_IBusSimplePlugin_decompressor_decompressed_16; reg [4:0] _zz_IBusSimplePlugin_decompressor_decompressed_17; wire [12:0] _zz_IBusSimplePlugin_decompressor_decompressed_18; wire [4:0] _zz_IBusSimplePlugin_decompressor_decompressed_19; wire [4:0] _zz_IBusSimplePlugin_decompressor_decompressed_20; wire [4:0] _zz_IBusSimplePlugin_decompressor_decompressed_21; wire [4:0] switch_Misc_l44; wire _zz_IBusSimplePlugin_decompressor_decompressed_22; wire [1:0] switch_Misc_l211; wire [1:0] switch_Misc_l211_1; reg [2:0] _zz_IBusSimplePlugin_decompressor_decompressed_23; reg [2:0] _zz_IBusSimplePlugin_decompressor_decompressed_24; wire _zz_IBusSimplePlugin_decompressor_decompressed_25; reg [6:0] _zz_IBusSimplePlugin_decompressor_decompressed_26; wire IBusSimplePlugin_decompressor_output_fire; wire IBusSimplePlugin_decompressor_bufferFill; wire when_Fetcher_l283; wire when_Fetcher_l286; wire when_Fetcher_l291; wire IBusSimplePlugin_injector_decodeInput_valid; wire IBusSimplePlugin_injector_decodeInput_ready; wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; reg _zz_IBusSimplePlugin_injector_decodeInput_valid; reg [31:0] _zz_IBusSimplePlugin_injector_decodeInput_payload_pc; reg _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error; reg [31:0] _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; reg _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc; reg IBusSimplePlugin_injector_nextPcCalc_valids_0; wire when_Fetcher_l329; reg IBusSimplePlugin_injector_nextPcCalc_valids_1; wire when_Fetcher_l329_1; reg IBusSimplePlugin_injector_nextPcCalc_valids_2; wire when_Fetcher_l329_2; reg IBusSimplePlugin_injector_nextPcCalc_valids_3; wire when_Fetcher_l329_3; reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; wire IBusSimplePlugin_predictor_historyWriteDelayPatched_valid; wire [9:0] IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_address; wire [19:0] IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_source; wire [1:0] IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_branchWish; wire IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_last2Bytes; wire [31:0] IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_target; reg IBusSimplePlugin_predictor_historyWrite_valid; reg [9:0] IBusSimplePlugin_predictor_historyWrite_payload_address; wire [19:0] IBusSimplePlugin_predictor_historyWrite_payload_data_source; reg [1:0] IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish; wire IBusSimplePlugin_predictor_historyWrite_payload_data_last2Bytes; wire [31:0] IBusSimplePlugin_predictor_historyWrite_payload_data_target; reg IBusSimplePlugin_predictor_writeLast_valid; reg [9:0] IBusSimplePlugin_predictor_writeLast_payload_address; reg [19:0] IBusSimplePlugin_predictor_writeLast_payload_data_source; reg [1:0] IBusSimplePlugin_predictor_writeLast_payload_data_branchWish; reg IBusSimplePlugin_predictor_writeLast_payload_data_last2Bytes; reg [31:0] IBusSimplePlugin_predictor_writeLast_payload_data_target; wire [29:0] _zz_IBusSimplePlugin_predictor_buffer_line_source; wire [19:0] IBusSimplePlugin_predictor_buffer_line_source; wire [1:0] IBusSimplePlugin_predictor_buffer_line_branchWish; wire IBusSimplePlugin_predictor_buffer_line_last2Bytes; wire [31:0] IBusSimplePlugin_predictor_buffer_line_target; wire [54:0] _zz_IBusSimplePlugin_predictor_buffer_line_source_1; reg IBusSimplePlugin_predictor_buffer_pcCorrected; wire IBusSimplePlugin_predictor_buffer_hazard; reg [19:0] IBusSimplePlugin_predictor_line_source; reg [1:0] IBusSimplePlugin_predictor_line_branchWish; reg IBusSimplePlugin_predictor_line_last2Bytes; reg [31:0] IBusSimplePlugin_predictor_line_target; reg IBusSimplePlugin_predictor_buffer_hazard_regNextWhen; wire IBusSimplePlugin_predictor_hazard; reg IBusSimplePlugin_predictor_hit; wire when_Fetcher_l550; wire IBusSimplePlugin_predictor_fetchContext_hazard; wire IBusSimplePlugin_predictor_fetchContext_hit; wire [19:0] IBusSimplePlugin_predictor_fetchContext_line_source; wire [1:0] IBusSimplePlugin_predictor_fetchContext_line_branchWish; wire IBusSimplePlugin_predictor_fetchContext_line_last2Bytes; wire [31:0] IBusSimplePlugin_predictor_fetchContext_line_target; wire IBusSimplePlugin_predictor_iBusRspContextOutput_hazard; reg IBusSimplePlugin_predictor_iBusRspContextOutput_hit; wire [19:0] IBusSimplePlugin_predictor_iBusRspContextOutput_line_source; wire [1:0] IBusSimplePlugin_predictor_iBusRspContextOutput_line_branchWish; wire IBusSimplePlugin_predictor_iBusRspContextOutput_line_last2Bytes; wire [31:0] IBusSimplePlugin_predictor_iBusRspContextOutput_line_target; reg IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_hazard; reg IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_hit; reg [19:0] IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_source; reg [1:0] IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_branchWish; reg IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_last2Bytes; reg [31:0] IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_target; wire IBusSimplePlugin_predictor_injectorContext_hazard; wire IBusSimplePlugin_predictor_injectorContext_hit; wire [19:0] IBusSimplePlugin_predictor_injectorContext_line_source; wire [1:0] IBusSimplePlugin_predictor_injectorContext_line_branchWish; wire IBusSimplePlugin_predictor_injectorContext_line_last2Bytes; wire [31:0] IBusSimplePlugin_predictor_injectorContext_line_target; wire when_Fetcher_l596; wire IBusSimplePlugin_predictor_compressor_predictionBranch; wire IBusSimplePlugin_predictor_compressor_unalignedWordIssue; wire when_Fetcher_l611; wire IBusSimplePlugin_injector_decodeInput_fire; wire IBusSimplePlugin_decompressor_output_fire_1; wire when_Fetcher_l617; wire IBusSimplePlugin_cmd_valid; wire IBusSimplePlugin_cmd_ready; wire [31:0] IBusSimplePlugin_cmd_payload_pc; wire IBusSimplePlugin_pending_inc; wire IBusSimplePlugin_pending_dec; reg [2:0] IBusSimplePlugin_pending_value; wire [2:0] IBusSimplePlugin_pending_next; wire IBusSimplePlugin_cmdFork_canEmit; wire when_IBusSimplePlugin_l305; wire IBusSimplePlugin_cmd_fire; wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid; wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready; wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; wire iBus_rsp_toStream_valid; wire iBus_rsp_toStream_ready; wire iBus_rsp_toStream_payload_error; wire [31:0] iBus_rsp_toStream_payload_inst; wire IBusSimplePlugin_rspJoin_rspBuffer_flush; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire; wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; wire when_IBusSimplePlugin_l376; wire IBusSimplePlugin_rspJoin_join_valid; wire IBusSimplePlugin_rspJoin_join_ready; wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; wire IBusSimplePlugin_rspJoin_join_payload_isRvc; wire IBusSimplePlugin_rspJoin_exceptionDetected; wire IBusSimplePlugin_rspJoin_join_fire; wire IBusSimplePlugin_rspJoin_join_fire_1; wire _zz_IBusSimplePlugin_iBusRsp_output_valid; wire _zz_dBus_cmd_valid; reg execute_DBusSimplePlugin_skipCmd; reg [31:0] _zz_dBus_cmd_payload_data; wire when_DBusSimplePlugin_l428; reg [3:0] _zz_execute_DBusSimplePlugin_formalMask; wire [3:0] execute_DBusSimplePlugin_formalMask; wire when_DBusSimplePlugin_l482; wire when_DBusSimplePlugin_l515; reg [31:0] writeBack_DBusSimplePlugin_rspShifted; wire [1:0] switch_Misc_l211_2; wire _zz_writeBack_DBusSimplePlugin_rspFormated; reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_1; wire _zz_writeBack_DBusSimplePlugin_rspFormated_2; reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_3; reg [31:0] writeBack_DBusSimplePlugin_rspFormated; wire when_DBusSimplePlugin_l558; wire [22:0] _zz_decode_BRANCH_CTRL_2; wire _zz_decode_BRANCH_CTRL_3; wire _zz_decode_BRANCH_CTRL_4; wire _zz_decode_BRANCH_CTRL_5; wire _zz_decode_BRANCH_CTRL_6; wire [1:0] _zz_decode_SRC1_CTRL_2; wire [1:0] _zz_decode_ALU_CTRL_2; wire [1:0] _zz_decode_SRC2_CTRL_2; wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2; wire [1:0] _zz_decode_SHIFT_CTRL_2; wire [1:0] _zz_decode_BRANCH_CTRL_7; wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; wire [31:0] decode_RegFilePlugin_rs2Data; reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; reg _zz_3; reg [31:0] execute_IntAluPlugin_bitwise; reg [31:0] _zz_execute_REGFILE_WRITE_DATA; reg [31:0] _zz_decode_SRC1_1; wire _zz_decode_SRC2_2; reg [19:0] _zz_decode_SRC2_3; wire _zz_decode_SRC2_4; reg [19:0] _zz_decode_SRC2_5; reg [31:0] _zz_decode_SRC2_6; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; reg [31:0] _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1; reg HazardSimplePlugin_src0Hazard; reg HazardSimplePlugin_src1Hazard; wire HazardSimplePlugin_writeBackWrites_valid; wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; reg HazardSimplePlugin_writeBackBuffer_valid; reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; wire HazardSimplePlugin_addr0Match; wire HazardSimplePlugin_addr1Match; wire when_HazardSimplePlugin_l59; wire when_HazardSimplePlugin_l62; wire when_HazardSimplePlugin_l57; wire when_HazardSimplePlugin_l58; wire when_HazardSimplePlugin_l59_1; wire when_HazardSimplePlugin_l62_1; wire when_HazardSimplePlugin_l57_1; wire when_HazardSimplePlugin_l58_1; wire when_HazardSimplePlugin_l59_2; wire when_HazardSimplePlugin_l62_2; wire when_HazardSimplePlugin_l57_2; wire when_HazardSimplePlugin_l58_2; wire when_HazardSimplePlugin_l105; wire when_HazardSimplePlugin_l108; wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; wire [2:0] switch_Misc_l211_3; reg _zz_execute_BRANCH_DO; reg _zz_execute_BRANCH_DO_1; wire [31:0] execute_BranchPlugin_branch_src1; wire _zz_execute_BRANCH_SRC22; reg [10:0] _zz_execute_BRANCH_SRC22_1; wire _zz_execute_BRANCH_SRC22_2; reg [19:0] _zz_execute_BRANCH_SRC22_3; wire _zz_execute_BRANCH_SRC22_4; reg [18:0] _zz_execute_BRANCH_SRC22_5; reg [31:0] _zz_execute_BRANCH_SRC22_6; wire [31:0] execute_BranchPlugin_branchAdder; wire memory_BranchPlugin_predictionMissmatch; wire when_Pipeline_l124; reg decode_to_execute_FORMAL_HALT; wire when_Pipeline_l124_1; reg execute_to_memory_FORMAL_HALT; wire when_Pipeline_l124_2; reg memory_to_writeBack_FORMAL_HALT; wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_PC; wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_PC; wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_PC; wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_INSTRUCTION; wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_INSTRUCTION; wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_INSTRUCTION; wire when_Pipeline_l124_9; reg decode_to_execute_IS_RVC; wire when_Pipeline_l124_10; reg execute_to_memory_IS_RVC; wire when_Pipeline_l124_11; reg [31:0] decode_to_execute_FORMAL_INSTRUCTION; wire when_Pipeline_l124_12; reg [31:0] execute_to_memory_FORMAL_INSTRUCTION; wire when_Pipeline_l124_13; reg [31:0] memory_to_writeBack_FORMAL_INSTRUCTION; wire when_Pipeline_l124_14; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; wire when_Pipeline_l124_15; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; wire when_Pipeline_l124_16; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; wire when_Pipeline_l124_17; reg decode_to_execute_PREDICTION_CONTEXT_hazard; reg decode_to_execute_PREDICTION_CONTEXT_hit; reg [19:0] decode_to_execute_PREDICTION_CONTEXT_line_source; reg [1:0] decode_to_execute_PREDICTION_CONTEXT_line_branchWish; reg decode_to_execute_PREDICTION_CONTEXT_line_last2Bytes; reg [31:0] decode_to_execute_PREDICTION_CONTEXT_line_target; wire when_Pipeline_l124_18; reg execute_to_memory_PREDICTION_CONTEXT_hazard; reg execute_to_memory_PREDICTION_CONTEXT_hit; reg [19:0] execute_to_memory_PREDICTION_CONTEXT_line_source; reg [1:0] execute_to_memory_PREDICTION_CONTEXT_line_branchWish; reg execute_to_memory_PREDICTION_CONTEXT_line_last2Bytes; reg [31:0] execute_to_memory_PREDICTION_CONTEXT_line_target; wire when_Pipeline_l124_19; reg decode_to_execute_SRC_USE_SUB_LESS; wire when_Pipeline_l124_20; reg decode_to_execute_MEMORY_ENABLE; wire when_Pipeline_l124_21; reg execute_to_memory_MEMORY_ENABLE; wire when_Pipeline_l124_22; reg memory_to_writeBack_MEMORY_ENABLE; wire when_Pipeline_l124_23; reg decode_to_execute_RS1_USE; wire when_Pipeline_l124_24; reg execute_to_memory_RS1_USE; wire when_Pipeline_l124_25; reg memory_to_writeBack_RS1_USE; wire when_Pipeline_l124_26; reg [1:0] decode_to_execute_ALU_CTRL; wire when_Pipeline_l124_27; reg decode_to_execute_REGFILE_WRITE_VALID; wire when_Pipeline_l124_28; reg execute_to_memory_REGFILE_WRITE_VALID; wire when_Pipeline_l124_29; reg memory_to_writeBack_REGFILE_WRITE_VALID; wire when_Pipeline_l124_30; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; wire when_Pipeline_l124_31; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; wire when_Pipeline_l124_32; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; wire when_Pipeline_l124_33; reg decode_to_execute_MEMORY_STORE; wire when_Pipeline_l124_34; reg execute_to_memory_MEMORY_STORE; wire when_Pipeline_l124_35; reg decode_to_execute_RS2_USE; wire when_Pipeline_l124_36; reg execute_to_memory_RS2_USE; wire when_Pipeline_l124_37; reg memory_to_writeBack_RS2_USE; wire when_Pipeline_l124_38; reg decode_to_execute_SRC_LESS_UNSIGNED; wire when_Pipeline_l124_39; reg [1:0] decode_to_execute_ALU_BITWISE_CTRL; wire when_Pipeline_l124_40; reg [1:0] decode_to_execute_SHIFT_CTRL; wire when_Pipeline_l124_41; reg [1:0] execute_to_memory_SHIFT_CTRL; wire when_Pipeline_l124_42; reg [1:0] decode_to_execute_BRANCH_CTRL; wire when_Pipeline_l124_43; reg [31:0] decode_to_execute_RS1; wire when_Pipeline_l124_44; reg [31:0] execute_to_memory_RS1; wire when_Pipeline_l124_45; reg [31:0] memory_to_writeBack_RS1; wire when_Pipeline_l124_46; reg [31:0] decode_to_execute_RS2; wire when_Pipeline_l124_47; reg [31:0] execute_to_memory_RS2; wire when_Pipeline_l124_48; reg [31:0] memory_to_writeBack_RS2; wire when_Pipeline_l124_49; reg decode_to_execute_SRC2_FORCE_ZERO; wire when_Pipeline_l124_50; reg [31:0] decode_to_execute_SRC1; wire when_Pipeline_l124_51; reg [31:0] decode_to_execute_SRC2; wire when_Pipeline_l124_52; reg execute_to_memory_ALIGNEMENT_FAULT; wire when_Pipeline_l124_53; reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; wire when_Pipeline_l124_54; reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; wire when_Pipeline_l124_55; reg [31:0] execute_to_memory_FORMAL_MEM_ADDR; wire when_Pipeline_l124_56; reg [31:0] memory_to_writeBack_FORMAL_MEM_ADDR; wire when_Pipeline_l124_57; reg [3:0] execute_to_memory_FORMAL_MEM_WMASK; wire when_Pipeline_l124_58; reg [3:0] memory_to_writeBack_FORMAL_MEM_WMASK; wire when_Pipeline_l124_59; reg [3:0] execute_to_memory_FORMAL_MEM_RMASK; wire when_Pipeline_l124_60; reg [3:0] memory_to_writeBack_FORMAL_MEM_RMASK; wire when_Pipeline_l124_61; reg [31:0] execute_to_memory_FORMAL_MEM_WDATA; wire when_Pipeline_l124_62; reg [31:0] memory_to_writeBack_FORMAL_MEM_WDATA; wire when_Pipeline_l124_63; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; wire when_Pipeline_l124_64; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; wire when_Pipeline_l124_65; reg [31:0] execute_to_memory_SHIFT_RIGHT; wire when_Pipeline_l124_66; reg execute_to_memory_BRANCH_DO; wire when_Pipeline_l124_67; reg [31:0] execute_to_memory_BRANCH_CALC; wire when_Pipeline_l124_68; reg [31:0] execute_to_memory_NEXT_PC2; wire when_Pipeline_l124_69; reg execute_to_memory_TARGET_MISSMATCH2; wire when_Pipeline_l124_70; reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; wire when_Pipeline_l151; wire when_Pipeline_l154; wire when_Pipeline_l151_1; wire when_Pipeline_l154_1; wire when_Pipeline_l151_2; wire when_Pipeline_l154_2; `ifndef SYNTHESIS reg [31:0] decode_BRANCH_CTRL_string; reg [31:0] _zz_decode_BRANCH_CTRL_string; reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; reg [71:0] _zz_decode_SHIFT_CTRL_string; reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; reg [63:0] _zz_decode_ALU_CTRL_string; reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [31:0] execute_BRANCH_CTRL_string; reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] decode_SRC2_CTRL_string; reg [23:0] _zz_decode_SRC2_CTRL_string; reg [95:0] decode_SRC1_CTRL_string; reg [95:0] _zz_decode_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; reg [31:0] _zz_decode_BRANCH_CTRL_1_string; reg [71:0] _zz_decode_SHIFT_CTRL_1_string; reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; reg [23:0] _zz_decode_SRC2_CTRL_1_string; reg [63:0] _zz_decode_ALU_CTRL_1_string; reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [95:0] _zz_decode_SRC1_CTRL_2_string; reg [63:0] _zz_decode_ALU_CTRL_2_string; reg [23:0] _zz_decode_SRC2_CTRL_2_string; reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; reg [71:0] _zz_decode_SHIFT_CTRL_2_string; reg [31:0] _zz_decode_BRANCH_CTRL_7_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; reg [71:0] decode_to_execute_SHIFT_CTRL_string; reg [71:0] execute_to_memory_SHIFT_CTRL_string; reg [31:0] decode_to_execute_BRANCH_CTRL_string; `endif reg [54:0] IBusSimplePlugin_predictor_history [0:1023]; reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; assign _zz_execute_NEXT_PC2_1 = (execute_IS_RVC ? 3'b010 : 3'b100); assign _zz_execute_NEXT_PC2 = {29'd0, _zz_execute_NEXT_PC2_1}; assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; assign _zz_IBusSimplePlugin_fetchPc_pc_1 = {IBusSimplePlugin_fetchPc_inc,2'b00}; assign _zz_IBusSimplePlugin_fetchPc_pc = {29'd0, _zz_IBusSimplePlugin_fetchPc_pc_1}; assign _zz_IBusSimplePlugin_decodePc_pcPlus_1 = (decode_IS_RVC ? 3'b010 : 3'b100); assign _zz_IBusSimplePlugin_decodePc_pcPlus = {29'd0, _zz_IBusSimplePlugin_decodePc_pcPlus_1}; assign _zz_IBusSimplePlugin_decompressor_decompressed_27 = {{_zz_IBusSimplePlugin_decompressor_decompressed_10,_zz_IBusSimplePlugin_decompressor_decompressed[6 : 2]},12'h0}; assign _zz_IBusSimplePlugin_decompressor_decompressed_34 = {{{4'b0000,_zz_IBusSimplePlugin_decompressor_decompressed[8 : 7]},_zz_IBusSimplePlugin_decompressor_decompressed[12 : 9]},2'b00}; assign _zz_IBusSimplePlugin_decompressor_decompressed_35 = {{{4'b0000,_zz_IBusSimplePlugin_decompressor_decompressed[8 : 7]},_zz_IBusSimplePlugin_decompressor_decompressed[12 : 9]},2'b00}; assign _zz__zz_decode_FORMAL_PC_NEXT_1 = (decode_IS_RVC ? 3'b010 : 3'b100); assign _zz__zz_decode_FORMAL_PC_NEXT = {29'd0, _zz__zz_decode_FORMAL_PC_NEXT_1}; assign _zz__zz_IBusSimplePlugin_predictor_buffer_line_source_1 = _zz_IBusSimplePlugin_predictor_buffer_line_source[9:0]; assign _zz_IBusSimplePlugin_predictor_buffer_hazard_1 = (IBusSimplePlugin_iBusRsp_stages_1_input_payload >>> 2); assign _zz_IBusSimplePlugin_predictor_buffer_hazard = _zz_IBusSimplePlugin_predictor_buffer_hazard_1[9:0]; assign _zz_IBusSimplePlugin_predictor_hit = (IBusSimplePlugin_iBusRsp_stages_1_input_payload >>> 12); assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish = (memory_PREDICTION_CONTEXT_line_branchWish + _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_1); assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_2 = (memory_PREDICTION_CONTEXT_line_branchWish == 2'b10); assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_1 = {1'd0, _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_2}; assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_4 = (memory_PREDICTION_CONTEXT_line_branchWish == 2'b01); assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_3 = {1'd0, _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_4}; assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_5 = (memory_PREDICTION_CONTEXT_line_branchWish - _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_6); assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_7 = memory_PREDICTION_CONTEXT_line_branchWish[1]; assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_6 = {1'd0, _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_7}; assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_9 = (! memory_PREDICTION_CONTEXT_line_branchWish[1]); assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_8 = {1'd0, _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_9}; assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_address = (IBusSimplePlugin_iBusRsp_stages_1_input_payload >>> 2); assign _zz_IBusSimplePlugin_pending_next = (IBusSimplePlugin_pending_value + _zz_IBusSimplePlugin_pending_next_1); assign _zz_IBusSimplePlugin_pending_next_2 = IBusSimplePlugin_pending_inc; assign _zz_IBusSimplePlugin_pending_next_1 = {2'd0, _zz_IBusSimplePlugin_pending_next_2}; assign _zz_IBusSimplePlugin_pending_next_4 = IBusSimplePlugin_pending_dec; assign _zz_IBusSimplePlugin_pending_next_3 = {2'd0, _zz_IBusSimplePlugin_pending_next_4}; assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter = {2'd0, _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1}; assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3 = IBusSimplePlugin_pending_dec; assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2 = {2'd0, _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3}; assign _zz_DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 3'b110 : 3'b100); assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; assign _zz__zz_decode_SRC1_1 = (decode_IS_RVC ? 3'b010 : 3'b100); assign _zz__zz_decode_SRC1_1_1 = decode_INSTRUCTION[19 : 15]; assign _zz__zz_decode_SRC2_4 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; assign _zz__zz_execute_BRANCH_SRC22 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; assign _zz__zz_execute_BRANCH_SRC22_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; assign _zz_IBusSimplePlugin_predictor_history_port = {IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_target,{IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_last2Bytes,{IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_branchWish,IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_source}}}; assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000407f; assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002013; assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023); assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003); assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000505f) == 32'h00000003),{((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h0000000f),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000607f; assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'hfe00007f); assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000033; assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013); assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033),((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033)}; assign _zz_IBusSimplePlugin_decompressor_decompressed_28 = (_zz_IBusSimplePlugin_decompressor_decompressed[11 : 10] == 2'b01); assign _zz_IBusSimplePlugin_decompressor_decompressed_29 = ((_zz_IBusSimplePlugin_decompressor_decompressed[11 : 10] == 2'b11) && (_zz_IBusSimplePlugin_decompressor_decompressed[6 : 5] == 2'b00)); assign _zz_IBusSimplePlugin_decompressor_decompressed_30 = 7'h0; assign _zz_IBusSimplePlugin_decompressor_decompressed_31 = _zz_IBusSimplePlugin_decompressor_decompressed[6 : 2]; assign _zz_IBusSimplePlugin_decompressor_decompressed_32 = _zz_IBusSimplePlugin_decompressor_decompressed[12]; assign _zz_IBusSimplePlugin_decompressor_decompressed_33 = _zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]; assign _zz__zz_decode_BRANCH_CTRL_2 = (decode_INSTRUCTION & 32'h0000001c); assign _zz__zz_decode_BRANCH_CTRL_2_1 = 32'h00000004; assign _zz__zz_decode_BRANCH_CTRL_2_2 = (decode_INSTRUCTION & 32'h00000048); assign _zz__zz_decode_BRANCH_CTRL_2_3 = 32'h00000040; assign _zz__zz_decode_BRANCH_CTRL_2_4 = ((decode_INSTRUCTION & 32'h00007014) == 32'h00005010); assign _zz__zz_decode_BRANCH_CTRL_2_5 = {((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_6) == 32'h40001010),((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_7) == 32'h00001010)}; assign _zz__zz_decode_BRANCH_CTRL_2_8 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_9) == 32'h00000024)); assign _zz__zz_decode_BRANCH_CTRL_2_10 = (|(_zz__zz_decode_BRANCH_CTRL_2_11 == _zz__zz_decode_BRANCH_CTRL_2_12)); assign _zz__zz_decode_BRANCH_CTRL_2_13 = {(|_zz__zz_decode_BRANCH_CTRL_2_14),{(|_zz__zz_decode_BRANCH_CTRL_2_15),{_zz__zz_decode_BRANCH_CTRL_2_18,{_zz__zz_decode_BRANCH_CTRL_2_20,_zz__zz_decode_BRANCH_CTRL_2_22}}}}; assign _zz__zz_decode_BRANCH_CTRL_2_6 = 32'h40003014; assign _zz__zz_decode_BRANCH_CTRL_2_7 = 32'h00007014; assign _zz__zz_decode_BRANCH_CTRL_2_9 = 32'h00000064; assign _zz__zz_decode_BRANCH_CTRL_2_11 = (decode_INSTRUCTION & 32'h00001000); assign _zz__zz_decode_BRANCH_CTRL_2_12 = 32'h00001000; assign _zz__zz_decode_BRANCH_CTRL_2_14 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); assign _zz__zz_decode_BRANCH_CTRL_2_15 = {((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_16) == 32'h00002000),((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_17) == 32'h00001000)}; assign _zz__zz_decode_BRANCH_CTRL_2_18 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_19) == 32'h00000020)); assign _zz__zz_decode_BRANCH_CTRL_2_20 = (|{_zz__zz_decode_BRANCH_CTRL_2_21,_zz_decode_BRANCH_CTRL_3}); assign _zz__zz_decode_BRANCH_CTRL_2_22 = {(|_zz__zz_decode_BRANCH_CTRL_2_23),{(|_zz__zz_decode_BRANCH_CTRL_2_24),{_zz__zz_decode_BRANCH_CTRL_2_25,{_zz__zz_decode_BRANCH_CTRL_2_28,_zz__zz_decode_BRANCH_CTRL_2_35}}}}; assign _zz__zz_decode_BRANCH_CTRL_2_16 = 32'h00002010; assign _zz__zz_decode_BRANCH_CTRL_2_17 = 32'h00005000; assign _zz__zz_decode_BRANCH_CTRL_2_19 = 32'h00000024; assign _zz__zz_decode_BRANCH_CTRL_2_21 = ((decode_INSTRUCTION & 32'h00000040) == 32'h00000040); assign _zz__zz_decode_BRANCH_CTRL_2_23 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); assign _zz__zz_decode_BRANCH_CTRL_2_24 = _zz_decode_BRANCH_CTRL_6; assign _zz__zz_decode_BRANCH_CTRL_2_25 = (|{_zz_decode_BRANCH_CTRL_4,{_zz__zz_decode_BRANCH_CTRL_2_26,_zz__zz_decode_BRANCH_CTRL_2_27}}); assign _zz__zz_decode_BRANCH_CTRL_2_28 = (|{_zz_decode_BRANCH_CTRL_6,{_zz__zz_decode_BRANCH_CTRL_2_29,_zz__zz_decode_BRANCH_CTRL_2_30}}); assign _zz__zz_decode_BRANCH_CTRL_2_35 = {(|{_zz__zz_decode_BRANCH_CTRL_2_36,_zz__zz_decode_BRANCH_CTRL_2_37}),{(|_zz__zz_decode_BRANCH_CTRL_2_39),{_zz__zz_decode_BRANCH_CTRL_2_42,{_zz__zz_decode_BRANCH_CTRL_2_45,_zz__zz_decode_BRANCH_CTRL_2_47}}}}; assign _zz__zz_decode_BRANCH_CTRL_2_26 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002010); assign _zz__zz_decode_BRANCH_CTRL_2_27 = ((decode_INSTRUCTION & 32'h00001010) == 32'h00000010); assign _zz__zz_decode_BRANCH_CTRL_2_29 = _zz_decode_BRANCH_CTRL_5; assign _zz__zz_decode_BRANCH_CTRL_2_30 = {(_zz__zz_decode_BRANCH_CTRL_2_31 == _zz__zz_decode_BRANCH_CTRL_2_32),(_zz__zz_decode_BRANCH_CTRL_2_33 == _zz__zz_decode_BRANCH_CTRL_2_34)}; assign _zz__zz_decode_BRANCH_CTRL_2_36 = _zz_decode_BRANCH_CTRL_4; assign _zz__zz_decode_BRANCH_CTRL_2_37 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_38) == 32'h00000020); assign _zz__zz_decode_BRANCH_CTRL_2_39 = {_zz_decode_BRANCH_CTRL_4,(_zz__zz_decode_BRANCH_CTRL_2_40 == _zz__zz_decode_BRANCH_CTRL_2_41)}; assign _zz__zz_decode_BRANCH_CTRL_2_42 = (|(_zz__zz_decode_BRANCH_CTRL_2_43 == _zz__zz_decode_BRANCH_CTRL_2_44)); assign _zz__zz_decode_BRANCH_CTRL_2_45 = (|_zz__zz_decode_BRANCH_CTRL_2_46); assign _zz__zz_decode_BRANCH_CTRL_2_47 = {(|_zz__zz_decode_BRANCH_CTRL_2_48),{_zz__zz_decode_BRANCH_CTRL_2_50,{_zz__zz_decode_BRANCH_CTRL_2_52,_zz__zz_decode_BRANCH_CTRL_2_56}}}; assign _zz__zz_decode_BRANCH_CTRL_2_31 = (decode_INSTRUCTION & 32'h0000000c); assign _zz__zz_decode_BRANCH_CTRL_2_32 = 32'h00000004; assign _zz__zz_decode_BRANCH_CTRL_2_33 = (decode_INSTRUCTION & 32'h00000028); assign _zz__zz_decode_BRANCH_CTRL_2_34 = 32'h0; assign _zz__zz_decode_BRANCH_CTRL_2_38 = 32'h00000070; assign _zz__zz_decode_BRANCH_CTRL_2_40 = (decode_INSTRUCTION & 32'h00000020); assign _zz__zz_decode_BRANCH_CTRL_2_41 = 32'h0; assign _zz__zz_decode_BRANCH_CTRL_2_43 = (decode_INSTRUCTION & 32'h00004014); assign _zz__zz_decode_BRANCH_CTRL_2_44 = 32'h00004010; assign _zz__zz_decode_BRANCH_CTRL_2_46 = ((decode_INSTRUCTION & 32'h00006014) == 32'h00002010); assign _zz__zz_decode_BRANCH_CTRL_2_48 = {((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_49) == 32'h0),_zz_decode_BRANCH_CTRL_3}; assign _zz__zz_decode_BRANCH_CTRL_2_50 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_51) == 32'h0)); assign _zz__zz_decode_BRANCH_CTRL_2_52 = (|{_zz__zz_decode_BRANCH_CTRL_2_53,{_zz__zz_decode_BRANCH_CTRL_2_54,_zz__zz_decode_BRANCH_CTRL_2_55}}); assign _zz__zz_decode_BRANCH_CTRL_2_56 = {(|_zz__zz_decode_BRANCH_CTRL_2_57),(|_zz__zz_decode_BRANCH_CTRL_2_58)}; assign _zz__zz_decode_BRANCH_CTRL_2_49 = 32'h00000004; assign _zz__zz_decode_BRANCH_CTRL_2_51 = 32'h00000058; assign _zz__zz_decode_BRANCH_CTRL_2_53 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); assign _zz__zz_decode_BRANCH_CTRL_2_54 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); assign _zz__zz_decode_BRANCH_CTRL_2_55 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); assign _zz__zz_decode_BRANCH_CTRL_2_57 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); assign _zz__zz_decode_BRANCH_CTRL_2_58 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); always @(posedge clk) begin if(_zz_2) begin IBusSimplePlugin_predictor_history[IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_address] <= _zz_IBusSimplePlugin_predictor_history_port; end end always @(posedge clk) begin if(IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin _zz_IBusSimplePlugin_predictor_history_port1 <= IBusSimplePlugin_predictor_history[_zz__zz_IBusSimplePlugin_predictor_buffer_line_source_1]; end end always @(posedge clk) begin if(_zz_decode_RegFilePlugin_rs1Data) begin _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @(posedge clk) begin if(_zz_decode_RegFilePlugin_rs2Data) begin _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @(posedge clk) begin if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( .io_push_valid (iBus_rsp_toStream_valid ), //i .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o .io_push_payload_error (iBus_rsp_toStream_payload_error ), //i .io_push_payload_inst (iBus_rsp_toStream_payload_inst[31:0] ), //i .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o .io_pop_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready ), //i .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o .io_flush (1'b0 ), //i .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o .clk (clk ), //i .reset (reset ) //i ); `ifndef SYNTHESIS always @(*) begin case(decode_BRANCH_CTRL) BranchCtrlEnum_INC : decode_BRANCH_CTRL_string = "INC "; BranchCtrlEnum_B : decode_BRANCH_CTRL_string = "B "; BranchCtrlEnum_JAL : decode_BRANCH_CTRL_string = "JAL "; BranchCtrlEnum_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(_zz_decode_BRANCH_CTRL) BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_string = "INC "; BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_string = "B "; BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(_zz_decode_to_execute_BRANCH_CTRL) BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(_zz_decode_to_execute_BRANCH_CTRL_1) BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin case(_zz_execute_to_memory_SHIFT_CTRL) ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(_zz_execute_to_memory_SHIFT_CTRL_1) ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) ShiftCtrlEnum_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; ShiftCtrlEnum_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; ShiftCtrlEnum_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; ShiftCtrlEnum_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(_zz_decode_SHIFT_CTRL) ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(_zz_decode_to_execute_SHIFT_CTRL) ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(_zz_decode_to_execute_SHIFT_CTRL_1) ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) AluBitwiseCtrlEnum_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; AluBitwiseCtrlEnum_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; AluBitwiseCtrlEnum_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(_zz_decode_ALU_BITWISE_CTRL) AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(_zz_decode_to_execute_ALU_BITWISE_CTRL) AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ALU_CTRL) AluCtrlEnum_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; AluCtrlEnum_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; AluCtrlEnum_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(_zz_decode_ALU_CTRL) AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(_zz_decode_to_execute_ALU_CTRL) AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(_zz_decode_to_execute_ALU_CTRL_1) AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) BranchCtrlEnum_INC : execute_BRANCH_CTRL_string = "INC "; BranchCtrlEnum_B : execute_BRANCH_CTRL_string = "B "; BranchCtrlEnum_JAL : execute_BRANCH_CTRL_string = "JAL "; BranchCtrlEnum_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(_zz_execute_BRANCH_CTRL) BranchCtrlEnum_INC : _zz_execute_BRANCH_CTRL_string = "INC "; BranchCtrlEnum_B : _zz_execute_BRANCH_CTRL_string = "B "; BranchCtrlEnum_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; BranchCtrlEnum_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) ShiftCtrlEnum_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; ShiftCtrlEnum_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; ShiftCtrlEnum_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; ShiftCtrlEnum_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(_zz_memory_SHIFT_CTRL) ShiftCtrlEnum_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; ShiftCtrlEnum_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; ShiftCtrlEnum_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; ShiftCtrlEnum_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) ShiftCtrlEnum_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; ShiftCtrlEnum_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; ShiftCtrlEnum_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; ShiftCtrlEnum_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(_zz_execute_SHIFT_CTRL) ShiftCtrlEnum_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; ShiftCtrlEnum_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; ShiftCtrlEnum_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; ShiftCtrlEnum_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_SRC2_CTRL) Src2CtrlEnum_RS : decode_SRC2_CTRL_string = "RS "; Src2CtrlEnum_IMI : decode_SRC2_CTRL_string = "IMI"; Src2CtrlEnum_IMS : decode_SRC2_CTRL_string = "IMS"; Src2CtrlEnum_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(_zz_decode_SRC2_CTRL) Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_string = "RS "; Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_string = "PC "; default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_SRC1_CTRL) Src1CtrlEnum_RS : decode_SRC1_CTRL_string = "RS "; Src1CtrlEnum_IMU : decode_SRC1_CTRL_string = "IMU "; Src1CtrlEnum_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; Src1CtrlEnum_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(_zz_decode_SRC1_CTRL) Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_string = "RS "; Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) AluCtrlEnum_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; AluCtrlEnum_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; AluCtrlEnum_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(_zz_execute_ALU_CTRL) AluCtrlEnum_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; AluCtrlEnum_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; AluCtrlEnum_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) AluBitwiseCtrlEnum_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; AluBitwiseCtrlEnum_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; AluBitwiseCtrlEnum_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(_zz_execute_ALU_BITWISE_CTRL) AluBitwiseCtrlEnum_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; AluBitwiseCtrlEnum_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; AluBitwiseCtrlEnum_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(_zz_decode_BRANCH_CTRL_1) BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_1_string = "B "; BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin case(_zz_decode_SHIFT_CTRL_1) ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(_zz_decode_ALU_BITWISE_CTRL_1) AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(_zz_decode_SRC2_CTRL_1) Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(_zz_decode_ALU_CTRL_1) AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(_zz_decode_SRC1_CTRL_1) Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(_zz_decode_SRC1_CTRL_2) Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin case(_zz_decode_ALU_CTRL_2) AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin case(_zz_decode_SRC2_CTRL_2) Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin case(_zz_decode_ALU_BITWISE_CTRL_2) AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin case(_zz_decode_SHIFT_CTRL_2) ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin case(_zz_decode_BRANCH_CTRL_7) BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_7_string = "INC "; BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_7_string = "B "; BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_7_string = "JAL "; BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_7_string = "JALR"; default : _zz_decode_BRANCH_CTRL_7_string = "????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) AluCtrlEnum_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; AluCtrlEnum_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; AluCtrlEnum_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) AluBitwiseCtrlEnum_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; AluBitwiseCtrlEnum_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; AluBitwiseCtrlEnum_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) ShiftCtrlEnum_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; ShiftCtrlEnum_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; ShiftCtrlEnum_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; ShiftCtrlEnum_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) ShiftCtrlEnum_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; ShiftCtrlEnum_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; ShiftCtrlEnum_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; ShiftCtrlEnum_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) BranchCtrlEnum_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; BranchCtrlEnum_B : decode_to_execute_BRANCH_CTRL_string = "B "; BranchCtrlEnum_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; BranchCtrlEnum_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end `endif assign writeBack_FORMAL_MEM_RDATA = writeBack_MEMORY_READ_DATA; assign memory_MEMORY_READ_DATA = dBus_rsp_data; assign execute_TARGET_MISSMATCH2 = (decode_PC != execute_BRANCH_CALC); assign execute_NEXT_PC2 = (execute_PC + _zz_execute_NEXT_PC2); assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; assign writeBack_FORMAL_MEM_WDATA = memory_to_writeBack_FORMAL_MEM_WDATA; assign memory_FORMAL_MEM_WDATA = execute_to_memory_FORMAL_MEM_WDATA; assign execute_FORMAL_MEM_WDATA = dBus_cmd_payload_data; assign writeBack_FORMAL_MEM_RMASK = memory_to_writeBack_FORMAL_MEM_RMASK; assign memory_FORMAL_MEM_RMASK = execute_to_memory_FORMAL_MEM_RMASK; assign execute_FORMAL_MEM_RMASK = ((dBus_cmd_valid && (! dBus_cmd_payload_wr)) ? execute_DBusSimplePlugin_formalMask : 4'b0000); assign writeBack_FORMAL_MEM_WMASK = memory_to_writeBack_FORMAL_MEM_WMASK; assign memory_FORMAL_MEM_WMASK = execute_to_memory_FORMAL_MEM_WMASK; assign execute_FORMAL_MEM_WMASK = ((dBus_cmd_valid && dBus_cmd_payload_wr) ? execute_DBusSimplePlugin_formalMask : 4'b0000); assign writeBack_FORMAL_MEM_ADDR = memory_to_writeBack_FORMAL_MEM_ADDR; assign memory_FORMAL_MEM_ADDR = execute_to_memory_FORMAL_MEM_ADDR; assign execute_FORMAL_MEM_ADDR = (dBus_cmd_payload_address & 32'hfffffffc); assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; assign decode_SRC2 = _zz_decode_SRC2_6; assign decode_SRC1 = _zz_decode_SRC1_1; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); assign writeBack_RS2 = memory_to_writeBack_RS2; assign memory_RS2 = execute_to_memory_RS2; assign decode_RS2 = decode_RegFilePlugin_rs2Data; assign writeBack_RS1 = memory_to_writeBack_RS1; assign memory_RS1 = execute_to_memory_RS1; assign decode_RS1 = decode_RegFilePlugin_rs1Data; assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; assign decode_SRC_LESS_UNSIGNED = _zz_decode_BRANCH_CTRL_2[15]; assign writeBack_RS2_USE = memory_to_writeBack_RS2_USE; assign memory_RS2_USE = execute_to_memory_RS2_USE; assign execute_RS2_USE = decode_to_execute_RS2_USE; assign decode_MEMORY_STORE = _zz_decode_BRANCH_CTRL_2[12]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_BRANCH_CTRL_2[11]; assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_BRANCH_CTRL_2[10]; assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; assign writeBack_RS1_USE = memory_to_writeBack_RS1_USE; assign memory_RS1_USE = execute_to_memory_RS1_USE; assign execute_RS1_USE = decode_to_execute_RS1_USE; assign decode_MEMORY_ENABLE = _zz_decode_BRANCH_CTRL_2[3]; assign execute_PREDICTION_CONTEXT_hazard = decode_to_execute_PREDICTION_CONTEXT_hazard; assign execute_PREDICTION_CONTEXT_hit = decode_to_execute_PREDICTION_CONTEXT_hit; assign execute_PREDICTION_CONTEXT_line_source = decode_to_execute_PREDICTION_CONTEXT_line_source; assign execute_PREDICTION_CONTEXT_line_branchWish = decode_to_execute_PREDICTION_CONTEXT_line_branchWish; assign execute_PREDICTION_CONTEXT_line_last2Bytes = decode_to_execute_PREDICTION_CONTEXT_line_last2Bytes; assign execute_PREDICTION_CONTEXT_line_target = decode_to_execute_PREDICTION_CONTEXT_line_target; assign decode_PREDICTION_CONTEXT_hazard = IBusSimplePlugin_predictor_injectorContext_hazard; assign decode_PREDICTION_CONTEXT_hit = IBusSimplePlugin_predictor_injectorContext_hit; assign decode_PREDICTION_CONTEXT_line_source = IBusSimplePlugin_predictor_injectorContext_line_source; assign decode_PREDICTION_CONTEXT_line_branchWish = IBusSimplePlugin_predictor_injectorContext_line_branchWish; assign decode_PREDICTION_CONTEXT_line_last2Bytes = IBusSimplePlugin_predictor_injectorContext_line_last2Bytes; assign decode_PREDICTION_CONTEXT_line_target = IBusSimplePlugin_predictor_injectorContext_line_target; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = _zz_decode_FORMAL_PC_NEXT; assign writeBack_FORMAL_INSTRUCTION = memory_to_writeBack_FORMAL_INSTRUCTION; assign memory_FORMAL_INSTRUCTION = execute_to_memory_FORMAL_INSTRUCTION; assign execute_FORMAL_INSTRUCTION = decode_to_execute_FORMAL_INSTRUCTION; assign decode_FORMAL_INSTRUCTION = IBusSimplePlugin_injector_formal_rawInDecode; assign writeBack_FORMAL_HALT = memory_to_writeBack_FORMAL_HALT; assign memory_FORMAL_HALT = execute_to_memory_FORMAL_HALT; assign execute_FORMAL_HALT = decode_to_execute_FORMAL_HALT; assign decode_FORMAL_HALT = 1'b0; assign memory_NEXT_PC2 = execute_to_memory_NEXT_PC2; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_TARGET_MISSMATCH2 = execute_to_memory_TARGET_MISSMATCH2; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_IS_RVC = decode_to_execute_IS_RVC; assign execute_BRANCH_SRC22 = _zz_execute_BRANCH_SRC22_6; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; assign decode_RS2_USE = _zz_decode_BRANCH_CTRL_2[14]; assign decode_RS1_USE = _zz_decode_BRANCH_CTRL_2[4]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; always @(*) begin _zz_memory_to_writeBack_REGFILE_WRITE_DATA = memory_REGFILE_WRITE_DATA; if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) ShiftCtrlEnum_SLL_1 : begin _zz_memory_to_writeBack_REGFILE_WRITE_DATA = _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1; end ShiftCtrlEnum_SRL_1, ShiftCtrlEnum_SRA_1 : begin _zz_memory_to_writeBack_REGFILE_WRITE_DATA = memory_SHIFT_RIGHT; end default : begin end endcase end end assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; assign _zz_decode_SRC2 = decode_PC; assign _zz_decode_SRC2_1 = decode_RS2; assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; assign _zz_decode_SRC1 = decode_RS1; assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; assign decode_SRC_USE_SUB_LESS = _zz_decode_BRANCH_CTRL_2[2]; assign decode_SRC_ADD_ZERO = _zz_decode_BRANCH_CTRL_2[18]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; assign execute_SRC2 = decode_to_execute_SRC2; assign execute_SRC1 = decode_to_execute_SRC1; assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; always @(*) begin _zz_1 = 1'b0; if(lastStageRegFileWrite_valid) begin _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_decompressor_output_payload_rsp_inst); always @(*) begin decode_REGFILE_WRITE_VALID = _zz_decode_BRANCH_CTRL_2[9]; if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end assign decode_LEGAL_INSTRUCTION = (|{((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00004063),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}}); assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); assign memory_IS_RVC = execute_to_memory_IS_RVC; assign memory_PC = execute_to_memory_PC; assign memory_PREDICTION_CONTEXT_hazard = execute_to_memory_PREDICTION_CONTEXT_hazard; assign memory_PREDICTION_CONTEXT_hit = execute_to_memory_PREDICTION_CONTEXT_hit; assign memory_PREDICTION_CONTEXT_line_source = execute_to_memory_PREDICTION_CONTEXT_line_source; assign memory_PREDICTION_CONTEXT_line_branchWish = execute_to_memory_PREDICTION_CONTEXT_line_branchWish; assign memory_PREDICTION_CONTEXT_line_last2Bytes = execute_to_memory_PREDICTION_CONTEXT_line_last2Bytes; assign memory_PREDICTION_CONTEXT_line_target = execute_to_memory_PREDICTION_CONTEXT_line_target; always @(*) begin _zz_2 = 1'b0; if(IBusSimplePlugin_predictor_historyWriteDelayPatched_valid) begin _zz_2 = 1'b1; end end always @(*) begin _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; if(BranchPlugin_jumpInterface_valid) begin _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end assign decode_PC = IBusSimplePlugin_decodePc_pcReg; assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; assign decode_IS_RVC = IBusSimplePlugin_injector_decodeInput_payload_isRvc; always @(*) begin _zz_when_FormalPlugin_l114 = writeBack_FORMAL_HALT; if(writeBack_arbitration_isFlushed) begin _zz_when_FormalPlugin_l114 = 1'b0; end if(writeBack_arbitration_isFlushed) begin _zz_when_FormalPlugin_l114 = 1'b0; end end always @(*) begin _zz_when_FormalPlugin_l114_1 = memory_FORMAL_HALT; if(memory_arbitration_isFlushed) begin _zz_when_FormalPlugin_l114_1 = 1'b0; end if(when_HaltOnExceptionPlugin_l34_1) begin _zz_when_FormalPlugin_l114_1 = 1'b1; end if(memory_arbitration_isFlushed) begin _zz_when_FormalPlugin_l114_1 = 1'b0; end end always @(*) begin _zz_when_FormalPlugin_l114_2 = execute_FORMAL_HALT; if(execute_arbitration_isFlushed) begin _zz_when_FormalPlugin_l114_2 = 1'b0; end if(execute_arbitration_isFlushed) begin _zz_when_FormalPlugin_l114_2 = 1'b0; end end always @(*) begin _zz_when_FormalPlugin_l114_3 = decode_FORMAL_HALT; if(when_HaltOnExceptionPlugin_l34) begin _zz_when_FormalPlugin_l114_3 = 1'b1; end if(decode_arbitration_isFlushed) begin _zz_when_FormalPlugin_l114_3 = 1'b0; end if(decode_arbitration_isFlushed) begin _zz_when_FormalPlugin_l114_3 = 1'b0; end end always @(*) begin _zz_rvfi_rd_wdata = writeBack_REGFILE_WRITE_DATA; if(when_DBusSimplePlugin_l558) begin _zz_rvfi_rd_wdata = writeBack_DBusSimplePlugin_rspFormated; end end assign _zz_rvfi_rd_addr = writeBack_REGFILE_WRITE_VALID; assign _zz_rvfi_rs2_addr = writeBack_RS2_USE; assign _zz_rvfi_rs1_addr = writeBack_INSTRUCTION; assign _zz_rvfi_rs1_addr_1 = writeBack_RS1_USE; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @(*) begin decode_arbitration_haltItself = 1'b0; if(when_HaltOnExceptionPlugin_l34) begin decode_arbitration_haltItself = 1'b1; end end always @(*) begin decode_arbitration_haltByOther = 1'b0; if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end end always @(*) begin decode_arbitration_removeIt = 1'b0; if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; assign decode_arbitration_flushNext = 1'b0; always @(*) begin execute_arbitration_haltItself = 1'b0; if(when_DBusSimplePlugin_l428) begin execute_arbitration_haltItself = 1'b1; end end assign execute_arbitration_haltByOther = 1'b0; always @(*) begin execute_arbitration_removeIt = 1'b0; if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_flushIt = 1'b0; assign execute_arbitration_flushNext = 1'b0; always @(*) begin memory_arbitration_haltItself = 1'b0; if(when_HaltOnExceptionPlugin_l34_1) begin memory_arbitration_haltItself = 1'b1; end if(when_DBusSimplePlugin_l482) begin memory_arbitration_haltItself = 1'b1; end end assign memory_arbitration_haltByOther = 1'b0; always @(*) begin memory_arbitration_removeIt = 1'b0; if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; always @(*) begin memory_arbitration_flushNext = 1'b0; if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end end assign writeBack_arbitration_haltItself = 1'b0; assign writeBack_arbitration_haltByOther = 1'b0; always @(*) begin writeBack_arbitration_removeIt = 1'b0; if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end assign writeBack_arbitration_flushIt = 1'b0; assign writeBack_arbitration_flushNext = 1'b0; assign lastStageInstruction = writeBack_INSTRUCTION; assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; assign IBusSimplePlugin_fetcherHalt = 1'b0; always @(*) begin IBusSimplePlugin_incomingInstruction = 1'b0; if(IBusSimplePlugin_iBusRsp_stages_1_input_valid) begin IBusSimplePlugin_incomingInstruction = 1'b1; end if(IBusSimplePlugin_injector_decodeInput_valid) begin IBusSimplePlugin_incomingInstruction = 1'b1; end end always @(*) begin rvfi_valid = writeBack_arbitration_isFiring; if(writeBack_FormalPlugin_haltRequest_delay_5) begin rvfi_valid = 1'b1; end if(writeBack_FormalPlugin_haltFired) begin rvfi_valid = 1'b0; end end assign rvfi_order = writeBack_FormalPlugin_order; assign rvfi_insn = writeBack_FORMAL_INSTRUCTION; always @(*) begin rvfi_trap = 1'b0; if(writeBack_FormalPlugin_haltRequest_delay_5) begin rvfi_trap = 1'b1; end end always @(*) begin rvfi_halt = 1'b0; if(writeBack_FormalPlugin_haltRequest_delay_5) begin rvfi_halt = 1'b1; end end assign rvfi_intr = 1'b0; assign rvfi_mode = 2'd3; assign rvfi_ixl = 2'd1; assign rvfi_rs1_addr = (_zz_rvfi_rs1_addr_1 ? _zz_rvfi_rs1_addr[19 : 15] : 5'h0); assign rvfi_rs2_addr = (_zz_rvfi_rs2_addr ? _zz_rvfi_rs1_addr[24 : 20] : 5'h0); assign rvfi_rs1_rdata = (_zz_rvfi_rs1_addr_1 ? writeBack_RS1 : 32'h0); assign rvfi_rs2_rdata = (_zz_rvfi_rs2_addr ? writeBack_RS2 : 32'h0); assign rvfi_rd_addr = (_zz_rvfi_rd_addr ? _zz_rvfi_rs1_addr[11 : 7] : 5'h0); assign rvfi_rd_wdata = (_zz_rvfi_rd_addr ? _zz_rvfi_rd_wdata : 32'h0); assign rvfi_pc_rdata = writeBack_PC; assign rvfi_pc_wdata = writeBack_FORMAL_PC_NEXT; assign rvfi_mem_addr = writeBack_FORMAL_MEM_ADDR; assign rvfi_mem_rmask = writeBack_FORMAL_MEM_RMASK; assign rvfi_mem_wmask = writeBack_FORMAL_MEM_WMASK; assign rvfi_mem_rdata = writeBack_FORMAL_MEM_RDATA; assign rvfi_mem_wdata = writeBack_FORMAL_MEM_WDATA; always @(*) begin writeBack_FormalPlugin_haltRequest = 1'b0; if(when_FormalPlugin_l114) begin if(when_FormalPlugin_l115) begin writeBack_FormalPlugin_haltRequest = 1'b1; end end if(when_FormalPlugin_l114_1) begin if(when_FormalPlugin_l115_1) begin writeBack_FormalPlugin_haltRequest = 1'b1; end end if(when_FormalPlugin_l114_2) begin if(when_FormalPlugin_l115_2) begin writeBack_FormalPlugin_haltRequest = 1'b1; end end if(when_FormalPlugin_l114_3) begin if(when_FormalPlugin_l115_3) begin writeBack_FormalPlugin_haltRequest = 1'b1; end end end assign when_FormalPlugin_l114 = (decode_arbitration_isValid && _zz_when_FormalPlugin_l114_3); assign when_FormalPlugin_l115 = (((1'b1 && (! execute_arbitration_isValid)) && (! memory_arbitration_isValid)) && (! writeBack_arbitration_isValid)); assign when_FormalPlugin_l114_1 = (execute_arbitration_isValid && _zz_when_FormalPlugin_l114_2); assign when_FormalPlugin_l115_1 = ((1'b1 && (! memory_arbitration_isValid)) && (! writeBack_arbitration_isValid)); assign when_FormalPlugin_l114_2 = (memory_arbitration_isValid && _zz_when_FormalPlugin_l114_1); assign when_FormalPlugin_l115_2 = (1'b1 && (! writeBack_arbitration_isValid)); assign when_FormalPlugin_l114_3 = (writeBack_arbitration_isValid && _zz_when_FormalPlugin_l114); assign when_FormalPlugin_l115_3 = 1'b1; assign when_FormalPlugin_l127 = (rvfi_valid && rvfi_halt); assign when_HaltOnExceptionPlugin_l34 = (decodeExceptionPort_valid != 1'b0); assign when_HaltOnExceptionPlugin_l34_1 = (DBusSimplePlugin_memoryExceptionPort_valid != 1'b0); assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusSimplePlugin_jump_pcLoad_valid = (BranchPlugin_jumpInterface_valid != 1'b0); assign IBusSimplePlugin_jump_pcLoad_payload = BranchPlugin_jumpInterface_payload; always @(*) begin IBusSimplePlugin_fetchPc_correction = 1'b0; if(IBusSimplePlugin_fetchPc_predictionPcLoad_valid) begin IBusSimplePlugin_fetchPc_correction = 1'b1; end if(IBusSimplePlugin_fetchPc_redo_valid) begin IBusSimplePlugin_fetchPc_correction = 1'b1; end if(IBusSimplePlugin_jump_pcLoad_valid) begin IBusSimplePlugin_fetchPc_correction = 1'b1; end end assign IBusSimplePlugin_fetchPc_output_fire = (IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready); assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); assign IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; assign when_Fetcher_l131 = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate); assign IBusSimplePlugin_fetchPc_output_fire_1 = (IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready); assign when_Fetcher_l131_1 = ((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready); always @(*) begin IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_IBusSimplePlugin_fetchPc_pc); if(IBusSimplePlugin_fetchPc_inc) begin IBusSimplePlugin_fetchPc_pc[1] = 1'b0; end if(IBusSimplePlugin_fetchPc_predictionPcLoad_valid) begin IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_predictionPcLoad_payload; end if(IBusSimplePlugin_fetchPc_redo_valid) begin IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_redo_payload; end if(IBusSimplePlugin_jump_pcLoad_valid) begin IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; end IBusSimplePlugin_fetchPc_pc[0] = 1'b0; end always @(*) begin IBusSimplePlugin_fetchPc_flushed = 1'b0; if(IBusSimplePlugin_fetchPc_redo_valid) begin IBusSimplePlugin_fetchPc_flushed = 1'b1; end if(IBusSimplePlugin_jump_pcLoad_valid) begin IBusSimplePlugin_fetchPc_flushed = 1'b1; end end assign when_Fetcher_l158 = (IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)); assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; always @(*) begin IBusSimplePlugin_decodePc_flushed = 1'b0; if(when_Fetcher_l192) begin IBusSimplePlugin_decodePc_flushed = 1'b1; end end assign IBusSimplePlugin_decodePc_pcPlus = (IBusSimplePlugin_decodePc_pcReg + _zz_IBusSimplePlugin_decodePc_pcPlus); assign IBusSimplePlugin_decodePc_injectedDecode = 1'b0; assign when_Fetcher_l180 = (decode_arbitration_isFiring && (! IBusSimplePlugin_decodePc_injectedDecode)); assign when_Fetcher_l192 = (IBusSimplePlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt)); always @(*) begin IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; if(IBusSimplePlugin_predictor_compressor_unalignedWordIssue) begin IBusSimplePlugin_iBusRsp_redoFetch = 1'b1; end end assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; always @(*) begin IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; if(when_IBusSimplePlugin_l305) begin IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; end end assign _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready = (! IBusSimplePlugin_iBusRsp_stages_0_halt); assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready); assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready); assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; assign _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready = (! IBusSimplePlugin_iBusRsp_stages_1_halt); assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready); assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready); assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; assign IBusSimplePlugin_fetchPc_redo_valid = IBusSimplePlugin_iBusRsp_redoFetch; always @(*) begin IBusSimplePlugin_fetchPc_redo_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; if(IBusSimplePlugin_decompressor_throw2BytesReg) begin IBusSimplePlugin_fetchPc_redo_payload[1] = 1'b1; end end assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid)) || IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_ready); assign IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid; assign IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_payload = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_payload; assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid; assign IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_ready = IBusSimplePlugin_iBusRsp_stages_1_input_ready; assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_payload; always @(*) begin IBusSimplePlugin_iBusRsp_readyForError = 1'b1; if(IBusSimplePlugin_injector_decodeInput_valid) begin IBusSimplePlugin_iBusRsp_readyForError = 1'b0; end end assign IBusSimplePlugin_decompressor_input_valid = (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_iBusRsp_redoFetch)); assign IBusSimplePlugin_decompressor_input_payload_pc = IBusSimplePlugin_iBusRsp_output_payload_pc; assign IBusSimplePlugin_decompressor_input_payload_rsp_error = IBusSimplePlugin_iBusRsp_output_payload_rsp_error; assign IBusSimplePlugin_decompressor_input_payload_rsp_inst = IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; assign IBusSimplePlugin_decompressor_input_payload_isRvc = IBusSimplePlugin_iBusRsp_output_payload_isRvc; assign IBusSimplePlugin_iBusRsp_output_ready = IBusSimplePlugin_decompressor_input_ready; assign IBusSimplePlugin_decompressor_flushNext = 1'b0; assign IBusSimplePlugin_decompressor_consumeCurrent = 1'b0; assign IBusSimplePlugin_decompressor_isInputLowRvc = (IBusSimplePlugin_decompressor_input_payload_rsp_inst[1 : 0] != 2'b11); assign IBusSimplePlugin_decompressor_isInputHighRvc = (IBusSimplePlugin_decompressor_input_payload_rsp_inst[17 : 16] != 2'b11); assign IBusSimplePlugin_decompressor_throw2Bytes = (IBusSimplePlugin_decompressor_throw2BytesReg || IBusSimplePlugin_decompressor_input_payload_pc[1]); assign IBusSimplePlugin_decompressor_unaligned = (IBusSimplePlugin_decompressor_throw2Bytes || IBusSimplePlugin_decompressor_bufferValid); assign IBusSimplePlugin_decompressor_bufferValidPatched = (IBusSimplePlugin_decompressor_input_valid ? IBusSimplePlugin_decompressor_bufferValid : IBusSimplePlugin_decompressor_bufferValidLatch); assign IBusSimplePlugin_decompressor_throw2BytesPatched = (IBusSimplePlugin_decompressor_input_valid ? IBusSimplePlugin_decompressor_throw2Bytes : IBusSimplePlugin_decompressor_throw2BytesLatch); assign IBusSimplePlugin_decompressor_raw = (IBusSimplePlugin_decompressor_bufferValidPatched ? {IBusSimplePlugin_decompressor_input_payload_rsp_inst[15 : 0],IBusSimplePlugin_decompressor_bufferData} : {IBusSimplePlugin_decompressor_input_payload_rsp_inst[31 : 16],(IBusSimplePlugin_decompressor_throw2BytesPatched ? IBusSimplePlugin_decompressor_input_payload_rsp_inst[31 : 16] : IBusSimplePlugin_decompressor_input_payload_rsp_inst[15 : 0])}); assign IBusSimplePlugin_decompressor_isRvc = (IBusSimplePlugin_decompressor_raw[1 : 0] != 2'b11); assign _zz_IBusSimplePlugin_decompressor_decompressed = IBusSimplePlugin_decompressor_raw[15 : 0]; always @(*) begin IBusSimplePlugin_decompressor_decompressed = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(switch_Misc_l44) 5'h0 : begin IBusSimplePlugin_decompressor_decompressed = {{{{{{{{{2'b00,_zz_IBusSimplePlugin_decompressor_decompressed[10 : 7]},_zz_IBusSimplePlugin_decompressor_decompressed[12 : 11]},_zz_IBusSimplePlugin_decompressor_decompressed[5]},_zz_IBusSimplePlugin_decompressor_decompressed[6]},2'b00},5'h02},3'b000},_zz_IBusSimplePlugin_decompressor_decompressed_2},7'h13}; end 5'h02 : begin IBusSimplePlugin_decompressor_decompressed = {{{{_zz_IBusSimplePlugin_decompressor_decompressed_3,_zz_IBusSimplePlugin_decompressor_decompressed_1},3'b010},_zz_IBusSimplePlugin_decompressor_decompressed_2},7'h03}; end 5'h06 : begin IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_IBusSimplePlugin_decompressor_decompressed_3[11 : 5],_zz_IBusSimplePlugin_decompressor_decompressed_2},_zz_IBusSimplePlugin_decompressor_decompressed_1},3'b010},_zz_IBusSimplePlugin_decompressor_decompressed_3[4 : 0]},7'h23}; end 5'h08 : begin IBusSimplePlugin_decompressor_decompressed = {{{{_zz_IBusSimplePlugin_decompressor_decompressed_5,_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},3'b000},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},7'h13}; end 5'h09 : begin IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_IBusSimplePlugin_decompressor_decompressed_8[20],_zz_IBusSimplePlugin_decompressor_decompressed_8[10 : 1]},_zz_IBusSimplePlugin_decompressor_decompressed_8[11]},_zz_IBusSimplePlugin_decompressor_decompressed_8[19 : 12]},_zz_IBusSimplePlugin_decompressor_decompressed_20},7'h6f}; end 5'h0a : begin IBusSimplePlugin_decompressor_decompressed = {{{{_zz_IBusSimplePlugin_decompressor_decompressed_5,5'h0},3'b000},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},7'h13}; end 5'h0b : begin IBusSimplePlugin_decompressor_decompressed = ((_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7] == 5'h02) ? {{{{{{{{{_zz_IBusSimplePlugin_decompressor_decompressed_12,_zz_IBusSimplePlugin_decompressor_decompressed[4 : 3]},_zz_IBusSimplePlugin_decompressor_decompressed[5]},_zz_IBusSimplePlugin_decompressor_decompressed[2]},_zz_IBusSimplePlugin_decompressor_decompressed[6]},4'b0000},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},3'b000},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},7'h13} : {{_zz_IBusSimplePlugin_decompressor_decompressed_27[31 : 12],_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},7'h37}); end 5'h0c : begin IBusSimplePlugin_decompressor_decompressed = {{{{{((_zz_IBusSimplePlugin_decompressor_decompressed[11 : 10] == 2'b10) ? _zz_IBusSimplePlugin_decompressor_decompressed_26 : {{1'b0,(_zz_IBusSimplePlugin_decompressor_decompressed_28 || _zz_IBusSimplePlugin_decompressor_decompressed_29)},5'h0}),(((! _zz_IBusSimplePlugin_decompressor_decompressed[11]) || _zz_IBusSimplePlugin_decompressor_decompressed_22) ? _zz_IBusSimplePlugin_decompressor_decompressed[6 : 2] : _zz_IBusSimplePlugin_decompressor_decompressed_2)},_zz_IBusSimplePlugin_decompressor_decompressed_1},_zz_IBusSimplePlugin_decompressor_decompressed_24},_zz_IBusSimplePlugin_decompressor_decompressed_1},(_zz_IBusSimplePlugin_decompressor_decompressed_22 ? 7'h13 : 7'h33)}; end 5'h0d : begin IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_IBusSimplePlugin_decompressor_decompressed_15[20],_zz_IBusSimplePlugin_decompressor_decompressed_15[10 : 1]},_zz_IBusSimplePlugin_decompressor_decompressed_15[11]},_zz_IBusSimplePlugin_decompressor_decompressed_15[19 : 12]},_zz_IBusSimplePlugin_decompressor_decompressed_19},7'h6f}; end 5'h0e : begin IBusSimplePlugin_decompressor_decompressed = {{{{{{{_zz_IBusSimplePlugin_decompressor_decompressed_18[12],_zz_IBusSimplePlugin_decompressor_decompressed_18[10 : 5]},_zz_IBusSimplePlugin_decompressor_decompressed_19},_zz_IBusSimplePlugin_decompressor_decompressed_1},3'b000},_zz_IBusSimplePlugin_decompressor_decompressed_18[4 : 1]},_zz_IBusSimplePlugin_decompressor_decompressed_18[11]},7'h63}; end 5'h0f : begin IBusSimplePlugin_decompressor_decompressed = {{{{{{{_zz_IBusSimplePlugin_decompressor_decompressed_18[12],_zz_IBusSimplePlugin_decompressor_decompressed_18[10 : 5]},_zz_IBusSimplePlugin_decompressor_decompressed_19},_zz_IBusSimplePlugin_decompressor_decompressed_1},3'b001},_zz_IBusSimplePlugin_decompressor_decompressed_18[4 : 1]},_zz_IBusSimplePlugin_decompressor_decompressed_18[11]},7'h63}; end 5'h10 : begin IBusSimplePlugin_decompressor_decompressed = {{{{{7'h0,_zz_IBusSimplePlugin_decompressor_decompressed[6 : 2]},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},3'b001},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},7'h13}; end 5'h12 : begin IBusSimplePlugin_decompressor_decompressed = {{{{{{{{4'b0000,_zz_IBusSimplePlugin_decompressor_decompressed[3 : 2]},_zz_IBusSimplePlugin_decompressor_decompressed[12]},_zz_IBusSimplePlugin_decompressor_decompressed[6 : 4]},2'b00},_zz_IBusSimplePlugin_decompressor_decompressed_21},3'b010},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},7'h03}; end 5'h14 : begin IBusSimplePlugin_decompressor_decompressed = ((_zz_IBusSimplePlugin_decompressor_decompressed[12 : 2] == 11'h400) ? 32'h00100073 : ((_zz_IBusSimplePlugin_decompressor_decompressed[6 : 2] == 5'h0) ? {{{{12'h0,_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},3'b000},(_zz_IBusSimplePlugin_decompressor_decompressed[12] ? _zz_IBusSimplePlugin_decompressor_decompressed_20 : _zz_IBusSimplePlugin_decompressor_decompressed_19)},7'h67} : {{{{{_zz_IBusSimplePlugin_decompressor_decompressed_30,_zz_IBusSimplePlugin_decompressor_decompressed_31},(_zz_IBusSimplePlugin_decompressor_decompressed_32 ? _zz_IBusSimplePlugin_decompressor_decompressed_33 : _zz_IBusSimplePlugin_decompressor_decompressed_19)},3'b000},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},7'h33})); end 5'h16 : begin IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_IBusSimplePlugin_decompressor_decompressed_34[11 : 5],_zz_IBusSimplePlugin_decompressor_decompressed[6 : 2]},_zz_IBusSimplePlugin_decompressor_decompressed_21},3'b010},_zz_IBusSimplePlugin_decompressor_decompressed_35[4 : 0]},7'h23}; end default : begin end endcase end assign _zz_IBusSimplePlugin_decompressor_decompressed_1 = {2'b01,_zz_IBusSimplePlugin_decompressor_decompressed[9 : 7]}; assign _zz_IBusSimplePlugin_decompressor_decompressed_2 = {2'b01,_zz_IBusSimplePlugin_decompressor_decompressed[4 : 2]}; assign _zz_IBusSimplePlugin_decompressor_decompressed_3 = {{{{5'h0,_zz_IBusSimplePlugin_decompressor_decompressed[5]},_zz_IBusSimplePlugin_decompressor_decompressed[12 : 10]},_zz_IBusSimplePlugin_decompressor_decompressed[6]},2'b00}; assign _zz_IBusSimplePlugin_decompressor_decompressed_4 = _zz_IBusSimplePlugin_decompressor_decompressed[12]; always @(*) begin _zz_IBusSimplePlugin_decompressor_decompressed_5[11] = _zz_IBusSimplePlugin_decompressor_decompressed_4; _zz_IBusSimplePlugin_decompressor_decompressed_5[10] = _zz_IBusSimplePlugin_decompressor_decompressed_4; _zz_IBusSimplePlugin_decompressor_decompressed_5[9] = _zz_IBusSimplePlugin_decompressor_decompressed_4; _zz_IBusSimplePlugin_decompressor_decompressed_5[8] = _zz_IBusSimplePlugin_decompressor_decompressed_4; _zz_IBusSimplePlugin_decompressor_decompressed_5[7] = _zz_IBusSimplePlugin_decompressor_decompressed_4; _zz_IBusSimplePlugin_decompressor_decompressed_5[6] = _zz_IBusSimplePlugin_decompressor_decompressed_4; _zz_IBusSimplePlugin_decompressor_decompressed_5[5] = _zz_IBusSimplePlugin_decompressor_decompressed_4; _zz_IBusSimplePlugin_decompressor_decompressed_5[4 : 0] = _zz_IBusSimplePlugin_decompressor_decompressed[6 : 2]; end assign _zz_IBusSimplePlugin_decompressor_decompressed_6 = _zz_IBusSimplePlugin_decompressor_decompressed[12]; always @(*) begin _zz_IBusSimplePlugin_decompressor_decompressed_7[9] = _zz_IBusSimplePlugin_decompressor_decompressed_6; _zz_IBusSimplePlugin_decompressor_decompressed_7[8] = _zz_IBusSimplePlugin_decompressor_decompressed_6; _zz_IBusSimplePlugin_decompressor_decompressed_7[7] = _zz_IBusSimplePlugin_decompressor_decompressed_6; _zz_IBusSimplePlugin_decompressor_decompressed_7[6] = _zz_IBusSimplePlugin_decompressor_decompressed_6; _zz_IBusSimplePlugin_decompressor_decompressed_7[5] = _zz_IBusSimplePlugin_decompressor_decompressed_6; _zz_IBusSimplePlugin_decompressor_decompressed_7[4] = _zz_IBusSimplePlugin_decompressor_decompressed_6; _zz_IBusSimplePlugin_decompressor_decompressed_7[3] = _zz_IBusSimplePlugin_decompressor_decompressed_6; _zz_IBusSimplePlugin_decompressor_decompressed_7[2] = _zz_IBusSimplePlugin_decompressor_decompressed_6; _zz_IBusSimplePlugin_decompressor_decompressed_7[1] = _zz_IBusSimplePlugin_decompressor_decompressed_6; _zz_IBusSimplePlugin_decompressor_decompressed_7[0] = _zz_IBusSimplePlugin_decompressor_decompressed_6; end assign _zz_IBusSimplePlugin_decompressor_decompressed_8 = {{{{{{{{_zz_IBusSimplePlugin_decompressor_decompressed_7,_zz_IBusSimplePlugin_decompressor_decompressed[8]},_zz_IBusSimplePlugin_decompressor_decompressed[10 : 9]},_zz_IBusSimplePlugin_decompressor_decompressed[6]},_zz_IBusSimplePlugin_decompressor_decompressed[7]},_zz_IBusSimplePlugin_decompressor_decompressed[2]},_zz_IBusSimplePlugin_decompressor_decompressed[11]},_zz_IBusSimplePlugin_decompressor_decompressed[5 : 3]},1'b0}; assign _zz_IBusSimplePlugin_decompressor_decompressed_9 = _zz_IBusSimplePlugin_decompressor_decompressed[12]; always @(*) begin _zz_IBusSimplePlugin_decompressor_decompressed_10[14] = _zz_IBusSimplePlugin_decompressor_decompressed_9; _zz_IBusSimplePlugin_decompressor_decompressed_10[13] = _zz_IBusSimplePlugin_decompressor_decompressed_9; _zz_IBusSimplePlugin_decompressor_decompressed_10[12] = _zz_IBusSimplePlugin_decompressor_decompressed_9; _zz_IBusSimplePlugin_decompressor_decompressed_10[11] = _zz_IBusSimplePlugin_decompressor_decompressed_9; _zz_IBusSimplePlugin_decompressor_decompressed_10[10] = _zz_IBusSimplePlugin_decompressor_decompressed_9; _zz_IBusSimplePlugin_decompressor_decompressed_10[9] = _zz_IBusSimplePlugin_decompressor_decompressed_9; _zz_IBusSimplePlugin_decompressor_decompressed_10[8] = _zz_IBusSimplePlugin_decompressor_decompressed_9; _zz_IBusSimplePlugin_decompressor_decompressed_10[7] = _zz_IBusSimplePlugin_decompressor_decompressed_9; _zz_IBusSimplePlugin_decompressor_decompressed_10[6] = _zz_IBusSimplePlugin_decompressor_decompressed_9; _zz_IBusSimplePlugin_decompressor_decompressed_10[5] = _zz_IBusSimplePlugin_decompressor_decompressed_9; _zz_IBusSimplePlugin_decompressor_decompressed_10[4] = _zz_IBusSimplePlugin_decompressor_decompressed_9; _zz_IBusSimplePlugin_decompressor_decompressed_10[3] = _zz_IBusSimplePlugin_decompressor_decompressed_9; _zz_IBusSimplePlugin_decompressor_decompressed_10[2] = _zz_IBusSimplePlugin_decompressor_decompressed_9; _zz_IBusSimplePlugin_decompressor_decompressed_10[1] = _zz_IBusSimplePlugin_decompressor_decompressed_9; _zz_IBusSimplePlugin_decompressor_decompressed_10[0] = _zz_IBusSimplePlugin_decompressor_decompressed_9; end assign _zz_IBusSimplePlugin_decompressor_decompressed_11 = _zz_IBusSimplePlugin_decompressor_decompressed[12]; always @(*) begin _zz_IBusSimplePlugin_decompressor_decompressed_12[2] = _zz_IBusSimplePlugin_decompressor_decompressed_11; _zz_IBusSimplePlugin_decompressor_decompressed_12[1] = _zz_IBusSimplePlugin_decompressor_decompressed_11; _zz_IBusSimplePlugin_decompressor_decompressed_12[0] = _zz_IBusSimplePlugin_decompressor_decompressed_11; end assign _zz_IBusSimplePlugin_decompressor_decompressed_13 = _zz_IBusSimplePlugin_decompressor_decompressed[12]; always @(*) begin _zz_IBusSimplePlugin_decompressor_decompressed_14[9] = _zz_IBusSimplePlugin_decompressor_decompressed_13; _zz_IBusSimplePlugin_decompressor_decompressed_14[8] = _zz_IBusSimplePlugin_decompressor_decompressed_13; _zz_IBusSimplePlugin_decompressor_decompressed_14[7] = _zz_IBusSimplePlugin_decompressor_decompressed_13; _zz_IBusSimplePlugin_decompressor_decompressed_14[6] = _zz_IBusSimplePlugin_decompressor_decompressed_13; _zz_IBusSimplePlugin_decompressor_decompressed_14[5] = _zz_IBusSimplePlugin_decompressor_decompressed_13; _zz_IBusSimplePlugin_decompressor_decompressed_14[4] = _zz_IBusSimplePlugin_decompressor_decompressed_13; _zz_IBusSimplePlugin_decompressor_decompressed_14[3] = _zz_IBusSimplePlugin_decompressor_decompressed_13; _zz_IBusSimplePlugin_decompressor_decompressed_14[2] = _zz_IBusSimplePlugin_decompressor_decompressed_13; _zz_IBusSimplePlugin_decompressor_decompressed_14[1] = _zz_IBusSimplePlugin_decompressor_decompressed_13; _zz_IBusSimplePlugin_decompressor_decompressed_14[0] = _zz_IBusSimplePlugin_decompressor_decompressed_13; end assign _zz_IBusSimplePlugin_decompressor_decompressed_15 = {{{{{{{{_zz_IBusSimplePlugin_decompressor_decompressed_14,_zz_IBusSimplePlugin_decompressor_decompressed[8]},_zz_IBusSimplePlugin_decompressor_decompressed[10 : 9]},_zz_IBusSimplePlugin_decompressor_decompressed[6]},_zz_IBusSimplePlugin_decompressor_decompressed[7]},_zz_IBusSimplePlugin_decompressor_decompressed[2]},_zz_IBusSimplePlugin_decompressor_decompressed[11]},_zz_IBusSimplePlugin_decompressor_decompressed[5 : 3]},1'b0}; assign _zz_IBusSimplePlugin_decompressor_decompressed_16 = _zz_IBusSimplePlugin_decompressor_decompressed[12]; always @(*) begin _zz_IBusSimplePlugin_decompressor_decompressed_17[4] = _zz_IBusSimplePlugin_decompressor_decompressed_16; _zz_IBusSimplePlugin_decompressor_decompressed_17[3] = _zz_IBusSimplePlugin_decompressor_decompressed_16; _zz_IBusSimplePlugin_decompressor_decompressed_17[2] = _zz_IBusSimplePlugin_decompressor_decompressed_16; _zz_IBusSimplePlugin_decompressor_decompressed_17[1] = _zz_IBusSimplePlugin_decompressor_decompressed_16; _zz_IBusSimplePlugin_decompressor_decompressed_17[0] = _zz_IBusSimplePlugin_decompressor_decompressed_16; end assign _zz_IBusSimplePlugin_decompressor_decompressed_18 = {{{{{_zz_IBusSimplePlugin_decompressor_decompressed_17,_zz_IBusSimplePlugin_decompressor_decompressed[6 : 5]},_zz_IBusSimplePlugin_decompressor_decompressed[2]},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 10]},_zz_IBusSimplePlugin_decompressor_decompressed[4 : 3]},1'b0}; assign _zz_IBusSimplePlugin_decompressor_decompressed_19 = 5'h0; assign _zz_IBusSimplePlugin_decompressor_decompressed_20 = 5'h01; assign _zz_IBusSimplePlugin_decompressor_decompressed_21 = 5'h02; assign switch_Misc_l44 = {_zz_IBusSimplePlugin_decompressor_decompressed[1 : 0],_zz_IBusSimplePlugin_decompressor_decompressed[15 : 13]}; assign _zz_IBusSimplePlugin_decompressor_decompressed_22 = (_zz_IBusSimplePlugin_decompressor_decompressed[11 : 10] != 2'b11); assign switch_Misc_l211 = _zz_IBusSimplePlugin_decompressor_decompressed[11 : 10]; assign switch_Misc_l211_1 = _zz_IBusSimplePlugin_decompressor_decompressed[6 : 5]; always @(*) begin case(switch_Misc_l211_1) 2'b00 : begin _zz_IBusSimplePlugin_decompressor_decompressed_23 = 3'b000; end 2'b01 : begin _zz_IBusSimplePlugin_decompressor_decompressed_23 = 3'b100; end 2'b10 : begin _zz_IBusSimplePlugin_decompressor_decompressed_23 = 3'b110; end default : begin _zz_IBusSimplePlugin_decompressor_decompressed_23 = 3'b111; end endcase end always @(*) begin case(switch_Misc_l211) 2'b00 : begin _zz_IBusSimplePlugin_decompressor_decompressed_24 = 3'b101; end 2'b01 : begin _zz_IBusSimplePlugin_decompressor_decompressed_24 = 3'b101; end 2'b10 : begin _zz_IBusSimplePlugin_decompressor_decompressed_24 = 3'b111; end default : begin _zz_IBusSimplePlugin_decompressor_decompressed_24 = _zz_IBusSimplePlugin_decompressor_decompressed_23; end endcase end assign _zz_IBusSimplePlugin_decompressor_decompressed_25 = _zz_IBusSimplePlugin_decompressor_decompressed[12]; always @(*) begin _zz_IBusSimplePlugin_decompressor_decompressed_26[6] = _zz_IBusSimplePlugin_decompressor_decompressed_25; _zz_IBusSimplePlugin_decompressor_decompressed_26[5] = _zz_IBusSimplePlugin_decompressor_decompressed_25; _zz_IBusSimplePlugin_decompressor_decompressed_26[4] = _zz_IBusSimplePlugin_decompressor_decompressed_25; _zz_IBusSimplePlugin_decompressor_decompressed_26[3] = _zz_IBusSimplePlugin_decompressor_decompressed_25; _zz_IBusSimplePlugin_decompressor_decompressed_26[2] = _zz_IBusSimplePlugin_decompressor_decompressed_25; _zz_IBusSimplePlugin_decompressor_decompressed_26[1] = _zz_IBusSimplePlugin_decompressor_decompressed_25; _zz_IBusSimplePlugin_decompressor_decompressed_26[0] = _zz_IBusSimplePlugin_decompressor_decompressed_25; end assign IBusSimplePlugin_decompressor_output_valid = (IBusSimplePlugin_decompressor_input_valid && (! ((IBusSimplePlugin_decompressor_throw2Bytes && (! IBusSimplePlugin_decompressor_bufferValid)) && (! IBusSimplePlugin_decompressor_isInputHighRvc)))); assign IBusSimplePlugin_decompressor_output_payload_pc = IBusSimplePlugin_decompressor_input_payload_pc; assign IBusSimplePlugin_decompressor_output_payload_isRvc = IBusSimplePlugin_decompressor_isRvc; assign IBusSimplePlugin_decompressor_output_payload_rsp_inst = (IBusSimplePlugin_decompressor_isRvc ? IBusSimplePlugin_decompressor_decompressed : IBusSimplePlugin_decompressor_raw); always @(*) begin IBusSimplePlugin_decompressor_input_ready = (IBusSimplePlugin_decompressor_output_ready && (((! IBusSimplePlugin_iBusRsp_stages_1_input_valid) || IBusSimplePlugin_decompressor_flushNext) || ((! (IBusSimplePlugin_decompressor_bufferValid && IBusSimplePlugin_decompressor_isInputHighRvc)) && (! (((! IBusSimplePlugin_decompressor_unaligned) && IBusSimplePlugin_decompressor_isInputLowRvc) && IBusSimplePlugin_decompressor_isInputHighRvc))))); if(when_Fetcher_l617) begin IBusSimplePlugin_decompressor_input_ready = 1'b1; end end assign IBusSimplePlugin_decompressor_output_fire = (IBusSimplePlugin_decompressor_output_valid && IBusSimplePlugin_decompressor_output_ready); assign IBusSimplePlugin_decompressor_bufferFill = (((((! IBusSimplePlugin_decompressor_unaligned) && IBusSimplePlugin_decompressor_isInputLowRvc) && (! IBusSimplePlugin_decompressor_isInputHighRvc)) || (IBusSimplePlugin_decompressor_bufferValid && (! IBusSimplePlugin_decompressor_isInputHighRvc))) || ((IBusSimplePlugin_decompressor_throw2Bytes && (! IBusSimplePlugin_decompressor_isRvc)) && (! IBusSimplePlugin_decompressor_isInputHighRvc))); assign when_Fetcher_l283 = (IBusSimplePlugin_decompressor_output_ready && IBusSimplePlugin_decompressor_input_valid); assign when_Fetcher_l286 = (IBusSimplePlugin_decompressor_output_ready && IBusSimplePlugin_decompressor_input_valid); assign when_Fetcher_l291 = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_decompressor_consumeCurrent); assign IBusSimplePlugin_decompressor_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); assign IBusSimplePlugin_injector_decodeInput_valid = _zz_IBusSimplePlugin_injector_decodeInput_valid; assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_IBusSimplePlugin_injector_decodeInput_payload_pc; assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error; assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc; assign when_Fetcher_l329 = (! 1'b0); assign when_Fetcher_l329_1 = (! execute_arbitration_isStuck); assign when_Fetcher_l329_2 = (! memory_arbitration_isStuck); assign when_Fetcher_l329_3 = (! writeBack_arbitration_isStuck); assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_0; assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_1; assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_2; assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_3; assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; always @(*) begin _zz_decode_FORMAL_PC_NEXT = (decode_PC + _zz__zz_decode_FORMAL_PC_NEXT); if(IBusSimplePlugin_decodePc_predictionPcLoad_valid) begin _zz_decode_FORMAL_PC_NEXT = IBusSimplePlugin_decodePc_predictionPcLoad_payload; end end assign IBusSimplePlugin_predictor_historyWriteDelayPatched_valid = IBusSimplePlugin_predictor_historyWrite_valid; assign IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_address = (IBusSimplePlugin_predictor_historyWrite_payload_address - 10'h001); assign IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_source = IBusSimplePlugin_predictor_historyWrite_payload_data_source; assign IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_branchWish = IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish; assign IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_last2Bytes = IBusSimplePlugin_predictor_historyWrite_payload_data_last2Bytes; assign IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_target = IBusSimplePlugin_predictor_historyWrite_payload_data_target; assign _zz_IBusSimplePlugin_predictor_buffer_line_source = (IBusSimplePlugin_iBusRsp_stages_0_input_payload >>> 2); assign _zz_IBusSimplePlugin_predictor_buffer_line_source_1 = _zz_IBusSimplePlugin_predictor_history_port1; assign IBusSimplePlugin_predictor_buffer_line_source = _zz_IBusSimplePlugin_predictor_buffer_line_source_1[19 : 0]; assign IBusSimplePlugin_predictor_buffer_line_branchWish = _zz_IBusSimplePlugin_predictor_buffer_line_source_1[21 : 20]; assign IBusSimplePlugin_predictor_buffer_line_last2Bytes = _zz_IBusSimplePlugin_predictor_buffer_line_source_1[22]; assign IBusSimplePlugin_predictor_buffer_line_target = _zz_IBusSimplePlugin_predictor_buffer_line_source_1[54 : 23]; assign IBusSimplePlugin_predictor_buffer_hazard = (IBusSimplePlugin_predictor_writeLast_valid && (IBusSimplePlugin_predictor_writeLast_payload_address == _zz_IBusSimplePlugin_predictor_buffer_hazard)); assign IBusSimplePlugin_predictor_hazard = (IBusSimplePlugin_predictor_buffer_hazard_regNextWhen || IBusSimplePlugin_predictor_buffer_pcCorrected); always @(*) begin IBusSimplePlugin_predictor_hit = (IBusSimplePlugin_predictor_line_source == _zz_IBusSimplePlugin_predictor_hit); if(when_Fetcher_l550) begin IBusSimplePlugin_predictor_hit = 1'b0; end end assign when_Fetcher_l550 = ((! IBusSimplePlugin_predictor_line_last2Bytes) && IBusSimplePlugin_iBusRsp_stages_1_input_payload[1]); assign IBusSimplePlugin_fetchPc_predictionPcLoad_valid = (((IBusSimplePlugin_predictor_line_branchWish[1] && IBusSimplePlugin_predictor_hit) && (! IBusSimplePlugin_predictor_hazard)) && IBusSimplePlugin_iBusRsp_stages_1_input_valid); assign IBusSimplePlugin_fetchPc_predictionPcLoad_payload = IBusSimplePlugin_predictor_line_target; assign IBusSimplePlugin_predictor_fetchContext_hazard = IBusSimplePlugin_predictor_hazard; assign IBusSimplePlugin_predictor_fetchContext_hit = IBusSimplePlugin_predictor_hit; assign IBusSimplePlugin_predictor_fetchContext_line_source = IBusSimplePlugin_predictor_line_source; assign IBusSimplePlugin_predictor_fetchContext_line_branchWish = IBusSimplePlugin_predictor_line_branchWish; assign IBusSimplePlugin_predictor_fetchContext_line_last2Bytes = IBusSimplePlugin_predictor_line_last2Bytes; assign IBusSimplePlugin_predictor_fetchContext_line_target = IBusSimplePlugin_predictor_line_target; assign IBusSimplePlugin_predictor_iBusRspContextOutput_hazard = IBusSimplePlugin_predictor_fetchContext_hazard; always @(*) begin IBusSimplePlugin_predictor_iBusRspContextOutput_hit = IBusSimplePlugin_predictor_fetchContext_hit; if(when_Fetcher_l611) begin IBusSimplePlugin_predictor_iBusRspContextOutput_hit = 1'b0; end end assign IBusSimplePlugin_predictor_iBusRspContextOutput_line_source = IBusSimplePlugin_predictor_fetchContext_line_source; assign IBusSimplePlugin_predictor_iBusRspContextOutput_line_branchWish = IBusSimplePlugin_predictor_fetchContext_line_branchWish; assign IBusSimplePlugin_predictor_iBusRspContextOutput_line_last2Bytes = IBusSimplePlugin_predictor_fetchContext_line_last2Bytes; assign IBusSimplePlugin_predictor_iBusRspContextOutput_line_target = IBusSimplePlugin_predictor_fetchContext_line_target; assign IBusSimplePlugin_predictor_injectorContext_hazard = IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_hazard; assign IBusSimplePlugin_predictor_injectorContext_hit = IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_hit; assign IBusSimplePlugin_predictor_injectorContext_line_source = IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_source; assign IBusSimplePlugin_predictor_injectorContext_line_branchWish = IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_branchWish; assign IBusSimplePlugin_predictor_injectorContext_line_last2Bytes = IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_last2Bytes; assign IBusSimplePlugin_predictor_injectorContext_line_target = IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_target; assign IBusSimplePlugin_fetchPrediction_cmd_hadBranch = ((memory_PREDICTION_CONTEXT_hit && (! memory_PREDICTION_CONTEXT_hazard)) && memory_PREDICTION_CONTEXT_line_branchWish[1]); assign IBusSimplePlugin_fetchPrediction_cmd_targetPc = memory_PREDICTION_CONTEXT_line_target; always @(*) begin IBusSimplePlugin_predictor_historyWrite_valid = 1'b0; if(IBusSimplePlugin_fetchPrediction_rsp_wasRight) begin IBusSimplePlugin_predictor_historyWrite_valid = memory_PREDICTION_CONTEXT_hit; end else begin if(memory_PREDICTION_CONTEXT_hit) begin IBusSimplePlugin_predictor_historyWrite_valid = 1'b1; end else begin IBusSimplePlugin_predictor_historyWrite_valid = 1'b1; end end if(when_Fetcher_l596) begin IBusSimplePlugin_predictor_historyWrite_valid = 1'b0; end if(IBusSimplePlugin_predictor_compressor_unalignedWordIssue) begin IBusSimplePlugin_predictor_historyWrite_valid = 1'b1; end end always @(*) begin IBusSimplePlugin_predictor_historyWrite_payload_address = IBusSimplePlugin_fetchPrediction_rsp_sourceLastWord[11 : 2]; if(IBusSimplePlugin_predictor_compressor_unalignedWordIssue) begin IBusSimplePlugin_predictor_historyWrite_payload_address = _zz_IBusSimplePlugin_predictor_historyWrite_payload_address[9:0]; end end assign IBusSimplePlugin_predictor_historyWrite_payload_data_source = (IBusSimplePlugin_fetchPrediction_rsp_sourceLastWord >>> 12); assign IBusSimplePlugin_predictor_historyWrite_payload_data_target = IBusSimplePlugin_fetchPrediction_rsp_finalPc; assign IBusSimplePlugin_predictor_historyWrite_payload_data_last2Bytes = (memory_PC[1] && memory_IS_RVC); always @(*) begin if(IBusSimplePlugin_fetchPrediction_rsp_wasRight) begin IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish = (_zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish - _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_3); end else begin if(memory_PREDICTION_CONTEXT_hit) begin IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish = (_zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_5 + _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_8); end else begin IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish = 2'b10; end end if(IBusSimplePlugin_predictor_compressor_unalignedWordIssue) begin IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish = 2'b00; end end assign when_Fetcher_l596 = (memory_PREDICTION_CONTEXT_hazard || (! memory_arbitration_isFiring)); assign IBusSimplePlugin_predictor_compressor_predictionBranch = ((IBusSimplePlugin_predictor_fetchContext_hit && (! IBusSimplePlugin_predictor_fetchContext_hazard)) && IBusSimplePlugin_predictor_fetchContext_line_branchWish[1]); assign IBusSimplePlugin_predictor_compressor_unalignedWordIssue = (((IBusSimplePlugin_iBusRsp_output_valid && IBusSimplePlugin_predictor_compressor_predictionBranch) && IBusSimplePlugin_predictor_fetchContext_line_last2Bytes) && (IBusSimplePlugin_decompressor_unaligned ? (! IBusSimplePlugin_decompressor_isInputHighRvc) : (IBusSimplePlugin_decompressor_isInputLowRvc && (! IBusSimplePlugin_decompressor_isInputHighRvc)))); assign when_Fetcher_l611 = (IBusSimplePlugin_predictor_fetchContext_line_last2Bytes && (IBusSimplePlugin_decompressor_bufferValid || ((! IBusSimplePlugin_decompressor_throw2Bytes) && IBusSimplePlugin_decompressor_isInputLowRvc))); assign IBusSimplePlugin_injector_decodeInput_fire = (IBusSimplePlugin_injector_decodeInput_valid && IBusSimplePlugin_injector_decodeInput_ready); assign IBusSimplePlugin_decodePc_predictionPcLoad_valid = (((IBusSimplePlugin_predictor_injectorContext_line_branchWish[1] && IBusSimplePlugin_predictor_injectorContext_hit) && (! IBusSimplePlugin_predictor_injectorContext_hazard)) && IBusSimplePlugin_injector_decodeInput_fire); assign IBusSimplePlugin_decodePc_predictionPcLoad_payload = IBusSimplePlugin_predictor_injectorContext_line_target; assign IBusSimplePlugin_decompressor_output_fire_1 = (IBusSimplePlugin_decompressor_output_valid && IBusSimplePlugin_decompressor_output_ready); assign when_Fetcher_l617 = (((IBusSimplePlugin_predictor_fetchContext_line_branchWish[1] && IBusSimplePlugin_predictor_iBusRspContextOutput_hit) && (! IBusSimplePlugin_predictor_fetchContext_hazard)) && IBusSimplePlugin_decompressor_output_fire_1); assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; assign IBusSimplePlugin_pending_next = (_zz_IBusSimplePlugin_pending_next - _zz_IBusSimplePlugin_pending_next_3); assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); assign when_IBusSimplePlugin_l305 = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))); assign IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); assign IBusSimplePlugin_cmd_fire = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); assign IBusSimplePlugin_pending_inc = IBusSimplePlugin_cmd_fire; assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_iBusRsp_stages_0_input_payload[31 : 2],2'b00}; assign iBus_rsp_toStream_valid = iBus_rsp_valid; assign iBus_rsp_toStream_payload_error = iBus_rsp_payload_error; assign iBus_rsp_toStream_payload_inst = iBus_rsp_payload_inst; assign iBus_rsp_toStream_ready = IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000) || IBusSimplePlugin_iBusRsp_flush); assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready); assign IBusSimplePlugin_pending_dec = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire; assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; always @(*) begin IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; if(when_IBusSimplePlugin_l376) begin IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; end end assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; assign when_IBusSimplePlugin_l376 = (! IBusSimplePlugin_rspJoin_rspBuffer_output_valid); assign IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; assign IBusSimplePlugin_rspJoin_join_fire = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? IBusSimplePlugin_rspJoin_join_fire : IBusSimplePlugin_rspJoin_join_ready); assign IBusSimplePlugin_rspJoin_join_fire_1 = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = IBusSimplePlugin_rspJoin_join_fire_1; assign _zz_IBusSimplePlugin_iBusRsp_output_valid = (! IBusSimplePlugin_rspJoin_exceptionDetected); assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_IBusSimplePlugin_iBusRsp_output_valid); assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_IBusSimplePlugin_iBusRsp_output_valid); assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; assign _zz_dBus_cmd_valid = 1'b0; always @(*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; if(execute_ALIGNEMENT_FAULT) begin execute_DBusSimplePlugin_skipCmd = 1'b1; end end assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; always @(*) begin case(dBus_cmd_payload_size) 2'b00 : begin _zz_dBus_cmd_payload_data = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin _zz_dBus_cmd_payload_data = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin _zz_dBus_cmd_payload_data = execute_RS2[31 : 0]; end endcase end assign dBus_cmd_payload_data = _zz_dBus_cmd_payload_data; assign when_DBusSimplePlugin_l428 = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); always @(*) begin case(dBus_cmd_payload_size) 2'b00 : begin _zz_execute_DBusSimplePlugin_formalMask = 4'b0001; end 2'b01 : begin _zz_execute_DBusSimplePlugin_formalMask = 4'b0011; end default : begin _zz_execute_DBusSimplePlugin_formalMask = 4'b1111; end endcase end assign execute_DBusSimplePlugin_formalMask = (_zz_execute_DBusSimplePlugin_formalMask <<< dBus_cmd_payload_address[1 : 0]); assign dBus_cmd_payload_address = execute_SRC_ADD; assign when_DBusSimplePlugin_l482 = (((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)); always @(*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; if(memory_ALIGNEMENT_FAULT) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end if(when_DBusSimplePlugin_l515) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @(*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; if(memory_ALIGNEMENT_FAULT) begin DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_DBusSimplePlugin_memoryExceptionPort_payload_code}; end end assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; assign when_DBusSimplePlugin_l515 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); always @(*) begin writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; end 2'b10 : begin writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; end 2'b11 : begin writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; end default : begin end endcase end assign switch_Misc_l211_2 = writeBack_INSTRUCTION[13 : 12]; assign _zz_writeBack_DBusSimplePlugin_rspFormated = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); always @(*) begin _zz_writeBack_DBusSimplePlugin_rspFormated_1[31] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[30] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[29] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[28] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[27] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[26] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[25] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[24] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[23] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[22] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[21] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[20] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[19] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[18] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[17] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[16] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[15] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[14] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[13] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[12] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[11] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[10] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[9] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[8] = _zz_writeBack_DBusSimplePlugin_rspFormated; _zz_writeBack_DBusSimplePlugin_rspFormated_1[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; end assign _zz_writeBack_DBusSimplePlugin_rspFormated_2 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); always @(*) begin _zz_writeBack_DBusSimplePlugin_rspFormated_3[31] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[30] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[29] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[28] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[27] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[26] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[25] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[24] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[23] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[22] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[21] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[20] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[19] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[18] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[17] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[16] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; _zz_writeBack_DBusSimplePlugin_rspFormated_3[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; end always @(*) begin case(switch_Misc_l211_2) 2'b00 : begin writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_1; end 2'b01 : begin writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_3; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; end endcase end assign when_DBusSimplePlugin_l558 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign _zz_decode_BRANCH_CTRL_3 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); assign _zz_decode_BRANCH_CTRL_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); assign _zz_decode_BRANCH_CTRL_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_decode_BRANCH_CTRL_6 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); assign _zz_decode_BRANCH_CTRL_2 = {(|{_zz_decode_BRANCH_CTRL_5,(_zz__zz_decode_BRANCH_CTRL_2 == _zz__zz_decode_BRANCH_CTRL_2_1)}),{(|(_zz__zz_decode_BRANCH_CTRL_2_2 == _zz__zz_decode_BRANCH_CTRL_2_3)),{(|_zz__zz_decode_BRANCH_CTRL_2_4),{(|_zz__zz_decode_BRANCH_CTRL_2_5),{_zz__zz_decode_BRANCH_CTRL_2_8,{_zz__zz_decode_BRANCH_CTRL_2_10,_zz__zz_decode_BRANCH_CTRL_2_13}}}}}}; assign _zz_decode_SRC1_CTRL_2 = _zz_decode_BRANCH_CTRL_2[1 : 0]; assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; assign _zz_decode_ALU_CTRL_2 = _zz_decode_BRANCH_CTRL_2[6 : 5]; assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; assign _zz_decode_SRC2_CTRL_2 = _zz_decode_BRANCH_CTRL_2[8 : 7]; assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_BRANCH_CTRL_2[17 : 16]; assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_BRANCH_CTRL_2[20 : 19]; assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; assign _zz_decode_BRANCH_CTRL_7 = _zz_decode_BRANCH_CTRL_2[22 : 21]; assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_7; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; always @(*) begin lastStageRegFileWrite_valid = (_zz_rvfi_rd_addr && writeBack_arbitration_isFiring); if(_zz_3) begin lastStageRegFileWrite_valid = 1'b1; end end always @(*) begin lastStageRegFileWrite_payload_address = _zz_rvfi_rs1_addr[11 : 7]; if(_zz_3) begin lastStageRegFileWrite_payload_address = 5'h0; end end always @(*) begin lastStageRegFileWrite_payload_data = _zz_rvfi_rd_wdata; if(_zz_3) begin lastStageRegFileWrite_payload_data = 32'h0; end end always @(*) begin case(execute_ALU_BITWISE_CTRL) AluBitwiseCtrlEnum_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end AluBitwiseCtrlEnum_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); end endcase end always @(*) begin case(execute_ALU_CTRL) AluCtrlEnum_BITWISE : begin _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end AluCtrlEnum_SLT_SLTU : begin _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end always @(*) begin case(decode_SRC1_CTRL) Src1CtrlEnum_RS : begin _zz_decode_SRC1_1 = _zz_decode_SRC1; end Src1CtrlEnum_PC_INCREMENT : begin _zz_decode_SRC1_1 = {29'd0, _zz__zz_decode_SRC1_1}; end Src1CtrlEnum_IMU : begin _zz_decode_SRC1_1 = {decode_INSTRUCTION[31 : 12],12'h0}; end default : begin _zz_decode_SRC1_1 = {27'd0, _zz__zz_decode_SRC1_1_1}; end endcase end assign _zz_decode_SRC2_2 = decode_INSTRUCTION[31]; always @(*) begin _zz_decode_SRC2_3[19] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[18] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[17] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[16] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[15] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[14] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[13] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[12] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[11] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[10] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[9] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[8] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[7] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[6] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[5] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[4] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[3] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[2] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[1] = _zz_decode_SRC2_2; _zz_decode_SRC2_3[0] = _zz_decode_SRC2_2; end assign _zz_decode_SRC2_4 = _zz__zz_decode_SRC2_4[11]; always @(*) begin _zz_decode_SRC2_5[19] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[18] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[17] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[16] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[15] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[14] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[13] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[12] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[11] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[10] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[9] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[8] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[7] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[6] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[5] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[4] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[3] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[2] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[1] = _zz_decode_SRC2_4; _zz_decode_SRC2_5[0] = _zz_decode_SRC2_4; end always @(*) begin case(decode_SRC2_CTRL) Src2CtrlEnum_RS : begin _zz_decode_SRC2_6 = _zz_decode_SRC2_1; end Src2CtrlEnum_IMI : begin _zz_decode_SRC2_6 = {_zz_decode_SRC2_3,decode_INSTRUCTION[31 : 20]}; end Src2CtrlEnum_IMS : begin _zz_decode_SRC2_6 = {_zz_decode_SRC2_5,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; end default : begin _zz_decode_SRC2_6 = _zz_decode_SRC2; end endcase end always @(*) begin execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @(*) begin _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; end assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == ShiftCtrlEnum_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); always @(*) begin _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[0] = memory_SHIFT_RIGHT[31]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[1] = memory_SHIFT_RIGHT[30]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[2] = memory_SHIFT_RIGHT[29]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[3] = memory_SHIFT_RIGHT[28]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[4] = memory_SHIFT_RIGHT[27]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[5] = memory_SHIFT_RIGHT[26]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[6] = memory_SHIFT_RIGHT[25]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[7] = memory_SHIFT_RIGHT[24]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[8] = memory_SHIFT_RIGHT[23]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[9] = memory_SHIFT_RIGHT[22]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[10] = memory_SHIFT_RIGHT[21]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[11] = memory_SHIFT_RIGHT[20]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[12] = memory_SHIFT_RIGHT[19]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[13] = memory_SHIFT_RIGHT[18]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[14] = memory_SHIFT_RIGHT[17]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[15] = memory_SHIFT_RIGHT[16]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[16] = memory_SHIFT_RIGHT[15]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[17] = memory_SHIFT_RIGHT[14]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[18] = memory_SHIFT_RIGHT[13]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[19] = memory_SHIFT_RIGHT[12]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[20] = memory_SHIFT_RIGHT[11]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[21] = memory_SHIFT_RIGHT[10]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[22] = memory_SHIFT_RIGHT[9]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[23] = memory_SHIFT_RIGHT[8]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[24] = memory_SHIFT_RIGHT[7]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[25] = memory_SHIFT_RIGHT[6]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[26] = memory_SHIFT_RIGHT[5]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[27] = memory_SHIFT_RIGHT[4]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[28] = memory_SHIFT_RIGHT[3]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[29] = memory_SHIFT_RIGHT[2]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[30] = memory_SHIFT_RIGHT[1]; _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[31] = memory_SHIFT_RIGHT[0]; end always @(*) begin HazardSimplePlugin_src0Hazard = 1'b0; if(HazardSimplePlugin_writeBackBuffer_valid) begin if(HazardSimplePlugin_addr0Match) begin HazardSimplePlugin_src0Hazard = 1'b1; end end if(when_HazardSimplePlugin_l57) begin if(when_HazardSimplePlugin_l58) begin if(when_HazardSimplePlugin_l59) begin HazardSimplePlugin_src0Hazard = 1'b1; end end end if(when_HazardSimplePlugin_l57_1) begin if(when_HazardSimplePlugin_l58_1) begin if(when_HazardSimplePlugin_l59_1) begin HazardSimplePlugin_src0Hazard = 1'b1; end end end if(when_HazardSimplePlugin_l57_2) begin if(when_HazardSimplePlugin_l58_2) begin if(when_HazardSimplePlugin_l59_2) begin HazardSimplePlugin_src0Hazard = 1'b1; end end end if(when_HazardSimplePlugin_l105) begin HazardSimplePlugin_src0Hazard = 1'b0; end end always @(*) begin HazardSimplePlugin_src1Hazard = 1'b0; if(HazardSimplePlugin_writeBackBuffer_valid) begin if(HazardSimplePlugin_addr1Match) begin HazardSimplePlugin_src1Hazard = 1'b1; end end if(when_HazardSimplePlugin_l57) begin if(when_HazardSimplePlugin_l58) begin if(when_HazardSimplePlugin_l62) begin HazardSimplePlugin_src1Hazard = 1'b1; end end end if(when_HazardSimplePlugin_l57_1) begin if(when_HazardSimplePlugin_l58_1) begin if(when_HazardSimplePlugin_l62_1) begin HazardSimplePlugin_src1Hazard = 1'b1; end end end if(when_HazardSimplePlugin_l57_2) begin if(when_HazardSimplePlugin_l58_2) begin if(when_HazardSimplePlugin_l62_2) begin HazardSimplePlugin_src1Hazard = 1'b1; end end end if(when_HazardSimplePlugin_l108) begin HazardSimplePlugin_src1Hazard = 1'b0; end end assign HazardSimplePlugin_writeBackWrites_valid = (_zz_rvfi_rd_addr && writeBack_arbitration_isFiring); assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_rvfi_rs1_addr[11 : 7]; assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_rvfi_rd_wdata; assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); assign when_HazardSimplePlugin_l59 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); assign when_HazardSimplePlugin_l62 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); assign when_HazardSimplePlugin_l58 = (1'b1 || (! 1'b1)); assign when_HazardSimplePlugin_l59_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); assign when_HazardSimplePlugin_l62_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); assign when_HazardSimplePlugin_l58_1 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); assign when_HazardSimplePlugin_l59_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); assign when_HazardSimplePlugin_l62_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); assign when_HazardSimplePlugin_l58_2 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); assign switch_Misc_l211_3 = execute_INSTRUCTION[14 : 12]; always @(*) begin casez(switch_Misc_l211_3) 3'b000 : begin _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; end 3'b001 : begin _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); end 3'b1?1 : begin _zz_execute_BRANCH_DO = (! execute_SRC_LESS); end default : begin _zz_execute_BRANCH_DO = execute_SRC_LESS; end endcase end always @(*) begin case(execute_BRANCH_CTRL) BranchCtrlEnum_INC : begin _zz_execute_BRANCH_DO_1 = 1'b0; end BranchCtrlEnum_JAL : begin _zz_execute_BRANCH_DO_1 = 1'b1; end BranchCtrlEnum_JALR : begin _zz_execute_BRANCH_DO_1 = 1'b1; end default : begin _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; end endcase end assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == BranchCtrlEnum_JALR) ? execute_RS1 : execute_PC); assign _zz_execute_BRANCH_SRC22 = _zz__zz_execute_BRANCH_SRC22[19]; always @(*) begin _zz_execute_BRANCH_SRC22_1[10] = _zz_execute_BRANCH_SRC22; _zz_execute_BRANCH_SRC22_1[9] = _zz_execute_BRANCH_SRC22; _zz_execute_BRANCH_SRC22_1[8] = _zz_execute_BRANCH_SRC22; _zz_execute_BRANCH_SRC22_1[7] = _zz_execute_BRANCH_SRC22; _zz_execute_BRANCH_SRC22_1[6] = _zz_execute_BRANCH_SRC22; _zz_execute_BRANCH_SRC22_1[5] = _zz_execute_BRANCH_SRC22; _zz_execute_BRANCH_SRC22_1[4] = _zz_execute_BRANCH_SRC22; _zz_execute_BRANCH_SRC22_1[3] = _zz_execute_BRANCH_SRC22; _zz_execute_BRANCH_SRC22_1[2] = _zz_execute_BRANCH_SRC22; _zz_execute_BRANCH_SRC22_1[1] = _zz_execute_BRANCH_SRC22; _zz_execute_BRANCH_SRC22_1[0] = _zz_execute_BRANCH_SRC22; end assign _zz_execute_BRANCH_SRC22_2 = execute_INSTRUCTION[31]; always @(*) begin _zz_execute_BRANCH_SRC22_3[19] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[18] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[17] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[16] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[15] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[14] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[13] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[12] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[11] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[10] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[9] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[8] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[7] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[6] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[5] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[4] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[3] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[2] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[1] = _zz_execute_BRANCH_SRC22_2; _zz_execute_BRANCH_SRC22_3[0] = _zz_execute_BRANCH_SRC22_2; end assign _zz_execute_BRANCH_SRC22_4 = _zz__zz_execute_BRANCH_SRC22_4[11]; always @(*) begin _zz_execute_BRANCH_SRC22_5[18] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[17] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[16] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[15] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[14] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[13] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[12] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[11] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[10] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[9] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[8] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[7] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[6] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[5] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[4] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[3] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[2] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[1] = _zz_execute_BRANCH_SRC22_4; _zz_execute_BRANCH_SRC22_5[0] = _zz_execute_BRANCH_SRC22_4; end always @(*) begin case(execute_BRANCH_CTRL) BranchCtrlEnum_JAL : begin _zz_execute_BRANCH_SRC22_6 = {{_zz_execute_BRANCH_SRC22_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end BranchCtrlEnum_JALR : begin _zz_execute_BRANCH_SRC22_6 = {_zz_execute_BRANCH_SRC22_3,execute_INSTRUCTION[31 : 20]}; end default : begin _zz_execute_BRANCH_SRC22_6 = {{_zz_execute_BRANCH_SRC22_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BRANCH_SRC22); assign memory_BranchPlugin_predictionMissmatch = ((IBusSimplePlugin_fetchPrediction_cmd_hadBranch != memory_BRANCH_DO) || (memory_BRANCH_DO && memory_TARGET_MISSMATCH2)); assign IBusSimplePlugin_fetchPrediction_rsp_wasRight = (! memory_BranchPlugin_predictionMissmatch); assign IBusSimplePlugin_fetchPrediction_rsp_finalPc = memory_BRANCH_CALC; assign IBusSimplePlugin_fetchPrediction_rsp_sourceLastWord = (((! memory_IS_RVC) && memory_PC[1]) ? memory_NEXT_PC2 : memory_PC); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BranchPlugin_predictionMissmatch) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = (memory_BRANCH_DO ? memory_BRANCH_CALC : memory_NEXT_PC2); assign when_Pipeline_l124 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_2 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_10 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_15 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_16 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_21 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_22 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_29 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_32 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_36 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_37 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_38 = (! execute_arbitration_isStuck); assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; assign when_Pipeline_l124_41 = (! memory_arbitration_isStuck); assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_44 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_45 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_47 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_48 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_51 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_56 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_58 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_63 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_64 = (! writeBack_arbitration_isStuck); assign when_Pipeline_l124_65 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_66 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_67 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_68 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_69 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_70 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); always @(posedge clk) begin if(reset) begin writeBack_FormalPlugin_order <= 64'h0; writeBack_FormalPlugin_haltRequest_delay_1 <= 1'b0; writeBack_FormalPlugin_haltRequest_delay_2 <= 1'b0; writeBack_FormalPlugin_haltRequest_delay_3 <= 1'b0; writeBack_FormalPlugin_haltRequest_delay_4 <= 1'b0; writeBack_FormalPlugin_haltRequest_delay_5 <= 1'b0; writeBack_FormalPlugin_haltFired <= 1'b0; IBusSimplePlugin_fetchPc_pcReg <= 32'h0; IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; IBusSimplePlugin_fetchPc_booted <= 1'b0; IBusSimplePlugin_fetchPc_inc <= 1'b0; IBusSimplePlugin_decodePc_pcReg <= 32'h0; _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid <= 1'b0; IBusSimplePlugin_decompressor_bufferValid <= 1'b0; IBusSimplePlugin_decompressor_throw2BytesReg <= 1'b0; _zz_IBusSimplePlugin_injector_decodeInput_valid <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusSimplePlugin_pending_value <= 3'b000; IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; _zz_3 <= 1'b1; HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; end else begin if(writeBack_arbitration_isFiring) begin writeBack_FormalPlugin_order <= (writeBack_FormalPlugin_order + 64'h0000000000000001); end writeBack_FormalPlugin_haltRequest_delay_1 <= writeBack_FormalPlugin_haltRequest; writeBack_FormalPlugin_haltRequest_delay_2 <= writeBack_FormalPlugin_haltRequest_delay_1; writeBack_FormalPlugin_haltRequest_delay_3 <= writeBack_FormalPlugin_haltRequest_delay_2; writeBack_FormalPlugin_haltRequest_delay_4 <= writeBack_FormalPlugin_haltRequest_delay_3; writeBack_FormalPlugin_haltRequest_delay_5 <= writeBack_FormalPlugin_haltRequest_delay_4; if(when_FormalPlugin_l127) begin writeBack_FormalPlugin_haltFired <= 1'b1; end if(IBusSimplePlugin_fetchPc_correction) begin IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; end if(IBusSimplePlugin_fetchPc_output_fire) begin IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; end IBusSimplePlugin_fetchPc_booted <= 1'b1; if(when_Fetcher_l131) begin IBusSimplePlugin_fetchPc_inc <= 1'b0; end if(IBusSimplePlugin_fetchPc_output_fire_1) begin IBusSimplePlugin_fetchPc_inc <= 1'b1; end if(when_Fetcher_l131_1) begin IBusSimplePlugin_fetchPc_inc <= 1'b0; end if(when_Fetcher_l158) begin IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; end if(when_Fetcher_l180) begin IBusSimplePlugin_decodePc_pcReg <= IBusSimplePlugin_decodePc_pcPlus; end if(IBusSimplePlugin_decodePc_predictionPcLoad_valid) begin IBusSimplePlugin_decodePc_pcReg <= IBusSimplePlugin_decodePc_predictionPcLoad_payload; end if(when_Fetcher_l192) begin IBusSimplePlugin_decodePc_pcReg <= IBusSimplePlugin_jump_pcLoad_payload; end if(IBusSimplePlugin_iBusRsp_flush) begin _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid <= 1'b0; end if(IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end if(IBusSimplePlugin_decompressor_output_fire) begin IBusSimplePlugin_decompressor_throw2BytesReg <= ((((! IBusSimplePlugin_decompressor_unaligned) && IBusSimplePlugin_decompressor_isInputLowRvc) && IBusSimplePlugin_decompressor_isInputHighRvc) || (IBusSimplePlugin_decompressor_bufferValid && IBusSimplePlugin_decompressor_isInputHighRvc)); end if(when_Fetcher_l283) begin IBusSimplePlugin_decompressor_bufferValid <= 1'b0; end if(when_Fetcher_l286) begin if(IBusSimplePlugin_decompressor_bufferFill) begin IBusSimplePlugin_decompressor_bufferValid <= 1'b1; end end if(when_Fetcher_l291) begin IBusSimplePlugin_decompressor_throw2BytesReg <= 1'b0; IBusSimplePlugin_decompressor_bufferValid <= 1'b0; end if(decode_arbitration_removeIt) begin _zz_IBusSimplePlugin_injector_decodeInput_valid <= 1'b0; end if(IBusSimplePlugin_decompressor_output_ready) begin _zz_IBusSimplePlugin_injector_decodeInput_valid <= (IBusSimplePlugin_decompressor_output_valid && (! IBusSimplePlugin_externalFlush)); end if(when_Fetcher_l329) begin IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; end if(IBusSimplePlugin_decodePc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if(when_Fetcher_l329_1) begin IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; end if(IBusSimplePlugin_decodePc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; end if(when_Fetcher_l329_2) begin IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; end if(IBusSimplePlugin_decodePc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; end if(when_Fetcher_l329_3) begin IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; end if(IBusSimplePlugin_decodePc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; end if(when_Fetcher_l617) begin IBusSimplePlugin_decompressor_bufferValid <= 1'b0; IBusSimplePlugin_decompressor_throw2BytesReg <= 1'b0; end IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter); if(IBusSimplePlugin_iBusRsp_flush) begin IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2); end _zz_3 <= 1'b0; HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end end end always @(posedge clk) begin if(IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_payload <= IBusSimplePlugin_iBusRsp_stages_0_output_payload; end if(IBusSimplePlugin_decompressor_input_valid) begin IBusSimplePlugin_decompressor_bufferValidLatch <= IBusSimplePlugin_decompressor_bufferValid; end if(IBusSimplePlugin_decompressor_input_valid) begin IBusSimplePlugin_decompressor_throw2BytesLatch <= IBusSimplePlugin_decompressor_throw2Bytes; end if(when_Fetcher_l286) begin IBusSimplePlugin_decompressor_bufferData <= IBusSimplePlugin_decompressor_input_payload_rsp_inst[31 : 16]; end if(IBusSimplePlugin_decompressor_output_ready) begin _zz_IBusSimplePlugin_injector_decodeInput_payload_pc <= IBusSimplePlugin_decompressor_output_payload_pc; _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error <= IBusSimplePlugin_decompressor_output_payload_rsp_error; _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst <= IBusSimplePlugin_decompressor_output_payload_rsp_inst; _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc <= IBusSimplePlugin_decompressor_output_payload_isRvc; end if(IBusSimplePlugin_injector_decodeInput_ready) begin IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_decompressor_raw; end if(IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin IBusSimplePlugin_predictor_writeLast_valid <= IBusSimplePlugin_predictor_historyWriteDelayPatched_valid; IBusSimplePlugin_predictor_writeLast_payload_address <= IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_address; IBusSimplePlugin_predictor_writeLast_payload_data_source <= IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_source; IBusSimplePlugin_predictor_writeLast_payload_data_branchWish <= IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_branchWish; IBusSimplePlugin_predictor_writeLast_payload_data_last2Bytes <= IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_last2Bytes; IBusSimplePlugin_predictor_writeLast_payload_data_target <= IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_target; end if(IBusSimplePlugin_iBusRsp_stages_0_input_ready) begin IBusSimplePlugin_predictor_buffer_pcCorrected <= IBusSimplePlugin_fetchPc_corrected; end if(IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin IBusSimplePlugin_predictor_line_source <= IBusSimplePlugin_predictor_buffer_line_source; IBusSimplePlugin_predictor_line_branchWish <= IBusSimplePlugin_predictor_buffer_line_branchWish; IBusSimplePlugin_predictor_line_last2Bytes <= IBusSimplePlugin_predictor_buffer_line_last2Bytes; IBusSimplePlugin_predictor_line_target <= IBusSimplePlugin_predictor_buffer_line_target; end if(IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin IBusSimplePlugin_predictor_buffer_hazard_regNextWhen <= IBusSimplePlugin_predictor_buffer_hazard; end if(IBusSimplePlugin_injector_decodeInput_ready) begin IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_hazard <= IBusSimplePlugin_predictor_iBusRspContextOutput_hazard; IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_hit <= IBusSimplePlugin_predictor_iBusRspContextOutput_hit; IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_source <= IBusSimplePlugin_predictor_iBusRspContextOutput_line_source; IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_branchWish <= IBusSimplePlugin_predictor_iBusRspContextOutput_line_branchWish; IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_last2Bytes <= IBusSimplePlugin_predictor_iBusRspContextOutput_line_last2Bytes; IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_target <= IBusSimplePlugin_predictor_iBusRspContextOutput_line_target; end HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; if(when_Pipeline_l124) begin decode_to_execute_FORMAL_HALT <= _zz_when_FormalPlugin_l114_3; end if(when_Pipeline_l124_1) begin execute_to_memory_FORMAL_HALT <= _zz_when_FormalPlugin_l114_2; end if(when_Pipeline_l124_2) begin memory_to_writeBack_FORMAL_HALT <= _zz_when_FormalPlugin_l114_1; end if(when_Pipeline_l124_3) begin decode_to_execute_PC <= _zz_decode_SRC2; end if(when_Pipeline_l124_4) begin execute_to_memory_PC <= execute_PC; end if(when_Pipeline_l124_5) begin memory_to_writeBack_PC <= memory_PC; end if(when_Pipeline_l124_6) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end if(when_Pipeline_l124_7) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end if(when_Pipeline_l124_8) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end if(when_Pipeline_l124_9) begin decode_to_execute_IS_RVC <= decode_IS_RVC; end if(when_Pipeline_l124_10) begin execute_to_memory_IS_RVC <= execute_IS_RVC; end if(when_Pipeline_l124_11) begin decode_to_execute_FORMAL_INSTRUCTION <= decode_FORMAL_INSTRUCTION; end if(when_Pipeline_l124_12) begin execute_to_memory_FORMAL_INSTRUCTION <= execute_FORMAL_INSTRUCTION; end if(when_Pipeline_l124_13) begin memory_to_writeBack_FORMAL_INSTRUCTION <= memory_FORMAL_INSTRUCTION; end if(when_Pipeline_l124_14) begin decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; end if(when_Pipeline_l124_15) begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end if(when_Pipeline_l124_16) begin memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end if(when_Pipeline_l124_17) begin decode_to_execute_PREDICTION_CONTEXT_hazard <= decode_PREDICTION_CONTEXT_hazard; decode_to_execute_PREDICTION_CONTEXT_hit <= decode_PREDICTION_CONTEXT_hit; decode_to_execute_PREDICTION_CONTEXT_line_source <= decode_PREDICTION_CONTEXT_line_source; decode_to_execute_PREDICTION_CONTEXT_line_branchWish <= decode_PREDICTION_CONTEXT_line_branchWish; decode_to_execute_PREDICTION_CONTEXT_line_last2Bytes <= decode_PREDICTION_CONTEXT_line_last2Bytes; decode_to_execute_PREDICTION_CONTEXT_line_target <= decode_PREDICTION_CONTEXT_line_target; end if(when_Pipeline_l124_18) begin execute_to_memory_PREDICTION_CONTEXT_hazard <= execute_PREDICTION_CONTEXT_hazard; execute_to_memory_PREDICTION_CONTEXT_hit <= execute_PREDICTION_CONTEXT_hit; execute_to_memory_PREDICTION_CONTEXT_line_source <= execute_PREDICTION_CONTEXT_line_source; execute_to_memory_PREDICTION_CONTEXT_line_branchWish <= execute_PREDICTION_CONTEXT_line_branchWish; execute_to_memory_PREDICTION_CONTEXT_line_last2Bytes <= execute_PREDICTION_CONTEXT_line_last2Bytes; execute_to_memory_PREDICTION_CONTEXT_line_target <= execute_PREDICTION_CONTEXT_line_target; end if(when_Pipeline_l124_19) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end if(when_Pipeline_l124_20) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end if(when_Pipeline_l124_21) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end if(when_Pipeline_l124_22) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end if(when_Pipeline_l124_23) begin decode_to_execute_RS1_USE <= decode_RS1_USE; end if(when_Pipeline_l124_24) begin execute_to_memory_RS1_USE <= execute_RS1_USE; end if(when_Pipeline_l124_25) begin memory_to_writeBack_RS1_USE <= memory_RS1_USE; end if(when_Pipeline_l124_26) begin decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end if(when_Pipeline_l124_27) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end if(when_Pipeline_l124_28) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end if(when_Pipeline_l124_29) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end if(when_Pipeline_l124_30) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end if(when_Pipeline_l124_31) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end if(when_Pipeline_l124_32) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end if(when_Pipeline_l124_33) begin decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end if(when_Pipeline_l124_34) begin execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; end if(when_Pipeline_l124_35) begin decode_to_execute_RS2_USE <= decode_RS2_USE; end if(when_Pipeline_l124_36) begin execute_to_memory_RS2_USE <= execute_RS2_USE; end if(when_Pipeline_l124_37) begin memory_to_writeBack_RS2_USE <= memory_RS2_USE; end if(when_Pipeline_l124_38) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end if(when_Pipeline_l124_39) begin decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end if(when_Pipeline_l124_40) begin decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end if(when_Pipeline_l124_41) begin execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end if(when_Pipeline_l124_42) begin decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end if(when_Pipeline_l124_43) begin decode_to_execute_RS1 <= _zz_decode_SRC1; end if(when_Pipeline_l124_44) begin execute_to_memory_RS1 <= execute_RS1; end if(when_Pipeline_l124_45) begin memory_to_writeBack_RS1 <= memory_RS1; end if(when_Pipeline_l124_46) begin decode_to_execute_RS2 <= _zz_decode_SRC2_1; end if(when_Pipeline_l124_47) begin execute_to_memory_RS2 <= execute_RS2; end if(when_Pipeline_l124_48) begin memory_to_writeBack_RS2 <= memory_RS2; end if(when_Pipeline_l124_49) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end if(when_Pipeline_l124_50) begin decode_to_execute_SRC1 <= decode_SRC1; end if(when_Pipeline_l124_51) begin decode_to_execute_SRC2 <= decode_SRC2; end if(when_Pipeline_l124_52) begin execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; end if(when_Pipeline_l124_53) begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; end if(when_Pipeline_l124_54) begin memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end if(when_Pipeline_l124_55) begin execute_to_memory_FORMAL_MEM_ADDR <= execute_FORMAL_MEM_ADDR; end if(when_Pipeline_l124_56) begin memory_to_writeBack_FORMAL_MEM_ADDR <= memory_FORMAL_MEM_ADDR; end if(when_Pipeline_l124_57) begin execute_to_memory_FORMAL_MEM_WMASK <= execute_FORMAL_MEM_WMASK; end if(when_Pipeline_l124_58) begin memory_to_writeBack_FORMAL_MEM_WMASK <= memory_FORMAL_MEM_WMASK; end if(when_Pipeline_l124_59) begin execute_to_memory_FORMAL_MEM_RMASK <= execute_FORMAL_MEM_RMASK; end if(when_Pipeline_l124_60) begin memory_to_writeBack_FORMAL_MEM_RMASK <= memory_FORMAL_MEM_RMASK; end if(when_Pipeline_l124_61) begin execute_to_memory_FORMAL_MEM_WDATA <= execute_FORMAL_MEM_WDATA; end if(when_Pipeline_l124_62) begin memory_to_writeBack_FORMAL_MEM_WDATA <= memory_FORMAL_MEM_WDATA; end if(when_Pipeline_l124_63) begin execute_to_memory_REGFILE_WRITE_DATA <= execute_REGFILE_WRITE_DATA; end if(when_Pipeline_l124_64) begin memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_memory_to_writeBack_REGFILE_WRITE_DATA; end if(when_Pipeline_l124_65) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end if(when_Pipeline_l124_66) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end if(when_Pipeline_l124_67) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end if(when_Pipeline_l124_68) begin execute_to_memory_NEXT_PC2 <= execute_NEXT_PC2; end if(when_Pipeline_l124_69) begin execute_to_memory_TARGET_MISSMATCH2 <= execute_TARGET_MISSMATCH2; end if(when_Pipeline_l124_70) begin memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; end end endmodule module StreamFifoLowLatency ( input io_push_valid, output io_push_ready, input io_push_payload_error, input [31:0] io_push_payload_inst, output reg io_pop_valid, input io_pop_ready, output reg io_pop_payload_error, output reg [31:0] io_pop_payload_inst, input io_flush, output [0:0] io_occupancy, input clk, input reset ); reg when_Phase_l623; reg pushPtr_willIncrement; reg pushPtr_willClear; wire pushPtr_willOverflowIfInc; wire pushPtr_willOverflow; reg popPtr_willIncrement; reg popPtr_willClear; wire popPtr_willOverflowIfInc; wire popPtr_willOverflow; wire ptrMatch; reg risingOccupancy; wire empty; wire full; wire pushing; wire popping; wire readed_error; wire [31:0] readed_inst; wire [32:0] _zz_readed_error; wire when_Stream_l1019; wire when_Stream_l1032; wire [32:0] _zz_readed_error_1; reg [32:0] _zz_readed_error_2; always @(*) begin when_Phase_l623 = 1'b0; if(pushing) begin when_Phase_l623 = 1'b1; end end always @(*) begin pushPtr_willIncrement = 1'b0; if(pushing) begin pushPtr_willIncrement = 1'b1; end end always @(*) begin pushPtr_willClear = 1'b0; if(io_flush) begin pushPtr_willClear = 1'b1; end end assign pushPtr_willOverflowIfInc = 1'b1; assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); always @(*) begin popPtr_willIncrement = 1'b0; if(popping) begin popPtr_willIncrement = 1'b1; end end always @(*) begin popPtr_willClear = 1'b0; if(io_flush) begin popPtr_willClear = 1'b1; end end assign popPtr_willOverflowIfInc = 1'b1; assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); assign ptrMatch = 1'b1; assign empty = (ptrMatch && (! risingOccupancy)); assign full = (ptrMatch && risingOccupancy); assign pushing = (io_push_valid && io_push_ready); assign popping = (io_pop_valid && io_pop_ready); assign io_push_ready = (! full); assign _zz_readed_error = _zz_readed_error_1; assign readed_error = _zz_readed_error[0]; assign readed_inst = _zz_readed_error[32 : 1]; assign when_Stream_l1019 = (! empty); always @(*) begin if(when_Stream_l1019) begin io_pop_valid = 1'b1; end else begin io_pop_valid = io_push_valid; end end always @(*) begin if(when_Stream_l1019) begin io_pop_payload_error = readed_error; end else begin io_pop_payload_error = io_push_payload_error; end end always @(*) begin if(when_Stream_l1019) begin io_pop_payload_inst = readed_inst; end else begin io_pop_payload_inst = io_push_payload_inst; end end assign when_Stream_l1032 = (pushing != popping); assign io_occupancy = (risingOccupancy && ptrMatch); assign _zz_readed_error_1 = _zz_readed_error_2; always @(posedge clk) begin if(reset) begin risingOccupancy <= 1'b0; end else begin if(when_Stream_l1032) begin risingOccupancy <= pushing; end if(io_flush) begin risingOccupancy <= 1'b0; end end end always @(posedge clk) begin if(when_Phase_l623) begin _zz_readed_error_2 <= {io_push_payload_inst,io_push_payload_error}; end end endmodule ================================================ FILE: cores/VexRiscv/checks.cfg ================================================ [options] isa rv32i [depth] insn 20 reg 15 30 pc_fwd 10 30 pc_bwd 10 30 liveness 1 10 30 unique 1 10 30 causal 10 30 [defines] `define RISCV_FORMAL_ALIGNED_MEM `define RISCV_FORMAL_ALTOPS `define DEBUGNETS [defines liveness] `define VEXRISCV_FAIRNESS [verilog-files] @basedir@/cores/@core@/wrapper.sv @basedir@/cores/@core@/@core@.v ================================================ FILE: cores/VexRiscv/disasm.py ================================================ #!/usr/bin/env python3 from Verilog_VCD.Verilog_VCD import parse_vcd from os import system from sys import argv rvfi_valid = None rvfi_order = None rvfi_insn = None for netinfo in parse_vcd(argv[1]).values(): for net in netinfo['nets']: # print(net["hier"], net["name"]) if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_valid": rvfi_valid = netinfo['tv'] if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_order": rvfi_order = netinfo['tv'] if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_insn": rvfi_insn = netinfo['tv'] assert len(rvfi_valid) == len(rvfi_order) assert len(rvfi_valid) == len(rvfi_insn) prog = list() for tv_valid, tv_order, tv_insn in zip(rvfi_valid, rvfi_order, rvfi_insn): if tv_valid[1] == '1': prog.append((int(tv_order[1], 2), int(tv_insn[1], 2))) with open("disasm.s", "w") as f: for tv_order, tv_insn in sorted(prog): if tv_insn & 3 != 3 and tv_insn & 0xffff0000 == 0: print(".hword 0x%04x # %d" % (tv_insn, tv_order), file=f) else: print(".word 0x%08x # %d" % (tv_insn, tv_order), file=f) system("riscv64-unknown-elf-gcc -c disasm.s") system("riscv64-unknown-elf-objdump -d -M numeric,no-aliases disasm.o") ================================================ FILE: cores/VexRiscv/dmemcheck.sby ================================================ [options] mode bmc append 0 tbtop testbench.uut depth 22 [engines] smtbmc --presat --unroll boolector [script] read_verilog -sv dmemcheck.sv read_verilog ../../VexRiscv.v prep -nordff -top testbench [files] dmemcheck.sv ../../checks/rvfi_macros.vh ../../checks/rvfi_channel.sv ../../checks/rvfi_testbench.sv ../../checks/rvfi_dmem_check.sv ================================================ FILE: cores/VexRiscv/dmemcheck.sv ================================================ `define RISCV_FORMAL `define RISCV_FORMAL_NRET 1 `define RISCV_FORMAL_XLEN 32 `define RISCV_FORMAL_ILEN 32 `define RISCV_FORMAL_ALIGNED_MEM `include "rvfi_macros.vh" `include "rvfi_channel.sv" `include "rvfi_dmem_check.sv" module testbench ( input clk ); reg reset = 1; always @(posedge clk) reset <= 0; (* keep *) wire iBus_cmd_valid; (* keep *) wire [31:0] iBus_cmd_payload_pc; (* keep *) `rvformal_rand_reg iBus_cmd_ready; (* keep *) `rvformal_rand_reg iBus_rsp_ready; (* keep *) `rvformal_rand_reg [31:0] iBus_rsp_inst; (* keep *) wire dBus_cmd_valid; (* keep *) wire dBus_cmd_payload_wr; (* keep *) wire [31:0] dBus_cmd_payload_address; (* keep *) wire [31:0] dBus_cmd_payload_data; (* keep *) wire [1:0] dBus_cmd_payload_size; (* keep *) `rvformal_rand_reg dBus_cmd_ready; (* keep *) `rvformal_rand_reg dBus_rsp_ready; (* keep *) `rvformal_rand_reg [31:0] dBus_rsp_data; `RVFI_WIRES (* keep *) wire [31:0] dmem_addr; (* keep *) reg [31:0] dmem_data; rvfi_dmem_check checker_inst ( .clock (clk ), .reset (reset ), .enable (1'b1 ), .dmem_addr (dmem_addr), `RVFI_CONN ); (* keep *) reg dmem_last_valid; (* keep *) wire [3:0] dBus_cmd_payload_mask; assign dBus_cmd_payload_mask = ((1 << (1 << dBus_cmd_payload_size))-1) << dBus_cmd_payload_address[1:0]; always @(posedge clk) begin if (reset) begin dmem_last_valid <= 0; end else begin if(dmem_last_valid) begin assume(dBus_rsp_data == dmem_data); end if(dBus_rsp_ready) begin dmem_last_valid <= 0; end if(dBus_cmd_valid && dBus_cmd_ready) begin if((dBus_cmd_payload_address >> 2) == (dmem_addr >> 2)) begin if(!dBus_cmd_payload_wr) begin dmem_last_valid <= 1; end else begin if (dBus_cmd_payload_mask[0]) dmem_data[ 7: 0] <= dBus_cmd_payload_data[ 7: 0]; if (dBus_cmd_payload_mask[1]) dmem_data[15: 8] <= dBus_cmd_payload_data[15: 8]; if (dBus_cmd_payload_mask[2]) dmem_data[23:16] <= dBus_cmd_payload_data[23:16]; if (dBus_cmd_payload_mask[3]) dmem_data[31:24] <= dBus_cmd_payload_data[31:24]; end end end end end VexRiscv uut ( .clk (clk ), .reset (reset ), .iBus_cmd_valid (iBus_cmd_valid), .iBus_cmd_ready (iBus_cmd_ready), .iBus_cmd_payload_pc (iBus_cmd_payload_pc ), .iBus_rsp_ready(iBus_rsp_ready), .iBus_rsp_inst (iBus_rsp_inst), .iBus_rsp_error(1'b0), .dBus_cmd_valid(dBus_cmd_valid), .dBus_cmd_payload_wr(dBus_cmd_payload_wr), .dBus_cmd_payload_address(dBus_cmd_payload_address), .dBus_cmd_payload_data(dBus_cmd_payload_data), .dBus_cmd_payload_size(dBus_cmd_payload_size), .dBus_cmd_ready(dBus_cmd_ready), .dBus_rsp_ready(dBus_rsp_ready), .dBus_rsp_data(dBus_rsp_data), .dBus_rsp_error(1'b0), `RVFI_CONN ); endmodule ================================================ FILE: cores/VexRiscv/imemcheck.sby ================================================ [options] mode bmc append 0 tbtop testbench.uut depth 22 [engines] smtbmc --presat --unroll boolector [script] read_verilog -sv imemcheck.sv read_verilog ../../VexRiscv.v prep -nordff -top testbench [files] imemcheck.sv ../../checks/rvfi_macros.vh ../../checks/rvfi_channel.sv ../../checks/rvfi_testbench.sv ../../checks/rvfi_imem_check.sv ================================================ FILE: cores/VexRiscv/imemcheck.sv ================================================ `define RISCV_FORMAL `define RISCV_FORMAL_NRET 1 `define RISCV_FORMAL_XLEN 32 `define RISCV_FORMAL_ILEN 32 `include "rvfi_macros.vh" `include "rvfi_channel.sv" `include "rvfi_imem_check.sv" module testbench ( input clk ); reg reset = 1; always @(posedge clk) reset <= 0; (* keep *) wire iBus_cmd_valid; (* keep *) wire [31:0] iBus_cmd_payload_pc; (* keep *) `rvformal_rand_reg iBus_cmd_ready; (* keep *) `rvformal_rand_reg iBus_rsp_ready; (* keep *) `rvformal_rand_reg [31:0] iBus_rsp_inst; (* keep *) wire dBus_cmd_valid; (* keep *) wire dBus_cmd_payload_wr; (* keep *) wire [31:0] dBus_cmd_payload_address; (* keep *) wire [31:0] dBus_cmd_payload_data; (* keep *) wire [1:0] dBus_cmd_payload_size; (* keep *) `rvformal_rand_reg dBus_cmd_ready; (* keep *) `rvformal_rand_reg dBus_rsp_ready; (* keep *) `rvformal_rand_reg [31:0] dBus_rsp_data; `RVFI_WIRES (* keep *) wire [31:0] imem_addr; (* keep *) wire [15:0] imem_data; rvfi_imem_check checker_inst ( .clock (clk ), .reset (reset ), .enable (1'b1 ), .imem_addr (imem_addr), .imem_data (imem_data), `RVFI_CONN ); (* keep *) wire imem_last_valid; (* keep *) wire [31:0] imem_last_addr; always @(posedge clk) begin if (reset) begin imem_last_valid <= 0; end else begin if(imem_last_valid) begin if (imem_last_addr == imem_addr) assume(iBus_rsp_inst[15:0] == imem_data); if (imem_last_addr+2 == imem_addr) assume(iBus_rsp_inst[31:16] == imem_data); end if(iBus_rsp_ready) begin imem_last_valid <= 0; end if(iBus_cmd_valid && iBus_cmd_ready) begin imem_last_valid <= 1; imem_last_addr <= iBus_cmd_payload_pc; end end end VexRiscv uut ( .clk (clk ), .reset (reset ), .iBus_cmd_valid (iBus_cmd_valid), .iBus_cmd_ready (iBus_cmd_ready), .iBus_cmd_payload_pc (iBus_cmd_payload_pc ), .iBus_rsp_ready(iBus_rsp_ready), .iBus_rsp_inst (iBus_rsp_inst), .iBus_rsp_error(1'b0), .dBus_cmd_valid(dBus_cmd_valid), .dBus_cmd_payload_wr(dBus_cmd_payload_wr), .dBus_cmd_payload_address(dBus_cmd_payload_address), .dBus_cmd_payload_data(dBus_cmd_payload_data), .dBus_cmd_payload_size(dBus_cmd_payload_size), .dBus_cmd_ready(dBus_cmd_ready), .dBus_rsp_ready(dBus_rsp_ready), .dBus_rsp_data(dBus_rsp_data), .dBus_rsp_error(1'b0), `RVFI_CONN ); endmodule ================================================ FILE: cores/VexRiscv/wrapper.sv ================================================ module rvfi_wrapper ( input clock, input reset, `RVFI_OUTPUTS ); (* keep *) wire trap; (* keep *) wire iBus_cmd_valid; (* keep *) wire [31:0] iBus_cmd_payload_pc; (* keep *) `rvformal_rand_reg iBus_cmd_ready; (* keep *) `rvformal_rand_reg iBus_rsp_ready; (* keep *) `rvformal_rand_reg [31:0] iBus_rsp_inst; (* keep *) wire dBus_cmd_valid; (* keep *) wire dBus_cmd_payload_wr; (* keep *) wire [31:0] dBus_cmd_payload_address; (* keep *) wire [31:0] dBus_cmd_payload_data; (* keep *) wire [1:0] dBus_cmd_payload_size; (* keep *) `rvformal_rand_reg dBus_cmd_ready; (* keep *) `rvformal_rand_reg dBus_rsp_ready; (* keep *) `rvformal_rand_reg [31:0] dBus_rsp_data; VexRiscv uut ( .clk (clock ), .reset (reset ), .iBus_cmd_valid (iBus_cmd_valid), .iBus_cmd_ready (iBus_cmd_ready), .iBus_cmd_payload_pc (iBus_cmd_payload_pc ), .iBus_rsp_valid(iBus_rsp_ready), .iBus_rsp_payload_inst(iBus_rsp_inst), .iBus_rsp_payload_error(1'b0), .dBus_cmd_valid(dBus_cmd_valid), .dBus_cmd_payload_wr(dBus_cmd_payload_wr), .dBus_cmd_payload_address(dBus_cmd_payload_address), .dBus_cmd_payload_data(dBus_cmd_payload_data), .dBus_cmd_payload_size(dBus_cmd_payload_size), .dBus_cmd_ready(dBus_cmd_ready), .dBus_rsp_ready(dBus_rsp_ready), .dBus_rsp_data(dBus_rsp_data), .dBus_rsp_error(1'b0), `RVFI_CONN ); `ifdef VEXRISCV_FAIRNESS (* keep *) reg [2:0] iBusCmdPendingCycles = 0; (* keep *) reg [2:0] iBusRspPendingCycles = 0; (* keep *) reg iBusRspPendingValid = 0; (* keep *) reg [2:0] dBusCmdPendingCycles = 0; (* keep *) reg [2:0] dBusRspPendingCycles = 0; (* keep *) reg dBusRspPendingValid = 0; always @(posedge clock) begin if(iBus_cmd_valid && !iBus_cmd_ready) begin iBusCmdPendingCycles <= iBusCmdPendingCycles + 1; end else begin iBusCmdPendingCycles <= 0; end if(iBusRspPendingValid <= 1) begin iBusRspPendingCycles <= iBusRspPendingCycles + 1; end if(iBus_rsp_ready) begin iBusRspPendingValid <= 0; iBusRspPendingCycles <= 0; end if(iBus_cmd_valid && iBus_cmd_ready && !dBus_cmd_payload_wr) begin iBusRspPendingValid <= 1; end if(dBus_cmd_valid && !dBus_cmd_ready) begin dBusCmdPendingCycles <= dBusCmdPendingCycles + 1; end else begin dBusCmdPendingCycles <= 0; end if(dBusRspPendingValid <= 1) begin dBusRspPendingCycles <= dBusRspPendingCycles + 1; end if(dBus_rsp_ready) begin dBusRspPendingValid <= 0; dBusRspPendingCycles <= 0; end if(dBus_cmd_valid && dBus_cmd_ready && !dBus_cmd_payload_wr) begin dBusRspPendingValid <= 1; end restrict property(~rvfi_trap && dBusCmdPendingCycles < 4 && dBusRspPendingCycles < 4 && iBusCmdPendingCycles < 4 && iBusRspPendingCycles < 4); end `endif endmodule ================================================ FILE: cores/nerv/.gitignore ================================================ /checks/ /cexdata/ /testbench.vcd /firmware.elf /firmware.hex /disasm.o /disasm.s /testbench /gtkwave.log ================================================ FILE: cores/nerv/COPYING ================================================ NERV -- Naive Educational RISC-V Processor Copyright (C) 2020 Claire Xenia Wolf Copyright (C) 2020 N. Engelhardt Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ================================================ FILE: cores/nerv/Makefile ================================================ # NERV -- Naive Educational RISC-V Processor # # Copyright (C) 2020 N. Engelhardt # Copyright (C) 2020 Claire Xenia Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. TOOLCHAIN_PREFIX?=riscv64-unknown-elf- RISCV_ARCH?=rv32i$(shell $(TOOLCHAIN_PREFIX)as -march=rv32i_zicsr --dump-config 2>/dev/null && echo _zicsr) test: firmware.hex testbench vvp -N testbench +vcd firmware.elf: firmware.s vectors.s firmware.c $(TOOLCHAIN_PREFIX)gcc -march=$(RISCV_ARCH) -mabi=ilp32 -Os -Wall -Wextra -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $^ firmware.hex: firmware.elf $(TOOLCHAIN_PREFIX)objcopy -O verilog $< $@ testbench: testbench.sv nerv.sv iverilog -g2012 -o testbench -D STALL -D NERV_DBGREGS testbench.sv nerv.sv checks: python3 ../../checks/genchecks.py $(MAKE) -C checks check: checks bash cexdata.sh cat cexdata/warnings.txt cat cexdata/status.txt show: gtkwave testbench.vcd testbench.gtkw >> gtkwave.log 2>&1 & trace: gtkwave cexdata/checks_$(TRACE_CHECK)_ch0.vcd trace.gtkw >> gtkwave.log 2>&1 & clean: rm -rf firmware.elf firmware.hex testbench testbench.vcd gtkwave.log rm -rf disasm.o disasm.s checks/ cexdata/ ================================================ FILE: cores/nerv/README.md ================================================ NERV - Naive Educational RISC-V Processor ========================================= NERV is a very simple single-stage RV32I processor. It is equipped with an [RVFI interface](https://github.com/yosyshq/riscv-formal/blob/master/docs/rvfi.md) and is formally verified. ![system diagram](NERV.png) Running the simulation testbench -------------------------------- ``` git clone https://github.com/yosyshq/nerv.git cd nerv make ``` Running the riscv-formal testbench ---------------------------------- ``` git clone https://github.com/yosyshq/riscv-formal.git cd riscv-formal/cores/nerv make -j8 check ``` Updating riscv-formal's included nerv core ------------------------------------------ From root `riscv-formal` directory: ``` git subtree pull --prefix cores/nerv git@github.com:YosysHQ/nerv.git main --squash ``` Updating upstream nerv with changes from riscv-formal ----------------------------------------------------- From root `riscv-formal` directory: ``` git subtree push --prefix cores/nerv git@github.com:YosysHQ/nerv.git main ``` iCEBreaker SOC example ---------------------- See the [iCEBreaker SOC README](examples/icebreaker/README.md) ================================================ FILE: cores/nerv/axi_cache/.gitignore ================================================ /SVA-AXI4-FVIP /checks_axi /checks_internal *.vcd *.hex *.elf testbench_internal testbench_axi ================================================ FILE: cores/nerv/axi_cache/Makefile ================================================ # NERV -- Naive Educational RISC-V Processor # # Copyright (C) 2020 N. Engelhardt # Copyright (C) 2020 Claire Xenia Wolf # Copyright (C) 2023 Jannis Harder # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. TOOLCHAIN_PREFIX?=riscv64-unknown-elf- TESTBENCH_DEFINES?=-D NERV_DBGREGS -D NERV_CSR TESTBENCH_ARGS?=+vcd CHECKS?= CLONE?=0 RISCV_ARCH?=rv32i$(shell $(TOOLCHAIN_PREFIX)as -march=rv32i_zicsr --dump-config 2>/dev/null && echo _zicsr) CACHE_SOURCES:=nerv_axi_cache.sv nerv_axi_cache_icache.sv nerv_axi_cache_dcache.sv .PHONY: test_internal test_axi verify_axi verify_axi_cover checks_internal checks_axi all test_internal: firmware.hex testbench_internal vvp -N testbench_internal $(TESTBENCH_ARGS) test_axi: firmware.hex testbench_axi vvp -N testbench_axi $(TESTBENCH_ARGS) verify_axi: SVA-AXI4-FVIP verify_axi.sby verify_axi.sv sby -f verify_axi.sby prove verify_axi_cover: SVA-AXI4-FVIP verify_axi.sby verify_axi.sv sby -f verify_axi.sby cover firmware.elf: ../firmware.s ../vectors.s firmware.c $(TOOLCHAIN_PREFIX)gcc -march=$(RISCV_ARCH) -mabi=ilp32 -Os -Wall -Wextra -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $^ firmware.hex: firmware.elf $(TOOLCHAIN_PREFIX)objcopy -O verilog $< $@ testbench_internal: testbench_internal.sv ../nerv.sv $(CACHE_SOURCES) iverilog -stestbench -g2012 -o $@ $(TESTBENCH_DEFINES) $^ testbench_axi: testbench_axi.sv ../nerv.sv $(CACHE_SOURCES) axi_ram.v iverilog -stestbench -g2012 -o $@ $(TESTBENCH_DEFINES) $^ ifeq ($(CLONE),1) SVA-AXI4-FVIP: git clone https://github.com/YosysHQ-GmbH/SVA-AXI4-FVIP else SVA-AXI4-FVIP: @echo "SVA-AXI4-FVIP repository not found, use 'make SVA-AXI4-FVIP CLONE=1' to clone from GitHub" @echo "alternatively manually clone or symlink a clone of https://github.com/YosysHQ-GmbH/SVA-AXI4-FVIP" @exit 1 endif checks_internal: cd .. && python3 ../../checks/genchecks.py axi_cache/checks_internal $(MAKE) -C checks_internal $(CHECKS) checks_axi: cd .. && python3 ../../checks/genchecks.py axi_cache/checks_axi $(MAKE) -C checks_axi $(CHECKS) all: test_internal test_axi verify_axi verify_axi_cover checks_internal checks_axi clean: rm -rf firmware.elf firmware.hex rm -rf testbench_internal testbench_internal.vcd rm -rf testbench_axi testbench_axi.vcd rm -rf verify_axi_prove verify_axi_cover rm -rf checks_internal checks_axi ================================================ FILE: cores/nerv/axi_cache/README.md ================================================ # Caches for NERV using an AXI interface ## Contents ### Cache Implementation Split across [`nerv_axi_cache.sv`](./nerv_axi_cache.sv), [`nerv_axi_cache_icache.sv`](./nerv_axi_cache_icache.sv) and [`nerv_axi_cache_dcache.sv`](./nerv_axi_cache_dcache.sv). The top-level module for the cache is `nerv_axi_cache` in [`nerv_axi_cache.sv`](./nerv_axi_cache.sv). Module parameters are documented in the comment above that module. ### Testbenches The testbenches were tested using `iverilog`, use `make test_axi` and `make test_internal` for running them. There is [`testbench_internal.sv`](./testbench_internal.sv) which uses the cache-internal bus instead of the AXI interface and [`testbench_axi.sv`](./testbench_axi.sv) which uses the full AXI-interfacing cache together with a third-party open-source AXI4 memory implementation in [`axi_ram.v`](./axi_ram.v) (Taken from [Alex Forencich's "Verilog AXI Components"](https://github.com/alexforencich/verilog-axi)). These testbenches also uses a different firmware than the top-level NERV testbench to actually exercise the cache a bit. ### Formal Verification Using SVA AXI Properties The caches' AXI interface is formally verified using the [YosysHQ SVA AXI Properties](https://github.com/YosysHQ-GmbH/SVA-AXI4-FVIP). Use `make verify_axi` to run this verification. The verification is setup in [`verify_axi.sby`](./verify_axi.sby) and [`verify_axi.sv`](./verify_axi.sv). Note that SVA-AXI4-FVIP requires SVA support and thus this part requires the Tabby CAD Suite and does not work with the OSS CAD Suite. This limitation does not apply to verifying NERV using riscv-formal. ### RISC-V Formal Bus Checks The caches' correct operation when used together with the NERV core is formally verified using riscv-formal's bus memory checks. This can be done for the complete caches using the AXI interface, using `make checks_axi`, as well as for the cache internal interface using `make checks_internal`. The riscv-formal configurations are in [`checks_axi.cfg`](./checks_axi.cfg) and [`checks_internal.cfg`](./checks_internal.cfg). The RVFI wrappers are [`wrapper_axi.sv`](./wrapper_axi.sv) and [`wrapper_internal.sv`](./wrapper_internal.sv). The RVFI wrapper for the AXI setup also uses a modified version of [`axi_ram.v`](./axi_ram.v) in which the actual memory is removed and read data is unconstrained. This modified version is contained in [`axi_ram_abstraction.v`](./axi_ram_abstraction.v). ================================================ FILE: cores/nerv/axi_cache/axi_ram.v ================================================ // Modified to comment out the timescale directive /* Copyright (c) 2018 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ // Language: Verilog 2001 `resetall // `timescale 1ns / 1ps `default_nettype none /* * AXI4 RAM */ module axi_ram # ( // Width of data bus in bits parameter DATA_WIDTH = 32, // Width of address bus in bits parameter ADDR_WIDTH = 16, // Width of wstrb (width of data bus in words) parameter STRB_WIDTH = (DATA_WIDTH/8), // Width of ID signal parameter ID_WIDTH = 8, // Extra pipeline register on output parameter PIPELINE_OUTPUT = 0 ) ( input wire clk, input wire rst, input wire [ID_WIDTH-1:0] s_axi_awid, input wire [ADDR_WIDTH-1:0] s_axi_awaddr, input wire [7:0] s_axi_awlen, input wire [2:0] s_axi_awsize, input wire [1:0] s_axi_awburst, input wire s_axi_awlock, input wire [3:0] s_axi_awcache, input wire [2:0] s_axi_awprot, input wire s_axi_awvalid, output wire s_axi_awready, input wire [DATA_WIDTH-1:0] s_axi_wdata, input wire [STRB_WIDTH-1:0] s_axi_wstrb, input wire s_axi_wlast, input wire s_axi_wvalid, output wire s_axi_wready, output wire [ID_WIDTH-1:0] s_axi_bid, output wire [1:0] s_axi_bresp, output wire s_axi_bvalid, input wire s_axi_bready, input wire [ID_WIDTH-1:0] s_axi_arid, input wire [ADDR_WIDTH-1:0] s_axi_araddr, input wire [7:0] s_axi_arlen, input wire [2:0] s_axi_arsize, input wire [1:0] s_axi_arburst, input wire s_axi_arlock, input wire [3:0] s_axi_arcache, input wire [2:0] s_axi_arprot, input wire s_axi_arvalid, output wire s_axi_arready, output wire [ID_WIDTH-1:0] s_axi_rid, output wire [DATA_WIDTH-1:0] s_axi_rdata, output wire [1:0] s_axi_rresp, output wire s_axi_rlast, output wire s_axi_rvalid, input wire s_axi_rready ); parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(STRB_WIDTH); parameter WORD_WIDTH = STRB_WIDTH; parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH; // bus width assertions initial begin if (WORD_SIZE * STRB_WIDTH != DATA_WIDTH) begin $error("Error: AXI data width not evenly divisble (instance %m)"); $finish; end if (2**$clog2(WORD_WIDTH) != WORD_WIDTH) begin $error("Error: AXI word width must be even power of two (instance %m)"); $finish; end end localparam [0:0] READ_STATE_IDLE = 1'd0, READ_STATE_BURST = 1'd1; reg [0:0] read_state_reg = READ_STATE_IDLE, read_state_next; localparam [1:0] WRITE_STATE_IDLE = 2'd0, WRITE_STATE_BURST = 2'd1, WRITE_STATE_RESP = 2'd2; reg [1:0] write_state_reg = WRITE_STATE_IDLE, write_state_next; reg mem_wr_en; reg mem_rd_en; reg [ID_WIDTH-1:0] read_id_reg = {ID_WIDTH{1'b0}}, read_id_next; reg [ADDR_WIDTH-1:0] read_addr_reg = {ADDR_WIDTH{1'b0}}, read_addr_next; reg [7:0] read_count_reg = 8'd0, read_count_next; reg [2:0] read_size_reg = 3'd0, read_size_next; reg [1:0] read_burst_reg = 2'd0, read_burst_next; reg [ID_WIDTH-1:0] write_id_reg = {ID_WIDTH{1'b0}}, write_id_next; reg [ADDR_WIDTH-1:0] write_addr_reg = {ADDR_WIDTH{1'b0}}, write_addr_next; reg [7:0] write_count_reg = 8'd0, write_count_next; reg [2:0] write_size_reg = 3'd0, write_size_next; reg [1:0] write_burst_reg = 2'd0, write_burst_next; reg s_axi_awready_reg = 1'b0, s_axi_awready_next; reg s_axi_wready_reg = 1'b0, s_axi_wready_next; reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}}, s_axi_bid_next; reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next; reg s_axi_arready_reg = 1'b0, s_axi_arready_next; reg [ID_WIDTH-1:0] s_axi_rid_reg = {ID_WIDTH{1'b0}}, s_axi_rid_next; reg [DATA_WIDTH-1:0] s_axi_rdata_reg = {DATA_WIDTH{1'b0}}, s_axi_rdata_next; reg s_axi_rlast_reg = 1'b0, s_axi_rlast_next; reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next; reg [ID_WIDTH-1:0] s_axi_rid_pipe_reg = {ID_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] s_axi_rdata_pipe_reg = {DATA_WIDTH{1'b0}}; reg s_axi_rlast_pipe_reg = 1'b0; reg s_axi_rvalid_pipe_reg = 1'b0; // (* RAM_STYLE="BLOCK" *) reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0]; wire [VALID_ADDR_WIDTH-1:0] s_axi_awaddr_valid = s_axi_awaddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH); wire [VALID_ADDR_WIDTH-1:0] s_axi_araddr_valid = s_axi_araddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH); wire [VALID_ADDR_WIDTH-1:0] read_addr_valid = read_addr_reg >> (ADDR_WIDTH - VALID_ADDR_WIDTH); wire [VALID_ADDR_WIDTH-1:0] write_addr_valid = write_addr_reg >> (ADDR_WIDTH - VALID_ADDR_WIDTH); assign s_axi_awready = s_axi_awready_reg; assign s_axi_wready = s_axi_wready_reg; assign s_axi_bid = s_axi_bid_reg; assign s_axi_bresp = 2'b00; assign s_axi_bvalid = s_axi_bvalid_reg; assign s_axi_arready = s_axi_arready_reg; assign s_axi_rid = PIPELINE_OUTPUT ? s_axi_rid_pipe_reg : s_axi_rid_reg; assign s_axi_rdata = PIPELINE_OUTPUT ? s_axi_rdata_pipe_reg : s_axi_rdata_reg; assign s_axi_rresp = 2'b00; assign s_axi_rlast = PIPELINE_OUTPUT ? s_axi_rlast_pipe_reg : s_axi_rlast_reg; assign s_axi_rvalid = PIPELINE_OUTPUT ? s_axi_rvalid_pipe_reg : s_axi_rvalid_reg; integer i, j; initial begin // two nested loops for smaller number of iterations per loop // workaround for synthesizer complaints about large loop counts for (i = 0; i < 2**VALID_ADDR_WIDTH; i = i + 2**(VALID_ADDR_WIDTH/2)) begin for (j = i; j < i + 2**(VALID_ADDR_WIDTH/2); j = j + 1) begin mem[j] = 0; end end end always @* begin write_state_next = WRITE_STATE_IDLE; mem_wr_en = 1'b0; write_id_next = write_id_reg; write_addr_next = write_addr_reg; write_count_next = write_count_reg; write_size_next = write_size_reg; write_burst_next = write_burst_reg; s_axi_awready_next = 1'b0; s_axi_wready_next = 1'b0; s_axi_bid_next = s_axi_bid_reg; s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_bready; case (write_state_reg) WRITE_STATE_IDLE: begin s_axi_awready_next = 1'b1; if (s_axi_awready && s_axi_awvalid) begin write_id_next = s_axi_awid; write_addr_next = s_axi_awaddr; write_count_next = s_axi_awlen; write_size_next = s_axi_awsize < $clog2(STRB_WIDTH) ? s_axi_awsize : $clog2(STRB_WIDTH); write_burst_next = s_axi_awburst; s_axi_awready_next = 1'b0; s_axi_wready_next = 1'b1; write_state_next = WRITE_STATE_BURST; end else begin write_state_next = WRITE_STATE_IDLE; end end WRITE_STATE_BURST: begin s_axi_wready_next = 1'b1; if (s_axi_wready && s_axi_wvalid) begin mem_wr_en = 1'b1; if (write_burst_reg != 2'b00) begin write_addr_next = write_addr_reg + (1 << write_size_reg); end write_count_next = write_count_reg - 1; if (write_count_reg > 0) begin write_state_next = WRITE_STATE_BURST; end else begin s_axi_wready_next = 1'b0; if (s_axi_bready || !s_axi_bvalid) begin s_axi_bid_next = write_id_reg; s_axi_bvalid_next = 1'b1; s_axi_awready_next = 1'b1; write_state_next = WRITE_STATE_IDLE; end else begin write_state_next = WRITE_STATE_RESP; end end end else begin write_state_next = WRITE_STATE_BURST; end end WRITE_STATE_RESP: begin if (s_axi_bready || !s_axi_bvalid) begin s_axi_bid_next = write_id_reg; s_axi_bvalid_next = 1'b1; s_axi_awready_next = 1'b1; write_state_next = WRITE_STATE_IDLE; end else begin write_state_next = WRITE_STATE_RESP; end end endcase end always @(posedge clk) begin write_state_reg <= write_state_next; write_id_reg <= write_id_next; write_addr_reg <= write_addr_next; write_count_reg <= write_count_next; write_size_reg <= write_size_next; write_burst_reg <= write_burst_next; s_axi_awready_reg <= s_axi_awready_next; s_axi_wready_reg <= s_axi_wready_next; s_axi_bid_reg <= s_axi_bid_next; s_axi_bvalid_reg <= s_axi_bvalid_next; for (i = 0; i < WORD_WIDTH; i = i + 1) begin if (mem_wr_en & s_axi_wstrb[i]) begin mem[write_addr_valid][WORD_SIZE*i +: WORD_SIZE] <= s_axi_wdata[WORD_SIZE*i +: WORD_SIZE]; end end if (rst) begin write_state_reg <= WRITE_STATE_IDLE; s_axi_awready_reg <= 1'b0; s_axi_wready_reg <= 1'b0; s_axi_bvalid_reg <= 1'b0; end end always @* begin read_state_next = READ_STATE_IDLE; mem_rd_en = 1'b0; s_axi_rid_next = s_axi_rid_reg; s_axi_rlast_next = s_axi_rlast_reg; s_axi_rvalid_next = s_axi_rvalid_reg && !(s_axi_rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg)); read_id_next = read_id_reg; read_addr_next = read_addr_reg; read_count_next = read_count_reg; read_size_next = read_size_reg; read_burst_next = read_burst_reg; s_axi_arready_next = 1'b0; case (read_state_reg) READ_STATE_IDLE: begin s_axi_arready_next = 1'b1; if (s_axi_arready && s_axi_arvalid) begin read_id_next = s_axi_arid; read_addr_next = s_axi_araddr; read_count_next = s_axi_arlen; read_size_next = s_axi_arsize < $clog2(STRB_WIDTH) ? s_axi_arsize : $clog2(STRB_WIDTH); read_burst_next = s_axi_arburst; s_axi_arready_next = 1'b0; read_state_next = READ_STATE_BURST; end else begin read_state_next = READ_STATE_IDLE; end end READ_STATE_BURST: begin if (s_axi_rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg) || !s_axi_rvalid_reg) begin mem_rd_en = 1'b1; s_axi_rvalid_next = 1'b1; s_axi_rid_next = read_id_reg; s_axi_rlast_next = read_count_reg == 0; if (read_burst_reg != 2'b00) begin read_addr_next = read_addr_reg + (1 << read_size_reg); end read_count_next = read_count_reg - 1; if (read_count_reg > 0) begin read_state_next = READ_STATE_BURST; end else begin s_axi_arready_next = 1'b1; read_state_next = READ_STATE_IDLE; end end else begin read_state_next = READ_STATE_BURST; end end endcase end always @(posedge clk) begin read_state_reg <= read_state_next; read_id_reg <= read_id_next; read_addr_reg <= read_addr_next; read_count_reg <= read_count_next; read_size_reg <= read_size_next; read_burst_reg <= read_burst_next; s_axi_arready_reg <= s_axi_arready_next; s_axi_rid_reg <= s_axi_rid_next; s_axi_rlast_reg <= s_axi_rlast_next; s_axi_rvalid_reg <= s_axi_rvalid_next; if (mem_rd_en) begin s_axi_rdata_reg <= mem[read_addr_valid]; end if (!s_axi_rvalid_pipe_reg || s_axi_rready) begin s_axi_rid_pipe_reg <= s_axi_rid_reg; s_axi_rdata_pipe_reg <= s_axi_rdata_reg; s_axi_rlast_pipe_reg <= s_axi_rlast_reg; s_axi_rvalid_pipe_reg <= s_axi_rvalid_reg; end if (rst) begin read_state_reg <= READ_STATE_IDLE; s_axi_arready_reg <= 1'b0; s_axi_rvalid_reg <= 1'b0; s_axi_rvalid_pipe_reg <= 1'b0; end end endmodule `resetall ================================================ FILE: cores/nerv/axi_cache/checks_axi.cfg ================================================ # NERV -- Naive Educational RISC-V Processor # # Copyright (C) 2020 Claire Xenia Wolf # Copyright (C) 2023 Jannis Harder # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. [options] isa rv32i nbus 2 buslen 32 mode bmc solver boolector [depth] insn 16 fault 16 causal_mem 1 16 causal_io 1 16 bus_imem 1 16 bus_imem_fault 1 16 bus_dmem 1 16 bus_dmem_fault 1 16 bus_dmem_io_read 1 16 bus_dmem_io_read_fault 1 16 bus_dmem_io_write 1 16 bus_dmem_io_write_fault 1 16 bus_dmem_io_order 1 16 [csrs] mcause [defines] `define YOSYS // Hotfix for older Tabby CAD Releases `define NERV_RVFI `define NERV_FAULT `define RISCV_FORMAL_ALIGNED_MEM `define RISCV_FORMAL_MEM_FAULT `define RISCV_FORMAL_FAULT_WIDTH 8 // The cache makes faults more coarse than single RVFI_BUS transfers `define RISCV_FORMAL_IOADDR(addr) addr[31:16] == 16'h1234 [defines liveness] `define NERV_FAIRNESS [verilog-files] @basedir@/bus/rvfi_bus_util.sv @basedir@/bus/rvfi_bus_axi4.sv @basedir@/cores/@core@/axi_cache/wrapper_axi.sv @basedir@/cores/@core@/@core@.sv @basedir@/cores/@core@/axi_cache/nerv_axi_cache.sv @basedir@/cores/@core@/axi_cache/nerv_axi_cache_icache.sv @basedir@/cores/@core@/axi_cache/nerv_axi_cache_dcache.sv ================================================ FILE: cores/nerv/axi_cache/checks_internal.cfg ================================================ # NERV -- Naive Educational RISC-V Processor # # Copyright (C) 2020 Claire Xenia Wolf # Copyright (C) 2023 Jannis Harder # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. [options] isa rv32i nbus 3 buslen 256 mode bmc solver boolector [depth] bus_imem 1 14 bus_imem_fault 1 14 bus_dmem 1 14 bus_dmem_fault 1 14 [csrs] mcause [defines] `define YOSYS // Hotfix for older Tabby CAD Releases `define NERV_RVFI `define NERV_FAULT `define RISCV_FORMAL_ALIGNED_MEM `define RISCV_FORMAL_MEM_FAULT [defines liveness] `define NERV_FAIRNESS [verilog-files] @basedir@/cores/@core@/axi_cache/wrapper_internal.sv @basedir@/cores/@core@/@core@.sv @basedir@/cores/@core@/axi_cache/nerv_axi_cache_icache.sv @basedir@/cores/@core@/axi_cache/nerv_axi_cache_dcache.sv ================================================ FILE: cores/nerv/axi_cache/firmware.c ================================================ /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 Claire Xenia Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ void putc(int c) { volatile char *p = (void*)0x02000000; *p = c; } void do_exit() { volatile unsigned *p = (void*)0x02000000; *p = 0x100; } void puts(char *s) { while (*s) putc(*(s++)); } #define SIEVE_SIZE 128 void print_num(unsigned p) { char force = 0; char c; c = '0'; while (p >= 100) p -= 100, c++; if (c != '0' || force) putc(c), force = 1; c = '0'; while (p >= 10) p -= 10, c++; if (c != '0' || force) putc(c), force = 1; putc('0' + p); putc('\n'); } int main() { char sieve[SIEVE_SIZE]; puts("Some Primes:\n"); for (unsigned i = 2; i < SIEVE_SIZE; i++) sieve[i] = 1; for (unsigned p = 2, p2 = 4; p < SIEVE_SIZE; p += 1, p2 += (p << 1) - 1) { if (sieve[p]) { print_num(p); if (p2 < SIEVE_SIZE) { for (unsigned i = p2; i < SIEVE_SIZE; i += p) { sieve[i] = 0; } } } } do_exit(); return 0; } ================================================ FILE: cores/nerv/axi_cache/nerv_axi_cache.sv ================================================ // Direct mapped, write-back/write-allocate AXI cache for the NERV core. // // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. `default_nettype none // The complete AXI cache. // // Provides NERV's native `imem_*` and `dmem_*` interface on one side and an // AXI4 manager interface on the other side. // // The NERV core expects single cycle accesses for both instruction and data // memory, and has a single `stall` signal that needs to be asserted to halt // the core when accesses take logner. To support multiplexing between the // cache and uncached memory/devices on the NERV side, this cache provides a // `stall` output and a `stalled` input. The `stalled` signal should be // connected to the same signal as NERV's `stall` input while NERV's `stall` // input should be an or of the cache's `stall` output with any other external // stall signal. // // ## Parameters // // This uses the convention that `_WIDTH` = `8 << _SIZE`. // // * `ADDRESS_WIDTH`: Address bit width for both AXI and NERV's interface. NERV // only supports 32 bit, but the cache is generic. // // * `DATA_SIZE`: Data size for NERV's interface, NERV only supports 2 // (corresponding to 32-bit). // // * `INSN_SIZE`: Instruction size for NERV's interface, NERV only supports 2 // (corresponding to 32-bit). // // * `LINE_SIZE`: Size of a cache line, needs to be larger than the maximum of // `DATA_SIZE` and `INSN_SIZE` (corresponding to a cache line that is at // least twice as wide as the NERV side accesses). // // * `ICACHE_INDEX_SIZE`, `DCACHE_INDEX_SIZE`: How many address bits are used // to index the instruction/data cache memory. The size of the corresponding // cache is `1 << INDEX_SIZE` cache lines. // // * `AXI_DATA_WIDTH`: Data width of the AXI interface, independent from the // the widths used for NERV's interface. // // * `AXI_ID_WIDTH`: ID width for the AXI interface, doesn't affect NERV's // interface. // // * `AXI_IMEM_ID`, `AXI_DMEM_ID`: which AXI ID to use for instruction and data // accesses. Can be the same. module nerv_axi_cache #( parameter ADDRESS_WIDTH = 32, parameter DATA_SIZE = 2, parameter INSN_SIZE = 2, parameter LINE_SIZE = 3, parameter ICACHE_INDEX_SIZE = 3, parameter DCACHE_INDEX_SIZE = 3, parameter AXI_DATA_WIDTH = 32, parameter AXI_ID_WIDTH = 1, parameter AXI_IMEM_ID = 0, parameter AXI_DMEM_ID = 1, localparam INSN_WIDTH = 8 << INSN_SIZE, localparam DATA_WIDTH = 8 << DATA_SIZE, localparam LINE_WIDTH = 8 << LINE_SIZE, localparam AXI_ADDRESS_WIDTH = ADDRESS_WIDTH, localparam AXI_AWUSER_WIDTH = 1, localparam AXI_WUSER_WIDTH = 1, localparam AXI_BUSER_WIDTH = 1, localparam AXI_ARUSER_WIDTH = 1, localparam AXI_RUSER_WIDTH = 1, localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8 ) ( input wire clock, input wire reset, input wire stalled, output var stall, // NERV's instruction memory interface input wire [ADDRESS_WIDTH-1:0] imem_addr, output var [INSN_WIDTH-1:0] imem_data, output var imem_fault, // NERV's data memory interface input wire dmem_valid, input wire [ADDRESS_WIDTH-1:0] dmem_addr, input wire [DATA_WIDTH/8-1:0] dmem_wstrb, input wire [DATA_WIDTH-1:0] dmem_wdata, output var [DATA_WIDTH-1:0] dmem_rdata, output var dmem_fault, // Bypass the data cache for this access. input wire dmem_io, // This can also be wired up as a condition on dmem_addr to implement fixed // uncached IO memory regions. // Write Address Channel (AW) output var [AXI_ID_WIDTH-1:0] axi_awid, output var [AXI_ADDRESS_WIDTH-1:0] axi_awaddr, output var [3:0] axi_awregion, // not used, default value output var [7:0] axi_awlen, output var [2:0] axi_awsize, output var [1:0] axi_awburst, output var axi_awlock, // not used, default value output var [3:0] axi_awcache, // not used, fixed value output var [2:0] axi_awprot, output var [3:0] axi_awqos, // not used, default value output var [AXI_AWUSER_WIDTH-1:0] axi_awuser, // not used, all zero output var axi_awvalid, input wire axi_awready, // Write Data Channel (W) output var [AXI_DATA_WIDTH-1:0] axi_wdata, output var [AXI_STRB_WIDTH-1:0] axi_wstrb, output var axi_wlast, output var [AXI_WUSER_WIDTH-1:0] axi_wuser, // not used, all zero output var axi_wvalid, input wire axi_wready, // Write Response Channel (B) input wire [AXI_ID_WIDTH-1:0] axi_bid, // ignored, cache does not use overlapping transactions input wire [1:0] axi_bresp, // ignored, cache does not handle faults during writeback input wire [AXI_BUSER_WIDTH-1:0] axi_buser, // ignored input wire axi_bvalid, output var axi_bready, // Read Address Channel (AR) output var [AXI_ID_WIDTH-1:0] axi_arid, output var [AXI_ADDRESS_WIDTH-1:0] axi_araddr, output var [3:0] axi_arregion, // not used, default value output var [7:0] axi_arlen, output var [2:0] axi_arsize, output var [1:0] axi_arburst, output var axi_arlock, // not used, default value output var [3:0] axi_arcache, // not used, fixed value output var [2:0] axi_arprot, output var [3:0] axi_arqos, // not used, default value output var [AXI_ARUSER_WIDTH-1:0] axi_aruser, // not used, all zero output var axi_arvalid, input wire axi_arready, // Read Data Channel (R) input wire [AXI_ID_WIDTH-1:0] axi_rid, // ignored, cache does not use overlapping transactions input wire [AXI_DATA_WIDTH-1:0] axi_rdata, input wire [1:0] axi_rresp, input wire axi_rlast, input wire [AXI_RUSER_WIDTH-1:0] axi_ruser, // ignored input wire axi_rvalid, output var axi_rready ); logic [ADDRESS_WIDTH-1:0] imem_req_addr; logic imem_req_valid; logic [LINE_WIDTH-1:0] imem_res_data; logic imem_res_fault; logic imem_res_valid; logic [ADDRESS_WIDTH-1:0] dmem_req_r_addr; logic dmem_req_r_valid; logic [LINE_WIDTH-1:0] dmem_res_r_data; logic dmem_res_r_fault; logic dmem_res_r_valid; logic [ADDRESS_WIDTH-1:0] dmem_req_w_addr; logic [LINE_WIDTH-1:0] dmem_req_w_data; logic dmem_req_w_valid; logic dmem_res_w_fault; logic dmem_res_w_valid; logic [ADDRESS_WIDTH-1:0] dmem_req_ur_addr; logic dmem_req_ur_valid; logic [DATA_WIDTH-1:0] dmem_res_ur_data; logic dmem_res_ur_fault; logic dmem_res_ur_valid; logic [ADDRESS_WIDTH-1:0] dmem_req_uw_addr; logic [DATA_WIDTH-1:0] dmem_req_uw_data; logic [DATA_WIDTH/8-1:0] dmem_req_uw_strb; logic dmem_req_uw_valid; logic dmem_res_uw_fault; logic dmem_res_uw_valid; logic icache_stall, dcache_stall, io_stall; assign stall = icache_stall || dcache_stall || io_stall; logic [DATA_WIDTH-1:0] dmem_rdata_cache; logic dmem_fault_cache; logic [DATA_WIDTH-1:0] dmem_rdata_io; logic dmem_fault_io; logic last_dmem_io; always @(posedge clock) begin if (!stalled && dmem_valid) begin last_dmem_io <= dmem_io; end end assign dmem_rdata = last_dmem_io ? dmem_rdata_io : dmem_rdata_cache; assign dmem_fault = last_dmem_io ? dmem_fault_io : dmem_fault_cache; nerv_axi_cache_axi #( .ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_SIZE(DATA_SIZE), .INSN_SIZE(INSN_SIZE), .LINE_SIZE(LINE_SIZE), .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .AXI_ID_WIDTH(AXI_ID_WIDTH), .AXI_IMEM_ID(AXI_IMEM_ID), .AXI_DMEM_ID(AXI_DMEM_ID) ) axi ( .clock(clock), .reset(reset), .imem_req_addr(imem_req_addr), .imem_req_valid(imem_req_valid), .imem_res_data(imem_res_data), .imem_res_fault(imem_res_fault), .imem_res_valid(imem_res_valid), .dmem_req_r_addr(dmem_req_r_addr), .dmem_req_r_valid(dmem_req_r_valid), .dmem_res_r_data(dmem_res_r_data), .dmem_res_r_fault(dmem_res_r_fault), .dmem_res_r_valid(dmem_res_r_valid), .dmem_req_w_addr(dmem_req_w_addr), .dmem_req_w_data(dmem_req_w_data), .dmem_req_w_valid(dmem_req_w_valid), .dmem_res_w_fault(dmem_res_w_fault), .dmem_res_w_valid(dmem_res_w_valid), .dmem_req_ur_addr(dmem_req_ur_addr), .dmem_req_ur_valid(dmem_req_ur_valid), .dmem_res_ur_data(dmem_res_ur_data), .dmem_res_ur_fault(dmem_res_ur_fault), .dmem_res_ur_valid(dmem_res_ur_valid), .dmem_req_uw_addr(dmem_req_uw_addr), .dmem_req_uw_data(dmem_req_uw_data), .dmem_req_uw_strb(dmem_req_uw_strb), .dmem_req_uw_valid(dmem_req_uw_valid), .dmem_res_uw_fault(dmem_res_uw_fault), .dmem_res_uw_valid(dmem_res_uw_valid), // Write Address Channel (AW) .axi_awid(axi_awid), .axi_awaddr(axi_awaddr), .axi_awregion(axi_awregion), .axi_awlen(axi_awlen), .axi_awsize(axi_awsize), .axi_awburst(axi_awburst), .axi_awlock(axi_awlock), .axi_awcache(axi_awcache), .axi_awprot(axi_awprot), .axi_awqos(axi_awqos), .axi_awuser(axi_awuser), .axi_awvalid(axi_awvalid), .axi_awready(axi_awready), // Write Data Channel (W) .axi_wdata(axi_wdata), .axi_wstrb(axi_wstrb), .axi_wlast(axi_wlast), .axi_wuser(axi_wuser), .axi_wvalid(axi_wvalid), .axi_wready(axi_wready), // Write Response Channel (B) .axi_bid(axi_bid), .axi_bresp(axi_bresp), .axi_buser(axi_buser), .axi_bvalid(axi_bvalid), .axi_bready(axi_bready), // Read Address Channel (AR) .axi_arid(axi_arid), .axi_araddr(axi_araddr), .axi_arregion(axi_arregion), .axi_arlen(axi_arlen), .axi_arsize(axi_arsize), .axi_arburst(axi_arburst), .axi_arlock(axi_arlock), .axi_arcache(axi_arcache), .axi_arprot(axi_arprot), .axi_arqos(axi_arqos), .axi_aruser(axi_aruser), .axi_arvalid(axi_arvalid), .axi_arready(axi_arready), // Read Data Channel (R) .axi_rid(axi_rid), .axi_rdata(axi_rdata), .axi_rresp(axi_rresp), .axi_rlast(axi_rlast), .axi_ruser(axi_ruser), .axi_rvalid(axi_rvalid), .axi_rready(axi_rready) ); nerv_axi_cache_icache #( .ADDRESS_WIDTH(ADDRESS_WIDTH), .INSN_SIZE(INSN_SIZE), .LINE_SIZE(LINE_SIZE), .INDEX_SIZE(ICACHE_INDEX_SIZE) ) icache ( .clock(clock), .reset(reset), .stalled(stalled), .stall(icache_stall), .imem_addr(imem_addr), .imem_data(imem_data), .imem_fault(imem_fault), .req_addr(imem_req_addr), .req_valid(imem_req_valid), .res_data(imem_res_data), .res_fault(imem_res_fault), .res_valid(imem_res_valid) ); nerv_axi_cache_dcache #( .ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_SIZE(DATA_SIZE), .LINE_SIZE(LINE_SIZE), .INDEX_SIZE(DCACHE_INDEX_SIZE) ) dcache ( .clock(clock), .reset(reset), .stalled(stalled), .stall(dcache_stall), .dmem_valid(dmem_valid && !dmem_io), .dmem_addr(dmem_addr), .dmem_wstrb(dmem_wstrb), .dmem_wdata(dmem_wdata), .dmem_rdata(dmem_rdata_cache), .dmem_fault(dmem_fault_cache), .req_r_addr(dmem_req_r_addr), .req_r_valid(dmem_req_r_valid), .res_r_data(dmem_res_r_data), .res_r_fault(dmem_res_r_fault), .res_r_valid(dmem_res_r_valid), .req_w_addr(dmem_req_w_addr), .req_w_data(dmem_req_w_data), .req_w_valid(dmem_req_w_valid), .res_w_fault(dmem_res_w_fault), .res_w_valid(dmem_res_w_valid) ); nerv_axi_cache_io #( .ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_SIZE(DATA_SIZE) ) io ( .clock(clock), .reset(reset), .stalled(stalled), .stall(io_stall), .dmem_valid(dmem_valid && dmem_io), .dmem_addr(dmem_addr), .dmem_wstrb(dmem_wstrb), .dmem_wdata(dmem_wdata), .dmem_rdata(dmem_rdata_io), .dmem_fault(dmem_fault_io), .req_ur_addr(dmem_req_ur_addr), .req_ur_valid(dmem_req_ur_valid), .res_ur_data(dmem_res_ur_data), .res_ur_fault(dmem_res_ur_fault), .res_ur_valid(dmem_res_ur_valid), .req_uw_addr(dmem_req_uw_addr), .req_uw_data(dmem_req_uw_data), .req_uw_strb(dmem_req_uw_strb), .req_uw_valid(dmem_req_uw_valid), .res_uw_fault(dmem_res_uw_fault), .res_uw_valid(dmem_res_uw_valid) ); endmodule module nerv_axi_cache_io #( parameter ADDRESS_WIDTH = 32, parameter DATA_SIZE = 2, localparam DATA_WIDTH = 8 << DATA_SIZE ) ( input wire clock, input wire reset, input wire stalled, output var stall, input wire dmem_valid, input wire [ADDRESS_WIDTH-1:0] dmem_addr, input wire [DATA_WIDTH/8-1:0] dmem_wstrb, input wire [DATA_WIDTH-1:0] dmem_wdata, output var [DATA_WIDTH-1:0] dmem_rdata, output var dmem_fault, output var [ADDRESS_WIDTH-1:0] req_ur_addr, output var req_ur_valid, input wire [DATA_WIDTH-1:0] res_ur_data, input wire res_ur_fault, input wire res_ur_valid, output var [ADDRESS_WIDTH-1:0] req_uw_addr, output var [DATA_WIDTH-1:0] req_uw_data, output var [DATA_WIDTH/8-1:0] req_uw_strb, output var req_uw_valid, input wire res_uw_fault, input wire res_uw_valid ); typedef logic [ADDRESS_WIDTH-1:0] addr_t; // cache last dmem interface values while the core is stalled addr_t stable_addr, stable_addr_q; logic [DATA_WIDTH/8-1:0] stable_wstrb; logic [DATA_WIDTH/8-1:0] stable_wstrb_q; logic [DATA_WIDTH-1:0] stable_wdata; logic [DATA_WIDTH-1:0] stable_wdata_q; logic stable_valid, stable_valid_q; logic stalled_q; logic reset_q; always_ff @(posedge clock) begin stable_addr_q <= stable_addr; stable_wstrb_q <= stable_wstrb; stable_wdata_q <= stable_wdata; stable_valid_q <= stable_valid; stalled_q <= stalled; reset_q <= reset; end always_comb begin stable_addr = stable_addr_q; stable_wstrb = stable_wstrb_q; stable_wdata = stable_wdata_q; stable_valid = stable_valid_q; if (!stalled && dmem_valid) begin stable_addr = dmem_addr; stable_wdata = dmem_wdata; stable_wstrb = dmem_wstrb; end if (!stalled) begin stable_valid = dmem_valid; end end logic [DATA_WIDTH-1:0] dmem_rdata_q; logic dmem_fault_q; always_ff @(posedge clock) begin dmem_rdata_q <= dmem_rdata; dmem_fault_q <= dmem_fault; end always_comb begin dmem_rdata = dmem_rdata_q; dmem_fault = dmem_fault_q; if (res_ur_valid) begin dmem_rdata = res_ur_data; dmem_fault = res_ur_fault; end if (res_uw_valid) begin dmem_fault = res_uw_fault; end end logic req_uw_valid_q; logic req_ur_valid_q; logic res_uw_valid_q; logic res_ur_valid_q; assign stall = req_ur_valid_q || req_uw_valid_q; always_ff @(posedge clock) begin req_uw_valid_q <= req_uw_valid; req_ur_valid_q <= req_ur_valid; res_uw_valid_q <= res_uw_valid; res_ur_valid_q <= res_ur_valid; end assign req_ur_addr = stable_addr; assign req_uw_addr = stable_addr; assign req_uw_data = stable_wdata; assign req_uw_strb = stable_wstrb; always_comb begin req_uw_valid = req_uw_valid_q; req_ur_valid = req_ur_valid_q; if (res_ur_valid_q) begin req_ur_valid = 0; end if (res_uw_valid_q) begin req_uw_valid = 0; end if (!stalled && dmem_valid && !dmem_wstrb) begin req_ur_valid = 1; end if (!stalled && dmem_valid && dmem_wstrb) begin req_uw_valid = 1; end if (reset || reset_q) begin req_uw_valid = 0; req_ur_valid = 0; end end endmodule // AXI protocol handling // // This has the AXI interface on one side and the actual instruction and data // caches on the other side. The caches are interfaced using an internal // interface ({imem,dmem}_{req,res}_{r,w}_*) that transfers whole cache lines // at once. // // See `nerv_axi_cache` for parameter descriptions. module nerv_axi_cache_axi #( parameter ADDRESS_WIDTH = 32, parameter DATA_SIZE = 2, parameter INSN_SIZE = 2, parameter LINE_SIZE = 3, parameter AXI_DATA_WIDTH = 32, parameter AXI_ID_WIDTH = 1, parameter AXI_IMEM_ID = 0, parameter AXI_DMEM_ID = 1, parameter AXI_IO_ID = AXI_DMEM_ID, localparam INSN_WIDTH = 8 << INSN_SIZE, localparam DATA_WIDTH = 8 << DATA_SIZE, localparam LINE_WIDTH = 8 << LINE_SIZE, localparam AXI_ADDRESS_WIDTH = ADDRESS_WIDTH, localparam AXI_AWUSER_WIDTH = 1, localparam AXI_WUSER_WIDTH = 1, localparam AXI_BUSER_WIDTH = 1, localparam AXI_ARUSER_WIDTH = 1, localparam AXI_RUSER_WIDTH = 1, localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8 ) ( input wire clock, input wire reset, input wire [ADDRESS_WIDTH-1:0] imem_req_addr, input wire imem_req_valid, output var [LINE_WIDTH-1:0] imem_res_data, output var imem_res_fault, output var imem_res_valid, input wire [ADDRESS_WIDTH-1:0] dmem_req_r_addr, input wire dmem_req_r_valid, output var [LINE_WIDTH-1:0] dmem_res_r_data, output var dmem_res_r_fault, output var dmem_res_r_valid, input wire [ADDRESS_WIDTH-1:0] dmem_req_w_addr, input wire [LINE_WIDTH-1:0] dmem_req_w_data, input wire dmem_req_w_valid, output var dmem_res_w_fault, output var dmem_res_w_valid, input wire [ADDRESS_WIDTH-1:0] dmem_req_ur_addr, input wire dmem_req_ur_valid, output var [DATA_WIDTH-1:0] dmem_res_ur_data, output var dmem_res_ur_fault, output var dmem_res_ur_valid, input wire [ADDRESS_WIDTH-1:0] dmem_req_uw_addr, input wire [DATA_WIDTH-1:0] dmem_req_uw_data, input wire [DATA_WIDTH/8-1:0] dmem_req_uw_strb, input wire dmem_req_uw_valid, output var dmem_res_uw_fault, output var dmem_res_uw_valid, // Write Address Channel (AW) output var [AXI_ID_WIDTH-1:0] axi_awid, output var [AXI_ADDRESS_WIDTH-1:0] axi_awaddr, output var [3:0] axi_awregion, // not used, default value output var [7:0] axi_awlen, output var [2:0] axi_awsize, output var [1:0] axi_awburst, output var axi_awlock, // not used, default value output var [3:0] axi_awcache, // not used, fixed value output var [2:0] axi_awprot, output var [3:0] axi_awqos, // not used, default value output var [AXI_AWUSER_WIDTH-1:0] axi_awuser, // not used, all zero output var axi_awvalid, input wire axi_awready, // Write Data Channel (W) output var [AXI_DATA_WIDTH-1:0] axi_wdata, output var [AXI_STRB_WIDTH-1:0] axi_wstrb, output var axi_wlast, output var [AXI_WUSER_WIDTH-1:0] axi_wuser, // not used, all zero output var axi_wvalid, input wire axi_wready, // Write Response Channel (B) input wire [AXI_ID_WIDTH-1:0] axi_bid, // ignored, cache does not use overlapping transactions input wire [1:0] axi_bresp, // ignored, cache does not handle faults during writeback input wire [AXI_BUSER_WIDTH-1:0] axi_buser, // ignored input wire axi_bvalid, output var axi_bready, // Read Address Channel (AR) output var [AXI_ID_WIDTH-1:0] axi_arid, output var [AXI_ADDRESS_WIDTH-1:0] axi_araddr, output var [3:0] axi_arregion, // not used, default value output var [7:0] axi_arlen, output var [2:0] axi_arsize, output var [1:0] axi_arburst, output var axi_arlock, // not used, default value output var [3:0] axi_arcache, // not used, fixed value output var [2:0] axi_arprot, output var [3:0] axi_arqos, // not used, default value output var [AXI_ARUSER_WIDTH-1:0] axi_aruser, // not used, all zero output var axi_arvalid, input wire axi_arready, // Read Data Channel (R) input wire [AXI_ID_WIDTH-1:0] axi_rid, // ignored, cache does not use overlapping transactions input wire [AXI_DATA_WIDTH-1:0] axi_rdata, input wire [1:0] axi_rresp, input wire axi_rlast, input wire [AXI_RUSER_WIDTH-1:0] axi_ruser, // ignored input wire axi_rvalid, output var axi_rready ); // handle reads typedef enum { R_IDLE, R_IFETCH, R_DFETCH, R_IOFETCH } read_state_t; read_state_t read_state, read_state_q; assign axi_arregion = 0; // not used assign axi_arlock = 0; // not used assign axi_arcache = 4'b1111; // not used, TODO also support uncached accesses assign axi_arqos = 0; // not used assign axi_aruser = 0; // not used assign axi_arsize = $clog2(AXI_DATA_WIDTH / 8); // always use full bus width assign axi_arburst = 2'b01; // always incr assign axi_rready = 1; // always ready logic axi_arready_q, axi_arvalid_q; logic [7:0] axi_arlen_q; logic [2:0] axi_arprot_q; logic [AXI_ID_WIDTH-1:0] axi_arid_q; logic [AXI_ADDRESS_WIDTH-1:0] axi_araddr_q; logic [LINE_WIDTH-1:0] read_data, read_data_q; logic read_fault, read_fault_q; logic read_valid; logic reset_q; always_ff @(posedge clock) begin axi_arready_q <= axi_arready; axi_arvalid_q <= axi_arvalid; axi_arlen_q <= axi_arlen; axi_arprot_q <= axi_arprot; axi_arid_q <= axi_arid; axi_araddr_q <= axi_araddr; read_data_q <= read_data; read_fault_q <= read_fault; read_state_q <= read_state; reset_q <= reset; end assign imem_res_fault = read_fault; assign dmem_res_r_fault = read_fault; assign dmem_res_ur_fault = read_fault; assign imem_res_valid = (read_state_q == R_IFETCH && read_valid); assign dmem_res_r_valid = (read_state_q == R_DFETCH && read_valid); assign dmem_res_ur_valid = (read_state_q == R_IOFETCH && read_valid); assign imem_res_data = read_data; assign dmem_res_r_data = read_data; assign dmem_res_ur_data = read_data[LINE_WIDTH - 1:LINE_WIDTH - DATA_WIDTH]; always_comb begin logic local_read_valid; axi_arvalid = axi_arvalid_q; axi_arlen = axi_arlen_q; axi_arprot = axi_arprot_q; axi_arid = axi_arid_q; axi_araddr = axi_araddr_q; read_data = read_data_q; read_fault = read_fault_q; read_state = read_state_q; local_read_valid = 0; if (axi_arready_q && axi_arvalid_q) begin axi_arvalid = 0; read_fault = 0; end case (read_state) R_IFETCH, R_DFETCH, R_IOFETCH: if (axi_rvalid && axi_rready) begin read_data = {axi_rdata, read_data[LINE_WIDTH - 1:AXI_DATA_WIDTH]}; if (axi_rresp[1]) begin read_fault = 1; end if (axi_rlast) begin read_state = R_IDLE; local_read_valid = 1; end end default: if (!axi_arvalid && !reset_q && (imem_req_valid || dmem_req_r_valid || dmem_req_ur_valid)) begin axi_arvalid = 1; // TODO also set axi_arcache if (imem_req_valid) begin axi_arid = AXI_IMEM_ID; axi_arprot = 3'b111; // insn, non-secure, priviliged axi_araddr = imem_req_addr; axi_arlen = (LINE_WIDTH / AXI_DATA_WIDTH) - 1; read_state = R_IFETCH; end else if (dmem_req_r_valid) begin axi_arid = AXI_DMEM_ID; axi_arprot = 3'b011; // data, non-secure, priviliged axi_araddr = dmem_req_r_addr; axi_arlen = (LINE_WIDTH / AXI_DATA_WIDTH) - 1; read_state = R_DFETCH; end else begin axi_arid = AXI_IO_ID; axi_arprot = 3'b011; // data, non-secure, priviliged axi_araddr = dmem_req_ur_addr; axi_arlen = 0; read_state = R_IOFETCH; end end endcase if (reset) begin axi_arvalid = 0; read_state = R_IDLE; end read_valid = local_read_valid; end // handle writes typedef enum { W_IDLE, W_DSTORE, W_IOSTORE } write_state_t; write_state_t write_state, write_state_q; assign axi_awregion = 0; // not used assign axi_awlock = 0; // not used assign axi_awcache = 4'b1111; // not used, TODO also support uncached accesses assign axi_awqos = 0; // not used assign axi_awuser = 0; // not used assign axi_awsize = $clog2(AXI_DATA_WIDTH / 8); // always use full bus width assign axi_awburst = 2'b01; // always incr assign axi_wuser = 0; // not used assign axi_bready = 1; // always ready logic axi_awready_q, axi_awvalid_q; logic [7:0] axi_awlen_q; logic [2:0] axi_awprot_q; logic [AXI_ID_WIDTH-1:0] axi_awid_q; logic [AXI_ADDRESS_WIDTH-1:0] axi_awaddr_q; logic [$clog2(LINE_WIDTH / AXI_DATA_WIDTH):0] wvalid_counter, wvalid_counter_q; logic axi_wready_q; logic [AXI_STRB_WIDTH-1:0] axi_wstrb_q; logic [LINE_WIDTH-1:0] wdata_shiftreg, wdata_shiftreg_q; logic axi_bvalid_q; assign axi_wvalid = wvalid_counter != 0; assign axi_wlast = wvalid_counter == 1; assign axi_wdata = wdata_shiftreg[AXI_DATA_WIDTH-1:0]; always_ff @(posedge clock) begin axi_awready_q <= axi_awready; axi_awvalid_q <= axi_awvalid; axi_awlen_q <= axi_awlen; axi_awprot_q <= axi_awprot; axi_awid_q <= axi_awid; axi_awaddr_q <= axi_awaddr; axi_wready_q <= axi_wready; axi_wstrb_q <= axi_wstrb; axi_bvalid_q <= axi_bvalid; wvalid_counter_q <= wvalid_counter; wdata_shiftreg_q <= wdata_shiftreg; write_state_q <= write_state; end assign dmem_res_w_valid = write_state_q == W_DSTORE && axi_bready && axi_bvalid; assign dmem_res_uw_valid = write_state_q == W_IOSTORE && axi_bready && axi_bvalid; // We ignore write responses / write faults for now as our cache will never // write something it hasn't successfully read before assign dmem_res_w_fault = 0; assign dmem_res_uw_fault = axi_bresp[1]; // TODO double check always_comb begin axi_awvalid = axi_awvalid_q; axi_awlen = axi_awlen_q; axi_awprot = axi_awprot_q; axi_awid = axi_awid_q; axi_awaddr = axi_awaddr_q; axi_wstrb = axi_wstrb_q; wvalid_counter = wvalid_counter_q; wdata_shiftreg = wdata_shiftreg_q; write_state = write_state_q; if (axi_awready_q && axi_awvalid_q) begin axi_awvalid = 0; end if (axi_wready_q && (wvalid_counter_q != 0)) begin wvalid_counter -= 1; wdata_shiftreg = {{AXI_DATA_WIDTH{1'b0}}, wdata_shiftreg[LINE_WIDTH-1:AXI_DATA_WIDTH]}; end if (axi_bvalid_q) begin write_state = W_IDLE; end if (write_state == W_IDLE && !axi_awvalid && wvalid_counter == 0 && (dmem_req_w_valid || dmem_req_uw_valid)) begin axi_awvalid = 1; if (dmem_req_w_valid) begin wvalid_counter = LINE_WIDTH / AXI_DATA_WIDTH; axi_awlen = wvalid_counter - 1; axi_awid = AXI_DMEM_ID; axi_awprot = 3'b011; // data, non-secure, priviliged axi_awaddr = dmem_req_w_addr; wdata_shiftreg = dmem_req_w_data; axi_wstrb = '1; write_state = W_DSTORE; end else begin wvalid_counter = 1; axi_awlen = wvalid_counter - 1; axi_awid = AXI_IO_ID; axi_awprot = 3'b011; // data, non-secure, priviliged axi_awaddr = dmem_req_uw_addr; wdata_shiftreg = dmem_req_uw_data; axi_wstrb = dmem_req_uw_strb; write_state = W_IOSTORE; end end if (reset) begin axi_awvalid = 0; wvalid_counter = 0; write_state = W_IDLE; end end endmodule ================================================ FILE: cores/nerv/axi_cache/nerv_axi_cache_dcache.sv ================================================ // Direct mapped, write-back/write-allocate AXI cache for the NERV core. // // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. `default_nettype none // Read/write data cache. // // This implements the instruction cache. It directly uses NERV's native // interface on the core side but uses a simple internal interface that // transfers whole cache lines on the bus side. Translating this into AXI is // done using `nerv_axi_cache_axi` which together with this and the data cache // is wrapped by `nerv_axi_cache`. // // See `nerv_axi_cache` for parameter descriptions. module nerv_axi_cache_dcache #( parameter ADDRESS_WIDTH = 32, parameter DATA_SIZE = 2, parameter LINE_SIZE = 5, parameter INDEX_SIZE = 4, localparam DATA_WIDTH = 8 << DATA_SIZE, localparam LINE_WIDTH = 8 << LINE_SIZE, localparam LINE_COUNT = 1 << INDEX_SIZE ) ( input wire clock, input wire reset, input wire stalled, output var stall, input wire dmem_valid, input wire [ADDRESS_WIDTH-1:0] dmem_addr, input wire [DATA_WIDTH/8-1:0] dmem_wstrb, input wire [DATA_WIDTH-1:0] dmem_wdata, output var [DATA_WIDTH-1:0] dmem_rdata, output var dmem_fault, output var [ADDRESS_WIDTH-1:0] req_r_addr, output var req_r_valid, input wire [LINE_WIDTH-1:0] res_r_data, input wire res_r_fault, input wire res_r_valid, output var [ADDRESS_WIDTH-1:0] req_w_addr, output var [LINE_WIDTH-1:0] req_w_data, output var req_w_valid, input wire res_w_fault, input wire res_w_valid ); typedef logic [ADDRESS_WIDTH-1:0] addr_t; typedef logic [ADDRESS_WIDTH-LINE_SIZE-1:0] line_addr_t; typedef logic [LINE_WIDTH-1:0] line_t; typedef logic [INDEX_SIZE-1:0] index_t; typedef logic [ADDRESS_WIDTH-LINE_SIZE-INDEX_SIZE-1:0] tag_t; // cache memory line_addr_t cache_line_addr_rd; (*keep*) line_addr_t cache_line_addr_wr; index_t cache_index_rd, cache_index_rd_q; tag_t cache_tag_rd, cache_tag_rd_q; index_t cache_index_wr; tag_t cache_tag_wr; assign {cache_tag_rd, cache_index_rd } = cache_line_addr_rd; assign {cache_tag_wr, cache_index_wr } = cache_line_addr_wr; line_t cache_data_mem [0:LINE_COUNT-1]; tag_t cache_tag_mem [0:LINE_COUNT-1]; logic [LINE_COUNT-1:0] cache_valid_mem; logic [LINE_COUNT-1:0] cache_dirty_mem; line_t cache_data_out, cache_data_out_q; tag_t cache_tag_out; logic cache_valid_out; logic cache_dirty_out; assign cache_data_out = cache_data_mem[cache_index_rd]; assign cache_tag_out = cache_tag_mem[cache_index_rd]; assign cache_valid_out = cache_valid_mem[cache_index_rd]; assign cache_dirty_out = cache_dirty_mem[cache_index_rd]; line_t cache_data_in; logic cache_valid_in; logic cache_dirty_in; always @(posedge clock) begin cache_data_out_q <= cache_data_out; cache_data_mem[cache_index_wr] <= cache_data_in; cache_tag_mem[cache_index_wr] <= cache_tag_wr; cache_valid_mem[cache_index_wr] <= cache_valid_in; cache_dirty_mem[cache_index_wr] <= cache_dirty_in; if (reset) begin cache_valid_mem <= 0; cache_dirty_mem <= 0; end end // cache last dmem interface values while the core is stalled addr_t stable_addr, stable_addr_q; logic [DATA_WIDTH/8-1:0] stable_wstrb; logic [DATA_WIDTH/8-1:0] stable_wstrb_q; logic [DATA_WIDTH-1:0] stable_wdata; logic [DATA_WIDTH-1:0] stable_wdata_q; logic stable_valid, stable_valid_q; logic stalled_q; always_ff @(posedge clock) begin stable_addr_q <= stable_addr; stable_wstrb_q <= stable_wstrb; stable_wdata_q <= stable_wdata; stable_valid_q <= stable_valid; stalled_q <= stalled; end always_comb begin stable_addr = stable_addr_q; stable_wstrb = stable_wstrb_q; stable_wdata = stable_wdata_q; stable_valid = stable_valid_q; if (!stalled && dmem_valid) begin stable_addr = dmem_addr; stable_wdata = dmem_wdata; stable_wstrb = dmem_wstrb; end if (!stalled) begin stable_valid = dmem_valid; end end // fast path for read and write hits wire line_addr_t line_addr = stable_addr[ADDRESS_WIDTH-1:LINE_SIZE]; wire line_addr_t line_addr_q = stable_addr_q[ADDRESS_WIDTH-1:LINE_SIZE]; assign cache_line_addr_rd = line_addr; assign cache_line_addr_wr = line_addr; wire logic [LINE_SIZE-DATA_SIZE-1:0] line_subaddr = stable_addr[LINE_SIZE-1:DATA_SIZE]; wire logic [LINE_SIZE-DATA_SIZE-1:0] line_subaddr_q = stable_addr_q[LINE_SIZE-1:DATA_SIZE]; line_t dmem_rdata_line, dmem_rdata_line_q; logic dmem_next_fault, dmem_next_fault_q; always_ff @(posedge clock) begin dmem_rdata_line_q <= dmem_rdata_line; dmem_next_fault_q <= dmem_next_fault; end assign dmem_rdata_line = cache_data_in; assign dmem_rdata = dmem_rdata_line_q[line_subaddr_q * DATA_WIDTH +: DATA_WIDTH]; assign dmem_fault = dmem_next_fault_q; wire logic cache_hit = (cache_tag_out == cache_tag_rd && cache_valid_out); wire logic cache_miss = (stable_valid && !cache_hit); logic cache_hit_q, cache_miss_q; wire logic cache_writeback = (cache_miss && cache_dirty_out && cache_valid_out); always_ff @(posedge clock) begin cache_hit_q <= cache_hit && !reset; cache_miss_q <= cache_miss && !reset; end always_comb begin dmem_next_fault = dmem_next_fault_q && stalled; cache_data_in = cache_data_out; cache_dirty_in = cache_dirty_out; cache_valid_in = cache_hit; // inject fetched data if (res_r_valid) begin cache_data_in = res_r_data; cache_dirty_in = 0; cache_valid_in = !res_r_fault; dmem_next_fault = res_r_fault; end for (int i = 0; i < DATA_WIDTH / 8; i++) begin if (stable_valid && stable_wstrb[i]) begin cache_dirty_in = 1; cache_data_in[line_subaddr * DATA_WIDTH + 8 * i +: 8] = stable_wdata[8 * i +: 8]; end end if (reset) begin dmem_next_fault = 0; end end // fetch misses and perform writebacks assign req_r_addr = {cache_line_addr_rd, {LINE_SIZE{1'b0}}}; addr_t req_w_addr_q; line_t req_w_data_q; logic req_w_valid_q; logic req_r_valid_q; logic res_w_valid_q; logic res_r_valid_q; always_ff @(posedge clock) begin req_w_addr_q <= req_w_addr; req_w_data_q <= req_w_data; req_w_valid_q <= req_w_valid; req_r_valid_q <= req_r_valid; res_w_valid_q <= res_w_valid; res_r_valid_q <= res_r_valid; end assign stall = (cache_miss_q && !dmem_next_fault_q) || req_w_valid_q; always_comb begin req_w_valid = req_w_valid_q; req_w_data = req_w_data_q; req_w_addr = req_w_addr_q; req_r_valid = req_r_valid_q; if (res_r_valid_q) begin req_r_valid = 0; end if (cache_miss && !stalled) begin req_r_valid = 1; end if (res_w_valid_q) begin req_w_valid = 0; end if (cache_writeback && !stalled) begin req_w_valid = 1; req_w_addr = {cache_tag_out, cache_index_rd, {LINE_SIZE{1'b0}}}; req_w_data = cache_data_out; end if (reset) begin req_w_valid = 0; req_r_valid = 0; end end endmodule ================================================ FILE: cores/nerv/axi_cache/nerv_axi_cache_icache.sv ================================================ // Direct mapped, write-back/write-allocate AXI cache for the NERV core. // // Copyright (C) 2023 Jannis Harder // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. `default_nettype none // Read only instruction cache. // // This implements the instruction cache. It directly uses NERV's native // interface on the core side but uses a simple internal interface that // transfers whole cache lines on the bus side. Translating this into AXI is // done using `nerv_axi_cache_axi` which together with this and the data cache // is wrapped by `nerv_axi_cache`. // // See `nerv_axi_cache` for parameter descriptions. module nerv_axi_cache_icache #( parameter ADDRESS_WIDTH = 32, parameter INSN_SIZE = 2, parameter LINE_SIZE = 3, parameter INDEX_SIZE = 2, localparam INSN_WIDTH = 8 << INSN_SIZE, localparam LINE_WIDTH = 8 << LINE_SIZE, localparam LINE_COUNT = 1 << INDEX_SIZE ) ( input wire clock, input wire reset, input wire stalled, output var stall, input wire [ADDRESS_WIDTH-1:0] imem_addr, output var [INSN_WIDTH-1:0] imem_data, output var imem_fault, output var [ADDRESS_WIDTH-1:0] req_addr, output var req_valid, input wire [LINE_WIDTH-1:0] res_data, input wire res_fault, input wire res_valid ); typedef logic [ADDRESS_WIDTH-1:0] addr_t; typedef logic [ADDRESS_WIDTH-LINE_SIZE-1:0] line_addr_t; typedef logic [LINE_WIDTH-1:0] line_t; typedef logic [INDEX_SIZE-1:0] index_t; typedef logic [ADDRESS_WIDTH-LINE_SIZE-INDEX_SIZE-1:0] tag_t; // cache memory line_addr_t cache_line_addr_rd; (*keep*) line_addr_t cache_line_addr_wr; index_t cache_index_rd, cache_index_rd_q; tag_t cache_tag_rd, cache_tag_rd_q; index_t cache_index_wr; tag_t cache_tag_wr; assign {cache_tag_rd, cache_index_rd } = cache_line_addr_rd; assign {cache_tag_wr, cache_index_wr } = cache_line_addr_wr; line_t cache_data_mem [0:LINE_COUNT-1]; tag_t cache_tag_mem [0:LINE_COUNT-1]; logic [LINE_COUNT-1:0] cache_valid_mem; logic [LINE_COUNT-1:0] cache_dirty_mem; line_t cache_data_out, cache_data_out_q; tag_t cache_tag_out; logic cache_valid_out; logic cache_dirty_out; assign cache_data_out = cache_data_mem[cache_index_rd]; assign cache_tag_out = cache_tag_mem[cache_index_rd]; assign cache_valid_out = cache_valid_mem[cache_index_rd]; assign cache_dirty_out = cache_dirty_mem[cache_index_rd]; line_t cache_data_in; logic cache_valid_in; logic cache_dirty_in; always @(posedge clock) begin cache_data_out_q <= cache_data_out; cache_data_mem[cache_index_wr] <= cache_data_in; cache_tag_mem[cache_index_wr] <= cache_tag_wr; cache_valid_mem[cache_index_wr] <= cache_valid_in; cache_dirty_mem[cache_index_wr] <= cache_dirty_in; if (reset) begin cache_valid_mem <= 0; cache_dirty_mem <= 0; end end // cache last imem interface values while the core is stalled addr_t stable_addr, stable_addr_q; logic stable_valid, stable_valid_q; logic stalled_q; always_ff @(posedge clock) begin stable_addr_q <= stable_addr; stable_valid_q <= stable_valid; stalled_q <= stalled; end always_comb begin stable_addr = stable_addr_q; stable_valid = stable_valid_q; if (!stalled) begin stable_addr = imem_addr; stable_valid = 1; end end // fast path for read and write hits wire line_addr_t line_addr = stable_addr[ADDRESS_WIDTH-1:LINE_SIZE]; wire line_addr_t line_addr_q = stable_addr_q[ADDRESS_WIDTH-1:LINE_SIZE]; assign cache_line_addr_rd = line_addr; assign cache_line_addr_wr = line_addr; wire logic [LINE_SIZE-INSN_SIZE-1:0] line_subaddr = stable_addr[LINE_SIZE-1:INSN_SIZE]; wire logic [LINE_SIZE-INSN_SIZE-1:0] line_subaddr_q = stable_addr_q[LINE_SIZE-1:INSN_SIZE]; line_t imem_data_line, imem_data_line_q; logic imem_next_fault, imem_next_fault_q; always_ff @(posedge clock) begin imem_data_line_q <= imem_data_line; imem_next_fault_q <= imem_next_fault; end assign imem_data_line = cache_data_in; assign imem_data = imem_data_line_q[line_subaddr_q * INSN_WIDTH +: INSN_WIDTH]; assign imem_fault = imem_next_fault_q; wire logic cache_hit = (cache_tag_out == cache_tag_rd && cache_valid_out); wire logic cache_miss = (stable_valid && !cache_hit); logic cache_hit_q, cache_miss_q; wire logic cache_writeback = (cache_miss && cache_dirty_out && cache_valid_out); always_ff @(posedge clock) begin cache_hit_q <= cache_hit && !reset; cache_miss_q <= cache_miss && !reset; end always_comb begin imem_next_fault = imem_next_fault_q && stalled; cache_data_in = cache_data_out; cache_dirty_in = cache_dirty_out; cache_valid_in = cache_hit; // inject fetched data if (res_valid) begin cache_data_in = res_data; cache_dirty_in = 0; cache_valid_in = !res_fault; imem_next_fault = res_fault; end if (reset) begin imem_next_fault = 0; end end assign stall = cache_miss_q && !imem_next_fault_q; // fetch misses assign req_addr = {cache_line_addr_rd, {LINE_SIZE{1'b0}}}; logic req_valid_q, res_valid_q; always_ff @(posedge clock) begin req_valid_q <= req_valid; res_valid_q <= res_valid; end always_comb begin req_valid = req_valid_q; if (res_valid_q) begin req_valid = 0; end if (cache_miss && !stalled) begin req_valid = 1; end if (reset) begin req_valid = 0; end end endmodule ================================================ FILE: cores/nerv/axi_cache/testbench_axi.sv ================================================ // Testbench using the AXI4 interface /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 N. Engelhardt * Copyright (C) 2023 Jannis Harder * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ module testbench; localparam MEM_ADDR_WIDTH = 16; localparam TIMEOUT = (1<<14); reg clock; reg reset = 1'b1; reg stall = 1'b0; wire trap; wire [31:0] imem_addr; wire [31:0] imem_data; wire imem_fault; wire dmem_valid; wire [31:0] dmem_addr; wire [ 3:0] dmem_wstrb; wire [31:0] dmem_wdata; reg [31:0] dmem_rdata; wire dmem_fault; reg [31:0] irq; initial irq = 0; always #5 clock = clock === 1'b0; always @(posedge clock) reset <= 0; reg [7:0] mem [0:(1<= (1<= TIMEOUT)) begin $display("Simulated %0d cycles", cycles); $finish; end end endmodule ================================================ FILE: cores/nerv/axi_cache/testbench_internal.sv ================================================ // Testbench using the internal bus side interface /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 N. Engelhardt * Copyright (C) 2023 Jannis Harder * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ module testbench; localparam MEM_ADDR_WIDTH = 16; localparam TIMEOUT = (1<<14); reg clock; reg reset = 1'b1; reg stall = 1'b0; wire trap; wire [31:0] imem_addr; wire [31:0] imem_data; wire dmem_valid; wire [31:0] dmem_addr; wire [ 3:0] dmem_wstrb; wire [31:0] dmem_wdata; reg [31:0] dmem_rdata; reg [31:0] irq; initial irq = 0; always #5 clock = clock === 1'b0; always @(posedge clock) reset <= 0; reg [7:0] mem [0:(1<= (1<= TIMEOUT)) begin $display("Simulated %0d cycles", cycles); $finish; end end endmodule ================================================ FILE: cores/nerv/axi_cache/verify_axi.sby ================================================ [tasks] prove cover [options] prove: mode prove cover: mode cover # The cache's AXI interface is too simple to cover everything SVA-AXI-FVIP's # can check for cover: expect fail [engines] prove: abc pdr cover: smtbmc boolector [script] verific -set-ignore VERI-1875 # Read packages first # This one should be alwyas read first read -sv amba_axi4_protocol_checker_pkg.sv # Then the rest of them read -sv amba_axi4_single_interface_requirements.sv read -sv amba_axi4_definition_of_axi4_lite.sv read -sv amba_axi4_atomic_accesses.sv read -sv amba_axi4_transaction_structure.sv read -sv amba_axi4_transaction_attributes.sv read -sv amba_axi4_low_power_interface.sv read -sv amba_axi4_low_power_channel.sv # This is a checker, not a package read -sv amba_axi4_write_response_dependencies.sv read -sv amba_axi4_exclusive_access_source_perspective.sv # The modules containing the properties read -sv amba_axi4_protocol_checker.sv read -sv amba_axi4_read_address_channel.sv read -sv amba_axi4_read_data_channel.sv read -sv amba_axi4_write_data_channel.sv read -sv amba_axi4_write_response_channel.sv read -sv amba_axi4_write_address_channel.sv # Then the dut read -sv nerv_axi_cache_icache.sv nerv_axi_cache_dcache.sv nerv_axi_cache.sv # The bind file read -sv verify_axi.sv # Elaborate prep -top nerv_axi_cache [files] # Packages SVA-AXI4-FVIP/AXI4/src/amba_axi4_protocol_checker_pkg.sv SVA-AXI4-FVIP/AXI4/src/amba_axi4_low_power_channel.sv SVA-AXI4-FVIP/AXI4/src/axi4_spec/amba_axi4_single_interface_requirements.sv SVA-AXI4-FVIP/AXI4/src/axi4_spec/amba_axi4_definition_of_axi4_lite.sv SVA-AXI4-FVIP/AXI4/src/axi4_spec/amba_axi4_atomic_accesses.sv SVA-AXI4-FVIP/AXI4/src/axi4_spec/amba_axi4_transaction_structure.sv SVA-AXI4-FVIP/AXI4/src/axi4_spec/amba_axi4_transaction_attributes.sv SVA-AXI4-FVIP/AXI4/src/axi4_spec/amba_axi4_low_power_interface.sv SVA-AXI4-FVIP/AXI4/src/axi4_lib/amba_axi4_write_response_dependencies.sv SVA-AXI4-FVIP/AXI4/src/axi4_lib/amba_axi4_exclusive_access_source_perspective.sv # Modules containing the properties SVA-AXI4-FVIP/AXI4/src/amba_axi4_protocol_checker.sv SVA-AXI4-FVIP/AXI4/src/amba_axi4_read_address_channel.sv SVA-AXI4-FVIP/AXI4/src/amba_axi4_read_data_channel.sv SVA-AXI4-FVIP/AXI4/src/amba_axi4_write_data_channel.sv SVA-AXI4-FVIP/AXI4/src/amba_axi4_write_response_channel.sv SVA-AXI4-FVIP/AXI4/src/amba_axi4_write_address_channel.sv # Bind file verify_axi.sv # # DUT nerv_axi_cache_icache.sv nerv_axi_cache_dcache.sv nerv_axi_cache.sv ================================================ FILE: cores/nerv/axi_cache/verify_axi.sv ================================================ `default_nettype none module resetgen(input wire clock, input wire reset, input wire axi_arvalid, input wire axi_arready); initial assume(reset); endmodule bind nerv_axi_cache resetgen resetgen(.*); bind nerv_axi_cache amba_axi4_protocol_checker #('{ID_WIDTH: 1, ADDRESS_WIDTH: 32, DATA_WIDTH: 32, AWUSER_WIDTH: 1, WUSER_WIDTH: 1, BUSER_WIDTH: 1, ARUSER_WIDTH: 1, RUSER_WIDTH: 1, MAX_WR_BURSTS: 1, MAX_RD_BURSTS: 1, MAX_WR_LENGTH: 2, MAX_RD_LENGTH: 2, MAXWAIT: 5, VERIFY_AGENT_TYPE: amba_axi4_protocol_checker_pkg::SOURCE, PROTOCOL_TYPE: amba_axi4_protocol_checker_pkg::AXI4FULL, INTERFACE_REQS: 1, ENABLE_COVER: 1, ENABLE_XPROP: 0, ARM_RECOMMENDED: 1, CHECK_PARAMETERS: 1, OPTIONAL_WSTRB: 0, FULL_WR_STRB: 1, OPTIONAL_RESET: 1, EXCLUSIVE_ACCESS: 0, OPTIONAL_LP: 0}) dest_check ( .ACLK(clock), .ARESETn(!reset), .AWID(axi_awid), .AWADDR(axi_awaddr), .AWREGION(axi_awregion), .AWLEN(axi_awlen), .AWSIZE(axi_awsize), .AWBURST(axi_awburst), .AWLOCK(axi_awlock), .AWCACHE(axi_awcache), .AWPROT(axi_awprot), .AWQOS(axi_awqos), .AWVALID(axi_awvalid), .AWREADY(axi_awready), .AWUSER(axi_awuser), .WDATA(axi_wdata), .WSTRB(axi_wstrb), .WLAST(axi_wlast), .WVALID(axi_wvalid), .WREADY(axi_wready), .WUSER(axi_wuser), .BID(axi_bid), .BRESP(axi_bresp), .BVALID(axi_bvalid), .BREADY(axi_bready), .BUSER(axi_buser), .ARID(axi_arid), .ARADDR(axi_araddr), .ARREGION(axi_arregion), .ARLEN(axi_arlen), .ARSIZE(axi_arsize), .ARBURST(axi_arburst), .ARLOCK(axi_arlock), .ARCACHE(axi_arcache), .ARPROT(axi_arprot), .ARQOS(axi_arqos), .ARVALID(axi_arvalid), .ARREADY(axi_arready), .ARUSER(axi_aruser), .RID(axi_rid), .RDATA(axi_rdata), .RRESP(axi_rresp), .RLAST(axi_rlast), .RVALID(axi_rvalid), .RREADY(axi_rready), .RUSER(axi_ruser), .CSYSREQ(1'b1), .CSYSACK(1'b1), .CACTIVE(1'b1) ); ================================================ FILE: cores/nerv/axi_cache/wrapper_axi.sv ================================================ /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 Claire Xenia Wolf * Copyright (C) 2023 Jannis Harder * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ `default_nettype wire module rvfi_wrapper ( input clock, input reset, `RVFI_OUTPUTS `RVFI_BUS_OUTPUTS ); (* keep *) `rvformal_rand_reg random_stall; wire cache_stall; (* keep *) `rvformal_rand_reg [31:0] random_imem_data; wire [31:0] imem_addr; wire [31:0] imem_data; wire imem_fault; wire dmem_valid; wire [31:0] dmem_addr; wire [ 3:0] dmem_wstrb; wire [31:0] dmem_wdata; wire [31:0] dmem_rdata; wire dmem_fault; wire stall = random_stall || cache_stall; wire trap; nerv #( ) uut ( .clock (clock ), .reset (reset ), .stall (stall ), .trap (trap ), .imem_addr (imem_addr ), .imem_data (imem_data ), .dmem_valid (dmem_valid), .dmem_addr (dmem_addr ), .dmem_wstrb (dmem_wstrb), .dmem_wdata (dmem_wdata), .dmem_rdata (dmem_rdata), `ifdef NERV_FAULT .imem_fault (imem_fault), .dmem_fault (dmem_fault), `endif .irq (0), `RVFI_CONN32 ); localparam AXI_DATA_WIDTH = 32; localparam AXI_ADDRESS_WIDTH = 32; localparam AXI_ID_WIDTH = 1; localparam AXI_AWUSER_WIDTH = 1; localparam AXI_WUSER_WIDTH = 1; localparam AXI_BUSER_WIDTH = 1; localparam AXI_ARUSER_WIDTH = 1; localparam AXI_RUSER_WIDTH = 1; localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; wire [AXI_ID_WIDTH-1:0] axi_awid; wire [AXI_ADDRESS_WIDTH-1:0] axi_awaddr; wire [3:0] axi_awregion; wire [7:0] axi_awlen; wire [2:0] axi_awsize; wire [1:0] axi_awburst; wire axi_awlock; wire [3:0] axi_awcache; wire [2:0] axi_awprot; wire [3:0] axi_awqos; wire [AXI_AWUSER_WIDTH-1:0] axi_awuser; wire axi_awvalid; wire axi_awready; // Write Data Channel (W) wire [AXI_DATA_WIDTH-1:0] axi_wdata; wire [AXI_STRB_WIDTH-1:0] axi_wstrb; wire axi_wlast; wire [AXI_WUSER_WIDTH-1:0] axi_wuser; wire axi_wvalid; wire axi_wready; // Write Response Channel (B) wire [AXI_ID_WIDTH-1:0] axi_bid; wire [1:0] axi_bresp; wire [AXI_BUSER_WIDTH-1:0] axi_buser; wire axi_bvalid; wire axi_bready; // Read Address Channel (AR) wire [AXI_ID_WIDTH-1:0] axi_arid; wire [AXI_ADDRESS_WIDTH-1:0] axi_araddr; wire [3:0] axi_arregion; wire [7:0] axi_arlen; wire [2:0] axi_arsize; wire [1:0] axi_arburst; wire axi_arlock; wire [3:0] axi_arcache; wire [2:0] axi_arprot; wire [3:0] axi_arqos; wire [AXI_ARUSER_WIDTH-1:0] axi_aruser; wire axi_arvalid; wire axi_arready; // Read Data Channel (R) wire [AXI_ID_WIDTH-1:0] axi_rid; wire [AXI_DATA_WIDTH-1:0] axi_rdata; wire [1:0] axi_rresp; wire axi_rlast; wire [AXI_RUSER_WIDTH-1:0] axi_ruser; wire axi_rvalid; wire axi_rready; `ifndef RISCV_FORMAL_MEM_FAULT always @* assume(!axi_rresp[1]); always @* assume(!axi_bresp[1]); `endif nerv_axi_cache #( .AXI_DATA_WIDTH(AXI_DATA_WIDTH), .LINE_SIZE(3), .ICACHE_INDEX_SIZE(1), .DCACHE_INDEX_SIZE(1) ) cache ( .clock(clock), .reset(reset), .stalled(stall), .stall(cache_stall), .imem_addr(imem_addr), .imem_data(imem_data), .imem_fault(imem_fault), .dmem_valid(dmem_valid), .dmem_addr(dmem_addr), .dmem_wstrb(dmem_wstrb), .dmem_wdata(dmem_wdata), .dmem_rdata(dmem_rdata), .dmem_fault(dmem_fault), .dmem_io(dmem_addr[31:16] == 16'h1234), // Write Address Channel (AW) .axi_awid(axi_awid), .axi_awaddr(axi_awaddr), .axi_awregion(axi_awregion), .axi_awlen(axi_awlen), .axi_awsize(axi_awsize), .axi_awburst(axi_awburst), .axi_awlock(axi_awlock), .axi_awcache(axi_awcache), .axi_awprot(axi_awprot), .axi_awqos(axi_awqos), .axi_awuser(axi_awuser), .axi_awvalid(axi_awvalid), .axi_awready(axi_awready), // Write Data Channel (W) .axi_wdata(axi_wdata), .axi_wstrb(axi_wstrb), .axi_wlast(axi_wlast), .axi_wuser(axi_wuser), .axi_wvalid(axi_wvalid), .axi_wready(axi_wready), // Write Response Channel (B) .axi_bid(axi_bid), .axi_bresp(axi_bresp), .axi_buser(axi_buser), .axi_bvalid(axi_bvalid), .axi_bready(axi_bready), // Read Address Channel (AR) .axi_arid(axi_arid), .axi_araddr(axi_araddr), .axi_arregion(axi_arregion), .axi_arlen(axi_arlen), .axi_arsize(axi_arsize), .axi_arburst(axi_arburst), .axi_arlock(axi_arlock), .axi_arcache(axi_arcache), .axi_arprot(axi_arprot), .axi_arqos(axi_arqos), .axi_aruser(axi_aruser), .axi_arvalid(axi_arvalid), .axi_arready(axi_arready), // Read Data Channel (R) .axi_rid(axi_rid), .axi_rdata(axi_rdata), .axi_rresp(axi_rresp), .axi_rlast(axi_rlast), .axi_ruser(axi_ruser), .axi_rvalid(axi_rvalid), .axi_rready(axi_rready) ); `ifdef RISCV_FORMAL_BUS rvfi_bus_axi4_observer_write axi_write ( .clock(clock), .reset(reset), // Write Address Channel (AW) .axi_awid(axi_awid), .axi_awaddr(axi_awaddr), .axi_awregion(axi_awregion), .axi_awlen(axi_awlen), .axi_awsize(axi_awsize), .axi_awburst(axi_awburst), .axi_awlock(axi_awlock), .axi_awcache(axi_awcache), .axi_awprot(axi_awprot), .axi_awqos(axi_awqos), .axi_awuser(axi_awuser), .axi_awvalid(axi_awvalid), .axi_awready(axi_awready), // Write Data Channel (W) .axi_wdata(axi_wdata), .axi_wstrb(axi_wstrb), .axi_wlast(axi_wlast), .axi_wuser(axi_wuser), .axi_wvalid(axi_wvalid), .axi_wready(axi_wready), // Write Response Channel (B) .axi_bid(axi_bid), .axi_bresp(axi_bresp), .axi_buser(axi_buser), .axi_bvalid(axi_bvalid), .axi_bready(axi_bready) `RVFI_BUS_CHANNEL_CONN(0) ); rvfi_bus_axi4_observer_read axi_read ( .clock(clock), .reset(reset), // Read Address Channel (AR) .axi_arid(axi_arid), .axi_araddr(axi_araddr), .axi_arregion(axi_arregion), .axi_arlen(axi_arlen), .axi_arsize(axi_arsize), .axi_arburst(axi_arburst), .axi_arlock(axi_arlock), .axi_arcache(axi_arcache), .axi_arprot(axi_arprot), .axi_arqos(axi_arqos), .axi_aruser(axi_aruser), .axi_arvalid(axi_arvalid), .axi_arready(axi_arready), // Read Data Channel (R) .axi_rid(axi_rid), .axi_rdata(axi_rdata), .axi_rresp(axi_rresp), .axi_rlast(axi_rlast), .axi_ruser(axi_ruser), .axi_rvalid(axi_rvalid), .axi_rready(axi_rready) `RVFI_BUS_CHANNEL_CONN(1) ); `endif rvfi_bus_axi4_abstract_read ram_read ( .clock(clock), .reset(reset), // Read Address Channel (AR) .axi_arid(axi_arid), .axi_araddr(axi_araddr), .axi_arregion(axi_arregion), .axi_arlen(axi_arlen), .axi_arsize(axi_arsize), .axi_arburst(axi_arburst), .axi_arlock(axi_arlock), .axi_arcache(axi_arcache), .axi_arprot(axi_arprot), .axi_arqos(axi_arqos), .axi_aruser(axi_aruser), .axi_arvalid(axi_arvalid), .axi_arready(axi_arready), // Read Data Channel (R) .axi_rid(axi_rid), .axi_rdata(axi_rdata), .axi_rresp(axi_rresp), .axi_rlast(axi_rlast), .axi_ruser(axi_ruser), .axi_rvalid(axi_rvalid), .axi_rready(axi_rready) ); rvfi_bus_axi4_abstract_write ram_write ( .clock(clock), .reset(reset), // Write Address Channel (AW) .axi_awid(axi_awid), .axi_awaddr(axi_awaddr), .axi_awregion(axi_awregion), .axi_awlen(axi_awlen), .axi_awsize(axi_awsize), .axi_awburst(axi_awburst), .axi_awlock(axi_awlock), .axi_awcache(axi_awcache), .axi_awprot(axi_awprot), .axi_awqos(axi_awqos), .axi_awuser(axi_awuser), .axi_awvalid(axi_awvalid), .axi_awready(axi_awready), // Write Data Channel (W) .axi_wdata(axi_wdata), .axi_wstrb(axi_wstrb), .axi_wlast(axi_wlast), .axi_wuser(axi_wuser), .axi_wvalid(axi_wvalid), .axi_wready(axi_wready), // Write Response Channel (B) .axi_bid(axi_bid), .axi_bresp(axi_bresp), .axi_buser(axi_buser), .axi_bvalid(axi_bvalid), .axi_bready(axi_bready) ); `ifdef NERV_FAIRNESS reg [2:0] stalled = 0; always @(posedge clock) begin stalled <= {stalled, random_stall}; assume (~stalled); end `endif endmodule ================================================ FILE: cores/nerv/axi_cache/wrapper_internal.sv ================================================ /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 Claire Xenia Wolf * Copyright (C) 2023 Jannis Harder * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ module rvfi_wrapper ( input clock, input reset, `RVFI_OUTPUTS `RVFI_BUS_OUTPUTS ); (* keep *) `rvformal_rand_reg random_stall; (* keep *) `rvformal_rand_reg [31:0] irq; wire imem_fault; wire dmem_fault; (* keep *) wire trap; (* keep *) wire [31:0] imem_addr; (* keep *) wire [31:0] imem_data; (* keep *) wire dmem_valid; (* keep *) wire [31:0] dmem_addr; (* keep *) wire [ 3:0] dmem_wstrb; (* keep *) wire [31:0] dmem_wdata; (* keep *) wire [31:0] dmem_rdata; wire icache_stall, dcache_stall; wire stall = random_stall || icache_stall || dcache_stall; wire [31:0] imem_req_addr; wire imem_req_valid; reg [255:0] imem_res_data; reg imem_res_fault; reg imem_res_valid; wire [31:0] dmem_req_r_addr; wire dmem_req_r_valid; reg [255:0] dmem_res_r_data; reg dmem_res_r_fault; reg dmem_res_r_valid; wire [31:0] dmem_req_w_addr; wire [255:0] dmem_req_w_data; wire dmem_req_w_valid; reg dmem_res_w_fault; reg dmem_res_w_valid; nerv_axi_cache_icache #(.LINE_SIZE(5), .INDEX_SIZE(1)) icache ( .clock(clock), .reset(reset), .stalled(stall), .stall(icache_stall), .imem_addr(imem_addr), .imem_data(imem_data), .imem_fault(imem_fault), .req_addr(imem_req_addr), .req_valid(imem_req_valid), .res_data(imem_res_data), .res_fault(imem_res_fault), .res_valid(imem_res_valid) ); nerv_axi_cache_dcache #(.LINE_SIZE(5), .INDEX_SIZE(1)) dcache ( .clock(clock), .reset(reset), .stalled(stall), .stall(dcache_stall), .dmem_valid(dmem_valid), .dmem_addr(dmem_addr), .dmem_wstrb(dmem_wstrb), .dmem_wdata(dmem_wdata), .dmem_rdata(dmem_rdata), .dmem_fault(dmem_fault), .req_r_addr(dmem_req_r_addr), .req_r_valid(dmem_req_r_valid), .res_r_data(dmem_res_r_data), .res_r_fault(dmem_res_r_fault), .res_r_valid(dmem_res_r_valid), .req_w_addr(dmem_req_w_addr), .req_w_data(dmem_req_w_data), .req_w_valid(dmem_req_w_valid), .res_w_fault(dmem_res_w_fault), .res_w_valid(dmem_res_w_valid) ); nerv uut ( .clock (clock ), .reset (reset ), .stall (stall ), .trap (trap ), .imem_addr (imem_addr ), .imem_data (imem_data ), .dmem_valid (dmem_valid), .dmem_addr (dmem_addr ), .dmem_wstrb (dmem_wstrb), .dmem_wdata (dmem_wdata), .dmem_rdata (dmem_rdata), `ifdef NERV_FAULT .imem_fault (imem_fault), .dmem_fault (dmem_fault), `endif .irq (irq), `RVFI_CONN32 ); `ifdef RISCV_FORMAL_BUS `define RISCV_FORMAL_CHANNEL_SIGNAL(channels, width, name) \ (* keep *) reg [(width) - 1:0] imem_``name; assign rvfi_``name[0 * (width) +: (width)] = imem_``name; `RVFI_BUS_SIGNALS `undef RISCV_FORMAL_CHANNEL_SIGNAL `define RISCV_FORMAL_CHANNEL_SIGNAL(channels, width, name) \ (* keep *) reg [(width) - 1:0] dmem_r_``name; assign rvfi_``name[1 * (width) +: (width)] = dmem_r_``name; `RVFI_BUS_SIGNALS `undef RISCV_FORMAL_CHANNEL_SIGNAL `define RISCV_FORMAL_CHANNEL_SIGNAL(channels, width, name) \ (* keep *) reg [(width) - 1:0] dmem_w_``name; assign rvfi_``name[2 * (width) +: (width)] = dmem_w_``name; `RVFI_BUS_SIGNALS `undef RISCV_FORMAL_CHANNEL_SIGNAL (* keep *) `rvformal_rand_reg [`RISCV_FORMAL_BUSLEN-1:0] next_imem_res_data; (* keep *) `rvformal_rand_reg next_imem_res_fault; (* keep *) `rvformal_rand_reg next_imem_res_valid; logic imem_req_valid_q; always @(posedge clock) begin imem_res_data <= next_imem_res_data; imem_res_fault <= next_imem_res_fault; imem_res_valid <= next_imem_res_valid && imem_req_valid && !imem_req_valid_q; imem_req_valid_q <= imem_req_valid && !reset; end always @* begin imem_bus_addr = imem_req_addr; imem_bus_insn = 1; imem_bus_data = 0; imem_bus_rmask = {`RISCV_FORMAL_BUSLEN / 8{1'b1}}; imem_bus_wmask = {`RISCV_FORMAL_BUSLEN / 8{1'b0}}; imem_bus_rdata = next_imem_res_data; imem_bus_wdata = 0; imem_bus_fault = next_imem_res_fault; imem_bus_valid = next_imem_res_valid && imem_req_valid && !imem_req_valid_q; end (* keep *) `rvformal_rand_reg [`RISCV_FORMAL_BUSLEN-1:0] next_dmem_res_r_data; (* keep *) `rvformal_rand_reg next_dmem_res_r_valid; (* keep *) `rvformal_rand_reg next_dmem_res_r_fault; logic dmem_req_r_valid_q; always @(posedge clock) begin dmem_res_r_data <= next_dmem_res_r_data; dmem_res_r_fault <= next_dmem_res_r_fault; dmem_res_r_valid <= next_dmem_res_r_valid && dmem_req_r_valid && !dmem_req_r_valid_q; dmem_req_r_valid_q <= dmem_req_r_valid && !reset; end always @* begin dmem_r_bus_addr = dmem_req_r_addr; dmem_r_bus_insn = 0; dmem_r_bus_data = 1; dmem_r_bus_rmask = {`RISCV_FORMAL_BUSLEN / 8{1'b1}}; dmem_r_bus_wmask = {`RISCV_FORMAL_BUSLEN / 8{1'b0}}; dmem_r_bus_rdata = next_dmem_res_r_data; dmem_r_bus_wdata = 0; dmem_r_bus_fault = next_dmem_res_r_fault; dmem_r_bus_valid = next_dmem_res_r_valid && dmem_req_r_valid && !dmem_req_r_valid_q; end (* keep *) `rvformal_rand_reg next_dmem_res_w_valid; (* keep *) `rvformal_rand_reg next_dmem_res_w_fault; logic dmem_req_w_valid_q; always @(posedge clock) begin dmem_res_w_valid <= next_dmem_res_w_valid && dmem_req_w_valid && !dmem_req_w_valid_q; dmem_res_w_fault <= next_dmem_res_w_fault; dmem_req_w_valid_q <= dmem_req_w_valid && !reset; end always @* begin dmem_w_bus_addr = dmem_req_w_addr; dmem_w_bus_insn = 0; dmem_w_bus_data = 1; dmem_w_bus_rmask = {`RISCV_FORMAL_BUSLEN / 8{1'b0}}; dmem_w_bus_wmask = {`RISCV_FORMAL_BUSLEN / 8{1'b1}}; dmem_w_bus_rdata = 0; dmem_w_bus_wdata = dmem_req_w_data; dmem_w_bus_fault = next_dmem_res_w_fault; dmem_w_bus_valid = next_dmem_res_w_valid && dmem_req_w_valid && !dmem_req_w_valid_q; end `endif `ifdef NERV_FAIRNESS reg [2:0] stalled = 0; always @(posedge clock) begin stalled <= {stalled, stall}; assume (~stalled); end `endif endmodule ================================================ FILE: cores/nerv/cexdata.sh ================================================ #!/bin/bash # # NERV -- Naive Educational RISC-V Processor # # Copyright (C) 2020 Claire Xenia Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. set -ex rm -rf cexdata mkdir cexdata for x in {checks,testbug[0-9][0-9][0-9]}/*/FAIL; do test -f $x || continue x=${x%/FAIL} y=${x/\//_} cp $x/logfile.txt cexdata/$y.log if test -f $x/engine_*/trace.vcd; then cp $x/engine_*/trace.vcd cexdata/$y.vcd python3 disasm.py cexdata/$y.vcd > cexdata/$y.asm fi done sed -re '/WARNING|[Ww]arning/ ! d; /\[VERI-1927\] .*\/wrapper.sv:/ d; s/^([^:]|:[^ ])*: //;' checks/*/logfile.txt | sort -Vu > cexdata/warnings.txt for x in {checks,testbug[0-9][0-9][0-9]}/*.sby; do test -f $x || continue x=${x%.sby} if [ -f $x/PASS ]; then printf "%-30s %s %10s\n" $x " pass " $(sed '/Elapsed process time/ { s/.*\]: //; s/ .*//; p; }; d;' $x/logfile.txt) elif [ -f $x/FAIL ]; then printf "%-30s %s %10s\n" $x "**FAIL**" $(sed '/Elapsed process time/ { s/.*\]: //; s/ .*//; p; }; d;' $x/logfile.txt) else printf "%-30s %s\n" $x unknown fi done | awk '{ print gensub(":", "", "g", $3), $0; }' | sort -n | cut -f2- -d' ' > cexdata/status.txt ================================================ FILE: cores/nerv/checks.cfg ================================================ # NERV -- Naive Educational RISC-V Processor # # Copyright (C) 2020 Claire Xenia Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. [options] isa rv32i nbus 2 csr_spec 1.12 [depth] insn 10 reg 5 10 pc_fwd 5 10 pc_bwd 5 10 unique 1 5 10 causal 5 10 cover 1 10 ill 10 csrw 10 csr_ill 10 bus_imem 1 10 bus_imem_fault 1 10 bus_dmem 1 10 bus_dmem_fault 1 10 csrc_zero 1 5 csrc_any 1 5 csrc_inc 1 5 csrc_const 1 5 csrc_upcnt 1 10 csrc_hpm 1 10 [sort] reg_ch0 bus_[id]mem(_fault)?_ch0 insn_[ls][bhw]u?_ch0 csrc_upcnt_(.*)_ch0 [csrs] mcycle upcnt minstret upcnt mhpmcounter5 inc mhpmevent5 hpm=1 mhpmevent9 hpm=2 mhpmevent3 hpm=3 [custom_csrs] fc0 m custom_ro const="32'h dead_beef" bc0 mu custom any [illegal_csrs] fff msu rw f11 m w [defines] `define YOSYS // Hotfix for older Tabby CAD Releases `define NERV_RVFI `define NERV_FAULT `define RISCV_FORMAL_ALIGNED_MEM `define RISCV_FORMAL_MEM_FAULT [defines liveness] `define NERV_FAIRNESS [verilog-files] @basedir@/cores/@core@/wrapper.sv @basedir@/cores/@core@/@core@.sv [cover] always @* if (!reset) cover (channel[0].cnt_insns == 2); always @* if (!reset) cover (rvfi_csr_mstatus_rdata[3] != 0 && rvfi_valid == 1); ================================================ FILE: cores/nerv/disasm.py ================================================ #!/usr/bin/env python3 # # NERV -- Naive Educational RISC-V Processor # # Copyright (C) 2020 Claire Xenia Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. from Verilog_VCD.Verilog_VCD import parse_vcd from os import system from sys import argv rvfi_valid = None rvfi_order = None rvfi_insn = None for netinfo in parse_vcd(argv[1]).values(): for net in netinfo['nets']: # print(net["hier"], net["name"]) if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_valid": rvfi_valid = netinfo['tv'] if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_order": rvfi_order = netinfo['tv'] if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_insn": rvfi_insn = netinfo['tv'] assert len(rvfi_valid) == len(rvfi_order) assert len(rvfi_valid) == len(rvfi_insn) prog = list() for tv_valid, tv_order, tv_insn in zip(rvfi_valid, rvfi_order, rvfi_insn): if tv_valid[1] == '1': prog.append((int(tv_order[1], 2), int(tv_insn[1], 2))) with open("disasm.s", "w") as f: for tv_order, tv_insn in sorted(prog): if tv_insn & 3 != 3 and tv_insn & 0xffff0000 == 0: print(".hword 0x%04x # %d" % (tv_insn, tv_order), file=f) else: print(".word 0x%08x # %d" % (tv_insn, tv_order), file=f) system("riscv64-unknown-elf-as -march=rv32i -o disasm.o disasm.s") system("riscv64-unknown-elf-objdump -d -M numeric,no-aliases disasm.o") ================================================ FILE: cores/nerv/examples/icebreaker/.gitignore ================================================ /testbench.vcd /firmware.elf /firmware.hex /testbench /*.log /design.* ================================================ FILE: cores/nerv/examples/icebreaker/Makefile ================================================ # NERV -- Naive Educational RISC-V Processor # # Copyright (C) 2020 N. Engelhardt # Copyright (C) 2020 Claire Xenia Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. TOOLCHAIN_PREFIX?=riscv64-unknown-elf- test: firmware.hex testbench vvp -N testbench +vcd firmware.elf: firmware.s firmware.c $(TOOLCHAIN_PREFIX)gcc -march=rv32i -mabi=ilp32 -Os -Wall -Wextra -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $^ firmware.hex: firmware.elf $(TOOLCHAIN_PREFIX)objcopy -O verilog $< /dev/stdout | sed -r 's,(..) (..) (..) (..),\4\3\2\1,g' > $@ testbench: testbench.sv ../../nerv.sv ../../nervsoc.sv top.v firmware.hex iverilog -o testbench -D STALL -D NERV_DBGREGS testbench.sv ../../nerv.sv ../../nervsoc.sv top.v design.json: ../../nerv.sv ../../nervsoc.sv top.v firmware.hex yosys -l design_ys.log -p 'synth_ice40 -top top -json $@' ../../nerv.sv ../../nervsoc.sv top.v design.asc: design.json icebreaker.pcf nextpnr-ice40 -l design_pnr.log --up5k --package sg48 --asc design.asc --pcf icebreaker.pcf --json design.json --placer heap design.bin: design.asc icepack $< $@ prog: design.bin iceprog $< show: gtkwave testbench.vcd testbench.gtkw >> gtkwave.log 2>&1 & clean: rm -rf firmware.elf firmware.hex testbench testbench.vcd gtkwave.log rm -rf design.json design.asc design.bin design_ys.log design_pnr.log ================================================ FILE: cores/nerv/examples/icebreaker/README.md ================================================ # SOC example for iCEBreaker ![iCEBreaker SOC](icebreaker_soc.png) # Demo Counts on the 8 LEDs. ``` make prog ``` # SOC The SOC instantiates [nervsoc](../../nervsoc.sv). * [top.v](top.v) Connects clock input and 8 LEDs on the iCEBreaker and provides power on reset * [sections.lds](sections.lds) sets flash and ram to 4k each. * [firmware.s](firmware.s) initialises registers, copies data section, initialises bss and starts main * [firmware.c](firmware.c) flashes the LEDs. ================================================ FILE: cores/nerv/examples/icebreaker/firmware.c ================================================ /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 Miodrag Milanovic * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include void delay(uint32_t count) { while(count-->0) { __asm__ volatile ("nop"); } } int main() { volatile uint32_t *leds = (void*)0x01000000; *leds = 0; uint32_t cnt = 0; while(1) { delay(100000); *leds = cnt++; } return 0; } ================================================ FILE: cores/nerv/examples/icebreaker/firmware.s ================================================ /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 Claire Xenia Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ .section .text .global main .global _start _start: addi x1, zero, 0 addi x2, zero, 0 addi x3, zero, 0 addi x4, zero, 0 addi x5, zero, 0 addi x6, zero, 0 addi x7, zero, 0 addi x8, zero, 0 addi x9, zero, 0 addi x10, zero, 0 addi x11, zero, 0 addi x12, zero, 0 addi x13, zero, 0 addi x14, zero, 0 addi x15, zero, 0 addi x16, zero, 0 addi x17, zero, 0 addi x18, zero, 0 addi x19, zero, 0 addi x20, zero, 0 addi x21, zero, 0 addi x22, zero, 0 addi x23, zero, 0 addi x24, zero, 0 addi x25, zero, 0 addi x26, zero, 0 addi x27, zero, 0 addi x28, zero, 0 addi x29, zero, 0 addi x30, zero, 0 addi x31, zero, 0 # copy data section la a0, _sidata la a1, _sdata la a2, _edata bge a1, a2, end_init_data loop_init_data: lw a3, 0(a0) sw a3, 0(a1) addi a0, a0, 4 addi a1, a1, 4 blt a1, a2, loop_init_data end_init_data: # zero-init bss section la a0, _sbss la a1, _ebss bge a0, a1, end_init_bss loop_init_bss: sw zero, 0(a0) addi a0, a0, 4 blt a0, a1, loop_init_bss end_init_bss: # place SP at the end of RAM li sp, 0x00001000 # call main call main # halt ebreak ================================================ FILE: cores/nerv/examples/icebreaker/icebreaker.pcf ================================================ # 12 MHz clock set_io -nowarn CLK 35 # RS232 set_io -nowarn RX 6 set_io -nowarn TX 9 # LEDs and Button set_io -nowarn BTN_N 10 set_io -nowarn LEDR_N 11 set_io -nowarn LEDG_N 37 # RGB LED Driver set_io -nowarn LED_RED_N 39 set_io -nowarn LED_GRN_N 40 set_io -nowarn LED_BLU_N 41 # SPI Flash set_io -nowarn FLASH_SCK 15 set_io -nowarn FLASH_SSB 16 set_io -nowarn FLASH_IO0 14 set_io -nowarn FLASH_IO1 17 set_io -nowarn FLASH_IO2 12 set_io -nowarn FLASH_IO3 13 # PMOD 1A set_io -nowarn P1A1 4 set_io -nowarn P1A2 2 set_io -nowarn P1A3 47 set_io -nowarn P1A4 45 set_io -nowarn P1A7 3 set_io -nowarn P1A8 48 set_io -nowarn P1A9 46 set_io -nowarn P1A10 44 # PMOD 1B set_io -nowarn P1B1 43 set_io -nowarn P1B2 38 set_io -nowarn P1B3 34 set_io -nowarn P1B4 31 set_io -nowarn P1B7 42 set_io -nowarn P1B8 36 set_io -nowarn P1B9 32 set_io -nowarn P1B10 28 # PMOD 2 set_io -nowarn P2_1 27 set_io -nowarn P2_2 25 set_io -nowarn P2_3 21 set_io -nowarn P2_4 19 set_io -nowarn P2_7 26 set_io -nowarn P2_8 23 set_io -nowarn P2_9 20 set_io -nowarn P2_10 18 # LEDs and Buttons (PMOD 2) set_io -nowarn LED1 27 set_io -nowarn LED2 25 set_io -nowarn LED3 21 set_io -nowarn BTN2 19 set_io -nowarn LED5 26 set_io -nowarn LED4 23 set_io -nowarn BTN1 20 set_io -nowarn BTN3 18 ================================================ FILE: cores/nerv/examples/icebreaker/sections.lds ================================================ MEMORY { FLASH(xr) : ORIGIN = 0x00000000, LENGTH = 0x001000 RAM (rw) : ORIGIN = 0x00000000, LENGTH = 0x001000 } SECTIONS { /* The program code and other data goes into FLASH */ .text : { . = ALIGN(4); *(.text) /* .text sections (code) */ *(.text*) /* .text* sections (code) */ *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ *(.srodata) /* .rodata sections (constants, strings, etc.) */ *(.srodata*) /* .rodata* sections (constants, strings, etc.) */ . = ALIGN(4); _etext = .; /* define a global symbol at end of code */ _sidata = _etext; /* This is used by the startup in order to initialize the .data secion */ } >FLASH /* This is the initialized data section The program executes knowing that the data is in the RAM but the loader puts the initial values in the FLASH (inidata). It is one task of the startup to copy the initial values from FLASH to RAM. */ .data : AT ( _sidata ) { . = ALIGN(4); _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ _ram_start = .; /* create a global symbol at ram start for garbage collector */ . = ALIGN(4); *(.data) /* .data sections */ *(.data*) /* .data* sections */ *(.sdata) /* .sdata sections */ *(.sdata*) /* .sdata* sections */ . = ALIGN(4); _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ } >RAM /* Uninitialized data section */ .bss : { . = ALIGN(4); _sbss = .; /* define a global symbol at bss start; used by startup code */ *(.bss) *(.bss*) *(.sbss) *(.sbss*) *(COMMON) . = ALIGN(4); _ebss = .; /* define a global symbol at bss end; used by startup code */ } >RAM /* this is to define the start of the heap, and make sure we have a minimum size */ .heap : { . = ALIGN(4); _heap_start = .; /* define a global symbol at heap start */ } >RAM } ================================================ FILE: cores/nerv/examples/icebreaker/testbench.gtkw ================================================ [*] [*] GTKWave Analyzer v3.3.108 (w)1999-2020 BSI [*] Tue Nov 3 15:34:10 2020 [*] [dumpfile] "/home/matt/work/symbiotic/riscv-formal/cores/nerv/examples/icebreaker/testbench.vcd" [dumpfile_mtime] "Tue Nov 3 15:33:50 2020" [dumpfile_size] 472777 [savefile] "/home/matt/work/symbiotic/riscv-formal/cores/nerv/examples/icebreaker/testbench.gtkw" [timestart] 0 [size] 1920 1015 [pos] -1 -1 *-11.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] testbench. [treeopen] testbench.dut. [treeopen] testbench.dut.soc. [sst_width] 240 [signals_width] 286 [sst_expanded] 1 [sst_vpaned_height] 289 @28 testbench.LEDR_N testbench.LEDG_N testbench.LED1 testbench.LED2 testbench.LED3 testbench.LED4 testbench.LED5 @201 - @28 testbench.clock @22 testbench.cycles[31:0] @200 - @28 testbench.dut.soc.clock @22 testbench.dut.soc.dmem_addr[31:0] testbench.dut.soc.dmem_rdata[31:0] @28 testbench.dut.soc.dmem_valid @22 testbench.dut.soc.dmem_wdata[31:0] testbench.dut.soc.dmem_wstrb[3:0] testbench.dut.soc.imem_addr[31:0] testbench.dut.soc.imem_data[31:0] testbench.dut.soc.leds[31:0] @28 testbench.dut.soc.reset testbench.dut.soc.stall testbench.dut.soc.trap [pattern_trace] 1 [pattern_trace] 0 ================================================ FILE: cores/nerv/examples/icebreaker/testbench.sv ================================================ /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 N. Engelhardt * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ module testbench; localparam TIMEOUT = (1<<10); reg clock; wire LEDR_N, LEDG_N, LED1, LED2, LED3, LED4, LED5; always #5 clock = clock === 1'b0; top dut ( .CLK(clock), .LEDR_N(LEDR_N), .LEDG_N(LEDG_N), .LED1(LED1), .LED2(LED2), .LED3(LED3), .LED4(LED4), .LED5(LED5) ); initial begin if ($test$plusargs("vcd")) begin $dumpfile("testbench.vcd"); $dumpvars(0, testbench); end end reg [31:0] cycles = 0; always @(posedge clock) begin cycles <= cycles + 32'h1; if (cycles >= TIMEOUT) begin $display("Simulated %0d cycles", cycles); $finish; end end endmodule ================================================ FILE: cores/nerv/examples/icebreaker/top.v ================================================ /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 Miodrag Milanovic * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ module top( input CLK, output LEDR_N, output LEDG_N, output LED1, output LED2, output LED3, output LED4, output LED5 ); // Create reset signal 16 clocks long reg reset = 1'b1; reg [3:0] reset_cnt = 0; always @(posedge CLK) begin reset <= (reset_cnt != 15); reset_cnt <= reset_cnt + (reset_cnt != 15); end // Map 7 LEDs that exists on icebreaker board wire [31:0] leds; assign { LEDR_N, LEDG_N, LED1, LED2, LED3, LED4, LED5 } = {~leds[6:5], leds[4:0]}; nervsoc soc ( .clock(CLK), .reset(reset), .leds(leds) ); endmodule ================================================ FILE: cores/nerv/firmware.c ================================================ /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 Claire Xenia Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ void putc(int c) { volatile char *p = (void*)0x02000000; *p = c; } void puts(char *s) { while (*s) putc(*(s++)); } int main() { puts("Hello World!\n"); putc(0); return 0; } ================================================ FILE: cores/nerv/firmware.s ================================================ /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 Claire Xenia Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ .section .text .global main .global _start _start: addi x1, zero, 0 addi x2, zero, 0 addi x3, zero, 0 addi x4, zero, 0 addi x5, zero, 0 addi x6, zero, 0 addi x7, zero, 0 addi x8, zero, 0 addi x9, zero, 0 addi x10, zero, 0 addi x11, zero, 0 addi x12, zero, 0 addi x13, zero, 0 addi x14, zero, 0 addi x15, zero, 0 addi x16, zero, 0 addi x17, zero, 0 addi x18, zero, 0 addi x19, zero, 0 addi x20, zero, 0 addi x21, zero, 0 addi x22, zero, 0 addi x23, zero, 0 addi x24, zero, 0 addi x25, zero, 0 addi x26, zero, 0 addi x27, zero, 0 addi x28, zero, 0 addi x29, zero, 0 addi x30, zero, 0 addi x31, zero, 0 # place SP at the end of RAM li sp, 0x00010000 # set vector table address and vectored mode la a0, __vector_start ori a0, a0, 0x1 csrw mtvec, a0 # enable all interrupts li a0, 0xffffffff csrw mie, a0 # set mie bit csrr a0, mstatus ori a0, a0, 0x8 csrw mstatus, a0 # copy data section la a0, _sidata la a1, _sdata la a2, _edata bge a1, a2, end_init_data loop_init_data: lw a3, 0(a0) sw a3, 0(a1) addi a0, a0, 4 addi a1, a1, 4 blt a1, a2, loop_init_data end_init_data: # zero-init bss section la a0, _sbss la a1, _ebss bge a0, a1, end_init_bss loop_init_bss: sw zero, 0(a0) addi a0, a0, 4 blt a0, a1, loop_init_bss end_init_bss: # call main call main #ecall #wfi # halt ebreak end_of_file: j end_of_file ================================================ FILE: cores/nerv/imemcheck.sby ================================================ [options] mode prove depth 10 [engines] smtbmc bitwuzla [script] read -sv defines.sv rvfi_imem_check.sv imemcheck.sv nerv.sv prep -flatten -nordff -top testbench chformal -early [files] imemcheck.sv nerv.sv ../../checks/rvfi_macros.vh ../../checks/rvfi_imem_check.sv [file defines.sv] `define RISCV_FORMAL `define RISCV_FORMAL_NRET 1 `define RISCV_FORMAL_XLEN 32 `define RISCV_FORMAL_ILEN 32 `define NERV_RVFI `define NERV_FAIRNESS # Required to make k-induction work `define RISCV_FORMAL_ALIGNED_MEM `include "rvfi_macros.vh" ================================================ FILE: cores/nerv/imemcheck.sv ================================================ /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 Claire Xenia Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ module testbench ( input clock, `RVFI_OUTPUTS ); reg reset = 1; always @(posedge clock) reset <= 0; (* keep *) `rvformal_rand_reg stall; (* keep *) `rvformal_rand_reg [31:0] imem_data; (* keep *) `rvformal_rand_reg [31:0] dmem_rdata; (* keep *) wire [31:0] imem_addr; (* keep *) wire dmem_valid; (* keep *) wire [31:0] dmem_addr; (* keep *) wire [ 3:0] dmem_wstrb; (* keep *) wire [31:0] dmem_wdata; wire [31:0] check_imem_addr; wire [15:0] check_imem_data; rvfi_imem_check checker_inst ( .clock(clock), .reset(reset), .enable(1'b1), .imem_addr(check_imem_addr), .imem_data(check_imem_data), `RVFI_CONN ); reg [31:0] imem_addr_q; always @(posedge clock) begin imem_addr_q <= imem_addr; end always @* begin if (!reset && !stall) begin if (imem_addr_q == check_imem_addr) assume(imem_data[15:0] == check_imem_data); if (imem_addr_q+2 == check_imem_addr) assume(imem_data[31:16] == check_imem_data); end end nerv uut ( .clock (clock ), .reset (reset ), .stall (stall ), .imem_addr (imem_addr ), .imem_data (imem_data ), .dmem_valid (dmem_valid), .dmem_addr (dmem_addr ), .dmem_wstrb (dmem_wstrb), .dmem_wdata (dmem_wdata), .dmem_rdata (dmem_rdata), `RVFI_CONN ); `ifdef NERV_FAIRNESS reg [2:0] stalled = 0; always @(posedge clock) begin stalled <= {stalled, stall}; assume (~stalled); end `endif endmodule ================================================ FILE: cores/nerv/nerv.sv ================================================ /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 Claire Xenia Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ `define NERV_CSR `ifdef NERV_CSR /********************** * CSR DECLARATIONS * **********************/ // Note: The Memory-Mapped Machine Timers (mtime and timecmp) are not // part of the processor core itself. It's up to the SoC to provide // this part of the RISC-V M-Mode Spec. // FIXME: Additional instructions: ECALL, EBREAK, MRET, WFI `define NERV_MACHINE_CSRS /* Machine Information CSRs */ \ /* all of these CSRs are mandatory but can legally be all 0 */ \ `NERV_CSR_VAL_MRO(mvendorid, 12'h F11, 32'h 0000_0000) \ `NERV_CSR_VAL_MRO(marchid, 12'h F12, 32'h 0000_0000) \ `NERV_CSR_VAL_MRO(mimpid, 12'h F13, 32'h 0000_0000) \ `NERV_CSR_VAL_MRO(mhartid, 12'h F14, 32'h 0000_0000) \ `NERV_CSR_VAL_MRO(mconfigptr, 12'h F15, 32'h 0000_0000) `define NERV_TRAP_SETUP_CSRS /* Machine Trap Setup CSRs */ \ `NERV_CSR_REG_MRW(mstatus, 12'h 300, 32'h 0000_0000) \ \ /* misa can legally return all zeros */ \ `NERV_CSR_REG_MRW(misa, 12'h 301, 32'h 0000_0000) \ \ /* medeleg and mideleg should only exist if S mode is available */ \ /* `NERV_CSR_REG_MRW(medeleg, 12'h 302, 32'h 0000_0000) */ \ /* `NERV_CSR_REG_MRW(mideleg, 12'h 303, 32'h 0000_0000) */ \ \ `NERV_CSR_REG_MRW(mie, 12'h 304, 32'h 0000_0000) \ \ /* mtvec can be implemented as read-only */ \ `NERV_CSR_REG_MRW(mtvec, 12'h 305, 32'h 0000_0000) \ \ /* mcounteren should only exist if U mode is available */ \ /* `NERV_CSR_REG_MRW(mcounteren, 12'h 306, 32'h 0000_0000) */ \ \ `NERV_CSR_REG_MRW(mstatush, 12'h 310, 32'h 0000_0000) `define NERV_TRAP_HANDLING_CSRS /* Machine Trap Handling CSRs */ \ `NERV_CSR_REG_MRW(mscratch, 12'h 340, 32'h 0000_0000) \ `NERV_CSR_REG_MRW(mepc, 12'h 341, 32'h 0000_0000) \ `NERV_CSR_REG_MRW(mcause, 12'h 342, 32'h 0000_0000) \ `NERV_CSR_REG_MRW(mtval, 12'h 343, 32'h 0000_0000) \ `NERV_CSR_REG_MRW(mip, 12'h 344, 32'h 0000_0000) \ \ /* mtinst and mtval2 added by hypervisor extension */ \ /* `NERV_CSR_REG_MRW(mtinst, 12'h 34A, 32'h 0000_0000) */ \ /* `NERV_CSR_REG_MRW(mtval2, 12'h 34B, 32'h 0000_0000) */ `define NERV_MACHINE_CONFIG_CSRS /* machine configuration CSRs */ \ /* menvcfg should only exist if U mode is available */ \ /* `NERV_CSR_REG_MRW(menvcfg, 12'h 30A, 32'h 0000_0000) */ \ /* `NERV_CSR_REG_MRW(menvcfgh, 12'h 31A, 32'h 0000_0000) */ \ \ /* mseccfg not yet fully defined, and is not currently required */ \ /* `NERV_CSR_REG_MRW(mseccfg, 12'h 747, 32'h 0000_0000) */ \ /* `NERV_CSR_REG_MRW(mseccfgh, 12'h 757, 32'h 0000_0000) */ `ifdef NERV_PMP /* PMP is optional and can be implemented with 0, 16, or 64 address CSRS */ `define NERV_PMP_CFG_CSRS /* Machine Memory Protection Config CSRs */ \ /* PMP configuration is 8-bits long, */ \ /* so each cfg controls four PMPs in RV32 */ \ `NERV_CSR_VAL_MRW(pmpcfg0, 12'h 3A0, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg1, 12'h 3A1, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg2, 12'h 3A2, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg3, 12'h 3A3, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg4, 12'h 3A4, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg5, 12'h 3A5, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg6, 12'h 3A6, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg7, 12'h 3A7, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg8, 12'h 3A8, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg9, 12'h 3A9, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg10, 12'h 3AA, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg11, 12'h 3AB, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg12, 12'h 3AC, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg13, 12'h 3AD, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg14, 12'h 3AE, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpcfg15, 12'h 3AF, 32'h 0000_0000) `define NERV_PMP_ADDR_CSRS /* Machine Memory Protection Addr CSRs */ \ `NERV_CSR_VAL_MRW(pmpaddr0, 12'h 3B0, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr1, 12'h 3B1, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr2, 12'h 3B2, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr3, 12'h 3B3, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr4, 12'h 3B4, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr5, 12'h 3B5, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr6, 12'h 3B6, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr7, 12'h 3B7, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr8, 12'h 3B8, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr9, 12'h 3B9, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr10, 12'h 3BA, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr11, 12'h 3BB, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr12, 12'h 3BC, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr13, 12'h 3BD, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr14, 12'h 3BE, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr15, 12'h 3BF, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr16, 12'h 3C0, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr17, 12'h 3C1, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr18, 12'h 3C2, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr19, 12'h 3C3, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr20, 12'h 3C4, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr21, 12'h 3C5, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr22, 12'h 3C6, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr23, 12'h 3C7, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr24, 12'h 3C8, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr25, 12'h 3C9, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr26, 12'h 3CA, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr27, 12'h 3CB, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr28, 12'h 3CC, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr29, 12'h 3CD, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr30, 12'h 3CE, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr31, 12'h 3CF, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr32, 12'h 3D0, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr33, 12'h 3D1, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr34, 12'h 3D2, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr35, 12'h 3D3, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr36, 12'h 3D4, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr37, 12'h 3D5, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr38, 12'h 3D6, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr39, 12'h 3D7, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr40, 12'h 3D8, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr41, 12'h 3D9, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr42, 12'h 3DA, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr43, 12'h 3DB, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr44, 12'h 3DC, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr45, 12'h 3DD, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr46, 12'h 3DE, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr47, 12'h 3DF, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr48, 12'h 3E0, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr49, 12'h 3E1, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr50, 12'h 3E2, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr51, 12'h 3E3, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr52, 12'h 3E4, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr53, 12'h 3E5, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr54, 12'h 3E6, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr55, 12'h 3E7, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr56, 12'h 3E8, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr57, 12'h 3E9, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr58, 12'h 3EA, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr59, 12'h 3EB, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr60, 12'h 3EC, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr61, 12'h 3ED, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr62, 12'h 3EE, 32'h 0000_0000) \ `NERV_CSR_VAL_MRW(pmpaddr63, 12'h 3EF, 32'h 0000_0000) `else `define NERV_PMP_CFG_CSRS `define NERV_PMP_ADDR_CSRS `endif `define NERV_COUNTER_CSRS /* Machine Counter/Timers CSRs */ \ `NERV_CSR_ARR_DEF(hpm_counter, 32) \ `NERV_CSR_ARR_MRW(hpm_counter, 0, mcycle, 12'h B00) \ `NERV_CSR_ARR_MRW(hpm_counter, 2, minstret, 12'h B02) \ \ /* mhpmcounter3..31 provide hardware performance monitoring */ \ /* the counted event is defined by the corresponding hpm_event CSR */ \ `NERV_CSR_ARR_MRW(hpm_counter, 3, mhpmcounter3, 12'h B03) \ `NERV_CSR_ARR_MRW(hpm_counter, 4, mhpmcounter4, 12'h B04) \ `NERV_CSR_ARR_MRW(hpm_counter, 5, mhpmcounter5, 12'h B05) \ `NERV_CSR_ARR_MRW(hpm_counter, 6, mhpmcounter6, 12'h B06) \ `NERV_CSR_ARR_MRW(hpm_counter, 7, mhpmcounter7, 12'h B07) \ `NERV_CSR_ARR_MRW(hpm_counter, 8, mhpmcounter8, 12'h B08) \ `NERV_CSR_ARR_MRW(hpm_counter, 9, mhpmcounter9, 12'h B09) \ `NERV_CSR_ARR_MRW(hpm_counter, 10, mhpmcounter10, 12'h B0A) \ `NERV_CSR_ARR_MRW(hpm_counter, 11, mhpmcounter11, 12'h B0B) \ `NERV_CSR_ARR_MRW(hpm_counter, 12, mhpmcounter12, 12'h B0C) \ `NERV_CSR_ARR_MRW(hpm_counter, 13, mhpmcounter13, 12'h B0D) \ `NERV_CSR_ARR_MRW(hpm_counter, 14, mhpmcounter14, 12'h B0E) \ `NERV_CSR_ARR_MRW(hpm_counter, 15, mhpmcounter15, 12'h B0F) \ `NERV_CSR_ARR_MRW(hpm_counter, 16, mhpmcounter16, 12'h B10) \ `NERV_CSR_ARR_MRW(hpm_counter, 17, mhpmcounter17, 12'h B11) \ `NERV_CSR_ARR_MRW(hpm_counter, 18, mhpmcounter18, 12'h B12) \ `NERV_CSR_ARR_MRW(hpm_counter, 19, mhpmcounter19, 12'h B13) \ `NERV_CSR_ARR_MRW(hpm_counter, 20, mhpmcounter20, 12'h B14) \ `NERV_CSR_ARR_MRW(hpm_counter, 21, mhpmcounter21, 12'h B15) \ `NERV_CSR_ARR_MRW(hpm_counter, 22, mhpmcounter22, 12'h B16) \ `NERV_CSR_ARR_MRW(hpm_counter, 23, mhpmcounter23, 12'h B17) \ `NERV_CSR_ARR_MRW(hpm_counter, 24, mhpmcounter24, 12'h B18) \ `NERV_CSR_ARR_MRW(hpm_counter, 25, mhpmcounter25, 12'h B19) \ `NERV_CSR_ARR_MRW(hpm_counter, 26, mhpmcounter26, 12'h B1A) \ `NERV_CSR_ARR_MRW(hpm_counter, 27, mhpmcounter27, 12'h B1B) \ `NERV_CSR_ARR_MRW(hpm_counter, 28, mhpmcounter28, 12'h B1C) \ `NERV_CSR_ARR_MRW(hpm_counter, 29, mhpmcounter29, 12'h B1D) \ `NERV_CSR_ARR_MRW(hpm_counter, 30, mhpmcounter30, 12'h B1E) \ `NERV_CSR_ARR_MRW(hpm_counter, 31, mhpmcounter31, 12'h B1F) \ \ `NERV_CSR_ARR_DEF(hpm_counterh, 32) \ `NERV_CSR_ARR_MRW(hpm_counterh, 0, mcycleh, 12'h B80) \ `NERV_CSR_ARR_MRW(hpm_counterh, 2, minstreth, 12'h B82) \ \ `NERV_CSR_ARR_MRW(hpm_counterh, 3, mhpmcounter3h, 12'h B83) \ `NERV_CSR_ARR_MRW(hpm_counterh, 4, mhpmcounter4h, 12'h B84) \ `NERV_CSR_ARR_MRW(hpm_counterh, 5, mhpmcounter5h, 12'h B85) \ `NERV_CSR_ARR_MRW(hpm_counterh, 6, mhpmcounter6h, 12'h B86) \ `NERV_CSR_ARR_MRW(hpm_counterh, 7, mhpmcounter7h, 12'h B87) \ `NERV_CSR_ARR_MRW(hpm_counterh, 8, mhpmcounter8h, 12'h B88) \ `NERV_CSR_ARR_MRW(hpm_counterh, 9, mhpmcounter9h, 12'h B89) \ `NERV_CSR_ARR_MRW(hpm_counterh, 10, mhpmcounter10h, 12'h B8A) \ `NERV_CSR_ARR_MRW(hpm_counterh, 11, mhpmcounter11h, 12'h B8B) \ `NERV_CSR_ARR_MRW(hpm_counterh, 12, mhpmcounter12h, 12'h B8C) \ `NERV_CSR_ARR_MRW(hpm_counterh, 13, mhpmcounter13h, 12'h B8D) \ `NERV_CSR_ARR_MRW(hpm_counterh, 14, mhpmcounter14h, 12'h B8E) \ `NERV_CSR_ARR_MRW(hpm_counterh, 15, mhpmcounter15h, 12'h B8F) \ `NERV_CSR_ARR_MRW(hpm_counterh, 16, mhpmcounter16h, 12'h B90) \ `NERV_CSR_ARR_MRW(hpm_counterh, 17, mhpmcounter17h, 12'h B91) \ `NERV_CSR_ARR_MRW(hpm_counterh, 18, mhpmcounter18h, 12'h B92) \ `NERV_CSR_ARR_MRW(hpm_counterh, 19, mhpmcounter19h, 12'h B93) \ `NERV_CSR_ARR_MRW(hpm_counterh, 20, mhpmcounter20h, 12'h B94) \ `NERV_CSR_ARR_MRW(hpm_counterh, 21, mhpmcounter21h, 12'h B95) \ `NERV_CSR_ARR_MRW(hpm_counterh, 22, mhpmcounter22h, 12'h B96) \ `NERV_CSR_ARR_MRW(hpm_counterh, 23, mhpmcounter23h, 12'h B97) \ `NERV_CSR_ARR_MRW(hpm_counterh, 24, mhpmcounter24h, 12'h B98) \ `NERV_CSR_ARR_MRW(hpm_counterh, 25, mhpmcounter25h, 12'h B99) \ `NERV_CSR_ARR_MRW(hpm_counterh, 26, mhpmcounter26h, 12'h B9A) \ `NERV_CSR_ARR_MRW(hpm_counterh, 27, mhpmcounter27h, 12'h B9B) \ `NERV_CSR_ARR_MRW(hpm_counterh, 28, mhpmcounter28h, 12'h B9C) \ `NERV_CSR_ARR_MRW(hpm_counterh, 29, mhpmcounter29h, 12'h B9D) \ `NERV_CSR_ARR_MRW(hpm_counterh, 30, mhpmcounter30h, 12'h B9E) \ `NERV_CSR_ARR_MRW(hpm_counterh, 31, mhpmcounter31h, 12'h B9F) `define NERV_COUNTER_SETUP_CSRS /* Machine Counter Setup CSRs */ \ /* mcountinhibit is optional */ \ /* `NERV_CSR_REG_MRW(mcountinhibit, 12'h 320, 32'h 0000_0000) */ \ \ /* mhpmevent3..31 select which hardware event the corresponding */ \ /* mhpmcounter should be triggered by and thus count */ \ `NERV_CSR_ARR_DEF(hpm_event, 32) \ `NERV_CSR_ARR_MRW(hpm_event, 3, mhpmevent3, 12'h 323) \ `NERV_CSR_ARR_MRW(hpm_event, 4, mhpmevent4, 12'h 324) \ `NERV_CSR_ARR_MRW(hpm_event, 5, mhpmevent5, 12'h 325) \ `NERV_CSR_ARR_MRW(hpm_event, 6, mhpmevent6, 12'h 326) \ `NERV_CSR_ARR_MRW(hpm_event, 7, mhpmevent7, 12'h 327) \ `NERV_CSR_ARR_MRW(hpm_event, 8, mhpmevent8, 12'h 328) \ `NERV_CSR_ARR_MRW(hpm_event, 9, mhpmevent9, 12'h 329) \ `NERV_CSR_ARR_MRW(hpm_event, 10, mhpmevent10, 12'h 32A) \ `NERV_CSR_ARR_MRW(hpm_event, 11, mhpmevent11, 12'h 32B) \ `NERV_CSR_ARR_MRW(hpm_event, 12, mhpmevent12, 12'h 32C) \ `NERV_CSR_ARR_MRW(hpm_event, 13, mhpmevent13, 12'h 32D) \ `NERV_CSR_ARR_MRW(hpm_event, 14, mhpmevent14, 12'h 32E) \ `NERV_CSR_ARR_MRW(hpm_event, 15, mhpmevent15, 12'h 32F) \ `NERV_CSR_ARR_MRW(hpm_event, 16, mhpmevent16, 12'h 330) \ `NERV_CSR_ARR_MRW(hpm_event, 17, mhpmevent17, 12'h 331) \ `NERV_CSR_ARR_MRW(hpm_event, 18, mhpmevent18, 12'h 332) \ `NERV_CSR_ARR_MRW(hpm_event, 19, mhpmevent19, 12'h 333) \ `NERV_CSR_ARR_MRW(hpm_event, 20, mhpmevent20, 12'h 334) \ `NERV_CSR_ARR_MRW(hpm_event, 21, mhpmevent21, 12'h 335) \ `NERV_CSR_ARR_MRW(hpm_event, 22, mhpmevent22, 12'h 336) \ `NERV_CSR_ARR_MRW(hpm_event, 23, mhpmevent23, 12'h 337) \ `NERV_CSR_ARR_MRW(hpm_event, 24, mhpmevent24, 12'h 338) \ `NERV_CSR_ARR_MRW(hpm_event, 25, mhpmevent25, 12'h 339) \ `NERV_CSR_ARR_MRW(hpm_event, 26, mhpmevent26, 12'h 33A) \ `NERV_CSR_ARR_MRW(hpm_event, 27, mhpmevent27, 12'h 33B) \ `NERV_CSR_ARR_MRW(hpm_event, 28, mhpmevent28, 12'h 33C) \ `NERV_CSR_ARR_MRW(hpm_event, 29, mhpmevent29, 12'h 33D) \ `NERV_CSR_ARR_MRW(hpm_event, 30, mhpmevent30, 12'h 33E) \ `NERV_CSR_ARR_MRW(hpm_event, 31, mhpmevent31, 12'h 33F) `define NERV_CUSTOM_CSRS /* Custom CSR for testing */ \ `NERV_CSR_REG_MRW(custom, 12'h BC0, 32'h 0000_0000) \ `NERV_CSR_VAL_MRO(custom_ro, 12'h FC0, 32'h dead_beef) `define NERV_CSRS \ `NERV_MACHINE_CSRS \ `NERV_TRAP_SETUP_CSRS \ `NERV_TRAP_HANDLING_CSRS \ `NERV_MACHINE_CONFIG_CSRS \ `NERV_PMP_CFG_CSRS \ `NERV_PMP_ADDR_CSRS \ `NERV_COUNTER_CSRS \ `NERV_COUNTER_SETUP_CSRS \ `NERV_CUSTOM_CSRS `endif module nerv #( parameter [31:0] RESET_ADDR = 32'h 0000_0000, parameter integer NUMREGS = 32 ) ( input clock, input reset, input stall, output trap, `ifdef NERV_RVFI output reg rvfi_valid, output reg [63:0] rvfi_order, output reg [31:0] rvfi_insn, output reg rvfi_trap, output reg rvfi_halt, output reg rvfi_intr, output reg [ 1:0] rvfi_mode, output reg [ 1:0] rvfi_ixl, output reg [ 4:0] rvfi_rs1_addr, output reg [ 4:0] rvfi_rs2_addr, output reg [31:0] rvfi_rs1_rdata, output reg [31:0] rvfi_rs2_rdata, output reg [ 4:0] rvfi_rd_addr, output reg [31:0] rvfi_rd_wdata, output reg [31:0] rvfi_pc_rdata, output reg [31:0] rvfi_pc_wdata, `ifdef NERV_CSR `define NERV_CSR_REG_MRW(NAME, ADDR, VALUE) \ output reg [31:0] rvfi_csr_``NAME``_rmask, \ output reg [31:0] rvfi_csr_``NAME``_wmask, \ output reg [31:0] rvfi_csr_``NAME``_rdata, \ output reg [31:0] rvfi_csr_``NAME``_wdata, `define NERV_CSR_VAL_MRW(NAME, ADDR, VALUE) \ `NERV_CSR_REG_MRW(NAME, ADDR, VALUE) `define NERV_CSR_VAL_MRO(NAME, ADDR, VALUE) \ `NERV_CSR_REG_MRW(NAME, ADDR, VALUE) `define NERV_CSR_ARR_DEF(ARRAY, DEPTH) `define NERV_CSR_ARR_MRW(ARRAY, INDEX, NAME, ADDR) \ output reg [31:0] rvfi_csr_``NAME``_rmask, \ output reg [31:0] rvfi_csr_``NAME``_wmask, \ output reg [31:0] rvfi_csr_``NAME``_rdata, \ output reg [31:0] rvfi_csr_``NAME``_wdata, `NERV_CSRS `undef NERV_CSR_REG_MRW `undef NERV_CSR_VAL_MRW `undef NERV_CSR_VAL_MRO `undef NERV_CSR_ARR_DEF `undef NERV_CSR_ARR_MRW `endif output reg [31:0] rvfi_mem_addr, output reg [ 3:0] rvfi_mem_rmask, output reg [ 3:0] rvfi_mem_wmask, output reg [31:0] rvfi_mem_rdata, output reg [31:0] rvfi_mem_wdata, `ifdef NERV_FAULT output reg rvfi_mem_fault, output reg [ 3:0] rvfi_mem_fault_rmask, output reg [ 3:0] rvfi_mem_fault_wmask, `endif `endif // we have 2 external memories // one is instruction memory output [31:0] imem_addr, input [31:0] imem_data, // the other is data memory output dmem_valid, output [31:0] dmem_addr, output [ 3:0] dmem_wstrb, output [31:0] dmem_wdata, input [31:0] dmem_rdata, `ifdef NERV_FAULT input imem_fault, input dmem_fault, `endif // interrupt inputs input [31:0] irq ); `ifndef NERV_FAULT wire imem_fault = 0; wire dmem_fault = 0; `endif reg mem_wr_enable; reg [31:0] mem_wr_addr; reg [31:0] mem_wr_data; reg [3:0] mem_wr_strb; reg mem_rd_enable; reg [31:0] mem_rd_addr; reg [4:0] mem_rd_reg; reg [4:0] mem_rd_func; reg mem_rd_enable_q; reg [4:0] mem_rd_reg_q; reg [4:0] mem_rd_func_q; reg mem_wr_enable_q; // delayed copies of mem_rd (and mem_wr for NERV_FAULTS) always @(posedge clock) begin if (!stall) begin mem_rd_enable_q <= mem_rd_enable; mem_rd_reg_q <= mem_rd_reg; mem_rd_func_q <= mem_rd_func; mem_wr_enable_q <= mem_wr_enable; end if (reset) begin mem_rd_enable_q <= 0; end end // memory signals assign dmem_valid = mem_wr_enable || mem_rd_enable; assign dmem_addr = mem_wr_enable ? mem_wr_addr : mem_rd_enable ? mem_rd_addr : 32'h x; assign dmem_wstrb = mem_wr_enable ? mem_wr_strb : mem_rd_enable ? 4'h 0 : 4'h x; assign dmem_wdata = mem_wr_enable ? mem_wr_data : 32'h x; // registers, instruction reg, program counter, next pc reg [31:0] regfile [0:NUMREGS-1]; wire [31:0] insn; reg [31:0] npc; reg [31:0] pc; reg [31:0] imem_addr_q; always @(posedge clock) begin imem_addr_q <= imem_addr; end // instruction memory pointer assign imem_addr = npc; assign insn = imem_data; // components of the instruction wire [6:0] insn_funct7; wire [4:0] insn_rs2; wire [4:0] insn_rs1; wire [2:0] insn_funct3; wire [4:0] insn_rd; wire [6:0] insn_opcode; // rs1 and rs2 are source for the instruction wire [31:0] rs1_value = !insn_rs1 ? 0 : regfile[insn_rs1]; wire [31:0] rs2_value = !insn_rs2 ? 0 : regfile[insn_rs2]; // split R-type instruction - see section 2.2 of RiscV spec assign {insn_funct7, insn_rs2, insn_rs1, insn_funct3, insn_rd, insn_opcode} = insn; // setup for I, S, B & J type instructions // I - short immediates and loads wire [11:0] imm_i; assign imm_i = insn[31:20]; // S - stores wire [11:0] imm_s; assign imm_s[11:5] = insn_funct7, imm_s[4:0] = insn_rd; // B - conditionals wire [12:0] imm_b; assign {imm_b[12], imm_b[10:5]} = insn_funct7, {imm_b[4:1], imm_b[11]} = insn_rd, imm_b[0] = 1'b0; // J - unconditional jumps wire [20:0] imm_j; assign {imm_j[20], imm_j[10:1], imm_j[11], imm_j[19:12], imm_j[0]} = {insn[31:12], 1'b0}; wire [31:0] imm_i_sext = $signed(imm_i); wire [31:0] imm_s_sext = $signed(imm_s); wire [31:0] imm_b_sext = $signed(imm_b); wire [31:0] imm_j_sext = $signed(imm_j); // opcodes - see section 19 of RiscV spec localparam OPCODE_LOAD = 7'b 00_000_11; localparam OPCODE_STORE = 7'b 01_000_11; localparam OPCODE_MADD = 7'b 10_000_11; localparam OPCODE_BRANCH = 7'b 11_000_11; localparam OPCODE_LOAD_FP = 7'b 00_001_11; localparam OPCODE_STORE_FP = 7'b 01_001_11; localparam OPCODE_MSUB = 7'b 10_001_11; localparam OPCODE_JALR = 7'b 11_001_11; localparam OPCODE_CUSTOM_0 = 7'b 00_010_11; localparam OPCODE_CUSTOM_1 = 7'b 01_010_11; localparam OPCODE_NMSUB = 7'b 10_010_11; localparam OPCODE_RESERVED_0 = 7'b 11_010_11; localparam OPCODE_MISC_MEM = 7'b 00_011_11; localparam OPCODE_AMO = 7'b 01_011_11; localparam OPCODE_NMADD = 7'b 10_011_11; localparam OPCODE_JAL = 7'b 11_011_11; localparam OPCODE_OP_IMM = 7'b 00_100_11; localparam OPCODE_OP = 7'b 01_100_11; localparam OPCODE_OP_FP = 7'b 10_100_11; localparam OPCODE_SYSTEM = 7'b 11_100_11; localparam OPCODE_AUIPC = 7'b 00_101_11; localparam OPCODE_LUI = 7'b 01_101_11; localparam OPCODE_RESERVED_1 = 7'b 10_101_11; localparam OPCODE_RESERVED_2 = 7'b 11_101_11; localparam OPCODE_OP_IMM_32 = 7'b 00_110_11; localparam OPCODE_OP_32 = 7'b 01_110_11; localparam OPCODE_CUSTOM_2 = 7'b 10_110_11; localparam OPCODE_CUSTOM_3 = 7'b 11_110_11; localparam MCAUSE_MACHINE_SOFTWARE_INTERRUPT = 32'h80000003; localparam MCAUSE_MACHINE_TIMER_INTERRUPT = 32'h80000007; localparam MCAUSE_MACHINE_EXTERNAL_INTERRUPT = 32'h8000000b; localparam MCAUSE_INSN_ADDRESS_MISALIGNED = 32'h00000000; localparam MCAUSE_INSN_ACCESS_FAULT = 32'h00000001; localparam MCAUSE_INVALID_INSTRUCTION = 32'h00000002; localparam MCAUSE_BREAKPOINT = 32'h00000003; localparam MCAUSE_LOAD_ADDRESS_MISALIGNED = 32'h00000004; localparam MCAUSE_LOAD_ACCESS_FAULT = 32'h00000005; localparam MCAUSE_STORE_ADDRESS_MISALIGNED = 32'h00000006; localparam MCAUSE_STORE_ACCESS_FAULT = 32'h00000007; localparam MCAUSE_ECALL_M_MODE = 32'h0000000b; localparam IRQ_MASK = 32'hFFFF0888; // next write, next destination (rd) value & register reg next_wr; reg [31:0] next_rd; reg [4:0] wr_rd; // illegal instruction registers reg illinsn; reg reset_q; wire running = !stall && !reset && !reset_q; // action to perform this cycle reg cycle_intr; // cycle to start fetching new PC for interrupts reg cycle_insn; // first non-trapping cycle of an instruction reg cycle_trap; // trap in the first cycle of an instruction reg cycle_late_wr; // 2nd cycle for mem_rd_enable instructions `ifdef NERV_FAULT reg cycle_dmem_fault; `endif assign trap = cycle_trap; `ifdef NERV_CSR /********************* * CSR DEFINITIONS * *********************/ reg csr_ack; reg [31:0] csr_rdval; reg [31:0] csr_next; wire imem_valid = !mem_rd_enable_q && !mem_wr_enable_q && !imem_fault; wire [ 1:0] csr_mode = (running && imem_valid && !irq_num && insn_opcode == OPCODE_SYSTEM) ? insn_funct3[1:0] : 2'b 00; // 00=None, 01=RW, 10=RS, 11=RC wire [11:0] csr_addr = imm_i; wire [31:0] csr_rsval = insn_funct3[2] ? insn_rs1 : rs1_value; wire csr_ro = csr_mode && (csr_mode != 2'b01 && !insn_rs1); integer hpm_idx, hpm_increment, hpm_event; `define NERV_CSR_REG_MRW(NAME, ADDR, VALUE) \ wire csr_``NAME``_sel = csr_mode && csr_addr == ADDR; \ reg [31:0] csr_``NAME``_value; \ reg [31:0] csr_``NAME``_wdata; \ reg [31:0] csr_``NAME``_next; \ always @(posedge clock) begin \ csr_``NAME``_value <= csr_``NAME``_next; \ if (reset || reset_q) \ csr_``NAME``_value <= VALUE; \ end `define NERV_CSR_VAL_MRW(NAME, ADDR, VALUE) \ wire csr_``NAME``_sel = csr_mode && csr_addr == ADDR; \ wire [31:0] csr_``NAME``_wdata = csr_``NAME``_sel ? csr_next : csr_``NAME``_value; \ localparam [31:0] csr_``NAME``_value = VALUE; `define NERV_CSR_VAL_MRO(NAME, ADDR, VALUE) \ wire csr_``NAME``_sel = csr_ro && csr_addr == ADDR; \ localparam [31:0] csr_``NAME``_value = VALUE; `define NERV_CSR_ARR_DEF(ARRAY, DEPTH) \ integer ARRAY``_idx; \ wire [DEPTH-1:0] csr_``ARRAY``_sel; \ reg [(DEPTH*32)-1:0] csr_``ARRAY``_value; \ reg [(DEPTH*32)-1:0] csr_``ARRAY``_wdata; \ reg [(DEPTH*32)-1:0] csr_``ARRAY``_next; \ always @(posedge clock) begin \ csr_``ARRAY``_value <= csr_``ARRAY``_next; \ if (reset || reset_q) \ csr_``ARRAY``_value <= 'b0; \ end `define NERV_CSR_ARR_MRW(ARRAY, INDEX, NAME, ADDR) \ wire csr_``NAME``_sel = csr_mode && csr_addr == ADDR; \ wire [31:0] csr_``NAME``_value = csr_``ARRAY``_value[(INDEX)*32 +: 32]; \ wire [31:0] csr_``NAME``_wdata = csr_``ARRAY``_wdata[(INDEX)*32 +: 32]; \ wire [31:0] csr_``NAME``_next = csr_``ARRAY``_next[(INDEX)*32 +: 32]; \ assign csr_``ARRAY``_sel[INDEX] = csr_``NAME``_sel; // dummy out missing select lines assign csr_hpm_event_sel[2:0] = 0; assign csr_hpm_counter_sel[1] = 0; assign csr_hpm_counterh_sel[1] = 0; `NERV_CSRS `undef NERV_CSR_REG_MRW `undef NERV_CSR_VAL_MRW `undef NERV_CSR_VAL_MRO `undef NERV_CSR_ARR_DEF `undef NERV_CSR_ARR_MRW `endif // NERV_CSR wire [31:0] irq_en; reg [4:0] irq_num; assign irq_en = irq & csr_mie_value; // resolve interrupt priority always @* begin if (irq_en[31]) irq_num = 5'd31; else if (irq_en[30]) irq_num = 5'd30; else if (irq_en[29]) irq_num = 5'd29; else if (irq_en[28]) irq_num = 5'd28; else if (irq_en[27]) irq_num = 5'd27; else if (irq_en[26]) irq_num = 5'd26; else if (irq_en[25]) irq_num = 5'd25; else if (irq_en[24]) irq_num = 5'd24; else if (irq_en[23]) irq_num = 5'd23; else if (irq_en[22]) irq_num = 5'd22; else if (irq_en[21]) irq_num = 5'd21; else if (irq_en[20]) irq_num = 5'd20; else if (irq_en[19]) irq_num = 5'd19; else if (irq_en[18]) irq_num = 5'd18; else if (irq_en[17]) irq_num = 5'd17; else if (irq_en[16]) irq_num = 5'd16; else if (irq_en[11]) irq_num = 5'd11; else if (irq_en[7]) irq_num = 5'd7; else if (irq_en[3]) irq_num = 5'd3; else irq_num = 5'd0; end always @* begin // advance pc npc = pc + 4; // defaults for read, write next_wr = 0; next_rd = 0; cycle_intr = 0; cycle_trap = 0; cycle_insn = 0; cycle_late_wr = 0; `ifdef NERV_FAULT cycle_dmem_fault = 0; `endif wr_rd = insn_rd; illinsn = 0; mem_wr_enable = 0; mem_wr_addr = 32'hx; mem_wr_data = 32'hx; mem_wr_strb = 4'hx; mem_rd_enable = 0; mem_rd_addr = 32'hx; mem_rd_reg = 5'hx; mem_rd_func = 5'hx; `ifdef NERV_CSR csr_ack = 0; csr_rdval = 'hx; unique case (1'b1) `define NERV_CSR_REG_MRW(NAME, ADDR, VALUE) \ csr_mode && csr_``NAME``_sel: begin \ csr_ack = 1; \ csr_rdval = csr_``NAME``_value; \ end `define NERV_CSR_VAL_MRW(NAME, ADDR, VALUE) \ csr_mode && csr_``NAME``_sel: begin \ csr_ack = 1; \ csr_rdval = csr_``NAME``_value; \ end `define NERV_CSR_VAL_MRO(NAME, ADDR, VALUE) \ csr_ro && csr_``NAME``_sel: begin \ csr_ack = 1; \ csr_rdval = csr_``NAME``_value; \ end `define NERV_CSR_ARR_DEF(ARRAY, DEPTH) `define NERV_CSR_ARR_MRW(ARRAY, INDEX, NAME, ADDR) \ `NERV_CSR_REG_MRW(NAME, ADDR, 32'h 0000_0000) `NERV_CSRS `undef NERV_CSR_REG_MRW `undef NERV_CSR_VAL_MRW `undef NERV_CSR_VAL_MRO `undef NERV_CSR_ARR_DEF `undef NERV_CSR_ARR_MRW default: /* nothing */; endcase csr_next = csr_rdval; case (csr_mode) 2'b 01 /* RW */: csr_next = csr_rsval; 2'b 10 /* RS */: csr_next = csr_next | csr_rsval; 2'b 11 /* RC */: csr_next = csr_next & ~csr_rsval; endcase `define NERV_CSR_REG_MRW(NAME, ADDR, VALUE) \ csr_``NAME``_wdata = csr_``NAME``_sel ? csr_next : csr_``NAME``_value; \ csr_``NAME``_next = csr_``NAME``_wdata; `define NERV_CSR_VAL_MRW(NAME, ADDR, VALUE) `define NERV_CSR_VAL_MRO(NAME, ADDR, VALUE) `define NERV_CSR_ARR_DEF(ARRAY, DEPTH) \ for (ARRAY``_idx=0; ARRAY``_idx < DEPTH; ARRAY``_idx=ARRAY``_idx+1) begin \ csr_``ARRAY``_wdata[(ARRAY``_idx)*32 +: 32] = \ csr_``ARRAY``_sel[ARRAY``_idx] \ ? csr_next \ : csr_``ARRAY``_value[(ARRAY``_idx)*32 +: 32]; \ end \ csr_``ARRAY``_next = csr_``ARRAY``_wdata; `define NERV_CSR_ARR_MRW(ARRAY, INDEX, NAME, ADDR) `NERV_CSRS `undef NERV_CSR_REG_MRW `undef NERV_CSR_VAL_MRW `undef NERV_CSR_VAL_MRO `undef NERV_CSR_ARR_DEF `undef NERV_CSR_ARR_MRW for (hpm_idx=0; hpm_idx < 32; hpm_idx=hpm_idx+1) begin case (hpm_idx) 0 /* mcycle */ : hpm_event = 32'h 1; 2 /* minstret */ : hpm_event = 32'h 2; default: hpm_event = csr_hpm_event_next[(hpm_idx)*32 +: 32]; endcase case (hpm_event) 32'h 1 /* cycle counter */: hpm_increment = 1; 32'h 2 /* instruction counter */: hpm_increment = running ? 1 : 0; 32'h 3 /* memory writes */: hpm_increment = mem_wr_enable_q ? 1 : 0; default: begin csr_hpm_event_next[(hpm_idx)*32 +: 32] = 0; hpm_increment = 0; end endcase {csr_hpm_counterh_next[(hpm_idx)*32 +: 32], csr_hpm_counter_next[(hpm_idx)*32 +: 32]} = {csr_hpm_counterh_next[(hpm_idx)*32 +: 32], csr_hpm_counter_next[(hpm_idx)*32 +: 32]} + hpm_increment; end // mstatus & mstatush - Machine Status csr_mstatus_next[31] = 'b0; // SD is always 0 if FS, VS, and XS are not enabled csr_mstatus_next[30:23] = 'b0; // WPRI csr_mstatus_next[22] = 'b0; // TSR = 0 if no S csr_mstatus_next[21] = 'b0; // TW = 0 if no U or S csr_mstatus_next[20] = 'b0; // TVM = 0 if no S csr_mstatus_next[19] = 'b0; // MXR = 0 if no S csr_mstatus_next[18] = 'b0; // SUM = 0 if no S csr_mstatus_next[17] = 'b0; // MPRV = 0 if no U csr_mstatus_next[16:15] = 'b0; // XS = 0 if no user extensions csr_mstatus_next[14:13] = 'b0; // FS = 0 if no S and no floating point extension csr_mstatus_next[12:11] = 2'b11; // MPP = b11 if no U csr_mstatus_next[10:9] = 'b0; // VS = 0 if no vector extension csr_mstatus_next[8] = 'b0; // SPP = 0 if no S //csr_mstatus_next[7] = ; // MPIE controlled by trap handling csr_mstatus_next[6] = 'b0; // UBE = 0 if no U csr_mstatus_next[5] = 'b0; // SPIE = 0 if no S csr_mstatus_next[4] = 'b0; // WPRI //csr_mstatus_next[3] = ; // MIE controlled by code csr_mstatus_next[2] = 'b0; // WPRI csr_mstatus_next[1] = 'b0; // SIE = 0 if no S csr_mstatus_next[0] = 'b0; // WPRI csr_mstatush_next[31:6] = 'b0; // WPRI csr_mstatush_next[5] = 1'b0; // MBE = 1 if big endian, 0 if little endian csr_mstatush_next[4] = 'b0; // SBE = 0 if no S csr_mstatush_next[3:0] = 'b0; // WPRI // misa - Machine ISA // read-only 0 for unimplemented register csr_misa_next[31:20] = 'b0; // MXL = 1 for XLEN=32 csr_misa_next[29:26] = 'b0; // 0 csr_misa_next[25:0] = 'b0; // Extensions enabled // mie - Machine Interrupt-Enable // A bit in mie must be writable if the corresponding interrupt can ever become pending. // Bits of mie that are not writable must be read-only 0. //csr_mie_next[31:16] = 'b0; // bits 16 and above for custom/platform interrupts csr_mie_next[15:12] = 'b0; // 0 //csr_mie_next[11] = 'b0; // MEIE - Machine-level External Interrupt Enable csr_mie_next[10] = 'b0; // 0 csr_mie_next[9] = 'b0; // SEIE = 0 if no S csr_mie_next[8] = 'b0; // 0 //csr_mie_next[7] = 'b0; // MTIE - Machine Timer Interrupt Enable csr_mie_next[6] = 'b0; // 0 csr_mie_next[5] = 'b0; // STIE = 0 if no S csr_mie_next[4] = 'b0; // 0 //csr_mie_next[3] = 'b0; // MSIE - Machine-level Software Interrupt Enable csr_mie_next[2] = 'b0; // 0 csr_mie_next[1] = 'b0; // SSIE = 0 if no S csr_mie_next[0] = 'b0; // 0 // mip - Machine Interrupt-Pending //csr_mip_next[31:16] = 'b0; // bits 16 and above for custom/platform interrupts //csr_mip_next[15:12] = 'b0; // 0 //csr_mip_next[11] = 'b0; // MEIE - Machine-level External Interrupt Pending //csr_mip_next[10] = 'b0; // 0 //csr_mip_next[9] = 'b0; // SEIE = 0 if no S //csr_mip_next[8] = 'b0; // 0 //csr_mip_next[7] = 'b0; // MTIE - Machine Timer Interrupt Pending //csr_mip_next[6] = 'b0; // 0 //csr_mip_next[5] = 'b0; // STIE = 0 if no S //csr_mip_next[4] = 'b0; // 0 //csr_mip_next[3] = 'b0; // MSIE - Machine-level Software Interrupt Pending //csr_mip_next[2] = 'b0; // 0 //csr_mip_next[1] = 'b0; // SSIE = 0 if no S //csr_mip_next[0] = 'b0; // 0 csr_mip_next = irq & IRQ_MASK; // mtvec - Machine Trap-Vector Base-Address csr_mtvec_next[1] = 'b0; // MODE - keep high bit always 0 // mcause - keep these bits at 0 csr_mcause_next[30:5] ='b0; // mepc - keep alignment csr_mepc_next[1:0] = 'b0; `endif // NERV_CSR // act on opcodes case (insn_opcode) // Load Upper Immediate OPCODE_LUI: begin next_wr = 1; next_rd = insn[31:12] << 12; end // Add Upper Immediate to Program Counter OPCODE_AUIPC: begin next_wr = 1; next_rd = (insn[31:12] << 12) + pc; end // Jump And Link (unconditional jump) OPCODE_JAL: begin next_wr = 1; next_rd = npc; npc = pc + imm_j_sext; if (npc & 32'b 11) begin illinsn = 1; npc = npc & ~32'b 11; end end // Jump And Link Register (indirect jump) OPCODE_JALR: begin case (insn_funct3) 3'b 000 /* JALR */: begin next_wr = 1; next_rd = npc; npc = (rs1_value + imm_i_sext) & ~32'b 1; end default: illinsn = 1; endcase if (npc & 32'b 11) begin illinsn = 1; npc = npc & ~32'b 11; end end // branch instructions: Branch If Equal, Branch Not Equal, Branch Less Than, Branch Greater Than, Branch Less Than Unsigned, Branch Greater Than Unsigned OPCODE_BRANCH: begin case (insn_funct3) 3'b 000 /* BEQ */: begin if (rs1_value == rs2_value) npc = pc + imm_b_sext; end 3'b 001 /* BNE */: begin if (rs1_value != rs2_value) npc = pc + imm_b_sext; end 3'b 100 /* BLT */: begin if ($signed(rs1_value) < $signed(rs2_value)) npc = pc + imm_b_sext; end 3'b 101 /* BGE */: begin if ($signed(rs1_value) >= $signed(rs2_value)) npc = pc + imm_b_sext; end 3'b 110 /* BLTU */: begin if (rs1_value < rs2_value) npc = pc + imm_b_sext; end 3'b 111 /* BGEU */: begin if (rs1_value >= rs2_value) npc = pc + imm_b_sext; end default: illinsn = 1; endcase if (npc & 32'b 11) begin illinsn = 1; npc = npc & ~32'b 11; end end // load from memory into rd: Load Byte, Load Halfword, Load Word, Load Byte Unsigned, Load Halfword Unsigned OPCODE_LOAD: begin mem_rd_addr = rs1_value + imm_i_sext; casez ({insn_funct3, mem_rd_addr[1:0]}) 5'b 000_zz /* LB */, 5'b 001_z0 /* LH */, 5'b 010_00 /* LW */, 5'b 100_zz /* LBU */, 5'b 101_z0 /* LHU */: begin mem_rd_enable = 1; mem_rd_reg = insn_rd; mem_rd_func = {mem_rd_addr[1:0], insn_funct3}; mem_rd_addr = {mem_rd_addr[31:2], 2'b 00}; end default: illinsn = 1; endcase end // store to memory instructions: Store Byte, Store Halfword, Store Word OPCODE_STORE: begin mem_wr_addr = rs1_value + imm_s_sext; casez ({insn_funct3, mem_wr_addr[1:0]}) 5'b 000_zz /* SB */, 5'b 001_z0 /* SH */, 5'b 010_00 /* SW */: begin mem_wr_enable = 1; mem_wr_data = rs2_value; mem_wr_strb = 4'b 1111; case (insn_funct3) 3'b 000 /* SB */: begin mem_wr_strb = 4'b 0001; end 3'b 001 /* SH */: begin mem_wr_strb = 4'b 0011; end 3'b 010 /* SW */: begin mem_wr_strb = 4'b 1111; end endcase mem_wr_data = mem_wr_data << (8*mem_wr_addr[1:0]); mem_wr_strb = mem_wr_strb << mem_wr_addr[1:0]; mem_wr_addr = {mem_wr_addr[31:2], 2'b 00}; end default: illinsn = 1; endcase end // immediate ALU instructions: Add Immediate, Set Less Than Immediate, Set Less Than Immediate Unsigned, XOR Immediate, // OR Immediate, And Immediate, Shift Left Logical Immediate, Shift Right Logical Immediate, Shift Right Arithmetic Immediate OPCODE_OP_IMM: begin casez ({insn_funct7, insn_funct3}) 10'b zzzzzzz_000 /* ADDI */: begin next_wr = 1; next_rd = rs1_value + imm_i_sext; end 10'b zzzzzzz_010 /* SLTI */: begin next_wr = 1; next_rd = $signed(rs1_value) < $signed(imm_i_sext); end 10'b zzzzzzz_011 /* SLTIU */: begin next_wr = 1; next_rd = rs1_value < imm_i_sext; end 10'b zzzzzzz_100 /* XORI */: begin next_wr = 1; next_rd = rs1_value ^ imm_i_sext; end 10'b zzzzzzz_110 /* ORI */: begin next_wr = 1; next_rd = rs1_value | imm_i_sext; end 10'b zzzzzzz_111 /* ANDI */: begin next_wr = 1; next_rd = rs1_value & imm_i_sext; end 10'b 0000000_001 /* SLLI */: begin next_wr = 1; next_rd = rs1_value << insn[24:20]; end 10'b 0000000_101 /* SRLI */: begin next_wr = 1; next_rd = rs1_value >> insn[24:20]; end 10'b 0100000_101 /* SRAI */: begin next_wr = 1; next_rd = $signed(rs1_value) >>> insn[24:20]; end default: illinsn = 1; endcase end OPCODE_OP: begin // ALU instructions: Add, Subtract, Shift Left Logical, Set Left Than, Set Less Than Unsigned, XOR, Shift Right Logical, // Shift Right Arithmetic, OR, AND case ({insn_funct7, insn_funct3}) 10'b 0000000_000 /* ADD */: begin next_wr = 1; next_rd = rs1_value + rs2_value; end 10'b 0100000_000 /* SUB */: begin next_wr = 1; next_rd = rs1_value - rs2_value; end 10'b 0000000_001 /* SLL */: begin next_wr = 1; next_rd = rs1_value << rs2_value[4:0]; end 10'b 0000000_010 /* SLT */: begin next_wr = 1; next_rd = $signed(rs1_value) < $signed(rs2_value); end 10'b 0000000_011 /* SLTU */: begin next_wr = 1; next_rd = rs1_value < rs2_value; end 10'b 0000000_100 /* XOR */: begin next_wr = 1; next_rd = rs1_value ^ rs2_value; end 10'b 0000000_101 /* SRL */: begin next_wr = 1; next_rd = rs1_value >> rs2_value[4:0]; end 10'b 0100000_101 /* SRA */: begin next_wr = 1; next_rd = $signed(rs1_value) >>> rs2_value[4:0]; end 10'b 0000000_110 /* OR */: begin next_wr = 1; next_rd = rs1_value | rs2_value; end 10'b 0000000_111 /* AND */: begin next_wr = 1; next_rd = rs1_value & rs2_value; end default: illinsn = 1; endcase end `ifdef NERV_CSR OPCODE_SYSTEM: begin case (insn_funct3) 3'b 000 : begin case ({insn_funct7, insn_rs2}) 12'b 0000000_00000 /* ECALL */: begin csr_mepc_next = { pc[31:2], 2'b00 }; npc = csr_mtvec_value & ~3; csr_mcause_next = MCAUSE_ECALL_M_MODE; csr_mstatus_next[7] = csr_mstatus_value[3]; // save MIE to MPIE csr_mstatus_next[3] = 0; // MIE to 0 end 12'b 0000000_00001 /* EBREAK */: begin csr_mepc_next = { pc[31:2], 2'b00 }; npc = csr_mtvec_value & ~3; csr_mcause_next = MCAUSE_BREAKPOINT; csr_mstatus_next[7] = csr_mstatus_value[3]; // save MIE to MPIE csr_mstatus_next[3] = 0; // MIE to 0 end 12'b 0011000_00010 /* MRET */: begin npc = csr_mepc_value; csr_mcause_next = 'b0; csr_mstatus_next[3] = csr_mstatus_value[7]; // restore MIE from MPIE end 12'b 0001000_00101 /* WFI */: begin // implemented as NOP end default: illinsn = 1; endcase end default : begin if (csr_ack) begin next_wr = 1; next_rd = csr_rdval; end else illinsn = 1; end endcase end `endif default: illinsn = 1; endcase if (reset || reset_q) begin // reset has the highest priority npc = RESET_ADDR; csr_mstatus_next[3] = 0; // MIE end else if (stall) begin // if this is a stall cycle, don't perform any action npc = pc; `ifdef NERV_FAULT end else if (mem_rd_enable_q || mem_wr_enable_q) begin npc = pc; if (dmem_fault) begin cycle_dmem_fault = 1; csr_mepc_next[31:2] = pc[31:2]; npc = csr_mtvec_value & ~3; csr_mcause_next = mem_wr_enable_q ? MCAUSE_STORE_ACCESS_FAULT : MCAUSE_LOAD_ACCESS_FAULT; csr_mcause_wdata = csr_mcause_next; csr_mstatus_next[7] = csr_mstatus_value[3]; // save MIE to MPIE csr_mstatus_next[3] = 0; // MIE to 0 end else begin cycle_late_wr = 1; if (mem_rd_enable_q) begin wr_rd = mem_rd_reg_q; next_rd = mem_rdata; end end `else end else if (mem_rd_enable_q) begin // if last cycle was a memory read, then this cycle is the 2nd part of it and imem_data will not be a valid instruction npc = pc; cycle_late_wr = 1; wr_rd = mem_rd_reg_q; next_rd = mem_rdata; `endif end else if (irq_num!=0) begin // if there's a pending IRQ, take it csr_mepc_next = { pc[31:2], 2'b00 }; csr_mcause_next = 1 << 31 | irq_num; if (csr_mtvec_value & 1) npc = (csr_mtvec_value & ~3) + (irq_num << 2); else npc = csr_mtvec_value & ~3; csr_mstatus_next[7] = 1; // MPIE to 1 csr_mstatus_next[3] = 0; // MIE to 0 cycle_intr = 1; end else if (imem_fault || illinsn) begin // instruction fetch memory fault cycle_trap = 1; csr_mepc_next[31:2] = pc[31:2]; npc = csr_mtvec_value & ~3; csr_mcause_next = imem_fault ? MCAUSE_INSN_ACCESS_FAULT : MCAUSE_INVALID_INSTRUCTION; csr_mcause_wdata = csr_mcause_next; csr_mstatus_next[7] = csr_mstatus_value[3]; // save MIE to MPIE csr_mstatus_next[3] = 0; // MIE to 0 end else begin // the instruction is valid and nothing else has priority cycle_insn = 1; end if (!cycle_insn) begin next_wr = cycle_late_wr && mem_rd_enable_q; mem_rd_enable = 0; mem_wr_enable = 0; end end reg [31:0] mem_rdata; `ifdef NERV_RVFI reg next_rvfi_intr; reg rvfi_trap_q; `ifdef NERV_FAULT wire next_rvfi_valid = (cycle_insn && !mem_rd_enable && !mem_wr_enable) || cycle_trap || cycle_dmem_fault || cycle_late_wr; `else wire next_rvfi_valid = (cycle_insn && !mem_rd_enable) || cycle_trap || cycle_late_wr; `endif `endif // mem read functions: Lower and Upper Bytes, signed and unsigned always @* begin mem_rdata = dmem_rdata >> (8*mem_rd_func_q[4:3]); case (mem_rd_func_q[2:0]) 3'b 000 /* LB */: begin mem_rdata = $signed(mem_rdata[7:0]); end 3'b 001 /* LH */: begin mem_rdata = $signed(mem_rdata[15:0]); end 3'b 100 /* LBU */: begin mem_rdata = mem_rdata[7:0]; end 3'b 101 /* LHU */: begin mem_rdata = mem_rdata[15:0]; end endcase end // every cycle always @(posedge clock) begin reset_q <= reset || (reset_q && stall); // update pc pc <= npc; if (next_wr) regfile[wr_rd] <= next_rd; `ifdef NERV_RVFI rvfi_valid <= next_rvfi_valid; if (cycle_intr) next_rvfi_intr <= 1; if (cycle_insn || cycle_late_wr || cycle_trap) begin rvfi_rd_addr <= next_wr ? wr_rd : 0; rvfi_rd_wdata <= next_wr && wr_rd ? next_rd : 0; rvfi_mem_rdata <= dmem_rdata; end if (cycle_insn || cycle_trap) begin next_rvfi_intr <= cycle_trap; rvfi_order <= rvfi_order + 1; rvfi_insn <= imem_fault ? 32'b0 : insn; rvfi_trap <= cycle_trap; rvfi_halt <= 0; rvfi_intr <= next_rvfi_intr; rvfi_mode <= 3; rvfi_ixl <= 1; rvfi_rs1_addr <= insn_rs1; rvfi_rs2_addr <= insn_rs2; rvfi_rs1_rdata <= rs1_value; rvfi_rs2_rdata <= rs2_value; rvfi_pc_rdata <= pc; rvfi_pc_wdata <= npc; if (dmem_valid) begin rvfi_mem_addr <= dmem_addr; case ({mem_rd_enable, insn_funct3}) 4'b 1_000 /* LB */: begin rvfi_mem_rmask <= 4'b 0001 << mem_rd_func[4:3]; end 4'b 1_001 /* LH */: begin rvfi_mem_rmask <= 4'b 0011 << mem_rd_func[4:3]; end 4'b 1_010 /* LW */: begin rvfi_mem_rmask <= 4'b 1111 << mem_rd_func[4:3]; end 4'b 1_100 /* LBU */: begin rvfi_mem_rmask <= 4'b 0001 << mem_rd_func[4:3]; end 4'b 1_101 /* LHU */: begin rvfi_mem_rmask <= 4'b 0011 << mem_rd_func[4:3]; end default: rvfi_mem_rmask <= 0; endcase rvfi_mem_wmask <= dmem_wstrb; rvfi_mem_wdata <= dmem_wdata; end else begin rvfi_mem_addr <= 0; rvfi_mem_rmask <= 0; rvfi_mem_wmask <= 0; rvfi_mem_wdata <= 0; end `ifdef NERV_FAULT rvfi_mem_fault <= imem_fault; rvfi_mem_fault_rmask <= 0; rvfi_mem_fault_wmask <= 0; `endif end `ifdef NERV_FAULT if (cycle_dmem_fault) begin next_rvfi_intr <= 1; rvfi_trap <= 1; rvfi_mem_fault <= 1; rvfi_rd_addr <= 0; rvfi_rd_wdata <= 0; rvfi_mem_fault_rmask <= rvfi_mem_rmask; rvfi_mem_fault_wmask <= rvfi_mem_wmask; rvfi_mem_rmask <= 0; rvfi_mem_wmask <= 0; end `endif if (next_rvfi_valid) begin `ifdef NERV_CSR `define NERV_CSR_REG_MRW(NAME, ADDR, VALUE) \ rvfi_csr_``NAME``_rmask <= 32'h ffff_ffff; \ rvfi_csr_``NAME``_wmask <= 32'h ffff_ffff; \ rvfi_csr_``NAME``_rdata <= csr_``NAME``_value; \ rvfi_csr_``NAME``_wdata <= csr_``NAME``_wdata; `define NERV_CSR_VAL_MRW(NAME, ADDR, VALUE) \ `NERV_CSR_REG_MRW(NAME, ADDR, VALUE) `define NERV_CSR_VAL_MRO(NAME, ADDR, VALUE) \ rvfi_csr_``NAME``_rmask <= 32'h ffff_ffff; \ rvfi_csr_``NAME``_wmask <= 32'h ffff_ffff; \ rvfi_csr_``NAME``_rdata <= csr_``NAME``_value; \ rvfi_csr_``NAME``_wdata <= csr_``NAME``_value; `define NERV_CSR_ARR_DEF(ARRAY, DEPTH) `define NERV_CSR_ARR_MRW(ARRAY, INDEX, NAME, ADDR) \ `NERV_CSR_REG_MRW(NAME, ADDR, 32'h 0000_0000) `NERV_CSRS `undef NERV_CSR_REG_MRW `undef NERV_CSR_VAL_MRW `undef NERV_CSR_VAL_MRO `undef NERV_CSR_ARR_DEF `undef NERV_CSR_ARR_MRW `endif end `endif // reset if (reset || reset_q) begin pc <= RESET_ADDR - (reset ? 4 : 0); `ifdef NERV_RVFI next_rvfi_intr <= 0; rvfi_valid <= 0; rvfi_order <= 0; rvfi_trap <= 0; `endif end end `ifdef NERV_DBGREGS wire [31:0] dbg_reg_x0 = 0; wire [31:0] dbg_reg_x1 = regfile[1]; wire [31:0] dbg_reg_x2 = regfile[2]; wire [31:0] dbg_reg_x3 = regfile[3]; wire [31:0] dbg_reg_x4 = regfile[4]; wire [31:0] dbg_reg_x5 = regfile[5]; wire [31:0] dbg_reg_x6 = regfile[6]; wire [31:0] dbg_reg_x7 = regfile[7]; wire [31:0] dbg_reg_x8 = regfile[8]; wire [31:0] dbg_reg_x9 = regfile[9]; wire [31:0] dbg_reg_x10 = regfile[10]; wire [31:0] dbg_reg_x11 = regfile[11]; wire [31:0] dbg_reg_x12 = regfile[12]; wire [31:0] dbg_reg_x13 = regfile[13]; wire [31:0] dbg_reg_x14 = regfile[14]; wire [31:0] dbg_reg_x15 = regfile[15]; wire [31:0] dbg_reg_x16 = regfile[16]; wire [31:0] dbg_reg_x17 = regfile[17]; wire [31:0] dbg_reg_x18 = regfile[18]; wire [31:0] dbg_reg_x19 = regfile[19]; wire [31:0] dbg_reg_x20 = regfile[20]; wire [31:0] dbg_reg_x21 = regfile[21]; wire [31:0] dbg_reg_x22 = regfile[22]; wire [31:0] dbg_reg_x23 = regfile[23]; wire [31:0] dbg_reg_x24 = regfile[24]; wire [31:0] dbg_reg_x25 = regfile[25]; wire [31:0] dbg_reg_x26 = regfile[26]; wire [31:0] dbg_reg_x27 = regfile[27]; wire [31:0] dbg_reg_x28 = regfile[28]; wire [31:0] dbg_reg_x29 = regfile[29]; wire [31:0] dbg_reg_x30 = regfile[30]; wire [31:0] dbg_reg_x31 = regfile[31]; `endif endmodule ================================================ FILE: cores/nerv/nervsoc.sv ================================================ /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 Claire Xenia Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ module nervsoc ( input clock, input reset, output reg [31:0] leds ); reg [31:0] imem [0:1023]; reg [31:0] dmem [0:1023]; wire stall = 0; wire trap; wire [31:0] imem_addr; reg [31:0] imem_data; wire dmem_valid; wire [31:0] dmem_addr; wire [3:0] dmem_wstrb; wire [31:0] dmem_wdata; reg [31:0] dmem_rdata; initial begin $readmemh("firmware.hex", imem); end always @(posedge clock) imem_data <= imem[imem_addr[31:2]]; always @(posedge clock) begin if (dmem_valid) begin if (dmem_addr == 32'h 0100_0000) begin if (dmem_wstrb[0]) leds[ 7: 0] <= dmem_wdata[ 7: 0]; if (dmem_wstrb[1]) leds[15: 8] <= dmem_wdata[15: 8]; if (dmem_wstrb[2]) leds[23:16] <= dmem_wdata[23:16]; if (dmem_wstrb[3]) leds[31:24] <= dmem_wdata[31:24]; end else begin if (dmem_wstrb[0]) dmem[dmem_addr[31:2]][ 7: 0] <= dmem_wdata[ 7: 0]; if (dmem_wstrb[1]) dmem[dmem_addr[31:2]][15: 8] <= dmem_wdata[15: 8]; if (dmem_wstrb[2]) dmem[dmem_addr[31:2]][23:16] <= dmem_wdata[23:16]; if (dmem_wstrb[3]) dmem[dmem_addr[31:2]][31:24] <= dmem_wdata[31:24]; end dmem_rdata <= dmem[dmem_addr[31:2]]; end end nerv cpu ( .clock (clock ), .reset (reset ), .stall (stall ), .trap (trap ), .imem_addr (imem_addr ), .imem_data (imem_data ), .dmem_valid(dmem_valid), .dmem_addr (dmem_addr ), .dmem_wstrb(dmem_wstrb), .dmem_wdata(dmem_wdata), .dmem_rdata(dmem_rdata) ); endmodule ================================================ FILE: cores/nerv/sections.lds ================================================ MEMORY { /* the memory in the testbench is 64k in size; * set LENGTH=48k and leave at least 16k for stack */ RAM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x00c000 } SECTIONS { /* The program code and other data goes into FLASH */ .text : { . = ALIGN(4); *(.text) /* .text sections (code) */ *(.text*) /* .text* sections (code) */ PROVIDE(__vector_start = .); KEEP(*(.vectors)); *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ *(.srodata) /* .rodata sections (constants, strings, etc.) */ *(.srodata*) /* .rodata* sections (constants, strings, etc.) */ . = ALIGN(4); _etext = .; /* define a global symbol at end of code */ _sidata = _etext; /* This is used by the startup in order to initialize the .data secion */ } >RAM /* This is the initialized data section The program executes knowing that the data is in the RAM but the loader puts the initial values in the FLASH (inidata). It is one task of the startup to copy the initial values from FLASH to RAM. */ .data : AT ( _sidata ) { . = ALIGN(4); _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ _ram_start = .; /* create a global symbol at ram start for garbage collector */ . = ALIGN(4); *(.data) /* .data sections */ *(.data*) /* .data* sections */ *(.sdata) /* .sdata sections */ *(.sdata*) /* .sdata* sections */ . = ALIGN(4); _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ } >RAM /* Uninitialized data section */ .bss : { . = ALIGN(4); _sbss = .; /* define a global symbol at bss start; used by startup code */ *(.bss) *(.bss*) *(.sbss) *(.sbss*) *(COMMON) . = ALIGN(4); _ebss = .; /* define a global symbol at bss end; used by startup code */ } >RAM /* this is to define the start of the heap, and make sure we have a minimum size */ .heap : { . = ALIGN(4); _heap_start = .; /* define a global symbol at heap start */ } >RAM } ================================================ FILE: cores/nerv/testbench.gtkw ================================================ [*] [*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI [*] Tue Oct 20 19:25:31 2020 [*] [dumpfile] "/home/claire/Work/riscv-formal/cores/nerv/testbench.vcd" [dumpfile_mtime] "Tue Oct 20 19:24:49 2020" [dumpfile_size] 76428 [savefile] "/home/claire/Work/riscv-formal/cores/nerv/testbench.gtkw" [timestart] 305 [size] 1397 995 [pos] -1 -1 *-6.000000 497 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] testbench. [sst_width] 240 [signals_width] 174 [sst_expanded] 1 [sst_vpaned_height] 289 @28 testbench.dut.clock testbench.dut.reset testbench.dut.stall testbench.dut.trap @200 - @22 testbench.dut.imem_addr[31:0] testbench.dut.imem_data[31:0] @200 - @28 testbench.dut.dmem_valid @22 testbench.dut.dmem_addr[31:0] testbench.dut.dmem_wstrb[3:0] testbench.dut.dmem_wdata[31:0] testbench.dut.dmem_rdata[31:0] @200 - @22 testbench.dut.pc[31:0] testbench.dut.insn[31:0] @28 testbench.dut.illinsn @c00200 -insn_decoded @22 testbench.dut.insn_funct7[6:0] testbench.dut.insn_rs2[4:0] testbench.dut.insn_rs1[4:0] @28 testbench.dut.insn_funct3[2:0] @22 testbench.dut.insn_rd[4:0] testbench.dut.insn_opcode[6:0] @200 - @22 testbench.dut.imm_b_sext[31:0] testbench.dut.imm_i_sext[31:0] testbench.dut.imm_j_sext[31:0] testbench.dut.imm_s_sext[31:0] @1401200 -insn_decoded @22 testbench.dut.rs1_value[31:0] testbench.dut.rs2_value[31:0] @28 testbench.dut.next_wr @22 testbench.dut.next_rd[31:0] @c00200 -registers @22 testbench.dut.dbg_reg_x0[31:0] testbench.dut.dbg_reg_x1[31:0] testbench.dut.dbg_reg_x2[31:0] testbench.dut.dbg_reg_x3[31:0] testbench.dut.dbg_reg_x4[31:0] testbench.dut.dbg_reg_x5[31:0] testbench.dut.dbg_reg_x6[31:0] testbench.dut.dbg_reg_x7[31:0] testbench.dut.dbg_reg_x8[31:0] testbench.dut.dbg_reg_x9[31:0] testbench.dut.dbg_reg_x10[31:0] testbench.dut.dbg_reg_x11[31:0] testbench.dut.dbg_reg_x12[31:0] testbench.dut.dbg_reg_x13[31:0] testbench.dut.dbg_reg_x14[31:0] testbench.dut.dbg_reg_x15[31:0] testbench.dut.dbg_reg_x16[31:0] testbench.dut.dbg_reg_x17[31:0] testbench.dut.dbg_reg_x18[31:0] testbench.dut.dbg_reg_x19[31:0] testbench.dut.dbg_reg_x20[31:0] testbench.dut.dbg_reg_x21[31:0] testbench.dut.dbg_reg_x22[31:0] testbench.dut.dbg_reg_x23[31:0] testbench.dut.dbg_reg_x24[31:0] testbench.dut.dbg_reg_x25[31:0] testbench.dut.dbg_reg_x26[31:0] testbench.dut.dbg_reg_x27[31:0] testbench.dut.dbg_reg_x28[31:0] testbench.dut.dbg_reg_x29[31:0] testbench.dut.dbg_reg_x30[31:0] testbench.dut.dbg_reg_x31[31:0] @1401200 -registers @200 - @28 testbench.dut.mem_rd_enable @22 testbench.dut.mem_rd_addr[31:0] testbench.dut.mem_rd_func[4:0] testbench.dut.mem_rd_reg[4:0] @200 - @28 testbench.dut.mem_rd_enable_q @22 testbench.dut.mem_rd_func_q[4:0] testbench.dut.mem_rd_reg_q[4:0] testbench.dut.mem_rdata[31:0] @200 - @28 testbench.dut.mem_wr_enable @22 testbench.dut.mem_wr_addr[31:0] testbench.dut.mem_wr_data[31:0] testbench.dut.mem_wr_strb[3:0] @200 - -CSRs @24 testbench.dut.csr_mcycle_value[31:0] testbench.dut.csr_minstret_value[31:0] @28 testbench.dut.csr_mstatus_value[31:0] @22 testbench.dut.csr_mtvec_value[31:0] testbench.dut.csr_mcause_value[31:0] testbench.dut.csr_mepc_value[31:0] @201 -Interrupts @22 testbench.dut.irq[31:0] testbench.dut.irq_en[31:0] testbench.dut.irq_num[4:0] [pattern_trace] 1 [pattern_trace] 0 ================================================ FILE: cores/nerv/testbench.sv ================================================ /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 N. Engelhardt * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ module testbench; localparam MEM_ADDR_WIDTH = 16; localparam TIMEOUT = (1<<10); reg clock; reg reset = 1'b1; reg stall = 1'b0; wire trap; wire [31:0] imem_addr; reg [31:0] imem_data; wire dmem_valid; wire [31:0] dmem_addr; wire [ 3:0] dmem_wstrb; wire [31:0] dmem_wdata; reg [31:0] dmem_rdata; reg [31:0] irq = 'b0; always #5 clock = clock === 1'b0; always @(posedge clock) reset <= 0; reg [7:0] mem [0:(1<= (1<= TIMEOUT)) begin $display("Simulated %0d cycles", cycles); $finish; end end endmodule ================================================ FILE: cores/nerv/trace.gtkw ================================================ [*] [*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI [*] Wed Oct 21 17:13:34 2020 [*] [dumpfile] "(null)" [savefile] "/home/claire/Work/riscv-formal/cores/nerv/trace.gtkw" [timestart] 0 [size] 1259 841 [pos] 2135 225 *-5.139064 105 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] rvfi_testbench. [treeopen] rvfi_testbench.checker_inst. [treeopen] rvfi_testbench.wrapper. [sst_width] 240 [signals_width] 287 [sst_expanded] 1 [sst_vpaned_height] 235 @24 smt_step @200 - -Core @28 rvfi_testbench.wrapper.uut.clock rvfi_testbench.wrapper.uut.reset rvfi_testbench.wrapper.uut.stall rvfi_testbench.wrapper.uut.trap @200 - @23 rvfi_testbench.wrapper.uut.pc[31:0] @22 rvfi_testbench.wrapper.uut.insn[31:0] @c00200 -insn_decoded @22 rvfi_testbench.wrapper.uut.insn_funct7[6:0] rvfi_testbench.wrapper.uut.insn_rs2[4:0] rvfi_testbench.wrapper.uut.insn_rs1[4:0] @28 rvfi_testbench.wrapper.uut.insn_funct3[2:0] @22 rvfi_testbench.wrapper.uut.insn_rd[4:0] rvfi_testbench.wrapper.uut.insn_opcode[6:0] @200 - @22 rvfi_testbench.wrapper.uut.imm_b_sext[31:0] rvfi_testbench.wrapper.uut.imm_i_sext[31:0] rvfi_testbench.wrapper.uut.imm_j_sext[31:0] rvfi_testbench.wrapper.uut.imm_s_sext[31:0] @1401200 -insn_decoded @200 - -Checker @24 rvfi_testbench.checker_inst.rvfi_order[63:0] @28 rvfi_testbench.checker_inst.rvfi_valid @29 rvfi_testbench.checker_inst.spec_valid @28 rvfi_testbench.checker_inst.rvfi_trap @22 rvfi_testbench.checker_inst.rvfi_insn[31:0] rvfi_testbench.wrapper.uut.rvfi_pc_rdata[31:0] @c00200 -spec @28 rvfi_testbench.checker_inst.spec_valid rvfi_testbench.checker_inst.spec_trap @200 - @22 rvfi_testbench.checker_inst.spec_rs1_addr[4:0] rvfi_testbench.checker_inst.spec_rs2_addr[4:0] rvfi_testbench.checker_inst.spec_rd_addr[4:0] rvfi_testbench.checker_inst.spec_rd_wdata[31:0] rvfi_testbench.checker_inst.spec_pc_wdata[31:0] @200 - @22 rvfi_testbench.checker_inst.spec_mem_addr[31:0] rvfi_testbench.checker_inst.spec_mem_wdata[31:0] rvfi_testbench.checker_inst.spec_mem_rmask[3:0] rvfi_testbench.checker_inst.spec_mem_wmask[3:0] @1401200 -spec @c00200 -rvfi @24 rvfi_testbench.checker_inst.rvfi_order[63:0] @28 rvfi_testbench.checker_inst.rvfi_valid rvfi_testbench.checker_inst.rvfi_trap rvfi_testbench.checker_inst.rvfi_halt rvfi_testbench.checker_inst.rvfi_intr rvfi_testbench.checker_inst.rvfi_ixl[1:0] rvfi_testbench.checker_inst.rvfi_mode[1:0] @22 rvfi_testbench.checker_inst.rvfi_insn[31:0] @200 - @22 rvfi_testbench.checker_inst.rvfi_pc_rdata[31:0] rvfi_testbench.checker_inst.rvfi_pc_wdata[31:0] @200 - @22 rvfi_testbench.checker_inst.rvfi_rs1_addr[4:0] rvfi_testbench.checker_inst.rvfi_rs2_addr[4:0] rvfi_testbench.checker_inst.rvfi_rd_addr[4:0] @200 - @22 rvfi_testbench.checker_inst.rvfi_rs1_rdata[31:0] rvfi_testbench.checker_inst.rvfi_rs2_rdata[31:0] rvfi_testbench.checker_inst.rvfi_rd_wdata[31:0] @200 - @22 rvfi_testbench.checker_inst.rvfi_mem_addr[31:0] rvfi_testbench.checker_inst.rvfi_mem_rdata[31:0] rvfi_testbench.checker_inst.rvfi_mem_rmask[3:0] rvfi_testbench.checker_inst.rvfi_mem_wdata[31:0] rvfi_testbench.checker_inst.rvfi_mem_wmask[3:0] @1401200 -rvfi @c00200 -csr @28 rvfi_testbench.checker_inst.check rvfi_testbench.checker_inst.csr_write_valid rvfi_testbench.checker_inst.csr_read_valid rvfi_testbench.checker_inst.csr_written rvfi_testbench.checker_inst.csr_read_shadowed rvfi_testbench.checker_inst.csr_mode_shadow @22 rvfi_testbench.checker_inst.csr_mode[1:0] rvfi_testbench.checker_inst.csr_insn_addr[11:0] rvfi_testbench.checker_inst.csr_insn_rdata[31:0] rvfi_testbench.checker_inst.csr_insn_rmask[31:0] rvfi_testbench.checker_inst.csr_insn_wdata[31:0] rvfi_testbench.checker_inst.csr_insn_wmask[31:0] rvfi_testbench.checker_inst.rsval_shadow[31:0] rvfi_testbench.checker_inst.wdata_shadow[31:0] rvfi_testbench.checker_inst.rdata_shadow[31:0] rvfi_testbench.checker_inst.csr_mode_shadow[1:0] @1401200 -csr [pattern_trace] 1 [pattern_trace] 0 ================================================ FILE: cores/nerv/vectors.s ================================================ /* * Copyright 2019 ETH Zürich and University of Bologna * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ .section .vectors, "ax" .option norvc vector_table: j sw_irq_handler /* 0 */ j __no_irq_handler /* 1 */ j __no_irq_handler /* 2 */ j software_irq_handler /* 3 */ j __no_irq_handler /* 4 */ j __no_irq_handler /* 5 */ j __no_irq_handler /* 6 */ j timer_irq_handler /* 7 */ j __no_irq_handler /* 8 */ j __no_irq_handler /* 9 */ j __no_irq_handler /* 10 */ j external_irq_handler /* 11 */ j __no_irq_handler /* 12 */ j __no_irq_handler /* 13 */ j __no_irq_handler /* 14 */ j __no_irq_handler /* 15 */ j __no_irq_handler /* 16 */ j __no_irq_handler /* 17 */ j __no_irq_handler /* 18 */ j __no_irq_handler /* 19 */ j __no_irq_handler /* 20 */ j __no_irq_handler /* 21 */ j __no_irq_handler /* 22 */ j __no_irq_handler /* 23 */ j __no_irq_handler /* 24 */ j __no_irq_handler /* 25 */ j __no_irq_handler /* 26 */ j __no_irq_handler /* 27 */ j __no_irq_handler /* 28 */ j __no_irq_handler /* 29 */ j __no_irq_handler /* 30 */ j __no_irq_handler /* 31 */ .section .text.vecs /* exception handling */ __no_irq_handler: la a0, no_exception_handler_msg jal ra, puts j __no_irq_handler sw_irq_handler: csrr t0, mcause slli t0, t0, 1 /* shift off the high bit */ srli t0, t0, 1 li t1, 2 beq t0, t1, handle_illegal_insn li t1, 11 beq t0, t1, handle_ecall li t1, 3 beq t0, t1, handle_ebreak j handle_unknown handle_ecall: la a0, ecall_msg jal ra, puts j end_handler handle_ebreak: la a0, ebreak_msg jal ra, puts j end_handler handle_illegal_insn: la a0, illegal_insn_msg jal ra, puts j end_handler handle_unknown: la a0, unknown_msg jal ra, puts j end_handler end_handler: csrr a0, mepc addi a0, a0, 4 csrw mepc, a0 mret /* this interrupt can be generated for verification purposes, random or when the PC is equal to a given value*/ verification_irq_handler: mret software_irq_handler: la a0, software_irq_msg jal ra, puts mret timer_irq_handler: la a0, timer_irq_msg jal ra, puts mret external_irq_handler: la a0, external_irq_msg jal ra, puts mret .section .rodata illegal_insn_msg: .string "illegal instruction exception handler entered\n" ecall_msg: .string "ecall exception handler entered\n" ebreak_msg: .string "ebreak exception handler entered\n" unknown_msg: .string "unknown exception handler entered\n" no_exception_handler_msg: .string "no exception handler installed\n" software_irq_msg: .string "software irq handler entered\n" timer_irq_msg: .string "timer irq handler entered\n" external_irq_msg: .string "external irq handler entered\n" ================================================ FILE: cores/nerv/wrapper.sv ================================================ /* * NERV -- Naive Educational RISC-V Processor * * Copyright (C) 2020 Claire Xenia Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ module rvfi_wrapper ( input clock, input reset, `RVFI_OUTPUTS `RVFI_BUS_OUTPUTS ); (* keep *) `rvformal_rand_reg stall; (* keep *) `rvformal_rand_reg [31:0] imem_data; (* keep *) `rvformal_rand_reg [31:0] dmem_rdata; (* keep *) `rvformal_rand_reg [31:0] irq; `ifdef NERV_FAULT (* keep *) `rvformal_rand_reg imem_fault; (* keep *) `rvformal_rand_reg dmem_fault; `else wire imem_fault = 0; wire dmem_fault = 0; `endif (* keep *) wire trap; (* keep *) wire [31:0] imem_addr; (* keep *) wire dmem_valid; (* keep *) wire [31:0] dmem_addr; (* keep *) wire [ 3:0] dmem_wstrb; (* keep *) wire [31:0] dmem_wdata; nerv uut ( .clock (clock ), .reset (reset ), .stall (stall ), .trap (trap ), .imem_addr (imem_addr ), .imem_data (imem_data ), .dmem_valid (dmem_valid), .dmem_addr (dmem_addr ), .dmem_wstrb (dmem_wstrb), .dmem_wdata (dmem_wdata), .dmem_rdata (dmem_rdata), `ifdef NERV_FAULT .imem_fault (imem_fault), .dmem_fault (dmem_fault), `endif .irq (irq), `RVFI_CONN32 ); `ifdef RISCV_FORMAL_BUS `define RISCV_FORMAL_CHANNEL_SIGNAL(channels, width, name) \ (* keep *) reg [(width) - 1:0] imem_``name; assign rvfi_``name[0 * (width) +: (width)] = imem_``name; `RVFI_BUS_SIGNALS `undef RISCV_FORMAL_CHANNEL_SIGNAL `define RISCV_FORMAL_CHANNEL_SIGNAL(channels, width, name) \ (* keep *) reg [(width) - 1:0] dmem_``name; assign rvfi_``name[1 * (width) +: (width)] = dmem_``name; `RVFI_BUS_SIGNALS `undef RISCV_FORMAL_CHANNEL_SIGNAL reg [31:0] imem_addr_q; always @(posedge clock) begin if (!stall) imem_addr_q <= imem_addr; end always @* begin imem_bus_addr = imem_addr_q; imem_bus_insn = 1; imem_bus_data = 0; imem_bus_rmask = 4'b1111; imem_bus_wmask = 4'b0000; imem_bus_rdata = imem_data; imem_bus_wdata = 0; imem_bus_fault = imem_fault; imem_bus_valid = !stall; end; reg dmem_valid_q; reg [31:0] dmem_addr_q; reg [ 3:0] dmem_wstrb_q; reg [31:0] dmem_wdata_q; (* keep *) `rvformal_rand_reg [31:0] next_dmem_rdata; reg [31:0] next_dmem_rdata_q; `ifdef NERV_FAULT (* keep *) `rvformal_rand_reg [31:0] next_dmem_fault; reg [31:0] next_dmem_fault_q; `endif always @(posedge clock) begin if (!stall) begin next_dmem_rdata_q <= next_dmem_rdata; `ifdef NERV_FAULT next_dmem_fault_q <= next_dmem_fault; `endif end end always @* begin if (!stall) begin assume (dmem_rdata == next_dmem_rdata_q); `ifdef NERV_FAULT assume (dmem_fault == next_dmem_fault_q); `endif end dmem_bus_addr = dmem_addr; dmem_bus_insn = 0; dmem_bus_data = 1; dmem_bus_rmask = dmem_wstrb ? 4'b0000 : 4'b1111; dmem_bus_wmask = dmem_wstrb; dmem_bus_rdata = next_dmem_rdata; dmem_bus_wdata = dmem_wdata; dmem_bus_fault = next_dmem_fault; dmem_bus_valid = !stall && dmem_valid; end; `endif `ifdef NERV_FAIRNESS reg [2:0] stalled = 0; always @(posedge clock) begin stalled <= {stalled, stall}; assume (~stalled); end `endif endmodule ================================================ FILE: cores/picorv32/.gitignore ================================================ /cover/ /complete/ /honest/ /checks/ /testbug[0-9][0-9][0-9].cfg /testbug[0-9][0-9][0-9]/ /testbugs.mk /cexdata-[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9] /cexdata-[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9].zip /picorv32.v /disasm.s /disasm.o ================================================ FILE: cores/picorv32/Makefile ================================================ picorv32.v: wget -O picorv32.v https://raw.githubusercontent.com/YosysHQ/picorv32/master/picorv32.v checks: picorv32.v python3 ../../checks/genchecks.py $(MAKE) -C checks check: checks bash cexdata.sh cat cexdata-*/status.txt clean: rm -f picorv32.v cexdata-*.zip rm -rf disasm.o disasm.s checks/ cexdata-*/ rm -f testbug*.cfg rm -rf testbug*/ ================================================ FILE: cores/picorv32/README.md ================================================ riscv-formal proofs for picorv32 ================================ Quickstart guide: First install Yosys, SBY, and the solvers. See the [SBY Installation Guide](https://yosyshq.readthedocs.io/projects/sby/en/latest/install.html) for instructions. Then download the core, generate the formal checks and run them: ``` make check -j$(nproc) ``` ================================================ FILE: cores/picorv32/cexdata.sh ================================================ #!/bin/bash set -ex cexdata="cexdata-$(date '+%Y%m%d')" rm -rf $cexdata mkdir $cexdata for x in {checks,testbug[0-9][0-9][0-9]}/*/FAIL; do test -f $x || continue x=${x%/FAIL} y=${x/\//_} cp $x/logfile.txt $cexdata/$y.log if test -f $x/engine_*/trace.vcd; then cp $x/engine_*/trace.vcd $cexdata/$y.vcd python3 disasm.py $cexdata/$y.vcd > $cexdata/$y.asm fi done for x in {checks,testbug[0-9][0-9][0-9]}/*.sby; do test -f $x || continue x=${x%.sby} if [ -f $x/PASS ]; then printf "%-30s %s %10s\n" $x pass $(sed '/Elapsed process time/ { s/.*\]: //; s/ .*//; p; }; d;' $x/logfile.txt) elif [ -f $x/FAIL ]; then printf "%-30s %s %10s\n" $x FAIL $(sed '/Elapsed process time/ { s/.*\]: //; s/ .*//; p; }; d;' $x/logfile.txt) else printf "%-30s %s\n" $x unknown fi done | awk '{ print gensub(":", "", "g", $3), $0; }' | sort -n | cut -f2- -d' ' > $cexdata/status.txt rm -f $cexdata.zip zip -r $cexdata.zip $cexdata/ ================================================ FILE: cores/picorv32/checks.cfg ================================================ [options] isa rv32imc [depth] insn 20 reg 15 25 pc_fwd 10 30 pc_bwd 10 30 liveness 1 10 30 unique 1 10 30 causal 10 30 cover 1 15 csrw 15 csr_ill 15 csrc_inc 1 15 csrc_upcnt 1 15 [sort] reg_ch0 [csrs] mcycle inc upcnt minstret inc upcnt [illegal_csrs] c00 u w c80 u w c02 u w c82 u w [defines] `define RISCV_FORMAL_ALIGNED_MEM `define RISCV_FORMAL_ALTOPS `define RISCV_FORMAL_UMODE `define PICORV32_TESTBUG_NONE `define DEBUGNETS [defines liveness] `define PICORV32_FAIRNESS [verilog-files] @basedir@/cores/@core@/wrapper.sv @basedir@/cores/@core@/@core@.v [cover] always @* if (!reset) cover (channel[0].cnt_insns == 2); ================================================ FILE: cores/picorv32/checks.gtkw ================================================ [*] [*] GTKWave Analyzer v3.3.65 (w)1999-2015 BSI [*] Wed Sep 13 00:29:24 2017 [*] [dumpfile] "(null)" [savefile] "/home/claire/Work/riscv-formal/cores/picorv32/checks.gtkw" [timestart] 0 [size] 1263 878 [pos] -1 -1 *-6.814997 100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] rvfi_testbench. [treeopen] rvfi_testbench.wrapper. [sst_width] 225 [signals_width] 335 [sst_expanded] 1 [sst_vpaned_height] 258 @24 smt_step @200 - -PicoRV32 @28 rvfi_testbench.wrapper.uut.resetn @820 rvfi_testbench.wrapper.uut.dbg_ascii_state[127:0] rvfi_testbench.wrapper.uut.dbg_ascii_instr[63:0] @200 - @28 rvfi_testbench.wrapper.mem_valid rvfi_testbench.wrapper.mem_ready rvfi_testbench.wrapper.mem_instr @22 rvfi_testbench.wrapper.mem_addr[31:0] rvfi_testbench.wrapper.mem_wstrb[3:0] rvfi_testbench.wrapper.mem_rdata[31:0] rvfi_testbench.wrapper.mem_wdata[31:0] @200 - -RVFI @28 rvfi_testbench.checker_inst.reset rvfi_testbench.checker_inst.trig rvfi_testbench.checker_inst.check @200 - @28 rvfi_testbench.checker_inst.rvfi_valid rvfi_testbench.checker_inst.rvfi_trap rvfi_testbench.checker_inst.rvfi_intr rvfi_testbench.checker_inst.rvfi_halt @200 - @25 rvfi_testbench.checker_inst.rvfi_order[63:0] @22 rvfi_testbench.checker_inst.rvfi_insn[31:0] rvfi_testbench.checker_inst.rvfi_pc_rdata[31:0] rvfi_testbench.checker_inst.rvfi_pc_wdata[31:0] @200 - @22 rvfi_testbench.checker_inst.rvfi_rs1_addr[4:0] rvfi_testbench.checker_inst.rvfi_rs2_addr[4:0] rvfi_testbench.checker_inst.rvfi_rd_addr[4:0] @200 - @22 rvfi_testbench.checker_inst.rvfi_rs1_rdata[31:0] rvfi_testbench.checker_inst.rvfi_rs2_rdata[31:0] rvfi_testbench.checker_inst.rvfi_rd_wdata[31:0] @200 - @22 rvfi_testbench.checker_inst.rvfi_mem_addr[31:0] rvfi_testbench.checker_inst.rvfi_mem_rmask[3:0] rvfi_testbench.checker_inst.rvfi_mem_wmask[3:0] rvfi_testbench.checker_inst.rvfi_mem_rdata[31:0] rvfi_testbench.checker_inst.rvfi_mem_wdata[31:0] @200 - [pattern_trace] 1 [pattern_trace] 0 ================================================ FILE: cores/picorv32/complete.sby ================================================ [options] mode bmc aigsmt z3 depth 20 [engines] abc bmc3 [script] verilog_defines -D DEBUGNETS verilog_defines -D RISCV_FORMAL verilog_defines -D RISCV_FORMAL_NRET=1 verilog_defines -D RISCV_FORMAL_XLEN=32 verilog_defines -D RISCV_FORMAL_ILEN=32 verilog_defines -D RISCV_FORMAL_COMPRESSED verilog_defines -D RISCV_FORMAL_ALIGNED_MEM read_verilog -sv rvfi_macros.vh read_verilog -sv picorv32.v --pycode-begin-- with open("../../insns/isa_rv32ic.txt") as f: for line in f: output("read_verilog -sv insn_%s.v" % line.strip()) --pycode-end-- read_verilog -sv isa_rv32ic.v read_verilog -sv complete.sv prep -nordff -top testbench [files] complete.sv ../../../picorv32/picorv32.v ../../checks/rvfi_macros.vh ../../insns/isa_rv32ic.v --pycode-begin-- with open("../../insns/isa_rv32ic.txt") as f: for line in f: output("../../insns/insn_%s.v" % line.strip()) --pycode-end-- ================================================ FILE: cores/picorv32/complete.sv ================================================ module testbench ( input clk, input mem_ready, output mem_valid, output mem_instr, output [31:0] mem_addr, output [31:0] mem_wdata, output [3:0] mem_wstrb, input [31:0] mem_rdata, ); reg resetn = 0; wire trap; always @(posedge clk) resetn <= 1; `RVFI_WIRES picorv32 #( .COMPRESSED_ISA(1), .BARREL_SHIFTER(1) ) uut ( .clk (clk ), .resetn (resetn ), .trap (trap ), .mem_valid (mem_valid ), .mem_instr (mem_instr ), .mem_ready (mem_ready ), .mem_addr (mem_addr ), .mem_wdata (mem_wdata ), .mem_wstrb (mem_wstrb ), .mem_rdata (mem_rdata ), `RVFI_CONN ); (* keep *) wire spec_valid; (* keep *) wire spec_trap; (* keep *) wire [ 4 : 0] spec_rs1_addr; (* keep *) wire [ 4 : 0] spec_rs2_addr; (* keep *) wire [ 4 : 0] spec_rd_addr; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask; (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask; (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata; rvfi_isa_rv32ic isa_spec ( .rvfi_valid (rvfi_valid ), .rvfi_insn (rvfi_insn ), .rvfi_pc_rdata (rvfi_pc_rdata ), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), .spec_valid (spec_valid ), .spec_trap (spec_trap ), .spec_rs1_addr (spec_rs1_addr ), .spec_rs2_addr (spec_rs2_addr ), .spec_rd_addr (spec_rd_addr ), .spec_rd_wdata (spec_rd_wdata ), .spec_pc_wdata (spec_pc_wdata ), .spec_mem_addr (spec_mem_addr ), .spec_mem_rmask(spec_mem_rmask), .spec_mem_wmask(spec_mem_wmask), .spec_mem_wdata(spec_mem_wdata) ); always @* begin if (resetn && rvfi_valid && !rvfi_trap) begin if (rvfi_insn[6:0] != 7'b1110011) assert(spec_valid && !spec_trap); end end endmodule ================================================ FILE: cores/picorv32/cover.sby ================================================ [options] mode cover depth 100 [engines] smtbmc boolector [script] verilog_defines -D RISCV_FORMAL verilog_defines -D RISCV_FORMAL_NRET=1 verilog_defines -D RISCV_FORMAL_XLEN=32 verilog_defines -D RISCV_FORMAL_ILEN=32 verilog_defines -D RISCV_FORMAL_ALIGNED_MEM read_verilog rvfi_macros.vh read_verilog picorv32.v read_verilog -sv -formal cover.sv prep -nordff -top testbench [files] ../../checks/rvfi_macros.vh ../../../picorv32/picorv32.v cover.sv ================================================ FILE: cores/picorv32/cover.sv ================================================ module testbench ( input clk, input mem_ready, output mem_valid, output mem_instr, output [31:0] mem_addr, output [31:0] mem_wdata, output [3:0] mem_wstrb, input [31:0] mem_rdata, ); reg resetn = 0; wire trap; always @(posedge clk) resetn <= 1; `RVFI_WIRES picorv32 #( .REGS_INIT_ZERO(1), .COMPRESSED_ISA(1), .BARREL_SHIFTER(1) ) uut ( .clk (clk ), .resetn (resetn ), .trap (trap ), .mem_valid (mem_valid ), .mem_instr (mem_instr ), .mem_ready (mem_ready ), .mem_addr (mem_addr ), .mem_wdata (mem_wdata ), .mem_wstrb (mem_wstrb ), .mem_rdata (mem_rdata ), `RVFI_CONN ); integer count_dmemrd = 0; integer count_dmemwr = 0; integer count_longinsn = 0; integer count_comprinsn = 0; always @(posedge clk) begin if (resetn && rvfi_valid) begin if (rvfi_mem_rmask) count_dmemrd <= count_dmemrd + 1; if (rvfi_mem_wmask) count_dmemwr <= count_dmemwr + 1; if (rvfi_insn[1:0] == 3) count_longinsn <= count_longinsn + 1; if (rvfi_insn[1:0] != 3) count_comprinsn <= count_comprinsn + 1; end end cover property (count_dmemrd); cover property (count_dmemwr); cover property (count_longinsn); cover property (count_comprinsn); cover property (count_dmemrd >= 1 && count_dmemwr >= 1 && count_longinsn >= 1 && count_comprinsn >= 1); cover property (count_dmemrd >= 2 && count_dmemwr >= 2 && count_longinsn >= 2 && count_comprinsn >= 2); cover property (count_dmemrd >= 3 && count_dmemwr >= 2 && count_longinsn >= 2 && count_comprinsn >= 2); cover property (count_dmemrd >= 2 && count_dmemwr >= 3 && count_longinsn >= 2 && count_comprinsn >= 2); cover property (count_dmemrd >= 2 && count_dmemwr >= 2 && count_longinsn >= 3 && count_comprinsn >= 2); cover property (count_dmemrd >= 2 && count_dmemwr >= 2 && count_longinsn >= 2 && count_comprinsn >= 3); endmodule ================================================ FILE: cores/picorv32/disasm.py ================================================ #!/usr/bin/env python3 from Verilog_VCD.Verilog_VCD import parse_vcd from os import system from sys import argv rvfi_valid = None rvfi_order = None rvfi_insn = None for netinfo in parse_vcd(argv[1]).values(): for net in netinfo['nets']: # print(net["hier"], net["name"]) if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_valid": rvfi_valid = netinfo['tv'] if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_order": rvfi_order = netinfo['tv'] if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_insn": rvfi_insn = netinfo['tv'] assert len(rvfi_valid) == len(rvfi_order) assert len(rvfi_valid) == len(rvfi_insn) prog = list() for tv_valid, tv_order, tv_insn in zip(rvfi_valid, rvfi_order, rvfi_insn): if tv_valid[1] == '1': prog.append((int(tv_order[1], 2), int(tv_insn[1], 2))) with open("disasm.s", "w") as f: for tv_order, tv_insn in sorted(prog): if tv_insn & 3 != 3 and tv_insn & 0xffff0000 == 0: print(".hword 0x%04x # %d" % (tv_insn, tv_order), file=f) else: print(".word 0x%08x # %d" % (tv_insn, tv_order), file=f) system("riscv32-unknown-elf-gcc -c disasm.s") system("riscv32-unknown-elf-objdump -d -M numeric,no-aliases disasm.o") ================================================ FILE: cores/picorv32/dmemcheck.sv ================================================ module testbench ( input clk, input mem_ready, output mem_valid, output mem_instr, output [31:0] mem_addr, output [31:0] mem_wdata, output [3:0] mem_wstrb, input [31:0] mem_rdata ); reg resetn = 0; wire trap; always @(posedge clk) resetn <= 1; `RVFI_WIRES wire [31:0] dmem_addr; reg [31:0] dmem_data; rvfi_dmem_check checker_inst ( .clock (clk ), .reset (!resetn ), .enable (1'b1 ), .dmem_addr (dmem_addr), `RVFI_CONN ); always @(posedge clk) begin if (resetn && mem_valid && mem_ready && mem_addr == dmem_addr) begin if (mem_wstrb[0]) dmem_data[ 7: 0] <= mem_wdata[ 7: 0]; if (mem_wstrb[1]) dmem_data[15: 8] <= mem_wdata[15: 8]; if (mem_wstrb[2]) dmem_data[23:16] <= mem_wdata[23:16]; if (mem_wstrb[3]) dmem_data[31:24] <= mem_wdata[31:24]; end end always @* begin if (resetn && mem_valid && mem_ready && mem_addr == dmem_addr && !mem_wstrb) assume(dmem_data == mem_rdata); end picorv32 #( .REGS_INIT_ZERO(1), .COMPRESSED_ISA(1), .BARREL_SHIFTER(1) ) uut ( .clk (clk ), .resetn (resetn ), .trap (trap ), .mem_valid (mem_valid ), .mem_instr (mem_instr ), .mem_ready (mem_ready ), .mem_addr (mem_addr ), .mem_wdata (mem_wdata ), .mem_wstrb (mem_wstrb ), .mem_rdata (mem_rdata ), `RVFI_CONN ); reg [4:0] mem_wait = 0; always @(posedge clk) begin mem_wait <= {mem_wait, mem_valid && !mem_ready}; // restrict(~mem_wait && !trap); end endmodule ================================================ FILE: cores/picorv32/equiv.sh ================================================ #!/bin/bash set -ex yosys -p ' read_verilog picorv32.v chparam -set COMPRESSED_ISA 0 -set BARREL_SHIFTER 1 picorv32 prep -flatten -top picorv32 design -stash gold read_verilog -D RISCV_FORMAL picorv32.v chparam -set COMPRESSED_ISA 0 -set BARREL_SHIFTER 1 picorv32 prep -flatten -top picorv32 delete -port picorv32/rvfi_* design -stash gate design -copy-from gold -as gold picorv32 design -copy-from gate -as gate picorv32 memory_map; opt -fast equiv_make gold gate equiv hierarchy -top equiv opt -fast equiv_simple equiv_induct equiv_status -assert ' ================================================ FILE: cores/picorv32/honest.sby ================================================ [options] mode bmc aigsmt z3 depth 30 [engines] abc bmc3 [script] verilog_defines -D DEBUGNETS verilog_defines -D RISCV_FORMAL verilog_defines -D RISCV_FORMAL_NRET=1 verilog_defines -D RISCV_FORMAL_XLEN=32 verilog_defines -D RISCV_FORMAL_ILEN=32 verilog_defines -D RISCV_FORMAL_COMPRESSED verilog_defines -D RISCV_FORMAL_ALIGNED_MEM read_verilog -sv rvfi_macros.vh read_verilog -sv picorv32.v read_verilog -sv honest.sv prep -nordff -top testbench [files] honest.sv ../../../picorv32/picorv32.v ../../checks/rvfi_macros.vh ================================================ FILE: cores/picorv32/honest.sv ================================================ module testbench ( input clk, input mem_ready, output mem_valid, output mem_instr, output [31:0] mem_addr, output [31:0] mem_wdata, output [3:0] mem_wstrb, input [31:0] mem_rdata, ); (* anyconst *) reg [31:0] monitor_insn; reg monitor_state = 0; reg [7:0] cycle = 0; reg resetn = 0; wire trap; always @(posedge clk) begin resetn <= 1; cycle <= cycle + 1; assume((!mem_valid || mem_ready) || $past(!mem_valid || mem_ready)); end `RVFI_WIRES picorv32 #( .COMPRESSED_ISA(1), .BARREL_SHIFTER(1) ) uut ( .clk (clk ), .resetn (resetn ), .trap (trap ), .mem_valid (mem_valid ), .mem_instr (mem_instr ), .mem_ready (mem_ready ), .mem_addr (mem_addr ), .mem_wdata (mem_wdata ), .mem_wstrb (mem_wstrb ), .mem_rdata (mem_rdata ), `RVFI_CONN ); always @* begin assume (mem_rdata == monitor_insn); if (!monitor_state) assert (cycle < 21); end always @(posedge clk) begin if (rvfi_valid && monitor_insn[1:0] == 3 && rvfi_insn == monitor_insn) monitor_state <= 1; if (rvfi_valid && monitor_insn[1:0] != 3 && rvfi_insn[15:0] == monitor_insn[15:0]) monitor_state <= 1; end endmodule ================================================ FILE: cores/picorv32/imemcheck.sv ================================================ module testbench ( input clk, input mem_ready, output mem_valid, output mem_instr, output [31:0] mem_addr, output [31:0] mem_wdata, output [3:0] mem_wstrb, input [31:0] mem_rdata ); reg resetn = 0; wire trap; always @(posedge clk) resetn <= 1; `RVFI_WIRES wire [31:0] imem_addr; wire [15:0] imem_data; rvfi_imem_check checker_inst ( .clock (clk ), .reset (!resetn ), .enable (1'b1 ), .imem_addr (imem_addr), .imem_data (imem_data), `RVFI_CONN ); always @* begin if (resetn && mem_valid && mem_ready) begin if (mem_addr == imem_addr) assume(mem_rdata[15:0] == imem_data); if (mem_addr+2 == imem_addr) assume(mem_rdata[31:16] == imem_data); end end picorv32 #( .REGS_INIT_ZERO(1), .COMPRESSED_ISA(1), .BARREL_SHIFTER(1) ) uut ( .clk (clk ), .resetn (resetn ), .trap (trap ), .mem_valid (mem_valid ), .mem_instr (mem_instr ), .mem_ready (mem_ready ), .mem_addr (mem_addr ), .mem_wdata (mem_wdata ), .mem_wstrb (mem_wstrb ), .mem_rdata (mem_rdata ), `RVFI_CONN ); reg [4:0] mem_wait = 0; always @(posedge clk) begin mem_wait <= {mem_wait, mem_valid && !mem_ready}; // restrict(~mem_wait && !trap); end endmodule ================================================ FILE: cores/picorv32/testbugs.sh ================================================ #!/bin/bash set -ex echo "all: checks" > testbugs.mk echo "checks::" >> testbugs.mk echo " \$(MAKE) -C checks" >> testbugs.mk if [ ! -d checks ]; then python3 ../../checks/genchecks.py fi for bug in 001 002 003 004 005; do sed "s/PICORV32_TESTBUG_NONE/PICORV32_TESTBUG_${bug}/" < checks.cfg > testbug${bug}.cfg echo "checks::" >> testbugs.mk echo " \$(MAKE) -C testbug${bug}" >> testbugs.mk if [ ! -d testbug${bug} ]; then python3 ../../checks/genchecks.py testbug${bug} fi done ================================================ FILE: cores/picorv32/wrapper.sv ================================================ module rvfi_wrapper ( input clock, input reset, `RVFI_OUTPUTS ); (* keep *) wire trap; (* keep *) `rvformal_rand_reg mem_ready; (* keep *) `rvformal_rand_reg [31:0] mem_rdata; (* keep *) wire mem_valid; (* keep *) wire mem_instr; (* keep *) wire [31:0] mem_addr; (* keep *) wire [31:0] mem_wdata; (* keep *) wire [3:0] mem_wstrb; picorv32 #( .COMPRESSED_ISA(1), .ENABLE_FAST_MUL(1), .ENABLE_DIV(1), .BARREL_SHIFTER(1) ) uut ( .clk (clock ), .resetn (!reset ), .trap (trap ), .mem_valid (mem_valid), .mem_instr (mem_instr), .mem_ready (mem_ready), .mem_addr (mem_addr ), .mem_wdata (mem_wdata), .mem_wstrb (mem_wstrb), .mem_rdata (mem_rdata), `RVFI_CONN ); `ifdef PICORV32_FAIRNESS reg [2:0] mem_wait = 0; always @(posedge clock) begin mem_wait <= {mem_wait, mem_valid && !mem_ready}; assume (~mem_wait || trap); end `endif `ifdef PICORV32_CSR_RESTRICT always @* begin if (rvfi_valid && rvfi_insn[6:0] == 7'b1110011) begin if (rvfi_insn[14:12] == 3'b010) begin assume (rvfi_insn[31:20] == 12'hC00 || rvfi_insn[31:20] == 12'hC01 || rvfi_insn[31:20] == 12'hC02 || rvfi_insn[31:20] == 12'hC80 || rvfi_insn[31:20] == 12'hC81 || rvfi_insn[31:20] == 12'hC82); assume (rvfi_insn[19:15] == 0); end assume (rvfi_insn[14:12] != 3'b001); assume (rvfi_insn[14:12] != 3'b011); assume (rvfi_insn[14:12] != 3'b101); assume (rvfi_insn[14:12] != 3'b110); assume (rvfi_insn[14:12] != 3'b111); end end `endif endmodule ================================================ FILE: cores/rocket/.gitignore ================================================ /riscv-tools /riscv-tools-build /rocket-chip /rocket-syn /cover /coverage /checks /checks.cfg /testbench /testbench.v /testbench.vcd /obj_dir /disasm.s /disasm.o /cexdata-[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9] /cexdata-[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9].zip /muldivlen_cover /muldivlen_check ================================================ FILE: cores/rocket/README.md ================================================ riscv-formal proofs for rocket-chip =================================== Quickstart guide: First install Yosys, SymbiYosys, and the solvers. See [here](http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing) for instructions. Then build the version of rocket-chip with RVFI support and rsicv-tools, and generate the formal checks: ``` sudo apt-get install autoconf automake autotools-dev curl \ device-tree-compiler libmpc-dev libmpfr-dev \ libgmp-dev gawk build-essential bison flex \ texinfo gperf libtool patchutils bc zlib1g-dev \ libusb-1.0-0-dev openjdk-8-jdk-headless bash generate.sh ``` Then run the formal checks: ``` make -C checks -j$(nproc) ``` Or if you just want to simulate Rocket with RVFIMonitor: ``` export CONFIG=DefaultConfigWithRVFIMonitors export RISCV=$PWD/riscv-tools cd rocket-chip/emulator make -j$(nproc) make run ``` Important Notes =============== This check sets all dangling wires in the design to constant zero. Without this there would be a problem with propagating Xs and the checks would fail. Obviously this is a problem that needs to be addressed in the design, but for now we work around it here so we can continue writing checks. ================================================ FILE: cores/rocket/cexdata.sh ================================================ #!/bin/bash set -ex cexdata="cexdata-$(date '+%Y%m%d')" rm -rf $cexdata mkdir $cexdata while read dir; do echo "$dir $(git -C $dir log -n1 --oneline)"; \ done < <( echo .; find rocket-chip -name '.git' -printf '%h\n'; ) | \ expand -t30 > $cexdata/version.txt cp rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v $cexdata/rocketchip.v cp rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.fir $cexdata/rocketchip.fir gzip $cexdata/rocketchip.v $cexdata/rocketchip.fir cp rocket-chip/src/main/scala/system/Configs.scala $cexdata/Configs.scala git -C rocket-chip diff src/main/scala/system/Configs.scala > $cexdata/Configs.scala.diff vcd2fst rocket-syn/init.vcd $cexdata/init.fst for x in checks/*/{FAIL,ERROR} coverage/{FAIL,ERROR}; do test -f $x || continue x=${x%/FAIL} x=${x%/ERROR} y=${x#checks/} cp $x/logfile.txt $cexdata/$y.log if test -f $x/engine_*/trace.vcd; then cp $x/engine_*/trace.vcd $cexdata/$y.vcd if grep -q "^isa rv64" checks.cfg; then python3 disasm.py --64 $cexdata/$y.vcd > $cexdata/$y.asm fi if grep -q "^isa rv32" checks.cfg; then python3 disasm.py $cexdata/$y.vcd > $cexdata/$y.asm fi vcd2fst $cexdata/$y.vcd $cexdata/$y.fst rm -f $cexdata/$y.vcd fi done for x in checks/*.sby; do x=${x%.sby} x=${x#checks/} if [ -f checks/$x/PASS ]; then printf "%-20s %s %10s\n" $x pass $(sed '/Elapsed process time/ { s/.*\]: //; s/ .*//; p; }; d;' checks/$x/logfile.txt) elif [ -f checks/$x/FAIL ]; then printf "%-20s %s %10s\n" $x FAIL $(sed '/Elapsed process time/ { s/.*\]: //; s/ .*//; p; }; d;' checks/$x/logfile.txt) elif [ -f checks/$x/ERROR ]; then printf "%-20s %s\n" $x ERROR else printf "%-20s %s\n" $x unknown fi done | awk '{ print gensub(":", "", "g", $3), $0; }' | sort -n | cut -f2- -d' ' > $cexdata/status.txt rm -f $cexdata.zip zip -r $cexdata.zip $cexdata/ ================================================ FILE: cores/rocket/checks.gtkw ================================================ [*] [*] GTKWave Analyzer v3.3.65 (w)1999-2015 BSI [*] Tue Sep 12 08:17:07 2017 [*] [dumpfile] "/home/claire/Work/riscv-formal/cores/rocket/checks/pc_fwd_ch0/engine_0/trace.vcd" [dumpfile_mtime] "Tue Sep 12 00:05:15 2017" [dumpfile_size] 4236356 [savefile] "/home/claire/Work/riscv-formal/cores/rocket/checks.gtkw" [timestart] 218 [size] 1024 1256 [pos] 999 -429 *-6.374269 285 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] rvfi_testbench. [treeopen] rvfi_testbench.wrapper. [sst_width] 225 [signals_width] 269 [sst_expanded] 1 [sst_vpaned_height] 391 @24 smt_step @28 rvfi_testbench.checker_inst.reset rvfi_testbench.checker_inst.check @200 - @22 rvfi_testbench.checker_inst.insn_order[63:0] rvfi_testbench.checker_inst.expect_pc[31:0] @29 rvfi_testbench.checker_inst.expect_pc_valid @200 - -RVFI #0 @28 rvfi_testbench.wrapper.rvfi_channel_0.valid rvfi_testbench.wrapper.rvfi_channel_0.trap rvfi_testbench.wrapper.rvfi_channel_0.intr @24 rvfi_testbench.wrapper.rvfi_channel_0.order[63:0] @22 rvfi_testbench.wrapper.rvfi_channel_0.insn[31:0] rvfi_testbench.wrapper.rvfi_channel_0.pc_rdata[31:0] rvfi_testbench.wrapper.rvfi_channel_0.pc_wdata[31:0] @200 - -RVFI #1 @28 rvfi_testbench.wrapper.rvfi_channel_1.valid rvfi_testbench.wrapper.rvfi_channel_1.trap rvfi_testbench.wrapper.rvfi_channel_1.intr @24 rvfi_testbench.wrapper.rvfi_channel_1.order[63:0] @22 rvfi_testbench.wrapper.rvfi_channel_1.insn[31:0] rvfi_testbench.wrapper.rvfi_channel_1.pc_rdata[31:0] rvfi_testbench.wrapper.rvfi_channel_1.pc_wdata[31:0] [pattern_trace] 1 [pattern_trace] 0 ================================================ FILE: cores/rocket/cover.gtkw ================================================ [*] [*] GTKWave Analyzer v3.3.89 (w)1999-2018 BSI [*] Wed Mar 28 21:36:23 2018 [*] [dumpfile] "/home/claire/Work/riscv-formal/cores/rocket/cover/engine_0/trace8.vcd" [dumpfile_mtime] "Wed Mar 28 21:28:42 2018" [dumpfile_size] 3363780 [savefile] "/home/claire/Work/riscv-formal/cores/rocket/cover.gtkw" [timestart] 0 [size] 1400 947 [pos] 471 0 *-6.307628 100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] testbench. [treeopen] testbench.uut. [sst_width] 225 [signals_width] 362 [sst_expanded] 1 [sst_vpaned_height] 277 @28 testbench.clk @200 - @28 testbench.rvfi_valid_ch0 @22 testbench.rvfi_insn_ch0[31:0] testbench.rvfi_pc_rdata_ch0[63:0] testbench.rvfi_mem_addr_ch0[63:0] @200 - @28 testbench.rvfi_valid_ch1 @22 testbench.rvfi_insn_ch1[31:0] testbench.rvfi_pc_rdata_ch1[63:0] testbench.rvfi_mem_addr_ch1[63:0] @200 - @29 testbench.p0o0 @28 testbench.p0o1 testbench.p0o2 testbench.p0o3m0 testbench.p0o3m1 testbench.p0o4m0 testbench.p0o4m1 testbench.p1o0 testbench.p1o1 testbench.p1o2 testbench.p1o3m0 testbench.p1o3m1 testbench.p1o4m0 testbench.p1o4m1 @200 - @28 testbench.uut.tilelink_slave.channel_a_valid testbench.uut.tilelink_slave.channel_a_ready @22 testbench.uut.tilelink_slave.channel_a_bits_size[3:0] testbench.uut.tilelink_slave.channel_a_bits_address[31:0] @200 - @28 testbench.uut.tilelink_slave.channel_d_valid testbench.uut.tilelink_slave.channel_d_ready @22 testbench.uut.tilelink_slave.channel_d_bits_data[63:0] [pattern_trace] 1 [pattern_trace] 0 ================================================ FILE: cores/rocket/cover.sby ================================================ [options] mode cover tbtop uut.rocket depth 55 [engines] smtbmc boolector [script] verilog_defines -D RISCV_FORMAL verilog_defines -D RISCV_FORMAL_NRET=2 verilog_defines -D RISCV_FORMAL_XLEN=64 verilog_defines -D RISCV_FORMAL_ILEN=32 verilog_defines -D RISCV_FORMAL_COMPRESSED verilog_defines -D RISCV_FORMAL_FAIRNESS verilog_defines -D RISCV_FORMAL_CSR_MCYCLE verilog_defines -D RISCV_FORMAL_CSR_MISA verilog_defines -D ROCKET_NORESET read_verilog -sv rvfi_macros.vh read_verilog -sv rvfi_channel.sv read_verilog -sv wrapper.sv read_verilog -sv cover.sv read_ilang rocket-hier.il prep -flatten -top testbench [files] cover.sv wrapper.sv rocket-syn/rocket-hier.il ../../checks/rvfi_macros.vh ../../checks/rvfi_channel.sv ================================================ FILE: cores/rocket/cover.sv ================================================ module testbench ( input clk, reset ); `RVFI_WIRES `RVFI_CHANNEL(rvfi_ch0, 0) `RVFI_CHANNEL(rvfi_ch1, 1) `ifdef YOSYS assume property (reset == $initstate); `endif rvfi_wrapper uut ( .clock (clk ), .reset (reset), `RVFI_CONN ); localparam [31:0] opcode0 = 32'h00051663; // bnez a0,18 localparam [31:0] opcode1 = 32'h00310093; // addi ra,sp,3 localparam [31:0] opcode2 = 32'h005201b3; // add gp,tp,t0 localparam [31:0] opcode3 = 32'h0003a303; // lw t1,0(t2) localparam [31:0] opcode4 = 32'h0084a023; // sw s0,0(s1) reg p0o0 = 0, p1o0 = 0; reg p0o1 = 0, p1o1 = 0; reg p0o2 = 0, p1o2 = 0; reg p0o3m0 = 0, p0o3m1 = 0, p1o3m0 = 0, p1o3m1 = 0; reg p0o4m0 = 0, p0o4m1 = 0, p1o4m0 = 0, p1o4m1 = 0; wire [3:0] icount_p0 = p0o0 + p1o0 + p0o1; wire [3:0] icount_p1 = p1o1 + p0o2 + p1o2; wire [3:0] mcount_p0 = p0o3m0 + p0o3m1 + p0o4m0 + p0o4m1; wire [3:0] mcount_p1 = p1o3m0 + p1o3m1 + p1o4m0 + p1o4m1; wire [3:0] tcount = |icount_p0 + |icount_p1 + |mcount_p0 + |mcount_p1; wire o0 = p0o0 || p1o0; wire o1 = p0o1 || p1o1; wire o2 = p0o2 || p1o2; wire o3 = p0o3m0 || p0o3m1 || p1o3m0 || p1o3m1; wire o4 = p0o4m0 || p0o4m1 || p1o4m0 || p1o4m1; wire is_p0_ch0 = (rvfi_ch0.pc_rdata & 32'hffff0000) == 32'h00010000; wire is_p1_ch0 = (rvfi_ch0.pc_rdata & 32'hffff0000) == 32'h00020000; wire is_m0_ch0 = (rvfi_ch0.mem_addr & 32'hffff0000) == 32'h00010000; wire is_m1_ch0 = (rvfi_ch0.mem_addr & 32'hffff0000) == 32'h00020000; wire is_p0_ch1 = (rvfi_ch1.pc_rdata & 32'hffff0000) == 32'h00010000; wire is_p1_ch1 = (rvfi_ch1.pc_rdata & 32'hffff0000) == 32'h00020000; wire is_m0_ch1 = (rvfi_ch1.mem_addr & 32'hffff0000) == 32'h00010000; wire is_m1_ch1 = (rvfi_ch1.mem_addr & 32'hffff0000) == 32'h00020000; always @(posedge clk) begin if (!reset) begin if (rvfi_ch0.valid) begin if (rvfi_ch0.insn == opcode0) begin if (is_p0_ch0) p0o0 <= 1; if (is_p1_ch0) p1o0 <= 1; end if (rvfi_ch0.insn == opcode1) begin if (is_p0_ch0) p0o1 <= 1; if (is_p1_ch0) p1o1 <= 1; end if (rvfi_ch0.insn == opcode2) begin if (is_p0_ch0) p0o2 <= 1; if (is_p1_ch0) p1o2 <= 1; end if (rvfi_ch0.insn == opcode3) begin if (is_p0_ch0 && is_m0_ch0) p0o3m0 <= 1; if (is_p0_ch0 && is_m1_ch0) p0o3m1 <= 1; if (is_p1_ch0 && is_m0_ch0) p1o3m0 <= 1; if (is_p1_ch0 && is_m1_ch0) p1o3m1 <= 1; end if (rvfi_ch0.insn == opcode4) begin if (is_p0_ch0 && is_m0_ch0) p0o4m0 <= 1; if (is_p0_ch0 && is_m1_ch0) p0o4m1 <= 1; if (is_p1_ch0 && is_m0_ch0) p1o4m0 <= 1; if (is_p1_ch0 && is_m1_ch0) p1o4m1 <= 1; end end if (rvfi_ch1.valid) begin if (rvfi_ch1.insn == opcode0) begin if (is_p0_ch1) p0o0 <= 1; if (is_p1_ch1) p1o0 <= 1; end if (rvfi_ch1.insn == opcode1) begin if (is_p0_ch1) p0o1 <= 1; if (is_p1_ch1) p1o1 <= 1; end if (rvfi_ch1.insn == opcode2) begin if (is_p0_ch1) p0o2 <= 1; if (is_p1_ch1) p1o2 <= 1; end if (rvfi_ch1.insn == opcode3) begin if (is_p0_ch1 && is_m0_ch1) p0o3m0 <= 1; if (is_p0_ch1 && is_m1_ch1) p0o3m1 <= 1; if (is_p1_ch1 && is_m0_ch1) p1o3m0 <= 1; if (is_p1_ch1 && is_m1_ch1) p1o3m1 <= 1; end if (rvfi_ch1.insn == opcode4) begin if (is_p0_ch1 && is_m0_ch1) p0o4m0 <= 1; if (is_p0_ch1 && is_m1_ch1) p0o4m1 <= 1; if (is_p1_ch1 && is_m0_ch1) p1o4m0 <= 1; if (is_p1_ch1 && is_m1_ch1) p1o4m1 <= 1; end end end end always @* begin cover (icount_p0 == 1); cover (icount_p0 == 2); cover (icount_p0 == 3); cover (icount_p1 == 1); cover (icount_p1 == 2); cover (icount_p1 == 3); cover (mcount_p0 == 1); cover (mcount_p0 == 2); cover (mcount_p0 == 3); cover (mcount_p0 == 4); cover (mcount_p1 == 1); cover (mcount_p1 == 2); cover (mcount_p1 == 3); cover (mcount_p1 == 4); cover (tcount == 2); cover (tcount == 3); cover (tcount == 4); end endmodule ================================================ FILE: cores/rocket/coverage.sby ================================================ [options] mode bmc tbtop uut.rocket depth 20 append 2 [engines] smtbmc boolector [script] verilog_defines -D RISCV_FORMAL verilog_defines -D RISCV_FORMAL_NRET=2 verilog_defines -D RISCV_FORMAL_XLEN=64 verilog_defines -D RISCV_FORMAL_ILEN=32 verilog_defines -D RISCV_FORMAL_COMPRESSED verilog_defines -D RISCV_FORMAL_FAIRNESS verilog_defines -D RISCV_FORMAL_CSR_MCYCLE verilog_defines -D ROCKET_NORESET read_verilog -sv rvfi_macros.vh read_verilog -sv rvfi_channel.sv read_verilog -sv riscv_rv64ic_insn.v read_verilog -sv wrapper.sv read_verilog -sv coverage.sv read_ilang rocket-hier.il prep -flatten -top testbench [files] coverage.sv wrapper.sv rocket-syn/rocket-hier.il ../../checks/rvfi_macros.vh ../../checks/rvfi_channel.sv ../../tests/coverage/riscv_rv64ic_insn.v ================================================ FILE: cores/rocket/coverage.sv ================================================ module testbench ( input clk, reset ); `RVFI_WIRES `RVFI_CHANNEL(rvfi_ch0, 0) `RVFI_CHANNEL(rvfi_ch1, 1) `ifdef YOSYS assume property (reset == $initstate); `endif rvfi_wrapper uut ( .clock (clk ), .reset (reset), `RVFI_CONN ); wire valid_ch0; wire valid_ch1; riscv_rv64ic_insn riscv_rv64ic_insn_ch0 ( .insn(rvfi_insn_ch0), .valid(valid_ch0) ); riscv_rv64ic_insn riscv_rv64ic_insn_ch1 ( .insn(rvfi_insn_ch1), .valid(valid_ch1) ); function [0:0] check_insn; input [31:0] insn; begin check_insn = 0; casez (insn) 32'b 0000000000000000_010_?00000?????_10:; // C.LWSP (fix pending) 32'b 0000000000000000_011_?00000?????_10:; // C.LDSP (fix pending) 32'b ???????_?????_?????_???_?????_1110011:; // SYSTEM 32'b ???????_?????_?????_000_?????_0001111:; // FENCE 32'b ???????_?????_?????_001_?????_0001111:; // FENCE.I 32'b 00010??_00000_?????_???_?????_0101111:; // LR.W 32'b 00011??_?????_?????_???_?????_0101111:; // SC.W 32'b 00001??_?????_?????_???_?????_0101111:; // AMOSWAP.W 32'b 00000??_?????_?????_???_?????_0101111:; // AMOADD.W 32'b 00100??_?????_?????_???_?????_0101111:; // AMOXOR.W 32'b 01100??_?????_?????_???_?????_0101111:; // AMOAND.W 32'b 01000??_?????_?????_???_?????_0101111:; // AMOOR.W 32'b 10000??_?????_?????_???_?????_0101111:; // AMOMIN.W 32'b 10100??_?????_?????_???_?????_0101111:; // AMOMAX.W 32'b 11000??_?????_?????_???_?????_0101111:; // AMOMINU.W 32'b 11100??_?????_?????_???_?????_0101111:; // AMOMAXU.W default: check_insn = 1; endcase end endfunction wire check_insn_ch0 = check_insn(rvfi_insn_ch0); wire check_insn_ch1 = check_insn(rvfi_insn_ch1); always @* begin if (!reset && rvfi_valid_ch0 && check_insn_ch0 && !rvfi_trap_ch0) begin assert (valid_ch0); end if (!reset && rvfi_valid_ch1 && check_insn_ch1 && !rvfi_trap_ch1) begin assert (valid_ch1); end end endmodule ================================================ FILE: cores/rocket/decode.sh ================================================ #!/bin/bash riscv=riscv32 case "$1" in -a) mopt="-M numeric"; shift;; -n) mopt="-M no-aliases"; shift;; -an) mopt=""; shift;; -64) riscv=riscv64; shift;; *) mopt="-M numeric,no-aliases" esac for w; do echo ".word 0x${w#0x}"; done > decode.s ${riscv}-unknown-elf-gcc -c decode.s ${riscv}-unknown-elf-objdump -d $mopt decode.o | grep -A999 ^000 rm -f decode.s decode.o ================================================ FILE: cores/rocket/disasm.py ================================================ #!/usr/bin/env python3 from Verilog_VCD.Verilog_VCD import parse_vcd from os import system from sys import argv, exit from getopt import getopt mode_d = False mode_64 = False def usage(): print("Usage: %s [-d] [--64] " % argv[0]) exit(1) try: opts, args = getopt(argv[1:], "d", ["64"]) except: usage() for o, a in opts: if o == "-d": mode_d = True elif o == "--64": mode_64 = True else: usage() if len(args) != 1: usage() if mode_d: tilelink_d_valid = None tilelink_d_ready = None tilelink_d_data = None for netinfo in parse_vcd(args[0]).values(): for net in netinfo['nets']: print(net["hier"], net["name"]) if net["hier"] in ["rvfi_testbench.wrapper", "testbench.uut"] and net["name"] == "io_master_0_d_valid": tilelink_d_valid = netinfo['tv'] if net["hier"] in ["rvfi_testbench.wrapper", "testbench.uut"] and net["name"] == "io_master_0_d_ready": tilelink_d_ready = netinfo['tv'] if net["hier"] in ["rvfi_testbench.wrapper", "testbench.uut"] and net["name"] == "io_master_0_d_bits_data": tilelink_d_data = netinfo['tv'] assert len(tilelink_d_valid) == len(tilelink_d_ready) assert len(tilelink_d_valid) == len(tilelink_d_data) with open("disasm.s", "w") as f: for tv_valid, tv_ready, tv_data in zip(tilelink_d_valid, tilelink_d_ready, tilelink_d_data): if int(tv_valid[1], 2) and int(tv_ready[1], 2): print(".word 0x%04x" % int(tv_data[1], 2), file=f) else: rvfi_valid_0 = None rvfi_valid_1 = None rvfi_order_0 = None rvfi_order_1 = None rvfi_insn_0 = None rvfi_insn_1 = None for netinfo in parse_vcd(args[0]).values(): for net in netinfo['nets']: # print(net["hier"], net["name"]) if net["hier"] in ["rvfi_testbench.wrapper.rvfi_channel_0", "testbench.uut.rvfi_channel_0"] and net["name"] == "valid": rvfi_valid_0 = netinfo['tv'] if net["hier"] in ["rvfi_testbench.wrapper.rvfi_channel_0", "testbench.uut.rvfi_channel_0"] and net["name"] == "order": rvfi_order_0 = netinfo['tv'] if net["hier"] in ["rvfi_testbench.wrapper.rvfi_channel_0", "testbench.uut.rvfi_channel_0"] and net["name"] == "insn": rvfi_insn_0 = netinfo['tv'] if net["hier"] in ["rvfi_testbench.wrapper.rvfi_channel_1", "testbench.uut.rvfi_channel_1"] and net["name"] == "valid": rvfi_valid_1 = netinfo['tv'] if net["hier"] in ["rvfi_testbench.wrapper.rvfi_channel_1", "testbench.uut.rvfi_channel_1"] and net["name"] == "order": rvfi_order_1 = netinfo['tv'] if net["hier"] in ["rvfi_testbench.wrapper.rvfi_channel_1", "testbench.uut.rvfi_channel_1"] and net["name"] == "insn": rvfi_insn_1 = netinfo['tv'] assert len(rvfi_valid_0) == len(rvfi_order_0) assert len(rvfi_valid_1) == len(rvfi_order_1) assert len(rvfi_valid_0) == len(rvfi_insn_0) assert len(rvfi_valid_1) == len(rvfi_insn_1) prog = list() for tv_valid, tv_order, tv_insn in zip(rvfi_valid_0, rvfi_order_0, rvfi_insn_0): if tv_valid[1] == '1': prog.append((int(tv_order[1], 2), int(tv_insn[1], 2))) for tv_valid, tv_order, tv_insn in zip(rvfi_valid_1, rvfi_order_1, rvfi_insn_1): if tv_valid[1] == '1': prog.append((int(tv_order[1], 2), int(tv_insn[1], 2))) with open("disasm.s", "w") as f: for tv_order, tv_insn in sorted(prog): if tv_insn & 3 != 3 and tv_insn & 0xffff0000 == 0: print(".hword 0x%04x # %d" % (tv_insn, tv_order), file=f) else: print(".word 0x%08x # %d" % (tv_insn, tv_order), file=f) if mode_64: system("riscv-tools/bin/riscv64-unknown-elf-gcc -c disasm.s") system("riscv-tools/bin/riscv64-unknown-elf-objdump -d -M numeric,no-aliases disasm.o") else: system("riscv-tools/bin/riscv32-unknown-elf-gcc -c disasm.s") system("riscv-tools/bin/riscv32-unknown-elf-objdump -d -M numeric,no-aliases disasm.o") ================================================ FILE: cores/rocket/generate.sh ================================================ #!/bin/sh set -ex export CONFIG=DefaultConfigWithRVFIMonitors export MAKEFLAGS="-j$(nproc)" export RISCV=$PWD/riscv-tools enable_compressed=true enable_inithack=true enable_64bits=true enable_muldiv=true enable_misa=true enable_pmp=false if [ ! -d rocket-chip ]; then git clone --recurse-submodules git@github.com:sifive/rocket-chip-grand-central.git rocket-chip cd rocket-chip # git checkout bc22847 # git submodule update --recursive if $enable_compressed; then ( cd ../../../monitor && python3 generate.py -i rv$(if $enable_64bits; then echo 64; else echo 32; fi)ic -p RVFIMonitor -c 2; ) > src/main/resources/vsrc/RVFIMonitor.v else sed -i -e '/DefaultConfigWithRVFIMonitors/,/^)/ { /new WithRVFIMonitors/ s/$/\n new WithoutCompressed ++/; };' src/main/scala/system/Configs.scala ( cd ../../../monitor && python3 generate.py -i rv$(if $enable_64bits; then echo 64; else echo 32; fi)i -p RVFIMonitor -c 2; ) > src/main/resources/vsrc/RVFIMonitor.v fi if $enable_misa; then sed -i -e '/DefaultConfigWithRVFIMonitors/,/^)/ { /new WithoutMISAWrite/ d; };' src/main/scala/system/Configs.scala fi if $enable_muldiv; then sed -i -e '/DefaultConfigWithRVFIMonitors/,/^)/ { /new WithoutMulDiv/ d; };' src/main/scala/system/Configs.scala fi if $enable_64bits; then sed -i -e '/DefaultConfigWithRVFIMonitors/,/^)/ { /freechips.rocketchip.tile.XLen/ s,32,64,; }' src/main/scala/system/Configs.scala else sed -i -e '/DefaultConfigWithRVFIMonitors/,/^)/ { /freechips.rocketchip.tile.XLen/ s,64,32,; }' src/main/scala/system/Configs.scala fi if ! $enable_pmp; then sed -i -e '/DefaultConfigWithRVFIMonitors/,/^)/ { /new WithNPMP/ s/[0-9]\+/0/; };' src/main/scala/system/Configs.scala fi sed -i 's/--top-module/-Wno-fatal &/' emulator/Makefrag-verilator cd .. fi if [ ! -d riscv-tools ]; then mkdir riscv-tools rm -rf riscv-tools-build git clone https://github.com/riscv/riscv-tools riscv-tools-build cd riscv-tools-build git checkout $(cat ../rocket-chip/riscv-tools.hash) git submodule update --init --recursive # sed -i 's/rv32ima/rv32i/g' build-rv32ima.sh ./build.sh ./build-rv32ima.sh cd .. fi make -C rocket-chip/vsim verilog rm -rf rocket-syn mkdir -p rocket-syn cat > rocket-syn/rocket-syn.ys << EOT verific -sv rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v verific -sv rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.behav_srams.v verific -sv rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors/plusarg_reader.v verific -sv rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors/AsyncResetReg.v verific -sv rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors/SimDTM.v verific -vlog-define RISCV_FORMAL verific -vlog-define RISCV_FORMAL_NRET=2 verific -vlog-define RISCV_FORMAL_XLEN=$(if $enable_64bits; then echo 64; else echo 32; fi) verific -vlog-define RISCV_FORMAL_ILEN=32 verific -vlog-define RISCV_FORMAL_UMODE verific -vlog-define RISCV_FORMAL_EXTAMO verific -vlog-define RISCV_FORMAL_CSR_MCYCLE verific -vlog-define RISCV_FORMAL_CSR_MINSTRET verific -vlog-define RISCV_FORMAL_CSR_MISA verific -vlog-define ROCKET_INIT $(if $enable_inithack; then echo "verific -vlog-define ROCKET_INITHACK"; fi) verific -sv ../../checks/rvfi_macros.vh ../../checks/rvfi_channel.sv wrapper.sv rocketrvfi.sv verific -import -extnets rvfi_wrapper # ---- Simulate init sequence ---- hierarchy -top rvfi_wrapper prep -nordff uniquify hierarchy setundef -undriven -zero w:* opt -fast write_ilang rocket-syn/init.il sim -clock clock -reset reset -rstlen 10 -zinit -w -vcd rocket-syn/init.vcd -n 300 # ---- Generate netlists ---- rename rvfi_wrapper.rocket_rvfi_tile RocketTileWithRVFI hierarchy -top RocketTileWithRVFI uniquify chtype -set MulDiv RocketTileWithRVFI.rocket_tile.core/div hierarchy # rename -hide w:_* $(if ! $enable_inithack; then echo "# "; fi)setparam -set INIT 16384'bx RocketTileWithRVFI.rocket_tile.frontend.icache.data_arrays_*/ram write_ilang rocket-syn/rocket-hier.il EOT yosys -v2 -l rocket-syn/rocket-syn.log rocket-syn/rocket-syn.ys cat > checks.cfg <trace(tfp, 99); tfp->open("testbench.vcd"); tb->clock = 0; tb->eval(); tfp->dump(timer++); while (tb->genclock) { if (timer > 1) tb->clock = ~tb->clock; tb->eval(); tfp->dump(timer++); } tfp->close(); delete tfp; delete tb; return 0; } ================================================ FILE: cores/rocket/testbench.sh ================================================ #!/bin/bash set -ex use_iverilog=false tracetb=insncheck/insn_sw_ch0/engine_0/trace_tb.v egrep -v 'UUT.(core.rvfi_|core.io_status_dprv|core.csr.io_time|core.csr.io_status_dprv|frontend.icache.io_resp_bits)' $tracetb > testbench.v if $use_iverilog; then iverilog -o testbench -s testbench -DSIMULATION -DRANDOMIZE_REG_INIT -DRANDOMIZE_MEM_INIT testbench.v \ rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v \ rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.behav_srams.v \ rocket-chip/vsrc/plusarg_reader.v rocket-chip/vsrc/RVFIMonitor.v ./testbench +vcd=testbench.vcd else verilator --exe --cc -Wno-fatal --top-module testbench --trace --trace-underscore -DSIMULATION testbench.v testbench.cc \ rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v \ rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.behav_srams.v \ rocket-chip/vsrc/plusarg_reader.v rocket-chip/vsrc/RVFIMonitor.v make -C obj_dir -f Vtestbench.mk ./obj_dir/Vtestbench fi ================================================ FILE: cores/rocket/wrapper.sv ================================================ `define XLEN_BYTES (`RISCV_FORMAL_XLEN == 32 ? 4 : 8) module rvfi_wrapper ( input clock, input reset, `RVFI_OUTPUTS ); `ifdef ROCKET_NORESET wire actual_reset = 0; `else reg [3:0] reset_cnt = 0; wire actual_reset = reset || |reset_cnt; always @(posedge clock) begin reset_cnt <= reset ? 4'd 5 : reset_cnt - |reset_cnt; end `endif (* keep *) wire [31:0] reset_vector = 32'h10040; // Rocket TileLink Slave (* keep *) wire tl_slave_a_ready; (* keep *) wire tl_slave_a_valid = 0; (* keep *) wire [2:0] tl_slave_a_bits_opcode = 0; (* keep *) wire [2:0] tl_slave_a_bits_param = 0; (* keep *) wire [2:0] tl_slave_a_bits_size = 0; (* keep *) wire [4:0] tl_slave_a_bits_source = 0; (* keep *) wire [31:0] tl_slave_a_bits_address = 0; (* keep *) wire [7:0] tl_slave_a_bits_mask = 0; (* keep *) wire [63:0] tl_slave_a_bits_data = 0; (* keep *) wire tl_slave_d_ready = 0; (* keep *) wire tl_slave_d_valid; (* keep *) wire [2:0] tl_slave_d_bits_opcode; (* keep *) wire [1:0] tl_slave_d_bits_param; (* keep *) wire [2:0] tl_slave_d_bits_size; (* keep *) wire [4:0] tl_slave_d_bits_source; (* keep *) wire tl_slave_d_bits_sink; (* keep *) wire tl_slave_d_bits_denied; (* keep *) wire [63:0] tl_slave_d_bits_data; (* keep *) wire tl_slave_d_bits_corrupt; // Rocket TileLink Master (* keep *) wire tl_master_a_ready; (* keep *) wire tl_master_a_valid; (* keep *) wire [2:0] tl_master_a_bits_opcode; (* keep *) wire [2:0] tl_master_a_bits_param; (* keep *) wire [3:0] tl_master_a_bits_size; (* keep *) wire tl_master_a_bits_source; (* keep *) wire [31:0] tl_master_a_bits_address; (* keep *) wire [7:0] tl_master_a_bits_mask; (* keep *) wire [63:0] tl_master_a_bits_data; (* keep *) wire tl_master_a_bits_corrupt; (* keep *) wire tl_master_d_ready; (* keep *) wire tl_master_d_valid; (* keep *) wire [2:0] tl_master_d_bits_opcode; (* keep *) wire [1:0] tl_master_d_bits_param; (* keep *) wire [3:0] tl_master_d_bits_size; (* keep *) wire tl_master_d_bits_source; (* keep *) wire tl_master_d_bits_sink; (* keep *) wire tl_master_d_bits_denied; (* keep *) wire [63:0] tl_master_d_bits_data; (* keep *) wire tl_master_d_bits_corrupt; // TileLink Master A-D Dummy Slave tilelink_ad_dummy tilelink_slave ( .clock (clock ), .reset (actual_reset ), .channel_a_ready (tl_master_a_ready ), .channel_a_valid (tl_master_a_valid ), .channel_a_bits_address (tl_master_a_bits_address), .channel_a_bits_data (tl_master_a_bits_data ), .channel_a_bits_mask (tl_master_a_bits_mask ), .channel_a_bits_opcode (tl_master_a_bits_opcode ), .channel_a_bits_param (tl_master_a_bits_param ), .channel_a_bits_size (tl_master_a_bits_size ), .channel_a_bits_source (tl_master_a_bits_source ), .channel_d_ready (tl_master_d_ready ), .channel_d_valid (tl_master_d_valid ), .channel_d_bits_data (tl_master_d_bits_data ), .channel_d_bits_denied (tl_master_d_bits_denied ), .channel_d_bits_corrupt (tl_master_d_bits_corrupt), .channel_d_bits_opcode (tl_master_d_bits_opcode ), .channel_d_bits_param (tl_master_d_bits_param ), .channel_d_bits_sink (tl_master_d_bits_sink ), .channel_d_bits_size (tl_master_d_bits_size ), .channel_d_bits_source (tl_master_d_bits_source ) ); // Rocket Tile RocketTileWithRVFI rocket_rvfi_tile ( .clock (clock ), .reset (actual_reset ), `RVFI_CONN, .intsink_sync_0 (1'b0 ), .int_1_sync_0 (1'b0 ), .int_0_sync_0 (1'b0 ), .int_0_sync_1 (1'b0 ), .tl_slave_a_ready (tl_slave_a_ready ), .tl_slave_a_valid (tl_slave_a_valid ), .tl_slave_a_bits_opcode (tl_slave_a_bits_opcode ), .tl_slave_a_bits_param (tl_slave_a_bits_param ), .tl_slave_a_bits_size (tl_slave_a_bits_size ), .tl_slave_a_bits_source (tl_slave_a_bits_source ), .tl_slave_a_bits_address (tl_slave_a_bits_address ), .tl_slave_a_bits_mask (tl_slave_a_bits_mask ), .tl_slave_a_bits_data (tl_slave_a_bits_data ), .tl_slave_d_ready (tl_slave_d_ready ), .tl_slave_d_valid (tl_slave_d_valid ), .tl_slave_d_bits_opcode (tl_slave_d_bits_opcode ), .tl_slave_d_bits_param (tl_slave_d_bits_param ), .tl_slave_d_bits_size (tl_slave_d_bits_size ), .tl_slave_d_bits_source (tl_slave_d_bits_source ), .tl_slave_d_bits_sink (tl_slave_d_bits_sink ), .tl_slave_d_bits_denied (tl_slave_d_bits_denied ), .tl_slave_d_bits_data (tl_slave_d_bits_data ), .tl_slave_d_bits_corrupt (tl_slave_d_bits_corrupt ), .tl_master_a_ready (tl_master_a_ready ), .tl_master_a_valid (tl_master_a_valid ), .tl_master_a_bits_opcode (tl_master_a_bits_opcode ), .tl_master_a_bits_param (tl_master_a_bits_param ), .tl_master_a_bits_size (tl_master_a_bits_size ), .tl_master_a_bits_source (tl_master_a_bits_source ), .tl_master_a_bits_address(tl_master_a_bits_address), .tl_master_a_bits_mask (tl_master_a_bits_mask ), .tl_master_a_bits_data (tl_master_a_bits_data ), .tl_master_a_bits_corrupt(tl_master_a_bits_corrupt), .tl_master_d_ready (tl_master_d_ready ), .tl_master_d_valid (tl_master_d_valid ), .tl_master_d_bits_opcode (tl_master_d_bits_opcode ), .tl_master_d_bits_param (tl_master_d_bits_param ), .tl_master_d_bits_size (tl_master_d_bits_size ), .tl_master_d_bits_source (tl_master_d_bits_source ), .tl_master_d_bits_sink (tl_master_d_bits_sink ), .tl_master_d_bits_denied (tl_master_d_bits_denied ), .tl_master_d_bits_data (tl_master_d_bits_data ), .tl_master_d_bits_corrupt(tl_master_d_bits_corrupt) ); (* keep *) rvfi_channel #(.CHANNEL_IDX(0)) rvfi_channel_0 (`RVFI_CONN); (* keep *) rvfi_channel #(.CHANNEL_IDX(1)) rvfi_channel_1 (`RVFI_CONN); endmodule module rocket_pma_map ( input [`RISCV_FORMAL_XLEN-1:0] address, input [1:0] log2len, output reg A, R, W, X, C ); reg [4:0] modes_first, modes_last; wire [`RISCV_FORMAL_XLEN-1:0] address_first = address; wire [`RISCV_FORMAL_XLEN-1:0] address_last = address + (1 << log2len) - 1; always @* begin // Generated Address Map // 0 - 1000 ARWX debug-controller@0 // 3000 - 4000 ARWX error-device@3000 // 10000 - 20000 R XC rom@10000 // 2000000 - 2010000 ARW clint@2000000 // c000000 - 10000000 ARW interrupt-controller@c000000 // 60000000 - 80000000 RWX mmio@60000000 // 80000000 - 80004000 ARWX dtim@80000000 modes_first = 5'b 00000; // if (64'h 00000000 <= address_first && address_first < 64'h 00001000) modes_first = 5'b 11110; if (64'h 00003000 <= address_first && address_first < 64'h 00004000) modes_first = 5'b 11110; if (64'h 00010000 <= address_first && address_first < 64'h 00020000) modes_first = 5'b 01010; if (64'h 02000000 <= address_first && address_first < 64'h 02010000) modes_first = 5'b 11100; if (64'h 0c000000 <= address_first && address_first < 64'h 10000000) modes_first = 5'b 11100; if (64'h 60000000 <= address_first && address_first < 64'h 80000000) modes_first = 5'b 01110; if (64'h 80000000 <= address_first && address_first < 64'h 80004000) modes_first = 5'b 11110; modes_last = 5'b 00000; // if (64'h 00000000 <= address_last && address_last < 64'h 00001000) modes_last = 5'b 11110; if (64'h 00003000 <= address_last && address_last < 64'h 00004000) modes_last = 5'b 11110; if (64'h 00010000 <= address_last && address_last < 64'h 00020000) modes_last = 5'b 01010; if (64'h 02000000 <= address_last && address_last < 64'h 02010000) modes_last = 5'b 11100; if (64'h 0c000000 <= address_last && address_last < 64'h 10000000) modes_last = 5'b 11100; if (64'h 60000000 <= address_last && address_last < 64'h 80000000) modes_last = 5'b 01110; if (64'h 80000000 <= address_last && address_last < 64'h 80004000) modes_last = 5'b 11110; {A, R, W, X, C} = modes_first & modes_last; if (log2len == 1 && address[0:0]) {A, R, W, C} = 0; if (log2len == 2 && address[1:0]) {A, R, W, C} = 0; if (log2len == 3 && address[2:0]) {A, R, W, C} = 0; end endmodule module tilelink_ad_dummy ( input clock, input reset, output channel_a_ready, input channel_a_valid, input [ 2:0] channel_a_bits_opcode, input [ 2:0] channel_a_bits_param, input [ 3:0] channel_a_bits_size, input channel_a_bits_source, input [ 31:0] channel_a_bits_address, input [ `XLEN_BYTES-1:0] channel_a_bits_mask, input [`RISCV_FORMAL_XLEN-1:0] channel_a_bits_data, input channel_d_ready, output channel_d_valid, output reg [ 2:0] channel_d_bits_opcode, output reg [ 1:0] channel_d_bits_param, output reg [ 3:0] channel_d_bits_size, output reg channel_d_bits_source, output reg channel_d_bits_sink, output reg [`RISCV_FORMAL_XLEN-1:0] channel_d_bits_data, output reg channel_d_bits_denied, output reg channel_d_bits_corrupt ); reg busy = 0, ready, last; reg [15:0] count, next_count; // -- TL-UL -- localparam [2:0] opcode_a_get = 4; // -> opcode_d_accessackdata localparam [2:0] opcode_a_putfulldata = 0; // -> opcode_d_accessack localparam [2:0] opcode_a_putpartialdata = 1; // -> opcode_d_accessack localparam [2:0] opcode_d_accessackdata = 1; localparam [2:0] opcode_d_accessack = 0; // -- TL-UH -- localparam [2:0] opcode_a_arithmeticdata = 2; // -> opcode_d_accessackdata localparam [2:0] opcode_a_logicaldata = 3; // -> opcode_d_accessackdata localparam [2:0] opcode_a_intent = 5; // -> opcode_d_hintack localparam [2:0] opcode_d_hintack = 2; reg [ 2:0] op_opcode; reg [ 2:0] op_param; reg [ 3:0] op_size; reg op_source; reg [`RISCV_FORMAL_XLEN-1:0] op_address; reg [ `XLEN_BYTES-1:0] op_mask; reg [`RISCV_FORMAL_XLEN-1:0] op_data; `ifdef ROCKET_INIT integer cycle = 0; always @(posedge clock) cycle <= cycle+1; `ifdef ROCKET_INITHACK wire delay_a = 0, delay_d = 0; `else wire delay_a = 1, delay_d = 1; `endif wire [ 2:0] channel_d_bits_opcode_nd = 0; wire [ 1:0] channel_d_bits_param_nd = 0; wire [ 3:0] channel_d_bits_size_nd = 0; wire channel_d_bits_source_nd = 0; wire channel_d_bits_sink_nd = 0; wire [`RISCV_FORMAL_XLEN-1:0] channel_d_bits_data_nd = op_address > 32'h 0001_0100 && cycle > 250 ? 64'h_f05ff06f_f05ff06f : 64'h_00000013_00000013; wire channel_d_bits_denied_nd = 0; wire channel_d_bits_corrupt_nd = 0; `else `rvformal_rand_reg delay_a_nd; `rvformal_rand_reg delay_d_nd; `ifdef RISCV_FORMAL_FAIRNESS wire delay_a = 0, delay_d = 0; `else wire delay_a = delay_a_nd, delay_d = delay_d_nd; `endif `rvformal_rand_reg [ 2:0] channel_d_bits_opcode_nd; `rvformal_rand_reg [ 1:0] channel_d_bits_param_nd; `rvformal_rand_reg [ 3:0] channel_d_bits_size_nd; `rvformal_rand_reg channel_d_bits_source_nd; `rvformal_rand_reg channel_d_bits_sink_nd; `rvformal_rand_reg [`RISCV_FORMAL_XLEN-1:0] channel_d_bits_data_nd; `rvformal_rand_reg channel_d_bits_denied_nd; `rvformal_rand_reg channel_d_bits_corrupt_nd; `endif assign channel_a_ready = (!busy || (last && channel_d_ready && channel_d_valid)) && !reset && !delay_a; assign channel_d_valid = ready && !reset && !delay_d; always @* begin last = 1; ready = 0; next_count = count; channel_d_bits_opcode = 0; // channel_d_bits_opcode_nd channel_d_bits_param = channel_d_bits_param_nd; channel_d_bits_size = channel_d_bits_size_nd; channel_d_bits_source = channel_d_bits_source_nd; channel_d_bits_sink = channel_d_bits_sink_nd; channel_d_bits_data = channel_d_bits_data_nd; channel_d_bits_denied = 1; // channel_d_bits_denied_nd channel_d_bits_corrupt = 1; // channel_d_bits_corrupt_nd if (busy) begin if (op_opcode == opcode_a_get) begin channel_d_bits_opcode = opcode_d_accessackdata; channel_d_bits_param = 0; channel_d_bits_size = op_size; channel_d_bits_source = op_source; channel_d_bits_denied = 0; channel_d_bits_corrupt = 0; next_count = (count + (`RISCV_FORMAL_XLEN / 8)) & 16'hffff; last = next_count >= (1 << op_size); ready = 1; end if (op_opcode == opcode_a_putfulldata) begin channel_d_bits_opcode = opcode_d_accessack; channel_d_bits_param = 0; channel_d_bits_size = op_size; channel_d_bits_source = op_source; channel_d_bits_denied = 0; channel_d_bits_corrupt = 0; last = 1; ready = 1; end // TBD: opcode_a_putpartialdata // TBD: opcode_a_arithmeticdata // TBD: opcode_a_logicaldata // TBD: opcode_a_intent end end always @(posedge clock) begin if (reset) begin busy <= 0; end else begin if (channel_d_ready && channel_d_valid) begin if (last) busy <= 0; else count <= next_count; end if (channel_a_ready && channel_a_valid) begin op_opcode <= channel_a_bits_opcode; op_param <= channel_a_bits_param; op_size <= channel_a_bits_size; op_source <= channel_a_bits_source; op_address <= channel_a_bits_address; op_mask <= channel_a_bits_mask; op_data <= channel_a_bits_data; busy <= 1; count <= 0; end end end endmodule `ifndef ROCKET_INIT module MulDiv ( input clock, input reset, output io__req_ready, input io__req_valid, input [ 3:0] io__req_bits_fn, input io__req_bits_dw, input [63:0] io__req_bits_in1, input [63:0] io__req_bits_in2, input [ 4:0] io__req_bits_tag, input io__kill, input io__resp_ready, output io__resp_valid, output [63:0] io__resp_bits_data, output [ 4:0] io__resp_bits_tag, output io_resp_valid, output io_resp_ready ); reg [63:0] internal_data; reg [ 4:0] internal_tag; reg internal_busy = 0; reg internal_done = 0; reg [63:0] result; always @* begin result = 123456789; case (io__req_bits_fn) 0: result = (io__req_bits_in1 + io__req_bits_in2) ^ 64'h 2cdf52a55876063e; // MUL 1: result = (io__req_bits_in1 + io__req_bits_in2) ^ 64'h 15d01651f6583fb7; // MULH 2: result = (io__req_bits_in1 - io__req_bits_in2) ^ 64'h ea3969edecfbe137; // MULHSU 3: result = (io__req_bits_in1 + io__req_bits_in2) ^ 64'h d13db50d949ce5e8; // MULHU 4: result = (io__req_bits_in1 - io__req_bits_in2) ^ 64'h 29bbf66f7f8529ec; // DIV 5: result = (io__req_bits_in1 - io__req_bits_in2) ^ 64'h 8c629acb10e8fd70; // DIVU 6: result = (io__req_bits_in1 - io__req_bits_in2) ^ 64'h f5b7d8538da68fa5; // REM 7: result = (io__req_bits_in1 - io__req_bits_in2) ^ 64'h bc4402413138d0e1; // REMU endcase if (!io__req_bits_dw) begin result = $signed(result << 32) >>> 32; end end `ifdef RISCV_FORMAL_FAIRNESS assign io__req_ready = !internal_busy; `else assign io__req_ready = $anyseq(1) && !internal_busy; `endif assign io__resp_valid = internal_done; assign io__resp_bits_data = internal_done ? internal_data : $anyseq(64); assign io__resp_bits_tag = internal_done ? internal_tag : $anyseq(5); assign io_resp_valid = io__resp_valid; assign io_resp_ready = io__resp_ready; always @(posedge clock) begin if (reset || io__kill) begin internal_busy <= 0; internal_done <= 0; end else begin if (io__req_ready && io__req_valid) begin internal_data <= result; internal_tag <= io__req_bits_tag; internal_busy <= 1; end `ifdef RISCV_FORMAL_FAIRNESS if (internal_busy) begin internal_done <= 1; end `else if (internal_busy && $anyseq(1)) begin internal_done <= 1; end `endif if (io__resp_ready && io__resp_valid) begin internal_busy <= 0; internal_done <= 0; end end end reg [2:0] done_cnt = 0; always @(posedge clock) begin done_cnt <= done_cnt + |{done_cnt, internal_done}; // cover(done_cnt == 7); end endmodule `endif ================================================ FILE: cores/serv/.gitignore ================================================ /checks /cover /serv-src /cexdata /cexdata.zip /disasm.s /disasm.o ================================================ FILE: cores/serv/README.md ================================================ riscv-formal proofs for SErial RiscV (SERV) =========================================== Quickstart guide: First install Yosys, SymbiYosys, and the solvers. See [here](http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing) for instructions. Then build the version of SERV with RVFI support and riscv-tools, and generate the formal checks: ``` bash generate.sh ``` Then run the formal checks: ``` make -C checks -j$(nproc) bash cexdata.sh ``` ================================================ FILE: cores/serv/cexdata.sh ================================================ #!/bin/bash set -ex rm -rf cexdata mkdir cexdata while read dir; do echo "$dir $(git -C $dir log -n1 --oneline)"; \ done < <( echo .; find serv-src -name '.git' -printf '%h\n'; ) | \ expand -t30 > cexdata/version.txt for x in checks/*/FAIL; do test -f $x || continue x=${x%/FAIL} y=${x#checks/} cp $x/logfile.txt cexdata/$y.log if test -f $x/engine_*/trace.vcd; then cp $x/engine_*/trace.vcd cexdata/$y.vcd if grep -q "^isa rv64" checks.cfg; then python3 disasm.py --64 cexdata/$y.vcd > cexdata/$y.asm fi if grep -q "^isa rv32" checks.cfg; then python3 disasm.py cexdata/$y.vcd > cexdata/$y.asm fi fi done for x in checks/*.sby; do x=${x%.sby} x=${x#checks/} if [ -f checks/$x/PASS ]; then printf "%-20s %s %10s\n" $x pass $(sed '/Elapsed process time/ { s/.*\]: //; s/ .*//; p; }; d;' checks/$x/logfile.txt) elif [ -f checks/$x/FAIL ]; then printf "%-20s %s %10s\n" $x FAIL $(sed '/Elapsed process time/ { s/.*\]: //; s/ .*//; p; }; d;' checks/$x/logfile.txt) else printf "%-20s %s\n" $x unknown fi done | awk '{ print gensub(":", "", "g", $3), $0; }' | sort -n | cut -f2- -d' ' > cexdata/status.txt rm -f cexdata.zip zip -r cexdata.zip cexdata/ ================================================ FILE: cores/serv/checks.cfg ================================================ [options] isa rv32i nret 1 [depth] insn 80 reg 1 80 pc_fwd 1 80 pc_bwd 1 80 liveness 1 40 150 unique 1 50 80 causal 1 80 [defines] `define RISCV_FORMAL_ALIGNED_MEM [defines liveness] `define MEMIO_FAIRNESS [verilog-files] @basedir@/cores/@core@/wrapper.sv @basedir@/cores/@core@/serv-src/rtl/serv_bufreg.v @basedir@/cores/@core@/serv-src/rtl/serv_bufreg2.v @basedir@/cores/@core@/serv-src/rtl/serv_alu.v @basedir@/cores/@core@/serv-src/rtl/serv_csr.v @basedir@/cores/@core@/serv-src/rtl/serv_ctrl.v @basedir@/cores/@core@/serv-src/rtl/serv_decode.v @basedir@/cores/@core@/serv-src/rtl/serv_immdec.v @basedir@/cores/@core@/serv-src/rtl/serv_mem_if.v @basedir@/cores/@core@/serv-src/rtl/serv_rf_if.v @basedir@/cores/@core@/serv-src/rtl/serv_rf_ram.v @basedir@/cores/@core@/serv-src/rtl/serv_rf_ram_if.v @basedir@/cores/@core@/serv-src/rtl/serv_state.v @basedir@/cores/@core@/serv-src/rtl/serv_top.v @basedir@/cores/@core@/serv-src/rtl/serv_rf_top.v ================================================ FILE: cores/serv/cover.gtkw ================================================ [*] [*] GTKWave Analyzer v3.3.89 (w)1999-2018 BSI [*] Thu Nov 1 11:25:45 2018 [*] [timestart] 0 [size] 1394 830 [pos] -1 -1 *-5.990967 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] rvfi_testbench. [treeopen] rvfi_testbench.wrapper. [sst_width] 225 [signals_width] 310 [sst_expanded] 1 [sst_vpaned_height] 241 @24 rvfi_testbench.cycle[7:0] @200 - @28 rvfi_testbench.wrapper.clock rvfi_testbench.wrapper.reset @200 - -I-MEM @28 rvfi_testbench.wrapper.ibus_cyc rvfi_testbench.wrapper.ibus_ack @22 rvfi_testbench.wrapper.ibus_adr[31:0] rvfi_testbench.wrapper.ibus_rdt[31:0] @200 - -D-MEM @28 rvfi_testbench.wrapper.dbus_cyc rvfi_testbench.wrapper.dbus_ack rvfi_testbench.wrapper.dbus_we @22 rvfi_testbench.wrapper.dbus_adr[31:0] rvfi_testbench.wrapper.dbus_dat[31:0] rvfi_testbench.wrapper.dbus_sel[3:0] rvfi_testbench.wrapper.dbus_rdt[31:0] @200 - -RVFI @28 rvfi_testbench.wrapper.rvfi_valid @22 rvfi_testbench.wrapper.rvfi_insn[31:0] rvfi_testbench.wrapper.rvfi_pc_rdata[31:0] @200 - - [pattern_trace] 1 [pattern_trace] 0 ================================================ FILE: cores/serv/cover.sby ================================================ [options] mode cover append 0 tbtop wrapper.uut depth 150 [engines] smtbmc boolector [script] read -sv defines.sv \ cover.sv \ wrapper.sv \ sbram.sv \ serv_bufreg.v \ serv_bufreg2.v \ serv_alu.v \ serv_csr.v \ serv_ctrl.v \ serv_decode.v \ serv_immdec.v \ serv_mem_if.v \ serv_rf_if.v \ serv_rf_ram.v \ serv_rf_ram_if.v \ serv_state.v \ serv_top.v \ serv_rf_top.v prep -flatten -nordff -top testbench [files] cover.sv wrapper.sv sbram.sv serv-src/rtl/serv_bufreg.v serv-src/rtl/serv_bufreg2.v serv-src/rtl/serv_alu.v serv-src/rtl/serv_csr.v serv-src/rtl/serv_ctrl.v serv-src/rtl/serv_decode.v serv-src/rtl/serv_immdec.v serv-src/rtl/serv_mem_if.v serv-src/rtl/serv_rf_if.v serv-src/rtl/serv_rf_ram.v serv-src/rtl/serv_rf_ram_if.v serv-src/rtl/serv_state.v serv-src/rtl/serv_top.v serv-src/rtl/serv_rf_top.v ../../checks/rvfi_macros.vh [file defines.sv] `define RISCV_FORMAL `define RISCV_FORMAL_NRET 1 `define RISCV_FORMAL_XLEN 32 `define RISCV_FORMAL_ILEN 32 `define RISCV_FORMAL_RESET_CYCLES 1 `define RISCV_FORMAL_CHECK_CYCLE 20 `define RISCV_FORMAL_CHANNEL_IDX 0 `define RISCV_FORMAL_CHECKER rvfi_insn_check `define RISCV_FORMAL_INSN_MODEL rvfi_insn_add `define RISCV_FORMAL_ALIGNED_MEM `define MEMIO_FAIRNESS `include "rvfi_macros.vh" ================================================ FILE: cores/serv/cover.sv ================================================ module testbench ( input clock, input reset, `RVFI_OUTPUTS ); rvfi_wrapper wrapper ( .clock(clock), .reset(reset), `RVFI_CONN ); integer cycle = 0; always @(posedge clock) cycle <= cycle + 1; always @(posedge clock) begin assume (reset == (cycle == 0)); cover (rvfi_valid); end endmodule ================================================ FILE: cores/serv/disasm.py ================================================ #!/usr/bin/env python3 from Verilog_VCD.Verilog_VCD import parse_vcd from os import system from sys import argv rvfi_valid = None rvfi_order = None rvfi_insn = None for netinfo in parse_vcd(argv[1]).values(): for net in netinfo['nets']: # print(net["hier"], net["name"]) if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_valid": rvfi_valid = netinfo['tv'] if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_order": rvfi_order = netinfo['tv'] if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_insn": rvfi_insn = netinfo['tv'] assert len(rvfi_valid) == len(rvfi_order) assert len(rvfi_valid) == len(rvfi_insn) prog = list() for tv_valid, tv_order, tv_insn in zip(rvfi_valid, rvfi_order, rvfi_insn): if tv_valid[1] == '1': prog.append((int(tv_order[1], 2), int(tv_insn[1], 2))) with open("disasm.s", "w") as f: for tv_order, tv_insn in sorted(prog): if tv_insn & 3 != 3 and tv_insn & 0xffff0000 == 0: print(".hword 0x%04x # %d" % (tv_insn, tv_order), file=f) else: print(".word 0x%08x # %d" % (tv_insn, tv_order), file=f) system("riscv64-unknown-elf-gcc -c disasm.s") system("riscv64-unknown-elf-objdump -d -M numeric,no-aliases disasm.o") ================================================ FILE: cores/serv/generate.sh ================================================ #!/bin/bash set -ex rm -rf serv-src git clone git@github.com:olofk/serv.git serv-src python3 ../../checks/genchecks.py ================================================ FILE: cores/serv/sbram.sv ================================================ // SiliconBlue RAM Cells module SB_RAM40_4K ( output [15:0] RDATA, input RCLK, RCLKE, RE, input [10:0] RADDR, input WCLK, WCLKE, WE, input [10:0] WADDR, input [15:0] MASK, WDATA ); // MODE 0: 256 x 16 // MODE 1: 512 x 8 // MODE 2: 1024 x 4 // MODE 3: 2048 x 2 parameter WRITE_MODE = 0; parameter READ_MODE = 0; parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; `ifndef BLACKBOX wire [15:0] WMASK_I; wire [15:0] RMASK_I; reg [15:0] RDATA_I; wire [15:0] WDATA_I; generate case (WRITE_MODE) 0: assign WMASK_I = MASK; 1: assign WMASK_I = WADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 : WADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx; 2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 : WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 : WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 : WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx; 3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 : WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 : WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 : WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 : WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 : WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 : WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 : WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx; endcase case (READ_MODE) 0: assign RMASK_I = 16'b 0000_0000_0000_0000; 1: assign RMASK_I = RADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 : RADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx; 2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 : RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 : RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 : RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx; 3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 : RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 : RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 : RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 : RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 : RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 : RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 : RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx; endcase case (WRITE_MODE) 0: assign WDATA_I = WDATA; 1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12], WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8], WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4], WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]}; 2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13], WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]}; 3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11], WDATA[11], WDATA[11], WDATA[11], WDATA[11], WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]}; endcase case (READ_MODE) 0: assign RDATA = RDATA_I; 1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8], 1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]}; 2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0}; 3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0}; endcase endgenerate integer i; reg [15:0] memory [0:255]; initial begin for (i=0; i<16; i=i+1) begin memory[ 0*16 + i] <= INIT_0[16*i +: 16]; memory[ 1*16 + i] <= INIT_1[16*i +: 16]; memory[ 2*16 + i] <= INIT_2[16*i +: 16]; memory[ 3*16 + i] <= INIT_3[16*i +: 16]; memory[ 4*16 + i] <= INIT_4[16*i +: 16]; memory[ 5*16 + i] <= INIT_5[16*i +: 16]; memory[ 6*16 + i] <= INIT_6[16*i +: 16]; memory[ 7*16 + i] <= INIT_7[16*i +: 16]; memory[ 8*16 + i] <= INIT_8[16*i +: 16]; memory[ 9*16 + i] <= INIT_9[16*i +: 16]; memory[10*16 + i] <= INIT_A[16*i +: 16]; memory[11*16 + i] <= INIT_B[16*i +: 16]; memory[12*16 + i] <= INIT_C[16*i +: 16]; memory[13*16 + i] <= INIT_D[16*i +: 16]; memory[14*16 + i] <= INIT_E[16*i +: 16]; memory[15*16 + i] <= INIT_F[16*i +: 16]; end end always @(posedge WCLK) begin if (WE && WCLKE) begin if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0]; if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1]; if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2]; if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3]; if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4]; if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5]; if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6]; if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7]; if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8]; if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9]; if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10]; if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11]; if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12]; if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13]; if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14]; if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15]; end end always @(posedge RCLK) begin if (RE && RCLKE) begin RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I; end end `endif endmodule module SB_RAM40_4KNR ( output [15:0] RDATA, input RCLKN, RCLKE, RE, input [10:0] RADDR, input WCLK, WCLKE, WE, input [10:0] WADDR, input [15:0] MASK, WDATA ); parameter WRITE_MODE = 0; parameter READ_MODE = 0; parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; SB_RAM40_4K #( .WRITE_MODE(WRITE_MODE), .READ_MODE (READ_MODE ), .INIT_0 (INIT_0 ), .INIT_1 (INIT_1 ), .INIT_2 (INIT_2 ), .INIT_3 (INIT_3 ), .INIT_4 (INIT_4 ), .INIT_5 (INIT_5 ), .INIT_6 (INIT_6 ), .INIT_7 (INIT_7 ), .INIT_8 (INIT_8 ), .INIT_9 (INIT_9 ), .INIT_A (INIT_A ), .INIT_B (INIT_B ), .INIT_C (INIT_C ), .INIT_D (INIT_D ), .INIT_E (INIT_E ), .INIT_F (INIT_F ) ) RAM ( .RDATA(RDATA), .RCLK (~RCLKN), .RCLKE(RCLKE), .RE (RE ), .RADDR(RADDR), .WCLK (WCLK ), .WCLKE(WCLKE), .WE (WE ), .WADDR(WADDR), .MASK (MASK ), .WDATA(WDATA) ); endmodule module SB_RAM40_4KNW ( output [15:0] RDATA, input RCLK, RCLKE, RE, input [10:0] RADDR, input WCLKN, WCLKE, WE, input [10:0] WADDR, input [15:0] MASK, WDATA ); parameter WRITE_MODE = 0; parameter READ_MODE = 0; parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; SB_RAM40_4K #( .WRITE_MODE(WRITE_MODE), .READ_MODE (READ_MODE ), .INIT_0 (INIT_0 ), .INIT_1 (INIT_1 ), .INIT_2 (INIT_2 ), .INIT_3 (INIT_3 ), .INIT_4 (INIT_4 ), .INIT_5 (INIT_5 ), .INIT_6 (INIT_6 ), .INIT_7 (INIT_7 ), .INIT_8 (INIT_8 ), .INIT_9 (INIT_9 ), .INIT_A (INIT_A ), .INIT_B (INIT_B ), .INIT_C (INIT_C ), .INIT_D (INIT_D ), .INIT_E (INIT_E ), .INIT_F (INIT_F ) ) RAM ( .RDATA(RDATA), .RCLK (RCLK ), .RCLKE(RCLKE), .RE (RE ), .RADDR(RADDR), .WCLK (~WCLKN), .WCLKE(WCLKE), .WE (WE ), .WADDR(WADDR), .MASK (MASK ), .WDATA(WDATA) ); endmodule module SB_RAM40_4KNRNW ( output [15:0] RDATA, input RCLKN, RCLKE, RE, input [10:0] RADDR, input WCLKN, WCLKE, WE, input [10:0] WADDR, input [15:0] MASK, WDATA ); parameter WRITE_MODE = 0; parameter READ_MODE = 0; parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; SB_RAM40_4K #( .WRITE_MODE(WRITE_MODE), .READ_MODE (READ_MODE ), .INIT_0 (INIT_0 ), .INIT_1 (INIT_1 ), .INIT_2 (INIT_2 ), .INIT_3 (INIT_3 ), .INIT_4 (INIT_4 ), .INIT_5 (INIT_5 ), .INIT_6 (INIT_6 ), .INIT_7 (INIT_7 ), .INIT_8 (INIT_8 ), .INIT_9 (INIT_9 ), .INIT_A (INIT_A ), .INIT_B (INIT_B ), .INIT_C (INIT_C ), .INIT_D (INIT_D ), .INIT_E (INIT_E ), .INIT_F (INIT_F ) ) RAM ( .RDATA(RDATA), .RCLK (~RCLKN), .RCLKE(RCLKE), .RE (RE ), .RADDR(RADDR), .WCLK (~WCLKN), .WCLKE(WCLKE), .WE (WE ), .WADDR(WADDR), .MASK (MASK ), .WDATA(WDATA) ); endmodule ================================================ FILE: cores/serv/wrapper.sv ================================================ module rvfi_wrapper ( input clock, input reset, `RVFI_OUTPUTS ); // I-MEM (* keep *) wire [31:0] ibus_adr; (* keep *) wire ibus_cyc; (* keep *) rand reg [31:0] ibus_rdt; (* keep *) rand reg ibus_ack; // D-MEM (* keep *) wire [31:0] dbus_adr; (* keep *) wire [31:0] dbus_dat; (* keep *) wire [3:0] dbus_sel; (* keep *) wire dbus_we; (* keep *) wire dbus_cyc; (* keep *) rand reg [31:0] dbus_rdt; (* keep *) rand reg dbus_ack; serv_rf_top uut ( .clk(clock), .i_rst(reset), .i_timer_irq(1'b0), `RVFI_CONN, .o_ibus_adr(ibus_adr), .o_ibus_cyc(ibus_cyc), .i_ibus_rdt(ibus_rdt), .i_ibus_ack(ibus_ack), .o_dbus_adr(dbus_adr), .o_dbus_dat(dbus_dat), .o_dbus_sel(dbus_sel), .o_dbus_we (dbus_we ), .o_dbus_cyc(dbus_cyc), .i_dbus_rdt(dbus_rdt), .i_dbus_ack(dbus_ack) ); // I-MEM always @(posedge clock) begin if (reset) begin assume (!ibus_ack); end if (!ibus_cyc) begin assume (!ibus_ack); end end // D-MEM always @(posedge clock) begin if (reset) begin assume (!dbus_ack); end if (!dbus_cyc) begin assume (!dbus_ack); end end `ifdef MEMIO_FAIRNESS reg [3:0] timeout_ibus = 0; reg [3:0] timeout_dbus = 0; always @(posedge clock) begin timeout_ibus <= 0; timeout_dbus <= 0; if (ibus_cyc && !ibus_ack) timeout_ibus <= timeout_ibus + 1; if (dbus_cyc && !dbus_ack) timeout_dbus <= timeout_dbus + 1; assume (!timeout_ibus[3]); assume (!timeout_dbus[3]); end `endif endmodule ================================================ FILE: docs/config.md ================================================ RISCV-FORMAL Configuration Macros ================================= The riscv-formal insn models and checkers are configured using a few Verilog pre-processor macros. They must be defined bofore reading any riscv-formal verilog files. The first riscv-formal verilog file read after defining the macros must be [rvfi_macros.vh](../checks/rvfi_macros.vh). Example configuration: `define RISCV_FORMAL `define RISCV_FORMAL_NRET 1 `define RISCV_FORMAL_XLEN 32 `define RISCV_FORMAL_ILEN 32 `define RISCV_FORMAL_COMPRESSED `define RISCV_FORMAL_ALIGNED_MEM The macros in this section must be defined by the user where relevant, while the next section includes additional macros which may be automatically generated depending on configuration. Defining `RISCV_FORMAL`, `RISCV_FORMAL_NRET`, `RISCV_FORMAL_XLEN`, and `RISCV_FORMAL_ILEN` is mandatory if `genchecks.py` is not being used. RISCV_FORMAL_UMODE ------------------ This macro must be defined when the core under tests supports U-mode. RISCV_FORMAL_SMODE ------------------ This macro must be defined when the core under tests supports S-mode. RISCV_FORMAL_ALTOPS ------------------- This macro must be defined if the core under tests implements [alternative arithmetic semantic](https://github.com/YosysHQ/riscv-formal/blob/master/docs/rvfi.md#alternative-arithmetic-operations). RISCV_FORMAL_ALIGNED_MEM ------------------------ Cores that only have hardware support for word-aligned memory access may choose to retire memory load/store operations for smaller units (half-words, bytes) word aligned with the appropiate `rmask/wmask` values to select the correct bytes. In this case the `RISCV_FORMAL_ALIGNED_MEM` macro must be defined. RISCV_FORMAL_VALIDADDR(addr) ---------------------------- Set this to an expression of `addr` that evaluates to 1 when the given address is a valid physical address for the processor under test. If not defined this expression will always evaluate to true. RISCV_FORMAL_VALIDHPMEVENT(event) --------------------------------- Set this to an expression of `event` that evaluates to 1 when the given event is a valid assignment for a hpmevent CSR. If not defined this expression will always evaluate to true. RISCV_FORMAL_IOADDR(addr) ------------------------- Set this to an expression of `addr` that evaluates to 1 when the given address belongs to an i/o memory region. If not defined this expression will always evaluate to true. RISCV_FORMAL_WAITINSN(insn) --------------------------- Set this to an expression of `insn` that evaluates to 1 when the given instruction is a wait instruction similar to WFI. (WFI does not need to be recognized by the expression. This is for non-standard instructions in addition to WFI.) RISCV_FORMAL_PMA_MAP -------------------- Set this to the name of a module that takes an address as input and outputs the PMA info for that address. The exact interface of such a module is not entirely defined yet. Testbench Macros ================ The following macros are all defined automatically when using `genchecks.py`. If tests are being performed manually without the generated framework, some of these macros may be required to be defined by the user prior to loading the testbench. Additional information may be found in the [configuring check generation section](procedure.md#Configuring-Check-Generation) of the procedure document. RISCV_FORMAL ------------ This macro is set whenever riscv-formal is used. It is actually never used by any of the riscv-formal Verilog files, but can be used by cores under test to enable or disable generation of the RVFI ports. RISCV_FORMAL_NRET ----------------- The number of channels for the RVFI port (and thus the theoretical maximum number of instructions the core can retire via RVFI in one cycle). The value of this macro can be set by providing the `nret` option in the check config. RISCV_FORMAL_XLEN ----------------- The width of integer registers in the ISA implemented by the core under test. Valid values are 32, 64, and 128. Only 32 is fully supported at the moment. `genchecks.py` will define this as 32, unless the `isa` string in the options contains rv64. RISCV_FORMAL_ILEN ----------------- The maximum width of an instruction retired by the core. For cores supporting fused instructions this is the maximum length of a complete fused instruction. There is currently no way to automatically generate tests with a value other than 32. RISCV_FORMAL_COMPRESSED ----------------------- For cores supporting the RISC-V Compressed ISA this define must be set. This will be automatically defined if the `c` extension appears in the `isa` string. RISCV_FORMAL_BLACKBOX_REGS -------------------------- When checking for correct implementation of the RISC-V instructions ("insncheck") it is possible to black-box the processor register file. This macro may be used in the core under test to black-box the register file. Controlled by the presence or absence of the `blackbox` option. RISCV_FORMAL_BLACKBOX_ALU ------------------------- When checking for consistency of the stream of retired instructions (such as "regcheck") it is possible to black-box the actual ALU operations. This macro may be used in the core under test to black-box the ALU. Controlled by the presence or absence of the `blackbox` option. RISCV_FORMAL_FAIRNESS --------------------- When checking for liveness of the core, then the peripherals and abstractions used in the check must guarantee fairness. This macro should be tested by the peripherals and abstractions to decide if fairness guarantees should be enabled. Automatically defined for `liveness` and `hang` checks. RISCV_FORMAL_RESET_CYCLES ------------------------- The number of cycles to hold reset high for at the start of the model checking. RISCV_FORMAL_CHECK_CYCLE ------------------------ The cycle number in which checks will be performed. For bounded model checking, this should be the solver depth. RISCV_FORMAL_TRIG_CYCLE ----------------------- The cycle number in which to trigger some check specific action. RISCV_FORMAL_CHANNEL_IDX ------------------------ For checks which only operate on a single channel, this macro defines which channel is being checked. RISCV_FORMAL_CHECKER -------------------- The name of the module to be instantiated by the testbench for formal verification. e.g. `rvfi_csrw_check`. RISCV_FORMAL_ASSUME ------------------- Indicates that the `assume_stmts.vh` file should be included in the testbench. This file is expected to contain a series of SV assumptions that the solver should make. RISCV_FORMAL_UNBOUNDED ---------------------- This macro is used to indicate that unbounded model checking is being used. RISCV_FORMAL_CSR_ -------------------------- Each CSR being connected over the RVFI interface should be defined with one of these macros. Refer to the [RVFI Interface Specification for CSRs](rvfi.md#Control-and-Status-Registers-(CSRs)) for more details on how this name is used. RISCV_FORMAL_CSRW_NAME ---------------------- This macro defines the name of the CSR under test during `csrw` checks. RISCV_FORMAL_CSRWH ------------------ This macro is used in the `csrw` checks to indicate that the current CSR consists of two registers, with the second being of the same name but appended with 'h'. RISCV_FORMAL_INSN_MODEL ----------------------- When performing `insn` checks, this is the name of the module for the current instruction. e.g. `rvfi_insn_add`. Macros defined by rvfi_macros.vh ================================ The Verilog file `rvfi_macros.vh` defines a few useful helper macros. RVFI_WIRES, RVFI_OUTPUTS, RVFI_INPUTS, RVFI_CONN ------------------------------------------------ Macros to declare wires, output ports, or input ports for all `rvfi_*` signals. The last macro is for creating the proper connections on module instances. This macros can be useful for routing the `rvfi_*` signals through the design hierarchy. rvformal_rand_reg and rvformal_rand_const_reg --------------------------------------------- Macros for defining unconstrained signals (`rvformal_rand_reg`) or constant signals with an unconstrained initial value (`rvformal_rand_const_reg`). Usage example: `rvformal_rand_reg [7:0] anyseq; `rvformal_rand_const_reg [7:0] anyconst; For formal verification with Yosys (i.e. when `YOSYS` is defined), this will be converted to the following code: rand reg [7:0] anyseq; rand const reg [7:0] anyconst; For simulation (i.e. when `SIMULATION` is defined), this will be converted to: reg [7:0] anyseq; reg [7:0] anyconst; And otherwise (for use with any formal verification tool): wire [7:0] anyseq; reg [7:0] anyconst; ================================================ FILE: docs/csrs.md ================================================ RISC-V Formal CSR Sematics ========================== For the most part the CSR values output via RVFI match exactly the CSR values observable via the ISA. But there are a few minor differences that are outlined here. Most importantly, for RV64 processors in RV32 mode, the values output via RVFI are still following RV64 CSR encondings, including some of the information that is not available through the RV32 ISA, such as SXL and UXL in `mstatus`. Counters are always output as singe 64-bit wide CSRs even on RV32 targets. M-mode CSRs ----------- ### Machine Information Registers #### mvendorid, marchid, mimpid, mhartid, mconfigptr These CSRs are mandatory and expected to be constant, but may be all 0. ### Machine Trap Setup #### mstatus Mandatory. (Reminder: RV64 processors in RV32 mode are expected to output the RV64 format.) May be all 0, reserved bits must be 0 regardless of writes. #### misa Can be read-only 0, but existence is mandatory. Reserved bits must be 0 regardless of writes. #### medeleg, mideleg Only exist if S mode is supported. #### mie, mtvec Mandatory. #### mcounteren Currently only the `IR` and `CY` bits of `mcounteren` are supported by riscv-formal. The other bits are ignored. mcounteren must only exist if U mode is supported. ### Machine Trap Handling #### mscratch Nothing special for this CSR. #### mepc The version of `mepc` observable through the ISA masks `mepc[1]` on CSR reads when the processor is in a mode that does not supprt 16-bit instruction alignment. However, writes to that bit shall still modify the underlying architectural state. In riscv-formal semantics the `mepc` value output via RVFI must be the actual architectural state with `mepc[1]` not masked. #### mcause, mtval, mip Nothing special for these CSRs. ### Machine Protection and Translation TBD ### Machine Counter/Timers #### mcycle, minstret Always 64-bit wide, even on pure RV32 processors (no mcycleh/minstreth). Incrementing those counters should happen "between instructions", this means for example that an instruction that isn't a CSR write to `mcycle` should always have `rvfi_csr_mcycle_rdata == rvfi_csr_mcycle_wdata`. #### mhpmcounter, mhpmevent Machine performance-monitoring counters are currently not supported by riscv-formal. ### CSR 0xFFF This address is used as a catch-all to mean no address and thus is not able to be tested normally. Debug-Mode CSRs --------------- TBD U-Mode CSRs ----------- TBD S-Mode CSRs ----------- TBD ================================================ FILE: docs/examplebugs.md ================================================ Examples of bugs found by riscv-formal ====================================== This page lists a few examples of common types of bugs found by riscv-formal. This page is intentionally a bit vague on the details. Its purpose is to give readers an idea of what kind of bugs can be found with riscv-formal, not to pillory implementations for long fixed bugs. Instruction Semantics --------------------- Some parts of the instruction semantics are easy to get wrong and are not tested very well by standard test-benches like riscv-torture or booting a linux kernel. ### Reserved C-extension opcodes and hint instructions The C-extension opcode map contains several reserved opcodes (that should trigger an illegal instruction trap) and hint instructions (that should be treated as NOPs). Some implementations get some of those opcodes wrong, and riscv-formal has found bugs like this. There were even instances of implementations that fixed issues like that, and then later reversed the fixes because someone looking over the code misread the standard and thought they would fix a bug but instead they re-introduced one. A good example why one should not only verify their implementation once, but continuously keep verifying it as long as changes are made to the design, even in cases where those changes are considered "only trivial minor changes". ### JALR clears LSB after addition The JALR instruction adds an immediate to its source register, clears the LSB of the sum, and then jumps to the resulting address. (It also stores the address of the next instruction in the desitination register.) The code C compilers generate usually (always?) have the LSB of the sum already cleared, so a bug in an implementation where the LSB is not cleared by the instruction (but, for example, an instruction address misaligned trap is triggered instead) is usually not discovered by just running compiler-generated code. With riscv-formal I have found this exact bug in several implementations. Troubles with bypassing and forwarding -------------------------------------- In pipelined architectures bypassing and forwarding are used to avoid pipeline stalls. Bugs in bypassing and forwarding often are only triggered by a specific sequence of instructions, combined with just the right (wrong?) timing for external events (such as completion of a memory operation). I have found several bugs like this with riscv-formal. Issues with reset ----------------- Reset issues can be incredibly hard to find using simulation. One implementation had a reset problem in the divider so that one could start a division, then reset the processor while the divide is in flight, and then divide again as one of the first instructions after reset. If the timing was just right then this second division would return immediately, with the result of the divide that was launched before the reset. Weird and bizarre programs -------------------------- Some assembler code snippets are so bizarre that rarely someone writes a test for them. But a proper implementation of RISC-V should of course still cope with those cases correctly. ### Disabling the C ISA extension while not 32-bit aligned On a processor that supports it, one can enable or disable individual ISA extensions by writing to the `misa` CSR. Disabling the C extension in an instruction that isn't aligned to a 32-bit word should cause the processor to trigger an instruction address misaligned trap for the next instruction. One processor had a bug so that when the next instruction was a load, that load was not killed properly and then caused some strange effects when the load finally completed. Noteworthy about this case is that disabling the C ISA extension while not 32-bit aligned is not sufficient to reproduce the bug. Instead this CSR write must be combined with a load instruction that should be killed by the trap, and then it must be checked if the destination register of that load changes at a later time (when the not-properly-killed load finishes). ================================================ FILE: docs/procedure.md ================================================ riscv-formal Verification Procedure =================================== The following formal test are performed to verify ISA compliance of RISC-V processors with `riscv-formal`. Depending on aspects like the strength of safety properties present in the core, the overall complexity of the core, and the verification requirements for the given application, the following tests might be set up as bounded model checks or as unbounded verification tasks. For most cores the easiest approach is to create a wrapper HDL module and a `checks.cfg` file and use the `genchecks.py` scripts to create the formal checks. See [cores/picorv32/](../cores/picorv32/) for an example implementation. The checks generated by `genchecks.py` are bounded model checks which use sby for verification. Configuring Check Generation ---------------------------- A config file with extension `.cfg` is used to configure the `genchecks.py` script. By default, the name of this config file is expected to be `checks`. Calling `genchecks.py` with an argument will instead use the provided name. For example, `python3 ../../checks/genchecks.py tests` will load config settings from a file named `tests.cfg`. Note that the script will generate a folder with the same config name in the directory it is run. It is expected for `genchecks.py` to be called from a subdirectory of the `cores` folder, such that the script is called as `../../checks/genchecks.py`, and the subdirectory is the name of the core. This core name will be used for naming certain intermediary files, but is otherwise arbitrary and does not need to match anything else. The config file consists of a number of sections, with each section starting with the name of the section in square brackets. Some of these sections are shared between tests, and some are used only for specific formal checks. The shared sections will be covered here, while check specific details will be covered in the relevant section below. Comments can be included in the config file by prefixing a line with a `#` character. #### `[options]` This section primarily contains options which describe the core under test. Possible options are listed below, along with their expected value. For options with no expected value, simply including the option enables the specified effect. | Option | Value | Description | | -------- | ------- | ----------- | | isa | String | ISA extensions, e.g. `RV64IMAFD`, or `rv32i`. Note that X and Z extensions are not currently supported and should be removed from the string. | | nret | Integer | The number of channels for the RVFI port. Defaults to 1. | | blackbox | None | Signifies register file and ALU should be black-boxed. | | solver | String | Name of solver, defaults to `boolector`. | | dumpsmt2 | None | Passed to `smtbmc` engine to output SMT2 trace. | | abspath | None | Generated makefile will use absolute path of generated files. | | mode | String | Solver mode, currently supports either `bmc` or `prove`, and defaults to `bmc`. | #### `[depth]` This section provides the execution depth to be used by the solver for each test. The name of the check is listed, followed by one or more integers separated by a space. For formal checks that expect multiple values to be provided here, the meaning of each will be defined in the relevant section. For cores with multiple channels, the channel number can be used in the name of the check by appending `_ch#`. Note that a more specific name will be used over a less specific name. For example, if `insn ` and `insn_ch1 ` are both listed, `insn` tests on channel 1 will use `depth1`, while all other channels will use `depth0`. If a formal check does not have a corresponding depth listed, it will not be generated. For example, providing `reg_ch2 ` but not `reg ` will run the `reg` check *only* on channel 2. #### `[groups]` This section defines a list of group names which are prepended to all check names which can then be used for grouping multiple checks together. These groups can then be used for testing with multiple depth values. Each group must be separated by whitespace. As an example, if groups `a` and `b` are listed with depth settings of `a_insn `, `b_insn_bne `, then all instructions will be tested with depth `x`, and the `bne` instruction will be tested to both depths `x` and `y`. #### `[sort]` If this section is included, any listed checks will be run in the order they appear in this list, and will be run *before* any un-listed checks. Each item should be placed on its own line. When multiple checks match the same ordering, alphabetical order will be used. Note that regex is used to search for a match of the *full* check name, including group and channel. This can be used to, for example, list all checks on channel 2 before any others by adding `.*?_ch2` as the first item. If the user is unfamiliar with regex, simply providing the names of checks verbatim will also work. Note that this sorting also determines the order in which checks are generated in the makefile. The order in which tests are started should be maintained by Make, however if parallelism is enabled then there is no guarantee that tests will *complete* in this order. #### `[filter-checks]` Specific checks can be enabled or disabled by adding them to this section prefixed with either a `+` or `-` and a space. As with `[sort]` above, regex is used for matching against each line. Note that the *first* match returns. For example, if `+ insn_(mul|div)_ch1` is listed before `- insn_.*_ch1`, then the `mul` and `div` instructions will be enabled for testing on channel 1, while all other instructions are disabled. #### `[assume]` Each line of this section provides a two value tuple. The first value is the regex pattern used to match the current check name, while the second value is code to be included in the file `assume_stmts.vh`. If the first value begins with a `!`, the code is used for all checks that *do not* match the pattern, otherwise the code is used for all checks that *do* match. This file is included verbatim at the end of the `rvfi_testbench` module in [checks/rvfi_testbench.sv](../checks/rvfi_testbench.sv), and so should be valid System Verilog code. ### Verbatim sections A number of sections are included in the sby script essentially as-is. These sections are formatted with a few keyword substitutions. If using these substitutions, the keywords should be prepended and appended with a `@` symbol, e.g. `@basedir@/cores/@core@/wrapper.sv` is using the `basedir` and `core` keywords to define the path. Possible keywords include: - basedir: the root directory of riscv-formal - core: the name of the directory from which the script is executed - ilang_file: filename of intermediary output - channel: the current rvfi channel - check: the current check, e.g. `csrc` - checkch: the full name of the current check, e.g. `a_csrc_misa_ch0` #### `[script-defines]` This section is included at the *start* of the sby `[script]` section. Check specific code can also be included as `[script-defines ]`, where `` is the current check. #### `[verilog-files]` and `[vhdl-files]` These sections list all of the core source files which should be included in testing. All verilog files will be listed after `read -sv `, while all vhdl files will be listed after `read -vhdl`. #### `[script-sources]` This section can be used to add any other source files which do not fit under `-sv` or `-vhdl`, and is included *before* the `prep` command. #### `[script-link]` This section is included *after* the `prep` command and *before* `chformal`. #### `[defines]` This section is included as part of `[file defines.sv]`. Check specific code can also be included as `[defines ]`, where `` is the current check. Standard Checks --------------- The following checks are managed by `genchecks.py` and can be implemented using the standard RVFI wrapper interface. ### Instruction Checks The majority of formal checks needed to verify a core with riscv-formal are instruction checks (one per RVFI channel and RISC-V instruction supported by the core). Instruction checks test if the instruction (`rvfi_insn`) matches the state transistion described by the other RVFI signals. ### PC Checks There are two PC checks: `pc_fwd` and `pc_bwd`. Both of them are run for each RVFI channel. The `pc_fwd` check assumes that the core retires an instruction at the end of the bounded model check, and that the previous instruction in the program (`rvfi_order-1`) was retired earlier. It then tests if `rvfi_pc_wdata` of the previous instruction matches `rvfi_pc_rdata` of the next instruction. `pc_bwd` is like `pc_fwd` but for pairs of instructions that have been executed out of order: The check assumes that the core retires an instruction at the end of the bounded model check, and that the next instruction in the program (`rvfi_order+1`) was retired earlier. It then tests if `rvfi_pc_wdata` of the previous instruction matches `rvfi_pc_rdata` of the next instruction. #### `[depth]` section Expects two values: first is the number of cycles to reset for; second is the execution depth. ### Register Checks This checks if writes to and reads from the register file are consistent with each other, i.e. if the value written to a register matches the value read from the register file by a later instructions. This check assumes that the last instruction at the end of the bounded model check, reads a register. It then checks that the value read is consistent with the matching write to the same register by an earlier instruction. #### `[depth]` section Expects two values: first is the number of cycles to reset for; second is the execution depth. ### Causality There are three causality checks: `causal`, `causal_mem` and `causal_io`. The core may retire instructions out-of-order as long as causality is preserved. (This means a write must be retired before the reads that depend on it.) The `causal` check tests if the instruction stream is causal with respect to registers. The `causal_mem` check tests if the instruction stream is causal with respect to memory. The `causal_io` check tests if the instruction stream is causal with respect to i/o memory, where every i/o memory access is assumed to depend on all earlier i/o memory accesses. Which areas of the adress space are considered to be i/o memory can be configured using the RISCV_FORMAL_IOADDR(addr) macro. #### `[depth]` section Expects two values: first is the number of cycles to reset for; second is the execution depth. #### `[depth]` section Expects two values: first is the number of cycles to reset for; second is the execution depth. ### Liveness This check makes sure that the core never freezes (unless an instruction with `rvfi_halt` asserted is retired): This check assumes that an instruction is retired at a configurable trigger point in the middle of the bounded model check. It then checks that the next instruction (`rvfi_order+1`) is also retired at some point during the span of the bounded model check. It might be neccessary to add some bounded fairness constraints to the design for this check to succeed. #### `[depth]` section Expects three values: first is the number of cycles to reset for; second is the trigger depth; and third is the execution depth. ### Uniqueness This check makes sure that no two instructions with the same `rvfi_order` are retired by the core. #### `[depth]` section Expects three values: first is the number of cycles to reset for; second is the trigger depth; and third is the execution depth. ### Faults This check makes sure that dynamically occuring memory faults are handled. It requires defining `RISCV_FORMAL_MEM_FAULT` and the `rvfi_mem_fault`, `rvfi_mem_fault_rmask` and `rvfi_mem_fault_wmask` signals. When the `mcause` CSR is exposed via RVFI, this will also check that it is correctly updated on a memory fault. #### `[depth]` section Expects two values: first is the number of cycles to reset for; second is the execution depth. ### Cover A formal check using `cover()` SystemVerilog statements for various interesting RVFI events or sequences of events. The purpose of this formal check is to collect some data about the required bounds to reach certain states to set the bounds for the other bounded model checks. This check can also be used for creating witness traces, for example to examine the conditions under which a specific CSR bit goes high. #### `[depth]` section Expects two values: first is the number of cycles to reset for; second is the execution depth. #### `[cover]` section All code in this section is included verbatim in the file `cover_stmts.vh`, which is included verbatim in [checks/rvfi_cover_check.sv](../checks/rvfi_cover_check.sv), and so should be valid System Verilog code. Standard Bus Checks ------------------- The following checks are managed by `genchecks.py` and can be implemented using the standard RVFI wrapper interface when implementing the RVFI_BUS extension. ### Instruction Bus Memcheck The `bus_imem` check adds a memory abstraction that only emulates a single word of memory (at an unconstrained address). This memory word is read-only and has an unconstrained value. The check makes sure that instructions fetched from this memory word are handled correctly and that the data from that memory word makes its way into `rvfi_insn` unharmed. When the granularity of access faults as observed from the core is coarser than the width of the bus, `RISCV_FORMAL_FAULT_WIDTH` needs to be defined and set to the corresponding width in bytes. E.g. for a setup where a single word fault the monitored bus means that from the perspective of the core, any access of the corresponding cache line will fault, you would define `RISCV_FORMAL_FAULT_WIDTH` to be the width of a cache line in bytes. ### Instruction Bus Fault Memcheck The `bus_imem_fault` check adds a memory abstraction that has a single always faulting word of memory (at an unconstrained address). The check makes sure that executing from this address causes an "instruction access fault" trap. The RVFI signalling for the instruction with a faulting fetch requires an all-zero `rvfi_insn` value with `rvfi_trap` set. When `RISCV_FORMAL_MEM_FAULT` is defined the associated signals must also be set correctly. ### Data Bus Memcheck This `bus_dmem` check adds a memory abstraction that only emulates a single word of memory (at an unconstrained address). The memory word is read/write. The check tests if writes to and reads from the memory location (as reported via RVFI) are consistent. Additionally it checks that an initial value as reported via RVFI matches the fetched value on the bus. This check does not require writes to appear on the bus and is thus compatible with caches between the core and the observed bus. When the granularity of access faults as observed from the core is coarser than the width of the bus, `RISCV_FORMAL_FAULT_WIDTH` needs to be defined. See "Instruction Bus Memcheck" above for more details. ### Data Bus Fault Memcheck The `bus_dmem_fault` check adds a memory abstraction that has a single always faulting word of memory (at an unconstrained address). The check makes sure that reading from or writing to this address causes a "load access fault" or "store/AMO access fault" trap respectively. The RVFI signalling for an instruction causing either fault has `rvfi_trap` and does not include a register update or memory write, even if the instruction would have performed one if the memory access didn't fault. When `RISCV_FORMAL_MEM_FAULT` is defined the associated signals must also be set correctly. ### Data Bus I/O Checks These checks can provide stronger guarantees on data bus accesses that are not required to hold in general, but should often hold for i/o memory regions. Depending on the use-case only a subset may be applicable or some checks may only be applicable for certain areas of the address space. The memory addresses for which these checks are run can be configured using the `RISCV_FORMAL_IOADDR(addr)` macro. #### Data Bus I/O Reads The `bus_dmem_io_read` check makes sure that every retired non-faulting i/o memory read access appears as an individual read on the bus. The whole read has to appear on its own in a single RVFI_BUS cycle. A read is allowed to also read adjacent bytes within the same RVFI_BUS cycle. #### Data Bus I/O Read Faults The `bus_dmem_io_read_fault` check makes sure that every retired faulting i/o memory read access appears as an individual faulting read on the bus. #### Data Bus I/O Writes The `bus_dmem_io_write` check makes sure that every retired non-faulting i/o memory write access appears as an individual write on the bus. The whole write has to appear on its own in a single RVFI_BUS cycle and may not write any additional adjacent bytes. #### Data Bus I/O Read Faults The `bus_dmem_io_read_fault` check makes sure that every retired faulting i/o memory write access appears as an individual faulting write on the bus. #### Data Bus I/O Ordering The `bus_dmem_io_order` check makes sure that all i/o memory accesses appear in-order on the bus. This is done by checking that every pair of adjacent i/o memory accesses (as observed via RVFI) corresponds to adjacent i/o memory accesses on the bus. Non-i/o accesses are ignored by this check, so they can be arbitrarily reordered relative to i/o accesses and relative to each other. CSR Checks ---------- The following checks are managed by `genchecks.py` and can be implemented using the standard RVFI wrapper interface. All checks operate on one channel at a time and may not work correctly if a CSR is able to be modified by more than one channel. ### CSR instruction check The `csrw` check validates that CSR instructions modify the correct rvfi signal ports. `RISCV_FORMAL_CSRW_NAME ` must be defined for the CSR under test, along with `csr_{m,s,u}index_ `. If the CSR has a corresponding 'h' register containing the upper bits, `RISCV_FORMAL_CSRWH` and `csr_{m,s,u}indexh_ ` should also be defined. As per the standard CSR address mapping convention: the top two bits (csr[11:10]) indicate whether the register is read/write (00, 01, or 10) or read-only (11); and the next two bits (csr[9:8]) encode the lowest privilege level that can access the CSR. A valid read instruction must assign `rvfi_csr__rdata` to `rvfi_rd_wdata`, as well as the correct `rvfi_rd_addr`. A valid write instruction must assign the correct value to `rvfi_csr__wdata`. And any illegal accesses should result in a trap. ### Illegal CSR access The `csr_ill` check validates illegal access exceptions are raised for access to CSRs which are not available through the RVFI wrapper interface, including those which may not be implemented. `RISCV_FORMAL_ILL_CSR_ADDR ` must be defined for the CSR under test. Defining `RISCV_FORMAL_ILL_{M,S,U}MODE` specifies which modes should be tested for access, and `RISCV_FORMAL_ILL_{WRITE,READ}` specifies what accesses are expected to be illegal. ### CSR consistency checks These checks perform multiple reads/writes and compare the values on `rvfi_csr__rdata` and `rvfi_csr__wdata` during the `check` cycle. In each case, `RISCV_FORMAL_CSRC_NAME ` must be defined for the CSR under test, along with the corresponsing `csr_{m,s,u}index_ `. #### CSR write-any The `csrc_any` check tests whether any value written to a CSR is then able to be read-back exactly as written. #### CSR increments The `csrc_inc` check tests whether the value in a CSR is always greater than or equal to a previous read/write of the csr. By constraining the most significant bit to be 0, this check can verify that the value of a CSR can never decrease except by writing to it. This is particularly useful for hardware performance monitors. #### CSR up-counter The `csrc_upcnt` check is similar to the CSR increments check but with more constraints. First, no writes of the csr under test are allowed. Second, the test value *must* be greater than the previously read value. Without fairness guarantees this has limited use, but can verify some hpm functions, especially `mcycle` and `minstret`. #### CSR hpm event cover check Unlike most of the other checks, `csrc_hpm` is a cover check. Similarly to the CSR up-counter check, the value of a hpm counter CSR is compared with a previously stored value and must increase. However, because this is a cover check this tests that the CSR *can* increase, not that it *must* increase. Used in conjunction with a `csrc_inc` test of the corresponding hpm counter CSR, this can verify that the hpm is able to increase and unable to decrease. This check must be performed on a hpm event CSR, with `RISCV_FORMAL_CSRC_NAME mhpmevent#` and `RISCV_FORMAL_CSRC_HPMCOUNTER mhpmcounter#`. The event must be defined by `RISCV_FORMAL_CSRC_HPMEVENT `. Note that both `RISCV_FORMAL_CSR_MHPMCOUNTER#` and `RISCV_FORMAL_CSR_MHPMEVENT#` must be defined and the corresponding rvfi signals connected. #### CSR read-constant The `csrc_const` check tests whether the value in a CSR is always the same, ignoring any value which may be written. `RISCV_FORMAL_CSRC_CONSTVAL ` must be defined as the value to be expected. For CSRs which can take any value so long as it remains constant during operation, a value of `rdata_shadow` can be assigned which will compare with the previously read value. #### CSR read-zero The `csrc_zero` check is similar to the CSR read-constant check, but exclusively tests for a constant value of all zero. ### genchecks config #### `[depth]` The `csrw` and `csr_ill` checks expect one value, indicating the maximum depth of the Bounded Model Checker (BMC). All `csrc_*` checks expect two values, with the first being the number of cycles to hold reset for, and the second being the maximum depth of the BMC. Depth can be specified for all tests of one type, e.g. `csrc_zero`, or individual to a particular CSR, e.g. `csrw_mcycle`. Any test without a corresponding value in the `depth` section will not be run. #### `[csrs]` The `csrs` config section lists all standard CSRs which can be tested. By default, all CSRs will be run through the CSR instruction check (`csrw`). Consistency checks can be defined as a space seperated list after the csr name. For checks which expect a value, using quotation marks will allow for verbatim values. e.g. `misa zero const="32'h 0"` declares two tests for the `misa` CSR. First using the `csrc_zero_check`, and then using the `csrc_const_check` with `RISCV_FORMAL_CSRC_CONSTVAL` defined as `32'h 0`. Each named CSR must be connected as described in the [RVFI specification](rvfi.md). Consistency checks can be appended with `_mask=` with a verilog expression which will be applied to the CSR as a bit mask before testing the return value. Note that `_mask` must be defined *after* any other value assignment for the check. For example, the statement `misa const=0_mask="32'h 0aaa_ffff"` masks the `misa` CSR and then checks for a constant value of 0. A mask value is currently only supported in the `const`, `zero`, and `any` checks. `const` supports value assignment, while `hpm` requires it. If no value is provided for `const`, a value of `rdata_shadow` will be assigned such that any value is accepted provided it is constant. In the case of `hpm` the value is assigned to the hpmevent register prior to testing if the hpmcounter register is able to increase. #### `[custom_csrs]` Platform defined CSRs can be included for testing in the `custom_csrs` section. Each line is a space separated list of values defining one CSR and the corresponding tests. The first value is the CSR address in hexadecimal, and the second value is the privilege modes in which the CSR is available. The rest of the line follows the same format as the `csrs` config section with the CSR name followed by any tests in addition to `csrw`. e.g. `fc0 m custom_ro const="32'h dead_beef"` defines a CSR in the machine-level custom read-only address space at address `0xFC0` called `custom_ro` which can be accessed from machine mode and should be tested for a constant value of `0xdeadbeef` using `csrc_const_check`. As with the standard CSRs, each of the custom CSRs must be connected through the RVFI wrapper. Note that the privilege modes defined will not prevent the CSR instruction check from expecting an illegal access exception based on the address. #### `[illegal_csrs]` The `illegal_csrs` section lists unnamed CSRs not available through the RVFI wrapper interface. Each line lists one CSR address to be tested with `csr_ill`, along with the relevant modes to check. Three space separated values are expected; the first provides the address in hexadecimal, the second is the privilege modes to test, and the third indicates whether to test reads and writes or just writes. e.g. `fff msu rw` defines a test at address oxFFF for machine, supervisor, and user modes which should cause an illegal access exception on both reads and writes. #### CSR spec test generation By setting `csr_spec` in the `options` section, it is possible to automatically generate tests for all CSRs to match the specification recommendations/requirements. This option will add all defined CSRs to be tested under `csrw` as well as generating corresponding `csrc` tests where relevant. For those CSRs which should only exist in certain conditions, e.g. if U mode is available, then those CSRs are included if the `isa` option includes them, otherwise the addresses are checked as being an expected illegal access exception. Optional CSRs are not automatically tested and will need to be specified as described above. CSRs which are defined with certain bits being reserved for future use (either WPRI or WARL) are tested as being constant zero, masking for just the reserved bits. At present the only supported value for `csr_spec` is `1.12`, corresponding to version 1.12 of the Machine ISA, as defined in the 20211203 Priveleged Architecture document. Other Checks ------------ The following checks are not yet managed by `genchecks.py` and can not be implemented using the standard RVFI wrapper interface. Some of them may be integrated with `genchecks.py` in the future. ### Instruction Memcheck This check adds a memory abstraction that only emulates a single word of memory (at an unconstrained address). This memory word is read-only and has an unconstrained value. The check makes sure that instructions fetched from this memory word are handled correctly and that the data from that memory word makes its way into `rvfi_insn` unharmed. See `imemcheck.sv` in [cores/picorv32/](../cores/picorv32/) for an example implementation. This check is superseded by the equivalent standard bus check above. ### Data Memcheck This check adds a memory abstraction that only emulates a single word of memory (at an unconstrained address). The memory word is read/write. The check tests if writes to and reads from the memory location (as reported via RVFI) are consistent. See `dmemcheck.sv` in [cores/picorv32/](../cores/picorv32/) for one possible implementation of this test. This check is superseded by the equivalent standard bus check above. ### Checking for equivalence of core with and without RVFI An equivalence check of the core with and without RVFI (with respect to the non-RVFI outputs) is performed. This proves that the verification results for the core with enabled RVFI also prove that the (non-RVFI) production core is correct without extra burden on the core designer to isolate the RVFI implementation from the rest of the core. See `equiv.sh` in [cores/picorv32/](../cores/picorv32/) for an example implementation. ### Complete An additional check to make sure the core can not (without trap) retire any instructions that are not covered by the riscv-formal instruction checks. See `complete.sv` in [cores/picorv32/](../cores/picorv32/) for one possible implementation of this test. ### Verification of riscv-formal models against spike models The checks in [tests/spike/](../tests/spike/) use the Yosys SimpleC back-end and CBMC to check the `riscv-formal` models and the C instruction models from spike for equivalence. ================================================ FILE: docs/quickstart.md ================================================ Quick Start Guide ================= So you want to get your hands dirty with riscv-formal? Install the tools and pick one of the exercises below. See also [this presentation slides](http://bygone.clairexen.net/papers/2017/riscv-formal/) for an introduction to riscv-formal. Prerequisites ------------- You'll need Yosys, SymbiYosys, and Boolector for the formal proofs. See [here](https://yosyshq.readthedocs.io/projects/sby/en/latest/install.html) for install instructions. For additional python requirements: ``` python3 -m pip install Verilog_VCD ``` Some of those tools are packaged for some of the major Linux distribution, but those packages are sometimes a few years old and do not work with riscv-formal. Follow the descriptions linked above and install from the latest sources instead. If you want to inspect counter example traces you will need [gtkwave](http://gtkwave.sourceforge.net/). Whatever version of gtkwave is pre-packaged in your distribution is probably fine. If you want to disassemble the code executed in the counter example traces you will need an installation of 32 bit [riscv-tools](https://github.com/riscv/riscv-tools), specifically you'll need `riscv32-unknown-elf-gcc` and `riscv32-unknown-elf-objdump` in your `$PATH`. For the 2nd exercise the PicoRV32 Makefile expects a toolchain with certain properties in `/opt/riscv32i`. The easiest way to build this is to check out the [PicoRV32 github repo](https://github.com/YosysHQ/picorv32) and run `make -j$(nproc) build-riscv32i-tools` (see [this](https://github.com/YosysHQ/picorv32#building-a-pure-rv32i-toolchain) for prerequisites and more documentation on the process). For the 2nd exercise you will also need [Icarus Verilog](http://iverilog.icarus.com/). If your distribution packages v10 or better then this is fine, otherwise you'll need to build it from source. Exercise 1: Formally verify a core ---------------------------------- Formally verify that the NERV processor complies with the RISC-V ISA: ``` cd riscv-formal cd cores/nerv/ make -j$(nproc) check ``` Now make a random change to `nerv.sv` and re-run the tests: ``` make clean make -j$(nproc) check ``` The check will likely fail now. (It will if the change did break ISA compliance of the core.) If you have a 32 bit version of riscv-tools installed (`riscv32-unknown-elf-gcc` and `riscv32-unknown-elf-objdump` are in `$PATH`) then you can use `disasm.py` to display the sequence of instructions that caused the error. Let's say `liveness_ch0` is the check that failed: ``` python3 disasm.py checks/liveness_ch0/engine_0/trace.vcd ``` Or you can simply use gtkwave to display the counter example trace: ``` gtkwave checks/liveness_ch0/engine_0/trace.vcd trace.gtkw ``` Exercise 2: Build an RVFI Monitor and run it -------------------------------------------- An RVFI Monitor can be run side-by-side with your core and will detect when the core violates the ISA spec. RVFI monitors are synthesizable, so in addition to simulation they can also be used in FPGA emulation testing. Let's build an RVFI Monitor to be used with PicoRV32. PicoRV32 supports the rv32ic ISA (`-i rv32ic`), its RVFI port is one channel wide (`-c 1`), and it performs memory operations with word alignment (`-a`): ``` cd monitor python3 generate.py -i rv32ic -c 1 -a -p picorv32_rvfimon > picorv32_rvfimon.v ``` Next we need to clone the PicoRV32 git repository and copy the monitor core: ``` git clone https://github.com/YosysHQ/picorv32.git cp picorv32_rvfimon.v picorv32/rvfimon.v cd picorv32 ``` And then run the test bench with RVFI monitor support: ``` make test_rvf ``` (You will need to make minor changes to the Makefile if you don't have an rv32i toolchain installed in `/opt/riscv32i`.) You can now try making changes to `picorv32.v` and see if the RVFI monitor catches errors in the test bench when you re-run `make test_rvf`. You can also try running `generate.py` with `-V`. This will generate a monitor that prints some information about each packet it sees on the RVFI port. ================================================ FILE: docs/references.md ================================================ References and related work =========================== ARM's [ISA-Formal Framework](https://alastairreid.github.io/papers/cav2016_isa_formal.pdf) follows a similar set of ideas and has inspired the work on `riscv-formal`. Other RISC-V formal verification projects and related materials: - [Kami: A Framework for (RISC-V) HW Verification](https://riscv.org/wp-content/uploads/2016/07/Wed1130_Kami_Framework_Murali_Vijayaraghavan.pdf) ([kami on github](https://github.com/mit-plv/kami)) - [Rewrite of Kami by SiFive](https://github.com/sifive/Kami) - [Verifying a RISC-V Processor, Nirav Dave, Prashanth Mundkur, SRI International](https://riscv.org/wp-content/uploads/2015/06/riscv-verification-workshop-june2015.pdf) ([l3riscv on github](https://github.com/SRI-CSL/l3riscv)) - [RISC-V ISA Model in Bluespec BSV by Rishiyur S. Nikhil](https://github.com/rsnikhil/RISCV_ISA_Formal_Spec_in_BSV) - [RISC-V ISA Model in Haskell by Adam Chlipala and group (MIT)](https://github.com/mit-plv/riscv-semantics) - [RISC-V ISA Specification in Coq by MIT CSAIL](https://github.com/mit-plv/riscv-coq) - [RISC-V ISA Specification in Coq by SiFive](https://github.com/sifive/RiscvSpecFormal) - [RISC-V ISA specification work in Sail 2](https://github.com/riscv/sail-riscv) - [Sail: a language for describing instruction semantics](http://www.cl.cam.ac.uk/~pes20/sail/) - [riscv-fs: F# RISC-V Instruction Set formal specification](https://github.com/mrLSD/riscv-fs) Please [open an issue](https://github.com/YosysHQ/riscv-formal/issues/new) if you know of other RISC-V formal verification projects I should link to in this section. ================================================ FILE: docs/rvfi.md ================================================ RISC-V Formal Interface (RVFI) ============================== RVFI Specification ------------------ In the following specification the term `XLEN` refers to the width of an `x` register in bits, as described in the RISC-V ISA specification. The term `NRET` refers to the maximum number of instructions that the core under test can retire in one cycle. If more than one of the retired instruction writes the same register, the channel with the highest index contains the instruction that wins the conflict. The term `ILEN` refers to the maximum instruction width for the processor under test. The Interface consists only of output signals. Each signal is a concatenation of `NRET` values of constant width, effectively creating `NRET` channels. For simplicity, the following descriptions refer to one such channel. For example, we refer to `rvfi_valid` as a 1-bit signal, not a `NRET`-bits signal. ### Instruction Metadata output [NRET - 1 : 0] rvfi_valid output [NRET * 64 - 1 : 0] rvfi_order output [NRET * ILEN - 1 : 0] rvfi_insn output [NRET - 1 : 0] rvfi_trap output [NRET - 1 : 0] rvfi_halt output [NRET - 1 : 0] rvfi_intr output [NRET * 2 - 1 : 0] rvfi_mode output [NRET * 2 - 1 : 0] rvfi_ixl When the core retires an instruction, it asserts the `rvfi_valid` signal and uses the signals described below to output the details of the retired instruction. The signals below are only valid during such a cycle and can be driven to arbitrary values in a cycle in which `rvfi_valid` is not asserted. The `rvfi_order` field must be set to the instruction index. No indices must be used twice and there must be no gaps. Instructions may be retired in a reordered fashion, as long as causality is preserved (register and memory write operations must be retired before the read operations that depend on them). `rvfi_insn` is the instruction word for the retired instruction. In case of an instruction with fewer than `ILEN` bits, the upper bits of this output must be all zero. For compressed instructions the compressed instruction word must be output on this port. For fused instructions the complete fused instruction sequence must be output. `rvfi_trap` must be set for an instruction that cannot be decoded as a legal instruction, such as 0x00000000. In addition, `rvfi_trap` must be set for a misaligned memory read or write in PMAs that don't allow misaligned access, or other memory access violations. `rvfi_trap` must also be set for a jump instruction that jumps to a misaligned instruction. The signal `rvfi_halt` must be set when the instruction is the last instruction that the core retires before halting execution. It should not be set for an instruction that triggers a trap condition if the CPU reacts to the trap by executing a trap handler. This signal enables verification of liveness properties. `rvfi_intr` must be set for the first instruction that is part of a trap handler, i.e. an instruction that has a `rvfi_pc_rdata` that does not match the `rvfi_pc_wdata` of the previous instruction. `rvfi_mode` must be set to the current privilege level, using the following encoding: 0=U-Mode, 1=S-Mode, 2=Reserved, 3=M-Mode Finally `rvfi_ixl` must be set to the value of MXL/SXL/UXL in the current privilege level, using the following encoding: 1=32, 2=64 ### Integer Register Read/Write output [NRET * 5 - 1 : 0] rvfi_rs1_addr output [NRET * 5 - 1 : 0] rvfi_rs2_addr output [NRET * XLEN - 1 : 0] rvfi_rs1_rdata output [NRET * XLEN - 1 : 0] rvfi_rs2_rdata `rvfi_rs1_addr` and `rvfi_rs2_addr` are the decoded `rs1` and `rs1` register addresses for the retired instruction. For an instruction that reads no `rs1`/`rs2` register, this output can have an arbitrary value. However, if this output is nonzero then `rvfi_rs1_rdata` must carry the value stored in that register in the pre-state. `rvfi_rs1_rdata`/`rvfi_rs2_rdata` is the value of the `x` register addressed by `rs1`/`rs2` before execution of this instruction. This output must be zero when `rs1`/`rs2` is zero. output [NRET * 5 - 1 : 0] rvfi_rd_addr output [NRET * XLEN - 1 : 0] rvfi_rd_wdata `rvfi_rd_addr` is the decoded `rd` register address for the retired instruction. For an instruction that writes no `rd` register, this output must always be zero. `rvfi_rd_wdata` is the value of the `x` register addressed by `rd` after execution of this instruction. This output must be zero when `rd` is zero. ### Program Counter output [NRET * XLEN - 1 : 0] rvfi_pc_rdata output [NRET * XLEN - 1 : 0] rvfi_pc_wdata This is the program counter (`pc`) before (`rvfi_pc_rdata`) and after (`rvfi_pc_wdata`) execution of this instruction. I.e. this is the address of the retired instruction and the address of the next instruction. ### Memory Access output [NRET * XLEN - 1 : 0] rvfi_mem_addr output [NRET * XLEN/8 - 1 : 0] rvfi_mem_rmask output [NRET * XLEN/8 - 1 : 0] rvfi_mem_wmask output [NRET * XLEN - 1 : 0] rvfi_mem_rdata output [NRET * XLEN - 1 : 0] rvfi_mem_wdata For memory operations (`rvfi_mem_rmask` and/or `rvfi_mem_wmask` are non-zero), `rvfi_mem_addr` holds the accessed memory location. When the define `RISCV_FORMAL_ALIGNED_MEM` is set, the address must have a 4-byte alignment for `XLEN=32` and an 8-byte alignment for `XLEN=64`. When the define is not set, then the address must point directly to the LSB or the word / half word / byte that is accessed. `rvfi_mem_rmask` is a bitmask that specifies which bytes in `rvfi_mem_rdata` contain valid read data from `rvfi_mem_addr`. `rvfi_mem_wmask` is a bitmask that specifies which bytes in `rvfi_mem_wdata` contain valid data that is written to `rvfi_mem_addr`. `rvfi_mem_rdata` is the pre-state data read from `rvfi_mem_addr`. `rvfi_mem_rmask` specifies which bytes are valid. `rvfi_mem_wdata` is the post-state data written to `rvfi_mem_addr`. `rvfi_mem_wmask` specifies which bytes are valid. When `RISCV_FORMAL_ALIGNED_MEM` is set then `riscv-formal` assumes that unaligned memory access causes a trap. ### Alternative Arithmetic Operations Some arithmetic operations (such as multiplication and division) are beyond to practical capabilities of even modern hardware model checkers. In order to still be able to verify things like bypassing for the arithmetic units performing those operations we define a set of alternative arithmetic operations. When the define `RISCV_FORMAL_ALTOPS` is set riscv-formal will expect the processor under test to implement those alternative operations instead. Commutative operations (like multiplication) are replaced with addition followed by applying XOR with a bitmask that indicates the type of the operation. Noncommutative operations (like division) are replaced with subtraction followed by applying XOR with a bitmask that indicates the type of the operation. The bitmasks are 64 bits wide. RV32 implementations only use the lower 32 bits of the bitmasks. The `*W` instructions in RV64 (such as `MULW`) are implemented by adding or subtracting the lower 32 bits of the operands, then XORing with the lower 32 bits of the bitmask, then sign extending the result to 64 bits. #### Integer Multiply/Divide Instructions | Operation | Add/Sub | Bitmask | |:----------|:--------:|:------------------:| | MUL | Add | 0x2cdf52a55876063e | | MULH | Add | 0x15d01651f6583fb7 | | MULHSU | Sub | 0xea3969edecfbe137 | | MULHU | Add | 0xd13db50d949ce5e8 | | DIV | Sub | 0x29bbf66f7f8529ec | | DIVU | Sub | 0x8c629acb10e8fd70 | | REM | Sub | 0xf5b7d8538da68fa5 | | REMU | Sub | 0xbc4402413138d0e1 | ### Control and Status Registers (CSRs) For each supported CSR there are four additional output ports: output [NRET * XLEN - 1 : 0] rvfi_csr__rmask output [NRET * XLEN - 1 : 0] rvfi_csr__wmask output [NRET * XLEN - 1 : 0] rvfi_csr__rdata output [NRET * XLEN - 1 : 0] rvfi_csr__wdata The `rmask` and `wmask` ports specify which bits of `rdata` and `wdata` are valid. It is always valid for an instruction to activate more `rmask`/`rdata` bits than required by the instruction, as long as the reported bits correctly reflect the machine state. If reading a CSR has side effects, those side effects are not triggered by raised `rmask` bits but by the type of the instruction. The Verilog define `RISCV_FORMAL_CSR_` must be set for each CSR traced via RVFI by the core under test. See [RISC-V Formal CSR Semantics](csrs.md) for the exact semantics of CSR values output via RVFI. ### Handling of Speculative Execution Out-of-order cores that execute speculatively can commit speculative instructions on RVFI. Rollbacks must be output via the rollback interface, that is enabled when `RISCV_FORMAL_ROLLBACK` is defined: output [ 0 : 0] rvfi_rollback_valid output [63 : 0] rvfi_rollback_order All RVFI packets output _prior_ to the cycle with asserted `rvfi_rollback_valid` with a `rvfi_order` field of _greater or equal_ to `rvfi_rollback_order` are invalidated by a rollback event. RVFI packets output in the same cycle as `rvfi_rollback_valid` are already part of the new instruction stream re-starting at the instruction number indicated in `rvfi_rollback_order`. ### Handling of Dynamic Faults Cores where the fault check for an instruction fetch or a data access is determined by an external bus response can signal such faults via RVFI. When `RISCV_FORMAL_MEM_FAULT` is defined, the RVFI interface is extended by the following signal: output [NRET - 1 : 0] rvfi_mem_fault output [NRET * XLEN/8 - 1 : 0] rvfi_mem_fault_rmask output [NRET * XLEN/8 - 1 : 0] rvfi_mem_fault_wmask An instruction fetch that faults sets `rvfi_insn` to all zero and set `rvfi_mem_fault`. A memory access that faults sets `rvfi_mem_fault` and does not signal any register or memory writes. Instead the bytes that would have been accessed (if the access hadn't faulted) are output to `rvfi_mem_fault_rmask` and `rvfi_mem_fault_wmask` instead. The address is still output via `rvfi_mem_addr`. ### Handling of External Memory Busses RISC-V Formal includes several checks that verify consistency properties between memory accesses observed via the RVFI and memory accesses observed on external instruction and/or data busses. To not tie those checks to a specific bus, those checks extend the RVFI with the RVFI_BUS interface. RVFI_BUS consists of further outputs that observe memory accesses on a bus while abstracting over the exact signalling used for the bus. To run these checks, the relevant busses of the core should be connected to an abstraction that implements the required bus signalling but provides unconstrai (This may be relaxed with an extensions )ned responses to the core. The accesses on the bus are then observed and constrained by these checks via the RVFI_BUS outputs. Note: When implementing such an abstraction it should output the access using RVFI_BUS as soon as the access first appears on the bus, even when the reply to the core happens in a later cycle. (Whether this is necessary and how much delay is acceptable depends on the checks performed and on the design of the core and the core's RVFI implementation. Too much delay can cause false positives by preventing the check from properly constraining the RVFI_BUS transfers.) For standard busses the same unconstrained abstractions and RVFI_BUS observers can be re-used for multiple cores. The RVFI_BUS extension can observe multiple busses using multiple RVFI_BUS channels. This is used to model separate data and instruction busses as well as busses that can transfer accesses to several unrelated addresses in the same cycle. The total number of channels is specified using `NBUS` which works like `NRET` for the main RVFI signals. The width of the observed bus is independent of `XLEN` and is specified using `BUSLEN`. If different channels observe busses of a different width, `BUSLEN` should be set to the maximum width in use. RVFI_BUS adds the following ouptuts: output [NBUS * 1 - 1 : 0] rvfi_bus_valid output [NBUS * 1 - 1 : 0] rvfi_bus_insn output [NBUS * 1 - 1 : 0] rvfi_bus_data output [NBUS * 1 - 1 : 0] rvfi_bus_fault output [NBUS * XLEN - 1 : 0] rvfi_bus_addr output [NBUS * BUSLEN/8 - 1 : 0] rvfi_bus_rmask output [NBUS * BUSLEN/8 - 1 : 0] rvfi_bus_wmask output [NBUS * BUSLEN - 1 : 0] rvfi_bus_rdata output [NBUS * BUSLEN - 1 : 0] rvfi_bus_wdata When `rvfi_bus_valid` is set, there is an observed memory access present on the RVFI_BUS channel, otherwise, all other RVFI_BUS outputs are ignored. The outputs `rvfi_bus_insn` and `rvfi_bus_data` are used to indicate whether the access is an instruction fetch or a data access. For cores or busses that do not distinguish between those, both have to be set. The `rvfi_bus_addr` output is the address of the access. The outputs `rvfi_bus_rmask` and `rvfi_bus_wmask` indicate which bytes starting with `rvfi_bus_addr` are accessed. This is used for both, masked writes as well as for outputting busses smaller than `BUSLEN`. Note that when the LSBs of `rvfi_bus_rmask` and `rvfi_bus_wmask` are cleared, `rvfi_bus_addr` may be lower than the first actually accessed byte. The outputs `rvfi_bus_rdata` and `rvfi_bus_wdata` contain the read and written data and are only valid for the bytes corresponding to the respective bits in `rvfi_bus_rmask` and `rvfi_bus_wmask`. All accesses observed using RVFI_BUS are assumed to be in order, including acceses in the same cycle which are ordered by increasing RVFI_BUS channel index. This may be relaxed by future extensions. #### RVFI_BUS observers for standard interfaces The `bus` directory contains implementations RVFI_BUS observers and abstractions for standard interfaces. Note that the observers are passive and do not constrain any signals on their own. That means to test a core in isolation, the core's interface may have to be connected to an abstraction that provides the handshaking that the core expects to properly function without constraining the data or timing beyond that. AXI4 observers and abstractions are provided in `bus/rvfi_bus_axi4.sv`, which also contains some notes about the timing when translating AXI4 into RVFI_BUS signals. RVFI TODOs and Requests for Comments ------------------------------------ The following section contains notes on future extensions to RVFI. They will come part of the spec as soon as there is at least one core that implements the feature, and a matching formal check that utilises the feature. In many cases the additional ports will only be used (and expected from the core) when additional to-be-defined `RISCV_FORMAL_*` Verilog defines are set. ### Support for fused instructions Fused instructions are simply handled as larger instructions in RVFI. Additional `rvfi_rs*` ports (or even `rvfi_rd*` ports) may be added to accommodate the fused instructions. No instruction models for fused instructions have been created yet. Alternatively fused instructions may be output as individual instructions in separate RVFI channels. ### Modelling of Floating-Point State The following is the proposed RVFI extension for floating point ISAs: output [NRET * 5 - 1 : 0] rvfi_frs1_addr output [NRET * 5 - 1 : 0] rvfi_frs2_addr output [NRET * 5 - 1 : 0] rvfi_frs3_addr output [NRET * 5 - 1 : 0] rvfi_frd_addr output [NRET - 1 : 0] rvfi_frs1_rvalid output [NRET - 1 : 0] rvfi_frs2_rvalid output [NRET - 1 : 0] rvfi_frs3_rvalid output [NRET - 1 : 0] rvfi_frd_wvalid output [NRET * FLEN - 1 : 0] rvfi_frs1_rdata output [NRET * FLEN - 1 : 0] rvfi_frs2_rdata output [NRET * FLEN - 1 : 0] rvfi_frs3_rdata output [NRET * FLEN - 1 : 0] rvfi_frd_wdata output [NRET * XLEN - 1 : 0] rvfi_csr_fcsr_rmask output [NRET * XLEN - 1 : 0] rvfi_csr_fcsr_wmask output [NRET * XLEN - 1 : 0] rvfi_csr_fcsr_rdata output [NRET * XLEN - 1 : 0] rvfi_csr_fcsr_wdata Since `f0` is not a zero register, additional `*_[rw]valid` signals are required to indicate if `frs1`, `frs2`, `frs3`, and `frd` and their corresponding pre- or post-values are valid. Alternative arithmetic operations (`RISCV_FORMAL_ALTOPS`) will be defined for all non-trivial floating point operations. ### Modelling of Virtual Memory For processors with support for S-mode and virtual memory we define the following additional RVFI signals for data load/stores: output [NRET * 64 - 1 : 0] rvfi_mem_paddr output [NRET * XLEN - 1 : 0] rvfi_mem_pte0 output [NRET * XLEN - 1 : 0] rvfi_mem_pte1 output [NRET * XLEN - 1 : 0] rvfi_mem_pte2 output [NRET * XLEN - 1 : 0] rvfi_mem_pte3 And the following additional RVFI signals for instruction fetches: output [NRET * 64 - 1 : 0] rvfi_pc_paddr output [NRET * XLEN - 1 : 0] rvfi_pc_pte0 output [NRET * XLEN - 1 : 0] rvfi_pc_pte1 output [NRET * XLEN - 1 : 0] rvfi_pc_pte2 output [NRET * XLEN - 1 : 0] rvfi_pc_pte3 And we require that the `satp` CSR is observable through RVFI: output [NRET * XLEN - 1 : 0] rvfi_csr_satp_rmask output [NRET * XLEN - 1 : 0] rvfi_csr_satp_wmask output [NRET * XLEN - 1 : 0] rvfi_csr_satp_rdata output [NRET * XLEN - 1 : 0] rvfi_csr_satp_wdata The `rvfi_mem_paddr` field carries the physical address of the memory access. The `rvfi_mem_pte[0123]` fields carry the values of the page table entries used to convert `rvfi_mem_addr` to `rvfi_mem_paddr`. Unused `rvfi_mem_pte[0123]` fields must always be set to zero. For memory accesses in M-mode, or with `satp.MODE=0`, `rvfi_mem_paddr` must have the same value as `rvfi_mem_addr` and all four `rvfi_mem_pte[0123]` fields must be set to zero. For example in Sv32 mode, modulo missing fences, `rvfi_mem_pte1` must carry the value of the 32-bit word at the following memory location: ``` pt1 = rvfi_csr_satp_rdata & 0x003fffff vpn1 = (rvfi_mem_addr >> 22) & 0x3ff pte1_addr = (pt1 << 12) | (vpn1 << 2) ``` And `rvfi_mem_pte0` must carry the value of the 32-bit word at the following memory location (or zero if `pte1.X` or `pte1.R` or `!pte1.V`): ``` pt0 = rvfi_mem_pte1 >> 10 vpn0 = (rvfi_mem_addr >> 12) & 0x3ff pte0_addr = (pt0 << 12) | (vpn0 << 2) ``` Finally, `rvfi_mem_paddr` must be set to the following address: ``` ppn = rvfi_mem_pte0 >> 10 offset = rvfi_mem_addr & 0xfff rvfi_mem_paddr = (ppn << 12) | offset ``` ### Modelling of Atomic Memory Operations AMO instructions (`AMOSWAP.W`, etc.) can be modelled using the existing `rvfi_mem_*` interface by asserting bits in both `rvfi_mem_rmask` and `rvfi_mem_wmask`. There is also no extension to the RVFI port necessary to accommodate the `LR`, `SC`, `FENCE` and `FENCE.I` instructions. Verification of this instructions for a single-core systems can be done using the RVFI port only. A strategy must be defined to verify their correct behavior in multicore systems. For atomic instructions with `rd = x0` a core might have no way of knowing the old or new value of the memory location. For those situations we add an additional RVFI output port: output [NRET - 1 : 0] rvfi_mem_extamo When `rvfi_mem_extamo` is set, `rvfi_mem_wdata` carries the `rs2` value used with the atomic instruction instead of the new value in the memory location. `rvfi_mem_rmask` is all-zeros in this case. ### Skipping instructions Consider the following sequence of instructions: .... add t0,t1,t2 beqz t3,label sub t0,t1,t3 label: .... When t3 has a non-zero value the processor could decide not to schedule the add instruction because its value is never going to be used. In this case the processor would be unable to produce a valid RVFI trace for the instruction sequence. An additional signal can be added to RVFI that can be used to mark such instructions: output [NRET - 1 : 0] rvfi_skip When `rvfi_skip` is high the core may output arbitrary data on the `*_rdata` and `*_wdata` ports (excluding `rvfi_pc_rdata` and `rvfi_pc_wdata`). The register values written by such intrustions may only be observed by other skipped instructions. An additional formal proof must be added to check this property. Memory operations (`rvfi_mem_rmask` and/or `rvfi_mem_wmask` are non-zero) can not be skipped. ================================================ FILE: insns/generate.py ================================================ #!/usr/bin/env python3 # # Copyright (C) 2017 Claire Xenia Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. current_isa = [] isa_database = dict() defaults_cache = None MISA_A = 1 << 0 # Atomic MISA_B = 1 << 1 # -reserved- MISA_C = 1 << 2 # Compressed MISA_D = 1 << 3 # Double-precision float MISA_E = 1 << 4 # RV32E base ISA MISA_F = 1 << 5 # Single-precision float MISA_G = 1 << 6 # Additional std extensions MISA_H = 1 << 7 # -reserved- MISA_I = 1 << 8 # RV32I/RV64I/RV128I base ISA MISA_J = 1 << 9 # -reserved- MISA_K = 1 << 10 # -reserved- MISA_L = 1 << 11 # -reserved- MISA_M = 1 << 12 # Muliply/Divide MISA_N = 1 << 13 # User-level interrupts MISA_O = 1 << 14 # -reserved- MISA_P = 1 << 15 # -reserved- MISA_Q = 1 << 16 # Quad-precision float MISA_R = 1 << 17 # -reserved- MISA_S = 1 << 18 # Supervisor mode MISA_T = 1 << 19 # -reserved- MISA_U = 1 << 20 # User mode MISA_V = 1 << 21 # -reserved- MISA_W = 1 << 22 # -reserved- MISA_X = 1 << 23 # Non-std extensions MISA_Y = 1 << 24 # -reserved- MISA_Z = 1 << 25 # -reserved- def header(f, insn, isa_mode=False): if not isa_mode: global isa_database for isa in current_isa: if isa not in isa_database: isa_database[isa] = set() isa_database[isa].add(insn) global defaults_cache defaults_cache = dict() print("// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py", file=f) print("", file=f) if isa_mode: print("module rvfi_isa_%s (" % insn, file=f) else: print("module rvfi_insn_%s (" % insn, file=f) print(" input rvfi_valid,", file=f) print(" input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn,", file=f) print(" input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata,", file=f) print(" input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata,", file=f) print(" input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata,", file=f) print(" input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata,", file=f) print("`ifdef RISCV_FORMAL_CSR_MISA", file=f) print(" input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata,", file=f) print(" output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask,", file=f) print("`endif", file=f) print("", file=f) print(" output spec_valid,", file=f) print(" output spec_trap,", file=f) print(" output [ 4 : 0] spec_rs1_addr,", file=f) print(" output [ 4 : 0] spec_rs2_addr,", file=f) print(" output [ 4 : 0] spec_rd_addr,", file=f) print(" output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata,", file=f) print(" output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata,", file=f) print(" output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr,", file=f) print(" output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,", file=f) print(" output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,", file=f) print(" output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata", file=f) print(");", file=f) defaults_cache["spec_valid"] = "0" defaults_cache["spec_rs1_addr"] = "0" defaults_cache["spec_rs2_addr"] = "0" defaults_cache["spec_rd_addr"] = "0" defaults_cache["spec_rd_wdata"] = "0" defaults_cache["spec_pc_wdata"] = "0" defaults_cache["spec_trap"] = "!misa_ok" defaults_cache["spec_mem_addr"] = "0" defaults_cache["spec_mem_rmask"] = "0" defaults_cache["spec_mem_wmask"] = "0" defaults_cache["spec_mem_wdata"] = "0" def assign(f, sig, val): print(" assign %s = %s;" % (sig, val), file=f) if sig in defaults_cache: del defaults_cache[sig] def misa_check(f, mask, ialign16=False): print("", file=f) print("`ifdef RISCV_FORMAL_CSR_MISA", file=f) print(" wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h %x) == `RISCV_FORMAL_XLEN'h %x;" % (mask, mask), file=f) print(" assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h %x;" % ((mask|MISA_C) if ialign16 else mask), file=f) if ialign16: print(" wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h %x) != `RISCV_FORMAL_XLEN'h 0;" % (MISA_C), file=f) print("`else", file=f) print(" wire misa_ok = 1;", file=f) if ialign16: print("`ifdef RISCV_FORMAL_COMPRESSED", file=f) print(" wire ialign16 = 1;", file=f) print("`else", file=f) print(" wire ialign16 = 0;", file=f) print("`endif", file=f) print("`endif", file=f) def footer(f): def default_assign(sig): if sig in defaults_cache: print(" assign %s = %s;" % (sig, defaults_cache[sig]), file=f) if len(defaults_cache) != 0: print("", file=f) print(" // default assignments", file=f) default_assign("spec_valid") default_assign("spec_rs1_addr") default_assign("spec_rs2_addr") default_assign("spec_rd_addr") default_assign("spec_rd_wdata") default_assign("spec_pc_wdata") default_assign("spec_trap") default_assign("spec_mem_addr") default_assign("spec_mem_rmask") default_assign("spec_mem_wmask") default_assign("spec_mem_wdata") print("endmodule", file=f) def format_r(f): print("", file=f) print(" // R-type instruction format", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;", file=f) print(" wire [6:0] insn_funct7 = rvfi_insn[31:25];", file=f) print(" wire [4:0] insn_rs2 = rvfi_insn[24:20];", file=f) print(" wire [4:0] insn_rs1 = rvfi_insn[19:15];", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[14:12];", file=f) print(" wire [4:0] insn_rd = rvfi_insn[11: 7];", file=f) print(" wire [6:0] insn_opcode = rvfi_insn[ 6: 0];", file=f) def format_ra(f): print("", file=f) print(" // R-type instruction format (atomics variation)", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;", file=f) print(" wire [6:0] insn_funct5 = rvfi_insn[31:27];", file=f) print(" wire insn_aq = rvfi_insn[26];", file=f) print(" wire insn_rl = rvfi_insn[25];", file=f) print(" wire [4:0] insn_rs2 = rvfi_insn[24:20];", file=f) print(" wire [4:0] insn_rs1 = rvfi_insn[19:15];", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[14:12];", file=f) print(" wire [4:0] insn_rd = rvfi_insn[11: 7];", file=f) print(" wire [6:0] insn_opcode = rvfi_insn[ 6: 0];", file=f) def format_i(f): print("", file=f) print(" // I-type instruction format", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);", file=f) print(" wire [4:0] insn_rs1 = rvfi_insn[19:15];", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[14:12];", file=f) print(" wire [4:0] insn_rd = rvfi_insn[11: 7];", file=f) print(" wire [6:0] insn_opcode = rvfi_insn[ 6: 0];", file=f) def format_i_shift(f): print("", file=f) print(" // I-type instruction format (shift variation)", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;", file=f) print(" wire [6:0] insn_funct6 = rvfi_insn[31:26];", file=f) print(" wire [5:0] insn_shamt = rvfi_insn[25:20];", file=f) print(" wire [4:0] insn_rs1 = rvfi_insn[19:15];", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[14:12];", file=f) print(" wire [4:0] insn_rd = rvfi_insn[11: 7];", file=f) print(" wire [6:0] insn_opcode = rvfi_insn[ 6: 0];", file=f) def format_s(f): print("", file=f) print(" // S-type instruction format", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:25], rvfi_insn[11:7]});", file=f) print(" wire [4:0] insn_rs2 = rvfi_insn[24:20];", file=f) print(" wire [4:0] insn_rs1 = rvfi_insn[19:15];", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[14:12];", file=f) print(" wire [6:0] insn_opcode = rvfi_insn[ 6: 0];", file=f) def format_sb(f): print("", file=f) print(" // SB-type instruction format", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0});", file=f) print(" wire [4:0] insn_rs2 = rvfi_insn[24:20];", file=f) print(" wire [4:0] insn_rs1 = rvfi_insn[19:15];", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[14:12];", file=f) print(" wire [6:0] insn_opcode = rvfi_insn[ 6: 0];", file=f) def format_u(f): print("", file=f) print(" // U-type instruction format", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:12], 12'b0});", file=f) print(" wire [4:0] insn_rd = rvfi_insn[11:7];", file=f) print(" wire [6:0] insn_opcode = rvfi_insn[ 6:0];", file=f) def format_uj(f): print("", file=f) print(" // UJ-type instruction format", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[19:12], rvfi_insn[20], rvfi_insn[30:21], 1'b0});", file=f) print(" wire [4:0] insn_rd = rvfi_insn[11:7];", file=f) print(" wire [6:0] insn_opcode = rvfi_insn[6:0];", file=f) def format_cr(f): print("", file=f) print(" // CI-type instruction format", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) print(" wire [3:0] insn_funct4 = rvfi_insn[15:12];", file=f) print(" wire [4:0] insn_rs1_rd = rvfi_insn[11:7];", file=f) print(" wire [4:0] insn_rs2 = rvfi_insn[6:2];", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def format_ci(f): print("", file=f) print(" // CI-type instruction format", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]});", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[15:13];", file=f) print(" wire [4:0] insn_rs1_rd = rvfi_insn[11:7];", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def format_ci_sp(f): print("", file=f) print(" // CI-type instruction format (SP variation)", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[4:3], rvfi_insn[5], rvfi_insn[2], rvfi_insn[6], 4'b0});", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[15:13];", file=f) print(" wire [4:0] insn_rs1_rd = rvfi_insn[11:7];", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def format_ci_lui(f): print("", file=f) print(" // CI-type instruction format (LUI variation)", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2], 12'b0});", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[15:13];", file=f) print(" wire [4:0] insn_rs1_rd = rvfi_insn[11:7];", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def format_ci_sri(f): print("", file=f) print(" // CI-type instruction format (SRI variation)", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) print(" wire [5:0] insn_shamt = {rvfi_insn[12], rvfi_insn[6:2]};", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[15:13];", file=f) print(" wire [1:0] insn_funct2 = rvfi_insn[11:10];", file=f) print(" wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def format_ci_sli(f): print("", file=f) print(" // CI-type instruction format (SLI variation)", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) print(" wire [5:0] insn_shamt = {rvfi_insn[12], rvfi_insn[6:2]};", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[15:13];", file=f) print(" wire [4:0] insn_rs1_rd = rvfi_insn[11:7];", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def format_ci_andi(f): print("", file=f) print(" // CI-type instruction format (ANDI variation)", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]});", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[15:13];", file=f) print(" wire [1:0] insn_funct2 = rvfi_insn[11:10];", file=f) print(" wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def format_ci_lsp(f, numbytes): print("", file=f) print(" // CI-type instruction format (LSP variation, %d bit version)" % (8*numbytes), file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) if numbytes == 4: print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[3:2], rvfi_insn[12], rvfi_insn[6:4], 2'b00};", file=f) elif numbytes == 8: print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[4:2], rvfi_insn[12], rvfi_insn[6:5], 3'b000};", file=f) else: assert False print(" wire [2:0] insn_funct3 = rvfi_insn[15:13];", file=f) print(" wire [4:0] insn_rd = rvfi_insn[11:7];", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def format_cl(f, numbytes): print("", file=f) print(" // CL-type instruction format (%d bit version)" % (8*numbytes), file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) if numbytes == 4: print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[5], rvfi_insn[12:10], rvfi_insn[6], 2'b00};", file=f) elif numbytes == 8: print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[6:5], rvfi_insn[12:10], 3'b000};", file=f) else: assert False print(" wire [2:0] insn_funct3 = rvfi_insn[15:13];", file=f) print(" wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]};", file=f) print(" wire [4:0] insn_rd = {1'b1, rvfi_insn[4:2]};", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def format_css(f, numbytes): print("", file=f) print(" // CSS-type instruction format (%d bit version)" % (8*numbytes), file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) if numbytes == 4: print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[8:7], rvfi_insn[12:9], 2'b00};", file=f) elif numbytes == 8: print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[9:7], rvfi_insn[12:10], 3'b000};", file=f) else: assert False print(" wire [2:0] insn_funct3 = rvfi_insn[15:13];", file=f) print(" wire [4:0] insn_rs2 = rvfi_insn[6:2];", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def format_cs(f, numbytes): print("", file=f) print(" // CS-type instruction format (%d bit version)" % (8*numbytes), file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) if numbytes == 4: print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[5], rvfi_insn[12:10], rvfi_insn[6], 2'b00};", file=f) elif numbytes == 8: print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[6:5], rvfi_insn[12:10], 3'b000};", file=f) else: assert False print(" wire [2:0] insn_funct3 = rvfi_insn[15:13];", file=f) print(" wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]};", file=f) print(" wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]};", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def format_cs_alu(f): print("", file=f) print(" // CS-type instruction format (ALU version)", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) print(" wire [5:0] insn_funct6 = rvfi_insn[15:10];", file=f) print(" wire [1:0] insn_funct2 = rvfi_insn[6:5];", file=f) print(" wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};", file=f) print(" wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]};", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def format_ciw(f): print("", file=f) print(" // CIW-type instruction format", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[10:7], rvfi_insn[12:11], rvfi_insn[5], rvfi_insn[6], 2'b00};", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[15:13];", file=f) print(" wire [4:0] insn_rd = {1'b1, rvfi_insn[4:2]};", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def format_cb(f): print("", file=f) print(" // CB-type instruction format", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:5], rvfi_insn[2], rvfi_insn[11:10], rvfi_insn[4:3], 1'b0});", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[15:13];", file=f) print(" wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]};", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def format_cj(f): print("", file=f) print(" // CJ-type instruction format", file=f) print(" wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[8], rvfi_insn[10], rvfi_insn[9],", file=f) print(" rvfi_insn[6], rvfi_insn[7], rvfi_insn[2], rvfi_insn[11], rvfi_insn[5], rvfi_insn[4], rvfi_insn[3], 1'b0});", file=f) print(" wire [2:0] insn_funct3 = rvfi_insn[15:13];", file=f) print(" wire [1:0] insn_opcode = rvfi_insn[1:0];", file=f) def insn_lui(insn="lui", misa=0): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_u(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_opcode == 7'b 0110111") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? insn_imm : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") footer(f) def insn_auipc(insn="auipc", misa=0): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_u(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_opcode == 7'b 0010111") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? rvfi_pc_rdata + insn_imm : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") footer(f) def insn_jal(insn="jal", misa=0): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_uj(f) misa_check(f, misa, ialign16=True) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_pc_rdata + insn_imm;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_opcode == 7'b 1101111") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? rvfi_pc_rdata + 4 : 0") assign(f, "spec_pc_wdata", "next_pc") assign(f, "spec_trap", "(ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok") footer(f) def insn_jalr(insn="jalr", misa=0): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_i(f) misa_check(f, misa, ialign16=True) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] next_pc = (rvfi_rs1_rdata + insn_imm) & ~1;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 1100111") assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? rvfi_pc_rdata + 4 : 0") assign(f, "spec_pc_wdata", "next_pc") assign(f, "spec_trap", "(ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok") footer(f) def insn_b(insn, funct3, expr, misa=0): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_sb(f) misa_check(f, misa, ialign16=True) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire cond = %s;" % expr, file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 4;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 7'b 1100011" % funct3) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rs2_addr", "insn_rs2") assign(f, "spec_pc_wdata", "next_pc") assign(f, "spec_trap", "(ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok") footer(f) def insn_l(insn, funct3, numbytes, signext, misa=0): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_i(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print("`ifdef RISCV_FORMAL_ALIGNED_MEM", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;", file=f) print(" wire [%d:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));" % (8*numbytes-1), file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 7'b 0000011" % funct3) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_mem_addr", "addr & ~(`RISCV_FORMAL_XLEN/8-1)") assign(f, "spec_mem_rmask", "((1 << %d)-1) << (addr-spec_mem_addr)" % numbytes) if signext: assign(f, "spec_rd_wdata", "spec_rd_addr ? $signed(result) : 0") else: assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") assign(f, "spec_trap", "((addr & (%d-1)) != 0) || !misa_ok" % numbytes) print("`else", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;", file=f) print(" wire [%d:0] result = rvfi_mem_rdata;" % (8*numbytes-1), file=f) assign(f, "spec_valid", "rvfi_valid && insn_funct3 == 3'b %s && insn_opcode == 7'b 0000011" % funct3) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_mem_addr", "addr") assign(f, "spec_mem_rmask", "((1 << %d)-1)" % numbytes) if signext: assign(f, "spec_rd_wdata", "spec_rd_addr ? $signed(result) : 0") else: assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") assign(f, "spec_trap", "!misa_ok") print("`endif", file=f) footer(f) def insn_s(insn, funct3, numbytes, misa=0): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_s(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print("`ifdef RISCV_FORMAL_ALIGNED_MEM", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 7'b 0100011" % funct3) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rs2_addr", "insn_rs2") assign(f, "spec_mem_addr", "addr & ~(`RISCV_FORMAL_XLEN/8-1)") assign(f, "spec_mem_wmask", "((1 << %d)-1) << (addr-spec_mem_addr)" % numbytes) assign(f, "spec_mem_wdata", "rvfi_rs2_rdata << (8*(addr-spec_mem_addr))") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") assign(f, "spec_trap", "((addr & (%d-1)) != 0) || !misa_ok" % numbytes) print("`else", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 7'b 0100011" % funct3) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rs2_addr", "insn_rs2") assign(f, "spec_mem_addr", "addr") assign(f, "spec_mem_wmask", "((1 << %d)-1)" % numbytes) assign(f, "spec_mem_wdata", "rvfi_rs2_rdata") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") assign(f, "spec_trap", "!misa_ok") print("`endif", file=f) footer(f) def insn_imm(insn, funct3, expr, wmode=False, misa=0): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_i(f) misa_check(f, misa) if wmode: result_range = "31:0" opcode = "0011011" else: result_range = "`RISCV_FORMAL_XLEN-1:0" opcode = "0010011" print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [%s] result = %s;" % (result_range, expr), file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 7'b %s" % (funct3, opcode)) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rd_addr", "insn_rd") if wmode: assign(f, "spec_rd_wdata", "spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0") else: assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") footer(f) def insn_shimm(insn, funct6, funct3, expr, wmode=False, misa=0): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_i_shift(f) misa_check(f, misa) if wmode: xtra_shamt_check = "!insn_shamt[5]" result_range = "31:0" opcode = "0011011" else: xtra_shamt_check = "(!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64)" result_range = "`RISCV_FORMAL_XLEN-1:0" opcode = "0010011" print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [%s] result = %s;" % (result_range, expr), file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct6 == 6'b %s && insn_funct3 == 3'b %s && insn_opcode == 7'b %s && %s" % (funct6, funct3, opcode, xtra_shamt_check)) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rd_addr", "insn_rd") if wmode: assign(f, "spec_rd_wdata", "spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0") else: assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") footer(f) def insn_alu(insn, funct7, funct3, expr, alt_add=None, alt_sub=None, shamt=False, wmode=False, misa=0): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_r(f) misa_check(f, misa) if wmode: result_range = "31:0" opcode = "0111011" else: result_range = "`RISCV_FORMAL_XLEN-1:0" opcode = "0110011" print("", file=f) print(" // %s instruction" % insn.upper(), file=f) if shamt: if wmode: print(" wire [4:0] shamt = rvfi_rs2_rdata[4:0];", file=f) else: print(" wire [5:0] shamt = `RISCV_FORMAL_XLEN == 64 ? rvfi_rs2_rdata[5:0] : rvfi_rs2_rdata[4:0];", file=f) if alt_add is not None or alt_sub is not None: print("`ifdef RISCV_FORMAL_ALTOPS", file=f) if alt_add is not None: print(" wire [%s] altops_bitmask = 64'h%016x;" % (result_range, alt_add), file=f) print(" wire [%s] result = (rvfi_rs1_rdata + rvfi_rs2_rdata) ^ altops_bitmask;" % result_range, file=f) else: print(" wire [%s] altops_bitmask = 64'h%016x;" % (result_range, alt_sub), file=f) print(" wire [%s] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask;" % result_range, file=f) print("`else", file=f) print(" wire [%s] result = %s;" % (result_range, expr), file=f) print("`endif", file=f) else: print(" wire [%s] result = %s;" % (result_range, expr), file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct7 == 7'b %s && insn_funct3 == 3'b %s && insn_opcode == 7'b %s" % (funct7, funct3, opcode)) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rs2_addr", "insn_rs2") assign(f, "spec_rd_addr", "insn_rd") if wmode: assign(f, "spec_rd_wdata", "spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0") else: assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") footer(f) def insn_amo(insn, funct5, funct3, expr, misa=MISA_A): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_ra(f) misa_check(f, misa) if funct3 == "010": oprange = "31:0" numbytes = 4 else: oprange = "63:0" numbytes = 8 print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [%s] mem_result = %s;" % (oprange, expr), file=f) print(" wire [%s] reg_result = rvfi_mem_rdata[%s];" % (oprange, oprange), file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata;", file=f) print("`ifdef RISCV_FORMAL_ALIGNED_MEM", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct5 == 5'b %s && insn_funct3 == 3'b %s && insn_opcode == 7'b 0101111" % (funct5, funct3)) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rs2_addr", "insn_rs2") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? $signed(reg_result) : 0") assign(f, "spec_mem_addr", "addr & ~(`RISCV_FORMAL_XLEN/8-1)") assign(f, "spec_mem_wmask", "((1 << %d)-1) << (addr-spec_mem_addr)" % numbytes) assign(f, "spec_mem_wdata", "mem_result << (8*(addr-spec_mem_addr))") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") assign(f, "spec_trap", "((addr & (%d-1)) != 0) || !misa_ok" % numbytes) print("`else", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct5 == 5'b %s && insn_funct3 == 3'b %s && insn_opcode == 7'b 0101111" % (funct5, funct3)) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rs2_addr", "insn_rs2") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? $signed(reg_result) : 0") assign(f, "spec_mem_addr", "addr") assign(f, "spec_mem_wmask", "((1 << %d)-1)" % numbytes) assign(f, "spec_mem_wdata", "mem_result") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 4") assign(f, "spec_trap", "((addr & (%d-1)) != 0) || !misa_ok" % numbytes) print("`endif", file=f) footer(f) def insn_c_addi4spn(insn="c_addi4spn", misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_ciw(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 00 && insn_imm") assign(f, "spec_rs1_addr", "2") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") footer(f) def insn_c_l(insn, funct3, numbytes, signext, misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_cl(f, numbytes) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print("`ifdef RISCV_FORMAL_ALIGNED_MEM", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;", file=f) print(" wire [%d:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));" % (8*numbytes-1), file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 00" % funct3) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_mem_addr", "addr & ~(`RISCV_FORMAL_XLEN/8-1)") assign(f, "spec_mem_rmask", "((1 << %d)-1) << (addr-spec_mem_addr)" % numbytes) if signext: assign(f, "spec_rd_wdata", "spec_rd_addr ? $signed(result) : 0") else: assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") assign(f, "spec_trap", "((addr & (%d-1)) != 0) || !misa_ok" % numbytes) print("`else", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;", file=f) print(" wire [%d:0] result = rvfi_mem_rdata;" % (8*numbytes-1), file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 00" % funct3) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_mem_addr", "addr") assign(f, "spec_mem_rmask", "((1 << %d)-1)" % numbytes) if signext: assign(f, "spec_rd_wdata", "spec_rd_addr ? $signed(result) : 0") else: assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") assign(f, "spec_trap", "!misa_ok") print("`endif", file=f) footer(f) def insn_c_s(insn, funct3, numbytes, misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_cs(f, numbytes) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;", file=f) print("`ifdef RISCV_FORMAL_ALIGNED_MEM", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 00" % funct3) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rs2_addr", "insn_rs2") assign(f, "spec_mem_addr", "addr & ~(`RISCV_FORMAL_XLEN/8-1)") assign(f, "spec_mem_wmask", "((1 << %d)-1) << (addr-spec_mem_addr)" % numbytes) assign(f, "spec_mem_wdata", "rvfi_rs2_rdata << (8*(addr-spec_mem_addr))") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") assign(f, "spec_trap", "((addr & (%d-1)) != 0) || !misa_ok" % numbytes) print("`else", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 00" % funct3) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_rs2_addr", "insn_rs2") assign(f, "spec_mem_addr", "addr") assign(f, "spec_mem_wmask", "((1 << %d)-1)" % numbytes) assign(f, "spec_mem_wdata", "rvfi_rs2_rdata") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") assign(f, "spec_trap", "!misa_ok") print("`endif", file=f) footer(f) def insn_c_addi(insn="c_addi", wmode=False, misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_ci(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) if wmode: print(" wire [31:0] result = rvfi_rs1_rdata[31:0] + insn_imm[31:0];", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 2'b 01 && insn_rs1_rd != 5'd 0") else: print(" wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 01") assign(f, "spec_rs1_addr", "insn_rs1_rd") assign(f, "spec_rd_addr", "insn_rs1_rd") if wmode: assign(f, "spec_rd_wdata", "spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0") else: assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") footer(f) def insn_c_jal(insn, funct3, link, misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_cj(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_pc_rdata + insn_imm;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 01" % (funct3)) if link: assign(f, "spec_rd_addr", "5'd 1") assign(f, "spec_rd_wdata", "rvfi_pc_rdata + 2") assign(f, "spec_pc_wdata", "next_pc") footer(f) def insn_c_li(insn="c_li", misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_ci(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] result = insn_imm;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 2'b 01") assign(f, "spec_rd_addr", "insn_rs1_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") footer(f) def insn_c_addi16sp(insn="c_addi16sp", misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_ci_sp(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 01 && insn_rs1_rd == 5'd 2 && insn_imm") assign(f, "spec_rs1_addr", "insn_rs1_rd") assign(f, "spec_rd_addr", "insn_rs1_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") footer(f) def insn_c_lui(insn="c_lui", misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_ci_lui(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] result = insn_imm;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 01 && insn_rs1_rd != 5'd 2 && insn_imm") assign(f, "spec_rd_addr", "insn_rs1_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") footer(f) def insn_c_sri(insn, funct2, expr, misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_ci_sri(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] result = %s;" % expr, file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_funct2 == 2'b %s && insn_opcode == 2'b 01 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64)" % funct2) assign(f, "spec_rs1_addr", "insn_rs1_rd") assign(f, "spec_rd_addr", "insn_rs1_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") footer(f) def insn_c_andi(insn="c_andi", misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_ci_andi(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & insn_imm;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_funct2 == 2'b 10 && insn_opcode == 2'b 01") assign(f, "spec_rs1_addr", "insn_rs1_rd") assign(f, "spec_rd_addr", "insn_rs1_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") footer(f) def insn_c_alu(insn, funct6, funct2, expr, wmode=False, misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_cs_alu(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) if wmode: print(" wire [31:0] result = %s;" % expr, file=f) else: print(" wire [`RISCV_FORMAL_XLEN-1:0] result = %s;" % expr, file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct6 == 6'b %s && insn_funct2 == 2'b %s && insn_opcode == 2'b 01" % (funct6, funct2)) assign(f, "spec_rs1_addr", "insn_rs1_rd") assign(f, "spec_rs2_addr", "insn_rs2") assign(f, "spec_rd_addr", "insn_rs1_rd") if wmode: assign(f, "spec_rd_wdata", "spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0") else: assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") footer(f) def insn_c_b(insn, funct3, expr, misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_cb(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire cond = %s;" % expr, file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 2;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 01" % funct3) assign(f, "spec_rs1_addr", "insn_rs1") assign(f, "spec_pc_wdata", "next_pc") assign(f, "spec_trap", "(next_pc[0] != 0) || !misa_ok") footer(f) def insn_c_sli(insn, expr, misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_ci_sli(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] result = %s;" % expr, file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 10 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64)") assign(f, "spec_rs1_addr", "insn_rs1_rd") assign(f, "spec_rd_addr", "insn_rs1_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") footer(f) def insn_c_lsp(insn, funct3, numbytes, signext, misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_ci_lsp(f, numbytes) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print("`ifdef RISCV_FORMAL_ALIGNED_MEM", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;", file=f) print(" wire [%d:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));" % (8*numbytes-1), file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 10 && insn_rd" % funct3) assign(f, "spec_rs1_addr", "2") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_mem_addr", "addr & ~(`RISCV_FORMAL_XLEN/8-1)") assign(f, "spec_mem_rmask", "((1 << %d)-1) << (addr-spec_mem_addr)" % numbytes) if signext: assign(f, "spec_rd_wdata", "spec_rd_addr ? $signed(result) : 0") else: assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") assign(f, "spec_trap", "((addr & (%d-1)) != 0) || !misa_ok" % numbytes) print("`else", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;", file=f) print(" wire [%d:0] result = rvfi_mem_rdata;" % (8*numbytes-1), file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 10 && insn_rd" % funct3) assign(f, "spec_rs1_addr", "2") assign(f, "spec_rd_addr", "insn_rd") assign(f, "spec_mem_addr", "addr") assign(f, "spec_mem_rmask", "((1 << %d)-1)" % numbytes) if signext: assign(f, "spec_rd_wdata", "spec_rd_addr ? $signed(result) : 0") else: assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") assign(f, "spec_trap", "!misa_ok") print("`endif", file=f) footer(f) def insn_c_ssp(insn, funct3, numbytes, misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_css(f, numbytes) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print("`ifdef RISCV_FORMAL_ALIGNED_MEM", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 10" % funct3) assign(f, "spec_rs1_addr", "2") assign(f, "spec_rs2_addr", "insn_rs2") assign(f, "spec_mem_addr", "addr & ~(`RISCV_FORMAL_XLEN/8-1)") assign(f, "spec_mem_wmask", "((1 << %d)-1) << (addr-spec_mem_addr)" % numbytes) assign(f, "spec_mem_wdata", "rvfi_rs2_rdata << (8*(addr-spec_mem_addr))") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") assign(f, "spec_trap", "((addr & (%d-1)) != 0) || !misa_ok" % numbytes) print("`else", file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 10" % funct3) assign(f, "spec_rs1_addr", "2") assign(f, "spec_rs2_addr", "insn_rs2") assign(f, "spec_mem_addr", "addr") assign(f, "spec_mem_wmask", "((1 << %d)-1)" % numbytes) assign(f, "spec_mem_wdata", "rvfi_rs2_rdata") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") assign(f, "spec_trap", "!misa_ok") print("`endif", file=f) footer(f) def insn_c_jalr(insn, funct4, link, misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_cr(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) print(" wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_rs1_rdata & ~1;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct4 == 4'b %s && insn_rs1_rd && !insn_rs2 && insn_opcode == 2'b 10" % funct4) assign(f, "spec_rs1_addr", "insn_rs1_rd") if link: assign(f, "spec_rd_addr", "5'd 1") assign(f, "spec_rd_wdata", "rvfi_pc_rdata + 2") assign(f, "spec_pc_wdata", "next_pc") assign(f, "spec_trap", "(next_pc[0] != 0) || !misa_ok") footer(f) def insn_c_mvadd(insn, funct4, add, misa=MISA_C): with open("insn_%s.v" % insn, "w") as f: header(f, insn) format_cr(f) misa_check(f, misa) print("", file=f) print(" // %s instruction" % insn.upper(), file=f) if add: print(" wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + rvfi_rs2_rdata;", file=f) else: print(" wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata;", file=f) assign(f, "spec_valid", "rvfi_valid && !insn_padding && insn_funct4 == 4'b %s && insn_rs2 && insn_opcode == 2'b 10" % funct4) if add: assign(f, "spec_rs1_addr", "insn_rs1_rd") assign(f, "spec_rs2_addr", "insn_rs2") assign(f, "spec_rd_addr", "insn_rs1_rd") assign(f, "spec_rd_wdata", "spec_rd_addr ? result : 0") assign(f, "spec_pc_wdata", "rvfi_pc_rdata + 2") footer(f) ## Base Integer ISA (I) current_isa = ["rv32i"] insn_lui() insn_auipc() insn_jal() insn_jalr() insn_b("beq", "000", "rvfi_rs1_rdata == rvfi_rs2_rdata") insn_b("bne", "001", "rvfi_rs1_rdata != rvfi_rs2_rdata") insn_b("blt", "100", "$signed(rvfi_rs1_rdata) < $signed(rvfi_rs2_rdata)") insn_b("bge", "101", "$signed(rvfi_rs1_rdata) >= $signed(rvfi_rs2_rdata)") insn_b("bltu", "110", "rvfi_rs1_rdata < rvfi_rs2_rdata") insn_b("bgeu", "111", "rvfi_rs1_rdata >= rvfi_rs2_rdata") insn_l("lb", "000", 1, True) insn_l("lh", "001", 2, True) insn_l("lw", "010", 4, True) insn_l("lbu", "100", 1, False) insn_l("lhu", "101", 2, False) insn_s("sb", "000", 1) insn_s("sh", "001", 2) insn_s("sw", "010", 4) insn_imm("addi", "000", "rvfi_rs1_rdata + insn_imm") insn_imm("slti", "010", "$signed(rvfi_rs1_rdata) < $signed(insn_imm)") insn_imm("sltiu", "011", "rvfi_rs1_rdata < insn_imm") insn_imm("xori", "100", "rvfi_rs1_rdata ^ insn_imm") insn_imm("ori", "110", "rvfi_rs1_rdata | insn_imm") insn_imm("andi", "111", "rvfi_rs1_rdata & insn_imm") insn_shimm("slli", "000000", "001", "rvfi_rs1_rdata << insn_shamt") insn_shimm("srli", "000000", "101", "rvfi_rs1_rdata >> insn_shamt") insn_shimm("srai", "010000", "101", "$signed(rvfi_rs1_rdata) >>> insn_shamt") insn_alu("add", "0000000", "000", "rvfi_rs1_rdata + rvfi_rs2_rdata") insn_alu("sub", "0100000", "000", "rvfi_rs1_rdata - rvfi_rs2_rdata") insn_alu("sll", "0000000", "001", "rvfi_rs1_rdata << shamt", shamt=True) insn_alu("slt", "0000000", "010", "$signed(rvfi_rs1_rdata) < $signed(rvfi_rs2_rdata)") insn_alu("sltu", "0000000", "011", "rvfi_rs1_rdata < rvfi_rs2_rdata") insn_alu("xor", "0000000", "100", "rvfi_rs1_rdata ^ rvfi_rs2_rdata") insn_alu("srl", "0000000", "101", "rvfi_rs1_rdata >> shamt", shamt=True) insn_alu("sra", "0100000", "101", "$signed(rvfi_rs1_rdata) >>> shamt", shamt=True) insn_alu("or", "0000000", "110", "rvfi_rs1_rdata | rvfi_rs2_rdata") insn_alu("and", "0000000", "111", "rvfi_rs1_rdata & rvfi_rs2_rdata") current_isa = ["rv64i"] insn_l("lwu", "110", 4, False) insn_l("ld", "011", 8, True) insn_s("sd", "011", 8) insn_imm("addiw", "000", "rvfi_rs1_rdata[31:0] + insn_imm[31:0]", wmode=True) insn_shimm("slliw", "000000", "001", "rvfi_rs1_rdata[31:0] << insn_shamt", wmode=True) insn_shimm("srliw", "000000", "101", "rvfi_rs1_rdata[31:0] >> insn_shamt", wmode=True) insn_shimm("sraiw", "010000", "101", "$signed(rvfi_rs1_rdata[31:0]) >>> insn_shamt", wmode=True) insn_alu("addw", "0000000", "000", "rvfi_rs1_rdata[31:0] + rvfi_rs2_rdata[31:0]", wmode=True) insn_alu("subw", "0100000", "000", "rvfi_rs1_rdata[31:0] - rvfi_rs2_rdata[31:0]", wmode=True) insn_alu("sllw", "0000000", "001", "rvfi_rs1_rdata[31:0] << shamt", shamt=True, wmode=True) insn_alu("srlw", "0000000", "101", "rvfi_rs1_rdata[31:0] >> shamt", shamt=True, wmode=True) insn_alu("sraw", "0100000", "101", "$signed(rvfi_rs1_rdata[31:0]) >>> shamt", shamt=True, wmode=True) ## Multiply/Divide ISA (M) current_isa = ["rv32im"] insn_alu("mul", "0000001", "000", "rvfi_rs1_rdata * rvfi_rs2_rdata", alt_add=0x2cdf52a55876063e, misa=MISA_M) insn_alu("mulh", "0000001", "001", "({{`RISCV_FORMAL_XLEN{rvfi_rs1_rdata[`RISCV_FORMAL_XLEN-1]}}, rvfi_rs1_rdata} *\n" + "\t\t{{`RISCV_FORMAL_XLEN{rvfi_rs2_rdata[`RISCV_FORMAL_XLEN-1]}}, rvfi_rs2_rdata}) >> `RISCV_FORMAL_XLEN", alt_add=0x15d01651f6583fb7, misa=MISA_M) insn_alu("mulhsu", "0000001", "010", "({{`RISCV_FORMAL_XLEN{rvfi_rs1_rdata[`RISCV_FORMAL_XLEN-1]}}, rvfi_rs1_rdata} *\n" + "\t\t{`RISCV_FORMAL_XLEN'b0, rvfi_rs2_rdata}) >> `RISCV_FORMAL_XLEN", alt_sub=0xea3969edecfbe137, misa=MISA_M) insn_alu("mulhu", "0000001", "011", "({`RISCV_FORMAL_XLEN'b0, rvfi_rs1_rdata} * {`RISCV_FORMAL_XLEN'b0, rvfi_rs2_rdata}) >> `RISCV_FORMAL_XLEN", alt_add=0xd13db50d949ce5e8, misa=MISA_M) insn_alu("div", "0000001", "100", """rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? {`RISCV_FORMAL_XLEN{1'b1}} : rvfi_rs1_rdata == {1'b1, {`RISCV_FORMAL_XLEN-1{1'b0}}} && rvfi_rs2_rdata == {`RISCV_FORMAL_XLEN{1'b1}} ? {1'b1, {`RISCV_FORMAL_XLEN-1{1'b0}}} : $signed(rvfi_rs1_rdata) / $signed(rvfi_rs2_rdata)""", alt_sub=0x29bbf66f7f8529ec, misa=MISA_M) insn_alu("divu", "0000001", "101", """rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? {`RISCV_FORMAL_XLEN{1'b1}} : rvfi_rs1_rdata / rvfi_rs2_rdata""", alt_sub=0x8c629acb10e8fd70, misa=MISA_M) insn_alu("rem", "0000001", "110", """rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? rvfi_rs1_rdata : rvfi_rs1_rdata == {1'b1, {`RISCV_FORMAL_XLEN-1{1'b0}}} && rvfi_rs2_rdata == {`RISCV_FORMAL_XLEN{1'b1}} ? {`RISCV_FORMAL_XLEN{1'b0}} : $signed(rvfi_rs1_rdata) % $signed(rvfi_rs2_rdata)""", alt_sub=0xf5b7d8538da68fa5, misa=MISA_M) insn_alu("remu", "0000001", "111", """rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? rvfi_rs1_rdata : rvfi_rs1_rdata % rvfi_rs2_rdata""", alt_sub=0xbc4402413138d0e1, misa=MISA_M) current_isa = ["rv64im"] insn_alu("mulw", "0000001", "000", "rvfi_rs1_rdata[31:0] * rvfi_rs2_rdata[31:0]", alt_add=0x2cdf52a55876063e, wmode=True, misa=MISA_M) insn_alu("divw", "0000001", "100", """rvfi_rs2_rdata[31:0] == 32'b0 ? {32{1'b1}} : rvfi_rs1_rdata == {1'b1, {31{1'b0}}} && rvfi_rs2_rdata == {32{1'b1}} ? {1'b1, {31{1'b0}}} : $signed(rvfi_rs1_rdata[31:0]) / $signed(rvfi_rs2_rdata[31:0])""", alt_sub=0x29bbf66f7f8529ec, wmode=True, misa=MISA_M) insn_alu("divuw", "0000001", "101", """rvfi_rs2_rdata[31:0] == 32'b0 ? {32{1'b1}} : rvfi_rs1_rdata[31:0] / rvfi_rs2_rdata[31:0]""", alt_sub=0x8c629acb10e8fd70, wmode=True, misa=MISA_M) insn_alu("remw", "0000001", "110", """rvfi_rs2_rdata == 32'b0 ? rvfi_rs1_rdata : rvfi_rs1_rdata == {1'b1, {31{1'b0}}} && rvfi_rs2_rdata == {32{1'b1}} ? {32{1'b0}} : $signed(rvfi_rs1_rdata[31:0]) % $signed(rvfi_rs2_rdata[31:0])""", alt_sub=0xf5b7d8538da68fa5, wmode=True, misa=MISA_M) insn_alu("remuw", "0000001", "111", """rvfi_rs2_rdata == 32'b0 ? rvfi_rs1_rdata : rvfi_rs1_rdata[31:0] % rvfi_rs2_rdata[31:0]""", alt_sub=0xbc4402413138d0e1, wmode=True, misa=MISA_M) ## Atomics ISA (A) # current_isa = ["rv32ia"] # FIXME: LR.W / SC.W # insn_amo("amoswap_w", "00001", "010", "rvfi_rs2_rdata[31:0]") # insn_amo("amoadd_w", "00000", "010", "rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : rvfi_mem_rdata + rvfi_rs2_rdata[31:0]") # insn_amo("amoxor_w", "00100", "010", "rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : rvfi_mem_rdata ^ rvfi_rs2_rdata[31:0]") # insn_amo("amoand_w", "01100", "010", "rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : rvfi_mem_rdata & rvfi_rs2_rdata[31:0]") # insn_amo("amoor_w", "01000", "010", "rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : rvfi_mem_rdata | rvfi_rs2_rdata[31:0]") # insn_amo("amomin_w", "10000", "010", "rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : ($signed(rvfi_mem_rdata) < $signed(rvfi_rs2_rdata[31:0]) ? rvfi_mem_rdata : rvfi_rs2_rdata[31:0])") # insn_amo("amomax_w", "10100", "010", "rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : ($signed(rvfi_mem_rdata) > $signed(rvfi_rs2_rdata[31:0]) ? rvfi_mem_rdata : rvfi_rs2_rdata[31:0])") # insn_amo("amominu_w", "11000", "010", "rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : (rvfi_mem_rdata < rvfi_rs2_rdata[31:0] ? rvfi_mem_rdata : rvfi_rs2_rdata[31:0])") # insn_amo("amomaxu_w", "11100", "010", "rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : (rvfi_mem_rdata > rvfi_rs2_rdata[31:0] ? rvfi_mem_rdata : rvfi_rs2_rdata[31:0])") # current_isa = ["rv64ia"] # FIXME: LR.D / SC.D # insn_amo("amoswap_d", "00001", "011", "rvfi_rs2_rdata[63:0]") # insn_amo("amoadd_d", "00000", "011", "rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : rvfi_mem_rdata + rvfi_rs2_rdata[63:0]") # insn_amo("amoxor_d", "00100", "011", "rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : rvfi_mem_rdata ^ rvfi_rs2_rdata[63:0]") # insn_amo("amoand_d", "01100", "011", "rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : rvfi_mem_rdata & rvfi_rs2_rdata[63:0]") # insn_amo("amoor_d", "01000", "011", "rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : rvfi_mem_rdata | rvfi_rs2_rdata[63:0]") # insn_amo("amomin_d", "10000", "011", "rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : ($signed(rvfi_mem_rdata) < $signed(rvfi_rs2_rdata[63:0]) ? rvfi_mem_rdata : rvfi_rs2_rdata[63:0])") # insn_amo("amomax_d", "10100", "011", "rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : ($signed(rvfi_mem_rdata) > $signed(rvfi_rs2_rdata[63:0]) ? rvfi_mem_rdata : rvfi_rs2_rdata[63:0])") # insn_amo("amominu_d", "11000", "011", "rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : (rvfi_mem_rdata < rvfi_rs2_rdata[63:0] ? rvfi_mem_rdata : rvfi_rs2_rdata[63:0])") # insn_amo("amomaxu_d", "11100", "011", "rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : (rvfi_mem_rdata > rvfi_rs2_rdata[63:0] ? rvfi_mem_rdata : rvfi_rs2_rdata[63:0])") ## Compressed Integer ISA (IC) current_isa = ["rv32ic"] insn_c_addi4spn() insn_c_l("c_lw", "010", 4, True) insn_c_s("c_sw", "110", 4) insn_c_addi() insn_c_jal("c_jal", "001", True) insn_c_li() insn_c_addi16sp() insn_c_lui() insn_c_sri("c_srli", "00", "rvfi_rs1_rdata >> insn_shamt") insn_c_sri("c_srai", "01", "$signed(rvfi_rs1_rdata) >>> insn_shamt") insn_c_andi() insn_c_alu("c_sub", "100011", "00", "rvfi_rs1_rdata - rvfi_rs2_rdata") insn_c_alu("c_xor", "100011", "01", "rvfi_rs1_rdata ^ rvfi_rs2_rdata") insn_c_alu("c_or", "100011", "10", "rvfi_rs1_rdata | rvfi_rs2_rdata") insn_c_alu("c_and", "100011", "11", "rvfi_rs1_rdata & rvfi_rs2_rdata") insn_c_jal("c_j", "101", False) insn_c_b("c_beqz", "110", "rvfi_rs1_rdata == 0") insn_c_b("c_bnez", "111", "rvfi_rs1_rdata != 0") insn_c_sli("c_slli", "rvfi_rs1_rdata << insn_shamt") insn_c_lsp("c_lwsp", "010", 4, True) insn_c_jalr("c_jr", "1000", False) insn_c_mvadd("c_mv", "1000", False) insn_c_jalr("c_jalr", "1001", True) insn_c_mvadd("c_add", "1001", True) insn_c_ssp("c_swsp", "110", 4) current_isa = ["rv64ic"] insn_c_addi("c_addiw", wmode=True) insn_c_alu("c_subw", "100111", "00", "rvfi_rs1_rdata[31:0] - rvfi_rs2_rdata[31:0]", wmode=True) insn_c_alu("c_addw", "100111", "01", "rvfi_rs1_rdata[31:0] + rvfi_rs2_rdata[31:0]", wmode=True) insn_c_l("c_ld", "011", 8, True) insn_c_s("c_sd", "111", 8) insn_c_lsp("c_ldsp", "011", 8, True) insn_c_ssp("c_sdsp", "111", 8) ## ISA Propagate def isa_propagate_pair(from_isa, to_isa): global isa_database assert from_isa in isa_database if to_isa not in isa_database: isa_database[to_isa] = set() isa_database[to_isa] |= isa_database[from_isa] def isa_propagate(suffix): for i in range(2 ** len(suffix)): src = "" for k in range(len(suffix)): if ((i >> k) & 1) == 0: src += suffix[k] if src != suffix: isa_propagate_pair("rv32i"+src, "rv32i"+suffix) isa_propagate_pair("rv64i"+src, "rv64i"+suffix) isa_propagate_pair("rv32i"+suffix, "rv64i"+suffix) isa_propagate("") isa_propagate("c") isa_propagate("m") isa_propagate("mc") ## ISA Fixup for isa, insns in isa_database.items(): if isa.startswith("rv64"): insns.discard("c_jal") ## ISA Listings and ISA Models for isa, insns in isa_database.items(): with open("isa_%s.txt" % isa, "w") as f: for insn in sorted(insns): print(insn, file=f) with open("isa_%s.v" % isa, "w") as f: header(f, isa, isa_mode=True) for insn in sorted(insns): print(" wire spec_insn_%s_valid;" % insn, file=f) print(" wire spec_insn_%s_trap;" % insn, file=f) print(" wire [ 4 : 0] spec_insn_%s_rs1_addr;" % insn, file=f) print(" wire [ 4 : 0] spec_insn_%s_rs2_addr;" % insn, file=f) print(" wire [ 4 : 0] spec_insn_%s_rd_addr;" % insn, file=f) print(" wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_%s_rd_wdata;" % insn, file=f) print(" wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_%s_pc_wdata;" % insn, file=f) print(" wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_%s_mem_addr;" % insn, file=f) print(" wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_%s_mem_rmask;" % insn, file=f) print(" wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_%s_mem_wmask;" % insn, file=f) print(" wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_%s_mem_wdata;" % insn, file=f) print("`ifdef RISCV_FORMAL_CSR_MISA", file=f) print(" wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_%s_csr_misa_rmask;" % insn, file=f) print("`endif", file=f) print("", file=f) print(" rvfi_insn_%s insn_%s (" % (insn, insn), file=f) print(" .rvfi_valid(rvfi_valid),", file=f) print(" .rvfi_insn(rvfi_insn),", file=f) print(" .rvfi_pc_rdata(rvfi_pc_rdata),", file=f) print(" .rvfi_rs1_rdata(rvfi_rs1_rdata),", file=f) print(" .rvfi_rs2_rdata(rvfi_rs2_rdata),", file=f) print(" .rvfi_mem_rdata(rvfi_mem_rdata),", file=f) print("`ifdef RISCV_FORMAL_CSR_MISA", file=f) print(" .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),", file=f) print(" .spec_csr_misa_rmask(spec_insn_%s_csr_misa_rmask)," % insn, file=f) print("`endif", file=f) print(" .spec_valid(spec_insn_%s_valid)," % insn, file=f) print(" .spec_trap(spec_insn_%s_trap)," % insn, file=f) print(" .spec_rs1_addr(spec_insn_%s_rs1_addr)," % insn, file=f) print(" .spec_rs2_addr(spec_insn_%s_rs2_addr)," % insn, file=f) print(" .spec_rd_addr(spec_insn_%s_rd_addr)," % insn, file=f) print(" .spec_rd_wdata(spec_insn_%s_rd_wdata)," % insn, file=f) print(" .spec_pc_wdata(spec_insn_%s_pc_wdata)," % insn, file=f) print(" .spec_mem_addr(spec_insn_%s_mem_addr)," % insn, file=f) print(" .spec_mem_rmask(spec_insn_%s_mem_rmask)," % insn, file=f) print(" .spec_mem_wmask(spec_insn_%s_mem_wmask)," % insn, file=f) print(" .spec_mem_wdata(spec_insn_%s_mem_wdata)" % insn, file=f) print(" );", file=f) print("", file=f) for port in ["valid", "trap", "rs1_addr", "rs2_addr", "rd_addr", "rd_wdata", "pc_wdata", "mem_addr", "mem_rmask", "mem_wmask", "mem_wdata"]: print(" assign spec_%s =\n\t\t%s : 0;" % (port, " :\n\t\t".join(["spec_insn_%s_valid ? spec_insn_%s_%s" % (insn, insn, port) for insn in sorted(insns)])), file=f) print("`ifdef RISCV_FORMAL_CSR_MISA", file=f) print(" assign spec_csr_misa_rmask =\n\t\t%s : 0;" % (" :\n\t\t".join(["spec_insn_%s_valid ? spec_insn_%s_csr_misa_rmask" % (insn, insn) for insn in sorted(insns)])), file=f) print("`endif", file=f) print("endmodule", file=f) ================================================ FILE: insns/insn_add.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_add ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // ADD instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + rvfi_rs2_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_addi.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_addi ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // ADDI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0010011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_addiw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_addiw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // ADDIW instruction wire [31:0] result = rvfi_rs1_rdata[31:0] + insn_imm[31:0]; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0011011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_addw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_addw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // ADDW instruction wire [31:0] result = rvfi_rs1_rdata[31:0] + rvfi_rs2_rdata[31:0]; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0111011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_and.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_and ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // AND instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & rvfi_rs2_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 111 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_andi.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_andi ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // ANDI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 7'b 0010011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_auipc.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_auipc ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // U-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:12], 12'b0}); wire [4:0] insn_rd = rvfi_insn[11:7]; wire [6:0] insn_opcode = rvfi_insn[ 6:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // AUIPC instruction assign spec_valid = rvfi_valid && !insn_padding && insn_opcode == 7'b 0010111; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? rvfi_pc_rdata + insn_imm : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs1_addr = 0; assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_beq.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_beq ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // SB-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0}); wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `ifdef RISCV_FORMAL_COMPRESSED wire ialign16 = 1; `else wire ialign16 = 0; `endif `endif // BEQ instruction wire cond = rvfi_rs1_rdata == rvfi_rs2_rdata; wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 4; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 1100011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_pc_wdata = next_pc; assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok; // default assignments assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_bge.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_bge ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // SB-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0}); wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `ifdef RISCV_FORMAL_COMPRESSED wire ialign16 = 1; `else wire ialign16 = 0; `endif `endif // BGE instruction wire cond = $signed(rvfi_rs1_rdata) >= $signed(rvfi_rs2_rdata); wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 4; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 101 && insn_opcode == 7'b 1100011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_pc_wdata = next_pc; assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok; // default assignments assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_bgeu.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_bgeu ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // SB-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0}); wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `ifdef RISCV_FORMAL_COMPRESSED wire ialign16 = 1; `else wire ialign16 = 0; `endif `endif // BGEU instruction wire cond = rvfi_rs1_rdata >= rvfi_rs2_rdata; wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 4; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 7'b 1100011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_pc_wdata = next_pc; assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok; // default assignments assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_blt.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_blt ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // SB-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0}); wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `ifdef RISCV_FORMAL_COMPRESSED wire ialign16 = 1; `else wire ialign16 = 0; `endif `endif // BLT instruction wire cond = $signed(rvfi_rs1_rdata) < $signed(rvfi_rs2_rdata); wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 4; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_opcode == 7'b 1100011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_pc_wdata = next_pc; assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok; // default assignments assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_bltu.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_bltu ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // SB-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0}); wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `ifdef RISCV_FORMAL_COMPRESSED wire ialign16 = 1; `else wire ialign16 = 0; `endif `endif // BLTU instruction wire cond = rvfi_rs1_rdata < rvfi_rs2_rdata; wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 4; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 7'b 1100011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_pc_wdata = next_pc; assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok; // default assignments assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_bne.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_bne ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // SB-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0}); wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `ifdef RISCV_FORMAL_COMPRESSED wire ialign16 = 1; `else wire ialign16 = 0; `endif `endif // BNE instruction wire cond = rvfi_rs1_rdata != rvfi_rs2_rdata; wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 4; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 7'b 1100011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_pc_wdata = next_pc; assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok; // default assignments assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_add.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_add ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [3:0] insn_funct4 = rvfi_insn[15:12]; wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; wire [4:0] insn_rs2 = rvfi_insn[6:2]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_ADD instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + rvfi_rs2_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct4 == 4'b 1001 && insn_rs2 && insn_opcode == 2'b 10; assign spec_rs1_addr = insn_rs1_rd; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_addi.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_addi ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]}); wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_ADDI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 01; assign spec_rs1_addr = insn_rs1_rd; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_addi16sp.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_addi16sp ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format (SP variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[4:3], rvfi_insn[5], rvfi_insn[2], rvfi_insn[6], 4'b0}); wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_ADDI16SP instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 01 && insn_rs1_rd == 5'd 2 && insn_imm; assign spec_rs1_addr = insn_rs1_rd; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_addi4spn.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_addi4spn ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CIW-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[10:7], rvfi_insn[12:11], rvfi_insn[5], rvfi_insn[6], 2'b00}; wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rd = {1'b1, rvfi_insn[4:2]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_ADDI4SPN instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 00 && insn_imm; assign spec_rs1_addr = 2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_addiw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_addiw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]}); wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_ADDIW instruction wire [31:0] result = rvfi_rs1_rdata[31:0] + insn_imm[31:0]; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 2'b 01 && insn_rs1_rd != 5'd 0; assign spec_rs1_addr = insn_rs1_rd; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_addw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_addw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CS-type instruction format (ALU version) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [5:0] insn_funct6 = rvfi_insn[15:10]; wire [1:0] insn_funct2 = rvfi_insn[6:5]; wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_ADDW instruction wire [31:0] result = rvfi_rs1_rdata[31:0] + rvfi_rs2_rdata[31:0]; assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100111 && insn_funct2 == 2'b 01 && insn_opcode == 2'b 01; assign spec_rs1_addr = insn_rs1_rd; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_and.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_and ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CS-type instruction format (ALU version) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [5:0] insn_funct6 = rvfi_insn[15:10]; wire [1:0] insn_funct2 = rvfi_insn[6:5]; wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_AND instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & rvfi_rs2_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100011 && insn_funct2 == 2'b 11 && insn_opcode == 2'b 01; assign spec_rs1_addr = insn_rs1_rd; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_andi.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_andi ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format (ANDI variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]}); wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [1:0] insn_funct2 = rvfi_insn[11:10]; wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_ANDI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_funct2 == 2'b 10 && insn_opcode == 2'b 01; assign spec_rs1_addr = insn_rs1_rd; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_beqz.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_beqz ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CB-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:5], rvfi_insn[2], rvfi_insn[11:10], rvfi_insn[4:3], 1'b0}); wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_BEQZ instruction wire cond = rvfi_rs1_rdata == 0; wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 2; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 2'b 01; assign spec_rs1_addr = insn_rs1; assign spec_pc_wdata = next_pc; assign spec_trap = (next_pc[0] != 0) || !misa_ok; // default assignments assign spec_rs2_addr = 0; assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_bnez.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_bnez ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CB-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:5], rvfi_insn[2], rvfi_insn[11:10], rvfi_insn[4:3], 1'b0}); wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_BNEZ instruction wire cond = rvfi_rs1_rdata != 0; wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 2; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 2'b 01; assign spec_rs1_addr = insn_rs1; assign spec_pc_wdata = next_pc; assign spec_trap = (next_pc[0] != 0) || !misa_ok; // default assignments assign spec_rs2_addr = 0; assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_j.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_j ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CJ-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[8], rvfi_insn[10], rvfi_insn[9], rvfi_insn[6], rvfi_insn[7], rvfi_insn[2], rvfi_insn[11], rvfi_insn[5], rvfi_insn[4], rvfi_insn[3], 1'b0}); wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_J instruction wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_pc_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 101 && insn_opcode == 2'b 01; assign spec_pc_wdata = next_pc; // default assignments assign spec_rs1_addr = 0; assign spec_rs2_addr = 0; assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_jal.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_jal ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CJ-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[8], rvfi_insn[10], rvfi_insn[9], rvfi_insn[6], rvfi_insn[7], rvfi_insn[2], rvfi_insn[11], rvfi_insn[5], rvfi_insn[4], rvfi_insn[3], 1'b0}); wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_JAL instruction wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_pc_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 2'b 01; assign spec_rd_addr = 5'd 1; assign spec_rd_wdata = rvfi_pc_rdata + 2; assign spec_pc_wdata = next_pc; // default assignments assign spec_rs1_addr = 0; assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_jalr.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_jalr ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [3:0] insn_funct4 = rvfi_insn[15:12]; wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; wire [4:0] insn_rs2 = rvfi_insn[6:2]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_JALR instruction wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_rs1_rdata & ~1; assign spec_valid = rvfi_valid && !insn_padding && insn_funct4 == 4'b 1001 && insn_rs1_rd && !insn_rs2 && insn_opcode == 2'b 10; assign spec_rs1_addr = insn_rs1_rd; assign spec_rd_addr = 5'd 1; assign spec_rd_wdata = rvfi_pc_rdata + 2; assign spec_pc_wdata = next_pc; assign spec_trap = (next_pc[0] != 0) || !misa_ok; // default assignments assign spec_rs2_addr = 0; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_jr.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_jr ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [3:0] insn_funct4 = rvfi_insn[15:12]; wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; wire [4:0] insn_rs2 = rvfi_insn[6:2]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_JR instruction wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_rs1_rdata & ~1; assign spec_valid = rvfi_valid && !insn_padding && insn_funct4 == 4'b 1000 && insn_rs1_rd && !insn_rs2 && insn_opcode == 2'b 10; assign spec_rs1_addr = insn_rs1_rd; assign spec_pc_wdata = next_pc; assign spec_trap = (next_pc[0] != 0) || !misa_ok; // default assignments assign spec_rs2_addr = 0; assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_ld.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_ld ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CL-type instruction format (64 bit version) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[6:5], rvfi_insn[12:10], 3'b000}; wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]}; wire [4:0] insn_rd = {1'b1, rvfi_insn[4:2]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_LD instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [63:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr)); assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 00; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_rmask = ((1 << 8)-1) << (addr-spec_mem_addr); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = ((addr & (8-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [63:0] result = rvfi_mem_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 00; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr; assign spec_mem_rmask = ((1 << 8)-1); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rs2_addr = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_ldsp.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_ldsp ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format (LSP variation, 64 bit version) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[4:2], rvfi_insn[12], rvfi_insn[6:5], 3'b000}; wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rd = rvfi_insn[11:7]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_LDSP instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [63:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr)); assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 10 && insn_rd; assign spec_rs1_addr = 2; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_rmask = ((1 << 8)-1) << (addr-spec_mem_addr); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = ((addr & (8-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [63:0] result = rvfi_mem_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 10 && insn_rd; assign spec_rs1_addr = 2; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr; assign spec_mem_rmask = ((1 << 8)-1); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rs2_addr = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_li.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_li ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]}); wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_LI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 2'b 01; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_rs1_addr = 0; assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_lui.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_lui ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format (LUI variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2], 12'b0}); wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_LUI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 01 && insn_rs1_rd != 5'd 2 && insn_imm; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_rs1_addr = 0; assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_lw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_lw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CL-type instruction format (32 bit version) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[5], rvfi_insn[12:10], rvfi_insn[6], 2'b00}; wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]}; wire [4:0] insn_rd = {1'b1, rvfi_insn[4:2]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_LW instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [31:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr)); assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 2'b 00; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_rmask = ((1 << 4)-1) << (addr-spec_mem_addr); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = ((addr & (4-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [31:0] result = rvfi_mem_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 2'b 00; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr; assign spec_mem_rmask = ((1 << 4)-1); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rs2_addr = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_lwsp.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_lwsp ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format (LSP variation, 32 bit version) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[3:2], rvfi_insn[12], rvfi_insn[6:4], 2'b00}; wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rd = rvfi_insn[11:7]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_LWSP instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [31:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr)); assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 2'b 10 && insn_rd; assign spec_rs1_addr = 2; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_rmask = ((1 << 4)-1) << (addr-spec_mem_addr); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = ((addr & (4-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [31:0] result = rvfi_mem_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 2'b 10 && insn_rd; assign spec_rs1_addr = 2; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr; assign spec_mem_rmask = ((1 << 4)-1); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rs2_addr = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_mv.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_mv ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [3:0] insn_funct4 = rvfi_insn[15:12]; wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; wire [4:0] insn_rs2 = rvfi_insn[6:2]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_MV instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct4 == 4'b 1000 && insn_rs2 && insn_opcode == 2'b 10; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_rs1_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_or.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_or ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CS-type instruction format (ALU version) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [5:0] insn_funct6 = rvfi_insn[15:10]; wire [1:0] insn_funct2 = rvfi_insn[6:5]; wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_OR instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata | rvfi_rs2_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100011 && insn_funct2 == 2'b 10 && insn_opcode == 2'b 01; assign spec_rs1_addr = insn_rs1_rd; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_sd.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_sd ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CS-type instruction format (64 bit version) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[6:5], rvfi_insn[12:10], 3'b000}; wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]}; wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_SD instruction wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; `ifdef RISCV_FORMAL_ALIGNED_MEM assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 2'b 00; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_wmask = ((1 << 8)-1) << (addr-spec_mem_addr); assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr)); assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = ((addr & (8-1)) != 0) || !misa_ok; `else assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 2'b 00; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr; assign spec_mem_wmask = ((1 << 8)-1); assign spec_mem_wdata = rvfi_rs2_rdata; assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_rmask = 0; endmodule ================================================ FILE: insns/insn_c_sdsp.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_sdsp ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CSS-type instruction format (64 bit version) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[9:7], rvfi_insn[12:10], 3'b000}; wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rs2 = rvfi_insn[6:2]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_SDSP instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 2'b 10; assign spec_rs1_addr = 2; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_wmask = ((1 << 8)-1) << (addr-spec_mem_addr); assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr)); assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = ((addr & (8-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 2'b 10; assign spec_rs1_addr = 2; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr; assign spec_mem_wmask = ((1 << 8)-1); assign spec_mem_wdata = rvfi_rs2_rdata; assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_rmask = 0; endmodule ================================================ FILE: insns/insn_c_slli.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_slli ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format (SLI variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [5:0] insn_shamt = {rvfi_insn[12], rvfi_insn[6:2]}; wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_SLLI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata << insn_shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 10 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); assign spec_rs1_addr = insn_rs1_rd; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_srai.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_srai ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format (SRI variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [5:0] insn_shamt = {rvfi_insn[12], rvfi_insn[6:2]}; wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [1:0] insn_funct2 = rvfi_insn[11:10]; wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_SRAI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = $signed(rvfi_rs1_rdata) >>> insn_shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_funct2 == 2'b 01 && insn_opcode == 2'b 01 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); assign spec_rs1_addr = insn_rs1_rd; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_srli.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_srli ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CI-type instruction format (SRI variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [5:0] insn_shamt = {rvfi_insn[12], rvfi_insn[6:2]}; wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [1:0] insn_funct2 = rvfi_insn[11:10]; wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_SRLI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata >> insn_shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_funct2 == 2'b 00 && insn_opcode == 2'b 01 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); assign spec_rs1_addr = insn_rs1_rd; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_sub.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_sub ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CS-type instruction format (ALU version) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [5:0] insn_funct6 = rvfi_insn[15:10]; wire [1:0] insn_funct2 = rvfi_insn[6:5]; wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_SUB instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata - rvfi_rs2_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100011 && insn_funct2 == 2'b 00 && insn_opcode == 2'b 01; assign spec_rs1_addr = insn_rs1_rd; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_subw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_subw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CS-type instruction format (ALU version) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [5:0] insn_funct6 = rvfi_insn[15:10]; wire [1:0] insn_funct2 = rvfi_insn[6:5]; wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_SUBW instruction wire [31:0] result = rvfi_rs1_rdata[31:0] - rvfi_rs2_rdata[31:0]; assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100111 && insn_funct2 == 2'b 00 && insn_opcode == 2'b 01; assign spec_rs1_addr = insn_rs1_rd; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_c_sw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_sw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CS-type instruction format (32 bit version) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[5], rvfi_insn[12:10], rvfi_insn[6], 2'b00}; wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]}; wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_SW instruction wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; `ifdef RISCV_FORMAL_ALIGNED_MEM assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 2'b 00; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_wmask = ((1 << 4)-1) << (addr-spec_mem_addr); assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr)); assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = ((addr & (4-1)) != 0) || !misa_ok; `else assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 2'b 00; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr; assign spec_mem_wmask = ((1 << 4)-1); assign spec_mem_wdata = rvfi_rs2_rdata; assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_rmask = 0; endmodule ================================================ FILE: insns/insn_c_swsp.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_swsp ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CSS-type instruction format (32 bit version) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[8:7], rvfi_insn[12:9], 2'b00}; wire [2:0] insn_funct3 = rvfi_insn[15:13]; wire [4:0] insn_rs2 = rvfi_insn[6:2]; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_SWSP instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 2'b 10; assign spec_rs1_addr = 2; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_wmask = ((1 << 4)-1) << (addr-spec_mem_addr); assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr)); assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = ((addr & (4-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 2'b 10; assign spec_rs1_addr = 2; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr; assign spec_mem_wmask = ((1 << 4)-1); assign spec_mem_wdata = rvfi_rs2_rdata; assign spec_pc_wdata = rvfi_pc_rdata + 2; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_rmask = 0; endmodule ================================================ FILE: insns/insn_c_xor.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_c_xor ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // CS-type instruction format (ALU version) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; wire [5:0] insn_funct6 = rvfi_insn[15:10]; wire [1:0] insn_funct2 = rvfi_insn[6:5]; wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]}; wire [1:0] insn_opcode = rvfi_insn[1:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; `else wire misa_ok = 1; `endif // C_XOR instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata ^ rvfi_rs2_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100011 && insn_funct2 == 2'b 01 && insn_opcode == 2'b 01; assign spec_rs1_addr = insn_rs1_rd; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rs1_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 2; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_div.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_div ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000; `else wire misa_ok = 1; `endif // DIV instruction `ifdef RISCV_FORMAL_ALTOPS wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'h29bbf66f7f8529ec; wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask; `else wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? {`RISCV_FORMAL_XLEN{1'b1}} : rvfi_rs1_rdata == {1'b1, {`RISCV_FORMAL_XLEN-1{1'b0}}} && rvfi_rs2_rdata == {`RISCV_FORMAL_XLEN{1'b1}} ? {1'b1, {`RISCV_FORMAL_XLEN-1{1'b0}}} : $signed(rvfi_rs1_rdata) / $signed(rvfi_rs2_rdata); `endif assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_divu.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_divu ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000; `else wire misa_ok = 1; `endif // DIVU instruction `ifdef RISCV_FORMAL_ALTOPS wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'h8c629acb10e8fd70; wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask; `else wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? {`RISCV_FORMAL_XLEN{1'b1}} : rvfi_rs1_rdata / rvfi_rs2_rdata; `endif assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_divuw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_divuw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000; `else wire misa_ok = 1; `endif // DIVUW instruction `ifdef RISCV_FORMAL_ALTOPS wire [31:0] altops_bitmask = 64'h8c629acb10e8fd70; wire [31:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask; `else wire [31:0] result = rvfi_rs2_rdata[31:0] == 32'b0 ? {32{1'b1}} : rvfi_rs1_rdata[31:0] / rvfi_rs2_rdata[31:0]; `endif assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0111011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_divw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_divw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000; `else wire misa_ok = 1; `endif // DIVW instruction `ifdef RISCV_FORMAL_ALTOPS wire [31:0] altops_bitmask = 64'h29bbf66f7f8529ec; wire [31:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask; `else wire [31:0] result = rvfi_rs2_rdata[31:0] == 32'b0 ? {32{1'b1}} : rvfi_rs1_rdata == {1'b1, {31{1'b0}}} && rvfi_rs2_rdata == {32{1'b1}} ? {1'b1, {31{1'b0}}} : $signed(rvfi_rs1_rdata[31:0]) / $signed(rvfi_rs2_rdata[31:0]); `endif assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0111011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_jal.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_jal ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // UJ-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[19:12], rvfi_insn[20], rvfi_insn[30:21], 1'b0}); wire [4:0] insn_rd = rvfi_insn[11:7]; wire [6:0] insn_opcode = rvfi_insn[6:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `ifdef RISCV_FORMAL_COMPRESSED wire ialign16 = 1; `else wire ialign16 = 0; `endif `endif // JAL instruction wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_pc_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_opcode == 7'b 1101111; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? rvfi_pc_rdata + 4 : 0; assign spec_pc_wdata = next_pc; assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok; // default assignments assign spec_rs1_addr = 0; assign spec_rs2_addr = 0; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_jalr.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_jalr ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `ifdef RISCV_FORMAL_COMPRESSED wire ialign16 = 1; `else wire ialign16 = 0; `endif `endif // JALR instruction wire [`RISCV_FORMAL_XLEN-1:0] next_pc = (rvfi_rs1_rdata + insn_imm) & ~1; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 1100111; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? rvfi_pc_rdata + 4 : 0; assign spec_pc_wdata = next_pc; assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok; // default assignments assign spec_rs2_addr = 0; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_lb.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_lb ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // LB instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [7:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr)); assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0000011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_rmask = ((1 << 1)-1) << (addr-spec_mem_addr); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = ((addr & (1-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [7:0] result = rvfi_mem_rdata; assign spec_valid = rvfi_valid && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0000011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr; assign spec_mem_rmask = ((1 << 1)-1); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rs2_addr = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_lbu.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_lbu ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // LBU instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [7:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr)); assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0000011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_rmask = ((1 << 1)-1) << (addr-spec_mem_addr); assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = ((addr & (1-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [7:0] result = rvfi_mem_rdata; assign spec_valid = rvfi_valid && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0000011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr; assign spec_mem_rmask = ((1 << 1)-1); assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rs2_addr = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_ld.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_ld ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // LD instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [63:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr)); assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0000011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_rmask = ((1 << 8)-1) << (addr-spec_mem_addr); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = ((addr & (8-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [63:0] result = rvfi_mem_rdata; assign spec_valid = rvfi_valid && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0000011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr; assign spec_mem_rmask = ((1 << 8)-1); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rs2_addr = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_lh.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_lh ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // LH instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [15:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr)); assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0000011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_rmask = ((1 << 2)-1) << (addr-spec_mem_addr); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = ((addr & (2-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [15:0] result = rvfi_mem_rdata; assign spec_valid = rvfi_valid && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0000011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr; assign spec_mem_rmask = ((1 << 2)-1); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rs2_addr = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_lhu.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_lhu ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // LHU instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [15:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr)); assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0000011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_rmask = ((1 << 2)-1) << (addr-spec_mem_addr); assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = ((addr & (2-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [15:0] result = rvfi_mem_rdata; assign spec_valid = rvfi_valid && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0000011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr; assign spec_mem_rmask = ((1 << 2)-1); assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rs2_addr = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_lui.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_lui ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // U-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:12], 12'b0}); wire [4:0] insn_rd = rvfi_insn[11:7]; wire [6:0] insn_opcode = rvfi_insn[ 6:0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // LUI instruction assign spec_valid = rvfi_valid && !insn_padding && insn_opcode == 7'b 0110111; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? insn_imm : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs1_addr = 0; assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_lw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_lw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // LW instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [31:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr)); assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0000011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_rmask = ((1 << 4)-1) << (addr-spec_mem_addr); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = ((addr & (4-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [31:0] result = rvfi_mem_rdata; assign spec_valid = rvfi_valid && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0000011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr; assign spec_mem_rmask = ((1 << 4)-1); assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rs2_addr = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_lwu.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_lwu ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // LWU instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [31:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr)); assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0000011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_rmask = ((1 << 4)-1) << (addr-spec_mem_addr); assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = ((addr & (4-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; wire [31:0] result = rvfi_mem_rdata; assign spec_valid = rvfi_valid && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0000011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_mem_addr = addr; assign spec_mem_rmask = ((1 << 4)-1); assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rs2_addr = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_mul.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_mul ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000; `else wire misa_ok = 1; `endif // MUL instruction `ifdef RISCV_FORMAL_ALTOPS wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'h2cdf52a55876063e; wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata + rvfi_rs2_rdata) ^ altops_bitmask; `else wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata * rvfi_rs2_rdata; `endif assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_mulh.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_mulh ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000; `else wire misa_ok = 1; `endif // MULH instruction `ifdef RISCV_FORMAL_ALTOPS wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'h15d01651f6583fb7; wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata + rvfi_rs2_rdata) ^ altops_bitmask; `else wire [`RISCV_FORMAL_XLEN-1:0] result = ({{`RISCV_FORMAL_XLEN{rvfi_rs1_rdata[`RISCV_FORMAL_XLEN-1]}}, rvfi_rs1_rdata} * {{`RISCV_FORMAL_XLEN{rvfi_rs2_rdata[`RISCV_FORMAL_XLEN-1]}}, rvfi_rs2_rdata}) >> `RISCV_FORMAL_XLEN; `endif assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_mulhsu.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_mulhsu ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000; `else wire misa_ok = 1; `endif // MULHSU instruction `ifdef RISCV_FORMAL_ALTOPS wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'hea3969edecfbe137; wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask; `else wire [`RISCV_FORMAL_XLEN-1:0] result = ({{`RISCV_FORMAL_XLEN{rvfi_rs1_rdata[`RISCV_FORMAL_XLEN-1]}}, rvfi_rs1_rdata} * {`RISCV_FORMAL_XLEN'b0, rvfi_rs2_rdata}) >> `RISCV_FORMAL_XLEN; `endif assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_mulhu.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_mulhu ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000; `else wire misa_ok = 1; `endif // MULHU instruction `ifdef RISCV_FORMAL_ALTOPS wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'hd13db50d949ce5e8; wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata + rvfi_rs2_rdata) ^ altops_bitmask; `else wire [`RISCV_FORMAL_XLEN-1:0] result = ({`RISCV_FORMAL_XLEN'b0, rvfi_rs1_rdata} * {`RISCV_FORMAL_XLEN'b0, rvfi_rs2_rdata}) >> `RISCV_FORMAL_XLEN; `endif assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_mulw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_mulw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000; `else wire misa_ok = 1; `endif // MULW instruction `ifdef RISCV_FORMAL_ALTOPS wire [31:0] altops_bitmask = 64'h2cdf52a55876063e; wire [31:0] result = (rvfi_rs1_rdata + rvfi_rs2_rdata) ^ altops_bitmask; `else wire [31:0] result = rvfi_rs1_rdata[31:0] * rvfi_rs2_rdata[31:0]; `endif assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0111011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_or.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_or ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // OR instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata | rvfi_rs2_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_ori.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_ori ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // ORI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata | insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0010011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_rem.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_rem ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000; `else wire misa_ok = 1; `endif // REM instruction `ifdef RISCV_FORMAL_ALTOPS wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'hf5b7d8538da68fa5; wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask; `else wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? rvfi_rs1_rdata : rvfi_rs1_rdata == {1'b1, {`RISCV_FORMAL_XLEN-1{1'b0}}} && rvfi_rs2_rdata == {`RISCV_FORMAL_XLEN{1'b1}} ? {`RISCV_FORMAL_XLEN{1'b0}} : $signed(rvfi_rs1_rdata) % $signed(rvfi_rs2_rdata); `endif assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_remu.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_remu ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000; `else wire misa_ok = 1; `endif // REMU instruction `ifdef RISCV_FORMAL_ALTOPS wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'hbc4402413138d0e1; wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask; `else wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? rvfi_rs1_rdata : rvfi_rs1_rdata % rvfi_rs2_rdata; `endif assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 111 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_remuw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_remuw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000; `else wire misa_ok = 1; `endif // REMUW instruction `ifdef RISCV_FORMAL_ALTOPS wire [31:0] altops_bitmask = 64'hbc4402413138d0e1; wire [31:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask; `else wire [31:0] result = rvfi_rs2_rdata == 32'b0 ? rvfi_rs1_rdata : rvfi_rs1_rdata[31:0] % rvfi_rs2_rdata[31:0]; `endif assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 111 && insn_opcode == 7'b 0111011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_remw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_remw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000; `else wire misa_ok = 1; `endif // REMW instruction `ifdef RISCV_FORMAL_ALTOPS wire [31:0] altops_bitmask = 64'hf5b7d8538da68fa5; wire [31:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask; `else wire [31:0] result = rvfi_rs2_rdata == 32'b0 ? rvfi_rs1_rdata : rvfi_rs1_rdata == {1'b1, {31{1'b0}}} && rvfi_rs2_rdata == {32{1'b1}} ? {32{1'b0}} : $signed(rvfi_rs1_rdata[31:0]) % $signed(rvfi_rs2_rdata[31:0]); `endif assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0111011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_sb.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_sb ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // S-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:25], rvfi_insn[11:7]}); wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SB instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0100011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_wmask = ((1 << 1)-1) << (addr-spec_mem_addr); assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr)); assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = ((addr & (1-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0100011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr; assign spec_mem_wmask = ((1 << 1)-1); assign spec_mem_wdata = rvfi_rs2_rdata; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_rmask = 0; endmodule ================================================ FILE: insns/insn_sd.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_sd ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // S-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:25], rvfi_insn[11:7]}); wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SD instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0100011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_wmask = ((1 << 8)-1) << (addr-spec_mem_addr); assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr)); assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = ((addr & (8-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0100011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr; assign spec_mem_wmask = ((1 << 8)-1); assign spec_mem_wdata = rvfi_rs2_rdata; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_rmask = 0; endmodule ================================================ FILE: insns/insn_sh.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_sh ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // S-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:25], rvfi_insn[11:7]}); wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SH instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0100011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_wmask = ((1 << 2)-1) << (addr-spec_mem_addr); assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr)); assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = ((addr & (2-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0100011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr; assign spec_mem_wmask = ((1 << 2)-1); assign spec_mem_wdata = rvfi_rs2_rdata; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_rmask = 0; endmodule ================================================ FILE: insns/insn_sll.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_sll ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SLL instruction wire [5:0] shamt = `RISCV_FORMAL_XLEN == 64 ? rvfi_rs2_rdata[5:0] : rvfi_rs2_rdata[4:0]; wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata << shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_slli.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_slli ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format (shift variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct6 = rvfi_insn[31:26]; wire [5:0] insn_shamt = rvfi_insn[25:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SLLI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata << insn_shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 000000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_slliw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_slliw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format (shift variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct6 = rvfi_insn[31:26]; wire [5:0] insn_shamt = rvfi_insn[25:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SLLIW instruction wire [31:0] result = rvfi_rs1_rdata[31:0] << insn_shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 000000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0011011 && !insn_shamt[5]; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_sllw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_sllw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SLLW instruction wire [4:0] shamt = rvfi_rs2_rdata[4:0]; wire [31:0] result = rvfi_rs1_rdata[31:0] << shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0111011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_slt.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_slt ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SLT instruction wire [`RISCV_FORMAL_XLEN-1:0] result = $signed(rvfi_rs1_rdata) < $signed(rvfi_rs2_rdata); assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_slti.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_slti ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SLTI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = $signed(rvfi_rs1_rdata) < $signed(insn_imm); assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0010011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_sltiu.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_sltiu ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SLTIU instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata < insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0010011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_sltu.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_sltu ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SLTU instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata < rvfi_rs2_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_sra.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_sra ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SRA instruction wire [5:0] shamt = `RISCV_FORMAL_XLEN == 64 ? rvfi_rs2_rdata[5:0] : rvfi_rs2_rdata[4:0]; wire [`RISCV_FORMAL_XLEN-1:0] result = $signed(rvfi_rs1_rdata) >>> shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0100000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_srai.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_srai ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format (shift variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct6 = rvfi_insn[31:26]; wire [5:0] insn_shamt = rvfi_insn[25:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SRAI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = $signed(rvfi_rs1_rdata) >>> insn_shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 010000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_sraiw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_sraiw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format (shift variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct6 = rvfi_insn[31:26]; wire [5:0] insn_shamt = rvfi_insn[25:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SRAIW instruction wire [31:0] result = $signed(rvfi_rs1_rdata[31:0]) >>> insn_shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 010000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0011011 && !insn_shamt[5]; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_sraw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_sraw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SRAW instruction wire [4:0] shamt = rvfi_rs2_rdata[4:0]; wire [31:0] result = $signed(rvfi_rs1_rdata[31:0]) >>> shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0100000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0111011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_srl.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_srl ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SRL instruction wire [5:0] shamt = `RISCV_FORMAL_XLEN == 64 ? rvfi_rs2_rdata[5:0] : rvfi_rs2_rdata[4:0]; wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata >> shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_srli.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_srli ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format (shift variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct6 = rvfi_insn[31:26]; wire [5:0] insn_shamt = rvfi_insn[25:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SRLI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata >> insn_shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 000000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_srliw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_srliw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format (shift variation) wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct6 = rvfi_insn[31:26]; wire [5:0] insn_shamt = rvfi_insn[25:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SRLIW instruction wire [31:0] result = rvfi_rs1_rdata[31:0] >> insn_shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 000000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0011011 && !insn_shamt[5]; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_srlw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_srlw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SRLW instruction wire [4:0] shamt = rvfi_rs2_rdata[4:0]; wire [31:0] result = rvfi_rs1_rdata[31:0] >> shamt; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0111011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_sub.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_sub ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SUB instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata - rvfi_rs2_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0100000 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_subw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_subw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SUBW instruction wire [31:0] result = rvfi_rs1_rdata[31:0] - rvfi_rs2_rdata[31:0]; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0100000 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0111011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_sw.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_sw ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // S-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:25], rvfi_insn[11:7]}); wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // SW instruction `ifdef RISCV_FORMAL_ALIGNED_MEM wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0100011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1); assign spec_mem_wmask = ((1 << 4)-1) << (addr-spec_mem_addr); assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr)); assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = ((addr & (4-1)) != 0) || !misa_ok; `else wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0100011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_mem_addr = addr; assign spec_mem_wmask = ((1 << 4)-1); assign spec_mem_wdata = rvfi_rs2_rdata; assign spec_pc_wdata = rvfi_pc_rdata + 4; assign spec_trap = !misa_ok; `endif // default assignments assign spec_rd_addr = 0; assign spec_rd_wdata = 0; assign spec_mem_rmask = 0; endmodule ================================================ FILE: insns/insn_xor.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_xor ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // R-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [6:0] insn_funct7 = rvfi_insn[31:25]; wire [4:0] insn_rs2 = rvfi_insn[24:20]; wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // XOR instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata ^ rvfi_rs2_rdata; assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0110011; assign spec_rs1_addr = insn_rs1; assign spec_rs2_addr = insn_rs2; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/insn_xori.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_insn_xori ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); // I-type instruction format wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16; wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); wire [4:0] insn_rs1 = rvfi_insn[19:15]; wire [2:0] insn_funct3 = rvfi_insn[14:12]; wire [4:0] insn_rd = rvfi_insn[11: 7]; wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; `ifdef RISCV_FORMAL_CSR_MISA wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; `else wire misa_ok = 1; `endif // XORI instruction wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata ^ insn_imm; assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0010011; assign spec_rs1_addr = insn_rs1; assign spec_rd_addr = insn_rd; assign spec_rd_wdata = spec_rd_addr ? result : 0; assign spec_pc_wdata = rvfi_pc_rdata + 4; // default assignments assign spec_rs2_addr = 0; assign spec_trap = !misa_ok; assign spec_mem_addr = 0; assign spec_mem_rmask = 0; assign spec_mem_wmask = 0; assign spec_mem_wdata = 0; endmodule ================================================ FILE: insns/isa_rv32i.txt ================================================ add addi and andi auipc beq bge bgeu blt bltu bne jal jalr lb lbu lh lhu lui lw or ori sb sh sll slli slt slti sltiu sltu sra srai srl srli sub sw xor xori ================================================ FILE: insns/isa_rv32i.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_isa_rv32i ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); wire spec_insn_add_valid; wire spec_insn_add_trap; wire [ 4 : 0] spec_insn_add_rs1_addr; wire [ 4 : 0] spec_insn_add_rs2_addr; wire [ 4 : 0] spec_insn_add_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; `endif rvfi_insn_add insn_add ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), `endif .spec_valid(spec_insn_add_valid), .spec_trap(spec_insn_add_trap), .spec_rs1_addr(spec_insn_add_rs1_addr), .spec_rs2_addr(spec_insn_add_rs2_addr), .spec_rd_addr(spec_insn_add_rd_addr), .spec_rd_wdata(spec_insn_add_rd_wdata), .spec_pc_wdata(spec_insn_add_pc_wdata), .spec_mem_addr(spec_insn_add_mem_addr), .spec_mem_rmask(spec_insn_add_mem_rmask), .spec_mem_wmask(spec_insn_add_mem_wmask), .spec_mem_wdata(spec_insn_add_mem_wdata) ); wire spec_insn_addi_valid; wire spec_insn_addi_trap; wire [ 4 : 0] spec_insn_addi_rs1_addr; wire [ 4 : 0] spec_insn_addi_rs2_addr; wire [ 4 : 0] spec_insn_addi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; `endif rvfi_insn_addi insn_addi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), `endif .spec_valid(spec_insn_addi_valid), .spec_trap(spec_insn_addi_trap), .spec_rs1_addr(spec_insn_addi_rs1_addr), .spec_rs2_addr(spec_insn_addi_rs2_addr), .spec_rd_addr(spec_insn_addi_rd_addr), .spec_rd_wdata(spec_insn_addi_rd_wdata), .spec_pc_wdata(spec_insn_addi_pc_wdata), .spec_mem_addr(spec_insn_addi_mem_addr), .spec_mem_rmask(spec_insn_addi_mem_rmask), .spec_mem_wmask(spec_insn_addi_mem_wmask), .spec_mem_wdata(spec_insn_addi_mem_wdata) ); wire spec_insn_and_valid; wire spec_insn_and_trap; wire [ 4 : 0] spec_insn_and_rs1_addr; wire [ 4 : 0] spec_insn_and_rs2_addr; wire [ 4 : 0] spec_insn_and_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; `endif rvfi_insn_and insn_and ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), `endif .spec_valid(spec_insn_and_valid), .spec_trap(spec_insn_and_trap), .spec_rs1_addr(spec_insn_and_rs1_addr), .spec_rs2_addr(spec_insn_and_rs2_addr), .spec_rd_addr(spec_insn_and_rd_addr), .spec_rd_wdata(spec_insn_and_rd_wdata), .spec_pc_wdata(spec_insn_and_pc_wdata), .spec_mem_addr(spec_insn_and_mem_addr), .spec_mem_rmask(spec_insn_and_mem_rmask), .spec_mem_wmask(spec_insn_and_mem_wmask), .spec_mem_wdata(spec_insn_and_mem_wdata) ); wire spec_insn_andi_valid; wire spec_insn_andi_trap; wire [ 4 : 0] spec_insn_andi_rs1_addr; wire [ 4 : 0] spec_insn_andi_rs2_addr; wire [ 4 : 0] spec_insn_andi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; `endif rvfi_insn_andi insn_andi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), `endif .spec_valid(spec_insn_andi_valid), .spec_trap(spec_insn_andi_trap), .spec_rs1_addr(spec_insn_andi_rs1_addr), .spec_rs2_addr(spec_insn_andi_rs2_addr), .spec_rd_addr(spec_insn_andi_rd_addr), .spec_rd_wdata(spec_insn_andi_rd_wdata), .spec_pc_wdata(spec_insn_andi_pc_wdata), .spec_mem_addr(spec_insn_andi_mem_addr), .spec_mem_rmask(spec_insn_andi_mem_rmask), .spec_mem_wmask(spec_insn_andi_mem_wmask), .spec_mem_wdata(spec_insn_andi_mem_wdata) ); wire spec_insn_auipc_valid; wire spec_insn_auipc_trap; wire [ 4 : 0] spec_insn_auipc_rs1_addr; wire [ 4 : 0] spec_insn_auipc_rs2_addr; wire [ 4 : 0] spec_insn_auipc_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; `endif rvfi_insn_auipc insn_auipc ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), `endif .spec_valid(spec_insn_auipc_valid), .spec_trap(spec_insn_auipc_trap), .spec_rs1_addr(spec_insn_auipc_rs1_addr), .spec_rs2_addr(spec_insn_auipc_rs2_addr), .spec_rd_addr(spec_insn_auipc_rd_addr), .spec_rd_wdata(spec_insn_auipc_rd_wdata), .spec_pc_wdata(spec_insn_auipc_pc_wdata), .spec_mem_addr(spec_insn_auipc_mem_addr), .spec_mem_rmask(spec_insn_auipc_mem_rmask), .spec_mem_wmask(spec_insn_auipc_mem_wmask), .spec_mem_wdata(spec_insn_auipc_mem_wdata) ); wire spec_insn_beq_valid; wire spec_insn_beq_trap; wire [ 4 : 0] spec_insn_beq_rs1_addr; wire [ 4 : 0] spec_insn_beq_rs2_addr; wire [ 4 : 0] spec_insn_beq_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; `endif rvfi_insn_beq insn_beq ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), `endif .spec_valid(spec_insn_beq_valid), .spec_trap(spec_insn_beq_trap), .spec_rs1_addr(spec_insn_beq_rs1_addr), .spec_rs2_addr(spec_insn_beq_rs2_addr), .spec_rd_addr(spec_insn_beq_rd_addr), .spec_rd_wdata(spec_insn_beq_rd_wdata), .spec_pc_wdata(spec_insn_beq_pc_wdata), .spec_mem_addr(spec_insn_beq_mem_addr), .spec_mem_rmask(spec_insn_beq_mem_rmask), .spec_mem_wmask(spec_insn_beq_mem_wmask), .spec_mem_wdata(spec_insn_beq_mem_wdata) ); wire spec_insn_bge_valid; wire spec_insn_bge_trap; wire [ 4 : 0] spec_insn_bge_rs1_addr; wire [ 4 : 0] spec_insn_bge_rs2_addr; wire [ 4 : 0] spec_insn_bge_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; `endif rvfi_insn_bge insn_bge ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), `endif .spec_valid(spec_insn_bge_valid), .spec_trap(spec_insn_bge_trap), .spec_rs1_addr(spec_insn_bge_rs1_addr), .spec_rs2_addr(spec_insn_bge_rs2_addr), .spec_rd_addr(spec_insn_bge_rd_addr), .spec_rd_wdata(spec_insn_bge_rd_wdata), .spec_pc_wdata(spec_insn_bge_pc_wdata), .spec_mem_addr(spec_insn_bge_mem_addr), .spec_mem_rmask(spec_insn_bge_mem_rmask), .spec_mem_wmask(spec_insn_bge_mem_wmask), .spec_mem_wdata(spec_insn_bge_mem_wdata) ); wire spec_insn_bgeu_valid; wire spec_insn_bgeu_trap; wire [ 4 : 0] spec_insn_bgeu_rs1_addr; wire [ 4 : 0] spec_insn_bgeu_rs2_addr; wire [ 4 : 0] spec_insn_bgeu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; `endif rvfi_insn_bgeu insn_bgeu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), `endif .spec_valid(spec_insn_bgeu_valid), .spec_trap(spec_insn_bgeu_trap), .spec_rs1_addr(spec_insn_bgeu_rs1_addr), .spec_rs2_addr(spec_insn_bgeu_rs2_addr), .spec_rd_addr(spec_insn_bgeu_rd_addr), .spec_rd_wdata(spec_insn_bgeu_rd_wdata), .spec_pc_wdata(spec_insn_bgeu_pc_wdata), .spec_mem_addr(spec_insn_bgeu_mem_addr), .spec_mem_rmask(spec_insn_bgeu_mem_rmask), .spec_mem_wmask(spec_insn_bgeu_mem_wmask), .spec_mem_wdata(spec_insn_bgeu_mem_wdata) ); wire spec_insn_blt_valid; wire spec_insn_blt_trap; wire [ 4 : 0] spec_insn_blt_rs1_addr; wire [ 4 : 0] spec_insn_blt_rs2_addr; wire [ 4 : 0] spec_insn_blt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; `endif rvfi_insn_blt insn_blt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), `endif .spec_valid(spec_insn_blt_valid), .spec_trap(spec_insn_blt_trap), .spec_rs1_addr(spec_insn_blt_rs1_addr), .spec_rs2_addr(spec_insn_blt_rs2_addr), .spec_rd_addr(spec_insn_blt_rd_addr), .spec_rd_wdata(spec_insn_blt_rd_wdata), .spec_pc_wdata(spec_insn_blt_pc_wdata), .spec_mem_addr(spec_insn_blt_mem_addr), .spec_mem_rmask(spec_insn_blt_mem_rmask), .spec_mem_wmask(spec_insn_blt_mem_wmask), .spec_mem_wdata(spec_insn_blt_mem_wdata) ); wire spec_insn_bltu_valid; wire spec_insn_bltu_trap; wire [ 4 : 0] spec_insn_bltu_rs1_addr; wire [ 4 : 0] spec_insn_bltu_rs2_addr; wire [ 4 : 0] spec_insn_bltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; `endif rvfi_insn_bltu insn_bltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), `endif .spec_valid(spec_insn_bltu_valid), .spec_trap(spec_insn_bltu_trap), .spec_rs1_addr(spec_insn_bltu_rs1_addr), .spec_rs2_addr(spec_insn_bltu_rs2_addr), .spec_rd_addr(spec_insn_bltu_rd_addr), .spec_rd_wdata(spec_insn_bltu_rd_wdata), .spec_pc_wdata(spec_insn_bltu_pc_wdata), .spec_mem_addr(spec_insn_bltu_mem_addr), .spec_mem_rmask(spec_insn_bltu_mem_rmask), .spec_mem_wmask(spec_insn_bltu_mem_wmask), .spec_mem_wdata(spec_insn_bltu_mem_wdata) ); wire spec_insn_bne_valid; wire spec_insn_bne_trap; wire [ 4 : 0] spec_insn_bne_rs1_addr; wire [ 4 : 0] spec_insn_bne_rs2_addr; wire [ 4 : 0] spec_insn_bne_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; `endif rvfi_insn_bne insn_bne ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), `endif .spec_valid(spec_insn_bne_valid), .spec_trap(spec_insn_bne_trap), .spec_rs1_addr(spec_insn_bne_rs1_addr), .spec_rs2_addr(spec_insn_bne_rs2_addr), .spec_rd_addr(spec_insn_bne_rd_addr), .spec_rd_wdata(spec_insn_bne_rd_wdata), .spec_pc_wdata(spec_insn_bne_pc_wdata), .spec_mem_addr(spec_insn_bne_mem_addr), .spec_mem_rmask(spec_insn_bne_mem_rmask), .spec_mem_wmask(spec_insn_bne_mem_wmask), .spec_mem_wdata(spec_insn_bne_mem_wdata) ); wire spec_insn_jal_valid; wire spec_insn_jal_trap; wire [ 4 : 0] spec_insn_jal_rs1_addr; wire [ 4 : 0] spec_insn_jal_rs2_addr; wire [ 4 : 0] spec_insn_jal_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; `endif rvfi_insn_jal insn_jal ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), `endif .spec_valid(spec_insn_jal_valid), .spec_trap(spec_insn_jal_trap), .spec_rs1_addr(spec_insn_jal_rs1_addr), .spec_rs2_addr(spec_insn_jal_rs2_addr), .spec_rd_addr(spec_insn_jal_rd_addr), .spec_rd_wdata(spec_insn_jal_rd_wdata), .spec_pc_wdata(spec_insn_jal_pc_wdata), .spec_mem_addr(spec_insn_jal_mem_addr), .spec_mem_rmask(spec_insn_jal_mem_rmask), .spec_mem_wmask(spec_insn_jal_mem_wmask), .spec_mem_wdata(spec_insn_jal_mem_wdata) ); wire spec_insn_jalr_valid; wire spec_insn_jalr_trap; wire [ 4 : 0] spec_insn_jalr_rs1_addr; wire [ 4 : 0] spec_insn_jalr_rs2_addr; wire [ 4 : 0] spec_insn_jalr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; `endif rvfi_insn_jalr insn_jalr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), `endif .spec_valid(spec_insn_jalr_valid), .spec_trap(spec_insn_jalr_trap), .spec_rs1_addr(spec_insn_jalr_rs1_addr), .spec_rs2_addr(spec_insn_jalr_rs2_addr), .spec_rd_addr(spec_insn_jalr_rd_addr), .spec_rd_wdata(spec_insn_jalr_rd_wdata), .spec_pc_wdata(spec_insn_jalr_pc_wdata), .spec_mem_addr(spec_insn_jalr_mem_addr), .spec_mem_rmask(spec_insn_jalr_mem_rmask), .spec_mem_wmask(spec_insn_jalr_mem_wmask), .spec_mem_wdata(spec_insn_jalr_mem_wdata) ); wire spec_insn_lb_valid; wire spec_insn_lb_trap; wire [ 4 : 0] spec_insn_lb_rs1_addr; wire [ 4 : 0] spec_insn_lb_rs2_addr; wire [ 4 : 0] spec_insn_lb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; `endif rvfi_insn_lb insn_lb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), `endif .spec_valid(spec_insn_lb_valid), .spec_trap(spec_insn_lb_trap), .spec_rs1_addr(spec_insn_lb_rs1_addr), .spec_rs2_addr(spec_insn_lb_rs2_addr), .spec_rd_addr(spec_insn_lb_rd_addr), .spec_rd_wdata(spec_insn_lb_rd_wdata), .spec_pc_wdata(spec_insn_lb_pc_wdata), .spec_mem_addr(spec_insn_lb_mem_addr), .spec_mem_rmask(spec_insn_lb_mem_rmask), .spec_mem_wmask(spec_insn_lb_mem_wmask), .spec_mem_wdata(spec_insn_lb_mem_wdata) ); wire spec_insn_lbu_valid; wire spec_insn_lbu_trap; wire [ 4 : 0] spec_insn_lbu_rs1_addr; wire [ 4 : 0] spec_insn_lbu_rs2_addr; wire [ 4 : 0] spec_insn_lbu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; `endif rvfi_insn_lbu insn_lbu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), `endif .spec_valid(spec_insn_lbu_valid), .spec_trap(spec_insn_lbu_trap), .spec_rs1_addr(spec_insn_lbu_rs1_addr), .spec_rs2_addr(spec_insn_lbu_rs2_addr), .spec_rd_addr(spec_insn_lbu_rd_addr), .spec_rd_wdata(spec_insn_lbu_rd_wdata), .spec_pc_wdata(spec_insn_lbu_pc_wdata), .spec_mem_addr(spec_insn_lbu_mem_addr), .spec_mem_rmask(spec_insn_lbu_mem_rmask), .spec_mem_wmask(spec_insn_lbu_mem_wmask), .spec_mem_wdata(spec_insn_lbu_mem_wdata) ); wire spec_insn_lh_valid; wire spec_insn_lh_trap; wire [ 4 : 0] spec_insn_lh_rs1_addr; wire [ 4 : 0] spec_insn_lh_rs2_addr; wire [ 4 : 0] spec_insn_lh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; `endif rvfi_insn_lh insn_lh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), `endif .spec_valid(spec_insn_lh_valid), .spec_trap(spec_insn_lh_trap), .spec_rs1_addr(spec_insn_lh_rs1_addr), .spec_rs2_addr(spec_insn_lh_rs2_addr), .spec_rd_addr(spec_insn_lh_rd_addr), .spec_rd_wdata(spec_insn_lh_rd_wdata), .spec_pc_wdata(spec_insn_lh_pc_wdata), .spec_mem_addr(spec_insn_lh_mem_addr), .spec_mem_rmask(spec_insn_lh_mem_rmask), .spec_mem_wmask(spec_insn_lh_mem_wmask), .spec_mem_wdata(spec_insn_lh_mem_wdata) ); wire spec_insn_lhu_valid; wire spec_insn_lhu_trap; wire [ 4 : 0] spec_insn_lhu_rs1_addr; wire [ 4 : 0] spec_insn_lhu_rs2_addr; wire [ 4 : 0] spec_insn_lhu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; `endif rvfi_insn_lhu insn_lhu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), `endif .spec_valid(spec_insn_lhu_valid), .spec_trap(spec_insn_lhu_trap), .spec_rs1_addr(spec_insn_lhu_rs1_addr), .spec_rs2_addr(spec_insn_lhu_rs2_addr), .spec_rd_addr(spec_insn_lhu_rd_addr), .spec_rd_wdata(spec_insn_lhu_rd_wdata), .spec_pc_wdata(spec_insn_lhu_pc_wdata), .spec_mem_addr(spec_insn_lhu_mem_addr), .spec_mem_rmask(spec_insn_lhu_mem_rmask), .spec_mem_wmask(spec_insn_lhu_mem_wmask), .spec_mem_wdata(spec_insn_lhu_mem_wdata) ); wire spec_insn_lui_valid; wire spec_insn_lui_trap; wire [ 4 : 0] spec_insn_lui_rs1_addr; wire [ 4 : 0] spec_insn_lui_rs2_addr; wire [ 4 : 0] spec_insn_lui_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; `endif rvfi_insn_lui insn_lui ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), `endif .spec_valid(spec_insn_lui_valid), .spec_trap(spec_insn_lui_trap), .spec_rs1_addr(spec_insn_lui_rs1_addr), .spec_rs2_addr(spec_insn_lui_rs2_addr), .spec_rd_addr(spec_insn_lui_rd_addr), .spec_rd_wdata(spec_insn_lui_rd_wdata), .spec_pc_wdata(spec_insn_lui_pc_wdata), .spec_mem_addr(spec_insn_lui_mem_addr), .spec_mem_rmask(spec_insn_lui_mem_rmask), .spec_mem_wmask(spec_insn_lui_mem_wmask), .spec_mem_wdata(spec_insn_lui_mem_wdata) ); wire spec_insn_lw_valid; wire spec_insn_lw_trap; wire [ 4 : 0] spec_insn_lw_rs1_addr; wire [ 4 : 0] spec_insn_lw_rs2_addr; wire [ 4 : 0] spec_insn_lw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; `endif rvfi_insn_lw insn_lw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), `endif .spec_valid(spec_insn_lw_valid), .spec_trap(spec_insn_lw_trap), .spec_rs1_addr(spec_insn_lw_rs1_addr), .spec_rs2_addr(spec_insn_lw_rs2_addr), .spec_rd_addr(spec_insn_lw_rd_addr), .spec_rd_wdata(spec_insn_lw_rd_wdata), .spec_pc_wdata(spec_insn_lw_pc_wdata), .spec_mem_addr(spec_insn_lw_mem_addr), .spec_mem_rmask(spec_insn_lw_mem_rmask), .spec_mem_wmask(spec_insn_lw_mem_wmask), .spec_mem_wdata(spec_insn_lw_mem_wdata) ); wire spec_insn_or_valid; wire spec_insn_or_trap; wire [ 4 : 0] spec_insn_or_rs1_addr; wire [ 4 : 0] spec_insn_or_rs2_addr; wire [ 4 : 0] spec_insn_or_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; `endif rvfi_insn_or insn_or ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), `endif .spec_valid(spec_insn_or_valid), .spec_trap(spec_insn_or_trap), .spec_rs1_addr(spec_insn_or_rs1_addr), .spec_rs2_addr(spec_insn_or_rs2_addr), .spec_rd_addr(spec_insn_or_rd_addr), .spec_rd_wdata(spec_insn_or_rd_wdata), .spec_pc_wdata(spec_insn_or_pc_wdata), .spec_mem_addr(spec_insn_or_mem_addr), .spec_mem_rmask(spec_insn_or_mem_rmask), .spec_mem_wmask(spec_insn_or_mem_wmask), .spec_mem_wdata(spec_insn_or_mem_wdata) ); wire spec_insn_ori_valid; wire spec_insn_ori_trap; wire [ 4 : 0] spec_insn_ori_rs1_addr; wire [ 4 : 0] spec_insn_ori_rs2_addr; wire [ 4 : 0] spec_insn_ori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; `endif rvfi_insn_ori insn_ori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), `endif .spec_valid(spec_insn_ori_valid), .spec_trap(spec_insn_ori_trap), .spec_rs1_addr(spec_insn_ori_rs1_addr), .spec_rs2_addr(spec_insn_ori_rs2_addr), .spec_rd_addr(spec_insn_ori_rd_addr), .spec_rd_wdata(spec_insn_ori_rd_wdata), .spec_pc_wdata(spec_insn_ori_pc_wdata), .spec_mem_addr(spec_insn_ori_mem_addr), .spec_mem_rmask(spec_insn_ori_mem_rmask), .spec_mem_wmask(spec_insn_ori_mem_wmask), .spec_mem_wdata(spec_insn_ori_mem_wdata) ); wire spec_insn_sb_valid; wire spec_insn_sb_trap; wire [ 4 : 0] spec_insn_sb_rs1_addr; wire [ 4 : 0] spec_insn_sb_rs2_addr; wire [ 4 : 0] spec_insn_sb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; `endif rvfi_insn_sb insn_sb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), `endif .spec_valid(spec_insn_sb_valid), .spec_trap(spec_insn_sb_trap), .spec_rs1_addr(spec_insn_sb_rs1_addr), .spec_rs2_addr(spec_insn_sb_rs2_addr), .spec_rd_addr(spec_insn_sb_rd_addr), .spec_rd_wdata(spec_insn_sb_rd_wdata), .spec_pc_wdata(spec_insn_sb_pc_wdata), .spec_mem_addr(spec_insn_sb_mem_addr), .spec_mem_rmask(spec_insn_sb_mem_rmask), .spec_mem_wmask(spec_insn_sb_mem_wmask), .spec_mem_wdata(spec_insn_sb_mem_wdata) ); wire spec_insn_sh_valid; wire spec_insn_sh_trap; wire [ 4 : 0] spec_insn_sh_rs1_addr; wire [ 4 : 0] spec_insn_sh_rs2_addr; wire [ 4 : 0] spec_insn_sh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; `endif rvfi_insn_sh insn_sh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), `endif .spec_valid(spec_insn_sh_valid), .spec_trap(spec_insn_sh_trap), .spec_rs1_addr(spec_insn_sh_rs1_addr), .spec_rs2_addr(spec_insn_sh_rs2_addr), .spec_rd_addr(spec_insn_sh_rd_addr), .spec_rd_wdata(spec_insn_sh_rd_wdata), .spec_pc_wdata(spec_insn_sh_pc_wdata), .spec_mem_addr(spec_insn_sh_mem_addr), .spec_mem_rmask(spec_insn_sh_mem_rmask), .spec_mem_wmask(spec_insn_sh_mem_wmask), .spec_mem_wdata(spec_insn_sh_mem_wdata) ); wire spec_insn_sll_valid; wire spec_insn_sll_trap; wire [ 4 : 0] spec_insn_sll_rs1_addr; wire [ 4 : 0] spec_insn_sll_rs2_addr; wire [ 4 : 0] spec_insn_sll_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; `endif rvfi_insn_sll insn_sll ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), `endif .spec_valid(spec_insn_sll_valid), .spec_trap(spec_insn_sll_trap), .spec_rs1_addr(spec_insn_sll_rs1_addr), .spec_rs2_addr(spec_insn_sll_rs2_addr), .spec_rd_addr(spec_insn_sll_rd_addr), .spec_rd_wdata(spec_insn_sll_rd_wdata), .spec_pc_wdata(spec_insn_sll_pc_wdata), .spec_mem_addr(spec_insn_sll_mem_addr), .spec_mem_rmask(spec_insn_sll_mem_rmask), .spec_mem_wmask(spec_insn_sll_mem_wmask), .spec_mem_wdata(spec_insn_sll_mem_wdata) ); wire spec_insn_slli_valid; wire spec_insn_slli_trap; wire [ 4 : 0] spec_insn_slli_rs1_addr; wire [ 4 : 0] spec_insn_slli_rs2_addr; wire [ 4 : 0] spec_insn_slli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; `endif rvfi_insn_slli insn_slli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), `endif .spec_valid(spec_insn_slli_valid), .spec_trap(spec_insn_slli_trap), .spec_rs1_addr(spec_insn_slli_rs1_addr), .spec_rs2_addr(spec_insn_slli_rs2_addr), .spec_rd_addr(spec_insn_slli_rd_addr), .spec_rd_wdata(spec_insn_slli_rd_wdata), .spec_pc_wdata(spec_insn_slli_pc_wdata), .spec_mem_addr(spec_insn_slli_mem_addr), .spec_mem_rmask(spec_insn_slli_mem_rmask), .spec_mem_wmask(spec_insn_slli_mem_wmask), .spec_mem_wdata(spec_insn_slli_mem_wdata) ); wire spec_insn_slt_valid; wire spec_insn_slt_trap; wire [ 4 : 0] spec_insn_slt_rs1_addr; wire [ 4 : 0] spec_insn_slt_rs2_addr; wire [ 4 : 0] spec_insn_slt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; `endif rvfi_insn_slt insn_slt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), `endif .spec_valid(spec_insn_slt_valid), .spec_trap(spec_insn_slt_trap), .spec_rs1_addr(spec_insn_slt_rs1_addr), .spec_rs2_addr(spec_insn_slt_rs2_addr), .spec_rd_addr(spec_insn_slt_rd_addr), .spec_rd_wdata(spec_insn_slt_rd_wdata), .spec_pc_wdata(spec_insn_slt_pc_wdata), .spec_mem_addr(spec_insn_slt_mem_addr), .spec_mem_rmask(spec_insn_slt_mem_rmask), .spec_mem_wmask(spec_insn_slt_mem_wmask), .spec_mem_wdata(spec_insn_slt_mem_wdata) ); wire spec_insn_slti_valid; wire spec_insn_slti_trap; wire [ 4 : 0] spec_insn_slti_rs1_addr; wire [ 4 : 0] spec_insn_slti_rs2_addr; wire [ 4 : 0] spec_insn_slti_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; `endif rvfi_insn_slti insn_slti ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), `endif .spec_valid(spec_insn_slti_valid), .spec_trap(spec_insn_slti_trap), .spec_rs1_addr(spec_insn_slti_rs1_addr), .spec_rs2_addr(spec_insn_slti_rs2_addr), .spec_rd_addr(spec_insn_slti_rd_addr), .spec_rd_wdata(spec_insn_slti_rd_wdata), .spec_pc_wdata(spec_insn_slti_pc_wdata), .spec_mem_addr(spec_insn_slti_mem_addr), .spec_mem_rmask(spec_insn_slti_mem_rmask), .spec_mem_wmask(spec_insn_slti_mem_wmask), .spec_mem_wdata(spec_insn_slti_mem_wdata) ); wire spec_insn_sltiu_valid; wire spec_insn_sltiu_trap; wire [ 4 : 0] spec_insn_sltiu_rs1_addr; wire [ 4 : 0] spec_insn_sltiu_rs2_addr; wire [ 4 : 0] spec_insn_sltiu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; `endif rvfi_insn_sltiu insn_sltiu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltiu_valid), .spec_trap(spec_insn_sltiu_trap), .spec_rs1_addr(spec_insn_sltiu_rs1_addr), .spec_rs2_addr(spec_insn_sltiu_rs2_addr), .spec_rd_addr(spec_insn_sltiu_rd_addr), .spec_rd_wdata(spec_insn_sltiu_rd_wdata), .spec_pc_wdata(spec_insn_sltiu_pc_wdata), .spec_mem_addr(spec_insn_sltiu_mem_addr), .spec_mem_rmask(spec_insn_sltiu_mem_rmask), .spec_mem_wmask(spec_insn_sltiu_mem_wmask), .spec_mem_wdata(spec_insn_sltiu_mem_wdata) ); wire spec_insn_sltu_valid; wire spec_insn_sltu_trap; wire [ 4 : 0] spec_insn_sltu_rs1_addr; wire [ 4 : 0] spec_insn_sltu_rs2_addr; wire [ 4 : 0] spec_insn_sltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; `endif rvfi_insn_sltu insn_sltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltu_valid), .spec_trap(spec_insn_sltu_trap), .spec_rs1_addr(spec_insn_sltu_rs1_addr), .spec_rs2_addr(spec_insn_sltu_rs2_addr), .spec_rd_addr(spec_insn_sltu_rd_addr), .spec_rd_wdata(spec_insn_sltu_rd_wdata), .spec_pc_wdata(spec_insn_sltu_pc_wdata), .spec_mem_addr(spec_insn_sltu_mem_addr), .spec_mem_rmask(spec_insn_sltu_mem_rmask), .spec_mem_wmask(spec_insn_sltu_mem_wmask), .spec_mem_wdata(spec_insn_sltu_mem_wdata) ); wire spec_insn_sra_valid; wire spec_insn_sra_trap; wire [ 4 : 0] spec_insn_sra_rs1_addr; wire [ 4 : 0] spec_insn_sra_rs2_addr; wire [ 4 : 0] spec_insn_sra_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; `endif rvfi_insn_sra insn_sra ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), `endif .spec_valid(spec_insn_sra_valid), .spec_trap(spec_insn_sra_trap), .spec_rs1_addr(spec_insn_sra_rs1_addr), .spec_rs2_addr(spec_insn_sra_rs2_addr), .spec_rd_addr(spec_insn_sra_rd_addr), .spec_rd_wdata(spec_insn_sra_rd_wdata), .spec_pc_wdata(spec_insn_sra_pc_wdata), .spec_mem_addr(spec_insn_sra_mem_addr), .spec_mem_rmask(spec_insn_sra_mem_rmask), .spec_mem_wmask(spec_insn_sra_mem_wmask), .spec_mem_wdata(spec_insn_sra_mem_wdata) ); wire spec_insn_srai_valid; wire spec_insn_srai_trap; wire [ 4 : 0] spec_insn_srai_rs1_addr; wire [ 4 : 0] spec_insn_srai_rs2_addr; wire [ 4 : 0] spec_insn_srai_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; `endif rvfi_insn_srai insn_srai ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), `endif .spec_valid(spec_insn_srai_valid), .spec_trap(spec_insn_srai_trap), .spec_rs1_addr(spec_insn_srai_rs1_addr), .spec_rs2_addr(spec_insn_srai_rs2_addr), .spec_rd_addr(spec_insn_srai_rd_addr), .spec_rd_wdata(spec_insn_srai_rd_wdata), .spec_pc_wdata(spec_insn_srai_pc_wdata), .spec_mem_addr(spec_insn_srai_mem_addr), .spec_mem_rmask(spec_insn_srai_mem_rmask), .spec_mem_wmask(spec_insn_srai_mem_wmask), .spec_mem_wdata(spec_insn_srai_mem_wdata) ); wire spec_insn_srl_valid; wire spec_insn_srl_trap; wire [ 4 : 0] spec_insn_srl_rs1_addr; wire [ 4 : 0] spec_insn_srl_rs2_addr; wire [ 4 : 0] spec_insn_srl_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; `endif rvfi_insn_srl insn_srl ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), `endif .spec_valid(spec_insn_srl_valid), .spec_trap(spec_insn_srl_trap), .spec_rs1_addr(spec_insn_srl_rs1_addr), .spec_rs2_addr(spec_insn_srl_rs2_addr), .spec_rd_addr(spec_insn_srl_rd_addr), .spec_rd_wdata(spec_insn_srl_rd_wdata), .spec_pc_wdata(spec_insn_srl_pc_wdata), .spec_mem_addr(spec_insn_srl_mem_addr), .spec_mem_rmask(spec_insn_srl_mem_rmask), .spec_mem_wmask(spec_insn_srl_mem_wmask), .spec_mem_wdata(spec_insn_srl_mem_wdata) ); wire spec_insn_srli_valid; wire spec_insn_srli_trap; wire [ 4 : 0] spec_insn_srli_rs1_addr; wire [ 4 : 0] spec_insn_srli_rs2_addr; wire [ 4 : 0] spec_insn_srli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; `endif rvfi_insn_srli insn_srli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), `endif .spec_valid(spec_insn_srli_valid), .spec_trap(spec_insn_srli_trap), .spec_rs1_addr(spec_insn_srli_rs1_addr), .spec_rs2_addr(spec_insn_srli_rs2_addr), .spec_rd_addr(spec_insn_srli_rd_addr), .spec_rd_wdata(spec_insn_srli_rd_wdata), .spec_pc_wdata(spec_insn_srli_pc_wdata), .spec_mem_addr(spec_insn_srli_mem_addr), .spec_mem_rmask(spec_insn_srli_mem_rmask), .spec_mem_wmask(spec_insn_srli_mem_wmask), .spec_mem_wdata(spec_insn_srli_mem_wdata) ); wire spec_insn_sub_valid; wire spec_insn_sub_trap; wire [ 4 : 0] spec_insn_sub_rs1_addr; wire [ 4 : 0] spec_insn_sub_rs2_addr; wire [ 4 : 0] spec_insn_sub_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; `endif rvfi_insn_sub insn_sub ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), `endif .spec_valid(spec_insn_sub_valid), .spec_trap(spec_insn_sub_trap), .spec_rs1_addr(spec_insn_sub_rs1_addr), .spec_rs2_addr(spec_insn_sub_rs2_addr), .spec_rd_addr(spec_insn_sub_rd_addr), .spec_rd_wdata(spec_insn_sub_rd_wdata), .spec_pc_wdata(spec_insn_sub_pc_wdata), .spec_mem_addr(spec_insn_sub_mem_addr), .spec_mem_rmask(spec_insn_sub_mem_rmask), .spec_mem_wmask(spec_insn_sub_mem_wmask), .spec_mem_wdata(spec_insn_sub_mem_wdata) ); wire spec_insn_sw_valid; wire spec_insn_sw_trap; wire [ 4 : 0] spec_insn_sw_rs1_addr; wire [ 4 : 0] spec_insn_sw_rs2_addr; wire [ 4 : 0] spec_insn_sw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; `endif rvfi_insn_sw insn_sw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), `endif .spec_valid(spec_insn_sw_valid), .spec_trap(spec_insn_sw_trap), .spec_rs1_addr(spec_insn_sw_rs1_addr), .spec_rs2_addr(spec_insn_sw_rs2_addr), .spec_rd_addr(spec_insn_sw_rd_addr), .spec_rd_wdata(spec_insn_sw_rd_wdata), .spec_pc_wdata(spec_insn_sw_pc_wdata), .spec_mem_addr(spec_insn_sw_mem_addr), .spec_mem_rmask(spec_insn_sw_mem_rmask), .spec_mem_wmask(spec_insn_sw_mem_wmask), .spec_mem_wdata(spec_insn_sw_mem_wdata) ); wire spec_insn_xor_valid; wire spec_insn_xor_trap; wire [ 4 : 0] spec_insn_xor_rs1_addr; wire [ 4 : 0] spec_insn_xor_rs2_addr; wire [ 4 : 0] spec_insn_xor_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; `endif rvfi_insn_xor insn_xor ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), `endif .spec_valid(spec_insn_xor_valid), .spec_trap(spec_insn_xor_trap), .spec_rs1_addr(spec_insn_xor_rs1_addr), .spec_rs2_addr(spec_insn_xor_rs2_addr), .spec_rd_addr(spec_insn_xor_rd_addr), .spec_rd_wdata(spec_insn_xor_rd_wdata), .spec_pc_wdata(spec_insn_xor_pc_wdata), .spec_mem_addr(spec_insn_xor_mem_addr), .spec_mem_rmask(spec_insn_xor_mem_rmask), .spec_mem_wmask(spec_insn_xor_mem_wmask), .spec_mem_wdata(spec_insn_xor_mem_wdata) ); wire spec_insn_xori_valid; wire spec_insn_xori_trap; wire [ 4 : 0] spec_insn_xori_rs1_addr; wire [ 4 : 0] spec_insn_xori_rs2_addr; wire [ 4 : 0] spec_insn_xori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; `endif rvfi_insn_xori insn_xori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), `endif .spec_valid(spec_insn_xori_valid), .spec_trap(spec_insn_xori_trap), .spec_rs1_addr(spec_insn_xori_rs1_addr), .spec_rs2_addr(spec_insn_xori_rs2_addr), .spec_rd_addr(spec_insn_xori_rd_addr), .spec_rd_wdata(spec_insn_xori_rd_wdata), .spec_pc_wdata(spec_insn_xori_pc_wdata), .spec_mem_addr(spec_insn_xori_mem_addr), .spec_mem_rmask(spec_insn_xori_mem_rmask), .spec_mem_wmask(spec_insn_xori_mem_wmask), .spec_mem_wdata(spec_insn_xori_mem_wdata) ); assign spec_valid = spec_insn_add_valid ? spec_insn_add_valid : spec_insn_addi_valid ? spec_insn_addi_valid : spec_insn_and_valid ? spec_insn_and_valid : spec_insn_andi_valid ? spec_insn_andi_valid : spec_insn_auipc_valid ? spec_insn_auipc_valid : spec_insn_beq_valid ? spec_insn_beq_valid : spec_insn_bge_valid ? spec_insn_bge_valid : spec_insn_bgeu_valid ? spec_insn_bgeu_valid : spec_insn_blt_valid ? spec_insn_blt_valid : spec_insn_bltu_valid ? spec_insn_bltu_valid : spec_insn_bne_valid ? spec_insn_bne_valid : spec_insn_jal_valid ? spec_insn_jal_valid : spec_insn_jalr_valid ? spec_insn_jalr_valid : spec_insn_lb_valid ? spec_insn_lb_valid : spec_insn_lbu_valid ? spec_insn_lbu_valid : spec_insn_lh_valid ? spec_insn_lh_valid : spec_insn_lhu_valid ? spec_insn_lhu_valid : spec_insn_lui_valid ? spec_insn_lui_valid : spec_insn_lw_valid ? spec_insn_lw_valid : spec_insn_or_valid ? spec_insn_or_valid : spec_insn_ori_valid ? spec_insn_ori_valid : spec_insn_sb_valid ? spec_insn_sb_valid : spec_insn_sh_valid ? spec_insn_sh_valid : spec_insn_sll_valid ? spec_insn_sll_valid : spec_insn_slli_valid ? spec_insn_slli_valid : spec_insn_slt_valid ? spec_insn_slt_valid : spec_insn_slti_valid ? spec_insn_slti_valid : spec_insn_sltiu_valid ? spec_insn_sltiu_valid : spec_insn_sltu_valid ? spec_insn_sltu_valid : spec_insn_sra_valid ? spec_insn_sra_valid : spec_insn_srai_valid ? spec_insn_srai_valid : spec_insn_srl_valid ? spec_insn_srl_valid : spec_insn_srli_valid ? spec_insn_srli_valid : spec_insn_sub_valid ? spec_insn_sub_valid : spec_insn_sw_valid ? spec_insn_sw_valid : spec_insn_xor_valid ? spec_insn_xor_valid : spec_insn_xori_valid ? spec_insn_xori_valid : 0; assign spec_trap = spec_insn_add_valid ? spec_insn_add_trap : spec_insn_addi_valid ? spec_insn_addi_trap : spec_insn_and_valid ? spec_insn_and_trap : spec_insn_andi_valid ? spec_insn_andi_trap : spec_insn_auipc_valid ? spec_insn_auipc_trap : spec_insn_beq_valid ? spec_insn_beq_trap : spec_insn_bge_valid ? spec_insn_bge_trap : spec_insn_bgeu_valid ? spec_insn_bgeu_trap : spec_insn_blt_valid ? spec_insn_blt_trap : spec_insn_bltu_valid ? spec_insn_bltu_trap : spec_insn_bne_valid ? spec_insn_bne_trap : spec_insn_jal_valid ? spec_insn_jal_trap : spec_insn_jalr_valid ? spec_insn_jalr_trap : spec_insn_lb_valid ? spec_insn_lb_trap : spec_insn_lbu_valid ? spec_insn_lbu_trap : spec_insn_lh_valid ? spec_insn_lh_trap : spec_insn_lhu_valid ? spec_insn_lhu_trap : spec_insn_lui_valid ? spec_insn_lui_trap : spec_insn_lw_valid ? spec_insn_lw_trap : spec_insn_or_valid ? spec_insn_or_trap : spec_insn_ori_valid ? spec_insn_ori_trap : spec_insn_sb_valid ? spec_insn_sb_trap : spec_insn_sh_valid ? spec_insn_sh_trap : spec_insn_sll_valid ? spec_insn_sll_trap : spec_insn_slli_valid ? spec_insn_slli_trap : spec_insn_slt_valid ? spec_insn_slt_trap : spec_insn_slti_valid ? spec_insn_slti_trap : spec_insn_sltiu_valid ? spec_insn_sltiu_trap : spec_insn_sltu_valid ? spec_insn_sltu_trap : spec_insn_sra_valid ? spec_insn_sra_trap : spec_insn_srai_valid ? spec_insn_srai_trap : spec_insn_srl_valid ? spec_insn_srl_trap : spec_insn_srli_valid ? spec_insn_srli_trap : spec_insn_sub_valid ? spec_insn_sub_trap : spec_insn_sw_valid ? spec_insn_sw_trap : spec_insn_xor_valid ? spec_insn_xor_trap : spec_insn_xori_valid ? spec_insn_xori_trap : 0; assign spec_rs1_addr = spec_insn_add_valid ? spec_insn_add_rs1_addr : spec_insn_addi_valid ? spec_insn_addi_rs1_addr : spec_insn_and_valid ? spec_insn_and_rs1_addr : spec_insn_andi_valid ? spec_insn_andi_rs1_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : spec_insn_beq_valid ? spec_insn_beq_rs1_addr : spec_insn_bge_valid ? spec_insn_bge_rs1_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : spec_insn_blt_valid ? spec_insn_blt_rs1_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : spec_insn_bne_valid ? spec_insn_bne_rs1_addr : spec_insn_jal_valid ? spec_insn_jal_rs1_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : spec_insn_lb_valid ? spec_insn_lb_rs1_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : spec_insn_lh_valid ? spec_insn_lh_rs1_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : spec_insn_lui_valid ? spec_insn_lui_rs1_addr : spec_insn_lw_valid ? spec_insn_lw_rs1_addr : spec_insn_or_valid ? spec_insn_or_rs1_addr : spec_insn_ori_valid ? spec_insn_ori_rs1_addr : spec_insn_sb_valid ? spec_insn_sb_rs1_addr : spec_insn_sh_valid ? spec_insn_sh_rs1_addr : spec_insn_sll_valid ? spec_insn_sll_rs1_addr : spec_insn_slli_valid ? spec_insn_slli_rs1_addr : spec_insn_slt_valid ? spec_insn_slt_rs1_addr : spec_insn_slti_valid ? spec_insn_slti_rs1_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : spec_insn_sra_valid ? spec_insn_sra_rs1_addr : spec_insn_srai_valid ? spec_insn_srai_rs1_addr : spec_insn_srl_valid ? spec_insn_srl_rs1_addr : spec_insn_srli_valid ? spec_insn_srli_rs1_addr : spec_insn_sub_valid ? spec_insn_sub_rs1_addr : spec_insn_sw_valid ? spec_insn_sw_rs1_addr : spec_insn_xor_valid ? spec_insn_xor_rs1_addr : spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; assign spec_rs2_addr = spec_insn_add_valid ? spec_insn_add_rs2_addr : spec_insn_addi_valid ? spec_insn_addi_rs2_addr : spec_insn_and_valid ? spec_insn_and_rs2_addr : spec_insn_andi_valid ? spec_insn_andi_rs2_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : spec_insn_beq_valid ? spec_insn_beq_rs2_addr : spec_insn_bge_valid ? spec_insn_bge_rs2_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : spec_insn_blt_valid ? spec_insn_blt_rs2_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : spec_insn_bne_valid ? spec_insn_bne_rs2_addr : spec_insn_jal_valid ? spec_insn_jal_rs2_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : spec_insn_lb_valid ? spec_insn_lb_rs2_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : spec_insn_lh_valid ? spec_insn_lh_rs2_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : spec_insn_lui_valid ? spec_insn_lui_rs2_addr : spec_insn_lw_valid ? spec_insn_lw_rs2_addr : spec_insn_or_valid ? spec_insn_or_rs2_addr : spec_insn_ori_valid ? spec_insn_ori_rs2_addr : spec_insn_sb_valid ? spec_insn_sb_rs2_addr : spec_insn_sh_valid ? spec_insn_sh_rs2_addr : spec_insn_sll_valid ? spec_insn_sll_rs2_addr : spec_insn_slli_valid ? spec_insn_slli_rs2_addr : spec_insn_slt_valid ? spec_insn_slt_rs2_addr : spec_insn_slti_valid ? spec_insn_slti_rs2_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : spec_insn_sra_valid ? spec_insn_sra_rs2_addr : spec_insn_srai_valid ? spec_insn_srai_rs2_addr : spec_insn_srl_valid ? spec_insn_srl_rs2_addr : spec_insn_srli_valid ? spec_insn_srli_rs2_addr : spec_insn_sub_valid ? spec_insn_sub_rs2_addr : spec_insn_sw_valid ? spec_insn_sw_rs2_addr : spec_insn_xor_valid ? spec_insn_xor_rs2_addr : spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; assign spec_rd_addr = spec_insn_add_valid ? spec_insn_add_rd_addr : spec_insn_addi_valid ? spec_insn_addi_rd_addr : spec_insn_and_valid ? spec_insn_and_rd_addr : spec_insn_andi_valid ? spec_insn_andi_rd_addr : spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : spec_insn_beq_valid ? spec_insn_beq_rd_addr : spec_insn_bge_valid ? spec_insn_bge_rd_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : spec_insn_blt_valid ? spec_insn_blt_rd_addr : spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : spec_insn_bne_valid ? spec_insn_bne_rd_addr : spec_insn_jal_valid ? spec_insn_jal_rd_addr : spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : spec_insn_lb_valid ? spec_insn_lb_rd_addr : spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : spec_insn_lh_valid ? spec_insn_lh_rd_addr : spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : spec_insn_lui_valid ? spec_insn_lui_rd_addr : spec_insn_lw_valid ? spec_insn_lw_rd_addr : spec_insn_or_valid ? spec_insn_or_rd_addr : spec_insn_ori_valid ? spec_insn_ori_rd_addr : spec_insn_sb_valid ? spec_insn_sb_rd_addr : spec_insn_sh_valid ? spec_insn_sh_rd_addr : spec_insn_sll_valid ? spec_insn_sll_rd_addr : spec_insn_slli_valid ? spec_insn_slli_rd_addr : spec_insn_slt_valid ? spec_insn_slt_rd_addr : spec_insn_slti_valid ? spec_insn_slti_rd_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : spec_insn_sra_valid ? spec_insn_sra_rd_addr : spec_insn_srai_valid ? spec_insn_srai_rd_addr : spec_insn_srl_valid ? spec_insn_srl_rd_addr : spec_insn_srli_valid ? spec_insn_srli_rd_addr : spec_insn_sub_valid ? spec_insn_sub_rd_addr : spec_insn_sw_valid ? spec_insn_sw_rd_addr : spec_insn_xor_valid ? spec_insn_xor_rd_addr : spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; assign spec_rd_wdata = spec_insn_add_valid ? spec_insn_add_rd_wdata : spec_insn_addi_valid ? spec_insn_addi_rd_wdata : spec_insn_and_valid ? spec_insn_and_rd_wdata : spec_insn_andi_valid ? spec_insn_andi_rd_wdata : spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : spec_insn_beq_valid ? spec_insn_beq_rd_wdata : spec_insn_bge_valid ? spec_insn_bge_rd_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : spec_insn_blt_valid ? spec_insn_blt_rd_wdata : spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : spec_insn_bne_valid ? spec_insn_bne_rd_wdata : spec_insn_jal_valid ? spec_insn_jal_rd_wdata : spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : spec_insn_lb_valid ? spec_insn_lb_rd_wdata : spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : spec_insn_lh_valid ? spec_insn_lh_rd_wdata : spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : spec_insn_lui_valid ? spec_insn_lui_rd_wdata : spec_insn_lw_valid ? spec_insn_lw_rd_wdata : spec_insn_or_valid ? spec_insn_or_rd_wdata : spec_insn_ori_valid ? spec_insn_ori_rd_wdata : spec_insn_sb_valid ? spec_insn_sb_rd_wdata : spec_insn_sh_valid ? spec_insn_sh_rd_wdata : spec_insn_sll_valid ? spec_insn_sll_rd_wdata : spec_insn_slli_valid ? spec_insn_slli_rd_wdata : spec_insn_slt_valid ? spec_insn_slt_rd_wdata : spec_insn_slti_valid ? spec_insn_slti_rd_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : spec_insn_sra_valid ? spec_insn_sra_rd_wdata : spec_insn_srai_valid ? spec_insn_srai_rd_wdata : spec_insn_srl_valid ? spec_insn_srl_rd_wdata : spec_insn_srli_valid ? spec_insn_srli_rd_wdata : spec_insn_sub_valid ? spec_insn_sub_rd_wdata : spec_insn_sw_valid ? spec_insn_sw_rd_wdata : spec_insn_xor_valid ? spec_insn_xor_rd_wdata : spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; assign spec_pc_wdata = spec_insn_add_valid ? spec_insn_add_pc_wdata : spec_insn_addi_valid ? spec_insn_addi_pc_wdata : spec_insn_and_valid ? spec_insn_and_pc_wdata : spec_insn_andi_valid ? spec_insn_andi_pc_wdata : spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : spec_insn_beq_valid ? spec_insn_beq_pc_wdata : spec_insn_bge_valid ? spec_insn_bge_pc_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : spec_insn_blt_valid ? spec_insn_blt_pc_wdata : spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : spec_insn_bne_valid ? spec_insn_bne_pc_wdata : spec_insn_jal_valid ? spec_insn_jal_pc_wdata : spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : spec_insn_lb_valid ? spec_insn_lb_pc_wdata : spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : spec_insn_lh_valid ? spec_insn_lh_pc_wdata : spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : spec_insn_lui_valid ? spec_insn_lui_pc_wdata : spec_insn_lw_valid ? spec_insn_lw_pc_wdata : spec_insn_or_valid ? spec_insn_or_pc_wdata : spec_insn_ori_valid ? spec_insn_ori_pc_wdata : spec_insn_sb_valid ? spec_insn_sb_pc_wdata : spec_insn_sh_valid ? spec_insn_sh_pc_wdata : spec_insn_sll_valid ? spec_insn_sll_pc_wdata : spec_insn_slli_valid ? spec_insn_slli_pc_wdata : spec_insn_slt_valid ? spec_insn_slt_pc_wdata : spec_insn_slti_valid ? spec_insn_slti_pc_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : spec_insn_sra_valid ? spec_insn_sra_pc_wdata : spec_insn_srai_valid ? spec_insn_srai_pc_wdata : spec_insn_srl_valid ? spec_insn_srl_pc_wdata : spec_insn_srli_valid ? spec_insn_srli_pc_wdata : spec_insn_sub_valid ? spec_insn_sub_pc_wdata : spec_insn_sw_valid ? spec_insn_sw_pc_wdata : spec_insn_xor_valid ? spec_insn_xor_pc_wdata : spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; assign spec_mem_addr = spec_insn_add_valid ? spec_insn_add_mem_addr : spec_insn_addi_valid ? spec_insn_addi_mem_addr : spec_insn_and_valid ? spec_insn_and_mem_addr : spec_insn_andi_valid ? spec_insn_andi_mem_addr : spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : spec_insn_beq_valid ? spec_insn_beq_mem_addr : spec_insn_bge_valid ? spec_insn_bge_mem_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : spec_insn_blt_valid ? spec_insn_blt_mem_addr : spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : spec_insn_bne_valid ? spec_insn_bne_mem_addr : spec_insn_jal_valid ? spec_insn_jal_mem_addr : spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : spec_insn_lb_valid ? spec_insn_lb_mem_addr : spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : spec_insn_lh_valid ? spec_insn_lh_mem_addr : spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : spec_insn_lui_valid ? spec_insn_lui_mem_addr : spec_insn_lw_valid ? spec_insn_lw_mem_addr : spec_insn_or_valid ? spec_insn_or_mem_addr : spec_insn_ori_valid ? spec_insn_ori_mem_addr : spec_insn_sb_valid ? spec_insn_sb_mem_addr : spec_insn_sh_valid ? spec_insn_sh_mem_addr : spec_insn_sll_valid ? spec_insn_sll_mem_addr : spec_insn_slli_valid ? spec_insn_slli_mem_addr : spec_insn_slt_valid ? spec_insn_slt_mem_addr : spec_insn_slti_valid ? spec_insn_slti_mem_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : spec_insn_sra_valid ? spec_insn_sra_mem_addr : spec_insn_srai_valid ? spec_insn_srai_mem_addr : spec_insn_srl_valid ? spec_insn_srl_mem_addr : spec_insn_srli_valid ? spec_insn_srli_mem_addr : spec_insn_sub_valid ? spec_insn_sub_mem_addr : spec_insn_sw_valid ? spec_insn_sw_mem_addr : spec_insn_xor_valid ? spec_insn_xor_mem_addr : spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; assign spec_mem_rmask = spec_insn_add_valid ? spec_insn_add_mem_rmask : spec_insn_addi_valid ? spec_insn_addi_mem_rmask : spec_insn_and_valid ? spec_insn_and_mem_rmask : spec_insn_andi_valid ? spec_insn_andi_mem_rmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : spec_insn_beq_valid ? spec_insn_beq_mem_rmask : spec_insn_bge_valid ? spec_insn_bge_mem_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : spec_insn_blt_valid ? spec_insn_blt_mem_rmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : spec_insn_bne_valid ? spec_insn_bne_mem_rmask : spec_insn_jal_valid ? spec_insn_jal_mem_rmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : spec_insn_lb_valid ? spec_insn_lb_mem_rmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : spec_insn_lh_valid ? spec_insn_lh_mem_rmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : spec_insn_lui_valid ? spec_insn_lui_mem_rmask : spec_insn_lw_valid ? spec_insn_lw_mem_rmask : spec_insn_or_valid ? spec_insn_or_mem_rmask : spec_insn_ori_valid ? spec_insn_ori_mem_rmask : spec_insn_sb_valid ? spec_insn_sb_mem_rmask : spec_insn_sh_valid ? spec_insn_sh_mem_rmask : spec_insn_sll_valid ? spec_insn_sll_mem_rmask : spec_insn_slli_valid ? spec_insn_slli_mem_rmask : spec_insn_slt_valid ? spec_insn_slt_mem_rmask : spec_insn_slti_valid ? spec_insn_slti_mem_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : spec_insn_sra_valid ? spec_insn_sra_mem_rmask : spec_insn_srai_valid ? spec_insn_srai_mem_rmask : spec_insn_srl_valid ? spec_insn_srl_mem_rmask : spec_insn_srli_valid ? spec_insn_srli_mem_rmask : spec_insn_sub_valid ? spec_insn_sub_mem_rmask : spec_insn_sw_valid ? spec_insn_sw_mem_rmask : spec_insn_xor_valid ? spec_insn_xor_mem_rmask : spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; assign spec_mem_wmask = spec_insn_add_valid ? spec_insn_add_mem_wmask : spec_insn_addi_valid ? spec_insn_addi_mem_wmask : spec_insn_and_valid ? spec_insn_and_mem_wmask : spec_insn_andi_valid ? spec_insn_andi_mem_wmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : spec_insn_beq_valid ? spec_insn_beq_mem_wmask : spec_insn_bge_valid ? spec_insn_bge_mem_wmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : spec_insn_blt_valid ? spec_insn_blt_mem_wmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : spec_insn_bne_valid ? spec_insn_bne_mem_wmask : spec_insn_jal_valid ? spec_insn_jal_mem_wmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : spec_insn_lb_valid ? spec_insn_lb_mem_wmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : spec_insn_lh_valid ? spec_insn_lh_mem_wmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : spec_insn_lui_valid ? spec_insn_lui_mem_wmask : spec_insn_lw_valid ? spec_insn_lw_mem_wmask : spec_insn_or_valid ? spec_insn_or_mem_wmask : spec_insn_ori_valid ? spec_insn_ori_mem_wmask : spec_insn_sb_valid ? spec_insn_sb_mem_wmask : spec_insn_sh_valid ? spec_insn_sh_mem_wmask : spec_insn_sll_valid ? spec_insn_sll_mem_wmask : spec_insn_slli_valid ? spec_insn_slli_mem_wmask : spec_insn_slt_valid ? spec_insn_slt_mem_wmask : spec_insn_slti_valid ? spec_insn_slti_mem_wmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : spec_insn_sra_valid ? spec_insn_sra_mem_wmask : spec_insn_srai_valid ? spec_insn_srai_mem_wmask : spec_insn_srl_valid ? spec_insn_srl_mem_wmask : spec_insn_srli_valid ? spec_insn_srli_mem_wmask : spec_insn_sub_valid ? spec_insn_sub_mem_wmask : spec_insn_sw_valid ? spec_insn_sw_mem_wmask : spec_insn_xor_valid ? spec_insn_xor_mem_wmask : spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; assign spec_mem_wdata = spec_insn_add_valid ? spec_insn_add_mem_wdata : spec_insn_addi_valid ? spec_insn_addi_mem_wdata : spec_insn_and_valid ? spec_insn_and_mem_wdata : spec_insn_andi_valid ? spec_insn_andi_mem_wdata : spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : spec_insn_beq_valid ? spec_insn_beq_mem_wdata : spec_insn_bge_valid ? spec_insn_bge_mem_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : spec_insn_blt_valid ? spec_insn_blt_mem_wdata : spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : spec_insn_bne_valid ? spec_insn_bne_mem_wdata : spec_insn_jal_valid ? spec_insn_jal_mem_wdata : spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : spec_insn_lb_valid ? spec_insn_lb_mem_wdata : spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : spec_insn_lh_valid ? spec_insn_lh_mem_wdata : spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : spec_insn_lui_valid ? spec_insn_lui_mem_wdata : spec_insn_lw_valid ? spec_insn_lw_mem_wdata : spec_insn_or_valid ? spec_insn_or_mem_wdata : spec_insn_ori_valid ? spec_insn_ori_mem_wdata : spec_insn_sb_valid ? spec_insn_sb_mem_wdata : spec_insn_sh_valid ? spec_insn_sh_mem_wdata : spec_insn_sll_valid ? spec_insn_sll_mem_wdata : spec_insn_slli_valid ? spec_insn_slli_mem_wdata : spec_insn_slt_valid ? spec_insn_slt_mem_wdata : spec_insn_slti_valid ? spec_insn_slti_mem_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : spec_insn_sra_valid ? spec_insn_sra_mem_wdata : spec_insn_srai_valid ? spec_insn_srai_mem_wdata : spec_insn_srl_valid ? spec_insn_srl_mem_wdata : spec_insn_srli_valid ? spec_insn_srli_mem_wdata : spec_insn_sub_valid ? spec_insn_sub_mem_wdata : spec_insn_sw_valid ? spec_insn_sw_mem_wdata : spec_insn_xor_valid ? spec_insn_xor_mem_wdata : spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; `ifdef RISCV_FORMAL_CSR_MISA assign spec_csr_misa_rmask = spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; `endif endmodule ================================================ FILE: insns/isa_rv32ic.txt ================================================ add addi and andi auipc beq bge bgeu blt bltu bne c_add c_addi c_addi16sp c_addi4spn c_and c_andi c_beqz c_bnez c_j c_jal c_jalr c_jr c_li c_lui c_lw c_lwsp c_mv c_or c_slli c_srai c_srli c_sub c_sw c_swsp c_xor jal jalr lb lbu lh lhu lui lw or ori sb sh sll slli slt slti sltiu sltu sra srai srl srli sub sw xor xori ================================================ FILE: insns/isa_rv32ic.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_isa_rv32ic ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); wire spec_insn_add_valid; wire spec_insn_add_trap; wire [ 4 : 0] spec_insn_add_rs1_addr; wire [ 4 : 0] spec_insn_add_rs2_addr; wire [ 4 : 0] spec_insn_add_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; `endif rvfi_insn_add insn_add ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), `endif .spec_valid(spec_insn_add_valid), .spec_trap(spec_insn_add_trap), .spec_rs1_addr(spec_insn_add_rs1_addr), .spec_rs2_addr(spec_insn_add_rs2_addr), .spec_rd_addr(spec_insn_add_rd_addr), .spec_rd_wdata(spec_insn_add_rd_wdata), .spec_pc_wdata(spec_insn_add_pc_wdata), .spec_mem_addr(spec_insn_add_mem_addr), .spec_mem_rmask(spec_insn_add_mem_rmask), .spec_mem_wmask(spec_insn_add_mem_wmask), .spec_mem_wdata(spec_insn_add_mem_wdata) ); wire spec_insn_addi_valid; wire spec_insn_addi_trap; wire [ 4 : 0] spec_insn_addi_rs1_addr; wire [ 4 : 0] spec_insn_addi_rs2_addr; wire [ 4 : 0] spec_insn_addi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; `endif rvfi_insn_addi insn_addi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), `endif .spec_valid(spec_insn_addi_valid), .spec_trap(spec_insn_addi_trap), .spec_rs1_addr(spec_insn_addi_rs1_addr), .spec_rs2_addr(spec_insn_addi_rs2_addr), .spec_rd_addr(spec_insn_addi_rd_addr), .spec_rd_wdata(spec_insn_addi_rd_wdata), .spec_pc_wdata(spec_insn_addi_pc_wdata), .spec_mem_addr(spec_insn_addi_mem_addr), .spec_mem_rmask(spec_insn_addi_mem_rmask), .spec_mem_wmask(spec_insn_addi_mem_wmask), .spec_mem_wdata(spec_insn_addi_mem_wdata) ); wire spec_insn_and_valid; wire spec_insn_and_trap; wire [ 4 : 0] spec_insn_and_rs1_addr; wire [ 4 : 0] spec_insn_and_rs2_addr; wire [ 4 : 0] spec_insn_and_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; `endif rvfi_insn_and insn_and ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), `endif .spec_valid(spec_insn_and_valid), .spec_trap(spec_insn_and_trap), .spec_rs1_addr(spec_insn_and_rs1_addr), .spec_rs2_addr(spec_insn_and_rs2_addr), .spec_rd_addr(spec_insn_and_rd_addr), .spec_rd_wdata(spec_insn_and_rd_wdata), .spec_pc_wdata(spec_insn_and_pc_wdata), .spec_mem_addr(spec_insn_and_mem_addr), .spec_mem_rmask(spec_insn_and_mem_rmask), .spec_mem_wmask(spec_insn_and_mem_wmask), .spec_mem_wdata(spec_insn_and_mem_wdata) ); wire spec_insn_andi_valid; wire spec_insn_andi_trap; wire [ 4 : 0] spec_insn_andi_rs1_addr; wire [ 4 : 0] spec_insn_andi_rs2_addr; wire [ 4 : 0] spec_insn_andi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; `endif rvfi_insn_andi insn_andi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), `endif .spec_valid(spec_insn_andi_valid), .spec_trap(spec_insn_andi_trap), .spec_rs1_addr(spec_insn_andi_rs1_addr), .spec_rs2_addr(spec_insn_andi_rs2_addr), .spec_rd_addr(spec_insn_andi_rd_addr), .spec_rd_wdata(spec_insn_andi_rd_wdata), .spec_pc_wdata(spec_insn_andi_pc_wdata), .spec_mem_addr(spec_insn_andi_mem_addr), .spec_mem_rmask(spec_insn_andi_mem_rmask), .spec_mem_wmask(spec_insn_andi_mem_wmask), .spec_mem_wdata(spec_insn_andi_mem_wdata) ); wire spec_insn_auipc_valid; wire spec_insn_auipc_trap; wire [ 4 : 0] spec_insn_auipc_rs1_addr; wire [ 4 : 0] spec_insn_auipc_rs2_addr; wire [ 4 : 0] spec_insn_auipc_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; `endif rvfi_insn_auipc insn_auipc ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), `endif .spec_valid(spec_insn_auipc_valid), .spec_trap(spec_insn_auipc_trap), .spec_rs1_addr(spec_insn_auipc_rs1_addr), .spec_rs2_addr(spec_insn_auipc_rs2_addr), .spec_rd_addr(spec_insn_auipc_rd_addr), .spec_rd_wdata(spec_insn_auipc_rd_wdata), .spec_pc_wdata(spec_insn_auipc_pc_wdata), .spec_mem_addr(spec_insn_auipc_mem_addr), .spec_mem_rmask(spec_insn_auipc_mem_rmask), .spec_mem_wmask(spec_insn_auipc_mem_wmask), .spec_mem_wdata(spec_insn_auipc_mem_wdata) ); wire spec_insn_beq_valid; wire spec_insn_beq_trap; wire [ 4 : 0] spec_insn_beq_rs1_addr; wire [ 4 : 0] spec_insn_beq_rs2_addr; wire [ 4 : 0] spec_insn_beq_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; `endif rvfi_insn_beq insn_beq ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), `endif .spec_valid(spec_insn_beq_valid), .spec_trap(spec_insn_beq_trap), .spec_rs1_addr(spec_insn_beq_rs1_addr), .spec_rs2_addr(spec_insn_beq_rs2_addr), .spec_rd_addr(spec_insn_beq_rd_addr), .spec_rd_wdata(spec_insn_beq_rd_wdata), .spec_pc_wdata(spec_insn_beq_pc_wdata), .spec_mem_addr(spec_insn_beq_mem_addr), .spec_mem_rmask(spec_insn_beq_mem_rmask), .spec_mem_wmask(spec_insn_beq_mem_wmask), .spec_mem_wdata(spec_insn_beq_mem_wdata) ); wire spec_insn_bge_valid; wire spec_insn_bge_trap; wire [ 4 : 0] spec_insn_bge_rs1_addr; wire [ 4 : 0] spec_insn_bge_rs2_addr; wire [ 4 : 0] spec_insn_bge_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; `endif rvfi_insn_bge insn_bge ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), `endif .spec_valid(spec_insn_bge_valid), .spec_trap(spec_insn_bge_trap), .spec_rs1_addr(spec_insn_bge_rs1_addr), .spec_rs2_addr(spec_insn_bge_rs2_addr), .spec_rd_addr(spec_insn_bge_rd_addr), .spec_rd_wdata(spec_insn_bge_rd_wdata), .spec_pc_wdata(spec_insn_bge_pc_wdata), .spec_mem_addr(spec_insn_bge_mem_addr), .spec_mem_rmask(spec_insn_bge_mem_rmask), .spec_mem_wmask(spec_insn_bge_mem_wmask), .spec_mem_wdata(spec_insn_bge_mem_wdata) ); wire spec_insn_bgeu_valid; wire spec_insn_bgeu_trap; wire [ 4 : 0] spec_insn_bgeu_rs1_addr; wire [ 4 : 0] spec_insn_bgeu_rs2_addr; wire [ 4 : 0] spec_insn_bgeu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; `endif rvfi_insn_bgeu insn_bgeu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), `endif .spec_valid(spec_insn_bgeu_valid), .spec_trap(spec_insn_bgeu_trap), .spec_rs1_addr(spec_insn_bgeu_rs1_addr), .spec_rs2_addr(spec_insn_bgeu_rs2_addr), .spec_rd_addr(spec_insn_bgeu_rd_addr), .spec_rd_wdata(spec_insn_bgeu_rd_wdata), .spec_pc_wdata(spec_insn_bgeu_pc_wdata), .spec_mem_addr(spec_insn_bgeu_mem_addr), .spec_mem_rmask(spec_insn_bgeu_mem_rmask), .spec_mem_wmask(spec_insn_bgeu_mem_wmask), .spec_mem_wdata(spec_insn_bgeu_mem_wdata) ); wire spec_insn_blt_valid; wire spec_insn_blt_trap; wire [ 4 : 0] spec_insn_blt_rs1_addr; wire [ 4 : 0] spec_insn_blt_rs2_addr; wire [ 4 : 0] spec_insn_blt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; `endif rvfi_insn_blt insn_blt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), `endif .spec_valid(spec_insn_blt_valid), .spec_trap(spec_insn_blt_trap), .spec_rs1_addr(spec_insn_blt_rs1_addr), .spec_rs2_addr(spec_insn_blt_rs2_addr), .spec_rd_addr(spec_insn_blt_rd_addr), .spec_rd_wdata(spec_insn_blt_rd_wdata), .spec_pc_wdata(spec_insn_blt_pc_wdata), .spec_mem_addr(spec_insn_blt_mem_addr), .spec_mem_rmask(spec_insn_blt_mem_rmask), .spec_mem_wmask(spec_insn_blt_mem_wmask), .spec_mem_wdata(spec_insn_blt_mem_wdata) ); wire spec_insn_bltu_valid; wire spec_insn_bltu_trap; wire [ 4 : 0] spec_insn_bltu_rs1_addr; wire [ 4 : 0] spec_insn_bltu_rs2_addr; wire [ 4 : 0] spec_insn_bltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; `endif rvfi_insn_bltu insn_bltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), `endif .spec_valid(spec_insn_bltu_valid), .spec_trap(spec_insn_bltu_trap), .spec_rs1_addr(spec_insn_bltu_rs1_addr), .spec_rs2_addr(spec_insn_bltu_rs2_addr), .spec_rd_addr(spec_insn_bltu_rd_addr), .spec_rd_wdata(spec_insn_bltu_rd_wdata), .spec_pc_wdata(spec_insn_bltu_pc_wdata), .spec_mem_addr(spec_insn_bltu_mem_addr), .spec_mem_rmask(spec_insn_bltu_mem_rmask), .spec_mem_wmask(spec_insn_bltu_mem_wmask), .spec_mem_wdata(spec_insn_bltu_mem_wdata) ); wire spec_insn_bne_valid; wire spec_insn_bne_trap; wire [ 4 : 0] spec_insn_bne_rs1_addr; wire [ 4 : 0] spec_insn_bne_rs2_addr; wire [ 4 : 0] spec_insn_bne_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; `endif rvfi_insn_bne insn_bne ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), `endif .spec_valid(spec_insn_bne_valid), .spec_trap(spec_insn_bne_trap), .spec_rs1_addr(spec_insn_bne_rs1_addr), .spec_rs2_addr(spec_insn_bne_rs2_addr), .spec_rd_addr(spec_insn_bne_rd_addr), .spec_rd_wdata(spec_insn_bne_rd_wdata), .spec_pc_wdata(spec_insn_bne_pc_wdata), .spec_mem_addr(spec_insn_bne_mem_addr), .spec_mem_rmask(spec_insn_bne_mem_rmask), .spec_mem_wmask(spec_insn_bne_mem_wmask), .spec_mem_wdata(spec_insn_bne_mem_wdata) ); wire spec_insn_c_add_valid; wire spec_insn_c_add_trap; wire [ 4 : 0] spec_insn_c_add_rs1_addr; wire [ 4 : 0] spec_insn_c_add_rs2_addr; wire [ 4 : 0] spec_insn_c_add_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_csr_misa_rmask; `endif rvfi_insn_c_add insn_c_add ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_add_csr_misa_rmask), `endif .spec_valid(spec_insn_c_add_valid), .spec_trap(spec_insn_c_add_trap), .spec_rs1_addr(spec_insn_c_add_rs1_addr), .spec_rs2_addr(spec_insn_c_add_rs2_addr), .spec_rd_addr(spec_insn_c_add_rd_addr), .spec_rd_wdata(spec_insn_c_add_rd_wdata), .spec_pc_wdata(spec_insn_c_add_pc_wdata), .spec_mem_addr(spec_insn_c_add_mem_addr), .spec_mem_rmask(spec_insn_c_add_mem_rmask), .spec_mem_wmask(spec_insn_c_add_mem_wmask), .spec_mem_wdata(spec_insn_c_add_mem_wdata) ); wire spec_insn_c_addi_valid; wire spec_insn_c_addi_trap; wire [ 4 : 0] spec_insn_c_addi_rs1_addr; wire [ 4 : 0] spec_insn_c_addi_rs2_addr; wire [ 4 : 0] spec_insn_c_addi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_csr_misa_rmask; `endif rvfi_insn_c_addi insn_c_addi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addi_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addi_valid), .spec_trap(spec_insn_c_addi_trap), .spec_rs1_addr(spec_insn_c_addi_rs1_addr), .spec_rs2_addr(spec_insn_c_addi_rs2_addr), .spec_rd_addr(spec_insn_c_addi_rd_addr), .spec_rd_wdata(spec_insn_c_addi_rd_wdata), .spec_pc_wdata(spec_insn_c_addi_pc_wdata), .spec_mem_addr(spec_insn_c_addi_mem_addr), .spec_mem_rmask(spec_insn_c_addi_mem_rmask), .spec_mem_wmask(spec_insn_c_addi_mem_wmask), .spec_mem_wdata(spec_insn_c_addi_mem_wdata) ); wire spec_insn_c_addi16sp_valid; wire spec_insn_c_addi16sp_trap; wire [ 4 : 0] spec_insn_c_addi16sp_rs1_addr; wire [ 4 : 0] spec_insn_c_addi16sp_rs2_addr; wire [ 4 : 0] spec_insn_c_addi16sp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_csr_misa_rmask; `endif rvfi_insn_c_addi16sp insn_c_addi16sp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addi16sp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addi16sp_valid), .spec_trap(spec_insn_c_addi16sp_trap), .spec_rs1_addr(spec_insn_c_addi16sp_rs1_addr), .spec_rs2_addr(spec_insn_c_addi16sp_rs2_addr), .spec_rd_addr(spec_insn_c_addi16sp_rd_addr), .spec_rd_wdata(spec_insn_c_addi16sp_rd_wdata), .spec_pc_wdata(spec_insn_c_addi16sp_pc_wdata), .spec_mem_addr(spec_insn_c_addi16sp_mem_addr), .spec_mem_rmask(spec_insn_c_addi16sp_mem_rmask), .spec_mem_wmask(spec_insn_c_addi16sp_mem_wmask), .spec_mem_wdata(spec_insn_c_addi16sp_mem_wdata) ); wire spec_insn_c_addi4spn_valid; wire spec_insn_c_addi4spn_trap; wire [ 4 : 0] spec_insn_c_addi4spn_rs1_addr; wire [ 4 : 0] spec_insn_c_addi4spn_rs2_addr; wire [ 4 : 0] spec_insn_c_addi4spn_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_csr_misa_rmask; `endif rvfi_insn_c_addi4spn insn_c_addi4spn ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addi4spn_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addi4spn_valid), .spec_trap(spec_insn_c_addi4spn_trap), .spec_rs1_addr(spec_insn_c_addi4spn_rs1_addr), .spec_rs2_addr(spec_insn_c_addi4spn_rs2_addr), .spec_rd_addr(spec_insn_c_addi4spn_rd_addr), .spec_rd_wdata(spec_insn_c_addi4spn_rd_wdata), .spec_pc_wdata(spec_insn_c_addi4spn_pc_wdata), .spec_mem_addr(spec_insn_c_addi4spn_mem_addr), .spec_mem_rmask(spec_insn_c_addi4spn_mem_rmask), .spec_mem_wmask(spec_insn_c_addi4spn_mem_wmask), .spec_mem_wdata(spec_insn_c_addi4spn_mem_wdata) ); wire spec_insn_c_and_valid; wire spec_insn_c_and_trap; wire [ 4 : 0] spec_insn_c_and_rs1_addr; wire [ 4 : 0] spec_insn_c_and_rs2_addr; wire [ 4 : 0] spec_insn_c_and_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_csr_misa_rmask; `endif rvfi_insn_c_and insn_c_and ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_and_csr_misa_rmask), `endif .spec_valid(spec_insn_c_and_valid), .spec_trap(spec_insn_c_and_trap), .spec_rs1_addr(spec_insn_c_and_rs1_addr), .spec_rs2_addr(spec_insn_c_and_rs2_addr), .spec_rd_addr(spec_insn_c_and_rd_addr), .spec_rd_wdata(spec_insn_c_and_rd_wdata), .spec_pc_wdata(spec_insn_c_and_pc_wdata), .spec_mem_addr(spec_insn_c_and_mem_addr), .spec_mem_rmask(spec_insn_c_and_mem_rmask), .spec_mem_wmask(spec_insn_c_and_mem_wmask), .spec_mem_wdata(spec_insn_c_and_mem_wdata) ); wire spec_insn_c_andi_valid; wire spec_insn_c_andi_trap; wire [ 4 : 0] spec_insn_c_andi_rs1_addr; wire [ 4 : 0] spec_insn_c_andi_rs2_addr; wire [ 4 : 0] spec_insn_c_andi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_csr_misa_rmask; `endif rvfi_insn_c_andi insn_c_andi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_andi_csr_misa_rmask), `endif .spec_valid(spec_insn_c_andi_valid), .spec_trap(spec_insn_c_andi_trap), .spec_rs1_addr(spec_insn_c_andi_rs1_addr), .spec_rs2_addr(spec_insn_c_andi_rs2_addr), .spec_rd_addr(spec_insn_c_andi_rd_addr), .spec_rd_wdata(spec_insn_c_andi_rd_wdata), .spec_pc_wdata(spec_insn_c_andi_pc_wdata), .spec_mem_addr(spec_insn_c_andi_mem_addr), .spec_mem_rmask(spec_insn_c_andi_mem_rmask), .spec_mem_wmask(spec_insn_c_andi_mem_wmask), .spec_mem_wdata(spec_insn_c_andi_mem_wdata) ); wire spec_insn_c_beqz_valid; wire spec_insn_c_beqz_trap; wire [ 4 : 0] spec_insn_c_beqz_rs1_addr; wire [ 4 : 0] spec_insn_c_beqz_rs2_addr; wire [ 4 : 0] spec_insn_c_beqz_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_csr_misa_rmask; `endif rvfi_insn_c_beqz insn_c_beqz ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_beqz_csr_misa_rmask), `endif .spec_valid(spec_insn_c_beqz_valid), .spec_trap(spec_insn_c_beqz_trap), .spec_rs1_addr(spec_insn_c_beqz_rs1_addr), .spec_rs2_addr(spec_insn_c_beqz_rs2_addr), .spec_rd_addr(spec_insn_c_beqz_rd_addr), .spec_rd_wdata(spec_insn_c_beqz_rd_wdata), .spec_pc_wdata(spec_insn_c_beqz_pc_wdata), .spec_mem_addr(spec_insn_c_beqz_mem_addr), .spec_mem_rmask(spec_insn_c_beqz_mem_rmask), .spec_mem_wmask(spec_insn_c_beqz_mem_wmask), .spec_mem_wdata(spec_insn_c_beqz_mem_wdata) ); wire spec_insn_c_bnez_valid; wire spec_insn_c_bnez_trap; wire [ 4 : 0] spec_insn_c_bnez_rs1_addr; wire [ 4 : 0] spec_insn_c_bnez_rs2_addr; wire [ 4 : 0] spec_insn_c_bnez_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_csr_misa_rmask; `endif rvfi_insn_c_bnez insn_c_bnez ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_bnez_csr_misa_rmask), `endif .spec_valid(spec_insn_c_bnez_valid), .spec_trap(spec_insn_c_bnez_trap), .spec_rs1_addr(spec_insn_c_bnez_rs1_addr), .spec_rs2_addr(spec_insn_c_bnez_rs2_addr), .spec_rd_addr(spec_insn_c_bnez_rd_addr), .spec_rd_wdata(spec_insn_c_bnez_rd_wdata), .spec_pc_wdata(spec_insn_c_bnez_pc_wdata), .spec_mem_addr(spec_insn_c_bnez_mem_addr), .spec_mem_rmask(spec_insn_c_bnez_mem_rmask), .spec_mem_wmask(spec_insn_c_bnez_mem_wmask), .spec_mem_wdata(spec_insn_c_bnez_mem_wdata) ); wire spec_insn_c_j_valid; wire spec_insn_c_j_trap; wire [ 4 : 0] spec_insn_c_j_rs1_addr; wire [ 4 : 0] spec_insn_c_j_rs2_addr; wire [ 4 : 0] spec_insn_c_j_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_csr_misa_rmask; `endif rvfi_insn_c_j insn_c_j ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_j_csr_misa_rmask), `endif .spec_valid(spec_insn_c_j_valid), .spec_trap(spec_insn_c_j_trap), .spec_rs1_addr(spec_insn_c_j_rs1_addr), .spec_rs2_addr(spec_insn_c_j_rs2_addr), .spec_rd_addr(spec_insn_c_j_rd_addr), .spec_rd_wdata(spec_insn_c_j_rd_wdata), .spec_pc_wdata(spec_insn_c_j_pc_wdata), .spec_mem_addr(spec_insn_c_j_mem_addr), .spec_mem_rmask(spec_insn_c_j_mem_rmask), .spec_mem_wmask(spec_insn_c_j_mem_wmask), .spec_mem_wdata(spec_insn_c_j_mem_wdata) ); wire spec_insn_c_jal_valid; wire spec_insn_c_jal_trap; wire [ 4 : 0] spec_insn_c_jal_rs1_addr; wire [ 4 : 0] spec_insn_c_jal_rs2_addr; wire [ 4 : 0] spec_insn_c_jal_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jal_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jal_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jal_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jal_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jal_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jal_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jal_csr_misa_rmask; `endif rvfi_insn_c_jal insn_c_jal ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_jal_csr_misa_rmask), `endif .spec_valid(spec_insn_c_jal_valid), .spec_trap(spec_insn_c_jal_trap), .spec_rs1_addr(spec_insn_c_jal_rs1_addr), .spec_rs2_addr(spec_insn_c_jal_rs2_addr), .spec_rd_addr(spec_insn_c_jal_rd_addr), .spec_rd_wdata(spec_insn_c_jal_rd_wdata), .spec_pc_wdata(spec_insn_c_jal_pc_wdata), .spec_mem_addr(spec_insn_c_jal_mem_addr), .spec_mem_rmask(spec_insn_c_jal_mem_rmask), .spec_mem_wmask(spec_insn_c_jal_mem_wmask), .spec_mem_wdata(spec_insn_c_jal_mem_wdata) ); wire spec_insn_c_jalr_valid; wire spec_insn_c_jalr_trap; wire [ 4 : 0] spec_insn_c_jalr_rs1_addr; wire [ 4 : 0] spec_insn_c_jalr_rs2_addr; wire [ 4 : 0] spec_insn_c_jalr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_csr_misa_rmask; `endif rvfi_insn_c_jalr insn_c_jalr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_jalr_csr_misa_rmask), `endif .spec_valid(spec_insn_c_jalr_valid), .spec_trap(spec_insn_c_jalr_trap), .spec_rs1_addr(spec_insn_c_jalr_rs1_addr), .spec_rs2_addr(spec_insn_c_jalr_rs2_addr), .spec_rd_addr(spec_insn_c_jalr_rd_addr), .spec_rd_wdata(spec_insn_c_jalr_rd_wdata), .spec_pc_wdata(spec_insn_c_jalr_pc_wdata), .spec_mem_addr(spec_insn_c_jalr_mem_addr), .spec_mem_rmask(spec_insn_c_jalr_mem_rmask), .spec_mem_wmask(spec_insn_c_jalr_mem_wmask), .spec_mem_wdata(spec_insn_c_jalr_mem_wdata) ); wire spec_insn_c_jr_valid; wire spec_insn_c_jr_trap; wire [ 4 : 0] spec_insn_c_jr_rs1_addr; wire [ 4 : 0] spec_insn_c_jr_rs2_addr; wire [ 4 : 0] spec_insn_c_jr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_csr_misa_rmask; `endif rvfi_insn_c_jr insn_c_jr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_jr_csr_misa_rmask), `endif .spec_valid(spec_insn_c_jr_valid), .spec_trap(spec_insn_c_jr_trap), .spec_rs1_addr(spec_insn_c_jr_rs1_addr), .spec_rs2_addr(spec_insn_c_jr_rs2_addr), .spec_rd_addr(spec_insn_c_jr_rd_addr), .spec_rd_wdata(spec_insn_c_jr_rd_wdata), .spec_pc_wdata(spec_insn_c_jr_pc_wdata), .spec_mem_addr(spec_insn_c_jr_mem_addr), .spec_mem_rmask(spec_insn_c_jr_mem_rmask), .spec_mem_wmask(spec_insn_c_jr_mem_wmask), .spec_mem_wdata(spec_insn_c_jr_mem_wdata) ); wire spec_insn_c_li_valid; wire spec_insn_c_li_trap; wire [ 4 : 0] spec_insn_c_li_rs1_addr; wire [ 4 : 0] spec_insn_c_li_rs2_addr; wire [ 4 : 0] spec_insn_c_li_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_csr_misa_rmask; `endif rvfi_insn_c_li insn_c_li ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_li_csr_misa_rmask), `endif .spec_valid(spec_insn_c_li_valid), .spec_trap(spec_insn_c_li_trap), .spec_rs1_addr(spec_insn_c_li_rs1_addr), .spec_rs2_addr(spec_insn_c_li_rs2_addr), .spec_rd_addr(spec_insn_c_li_rd_addr), .spec_rd_wdata(spec_insn_c_li_rd_wdata), .spec_pc_wdata(spec_insn_c_li_pc_wdata), .spec_mem_addr(spec_insn_c_li_mem_addr), .spec_mem_rmask(spec_insn_c_li_mem_rmask), .spec_mem_wmask(spec_insn_c_li_mem_wmask), .spec_mem_wdata(spec_insn_c_li_mem_wdata) ); wire spec_insn_c_lui_valid; wire spec_insn_c_lui_trap; wire [ 4 : 0] spec_insn_c_lui_rs1_addr; wire [ 4 : 0] spec_insn_c_lui_rs2_addr; wire [ 4 : 0] spec_insn_c_lui_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_csr_misa_rmask; `endif rvfi_insn_c_lui insn_c_lui ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_lui_csr_misa_rmask), `endif .spec_valid(spec_insn_c_lui_valid), .spec_trap(spec_insn_c_lui_trap), .spec_rs1_addr(spec_insn_c_lui_rs1_addr), .spec_rs2_addr(spec_insn_c_lui_rs2_addr), .spec_rd_addr(spec_insn_c_lui_rd_addr), .spec_rd_wdata(spec_insn_c_lui_rd_wdata), .spec_pc_wdata(spec_insn_c_lui_pc_wdata), .spec_mem_addr(spec_insn_c_lui_mem_addr), .spec_mem_rmask(spec_insn_c_lui_mem_rmask), .spec_mem_wmask(spec_insn_c_lui_mem_wmask), .spec_mem_wdata(spec_insn_c_lui_mem_wdata) ); wire spec_insn_c_lw_valid; wire spec_insn_c_lw_trap; wire [ 4 : 0] spec_insn_c_lw_rs1_addr; wire [ 4 : 0] spec_insn_c_lw_rs2_addr; wire [ 4 : 0] spec_insn_c_lw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_csr_misa_rmask; `endif rvfi_insn_c_lw insn_c_lw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_lw_csr_misa_rmask), `endif .spec_valid(spec_insn_c_lw_valid), .spec_trap(spec_insn_c_lw_trap), .spec_rs1_addr(spec_insn_c_lw_rs1_addr), .spec_rs2_addr(spec_insn_c_lw_rs2_addr), .spec_rd_addr(spec_insn_c_lw_rd_addr), .spec_rd_wdata(spec_insn_c_lw_rd_wdata), .spec_pc_wdata(spec_insn_c_lw_pc_wdata), .spec_mem_addr(spec_insn_c_lw_mem_addr), .spec_mem_rmask(spec_insn_c_lw_mem_rmask), .spec_mem_wmask(spec_insn_c_lw_mem_wmask), .spec_mem_wdata(spec_insn_c_lw_mem_wdata) ); wire spec_insn_c_lwsp_valid; wire spec_insn_c_lwsp_trap; wire [ 4 : 0] spec_insn_c_lwsp_rs1_addr; wire [ 4 : 0] spec_insn_c_lwsp_rs2_addr; wire [ 4 : 0] spec_insn_c_lwsp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_csr_misa_rmask; `endif rvfi_insn_c_lwsp insn_c_lwsp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_lwsp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_lwsp_valid), .spec_trap(spec_insn_c_lwsp_trap), .spec_rs1_addr(spec_insn_c_lwsp_rs1_addr), .spec_rs2_addr(spec_insn_c_lwsp_rs2_addr), .spec_rd_addr(spec_insn_c_lwsp_rd_addr), .spec_rd_wdata(spec_insn_c_lwsp_rd_wdata), .spec_pc_wdata(spec_insn_c_lwsp_pc_wdata), .spec_mem_addr(spec_insn_c_lwsp_mem_addr), .spec_mem_rmask(spec_insn_c_lwsp_mem_rmask), .spec_mem_wmask(spec_insn_c_lwsp_mem_wmask), .spec_mem_wdata(spec_insn_c_lwsp_mem_wdata) ); wire spec_insn_c_mv_valid; wire spec_insn_c_mv_trap; wire [ 4 : 0] spec_insn_c_mv_rs1_addr; wire [ 4 : 0] spec_insn_c_mv_rs2_addr; wire [ 4 : 0] spec_insn_c_mv_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_csr_misa_rmask; `endif rvfi_insn_c_mv insn_c_mv ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_mv_csr_misa_rmask), `endif .spec_valid(spec_insn_c_mv_valid), .spec_trap(spec_insn_c_mv_trap), .spec_rs1_addr(spec_insn_c_mv_rs1_addr), .spec_rs2_addr(spec_insn_c_mv_rs2_addr), .spec_rd_addr(spec_insn_c_mv_rd_addr), .spec_rd_wdata(spec_insn_c_mv_rd_wdata), .spec_pc_wdata(spec_insn_c_mv_pc_wdata), .spec_mem_addr(spec_insn_c_mv_mem_addr), .spec_mem_rmask(spec_insn_c_mv_mem_rmask), .spec_mem_wmask(spec_insn_c_mv_mem_wmask), .spec_mem_wdata(spec_insn_c_mv_mem_wdata) ); wire spec_insn_c_or_valid; wire spec_insn_c_or_trap; wire [ 4 : 0] spec_insn_c_or_rs1_addr; wire [ 4 : 0] spec_insn_c_or_rs2_addr; wire [ 4 : 0] spec_insn_c_or_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_csr_misa_rmask; `endif rvfi_insn_c_or insn_c_or ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_or_csr_misa_rmask), `endif .spec_valid(spec_insn_c_or_valid), .spec_trap(spec_insn_c_or_trap), .spec_rs1_addr(spec_insn_c_or_rs1_addr), .spec_rs2_addr(spec_insn_c_or_rs2_addr), .spec_rd_addr(spec_insn_c_or_rd_addr), .spec_rd_wdata(spec_insn_c_or_rd_wdata), .spec_pc_wdata(spec_insn_c_or_pc_wdata), .spec_mem_addr(spec_insn_c_or_mem_addr), .spec_mem_rmask(spec_insn_c_or_mem_rmask), .spec_mem_wmask(spec_insn_c_or_mem_wmask), .spec_mem_wdata(spec_insn_c_or_mem_wdata) ); wire spec_insn_c_slli_valid; wire spec_insn_c_slli_trap; wire [ 4 : 0] spec_insn_c_slli_rs1_addr; wire [ 4 : 0] spec_insn_c_slli_rs2_addr; wire [ 4 : 0] spec_insn_c_slli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_csr_misa_rmask; `endif rvfi_insn_c_slli insn_c_slli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_slli_csr_misa_rmask), `endif .spec_valid(spec_insn_c_slli_valid), .spec_trap(spec_insn_c_slli_trap), .spec_rs1_addr(spec_insn_c_slli_rs1_addr), .spec_rs2_addr(spec_insn_c_slli_rs2_addr), .spec_rd_addr(spec_insn_c_slli_rd_addr), .spec_rd_wdata(spec_insn_c_slli_rd_wdata), .spec_pc_wdata(spec_insn_c_slli_pc_wdata), .spec_mem_addr(spec_insn_c_slli_mem_addr), .spec_mem_rmask(spec_insn_c_slli_mem_rmask), .spec_mem_wmask(spec_insn_c_slli_mem_wmask), .spec_mem_wdata(spec_insn_c_slli_mem_wdata) ); wire spec_insn_c_srai_valid; wire spec_insn_c_srai_trap; wire [ 4 : 0] spec_insn_c_srai_rs1_addr; wire [ 4 : 0] spec_insn_c_srai_rs2_addr; wire [ 4 : 0] spec_insn_c_srai_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_csr_misa_rmask; `endif rvfi_insn_c_srai insn_c_srai ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_srai_csr_misa_rmask), `endif .spec_valid(spec_insn_c_srai_valid), .spec_trap(spec_insn_c_srai_trap), .spec_rs1_addr(spec_insn_c_srai_rs1_addr), .spec_rs2_addr(spec_insn_c_srai_rs2_addr), .spec_rd_addr(spec_insn_c_srai_rd_addr), .spec_rd_wdata(spec_insn_c_srai_rd_wdata), .spec_pc_wdata(spec_insn_c_srai_pc_wdata), .spec_mem_addr(spec_insn_c_srai_mem_addr), .spec_mem_rmask(spec_insn_c_srai_mem_rmask), .spec_mem_wmask(spec_insn_c_srai_mem_wmask), .spec_mem_wdata(spec_insn_c_srai_mem_wdata) ); wire spec_insn_c_srli_valid; wire spec_insn_c_srli_trap; wire [ 4 : 0] spec_insn_c_srli_rs1_addr; wire [ 4 : 0] spec_insn_c_srli_rs2_addr; wire [ 4 : 0] spec_insn_c_srli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_csr_misa_rmask; `endif rvfi_insn_c_srli insn_c_srli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_srli_csr_misa_rmask), `endif .spec_valid(spec_insn_c_srli_valid), .spec_trap(spec_insn_c_srli_trap), .spec_rs1_addr(spec_insn_c_srli_rs1_addr), .spec_rs2_addr(spec_insn_c_srli_rs2_addr), .spec_rd_addr(spec_insn_c_srli_rd_addr), .spec_rd_wdata(spec_insn_c_srli_rd_wdata), .spec_pc_wdata(spec_insn_c_srli_pc_wdata), .spec_mem_addr(spec_insn_c_srli_mem_addr), .spec_mem_rmask(spec_insn_c_srli_mem_rmask), .spec_mem_wmask(spec_insn_c_srli_mem_wmask), .spec_mem_wdata(spec_insn_c_srli_mem_wdata) ); wire spec_insn_c_sub_valid; wire spec_insn_c_sub_trap; wire [ 4 : 0] spec_insn_c_sub_rs1_addr; wire [ 4 : 0] spec_insn_c_sub_rs2_addr; wire [ 4 : 0] spec_insn_c_sub_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_csr_misa_rmask; `endif rvfi_insn_c_sub insn_c_sub ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_sub_csr_misa_rmask), `endif .spec_valid(spec_insn_c_sub_valid), .spec_trap(spec_insn_c_sub_trap), .spec_rs1_addr(spec_insn_c_sub_rs1_addr), .spec_rs2_addr(spec_insn_c_sub_rs2_addr), .spec_rd_addr(spec_insn_c_sub_rd_addr), .spec_rd_wdata(spec_insn_c_sub_rd_wdata), .spec_pc_wdata(spec_insn_c_sub_pc_wdata), .spec_mem_addr(spec_insn_c_sub_mem_addr), .spec_mem_rmask(spec_insn_c_sub_mem_rmask), .spec_mem_wmask(spec_insn_c_sub_mem_wmask), .spec_mem_wdata(spec_insn_c_sub_mem_wdata) ); wire spec_insn_c_sw_valid; wire spec_insn_c_sw_trap; wire [ 4 : 0] spec_insn_c_sw_rs1_addr; wire [ 4 : 0] spec_insn_c_sw_rs2_addr; wire [ 4 : 0] spec_insn_c_sw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_csr_misa_rmask; `endif rvfi_insn_c_sw insn_c_sw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_sw_csr_misa_rmask), `endif .spec_valid(spec_insn_c_sw_valid), .spec_trap(spec_insn_c_sw_trap), .spec_rs1_addr(spec_insn_c_sw_rs1_addr), .spec_rs2_addr(spec_insn_c_sw_rs2_addr), .spec_rd_addr(spec_insn_c_sw_rd_addr), .spec_rd_wdata(spec_insn_c_sw_rd_wdata), .spec_pc_wdata(spec_insn_c_sw_pc_wdata), .spec_mem_addr(spec_insn_c_sw_mem_addr), .spec_mem_rmask(spec_insn_c_sw_mem_rmask), .spec_mem_wmask(spec_insn_c_sw_mem_wmask), .spec_mem_wdata(spec_insn_c_sw_mem_wdata) ); wire spec_insn_c_swsp_valid; wire spec_insn_c_swsp_trap; wire [ 4 : 0] spec_insn_c_swsp_rs1_addr; wire [ 4 : 0] spec_insn_c_swsp_rs2_addr; wire [ 4 : 0] spec_insn_c_swsp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_csr_misa_rmask; `endif rvfi_insn_c_swsp insn_c_swsp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_swsp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_swsp_valid), .spec_trap(spec_insn_c_swsp_trap), .spec_rs1_addr(spec_insn_c_swsp_rs1_addr), .spec_rs2_addr(spec_insn_c_swsp_rs2_addr), .spec_rd_addr(spec_insn_c_swsp_rd_addr), .spec_rd_wdata(spec_insn_c_swsp_rd_wdata), .spec_pc_wdata(spec_insn_c_swsp_pc_wdata), .spec_mem_addr(spec_insn_c_swsp_mem_addr), .spec_mem_rmask(spec_insn_c_swsp_mem_rmask), .spec_mem_wmask(spec_insn_c_swsp_mem_wmask), .spec_mem_wdata(spec_insn_c_swsp_mem_wdata) ); wire spec_insn_c_xor_valid; wire spec_insn_c_xor_trap; wire [ 4 : 0] spec_insn_c_xor_rs1_addr; wire [ 4 : 0] spec_insn_c_xor_rs2_addr; wire [ 4 : 0] spec_insn_c_xor_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_csr_misa_rmask; `endif rvfi_insn_c_xor insn_c_xor ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_xor_csr_misa_rmask), `endif .spec_valid(spec_insn_c_xor_valid), .spec_trap(spec_insn_c_xor_trap), .spec_rs1_addr(spec_insn_c_xor_rs1_addr), .spec_rs2_addr(spec_insn_c_xor_rs2_addr), .spec_rd_addr(spec_insn_c_xor_rd_addr), .spec_rd_wdata(spec_insn_c_xor_rd_wdata), .spec_pc_wdata(spec_insn_c_xor_pc_wdata), .spec_mem_addr(spec_insn_c_xor_mem_addr), .spec_mem_rmask(spec_insn_c_xor_mem_rmask), .spec_mem_wmask(spec_insn_c_xor_mem_wmask), .spec_mem_wdata(spec_insn_c_xor_mem_wdata) ); wire spec_insn_jal_valid; wire spec_insn_jal_trap; wire [ 4 : 0] spec_insn_jal_rs1_addr; wire [ 4 : 0] spec_insn_jal_rs2_addr; wire [ 4 : 0] spec_insn_jal_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; `endif rvfi_insn_jal insn_jal ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), `endif .spec_valid(spec_insn_jal_valid), .spec_trap(spec_insn_jal_trap), .spec_rs1_addr(spec_insn_jal_rs1_addr), .spec_rs2_addr(spec_insn_jal_rs2_addr), .spec_rd_addr(spec_insn_jal_rd_addr), .spec_rd_wdata(spec_insn_jal_rd_wdata), .spec_pc_wdata(spec_insn_jal_pc_wdata), .spec_mem_addr(spec_insn_jal_mem_addr), .spec_mem_rmask(spec_insn_jal_mem_rmask), .spec_mem_wmask(spec_insn_jal_mem_wmask), .spec_mem_wdata(spec_insn_jal_mem_wdata) ); wire spec_insn_jalr_valid; wire spec_insn_jalr_trap; wire [ 4 : 0] spec_insn_jalr_rs1_addr; wire [ 4 : 0] spec_insn_jalr_rs2_addr; wire [ 4 : 0] spec_insn_jalr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; `endif rvfi_insn_jalr insn_jalr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), `endif .spec_valid(spec_insn_jalr_valid), .spec_trap(spec_insn_jalr_trap), .spec_rs1_addr(spec_insn_jalr_rs1_addr), .spec_rs2_addr(spec_insn_jalr_rs2_addr), .spec_rd_addr(spec_insn_jalr_rd_addr), .spec_rd_wdata(spec_insn_jalr_rd_wdata), .spec_pc_wdata(spec_insn_jalr_pc_wdata), .spec_mem_addr(spec_insn_jalr_mem_addr), .spec_mem_rmask(spec_insn_jalr_mem_rmask), .spec_mem_wmask(spec_insn_jalr_mem_wmask), .spec_mem_wdata(spec_insn_jalr_mem_wdata) ); wire spec_insn_lb_valid; wire spec_insn_lb_trap; wire [ 4 : 0] spec_insn_lb_rs1_addr; wire [ 4 : 0] spec_insn_lb_rs2_addr; wire [ 4 : 0] spec_insn_lb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; `endif rvfi_insn_lb insn_lb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), `endif .spec_valid(spec_insn_lb_valid), .spec_trap(spec_insn_lb_trap), .spec_rs1_addr(spec_insn_lb_rs1_addr), .spec_rs2_addr(spec_insn_lb_rs2_addr), .spec_rd_addr(spec_insn_lb_rd_addr), .spec_rd_wdata(spec_insn_lb_rd_wdata), .spec_pc_wdata(spec_insn_lb_pc_wdata), .spec_mem_addr(spec_insn_lb_mem_addr), .spec_mem_rmask(spec_insn_lb_mem_rmask), .spec_mem_wmask(spec_insn_lb_mem_wmask), .spec_mem_wdata(spec_insn_lb_mem_wdata) ); wire spec_insn_lbu_valid; wire spec_insn_lbu_trap; wire [ 4 : 0] spec_insn_lbu_rs1_addr; wire [ 4 : 0] spec_insn_lbu_rs2_addr; wire [ 4 : 0] spec_insn_lbu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; `endif rvfi_insn_lbu insn_lbu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), `endif .spec_valid(spec_insn_lbu_valid), .spec_trap(spec_insn_lbu_trap), .spec_rs1_addr(spec_insn_lbu_rs1_addr), .spec_rs2_addr(spec_insn_lbu_rs2_addr), .spec_rd_addr(spec_insn_lbu_rd_addr), .spec_rd_wdata(spec_insn_lbu_rd_wdata), .spec_pc_wdata(spec_insn_lbu_pc_wdata), .spec_mem_addr(spec_insn_lbu_mem_addr), .spec_mem_rmask(spec_insn_lbu_mem_rmask), .spec_mem_wmask(spec_insn_lbu_mem_wmask), .spec_mem_wdata(spec_insn_lbu_mem_wdata) ); wire spec_insn_lh_valid; wire spec_insn_lh_trap; wire [ 4 : 0] spec_insn_lh_rs1_addr; wire [ 4 : 0] spec_insn_lh_rs2_addr; wire [ 4 : 0] spec_insn_lh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; `endif rvfi_insn_lh insn_lh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), `endif .spec_valid(spec_insn_lh_valid), .spec_trap(spec_insn_lh_trap), .spec_rs1_addr(spec_insn_lh_rs1_addr), .spec_rs2_addr(spec_insn_lh_rs2_addr), .spec_rd_addr(spec_insn_lh_rd_addr), .spec_rd_wdata(spec_insn_lh_rd_wdata), .spec_pc_wdata(spec_insn_lh_pc_wdata), .spec_mem_addr(spec_insn_lh_mem_addr), .spec_mem_rmask(spec_insn_lh_mem_rmask), .spec_mem_wmask(spec_insn_lh_mem_wmask), .spec_mem_wdata(spec_insn_lh_mem_wdata) ); wire spec_insn_lhu_valid; wire spec_insn_lhu_trap; wire [ 4 : 0] spec_insn_lhu_rs1_addr; wire [ 4 : 0] spec_insn_lhu_rs2_addr; wire [ 4 : 0] spec_insn_lhu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; `endif rvfi_insn_lhu insn_lhu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), `endif .spec_valid(spec_insn_lhu_valid), .spec_trap(spec_insn_lhu_trap), .spec_rs1_addr(spec_insn_lhu_rs1_addr), .spec_rs2_addr(spec_insn_lhu_rs2_addr), .spec_rd_addr(spec_insn_lhu_rd_addr), .spec_rd_wdata(spec_insn_lhu_rd_wdata), .spec_pc_wdata(spec_insn_lhu_pc_wdata), .spec_mem_addr(spec_insn_lhu_mem_addr), .spec_mem_rmask(spec_insn_lhu_mem_rmask), .spec_mem_wmask(spec_insn_lhu_mem_wmask), .spec_mem_wdata(spec_insn_lhu_mem_wdata) ); wire spec_insn_lui_valid; wire spec_insn_lui_trap; wire [ 4 : 0] spec_insn_lui_rs1_addr; wire [ 4 : 0] spec_insn_lui_rs2_addr; wire [ 4 : 0] spec_insn_lui_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; `endif rvfi_insn_lui insn_lui ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), `endif .spec_valid(spec_insn_lui_valid), .spec_trap(spec_insn_lui_trap), .spec_rs1_addr(spec_insn_lui_rs1_addr), .spec_rs2_addr(spec_insn_lui_rs2_addr), .spec_rd_addr(spec_insn_lui_rd_addr), .spec_rd_wdata(spec_insn_lui_rd_wdata), .spec_pc_wdata(spec_insn_lui_pc_wdata), .spec_mem_addr(spec_insn_lui_mem_addr), .spec_mem_rmask(spec_insn_lui_mem_rmask), .spec_mem_wmask(spec_insn_lui_mem_wmask), .spec_mem_wdata(spec_insn_lui_mem_wdata) ); wire spec_insn_lw_valid; wire spec_insn_lw_trap; wire [ 4 : 0] spec_insn_lw_rs1_addr; wire [ 4 : 0] spec_insn_lw_rs2_addr; wire [ 4 : 0] spec_insn_lw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; `endif rvfi_insn_lw insn_lw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), `endif .spec_valid(spec_insn_lw_valid), .spec_trap(spec_insn_lw_trap), .spec_rs1_addr(spec_insn_lw_rs1_addr), .spec_rs2_addr(spec_insn_lw_rs2_addr), .spec_rd_addr(spec_insn_lw_rd_addr), .spec_rd_wdata(spec_insn_lw_rd_wdata), .spec_pc_wdata(spec_insn_lw_pc_wdata), .spec_mem_addr(spec_insn_lw_mem_addr), .spec_mem_rmask(spec_insn_lw_mem_rmask), .spec_mem_wmask(spec_insn_lw_mem_wmask), .spec_mem_wdata(spec_insn_lw_mem_wdata) ); wire spec_insn_or_valid; wire spec_insn_or_trap; wire [ 4 : 0] spec_insn_or_rs1_addr; wire [ 4 : 0] spec_insn_or_rs2_addr; wire [ 4 : 0] spec_insn_or_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; `endif rvfi_insn_or insn_or ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), `endif .spec_valid(spec_insn_or_valid), .spec_trap(spec_insn_or_trap), .spec_rs1_addr(spec_insn_or_rs1_addr), .spec_rs2_addr(spec_insn_or_rs2_addr), .spec_rd_addr(spec_insn_or_rd_addr), .spec_rd_wdata(spec_insn_or_rd_wdata), .spec_pc_wdata(spec_insn_or_pc_wdata), .spec_mem_addr(spec_insn_or_mem_addr), .spec_mem_rmask(spec_insn_or_mem_rmask), .spec_mem_wmask(spec_insn_or_mem_wmask), .spec_mem_wdata(spec_insn_or_mem_wdata) ); wire spec_insn_ori_valid; wire spec_insn_ori_trap; wire [ 4 : 0] spec_insn_ori_rs1_addr; wire [ 4 : 0] spec_insn_ori_rs2_addr; wire [ 4 : 0] spec_insn_ori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; `endif rvfi_insn_ori insn_ori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), `endif .spec_valid(spec_insn_ori_valid), .spec_trap(spec_insn_ori_trap), .spec_rs1_addr(spec_insn_ori_rs1_addr), .spec_rs2_addr(spec_insn_ori_rs2_addr), .spec_rd_addr(spec_insn_ori_rd_addr), .spec_rd_wdata(spec_insn_ori_rd_wdata), .spec_pc_wdata(spec_insn_ori_pc_wdata), .spec_mem_addr(spec_insn_ori_mem_addr), .spec_mem_rmask(spec_insn_ori_mem_rmask), .spec_mem_wmask(spec_insn_ori_mem_wmask), .spec_mem_wdata(spec_insn_ori_mem_wdata) ); wire spec_insn_sb_valid; wire spec_insn_sb_trap; wire [ 4 : 0] spec_insn_sb_rs1_addr; wire [ 4 : 0] spec_insn_sb_rs2_addr; wire [ 4 : 0] spec_insn_sb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; `endif rvfi_insn_sb insn_sb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), `endif .spec_valid(spec_insn_sb_valid), .spec_trap(spec_insn_sb_trap), .spec_rs1_addr(spec_insn_sb_rs1_addr), .spec_rs2_addr(spec_insn_sb_rs2_addr), .spec_rd_addr(spec_insn_sb_rd_addr), .spec_rd_wdata(spec_insn_sb_rd_wdata), .spec_pc_wdata(spec_insn_sb_pc_wdata), .spec_mem_addr(spec_insn_sb_mem_addr), .spec_mem_rmask(spec_insn_sb_mem_rmask), .spec_mem_wmask(spec_insn_sb_mem_wmask), .spec_mem_wdata(spec_insn_sb_mem_wdata) ); wire spec_insn_sh_valid; wire spec_insn_sh_trap; wire [ 4 : 0] spec_insn_sh_rs1_addr; wire [ 4 : 0] spec_insn_sh_rs2_addr; wire [ 4 : 0] spec_insn_sh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; `endif rvfi_insn_sh insn_sh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), `endif .spec_valid(spec_insn_sh_valid), .spec_trap(spec_insn_sh_trap), .spec_rs1_addr(spec_insn_sh_rs1_addr), .spec_rs2_addr(spec_insn_sh_rs2_addr), .spec_rd_addr(spec_insn_sh_rd_addr), .spec_rd_wdata(spec_insn_sh_rd_wdata), .spec_pc_wdata(spec_insn_sh_pc_wdata), .spec_mem_addr(spec_insn_sh_mem_addr), .spec_mem_rmask(spec_insn_sh_mem_rmask), .spec_mem_wmask(spec_insn_sh_mem_wmask), .spec_mem_wdata(spec_insn_sh_mem_wdata) ); wire spec_insn_sll_valid; wire spec_insn_sll_trap; wire [ 4 : 0] spec_insn_sll_rs1_addr; wire [ 4 : 0] spec_insn_sll_rs2_addr; wire [ 4 : 0] spec_insn_sll_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; `endif rvfi_insn_sll insn_sll ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), `endif .spec_valid(spec_insn_sll_valid), .spec_trap(spec_insn_sll_trap), .spec_rs1_addr(spec_insn_sll_rs1_addr), .spec_rs2_addr(spec_insn_sll_rs2_addr), .spec_rd_addr(spec_insn_sll_rd_addr), .spec_rd_wdata(spec_insn_sll_rd_wdata), .spec_pc_wdata(spec_insn_sll_pc_wdata), .spec_mem_addr(spec_insn_sll_mem_addr), .spec_mem_rmask(spec_insn_sll_mem_rmask), .spec_mem_wmask(spec_insn_sll_mem_wmask), .spec_mem_wdata(spec_insn_sll_mem_wdata) ); wire spec_insn_slli_valid; wire spec_insn_slli_trap; wire [ 4 : 0] spec_insn_slli_rs1_addr; wire [ 4 : 0] spec_insn_slli_rs2_addr; wire [ 4 : 0] spec_insn_slli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; `endif rvfi_insn_slli insn_slli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), `endif .spec_valid(spec_insn_slli_valid), .spec_trap(spec_insn_slli_trap), .spec_rs1_addr(spec_insn_slli_rs1_addr), .spec_rs2_addr(spec_insn_slli_rs2_addr), .spec_rd_addr(spec_insn_slli_rd_addr), .spec_rd_wdata(spec_insn_slli_rd_wdata), .spec_pc_wdata(spec_insn_slli_pc_wdata), .spec_mem_addr(spec_insn_slli_mem_addr), .spec_mem_rmask(spec_insn_slli_mem_rmask), .spec_mem_wmask(spec_insn_slli_mem_wmask), .spec_mem_wdata(spec_insn_slli_mem_wdata) ); wire spec_insn_slt_valid; wire spec_insn_slt_trap; wire [ 4 : 0] spec_insn_slt_rs1_addr; wire [ 4 : 0] spec_insn_slt_rs2_addr; wire [ 4 : 0] spec_insn_slt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; `endif rvfi_insn_slt insn_slt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), `endif .spec_valid(spec_insn_slt_valid), .spec_trap(spec_insn_slt_trap), .spec_rs1_addr(spec_insn_slt_rs1_addr), .spec_rs2_addr(spec_insn_slt_rs2_addr), .spec_rd_addr(spec_insn_slt_rd_addr), .spec_rd_wdata(spec_insn_slt_rd_wdata), .spec_pc_wdata(spec_insn_slt_pc_wdata), .spec_mem_addr(spec_insn_slt_mem_addr), .spec_mem_rmask(spec_insn_slt_mem_rmask), .spec_mem_wmask(spec_insn_slt_mem_wmask), .spec_mem_wdata(spec_insn_slt_mem_wdata) ); wire spec_insn_slti_valid; wire spec_insn_slti_trap; wire [ 4 : 0] spec_insn_slti_rs1_addr; wire [ 4 : 0] spec_insn_slti_rs2_addr; wire [ 4 : 0] spec_insn_slti_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; `endif rvfi_insn_slti insn_slti ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), `endif .spec_valid(spec_insn_slti_valid), .spec_trap(spec_insn_slti_trap), .spec_rs1_addr(spec_insn_slti_rs1_addr), .spec_rs2_addr(spec_insn_slti_rs2_addr), .spec_rd_addr(spec_insn_slti_rd_addr), .spec_rd_wdata(spec_insn_slti_rd_wdata), .spec_pc_wdata(spec_insn_slti_pc_wdata), .spec_mem_addr(spec_insn_slti_mem_addr), .spec_mem_rmask(spec_insn_slti_mem_rmask), .spec_mem_wmask(spec_insn_slti_mem_wmask), .spec_mem_wdata(spec_insn_slti_mem_wdata) ); wire spec_insn_sltiu_valid; wire spec_insn_sltiu_trap; wire [ 4 : 0] spec_insn_sltiu_rs1_addr; wire [ 4 : 0] spec_insn_sltiu_rs2_addr; wire [ 4 : 0] spec_insn_sltiu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; `endif rvfi_insn_sltiu insn_sltiu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltiu_valid), .spec_trap(spec_insn_sltiu_trap), .spec_rs1_addr(spec_insn_sltiu_rs1_addr), .spec_rs2_addr(spec_insn_sltiu_rs2_addr), .spec_rd_addr(spec_insn_sltiu_rd_addr), .spec_rd_wdata(spec_insn_sltiu_rd_wdata), .spec_pc_wdata(spec_insn_sltiu_pc_wdata), .spec_mem_addr(spec_insn_sltiu_mem_addr), .spec_mem_rmask(spec_insn_sltiu_mem_rmask), .spec_mem_wmask(spec_insn_sltiu_mem_wmask), .spec_mem_wdata(spec_insn_sltiu_mem_wdata) ); wire spec_insn_sltu_valid; wire spec_insn_sltu_trap; wire [ 4 : 0] spec_insn_sltu_rs1_addr; wire [ 4 : 0] spec_insn_sltu_rs2_addr; wire [ 4 : 0] spec_insn_sltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; `endif rvfi_insn_sltu insn_sltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltu_valid), .spec_trap(spec_insn_sltu_trap), .spec_rs1_addr(spec_insn_sltu_rs1_addr), .spec_rs2_addr(spec_insn_sltu_rs2_addr), .spec_rd_addr(spec_insn_sltu_rd_addr), .spec_rd_wdata(spec_insn_sltu_rd_wdata), .spec_pc_wdata(spec_insn_sltu_pc_wdata), .spec_mem_addr(spec_insn_sltu_mem_addr), .spec_mem_rmask(spec_insn_sltu_mem_rmask), .spec_mem_wmask(spec_insn_sltu_mem_wmask), .spec_mem_wdata(spec_insn_sltu_mem_wdata) ); wire spec_insn_sra_valid; wire spec_insn_sra_trap; wire [ 4 : 0] spec_insn_sra_rs1_addr; wire [ 4 : 0] spec_insn_sra_rs2_addr; wire [ 4 : 0] spec_insn_sra_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; `endif rvfi_insn_sra insn_sra ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), `endif .spec_valid(spec_insn_sra_valid), .spec_trap(spec_insn_sra_trap), .spec_rs1_addr(spec_insn_sra_rs1_addr), .spec_rs2_addr(spec_insn_sra_rs2_addr), .spec_rd_addr(spec_insn_sra_rd_addr), .spec_rd_wdata(spec_insn_sra_rd_wdata), .spec_pc_wdata(spec_insn_sra_pc_wdata), .spec_mem_addr(spec_insn_sra_mem_addr), .spec_mem_rmask(spec_insn_sra_mem_rmask), .spec_mem_wmask(spec_insn_sra_mem_wmask), .spec_mem_wdata(spec_insn_sra_mem_wdata) ); wire spec_insn_srai_valid; wire spec_insn_srai_trap; wire [ 4 : 0] spec_insn_srai_rs1_addr; wire [ 4 : 0] spec_insn_srai_rs2_addr; wire [ 4 : 0] spec_insn_srai_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; `endif rvfi_insn_srai insn_srai ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), `endif .spec_valid(spec_insn_srai_valid), .spec_trap(spec_insn_srai_trap), .spec_rs1_addr(spec_insn_srai_rs1_addr), .spec_rs2_addr(spec_insn_srai_rs2_addr), .spec_rd_addr(spec_insn_srai_rd_addr), .spec_rd_wdata(spec_insn_srai_rd_wdata), .spec_pc_wdata(spec_insn_srai_pc_wdata), .spec_mem_addr(spec_insn_srai_mem_addr), .spec_mem_rmask(spec_insn_srai_mem_rmask), .spec_mem_wmask(spec_insn_srai_mem_wmask), .spec_mem_wdata(spec_insn_srai_mem_wdata) ); wire spec_insn_srl_valid; wire spec_insn_srl_trap; wire [ 4 : 0] spec_insn_srl_rs1_addr; wire [ 4 : 0] spec_insn_srl_rs2_addr; wire [ 4 : 0] spec_insn_srl_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; `endif rvfi_insn_srl insn_srl ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), `endif .spec_valid(spec_insn_srl_valid), .spec_trap(spec_insn_srl_trap), .spec_rs1_addr(spec_insn_srl_rs1_addr), .spec_rs2_addr(spec_insn_srl_rs2_addr), .spec_rd_addr(spec_insn_srl_rd_addr), .spec_rd_wdata(spec_insn_srl_rd_wdata), .spec_pc_wdata(spec_insn_srl_pc_wdata), .spec_mem_addr(spec_insn_srl_mem_addr), .spec_mem_rmask(spec_insn_srl_mem_rmask), .spec_mem_wmask(spec_insn_srl_mem_wmask), .spec_mem_wdata(spec_insn_srl_mem_wdata) ); wire spec_insn_srli_valid; wire spec_insn_srli_trap; wire [ 4 : 0] spec_insn_srli_rs1_addr; wire [ 4 : 0] spec_insn_srli_rs2_addr; wire [ 4 : 0] spec_insn_srli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; `endif rvfi_insn_srli insn_srli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), `endif .spec_valid(spec_insn_srli_valid), .spec_trap(spec_insn_srli_trap), .spec_rs1_addr(spec_insn_srli_rs1_addr), .spec_rs2_addr(spec_insn_srli_rs2_addr), .spec_rd_addr(spec_insn_srli_rd_addr), .spec_rd_wdata(spec_insn_srli_rd_wdata), .spec_pc_wdata(spec_insn_srli_pc_wdata), .spec_mem_addr(spec_insn_srli_mem_addr), .spec_mem_rmask(spec_insn_srli_mem_rmask), .spec_mem_wmask(spec_insn_srli_mem_wmask), .spec_mem_wdata(spec_insn_srli_mem_wdata) ); wire spec_insn_sub_valid; wire spec_insn_sub_trap; wire [ 4 : 0] spec_insn_sub_rs1_addr; wire [ 4 : 0] spec_insn_sub_rs2_addr; wire [ 4 : 0] spec_insn_sub_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; `endif rvfi_insn_sub insn_sub ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), `endif .spec_valid(spec_insn_sub_valid), .spec_trap(spec_insn_sub_trap), .spec_rs1_addr(spec_insn_sub_rs1_addr), .spec_rs2_addr(spec_insn_sub_rs2_addr), .spec_rd_addr(spec_insn_sub_rd_addr), .spec_rd_wdata(spec_insn_sub_rd_wdata), .spec_pc_wdata(spec_insn_sub_pc_wdata), .spec_mem_addr(spec_insn_sub_mem_addr), .spec_mem_rmask(spec_insn_sub_mem_rmask), .spec_mem_wmask(spec_insn_sub_mem_wmask), .spec_mem_wdata(spec_insn_sub_mem_wdata) ); wire spec_insn_sw_valid; wire spec_insn_sw_trap; wire [ 4 : 0] spec_insn_sw_rs1_addr; wire [ 4 : 0] spec_insn_sw_rs2_addr; wire [ 4 : 0] spec_insn_sw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; `endif rvfi_insn_sw insn_sw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), `endif .spec_valid(spec_insn_sw_valid), .spec_trap(spec_insn_sw_trap), .spec_rs1_addr(spec_insn_sw_rs1_addr), .spec_rs2_addr(spec_insn_sw_rs2_addr), .spec_rd_addr(spec_insn_sw_rd_addr), .spec_rd_wdata(spec_insn_sw_rd_wdata), .spec_pc_wdata(spec_insn_sw_pc_wdata), .spec_mem_addr(spec_insn_sw_mem_addr), .spec_mem_rmask(spec_insn_sw_mem_rmask), .spec_mem_wmask(spec_insn_sw_mem_wmask), .spec_mem_wdata(spec_insn_sw_mem_wdata) ); wire spec_insn_xor_valid; wire spec_insn_xor_trap; wire [ 4 : 0] spec_insn_xor_rs1_addr; wire [ 4 : 0] spec_insn_xor_rs2_addr; wire [ 4 : 0] spec_insn_xor_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; `endif rvfi_insn_xor insn_xor ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), `endif .spec_valid(spec_insn_xor_valid), .spec_trap(spec_insn_xor_trap), .spec_rs1_addr(spec_insn_xor_rs1_addr), .spec_rs2_addr(spec_insn_xor_rs2_addr), .spec_rd_addr(spec_insn_xor_rd_addr), .spec_rd_wdata(spec_insn_xor_rd_wdata), .spec_pc_wdata(spec_insn_xor_pc_wdata), .spec_mem_addr(spec_insn_xor_mem_addr), .spec_mem_rmask(spec_insn_xor_mem_rmask), .spec_mem_wmask(spec_insn_xor_mem_wmask), .spec_mem_wdata(spec_insn_xor_mem_wdata) ); wire spec_insn_xori_valid; wire spec_insn_xori_trap; wire [ 4 : 0] spec_insn_xori_rs1_addr; wire [ 4 : 0] spec_insn_xori_rs2_addr; wire [ 4 : 0] spec_insn_xori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; `endif rvfi_insn_xori insn_xori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), `endif .spec_valid(spec_insn_xori_valid), .spec_trap(spec_insn_xori_trap), .spec_rs1_addr(spec_insn_xori_rs1_addr), .spec_rs2_addr(spec_insn_xori_rs2_addr), .spec_rd_addr(spec_insn_xori_rd_addr), .spec_rd_wdata(spec_insn_xori_rd_wdata), .spec_pc_wdata(spec_insn_xori_pc_wdata), .spec_mem_addr(spec_insn_xori_mem_addr), .spec_mem_rmask(spec_insn_xori_mem_rmask), .spec_mem_wmask(spec_insn_xori_mem_wmask), .spec_mem_wdata(spec_insn_xori_mem_wdata) ); assign spec_valid = spec_insn_add_valid ? spec_insn_add_valid : spec_insn_addi_valid ? spec_insn_addi_valid : spec_insn_and_valid ? spec_insn_and_valid : spec_insn_andi_valid ? spec_insn_andi_valid : spec_insn_auipc_valid ? spec_insn_auipc_valid : spec_insn_beq_valid ? spec_insn_beq_valid : spec_insn_bge_valid ? spec_insn_bge_valid : spec_insn_bgeu_valid ? spec_insn_bgeu_valid : spec_insn_blt_valid ? spec_insn_blt_valid : spec_insn_bltu_valid ? spec_insn_bltu_valid : spec_insn_bne_valid ? spec_insn_bne_valid : spec_insn_c_add_valid ? spec_insn_c_add_valid : spec_insn_c_addi_valid ? spec_insn_c_addi_valid : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_valid : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_valid : spec_insn_c_and_valid ? spec_insn_c_and_valid : spec_insn_c_andi_valid ? spec_insn_c_andi_valid : spec_insn_c_beqz_valid ? spec_insn_c_beqz_valid : spec_insn_c_bnez_valid ? spec_insn_c_bnez_valid : spec_insn_c_j_valid ? spec_insn_c_j_valid : spec_insn_c_jal_valid ? spec_insn_c_jal_valid : spec_insn_c_jalr_valid ? spec_insn_c_jalr_valid : spec_insn_c_jr_valid ? spec_insn_c_jr_valid : spec_insn_c_li_valid ? spec_insn_c_li_valid : spec_insn_c_lui_valid ? spec_insn_c_lui_valid : spec_insn_c_lw_valid ? spec_insn_c_lw_valid : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_valid : spec_insn_c_mv_valid ? spec_insn_c_mv_valid : spec_insn_c_or_valid ? spec_insn_c_or_valid : spec_insn_c_slli_valid ? spec_insn_c_slli_valid : spec_insn_c_srai_valid ? spec_insn_c_srai_valid : spec_insn_c_srli_valid ? spec_insn_c_srli_valid : spec_insn_c_sub_valid ? spec_insn_c_sub_valid : spec_insn_c_sw_valid ? spec_insn_c_sw_valid : spec_insn_c_swsp_valid ? spec_insn_c_swsp_valid : spec_insn_c_xor_valid ? spec_insn_c_xor_valid : spec_insn_jal_valid ? spec_insn_jal_valid : spec_insn_jalr_valid ? spec_insn_jalr_valid : spec_insn_lb_valid ? spec_insn_lb_valid : spec_insn_lbu_valid ? spec_insn_lbu_valid : spec_insn_lh_valid ? spec_insn_lh_valid : spec_insn_lhu_valid ? spec_insn_lhu_valid : spec_insn_lui_valid ? spec_insn_lui_valid : spec_insn_lw_valid ? spec_insn_lw_valid : spec_insn_or_valid ? spec_insn_or_valid : spec_insn_ori_valid ? spec_insn_ori_valid : spec_insn_sb_valid ? spec_insn_sb_valid : spec_insn_sh_valid ? spec_insn_sh_valid : spec_insn_sll_valid ? spec_insn_sll_valid : spec_insn_slli_valid ? spec_insn_slli_valid : spec_insn_slt_valid ? spec_insn_slt_valid : spec_insn_slti_valid ? spec_insn_slti_valid : spec_insn_sltiu_valid ? spec_insn_sltiu_valid : spec_insn_sltu_valid ? spec_insn_sltu_valid : spec_insn_sra_valid ? spec_insn_sra_valid : spec_insn_srai_valid ? spec_insn_srai_valid : spec_insn_srl_valid ? spec_insn_srl_valid : spec_insn_srli_valid ? spec_insn_srli_valid : spec_insn_sub_valid ? spec_insn_sub_valid : spec_insn_sw_valid ? spec_insn_sw_valid : spec_insn_xor_valid ? spec_insn_xor_valid : spec_insn_xori_valid ? spec_insn_xori_valid : 0; assign spec_trap = spec_insn_add_valid ? spec_insn_add_trap : spec_insn_addi_valid ? spec_insn_addi_trap : spec_insn_and_valid ? spec_insn_and_trap : spec_insn_andi_valid ? spec_insn_andi_trap : spec_insn_auipc_valid ? spec_insn_auipc_trap : spec_insn_beq_valid ? spec_insn_beq_trap : spec_insn_bge_valid ? spec_insn_bge_trap : spec_insn_bgeu_valid ? spec_insn_bgeu_trap : spec_insn_blt_valid ? spec_insn_blt_trap : spec_insn_bltu_valid ? spec_insn_bltu_trap : spec_insn_bne_valid ? spec_insn_bne_trap : spec_insn_c_add_valid ? spec_insn_c_add_trap : spec_insn_c_addi_valid ? spec_insn_c_addi_trap : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_trap : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_trap : spec_insn_c_and_valid ? spec_insn_c_and_trap : spec_insn_c_andi_valid ? spec_insn_c_andi_trap : spec_insn_c_beqz_valid ? spec_insn_c_beqz_trap : spec_insn_c_bnez_valid ? spec_insn_c_bnez_trap : spec_insn_c_j_valid ? spec_insn_c_j_trap : spec_insn_c_jal_valid ? spec_insn_c_jal_trap : spec_insn_c_jalr_valid ? spec_insn_c_jalr_trap : spec_insn_c_jr_valid ? spec_insn_c_jr_trap : spec_insn_c_li_valid ? spec_insn_c_li_trap : spec_insn_c_lui_valid ? spec_insn_c_lui_trap : spec_insn_c_lw_valid ? spec_insn_c_lw_trap : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_trap : spec_insn_c_mv_valid ? spec_insn_c_mv_trap : spec_insn_c_or_valid ? spec_insn_c_or_trap : spec_insn_c_slli_valid ? spec_insn_c_slli_trap : spec_insn_c_srai_valid ? spec_insn_c_srai_trap : spec_insn_c_srli_valid ? spec_insn_c_srli_trap : spec_insn_c_sub_valid ? spec_insn_c_sub_trap : spec_insn_c_sw_valid ? spec_insn_c_sw_trap : spec_insn_c_swsp_valid ? spec_insn_c_swsp_trap : spec_insn_c_xor_valid ? spec_insn_c_xor_trap : spec_insn_jal_valid ? spec_insn_jal_trap : spec_insn_jalr_valid ? spec_insn_jalr_trap : spec_insn_lb_valid ? spec_insn_lb_trap : spec_insn_lbu_valid ? spec_insn_lbu_trap : spec_insn_lh_valid ? spec_insn_lh_trap : spec_insn_lhu_valid ? spec_insn_lhu_trap : spec_insn_lui_valid ? spec_insn_lui_trap : spec_insn_lw_valid ? spec_insn_lw_trap : spec_insn_or_valid ? spec_insn_or_trap : spec_insn_ori_valid ? spec_insn_ori_trap : spec_insn_sb_valid ? spec_insn_sb_trap : spec_insn_sh_valid ? spec_insn_sh_trap : spec_insn_sll_valid ? spec_insn_sll_trap : spec_insn_slli_valid ? spec_insn_slli_trap : spec_insn_slt_valid ? spec_insn_slt_trap : spec_insn_slti_valid ? spec_insn_slti_trap : spec_insn_sltiu_valid ? spec_insn_sltiu_trap : spec_insn_sltu_valid ? spec_insn_sltu_trap : spec_insn_sra_valid ? spec_insn_sra_trap : spec_insn_srai_valid ? spec_insn_srai_trap : spec_insn_srl_valid ? spec_insn_srl_trap : spec_insn_srli_valid ? spec_insn_srli_trap : spec_insn_sub_valid ? spec_insn_sub_trap : spec_insn_sw_valid ? spec_insn_sw_trap : spec_insn_xor_valid ? spec_insn_xor_trap : spec_insn_xori_valid ? spec_insn_xori_trap : 0; assign spec_rs1_addr = spec_insn_add_valid ? spec_insn_add_rs1_addr : spec_insn_addi_valid ? spec_insn_addi_rs1_addr : spec_insn_and_valid ? spec_insn_and_rs1_addr : spec_insn_andi_valid ? spec_insn_andi_rs1_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : spec_insn_beq_valid ? spec_insn_beq_rs1_addr : spec_insn_bge_valid ? spec_insn_bge_rs1_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : spec_insn_blt_valid ? spec_insn_blt_rs1_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : spec_insn_bne_valid ? spec_insn_bne_rs1_addr : spec_insn_c_add_valid ? spec_insn_c_add_rs1_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_rs1_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs1_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs1_addr : spec_insn_c_and_valid ? spec_insn_c_and_rs1_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_rs1_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rs1_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rs1_addr : spec_insn_c_j_valid ? spec_insn_c_j_rs1_addr : spec_insn_c_jal_valid ? spec_insn_c_jal_rs1_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rs1_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_rs1_addr : spec_insn_c_li_valid ? spec_insn_c_li_rs1_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_rs1_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_rs1_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs1_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_rs1_addr : spec_insn_c_or_valid ? spec_insn_c_or_rs1_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_rs1_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_rs1_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_rs1_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_rs1_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_rs1_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rs1_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_rs1_addr : spec_insn_jal_valid ? spec_insn_jal_rs1_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : spec_insn_lb_valid ? spec_insn_lb_rs1_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : spec_insn_lh_valid ? spec_insn_lh_rs1_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : spec_insn_lui_valid ? spec_insn_lui_rs1_addr : spec_insn_lw_valid ? spec_insn_lw_rs1_addr : spec_insn_or_valid ? spec_insn_or_rs1_addr : spec_insn_ori_valid ? spec_insn_ori_rs1_addr : spec_insn_sb_valid ? spec_insn_sb_rs1_addr : spec_insn_sh_valid ? spec_insn_sh_rs1_addr : spec_insn_sll_valid ? spec_insn_sll_rs1_addr : spec_insn_slli_valid ? spec_insn_slli_rs1_addr : spec_insn_slt_valid ? spec_insn_slt_rs1_addr : spec_insn_slti_valid ? spec_insn_slti_rs1_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : spec_insn_sra_valid ? spec_insn_sra_rs1_addr : spec_insn_srai_valid ? spec_insn_srai_rs1_addr : spec_insn_srl_valid ? spec_insn_srl_rs1_addr : spec_insn_srli_valid ? spec_insn_srli_rs1_addr : spec_insn_sub_valid ? spec_insn_sub_rs1_addr : spec_insn_sw_valid ? spec_insn_sw_rs1_addr : spec_insn_xor_valid ? spec_insn_xor_rs1_addr : spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; assign spec_rs2_addr = spec_insn_add_valid ? spec_insn_add_rs2_addr : spec_insn_addi_valid ? spec_insn_addi_rs2_addr : spec_insn_and_valid ? spec_insn_and_rs2_addr : spec_insn_andi_valid ? spec_insn_andi_rs2_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : spec_insn_beq_valid ? spec_insn_beq_rs2_addr : spec_insn_bge_valid ? spec_insn_bge_rs2_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : spec_insn_blt_valid ? spec_insn_blt_rs2_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : spec_insn_bne_valid ? spec_insn_bne_rs2_addr : spec_insn_c_add_valid ? spec_insn_c_add_rs2_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_rs2_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs2_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs2_addr : spec_insn_c_and_valid ? spec_insn_c_and_rs2_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_rs2_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rs2_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rs2_addr : spec_insn_c_j_valid ? spec_insn_c_j_rs2_addr : spec_insn_c_jal_valid ? spec_insn_c_jal_rs2_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rs2_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_rs2_addr : spec_insn_c_li_valid ? spec_insn_c_li_rs2_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_rs2_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_rs2_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs2_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_rs2_addr : spec_insn_c_or_valid ? spec_insn_c_or_rs2_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_rs2_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_rs2_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_rs2_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_rs2_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_rs2_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rs2_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_rs2_addr : spec_insn_jal_valid ? spec_insn_jal_rs2_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : spec_insn_lb_valid ? spec_insn_lb_rs2_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : spec_insn_lh_valid ? spec_insn_lh_rs2_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : spec_insn_lui_valid ? spec_insn_lui_rs2_addr : spec_insn_lw_valid ? spec_insn_lw_rs2_addr : spec_insn_or_valid ? spec_insn_or_rs2_addr : spec_insn_ori_valid ? spec_insn_ori_rs2_addr : spec_insn_sb_valid ? spec_insn_sb_rs2_addr : spec_insn_sh_valid ? spec_insn_sh_rs2_addr : spec_insn_sll_valid ? spec_insn_sll_rs2_addr : spec_insn_slli_valid ? spec_insn_slli_rs2_addr : spec_insn_slt_valid ? spec_insn_slt_rs2_addr : spec_insn_slti_valid ? spec_insn_slti_rs2_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : spec_insn_sra_valid ? spec_insn_sra_rs2_addr : spec_insn_srai_valid ? spec_insn_srai_rs2_addr : spec_insn_srl_valid ? spec_insn_srl_rs2_addr : spec_insn_srli_valid ? spec_insn_srli_rs2_addr : spec_insn_sub_valid ? spec_insn_sub_rs2_addr : spec_insn_sw_valid ? spec_insn_sw_rs2_addr : spec_insn_xor_valid ? spec_insn_xor_rs2_addr : spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; assign spec_rd_addr = spec_insn_add_valid ? spec_insn_add_rd_addr : spec_insn_addi_valid ? spec_insn_addi_rd_addr : spec_insn_and_valid ? spec_insn_and_rd_addr : spec_insn_andi_valid ? spec_insn_andi_rd_addr : spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : spec_insn_beq_valid ? spec_insn_beq_rd_addr : spec_insn_bge_valid ? spec_insn_bge_rd_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : spec_insn_blt_valid ? spec_insn_blt_rd_addr : spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : spec_insn_bne_valid ? spec_insn_bne_rd_addr : spec_insn_c_add_valid ? spec_insn_c_add_rd_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_rd_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_addr : spec_insn_c_and_valid ? spec_insn_c_and_rd_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_rd_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_addr : spec_insn_c_j_valid ? spec_insn_c_j_rd_addr : spec_insn_c_jal_valid ? spec_insn_c_jal_rd_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_rd_addr : spec_insn_c_li_valid ? spec_insn_c_li_rd_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_rd_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_rd_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_rd_addr : spec_insn_c_or_valid ? spec_insn_c_or_rd_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_rd_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_rd_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_rd_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_rd_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_rd_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_rd_addr : spec_insn_jal_valid ? spec_insn_jal_rd_addr : spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : spec_insn_lb_valid ? spec_insn_lb_rd_addr : spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : spec_insn_lh_valid ? spec_insn_lh_rd_addr : spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : spec_insn_lui_valid ? spec_insn_lui_rd_addr : spec_insn_lw_valid ? spec_insn_lw_rd_addr : spec_insn_or_valid ? spec_insn_or_rd_addr : spec_insn_ori_valid ? spec_insn_ori_rd_addr : spec_insn_sb_valid ? spec_insn_sb_rd_addr : spec_insn_sh_valid ? spec_insn_sh_rd_addr : spec_insn_sll_valid ? spec_insn_sll_rd_addr : spec_insn_slli_valid ? spec_insn_slli_rd_addr : spec_insn_slt_valid ? spec_insn_slt_rd_addr : spec_insn_slti_valid ? spec_insn_slti_rd_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : spec_insn_sra_valid ? spec_insn_sra_rd_addr : spec_insn_srai_valid ? spec_insn_srai_rd_addr : spec_insn_srl_valid ? spec_insn_srl_rd_addr : spec_insn_srli_valid ? spec_insn_srli_rd_addr : spec_insn_sub_valid ? spec_insn_sub_rd_addr : spec_insn_sw_valid ? spec_insn_sw_rd_addr : spec_insn_xor_valid ? spec_insn_xor_rd_addr : spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; assign spec_rd_wdata = spec_insn_add_valid ? spec_insn_add_rd_wdata : spec_insn_addi_valid ? spec_insn_addi_rd_wdata : spec_insn_and_valid ? spec_insn_and_rd_wdata : spec_insn_andi_valid ? spec_insn_andi_rd_wdata : spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : spec_insn_beq_valid ? spec_insn_beq_rd_wdata : spec_insn_bge_valid ? spec_insn_bge_rd_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : spec_insn_blt_valid ? spec_insn_blt_rd_wdata : spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : spec_insn_bne_valid ? spec_insn_bne_rd_wdata : spec_insn_c_add_valid ? spec_insn_c_add_rd_wdata : spec_insn_c_addi_valid ? spec_insn_c_addi_rd_wdata : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_wdata : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_wdata : spec_insn_c_and_valid ? spec_insn_c_and_rd_wdata : spec_insn_c_andi_valid ? spec_insn_c_andi_rd_wdata : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_wdata : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_wdata : spec_insn_c_j_valid ? spec_insn_c_j_rd_wdata : spec_insn_c_jal_valid ? spec_insn_c_jal_rd_wdata : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_wdata : spec_insn_c_jr_valid ? spec_insn_c_jr_rd_wdata : spec_insn_c_li_valid ? spec_insn_c_li_rd_wdata : spec_insn_c_lui_valid ? spec_insn_c_lui_rd_wdata : spec_insn_c_lw_valid ? spec_insn_c_lw_rd_wdata : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_wdata : spec_insn_c_mv_valid ? spec_insn_c_mv_rd_wdata : spec_insn_c_or_valid ? spec_insn_c_or_rd_wdata : spec_insn_c_slli_valid ? spec_insn_c_slli_rd_wdata : spec_insn_c_srai_valid ? spec_insn_c_srai_rd_wdata : spec_insn_c_srli_valid ? spec_insn_c_srli_rd_wdata : spec_insn_c_sub_valid ? spec_insn_c_sub_rd_wdata : spec_insn_c_sw_valid ? spec_insn_c_sw_rd_wdata : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_wdata : spec_insn_c_xor_valid ? spec_insn_c_xor_rd_wdata : spec_insn_jal_valid ? spec_insn_jal_rd_wdata : spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : spec_insn_lb_valid ? spec_insn_lb_rd_wdata : spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : spec_insn_lh_valid ? spec_insn_lh_rd_wdata : spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : spec_insn_lui_valid ? spec_insn_lui_rd_wdata : spec_insn_lw_valid ? spec_insn_lw_rd_wdata : spec_insn_or_valid ? spec_insn_or_rd_wdata : spec_insn_ori_valid ? spec_insn_ori_rd_wdata : spec_insn_sb_valid ? spec_insn_sb_rd_wdata : spec_insn_sh_valid ? spec_insn_sh_rd_wdata : spec_insn_sll_valid ? spec_insn_sll_rd_wdata : spec_insn_slli_valid ? spec_insn_slli_rd_wdata : spec_insn_slt_valid ? spec_insn_slt_rd_wdata : spec_insn_slti_valid ? spec_insn_slti_rd_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : spec_insn_sra_valid ? spec_insn_sra_rd_wdata : spec_insn_srai_valid ? spec_insn_srai_rd_wdata : spec_insn_srl_valid ? spec_insn_srl_rd_wdata : spec_insn_srli_valid ? spec_insn_srli_rd_wdata : spec_insn_sub_valid ? spec_insn_sub_rd_wdata : spec_insn_sw_valid ? spec_insn_sw_rd_wdata : spec_insn_xor_valid ? spec_insn_xor_rd_wdata : spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; assign spec_pc_wdata = spec_insn_add_valid ? spec_insn_add_pc_wdata : spec_insn_addi_valid ? spec_insn_addi_pc_wdata : spec_insn_and_valid ? spec_insn_and_pc_wdata : spec_insn_andi_valid ? spec_insn_andi_pc_wdata : spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : spec_insn_beq_valid ? spec_insn_beq_pc_wdata : spec_insn_bge_valid ? spec_insn_bge_pc_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : spec_insn_blt_valid ? spec_insn_blt_pc_wdata : spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : spec_insn_bne_valid ? spec_insn_bne_pc_wdata : spec_insn_c_add_valid ? spec_insn_c_add_pc_wdata : spec_insn_c_addi_valid ? spec_insn_c_addi_pc_wdata : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_pc_wdata : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_pc_wdata : spec_insn_c_and_valid ? spec_insn_c_and_pc_wdata : spec_insn_c_andi_valid ? spec_insn_c_andi_pc_wdata : spec_insn_c_beqz_valid ? spec_insn_c_beqz_pc_wdata : spec_insn_c_bnez_valid ? spec_insn_c_bnez_pc_wdata : spec_insn_c_j_valid ? spec_insn_c_j_pc_wdata : spec_insn_c_jal_valid ? spec_insn_c_jal_pc_wdata : spec_insn_c_jalr_valid ? spec_insn_c_jalr_pc_wdata : spec_insn_c_jr_valid ? spec_insn_c_jr_pc_wdata : spec_insn_c_li_valid ? spec_insn_c_li_pc_wdata : spec_insn_c_lui_valid ? spec_insn_c_lui_pc_wdata : spec_insn_c_lw_valid ? spec_insn_c_lw_pc_wdata : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_pc_wdata : spec_insn_c_mv_valid ? spec_insn_c_mv_pc_wdata : spec_insn_c_or_valid ? spec_insn_c_or_pc_wdata : spec_insn_c_slli_valid ? spec_insn_c_slli_pc_wdata : spec_insn_c_srai_valid ? spec_insn_c_srai_pc_wdata : spec_insn_c_srli_valid ? spec_insn_c_srli_pc_wdata : spec_insn_c_sub_valid ? spec_insn_c_sub_pc_wdata : spec_insn_c_sw_valid ? spec_insn_c_sw_pc_wdata : spec_insn_c_swsp_valid ? spec_insn_c_swsp_pc_wdata : spec_insn_c_xor_valid ? spec_insn_c_xor_pc_wdata : spec_insn_jal_valid ? spec_insn_jal_pc_wdata : spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : spec_insn_lb_valid ? spec_insn_lb_pc_wdata : spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : spec_insn_lh_valid ? spec_insn_lh_pc_wdata : spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : spec_insn_lui_valid ? spec_insn_lui_pc_wdata : spec_insn_lw_valid ? spec_insn_lw_pc_wdata : spec_insn_or_valid ? spec_insn_or_pc_wdata : spec_insn_ori_valid ? spec_insn_ori_pc_wdata : spec_insn_sb_valid ? spec_insn_sb_pc_wdata : spec_insn_sh_valid ? spec_insn_sh_pc_wdata : spec_insn_sll_valid ? spec_insn_sll_pc_wdata : spec_insn_slli_valid ? spec_insn_slli_pc_wdata : spec_insn_slt_valid ? spec_insn_slt_pc_wdata : spec_insn_slti_valid ? spec_insn_slti_pc_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : spec_insn_sra_valid ? spec_insn_sra_pc_wdata : spec_insn_srai_valid ? spec_insn_srai_pc_wdata : spec_insn_srl_valid ? spec_insn_srl_pc_wdata : spec_insn_srli_valid ? spec_insn_srli_pc_wdata : spec_insn_sub_valid ? spec_insn_sub_pc_wdata : spec_insn_sw_valid ? spec_insn_sw_pc_wdata : spec_insn_xor_valid ? spec_insn_xor_pc_wdata : spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; assign spec_mem_addr = spec_insn_add_valid ? spec_insn_add_mem_addr : spec_insn_addi_valid ? spec_insn_addi_mem_addr : spec_insn_and_valid ? spec_insn_and_mem_addr : spec_insn_andi_valid ? spec_insn_andi_mem_addr : spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : spec_insn_beq_valid ? spec_insn_beq_mem_addr : spec_insn_bge_valid ? spec_insn_bge_mem_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : spec_insn_blt_valid ? spec_insn_blt_mem_addr : spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : spec_insn_bne_valid ? spec_insn_bne_mem_addr : spec_insn_c_add_valid ? spec_insn_c_add_mem_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_addr : spec_insn_c_and_valid ? spec_insn_c_and_mem_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_addr : spec_insn_c_j_valid ? spec_insn_c_j_mem_addr : spec_insn_c_jal_valid ? spec_insn_c_jal_mem_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_addr : spec_insn_c_li_valid ? spec_insn_c_li_mem_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_addr : spec_insn_c_or_valid ? spec_insn_c_or_mem_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_addr : spec_insn_jal_valid ? spec_insn_jal_mem_addr : spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : spec_insn_lb_valid ? spec_insn_lb_mem_addr : spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : spec_insn_lh_valid ? spec_insn_lh_mem_addr : spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : spec_insn_lui_valid ? spec_insn_lui_mem_addr : spec_insn_lw_valid ? spec_insn_lw_mem_addr : spec_insn_or_valid ? spec_insn_or_mem_addr : spec_insn_ori_valid ? spec_insn_ori_mem_addr : spec_insn_sb_valid ? spec_insn_sb_mem_addr : spec_insn_sh_valid ? spec_insn_sh_mem_addr : spec_insn_sll_valid ? spec_insn_sll_mem_addr : spec_insn_slli_valid ? spec_insn_slli_mem_addr : spec_insn_slt_valid ? spec_insn_slt_mem_addr : spec_insn_slti_valid ? spec_insn_slti_mem_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : spec_insn_sra_valid ? spec_insn_sra_mem_addr : spec_insn_srai_valid ? spec_insn_srai_mem_addr : spec_insn_srl_valid ? spec_insn_srl_mem_addr : spec_insn_srli_valid ? spec_insn_srli_mem_addr : spec_insn_sub_valid ? spec_insn_sub_mem_addr : spec_insn_sw_valid ? spec_insn_sw_mem_addr : spec_insn_xor_valid ? spec_insn_xor_mem_addr : spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; assign spec_mem_rmask = spec_insn_add_valid ? spec_insn_add_mem_rmask : spec_insn_addi_valid ? spec_insn_addi_mem_rmask : spec_insn_and_valid ? spec_insn_and_mem_rmask : spec_insn_andi_valid ? spec_insn_andi_mem_rmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : spec_insn_beq_valid ? spec_insn_beq_mem_rmask : spec_insn_bge_valid ? spec_insn_bge_mem_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : spec_insn_blt_valid ? spec_insn_blt_mem_rmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : spec_insn_bne_valid ? spec_insn_bne_mem_rmask : spec_insn_c_add_valid ? spec_insn_c_add_mem_rmask : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_rmask : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_rmask : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_rmask : spec_insn_c_and_valid ? spec_insn_c_and_mem_rmask : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_rmask : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_rmask : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_rmask : spec_insn_c_j_valid ? spec_insn_c_j_mem_rmask : spec_insn_c_jal_valid ? spec_insn_c_jal_mem_rmask : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_rmask : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_rmask : spec_insn_c_li_valid ? spec_insn_c_li_mem_rmask : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_rmask : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_rmask : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_rmask : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_rmask : spec_insn_c_or_valid ? spec_insn_c_or_mem_rmask : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_rmask : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_rmask : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_rmask : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_rmask : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_rmask : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_rmask : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_rmask : spec_insn_jal_valid ? spec_insn_jal_mem_rmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : spec_insn_lb_valid ? spec_insn_lb_mem_rmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : spec_insn_lh_valid ? spec_insn_lh_mem_rmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : spec_insn_lui_valid ? spec_insn_lui_mem_rmask : spec_insn_lw_valid ? spec_insn_lw_mem_rmask : spec_insn_or_valid ? spec_insn_or_mem_rmask : spec_insn_ori_valid ? spec_insn_ori_mem_rmask : spec_insn_sb_valid ? spec_insn_sb_mem_rmask : spec_insn_sh_valid ? spec_insn_sh_mem_rmask : spec_insn_sll_valid ? spec_insn_sll_mem_rmask : spec_insn_slli_valid ? spec_insn_slli_mem_rmask : spec_insn_slt_valid ? spec_insn_slt_mem_rmask : spec_insn_slti_valid ? spec_insn_slti_mem_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : spec_insn_sra_valid ? spec_insn_sra_mem_rmask : spec_insn_srai_valid ? spec_insn_srai_mem_rmask : spec_insn_srl_valid ? spec_insn_srl_mem_rmask : spec_insn_srli_valid ? spec_insn_srli_mem_rmask : spec_insn_sub_valid ? spec_insn_sub_mem_rmask : spec_insn_sw_valid ? spec_insn_sw_mem_rmask : spec_insn_xor_valid ? spec_insn_xor_mem_rmask : spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; assign spec_mem_wmask = spec_insn_add_valid ? spec_insn_add_mem_wmask : spec_insn_addi_valid ? spec_insn_addi_mem_wmask : spec_insn_and_valid ? spec_insn_and_mem_wmask : spec_insn_andi_valid ? spec_insn_andi_mem_wmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : spec_insn_beq_valid ? spec_insn_beq_mem_wmask : spec_insn_bge_valid ? spec_insn_bge_mem_wmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : spec_insn_blt_valid ? spec_insn_blt_mem_wmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : spec_insn_bne_valid ? spec_insn_bne_mem_wmask : spec_insn_c_add_valid ? spec_insn_c_add_mem_wmask : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_wmask : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wmask : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wmask : spec_insn_c_and_valid ? spec_insn_c_and_mem_wmask : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_wmask : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wmask : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wmask : spec_insn_c_j_valid ? spec_insn_c_j_mem_wmask : spec_insn_c_jal_valid ? spec_insn_c_jal_mem_wmask : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wmask : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_wmask : spec_insn_c_li_valid ? spec_insn_c_li_mem_wmask : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_wmask : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_wmask : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wmask : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_wmask : spec_insn_c_or_valid ? spec_insn_c_or_mem_wmask : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_wmask : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_wmask : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_wmask : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_wmask : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_wmask : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wmask : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_wmask : spec_insn_jal_valid ? spec_insn_jal_mem_wmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : spec_insn_lb_valid ? spec_insn_lb_mem_wmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : spec_insn_lh_valid ? spec_insn_lh_mem_wmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : spec_insn_lui_valid ? spec_insn_lui_mem_wmask : spec_insn_lw_valid ? spec_insn_lw_mem_wmask : spec_insn_or_valid ? spec_insn_or_mem_wmask : spec_insn_ori_valid ? spec_insn_ori_mem_wmask : spec_insn_sb_valid ? spec_insn_sb_mem_wmask : spec_insn_sh_valid ? spec_insn_sh_mem_wmask : spec_insn_sll_valid ? spec_insn_sll_mem_wmask : spec_insn_slli_valid ? spec_insn_slli_mem_wmask : spec_insn_slt_valid ? spec_insn_slt_mem_wmask : spec_insn_slti_valid ? spec_insn_slti_mem_wmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : spec_insn_sra_valid ? spec_insn_sra_mem_wmask : spec_insn_srai_valid ? spec_insn_srai_mem_wmask : spec_insn_srl_valid ? spec_insn_srl_mem_wmask : spec_insn_srli_valid ? spec_insn_srli_mem_wmask : spec_insn_sub_valid ? spec_insn_sub_mem_wmask : spec_insn_sw_valid ? spec_insn_sw_mem_wmask : spec_insn_xor_valid ? spec_insn_xor_mem_wmask : spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; assign spec_mem_wdata = spec_insn_add_valid ? spec_insn_add_mem_wdata : spec_insn_addi_valid ? spec_insn_addi_mem_wdata : spec_insn_and_valid ? spec_insn_and_mem_wdata : spec_insn_andi_valid ? spec_insn_andi_mem_wdata : spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : spec_insn_beq_valid ? spec_insn_beq_mem_wdata : spec_insn_bge_valid ? spec_insn_bge_mem_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : spec_insn_blt_valid ? spec_insn_blt_mem_wdata : spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : spec_insn_bne_valid ? spec_insn_bne_mem_wdata : spec_insn_c_add_valid ? spec_insn_c_add_mem_wdata : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_wdata : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wdata : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wdata : spec_insn_c_and_valid ? spec_insn_c_and_mem_wdata : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_wdata : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wdata : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wdata : spec_insn_c_j_valid ? spec_insn_c_j_mem_wdata : spec_insn_c_jal_valid ? spec_insn_c_jal_mem_wdata : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wdata : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_wdata : spec_insn_c_li_valid ? spec_insn_c_li_mem_wdata : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_wdata : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_wdata : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wdata : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_wdata : spec_insn_c_or_valid ? spec_insn_c_or_mem_wdata : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_wdata : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_wdata : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_wdata : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_wdata : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_wdata : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wdata : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_wdata : spec_insn_jal_valid ? spec_insn_jal_mem_wdata : spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : spec_insn_lb_valid ? spec_insn_lb_mem_wdata : spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : spec_insn_lh_valid ? spec_insn_lh_mem_wdata : spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : spec_insn_lui_valid ? spec_insn_lui_mem_wdata : spec_insn_lw_valid ? spec_insn_lw_mem_wdata : spec_insn_or_valid ? spec_insn_or_mem_wdata : spec_insn_ori_valid ? spec_insn_ori_mem_wdata : spec_insn_sb_valid ? spec_insn_sb_mem_wdata : spec_insn_sh_valid ? spec_insn_sh_mem_wdata : spec_insn_sll_valid ? spec_insn_sll_mem_wdata : spec_insn_slli_valid ? spec_insn_slli_mem_wdata : spec_insn_slt_valid ? spec_insn_slt_mem_wdata : spec_insn_slti_valid ? spec_insn_slti_mem_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : spec_insn_sra_valid ? spec_insn_sra_mem_wdata : spec_insn_srai_valid ? spec_insn_srai_mem_wdata : spec_insn_srl_valid ? spec_insn_srl_mem_wdata : spec_insn_srli_valid ? spec_insn_srli_mem_wdata : spec_insn_sub_valid ? spec_insn_sub_mem_wdata : spec_insn_sw_valid ? spec_insn_sw_mem_wdata : spec_insn_xor_valid ? spec_insn_xor_mem_wdata : spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; `ifdef RISCV_FORMAL_CSR_MISA assign spec_csr_misa_rmask = spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : spec_insn_c_add_valid ? spec_insn_c_add_csr_misa_rmask : spec_insn_c_addi_valid ? spec_insn_c_addi_csr_misa_rmask : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_csr_misa_rmask : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_csr_misa_rmask : spec_insn_c_and_valid ? spec_insn_c_and_csr_misa_rmask : spec_insn_c_andi_valid ? spec_insn_c_andi_csr_misa_rmask : spec_insn_c_beqz_valid ? spec_insn_c_beqz_csr_misa_rmask : spec_insn_c_bnez_valid ? spec_insn_c_bnez_csr_misa_rmask : spec_insn_c_j_valid ? spec_insn_c_j_csr_misa_rmask : spec_insn_c_jal_valid ? spec_insn_c_jal_csr_misa_rmask : spec_insn_c_jalr_valid ? spec_insn_c_jalr_csr_misa_rmask : spec_insn_c_jr_valid ? spec_insn_c_jr_csr_misa_rmask : spec_insn_c_li_valid ? spec_insn_c_li_csr_misa_rmask : spec_insn_c_lui_valid ? spec_insn_c_lui_csr_misa_rmask : spec_insn_c_lw_valid ? spec_insn_c_lw_csr_misa_rmask : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_csr_misa_rmask : spec_insn_c_mv_valid ? spec_insn_c_mv_csr_misa_rmask : spec_insn_c_or_valid ? spec_insn_c_or_csr_misa_rmask : spec_insn_c_slli_valid ? spec_insn_c_slli_csr_misa_rmask : spec_insn_c_srai_valid ? spec_insn_c_srai_csr_misa_rmask : spec_insn_c_srli_valid ? spec_insn_c_srli_csr_misa_rmask : spec_insn_c_sub_valid ? spec_insn_c_sub_csr_misa_rmask : spec_insn_c_sw_valid ? spec_insn_c_sw_csr_misa_rmask : spec_insn_c_swsp_valid ? spec_insn_c_swsp_csr_misa_rmask : spec_insn_c_xor_valid ? spec_insn_c_xor_csr_misa_rmask : spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; `endif endmodule ================================================ FILE: insns/isa_rv32im.txt ================================================ add addi and andi auipc beq bge bgeu blt bltu bne div divu jal jalr lb lbu lh lhu lui lw mul mulh mulhsu mulhu or ori rem remu sb sh sll slli slt slti sltiu sltu sra srai srl srli sub sw xor xori ================================================ FILE: insns/isa_rv32im.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_isa_rv32im ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); wire spec_insn_add_valid; wire spec_insn_add_trap; wire [ 4 : 0] spec_insn_add_rs1_addr; wire [ 4 : 0] spec_insn_add_rs2_addr; wire [ 4 : 0] spec_insn_add_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; `endif rvfi_insn_add insn_add ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), `endif .spec_valid(spec_insn_add_valid), .spec_trap(spec_insn_add_trap), .spec_rs1_addr(spec_insn_add_rs1_addr), .spec_rs2_addr(spec_insn_add_rs2_addr), .spec_rd_addr(spec_insn_add_rd_addr), .spec_rd_wdata(spec_insn_add_rd_wdata), .spec_pc_wdata(spec_insn_add_pc_wdata), .spec_mem_addr(spec_insn_add_mem_addr), .spec_mem_rmask(spec_insn_add_mem_rmask), .spec_mem_wmask(spec_insn_add_mem_wmask), .spec_mem_wdata(spec_insn_add_mem_wdata) ); wire spec_insn_addi_valid; wire spec_insn_addi_trap; wire [ 4 : 0] spec_insn_addi_rs1_addr; wire [ 4 : 0] spec_insn_addi_rs2_addr; wire [ 4 : 0] spec_insn_addi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; `endif rvfi_insn_addi insn_addi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), `endif .spec_valid(spec_insn_addi_valid), .spec_trap(spec_insn_addi_trap), .spec_rs1_addr(spec_insn_addi_rs1_addr), .spec_rs2_addr(spec_insn_addi_rs2_addr), .spec_rd_addr(spec_insn_addi_rd_addr), .spec_rd_wdata(spec_insn_addi_rd_wdata), .spec_pc_wdata(spec_insn_addi_pc_wdata), .spec_mem_addr(spec_insn_addi_mem_addr), .spec_mem_rmask(spec_insn_addi_mem_rmask), .spec_mem_wmask(spec_insn_addi_mem_wmask), .spec_mem_wdata(spec_insn_addi_mem_wdata) ); wire spec_insn_and_valid; wire spec_insn_and_trap; wire [ 4 : 0] spec_insn_and_rs1_addr; wire [ 4 : 0] spec_insn_and_rs2_addr; wire [ 4 : 0] spec_insn_and_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; `endif rvfi_insn_and insn_and ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), `endif .spec_valid(spec_insn_and_valid), .spec_trap(spec_insn_and_trap), .spec_rs1_addr(spec_insn_and_rs1_addr), .spec_rs2_addr(spec_insn_and_rs2_addr), .spec_rd_addr(spec_insn_and_rd_addr), .spec_rd_wdata(spec_insn_and_rd_wdata), .spec_pc_wdata(spec_insn_and_pc_wdata), .spec_mem_addr(spec_insn_and_mem_addr), .spec_mem_rmask(spec_insn_and_mem_rmask), .spec_mem_wmask(spec_insn_and_mem_wmask), .spec_mem_wdata(spec_insn_and_mem_wdata) ); wire spec_insn_andi_valid; wire spec_insn_andi_trap; wire [ 4 : 0] spec_insn_andi_rs1_addr; wire [ 4 : 0] spec_insn_andi_rs2_addr; wire [ 4 : 0] spec_insn_andi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; `endif rvfi_insn_andi insn_andi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), `endif .spec_valid(spec_insn_andi_valid), .spec_trap(spec_insn_andi_trap), .spec_rs1_addr(spec_insn_andi_rs1_addr), .spec_rs2_addr(spec_insn_andi_rs2_addr), .spec_rd_addr(spec_insn_andi_rd_addr), .spec_rd_wdata(spec_insn_andi_rd_wdata), .spec_pc_wdata(spec_insn_andi_pc_wdata), .spec_mem_addr(spec_insn_andi_mem_addr), .spec_mem_rmask(spec_insn_andi_mem_rmask), .spec_mem_wmask(spec_insn_andi_mem_wmask), .spec_mem_wdata(spec_insn_andi_mem_wdata) ); wire spec_insn_auipc_valid; wire spec_insn_auipc_trap; wire [ 4 : 0] spec_insn_auipc_rs1_addr; wire [ 4 : 0] spec_insn_auipc_rs2_addr; wire [ 4 : 0] spec_insn_auipc_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; `endif rvfi_insn_auipc insn_auipc ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), `endif .spec_valid(spec_insn_auipc_valid), .spec_trap(spec_insn_auipc_trap), .spec_rs1_addr(spec_insn_auipc_rs1_addr), .spec_rs2_addr(spec_insn_auipc_rs2_addr), .spec_rd_addr(spec_insn_auipc_rd_addr), .spec_rd_wdata(spec_insn_auipc_rd_wdata), .spec_pc_wdata(spec_insn_auipc_pc_wdata), .spec_mem_addr(spec_insn_auipc_mem_addr), .spec_mem_rmask(spec_insn_auipc_mem_rmask), .spec_mem_wmask(spec_insn_auipc_mem_wmask), .spec_mem_wdata(spec_insn_auipc_mem_wdata) ); wire spec_insn_beq_valid; wire spec_insn_beq_trap; wire [ 4 : 0] spec_insn_beq_rs1_addr; wire [ 4 : 0] spec_insn_beq_rs2_addr; wire [ 4 : 0] spec_insn_beq_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; `endif rvfi_insn_beq insn_beq ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), `endif .spec_valid(spec_insn_beq_valid), .spec_trap(spec_insn_beq_trap), .spec_rs1_addr(spec_insn_beq_rs1_addr), .spec_rs2_addr(spec_insn_beq_rs2_addr), .spec_rd_addr(spec_insn_beq_rd_addr), .spec_rd_wdata(spec_insn_beq_rd_wdata), .spec_pc_wdata(spec_insn_beq_pc_wdata), .spec_mem_addr(spec_insn_beq_mem_addr), .spec_mem_rmask(spec_insn_beq_mem_rmask), .spec_mem_wmask(spec_insn_beq_mem_wmask), .spec_mem_wdata(spec_insn_beq_mem_wdata) ); wire spec_insn_bge_valid; wire spec_insn_bge_trap; wire [ 4 : 0] spec_insn_bge_rs1_addr; wire [ 4 : 0] spec_insn_bge_rs2_addr; wire [ 4 : 0] spec_insn_bge_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; `endif rvfi_insn_bge insn_bge ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), `endif .spec_valid(spec_insn_bge_valid), .spec_trap(spec_insn_bge_trap), .spec_rs1_addr(spec_insn_bge_rs1_addr), .spec_rs2_addr(spec_insn_bge_rs2_addr), .spec_rd_addr(spec_insn_bge_rd_addr), .spec_rd_wdata(spec_insn_bge_rd_wdata), .spec_pc_wdata(spec_insn_bge_pc_wdata), .spec_mem_addr(spec_insn_bge_mem_addr), .spec_mem_rmask(spec_insn_bge_mem_rmask), .spec_mem_wmask(spec_insn_bge_mem_wmask), .spec_mem_wdata(spec_insn_bge_mem_wdata) ); wire spec_insn_bgeu_valid; wire spec_insn_bgeu_trap; wire [ 4 : 0] spec_insn_bgeu_rs1_addr; wire [ 4 : 0] spec_insn_bgeu_rs2_addr; wire [ 4 : 0] spec_insn_bgeu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; `endif rvfi_insn_bgeu insn_bgeu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), `endif .spec_valid(spec_insn_bgeu_valid), .spec_trap(spec_insn_bgeu_trap), .spec_rs1_addr(spec_insn_bgeu_rs1_addr), .spec_rs2_addr(spec_insn_bgeu_rs2_addr), .spec_rd_addr(spec_insn_bgeu_rd_addr), .spec_rd_wdata(spec_insn_bgeu_rd_wdata), .spec_pc_wdata(spec_insn_bgeu_pc_wdata), .spec_mem_addr(spec_insn_bgeu_mem_addr), .spec_mem_rmask(spec_insn_bgeu_mem_rmask), .spec_mem_wmask(spec_insn_bgeu_mem_wmask), .spec_mem_wdata(spec_insn_bgeu_mem_wdata) ); wire spec_insn_blt_valid; wire spec_insn_blt_trap; wire [ 4 : 0] spec_insn_blt_rs1_addr; wire [ 4 : 0] spec_insn_blt_rs2_addr; wire [ 4 : 0] spec_insn_blt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; `endif rvfi_insn_blt insn_blt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), `endif .spec_valid(spec_insn_blt_valid), .spec_trap(spec_insn_blt_trap), .spec_rs1_addr(spec_insn_blt_rs1_addr), .spec_rs2_addr(spec_insn_blt_rs2_addr), .spec_rd_addr(spec_insn_blt_rd_addr), .spec_rd_wdata(spec_insn_blt_rd_wdata), .spec_pc_wdata(spec_insn_blt_pc_wdata), .spec_mem_addr(spec_insn_blt_mem_addr), .spec_mem_rmask(spec_insn_blt_mem_rmask), .spec_mem_wmask(spec_insn_blt_mem_wmask), .spec_mem_wdata(spec_insn_blt_mem_wdata) ); wire spec_insn_bltu_valid; wire spec_insn_bltu_trap; wire [ 4 : 0] spec_insn_bltu_rs1_addr; wire [ 4 : 0] spec_insn_bltu_rs2_addr; wire [ 4 : 0] spec_insn_bltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; `endif rvfi_insn_bltu insn_bltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), `endif .spec_valid(spec_insn_bltu_valid), .spec_trap(spec_insn_bltu_trap), .spec_rs1_addr(spec_insn_bltu_rs1_addr), .spec_rs2_addr(spec_insn_bltu_rs2_addr), .spec_rd_addr(spec_insn_bltu_rd_addr), .spec_rd_wdata(spec_insn_bltu_rd_wdata), .spec_pc_wdata(spec_insn_bltu_pc_wdata), .spec_mem_addr(spec_insn_bltu_mem_addr), .spec_mem_rmask(spec_insn_bltu_mem_rmask), .spec_mem_wmask(spec_insn_bltu_mem_wmask), .spec_mem_wdata(spec_insn_bltu_mem_wdata) ); wire spec_insn_bne_valid; wire spec_insn_bne_trap; wire [ 4 : 0] spec_insn_bne_rs1_addr; wire [ 4 : 0] spec_insn_bne_rs2_addr; wire [ 4 : 0] spec_insn_bne_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; `endif rvfi_insn_bne insn_bne ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), `endif .spec_valid(spec_insn_bne_valid), .spec_trap(spec_insn_bne_trap), .spec_rs1_addr(spec_insn_bne_rs1_addr), .spec_rs2_addr(spec_insn_bne_rs2_addr), .spec_rd_addr(spec_insn_bne_rd_addr), .spec_rd_wdata(spec_insn_bne_rd_wdata), .spec_pc_wdata(spec_insn_bne_pc_wdata), .spec_mem_addr(spec_insn_bne_mem_addr), .spec_mem_rmask(spec_insn_bne_mem_rmask), .spec_mem_wmask(spec_insn_bne_mem_wmask), .spec_mem_wdata(spec_insn_bne_mem_wdata) ); wire spec_insn_div_valid; wire spec_insn_div_trap; wire [ 4 : 0] spec_insn_div_rs1_addr; wire [ 4 : 0] spec_insn_div_rs2_addr; wire [ 4 : 0] spec_insn_div_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_csr_misa_rmask; `endif rvfi_insn_div insn_div ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_div_csr_misa_rmask), `endif .spec_valid(spec_insn_div_valid), .spec_trap(spec_insn_div_trap), .spec_rs1_addr(spec_insn_div_rs1_addr), .spec_rs2_addr(spec_insn_div_rs2_addr), .spec_rd_addr(spec_insn_div_rd_addr), .spec_rd_wdata(spec_insn_div_rd_wdata), .spec_pc_wdata(spec_insn_div_pc_wdata), .spec_mem_addr(spec_insn_div_mem_addr), .spec_mem_rmask(spec_insn_div_mem_rmask), .spec_mem_wmask(spec_insn_div_mem_wmask), .spec_mem_wdata(spec_insn_div_mem_wdata) ); wire spec_insn_divu_valid; wire spec_insn_divu_trap; wire [ 4 : 0] spec_insn_divu_rs1_addr; wire [ 4 : 0] spec_insn_divu_rs2_addr; wire [ 4 : 0] spec_insn_divu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_csr_misa_rmask; `endif rvfi_insn_divu insn_divu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_divu_csr_misa_rmask), `endif .spec_valid(spec_insn_divu_valid), .spec_trap(spec_insn_divu_trap), .spec_rs1_addr(spec_insn_divu_rs1_addr), .spec_rs2_addr(spec_insn_divu_rs2_addr), .spec_rd_addr(spec_insn_divu_rd_addr), .spec_rd_wdata(spec_insn_divu_rd_wdata), .spec_pc_wdata(spec_insn_divu_pc_wdata), .spec_mem_addr(spec_insn_divu_mem_addr), .spec_mem_rmask(spec_insn_divu_mem_rmask), .spec_mem_wmask(spec_insn_divu_mem_wmask), .spec_mem_wdata(spec_insn_divu_mem_wdata) ); wire spec_insn_jal_valid; wire spec_insn_jal_trap; wire [ 4 : 0] spec_insn_jal_rs1_addr; wire [ 4 : 0] spec_insn_jal_rs2_addr; wire [ 4 : 0] spec_insn_jal_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; `endif rvfi_insn_jal insn_jal ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), `endif .spec_valid(spec_insn_jal_valid), .spec_trap(spec_insn_jal_trap), .spec_rs1_addr(spec_insn_jal_rs1_addr), .spec_rs2_addr(spec_insn_jal_rs2_addr), .spec_rd_addr(spec_insn_jal_rd_addr), .spec_rd_wdata(spec_insn_jal_rd_wdata), .spec_pc_wdata(spec_insn_jal_pc_wdata), .spec_mem_addr(spec_insn_jal_mem_addr), .spec_mem_rmask(spec_insn_jal_mem_rmask), .spec_mem_wmask(spec_insn_jal_mem_wmask), .spec_mem_wdata(spec_insn_jal_mem_wdata) ); wire spec_insn_jalr_valid; wire spec_insn_jalr_trap; wire [ 4 : 0] spec_insn_jalr_rs1_addr; wire [ 4 : 0] spec_insn_jalr_rs2_addr; wire [ 4 : 0] spec_insn_jalr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; `endif rvfi_insn_jalr insn_jalr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), `endif .spec_valid(spec_insn_jalr_valid), .spec_trap(spec_insn_jalr_trap), .spec_rs1_addr(spec_insn_jalr_rs1_addr), .spec_rs2_addr(spec_insn_jalr_rs2_addr), .spec_rd_addr(spec_insn_jalr_rd_addr), .spec_rd_wdata(spec_insn_jalr_rd_wdata), .spec_pc_wdata(spec_insn_jalr_pc_wdata), .spec_mem_addr(spec_insn_jalr_mem_addr), .spec_mem_rmask(spec_insn_jalr_mem_rmask), .spec_mem_wmask(spec_insn_jalr_mem_wmask), .spec_mem_wdata(spec_insn_jalr_mem_wdata) ); wire spec_insn_lb_valid; wire spec_insn_lb_trap; wire [ 4 : 0] spec_insn_lb_rs1_addr; wire [ 4 : 0] spec_insn_lb_rs2_addr; wire [ 4 : 0] spec_insn_lb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; `endif rvfi_insn_lb insn_lb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), `endif .spec_valid(spec_insn_lb_valid), .spec_trap(spec_insn_lb_trap), .spec_rs1_addr(spec_insn_lb_rs1_addr), .spec_rs2_addr(spec_insn_lb_rs2_addr), .spec_rd_addr(spec_insn_lb_rd_addr), .spec_rd_wdata(spec_insn_lb_rd_wdata), .spec_pc_wdata(spec_insn_lb_pc_wdata), .spec_mem_addr(spec_insn_lb_mem_addr), .spec_mem_rmask(spec_insn_lb_mem_rmask), .spec_mem_wmask(spec_insn_lb_mem_wmask), .spec_mem_wdata(spec_insn_lb_mem_wdata) ); wire spec_insn_lbu_valid; wire spec_insn_lbu_trap; wire [ 4 : 0] spec_insn_lbu_rs1_addr; wire [ 4 : 0] spec_insn_lbu_rs2_addr; wire [ 4 : 0] spec_insn_lbu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; `endif rvfi_insn_lbu insn_lbu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), `endif .spec_valid(spec_insn_lbu_valid), .spec_trap(spec_insn_lbu_trap), .spec_rs1_addr(spec_insn_lbu_rs1_addr), .spec_rs2_addr(spec_insn_lbu_rs2_addr), .spec_rd_addr(spec_insn_lbu_rd_addr), .spec_rd_wdata(spec_insn_lbu_rd_wdata), .spec_pc_wdata(spec_insn_lbu_pc_wdata), .spec_mem_addr(spec_insn_lbu_mem_addr), .spec_mem_rmask(spec_insn_lbu_mem_rmask), .spec_mem_wmask(spec_insn_lbu_mem_wmask), .spec_mem_wdata(spec_insn_lbu_mem_wdata) ); wire spec_insn_lh_valid; wire spec_insn_lh_trap; wire [ 4 : 0] spec_insn_lh_rs1_addr; wire [ 4 : 0] spec_insn_lh_rs2_addr; wire [ 4 : 0] spec_insn_lh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; `endif rvfi_insn_lh insn_lh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), `endif .spec_valid(spec_insn_lh_valid), .spec_trap(spec_insn_lh_trap), .spec_rs1_addr(spec_insn_lh_rs1_addr), .spec_rs2_addr(spec_insn_lh_rs2_addr), .spec_rd_addr(spec_insn_lh_rd_addr), .spec_rd_wdata(spec_insn_lh_rd_wdata), .spec_pc_wdata(spec_insn_lh_pc_wdata), .spec_mem_addr(spec_insn_lh_mem_addr), .spec_mem_rmask(spec_insn_lh_mem_rmask), .spec_mem_wmask(spec_insn_lh_mem_wmask), .spec_mem_wdata(spec_insn_lh_mem_wdata) ); wire spec_insn_lhu_valid; wire spec_insn_lhu_trap; wire [ 4 : 0] spec_insn_lhu_rs1_addr; wire [ 4 : 0] spec_insn_lhu_rs2_addr; wire [ 4 : 0] spec_insn_lhu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; `endif rvfi_insn_lhu insn_lhu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), `endif .spec_valid(spec_insn_lhu_valid), .spec_trap(spec_insn_lhu_trap), .spec_rs1_addr(spec_insn_lhu_rs1_addr), .spec_rs2_addr(spec_insn_lhu_rs2_addr), .spec_rd_addr(spec_insn_lhu_rd_addr), .spec_rd_wdata(spec_insn_lhu_rd_wdata), .spec_pc_wdata(spec_insn_lhu_pc_wdata), .spec_mem_addr(spec_insn_lhu_mem_addr), .spec_mem_rmask(spec_insn_lhu_mem_rmask), .spec_mem_wmask(spec_insn_lhu_mem_wmask), .spec_mem_wdata(spec_insn_lhu_mem_wdata) ); wire spec_insn_lui_valid; wire spec_insn_lui_trap; wire [ 4 : 0] spec_insn_lui_rs1_addr; wire [ 4 : 0] spec_insn_lui_rs2_addr; wire [ 4 : 0] spec_insn_lui_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; `endif rvfi_insn_lui insn_lui ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), `endif .spec_valid(spec_insn_lui_valid), .spec_trap(spec_insn_lui_trap), .spec_rs1_addr(spec_insn_lui_rs1_addr), .spec_rs2_addr(spec_insn_lui_rs2_addr), .spec_rd_addr(spec_insn_lui_rd_addr), .spec_rd_wdata(spec_insn_lui_rd_wdata), .spec_pc_wdata(spec_insn_lui_pc_wdata), .spec_mem_addr(spec_insn_lui_mem_addr), .spec_mem_rmask(spec_insn_lui_mem_rmask), .spec_mem_wmask(spec_insn_lui_mem_wmask), .spec_mem_wdata(spec_insn_lui_mem_wdata) ); wire spec_insn_lw_valid; wire spec_insn_lw_trap; wire [ 4 : 0] spec_insn_lw_rs1_addr; wire [ 4 : 0] spec_insn_lw_rs2_addr; wire [ 4 : 0] spec_insn_lw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; `endif rvfi_insn_lw insn_lw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), `endif .spec_valid(spec_insn_lw_valid), .spec_trap(spec_insn_lw_trap), .spec_rs1_addr(spec_insn_lw_rs1_addr), .spec_rs2_addr(spec_insn_lw_rs2_addr), .spec_rd_addr(spec_insn_lw_rd_addr), .spec_rd_wdata(spec_insn_lw_rd_wdata), .spec_pc_wdata(spec_insn_lw_pc_wdata), .spec_mem_addr(spec_insn_lw_mem_addr), .spec_mem_rmask(spec_insn_lw_mem_rmask), .spec_mem_wmask(spec_insn_lw_mem_wmask), .spec_mem_wdata(spec_insn_lw_mem_wdata) ); wire spec_insn_mul_valid; wire spec_insn_mul_trap; wire [ 4 : 0] spec_insn_mul_rs1_addr; wire [ 4 : 0] spec_insn_mul_rs2_addr; wire [ 4 : 0] spec_insn_mul_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_csr_misa_rmask; `endif rvfi_insn_mul insn_mul ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mul_csr_misa_rmask), `endif .spec_valid(spec_insn_mul_valid), .spec_trap(spec_insn_mul_trap), .spec_rs1_addr(spec_insn_mul_rs1_addr), .spec_rs2_addr(spec_insn_mul_rs2_addr), .spec_rd_addr(spec_insn_mul_rd_addr), .spec_rd_wdata(spec_insn_mul_rd_wdata), .spec_pc_wdata(spec_insn_mul_pc_wdata), .spec_mem_addr(spec_insn_mul_mem_addr), .spec_mem_rmask(spec_insn_mul_mem_rmask), .spec_mem_wmask(spec_insn_mul_mem_wmask), .spec_mem_wdata(spec_insn_mul_mem_wdata) ); wire spec_insn_mulh_valid; wire spec_insn_mulh_trap; wire [ 4 : 0] spec_insn_mulh_rs1_addr; wire [ 4 : 0] spec_insn_mulh_rs2_addr; wire [ 4 : 0] spec_insn_mulh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_csr_misa_rmask; `endif rvfi_insn_mulh insn_mulh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mulh_csr_misa_rmask), `endif .spec_valid(spec_insn_mulh_valid), .spec_trap(spec_insn_mulh_trap), .spec_rs1_addr(spec_insn_mulh_rs1_addr), .spec_rs2_addr(spec_insn_mulh_rs2_addr), .spec_rd_addr(spec_insn_mulh_rd_addr), .spec_rd_wdata(spec_insn_mulh_rd_wdata), .spec_pc_wdata(spec_insn_mulh_pc_wdata), .spec_mem_addr(spec_insn_mulh_mem_addr), .spec_mem_rmask(spec_insn_mulh_mem_rmask), .spec_mem_wmask(spec_insn_mulh_mem_wmask), .spec_mem_wdata(spec_insn_mulh_mem_wdata) ); wire spec_insn_mulhsu_valid; wire spec_insn_mulhsu_trap; wire [ 4 : 0] spec_insn_mulhsu_rs1_addr; wire [ 4 : 0] spec_insn_mulhsu_rs2_addr; wire [ 4 : 0] spec_insn_mulhsu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_csr_misa_rmask; `endif rvfi_insn_mulhsu insn_mulhsu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mulhsu_csr_misa_rmask), `endif .spec_valid(spec_insn_mulhsu_valid), .spec_trap(spec_insn_mulhsu_trap), .spec_rs1_addr(spec_insn_mulhsu_rs1_addr), .spec_rs2_addr(spec_insn_mulhsu_rs2_addr), .spec_rd_addr(spec_insn_mulhsu_rd_addr), .spec_rd_wdata(spec_insn_mulhsu_rd_wdata), .spec_pc_wdata(spec_insn_mulhsu_pc_wdata), .spec_mem_addr(spec_insn_mulhsu_mem_addr), .spec_mem_rmask(spec_insn_mulhsu_mem_rmask), .spec_mem_wmask(spec_insn_mulhsu_mem_wmask), .spec_mem_wdata(spec_insn_mulhsu_mem_wdata) ); wire spec_insn_mulhu_valid; wire spec_insn_mulhu_trap; wire [ 4 : 0] spec_insn_mulhu_rs1_addr; wire [ 4 : 0] spec_insn_mulhu_rs2_addr; wire [ 4 : 0] spec_insn_mulhu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_csr_misa_rmask; `endif rvfi_insn_mulhu insn_mulhu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mulhu_csr_misa_rmask), `endif .spec_valid(spec_insn_mulhu_valid), .spec_trap(spec_insn_mulhu_trap), .spec_rs1_addr(spec_insn_mulhu_rs1_addr), .spec_rs2_addr(spec_insn_mulhu_rs2_addr), .spec_rd_addr(spec_insn_mulhu_rd_addr), .spec_rd_wdata(spec_insn_mulhu_rd_wdata), .spec_pc_wdata(spec_insn_mulhu_pc_wdata), .spec_mem_addr(spec_insn_mulhu_mem_addr), .spec_mem_rmask(spec_insn_mulhu_mem_rmask), .spec_mem_wmask(spec_insn_mulhu_mem_wmask), .spec_mem_wdata(spec_insn_mulhu_mem_wdata) ); wire spec_insn_or_valid; wire spec_insn_or_trap; wire [ 4 : 0] spec_insn_or_rs1_addr; wire [ 4 : 0] spec_insn_or_rs2_addr; wire [ 4 : 0] spec_insn_or_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; `endif rvfi_insn_or insn_or ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), `endif .spec_valid(spec_insn_or_valid), .spec_trap(spec_insn_or_trap), .spec_rs1_addr(spec_insn_or_rs1_addr), .spec_rs2_addr(spec_insn_or_rs2_addr), .spec_rd_addr(spec_insn_or_rd_addr), .spec_rd_wdata(spec_insn_or_rd_wdata), .spec_pc_wdata(spec_insn_or_pc_wdata), .spec_mem_addr(spec_insn_or_mem_addr), .spec_mem_rmask(spec_insn_or_mem_rmask), .spec_mem_wmask(spec_insn_or_mem_wmask), .spec_mem_wdata(spec_insn_or_mem_wdata) ); wire spec_insn_ori_valid; wire spec_insn_ori_trap; wire [ 4 : 0] spec_insn_ori_rs1_addr; wire [ 4 : 0] spec_insn_ori_rs2_addr; wire [ 4 : 0] spec_insn_ori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; `endif rvfi_insn_ori insn_ori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), `endif .spec_valid(spec_insn_ori_valid), .spec_trap(spec_insn_ori_trap), .spec_rs1_addr(spec_insn_ori_rs1_addr), .spec_rs2_addr(spec_insn_ori_rs2_addr), .spec_rd_addr(spec_insn_ori_rd_addr), .spec_rd_wdata(spec_insn_ori_rd_wdata), .spec_pc_wdata(spec_insn_ori_pc_wdata), .spec_mem_addr(spec_insn_ori_mem_addr), .spec_mem_rmask(spec_insn_ori_mem_rmask), .spec_mem_wmask(spec_insn_ori_mem_wmask), .spec_mem_wdata(spec_insn_ori_mem_wdata) ); wire spec_insn_rem_valid; wire spec_insn_rem_trap; wire [ 4 : 0] spec_insn_rem_rs1_addr; wire [ 4 : 0] spec_insn_rem_rs2_addr; wire [ 4 : 0] spec_insn_rem_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_csr_misa_rmask; `endif rvfi_insn_rem insn_rem ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_rem_csr_misa_rmask), `endif .spec_valid(spec_insn_rem_valid), .spec_trap(spec_insn_rem_trap), .spec_rs1_addr(spec_insn_rem_rs1_addr), .spec_rs2_addr(spec_insn_rem_rs2_addr), .spec_rd_addr(spec_insn_rem_rd_addr), .spec_rd_wdata(spec_insn_rem_rd_wdata), .spec_pc_wdata(spec_insn_rem_pc_wdata), .spec_mem_addr(spec_insn_rem_mem_addr), .spec_mem_rmask(spec_insn_rem_mem_rmask), .spec_mem_wmask(spec_insn_rem_mem_wmask), .spec_mem_wdata(spec_insn_rem_mem_wdata) ); wire spec_insn_remu_valid; wire spec_insn_remu_trap; wire [ 4 : 0] spec_insn_remu_rs1_addr; wire [ 4 : 0] spec_insn_remu_rs2_addr; wire [ 4 : 0] spec_insn_remu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_csr_misa_rmask; `endif rvfi_insn_remu insn_remu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_remu_csr_misa_rmask), `endif .spec_valid(spec_insn_remu_valid), .spec_trap(spec_insn_remu_trap), .spec_rs1_addr(spec_insn_remu_rs1_addr), .spec_rs2_addr(spec_insn_remu_rs2_addr), .spec_rd_addr(spec_insn_remu_rd_addr), .spec_rd_wdata(spec_insn_remu_rd_wdata), .spec_pc_wdata(spec_insn_remu_pc_wdata), .spec_mem_addr(spec_insn_remu_mem_addr), .spec_mem_rmask(spec_insn_remu_mem_rmask), .spec_mem_wmask(spec_insn_remu_mem_wmask), .spec_mem_wdata(spec_insn_remu_mem_wdata) ); wire spec_insn_sb_valid; wire spec_insn_sb_trap; wire [ 4 : 0] spec_insn_sb_rs1_addr; wire [ 4 : 0] spec_insn_sb_rs2_addr; wire [ 4 : 0] spec_insn_sb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; `endif rvfi_insn_sb insn_sb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), `endif .spec_valid(spec_insn_sb_valid), .spec_trap(spec_insn_sb_trap), .spec_rs1_addr(spec_insn_sb_rs1_addr), .spec_rs2_addr(spec_insn_sb_rs2_addr), .spec_rd_addr(spec_insn_sb_rd_addr), .spec_rd_wdata(spec_insn_sb_rd_wdata), .spec_pc_wdata(spec_insn_sb_pc_wdata), .spec_mem_addr(spec_insn_sb_mem_addr), .spec_mem_rmask(spec_insn_sb_mem_rmask), .spec_mem_wmask(spec_insn_sb_mem_wmask), .spec_mem_wdata(spec_insn_sb_mem_wdata) ); wire spec_insn_sh_valid; wire spec_insn_sh_trap; wire [ 4 : 0] spec_insn_sh_rs1_addr; wire [ 4 : 0] spec_insn_sh_rs2_addr; wire [ 4 : 0] spec_insn_sh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; `endif rvfi_insn_sh insn_sh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), `endif .spec_valid(spec_insn_sh_valid), .spec_trap(spec_insn_sh_trap), .spec_rs1_addr(spec_insn_sh_rs1_addr), .spec_rs2_addr(spec_insn_sh_rs2_addr), .spec_rd_addr(spec_insn_sh_rd_addr), .spec_rd_wdata(spec_insn_sh_rd_wdata), .spec_pc_wdata(spec_insn_sh_pc_wdata), .spec_mem_addr(spec_insn_sh_mem_addr), .spec_mem_rmask(spec_insn_sh_mem_rmask), .spec_mem_wmask(spec_insn_sh_mem_wmask), .spec_mem_wdata(spec_insn_sh_mem_wdata) ); wire spec_insn_sll_valid; wire spec_insn_sll_trap; wire [ 4 : 0] spec_insn_sll_rs1_addr; wire [ 4 : 0] spec_insn_sll_rs2_addr; wire [ 4 : 0] spec_insn_sll_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; `endif rvfi_insn_sll insn_sll ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), `endif .spec_valid(spec_insn_sll_valid), .spec_trap(spec_insn_sll_trap), .spec_rs1_addr(spec_insn_sll_rs1_addr), .spec_rs2_addr(spec_insn_sll_rs2_addr), .spec_rd_addr(spec_insn_sll_rd_addr), .spec_rd_wdata(spec_insn_sll_rd_wdata), .spec_pc_wdata(spec_insn_sll_pc_wdata), .spec_mem_addr(spec_insn_sll_mem_addr), .spec_mem_rmask(spec_insn_sll_mem_rmask), .spec_mem_wmask(spec_insn_sll_mem_wmask), .spec_mem_wdata(spec_insn_sll_mem_wdata) ); wire spec_insn_slli_valid; wire spec_insn_slli_trap; wire [ 4 : 0] spec_insn_slli_rs1_addr; wire [ 4 : 0] spec_insn_slli_rs2_addr; wire [ 4 : 0] spec_insn_slli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; `endif rvfi_insn_slli insn_slli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), `endif .spec_valid(spec_insn_slli_valid), .spec_trap(spec_insn_slli_trap), .spec_rs1_addr(spec_insn_slli_rs1_addr), .spec_rs2_addr(spec_insn_slli_rs2_addr), .spec_rd_addr(spec_insn_slli_rd_addr), .spec_rd_wdata(spec_insn_slli_rd_wdata), .spec_pc_wdata(spec_insn_slli_pc_wdata), .spec_mem_addr(spec_insn_slli_mem_addr), .spec_mem_rmask(spec_insn_slli_mem_rmask), .spec_mem_wmask(spec_insn_slli_mem_wmask), .spec_mem_wdata(spec_insn_slli_mem_wdata) ); wire spec_insn_slt_valid; wire spec_insn_slt_trap; wire [ 4 : 0] spec_insn_slt_rs1_addr; wire [ 4 : 0] spec_insn_slt_rs2_addr; wire [ 4 : 0] spec_insn_slt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; `endif rvfi_insn_slt insn_slt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), `endif .spec_valid(spec_insn_slt_valid), .spec_trap(spec_insn_slt_trap), .spec_rs1_addr(spec_insn_slt_rs1_addr), .spec_rs2_addr(spec_insn_slt_rs2_addr), .spec_rd_addr(spec_insn_slt_rd_addr), .spec_rd_wdata(spec_insn_slt_rd_wdata), .spec_pc_wdata(spec_insn_slt_pc_wdata), .spec_mem_addr(spec_insn_slt_mem_addr), .spec_mem_rmask(spec_insn_slt_mem_rmask), .spec_mem_wmask(spec_insn_slt_mem_wmask), .spec_mem_wdata(spec_insn_slt_mem_wdata) ); wire spec_insn_slti_valid; wire spec_insn_slti_trap; wire [ 4 : 0] spec_insn_slti_rs1_addr; wire [ 4 : 0] spec_insn_slti_rs2_addr; wire [ 4 : 0] spec_insn_slti_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; `endif rvfi_insn_slti insn_slti ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), `endif .spec_valid(spec_insn_slti_valid), .spec_trap(spec_insn_slti_trap), .spec_rs1_addr(spec_insn_slti_rs1_addr), .spec_rs2_addr(spec_insn_slti_rs2_addr), .spec_rd_addr(spec_insn_slti_rd_addr), .spec_rd_wdata(spec_insn_slti_rd_wdata), .spec_pc_wdata(spec_insn_slti_pc_wdata), .spec_mem_addr(spec_insn_slti_mem_addr), .spec_mem_rmask(spec_insn_slti_mem_rmask), .spec_mem_wmask(spec_insn_slti_mem_wmask), .spec_mem_wdata(spec_insn_slti_mem_wdata) ); wire spec_insn_sltiu_valid; wire spec_insn_sltiu_trap; wire [ 4 : 0] spec_insn_sltiu_rs1_addr; wire [ 4 : 0] spec_insn_sltiu_rs2_addr; wire [ 4 : 0] spec_insn_sltiu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; `endif rvfi_insn_sltiu insn_sltiu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltiu_valid), .spec_trap(spec_insn_sltiu_trap), .spec_rs1_addr(spec_insn_sltiu_rs1_addr), .spec_rs2_addr(spec_insn_sltiu_rs2_addr), .spec_rd_addr(spec_insn_sltiu_rd_addr), .spec_rd_wdata(spec_insn_sltiu_rd_wdata), .spec_pc_wdata(spec_insn_sltiu_pc_wdata), .spec_mem_addr(spec_insn_sltiu_mem_addr), .spec_mem_rmask(spec_insn_sltiu_mem_rmask), .spec_mem_wmask(spec_insn_sltiu_mem_wmask), .spec_mem_wdata(spec_insn_sltiu_mem_wdata) ); wire spec_insn_sltu_valid; wire spec_insn_sltu_trap; wire [ 4 : 0] spec_insn_sltu_rs1_addr; wire [ 4 : 0] spec_insn_sltu_rs2_addr; wire [ 4 : 0] spec_insn_sltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; `endif rvfi_insn_sltu insn_sltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltu_valid), .spec_trap(spec_insn_sltu_trap), .spec_rs1_addr(spec_insn_sltu_rs1_addr), .spec_rs2_addr(spec_insn_sltu_rs2_addr), .spec_rd_addr(spec_insn_sltu_rd_addr), .spec_rd_wdata(spec_insn_sltu_rd_wdata), .spec_pc_wdata(spec_insn_sltu_pc_wdata), .spec_mem_addr(spec_insn_sltu_mem_addr), .spec_mem_rmask(spec_insn_sltu_mem_rmask), .spec_mem_wmask(spec_insn_sltu_mem_wmask), .spec_mem_wdata(spec_insn_sltu_mem_wdata) ); wire spec_insn_sra_valid; wire spec_insn_sra_trap; wire [ 4 : 0] spec_insn_sra_rs1_addr; wire [ 4 : 0] spec_insn_sra_rs2_addr; wire [ 4 : 0] spec_insn_sra_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; `endif rvfi_insn_sra insn_sra ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), `endif .spec_valid(spec_insn_sra_valid), .spec_trap(spec_insn_sra_trap), .spec_rs1_addr(spec_insn_sra_rs1_addr), .spec_rs2_addr(spec_insn_sra_rs2_addr), .spec_rd_addr(spec_insn_sra_rd_addr), .spec_rd_wdata(spec_insn_sra_rd_wdata), .spec_pc_wdata(spec_insn_sra_pc_wdata), .spec_mem_addr(spec_insn_sra_mem_addr), .spec_mem_rmask(spec_insn_sra_mem_rmask), .spec_mem_wmask(spec_insn_sra_mem_wmask), .spec_mem_wdata(spec_insn_sra_mem_wdata) ); wire spec_insn_srai_valid; wire spec_insn_srai_trap; wire [ 4 : 0] spec_insn_srai_rs1_addr; wire [ 4 : 0] spec_insn_srai_rs2_addr; wire [ 4 : 0] spec_insn_srai_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; `endif rvfi_insn_srai insn_srai ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), `endif .spec_valid(spec_insn_srai_valid), .spec_trap(spec_insn_srai_trap), .spec_rs1_addr(spec_insn_srai_rs1_addr), .spec_rs2_addr(spec_insn_srai_rs2_addr), .spec_rd_addr(spec_insn_srai_rd_addr), .spec_rd_wdata(spec_insn_srai_rd_wdata), .spec_pc_wdata(spec_insn_srai_pc_wdata), .spec_mem_addr(spec_insn_srai_mem_addr), .spec_mem_rmask(spec_insn_srai_mem_rmask), .spec_mem_wmask(spec_insn_srai_mem_wmask), .spec_mem_wdata(spec_insn_srai_mem_wdata) ); wire spec_insn_srl_valid; wire spec_insn_srl_trap; wire [ 4 : 0] spec_insn_srl_rs1_addr; wire [ 4 : 0] spec_insn_srl_rs2_addr; wire [ 4 : 0] spec_insn_srl_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; `endif rvfi_insn_srl insn_srl ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), `endif .spec_valid(spec_insn_srl_valid), .spec_trap(spec_insn_srl_trap), .spec_rs1_addr(spec_insn_srl_rs1_addr), .spec_rs2_addr(spec_insn_srl_rs2_addr), .spec_rd_addr(spec_insn_srl_rd_addr), .spec_rd_wdata(spec_insn_srl_rd_wdata), .spec_pc_wdata(spec_insn_srl_pc_wdata), .spec_mem_addr(spec_insn_srl_mem_addr), .spec_mem_rmask(spec_insn_srl_mem_rmask), .spec_mem_wmask(spec_insn_srl_mem_wmask), .spec_mem_wdata(spec_insn_srl_mem_wdata) ); wire spec_insn_srli_valid; wire spec_insn_srli_trap; wire [ 4 : 0] spec_insn_srli_rs1_addr; wire [ 4 : 0] spec_insn_srli_rs2_addr; wire [ 4 : 0] spec_insn_srli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; `endif rvfi_insn_srli insn_srli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), `endif .spec_valid(spec_insn_srli_valid), .spec_trap(spec_insn_srli_trap), .spec_rs1_addr(spec_insn_srli_rs1_addr), .spec_rs2_addr(spec_insn_srli_rs2_addr), .spec_rd_addr(spec_insn_srli_rd_addr), .spec_rd_wdata(spec_insn_srli_rd_wdata), .spec_pc_wdata(spec_insn_srli_pc_wdata), .spec_mem_addr(spec_insn_srli_mem_addr), .spec_mem_rmask(spec_insn_srli_mem_rmask), .spec_mem_wmask(spec_insn_srli_mem_wmask), .spec_mem_wdata(spec_insn_srli_mem_wdata) ); wire spec_insn_sub_valid; wire spec_insn_sub_trap; wire [ 4 : 0] spec_insn_sub_rs1_addr; wire [ 4 : 0] spec_insn_sub_rs2_addr; wire [ 4 : 0] spec_insn_sub_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; `endif rvfi_insn_sub insn_sub ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), `endif .spec_valid(spec_insn_sub_valid), .spec_trap(spec_insn_sub_trap), .spec_rs1_addr(spec_insn_sub_rs1_addr), .spec_rs2_addr(spec_insn_sub_rs2_addr), .spec_rd_addr(spec_insn_sub_rd_addr), .spec_rd_wdata(spec_insn_sub_rd_wdata), .spec_pc_wdata(spec_insn_sub_pc_wdata), .spec_mem_addr(spec_insn_sub_mem_addr), .spec_mem_rmask(spec_insn_sub_mem_rmask), .spec_mem_wmask(spec_insn_sub_mem_wmask), .spec_mem_wdata(spec_insn_sub_mem_wdata) ); wire spec_insn_sw_valid; wire spec_insn_sw_trap; wire [ 4 : 0] spec_insn_sw_rs1_addr; wire [ 4 : 0] spec_insn_sw_rs2_addr; wire [ 4 : 0] spec_insn_sw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; `endif rvfi_insn_sw insn_sw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), `endif .spec_valid(spec_insn_sw_valid), .spec_trap(spec_insn_sw_trap), .spec_rs1_addr(spec_insn_sw_rs1_addr), .spec_rs2_addr(spec_insn_sw_rs2_addr), .spec_rd_addr(spec_insn_sw_rd_addr), .spec_rd_wdata(spec_insn_sw_rd_wdata), .spec_pc_wdata(spec_insn_sw_pc_wdata), .spec_mem_addr(spec_insn_sw_mem_addr), .spec_mem_rmask(spec_insn_sw_mem_rmask), .spec_mem_wmask(spec_insn_sw_mem_wmask), .spec_mem_wdata(spec_insn_sw_mem_wdata) ); wire spec_insn_xor_valid; wire spec_insn_xor_trap; wire [ 4 : 0] spec_insn_xor_rs1_addr; wire [ 4 : 0] spec_insn_xor_rs2_addr; wire [ 4 : 0] spec_insn_xor_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; `endif rvfi_insn_xor insn_xor ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), `endif .spec_valid(spec_insn_xor_valid), .spec_trap(spec_insn_xor_trap), .spec_rs1_addr(spec_insn_xor_rs1_addr), .spec_rs2_addr(spec_insn_xor_rs2_addr), .spec_rd_addr(spec_insn_xor_rd_addr), .spec_rd_wdata(spec_insn_xor_rd_wdata), .spec_pc_wdata(spec_insn_xor_pc_wdata), .spec_mem_addr(spec_insn_xor_mem_addr), .spec_mem_rmask(spec_insn_xor_mem_rmask), .spec_mem_wmask(spec_insn_xor_mem_wmask), .spec_mem_wdata(spec_insn_xor_mem_wdata) ); wire spec_insn_xori_valid; wire spec_insn_xori_trap; wire [ 4 : 0] spec_insn_xori_rs1_addr; wire [ 4 : 0] spec_insn_xori_rs2_addr; wire [ 4 : 0] spec_insn_xori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; `endif rvfi_insn_xori insn_xori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), `endif .spec_valid(spec_insn_xori_valid), .spec_trap(spec_insn_xori_trap), .spec_rs1_addr(spec_insn_xori_rs1_addr), .spec_rs2_addr(spec_insn_xori_rs2_addr), .spec_rd_addr(spec_insn_xori_rd_addr), .spec_rd_wdata(spec_insn_xori_rd_wdata), .spec_pc_wdata(spec_insn_xori_pc_wdata), .spec_mem_addr(spec_insn_xori_mem_addr), .spec_mem_rmask(spec_insn_xori_mem_rmask), .spec_mem_wmask(spec_insn_xori_mem_wmask), .spec_mem_wdata(spec_insn_xori_mem_wdata) ); assign spec_valid = spec_insn_add_valid ? spec_insn_add_valid : spec_insn_addi_valid ? spec_insn_addi_valid : spec_insn_and_valid ? spec_insn_and_valid : spec_insn_andi_valid ? spec_insn_andi_valid : spec_insn_auipc_valid ? spec_insn_auipc_valid : spec_insn_beq_valid ? spec_insn_beq_valid : spec_insn_bge_valid ? spec_insn_bge_valid : spec_insn_bgeu_valid ? spec_insn_bgeu_valid : spec_insn_blt_valid ? spec_insn_blt_valid : spec_insn_bltu_valid ? spec_insn_bltu_valid : spec_insn_bne_valid ? spec_insn_bne_valid : spec_insn_div_valid ? spec_insn_div_valid : spec_insn_divu_valid ? spec_insn_divu_valid : spec_insn_jal_valid ? spec_insn_jal_valid : spec_insn_jalr_valid ? spec_insn_jalr_valid : spec_insn_lb_valid ? spec_insn_lb_valid : spec_insn_lbu_valid ? spec_insn_lbu_valid : spec_insn_lh_valid ? spec_insn_lh_valid : spec_insn_lhu_valid ? spec_insn_lhu_valid : spec_insn_lui_valid ? spec_insn_lui_valid : spec_insn_lw_valid ? spec_insn_lw_valid : spec_insn_mul_valid ? spec_insn_mul_valid : spec_insn_mulh_valid ? spec_insn_mulh_valid : spec_insn_mulhsu_valid ? spec_insn_mulhsu_valid : spec_insn_mulhu_valid ? spec_insn_mulhu_valid : spec_insn_or_valid ? spec_insn_or_valid : spec_insn_ori_valid ? spec_insn_ori_valid : spec_insn_rem_valid ? spec_insn_rem_valid : spec_insn_remu_valid ? spec_insn_remu_valid : spec_insn_sb_valid ? spec_insn_sb_valid : spec_insn_sh_valid ? spec_insn_sh_valid : spec_insn_sll_valid ? spec_insn_sll_valid : spec_insn_slli_valid ? spec_insn_slli_valid : spec_insn_slt_valid ? spec_insn_slt_valid : spec_insn_slti_valid ? spec_insn_slti_valid : spec_insn_sltiu_valid ? spec_insn_sltiu_valid : spec_insn_sltu_valid ? spec_insn_sltu_valid : spec_insn_sra_valid ? spec_insn_sra_valid : spec_insn_srai_valid ? spec_insn_srai_valid : spec_insn_srl_valid ? spec_insn_srl_valid : spec_insn_srli_valid ? spec_insn_srli_valid : spec_insn_sub_valid ? spec_insn_sub_valid : spec_insn_sw_valid ? spec_insn_sw_valid : spec_insn_xor_valid ? spec_insn_xor_valid : spec_insn_xori_valid ? spec_insn_xori_valid : 0; assign spec_trap = spec_insn_add_valid ? spec_insn_add_trap : spec_insn_addi_valid ? spec_insn_addi_trap : spec_insn_and_valid ? spec_insn_and_trap : spec_insn_andi_valid ? spec_insn_andi_trap : spec_insn_auipc_valid ? spec_insn_auipc_trap : spec_insn_beq_valid ? spec_insn_beq_trap : spec_insn_bge_valid ? spec_insn_bge_trap : spec_insn_bgeu_valid ? spec_insn_bgeu_trap : spec_insn_blt_valid ? spec_insn_blt_trap : spec_insn_bltu_valid ? spec_insn_bltu_trap : spec_insn_bne_valid ? spec_insn_bne_trap : spec_insn_div_valid ? spec_insn_div_trap : spec_insn_divu_valid ? spec_insn_divu_trap : spec_insn_jal_valid ? spec_insn_jal_trap : spec_insn_jalr_valid ? spec_insn_jalr_trap : spec_insn_lb_valid ? spec_insn_lb_trap : spec_insn_lbu_valid ? spec_insn_lbu_trap : spec_insn_lh_valid ? spec_insn_lh_trap : spec_insn_lhu_valid ? spec_insn_lhu_trap : spec_insn_lui_valid ? spec_insn_lui_trap : spec_insn_lw_valid ? spec_insn_lw_trap : spec_insn_mul_valid ? spec_insn_mul_trap : spec_insn_mulh_valid ? spec_insn_mulh_trap : spec_insn_mulhsu_valid ? spec_insn_mulhsu_trap : spec_insn_mulhu_valid ? spec_insn_mulhu_trap : spec_insn_or_valid ? spec_insn_or_trap : spec_insn_ori_valid ? spec_insn_ori_trap : spec_insn_rem_valid ? spec_insn_rem_trap : spec_insn_remu_valid ? spec_insn_remu_trap : spec_insn_sb_valid ? spec_insn_sb_trap : spec_insn_sh_valid ? spec_insn_sh_trap : spec_insn_sll_valid ? spec_insn_sll_trap : spec_insn_slli_valid ? spec_insn_slli_trap : spec_insn_slt_valid ? spec_insn_slt_trap : spec_insn_slti_valid ? spec_insn_slti_trap : spec_insn_sltiu_valid ? spec_insn_sltiu_trap : spec_insn_sltu_valid ? spec_insn_sltu_trap : spec_insn_sra_valid ? spec_insn_sra_trap : spec_insn_srai_valid ? spec_insn_srai_trap : spec_insn_srl_valid ? spec_insn_srl_trap : spec_insn_srli_valid ? spec_insn_srli_trap : spec_insn_sub_valid ? spec_insn_sub_trap : spec_insn_sw_valid ? spec_insn_sw_trap : spec_insn_xor_valid ? spec_insn_xor_trap : spec_insn_xori_valid ? spec_insn_xori_trap : 0; assign spec_rs1_addr = spec_insn_add_valid ? spec_insn_add_rs1_addr : spec_insn_addi_valid ? spec_insn_addi_rs1_addr : spec_insn_and_valid ? spec_insn_and_rs1_addr : spec_insn_andi_valid ? spec_insn_andi_rs1_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : spec_insn_beq_valid ? spec_insn_beq_rs1_addr : spec_insn_bge_valid ? spec_insn_bge_rs1_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : spec_insn_blt_valid ? spec_insn_blt_rs1_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : spec_insn_bne_valid ? spec_insn_bne_rs1_addr : spec_insn_div_valid ? spec_insn_div_rs1_addr : spec_insn_divu_valid ? spec_insn_divu_rs1_addr : spec_insn_jal_valid ? spec_insn_jal_rs1_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : spec_insn_lb_valid ? spec_insn_lb_rs1_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : spec_insn_lh_valid ? spec_insn_lh_rs1_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : spec_insn_lui_valid ? spec_insn_lui_rs1_addr : spec_insn_lw_valid ? spec_insn_lw_rs1_addr : spec_insn_mul_valid ? spec_insn_mul_rs1_addr : spec_insn_mulh_valid ? spec_insn_mulh_rs1_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rs1_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_rs1_addr : spec_insn_or_valid ? spec_insn_or_rs1_addr : spec_insn_ori_valid ? spec_insn_ori_rs1_addr : spec_insn_rem_valid ? spec_insn_rem_rs1_addr : spec_insn_remu_valid ? spec_insn_remu_rs1_addr : spec_insn_sb_valid ? spec_insn_sb_rs1_addr : spec_insn_sh_valid ? spec_insn_sh_rs1_addr : spec_insn_sll_valid ? spec_insn_sll_rs1_addr : spec_insn_slli_valid ? spec_insn_slli_rs1_addr : spec_insn_slt_valid ? spec_insn_slt_rs1_addr : spec_insn_slti_valid ? spec_insn_slti_rs1_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : spec_insn_sra_valid ? spec_insn_sra_rs1_addr : spec_insn_srai_valid ? spec_insn_srai_rs1_addr : spec_insn_srl_valid ? spec_insn_srl_rs1_addr : spec_insn_srli_valid ? spec_insn_srli_rs1_addr : spec_insn_sub_valid ? spec_insn_sub_rs1_addr : spec_insn_sw_valid ? spec_insn_sw_rs1_addr : spec_insn_xor_valid ? spec_insn_xor_rs1_addr : spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; assign spec_rs2_addr = spec_insn_add_valid ? spec_insn_add_rs2_addr : spec_insn_addi_valid ? spec_insn_addi_rs2_addr : spec_insn_and_valid ? spec_insn_and_rs2_addr : spec_insn_andi_valid ? spec_insn_andi_rs2_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : spec_insn_beq_valid ? spec_insn_beq_rs2_addr : spec_insn_bge_valid ? spec_insn_bge_rs2_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : spec_insn_blt_valid ? spec_insn_blt_rs2_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : spec_insn_bne_valid ? spec_insn_bne_rs2_addr : spec_insn_div_valid ? spec_insn_div_rs2_addr : spec_insn_divu_valid ? spec_insn_divu_rs2_addr : spec_insn_jal_valid ? spec_insn_jal_rs2_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : spec_insn_lb_valid ? spec_insn_lb_rs2_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : spec_insn_lh_valid ? spec_insn_lh_rs2_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : spec_insn_lui_valid ? spec_insn_lui_rs2_addr : spec_insn_lw_valid ? spec_insn_lw_rs2_addr : spec_insn_mul_valid ? spec_insn_mul_rs2_addr : spec_insn_mulh_valid ? spec_insn_mulh_rs2_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rs2_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_rs2_addr : spec_insn_or_valid ? spec_insn_or_rs2_addr : spec_insn_ori_valid ? spec_insn_ori_rs2_addr : spec_insn_rem_valid ? spec_insn_rem_rs2_addr : spec_insn_remu_valid ? spec_insn_remu_rs2_addr : spec_insn_sb_valid ? spec_insn_sb_rs2_addr : spec_insn_sh_valid ? spec_insn_sh_rs2_addr : spec_insn_sll_valid ? spec_insn_sll_rs2_addr : spec_insn_slli_valid ? spec_insn_slli_rs2_addr : spec_insn_slt_valid ? spec_insn_slt_rs2_addr : spec_insn_slti_valid ? spec_insn_slti_rs2_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : spec_insn_sra_valid ? spec_insn_sra_rs2_addr : spec_insn_srai_valid ? spec_insn_srai_rs2_addr : spec_insn_srl_valid ? spec_insn_srl_rs2_addr : spec_insn_srli_valid ? spec_insn_srli_rs2_addr : spec_insn_sub_valid ? spec_insn_sub_rs2_addr : spec_insn_sw_valid ? spec_insn_sw_rs2_addr : spec_insn_xor_valid ? spec_insn_xor_rs2_addr : spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; assign spec_rd_addr = spec_insn_add_valid ? spec_insn_add_rd_addr : spec_insn_addi_valid ? spec_insn_addi_rd_addr : spec_insn_and_valid ? spec_insn_and_rd_addr : spec_insn_andi_valid ? spec_insn_andi_rd_addr : spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : spec_insn_beq_valid ? spec_insn_beq_rd_addr : spec_insn_bge_valid ? spec_insn_bge_rd_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : spec_insn_blt_valid ? spec_insn_blt_rd_addr : spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : spec_insn_bne_valid ? spec_insn_bne_rd_addr : spec_insn_div_valid ? spec_insn_div_rd_addr : spec_insn_divu_valid ? spec_insn_divu_rd_addr : spec_insn_jal_valid ? spec_insn_jal_rd_addr : spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : spec_insn_lb_valid ? spec_insn_lb_rd_addr : spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : spec_insn_lh_valid ? spec_insn_lh_rd_addr : spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : spec_insn_lui_valid ? spec_insn_lui_rd_addr : spec_insn_lw_valid ? spec_insn_lw_rd_addr : spec_insn_mul_valid ? spec_insn_mul_rd_addr : spec_insn_mulh_valid ? spec_insn_mulh_rd_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_rd_addr : spec_insn_or_valid ? spec_insn_or_rd_addr : spec_insn_ori_valid ? spec_insn_ori_rd_addr : spec_insn_rem_valid ? spec_insn_rem_rd_addr : spec_insn_remu_valid ? spec_insn_remu_rd_addr : spec_insn_sb_valid ? spec_insn_sb_rd_addr : spec_insn_sh_valid ? spec_insn_sh_rd_addr : spec_insn_sll_valid ? spec_insn_sll_rd_addr : spec_insn_slli_valid ? spec_insn_slli_rd_addr : spec_insn_slt_valid ? spec_insn_slt_rd_addr : spec_insn_slti_valid ? spec_insn_slti_rd_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : spec_insn_sra_valid ? spec_insn_sra_rd_addr : spec_insn_srai_valid ? spec_insn_srai_rd_addr : spec_insn_srl_valid ? spec_insn_srl_rd_addr : spec_insn_srli_valid ? spec_insn_srli_rd_addr : spec_insn_sub_valid ? spec_insn_sub_rd_addr : spec_insn_sw_valid ? spec_insn_sw_rd_addr : spec_insn_xor_valid ? spec_insn_xor_rd_addr : spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; assign spec_rd_wdata = spec_insn_add_valid ? spec_insn_add_rd_wdata : spec_insn_addi_valid ? spec_insn_addi_rd_wdata : spec_insn_and_valid ? spec_insn_and_rd_wdata : spec_insn_andi_valid ? spec_insn_andi_rd_wdata : spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : spec_insn_beq_valid ? spec_insn_beq_rd_wdata : spec_insn_bge_valid ? spec_insn_bge_rd_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : spec_insn_blt_valid ? spec_insn_blt_rd_wdata : spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : spec_insn_bne_valid ? spec_insn_bne_rd_wdata : spec_insn_div_valid ? spec_insn_div_rd_wdata : spec_insn_divu_valid ? spec_insn_divu_rd_wdata : spec_insn_jal_valid ? spec_insn_jal_rd_wdata : spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : spec_insn_lb_valid ? spec_insn_lb_rd_wdata : spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : spec_insn_lh_valid ? spec_insn_lh_rd_wdata : spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : spec_insn_lui_valid ? spec_insn_lui_rd_wdata : spec_insn_lw_valid ? spec_insn_lw_rd_wdata : spec_insn_mul_valid ? spec_insn_mul_rd_wdata : spec_insn_mulh_valid ? spec_insn_mulh_rd_wdata : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_wdata : spec_insn_mulhu_valid ? spec_insn_mulhu_rd_wdata : spec_insn_or_valid ? spec_insn_or_rd_wdata : spec_insn_ori_valid ? spec_insn_ori_rd_wdata : spec_insn_rem_valid ? spec_insn_rem_rd_wdata : spec_insn_remu_valid ? spec_insn_remu_rd_wdata : spec_insn_sb_valid ? spec_insn_sb_rd_wdata : spec_insn_sh_valid ? spec_insn_sh_rd_wdata : spec_insn_sll_valid ? spec_insn_sll_rd_wdata : spec_insn_slli_valid ? spec_insn_slli_rd_wdata : spec_insn_slt_valid ? spec_insn_slt_rd_wdata : spec_insn_slti_valid ? spec_insn_slti_rd_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : spec_insn_sra_valid ? spec_insn_sra_rd_wdata : spec_insn_srai_valid ? spec_insn_srai_rd_wdata : spec_insn_srl_valid ? spec_insn_srl_rd_wdata : spec_insn_srli_valid ? spec_insn_srli_rd_wdata : spec_insn_sub_valid ? spec_insn_sub_rd_wdata : spec_insn_sw_valid ? spec_insn_sw_rd_wdata : spec_insn_xor_valid ? spec_insn_xor_rd_wdata : spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; assign spec_pc_wdata = spec_insn_add_valid ? spec_insn_add_pc_wdata : spec_insn_addi_valid ? spec_insn_addi_pc_wdata : spec_insn_and_valid ? spec_insn_and_pc_wdata : spec_insn_andi_valid ? spec_insn_andi_pc_wdata : spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : spec_insn_beq_valid ? spec_insn_beq_pc_wdata : spec_insn_bge_valid ? spec_insn_bge_pc_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : spec_insn_blt_valid ? spec_insn_blt_pc_wdata : spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : spec_insn_bne_valid ? spec_insn_bne_pc_wdata : spec_insn_div_valid ? spec_insn_div_pc_wdata : spec_insn_divu_valid ? spec_insn_divu_pc_wdata : spec_insn_jal_valid ? spec_insn_jal_pc_wdata : spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : spec_insn_lb_valid ? spec_insn_lb_pc_wdata : spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : spec_insn_lh_valid ? spec_insn_lh_pc_wdata : spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : spec_insn_lui_valid ? spec_insn_lui_pc_wdata : spec_insn_lw_valid ? spec_insn_lw_pc_wdata : spec_insn_mul_valid ? spec_insn_mul_pc_wdata : spec_insn_mulh_valid ? spec_insn_mulh_pc_wdata : spec_insn_mulhsu_valid ? spec_insn_mulhsu_pc_wdata : spec_insn_mulhu_valid ? spec_insn_mulhu_pc_wdata : spec_insn_or_valid ? spec_insn_or_pc_wdata : spec_insn_ori_valid ? spec_insn_ori_pc_wdata : spec_insn_rem_valid ? spec_insn_rem_pc_wdata : spec_insn_remu_valid ? spec_insn_remu_pc_wdata : spec_insn_sb_valid ? spec_insn_sb_pc_wdata : spec_insn_sh_valid ? spec_insn_sh_pc_wdata : spec_insn_sll_valid ? spec_insn_sll_pc_wdata : spec_insn_slli_valid ? spec_insn_slli_pc_wdata : spec_insn_slt_valid ? spec_insn_slt_pc_wdata : spec_insn_slti_valid ? spec_insn_slti_pc_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : spec_insn_sra_valid ? spec_insn_sra_pc_wdata : spec_insn_srai_valid ? spec_insn_srai_pc_wdata : spec_insn_srl_valid ? spec_insn_srl_pc_wdata : spec_insn_srli_valid ? spec_insn_srli_pc_wdata : spec_insn_sub_valid ? spec_insn_sub_pc_wdata : spec_insn_sw_valid ? spec_insn_sw_pc_wdata : spec_insn_xor_valid ? spec_insn_xor_pc_wdata : spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; assign spec_mem_addr = spec_insn_add_valid ? spec_insn_add_mem_addr : spec_insn_addi_valid ? spec_insn_addi_mem_addr : spec_insn_and_valid ? spec_insn_and_mem_addr : spec_insn_andi_valid ? spec_insn_andi_mem_addr : spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : spec_insn_beq_valid ? spec_insn_beq_mem_addr : spec_insn_bge_valid ? spec_insn_bge_mem_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : spec_insn_blt_valid ? spec_insn_blt_mem_addr : spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : spec_insn_bne_valid ? spec_insn_bne_mem_addr : spec_insn_div_valid ? spec_insn_div_mem_addr : spec_insn_divu_valid ? spec_insn_divu_mem_addr : spec_insn_jal_valid ? spec_insn_jal_mem_addr : spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : spec_insn_lb_valid ? spec_insn_lb_mem_addr : spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : spec_insn_lh_valid ? spec_insn_lh_mem_addr : spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : spec_insn_lui_valid ? spec_insn_lui_mem_addr : spec_insn_lw_valid ? spec_insn_lw_mem_addr : spec_insn_mul_valid ? spec_insn_mul_mem_addr : spec_insn_mulh_valid ? spec_insn_mulh_mem_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_addr : spec_insn_or_valid ? spec_insn_or_mem_addr : spec_insn_ori_valid ? spec_insn_ori_mem_addr : spec_insn_rem_valid ? spec_insn_rem_mem_addr : spec_insn_remu_valid ? spec_insn_remu_mem_addr : spec_insn_sb_valid ? spec_insn_sb_mem_addr : spec_insn_sh_valid ? spec_insn_sh_mem_addr : spec_insn_sll_valid ? spec_insn_sll_mem_addr : spec_insn_slli_valid ? spec_insn_slli_mem_addr : spec_insn_slt_valid ? spec_insn_slt_mem_addr : spec_insn_slti_valid ? spec_insn_slti_mem_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : spec_insn_sra_valid ? spec_insn_sra_mem_addr : spec_insn_srai_valid ? spec_insn_srai_mem_addr : spec_insn_srl_valid ? spec_insn_srl_mem_addr : spec_insn_srli_valid ? spec_insn_srli_mem_addr : spec_insn_sub_valid ? spec_insn_sub_mem_addr : spec_insn_sw_valid ? spec_insn_sw_mem_addr : spec_insn_xor_valid ? spec_insn_xor_mem_addr : spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; assign spec_mem_rmask = spec_insn_add_valid ? spec_insn_add_mem_rmask : spec_insn_addi_valid ? spec_insn_addi_mem_rmask : spec_insn_and_valid ? spec_insn_and_mem_rmask : spec_insn_andi_valid ? spec_insn_andi_mem_rmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : spec_insn_beq_valid ? spec_insn_beq_mem_rmask : spec_insn_bge_valid ? spec_insn_bge_mem_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : spec_insn_blt_valid ? spec_insn_blt_mem_rmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : spec_insn_bne_valid ? spec_insn_bne_mem_rmask : spec_insn_div_valid ? spec_insn_div_mem_rmask : spec_insn_divu_valid ? spec_insn_divu_mem_rmask : spec_insn_jal_valid ? spec_insn_jal_mem_rmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : spec_insn_lb_valid ? spec_insn_lb_mem_rmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : spec_insn_lh_valid ? spec_insn_lh_mem_rmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : spec_insn_lui_valid ? spec_insn_lui_mem_rmask : spec_insn_lw_valid ? spec_insn_lw_mem_rmask : spec_insn_mul_valid ? spec_insn_mul_mem_rmask : spec_insn_mulh_valid ? spec_insn_mulh_mem_rmask : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_rmask : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_rmask : spec_insn_or_valid ? spec_insn_or_mem_rmask : spec_insn_ori_valid ? spec_insn_ori_mem_rmask : spec_insn_rem_valid ? spec_insn_rem_mem_rmask : spec_insn_remu_valid ? spec_insn_remu_mem_rmask : spec_insn_sb_valid ? spec_insn_sb_mem_rmask : spec_insn_sh_valid ? spec_insn_sh_mem_rmask : spec_insn_sll_valid ? spec_insn_sll_mem_rmask : spec_insn_slli_valid ? spec_insn_slli_mem_rmask : spec_insn_slt_valid ? spec_insn_slt_mem_rmask : spec_insn_slti_valid ? spec_insn_slti_mem_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : spec_insn_sra_valid ? spec_insn_sra_mem_rmask : spec_insn_srai_valid ? spec_insn_srai_mem_rmask : spec_insn_srl_valid ? spec_insn_srl_mem_rmask : spec_insn_srli_valid ? spec_insn_srli_mem_rmask : spec_insn_sub_valid ? spec_insn_sub_mem_rmask : spec_insn_sw_valid ? spec_insn_sw_mem_rmask : spec_insn_xor_valid ? spec_insn_xor_mem_rmask : spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; assign spec_mem_wmask = spec_insn_add_valid ? spec_insn_add_mem_wmask : spec_insn_addi_valid ? spec_insn_addi_mem_wmask : spec_insn_and_valid ? spec_insn_and_mem_wmask : spec_insn_andi_valid ? spec_insn_andi_mem_wmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : spec_insn_beq_valid ? spec_insn_beq_mem_wmask : spec_insn_bge_valid ? spec_insn_bge_mem_wmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : spec_insn_blt_valid ? spec_insn_blt_mem_wmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : spec_insn_bne_valid ? spec_insn_bne_mem_wmask : spec_insn_div_valid ? spec_insn_div_mem_wmask : spec_insn_divu_valid ? spec_insn_divu_mem_wmask : spec_insn_jal_valid ? spec_insn_jal_mem_wmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : spec_insn_lb_valid ? spec_insn_lb_mem_wmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : spec_insn_lh_valid ? spec_insn_lh_mem_wmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : spec_insn_lui_valid ? spec_insn_lui_mem_wmask : spec_insn_lw_valid ? spec_insn_lw_mem_wmask : spec_insn_mul_valid ? spec_insn_mul_mem_wmask : spec_insn_mulh_valid ? spec_insn_mulh_mem_wmask : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wmask : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_wmask : spec_insn_or_valid ? spec_insn_or_mem_wmask : spec_insn_ori_valid ? spec_insn_ori_mem_wmask : spec_insn_rem_valid ? spec_insn_rem_mem_wmask : spec_insn_remu_valid ? spec_insn_remu_mem_wmask : spec_insn_sb_valid ? spec_insn_sb_mem_wmask : spec_insn_sh_valid ? spec_insn_sh_mem_wmask : spec_insn_sll_valid ? spec_insn_sll_mem_wmask : spec_insn_slli_valid ? spec_insn_slli_mem_wmask : spec_insn_slt_valid ? spec_insn_slt_mem_wmask : spec_insn_slti_valid ? spec_insn_slti_mem_wmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : spec_insn_sra_valid ? spec_insn_sra_mem_wmask : spec_insn_srai_valid ? spec_insn_srai_mem_wmask : spec_insn_srl_valid ? spec_insn_srl_mem_wmask : spec_insn_srli_valid ? spec_insn_srli_mem_wmask : spec_insn_sub_valid ? spec_insn_sub_mem_wmask : spec_insn_sw_valid ? spec_insn_sw_mem_wmask : spec_insn_xor_valid ? spec_insn_xor_mem_wmask : spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; assign spec_mem_wdata = spec_insn_add_valid ? spec_insn_add_mem_wdata : spec_insn_addi_valid ? spec_insn_addi_mem_wdata : spec_insn_and_valid ? spec_insn_and_mem_wdata : spec_insn_andi_valid ? spec_insn_andi_mem_wdata : spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : spec_insn_beq_valid ? spec_insn_beq_mem_wdata : spec_insn_bge_valid ? spec_insn_bge_mem_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : spec_insn_blt_valid ? spec_insn_blt_mem_wdata : spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : spec_insn_bne_valid ? spec_insn_bne_mem_wdata : spec_insn_div_valid ? spec_insn_div_mem_wdata : spec_insn_divu_valid ? spec_insn_divu_mem_wdata : spec_insn_jal_valid ? spec_insn_jal_mem_wdata : spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : spec_insn_lb_valid ? spec_insn_lb_mem_wdata : spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : spec_insn_lh_valid ? spec_insn_lh_mem_wdata : spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : spec_insn_lui_valid ? spec_insn_lui_mem_wdata : spec_insn_lw_valid ? spec_insn_lw_mem_wdata : spec_insn_mul_valid ? spec_insn_mul_mem_wdata : spec_insn_mulh_valid ? spec_insn_mulh_mem_wdata : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wdata : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_wdata : spec_insn_or_valid ? spec_insn_or_mem_wdata : spec_insn_ori_valid ? spec_insn_ori_mem_wdata : spec_insn_rem_valid ? spec_insn_rem_mem_wdata : spec_insn_remu_valid ? spec_insn_remu_mem_wdata : spec_insn_sb_valid ? spec_insn_sb_mem_wdata : spec_insn_sh_valid ? spec_insn_sh_mem_wdata : spec_insn_sll_valid ? spec_insn_sll_mem_wdata : spec_insn_slli_valid ? spec_insn_slli_mem_wdata : spec_insn_slt_valid ? spec_insn_slt_mem_wdata : spec_insn_slti_valid ? spec_insn_slti_mem_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : spec_insn_sra_valid ? spec_insn_sra_mem_wdata : spec_insn_srai_valid ? spec_insn_srai_mem_wdata : spec_insn_srl_valid ? spec_insn_srl_mem_wdata : spec_insn_srli_valid ? spec_insn_srli_mem_wdata : spec_insn_sub_valid ? spec_insn_sub_mem_wdata : spec_insn_sw_valid ? spec_insn_sw_mem_wdata : spec_insn_xor_valid ? spec_insn_xor_mem_wdata : spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; `ifdef RISCV_FORMAL_CSR_MISA assign spec_csr_misa_rmask = spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : spec_insn_div_valid ? spec_insn_div_csr_misa_rmask : spec_insn_divu_valid ? spec_insn_divu_csr_misa_rmask : spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : spec_insn_mul_valid ? spec_insn_mul_csr_misa_rmask : spec_insn_mulh_valid ? spec_insn_mulh_csr_misa_rmask : spec_insn_mulhsu_valid ? spec_insn_mulhsu_csr_misa_rmask : spec_insn_mulhu_valid ? spec_insn_mulhu_csr_misa_rmask : spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : spec_insn_rem_valid ? spec_insn_rem_csr_misa_rmask : spec_insn_remu_valid ? spec_insn_remu_csr_misa_rmask : spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; `endif endmodule ================================================ FILE: insns/isa_rv32imc.txt ================================================ add addi and andi auipc beq bge bgeu blt bltu bne c_add c_addi c_addi16sp c_addi4spn c_and c_andi c_beqz c_bnez c_j c_jal c_jalr c_jr c_li c_lui c_lw c_lwsp c_mv c_or c_slli c_srai c_srli c_sub c_sw c_swsp c_xor div divu jal jalr lb lbu lh lhu lui lw mul mulh mulhsu mulhu or ori rem remu sb sh sll slli slt slti sltiu sltu sra srai srl srli sub sw xor xori ================================================ FILE: insns/isa_rv32imc.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_isa_rv32imc ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); wire spec_insn_add_valid; wire spec_insn_add_trap; wire [ 4 : 0] spec_insn_add_rs1_addr; wire [ 4 : 0] spec_insn_add_rs2_addr; wire [ 4 : 0] spec_insn_add_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; `endif rvfi_insn_add insn_add ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), `endif .spec_valid(spec_insn_add_valid), .spec_trap(spec_insn_add_trap), .spec_rs1_addr(spec_insn_add_rs1_addr), .spec_rs2_addr(spec_insn_add_rs2_addr), .spec_rd_addr(spec_insn_add_rd_addr), .spec_rd_wdata(spec_insn_add_rd_wdata), .spec_pc_wdata(spec_insn_add_pc_wdata), .spec_mem_addr(spec_insn_add_mem_addr), .spec_mem_rmask(spec_insn_add_mem_rmask), .spec_mem_wmask(spec_insn_add_mem_wmask), .spec_mem_wdata(spec_insn_add_mem_wdata) ); wire spec_insn_addi_valid; wire spec_insn_addi_trap; wire [ 4 : 0] spec_insn_addi_rs1_addr; wire [ 4 : 0] spec_insn_addi_rs2_addr; wire [ 4 : 0] spec_insn_addi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; `endif rvfi_insn_addi insn_addi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), `endif .spec_valid(spec_insn_addi_valid), .spec_trap(spec_insn_addi_trap), .spec_rs1_addr(spec_insn_addi_rs1_addr), .spec_rs2_addr(spec_insn_addi_rs2_addr), .spec_rd_addr(spec_insn_addi_rd_addr), .spec_rd_wdata(spec_insn_addi_rd_wdata), .spec_pc_wdata(spec_insn_addi_pc_wdata), .spec_mem_addr(spec_insn_addi_mem_addr), .spec_mem_rmask(spec_insn_addi_mem_rmask), .spec_mem_wmask(spec_insn_addi_mem_wmask), .spec_mem_wdata(spec_insn_addi_mem_wdata) ); wire spec_insn_and_valid; wire spec_insn_and_trap; wire [ 4 : 0] spec_insn_and_rs1_addr; wire [ 4 : 0] spec_insn_and_rs2_addr; wire [ 4 : 0] spec_insn_and_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; `endif rvfi_insn_and insn_and ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), `endif .spec_valid(spec_insn_and_valid), .spec_trap(spec_insn_and_trap), .spec_rs1_addr(spec_insn_and_rs1_addr), .spec_rs2_addr(spec_insn_and_rs2_addr), .spec_rd_addr(spec_insn_and_rd_addr), .spec_rd_wdata(spec_insn_and_rd_wdata), .spec_pc_wdata(spec_insn_and_pc_wdata), .spec_mem_addr(spec_insn_and_mem_addr), .spec_mem_rmask(spec_insn_and_mem_rmask), .spec_mem_wmask(spec_insn_and_mem_wmask), .spec_mem_wdata(spec_insn_and_mem_wdata) ); wire spec_insn_andi_valid; wire spec_insn_andi_trap; wire [ 4 : 0] spec_insn_andi_rs1_addr; wire [ 4 : 0] spec_insn_andi_rs2_addr; wire [ 4 : 0] spec_insn_andi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; `endif rvfi_insn_andi insn_andi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), `endif .spec_valid(spec_insn_andi_valid), .spec_trap(spec_insn_andi_trap), .spec_rs1_addr(spec_insn_andi_rs1_addr), .spec_rs2_addr(spec_insn_andi_rs2_addr), .spec_rd_addr(spec_insn_andi_rd_addr), .spec_rd_wdata(spec_insn_andi_rd_wdata), .spec_pc_wdata(spec_insn_andi_pc_wdata), .spec_mem_addr(spec_insn_andi_mem_addr), .spec_mem_rmask(spec_insn_andi_mem_rmask), .spec_mem_wmask(spec_insn_andi_mem_wmask), .spec_mem_wdata(spec_insn_andi_mem_wdata) ); wire spec_insn_auipc_valid; wire spec_insn_auipc_trap; wire [ 4 : 0] spec_insn_auipc_rs1_addr; wire [ 4 : 0] spec_insn_auipc_rs2_addr; wire [ 4 : 0] spec_insn_auipc_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; `endif rvfi_insn_auipc insn_auipc ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), `endif .spec_valid(spec_insn_auipc_valid), .spec_trap(spec_insn_auipc_trap), .spec_rs1_addr(spec_insn_auipc_rs1_addr), .spec_rs2_addr(spec_insn_auipc_rs2_addr), .spec_rd_addr(spec_insn_auipc_rd_addr), .spec_rd_wdata(spec_insn_auipc_rd_wdata), .spec_pc_wdata(spec_insn_auipc_pc_wdata), .spec_mem_addr(spec_insn_auipc_mem_addr), .spec_mem_rmask(spec_insn_auipc_mem_rmask), .spec_mem_wmask(spec_insn_auipc_mem_wmask), .spec_mem_wdata(spec_insn_auipc_mem_wdata) ); wire spec_insn_beq_valid; wire spec_insn_beq_trap; wire [ 4 : 0] spec_insn_beq_rs1_addr; wire [ 4 : 0] spec_insn_beq_rs2_addr; wire [ 4 : 0] spec_insn_beq_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; `endif rvfi_insn_beq insn_beq ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), `endif .spec_valid(spec_insn_beq_valid), .spec_trap(spec_insn_beq_trap), .spec_rs1_addr(spec_insn_beq_rs1_addr), .spec_rs2_addr(spec_insn_beq_rs2_addr), .spec_rd_addr(spec_insn_beq_rd_addr), .spec_rd_wdata(spec_insn_beq_rd_wdata), .spec_pc_wdata(spec_insn_beq_pc_wdata), .spec_mem_addr(spec_insn_beq_mem_addr), .spec_mem_rmask(spec_insn_beq_mem_rmask), .spec_mem_wmask(spec_insn_beq_mem_wmask), .spec_mem_wdata(spec_insn_beq_mem_wdata) ); wire spec_insn_bge_valid; wire spec_insn_bge_trap; wire [ 4 : 0] spec_insn_bge_rs1_addr; wire [ 4 : 0] spec_insn_bge_rs2_addr; wire [ 4 : 0] spec_insn_bge_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; `endif rvfi_insn_bge insn_bge ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), `endif .spec_valid(spec_insn_bge_valid), .spec_trap(spec_insn_bge_trap), .spec_rs1_addr(spec_insn_bge_rs1_addr), .spec_rs2_addr(spec_insn_bge_rs2_addr), .spec_rd_addr(spec_insn_bge_rd_addr), .spec_rd_wdata(spec_insn_bge_rd_wdata), .spec_pc_wdata(spec_insn_bge_pc_wdata), .spec_mem_addr(spec_insn_bge_mem_addr), .spec_mem_rmask(spec_insn_bge_mem_rmask), .spec_mem_wmask(spec_insn_bge_mem_wmask), .spec_mem_wdata(spec_insn_bge_mem_wdata) ); wire spec_insn_bgeu_valid; wire spec_insn_bgeu_trap; wire [ 4 : 0] spec_insn_bgeu_rs1_addr; wire [ 4 : 0] spec_insn_bgeu_rs2_addr; wire [ 4 : 0] spec_insn_bgeu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; `endif rvfi_insn_bgeu insn_bgeu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), `endif .spec_valid(spec_insn_bgeu_valid), .spec_trap(spec_insn_bgeu_trap), .spec_rs1_addr(spec_insn_bgeu_rs1_addr), .spec_rs2_addr(spec_insn_bgeu_rs2_addr), .spec_rd_addr(spec_insn_bgeu_rd_addr), .spec_rd_wdata(spec_insn_bgeu_rd_wdata), .spec_pc_wdata(spec_insn_bgeu_pc_wdata), .spec_mem_addr(spec_insn_bgeu_mem_addr), .spec_mem_rmask(spec_insn_bgeu_mem_rmask), .spec_mem_wmask(spec_insn_bgeu_mem_wmask), .spec_mem_wdata(spec_insn_bgeu_mem_wdata) ); wire spec_insn_blt_valid; wire spec_insn_blt_trap; wire [ 4 : 0] spec_insn_blt_rs1_addr; wire [ 4 : 0] spec_insn_blt_rs2_addr; wire [ 4 : 0] spec_insn_blt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; `endif rvfi_insn_blt insn_blt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), `endif .spec_valid(spec_insn_blt_valid), .spec_trap(spec_insn_blt_trap), .spec_rs1_addr(spec_insn_blt_rs1_addr), .spec_rs2_addr(spec_insn_blt_rs2_addr), .spec_rd_addr(spec_insn_blt_rd_addr), .spec_rd_wdata(spec_insn_blt_rd_wdata), .spec_pc_wdata(spec_insn_blt_pc_wdata), .spec_mem_addr(spec_insn_blt_mem_addr), .spec_mem_rmask(spec_insn_blt_mem_rmask), .spec_mem_wmask(spec_insn_blt_mem_wmask), .spec_mem_wdata(spec_insn_blt_mem_wdata) ); wire spec_insn_bltu_valid; wire spec_insn_bltu_trap; wire [ 4 : 0] spec_insn_bltu_rs1_addr; wire [ 4 : 0] spec_insn_bltu_rs2_addr; wire [ 4 : 0] spec_insn_bltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; `endif rvfi_insn_bltu insn_bltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), `endif .spec_valid(spec_insn_bltu_valid), .spec_trap(spec_insn_bltu_trap), .spec_rs1_addr(spec_insn_bltu_rs1_addr), .spec_rs2_addr(spec_insn_bltu_rs2_addr), .spec_rd_addr(spec_insn_bltu_rd_addr), .spec_rd_wdata(spec_insn_bltu_rd_wdata), .spec_pc_wdata(spec_insn_bltu_pc_wdata), .spec_mem_addr(spec_insn_bltu_mem_addr), .spec_mem_rmask(spec_insn_bltu_mem_rmask), .spec_mem_wmask(spec_insn_bltu_mem_wmask), .spec_mem_wdata(spec_insn_bltu_mem_wdata) ); wire spec_insn_bne_valid; wire spec_insn_bne_trap; wire [ 4 : 0] spec_insn_bne_rs1_addr; wire [ 4 : 0] spec_insn_bne_rs2_addr; wire [ 4 : 0] spec_insn_bne_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; `endif rvfi_insn_bne insn_bne ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), `endif .spec_valid(spec_insn_bne_valid), .spec_trap(spec_insn_bne_trap), .spec_rs1_addr(spec_insn_bne_rs1_addr), .spec_rs2_addr(spec_insn_bne_rs2_addr), .spec_rd_addr(spec_insn_bne_rd_addr), .spec_rd_wdata(spec_insn_bne_rd_wdata), .spec_pc_wdata(spec_insn_bne_pc_wdata), .spec_mem_addr(spec_insn_bne_mem_addr), .spec_mem_rmask(spec_insn_bne_mem_rmask), .spec_mem_wmask(spec_insn_bne_mem_wmask), .spec_mem_wdata(spec_insn_bne_mem_wdata) ); wire spec_insn_c_add_valid; wire spec_insn_c_add_trap; wire [ 4 : 0] spec_insn_c_add_rs1_addr; wire [ 4 : 0] spec_insn_c_add_rs2_addr; wire [ 4 : 0] spec_insn_c_add_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_csr_misa_rmask; `endif rvfi_insn_c_add insn_c_add ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_add_csr_misa_rmask), `endif .spec_valid(spec_insn_c_add_valid), .spec_trap(spec_insn_c_add_trap), .spec_rs1_addr(spec_insn_c_add_rs1_addr), .spec_rs2_addr(spec_insn_c_add_rs2_addr), .spec_rd_addr(spec_insn_c_add_rd_addr), .spec_rd_wdata(spec_insn_c_add_rd_wdata), .spec_pc_wdata(spec_insn_c_add_pc_wdata), .spec_mem_addr(spec_insn_c_add_mem_addr), .spec_mem_rmask(spec_insn_c_add_mem_rmask), .spec_mem_wmask(spec_insn_c_add_mem_wmask), .spec_mem_wdata(spec_insn_c_add_mem_wdata) ); wire spec_insn_c_addi_valid; wire spec_insn_c_addi_trap; wire [ 4 : 0] spec_insn_c_addi_rs1_addr; wire [ 4 : 0] spec_insn_c_addi_rs2_addr; wire [ 4 : 0] spec_insn_c_addi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_csr_misa_rmask; `endif rvfi_insn_c_addi insn_c_addi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addi_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addi_valid), .spec_trap(spec_insn_c_addi_trap), .spec_rs1_addr(spec_insn_c_addi_rs1_addr), .spec_rs2_addr(spec_insn_c_addi_rs2_addr), .spec_rd_addr(spec_insn_c_addi_rd_addr), .spec_rd_wdata(spec_insn_c_addi_rd_wdata), .spec_pc_wdata(spec_insn_c_addi_pc_wdata), .spec_mem_addr(spec_insn_c_addi_mem_addr), .spec_mem_rmask(spec_insn_c_addi_mem_rmask), .spec_mem_wmask(spec_insn_c_addi_mem_wmask), .spec_mem_wdata(spec_insn_c_addi_mem_wdata) ); wire spec_insn_c_addi16sp_valid; wire spec_insn_c_addi16sp_trap; wire [ 4 : 0] spec_insn_c_addi16sp_rs1_addr; wire [ 4 : 0] spec_insn_c_addi16sp_rs2_addr; wire [ 4 : 0] spec_insn_c_addi16sp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_csr_misa_rmask; `endif rvfi_insn_c_addi16sp insn_c_addi16sp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addi16sp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addi16sp_valid), .spec_trap(spec_insn_c_addi16sp_trap), .spec_rs1_addr(spec_insn_c_addi16sp_rs1_addr), .spec_rs2_addr(spec_insn_c_addi16sp_rs2_addr), .spec_rd_addr(spec_insn_c_addi16sp_rd_addr), .spec_rd_wdata(spec_insn_c_addi16sp_rd_wdata), .spec_pc_wdata(spec_insn_c_addi16sp_pc_wdata), .spec_mem_addr(spec_insn_c_addi16sp_mem_addr), .spec_mem_rmask(spec_insn_c_addi16sp_mem_rmask), .spec_mem_wmask(spec_insn_c_addi16sp_mem_wmask), .spec_mem_wdata(spec_insn_c_addi16sp_mem_wdata) ); wire spec_insn_c_addi4spn_valid; wire spec_insn_c_addi4spn_trap; wire [ 4 : 0] spec_insn_c_addi4spn_rs1_addr; wire [ 4 : 0] spec_insn_c_addi4spn_rs2_addr; wire [ 4 : 0] spec_insn_c_addi4spn_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_csr_misa_rmask; `endif rvfi_insn_c_addi4spn insn_c_addi4spn ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addi4spn_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addi4spn_valid), .spec_trap(spec_insn_c_addi4spn_trap), .spec_rs1_addr(spec_insn_c_addi4spn_rs1_addr), .spec_rs2_addr(spec_insn_c_addi4spn_rs2_addr), .spec_rd_addr(spec_insn_c_addi4spn_rd_addr), .spec_rd_wdata(spec_insn_c_addi4spn_rd_wdata), .spec_pc_wdata(spec_insn_c_addi4spn_pc_wdata), .spec_mem_addr(spec_insn_c_addi4spn_mem_addr), .spec_mem_rmask(spec_insn_c_addi4spn_mem_rmask), .spec_mem_wmask(spec_insn_c_addi4spn_mem_wmask), .spec_mem_wdata(spec_insn_c_addi4spn_mem_wdata) ); wire spec_insn_c_and_valid; wire spec_insn_c_and_trap; wire [ 4 : 0] spec_insn_c_and_rs1_addr; wire [ 4 : 0] spec_insn_c_and_rs2_addr; wire [ 4 : 0] spec_insn_c_and_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_csr_misa_rmask; `endif rvfi_insn_c_and insn_c_and ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_and_csr_misa_rmask), `endif .spec_valid(spec_insn_c_and_valid), .spec_trap(spec_insn_c_and_trap), .spec_rs1_addr(spec_insn_c_and_rs1_addr), .spec_rs2_addr(spec_insn_c_and_rs2_addr), .spec_rd_addr(spec_insn_c_and_rd_addr), .spec_rd_wdata(spec_insn_c_and_rd_wdata), .spec_pc_wdata(spec_insn_c_and_pc_wdata), .spec_mem_addr(spec_insn_c_and_mem_addr), .spec_mem_rmask(spec_insn_c_and_mem_rmask), .spec_mem_wmask(spec_insn_c_and_mem_wmask), .spec_mem_wdata(spec_insn_c_and_mem_wdata) ); wire spec_insn_c_andi_valid; wire spec_insn_c_andi_trap; wire [ 4 : 0] spec_insn_c_andi_rs1_addr; wire [ 4 : 0] spec_insn_c_andi_rs2_addr; wire [ 4 : 0] spec_insn_c_andi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_csr_misa_rmask; `endif rvfi_insn_c_andi insn_c_andi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_andi_csr_misa_rmask), `endif .spec_valid(spec_insn_c_andi_valid), .spec_trap(spec_insn_c_andi_trap), .spec_rs1_addr(spec_insn_c_andi_rs1_addr), .spec_rs2_addr(spec_insn_c_andi_rs2_addr), .spec_rd_addr(spec_insn_c_andi_rd_addr), .spec_rd_wdata(spec_insn_c_andi_rd_wdata), .spec_pc_wdata(spec_insn_c_andi_pc_wdata), .spec_mem_addr(spec_insn_c_andi_mem_addr), .spec_mem_rmask(spec_insn_c_andi_mem_rmask), .spec_mem_wmask(spec_insn_c_andi_mem_wmask), .spec_mem_wdata(spec_insn_c_andi_mem_wdata) ); wire spec_insn_c_beqz_valid; wire spec_insn_c_beqz_trap; wire [ 4 : 0] spec_insn_c_beqz_rs1_addr; wire [ 4 : 0] spec_insn_c_beqz_rs2_addr; wire [ 4 : 0] spec_insn_c_beqz_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_csr_misa_rmask; `endif rvfi_insn_c_beqz insn_c_beqz ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_beqz_csr_misa_rmask), `endif .spec_valid(spec_insn_c_beqz_valid), .spec_trap(spec_insn_c_beqz_trap), .spec_rs1_addr(spec_insn_c_beqz_rs1_addr), .spec_rs2_addr(spec_insn_c_beqz_rs2_addr), .spec_rd_addr(spec_insn_c_beqz_rd_addr), .spec_rd_wdata(spec_insn_c_beqz_rd_wdata), .spec_pc_wdata(spec_insn_c_beqz_pc_wdata), .spec_mem_addr(spec_insn_c_beqz_mem_addr), .spec_mem_rmask(spec_insn_c_beqz_mem_rmask), .spec_mem_wmask(spec_insn_c_beqz_mem_wmask), .spec_mem_wdata(spec_insn_c_beqz_mem_wdata) ); wire spec_insn_c_bnez_valid; wire spec_insn_c_bnez_trap; wire [ 4 : 0] spec_insn_c_bnez_rs1_addr; wire [ 4 : 0] spec_insn_c_bnez_rs2_addr; wire [ 4 : 0] spec_insn_c_bnez_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_csr_misa_rmask; `endif rvfi_insn_c_bnez insn_c_bnez ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_bnez_csr_misa_rmask), `endif .spec_valid(spec_insn_c_bnez_valid), .spec_trap(spec_insn_c_bnez_trap), .spec_rs1_addr(spec_insn_c_bnez_rs1_addr), .spec_rs2_addr(spec_insn_c_bnez_rs2_addr), .spec_rd_addr(spec_insn_c_bnez_rd_addr), .spec_rd_wdata(spec_insn_c_bnez_rd_wdata), .spec_pc_wdata(spec_insn_c_bnez_pc_wdata), .spec_mem_addr(spec_insn_c_bnez_mem_addr), .spec_mem_rmask(spec_insn_c_bnez_mem_rmask), .spec_mem_wmask(spec_insn_c_bnez_mem_wmask), .spec_mem_wdata(spec_insn_c_bnez_mem_wdata) ); wire spec_insn_c_j_valid; wire spec_insn_c_j_trap; wire [ 4 : 0] spec_insn_c_j_rs1_addr; wire [ 4 : 0] spec_insn_c_j_rs2_addr; wire [ 4 : 0] spec_insn_c_j_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_csr_misa_rmask; `endif rvfi_insn_c_j insn_c_j ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_j_csr_misa_rmask), `endif .spec_valid(spec_insn_c_j_valid), .spec_trap(spec_insn_c_j_trap), .spec_rs1_addr(spec_insn_c_j_rs1_addr), .spec_rs2_addr(spec_insn_c_j_rs2_addr), .spec_rd_addr(spec_insn_c_j_rd_addr), .spec_rd_wdata(spec_insn_c_j_rd_wdata), .spec_pc_wdata(spec_insn_c_j_pc_wdata), .spec_mem_addr(spec_insn_c_j_mem_addr), .spec_mem_rmask(spec_insn_c_j_mem_rmask), .spec_mem_wmask(spec_insn_c_j_mem_wmask), .spec_mem_wdata(spec_insn_c_j_mem_wdata) ); wire spec_insn_c_jal_valid; wire spec_insn_c_jal_trap; wire [ 4 : 0] spec_insn_c_jal_rs1_addr; wire [ 4 : 0] spec_insn_c_jal_rs2_addr; wire [ 4 : 0] spec_insn_c_jal_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jal_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jal_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jal_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jal_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jal_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jal_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jal_csr_misa_rmask; `endif rvfi_insn_c_jal insn_c_jal ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_jal_csr_misa_rmask), `endif .spec_valid(spec_insn_c_jal_valid), .spec_trap(spec_insn_c_jal_trap), .spec_rs1_addr(spec_insn_c_jal_rs1_addr), .spec_rs2_addr(spec_insn_c_jal_rs2_addr), .spec_rd_addr(spec_insn_c_jal_rd_addr), .spec_rd_wdata(spec_insn_c_jal_rd_wdata), .spec_pc_wdata(spec_insn_c_jal_pc_wdata), .spec_mem_addr(spec_insn_c_jal_mem_addr), .spec_mem_rmask(spec_insn_c_jal_mem_rmask), .spec_mem_wmask(spec_insn_c_jal_mem_wmask), .spec_mem_wdata(spec_insn_c_jal_mem_wdata) ); wire spec_insn_c_jalr_valid; wire spec_insn_c_jalr_trap; wire [ 4 : 0] spec_insn_c_jalr_rs1_addr; wire [ 4 : 0] spec_insn_c_jalr_rs2_addr; wire [ 4 : 0] spec_insn_c_jalr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_csr_misa_rmask; `endif rvfi_insn_c_jalr insn_c_jalr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_jalr_csr_misa_rmask), `endif .spec_valid(spec_insn_c_jalr_valid), .spec_trap(spec_insn_c_jalr_trap), .spec_rs1_addr(spec_insn_c_jalr_rs1_addr), .spec_rs2_addr(spec_insn_c_jalr_rs2_addr), .spec_rd_addr(spec_insn_c_jalr_rd_addr), .spec_rd_wdata(spec_insn_c_jalr_rd_wdata), .spec_pc_wdata(spec_insn_c_jalr_pc_wdata), .spec_mem_addr(spec_insn_c_jalr_mem_addr), .spec_mem_rmask(spec_insn_c_jalr_mem_rmask), .spec_mem_wmask(spec_insn_c_jalr_mem_wmask), .spec_mem_wdata(spec_insn_c_jalr_mem_wdata) ); wire spec_insn_c_jr_valid; wire spec_insn_c_jr_trap; wire [ 4 : 0] spec_insn_c_jr_rs1_addr; wire [ 4 : 0] spec_insn_c_jr_rs2_addr; wire [ 4 : 0] spec_insn_c_jr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_csr_misa_rmask; `endif rvfi_insn_c_jr insn_c_jr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_jr_csr_misa_rmask), `endif .spec_valid(spec_insn_c_jr_valid), .spec_trap(spec_insn_c_jr_trap), .spec_rs1_addr(spec_insn_c_jr_rs1_addr), .spec_rs2_addr(spec_insn_c_jr_rs2_addr), .spec_rd_addr(spec_insn_c_jr_rd_addr), .spec_rd_wdata(spec_insn_c_jr_rd_wdata), .spec_pc_wdata(spec_insn_c_jr_pc_wdata), .spec_mem_addr(spec_insn_c_jr_mem_addr), .spec_mem_rmask(spec_insn_c_jr_mem_rmask), .spec_mem_wmask(spec_insn_c_jr_mem_wmask), .spec_mem_wdata(spec_insn_c_jr_mem_wdata) ); wire spec_insn_c_li_valid; wire spec_insn_c_li_trap; wire [ 4 : 0] spec_insn_c_li_rs1_addr; wire [ 4 : 0] spec_insn_c_li_rs2_addr; wire [ 4 : 0] spec_insn_c_li_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_csr_misa_rmask; `endif rvfi_insn_c_li insn_c_li ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_li_csr_misa_rmask), `endif .spec_valid(spec_insn_c_li_valid), .spec_trap(spec_insn_c_li_trap), .spec_rs1_addr(spec_insn_c_li_rs1_addr), .spec_rs2_addr(spec_insn_c_li_rs2_addr), .spec_rd_addr(spec_insn_c_li_rd_addr), .spec_rd_wdata(spec_insn_c_li_rd_wdata), .spec_pc_wdata(spec_insn_c_li_pc_wdata), .spec_mem_addr(spec_insn_c_li_mem_addr), .spec_mem_rmask(spec_insn_c_li_mem_rmask), .spec_mem_wmask(spec_insn_c_li_mem_wmask), .spec_mem_wdata(spec_insn_c_li_mem_wdata) ); wire spec_insn_c_lui_valid; wire spec_insn_c_lui_trap; wire [ 4 : 0] spec_insn_c_lui_rs1_addr; wire [ 4 : 0] spec_insn_c_lui_rs2_addr; wire [ 4 : 0] spec_insn_c_lui_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_csr_misa_rmask; `endif rvfi_insn_c_lui insn_c_lui ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_lui_csr_misa_rmask), `endif .spec_valid(spec_insn_c_lui_valid), .spec_trap(spec_insn_c_lui_trap), .spec_rs1_addr(spec_insn_c_lui_rs1_addr), .spec_rs2_addr(spec_insn_c_lui_rs2_addr), .spec_rd_addr(spec_insn_c_lui_rd_addr), .spec_rd_wdata(spec_insn_c_lui_rd_wdata), .spec_pc_wdata(spec_insn_c_lui_pc_wdata), .spec_mem_addr(spec_insn_c_lui_mem_addr), .spec_mem_rmask(spec_insn_c_lui_mem_rmask), .spec_mem_wmask(spec_insn_c_lui_mem_wmask), .spec_mem_wdata(spec_insn_c_lui_mem_wdata) ); wire spec_insn_c_lw_valid; wire spec_insn_c_lw_trap; wire [ 4 : 0] spec_insn_c_lw_rs1_addr; wire [ 4 : 0] spec_insn_c_lw_rs2_addr; wire [ 4 : 0] spec_insn_c_lw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_csr_misa_rmask; `endif rvfi_insn_c_lw insn_c_lw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_lw_csr_misa_rmask), `endif .spec_valid(spec_insn_c_lw_valid), .spec_trap(spec_insn_c_lw_trap), .spec_rs1_addr(spec_insn_c_lw_rs1_addr), .spec_rs2_addr(spec_insn_c_lw_rs2_addr), .spec_rd_addr(spec_insn_c_lw_rd_addr), .spec_rd_wdata(spec_insn_c_lw_rd_wdata), .spec_pc_wdata(spec_insn_c_lw_pc_wdata), .spec_mem_addr(spec_insn_c_lw_mem_addr), .spec_mem_rmask(spec_insn_c_lw_mem_rmask), .spec_mem_wmask(spec_insn_c_lw_mem_wmask), .spec_mem_wdata(spec_insn_c_lw_mem_wdata) ); wire spec_insn_c_lwsp_valid; wire spec_insn_c_lwsp_trap; wire [ 4 : 0] spec_insn_c_lwsp_rs1_addr; wire [ 4 : 0] spec_insn_c_lwsp_rs2_addr; wire [ 4 : 0] spec_insn_c_lwsp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_csr_misa_rmask; `endif rvfi_insn_c_lwsp insn_c_lwsp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_lwsp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_lwsp_valid), .spec_trap(spec_insn_c_lwsp_trap), .spec_rs1_addr(spec_insn_c_lwsp_rs1_addr), .spec_rs2_addr(spec_insn_c_lwsp_rs2_addr), .spec_rd_addr(spec_insn_c_lwsp_rd_addr), .spec_rd_wdata(spec_insn_c_lwsp_rd_wdata), .spec_pc_wdata(spec_insn_c_lwsp_pc_wdata), .spec_mem_addr(spec_insn_c_lwsp_mem_addr), .spec_mem_rmask(spec_insn_c_lwsp_mem_rmask), .spec_mem_wmask(spec_insn_c_lwsp_mem_wmask), .spec_mem_wdata(spec_insn_c_lwsp_mem_wdata) ); wire spec_insn_c_mv_valid; wire spec_insn_c_mv_trap; wire [ 4 : 0] spec_insn_c_mv_rs1_addr; wire [ 4 : 0] spec_insn_c_mv_rs2_addr; wire [ 4 : 0] spec_insn_c_mv_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_csr_misa_rmask; `endif rvfi_insn_c_mv insn_c_mv ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_mv_csr_misa_rmask), `endif .spec_valid(spec_insn_c_mv_valid), .spec_trap(spec_insn_c_mv_trap), .spec_rs1_addr(spec_insn_c_mv_rs1_addr), .spec_rs2_addr(spec_insn_c_mv_rs2_addr), .spec_rd_addr(spec_insn_c_mv_rd_addr), .spec_rd_wdata(spec_insn_c_mv_rd_wdata), .spec_pc_wdata(spec_insn_c_mv_pc_wdata), .spec_mem_addr(spec_insn_c_mv_mem_addr), .spec_mem_rmask(spec_insn_c_mv_mem_rmask), .spec_mem_wmask(spec_insn_c_mv_mem_wmask), .spec_mem_wdata(spec_insn_c_mv_mem_wdata) ); wire spec_insn_c_or_valid; wire spec_insn_c_or_trap; wire [ 4 : 0] spec_insn_c_or_rs1_addr; wire [ 4 : 0] spec_insn_c_or_rs2_addr; wire [ 4 : 0] spec_insn_c_or_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_csr_misa_rmask; `endif rvfi_insn_c_or insn_c_or ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_or_csr_misa_rmask), `endif .spec_valid(spec_insn_c_or_valid), .spec_trap(spec_insn_c_or_trap), .spec_rs1_addr(spec_insn_c_or_rs1_addr), .spec_rs2_addr(spec_insn_c_or_rs2_addr), .spec_rd_addr(spec_insn_c_or_rd_addr), .spec_rd_wdata(spec_insn_c_or_rd_wdata), .spec_pc_wdata(spec_insn_c_or_pc_wdata), .spec_mem_addr(spec_insn_c_or_mem_addr), .spec_mem_rmask(spec_insn_c_or_mem_rmask), .spec_mem_wmask(spec_insn_c_or_mem_wmask), .spec_mem_wdata(spec_insn_c_or_mem_wdata) ); wire spec_insn_c_slli_valid; wire spec_insn_c_slli_trap; wire [ 4 : 0] spec_insn_c_slli_rs1_addr; wire [ 4 : 0] spec_insn_c_slli_rs2_addr; wire [ 4 : 0] spec_insn_c_slli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_csr_misa_rmask; `endif rvfi_insn_c_slli insn_c_slli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_slli_csr_misa_rmask), `endif .spec_valid(spec_insn_c_slli_valid), .spec_trap(spec_insn_c_slli_trap), .spec_rs1_addr(spec_insn_c_slli_rs1_addr), .spec_rs2_addr(spec_insn_c_slli_rs2_addr), .spec_rd_addr(spec_insn_c_slli_rd_addr), .spec_rd_wdata(spec_insn_c_slli_rd_wdata), .spec_pc_wdata(spec_insn_c_slli_pc_wdata), .spec_mem_addr(spec_insn_c_slli_mem_addr), .spec_mem_rmask(spec_insn_c_slli_mem_rmask), .spec_mem_wmask(spec_insn_c_slli_mem_wmask), .spec_mem_wdata(spec_insn_c_slli_mem_wdata) ); wire spec_insn_c_srai_valid; wire spec_insn_c_srai_trap; wire [ 4 : 0] spec_insn_c_srai_rs1_addr; wire [ 4 : 0] spec_insn_c_srai_rs2_addr; wire [ 4 : 0] spec_insn_c_srai_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_csr_misa_rmask; `endif rvfi_insn_c_srai insn_c_srai ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_srai_csr_misa_rmask), `endif .spec_valid(spec_insn_c_srai_valid), .spec_trap(spec_insn_c_srai_trap), .spec_rs1_addr(spec_insn_c_srai_rs1_addr), .spec_rs2_addr(spec_insn_c_srai_rs2_addr), .spec_rd_addr(spec_insn_c_srai_rd_addr), .spec_rd_wdata(spec_insn_c_srai_rd_wdata), .spec_pc_wdata(spec_insn_c_srai_pc_wdata), .spec_mem_addr(spec_insn_c_srai_mem_addr), .spec_mem_rmask(spec_insn_c_srai_mem_rmask), .spec_mem_wmask(spec_insn_c_srai_mem_wmask), .spec_mem_wdata(spec_insn_c_srai_mem_wdata) ); wire spec_insn_c_srli_valid; wire spec_insn_c_srli_trap; wire [ 4 : 0] spec_insn_c_srli_rs1_addr; wire [ 4 : 0] spec_insn_c_srli_rs2_addr; wire [ 4 : 0] spec_insn_c_srli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_csr_misa_rmask; `endif rvfi_insn_c_srli insn_c_srli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_srli_csr_misa_rmask), `endif .spec_valid(spec_insn_c_srli_valid), .spec_trap(spec_insn_c_srli_trap), .spec_rs1_addr(spec_insn_c_srli_rs1_addr), .spec_rs2_addr(spec_insn_c_srli_rs2_addr), .spec_rd_addr(spec_insn_c_srli_rd_addr), .spec_rd_wdata(spec_insn_c_srli_rd_wdata), .spec_pc_wdata(spec_insn_c_srli_pc_wdata), .spec_mem_addr(spec_insn_c_srli_mem_addr), .spec_mem_rmask(spec_insn_c_srli_mem_rmask), .spec_mem_wmask(spec_insn_c_srli_mem_wmask), .spec_mem_wdata(spec_insn_c_srli_mem_wdata) ); wire spec_insn_c_sub_valid; wire spec_insn_c_sub_trap; wire [ 4 : 0] spec_insn_c_sub_rs1_addr; wire [ 4 : 0] spec_insn_c_sub_rs2_addr; wire [ 4 : 0] spec_insn_c_sub_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_csr_misa_rmask; `endif rvfi_insn_c_sub insn_c_sub ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_sub_csr_misa_rmask), `endif .spec_valid(spec_insn_c_sub_valid), .spec_trap(spec_insn_c_sub_trap), .spec_rs1_addr(spec_insn_c_sub_rs1_addr), .spec_rs2_addr(spec_insn_c_sub_rs2_addr), .spec_rd_addr(spec_insn_c_sub_rd_addr), .spec_rd_wdata(spec_insn_c_sub_rd_wdata), .spec_pc_wdata(spec_insn_c_sub_pc_wdata), .spec_mem_addr(spec_insn_c_sub_mem_addr), .spec_mem_rmask(spec_insn_c_sub_mem_rmask), .spec_mem_wmask(spec_insn_c_sub_mem_wmask), .spec_mem_wdata(spec_insn_c_sub_mem_wdata) ); wire spec_insn_c_sw_valid; wire spec_insn_c_sw_trap; wire [ 4 : 0] spec_insn_c_sw_rs1_addr; wire [ 4 : 0] spec_insn_c_sw_rs2_addr; wire [ 4 : 0] spec_insn_c_sw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_csr_misa_rmask; `endif rvfi_insn_c_sw insn_c_sw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_sw_csr_misa_rmask), `endif .spec_valid(spec_insn_c_sw_valid), .spec_trap(spec_insn_c_sw_trap), .spec_rs1_addr(spec_insn_c_sw_rs1_addr), .spec_rs2_addr(spec_insn_c_sw_rs2_addr), .spec_rd_addr(spec_insn_c_sw_rd_addr), .spec_rd_wdata(spec_insn_c_sw_rd_wdata), .spec_pc_wdata(spec_insn_c_sw_pc_wdata), .spec_mem_addr(spec_insn_c_sw_mem_addr), .spec_mem_rmask(spec_insn_c_sw_mem_rmask), .spec_mem_wmask(spec_insn_c_sw_mem_wmask), .spec_mem_wdata(spec_insn_c_sw_mem_wdata) ); wire spec_insn_c_swsp_valid; wire spec_insn_c_swsp_trap; wire [ 4 : 0] spec_insn_c_swsp_rs1_addr; wire [ 4 : 0] spec_insn_c_swsp_rs2_addr; wire [ 4 : 0] spec_insn_c_swsp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_csr_misa_rmask; `endif rvfi_insn_c_swsp insn_c_swsp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_swsp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_swsp_valid), .spec_trap(spec_insn_c_swsp_trap), .spec_rs1_addr(spec_insn_c_swsp_rs1_addr), .spec_rs2_addr(spec_insn_c_swsp_rs2_addr), .spec_rd_addr(spec_insn_c_swsp_rd_addr), .spec_rd_wdata(spec_insn_c_swsp_rd_wdata), .spec_pc_wdata(spec_insn_c_swsp_pc_wdata), .spec_mem_addr(spec_insn_c_swsp_mem_addr), .spec_mem_rmask(spec_insn_c_swsp_mem_rmask), .spec_mem_wmask(spec_insn_c_swsp_mem_wmask), .spec_mem_wdata(spec_insn_c_swsp_mem_wdata) ); wire spec_insn_c_xor_valid; wire spec_insn_c_xor_trap; wire [ 4 : 0] spec_insn_c_xor_rs1_addr; wire [ 4 : 0] spec_insn_c_xor_rs2_addr; wire [ 4 : 0] spec_insn_c_xor_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_csr_misa_rmask; `endif rvfi_insn_c_xor insn_c_xor ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_xor_csr_misa_rmask), `endif .spec_valid(spec_insn_c_xor_valid), .spec_trap(spec_insn_c_xor_trap), .spec_rs1_addr(spec_insn_c_xor_rs1_addr), .spec_rs2_addr(spec_insn_c_xor_rs2_addr), .spec_rd_addr(spec_insn_c_xor_rd_addr), .spec_rd_wdata(spec_insn_c_xor_rd_wdata), .spec_pc_wdata(spec_insn_c_xor_pc_wdata), .spec_mem_addr(spec_insn_c_xor_mem_addr), .spec_mem_rmask(spec_insn_c_xor_mem_rmask), .spec_mem_wmask(spec_insn_c_xor_mem_wmask), .spec_mem_wdata(spec_insn_c_xor_mem_wdata) ); wire spec_insn_div_valid; wire spec_insn_div_trap; wire [ 4 : 0] spec_insn_div_rs1_addr; wire [ 4 : 0] spec_insn_div_rs2_addr; wire [ 4 : 0] spec_insn_div_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_csr_misa_rmask; `endif rvfi_insn_div insn_div ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_div_csr_misa_rmask), `endif .spec_valid(spec_insn_div_valid), .spec_trap(spec_insn_div_trap), .spec_rs1_addr(spec_insn_div_rs1_addr), .spec_rs2_addr(spec_insn_div_rs2_addr), .spec_rd_addr(spec_insn_div_rd_addr), .spec_rd_wdata(spec_insn_div_rd_wdata), .spec_pc_wdata(spec_insn_div_pc_wdata), .spec_mem_addr(spec_insn_div_mem_addr), .spec_mem_rmask(spec_insn_div_mem_rmask), .spec_mem_wmask(spec_insn_div_mem_wmask), .spec_mem_wdata(spec_insn_div_mem_wdata) ); wire spec_insn_divu_valid; wire spec_insn_divu_trap; wire [ 4 : 0] spec_insn_divu_rs1_addr; wire [ 4 : 0] spec_insn_divu_rs2_addr; wire [ 4 : 0] spec_insn_divu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_csr_misa_rmask; `endif rvfi_insn_divu insn_divu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_divu_csr_misa_rmask), `endif .spec_valid(spec_insn_divu_valid), .spec_trap(spec_insn_divu_trap), .spec_rs1_addr(spec_insn_divu_rs1_addr), .spec_rs2_addr(spec_insn_divu_rs2_addr), .spec_rd_addr(spec_insn_divu_rd_addr), .spec_rd_wdata(spec_insn_divu_rd_wdata), .spec_pc_wdata(spec_insn_divu_pc_wdata), .spec_mem_addr(spec_insn_divu_mem_addr), .spec_mem_rmask(spec_insn_divu_mem_rmask), .spec_mem_wmask(spec_insn_divu_mem_wmask), .spec_mem_wdata(spec_insn_divu_mem_wdata) ); wire spec_insn_jal_valid; wire spec_insn_jal_trap; wire [ 4 : 0] spec_insn_jal_rs1_addr; wire [ 4 : 0] spec_insn_jal_rs2_addr; wire [ 4 : 0] spec_insn_jal_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; `endif rvfi_insn_jal insn_jal ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), `endif .spec_valid(spec_insn_jal_valid), .spec_trap(spec_insn_jal_trap), .spec_rs1_addr(spec_insn_jal_rs1_addr), .spec_rs2_addr(spec_insn_jal_rs2_addr), .spec_rd_addr(spec_insn_jal_rd_addr), .spec_rd_wdata(spec_insn_jal_rd_wdata), .spec_pc_wdata(spec_insn_jal_pc_wdata), .spec_mem_addr(spec_insn_jal_mem_addr), .spec_mem_rmask(spec_insn_jal_mem_rmask), .spec_mem_wmask(spec_insn_jal_mem_wmask), .spec_mem_wdata(spec_insn_jal_mem_wdata) ); wire spec_insn_jalr_valid; wire spec_insn_jalr_trap; wire [ 4 : 0] spec_insn_jalr_rs1_addr; wire [ 4 : 0] spec_insn_jalr_rs2_addr; wire [ 4 : 0] spec_insn_jalr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; `endif rvfi_insn_jalr insn_jalr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), `endif .spec_valid(spec_insn_jalr_valid), .spec_trap(spec_insn_jalr_trap), .spec_rs1_addr(spec_insn_jalr_rs1_addr), .spec_rs2_addr(spec_insn_jalr_rs2_addr), .spec_rd_addr(spec_insn_jalr_rd_addr), .spec_rd_wdata(spec_insn_jalr_rd_wdata), .spec_pc_wdata(spec_insn_jalr_pc_wdata), .spec_mem_addr(spec_insn_jalr_mem_addr), .spec_mem_rmask(spec_insn_jalr_mem_rmask), .spec_mem_wmask(spec_insn_jalr_mem_wmask), .spec_mem_wdata(spec_insn_jalr_mem_wdata) ); wire spec_insn_lb_valid; wire spec_insn_lb_trap; wire [ 4 : 0] spec_insn_lb_rs1_addr; wire [ 4 : 0] spec_insn_lb_rs2_addr; wire [ 4 : 0] spec_insn_lb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; `endif rvfi_insn_lb insn_lb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), `endif .spec_valid(spec_insn_lb_valid), .spec_trap(spec_insn_lb_trap), .spec_rs1_addr(spec_insn_lb_rs1_addr), .spec_rs2_addr(spec_insn_lb_rs2_addr), .spec_rd_addr(spec_insn_lb_rd_addr), .spec_rd_wdata(spec_insn_lb_rd_wdata), .spec_pc_wdata(spec_insn_lb_pc_wdata), .spec_mem_addr(spec_insn_lb_mem_addr), .spec_mem_rmask(spec_insn_lb_mem_rmask), .spec_mem_wmask(spec_insn_lb_mem_wmask), .spec_mem_wdata(spec_insn_lb_mem_wdata) ); wire spec_insn_lbu_valid; wire spec_insn_lbu_trap; wire [ 4 : 0] spec_insn_lbu_rs1_addr; wire [ 4 : 0] spec_insn_lbu_rs2_addr; wire [ 4 : 0] spec_insn_lbu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; `endif rvfi_insn_lbu insn_lbu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), `endif .spec_valid(spec_insn_lbu_valid), .spec_trap(spec_insn_lbu_trap), .spec_rs1_addr(spec_insn_lbu_rs1_addr), .spec_rs2_addr(spec_insn_lbu_rs2_addr), .spec_rd_addr(spec_insn_lbu_rd_addr), .spec_rd_wdata(spec_insn_lbu_rd_wdata), .spec_pc_wdata(spec_insn_lbu_pc_wdata), .spec_mem_addr(spec_insn_lbu_mem_addr), .spec_mem_rmask(spec_insn_lbu_mem_rmask), .spec_mem_wmask(spec_insn_lbu_mem_wmask), .spec_mem_wdata(spec_insn_lbu_mem_wdata) ); wire spec_insn_lh_valid; wire spec_insn_lh_trap; wire [ 4 : 0] spec_insn_lh_rs1_addr; wire [ 4 : 0] spec_insn_lh_rs2_addr; wire [ 4 : 0] spec_insn_lh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; `endif rvfi_insn_lh insn_lh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), `endif .spec_valid(spec_insn_lh_valid), .spec_trap(spec_insn_lh_trap), .spec_rs1_addr(spec_insn_lh_rs1_addr), .spec_rs2_addr(spec_insn_lh_rs2_addr), .spec_rd_addr(spec_insn_lh_rd_addr), .spec_rd_wdata(spec_insn_lh_rd_wdata), .spec_pc_wdata(spec_insn_lh_pc_wdata), .spec_mem_addr(spec_insn_lh_mem_addr), .spec_mem_rmask(spec_insn_lh_mem_rmask), .spec_mem_wmask(spec_insn_lh_mem_wmask), .spec_mem_wdata(spec_insn_lh_mem_wdata) ); wire spec_insn_lhu_valid; wire spec_insn_lhu_trap; wire [ 4 : 0] spec_insn_lhu_rs1_addr; wire [ 4 : 0] spec_insn_lhu_rs2_addr; wire [ 4 : 0] spec_insn_lhu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; `endif rvfi_insn_lhu insn_lhu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), `endif .spec_valid(spec_insn_lhu_valid), .spec_trap(spec_insn_lhu_trap), .spec_rs1_addr(spec_insn_lhu_rs1_addr), .spec_rs2_addr(spec_insn_lhu_rs2_addr), .spec_rd_addr(spec_insn_lhu_rd_addr), .spec_rd_wdata(spec_insn_lhu_rd_wdata), .spec_pc_wdata(spec_insn_lhu_pc_wdata), .spec_mem_addr(spec_insn_lhu_mem_addr), .spec_mem_rmask(spec_insn_lhu_mem_rmask), .spec_mem_wmask(spec_insn_lhu_mem_wmask), .spec_mem_wdata(spec_insn_lhu_mem_wdata) ); wire spec_insn_lui_valid; wire spec_insn_lui_trap; wire [ 4 : 0] spec_insn_lui_rs1_addr; wire [ 4 : 0] spec_insn_lui_rs2_addr; wire [ 4 : 0] spec_insn_lui_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; `endif rvfi_insn_lui insn_lui ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), `endif .spec_valid(spec_insn_lui_valid), .spec_trap(spec_insn_lui_trap), .spec_rs1_addr(spec_insn_lui_rs1_addr), .spec_rs2_addr(spec_insn_lui_rs2_addr), .spec_rd_addr(spec_insn_lui_rd_addr), .spec_rd_wdata(spec_insn_lui_rd_wdata), .spec_pc_wdata(spec_insn_lui_pc_wdata), .spec_mem_addr(spec_insn_lui_mem_addr), .spec_mem_rmask(spec_insn_lui_mem_rmask), .spec_mem_wmask(spec_insn_lui_mem_wmask), .spec_mem_wdata(spec_insn_lui_mem_wdata) ); wire spec_insn_lw_valid; wire spec_insn_lw_trap; wire [ 4 : 0] spec_insn_lw_rs1_addr; wire [ 4 : 0] spec_insn_lw_rs2_addr; wire [ 4 : 0] spec_insn_lw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; `endif rvfi_insn_lw insn_lw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), `endif .spec_valid(spec_insn_lw_valid), .spec_trap(spec_insn_lw_trap), .spec_rs1_addr(spec_insn_lw_rs1_addr), .spec_rs2_addr(spec_insn_lw_rs2_addr), .spec_rd_addr(spec_insn_lw_rd_addr), .spec_rd_wdata(spec_insn_lw_rd_wdata), .spec_pc_wdata(spec_insn_lw_pc_wdata), .spec_mem_addr(spec_insn_lw_mem_addr), .spec_mem_rmask(spec_insn_lw_mem_rmask), .spec_mem_wmask(spec_insn_lw_mem_wmask), .spec_mem_wdata(spec_insn_lw_mem_wdata) ); wire spec_insn_mul_valid; wire spec_insn_mul_trap; wire [ 4 : 0] spec_insn_mul_rs1_addr; wire [ 4 : 0] spec_insn_mul_rs2_addr; wire [ 4 : 0] spec_insn_mul_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_csr_misa_rmask; `endif rvfi_insn_mul insn_mul ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mul_csr_misa_rmask), `endif .spec_valid(spec_insn_mul_valid), .spec_trap(spec_insn_mul_trap), .spec_rs1_addr(spec_insn_mul_rs1_addr), .spec_rs2_addr(spec_insn_mul_rs2_addr), .spec_rd_addr(spec_insn_mul_rd_addr), .spec_rd_wdata(spec_insn_mul_rd_wdata), .spec_pc_wdata(spec_insn_mul_pc_wdata), .spec_mem_addr(spec_insn_mul_mem_addr), .spec_mem_rmask(spec_insn_mul_mem_rmask), .spec_mem_wmask(spec_insn_mul_mem_wmask), .spec_mem_wdata(spec_insn_mul_mem_wdata) ); wire spec_insn_mulh_valid; wire spec_insn_mulh_trap; wire [ 4 : 0] spec_insn_mulh_rs1_addr; wire [ 4 : 0] spec_insn_mulh_rs2_addr; wire [ 4 : 0] spec_insn_mulh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_csr_misa_rmask; `endif rvfi_insn_mulh insn_mulh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mulh_csr_misa_rmask), `endif .spec_valid(spec_insn_mulh_valid), .spec_trap(spec_insn_mulh_trap), .spec_rs1_addr(spec_insn_mulh_rs1_addr), .spec_rs2_addr(spec_insn_mulh_rs2_addr), .spec_rd_addr(spec_insn_mulh_rd_addr), .spec_rd_wdata(spec_insn_mulh_rd_wdata), .spec_pc_wdata(spec_insn_mulh_pc_wdata), .spec_mem_addr(spec_insn_mulh_mem_addr), .spec_mem_rmask(spec_insn_mulh_mem_rmask), .spec_mem_wmask(spec_insn_mulh_mem_wmask), .spec_mem_wdata(spec_insn_mulh_mem_wdata) ); wire spec_insn_mulhsu_valid; wire spec_insn_mulhsu_trap; wire [ 4 : 0] spec_insn_mulhsu_rs1_addr; wire [ 4 : 0] spec_insn_mulhsu_rs2_addr; wire [ 4 : 0] spec_insn_mulhsu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_csr_misa_rmask; `endif rvfi_insn_mulhsu insn_mulhsu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mulhsu_csr_misa_rmask), `endif .spec_valid(spec_insn_mulhsu_valid), .spec_trap(spec_insn_mulhsu_trap), .spec_rs1_addr(spec_insn_mulhsu_rs1_addr), .spec_rs2_addr(spec_insn_mulhsu_rs2_addr), .spec_rd_addr(spec_insn_mulhsu_rd_addr), .spec_rd_wdata(spec_insn_mulhsu_rd_wdata), .spec_pc_wdata(spec_insn_mulhsu_pc_wdata), .spec_mem_addr(spec_insn_mulhsu_mem_addr), .spec_mem_rmask(spec_insn_mulhsu_mem_rmask), .spec_mem_wmask(spec_insn_mulhsu_mem_wmask), .spec_mem_wdata(spec_insn_mulhsu_mem_wdata) ); wire spec_insn_mulhu_valid; wire spec_insn_mulhu_trap; wire [ 4 : 0] spec_insn_mulhu_rs1_addr; wire [ 4 : 0] spec_insn_mulhu_rs2_addr; wire [ 4 : 0] spec_insn_mulhu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_csr_misa_rmask; `endif rvfi_insn_mulhu insn_mulhu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mulhu_csr_misa_rmask), `endif .spec_valid(spec_insn_mulhu_valid), .spec_trap(spec_insn_mulhu_trap), .spec_rs1_addr(spec_insn_mulhu_rs1_addr), .spec_rs2_addr(spec_insn_mulhu_rs2_addr), .spec_rd_addr(spec_insn_mulhu_rd_addr), .spec_rd_wdata(spec_insn_mulhu_rd_wdata), .spec_pc_wdata(spec_insn_mulhu_pc_wdata), .spec_mem_addr(spec_insn_mulhu_mem_addr), .spec_mem_rmask(spec_insn_mulhu_mem_rmask), .spec_mem_wmask(spec_insn_mulhu_mem_wmask), .spec_mem_wdata(spec_insn_mulhu_mem_wdata) ); wire spec_insn_or_valid; wire spec_insn_or_trap; wire [ 4 : 0] spec_insn_or_rs1_addr; wire [ 4 : 0] spec_insn_or_rs2_addr; wire [ 4 : 0] spec_insn_or_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; `endif rvfi_insn_or insn_or ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), `endif .spec_valid(spec_insn_or_valid), .spec_trap(spec_insn_or_trap), .spec_rs1_addr(spec_insn_or_rs1_addr), .spec_rs2_addr(spec_insn_or_rs2_addr), .spec_rd_addr(spec_insn_or_rd_addr), .spec_rd_wdata(spec_insn_or_rd_wdata), .spec_pc_wdata(spec_insn_or_pc_wdata), .spec_mem_addr(spec_insn_or_mem_addr), .spec_mem_rmask(spec_insn_or_mem_rmask), .spec_mem_wmask(spec_insn_or_mem_wmask), .spec_mem_wdata(spec_insn_or_mem_wdata) ); wire spec_insn_ori_valid; wire spec_insn_ori_trap; wire [ 4 : 0] spec_insn_ori_rs1_addr; wire [ 4 : 0] spec_insn_ori_rs2_addr; wire [ 4 : 0] spec_insn_ori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; `endif rvfi_insn_ori insn_ori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), `endif .spec_valid(spec_insn_ori_valid), .spec_trap(spec_insn_ori_trap), .spec_rs1_addr(spec_insn_ori_rs1_addr), .spec_rs2_addr(spec_insn_ori_rs2_addr), .spec_rd_addr(spec_insn_ori_rd_addr), .spec_rd_wdata(spec_insn_ori_rd_wdata), .spec_pc_wdata(spec_insn_ori_pc_wdata), .spec_mem_addr(spec_insn_ori_mem_addr), .spec_mem_rmask(spec_insn_ori_mem_rmask), .spec_mem_wmask(spec_insn_ori_mem_wmask), .spec_mem_wdata(spec_insn_ori_mem_wdata) ); wire spec_insn_rem_valid; wire spec_insn_rem_trap; wire [ 4 : 0] spec_insn_rem_rs1_addr; wire [ 4 : 0] spec_insn_rem_rs2_addr; wire [ 4 : 0] spec_insn_rem_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_csr_misa_rmask; `endif rvfi_insn_rem insn_rem ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_rem_csr_misa_rmask), `endif .spec_valid(spec_insn_rem_valid), .spec_trap(spec_insn_rem_trap), .spec_rs1_addr(spec_insn_rem_rs1_addr), .spec_rs2_addr(spec_insn_rem_rs2_addr), .spec_rd_addr(spec_insn_rem_rd_addr), .spec_rd_wdata(spec_insn_rem_rd_wdata), .spec_pc_wdata(spec_insn_rem_pc_wdata), .spec_mem_addr(spec_insn_rem_mem_addr), .spec_mem_rmask(spec_insn_rem_mem_rmask), .spec_mem_wmask(spec_insn_rem_mem_wmask), .spec_mem_wdata(spec_insn_rem_mem_wdata) ); wire spec_insn_remu_valid; wire spec_insn_remu_trap; wire [ 4 : 0] spec_insn_remu_rs1_addr; wire [ 4 : 0] spec_insn_remu_rs2_addr; wire [ 4 : 0] spec_insn_remu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_csr_misa_rmask; `endif rvfi_insn_remu insn_remu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_remu_csr_misa_rmask), `endif .spec_valid(spec_insn_remu_valid), .spec_trap(spec_insn_remu_trap), .spec_rs1_addr(spec_insn_remu_rs1_addr), .spec_rs2_addr(spec_insn_remu_rs2_addr), .spec_rd_addr(spec_insn_remu_rd_addr), .spec_rd_wdata(spec_insn_remu_rd_wdata), .spec_pc_wdata(spec_insn_remu_pc_wdata), .spec_mem_addr(spec_insn_remu_mem_addr), .spec_mem_rmask(spec_insn_remu_mem_rmask), .spec_mem_wmask(spec_insn_remu_mem_wmask), .spec_mem_wdata(spec_insn_remu_mem_wdata) ); wire spec_insn_sb_valid; wire spec_insn_sb_trap; wire [ 4 : 0] spec_insn_sb_rs1_addr; wire [ 4 : 0] spec_insn_sb_rs2_addr; wire [ 4 : 0] spec_insn_sb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; `endif rvfi_insn_sb insn_sb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), `endif .spec_valid(spec_insn_sb_valid), .spec_trap(spec_insn_sb_trap), .spec_rs1_addr(spec_insn_sb_rs1_addr), .spec_rs2_addr(spec_insn_sb_rs2_addr), .spec_rd_addr(spec_insn_sb_rd_addr), .spec_rd_wdata(spec_insn_sb_rd_wdata), .spec_pc_wdata(spec_insn_sb_pc_wdata), .spec_mem_addr(spec_insn_sb_mem_addr), .spec_mem_rmask(spec_insn_sb_mem_rmask), .spec_mem_wmask(spec_insn_sb_mem_wmask), .spec_mem_wdata(spec_insn_sb_mem_wdata) ); wire spec_insn_sh_valid; wire spec_insn_sh_trap; wire [ 4 : 0] spec_insn_sh_rs1_addr; wire [ 4 : 0] spec_insn_sh_rs2_addr; wire [ 4 : 0] spec_insn_sh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; `endif rvfi_insn_sh insn_sh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), `endif .spec_valid(spec_insn_sh_valid), .spec_trap(spec_insn_sh_trap), .spec_rs1_addr(spec_insn_sh_rs1_addr), .spec_rs2_addr(spec_insn_sh_rs2_addr), .spec_rd_addr(spec_insn_sh_rd_addr), .spec_rd_wdata(spec_insn_sh_rd_wdata), .spec_pc_wdata(spec_insn_sh_pc_wdata), .spec_mem_addr(spec_insn_sh_mem_addr), .spec_mem_rmask(spec_insn_sh_mem_rmask), .spec_mem_wmask(spec_insn_sh_mem_wmask), .spec_mem_wdata(spec_insn_sh_mem_wdata) ); wire spec_insn_sll_valid; wire spec_insn_sll_trap; wire [ 4 : 0] spec_insn_sll_rs1_addr; wire [ 4 : 0] spec_insn_sll_rs2_addr; wire [ 4 : 0] spec_insn_sll_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; `endif rvfi_insn_sll insn_sll ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), `endif .spec_valid(spec_insn_sll_valid), .spec_trap(spec_insn_sll_trap), .spec_rs1_addr(spec_insn_sll_rs1_addr), .spec_rs2_addr(spec_insn_sll_rs2_addr), .spec_rd_addr(spec_insn_sll_rd_addr), .spec_rd_wdata(spec_insn_sll_rd_wdata), .spec_pc_wdata(spec_insn_sll_pc_wdata), .spec_mem_addr(spec_insn_sll_mem_addr), .spec_mem_rmask(spec_insn_sll_mem_rmask), .spec_mem_wmask(spec_insn_sll_mem_wmask), .spec_mem_wdata(spec_insn_sll_mem_wdata) ); wire spec_insn_slli_valid; wire spec_insn_slli_trap; wire [ 4 : 0] spec_insn_slli_rs1_addr; wire [ 4 : 0] spec_insn_slli_rs2_addr; wire [ 4 : 0] spec_insn_slli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; `endif rvfi_insn_slli insn_slli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), `endif .spec_valid(spec_insn_slli_valid), .spec_trap(spec_insn_slli_trap), .spec_rs1_addr(spec_insn_slli_rs1_addr), .spec_rs2_addr(spec_insn_slli_rs2_addr), .spec_rd_addr(spec_insn_slli_rd_addr), .spec_rd_wdata(spec_insn_slli_rd_wdata), .spec_pc_wdata(spec_insn_slli_pc_wdata), .spec_mem_addr(spec_insn_slli_mem_addr), .spec_mem_rmask(spec_insn_slli_mem_rmask), .spec_mem_wmask(spec_insn_slli_mem_wmask), .spec_mem_wdata(spec_insn_slli_mem_wdata) ); wire spec_insn_slt_valid; wire spec_insn_slt_trap; wire [ 4 : 0] spec_insn_slt_rs1_addr; wire [ 4 : 0] spec_insn_slt_rs2_addr; wire [ 4 : 0] spec_insn_slt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; `endif rvfi_insn_slt insn_slt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), `endif .spec_valid(spec_insn_slt_valid), .spec_trap(spec_insn_slt_trap), .spec_rs1_addr(spec_insn_slt_rs1_addr), .spec_rs2_addr(spec_insn_slt_rs2_addr), .spec_rd_addr(spec_insn_slt_rd_addr), .spec_rd_wdata(spec_insn_slt_rd_wdata), .spec_pc_wdata(spec_insn_slt_pc_wdata), .spec_mem_addr(spec_insn_slt_mem_addr), .spec_mem_rmask(spec_insn_slt_mem_rmask), .spec_mem_wmask(spec_insn_slt_mem_wmask), .spec_mem_wdata(spec_insn_slt_mem_wdata) ); wire spec_insn_slti_valid; wire spec_insn_slti_trap; wire [ 4 : 0] spec_insn_slti_rs1_addr; wire [ 4 : 0] spec_insn_slti_rs2_addr; wire [ 4 : 0] spec_insn_slti_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; `endif rvfi_insn_slti insn_slti ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), `endif .spec_valid(spec_insn_slti_valid), .spec_trap(spec_insn_slti_trap), .spec_rs1_addr(spec_insn_slti_rs1_addr), .spec_rs2_addr(spec_insn_slti_rs2_addr), .spec_rd_addr(spec_insn_slti_rd_addr), .spec_rd_wdata(spec_insn_slti_rd_wdata), .spec_pc_wdata(spec_insn_slti_pc_wdata), .spec_mem_addr(spec_insn_slti_mem_addr), .spec_mem_rmask(spec_insn_slti_mem_rmask), .spec_mem_wmask(spec_insn_slti_mem_wmask), .spec_mem_wdata(spec_insn_slti_mem_wdata) ); wire spec_insn_sltiu_valid; wire spec_insn_sltiu_trap; wire [ 4 : 0] spec_insn_sltiu_rs1_addr; wire [ 4 : 0] spec_insn_sltiu_rs2_addr; wire [ 4 : 0] spec_insn_sltiu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; `endif rvfi_insn_sltiu insn_sltiu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltiu_valid), .spec_trap(spec_insn_sltiu_trap), .spec_rs1_addr(spec_insn_sltiu_rs1_addr), .spec_rs2_addr(spec_insn_sltiu_rs2_addr), .spec_rd_addr(spec_insn_sltiu_rd_addr), .spec_rd_wdata(spec_insn_sltiu_rd_wdata), .spec_pc_wdata(spec_insn_sltiu_pc_wdata), .spec_mem_addr(spec_insn_sltiu_mem_addr), .spec_mem_rmask(spec_insn_sltiu_mem_rmask), .spec_mem_wmask(spec_insn_sltiu_mem_wmask), .spec_mem_wdata(spec_insn_sltiu_mem_wdata) ); wire spec_insn_sltu_valid; wire spec_insn_sltu_trap; wire [ 4 : 0] spec_insn_sltu_rs1_addr; wire [ 4 : 0] spec_insn_sltu_rs2_addr; wire [ 4 : 0] spec_insn_sltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; `endif rvfi_insn_sltu insn_sltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltu_valid), .spec_trap(spec_insn_sltu_trap), .spec_rs1_addr(spec_insn_sltu_rs1_addr), .spec_rs2_addr(spec_insn_sltu_rs2_addr), .spec_rd_addr(spec_insn_sltu_rd_addr), .spec_rd_wdata(spec_insn_sltu_rd_wdata), .spec_pc_wdata(spec_insn_sltu_pc_wdata), .spec_mem_addr(spec_insn_sltu_mem_addr), .spec_mem_rmask(spec_insn_sltu_mem_rmask), .spec_mem_wmask(spec_insn_sltu_mem_wmask), .spec_mem_wdata(spec_insn_sltu_mem_wdata) ); wire spec_insn_sra_valid; wire spec_insn_sra_trap; wire [ 4 : 0] spec_insn_sra_rs1_addr; wire [ 4 : 0] spec_insn_sra_rs2_addr; wire [ 4 : 0] spec_insn_sra_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; `endif rvfi_insn_sra insn_sra ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), `endif .spec_valid(spec_insn_sra_valid), .spec_trap(spec_insn_sra_trap), .spec_rs1_addr(spec_insn_sra_rs1_addr), .spec_rs2_addr(spec_insn_sra_rs2_addr), .spec_rd_addr(spec_insn_sra_rd_addr), .spec_rd_wdata(spec_insn_sra_rd_wdata), .spec_pc_wdata(spec_insn_sra_pc_wdata), .spec_mem_addr(spec_insn_sra_mem_addr), .spec_mem_rmask(spec_insn_sra_mem_rmask), .spec_mem_wmask(spec_insn_sra_mem_wmask), .spec_mem_wdata(spec_insn_sra_mem_wdata) ); wire spec_insn_srai_valid; wire spec_insn_srai_trap; wire [ 4 : 0] spec_insn_srai_rs1_addr; wire [ 4 : 0] spec_insn_srai_rs2_addr; wire [ 4 : 0] spec_insn_srai_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; `endif rvfi_insn_srai insn_srai ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), `endif .spec_valid(spec_insn_srai_valid), .spec_trap(spec_insn_srai_trap), .spec_rs1_addr(spec_insn_srai_rs1_addr), .spec_rs2_addr(spec_insn_srai_rs2_addr), .spec_rd_addr(spec_insn_srai_rd_addr), .spec_rd_wdata(spec_insn_srai_rd_wdata), .spec_pc_wdata(spec_insn_srai_pc_wdata), .spec_mem_addr(spec_insn_srai_mem_addr), .spec_mem_rmask(spec_insn_srai_mem_rmask), .spec_mem_wmask(spec_insn_srai_mem_wmask), .spec_mem_wdata(spec_insn_srai_mem_wdata) ); wire spec_insn_srl_valid; wire spec_insn_srl_trap; wire [ 4 : 0] spec_insn_srl_rs1_addr; wire [ 4 : 0] spec_insn_srl_rs2_addr; wire [ 4 : 0] spec_insn_srl_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; `endif rvfi_insn_srl insn_srl ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), `endif .spec_valid(spec_insn_srl_valid), .spec_trap(spec_insn_srl_trap), .spec_rs1_addr(spec_insn_srl_rs1_addr), .spec_rs2_addr(spec_insn_srl_rs2_addr), .spec_rd_addr(spec_insn_srl_rd_addr), .spec_rd_wdata(spec_insn_srl_rd_wdata), .spec_pc_wdata(spec_insn_srl_pc_wdata), .spec_mem_addr(spec_insn_srl_mem_addr), .spec_mem_rmask(spec_insn_srl_mem_rmask), .spec_mem_wmask(spec_insn_srl_mem_wmask), .spec_mem_wdata(spec_insn_srl_mem_wdata) ); wire spec_insn_srli_valid; wire spec_insn_srli_trap; wire [ 4 : 0] spec_insn_srli_rs1_addr; wire [ 4 : 0] spec_insn_srli_rs2_addr; wire [ 4 : 0] spec_insn_srli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; `endif rvfi_insn_srli insn_srli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), `endif .spec_valid(spec_insn_srli_valid), .spec_trap(spec_insn_srli_trap), .spec_rs1_addr(spec_insn_srli_rs1_addr), .spec_rs2_addr(spec_insn_srli_rs2_addr), .spec_rd_addr(spec_insn_srli_rd_addr), .spec_rd_wdata(spec_insn_srli_rd_wdata), .spec_pc_wdata(spec_insn_srli_pc_wdata), .spec_mem_addr(spec_insn_srli_mem_addr), .spec_mem_rmask(spec_insn_srli_mem_rmask), .spec_mem_wmask(spec_insn_srli_mem_wmask), .spec_mem_wdata(spec_insn_srli_mem_wdata) ); wire spec_insn_sub_valid; wire spec_insn_sub_trap; wire [ 4 : 0] spec_insn_sub_rs1_addr; wire [ 4 : 0] spec_insn_sub_rs2_addr; wire [ 4 : 0] spec_insn_sub_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; `endif rvfi_insn_sub insn_sub ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), `endif .spec_valid(spec_insn_sub_valid), .spec_trap(spec_insn_sub_trap), .spec_rs1_addr(spec_insn_sub_rs1_addr), .spec_rs2_addr(spec_insn_sub_rs2_addr), .spec_rd_addr(spec_insn_sub_rd_addr), .spec_rd_wdata(spec_insn_sub_rd_wdata), .spec_pc_wdata(spec_insn_sub_pc_wdata), .spec_mem_addr(spec_insn_sub_mem_addr), .spec_mem_rmask(spec_insn_sub_mem_rmask), .spec_mem_wmask(spec_insn_sub_mem_wmask), .spec_mem_wdata(spec_insn_sub_mem_wdata) ); wire spec_insn_sw_valid; wire spec_insn_sw_trap; wire [ 4 : 0] spec_insn_sw_rs1_addr; wire [ 4 : 0] spec_insn_sw_rs2_addr; wire [ 4 : 0] spec_insn_sw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; `endif rvfi_insn_sw insn_sw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), `endif .spec_valid(spec_insn_sw_valid), .spec_trap(spec_insn_sw_trap), .spec_rs1_addr(spec_insn_sw_rs1_addr), .spec_rs2_addr(spec_insn_sw_rs2_addr), .spec_rd_addr(spec_insn_sw_rd_addr), .spec_rd_wdata(spec_insn_sw_rd_wdata), .spec_pc_wdata(spec_insn_sw_pc_wdata), .spec_mem_addr(spec_insn_sw_mem_addr), .spec_mem_rmask(spec_insn_sw_mem_rmask), .spec_mem_wmask(spec_insn_sw_mem_wmask), .spec_mem_wdata(spec_insn_sw_mem_wdata) ); wire spec_insn_xor_valid; wire spec_insn_xor_trap; wire [ 4 : 0] spec_insn_xor_rs1_addr; wire [ 4 : 0] spec_insn_xor_rs2_addr; wire [ 4 : 0] spec_insn_xor_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; `endif rvfi_insn_xor insn_xor ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), `endif .spec_valid(spec_insn_xor_valid), .spec_trap(spec_insn_xor_trap), .spec_rs1_addr(spec_insn_xor_rs1_addr), .spec_rs2_addr(spec_insn_xor_rs2_addr), .spec_rd_addr(spec_insn_xor_rd_addr), .spec_rd_wdata(spec_insn_xor_rd_wdata), .spec_pc_wdata(spec_insn_xor_pc_wdata), .spec_mem_addr(spec_insn_xor_mem_addr), .spec_mem_rmask(spec_insn_xor_mem_rmask), .spec_mem_wmask(spec_insn_xor_mem_wmask), .spec_mem_wdata(spec_insn_xor_mem_wdata) ); wire spec_insn_xori_valid; wire spec_insn_xori_trap; wire [ 4 : 0] spec_insn_xori_rs1_addr; wire [ 4 : 0] spec_insn_xori_rs2_addr; wire [ 4 : 0] spec_insn_xori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; `endif rvfi_insn_xori insn_xori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), `endif .spec_valid(spec_insn_xori_valid), .spec_trap(spec_insn_xori_trap), .spec_rs1_addr(spec_insn_xori_rs1_addr), .spec_rs2_addr(spec_insn_xori_rs2_addr), .spec_rd_addr(spec_insn_xori_rd_addr), .spec_rd_wdata(spec_insn_xori_rd_wdata), .spec_pc_wdata(spec_insn_xori_pc_wdata), .spec_mem_addr(spec_insn_xori_mem_addr), .spec_mem_rmask(spec_insn_xori_mem_rmask), .spec_mem_wmask(spec_insn_xori_mem_wmask), .spec_mem_wdata(spec_insn_xori_mem_wdata) ); assign spec_valid = spec_insn_add_valid ? spec_insn_add_valid : spec_insn_addi_valid ? spec_insn_addi_valid : spec_insn_and_valid ? spec_insn_and_valid : spec_insn_andi_valid ? spec_insn_andi_valid : spec_insn_auipc_valid ? spec_insn_auipc_valid : spec_insn_beq_valid ? spec_insn_beq_valid : spec_insn_bge_valid ? spec_insn_bge_valid : spec_insn_bgeu_valid ? spec_insn_bgeu_valid : spec_insn_blt_valid ? spec_insn_blt_valid : spec_insn_bltu_valid ? spec_insn_bltu_valid : spec_insn_bne_valid ? spec_insn_bne_valid : spec_insn_c_add_valid ? spec_insn_c_add_valid : spec_insn_c_addi_valid ? spec_insn_c_addi_valid : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_valid : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_valid : spec_insn_c_and_valid ? spec_insn_c_and_valid : spec_insn_c_andi_valid ? spec_insn_c_andi_valid : spec_insn_c_beqz_valid ? spec_insn_c_beqz_valid : spec_insn_c_bnez_valid ? spec_insn_c_bnez_valid : spec_insn_c_j_valid ? spec_insn_c_j_valid : spec_insn_c_jal_valid ? spec_insn_c_jal_valid : spec_insn_c_jalr_valid ? spec_insn_c_jalr_valid : spec_insn_c_jr_valid ? spec_insn_c_jr_valid : spec_insn_c_li_valid ? spec_insn_c_li_valid : spec_insn_c_lui_valid ? spec_insn_c_lui_valid : spec_insn_c_lw_valid ? spec_insn_c_lw_valid : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_valid : spec_insn_c_mv_valid ? spec_insn_c_mv_valid : spec_insn_c_or_valid ? spec_insn_c_or_valid : spec_insn_c_slli_valid ? spec_insn_c_slli_valid : spec_insn_c_srai_valid ? spec_insn_c_srai_valid : spec_insn_c_srli_valid ? spec_insn_c_srli_valid : spec_insn_c_sub_valid ? spec_insn_c_sub_valid : spec_insn_c_sw_valid ? spec_insn_c_sw_valid : spec_insn_c_swsp_valid ? spec_insn_c_swsp_valid : spec_insn_c_xor_valid ? spec_insn_c_xor_valid : spec_insn_div_valid ? spec_insn_div_valid : spec_insn_divu_valid ? spec_insn_divu_valid : spec_insn_jal_valid ? spec_insn_jal_valid : spec_insn_jalr_valid ? spec_insn_jalr_valid : spec_insn_lb_valid ? spec_insn_lb_valid : spec_insn_lbu_valid ? spec_insn_lbu_valid : spec_insn_lh_valid ? spec_insn_lh_valid : spec_insn_lhu_valid ? spec_insn_lhu_valid : spec_insn_lui_valid ? spec_insn_lui_valid : spec_insn_lw_valid ? spec_insn_lw_valid : spec_insn_mul_valid ? spec_insn_mul_valid : spec_insn_mulh_valid ? spec_insn_mulh_valid : spec_insn_mulhsu_valid ? spec_insn_mulhsu_valid : spec_insn_mulhu_valid ? spec_insn_mulhu_valid : spec_insn_or_valid ? spec_insn_or_valid : spec_insn_ori_valid ? spec_insn_ori_valid : spec_insn_rem_valid ? spec_insn_rem_valid : spec_insn_remu_valid ? spec_insn_remu_valid : spec_insn_sb_valid ? spec_insn_sb_valid : spec_insn_sh_valid ? spec_insn_sh_valid : spec_insn_sll_valid ? spec_insn_sll_valid : spec_insn_slli_valid ? spec_insn_slli_valid : spec_insn_slt_valid ? spec_insn_slt_valid : spec_insn_slti_valid ? spec_insn_slti_valid : spec_insn_sltiu_valid ? spec_insn_sltiu_valid : spec_insn_sltu_valid ? spec_insn_sltu_valid : spec_insn_sra_valid ? spec_insn_sra_valid : spec_insn_srai_valid ? spec_insn_srai_valid : spec_insn_srl_valid ? spec_insn_srl_valid : spec_insn_srli_valid ? spec_insn_srli_valid : spec_insn_sub_valid ? spec_insn_sub_valid : spec_insn_sw_valid ? spec_insn_sw_valid : spec_insn_xor_valid ? spec_insn_xor_valid : spec_insn_xori_valid ? spec_insn_xori_valid : 0; assign spec_trap = spec_insn_add_valid ? spec_insn_add_trap : spec_insn_addi_valid ? spec_insn_addi_trap : spec_insn_and_valid ? spec_insn_and_trap : spec_insn_andi_valid ? spec_insn_andi_trap : spec_insn_auipc_valid ? spec_insn_auipc_trap : spec_insn_beq_valid ? spec_insn_beq_trap : spec_insn_bge_valid ? spec_insn_bge_trap : spec_insn_bgeu_valid ? spec_insn_bgeu_trap : spec_insn_blt_valid ? spec_insn_blt_trap : spec_insn_bltu_valid ? spec_insn_bltu_trap : spec_insn_bne_valid ? spec_insn_bne_trap : spec_insn_c_add_valid ? spec_insn_c_add_trap : spec_insn_c_addi_valid ? spec_insn_c_addi_trap : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_trap : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_trap : spec_insn_c_and_valid ? spec_insn_c_and_trap : spec_insn_c_andi_valid ? spec_insn_c_andi_trap : spec_insn_c_beqz_valid ? spec_insn_c_beqz_trap : spec_insn_c_bnez_valid ? spec_insn_c_bnez_trap : spec_insn_c_j_valid ? spec_insn_c_j_trap : spec_insn_c_jal_valid ? spec_insn_c_jal_trap : spec_insn_c_jalr_valid ? spec_insn_c_jalr_trap : spec_insn_c_jr_valid ? spec_insn_c_jr_trap : spec_insn_c_li_valid ? spec_insn_c_li_trap : spec_insn_c_lui_valid ? spec_insn_c_lui_trap : spec_insn_c_lw_valid ? spec_insn_c_lw_trap : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_trap : spec_insn_c_mv_valid ? spec_insn_c_mv_trap : spec_insn_c_or_valid ? spec_insn_c_or_trap : spec_insn_c_slli_valid ? spec_insn_c_slli_trap : spec_insn_c_srai_valid ? spec_insn_c_srai_trap : spec_insn_c_srli_valid ? spec_insn_c_srli_trap : spec_insn_c_sub_valid ? spec_insn_c_sub_trap : spec_insn_c_sw_valid ? spec_insn_c_sw_trap : spec_insn_c_swsp_valid ? spec_insn_c_swsp_trap : spec_insn_c_xor_valid ? spec_insn_c_xor_trap : spec_insn_div_valid ? spec_insn_div_trap : spec_insn_divu_valid ? spec_insn_divu_trap : spec_insn_jal_valid ? spec_insn_jal_trap : spec_insn_jalr_valid ? spec_insn_jalr_trap : spec_insn_lb_valid ? spec_insn_lb_trap : spec_insn_lbu_valid ? spec_insn_lbu_trap : spec_insn_lh_valid ? spec_insn_lh_trap : spec_insn_lhu_valid ? spec_insn_lhu_trap : spec_insn_lui_valid ? spec_insn_lui_trap : spec_insn_lw_valid ? spec_insn_lw_trap : spec_insn_mul_valid ? spec_insn_mul_trap : spec_insn_mulh_valid ? spec_insn_mulh_trap : spec_insn_mulhsu_valid ? spec_insn_mulhsu_trap : spec_insn_mulhu_valid ? spec_insn_mulhu_trap : spec_insn_or_valid ? spec_insn_or_trap : spec_insn_ori_valid ? spec_insn_ori_trap : spec_insn_rem_valid ? spec_insn_rem_trap : spec_insn_remu_valid ? spec_insn_remu_trap : spec_insn_sb_valid ? spec_insn_sb_trap : spec_insn_sh_valid ? spec_insn_sh_trap : spec_insn_sll_valid ? spec_insn_sll_trap : spec_insn_slli_valid ? spec_insn_slli_trap : spec_insn_slt_valid ? spec_insn_slt_trap : spec_insn_slti_valid ? spec_insn_slti_trap : spec_insn_sltiu_valid ? spec_insn_sltiu_trap : spec_insn_sltu_valid ? spec_insn_sltu_trap : spec_insn_sra_valid ? spec_insn_sra_trap : spec_insn_srai_valid ? spec_insn_srai_trap : spec_insn_srl_valid ? spec_insn_srl_trap : spec_insn_srli_valid ? spec_insn_srli_trap : spec_insn_sub_valid ? spec_insn_sub_trap : spec_insn_sw_valid ? spec_insn_sw_trap : spec_insn_xor_valid ? spec_insn_xor_trap : spec_insn_xori_valid ? spec_insn_xori_trap : 0; assign spec_rs1_addr = spec_insn_add_valid ? spec_insn_add_rs1_addr : spec_insn_addi_valid ? spec_insn_addi_rs1_addr : spec_insn_and_valid ? spec_insn_and_rs1_addr : spec_insn_andi_valid ? spec_insn_andi_rs1_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : spec_insn_beq_valid ? spec_insn_beq_rs1_addr : spec_insn_bge_valid ? spec_insn_bge_rs1_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : spec_insn_blt_valid ? spec_insn_blt_rs1_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : spec_insn_bne_valid ? spec_insn_bne_rs1_addr : spec_insn_c_add_valid ? spec_insn_c_add_rs1_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_rs1_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs1_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs1_addr : spec_insn_c_and_valid ? spec_insn_c_and_rs1_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_rs1_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rs1_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rs1_addr : spec_insn_c_j_valid ? spec_insn_c_j_rs1_addr : spec_insn_c_jal_valid ? spec_insn_c_jal_rs1_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rs1_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_rs1_addr : spec_insn_c_li_valid ? spec_insn_c_li_rs1_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_rs1_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_rs1_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs1_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_rs1_addr : spec_insn_c_or_valid ? spec_insn_c_or_rs1_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_rs1_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_rs1_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_rs1_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_rs1_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_rs1_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rs1_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_rs1_addr : spec_insn_div_valid ? spec_insn_div_rs1_addr : spec_insn_divu_valid ? spec_insn_divu_rs1_addr : spec_insn_jal_valid ? spec_insn_jal_rs1_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : spec_insn_lb_valid ? spec_insn_lb_rs1_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : spec_insn_lh_valid ? spec_insn_lh_rs1_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : spec_insn_lui_valid ? spec_insn_lui_rs1_addr : spec_insn_lw_valid ? spec_insn_lw_rs1_addr : spec_insn_mul_valid ? spec_insn_mul_rs1_addr : spec_insn_mulh_valid ? spec_insn_mulh_rs1_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rs1_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_rs1_addr : spec_insn_or_valid ? spec_insn_or_rs1_addr : spec_insn_ori_valid ? spec_insn_ori_rs1_addr : spec_insn_rem_valid ? spec_insn_rem_rs1_addr : spec_insn_remu_valid ? spec_insn_remu_rs1_addr : spec_insn_sb_valid ? spec_insn_sb_rs1_addr : spec_insn_sh_valid ? spec_insn_sh_rs1_addr : spec_insn_sll_valid ? spec_insn_sll_rs1_addr : spec_insn_slli_valid ? spec_insn_slli_rs1_addr : spec_insn_slt_valid ? spec_insn_slt_rs1_addr : spec_insn_slti_valid ? spec_insn_slti_rs1_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : spec_insn_sra_valid ? spec_insn_sra_rs1_addr : spec_insn_srai_valid ? spec_insn_srai_rs1_addr : spec_insn_srl_valid ? spec_insn_srl_rs1_addr : spec_insn_srli_valid ? spec_insn_srli_rs1_addr : spec_insn_sub_valid ? spec_insn_sub_rs1_addr : spec_insn_sw_valid ? spec_insn_sw_rs1_addr : spec_insn_xor_valid ? spec_insn_xor_rs1_addr : spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; assign spec_rs2_addr = spec_insn_add_valid ? spec_insn_add_rs2_addr : spec_insn_addi_valid ? spec_insn_addi_rs2_addr : spec_insn_and_valid ? spec_insn_and_rs2_addr : spec_insn_andi_valid ? spec_insn_andi_rs2_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : spec_insn_beq_valid ? spec_insn_beq_rs2_addr : spec_insn_bge_valid ? spec_insn_bge_rs2_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : spec_insn_blt_valid ? spec_insn_blt_rs2_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : spec_insn_bne_valid ? spec_insn_bne_rs2_addr : spec_insn_c_add_valid ? spec_insn_c_add_rs2_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_rs2_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs2_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs2_addr : spec_insn_c_and_valid ? spec_insn_c_and_rs2_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_rs2_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rs2_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rs2_addr : spec_insn_c_j_valid ? spec_insn_c_j_rs2_addr : spec_insn_c_jal_valid ? spec_insn_c_jal_rs2_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rs2_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_rs2_addr : spec_insn_c_li_valid ? spec_insn_c_li_rs2_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_rs2_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_rs2_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs2_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_rs2_addr : spec_insn_c_or_valid ? spec_insn_c_or_rs2_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_rs2_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_rs2_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_rs2_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_rs2_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_rs2_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rs2_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_rs2_addr : spec_insn_div_valid ? spec_insn_div_rs2_addr : spec_insn_divu_valid ? spec_insn_divu_rs2_addr : spec_insn_jal_valid ? spec_insn_jal_rs2_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : spec_insn_lb_valid ? spec_insn_lb_rs2_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : spec_insn_lh_valid ? spec_insn_lh_rs2_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : spec_insn_lui_valid ? spec_insn_lui_rs2_addr : spec_insn_lw_valid ? spec_insn_lw_rs2_addr : spec_insn_mul_valid ? spec_insn_mul_rs2_addr : spec_insn_mulh_valid ? spec_insn_mulh_rs2_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rs2_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_rs2_addr : spec_insn_or_valid ? spec_insn_or_rs2_addr : spec_insn_ori_valid ? spec_insn_ori_rs2_addr : spec_insn_rem_valid ? spec_insn_rem_rs2_addr : spec_insn_remu_valid ? spec_insn_remu_rs2_addr : spec_insn_sb_valid ? spec_insn_sb_rs2_addr : spec_insn_sh_valid ? spec_insn_sh_rs2_addr : spec_insn_sll_valid ? spec_insn_sll_rs2_addr : spec_insn_slli_valid ? spec_insn_slli_rs2_addr : spec_insn_slt_valid ? spec_insn_slt_rs2_addr : spec_insn_slti_valid ? spec_insn_slti_rs2_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : spec_insn_sra_valid ? spec_insn_sra_rs2_addr : spec_insn_srai_valid ? spec_insn_srai_rs2_addr : spec_insn_srl_valid ? spec_insn_srl_rs2_addr : spec_insn_srli_valid ? spec_insn_srli_rs2_addr : spec_insn_sub_valid ? spec_insn_sub_rs2_addr : spec_insn_sw_valid ? spec_insn_sw_rs2_addr : spec_insn_xor_valid ? spec_insn_xor_rs2_addr : spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; assign spec_rd_addr = spec_insn_add_valid ? spec_insn_add_rd_addr : spec_insn_addi_valid ? spec_insn_addi_rd_addr : spec_insn_and_valid ? spec_insn_and_rd_addr : spec_insn_andi_valid ? spec_insn_andi_rd_addr : spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : spec_insn_beq_valid ? spec_insn_beq_rd_addr : spec_insn_bge_valid ? spec_insn_bge_rd_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : spec_insn_blt_valid ? spec_insn_blt_rd_addr : spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : spec_insn_bne_valid ? spec_insn_bne_rd_addr : spec_insn_c_add_valid ? spec_insn_c_add_rd_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_rd_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_addr : spec_insn_c_and_valid ? spec_insn_c_and_rd_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_rd_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_addr : spec_insn_c_j_valid ? spec_insn_c_j_rd_addr : spec_insn_c_jal_valid ? spec_insn_c_jal_rd_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_rd_addr : spec_insn_c_li_valid ? spec_insn_c_li_rd_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_rd_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_rd_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_rd_addr : spec_insn_c_or_valid ? spec_insn_c_or_rd_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_rd_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_rd_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_rd_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_rd_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_rd_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_rd_addr : spec_insn_div_valid ? spec_insn_div_rd_addr : spec_insn_divu_valid ? spec_insn_divu_rd_addr : spec_insn_jal_valid ? spec_insn_jal_rd_addr : spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : spec_insn_lb_valid ? spec_insn_lb_rd_addr : spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : spec_insn_lh_valid ? spec_insn_lh_rd_addr : spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : spec_insn_lui_valid ? spec_insn_lui_rd_addr : spec_insn_lw_valid ? spec_insn_lw_rd_addr : spec_insn_mul_valid ? spec_insn_mul_rd_addr : spec_insn_mulh_valid ? spec_insn_mulh_rd_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_rd_addr : spec_insn_or_valid ? spec_insn_or_rd_addr : spec_insn_ori_valid ? spec_insn_ori_rd_addr : spec_insn_rem_valid ? spec_insn_rem_rd_addr : spec_insn_remu_valid ? spec_insn_remu_rd_addr : spec_insn_sb_valid ? spec_insn_sb_rd_addr : spec_insn_sh_valid ? spec_insn_sh_rd_addr : spec_insn_sll_valid ? spec_insn_sll_rd_addr : spec_insn_slli_valid ? spec_insn_slli_rd_addr : spec_insn_slt_valid ? spec_insn_slt_rd_addr : spec_insn_slti_valid ? spec_insn_slti_rd_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : spec_insn_sra_valid ? spec_insn_sra_rd_addr : spec_insn_srai_valid ? spec_insn_srai_rd_addr : spec_insn_srl_valid ? spec_insn_srl_rd_addr : spec_insn_srli_valid ? spec_insn_srli_rd_addr : spec_insn_sub_valid ? spec_insn_sub_rd_addr : spec_insn_sw_valid ? spec_insn_sw_rd_addr : spec_insn_xor_valid ? spec_insn_xor_rd_addr : spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; assign spec_rd_wdata = spec_insn_add_valid ? spec_insn_add_rd_wdata : spec_insn_addi_valid ? spec_insn_addi_rd_wdata : spec_insn_and_valid ? spec_insn_and_rd_wdata : spec_insn_andi_valid ? spec_insn_andi_rd_wdata : spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : spec_insn_beq_valid ? spec_insn_beq_rd_wdata : spec_insn_bge_valid ? spec_insn_bge_rd_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : spec_insn_blt_valid ? spec_insn_blt_rd_wdata : spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : spec_insn_bne_valid ? spec_insn_bne_rd_wdata : spec_insn_c_add_valid ? spec_insn_c_add_rd_wdata : spec_insn_c_addi_valid ? spec_insn_c_addi_rd_wdata : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_wdata : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_wdata : spec_insn_c_and_valid ? spec_insn_c_and_rd_wdata : spec_insn_c_andi_valid ? spec_insn_c_andi_rd_wdata : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_wdata : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_wdata : spec_insn_c_j_valid ? spec_insn_c_j_rd_wdata : spec_insn_c_jal_valid ? spec_insn_c_jal_rd_wdata : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_wdata : spec_insn_c_jr_valid ? spec_insn_c_jr_rd_wdata : spec_insn_c_li_valid ? spec_insn_c_li_rd_wdata : spec_insn_c_lui_valid ? spec_insn_c_lui_rd_wdata : spec_insn_c_lw_valid ? spec_insn_c_lw_rd_wdata : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_wdata : spec_insn_c_mv_valid ? spec_insn_c_mv_rd_wdata : spec_insn_c_or_valid ? spec_insn_c_or_rd_wdata : spec_insn_c_slli_valid ? spec_insn_c_slli_rd_wdata : spec_insn_c_srai_valid ? spec_insn_c_srai_rd_wdata : spec_insn_c_srli_valid ? spec_insn_c_srli_rd_wdata : spec_insn_c_sub_valid ? spec_insn_c_sub_rd_wdata : spec_insn_c_sw_valid ? spec_insn_c_sw_rd_wdata : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_wdata : spec_insn_c_xor_valid ? spec_insn_c_xor_rd_wdata : spec_insn_div_valid ? spec_insn_div_rd_wdata : spec_insn_divu_valid ? spec_insn_divu_rd_wdata : spec_insn_jal_valid ? spec_insn_jal_rd_wdata : spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : spec_insn_lb_valid ? spec_insn_lb_rd_wdata : spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : spec_insn_lh_valid ? spec_insn_lh_rd_wdata : spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : spec_insn_lui_valid ? spec_insn_lui_rd_wdata : spec_insn_lw_valid ? spec_insn_lw_rd_wdata : spec_insn_mul_valid ? spec_insn_mul_rd_wdata : spec_insn_mulh_valid ? spec_insn_mulh_rd_wdata : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_wdata : spec_insn_mulhu_valid ? spec_insn_mulhu_rd_wdata : spec_insn_or_valid ? spec_insn_or_rd_wdata : spec_insn_ori_valid ? spec_insn_ori_rd_wdata : spec_insn_rem_valid ? spec_insn_rem_rd_wdata : spec_insn_remu_valid ? spec_insn_remu_rd_wdata : spec_insn_sb_valid ? spec_insn_sb_rd_wdata : spec_insn_sh_valid ? spec_insn_sh_rd_wdata : spec_insn_sll_valid ? spec_insn_sll_rd_wdata : spec_insn_slli_valid ? spec_insn_slli_rd_wdata : spec_insn_slt_valid ? spec_insn_slt_rd_wdata : spec_insn_slti_valid ? spec_insn_slti_rd_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : spec_insn_sra_valid ? spec_insn_sra_rd_wdata : spec_insn_srai_valid ? spec_insn_srai_rd_wdata : spec_insn_srl_valid ? spec_insn_srl_rd_wdata : spec_insn_srli_valid ? spec_insn_srli_rd_wdata : spec_insn_sub_valid ? spec_insn_sub_rd_wdata : spec_insn_sw_valid ? spec_insn_sw_rd_wdata : spec_insn_xor_valid ? spec_insn_xor_rd_wdata : spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; assign spec_pc_wdata = spec_insn_add_valid ? spec_insn_add_pc_wdata : spec_insn_addi_valid ? spec_insn_addi_pc_wdata : spec_insn_and_valid ? spec_insn_and_pc_wdata : spec_insn_andi_valid ? spec_insn_andi_pc_wdata : spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : spec_insn_beq_valid ? spec_insn_beq_pc_wdata : spec_insn_bge_valid ? spec_insn_bge_pc_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : spec_insn_blt_valid ? spec_insn_blt_pc_wdata : spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : spec_insn_bne_valid ? spec_insn_bne_pc_wdata : spec_insn_c_add_valid ? spec_insn_c_add_pc_wdata : spec_insn_c_addi_valid ? spec_insn_c_addi_pc_wdata : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_pc_wdata : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_pc_wdata : spec_insn_c_and_valid ? spec_insn_c_and_pc_wdata : spec_insn_c_andi_valid ? spec_insn_c_andi_pc_wdata : spec_insn_c_beqz_valid ? spec_insn_c_beqz_pc_wdata : spec_insn_c_bnez_valid ? spec_insn_c_bnez_pc_wdata : spec_insn_c_j_valid ? spec_insn_c_j_pc_wdata : spec_insn_c_jal_valid ? spec_insn_c_jal_pc_wdata : spec_insn_c_jalr_valid ? spec_insn_c_jalr_pc_wdata : spec_insn_c_jr_valid ? spec_insn_c_jr_pc_wdata : spec_insn_c_li_valid ? spec_insn_c_li_pc_wdata : spec_insn_c_lui_valid ? spec_insn_c_lui_pc_wdata : spec_insn_c_lw_valid ? spec_insn_c_lw_pc_wdata : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_pc_wdata : spec_insn_c_mv_valid ? spec_insn_c_mv_pc_wdata : spec_insn_c_or_valid ? spec_insn_c_or_pc_wdata : spec_insn_c_slli_valid ? spec_insn_c_slli_pc_wdata : spec_insn_c_srai_valid ? spec_insn_c_srai_pc_wdata : spec_insn_c_srli_valid ? spec_insn_c_srli_pc_wdata : spec_insn_c_sub_valid ? spec_insn_c_sub_pc_wdata : spec_insn_c_sw_valid ? spec_insn_c_sw_pc_wdata : spec_insn_c_swsp_valid ? spec_insn_c_swsp_pc_wdata : spec_insn_c_xor_valid ? spec_insn_c_xor_pc_wdata : spec_insn_div_valid ? spec_insn_div_pc_wdata : spec_insn_divu_valid ? spec_insn_divu_pc_wdata : spec_insn_jal_valid ? spec_insn_jal_pc_wdata : spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : spec_insn_lb_valid ? spec_insn_lb_pc_wdata : spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : spec_insn_lh_valid ? spec_insn_lh_pc_wdata : spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : spec_insn_lui_valid ? spec_insn_lui_pc_wdata : spec_insn_lw_valid ? spec_insn_lw_pc_wdata : spec_insn_mul_valid ? spec_insn_mul_pc_wdata : spec_insn_mulh_valid ? spec_insn_mulh_pc_wdata : spec_insn_mulhsu_valid ? spec_insn_mulhsu_pc_wdata : spec_insn_mulhu_valid ? spec_insn_mulhu_pc_wdata : spec_insn_or_valid ? spec_insn_or_pc_wdata : spec_insn_ori_valid ? spec_insn_ori_pc_wdata : spec_insn_rem_valid ? spec_insn_rem_pc_wdata : spec_insn_remu_valid ? spec_insn_remu_pc_wdata : spec_insn_sb_valid ? spec_insn_sb_pc_wdata : spec_insn_sh_valid ? spec_insn_sh_pc_wdata : spec_insn_sll_valid ? spec_insn_sll_pc_wdata : spec_insn_slli_valid ? spec_insn_slli_pc_wdata : spec_insn_slt_valid ? spec_insn_slt_pc_wdata : spec_insn_slti_valid ? spec_insn_slti_pc_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : spec_insn_sra_valid ? spec_insn_sra_pc_wdata : spec_insn_srai_valid ? spec_insn_srai_pc_wdata : spec_insn_srl_valid ? spec_insn_srl_pc_wdata : spec_insn_srli_valid ? spec_insn_srli_pc_wdata : spec_insn_sub_valid ? spec_insn_sub_pc_wdata : spec_insn_sw_valid ? spec_insn_sw_pc_wdata : spec_insn_xor_valid ? spec_insn_xor_pc_wdata : spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; assign spec_mem_addr = spec_insn_add_valid ? spec_insn_add_mem_addr : spec_insn_addi_valid ? spec_insn_addi_mem_addr : spec_insn_and_valid ? spec_insn_and_mem_addr : spec_insn_andi_valid ? spec_insn_andi_mem_addr : spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : spec_insn_beq_valid ? spec_insn_beq_mem_addr : spec_insn_bge_valid ? spec_insn_bge_mem_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : spec_insn_blt_valid ? spec_insn_blt_mem_addr : spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : spec_insn_bne_valid ? spec_insn_bne_mem_addr : spec_insn_c_add_valid ? spec_insn_c_add_mem_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_addr : spec_insn_c_and_valid ? spec_insn_c_and_mem_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_addr : spec_insn_c_j_valid ? spec_insn_c_j_mem_addr : spec_insn_c_jal_valid ? spec_insn_c_jal_mem_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_addr : spec_insn_c_li_valid ? spec_insn_c_li_mem_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_addr : spec_insn_c_or_valid ? spec_insn_c_or_mem_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_addr : spec_insn_div_valid ? spec_insn_div_mem_addr : spec_insn_divu_valid ? spec_insn_divu_mem_addr : spec_insn_jal_valid ? spec_insn_jal_mem_addr : spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : spec_insn_lb_valid ? spec_insn_lb_mem_addr : spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : spec_insn_lh_valid ? spec_insn_lh_mem_addr : spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : spec_insn_lui_valid ? spec_insn_lui_mem_addr : spec_insn_lw_valid ? spec_insn_lw_mem_addr : spec_insn_mul_valid ? spec_insn_mul_mem_addr : spec_insn_mulh_valid ? spec_insn_mulh_mem_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_addr : spec_insn_or_valid ? spec_insn_or_mem_addr : spec_insn_ori_valid ? spec_insn_ori_mem_addr : spec_insn_rem_valid ? spec_insn_rem_mem_addr : spec_insn_remu_valid ? spec_insn_remu_mem_addr : spec_insn_sb_valid ? spec_insn_sb_mem_addr : spec_insn_sh_valid ? spec_insn_sh_mem_addr : spec_insn_sll_valid ? spec_insn_sll_mem_addr : spec_insn_slli_valid ? spec_insn_slli_mem_addr : spec_insn_slt_valid ? spec_insn_slt_mem_addr : spec_insn_slti_valid ? spec_insn_slti_mem_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : spec_insn_sra_valid ? spec_insn_sra_mem_addr : spec_insn_srai_valid ? spec_insn_srai_mem_addr : spec_insn_srl_valid ? spec_insn_srl_mem_addr : spec_insn_srli_valid ? spec_insn_srli_mem_addr : spec_insn_sub_valid ? spec_insn_sub_mem_addr : spec_insn_sw_valid ? spec_insn_sw_mem_addr : spec_insn_xor_valid ? spec_insn_xor_mem_addr : spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; assign spec_mem_rmask = spec_insn_add_valid ? spec_insn_add_mem_rmask : spec_insn_addi_valid ? spec_insn_addi_mem_rmask : spec_insn_and_valid ? spec_insn_and_mem_rmask : spec_insn_andi_valid ? spec_insn_andi_mem_rmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : spec_insn_beq_valid ? spec_insn_beq_mem_rmask : spec_insn_bge_valid ? spec_insn_bge_mem_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : spec_insn_blt_valid ? spec_insn_blt_mem_rmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : spec_insn_bne_valid ? spec_insn_bne_mem_rmask : spec_insn_c_add_valid ? spec_insn_c_add_mem_rmask : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_rmask : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_rmask : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_rmask : spec_insn_c_and_valid ? spec_insn_c_and_mem_rmask : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_rmask : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_rmask : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_rmask : spec_insn_c_j_valid ? spec_insn_c_j_mem_rmask : spec_insn_c_jal_valid ? spec_insn_c_jal_mem_rmask : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_rmask : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_rmask : spec_insn_c_li_valid ? spec_insn_c_li_mem_rmask : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_rmask : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_rmask : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_rmask : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_rmask : spec_insn_c_or_valid ? spec_insn_c_or_mem_rmask : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_rmask : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_rmask : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_rmask : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_rmask : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_rmask : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_rmask : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_rmask : spec_insn_div_valid ? spec_insn_div_mem_rmask : spec_insn_divu_valid ? spec_insn_divu_mem_rmask : spec_insn_jal_valid ? spec_insn_jal_mem_rmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : spec_insn_lb_valid ? spec_insn_lb_mem_rmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : spec_insn_lh_valid ? spec_insn_lh_mem_rmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : spec_insn_lui_valid ? spec_insn_lui_mem_rmask : spec_insn_lw_valid ? spec_insn_lw_mem_rmask : spec_insn_mul_valid ? spec_insn_mul_mem_rmask : spec_insn_mulh_valid ? spec_insn_mulh_mem_rmask : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_rmask : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_rmask : spec_insn_or_valid ? spec_insn_or_mem_rmask : spec_insn_ori_valid ? spec_insn_ori_mem_rmask : spec_insn_rem_valid ? spec_insn_rem_mem_rmask : spec_insn_remu_valid ? spec_insn_remu_mem_rmask : spec_insn_sb_valid ? spec_insn_sb_mem_rmask : spec_insn_sh_valid ? spec_insn_sh_mem_rmask : spec_insn_sll_valid ? spec_insn_sll_mem_rmask : spec_insn_slli_valid ? spec_insn_slli_mem_rmask : spec_insn_slt_valid ? spec_insn_slt_mem_rmask : spec_insn_slti_valid ? spec_insn_slti_mem_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : spec_insn_sra_valid ? spec_insn_sra_mem_rmask : spec_insn_srai_valid ? spec_insn_srai_mem_rmask : spec_insn_srl_valid ? spec_insn_srl_mem_rmask : spec_insn_srli_valid ? spec_insn_srli_mem_rmask : spec_insn_sub_valid ? spec_insn_sub_mem_rmask : spec_insn_sw_valid ? spec_insn_sw_mem_rmask : spec_insn_xor_valid ? spec_insn_xor_mem_rmask : spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; assign spec_mem_wmask = spec_insn_add_valid ? spec_insn_add_mem_wmask : spec_insn_addi_valid ? spec_insn_addi_mem_wmask : spec_insn_and_valid ? spec_insn_and_mem_wmask : spec_insn_andi_valid ? spec_insn_andi_mem_wmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : spec_insn_beq_valid ? spec_insn_beq_mem_wmask : spec_insn_bge_valid ? spec_insn_bge_mem_wmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : spec_insn_blt_valid ? spec_insn_blt_mem_wmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : spec_insn_bne_valid ? spec_insn_bne_mem_wmask : spec_insn_c_add_valid ? spec_insn_c_add_mem_wmask : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_wmask : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wmask : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wmask : spec_insn_c_and_valid ? spec_insn_c_and_mem_wmask : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_wmask : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wmask : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wmask : spec_insn_c_j_valid ? spec_insn_c_j_mem_wmask : spec_insn_c_jal_valid ? spec_insn_c_jal_mem_wmask : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wmask : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_wmask : spec_insn_c_li_valid ? spec_insn_c_li_mem_wmask : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_wmask : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_wmask : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wmask : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_wmask : spec_insn_c_or_valid ? spec_insn_c_or_mem_wmask : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_wmask : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_wmask : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_wmask : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_wmask : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_wmask : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wmask : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_wmask : spec_insn_div_valid ? spec_insn_div_mem_wmask : spec_insn_divu_valid ? spec_insn_divu_mem_wmask : spec_insn_jal_valid ? spec_insn_jal_mem_wmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : spec_insn_lb_valid ? spec_insn_lb_mem_wmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : spec_insn_lh_valid ? spec_insn_lh_mem_wmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : spec_insn_lui_valid ? spec_insn_lui_mem_wmask : spec_insn_lw_valid ? spec_insn_lw_mem_wmask : spec_insn_mul_valid ? spec_insn_mul_mem_wmask : spec_insn_mulh_valid ? spec_insn_mulh_mem_wmask : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wmask : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_wmask : spec_insn_or_valid ? spec_insn_or_mem_wmask : spec_insn_ori_valid ? spec_insn_ori_mem_wmask : spec_insn_rem_valid ? spec_insn_rem_mem_wmask : spec_insn_remu_valid ? spec_insn_remu_mem_wmask : spec_insn_sb_valid ? spec_insn_sb_mem_wmask : spec_insn_sh_valid ? spec_insn_sh_mem_wmask : spec_insn_sll_valid ? spec_insn_sll_mem_wmask : spec_insn_slli_valid ? spec_insn_slli_mem_wmask : spec_insn_slt_valid ? spec_insn_slt_mem_wmask : spec_insn_slti_valid ? spec_insn_slti_mem_wmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : spec_insn_sra_valid ? spec_insn_sra_mem_wmask : spec_insn_srai_valid ? spec_insn_srai_mem_wmask : spec_insn_srl_valid ? spec_insn_srl_mem_wmask : spec_insn_srli_valid ? spec_insn_srli_mem_wmask : spec_insn_sub_valid ? spec_insn_sub_mem_wmask : spec_insn_sw_valid ? spec_insn_sw_mem_wmask : spec_insn_xor_valid ? spec_insn_xor_mem_wmask : spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; assign spec_mem_wdata = spec_insn_add_valid ? spec_insn_add_mem_wdata : spec_insn_addi_valid ? spec_insn_addi_mem_wdata : spec_insn_and_valid ? spec_insn_and_mem_wdata : spec_insn_andi_valid ? spec_insn_andi_mem_wdata : spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : spec_insn_beq_valid ? spec_insn_beq_mem_wdata : spec_insn_bge_valid ? spec_insn_bge_mem_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : spec_insn_blt_valid ? spec_insn_blt_mem_wdata : spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : spec_insn_bne_valid ? spec_insn_bne_mem_wdata : spec_insn_c_add_valid ? spec_insn_c_add_mem_wdata : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_wdata : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wdata : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wdata : spec_insn_c_and_valid ? spec_insn_c_and_mem_wdata : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_wdata : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wdata : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wdata : spec_insn_c_j_valid ? spec_insn_c_j_mem_wdata : spec_insn_c_jal_valid ? spec_insn_c_jal_mem_wdata : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wdata : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_wdata : spec_insn_c_li_valid ? spec_insn_c_li_mem_wdata : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_wdata : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_wdata : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wdata : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_wdata : spec_insn_c_or_valid ? spec_insn_c_or_mem_wdata : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_wdata : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_wdata : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_wdata : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_wdata : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_wdata : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wdata : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_wdata : spec_insn_div_valid ? spec_insn_div_mem_wdata : spec_insn_divu_valid ? spec_insn_divu_mem_wdata : spec_insn_jal_valid ? spec_insn_jal_mem_wdata : spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : spec_insn_lb_valid ? spec_insn_lb_mem_wdata : spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : spec_insn_lh_valid ? spec_insn_lh_mem_wdata : spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : spec_insn_lui_valid ? spec_insn_lui_mem_wdata : spec_insn_lw_valid ? spec_insn_lw_mem_wdata : spec_insn_mul_valid ? spec_insn_mul_mem_wdata : spec_insn_mulh_valid ? spec_insn_mulh_mem_wdata : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wdata : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_wdata : spec_insn_or_valid ? spec_insn_or_mem_wdata : spec_insn_ori_valid ? spec_insn_ori_mem_wdata : spec_insn_rem_valid ? spec_insn_rem_mem_wdata : spec_insn_remu_valid ? spec_insn_remu_mem_wdata : spec_insn_sb_valid ? spec_insn_sb_mem_wdata : spec_insn_sh_valid ? spec_insn_sh_mem_wdata : spec_insn_sll_valid ? spec_insn_sll_mem_wdata : spec_insn_slli_valid ? spec_insn_slli_mem_wdata : spec_insn_slt_valid ? spec_insn_slt_mem_wdata : spec_insn_slti_valid ? spec_insn_slti_mem_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : spec_insn_sra_valid ? spec_insn_sra_mem_wdata : spec_insn_srai_valid ? spec_insn_srai_mem_wdata : spec_insn_srl_valid ? spec_insn_srl_mem_wdata : spec_insn_srli_valid ? spec_insn_srli_mem_wdata : spec_insn_sub_valid ? spec_insn_sub_mem_wdata : spec_insn_sw_valid ? spec_insn_sw_mem_wdata : spec_insn_xor_valid ? spec_insn_xor_mem_wdata : spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; `ifdef RISCV_FORMAL_CSR_MISA assign spec_csr_misa_rmask = spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : spec_insn_c_add_valid ? spec_insn_c_add_csr_misa_rmask : spec_insn_c_addi_valid ? spec_insn_c_addi_csr_misa_rmask : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_csr_misa_rmask : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_csr_misa_rmask : spec_insn_c_and_valid ? spec_insn_c_and_csr_misa_rmask : spec_insn_c_andi_valid ? spec_insn_c_andi_csr_misa_rmask : spec_insn_c_beqz_valid ? spec_insn_c_beqz_csr_misa_rmask : spec_insn_c_bnez_valid ? spec_insn_c_bnez_csr_misa_rmask : spec_insn_c_j_valid ? spec_insn_c_j_csr_misa_rmask : spec_insn_c_jal_valid ? spec_insn_c_jal_csr_misa_rmask : spec_insn_c_jalr_valid ? spec_insn_c_jalr_csr_misa_rmask : spec_insn_c_jr_valid ? spec_insn_c_jr_csr_misa_rmask : spec_insn_c_li_valid ? spec_insn_c_li_csr_misa_rmask : spec_insn_c_lui_valid ? spec_insn_c_lui_csr_misa_rmask : spec_insn_c_lw_valid ? spec_insn_c_lw_csr_misa_rmask : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_csr_misa_rmask : spec_insn_c_mv_valid ? spec_insn_c_mv_csr_misa_rmask : spec_insn_c_or_valid ? spec_insn_c_or_csr_misa_rmask : spec_insn_c_slli_valid ? spec_insn_c_slli_csr_misa_rmask : spec_insn_c_srai_valid ? spec_insn_c_srai_csr_misa_rmask : spec_insn_c_srli_valid ? spec_insn_c_srli_csr_misa_rmask : spec_insn_c_sub_valid ? spec_insn_c_sub_csr_misa_rmask : spec_insn_c_sw_valid ? spec_insn_c_sw_csr_misa_rmask : spec_insn_c_swsp_valid ? spec_insn_c_swsp_csr_misa_rmask : spec_insn_c_xor_valid ? spec_insn_c_xor_csr_misa_rmask : spec_insn_div_valid ? spec_insn_div_csr_misa_rmask : spec_insn_divu_valid ? spec_insn_divu_csr_misa_rmask : spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : spec_insn_mul_valid ? spec_insn_mul_csr_misa_rmask : spec_insn_mulh_valid ? spec_insn_mulh_csr_misa_rmask : spec_insn_mulhsu_valid ? spec_insn_mulhsu_csr_misa_rmask : spec_insn_mulhu_valid ? spec_insn_mulhu_csr_misa_rmask : spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : spec_insn_rem_valid ? spec_insn_rem_csr_misa_rmask : spec_insn_remu_valid ? spec_insn_remu_csr_misa_rmask : spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; `endif endmodule ================================================ FILE: insns/isa_rv64i.txt ================================================ add addi addiw addw and andi auipc beq bge bgeu blt bltu bne jal jalr lb lbu ld lh lhu lui lw lwu or ori sb sd sh sll slli slliw sllw slt slti sltiu sltu sra srai sraiw sraw srl srli srliw srlw sub subw sw xor xori ================================================ FILE: insns/isa_rv64i.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_isa_rv64i ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); wire spec_insn_add_valid; wire spec_insn_add_trap; wire [ 4 : 0] spec_insn_add_rs1_addr; wire [ 4 : 0] spec_insn_add_rs2_addr; wire [ 4 : 0] spec_insn_add_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; `endif rvfi_insn_add insn_add ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), `endif .spec_valid(spec_insn_add_valid), .spec_trap(spec_insn_add_trap), .spec_rs1_addr(spec_insn_add_rs1_addr), .spec_rs2_addr(spec_insn_add_rs2_addr), .spec_rd_addr(spec_insn_add_rd_addr), .spec_rd_wdata(spec_insn_add_rd_wdata), .spec_pc_wdata(spec_insn_add_pc_wdata), .spec_mem_addr(spec_insn_add_mem_addr), .spec_mem_rmask(spec_insn_add_mem_rmask), .spec_mem_wmask(spec_insn_add_mem_wmask), .spec_mem_wdata(spec_insn_add_mem_wdata) ); wire spec_insn_addi_valid; wire spec_insn_addi_trap; wire [ 4 : 0] spec_insn_addi_rs1_addr; wire [ 4 : 0] spec_insn_addi_rs2_addr; wire [ 4 : 0] spec_insn_addi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; `endif rvfi_insn_addi insn_addi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), `endif .spec_valid(spec_insn_addi_valid), .spec_trap(spec_insn_addi_trap), .spec_rs1_addr(spec_insn_addi_rs1_addr), .spec_rs2_addr(spec_insn_addi_rs2_addr), .spec_rd_addr(spec_insn_addi_rd_addr), .spec_rd_wdata(spec_insn_addi_rd_wdata), .spec_pc_wdata(spec_insn_addi_pc_wdata), .spec_mem_addr(spec_insn_addi_mem_addr), .spec_mem_rmask(spec_insn_addi_mem_rmask), .spec_mem_wmask(spec_insn_addi_mem_wmask), .spec_mem_wdata(spec_insn_addi_mem_wdata) ); wire spec_insn_addiw_valid; wire spec_insn_addiw_trap; wire [ 4 : 0] spec_insn_addiw_rs1_addr; wire [ 4 : 0] spec_insn_addiw_rs2_addr; wire [ 4 : 0] spec_insn_addiw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_csr_misa_rmask; `endif rvfi_insn_addiw insn_addiw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addiw_csr_misa_rmask), `endif .spec_valid(spec_insn_addiw_valid), .spec_trap(spec_insn_addiw_trap), .spec_rs1_addr(spec_insn_addiw_rs1_addr), .spec_rs2_addr(spec_insn_addiw_rs2_addr), .spec_rd_addr(spec_insn_addiw_rd_addr), .spec_rd_wdata(spec_insn_addiw_rd_wdata), .spec_pc_wdata(spec_insn_addiw_pc_wdata), .spec_mem_addr(spec_insn_addiw_mem_addr), .spec_mem_rmask(spec_insn_addiw_mem_rmask), .spec_mem_wmask(spec_insn_addiw_mem_wmask), .spec_mem_wdata(spec_insn_addiw_mem_wdata) ); wire spec_insn_addw_valid; wire spec_insn_addw_trap; wire [ 4 : 0] spec_insn_addw_rs1_addr; wire [ 4 : 0] spec_insn_addw_rs2_addr; wire [ 4 : 0] spec_insn_addw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_csr_misa_rmask; `endif rvfi_insn_addw insn_addw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addw_csr_misa_rmask), `endif .spec_valid(spec_insn_addw_valid), .spec_trap(spec_insn_addw_trap), .spec_rs1_addr(spec_insn_addw_rs1_addr), .spec_rs2_addr(spec_insn_addw_rs2_addr), .spec_rd_addr(spec_insn_addw_rd_addr), .spec_rd_wdata(spec_insn_addw_rd_wdata), .spec_pc_wdata(spec_insn_addw_pc_wdata), .spec_mem_addr(spec_insn_addw_mem_addr), .spec_mem_rmask(spec_insn_addw_mem_rmask), .spec_mem_wmask(spec_insn_addw_mem_wmask), .spec_mem_wdata(spec_insn_addw_mem_wdata) ); wire spec_insn_and_valid; wire spec_insn_and_trap; wire [ 4 : 0] spec_insn_and_rs1_addr; wire [ 4 : 0] spec_insn_and_rs2_addr; wire [ 4 : 0] spec_insn_and_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; `endif rvfi_insn_and insn_and ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), `endif .spec_valid(spec_insn_and_valid), .spec_trap(spec_insn_and_trap), .spec_rs1_addr(spec_insn_and_rs1_addr), .spec_rs2_addr(spec_insn_and_rs2_addr), .spec_rd_addr(spec_insn_and_rd_addr), .spec_rd_wdata(spec_insn_and_rd_wdata), .spec_pc_wdata(spec_insn_and_pc_wdata), .spec_mem_addr(spec_insn_and_mem_addr), .spec_mem_rmask(spec_insn_and_mem_rmask), .spec_mem_wmask(spec_insn_and_mem_wmask), .spec_mem_wdata(spec_insn_and_mem_wdata) ); wire spec_insn_andi_valid; wire spec_insn_andi_trap; wire [ 4 : 0] spec_insn_andi_rs1_addr; wire [ 4 : 0] spec_insn_andi_rs2_addr; wire [ 4 : 0] spec_insn_andi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; `endif rvfi_insn_andi insn_andi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), `endif .spec_valid(spec_insn_andi_valid), .spec_trap(spec_insn_andi_trap), .spec_rs1_addr(spec_insn_andi_rs1_addr), .spec_rs2_addr(spec_insn_andi_rs2_addr), .spec_rd_addr(spec_insn_andi_rd_addr), .spec_rd_wdata(spec_insn_andi_rd_wdata), .spec_pc_wdata(spec_insn_andi_pc_wdata), .spec_mem_addr(spec_insn_andi_mem_addr), .spec_mem_rmask(spec_insn_andi_mem_rmask), .spec_mem_wmask(spec_insn_andi_mem_wmask), .spec_mem_wdata(spec_insn_andi_mem_wdata) ); wire spec_insn_auipc_valid; wire spec_insn_auipc_trap; wire [ 4 : 0] spec_insn_auipc_rs1_addr; wire [ 4 : 0] spec_insn_auipc_rs2_addr; wire [ 4 : 0] spec_insn_auipc_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; `endif rvfi_insn_auipc insn_auipc ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), `endif .spec_valid(spec_insn_auipc_valid), .spec_trap(spec_insn_auipc_trap), .spec_rs1_addr(spec_insn_auipc_rs1_addr), .spec_rs2_addr(spec_insn_auipc_rs2_addr), .spec_rd_addr(spec_insn_auipc_rd_addr), .spec_rd_wdata(spec_insn_auipc_rd_wdata), .spec_pc_wdata(spec_insn_auipc_pc_wdata), .spec_mem_addr(spec_insn_auipc_mem_addr), .spec_mem_rmask(spec_insn_auipc_mem_rmask), .spec_mem_wmask(spec_insn_auipc_mem_wmask), .spec_mem_wdata(spec_insn_auipc_mem_wdata) ); wire spec_insn_beq_valid; wire spec_insn_beq_trap; wire [ 4 : 0] spec_insn_beq_rs1_addr; wire [ 4 : 0] spec_insn_beq_rs2_addr; wire [ 4 : 0] spec_insn_beq_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; `endif rvfi_insn_beq insn_beq ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), `endif .spec_valid(spec_insn_beq_valid), .spec_trap(spec_insn_beq_trap), .spec_rs1_addr(spec_insn_beq_rs1_addr), .spec_rs2_addr(spec_insn_beq_rs2_addr), .spec_rd_addr(spec_insn_beq_rd_addr), .spec_rd_wdata(spec_insn_beq_rd_wdata), .spec_pc_wdata(spec_insn_beq_pc_wdata), .spec_mem_addr(spec_insn_beq_mem_addr), .spec_mem_rmask(spec_insn_beq_mem_rmask), .spec_mem_wmask(spec_insn_beq_mem_wmask), .spec_mem_wdata(spec_insn_beq_mem_wdata) ); wire spec_insn_bge_valid; wire spec_insn_bge_trap; wire [ 4 : 0] spec_insn_bge_rs1_addr; wire [ 4 : 0] spec_insn_bge_rs2_addr; wire [ 4 : 0] spec_insn_bge_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; `endif rvfi_insn_bge insn_bge ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), `endif .spec_valid(spec_insn_bge_valid), .spec_trap(spec_insn_bge_trap), .spec_rs1_addr(spec_insn_bge_rs1_addr), .spec_rs2_addr(spec_insn_bge_rs2_addr), .spec_rd_addr(spec_insn_bge_rd_addr), .spec_rd_wdata(spec_insn_bge_rd_wdata), .spec_pc_wdata(spec_insn_bge_pc_wdata), .spec_mem_addr(spec_insn_bge_mem_addr), .spec_mem_rmask(spec_insn_bge_mem_rmask), .spec_mem_wmask(spec_insn_bge_mem_wmask), .spec_mem_wdata(spec_insn_bge_mem_wdata) ); wire spec_insn_bgeu_valid; wire spec_insn_bgeu_trap; wire [ 4 : 0] spec_insn_bgeu_rs1_addr; wire [ 4 : 0] spec_insn_bgeu_rs2_addr; wire [ 4 : 0] spec_insn_bgeu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; `endif rvfi_insn_bgeu insn_bgeu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), `endif .spec_valid(spec_insn_bgeu_valid), .spec_trap(spec_insn_bgeu_trap), .spec_rs1_addr(spec_insn_bgeu_rs1_addr), .spec_rs2_addr(spec_insn_bgeu_rs2_addr), .spec_rd_addr(spec_insn_bgeu_rd_addr), .spec_rd_wdata(spec_insn_bgeu_rd_wdata), .spec_pc_wdata(spec_insn_bgeu_pc_wdata), .spec_mem_addr(spec_insn_bgeu_mem_addr), .spec_mem_rmask(spec_insn_bgeu_mem_rmask), .spec_mem_wmask(spec_insn_bgeu_mem_wmask), .spec_mem_wdata(spec_insn_bgeu_mem_wdata) ); wire spec_insn_blt_valid; wire spec_insn_blt_trap; wire [ 4 : 0] spec_insn_blt_rs1_addr; wire [ 4 : 0] spec_insn_blt_rs2_addr; wire [ 4 : 0] spec_insn_blt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; `endif rvfi_insn_blt insn_blt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), `endif .spec_valid(spec_insn_blt_valid), .spec_trap(spec_insn_blt_trap), .spec_rs1_addr(spec_insn_blt_rs1_addr), .spec_rs2_addr(spec_insn_blt_rs2_addr), .spec_rd_addr(spec_insn_blt_rd_addr), .spec_rd_wdata(spec_insn_blt_rd_wdata), .spec_pc_wdata(spec_insn_blt_pc_wdata), .spec_mem_addr(spec_insn_blt_mem_addr), .spec_mem_rmask(spec_insn_blt_mem_rmask), .spec_mem_wmask(spec_insn_blt_mem_wmask), .spec_mem_wdata(spec_insn_blt_mem_wdata) ); wire spec_insn_bltu_valid; wire spec_insn_bltu_trap; wire [ 4 : 0] spec_insn_bltu_rs1_addr; wire [ 4 : 0] spec_insn_bltu_rs2_addr; wire [ 4 : 0] spec_insn_bltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; `endif rvfi_insn_bltu insn_bltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), `endif .spec_valid(spec_insn_bltu_valid), .spec_trap(spec_insn_bltu_trap), .spec_rs1_addr(spec_insn_bltu_rs1_addr), .spec_rs2_addr(spec_insn_bltu_rs2_addr), .spec_rd_addr(spec_insn_bltu_rd_addr), .spec_rd_wdata(spec_insn_bltu_rd_wdata), .spec_pc_wdata(spec_insn_bltu_pc_wdata), .spec_mem_addr(spec_insn_bltu_mem_addr), .spec_mem_rmask(spec_insn_bltu_mem_rmask), .spec_mem_wmask(spec_insn_bltu_mem_wmask), .spec_mem_wdata(spec_insn_bltu_mem_wdata) ); wire spec_insn_bne_valid; wire spec_insn_bne_trap; wire [ 4 : 0] spec_insn_bne_rs1_addr; wire [ 4 : 0] spec_insn_bne_rs2_addr; wire [ 4 : 0] spec_insn_bne_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; `endif rvfi_insn_bne insn_bne ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), `endif .spec_valid(spec_insn_bne_valid), .spec_trap(spec_insn_bne_trap), .spec_rs1_addr(spec_insn_bne_rs1_addr), .spec_rs2_addr(spec_insn_bne_rs2_addr), .spec_rd_addr(spec_insn_bne_rd_addr), .spec_rd_wdata(spec_insn_bne_rd_wdata), .spec_pc_wdata(spec_insn_bne_pc_wdata), .spec_mem_addr(spec_insn_bne_mem_addr), .spec_mem_rmask(spec_insn_bne_mem_rmask), .spec_mem_wmask(spec_insn_bne_mem_wmask), .spec_mem_wdata(spec_insn_bne_mem_wdata) ); wire spec_insn_jal_valid; wire spec_insn_jal_trap; wire [ 4 : 0] spec_insn_jal_rs1_addr; wire [ 4 : 0] spec_insn_jal_rs2_addr; wire [ 4 : 0] spec_insn_jal_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; `endif rvfi_insn_jal insn_jal ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), `endif .spec_valid(spec_insn_jal_valid), .spec_trap(spec_insn_jal_trap), .spec_rs1_addr(spec_insn_jal_rs1_addr), .spec_rs2_addr(spec_insn_jal_rs2_addr), .spec_rd_addr(spec_insn_jal_rd_addr), .spec_rd_wdata(spec_insn_jal_rd_wdata), .spec_pc_wdata(spec_insn_jal_pc_wdata), .spec_mem_addr(spec_insn_jal_mem_addr), .spec_mem_rmask(spec_insn_jal_mem_rmask), .spec_mem_wmask(spec_insn_jal_mem_wmask), .spec_mem_wdata(spec_insn_jal_mem_wdata) ); wire spec_insn_jalr_valid; wire spec_insn_jalr_trap; wire [ 4 : 0] spec_insn_jalr_rs1_addr; wire [ 4 : 0] spec_insn_jalr_rs2_addr; wire [ 4 : 0] spec_insn_jalr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; `endif rvfi_insn_jalr insn_jalr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), `endif .spec_valid(spec_insn_jalr_valid), .spec_trap(spec_insn_jalr_trap), .spec_rs1_addr(spec_insn_jalr_rs1_addr), .spec_rs2_addr(spec_insn_jalr_rs2_addr), .spec_rd_addr(spec_insn_jalr_rd_addr), .spec_rd_wdata(spec_insn_jalr_rd_wdata), .spec_pc_wdata(spec_insn_jalr_pc_wdata), .spec_mem_addr(spec_insn_jalr_mem_addr), .spec_mem_rmask(spec_insn_jalr_mem_rmask), .spec_mem_wmask(spec_insn_jalr_mem_wmask), .spec_mem_wdata(spec_insn_jalr_mem_wdata) ); wire spec_insn_lb_valid; wire spec_insn_lb_trap; wire [ 4 : 0] spec_insn_lb_rs1_addr; wire [ 4 : 0] spec_insn_lb_rs2_addr; wire [ 4 : 0] spec_insn_lb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; `endif rvfi_insn_lb insn_lb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), `endif .spec_valid(spec_insn_lb_valid), .spec_trap(spec_insn_lb_trap), .spec_rs1_addr(spec_insn_lb_rs1_addr), .spec_rs2_addr(spec_insn_lb_rs2_addr), .spec_rd_addr(spec_insn_lb_rd_addr), .spec_rd_wdata(spec_insn_lb_rd_wdata), .spec_pc_wdata(spec_insn_lb_pc_wdata), .spec_mem_addr(spec_insn_lb_mem_addr), .spec_mem_rmask(spec_insn_lb_mem_rmask), .spec_mem_wmask(spec_insn_lb_mem_wmask), .spec_mem_wdata(spec_insn_lb_mem_wdata) ); wire spec_insn_lbu_valid; wire spec_insn_lbu_trap; wire [ 4 : 0] spec_insn_lbu_rs1_addr; wire [ 4 : 0] spec_insn_lbu_rs2_addr; wire [ 4 : 0] spec_insn_lbu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; `endif rvfi_insn_lbu insn_lbu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), `endif .spec_valid(spec_insn_lbu_valid), .spec_trap(spec_insn_lbu_trap), .spec_rs1_addr(spec_insn_lbu_rs1_addr), .spec_rs2_addr(spec_insn_lbu_rs2_addr), .spec_rd_addr(spec_insn_lbu_rd_addr), .spec_rd_wdata(spec_insn_lbu_rd_wdata), .spec_pc_wdata(spec_insn_lbu_pc_wdata), .spec_mem_addr(spec_insn_lbu_mem_addr), .spec_mem_rmask(spec_insn_lbu_mem_rmask), .spec_mem_wmask(spec_insn_lbu_mem_wmask), .spec_mem_wdata(spec_insn_lbu_mem_wdata) ); wire spec_insn_ld_valid; wire spec_insn_ld_trap; wire [ 4 : 0] spec_insn_ld_rs1_addr; wire [ 4 : 0] spec_insn_ld_rs2_addr; wire [ 4 : 0] spec_insn_ld_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_csr_misa_rmask; `endif rvfi_insn_ld insn_ld ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_ld_csr_misa_rmask), `endif .spec_valid(spec_insn_ld_valid), .spec_trap(spec_insn_ld_trap), .spec_rs1_addr(spec_insn_ld_rs1_addr), .spec_rs2_addr(spec_insn_ld_rs2_addr), .spec_rd_addr(spec_insn_ld_rd_addr), .spec_rd_wdata(spec_insn_ld_rd_wdata), .spec_pc_wdata(spec_insn_ld_pc_wdata), .spec_mem_addr(spec_insn_ld_mem_addr), .spec_mem_rmask(spec_insn_ld_mem_rmask), .spec_mem_wmask(spec_insn_ld_mem_wmask), .spec_mem_wdata(spec_insn_ld_mem_wdata) ); wire spec_insn_lh_valid; wire spec_insn_lh_trap; wire [ 4 : 0] spec_insn_lh_rs1_addr; wire [ 4 : 0] spec_insn_lh_rs2_addr; wire [ 4 : 0] spec_insn_lh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; `endif rvfi_insn_lh insn_lh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), `endif .spec_valid(spec_insn_lh_valid), .spec_trap(spec_insn_lh_trap), .spec_rs1_addr(spec_insn_lh_rs1_addr), .spec_rs2_addr(spec_insn_lh_rs2_addr), .spec_rd_addr(spec_insn_lh_rd_addr), .spec_rd_wdata(spec_insn_lh_rd_wdata), .spec_pc_wdata(spec_insn_lh_pc_wdata), .spec_mem_addr(spec_insn_lh_mem_addr), .spec_mem_rmask(spec_insn_lh_mem_rmask), .spec_mem_wmask(spec_insn_lh_mem_wmask), .spec_mem_wdata(spec_insn_lh_mem_wdata) ); wire spec_insn_lhu_valid; wire spec_insn_lhu_trap; wire [ 4 : 0] spec_insn_lhu_rs1_addr; wire [ 4 : 0] spec_insn_lhu_rs2_addr; wire [ 4 : 0] spec_insn_lhu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; `endif rvfi_insn_lhu insn_lhu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), `endif .spec_valid(spec_insn_lhu_valid), .spec_trap(spec_insn_lhu_trap), .spec_rs1_addr(spec_insn_lhu_rs1_addr), .spec_rs2_addr(spec_insn_lhu_rs2_addr), .spec_rd_addr(spec_insn_lhu_rd_addr), .spec_rd_wdata(spec_insn_lhu_rd_wdata), .spec_pc_wdata(spec_insn_lhu_pc_wdata), .spec_mem_addr(spec_insn_lhu_mem_addr), .spec_mem_rmask(spec_insn_lhu_mem_rmask), .spec_mem_wmask(spec_insn_lhu_mem_wmask), .spec_mem_wdata(spec_insn_lhu_mem_wdata) ); wire spec_insn_lui_valid; wire spec_insn_lui_trap; wire [ 4 : 0] spec_insn_lui_rs1_addr; wire [ 4 : 0] spec_insn_lui_rs2_addr; wire [ 4 : 0] spec_insn_lui_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; `endif rvfi_insn_lui insn_lui ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), `endif .spec_valid(spec_insn_lui_valid), .spec_trap(spec_insn_lui_trap), .spec_rs1_addr(spec_insn_lui_rs1_addr), .spec_rs2_addr(spec_insn_lui_rs2_addr), .spec_rd_addr(spec_insn_lui_rd_addr), .spec_rd_wdata(spec_insn_lui_rd_wdata), .spec_pc_wdata(spec_insn_lui_pc_wdata), .spec_mem_addr(spec_insn_lui_mem_addr), .spec_mem_rmask(spec_insn_lui_mem_rmask), .spec_mem_wmask(spec_insn_lui_mem_wmask), .spec_mem_wdata(spec_insn_lui_mem_wdata) ); wire spec_insn_lw_valid; wire spec_insn_lw_trap; wire [ 4 : 0] spec_insn_lw_rs1_addr; wire [ 4 : 0] spec_insn_lw_rs2_addr; wire [ 4 : 0] spec_insn_lw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; `endif rvfi_insn_lw insn_lw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), `endif .spec_valid(spec_insn_lw_valid), .spec_trap(spec_insn_lw_trap), .spec_rs1_addr(spec_insn_lw_rs1_addr), .spec_rs2_addr(spec_insn_lw_rs2_addr), .spec_rd_addr(spec_insn_lw_rd_addr), .spec_rd_wdata(spec_insn_lw_rd_wdata), .spec_pc_wdata(spec_insn_lw_pc_wdata), .spec_mem_addr(spec_insn_lw_mem_addr), .spec_mem_rmask(spec_insn_lw_mem_rmask), .spec_mem_wmask(spec_insn_lw_mem_wmask), .spec_mem_wdata(spec_insn_lw_mem_wdata) ); wire spec_insn_lwu_valid; wire spec_insn_lwu_trap; wire [ 4 : 0] spec_insn_lwu_rs1_addr; wire [ 4 : 0] spec_insn_lwu_rs2_addr; wire [ 4 : 0] spec_insn_lwu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_csr_misa_rmask; `endif rvfi_insn_lwu insn_lwu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lwu_csr_misa_rmask), `endif .spec_valid(spec_insn_lwu_valid), .spec_trap(spec_insn_lwu_trap), .spec_rs1_addr(spec_insn_lwu_rs1_addr), .spec_rs2_addr(spec_insn_lwu_rs2_addr), .spec_rd_addr(spec_insn_lwu_rd_addr), .spec_rd_wdata(spec_insn_lwu_rd_wdata), .spec_pc_wdata(spec_insn_lwu_pc_wdata), .spec_mem_addr(spec_insn_lwu_mem_addr), .spec_mem_rmask(spec_insn_lwu_mem_rmask), .spec_mem_wmask(spec_insn_lwu_mem_wmask), .spec_mem_wdata(spec_insn_lwu_mem_wdata) ); wire spec_insn_or_valid; wire spec_insn_or_trap; wire [ 4 : 0] spec_insn_or_rs1_addr; wire [ 4 : 0] spec_insn_or_rs2_addr; wire [ 4 : 0] spec_insn_or_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; `endif rvfi_insn_or insn_or ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), `endif .spec_valid(spec_insn_or_valid), .spec_trap(spec_insn_or_trap), .spec_rs1_addr(spec_insn_or_rs1_addr), .spec_rs2_addr(spec_insn_or_rs2_addr), .spec_rd_addr(spec_insn_or_rd_addr), .spec_rd_wdata(spec_insn_or_rd_wdata), .spec_pc_wdata(spec_insn_or_pc_wdata), .spec_mem_addr(spec_insn_or_mem_addr), .spec_mem_rmask(spec_insn_or_mem_rmask), .spec_mem_wmask(spec_insn_or_mem_wmask), .spec_mem_wdata(spec_insn_or_mem_wdata) ); wire spec_insn_ori_valid; wire spec_insn_ori_trap; wire [ 4 : 0] spec_insn_ori_rs1_addr; wire [ 4 : 0] spec_insn_ori_rs2_addr; wire [ 4 : 0] spec_insn_ori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; `endif rvfi_insn_ori insn_ori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), `endif .spec_valid(spec_insn_ori_valid), .spec_trap(spec_insn_ori_trap), .spec_rs1_addr(spec_insn_ori_rs1_addr), .spec_rs2_addr(spec_insn_ori_rs2_addr), .spec_rd_addr(spec_insn_ori_rd_addr), .spec_rd_wdata(spec_insn_ori_rd_wdata), .spec_pc_wdata(spec_insn_ori_pc_wdata), .spec_mem_addr(spec_insn_ori_mem_addr), .spec_mem_rmask(spec_insn_ori_mem_rmask), .spec_mem_wmask(spec_insn_ori_mem_wmask), .spec_mem_wdata(spec_insn_ori_mem_wdata) ); wire spec_insn_sb_valid; wire spec_insn_sb_trap; wire [ 4 : 0] spec_insn_sb_rs1_addr; wire [ 4 : 0] spec_insn_sb_rs2_addr; wire [ 4 : 0] spec_insn_sb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; `endif rvfi_insn_sb insn_sb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), `endif .spec_valid(spec_insn_sb_valid), .spec_trap(spec_insn_sb_trap), .spec_rs1_addr(spec_insn_sb_rs1_addr), .spec_rs2_addr(spec_insn_sb_rs2_addr), .spec_rd_addr(spec_insn_sb_rd_addr), .spec_rd_wdata(spec_insn_sb_rd_wdata), .spec_pc_wdata(spec_insn_sb_pc_wdata), .spec_mem_addr(spec_insn_sb_mem_addr), .spec_mem_rmask(spec_insn_sb_mem_rmask), .spec_mem_wmask(spec_insn_sb_mem_wmask), .spec_mem_wdata(spec_insn_sb_mem_wdata) ); wire spec_insn_sd_valid; wire spec_insn_sd_trap; wire [ 4 : 0] spec_insn_sd_rs1_addr; wire [ 4 : 0] spec_insn_sd_rs2_addr; wire [ 4 : 0] spec_insn_sd_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_csr_misa_rmask; `endif rvfi_insn_sd insn_sd ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sd_csr_misa_rmask), `endif .spec_valid(spec_insn_sd_valid), .spec_trap(spec_insn_sd_trap), .spec_rs1_addr(spec_insn_sd_rs1_addr), .spec_rs2_addr(spec_insn_sd_rs2_addr), .spec_rd_addr(spec_insn_sd_rd_addr), .spec_rd_wdata(spec_insn_sd_rd_wdata), .spec_pc_wdata(spec_insn_sd_pc_wdata), .spec_mem_addr(spec_insn_sd_mem_addr), .spec_mem_rmask(spec_insn_sd_mem_rmask), .spec_mem_wmask(spec_insn_sd_mem_wmask), .spec_mem_wdata(spec_insn_sd_mem_wdata) ); wire spec_insn_sh_valid; wire spec_insn_sh_trap; wire [ 4 : 0] spec_insn_sh_rs1_addr; wire [ 4 : 0] spec_insn_sh_rs2_addr; wire [ 4 : 0] spec_insn_sh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; `endif rvfi_insn_sh insn_sh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), `endif .spec_valid(spec_insn_sh_valid), .spec_trap(spec_insn_sh_trap), .spec_rs1_addr(spec_insn_sh_rs1_addr), .spec_rs2_addr(spec_insn_sh_rs2_addr), .spec_rd_addr(spec_insn_sh_rd_addr), .spec_rd_wdata(spec_insn_sh_rd_wdata), .spec_pc_wdata(spec_insn_sh_pc_wdata), .spec_mem_addr(spec_insn_sh_mem_addr), .spec_mem_rmask(spec_insn_sh_mem_rmask), .spec_mem_wmask(spec_insn_sh_mem_wmask), .spec_mem_wdata(spec_insn_sh_mem_wdata) ); wire spec_insn_sll_valid; wire spec_insn_sll_trap; wire [ 4 : 0] spec_insn_sll_rs1_addr; wire [ 4 : 0] spec_insn_sll_rs2_addr; wire [ 4 : 0] spec_insn_sll_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; `endif rvfi_insn_sll insn_sll ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), `endif .spec_valid(spec_insn_sll_valid), .spec_trap(spec_insn_sll_trap), .spec_rs1_addr(spec_insn_sll_rs1_addr), .spec_rs2_addr(spec_insn_sll_rs2_addr), .spec_rd_addr(spec_insn_sll_rd_addr), .spec_rd_wdata(spec_insn_sll_rd_wdata), .spec_pc_wdata(spec_insn_sll_pc_wdata), .spec_mem_addr(spec_insn_sll_mem_addr), .spec_mem_rmask(spec_insn_sll_mem_rmask), .spec_mem_wmask(spec_insn_sll_mem_wmask), .spec_mem_wdata(spec_insn_sll_mem_wdata) ); wire spec_insn_slli_valid; wire spec_insn_slli_trap; wire [ 4 : 0] spec_insn_slli_rs1_addr; wire [ 4 : 0] spec_insn_slli_rs2_addr; wire [ 4 : 0] spec_insn_slli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; `endif rvfi_insn_slli insn_slli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), `endif .spec_valid(spec_insn_slli_valid), .spec_trap(spec_insn_slli_trap), .spec_rs1_addr(spec_insn_slli_rs1_addr), .spec_rs2_addr(spec_insn_slli_rs2_addr), .spec_rd_addr(spec_insn_slli_rd_addr), .spec_rd_wdata(spec_insn_slli_rd_wdata), .spec_pc_wdata(spec_insn_slli_pc_wdata), .spec_mem_addr(spec_insn_slli_mem_addr), .spec_mem_rmask(spec_insn_slli_mem_rmask), .spec_mem_wmask(spec_insn_slli_mem_wmask), .spec_mem_wdata(spec_insn_slli_mem_wdata) ); wire spec_insn_slliw_valid; wire spec_insn_slliw_trap; wire [ 4 : 0] spec_insn_slliw_rs1_addr; wire [ 4 : 0] spec_insn_slliw_rs2_addr; wire [ 4 : 0] spec_insn_slliw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_csr_misa_rmask; `endif rvfi_insn_slliw insn_slliw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slliw_csr_misa_rmask), `endif .spec_valid(spec_insn_slliw_valid), .spec_trap(spec_insn_slliw_trap), .spec_rs1_addr(spec_insn_slliw_rs1_addr), .spec_rs2_addr(spec_insn_slliw_rs2_addr), .spec_rd_addr(spec_insn_slliw_rd_addr), .spec_rd_wdata(spec_insn_slliw_rd_wdata), .spec_pc_wdata(spec_insn_slliw_pc_wdata), .spec_mem_addr(spec_insn_slliw_mem_addr), .spec_mem_rmask(spec_insn_slliw_mem_rmask), .spec_mem_wmask(spec_insn_slliw_mem_wmask), .spec_mem_wdata(spec_insn_slliw_mem_wdata) ); wire spec_insn_sllw_valid; wire spec_insn_sllw_trap; wire [ 4 : 0] spec_insn_sllw_rs1_addr; wire [ 4 : 0] spec_insn_sllw_rs2_addr; wire [ 4 : 0] spec_insn_sllw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_csr_misa_rmask; `endif rvfi_insn_sllw insn_sllw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sllw_csr_misa_rmask), `endif .spec_valid(spec_insn_sllw_valid), .spec_trap(spec_insn_sllw_trap), .spec_rs1_addr(spec_insn_sllw_rs1_addr), .spec_rs2_addr(spec_insn_sllw_rs2_addr), .spec_rd_addr(spec_insn_sllw_rd_addr), .spec_rd_wdata(spec_insn_sllw_rd_wdata), .spec_pc_wdata(spec_insn_sllw_pc_wdata), .spec_mem_addr(spec_insn_sllw_mem_addr), .spec_mem_rmask(spec_insn_sllw_mem_rmask), .spec_mem_wmask(spec_insn_sllw_mem_wmask), .spec_mem_wdata(spec_insn_sllw_mem_wdata) ); wire spec_insn_slt_valid; wire spec_insn_slt_trap; wire [ 4 : 0] spec_insn_slt_rs1_addr; wire [ 4 : 0] spec_insn_slt_rs2_addr; wire [ 4 : 0] spec_insn_slt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; `endif rvfi_insn_slt insn_slt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), `endif .spec_valid(spec_insn_slt_valid), .spec_trap(spec_insn_slt_trap), .spec_rs1_addr(spec_insn_slt_rs1_addr), .spec_rs2_addr(spec_insn_slt_rs2_addr), .spec_rd_addr(spec_insn_slt_rd_addr), .spec_rd_wdata(spec_insn_slt_rd_wdata), .spec_pc_wdata(spec_insn_slt_pc_wdata), .spec_mem_addr(spec_insn_slt_mem_addr), .spec_mem_rmask(spec_insn_slt_mem_rmask), .spec_mem_wmask(spec_insn_slt_mem_wmask), .spec_mem_wdata(spec_insn_slt_mem_wdata) ); wire spec_insn_slti_valid; wire spec_insn_slti_trap; wire [ 4 : 0] spec_insn_slti_rs1_addr; wire [ 4 : 0] spec_insn_slti_rs2_addr; wire [ 4 : 0] spec_insn_slti_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; `endif rvfi_insn_slti insn_slti ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), `endif .spec_valid(spec_insn_slti_valid), .spec_trap(spec_insn_slti_trap), .spec_rs1_addr(spec_insn_slti_rs1_addr), .spec_rs2_addr(spec_insn_slti_rs2_addr), .spec_rd_addr(spec_insn_slti_rd_addr), .spec_rd_wdata(spec_insn_slti_rd_wdata), .spec_pc_wdata(spec_insn_slti_pc_wdata), .spec_mem_addr(spec_insn_slti_mem_addr), .spec_mem_rmask(spec_insn_slti_mem_rmask), .spec_mem_wmask(spec_insn_slti_mem_wmask), .spec_mem_wdata(spec_insn_slti_mem_wdata) ); wire spec_insn_sltiu_valid; wire spec_insn_sltiu_trap; wire [ 4 : 0] spec_insn_sltiu_rs1_addr; wire [ 4 : 0] spec_insn_sltiu_rs2_addr; wire [ 4 : 0] spec_insn_sltiu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; `endif rvfi_insn_sltiu insn_sltiu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltiu_valid), .spec_trap(spec_insn_sltiu_trap), .spec_rs1_addr(spec_insn_sltiu_rs1_addr), .spec_rs2_addr(spec_insn_sltiu_rs2_addr), .spec_rd_addr(spec_insn_sltiu_rd_addr), .spec_rd_wdata(spec_insn_sltiu_rd_wdata), .spec_pc_wdata(spec_insn_sltiu_pc_wdata), .spec_mem_addr(spec_insn_sltiu_mem_addr), .spec_mem_rmask(spec_insn_sltiu_mem_rmask), .spec_mem_wmask(spec_insn_sltiu_mem_wmask), .spec_mem_wdata(spec_insn_sltiu_mem_wdata) ); wire spec_insn_sltu_valid; wire spec_insn_sltu_trap; wire [ 4 : 0] spec_insn_sltu_rs1_addr; wire [ 4 : 0] spec_insn_sltu_rs2_addr; wire [ 4 : 0] spec_insn_sltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; `endif rvfi_insn_sltu insn_sltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltu_valid), .spec_trap(spec_insn_sltu_trap), .spec_rs1_addr(spec_insn_sltu_rs1_addr), .spec_rs2_addr(spec_insn_sltu_rs2_addr), .spec_rd_addr(spec_insn_sltu_rd_addr), .spec_rd_wdata(spec_insn_sltu_rd_wdata), .spec_pc_wdata(spec_insn_sltu_pc_wdata), .spec_mem_addr(spec_insn_sltu_mem_addr), .spec_mem_rmask(spec_insn_sltu_mem_rmask), .spec_mem_wmask(spec_insn_sltu_mem_wmask), .spec_mem_wdata(spec_insn_sltu_mem_wdata) ); wire spec_insn_sra_valid; wire spec_insn_sra_trap; wire [ 4 : 0] spec_insn_sra_rs1_addr; wire [ 4 : 0] spec_insn_sra_rs2_addr; wire [ 4 : 0] spec_insn_sra_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; `endif rvfi_insn_sra insn_sra ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), `endif .spec_valid(spec_insn_sra_valid), .spec_trap(spec_insn_sra_trap), .spec_rs1_addr(spec_insn_sra_rs1_addr), .spec_rs2_addr(spec_insn_sra_rs2_addr), .spec_rd_addr(spec_insn_sra_rd_addr), .spec_rd_wdata(spec_insn_sra_rd_wdata), .spec_pc_wdata(spec_insn_sra_pc_wdata), .spec_mem_addr(spec_insn_sra_mem_addr), .spec_mem_rmask(spec_insn_sra_mem_rmask), .spec_mem_wmask(spec_insn_sra_mem_wmask), .spec_mem_wdata(spec_insn_sra_mem_wdata) ); wire spec_insn_srai_valid; wire spec_insn_srai_trap; wire [ 4 : 0] spec_insn_srai_rs1_addr; wire [ 4 : 0] spec_insn_srai_rs2_addr; wire [ 4 : 0] spec_insn_srai_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; `endif rvfi_insn_srai insn_srai ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), `endif .spec_valid(spec_insn_srai_valid), .spec_trap(spec_insn_srai_trap), .spec_rs1_addr(spec_insn_srai_rs1_addr), .spec_rs2_addr(spec_insn_srai_rs2_addr), .spec_rd_addr(spec_insn_srai_rd_addr), .spec_rd_wdata(spec_insn_srai_rd_wdata), .spec_pc_wdata(spec_insn_srai_pc_wdata), .spec_mem_addr(spec_insn_srai_mem_addr), .spec_mem_rmask(spec_insn_srai_mem_rmask), .spec_mem_wmask(spec_insn_srai_mem_wmask), .spec_mem_wdata(spec_insn_srai_mem_wdata) ); wire spec_insn_sraiw_valid; wire spec_insn_sraiw_trap; wire [ 4 : 0] spec_insn_sraiw_rs1_addr; wire [ 4 : 0] spec_insn_sraiw_rs2_addr; wire [ 4 : 0] spec_insn_sraiw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_csr_misa_rmask; `endif rvfi_insn_sraiw insn_sraiw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sraiw_csr_misa_rmask), `endif .spec_valid(spec_insn_sraiw_valid), .spec_trap(spec_insn_sraiw_trap), .spec_rs1_addr(spec_insn_sraiw_rs1_addr), .spec_rs2_addr(spec_insn_sraiw_rs2_addr), .spec_rd_addr(spec_insn_sraiw_rd_addr), .spec_rd_wdata(spec_insn_sraiw_rd_wdata), .spec_pc_wdata(spec_insn_sraiw_pc_wdata), .spec_mem_addr(spec_insn_sraiw_mem_addr), .spec_mem_rmask(spec_insn_sraiw_mem_rmask), .spec_mem_wmask(spec_insn_sraiw_mem_wmask), .spec_mem_wdata(spec_insn_sraiw_mem_wdata) ); wire spec_insn_sraw_valid; wire spec_insn_sraw_trap; wire [ 4 : 0] spec_insn_sraw_rs1_addr; wire [ 4 : 0] spec_insn_sraw_rs2_addr; wire [ 4 : 0] spec_insn_sraw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_csr_misa_rmask; `endif rvfi_insn_sraw insn_sraw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sraw_csr_misa_rmask), `endif .spec_valid(spec_insn_sraw_valid), .spec_trap(spec_insn_sraw_trap), .spec_rs1_addr(spec_insn_sraw_rs1_addr), .spec_rs2_addr(spec_insn_sraw_rs2_addr), .spec_rd_addr(spec_insn_sraw_rd_addr), .spec_rd_wdata(spec_insn_sraw_rd_wdata), .spec_pc_wdata(spec_insn_sraw_pc_wdata), .spec_mem_addr(spec_insn_sraw_mem_addr), .spec_mem_rmask(spec_insn_sraw_mem_rmask), .spec_mem_wmask(spec_insn_sraw_mem_wmask), .spec_mem_wdata(spec_insn_sraw_mem_wdata) ); wire spec_insn_srl_valid; wire spec_insn_srl_trap; wire [ 4 : 0] spec_insn_srl_rs1_addr; wire [ 4 : 0] spec_insn_srl_rs2_addr; wire [ 4 : 0] spec_insn_srl_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; `endif rvfi_insn_srl insn_srl ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), `endif .spec_valid(spec_insn_srl_valid), .spec_trap(spec_insn_srl_trap), .spec_rs1_addr(spec_insn_srl_rs1_addr), .spec_rs2_addr(spec_insn_srl_rs2_addr), .spec_rd_addr(spec_insn_srl_rd_addr), .spec_rd_wdata(spec_insn_srl_rd_wdata), .spec_pc_wdata(spec_insn_srl_pc_wdata), .spec_mem_addr(spec_insn_srl_mem_addr), .spec_mem_rmask(spec_insn_srl_mem_rmask), .spec_mem_wmask(spec_insn_srl_mem_wmask), .spec_mem_wdata(spec_insn_srl_mem_wdata) ); wire spec_insn_srli_valid; wire spec_insn_srli_trap; wire [ 4 : 0] spec_insn_srli_rs1_addr; wire [ 4 : 0] spec_insn_srli_rs2_addr; wire [ 4 : 0] spec_insn_srli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; `endif rvfi_insn_srli insn_srli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), `endif .spec_valid(spec_insn_srli_valid), .spec_trap(spec_insn_srli_trap), .spec_rs1_addr(spec_insn_srli_rs1_addr), .spec_rs2_addr(spec_insn_srli_rs2_addr), .spec_rd_addr(spec_insn_srli_rd_addr), .spec_rd_wdata(spec_insn_srli_rd_wdata), .spec_pc_wdata(spec_insn_srli_pc_wdata), .spec_mem_addr(spec_insn_srli_mem_addr), .spec_mem_rmask(spec_insn_srli_mem_rmask), .spec_mem_wmask(spec_insn_srli_mem_wmask), .spec_mem_wdata(spec_insn_srli_mem_wdata) ); wire spec_insn_srliw_valid; wire spec_insn_srliw_trap; wire [ 4 : 0] spec_insn_srliw_rs1_addr; wire [ 4 : 0] spec_insn_srliw_rs2_addr; wire [ 4 : 0] spec_insn_srliw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_csr_misa_rmask; `endif rvfi_insn_srliw insn_srliw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srliw_csr_misa_rmask), `endif .spec_valid(spec_insn_srliw_valid), .spec_trap(spec_insn_srliw_trap), .spec_rs1_addr(spec_insn_srliw_rs1_addr), .spec_rs2_addr(spec_insn_srliw_rs2_addr), .spec_rd_addr(spec_insn_srliw_rd_addr), .spec_rd_wdata(spec_insn_srliw_rd_wdata), .spec_pc_wdata(spec_insn_srliw_pc_wdata), .spec_mem_addr(spec_insn_srliw_mem_addr), .spec_mem_rmask(spec_insn_srliw_mem_rmask), .spec_mem_wmask(spec_insn_srliw_mem_wmask), .spec_mem_wdata(spec_insn_srliw_mem_wdata) ); wire spec_insn_srlw_valid; wire spec_insn_srlw_trap; wire [ 4 : 0] spec_insn_srlw_rs1_addr; wire [ 4 : 0] spec_insn_srlw_rs2_addr; wire [ 4 : 0] spec_insn_srlw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_csr_misa_rmask; `endif rvfi_insn_srlw insn_srlw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srlw_csr_misa_rmask), `endif .spec_valid(spec_insn_srlw_valid), .spec_trap(spec_insn_srlw_trap), .spec_rs1_addr(spec_insn_srlw_rs1_addr), .spec_rs2_addr(spec_insn_srlw_rs2_addr), .spec_rd_addr(spec_insn_srlw_rd_addr), .spec_rd_wdata(spec_insn_srlw_rd_wdata), .spec_pc_wdata(spec_insn_srlw_pc_wdata), .spec_mem_addr(spec_insn_srlw_mem_addr), .spec_mem_rmask(spec_insn_srlw_mem_rmask), .spec_mem_wmask(spec_insn_srlw_mem_wmask), .spec_mem_wdata(spec_insn_srlw_mem_wdata) ); wire spec_insn_sub_valid; wire spec_insn_sub_trap; wire [ 4 : 0] spec_insn_sub_rs1_addr; wire [ 4 : 0] spec_insn_sub_rs2_addr; wire [ 4 : 0] spec_insn_sub_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; `endif rvfi_insn_sub insn_sub ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), `endif .spec_valid(spec_insn_sub_valid), .spec_trap(spec_insn_sub_trap), .spec_rs1_addr(spec_insn_sub_rs1_addr), .spec_rs2_addr(spec_insn_sub_rs2_addr), .spec_rd_addr(spec_insn_sub_rd_addr), .spec_rd_wdata(spec_insn_sub_rd_wdata), .spec_pc_wdata(spec_insn_sub_pc_wdata), .spec_mem_addr(spec_insn_sub_mem_addr), .spec_mem_rmask(spec_insn_sub_mem_rmask), .spec_mem_wmask(spec_insn_sub_mem_wmask), .spec_mem_wdata(spec_insn_sub_mem_wdata) ); wire spec_insn_subw_valid; wire spec_insn_subw_trap; wire [ 4 : 0] spec_insn_subw_rs1_addr; wire [ 4 : 0] spec_insn_subw_rs2_addr; wire [ 4 : 0] spec_insn_subw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_csr_misa_rmask; `endif rvfi_insn_subw insn_subw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_subw_csr_misa_rmask), `endif .spec_valid(spec_insn_subw_valid), .spec_trap(spec_insn_subw_trap), .spec_rs1_addr(spec_insn_subw_rs1_addr), .spec_rs2_addr(spec_insn_subw_rs2_addr), .spec_rd_addr(spec_insn_subw_rd_addr), .spec_rd_wdata(spec_insn_subw_rd_wdata), .spec_pc_wdata(spec_insn_subw_pc_wdata), .spec_mem_addr(spec_insn_subw_mem_addr), .spec_mem_rmask(spec_insn_subw_mem_rmask), .spec_mem_wmask(spec_insn_subw_mem_wmask), .spec_mem_wdata(spec_insn_subw_mem_wdata) ); wire spec_insn_sw_valid; wire spec_insn_sw_trap; wire [ 4 : 0] spec_insn_sw_rs1_addr; wire [ 4 : 0] spec_insn_sw_rs2_addr; wire [ 4 : 0] spec_insn_sw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; `endif rvfi_insn_sw insn_sw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), `endif .spec_valid(spec_insn_sw_valid), .spec_trap(spec_insn_sw_trap), .spec_rs1_addr(spec_insn_sw_rs1_addr), .spec_rs2_addr(spec_insn_sw_rs2_addr), .spec_rd_addr(spec_insn_sw_rd_addr), .spec_rd_wdata(spec_insn_sw_rd_wdata), .spec_pc_wdata(spec_insn_sw_pc_wdata), .spec_mem_addr(spec_insn_sw_mem_addr), .spec_mem_rmask(spec_insn_sw_mem_rmask), .spec_mem_wmask(spec_insn_sw_mem_wmask), .spec_mem_wdata(spec_insn_sw_mem_wdata) ); wire spec_insn_xor_valid; wire spec_insn_xor_trap; wire [ 4 : 0] spec_insn_xor_rs1_addr; wire [ 4 : 0] spec_insn_xor_rs2_addr; wire [ 4 : 0] spec_insn_xor_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; `endif rvfi_insn_xor insn_xor ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), `endif .spec_valid(spec_insn_xor_valid), .spec_trap(spec_insn_xor_trap), .spec_rs1_addr(spec_insn_xor_rs1_addr), .spec_rs2_addr(spec_insn_xor_rs2_addr), .spec_rd_addr(spec_insn_xor_rd_addr), .spec_rd_wdata(spec_insn_xor_rd_wdata), .spec_pc_wdata(spec_insn_xor_pc_wdata), .spec_mem_addr(spec_insn_xor_mem_addr), .spec_mem_rmask(spec_insn_xor_mem_rmask), .spec_mem_wmask(spec_insn_xor_mem_wmask), .spec_mem_wdata(spec_insn_xor_mem_wdata) ); wire spec_insn_xori_valid; wire spec_insn_xori_trap; wire [ 4 : 0] spec_insn_xori_rs1_addr; wire [ 4 : 0] spec_insn_xori_rs2_addr; wire [ 4 : 0] spec_insn_xori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; `endif rvfi_insn_xori insn_xori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), `endif .spec_valid(spec_insn_xori_valid), .spec_trap(spec_insn_xori_trap), .spec_rs1_addr(spec_insn_xori_rs1_addr), .spec_rs2_addr(spec_insn_xori_rs2_addr), .spec_rd_addr(spec_insn_xori_rd_addr), .spec_rd_wdata(spec_insn_xori_rd_wdata), .spec_pc_wdata(spec_insn_xori_pc_wdata), .spec_mem_addr(spec_insn_xori_mem_addr), .spec_mem_rmask(spec_insn_xori_mem_rmask), .spec_mem_wmask(spec_insn_xori_mem_wmask), .spec_mem_wdata(spec_insn_xori_mem_wdata) ); assign spec_valid = spec_insn_add_valid ? spec_insn_add_valid : spec_insn_addi_valid ? spec_insn_addi_valid : spec_insn_addiw_valid ? spec_insn_addiw_valid : spec_insn_addw_valid ? spec_insn_addw_valid : spec_insn_and_valid ? spec_insn_and_valid : spec_insn_andi_valid ? spec_insn_andi_valid : spec_insn_auipc_valid ? spec_insn_auipc_valid : spec_insn_beq_valid ? spec_insn_beq_valid : spec_insn_bge_valid ? spec_insn_bge_valid : spec_insn_bgeu_valid ? spec_insn_bgeu_valid : spec_insn_blt_valid ? spec_insn_blt_valid : spec_insn_bltu_valid ? spec_insn_bltu_valid : spec_insn_bne_valid ? spec_insn_bne_valid : spec_insn_jal_valid ? spec_insn_jal_valid : spec_insn_jalr_valid ? spec_insn_jalr_valid : spec_insn_lb_valid ? spec_insn_lb_valid : spec_insn_lbu_valid ? spec_insn_lbu_valid : spec_insn_ld_valid ? spec_insn_ld_valid : spec_insn_lh_valid ? spec_insn_lh_valid : spec_insn_lhu_valid ? spec_insn_lhu_valid : spec_insn_lui_valid ? spec_insn_lui_valid : spec_insn_lw_valid ? spec_insn_lw_valid : spec_insn_lwu_valid ? spec_insn_lwu_valid : spec_insn_or_valid ? spec_insn_or_valid : spec_insn_ori_valid ? spec_insn_ori_valid : spec_insn_sb_valid ? spec_insn_sb_valid : spec_insn_sd_valid ? spec_insn_sd_valid : spec_insn_sh_valid ? spec_insn_sh_valid : spec_insn_sll_valid ? spec_insn_sll_valid : spec_insn_slli_valid ? spec_insn_slli_valid : spec_insn_slliw_valid ? spec_insn_slliw_valid : spec_insn_sllw_valid ? spec_insn_sllw_valid : spec_insn_slt_valid ? spec_insn_slt_valid : spec_insn_slti_valid ? spec_insn_slti_valid : spec_insn_sltiu_valid ? spec_insn_sltiu_valid : spec_insn_sltu_valid ? spec_insn_sltu_valid : spec_insn_sra_valid ? spec_insn_sra_valid : spec_insn_srai_valid ? spec_insn_srai_valid : spec_insn_sraiw_valid ? spec_insn_sraiw_valid : spec_insn_sraw_valid ? spec_insn_sraw_valid : spec_insn_srl_valid ? spec_insn_srl_valid : spec_insn_srli_valid ? spec_insn_srli_valid : spec_insn_srliw_valid ? spec_insn_srliw_valid : spec_insn_srlw_valid ? spec_insn_srlw_valid : spec_insn_sub_valid ? spec_insn_sub_valid : spec_insn_subw_valid ? spec_insn_subw_valid : spec_insn_sw_valid ? spec_insn_sw_valid : spec_insn_xor_valid ? spec_insn_xor_valid : spec_insn_xori_valid ? spec_insn_xori_valid : 0; assign spec_trap = spec_insn_add_valid ? spec_insn_add_trap : spec_insn_addi_valid ? spec_insn_addi_trap : spec_insn_addiw_valid ? spec_insn_addiw_trap : spec_insn_addw_valid ? spec_insn_addw_trap : spec_insn_and_valid ? spec_insn_and_trap : spec_insn_andi_valid ? spec_insn_andi_trap : spec_insn_auipc_valid ? spec_insn_auipc_trap : spec_insn_beq_valid ? spec_insn_beq_trap : spec_insn_bge_valid ? spec_insn_bge_trap : spec_insn_bgeu_valid ? spec_insn_bgeu_trap : spec_insn_blt_valid ? spec_insn_blt_trap : spec_insn_bltu_valid ? spec_insn_bltu_trap : spec_insn_bne_valid ? spec_insn_bne_trap : spec_insn_jal_valid ? spec_insn_jal_trap : spec_insn_jalr_valid ? spec_insn_jalr_trap : spec_insn_lb_valid ? spec_insn_lb_trap : spec_insn_lbu_valid ? spec_insn_lbu_trap : spec_insn_ld_valid ? spec_insn_ld_trap : spec_insn_lh_valid ? spec_insn_lh_trap : spec_insn_lhu_valid ? spec_insn_lhu_trap : spec_insn_lui_valid ? spec_insn_lui_trap : spec_insn_lw_valid ? spec_insn_lw_trap : spec_insn_lwu_valid ? spec_insn_lwu_trap : spec_insn_or_valid ? spec_insn_or_trap : spec_insn_ori_valid ? spec_insn_ori_trap : spec_insn_sb_valid ? spec_insn_sb_trap : spec_insn_sd_valid ? spec_insn_sd_trap : spec_insn_sh_valid ? spec_insn_sh_trap : spec_insn_sll_valid ? spec_insn_sll_trap : spec_insn_slli_valid ? spec_insn_slli_trap : spec_insn_slliw_valid ? spec_insn_slliw_trap : spec_insn_sllw_valid ? spec_insn_sllw_trap : spec_insn_slt_valid ? spec_insn_slt_trap : spec_insn_slti_valid ? spec_insn_slti_trap : spec_insn_sltiu_valid ? spec_insn_sltiu_trap : spec_insn_sltu_valid ? spec_insn_sltu_trap : spec_insn_sra_valid ? spec_insn_sra_trap : spec_insn_srai_valid ? spec_insn_srai_trap : spec_insn_sraiw_valid ? spec_insn_sraiw_trap : spec_insn_sraw_valid ? spec_insn_sraw_trap : spec_insn_srl_valid ? spec_insn_srl_trap : spec_insn_srli_valid ? spec_insn_srli_trap : spec_insn_srliw_valid ? spec_insn_srliw_trap : spec_insn_srlw_valid ? spec_insn_srlw_trap : spec_insn_sub_valid ? spec_insn_sub_trap : spec_insn_subw_valid ? spec_insn_subw_trap : spec_insn_sw_valid ? spec_insn_sw_trap : spec_insn_xor_valid ? spec_insn_xor_trap : spec_insn_xori_valid ? spec_insn_xori_trap : 0; assign spec_rs1_addr = spec_insn_add_valid ? spec_insn_add_rs1_addr : spec_insn_addi_valid ? spec_insn_addi_rs1_addr : spec_insn_addiw_valid ? spec_insn_addiw_rs1_addr : spec_insn_addw_valid ? spec_insn_addw_rs1_addr : spec_insn_and_valid ? spec_insn_and_rs1_addr : spec_insn_andi_valid ? spec_insn_andi_rs1_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : spec_insn_beq_valid ? spec_insn_beq_rs1_addr : spec_insn_bge_valid ? spec_insn_bge_rs1_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : spec_insn_blt_valid ? spec_insn_blt_rs1_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : spec_insn_bne_valid ? spec_insn_bne_rs1_addr : spec_insn_jal_valid ? spec_insn_jal_rs1_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : spec_insn_lb_valid ? spec_insn_lb_rs1_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : spec_insn_ld_valid ? spec_insn_ld_rs1_addr : spec_insn_lh_valid ? spec_insn_lh_rs1_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : spec_insn_lui_valid ? spec_insn_lui_rs1_addr : spec_insn_lw_valid ? spec_insn_lw_rs1_addr : spec_insn_lwu_valid ? spec_insn_lwu_rs1_addr : spec_insn_or_valid ? spec_insn_or_rs1_addr : spec_insn_ori_valid ? spec_insn_ori_rs1_addr : spec_insn_sb_valid ? spec_insn_sb_rs1_addr : spec_insn_sd_valid ? spec_insn_sd_rs1_addr : spec_insn_sh_valid ? spec_insn_sh_rs1_addr : spec_insn_sll_valid ? spec_insn_sll_rs1_addr : spec_insn_slli_valid ? spec_insn_slli_rs1_addr : spec_insn_slliw_valid ? spec_insn_slliw_rs1_addr : spec_insn_sllw_valid ? spec_insn_sllw_rs1_addr : spec_insn_slt_valid ? spec_insn_slt_rs1_addr : spec_insn_slti_valid ? spec_insn_slti_rs1_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : spec_insn_sra_valid ? spec_insn_sra_rs1_addr : spec_insn_srai_valid ? spec_insn_srai_rs1_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_rs1_addr : spec_insn_sraw_valid ? spec_insn_sraw_rs1_addr : spec_insn_srl_valid ? spec_insn_srl_rs1_addr : spec_insn_srli_valid ? spec_insn_srli_rs1_addr : spec_insn_srliw_valid ? spec_insn_srliw_rs1_addr : spec_insn_srlw_valid ? spec_insn_srlw_rs1_addr : spec_insn_sub_valid ? spec_insn_sub_rs1_addr : spec_insn_subw_valid ? spec_insn_subw_rs1_addr : spec_insn_sw_valid ? spec_insn_sw_rs1_addr : spec_insn_xor_valid ? spec_insn_xor_rs1_addr : spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; assign spec_rs2_addr = spec_insn_add_valid ? spec_insn_add_rs2_addr : spec_insn_addi_valid ? spec_insn_addi_rs2_addr : spec_insn_addiw_valid ? spec_insn_addiw_rs2_addr : spec_insn_addw_valid ? spec_insn_addw_rs2_addr : spec_insn_and_valid ? spec_insn_and_rs2_addr : spec_insn_andi_valid ? spec_insn_andi_rs2_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : spec_insn_beq_valid ? spec_insn_beq_rs2_addr : spec_insn_bge_valid ? spec_insn_bge_rs2_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : spec_insn_blt_valid ? spec_insn_blt_rs2_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : spec_insn_bne_valid ? spec_insn_bne_rs2_addr : spec_insn_jal_valid ? spec_insn_jal_rs2_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : spec_insn_lb_valid ? spec_insn_lb_rs2_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : spec_insn_ld_valid ? spec_insn_ld_rs2_addr : spec_insn_lh_valid ? spec_insn_lh_rs2_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : spec_insn_lui_valid ? spec_insn_lui_rs2_addr : spec_insn_lw_valid ? spec_insn_lw_rs2_addr : spec_insn_lwu_valid ? spec_insn_lwu_rs2_addr : spec_insn_or_valid ? spec_insn_or_rs2_addr : spec_insn_ori_valid ? spec_insn_ori_rs2_addr : spec_insn_sb_valid ? spec_insn_sb_rs2_addr : spec_insn_sd_valid ? spec_insn_sd_rs2_addr : spec_insn_sh_valid ? spec_insn_sh_rs2_addr : spec_insn_sll_valid ? spec_insn_sll_rs2_addr : spec_insn_slli_valid ? spec_insn_slli_rs2_addr : spec_insn_slliw_valid ? spec_insn_slliw_rs2_addr : spec_insn_sllw_valid ? spec_insn_sllw_rs2_addr : spec_insn_slt_valid ? spec_insn_slt_rs2_addr : spec_insn_slti_valid ? spec_insn_slti_rs2_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : spec_insn_sra_valid ? spec_insn_sra_rs2_addr : spec_insn_srai_valid ? spec_insn_srai_rs2_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_rs2_addr : spec_insn_sraw_valid ? spec_insn_sraw_rs2_addr : spec_insn_srl_valid ? spec_insn_srl_rs2_addr : spec_insn_srli_valid ? spec_insn_srli_rs2_addr : spec_insn_srliw_valid ? spec_insn_srliw_rs2_addr : spec_insn_srlw_valid ? spec_insn_srlw_rs2_addr : spec_insn_sub_valid ? spec_insn_sub_rs2_addr : spec_insn_subw_valid ? spec_insn_subw_rs2_addr : spec_insn_sw_valid ? spec_insn_sw_rs2_addr : spec_insn_xor_valid ? spec_insn_xor_rs2_addr : spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; assign spec_rd_addr = spec_insn_add_valid ? spec_insn_add_rd_addr : spec_insn_addi_valid ? spec_insn_addi_rd_addr : spec_insn_addiw_valid ? spec_insn_addiw_rd_addr : spec_insn_addw_valid ? spec_insn_addw_rd_addr : spec_insn_and_valid ? spec_insn_and_rd_addr : spec_insn_andi_valid ? spec_insn_andi_rd_addr : spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : spec_insn_beq_valid ? spec_insn_beq_rd_addr : spec_insn_bge_valid ? spec_insn_bge_rd_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : spec_insn_blt_valid ? spec_insn_blt_rd_addr : spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : spec_insn_bne_valid ? spec_insn_bne_rd_addr : spec_insn_jal_valid ? spec_insn_jal_rd_addr : spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : spec_insn_lb_valid ? spec_insn_lb_rd_addr : spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : spec_insn_ld_valid ? spec_insn_ld_rd_addr : spec_insn_lh_valid ? spec_insn_lh_rd_addr : spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : spec_insn_lui_valid ? spec_insn_lui_rd_addr : spec_insn_lw_valid ? spec_insn_lw_rd_addr : spec_insn_lwu_valid ? spec_insn_lwu_rd_addr : spec_insn_or_valid ? spec_insn_or_rd_addr : spec_insn_ori_valid ? spec_insn_ori_rd_addr : spec_insn_sb_valid ? spec_insn_sb_rd_addr : spec_insn_sd_valid ? spec_insn_sd_rd_addr : spec_insn_sh_valid ? spec_insn_sh_rd_addr : spec_insn_sll_valid ? spec_insn_sll_rd_addr : spec_insn_slli_valid ? spec_insn_slli_rd_addr : spec_insn_slliw_valid ? spec_insn_slliw_rd_addr : spec_insn_sllw_valid ? spec_insn_sllw_rd_addr : spec_insn_slt_valid ? spec_insn_slt_rd_addr : spec_insn_slti_valid ? spec_insn_slti_rd_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : spec_insn_sra_valid ? spec_insn_sra_rd_addr : spec_insn_srai_valid ? spec_insn_srai_rd_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_rd_addr : spec_insn_sraw_valid ? spec_insn_sraw_rd_addr : spec_insn_srl_valid ? spec_insn_srl_rd_addr : spec_insn_srli_valid ? spec_insn_srli_rd_addr : spec_insn_srliw_valid ? spec_insn_srliw_rd_addr : spec_insn_srlw_valid ? spec_insn_srlw_rd_addr : spec_insn_sub_valid ? spec_insn_sub_rd_addr : spec_insn_subw_valid ? spec_insn_subw_rd_addr : spec_insn_sw_valid ? spec_insn_sw_rd_addr : spec_insn_xor_valid ? spec_insn_xor_rd_addr : spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; assign spec_rd_wdata = spec_insn_add_valid ? spec_insn_add_rd_wdata : spec_insn_addi_valid ? spec_insn_addi_rd_wdata : spec_insn_addiw_valid ? spec_insn_addiw_rd_wdata : spec_insn_addw_valid ? spec_insn_addw_rd_wdata : spec_insn_and_valid ? spec_insn_and_rd_wdata : spec_insn_andi_valid ? spec_insn_andi_rd_wdata : spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : spec_insn_beq_valid ? spec_insn_beq_rd_wdata : spec_insn_bge_valid ? spec_insn_bge_rd_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : spec_insn_blt_valid ? spec_insn_blt_rd_wdata : spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : spec_insn_bne_valid ? spec_insn_bne_rd_wdata : spec_insn_jal_valid ? spec_insn_jal_rd_wdata : spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : spec_insn_lb_valid ? spec_insn_lb_rd_wdata : spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : spec_insn_ld_valid ? spec_insn_ld_rd_wdata : spec_insn_lh_valid ? spec_insn_lh_rd_wdata : spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : spec_insn_lui_valid ? spec_insn_lui_rd_wdata : spec_insn_lw_valid ? spec_insn_lw_rd_wdata : spec_insn_lwu_valid ? spec_insn_lwu_rd_wdata : spec_insn_or_valid ? spec_insn_or_rd_wdata : spec_insn_ori_valid ? spec_insn_ori_rd_wdata : spec_insn_sb_valid ? spec_insn_sb_rd_wdata : spec_insn_sd_valid ? spec_insn_sd_rd_wdata : spec_insn_sh_valid ? spec_insn_sh_rd_wdata : spec_insn_sll_valid ? spec_insn_sll_rd_wdata : spec_insn_slli_valid ? spec_insn_slli_rd_wdata : spec_insn_slliw_valid ? spec_insn_slliw_rd_wdata : spec_insn_sllw_valid ? spec_insn_sllw_rd_wdata : spec_insn_slt_valid ? spec_insn_slt_rd_wdata : spec_insn_slti_valid ? spec_insn_slti_rd_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : spec_insn_sra_valid ? spec_insn_sra_rd_wdata : spec_insn_srai_valid ? spec_insn_srai_rd_wdata : spec_insn_sraiw_valid ? spec_insn_sraiw_rd_wdata : spec_insn_sraw_valid ? spec_insn_sraw_rd_wdata : spec_insn_srl_valid ? spec_insn_srl_rd_wdata : spec_insn_srli_valid ? spec_insn_srli_rd_wdata : spec_insn_srliw_valid ? spec_insn_srliw_rd_wdata : spec_insn_srlw_valid ? spec_insn_srlw_rd_wdata : spec_insn_sub_valid ? spec_insn_sub_rd_wdata : spec_insn_subw_valid ? spec_insn_subw_rd_wdata : spec_insn_sw_valid ? spec_insn_sw_rd_wdata : spec_insn_xor_valid ? spec_insn_xor_rd_wdata : spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; assign spec_pc_wdata = spec_insn_add_valid ? spec_insn_add_pc_wdata : spec_insn_addi_valid ? spec_insn_addi_pc_wdata : spec_insn_addiw_valid ? spec_insn_addiw_pc_wdata : spec_insn_addw_valid ? spec_insn_addw_pc_wdata : spec_insn_and_valid ? spec_insn_and_pc_wdata : spec_insn_andi_valid ? spec_insn_andi_pc_wdata : spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : spec_insn_beq_valid ? spec_insn_beq_pc_wdata : spec_insn_bge_valid ? spec_insn_bge_pc_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : spec_insn_blt_valid ? spec_insn_blt_pc_wdata : spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : spec_insn_bne_valid ? spec_insn_bne_pc_wdata : spec_insn_jal_valid ? spec_insn_jal_pc_wdata : spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : spec_insn_lb_valid ? spec_insn_lb_pc_wdata : spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : spec_insn_ld_valid ? spec_insn_ld_pc_wdata : spec_insn_lh_valid ? spec_insn_lh_pc_wdata : spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : spec_insn_lui_valid ? spec_insn_lui_pc_wdata : spec_insn_lw_valid ? spec_insn_lw_pc_wdata : spec_insn_lwu_valid ? spec_insn_lwu_pc_wdata : spec_insn_or_valid ? spec_insn_or_pc_wdata : spec_insn_ori_valid ? spec_insn_ori_pc_wdata : spec_insn_sb_valid ? spec_insn_sb_pc_wdata : spec_insn_sd_valid ? spec_insn_sd_pc_wdata : spec_insn_sh_valid ? spec_insn_sh_pc_wdata : spec_insn_sll_valid ? spec_insn_sll_pc_wdata : spec_insn_slli_valid ? spec_insn_slli_pc_wdata : spec_insn_slliw_valid ? spec_insn_slliw_pc_wdata : spec_insn_sllw_valid ? spec_insn_sllw_pc_wdata : spec_insn_slt_valid ? spec_insn_slt_pc_wdata : spec_insn_slti_valid ? spec_insn_slti_pc_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : spec_insn_sra_valid ? spec_insn_sra_pc_wdata : spec_insn_srai_valid ? spec_insn_srai_pc_wdata : spec_insn_sraiw_valid ? spec_insn_sraiw_pc_wdata : spec_insn_sraw_valid ? spec_insn_sraw_pc_wdata : spec_insn_srl_valid ? spec_insn_srl_pc_wdata : spec_insn_srli_valid ? spec_insn_srli_pc_wdata : spec_insn_srliw_valid ? spec_insn_srliw_pc_wdata : spec_insn_srlw_valid ? spec_insn_srlw_pc_wdata : spec_insn_sub_valid ? spec_insn_sub_pc_wdata : spec_insn_subw_valid ? spec_insn_subw_pc_wdata : spec_insn_sw_valid ? spec_insn_sw_pc_wdata : spec_insn_xor_valid ? spec_insn_xor_pc_wdata : spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; assign spec_mem_addr = spec_insn_add_valid ? spec_insn_add_mem_addr : spec_insn_addi_valid ? spec_insn_addi_mem_addr : spec_insn_addiw_valid ? spec_insn_addiw_mem_addr : spec_insn_addw_valid ? spec_insn_addw_mem_addr : spec_insn_and_valid ? spec_insn_and_mem_addr : spec_insn_andi_valid ? spec_insn_andi_mem_addr : spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : spec_insn_beq_valid ? spec_insn_beq_mem_addr : spec_insn_bge_valid ? spec_insn_bge_mem_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : spec_insn_blt_valid ? spec_insn_blt_mem_addr : spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : spec_insn_bne_valid ? spec_insn_bne_mem_addr : spec_insn_jal_valid ? spec_insn_jal_mem_addr : spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : spec_insn_lb_valid ? spec_insn_lb_mem_addr : spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : spec_insn_ld_valid ? spec_insn_ld_mem_addr : spec_insn_lh_valid ? spec_insn_lh_mem_addr : spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : spec_insn_lui_valid ? spec_insn_lui_mem_addr : spec_insn_lw_valid ? spec_insn_lw_mem_addr : spec_insn_lwu_valid ? spec_insn_lwu_mem_addr : spec_insn_or_valid ? spec_insn_or_mem_addr : spec_insn_ori_valid ? spec_insn_ori_mem_addr : spec_insn_sb_valid ? spec_insn_sb_mem_addr : spec_insn_sd_valid ? spec_insn_sd_mem_addr : spec_insn_sh_valid ? spec_insn_sh_mem_addr : spec_insn_sll_valid ? spec_insn_sll_mem_addr : spec_insn_slli_valid ? spec_insn_slli_mem_addr : spec_insn_slliw_valid ? spec_insn_slliw_mem_addr : spec_insn_sllw_valid ? spec_insn_sllw_mem_addr : spec_insn_slt_valid ? spec_insn_slt_mem_addr : spec_insn_slti_valid ? spec_insn_slti_mem_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : spec_insn_sra_valid ? spec_insn_sra_mem_addr : spec_insn_srai_valid ? spec_insn_srai_mem_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_addr : spec_insn_sraw_valid ? spec_insn_sraw_mem_addr : spec_insn_srl_valid ? spec_insn_srl_mem_addr : spec_insn_srli_valid ? spec_insn_srli_mem_addr : spec_insn_srliw_valid ? spec_insn_srliw_mem_addr : spec_insn_srlw_valid ? spec_insn_srlw_mem_addr : spec_insn_sub_valid ? spec_insn_sub_mem_addr : spec_insn_subw_valid ? spec_insn_subw_mem_addr : spec_insn_sw_valid ? spec_insn_sw_mem_addr : spec_insn_xor_valid ? spec_insn_xor_mem_addr : spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; assign spec_mem_rmask = spec_insn_add_valid ? spec_insn_add_mem_rmask : spec_insn_addi_valid ? spec_insn_addi_mem_rmask : spec_insn_addiw_valid ? spec_insn_addiw_mem_rmask : spec_insn_addw_valid ? spec_insn_addw_mem_rmask : spec_insn_and_valid ? spec_insn_and_mem_rmask : spec_insn_andi_valid ? spec_insn_andi_mem_rmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : spec_insn_beq_valid ? spec_insn_beq_mem_rmask : spec_insn_bge_valid ? spec_insn_bge_mem_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : spec_insn_blt_valid ? spec_insn_blt_mem_rmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : spec_insn_bne_valid ? spec_insn_bne_mem_rmask : spec_insn_jal_valid ? spec_insn_jal_mem_rmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : spec_insn_lb_valid ? spec_insn_lb_mem_rmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : spec_insn_ld_valid ? spec_insn_ld_mem_rmask : spec_insn_lh_valid ? spec_insn_lh_mem_rmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : spec_insn_lui_valid ? spec_insn_lui_mem_rmask : spec_insn_lw_valid ? spec_insn_lw_mem_rmask : spec_insn_lwu_valid ? spec_insn_lwu_mem_rmask : spec_insn_or_valid ? spec_insn_or_mem_rmask : spec_insn_ori_valid ? spec_insn_ori_mem_rmask : spec_insn_sb_valid ? spec_insn_sb_mem_rmask : spec_insn_sd_valid ? spec_insn_sd_mem_rmask : spec_insn_sh_valid ? spec_insn_sh_mem_rmask : spec_insn_sll_valid ? spec_insn_sll_mem_rmask : spec_insn_slli_valid ? spec_insn_slli_mem_rmask : spec_insn_slliw_valid ? spec_insn_slliw_mem_rmask : spec_insn_sllw_valid ? spec_insn_sllw_mem_rmask : spec_insn_slt_valid ? spec_insn_slt_mem_rmask : spec_insn_slti_valid ? spec_insn_slti_mem_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : spec_insn_sra_valid ? spec_insn_sra_mem_rmask : spec_insn_srai_valid ? spec_insn_srai_mem_rmask : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_rmask : spec_insn_sraw_valid ? spec_insn_sraw_mem_rmask : spec_insn_srl_valid ? spec_insn_srl_mem_rmask : spec_insn_srli_valid ? spec_insn_srli_mem_rmask : spec_insn_srliw_valid ? spec_insn_srliw_mem_rmask : spec_insn_srlw_valid ? spec_insn_srlw_mem_rmask : spec_insn_sub_valid ? spec_insn_sub_mem_rmask : spec_insn_subw_valid ? spec_insn_subw_mem_rmask : spec_insn_sw_valid ? spec_insn_sw_mem_rmask : spec_insn_xor_valid ? spec_insn_xor_mem_rmask : spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; assign spec_mem_wmask = spec_insn_add_valid ? spec_insn_add_mem_wmask : spec_insn_addi_valid ? spec_insn_addi_mem_wmask : spec_insn_addiw_valid ? spec_insn_addiw_mem_wmask : spec_insn_addw_valid ? spec_insn_addw_mem_wmask : spec_insn_and_valid ? spec_insn_and_mem_wmask : spec_insn_andi_valid ? spec_insn_andi_mem_wmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : spec_insn_beq_valid ? spec_insn_beq_mem_wmask : spec_insn_bge_valid ? spec_insn_bge_mem_wmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : spec_insn_blt_valid ? spec_insn_blt_mem_wmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : spec_insn_bne_valid ? spec_insn_bne_mem_wmask : spec_insn_jal_valid ? spec_insn_jal_mem_wmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : spec_insn_lb_valid ? spec_insn_lb_mem_wmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : spec_insn_ld_valid ? spec_insn_ld_mem_wmask : spec_insn_lh_valid ? spec_insn_lh_mem_wmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : spec_insn_lui_valid ? spec_insn_lui_mem_wmask : spec_insn_lw_valid ? spec_insn_lw_mem_wmask : spec_insn_lwu_valid ? spec_insn_lwu_mem_wmask : spec_insn_or_valid ? spec_insn_or_mem_wmask : spec_insn_ori_valid ? spec_insn_ori_mem_wmask : spec_insn_sb_valid ? spec_insn_sb_mem_wmask : spec_insn_sd_valid ? spec_insn_sd_mem_wmask : spec_insn_sh_valid ? spec_insn_sh_mem_wmask : spec_insn_sll_valid ? spec_insn_sll_mem_wmask : spec_insn_slli_valid ? spec_insn_slli_mem_wmask : spec_insn_slliw_valid ? spec_insn_slliw_mem_wmask : spec_insn_sllw_valid ? spec_insn_sllw_mem_wmask : spec_insn_slt_valid ? spec_insn_slt_mem_wmask : spec_insn_slti_valid ? spec_insn_slti_mem_wmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : spec_insn_sra_valid ? spec_insn_sra_mem_wmask : spec_insn_srai_valid ? spec_insn_srai_mem_wmask : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wmask : spec_insn_sraw_valid ? spec_insn_sraw_mem_wmask : spec_insn_srl_valid ? spec_insn_srl_mem_wmask : spec_insn_srli_valid ? spec_insn_srli_mem_wmask : spec_insn_srliw_valid ? spec_insn_srliw_mem_wmask : spec_insn_srlw_valid ? spec_insn_srlw_mem_wmask : spec_insn_sub_valid ? spec_insn_sub_mem_wmask : spec_insn_subw_valid ? spec_insn_subw_mem_wmask : spec_insn_sw_valid ? spec_insn_sw_mem_wmask : spec_insn_xor_valid ? spec_insn_xor_mem_wmask : spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; assign spec_mem_wdata = spec_insn_add_valid ? spec_insn_add_mem_wdata : spec_insn_addi_valid ? spec_insn_addi_mem_wdata : spec_insn_addiw_valid ? spec_insn_addiw_mem_wdata : spec_insn_addw_valid ? spec_insn_addw_mem_wdata : spec_insn_and_valid ? spec_insn_and_mem_wdata : spec_insn_andi_valid ? spec_insn_andi_mem_wdata : spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : spec_insn_beq_valid ? spec_insn_beq_mem_wdata : spec_insn_bge_valid ? spec_insn_bge_mem_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : spec_insn_blt_valid ? spec_insn_blt_mem_wdata : spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : spec_insn_bne_valid ? spec_insn_bne_mem_wdata : spec_insn_jal_valid ? spec_insn_jal_mem_wdata : spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : spec_insn_lb_valid ? spec_insn_lb_mem_wdata : spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : spec_insn_ld_valid ? spec_insn_ld_mem_wdata : spec_insn_lh_valid ? spec_insn_lh_mem_wdata : spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : spec_insn_lui_valid ? spec_insn_lui_mem_wdata : spec_insn_lw_valid ? spec_insn_lw_mem_wdata : spec_insn_lwu_valid ? spec_insn_lwu_mem_wdata : spec_insn_or_valid ? spec_insn_or_mem_wdata : spec_insn_ori_valid ? spec_insn_ori_mem_wdata : spec_insn_sb_valid ? spec_insn_sb_mem_wdata : spec_insn_sd_valid ? spec_insn_sd_mem_wdata : spec_insn_sh_valid ? spec_insn_sh_mem_wdata : spec_insn_sll_valid ? spec_insn_sll_mem_wdata : spec_insn_slli_valid ? spec_insn_slli_mem_wdata : spec_insn_slliw_valid ? spec_insn_slliw_mem_wdata : spec_insn_sllw_valid ? spec_insn_sllw_mem_wdata : spec_insn_slt_valid ? spec_insn_slt_mem_wdata : spec_insn_slti_valid ? spec_insn_slti_mem_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : spec_insn_sra_valid ? spec_insn_sra_mem_wdata : spec_insn_srai_valid ? spec_insn_srai_mem_wdata : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wdata : spec_insn_sraw_valid ? spec_insn_sraw_mem_wdata : spec_insn_srl_valid ? spec_insn_srl_mem_wdata : spec_insn_srli_valid ? spec_insn_srli_mem_wdata : spec_insn_srliw_valid ? spec_insn_srliw_mem_wdata : spec_insn_srlw_valid ? spec_insn_srlw_mem_wdata : spec_insn_sub_valid ? spec_insn_sub_mem_wdata : spec_insn_subw_valid ? spec_insn_subw_mem_wdata : spec_insn_sw_valid ? spec_insn_sw_mem_wdata : spec_insn_xor_valid ? spec_insn_xor_mem_wdata : spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; `ifdef RISCV_FORMAL_CSR_MISA assign spec_csr_misa_rmask = spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : spec_insn_addiw_valid ? spec_insn_addiw_csr_misa_rmask : spec_insn_addw_valid ? spec_insn_addw_csr_misa_rmask : spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : spec_insn_ld_valid ? spec_insn_ld_csr_misa_rmask : spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : spec_insn_lwu_valid ? spec_insn_lwu_csr_misa_rmask : spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : spec_insn_sd_valid ? spec_insn_sd_csr_misa_rmask : spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : spec_insn_slliw_valid ? spec_insn_slliw_csr_misa_rmask : spec_insn_sllw_valid ? spec_insn_sllw_csr_misa_rmask : spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : spec_insn_sraiw_valid ? spec_insn_sraiw_csr_misa_rmask : spec_insn_sraw_valid ? spec_insn_sraw_csr_misa_rmask : spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : spec_insn_srliw_valid ? spec_insn_srliw_csr_misa_rmask : spec_insn_srlw_valid ? spec_insn_srlw_csr_misa_rmask : spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : spec_insn_subw_valid ? spec_insn_subw_csr_misa_rmask : spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; `endif endmodule ================================================ FILE: insns/isa_rv64ic.txt ================================================ add addi addiw addw and andi auipc beq bge bgeu blt bltu bne c_add c_addi c_addi16sp c_addi4spn c_addiw c_addw c_and c_andi c_beqz c_bnez c_j c_jalr c_jr c_ld c_ldsp c_li c_lui c_lw c_lwsp c_mv c_or c_sd c_sdsp c_slli c_srai c_srli c_sub c_subw c_sw c_swsp c_xor jal jalr lb lbu ld lh lhu lui lw lwu or ori sb sd sh sll slli slliw sllw slt slti sltiu sltu sra srai sraiw sraw srl srli srliw srlw sub subw sw xor xori ================================================ FILE: insns/isa_rv64ic.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_isa_rv64ic ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); wire spec_insn_add_valid; wire spec_insn_add_trap; wire [ 4 : 0] spec_insn_add_rs1_addr; wire [ 4 : 0] spec_insn_add_rs2_addr; wire [ 4 : 0] spec_insn_add_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; `endif rvfi_insn_add insn_add ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), `endif .spec_valid(spec_insn_add_valid), .spec_trap(spec_insn_add_trap), .spec_rs1_addr(spec_insn_add_rs1_addr), .spec_rs2_addr(spec_insn_add_rs2_addr), .spec_rd_addr(spec_insn_add_rd_addr), .spec_rd_wdata(spec_insn_add_rd_wdata), .spec_pc_wdata(spec_insn_add_pc_wdata), .spec_mem_addr(spec_insn_add_mem_addr), .spec_mem_rmask(spec_insn_add_mem_rmask), .spec_mem_wmask(spec_insn_add_mem_wmask), .spec_mem_wdata(spec_insn_add_mem_wdata) ); wire spec_insn_addi_valid; wire spec_insn_addi_trap; wire [ 4 : 0] spec_insn_addi_rs1_addr; wire [ 4 : 0] spec_insn_addi_rs2_addr; wire [ 4 : 0] spec_insn_addi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; `endif rvfi_insn_addi insn_addi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), `endif .spec_valid(spec_insn_addi_valid), .spec_trap(spec_insn_addi_trap), .spec_rs1_addr(spec_insn_addi_rs1_addr), .spec_rs2_addr(spec_insn_addi_rs2_addr), .spec_rd_addr(spec_insn_addi_rd_addr), .spec_rd_wdata(spec_insn_addi_rd_wdata), .spec_pc_wdata(spec_insn_addi_pc_wdata), .spec_mem_addr(spec_insn_addi_mem_addr), .spec_mem_rmask(spec_insn_addi_mem_rmask), .spec_mem_wmask(spec_insn_addi_mem_wmask), .spec_mem_wdata(spec_insn_addi_mem_wdata) ); wire spec_insn_addiw_valid; wire spec_insn_addiw_trap; wire [ 4 : 0] spec_insn_addiw_rs1_addr; wire [ 4 : 0] spec_insn_addiw_rs2_addr; wire [ 4 : 0] spec_insn_addiw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_csr_misa_rmask; `endif rvfi_insn_addiw insn_addiw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addiw_csr_misa_rmask), `endif .spec_valid(spec_insn_addiw_valid), .spec_trap(spec_insn_addiw_trap), .spec_rs1_addr(spec_insn_addiw_rs1_addr), .spec_rs2_addr(spec_insn_addiw_rs2_addr), .spec_rd_addr(spec_insn_addiw_rd_addr), .spec_rd_wdata(spec_insn_addiw_rd_wdata), .spec_pc_wdata(spec_insn_addiw_pc_wdata), .spec_mem_addr(spec_insn_addiw_mem_addr), .spec_mem_rmask(spec_insn_addiw_mem_rmask), .spec_mem_wmask(spec_insn_addiw_mem_wmask), .spec_mem_wdata(spec_insn_addiw_mem_wdata) ); wire spec_insn_addw_valid; wire spec_insn_addw_trap; wire [ 4 : 0] spec_insn_addw_rs1_addr; wire [ 4 : 0] spec_insn_addw_rs2_addr; wire [ 4 : 0] spec_insn_addw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_csr_misa_rmask; `endif rvfi_insn_addw insn_addw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addw_csr_misa_rmask), `endif .spec_valid(spec_insn_addw_valid), .spec_trap(spec_insn_addw_trap), .spec_rs1_addr(spec_insn_addw_rs1_addr), .spec_rs2_addr(spec_insn_addw_rs2_addr), .spec_rd_addr(spec_insn_addw_rd_addr), .spec_rd_wdata(spec_insn_addw_rd_wdata), .spec_pc_wdata(spec_insn_addw_pc_wdata), .spec_mem_addr(spec_insn_addw_mem_addr), .spec_mem_rmask(spec_insn_addw_mem_rmask), .spec_mem_wmask(spec_insn_addw_mem_wmask), .spec_mem_wdata(spec_insn_addw_mem_wdata) ); wire spec_insn_and_valid; wire spec_insn_and_trap; wire [ 4 : 0] spec_insn_and_rs1_addr; wire [ 4 : 0] spec_insn_and_rs2_addr; wire [ 4 : 0] spec_insn_and_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; `endif rvfi_insn_and insn_and ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), `endif .spec_valid(spec_insn_and_valid), .spec_trap(spec_insn_and_trap), .spec_rs1_addr(spec_insn_and_rs1_addr), .spec_rs2_addr(spec_insn_and_rs2_addr), .spec_rd_addr(spec_insn_and_rd_addr), .spec_rd_wdata(spec_insn_and_rd_wdata), .spec_pc_wdata(spec_insn_and_pc_wdata), .spec_mem_addr(spec_insn_and_mem_addr), .spec_mem_rmask(spec_insn_and_mem_rmask), .spec_mem_wmask(spec_insn_and_mem_wmask), .spec_mem_wdata(spec_insn_and_mem_wdata) ); wire spec_insn_andi_valid; wire spec_insn_andi_trap; wire [ 4 : 0] spec_insn_andi_rs1_addr; wire [ 4 : 0] spec_insn_andi_rs2_addr; wire [ 4 : 0] spec_insn_andi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; `endif rvfi_insn_andi insn_andi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), `endif .spec_valid(spec_insn_andi_valid), .spec_trap(spec_insn_andi_trap), .spec_rs1_addr(spec_insn_andi_rs1_addr), .spec_rs2_addr(spec_insn_andi_rs2_addr), .spec_rd_addr(spec_insn_andi_rd_addr), .spec_rd_wdata(spec_insn_andi_rd_wdata), .spec_pc_wdata(spec_insn_andi_pc_wdata), .spec_mem_addr(spec_insn_andi_mem_addr), .spec_mem_rmask(spec_insn_andi_mem_rmask), .spec_mem_wmask(spec_insn_andi_mem_wmask), .spec_mem_wdata(spec_insn_andi_mem_wdata) ); wire spec_insn_auipc_valid; wire spec_insn_auipc_trap; wire [ 4 : 0] spec_insn_auipc_rs1_addr; wire [ 4 : 0] spec_insn_auipc_rs2_addr; wire [ 4 : 0] spec_insn_auipc_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; `endif rvfi_insn_auipc insn_auipc ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), `endif .spec_valid(spec_insn_auipc_valid), .spec_trap(spec_insn_auipc_trap), .spec_rs1_addr(spec_insn_auipc_rs1_addr), .spec_rs2_addr(spec_insn_auipc_rs2_addr), .spec_rd_addr(spec_insn_auipc_rd_addr), .spec_rd_wdata(spec_insn_auipc_rd_wdata), .spec_pc_wdata(spec_insn_auipc_pc_wdata), .spec_mem_addr(spec_insn_auipc_mem_addr), .spec_mem_rmask(spec_insn_auipc_mem_rmask), .spec_mem_wmask(spec_insn_auipc_mem_wmask), .spec_mem_wdata(spec_insn_auipc_mem_wdata) ); wire spec_insn_beq_valid; wire spec_insn_beq_trap; wire [ 4 : 0] spec_insn_beq_rs1_addr; wire [ 4 : 0] spec_insn_beq_rs2_addr; wire [ 4 : 0] spec_insn_beq_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; `endif rvfi_insn_beq insn_beq ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), `endif .spec_valid(spec_insn_beq_valid), .spec_trap(spec_insn_beq_trap), .spec_rs1_addr(spec_insn_beq_rs1_addr), .spec_rs2_addr(spec_insn_beq_rs2_addr), .spec_rd_addr(spec_insn_beq_rd_addr), .spec_rd_wdata(spec_insn_beq_rd_wdata), .spec_pc_wdata(spec_insn_beq_pc_wdata), .spec_mem_addr(spec_insn_beq_mem_addr), .spec_mem_rmask(spec_insn_beq_mem_rmask), .spec_mem_wmask(spec_insn_beq_mem_wmask), .spec_mem_wdata(spec_insn_beq_mem_wdata) ); wire spec_insn_bge_valid; wire spec_insn_bge_trap; wire [ 4 : 0] spec_insn_bge_rs1_addr; wire [ 4 : 0] spec_insn_bge_rs2_addr; wire [ 4 : 0] spec_insn_bge_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; `endif rvfi_insn_bge insn_bge ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), `endif .spec_valid(spec_insn_bge_valid), .spec_trap(spec_insn_bge_trap), .spec_rs1_addr(spec_insn_bge_rs1_addr), .spec_rs2_addr(spec_insn_bge_rs2_addr), .spec_rd_addr(spec_insn_bge_rd_addr), .spec_rd_wdata(spec_insn_bge_rd_wdata), .spec_pc_wdata(spec_insn_bge_pc_wdata), .spec_mem_addr(spec_insn_bge_mem_addr), .spec_mem_rmask(spec_insn_bge_mem_rmask), .spec_mem_wmask(spec_insn_bge_mem_wmask), .spec_mem_wdata(spec_insn_bge_mem_wdata) ); wire spec_insn_bgeu_valid; wire spec_insn_bgeu_trap; wire [ 4 : 0] spec_insn_bgeu_rs1_addr; wire [ 4 : 0] spec_insn_bgeu_rs2_addr; wire [ 4 : 0] spec_insn_bgeu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; `endif rvfi_insn_bgeu insn_bgeu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), `endif .spec_valid(spec_insn_bgeu_valid), .spec_trap(spec_insn_bgeu_trap), .spec_rs1_addr(spec_insn_bgeu_rs1_addr), .spec_rs2_addr(spec_insn_bgeu_rs2_addr), .spec_rd_addr(spec_insn_bgeu_rd_addr), .spec_rd_wdata(spec_insn_bgeu_rd_wdata), .spec_pc_wdata(spec_insn_bgeu_pc_wdata), .spec_mem_addr(spec_insn_bgeu_mem_addr), .spec_mem_rmask(spec_insn_bgeu_mem_rmask), .spec_mem_wmask(spec_insn_bgeu_mem_wmask), .spec_mem_wdata(spec_insn_bgeu_mem_wdata) ); wire spec_insn_blt_valid; wire spec_insn_blt_trap; wire [ 4 : 0] spec_insn_blt_rs1_addr; wire [ 4 : 0] spec_insn_blt_rs2_addr; wire [ 4 : 0] spec_insn_blt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; `endif rvfi_insn_blt insn_blt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), `endif .spec_valid(spec_insn_blt_valid), .spec_trap(spec_insn_blt_trap), .spec_rs1_addr(spec_insn_blt_rs1_addr), .spec_rs2_addr(spec_insn_blt_rs2_addr), .spec_rd_addr(spec_insn_blt_rd_addr), .spec_rd_wdata(spec_insn_blt_rd_wdata), .spec_pc_wdata(spec_insn_blt_pc_wdata), .spec_mem_addr(spec_insn_blt_mem_addr), .spec_mem_rmask(spec_insn_blt_mem_rmask), .spec_mem_wmask(spec_insn_blt_mem_wmask), .spec_mem_wdata(spec_insn_blt_mem_wdata) ); wire spec_insn_bltu_valid; wire spec_insn_bltu_trap; wire [ 4 : 0] spec_insn_bltu_rs1_addr; wire [ 4 : 0] spec_insn_bltu_rs2_addr; wire [ 4 : 0] spec_insn_bltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; `endif rvfi_insn_bltu insn_bltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), `endif .spec_valid(spec_insn_bltu_valid), .spec_trap(spec_insn_bltu_trap), .spec_rs1_addr(spec_insn_bltu_rs1_addr), .spec_rs2_addr(spec_insn_bltu_rs2_addr), .spec_rd_addr(spec_insn_bltu_rd_addr), .spec_rd_wdata(spec_insn_bltu_rd_wdata), .spec_pc_wdata(spec_insn_bltu_pc_wdata), .spec_mem_addr(spec_insn_bltu_mem_addr), .spec_mem_rmask(spec_insn_bltu_mem_rmask), .spec_mem_wmask(spec_insn_bltu_mem_wmask), .spec_mem_wdata(spec_insn_bltu_mem_wdata) ); wire spec_insn_bne_valid; wire spec_insn_bne_trap; wire [ 4 : 0] spec_insn_bne_rs1_addr; wire [ 4 : 0] spec_insn_bne_rs2_addr; wire [ 4 : 0] spec_insn_bne_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; `endif rvfi_insn_bne insn_bne ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), `endif .spec_valid(spec_insn_bne_valid), .spec_trap(spec_insn_bne_trap), .spec_rs1_addr(spec_insn_bne_rs1_addr), .spec_rs2_addr(spec_insn_bne_rs2_addr), .spec_rd_addr(spec_insn_bne_rd_addr), .spec_rd_wdata(spec_insn_bne_rd_wdata), .spec_pc_wdata(spec_insn_bne_pc_wdata), .spec_mem_addr(spec_insn_bne_mem_addr), .spec_mem_rmask(spec_insn_bne_mem_rmask), .spec_mem_wmask(spec_insn_bne_mem_wmask), .spec_mem_wdata(spec_insn_bne_mem_wdata) ); wire spec_insn_c_add_valid; wire spec_insn_c_add_trap; wire [ 4 : 0] spec_insn_c_add_rs1_addr; wire [ 4 : 0] spec_insn_c_add_rs2_addr; wire [ 4 : 0] spec_insn_c_add_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_csr_misa_rmask; `endif rvfi_insn_c_add insn_c_add ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_add_csr_misa_rmask), `endif .spec_valid(spec_insn_c_add_valid), .spec_trap(spec_insn_c_add_trap), .spec_rs1_addr(spec_insn_c_add_rs1_addr), .spec_rs2_addr(spec_insn_c_add_rs2_addr), .spec_rd_addr(spec_insn_c_add_rd_addr), .spec_rd_wdata(spec_insn_c_add_rd_wdata), .spec_pc_wdata(spec_insn_c_add_pc_wdata), .spec_mem_addr(spec_insn_c_add_mem_addr), .spec_mem_rmask(spec_insn_c_add_mem_rmask), .spec_mem_wmask(spec_insn_c_add_mem_wmask), .spec_mem_wdata(spec_insn_c_add_mem_wdata) ); wire spec_insn_c_addi_valid; wire spec_insn_c_addi_trap; wire [ 4 : 0] spec_insn_c_addi_rs1_addr; wire [ 4 : 0] spec_insn_c_addi_rs2_addr; wire [ 4 : 0] spec_insn_c_addi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_csr_misa_rmask; `endif rvfi_insn_c_addi insn_c_addi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addi_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addi_valid), .spec_trap(spec_insn_c_addi_trap), .spec_rs1_addr(spec_insn_c_addi_rs1_addr), .spec_rs2_addr(spec_insn_c_addi_rs2_addr), .spec_rd_addr(spec_insn_c_addi_rd_addr), .spec_rd_wdata(spec_insn_c_addi_rd_wdata), .spec_pc_wdata(spec_insn_c_addi_pc_wdata), .spec_mem_addr(spec_insn_c_addi_mem_addr), .spec_mem_rmask(spec_insn_c_addi_mem_rmask), .spec_mem_wmask(spec_insn_c_addi_mem_wmask), .spec_mem_wdata(spec_insn_c_addi_mem_wdata) ); wire spec_insn_c_addi16sp_valid; wire spec_insn_c_addi16sp_trap; wire [ 4 : 0] spec_insn_c_addi16sp_rs1_addr; wire [ 4 : 0] spec_insn_c_addi16sp_rs2_addr; wire [ 4 : 0] spec_insn_c_addi16sp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_csr_misa_rmask; `endif rvfi_insn_c_addi16sp insn_c_addi16sp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addi16sp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addi16sp_valid), .spec_trap(spec_insn_c_addi16sp_trap), .spec_rs1_addr(spec_insn_c_addi16sp_rs1_addr), .spec_rs2_addr(spec_insn_c_addi16sp_rs2_addr), .spec_rd_addr(spec_insn_c_addi16sp_rd_addr), .spec_rd_wdata(spec_insn_c_addi16sp_rd_wdata), .spec_pc_wdata(spec_insn_c_addi16sp_pc_wdata), .spec_mem_addr(spec_insn_c_addi16sp_mem_addr), .spec_mem_rmask(spec_insn_c_addi16sp_mem_rmask), .spec_mem_wmask(spec_insn_c_addi16sp_mem_wmask), .spec_mem_wdata(spec_insn_c_addi16sp_mem_wdata) ); wire spec_insn_c_addi4spn_valid; wire spec_insn_c_addi4spn_trap; wire [ 4 : 0] spec_insn_c_addi4spn_rs1_addr; wire [ 4 : 0] spec_insn_c_addi4spn_rs2_addr; wire [ 4 : 0] spec_insn_c_addi4spn_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_csr_misa_rmask; `endif rvfi_insn_c_addi4spn insn_c_addi4spn ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addi4spn_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addi4spn_valid), .spec_trap(spec_insn_c_addi4spn_trap), .spec_rs1_addr(spec_insn_c_addi4spn_rs1_addr), .spec_rs2_addr(spec_insn_c_addi4spn_rs2_addr), .spec_rd_addr(spec_insn_c_addi4spn_rd_addr), .spec_rd_wdata(spec_insn_c_addi4spn_rd_wdata), .spec_pc_wdata(spec_insn_c_addi4spn_pc_wdata), .spec_mem_addr(spec_insn_c_addi4spn_mem_addr), .spec_mem_rmask(spec_insn_c_addi4spn_mem_rmask), .spec_mem_wmask(spec_insn_c_addi4spn_mem_wmask), .spec_mem_wdata(spec_insn_c_addi4spn_mem_wdata) ); wire spec_insn_c_addiw_valid; wire spec_insn_c_addiw_trap; wire [ 4 : 0] spec_insn_c_addiw_rs1_addr; wire [ 4 : 0] spec_insn_c_addiw_rs2_addr; wire [ 4 : 0] spec_insn_c_addiw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addiw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addiw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addiw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addiw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addiw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addiw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addiw_csr_misa_rmask; `endif rvfi_insn_c_addiw insn_c_addiw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addiw_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addiw_valid), .spec_trap(spec_insn_c_addiw_trap), .spec_rs1_addr(spec_insn_c_addiw_rs1_addr), .spec_rs2_addr(spec_insn_c_addiw_rs2_addr), .spec_rd_addr(spec_insn_c_addiw_rd_addr), .spec_rd_wdata(spec_insn_c_addiw_rd_wdata), .spec_pc_wdata(spec_insn_c_addiw_pc_wdata), .spec_mem_addr(spec_insn_c_addiw_mem_addr), .spec_mem_rmask(spec_insn_c_addiw_mem_rmask), .spec_mem_wmask(spec_insn_c_addiw_mem_wmask), .spec_mem_wdata(spec_insn_c_addiw_mem_wdata) ); wire spec_insn_c_addw_valid; wire spec_insn_c_addw_trap; wire [ 4 : 0] spec_insn_c_addw_rs1_addr; wire [ 4 : 0] spec_insn_c_addw_rs2_addr; wire [ 4 : 0] spec_insn_c_addw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addw_csr_misa_rmask; `endif rvfi_insn_c_addw insn_c_addw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addw_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addw_valid), .spec_trap(spec_insn_c_addw_trap), .spec_rs1_addr(spec_insn_c_addw_rs1_addr), .spec_rs2_addr(spec_insn_c_addw_rs2_addr), .spec_rd_addr(spec_insn_c_addw_rd_addr), .spec_rd_wdata(spec_insn_c_addw_rd_wdata), .spec_pc_wdata(spec_insn_c_addw_pc_wdata), .spec_mem_addr(spec_insn_c_addw_mem_addr), .spec_mem_rmask(spec_insn_c_addw_mem_rmask), .spec_mem_wmask(spec_insn_c_addw_mem_wmask), .spec_mem_wdata(spec_insn_c_addw_mem_wdata) ); wire spec_insn_c_and_valid; wire spec_insn_c_and_trap; wire [ 4 : 0] spec_insn_c_and_rs1_addr; wire [ 4 : 0] spec_insn_c_and_rs2_addr; wire [ 4 : 0] spec_insn_c_and_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_csr_misa_rmask; `endif rvfi_insn_c_and insn_c_and ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_and_csr_misa_rmask), `endif .spec_valid(spec_insn_c_and_valid), .spec_trap(spec_insn_c_and_trap), .spec_rs1_addr(spec_insn_c_and_rs1_addr), .spec_rs2_addr(spec_insn_c_and_rs2_addr), .spec_rd_addr(spec_insn_c_and_rd_addr), .spec_rd_wdata(spec_insn_c_and_rd_wdata), .spec_pc_wdata(spec_insn_c_and_pc_wdata), .spec_mem_addr(spec_insn_c_and_mem_addr), .spec_mem_rmask(spec_insn_c_and_mem_rmask), .spec_mem_wmask(spec_insn_c_and_mem_wmask), .spec_mem_wdata(spec_insn_c_and_mem_wdata) ); wire spec_insn_c_andi_valid; wire spec_insn_c_andi_trap; wire [ 4 : 0] spec_insn_c_andi_rs1_addr; wire [ 4 : 0] spec_insn_c_andi_rs2_addr; wire [ 4 : 0] spec_insn_c_andi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_csr_misa_rmask; `endif rvfi_insn_c_andi insn_c_andi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_andi_csr_misa_rmask), `endif .spec_valid(spec_insn_c_andi_valid), .spec_trap(spec_insn_c_andi_trap), .spec_rs1_addr(spec_insn_c_andi_rs1_addr), .spec_rs2_addr(spec_insn_c_andi_rs2_addr), .spec_rd_addr(spec_insn_c_andi_rd_addr), .spec_rd_wdata(spec_insn_c_andi_rd_wdata), .spec_pc_wdata(spec_insn_c_andi_pc_wdata), .spec_mem_addr(spec_insn_c_andi_mem_addr), .spec_mem_rmask(spec_insn_c_andi_mem_rmask), .spec_mem_wmask(spec_insn_c_andi_mem_wmask), .spec_mem_wdata(spec_insn_c_andi_mem_wdata) ); wire spec_insn_c_beqz_valid; wire spec_insn_c_beqz_trap; wire [ 4 : 0] spec_insn_c_beqz_rs1_addr; wire [ 4 : 0] spec_insn_c_beqz_rs2_addr; wire [ 4 : 0] spec_insn_c_beqz_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_csr_misa_rmask; `endif rvfi_insn_c_beqz insn_c_beqz ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_beqz_csr_misa_rmask), `endif .spec_valid(spec_insn_c_beqz_valid), .spec_trap(spec_insn_c_beqz_trap), .spec_rs1_addr(spec_insn_c_beqz_rs1_addr), .spec_rs2_addr(spec_insn_c_beqz_rs2_addr), .spec_rd_addr(spec_insn_c_beqz_rd_addr), .spec_rd_wdata(spec_insn_c_beqz_rd_wdata), .spec_pc_wdata(spec_insn_c_beqz_pc_wdata), .spec_mem_addr(spec_insn_c_beqz_mem_addr), .spec_mem_rmask(spec_insn_c_beqz_mem_rmask), .spec_mem_wmask(spec_insn_c_beqz_mem_wmask), .spec_mem_wdata(spec_insn_c_beqz_mem_wdata) ); wire spec_insn_c_bnez_valid; wire spec_insn_c_bnez_trap; wire [ 4 : 0] spec_insn_c_bnez_rs1_addr; wire [ 4 : 0] spec_insn_c_bnez_rs2_addr; wire [ 4 : 0] spec_insn_c_bnez_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_csr_misa_rmask; `endif rvfi_insn_c_bnez insn_c_bnez ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_bnez_csr_misa_rmask), `endif .spec_valid(spec_insn_c_bnez_valid), .spec_trap(spec_insn_c_bnez_trap), .spec_rs1_addr(spec_insn_c_bnez_rs1_addr), .spec_rs2_addr(spec_insn_c_bnez_rs2_addr), .spec_rd_addr(spec_insn_c_bnez_rd_addr), .spec_rd_wdata(spec_insn_c_bnez_rd_wdata), .spec_pc_wdata(spec_insn_c_bnez_pc_wdata), .spec_mem_addr(spec_insn_c_bnez_mem_addr), .spec_mem_rmask(spec_insn_c_bnez_mem_rmask), .spec_mem_wmask(spec_insn_c_bnez_mem_wmask), .spec_mem_wdata(spec_insn_c_bnez_mem_wdata) ); wire spec_insn_c_j_valid; wire spec_insn_c_j_trap; wire [ 4 : 0] spec_insn_c_j_rs1_addr; wire [ 4 : 0] spec_insn_c_j_rs2_addr; wire [ 4 : 0] spec_insn_c_j_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_csr_misa_rmask; `endif rvfi_insn_c_j insn_c_j ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_j_csr_misa_rmask), `endif .spec_valid(spec_insn_c_j_valid), .spec_trap(spec_insn_c_j_trap), .spec_rs1_addr(spec_insn_c_j_rs1_addr), .spec_rs2_addr(spec_insn_c_j_rs2_addr), .spec_rd_addr(spec_insn_c_j_rd_addr), .spec_rd_wdata(spec_insn_c_j_rd_wdata), .spec_pc_wdata(spec_insn_c_j_pc_wdata), .spec_mem_addr(spec_insn_c_j_mem_addr), .spec_mem_rmask(spec_insn_c_j_mem_rmask), .spec_mem_wmask(spec_insn_c_j_mem_wmask), .spec_mem_wdata(spec_insn_c_j_mem_wdata) ); wire spec_insn_c_jalr_valid; wire spec_insn_c_jalr_trap; wire [ 4 : 0] spec_insn_c_jalr_rs1_addr; wire [ 4 : 0] spec_insn_c_jalr_rs2_addr; wire [ 4 : 0] spec_insn_c_jalr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_csr_misa_rmask; `endif rvfi_insn_c_jalr insn_c_jalr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_jalr_csr_misa_rmask), `endif .spec_valid(spec_insn_c_jalr_valid), .spec_trap(spec_insn_c_jalr_trap), .spec_rs1_addr(spec_insn_c_jalr_rs1_addr), .spec_rs2_addr(spec_insn_c_jalr_rs2_addr), .spec_rd_addr(spec_insn_c_jalr_rd_addr), .spec_rd_wdata(spec_insn_c_jalr_rd_wdata), .spec_pc_wdata(spec_insn_c_jalr_pc_wdata), .spec_mem_addr(spec_insn_c_jalr_mem_addr), .spec_mem_rmask(spec_insn_c_jalr_mem_rmask), .spec_mem_wmask(spec_insn_c_jalr_mem_wmask), .spec_mem_wdata(spec_insn_c_jalr_mem_wdata) ); wire spec_insn_c_jr_valid; wire spec_insn_c_jr_trap; wire [ 4 : 0] spec_insn_c_jr_rs1_addr; wire [ 4 : 0] spec_insn_c_jr_rs2_addr; wire [ 4 : 0] spec_insn_c_jr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_csr_misa_rmask; `endif rvfi_insn_c_jr insn_c_jr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_jr_csr_misa_rmask), `endif .spec_valid(spec_insn_c_jr_valid), .spec_trap(spec_insn_c_jr_trap), .spec_rs1_addr(spec_insn_c_jr_rs1_addr), .spec_rs2_addr(spec_insn_c_jr_rs2_addr), .spec_rd_addr(spec_insn_c_jr_rd_addr), .spec_rd_wdata(spec_insn_c_jr_rd_wdata), .spec_pc_wdata(spec_insn_c_jr_pc_wdata), .spec_mem_addr(spec_insn_c_jr_mem_addr), .spec_mem_rmask(spec_insn_c_jr_mem_rmask), .spec_mem_wmask(spec_insn_c_jr_mem_wmask), .spec_mem_wdata(spec_insn_c_jr_mem_wdata) ); wire spec_insn_c_ld_valid; wire spec_insn_c_ld_trap; wire [ 4 : 0] spec_insn_c_ld_rs1_addr; wire [ 4 : 0] spec_insn_c_ld_rs2_addr; wire [ 4 : 0] spec_insn_c_ld_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ld_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ld_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ld_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ld_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ld_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ld_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ld_csr_misa_rmask; `endif rvfi_insn_c_ld insn_c_ld ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_ld_csr_misa_rmask), `endif .spec_valid(spec_insn_c_ld_valid), .spec_trap(spec_insn_c_ld_trap), .spec_rs1_addr(spec_insn_c_ld_rs1_addr), .spec_rs2_addr(spec_insn_c_ld_rs2_addr), .spec_rd_addr(spec_insn_c_ld_rd_addr), .spec_rd_wdata(spec_insn_c_ld_rd_wdata), .spec_pc_wdata(spec_insn_c_ld_pc_wdata), .spec_mem_addr(spec_insn_c_ld_mem_addr), .spec_mem_rmask(spec_insn_c_ld_mem_rmask), .spec_mem_wmask(spec_insn_c_ld_mem_wmask), .spec_mem_wdata(spec_insn_c_ld_mem_wdata) ); wire spec_insn_c_ldsp_valid; wire spec_insn_c_ldsp_trap; wire [ 4 : 0] spec_insn_c_ldsp_rs1_addr; wire [ 4 : 0] spec_insn_c_ldsp_rs2_addr; wire [ 4 : 0] spec_insn_c_ldsp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ldsp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ldsp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ldsp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ldsp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ldsp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ldsp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ldsp_csr_misa_rmask; `endif rvfi_insn_c_ldsp insn_c_ldsp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_ldsp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_ldsp_valid), .spec_trap(spec_insn_c_ldsp_trap), .spec_rs1_addr(spec_insn_c_ldsp_rs1_addr), .spec_rs2_addr(spec_insn_c_ldsp_rs2_addr), .spec_rd_addr(spec_insn_c_ldsp_rd_addr), .spec_rd_wdata(spec_insn_c_ldsp_rd_wdata), .spec_pc_wdata(spec_insn_c_ldsp_pc_wdata), .spec_mem_addr(spec_insn_c_ldsp_mem_addr), .spec_mem_rmask(spec_insn_c_ldsp_mem_rmask), .spec_mem_wmask(spec_insn_c_ldsp_mem_wmask), .spec_mem_wdata(spec_insn_c_ldsp_mem_wdata) ); wire spec_insn_c_li_valid; wire spec_insn_c_li_trap; wire [ 4 : 0] spec_insn_c_li_rs1_addr; wire [ 4 : 0] spec_insn_c_li_rs2_addr; wire [ 4 : 0] spec_insn_c_li_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_csr_misa_rmask; `endif rvfi_insn_c_li insn_c_li ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_li_csr_misa_rmask), `endif .spec_valid(spec_insn_c_li_valid), .spec_trap(spec_insn_c_li_trap), .spec_rs1_addr(spec_insn_c_li_rs1_addr), .spec_rs2_addr(spec_insn_c_li_rs2_addr), .spec_rd_addr(spec_insn_c_li_rd_addr), .spec_rd_wdata(spec_insn_c_li_rd_wdata), .spec_pc_wdata(spec_insn_c_li_pc_wdata), .spec_mem_addr(spec_insn_c_li_mem_addr), .spec_mem_rmask(spec_insn_c_li_mem_rmask), .spec_mem_wmask(spec_insn_c_li_mem_wmask), .spec_mem_wdata(spec_insn_c_li_mem_wdata) ); wire spec_insn_c_lui_valid; wire spec_insn_c_lui_trap; wire [ 4 : 0] spec_insn_c_lui_rs1_addr; wire [ 4 : 0] spec_insn_c_lui_rs2_addr; wire [ 4 : 0] spec_insn_c_lui_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_csr_misa_rmask; `endif rvfi_insn_c_lui insn_c_lui ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_lui_csr_misa_rmask), `endif .spec_valid(spec_insn_c_lui_valid), .spec_trap(spec_insn_c_lui_trap), .spec_rs1_addr(spec_insn_c_lui_rs1_addr), .spec_rs2_addr(spec_insn_c_lui_rs2_addr), .spec_rd_addr(spec_insn_c_lui_rd_addr), .spec_rd_wdata(spec_insn_c_lui_rd_wdata), .spec_pc_wdata(spec_insn_c_lui_pc_wdata), .spec_mem_addr(spec_insn_c_lui_mem_addr), .spec_mem_rmask(spec_insn_c_lui_mem_rmask), .spec_mem_wmask(spec_insn_c_lui_mem_wmask), .spec_mem_wdata(spec_insn_c_lui_mem_wdata) ); wire spec_insn_c_lw_valid; wire spec_insn_c_lw_trap; wire [ 4 : 0] spec_insn_c_lw_rs1_addr; wire [ 4 : 0] spec_insn_c_lw_rs2_addr; wire [ 4 : 0] spec_insn_c_lw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_csr_misa_rmask; `endif rvfi_insn_c_lw insn_c_lw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_lw_csr_misa_rmask), `endif .spec_valid(spec_insn_c_lw_valid), .spec_trap(spec_insn_c_lw_trap), .spec_rs1_addr(spec_insn_c_lw_rs1_addr), .spec_rs2_addr(spec_insn_c_lw_rs2_addr), .spec_rd_addr(spec_insn_c_lw_rd_addr), .spec_rd_wdata(spec_insn_c_lw_rd_wdata), .spec_pc_wdata(spec_insn_c_lw_pc_wdata), .spec_mem_addr(spec_insn_c_lw_mem_addr), .spec_mem_rmask(spec_insn_c_lw_mem_rmask), .spec_mem_wmask(spec_insn_c_lw_mem_wmask), .spec_mem_wdata(spec_insn_c_lw_mem_wdata) ); wire spec_insn_c_lwsp_valid; wire spec_insn_c_lwsp_trap; wire [ 4 : 0] spec_insn_c_lwsp_rs1_addr; wire [ 4 : 0] spec_insn_c_lwsp_rs2_addr; wire [ 4 : 0] spec_insn_c_lwsp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_csr_misa_rmask; `endif rvfi_insn_c_lwsp insn_c_lwsp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_lwsp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_lwsp_valid), .spec_trap(spec_insn_c_lwsp_trap), .spec_rs1_addr(spec_insn_c_lwsp_rs1_addr), .spec_rs2_addr(spec_insn_c_lwsp_rs2_addr), .spec_rd_addr(spec_insn_c_lwsp_rd_addr), .spec_rd_wdata(spec_insn_c_lwsp_rd_wdata), .spec_pc_wdata(spec_insn_c_lwsp_pc_wdata), .spec_mem_addr(spec_insn_c_lwsp_mem_addr), .spec_mem_rmask(spec_insn_c_lwsp_mem_rmask), .spec_mem_wmask(spec_insn_c_lwsp_mem_wmask), .spec_mem_wdata(spec_insn_c_lwsp_mem_wdata) ); wire spec_insn_c_mv_valid; wire spec_insn_c_mv_trap; wire [ 4 : 0] spec_insn_c_mv_rs1_addr; wire [ 4 : 0] spec_insn_c_mv_rs2_addr; wire [ 4 : 0] spec_insn_c_mv_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_csr_misa_rmask; `endif rvfi_insn_c_mv insn_c_mv ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_mv_csr_misa_rmask), `endif .spec_valid(spec_insn_c_mv_valid), .spec_trap(spec_insn_c_mv_trap), .spec_rs1_addr(spec_insn_c_mv_rs1_addr), .spec_rs2_addr(spec_insn_c_mv_rs2_addr), .spec_rd_addr(spec_insn_c_mv_rd_addr), .spec_rd_wdata(spec_insn_c_mv_rd_wdata), .spec_pc_wdata(spec_insn_c_mv_pc_wdata), .spec_mem_addr(spec_insn_c_mv_mem_addr), .spec_mem_rmask(spec_insn_c_mv_mem_rmask), .spec_mem_wmask(spec_insn_c_mv_mem_wmask), .spec_mem_wdata(spec_insn_c_mv_mem_wdata) ); wire spec_insn_c_or_valid; wire spec_insn_c_or_trap; wire [ 4 : 0] spec_insn_c_or_rs1_addr; wire [ 4 : 0] spec_insn_c_or_rs2_addr; wire [ 4 : 0] spec_insn_c_or_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_csr_misa_rmask; `endif rvfi_insn_c_or insn_c_or ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_or_csr_misa_rmask), `endif .spec_valid(spec_insn_c_or_valid), .spec_trap(spec_insn_c_or_trap), .spec_rs1_addr(spec_insn_c_or_rs1_addr), .spec_rs2_addr(spec_insn_c_or_rs2_addr), .spec_rd_addr(spec_insn_c_or_rd_addr), .spec_rd_wdata(spec_insn_c_or_rd_wdata), .spec_pc_wdata(spec_insn_c_or_pc_wdata), .spec_mem_addr(spec_insn_c_or_mem_addr), .spec_mem_rmask(spec_insn_c_or_mem_rmask), .spec_mem_wmask(spec_insn_c_or_mem_wmask), .spec_mem_wdata(spec_insn_c_or_mem_wdata) ); wire spec_insn_c_sd_valid; wire spec_insn_c_sd_trap; wire [ 4 : 0] spec_insn_c_sd_rs1_addr; wire [ 4 : 0] spec_insn_c_sd_rs2_addr; wire [ 4 : 0] spec_insn_c_sd_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sd_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sd_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sd_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sd_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sd_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sd_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sd_csr_misa_rmask; `endif rvfi_insn_c_sd insn_c_sd ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_sd_csr_misa_rmask), `endif .spec_valid(spec_insn_c_sd_valid), .spec_trap(spec_insn_c_sd_trap), .spec_rs1_addr(spec_insn_c_sd_rs1_addr), .spec_rs2_addr(spec_insn_c_sd_rs2_addr), .spec_rd_addr(spec_insn_c_sd_rd_addr), .spec_rd_wdata(spec_insn_c_sd_rd_wdata), .spec_pc_wdata(spec_insn_c_sd_pc_wdata), .spec_mem_addr(spec_insn_c_sd_mem_addr), .spec_mem_rmask(spec_insn_c_sd_mem_rmask), .spec_mem_wmask(spec_insn_c_sd_mem_wmask), .spec_mem_wdata(spec_insn_c_sd_mem_wdata) ); wire spec_insn_c_sdsp_valid; wire spec_insn_c_sdsp_trap; wire [ 4 : 0] spec_insn_c_sdsp_rs1_addr; wire [ 4 : 0] spec_insn_c_sdsp_rs2_addr; wire [ 4 : 0] spec_insn_c_sdsp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sdsp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sdsp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sdsp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sdsp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sdsp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sdsp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sdsp_csr_misa_rmask; `endif rvfi_insn_c_sdsp insn_c_sdsp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_sdsp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_sdsp_valid), .spec_trap(spec_insn_c_sdsp_trap), .spec_rs1_addr(spec_insn_c_sdsp_rs1_addr), .spec_rs2_addr(spec_insn_c_sdsp_rs2_addr), .spec_rd_addr(spec_insn_c_sdsp_rd_addr), .spec_rd_wdata(spec_insn_c_sdsp_rd_wdata), .spec_pc_wdata(spec_insn_c_sdsp_pc_wdata), .spec_mem_addr(spec_insn_c_sdsp_mem_addr), .spec_mem_rmask(spec_insn_c_sdsp_mem_rmask), .spec_mem_wmask(spec_insn_c_sdsp_mem_wmask), .spec_mem_wdata(spec_insn_c_sdsp_mem_wdata) ); wire spec_insn_c_slli_valid; wire spec_insn_c_slli_trap; wire [ 4 : 0] spec_insn_c_slli_rs1_addr; wire [ 4 : 0] spec_insn_c_slli_rs2_addr; wire [ 4 : 0] spec_insn_c_slli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_csr_misa_rmask; `endif rvfi_insn_c_slli insn_c_slli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_slli_csr_misa_rmask), `endif .spec_valid(spec_insn_c_slli_valid), .spec_trap(spec_insn_c_slli_trap), .spec_rs1_addr(spec_insn_c_slli_rs1_addr), .spec_rs2_addr(spec_insn_c_slli_rs2_addr), .spec_rd_addr(spec_insn_c_slli_rd_addr), .spec_rd_wdata(spec_insn_c_slli_rd_wdata), .spec_pc_wdata(spec_insn_c_slli_pc_wdata), .spec_mem_addr(spec_insn_c_slli_mem_addr), .spec_mem_rmask(spec_insn_c_slli_mem_rmask), .spec_mem_wmask(spec_insn_c_slli_mem_wmask), .spec_mem_wdata(spec_insn_c_slli_mem_wdata) ); wire spec_insn_c_srai_valid; wire spec_insn_c_srai_trap; wire [ 4 : 0] spec_insn_c_srai_rs1_addr; wire [ 4 : 0] spec_insn_c_srai_rs2_addr; wire [ 4 : 0] spec_insn_c_srai_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_csr_misa_rmask; `endif rvfi_insn_c_srai insn_c_srai ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_srai_csr_misa_rmask), `endif .spec_valid(spec_insn_c_srai_valid), .spec_trap(spec_insn_c_srai_trap), .spec_rs1_addr(spec_insn_c_srai_rs1_addr), .spec_rs2_addr(spec_insn_c_srai_rs2_addr), .spec_rd_addr(spec_insn_c_srai_rd_addr), .spec_rd_wdata(spec_insn_c_srai_rd_wdata), .spec_pc_wdata(spec_insn_c_srai_pc_wdata), .spec_mem_addr(spec_insn_c_srai_mem_addr), .spec_mem_rmask(spec_insn_c_srai_mem_rmask), .spec_mem_wmask(spec_insn_c_srai_mem_wmask), .spec_mem_wdata(spec_insn_c_srai_mem_wdata) ); wire spec_insn_c_srli_valid; wire spec_insn_c_srli_trap; wire [ 4 : 0] spec_insn_c_srli_rs1_addr; wire [ 4 : 0] spec_insn_c_srli_rs2_addr; wire [ 4 : 0] spec_insn_c_srli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_csr_misa_rmask; `endif rvfi_insn_c_srli insn_c_srli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_srli_csr_misa_rmask), `endif .spec_valid(spec_insn_c_srli_valid), .spec_trap(spec_insn_c_srli_trap), .spec_rs1_addr(spec_insn_c_srli_rs1_addr), .spec_rs2_addr(spec_insn_c_srli_rs2_addr), .spec_rd_addr(spec_insn_c_srli_rd_addr), .spec_rd_wdata(spec_insn_c_srli_rd_wdata), .spec_pc_wdata(spec_insn_c_srli_pc_wdata), .spec_mem_addr(spec_insn_c_srli_mem_addr), .spec_mem_rmask(spec_insn_c_srli_mem_rmask), .spec_mem_wmask(spec_insn_c_srli_mem_wmask), .spec_mem_wdata(spec_insn_c_srli_mem_wdata) ); wire spec_insn_c_sub_valid; wire spec_insn_c_sub_trap; wire [ 4 : 0] spec_insn_c_sub_rs1_addr; wire [ 4 : 0] spec_insn_c_sub_rs2_addr; wire [ 4 : 0] spec_insn_c_sub_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_csr_misa_rmask; `endif rvfi_insn_c_sub insn_c_sub ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_sub_csr_misa_rmask), `endif .spec_valid(spec_insn_c_sub_valid), .spec_trap(spec_insn_c_sub_trap), .spec_rs1_addr(spec_insn_c_sub_rs1_addr), .spec_rs2_addr(spec_insn_c_sub_rs2_addr), .spec_rd_addr(spec_insn_c_sub_rd_addr), .spec_rd_wdata(spec_insn_c_sub_rd_wdata), .spec_pc_wdata(spec_insn_c_sub_pc_wdata), .spec_mem_addr(spec_insn_c_sub_mem_addr), .spec_mem_rmask(spec_insn_c_sub_mem_rmask), .spec_mem_wmask(spec_insn_c_sub_mem_wmask), .spec_mem_wdata(spec_insn_c_sub_mem_wdata) ); wire spec_insn_c_subw_valid; wire spec_insn_c_subw_trap; wire [ 4 : 0] spec_insn_c_subw_rs1_addr; wire [ 4 : 0] spec_insn_c_subw_rs2_addr; wire [ 4 : 0] spec_insn_c_subw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_subw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_subw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_subw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_subw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_subw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_subw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_subw_csr_misa_rmask; `endif rvfi_insn_c_subw insn_c_subw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_subw_csr_misa_rmask), `endif .spec_valid(spec_insn_c_subw_valid), .spec_trap(spec_insn_c_subw_trap), .spec_rs1_addr(spec_insn_c_subw_rs1_addr), .spec_rs2_addr(spec_insn_c_subw_rs2_addr), .spec_rd_addr(spec_insn_c_subw_rd_addr), .spec_rd_wdata(spec_insn_c_subw_rd_wdata), .spec_pc_wdata(spec_insn_c_subw_pc_wdata), .spec_mem_addr(spec_insn_c_subw_mem_addr), .spec_mem_rmask(spec_insn_c_subw_mem_rmask), .spec_mem_wmask(spec_insn_c_subw_mem_wmask), .spec_mem_wdata(spec_insn_c_subw_mem_wdata) ); wire spec_insn_c_sw_valid; wire spec_insn_c_sw_trap; wire [ 4 : 0] spec_insn_c_sw_rs1_addr; wire [ 4 : 0] spec_insn_c_sw_rs2_addr; wire [ 4 : 0] spec_insn_c_sw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_csr_misa_rmask; `endif rvfi_insn_c_sw insn_c_sw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_sw_csr_misa_rmask), `endif .spec_valid(spec_insn_c_sw_valid), .spec_trap(spec_insn_c_sw_trap), .spec_rs1_addr(spec_insn_c_sw_rs1_addr), .spec_rs2_addr(spec_insn_c_sw_rs2_addr), .spec_rd_addr(spec_insn_c_sw_rd_addr), .spec_rd_wdata(spec_insn_c_sw_rd_wdata), .spec_pc_wdata(spec_insn_c_sw_pc_wdata), .spec_mem_addr(spec_insn_c_sw_mem_addr), .spec_mem_rmask(spec_insn_c_sw_mem_rmask), .spec_mem_wmask(spec_insn_c_sw_mem_wmask), .spec_mem_wdata(spec_insn_c_sw_mem_wdata) ); wire spec_insn_c_swsp_valid; wire spec_insn_c_swsp_trap; wire [ 4 : 0] spec_insn_c_swsp_rs1_addr; wire [ 4 : 0] spec_insn_c_swsp_rs2_addr; wire [ 4 : 0] spec_insn_c_swsp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_csr_misa_rmask; `endif rvfi_insn_c_swsp insn_c_swsp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_swsp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_swsp_valid), .spec_trap(spec_insn_c_swsp_trap), .spec_rs1_addr(spec_insn_c_swsp_rs1_addr), .spec_rs2_addr(spec_insn_c_swsp_rs2_addr), .spec_rd_addr(spec_insn_c_swsp_rd_addr), .spec_rd_wdata(spec_insn_c_swsp_rd_wdata), .spec_pc_wdata(spec_insn_c_swsp_pc_wdata), .spec_mem_addr(spec_insn_c_swsp_mem_addr), .spec_mem_rmask(spec_insn_c_swsp_mem_rmask), .spec_mem_wmask(spec_insn_c_swsp_mem_wmask), .spec_mem_wdata(spec_insn_c_swsp_mem_wdata) ); wire spec_insn_c_xor_valid; wire spec_insn_c_xor_trap; wire [ 4 : 0] spec_insn_c_xor_rs1_addr; wire [ 4 : 0] spec_insn_c_xor_rs2_addr; wire [ 4 : 0] spec_insn_c_xor_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_csr_misa_rmask; `endif rvfi_insn_c_xor insn_c_xor ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_xor_csr_misa_rmask), `endif .spec_valid(spec_insn_c_xor_valid), .spec_trap(spec_insn_c_xor_trap), .spec_rs1_addr(spec_insn_c_xor_rs1_addr), .spec_rs2_addr(spec_insn_c_xor_rs2_addr), .spec_rd_addr(spec_insn_c_xor_rd_addr), .spec_rd_wdata(spec_insn_c_xor_rd_wdata), .spec_pc_wdata(spec_insn_c_xor_pc_wdata), .spec_mem_addr(spec_insn_c_xor_mem_addr), .spec_mem_rmask(spec_insn_c_xor_mem_rmask), .spec_mem_wmask(spec_insn_c_xor_mem_wmask), .spec_mem_wdata(spec_insn_c_xor_mem_wdata) ); wire spec_insn_jal_valid; wire spec_insn_jal_trap; wire [ 4 : 0] spec_insn_jal_rs1_addr; wire [ 4 : 0] spec_insn_jal_rs2_addr; wire [ 4 : 0] spec_insn_jal_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; `endif rvfi_insn_jal insn_jal ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), `endif .spec_valid(spec_insn_jal_valid), .spec_trap(spec_insn_jal_trap), .spec_rs1_addr(spec_insn_jal_rs1_addr), .spec_rs2_addr(spec_insn_jal_rs2_addr), .spec_rd_addr(spec_insn_jal_rd_addr), .spec_rd_wdata(spec_insn_jal_rd_wdata), .spec_pc_wdata(spec_insn_jal_pc_wdata), .spec_mem_addr(spec_insn_jal_mem_addr), .spec_mem_rmask(spec_insn_jal_mem_rmask), .spec_mem_wmask(spec_insn_jal_mem_wmask), .spec_mem_wdata(spec_insn_jal_mem_wdata) ); wire spec_insn_jalr_valid; wire spec_insn_jalr_trap; wire [ 4 : 0] spec_insn_jalr_rs1_addr; wire [ 4 : 0] spec_insn_jalr_rs2_addr; wire [ 4 : 0] spec_insn_jalr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; `endif rvfi_insn_jalr insn_jalr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), `endif .spec_valid(spec_insn_jalr_valid), .spec_trap(spec_insn_jalr_trap), .spec_rs1_addr(spec_insn_jalr_rs1_addr), .spec_rs2_addr(spec_insn_jalr_rs2_addr), .spec_rd_addr(spec_insn_jalr_rd_addr), .spec_rd_wdata(spec_insn_jalr_rd_wdata), .spec_pc_wdata(spec_insn_jalr_pc_wdata), .spec_mem_addr(spec_insn_jalr_mem_addr), .spec_mem_rmask(spec_insn_jalr_mem_rmask), .spec_mem_wmask(spec_insn_jalr_mem_wmask), .spec_mem_wdata(spec_insn_jalr_mem_wdata) ); wire spec_insn_lb_valid; wire spec_insn_lb_trap; wire [ 4 : 0] spec_insn_lb_rs1_addr; wire [ 4 : 0] spec_insn_lb_rs2_addr; wire [ 4 : 0] spec_insn_lb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; `endif rvfi_insn_lb insn_lb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), `endif .spec_valid(spec_insn_lb_valid), .spec_trap(spec_insn_lb_trap), .spec_rs1_addr(spec_insn_lb_rs1_addr), .spec_rs2_addr(spec_insn_lb_rs2_addr), .spec_rd_addr(spec_insn_lb_rd_addr), .spec_rd_wdata(spec_insn_lb_rd_wdata), .spec_pc_wdata(spec_insn_lb_pc_wdata), .spec_mem_addr(spec_insn_lb_mem_addr), .spec_mem_rmask(spec_insn_lb_mem_rmask), .spec_mem_wmask(spec_insn_lb_mem_wmask), .spec_mem_wdata(spec_insn_lb_mem_wdata) ); wire spec_insn_lbu_valid; wire spec_insn_lbu_trap; wire [ 4 : 0] spec_insn_lbu_rs1_addr; wire [ 4 : 0] spec_insn_lbu_rs2_addr; wire [ 4 : 0] spec_insn_lbu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; `endif rvfi_insn_lbu insn_lbu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), `endif .spec_valid(spec_insn_lbu_valid), .spec_trap(spec_insn_lbu_trap), .spec_rs1_addr(spec_insn_lbu_rs1_addr), .spec_rs2_addr(spec_insn_lbu_rs2_addr), .spec_rd_addr(spec_insn_lbu_rd_addr), .spec_rd_wdata(spec_insn_lbu_rd_wdata), .spec_pc_wdata(spec_insn_lbu_pc_wdata), .spec_mem_addr(spec_insn_lbu_mem_addr), .spec_mem_rmask(spec_insn_lbu_mem_rmask), .spec_mem_wmask(spec_insn_lbu_mem_wmask), .spec_mem_wdata(spec_insn_lbu_mem_wdata) ); wire spec_insn_ld_valid; wire spec_insn_ld_trap; wire [ 4 : 0] spec_insn_ld_rs1_addr; wire [ 4 : 0] spec_insn_ld_rs2_addr; wire [ 4 : 0] spec_insn_ld_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_csr_misa_rmask; `endif rvfi_insn_ld insn_ld ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_ld_csr_misa_rmask), `endif .spec_valid(spec_insn_ld_valid), .spec_trap(spec_insn_ld_trap), .spec_rs1_addr(spec_insn_ld_rs1_addr), .spec_rs2_addr(spec_insn_ld_rs2_addr), .spec_rd_addr(spec_insn_ld_rd_addr), .spec_rd_wdata(spec_insn_ld_rd_wdata), .spec_pc_wdata(spec_insn_ld_pc_wdata), .spec_mem_addr(spec_insn_ld_mem_addr), .spec_mem_rmask(spec_insn_ld_mem_rmask), .spec_mem_wmask(spec_insn_ld_mem_wmask), .spec_mem_wdata(spec_insn_ld_mem_wdata) ); wire spec_insn_lh_valid; wire spec_insn_lh_trap; wire [ 4 : 0] spec_insn_lh_rs1_addr; wire [ 4 : 0] spec_insn_lh_rs2_addr; wire [ 4 : 0] spec_insn_lh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; `endif rvfi_insn_lh insn_lh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), `endif .spec_valid(spec_insn_lh_valid), .spec_trap(spec_insn_lh_trap), .spec_rs1_addr(spec_insn_lh_rs1_addr), .spec_rs2_addr(spec_insn_lh_rs2_addr), .spec_rd_addr(spec_insn_lh_rd_addr), .spec_rd_wdata(spec_insn_lh_rd_wdata), .spec_pc_wdata(spec_insn_lh_pc_wdata), .spec_mem_addr(spec_insn_lh_mem_addr), .spec_mem_rmask(spec_insn_lh_mem_rmask), .spec_mem_wmask(spec_insn_lh_mem_wmask), .spec_mem_wdata(spec_insn_lh_mem_wdata) ); wire spec_insn_lhu_valid; wire spec_insn_lhu_trap; wire [ 4 : 0] spec_insn_lhu_rs1_addr; wire [ 4 : 0] spec_insn_lhu_rs2_addr; wire [ 4 : 0] spec_insn_lhu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; `endif rvfi_insn_lhu insn_lhu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), `endif .spec_valid(spec_insn_lhu_valid), .spec_trap(spec_insn_lhu_trap), .spec_rs1_addr(spec_insn_lhu_rs1_addr), .spec_rs2_addr(spec_insn_lhu_rs2_addr), .spec_rd_addr(spec_insn_lhu_rd_addr), .spec_rd_wdata(spec_insn_lhu_rd_wdata), .spec_pc_wdata(spec_insn_lhu_pc_wdata), .spec_mem_addr(spec_insn_lhu_mem_addr), .spec_mem_rmask(spec_insn_lhu_mem_rmask), .spec_mem_wmask(spec_insn_lhu_mem_wmask), .spec_mem_wdata(spec_insn_lhu_mem_wdata) ); wire spec_insn_lui_valid; wire spec_insn_lui_trap; wire [ 4 : 0] spec_insn_lui_rs1_addr; wire [ 4 : 0] spec_insn_lui_rs2_addr; wire [ 4 : 0] spec_insn_lui_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; `endif rvfi_insn_lui insn_lui ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), `endif .spec_valid(spec_insn_lui_valid), .spec_trap(spec_insn_lui_trap), .spec_rs1_addr(spec_insn_lui_rs1_addr), .spec_rs2_addr(spec_insn_lui_rs2_addr), .spec_rd_addr(spec_insn_lui_rd_addr), .spec_rd_wdata(spec_insn_lui_rd_wdata), .spec_pc_wdata(spec_insn_lui_pc_wdata), .spec_mem_addr(spec_insn_lui_mem_addr), .spec_mem_rmask(spec_insn_lui_mem_rmask), .spec_mem_wmask(spec_insn_lui_mem_wmask), .spec_mem_wdata(spec_insn_lui_mem_wdata) ); wire spec_insn_lw_valid; wire spec_insn_lw_trap; wire [ 4 : 0] spec_insn_lw_rs1_addr; wire [ 4 : 0] spec_insn_lw_rs2_addr; wire [ 4 : 0] spec_insn_lw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; `endif rvfi_insn_lw insn_lw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), `endif .spec_valid(spec_insn_lw_valid), .spec_trap(spec_insn_lw_trap), .spec_rs1_addr(spec_insn_lw_rs1_addr), .spec_rs2_addr(spec_insn_lw_rs2_addr), .spec_rd_addr(spec_insn_lw_rd_addr), .spec_rd_wdata(spec_insn_lw_rd_wdata), .spec_pc_wdata(spec_insn_lw_pc_wdata), .spec_mem_addr(spec_insn_lw_mem_addr), .spec_mem_rmask(spec_insn_lw_mem_rmask), .spec_mem_wmask(spec_insn_lw_mem_wmask), .spec_mem_wdata(spec_insn_lw_mem_wdata) ); wire spec_insn_lwu_valid; wire spec_insn_lwu_trap; wire [ 4 : 0] spec_insn_lwu_rs1_addr; wire [ 4 : 0] spec_insn_lwu_rs2_addr; wire [ 4 : 0] spec_insn_lwu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_csr_misa_rmask; `endif rvfi_insn_lwu insn_lwu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lwu_csr_misa_rmask), `endif .spec_valid(spec_insn_lwu_valid), .spec_trap(spec_insn_lwu_trap), .spec_rs1_addr(spec_insn_lwu_rs1_addr), .spec_rs2_addr(spec_insn_lwu_rs2_addr), .spec_rd_addr(spec_insn_lwu_rd_addr), .spec_rd_wdata(spec_insn_lwu_rd_wdata), .spec_pc_wdata(spec_insn_lwu_pc_wdata), .spec_mem_addr(spec_insn_lwu_mem_addr), .spec_mem_rmask(spec_insn_lwu_mem_rmask), .spec_mem_wmask(spec_insn_lwu_mem_wmask), .spec_mem_wdata(spec_insn_lwu_mem_wdata) ); wire spec_insn_or_valid; wire spec_insn_or_trap; wire [ 4 : 0] spec_insn_or_rs1_addr; wire [ 4 : 0] spec_insn_or_rs2_addr; wire [ 4 : 0] spec_insn_or_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; `endif rvfi_insn_or insn_or ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), `endif .spec_valid(spec_insn_or_valid), .spec_trap(spec_insn_or_trap), .spec_rs1_addr(spec_insn_or_rs1_addr), .spec_rs2_addr(spec_insn_or_rs2_addr), .spec_rd_addr(spec_insn_or_rd_addr), .spec_rd_wdata(spec_insn_or_rd_wdata), .spec_pc_wdata(spec_insn_or_pc_wdata), .spec_mem_addr(spec_insn_or_mem_addr), .spec_mem_rmask(spec_insn_or_mem_rmask), .spec_mem_wmask(spec_insn_or_mem_wmask), .spec_mem_wdata(spec_insn_or_mem_wdata) ); wire spec_insn_ori_valid; wire spec_insn_ori_trap; wire [ 4 : 0] spec_insn_ori_rs1_addr; wire [ 4 : 0] spec_insn_ori_rs2_addr; wire [ 4 : 0] spec_insn_ori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; `endif rvfi_insn_ori insn_ori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), `endif .spec_valid(spec_insn_ori_valid), .spec_trap(spec_insn_ori_trap), .spec_rs1_addr(spec_insn_ori_rs1_addr), .spec_rs2_addr(spec_insn_ori_rs2_addr), .spec_rd_addr(spec_insn_ori_rd_addr), .spec_rd_wdata(spec_insn_ori_rd_wdata), .spec_pc_wdata(spec_insn_ori_pc_wdata), .spec_mem_addr(spec_insn_ori_mem_addr), .spec_mem_rmask(spec_insn_ori_mem_rmask), .spec_mem_wmask(spec_insn_ori_mem_wmask), .spec_mem_wdata(spec_insn_ori_mem_wdata) ); wire spec_insn_sb_valid; wire spec_insn_sb_trap; wire [ 4 : 0] spec_insn_sb_rs1_addr; wire [ 4 : 0] spec_insn_sb_rs2_addr; wire [ 4 : 0] spec_insn_sb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; `endif rvfi_insn_sb insn_sb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), `endif .spec_valid(spec_insn_sb_valid), .spec_trap(spec_insn_sb_trap), .spec_rs1_addr(spec_insn_sb_rs1_addr), .spec_rs2_addr(spec_insn_sb_rs2_addr), .spec_rd_addr(spec_insn_sb_rd_addr), .spec_rd_wdata(spec_insn_sb_rd_wdata), .spec_pc_wdata(spec_insn_sb_pc_wdata), .spec_mem_addr(spec_insn_sb_mem_addr), .spec_mem_rmask(spec_insn_sb_mem_rmask), .spec_mem_wmask(spec_insn_sb_mem_wmask), .spec_mem_wdata(spec_insn_sb_mem_wdata) ); wire spec_insn_sd_valid; wire spec_insn_sd_trap; wire [ 4 : 0] spec_insn_sd_rs1_addr; wire [ 4 : 0] spec_insn_sd_rs2_addr; wire [ 4 : 0] spec_insn_sd_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_csr_misa_rmask; `endif rvfi_insn_sd insn_sd ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sd_csr_misa_rmask), `endif .spec_valid(spec_insn_sd_valid), .spec_trap(spec_insn_sd_trap), .spec_rs1_addr(spec_insn_sd_rs1_addr), .spec_rs2_addr(spec_insn_sd_rs2_addr), .spec_rd_addr(spec_insn_sd_rd_addr), .spec_rd_wdata(spec_insn_sd_rd_wdata), .spec_pc_wdata(spec_insn_sd_pc_wdata), .spec_mem_addr(spec_insn_sd_mem_addr), .spec_mem_rmask(spec_insn_sd_mem_rmask), .spec_mem_wmask(spec_insn_sd_mem_wmask), .spec_mem_wdata(spec_insn_sd_mem_wdata) ); wire spec_insn_sh_valid; wire spec_insn_sh_trap; wire [ 4 : 0] spec_insn_sh_rs1_addr; wire [ 4 : 0] spec_insn_sh_rs2_addr; wire [ 4 : 0] spec_insn_sh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; `endif rvfi_insn_sh insn_sh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), `endif .spec_valid(spec_insn_sh_valid), .spec_trap(spec_insn_sh_trap), .spec_rs1_addr(spec_insn_sh_rs1_addr), .spec_rs2_addr(spec_insn_sh_rs2_addr), .spec_rd_addr(spec_insn_sh_rd_addr), .spec_rd_wdata(spec_insn_sh_rd_wdata), .spec_pc_wdata(spec_insn_sh_pc_wdata), .spec_mem_addr(spec_insn_sh_mem_addr), .spec_mem_rmask(spec_insn_sh_mem_rmask), .spec_mem_wmask(spec_insn_sh_mem_wmask), .spec_mem_wdata(spec_insn_sh_mem_wdata) ); wire spec_insn_sll_valid; wire spec_insn_sll_trap; wire [ 4 : 0] spec_insn_sll_rs1_addr; wire [ 4 : 0] spec_insn_sll_rs2_addr; wire [ 4 : 0] spec_insn_sll_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; `endif rvfi_insn_sll insn_sll ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), `endif .spec_valid(spec_insn_sll_valid), .spec_trap(spec_insn_sll_trap), .spec_rs1_addr(spec_insn_sll_rs1_addr), .spec_rs2_addr(spec_insn_sll_rs2_addr), .spec_rd_addr(spec_insn_sll_rd_addr), .spec_rd_wdata(spec_insn_sll_rd_wdata), .spec_pc_wdata(spec_insn_sll_pc_wdata), .spec_mem_addr(spec_insn_sll_mem_addr), .spec_mem_rmask(spec_insn_sll_mem_rmask), .spec_mem_wmask(spec_insn_sll_mem_wmask), .spec_mem_wdata(spec_insn_sll_mem_wdata) ); wire spec_insn_slli_valid; wire spec_insn_slli_trap; wire [ 4 : 0] spec_insn_slli_rs1_addr; wire [ 4 : 0] spec_insn_slli_rs2_addr; wire [ 4 : 0] spec_insn_slli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; `endif rvfi_insn_slli insn_slli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), `endif .spec_valid(spec_insn_slli_valid), .spec_trap(spec_insn_slli_trap), .spec_rs1_addr(spec_insn_slli_rs1_addr), .spec_rs2_addr(spec_insn_slli_rs2_addr), .spec_rd_addr(spec_insn_slli_rd_addr), .spec_rd_wdata(spec_insn_slli_rd_wdata), .spec_pc_wdata(spec_insn_slli_pc_wdata), .spec_mem_addr(spec_insn_slli_mem_addr), .spec_mem_rmask(spec_insn_slli_mem_rmask), .spec_mem_wmask(spec_insn_slli_mem_wmask), .spec_mem_wdata(spec_insn_slli_mem_wdata) ); wire spec_insn_slliw_valid; wire spec_insn_slliw_trap; wire [ 4 : 0] spec_insn_slliw_rs1_addr; wire [ 4 : 0] spec_insn_slliw_rs2_addr; wire [ 4 : 0] spec_insn_slliw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_csr_misa_rmask; `endif rvfi_insn_slliw insn_slliw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slliw_csr_misa_rmask), `endif .spec_valid(spec_insn_slliw_valid), .spec_trap(spec_insn_slliw_trap), .spec_rs1_addr(spec_insn_slliw_rs1_addr), .spec_rs2_addr(spec_insn_slliw_rs2_addr), .spec_rd_addr(spec_insn_slliw_rd_addr), .spec_rd_wdata(spec_insn_slliw_rd_wdata), .spec_pc_wdata(spec_insn_slliw_pc_wdata), .spec_mem_addr(spec_insn_slliw_mem_addr), .spec_mem_rmask(spec_insn_slliw_mem_rmask), .spec_mem_wmask(spec_insn_slliw_mem_wmask), .spec_mem_wdata(spec_insn_slliw_mem_wdata) ); wire spec_insn_sllw_valid; wire spec_insn_sllw_trap; wire [ 4 : 0] spec_insn_sllw_rs1_addr; wire [ 4 : 0] spec_insn_sllw_rs2_addr; wire [ 4 : 0] spec_insn_sllw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_csr_misa_rmask; `endif rvfi_insn_sllw insn_sllw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sllw_csr_misa_rmask), `endif .spec_valid(spec_insn_sllw_valid), .spec_trap(spec_insn_sllw_trap), .spec_rs1_addr(spec_insn_sllw_rs1_addr), .spec_rs2_addr(spec_insn_sllw_rs2_addr), .spec_rd_addr(spec_insn_sllw_rd_addr), .spec_rd_wdata(spec_insn_sllw_rd_wdata), .spec_pc_wdata(spec_insn_sllw_pc_wdata), .spec_mem_addr(spec_insn_sllw_mem_addr), .spec_mem_rmask(spec_insn_sllw_mem_rmask), .spec_mem_wmask(spec_insn_sllw_mem_wmask), .spec_mem_wdata(spec_insn_sllw_mem_wdata) ); wire spec_insn_slt_valid; wire spec_insn_slt_trap; wire [ 4 : 0] spec_insn_slt_rs1_addr; wire [ 4 : 0] spec_insn_slt_rs2_addr; wire [ 4 : 0] spec_insn_slt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; `endif rvfi_insn_slt insn_slt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), `endif .spec_valid(spec_insn_slt_valid), .spec_trap(spec_insn_slt_trap), .spec_rs1_addr(spec_insn_slt_rs1_addr), .spec_rs2_addr(spec_insn_slt_rs2_addr), .spec_rd_addr(spec_insn_slt_rd_addr), .spec_rd_wdata(spec_insn_slt_rd_wdata), .spec_pc_wdata(spec_insn_slt_pc_wdata), .spec_mem_addr(spec_insn_slt_mem_addr), .spec_mem_rmask(spec_insn_slt_mem_rmask), .spec_mem_wmask(spec_insn_slt_mem_wmask), .spec_mem_wdata(spec_insn_slt_mem_wdata) ); wire spec_insn_slti_valid; wire spec_insn_slti_trap; wire [ 4 : 0] spec_insn_slti_rs1_addr; wire [ 4 : 0] spec_insn_slti_rs2_addr; wire [ 4 : 0] spec_insn_slti_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; `endif rvfi_insn_slti insn_slti ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), `endif .spec_valid(spec_insn_slti_valid), .spec_trap(spec_insn_slti_trap), .spec_rs1_addr(spec_insn_slti_rs1_addr), .spec_rs2_addr(spec_insn_slti_rs2_addr), .spec_rd_addr(spec_insn_slti_rd_addr), .spec_rd_wdata(spec_insn_slti_rd_wdata), .spec_pc_wdata(spec_insn_slti_pc_wdata), .spec_mem_addr(spec_insn_slti_mem_addr), .spec_mem_rmask(spec_insn_slti_mem_rmask), .spec_mem_wmask(spec_insn_slti_mem_wmask), .spec_mem_wdata(spec_insn_slti_mem_wdata) ); wire spec_insn_sltiu_valid; wire spec_insn_sltiu_trap; wire [ 4 : 0] spec_insn_sltiu_rs1_addr; wire [ 4 : 0] spec_insn_sltiu_rs2_addr; wire [ 4 : 0] spec_insn_sltiu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; `endif rvfi_insn_sltiu insn_sltiu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltiu_valid), .spec_trap(spec_insn_sltiu_trap), .spec_rs1_addr(spec_insn_sltiu_rs1_addr), .spec_rs2_addr(spec_insn_sltiu_rs2_addr), .spec_rd_addr(spec_insn_sltiu_rd_addr), .spec_rd_wdata(spec_insn_sltiu_rd_wdata), .spec_pc_wdata(spec_insn_sltiu_pc_wdata), .spec_mem_addr(spec_insn_sltiu_mem_addr), .spec_mem_rmask(spec_insn_sltiu_mem_rmask), .spec_mem_wmask(spec_insn_sltiu_mem_wmask), .spec_mem_wdata(spec_insn_sltiu_mem_wdata) ); wire spec_insn_sltu_valid; wire spec_insn_sltu_trap; wire [ 4 : 0] spec_insn_sltu_rs1_addr; wire [ 4 : 0] spec_insn_sltu_rs2_addr; wire [ 4 : 0] spec_insn_sltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; `endif rvfi_insn_sltu insn_sltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltu_valid), .spec_trap(spec_insn_sltu_trap), .spec_rs1_addr(spec_insn_sltu_rs1_addr), .spec_rs2_addr(spec_insn_sltu_rs2_addr), .spec_rd_addr(spec_insn_sltu_rd_addr), .spec_rd_wdata(spec_insn_sltu_rd_wdata), .spec_pc_wdata(spec_insn_sltu_pc_wdata), .spec_mem_addr(spec_insn_sltu_mem_addr), .spec_mem_rmask(spec_insn_sltu_mem_rmask), .spec_mem_wmask(spec_insn_sltu_mem_wmask), .spec_mem_wdata(spec_insn_sltu_mem_wdata) ); wire spec_insn_sra_valid; wire spec_insn_sra_trap; wire [ 4 : 0] spec_insn_sra_rs1_addr; wire [ 4 : 0] spec_insn_sra_rs2_addr; wire [ 4 : 0] spec_insn_sra_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; `endif rvfi_insn_sra insn_sra ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), `endif .spec_valid(spec_insn_sra_valid), .spec_trap(spec_insn_sra_trap), .spec_rs1_addr(spec_insn_sra_rs1_addr), .spec_rs2_addr(spec_insn_sra_rs2_addr), .spec_rd_addr(spec_insn_sra_rd_addr), .spec_rd_wdata(spec_insn_sra_rd_wdata), .spec_pc_wdata(spec_insn_sra_pc_wdata), .spec_mem_addr(spec_insn_sra_mem_addr), .spec_mem_rmask(spec_insn_sra_mem_rmask), .spec_mem_wmask(spec_insn_sra_mem_wmask), .spec_mem_wdata(spec_insn_sra_mem_wdata) ); wire spec_insn_srai_valid; wire spec_insn_srai_trap; wire [ 4 : 0] spec_insn_srai_rs1_addr; wire [ 4 : 0] spec_insn_srai_rs2_addr; wire [ 4 : 0] spec_insn_srai_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; `endif rvfi_insn_srai insn_srai ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), `endif .spec_valid(spec_insn_srai_valid), .spec_trap(spec_insn_srai_trap), .spec_rs1_addr(spec_insn_srai_rs1_addr), .spec_rs2_addr(spec_insn_srai_rs2_addr), .spec_rd_addr(spec_insn_srai_rd_addr), .spec_rd_wdata(spec_insn_srai_rd_wdata), .spec_pc_wdata(spec_insn_srai_pc_wdata), .spec_mem_addr(spec_insn_srai_mem_addr), .spec_mem_rmask(spec_insn_srai_mem_rmask), .spec_mem_wmask(spec_insn_srai_mem_wmask), .spec_mem_wdata(spec_insn_srai_mem_wdata) ); wire spec_insn_sraiw_valid; wire spec_insn_sraiw_trap; wire [ 4 : 0] spec_insn_sraiw_rs1_addr; wire [ 4 : 0] spec_insn_sraiw_rs2_addr; wire [ 4 : 0] spec_insn_sraiw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_csr_misa_rmask; `endif rvfi_insn_sraiw insn_sraiw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sraiw_csr_misa_rmask), `endif .spec_valid(spec_insn_sraiw_valid), .spec_trap(spec_insn_sraiw_trap), .spec_rs1_addr(spec_insn_sraiw_rs1_addr), .spec_rs2_addr(spec_insn_sraiw_rs2_addr), .spec_rd_addr(spec_insn_sraiw_rd_addr), .spec_rd_wdata(spec_insn_sraiw_rd_wdata), .spec_pc_wdata(spec_insn_sraiw_pc_wdata), .spec_mem_addr(spec_insn_sraiw_mem_addr), .spec_mem_rmask(spec_insn_sraiw_mem_rmask), .spec_mem_wmask(spec_insn_sraiw_mem_wmask), .spec_mem_wdata(spec_insn_sraiw_mem_wdata) ); wire spec_insn_sraw_valid; wire spec_insn_sraw_trap; wire [ 4 : 0] spec_insn_sraw_rs1_addr; wire [ 4 : 0] spec_insn_sraw_rs2_addr; wire [ 4 : 0] spec_insn_sraw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_csr_misa_rmask; `endif rvfi_insn_sraw insn_sraw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sraw_csr_misa_rmask), `endif .spec_valid(spec_insn_sraw_valid), .spec_trap(spec_insn_sraw_trap), .spec_rs1_addr(spec_insn_sraw_rs1_addr), .spec_rs2_addr(spec_insn_sraw_rs2_addr), .spec_rd_addr(spec_insn_sraw_rd_addr), .spec_rd_wdata(spec_insn_sraw_rd_wdata), .spec_pc_wdata(spec_insn_sraw_pc_wdata), .spec_mem_addr(spec_insn_sraw_mem_addr), .spec_mem_rmask(spec_insn_sraw_mem_rmask), .spec_mem_wmask(spec_insn_sraw_mem_wmask), .spec_mem_wdata(spec_insn_sraw_mem_wdata) ); wire spec_insn_srl_valid; wire spec_insn_srl_trap; wire [ 4 : 0] spec_insn_srl_rs1_addr; wire [ 4 : 0] spec_insn_srl_rs2_addr; wire [ 4 : 0] spec_insn_srl_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; `endif rvfi_insn_srl insn_srl ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), `endif .spec_valid(spec_insn_srl_valid), .spec_trap(spec_insn_srl_trap), .spec_rs1_addr(spec_insn_srl_rs1_addr), .spec_rs2_addr(spec_insn_srl_rs2_addr), .spec_rd_addr(spec_insn_srl_rd_addr), .spec_rd_wdata(spec_insn_srl_rd_wdata), .spec_pc_wdata(spec_insn_srl_pc_wdata), .spec_mem_addr(spec_insn_srl_mem_addr), .spec_mem_rmask(spec_insn_srl_mem_rmask), .spec_mem_wmask(spec_insn_srl_mem_wmask), .spec_mem_wdata(spec_insn_srl_mem_wdata) ); wire spec_insn_srli_valid; wire spec_insn_srli_trap; wire [ 4 : 0] spec_insn_srli_rs1_addr; wire [ 4 : 0] spec_insn_srli_rs2_addr; wire [ 4 : 0] spec_insn_srli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; `endif rvfi_insn_srli insn_srli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), `endif .spec_valid(spec_insn_srli_valid), .spec_trap(spec_insn_srli_trap), .spec_rs1_addr(spec_insn_srli_rs1_addr), .spec_rs2_addr(spec_insn_srli_rs2_addr), .spec_rd_addr(spec_insn_srli_rd_addr), .spec_rd_wdata(spec_insn_srli_rd_wdata), .spec_pc_wdata(spec_insn_srli_pc_wdata), .spec_mem_addr(spec_insn_srli_mem_addr), .spec_mem_rmask(spec_insn_srli_mem_rmask), .spec_mem_wmask(spec_insn_srli_mem_wmask), .spec_mem_wdata(spec_insn_srli_mem_wdata) ); wire spec_insn_srliw_valid; wire spec_insn_srliw_trap; wire [ 4 : 0] spec_insn_srliw_rs1_addr; wire [ 4 : 0] spec_insn_srliw_rs2_addr; wire [ 4 : 0] spec_insn_srliw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_csr_misa_rmask; `endif rvfi_insn_srliw insn_srliw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srliw_csr_misa_rmask), `endif .spec_valid(spec_insn_srliw_valid), .spec_trap(spec_insn_srliw_trap), .spec_rs1_addr(spec_insn_srliw_rs1_addr), .spec_rs2_addr(spec_insn_srliw_rs2_addr), .spec_rd_addr(spec_insn_srliw_rd_addr), .spec_rd_wdata(spec_insn_srliw_rd_wdata), .spec_pc_wdata(spec_insn_srliw_pc_wdata), .spec_mem_addr(spec_insn_srliw_mem_addr), .spec_mem_rmask(spec_insn_srliw_mem_rmask), .spec_mem_wmask(spec_insn_srliw_mem_wmask), .spec_mem_wdata(spec_insn_srliw_mem_wdata) ); wire spec_insn_srlw_valid; wire spec_insn_srlw_trap; wire [ 4 : 0] spec_insn_srlw_rs1_addr; wire [ 4 : 0] spec_insn_srlw_rs2_addr; wire [ 4 : 0] spec_insn_srlw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_csr_misa_rmask; `endif rvfi_insn_srlw insn_srlw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srlw_csr_misa_rmask), `endif .spec_valid(spec_insn_srlw_valid), .spec_trap(spec_insn_srlw_trap), .spec_rs1_addr(spec_insn_srlw_rs1_addr), .spec_rs2_addr(spec_insn_srlw_rs2_addr), .spec_rd_addr(spec_insn_srlw_rd_addr), .spec_rd_wdata(spec_insn_srlw_rd_wdata), .spec_pc_wdata(spec_insn_srlw_pc_wdata), .spec_mem_addr(spec_insn_srlw_mem_addr), .spec_mem_rmask(spec_insn_srlw_mem_rmask), .spec_mem_wmask(spec_insn_srlw_mem_wmask), .spec_mem_wdata(spec_insn_srlw_mem_wdata) ); wire spec_insn_sub_valid; wire spec_insn_sub_trap; wire [ 4 : 0] spec_insn_sub_rs1_addr; wire [ 4 : 0] spec_insn_sub_rs2_addr; wire [ 4 : 0] spec_insn_sub_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; `endif rvfi_insn_sub insn_sub ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), `endif .spec_valid(spec_insn_sub_valid), .spec_trap(spec_insn_sub_trap), .spec_rs1_addr(spec_insn_sub_rs1_addr), .spec_rs2_addr(spec_insn_sub_rs2_addr), .spec_rd_addr(spec_insn_sub_rd_addr), .spec_rd_wdata(spec_insn_sub_rd_wdata), .spec_pc_wdata(spec_insn_sub_pc_wdata), .spec_mem_addr(spec_insn_sub_mem_addr), .spec_mem_rmask(spec_insn_sub_mem_rmask), .spec_mem_wmask(spec_insn_sub_mem_wmask), .spec_mem_wdata(spec_insn_sub_mem_wdata) ); wire spec_insn_subw_valid; wire spec_insn_subw_trap; wire [ 4 : 0] spec_insn_subw_rs1_addr; wire [ 4 : 0] spec_insn_subw_rs2_addr; wire [ 4 : 0] spec_insn_subw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_csr_misa_rmask; `endif rvfi_insn_subw insn_subw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_subw_csr_misa_rmask), `endif .spec_valid(spec_insn_subw_valid), .spec_trap(spec_insn_subw_trap), .spec_rs1_addr(spec_insn_subw_rs1_addr), .spec_rs2_addr(spec_insn_subw_rs2_addr), .spec_rd_addr(spec_insn_subw_rd_addr), .spec_rd_wdata(spec_insn_subw_rd_wdata), .spec_pc_wdata(spec_insn_subw_pc_wdata), .spec_mem_addr(spec_insn_subw_mem_addr), .spec_mem_rmask(spec_insn_subw_mem_rmask), .spec_mem_wmask(spec_insn_subw_mem_wmask), .spec_mem_wdata(spec_insn_subw_mem_wdata) ); wire spec_insn_sw_valid; wire spec_insn_sw_trap; wire [ 4 : 0] spec_insn_sw_rs1_addr; wire [ 4 : 0] spec_insn_sw_rs2_addr; wire [ 4 : 0] spec_insn_sw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; `endif rvfi_insn_sw insn_sw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), `endif .spec_valid(spec_insn_sw_valid), .spec_trap(spec_insn_sw_trap), .spec_rs1_addr(spec_insn_sw_rs1_addr), .spec_rs2_addr(spec_insn_sw_rs2_addr), .spec_rd_addr(spec_insn_sw_rd_addr), .spec_rd_wdata(spec_insn_sw_rd_wdata), .spec_pc_wdata(spec_insn_sw_pc_wdata), .spec_mem_addr(spec_insn_sw_mem_addr), .spec_mem_rmask(spec_insn_sw_mem_rmask), .spec_mem_wmask(spec_insn_sw_mem_wmask), .spec_mem_wdata(spec_insn_sw_mem_wdata) ); wire spec_insn_xor_valid; wire spec_insn_xor_trap; wire [ 4 : 0] spec_insn_xor_rs1_addr; wire [ 4 : 0] spec_insn_xor_rs2_addr; wire [ 4 : 0] spec_insn_xor_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; `endif rvfi_insn_xor insn_xor ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), `endif .spec_valid(spec_insn_xor_valid), .spec_trap(spec_insn_xor_trap), .spec_rs1_addr(spec_insn_xor_rs1_addr), .spec_rs2_addr(spec_insn_xor_rs2_addr), .spec_rd_addr(spec_insn_xor_rd_addr), .spec_rd_wdata(spec_insn_xor_rd_wdata), .spec_pc_wdata(spec_insn_xor_pc_wdata), .spec_mem_addr(spec_insn_xor_mem_addr), .spec_mem_rmask(spec_insn_xor_mem_rmask), .spec_mem_wmask(spec_insn_xor_mem_wmask), .spec_mem_wdata(spec_insn_xor_mem_wdata) ); wire spec_insn_xori_valid; wire spec_insn_xori_trap; wire [ 4 : 0] spec_insn_xori_rs1_addr; wire [ 4 : 0] spec_insn_xori_rs2_addr; wire [ 4 : 0] spec_insn_xori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; `endif rvfi_insn_xori insn_xori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), `endif .spec_valid(spec_insn_xori_valid), .spec_trap(spec_insn_xori_trap), .spec_rs1_addr(spec_insn_xori_rs1_addr), .spec_rs2_addr(spec_insn_xori_rs2_addr), .spec_rd_addr(spec_insn_xori_rd_addr), .spec_rd_wdata(spec_insn_xori_rd_wdata), .spec_pc_wdata(spec_insn_xori_pc_wdata), .spec_mem_addr(spec_insn_xori_mem_addr), .spec_mem_rmask(spec_insn_xori_mem_rmask), .spec_mem_wmask(spec_insn_xori_mem_wmask), .spec_mem_wdata(spec_insn_xori_mem_wdata) ); assign spec_valid = spec_insn_add_valid ? spec_insn_add_valid : spec_insn_addi_valid ? spec_insn_addi_valid : spec_insn_addiw_valid ? spec_insn_addiw_valid : spec_insn_addw_valid ? spec_insn_addw_valid : spec_insn_and_valid ? spec_insn_and_valid : spec_insn_andi_valid ? spec_insn_andi_valid : spec_insn_auipc_valid ? spec_insn_auipc_valid : spec_insn_beq_valid ? spec_insn_beq_valid : spec_insn_bge_valid ? spec_insn_bge_valid : spec_insn_bgeu_valid ? spec_insn_bgeu_valid : spec_insn_blt_valid ? spec_insn_blt_valid : spec_insn_bltu_valid ? spec_insn_bltu_valid : spec_insn_bne_valid ? spec_insn_bne_valid : spec_insn_c_add_valid ? spec_insn_c_add_valid : spec_insn_c_addi_valid ? spec_insn_c_addi_valid : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_valid : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_valid : spec_insn_c_addiw_valid ? spec_insn_c_addiw_valid : spec_insn_c_addw_valid ? spec_insn_c_addw_valid : spec_insn_c_and_valid ? spec_insn_c_and_valid : spec_insn_c_andi_valid ? spec_insn_c_andi_valid : spec_insn_c_beqz_valid ? spec_insn_c_beqz_valid : spec_insn_c_bnez_valid ? spec_insn_c_bnez_valid : spec_insn_c_j_valid ? spec_insn_c_j_valid : spec_insn_c_jalr_valid ? spec_insn_c_jalr_valid : spec_insn_c_jr_valid ? spec_insn_c_jr_valid : spec_insn_c_ld_valid ? spec_insn_c_ld_valid : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_valid : spec_insn_c_li_valid ? spec_insn_c_li_valid : spec_insn_c_lui_valid ? spec_insn_c_lui_valid : spec_insn_c_lw_valid ? spec_insn_c_lw_valid : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_valid : spec_insn_c_mv_valid ? spec_insn_c_mv_valid : spec_insn_c_or_valid ? spec_insn_c_or_valid : spec_insn_c_sd_valid ? spec_insn_c_sd_valid : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_valid : spec_insn_c_slli_valid ? spec_insn_c_slli_valid : spec_insn_c_srai_valid ? spec_insn_c_srai_valid : spec_insn_c_srli_valid ? spec_insn_c_srli_valid : spec_insn_c_sub_valid ? spec_insn_c_sub_valid : spec_insn_c_subw_valid ? spec_insn_c_subw_valid : spec_insn_c_sw_valid ? spec_insn_c_sw_valid : spec_insn_c_swsp_valid ? spec_insn_c_swsp_valid : spec_insn_c_xor_valid ? spec_insn_c_xor_valid : spec_insn_jal_valid ? spec_insn_jal_valid : spec_insn_jalr_valid ? spec_insn_jalr_valid : spec_insn_lb_valid ? spec_insn_lb_valid : spec_insn_lbu_valid ? spec_insn_lbu_valid : spec_insn_ld_valid ? spec_insn_ld_valid : spec_insn_lh_valid ? spec_insn_lh_valid : spec_insn_lhu_valid ? spec_insn_lhu_valid : spec_insn_lui_valid ? spec_insn_lui_valid : spec_insn_lw_valid ? spec_insn_lw_valid : spec_insn_lwu_valid ? spec_insn_lwu_valid : spec_insn_or_valid ? spec_insn_or_valid : spec_insn_ori_valid ? spec_insn_ori_valid : spec_insn_sb_valid ? spec_insn_sb_valid : spec_insn_sd_valid ? spec_insn_sd_valid : spec_insn_sh_valid ? spec_insn_sh_valid : spec_insn_sll_valid ? spec_insn_sll_valid : spec_insn_slli_valid ? spec_insn_slli_valid : spec_insn_slliw_valid ? spec_insn_slliw_valid : spec_insn_sllw_valid ? spec_insn_sllw_valid : spec_insn_slt_valid ? spec_insn_slt_valid : spec_insn_slti_valid ? spec_insn_slti_valid : spec_insn_sltiu_valid ? spec_insn_sltiu_valid : spec_insn_sltu_valid ? spec_insn_sltu_valid : spec_insn_sra_valid ? spec_insn_sra_valid : spec_insn_srai_valid ? spec_insn_srai_valid : spec_insn_sraiw_valid ? spec_insn_sraiw_valid : spec_insn_sraw_valid ? spec_insn_sraw_valid : spec_insn_srl_valid ? spec_insn_srl_valid : spec_insn_srli_valid ? spec_insn_srli_valid : spec_insn_srliw_valid ? spec_insn_srliw_valid : spec_insn_srlw_valid ? spec_insn_srlw_valid : spec_insn_sub_valid ? spec_insn_sub_valid : spec_insn_subw_valid ? spec_insn_subw_valid : spec_insn_sw_valid ? spec_insn_sw_valid : spec_insn_xor_valid ? spec_insn_xor_valid : spec_insn_xori_valid ? spec_insn_xori_valid : 0; assign spec_trap = spec_insn_add_valid ? spec_insn_add_trap : spec_insn_addi_valid ? spec_insn_addi_trap : spec_insn_addiw_valid ? spec_insn_addiw_trap : spec_insn_addw_valid ? spec_insn_addw_trap : spec_insn_and_valid ? spec_insn_and_trap : spec_insn_andi_valid ? spec_insn_andi_trap : spec_insn_auipc_valid ? spec_insn_auipc_trap : spec_insn_beq_valid ? spec_insn_beq_trap : spec_insn_bge_valid ? spec_insn_bge_trap : spec_insn_bgeu_valid ? spec_insn_bgeu_trap : spec_insn_blt_valid ? spec_insn_blt_trap : spec_insn_bltu_valid ? spec_insn_bltu_trap : spec_insn_bne_valid ? spec_insn_bne_trap : spec_insn_c_add_valid ? spec_insn_c_add_trap : spec_insn_c_addi_valid ? spec_insn_c_addi_trap : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_trap : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_trap : spec_insn_c_addiw_valid ? spec_insn_c_addiw_trap : spec_insn_c_addw_valid ? spec_insn_c_addw_trap : spec_insn_c_and_valid ? spec_insn_c_and_trap : spec_insn_c_andi_valid ? spec_insn_c_andi_trap : spec_insn_c_beqz_valid ? spec_insn_c_beqz_trap : spec_insn_c_bnez_valid ? spec_insn_c_bnez_trap : spec_insn_c_j_valid ? spec_insn_c_j_trap : spec_insn_c_jalr_valid ? spec_insn_c_jalr_trap : spec_insn_c_jr_valid ? spec_insn_c_jr_trap : spec_insn_c_ld_valid ? spec_insn_c_ld_trap : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_trap : spec_insn_c_li_valid ? spec_insn_c_li_trap : spec_insn_c_lui_valid ? spec_insn_c_lui_trap : spec_insn_c_lw_valid ? spec_insn_c_lw_trap : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_trap : spec_insn_c_mv_valid ? spec_insn_c_mv_trap : spec_insn_c_or_valid ? spec_insn_c_or_trap : spec_insn_c_sd_valid ? spec_insn_c_sd_trap : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_trap : spec_insn_c_slli_valid ? spec_insn_c_slli_trap : spec_insn_c_srai_valid ? spec_insn_c_srai_trap : spec_insn_c_srli_valid ? spec_insn_c_srli_trap : spec_insn_c_sub_valid ? spec_insn_c_sub_trap : spec_insn_c_subw_valid ? spec_insn_c_subw_trap : spec_insn_c_sw_valid ? spec_insn_c_sw_trap : spec_insn_c_swsp_valid ? spec_insn_c_swsp_trap : spec_insn_c_xor_valid ? spec_insn_c_xor_trap : spec_insn_jal_valid ? spec_insn_jal_trap : spec_insn_jalr_valid ? spec_insn_jalr_trap : spec_insn_lb_valid ? spec_insn_lb_trap : spec_insn_lbu_valid ? spec_insn_lbu_trap : spec_insn_ld_valid ? spec_insn_ld_trap : spec_insn_lh_valid ? spec_insn_lh_trap : spec_insn_lhu_valid ? spec_insn_lhu_trap : spec_insn_lui_valid ? spec_insn_lui_trap : spec_insn_lw_valid ? spec_insn_lw_trap : spec_insn_lwu_valid ? spec_insn_lwu_trap : spec_insn_or_valid ? spec_insn_or_trap : spec_insn_ori_valid ? spec_insn_ori_trap : spec_insn_sb_valid ? spec_insn_sb_trap : spec_insn_sd_valid ? spec_insn_sd_trap : spec_insn_sh_valid ? spec_insn_sh_trap : spec_insn_sll_valid ? spec_insn_sll_trap : spec_insn_slli_valid ? spec_insn_slli_trap : spec_insn_slliw_valid ? spec_insn_slliw_trap : spec_insn_sllw_valid ? spec_insn_sllw_trap : spec_insn_slt_valid ? spec_insn_slt_trap : spec_insn_slti_valid ? spec_insn_slti_trap : spec_insn_sltiu_valid ? spec_insn_sltiu_trap : spec_insn_sltu_valid ? spec_insn_sltu_trap : spec_insn_sra_valid ? spec_insn_sra_trap : spec_insn_srai_valid ? spec_insn_srai_trap : spec_insn_sraiw_valid ? spec_insn_sraiw_trap : spec_insn_sraw_valid ? spec_insn_sraw_trap : spec_insn_srl_valid ? spec_insn_srl_trap : spec_insn_srli_valid ? spec_insn_srli_trap : spec_insn_srliw_valid ? spec_insn_srliw_trap : spec_insn_srlw_valid ? spec_insn_srlw_trap : spec_insn_sub_valid ? spec_insn_sub_trap : spec_insn_subw_valid ? spec_insn_subw_trap : spec_insn_sw_valid ? spec_insn_sw_trap : spec_insn_xor_valid ? spec_insn_xor_trap : spec_insn_xori_valid ? spec_insn_xori_trap : 0; assign spec_rs1_addr = spec_insn_add_valid ? spec_insn_add_rs1_addr : spec_insn_addi_valid ? spec_insn_addi_rs1_addr : spec_insn_addiw_valid ? spec_insn_addiw_rs1_addr : spec_insn_addw_valid ? spec_insn_addw_rs1_addr : spec_insn_and_valid ? spec_insn_and_rs1_addr : spec_insn_andi_valid ? spec_insn_andi_rs1_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : spec_insn_beq_valid ? spec_insn_beq_rs1_addr : spec_insn_bge_valid ? spec_insn_bge_rs1_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : spec_insn_blt_valid ? spec_insn_blt_rs1_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : spec_insn_bne_valid ? spec_insn_bne_rs1_addr : spec_insn_c_add_valid ? spec_insn_c_add_rs1_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_rs1_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs1_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs1_addr : spec_insn_c_addiw_valid ? spec_insn_c_addiw_rs1_addr : spec_insn_c_addw_valid ? spec_insn_c_addw_rs1_addr : spec_insn_c_and_valid ? spec_insn_c_and_rs1_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_rs1_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rs1_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rs1_addr : spec_insn_c_j_valid ? spec_insn_c_j_rs1_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rs1_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_rs1_addr : spec_insn_c_ld_valid ? spec_insn_c_ld_rs1_addr : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rs1_addr : spec_insn_c_li_valid ? spec_insn_c_li_rs1_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_rs1_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_rs1_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs1_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_rs1_addr : spec_insn_c_or_valid ? spec_insn_c_or_rs1_addr : spec_insn_c_sd_valid ? spec_insn_c_sd_rs1_addr : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rs1_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_rs1_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_rs1_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_rs1_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_rs1_addr : spec_insn_c_subw_valid ? spec_insn_c_subw_rs1_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_rs1_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rs1_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_rs1_addr : spec_insn_jal_valid ? spec_insn_jal_rs1_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : spec_insn_lb_valid ? spec_insn_lb_rs1_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : spec_insn_ld_valid ? spec_insn_ld_rs1_addr : spec_insn_lh_valid ? spec_insn_lh_rs1_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : spec_insn_lui_valid ? spec_insn_lui_rs1_addr : spec_insn_lw_valid ? spec_insn_lw_rs1_addr : spec_insn_lwu_valid ? spec_insn_lwu_rs1_addr : spec_insn_or_valid ? spec_insn_or_rs1_addr : spec_insn_ori_valid ? spec_insn_ori_rs1_addr : spec_insn_sb_valid ? spec_insn_sb_rs1_addr : spec_insn_sd_valid ? spec_insn_sd_rs1_addr : spec_insn_sh_valid ? spec_insn_sh_rs1_addr : spec_insn_sll_valid ? spec_insn_sll_rs1_addr : spec_insn_slli_valid ? spec_insn_slli_rs1_addr : spec_insn_slliw_valid ? spec_insn_slliw_rs1_addr : spec_insn_sllw_valid ? spec_insn_sllw_rs1_addr : spec_insn_slt_valid ? spec_insn_slt_rs1_addr : spec_insn_slti_valid ? spec_insn_slti_rs1_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : spec_insn_sra_valid ? spec_insn_sra_rs1_addr : spec_insn_srai_valid ? spec_insn_srai_rs1_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_rs1_addr : spec_insn_sraw_valid ? spec_insn_sraw_rs1_addr : spec_insn_srl_valid ? spec_insn_srl_rs1_addr : spec_insn_srli_valid ? spec_insn_srli_rs1_addr : spec_insn_srliw_valid ? spec_insn_srliw_rs1_addr : spec_insn_srlw_valid ? spec_insn_srlw_rs1_addr : spec_insn_sub_valid ? spec_insn_sub_rs1_addr : spec_insn_subw_valid ? spec_insn_subw_rs1_addr : spec_insn_sw_valid ? spec_insn_sw_rs1_addr : spec_insn_xor_valid ? spec_insn_xor_rs1_addr : spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; assign spec_rs2_addr = spec_insn_add_valid ? spec_insn_add_rs2_addr : spec_insn_addi_valid ? spec_insn_addi_rs2_addr : spec_insn_addiw_valid ? spec_insn_addiw_rs2_addr : spec_insn_addw_valid ? spec_insn_addw_rs2_addr : spec_insn_and_valid ? spec_insn_and_rs2_addr : spec_insn_andi_valid ? spec_insn_andi_rs2_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : spec_insn_beq_valid ? spec_insn_beq_rs2_addr : spec_insn_bge_valid ? spec_insn_bge_rs2_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : spec_insn_blt_valid ? spec_insn_blt_rs2_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : spec_insn_bne_valid ? spec_insn_bne_rs2_addr : spec_insn_c_add_valid ? spec_insn_c_add_rs2_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_rs2_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs2_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs2_addr : spec_insn_c_addiw_valid ? spec_insn_c_addiw_rs2_addr : spec_insn_c_addw_valid ? spec_insn_c_addw_rs2_addr : spec_insn_c_and_valid ? spec_insn_c_and_rs2_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_rs2_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rs2_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rs2_addr : spec_insn_c_j_valid ? spec_insn_c_j_rs2_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rs2_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_rs2_addr : spec_insn_c_ld_valid ? spec_insn_c_ld_rs2_addr : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rs2_addr : spec_insn_c_li_valid ? spec_insn_c_li_rs2_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_rs2_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_rs2_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs2_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_rs2_addr : spec_insn_c_or_valid ? spec_insn_c_or_rs2_addr : spec_insn_c_sd_valid ? spec_insn_c_sd_rs2_addr : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rs2_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_rs2_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_rs2_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_rs2_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_rs2_addr : spec_insn_c_subw_valid ? spec_insn_c_subw_rs2_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_rs2_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rs2_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_rs2_addr : spec_insn_jal_valid ? spec_insn_jal_rs2_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : spec_insn_lb_valid ? spec_insn_lb_rs2_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : spec_insn_ld_valid ? spec_insn_ld_rs2_addr : spec_insn_lh_valid ? spec_insn_lh_rs2_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : spec_insn_lui_valid ? spec_insn_lui_rs2_addr : spec_insn_lw_valid ? spec_insn_lw_rs2_addr : spec_insn_lwu_valid ? spec_insn_lwu_rs2_addr : spec_insn_or_valid ? spec_insn_or_rs2_addr : spec_insn_ori_valid ? spec_insn_ori_rs2_addr : spec_insn_sb_valid ? spec_insn_sb_rs2_addr : spec_insn_sd_valid ? spec_insn_sd_rs2_addr : spec_insn_sh_valid ? spec_insn_sh_rs2_addr : spec_insn_sll_valid ? spec_insn_sll_rs2_addr : spec_insn_slli_valid ? spec_insn_slli_rs2_addr : spec_insn_slliw_valid ? spec_insn_slliw_rs2_addr : spec_insn_sllw_valid ? spec_insn_sllw_rs2_addr : spec_insn_slt_valid ? spec_insn_slt_rs2_addr : spec_insn_slti_valid ? spec_insn_slti_rs2_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : spec_insn_sra_valid ? spec_insn_sra_rs2_addr : spec_insn_srai_valid ? spec_insn_srai_rs2_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_rs2_addr : spec_insn_sraw_valid ? spec_insn_sraw_rs2_addr : spec_insn_srl_valid ? spec_insn_srl_rs2_addr : spec_insn_srli_valid ? spec_insn_srli_rs2_addr : spec_insn_srliw_valid ? spec_insn_srliw_rs2_addr : spec_insn_srlw_valid ? spec_insn_srlw_rs2_addr : spec_insn_sub_valid ? spec_insn_sub_rs2_addr : spec_insn_subw_valid ? spec_insn_subw_rs2_addr : spec_insn_sw_valid ? spec_insn_sw_rs2_addr : spec_insn_xor_valid ? spec_insn_xor_rs2_addr : spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; assign spec_rd_addr = spec_insn_add_valid ? spec_insn_add_rd_addr : spec_insn_addi_valid ? spec_insn_addi_rd_addr : spec_insn_addiw_valid ? spec_insn_addiw_rd_addr : spec_insn_addw_valid ? spec_insn_addw_rd_addr : spec_insn_and_valid ? spec_insn_and_rd_addr : spec_insn_andi_valid ? spec_insn_andi_rd_addr : spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : spec_insn_beq_valid ? spec_insn_beq_rd_addr : spec_insn_bge_valid ? spec_insn_bge_rd_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : spec_insn_blt_valid ? spec_insn_blt_rd_addr : spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : spec_insn_bne_valid ? spec_insn_bne_rd_addr : spec_insn_c_add_valid ? spec_insn_c_add_rd_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_rd_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_addr : spec_insn_c_addiw_valid ? spec_insn_c_addiw_rd_addr : spec_insn_c_addw_valid ? spec_insn_c_addw_rd_addr : spec_insn_c_and_valid ? spec_insn_c_and_rd_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_rd_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_addr : spec_insn_c_j_valid ? spec_insn_c_j_rd_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_rd_addr : spec_insn_c_ld_valid ? spec_insn_c_ld_rd_addr : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rd_addr : spec_insn_c_li_valid ? spec_insn_c_li_rd_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_rd_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_rd_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_rd_addr : spec_insn_c_or_valid ? spec_insn_c_or_rd_addr : spec_insn_c_sd_valid ? spec_insn_c_sd_rd_addr : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rd_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_rd_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_rd_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_rd_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_rd_addr : spec_insn_c_subw_valid ? spec_insn_c_subw_rd_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_rd_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_rd_addr : spec_insn_jal_valid ? spec_insn_jal_rd_addr : spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : spec_insn_lb_valid ? spec_insn_lb_rd_addr : spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : spec_insn_ld_valid ? spec_insn_ld_rd_addr : spec_insn_lh_valid ? spec_insn_lh_rd_addr : spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : spec_insn_lui_valid ? spec_insn_lui_rd_addr : spec_insn_lw_valid ? spec_insn_lw_rd_addr : spec_insn_lwu_valid ? spec_insn_lwu_rd_addr : spec_insn_or_valid ? spec_insn_or_rd_addr : spec_insn_ori_valid ? spec_insn_ori_rd_addr : spec_insn_sb_valid ? spec_insn_sb_rd_addr : spec_insn_sd_valid ? spec_insn_sd_rd_addr : spec_insn_sh_valid ? spec_insn_sh_rd_addr : spec_insn_sll_valid ? spec_insn_sll_rd_addr : spec_insn_slli_valid ? spec_insn_slli_rd_addr : spec_insn_slliw_valid ? spec_insn_slliw_rd_addr : spec_insn_sllw_valid ? spec_insn_sllw_rd_addr : spec_insn_slt_valid ? spec_insn_slt_rd_addr : spec_insn_slti_valid ? spec_insn_slti_rd_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : spec_insn_sra_valid ? spec_insn_sra_rd_addr : spec_insn_srai_valid ? spec_insn_srai_rd_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_rd_addr : spec_insn_sraw_valid ? spec_insn_sraw_rd_addr : spec_insn_srl_valid ? spec_insn_srl_rd_addr : spec_insn_srli_valid ? spec_insn_srli_rd_addr : spec_insn_srliw_valid ? spec_insn_srliw_rd_addr : spec_insn_srlw_valid ? spec_insn_srlw_rd_addr : spec_insn_sub_valid ? spec_insn_sub_rd_addr : spec_insn_subw_valid ? spec_insn_subw_rd_addr : spec_insn_sw_valid ? spec_insn_sw_rd_addr : spec_insn_xor_valid ? spec_insn_xor_rd_addr : spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; assign spec_rd_wdata = spec_insn_add_valid ? spec_insn_add_rd_wdata : spec_insn_addi_valid ? spec_insn_addi_rd_wdata : spec_insn_addiw_valid ? spec_insn_addiw_rd_wdata : spec_insn_addw_valid ? spec_insn_addw_rd_wdata : spec_insn_and_valid ? spec_insn_and_rd_wdata : spec_insn_andi_valid ? spec_insn_andi_rd_wdata : spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : spec_insn_beq_valid ? spec_insn_beq_rd_wdata : spec_insn_bge_valid ? spec_insn_bge_rd_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : spec_insn_blt_valid ? spec_insn_blt_rd_wdata : spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : spec_insn_bne_valid ? spec_insn_bne_rd_wdata : spec_insn_c_add_valid ? spec_insn_c_add_rd_wdata : spec_insn_c_addi_valid ? spec_insn_c_addi_rd_wdata : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_wdata : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_wdata : spec_insn_c_addiw_valid ? spec_insn_c_addiw_rd_wdata : spec_insn_c_addw_valid ? spec_insn_c_addw_rd_wdata : spec_insn_c_and_valid ? spec_insn_c_and_rd_wdata : spec_insn_c_andi_valid ? spec_insn_c_andi_rd_wdata : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_wdata : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_wdata : spec_insn_c_j_valid ? spec_insn_c_j_rd_wdata : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_wdata : spec_insn_c_jr_valid ? spec_insn_c_jr_rd_wdata : spec_insn_c_ld_valid ? spec_insn_c_ld_rd_wdata : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rd_wdata : spec_insn_c_li_valid ? spec_insn_c_li_rd_wdata : spec_insn_c_lui_valid ? spec_insn_c_lui_rd_wdata : spec_insn_c_lw_valid ? spec_insn_c_lw_rd_wdata : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_wdata : spec_insn_c_mv_valid ? spec_insn_c_mv_rd_wdata : spec_insn_c_or_valid ? spec_insn_c_or_rd_wdata : spec_insn_c_sd_valid ? spec_insn_c_sd_rd_wdata : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rd_wdata : spec_insn_c_slli_valid ? spec_insn_c_slli_rd_wdata : spec_insn_c_srai_valid ? spec_insn_c_srai_rd_wdata : spec_insn_c_srli_valid ? spec_insn_c_srli_rd_wdata : spec_insn_c_sub_valid ? spec_insn_c_sub_rd_wdata : spec_insn_c_subw_valid ? spec_insn_c_subw_rd_wdata : spec_insn_c_sw_valid ? spec_insn_c_sw_rd_wdata : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_wdata : spec_insn_c_xor_valid ? spec_insn_c_xor_rd_wdata : spec_insn_jal_valid ? spec_insn_jal_rd_wdata : spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : spec_insn_lb_valid ? spec_insn_lb_rd_wdata : spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : spec_insn_ld_valid ? spec_insn_ld_rd_wdata : spec_insn_lh_valid ? spec_insn_lh_rd_wdata : spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : spec_insn_lui_valid ? spec_insn_lui_rd_wdata : spec_insn_lw_valid ? spec_insn_lw_rd_wdata : spec_insn_lwu_valid ? spec_insn_lwu_rd_wdata : spec_insn_or_valid ? spec_insn_or_rd_wdata : spec_insn_ori_valid ? spec_insn_ori_rd_wdata : spec_insn_sb_valid ? spec_insn_sb_rd_wdata : spec_insn_sd_valid ? spec_insn_sd_rd_wdata : spec_insn_sh_valid ? spec_insn_sh_rd_wdata : spec_insn_sll_valid ? spec_insn_sll_rd_wdata : spec_insn_slli_valid ? spec_insn_slli_rd_wdata : spec_insn_slliw_valid ? spec_insn_slliw_rd_wdata : spec_insn_sllw_valid ? spec_insn_sllw_rd_wdata : spec_insn_slt_valid ? spec_insn_slt_rd_wdata : spec_insn_slti_valid ? spec_insn_slti_rd_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : spec_insn_sra_valid ? spec_insn_sra_rd_wdata : spec_insn_srai_valid ? spec_insn_srai_rd_wdata : spec_insn_sraiw_valid ? spec_insn_sraiw_rd_wdata : spec_insn_sraw_valid ? spec_insn_sraw_rd_wdata : spec_insn_srl_valid ? spec_insn_srl_rd_wdata : spec_insn_srli_valid ? spec_insn_srli_rd_wdata : spec_insn_srliw_valid ? spec_insn_srliw_rd_wdata : spec_insn_srlw_valid ? spec_insn_srlw_rd_wdata : spec_insn_sub_valid ? spec_insn_sub_rd_wdata : spec_insn_subw_valid ? spec_insn_subw_rd_wdata : spec_insn_sw_valid ? spec_insn_sw_rd_wdata : spec_insn_xor_valid ? spec_insn_xor_rd_wdata : spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; assign spec_pc_wdata = spec_insn_add_valid ? spec_insn_add_pc_wdata : spec_insn_addi_valid ? spec_insn_addi_pc_wdata : spec_insn_addiw_valid ? spec_insn_addiw_pc_wdata : spec_insn_addw_valid ? spec_insn_addw_pc_wdata : spec_insn_and_valid ? spec_insn_and_pc_wdata : spec_insn_andi_valid ? spec_insn_andi_pc_wdata : spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : spec_insn_beq_valid ? spec_insn_beq_pc_wdata : spec_insn_bge_valid ? spec_insn_bge_pc_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : spec_insn_blt_valid ? spec_insn_blt_pc_wdata : spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : spec_insn_bne_valid ? spec_insn_bne_pc_wdata : spec_insn_c_add_valid ? spec_insn_c_add_pc_wdata : spec_insn_c_addi_valid ? spec_insn_c_addi_pc_wdata : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_pc_wdata : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_pc_wdata : spec_insn_c_addiw_valid ? spec_insn_c_addiw_pc_wdata : spec_insn_c_addw_valid ? spec_insn_c_addw_pc_wdata : spec_insn_c_and_valid ? spec_insn_c_and_pc_wdata : spec_insn_c_andi_valid ? spec_insn_c_andi_pc_wdata : spec_insn_c_beqz_valid ? spec_insn_c_beqz_pc_wdata : spec_insn_c_bnez_valid ? spec_insn_c_bnez_pc_wdata : spec_insn_c_j_valid ? spec_insn_c_j_pc_wdata : spec_insn_c_jalr_valid ? spec_insn_c_jalr_pc_wdata : spec_insn_c_jr_valid ? spec_insn_c_jr_pc_wdata : spec_insn_c_ld_valid ? spec_insn_c_ld_pc_wdata : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_pc_wdata : spec_insn_c_li_valid ? spec_insn_c_li_pc_wdata : spec_insn_c_lui_valid ? spec_insn_c_lui_pc_wdata : spec_insn_c_lw_valid ? spec_insn_c_lw_pc_wdata : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_pc_wdata : spec_insn_c_mv_valid ? spec_insn_c_mv_pc_wdata : spec_insn_c_or_valid ? spec_insn_c_or_pc_wdata : spec_insn_c_sd_valid ? spec_insn_c_sd_pc_wdata : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_pc_wdata : spec_insn_c_slli_valid ? spec_insn_c_slli_pc_wdata : spec_insn_c_srai_valid ? spec_insn_c_srai_pc_wdata : spec_insn_c_srli_valid ? spec_insn_c_srli_pc_wdata : spec_insn_c_sub_valid ? spec_insn_c_sub_pc_wdata : spec_insn_c_subw_valid ? spec_insn_c_subw_pc_wdata : spec_insn_c_sw_valid ? spec_insn_c_sw_pc_wdata : spec_insn_c_swsp_valid ? spec_insn_c_swsp_pc_wdata : spec_insn_c_xor_valid ? spec_insn_c_xor_pc_wdata : spec_insn_jal_valid ? spec_insn_jal_pc_wdata : spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : spec_insn_lb_valid ? spec_insn_lb_pc_wdata : spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : spec_insn_ld_valid ? spec_insn_ld_pc_wdata : spec_insn_lh_valid ? spec_insn_lh_pc_wdata : spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : spec_insn_lui_valid ? spec_insn_lui_pc_wdata : spec_insn_lw_valid ? spec_insn_lw_pc_wdata : spec_insn_lwu_valid ? spec_insn_lwu_pc_wdata : spec_insn_or_valid ? spec_insn_or_pc_wdata : spec_insn_ori_valid ? spec_insn_ori_pc_wdata : spec_insn_sb_valid ? spec_insn_sb_pc_wdata : spec_insn_sd_valid ? spec_insn_sd_pc_wdata : spec_insn_sh_valid ? spec_insn_sh_pc_wdata : spec_insn_sll_valid ? spec_insn_sll_pc_wdata : spec_insn_slli_valid ? spec_insn_slli_pc_wdata : spec_insn_slliw_valid ? spec_insn_slliw_pc_wdata : spec_insn_sllw_valid ? spec_insn_sllw_pc_wdata : spec_insn_slt_valid ? spec_insn_slt_pc_wdata : spec_insn_slti_valid ? spec_insn_slti_pc_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : spec_insn_sra_valid ? spec_insn_sra_pc_wdata : spec_insn_srai_valid ? spec_insn_srai_pc_wdata : spec_insn_sraiw_valid ? spec_insn_sraiw_pc_wdata : spec_insn_sraw_valid ? spec_insn_sraw_pc_wdata : spec_insn_srl_valid ? spec_insn_srl_pc_wdata : spec_insn_srli_valid ? spec_insn_srli_pc_wdata : spec_insn_srliw_valid ? spec_insn_srliw_pc_wdata : spec_insn_srlw_valid ? spec_insn_srlw_pc_wdata : spec_insn_sub_valid ? spec_insn_sub_pc_wdata : spec_insn_subw_valid ? spec_insn_subw_pc_wdata : spec_insn_sw_valid ? spec_insn_sw_pc_wdata : spec_insn_xor_valid ? spec_insn_xor_pc_wdata : spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; assign spec_mem_addr = spec_insn_add_valid ? spec_insn_add_mem_addr : spec_insn_addi_valid ? spec_insn_addi_mem_addr : spec_insn_addiw_valid ? spec_insn_addiw_mem_addr : spec_insn_addw_valid ? spec_insn_addw_mem_addr : spec_insn_and_valid ? spec_insn_and_mem_addr : spec_insn_andi_valid ? spec_insn_andi_mem_addr : spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : spec_insn_beq_valid ? spec_insn_beq_mem_addr : spec_insn_bge_valid ? spec_insn_bge_mem_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : spec_insn_blt_valid ? spec_insn_blt_mem_addr : spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : spec_insn_bne_valid ? spec_insn_bne_mem_addr : spec_insn_c_add_valid ? spec_insn_c_add_mem_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_addr : spec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_addr : spec_insn_c_addw_valid ? spec_insn_c_addw_mem_addr : spec_insn_c_and_valid ? spec_insn_c_and_mem_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_addr : spec_insn_c_j_valid ? spec_insn_c_j_mem_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_addr : spec_insn_c_ld_valid ? spec_insn_c_ld_mem_addr : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_addr : spec_insn_c_li_valid ? spec_insn_c_li_mem_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_addr : spec_insn_c_or_valid ? spec_insn_c_or_mem_addr : spec_insn_c_sd_valid ? spec_insn_c_sd_mem_addr : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_addr : spec_insn_c_subw_valid ? spec_insn_c_subw_mem_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_addr : spec_insn_jal_valid ? spec_insn_jal_mem_addr : spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : spec_insn_lb_valid ? spec_insn_lb_mem_addr : spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : spec_insn_ld_valid ? spec_insn_ld_mem_addr : spec_insn_lh_valid ? spec_insn_lh_mem_addr : spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : spec_insn_lui_valid ? spec_insn_lui_mem_addr : spec_insn_lw_valid ? spec_insn_lw_mem_addr : spec_insn_lwu_valid ? spec_insn_lwu_mem_addr : spec_insn_or_valid ? spec_insn_or_mem_addr : spec_insn_ori_valid ? spec_insn_ori_mem_addr : spec_insn_sb_valid ? spec_insn_sb_mem_addr : spec_insn_sd_valid ? spec_insn_sd_mem_addr : spec_insn_sh_valid ? spec_insn_sh_mem_addr : spec_insn_sll_valid ? spec_insn_sll_mem_addr : spec_insn_slli_valid ? spec_insn_slli_mem_addr : spec_insn_slliw_valid ? spec_insn_slliw_mem_addr : spec_insn_sllw_valid ? spec_insn_sllw_mem_addr : spec_insn_slt_valid ? spec_insn_slt_mem_addr : spec_insn_slti_valid ? spec_insn_slti_mem_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : spec_insn_sra_valid ? spec_insn_sra_mem_addr : spec_insn_srai_valid ? spec_insn_srai_mem_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_addr : spec_insn_sraw_valid ? spec_insn_sraw_mem_addr : spec_insn_srl_valid ? spec_insn_srl_mem_addr : spec_insn_srli_valid ? spec_insn_srli_mem_addr : spec_insn_srliw_valid ? spec_insn_srliw_mem_addr : spec_insn_srlw_valid ? spec_insn_srlw_mem_addr : spec_insn_sub_valid ? spec_insn_sub_mem_addr : spec_insn_subw_valid ? spec_insn_subw_mem_addr : spec_insn_sw_valid ? spec_insn_sw_mem_addr : spec_insn_xor_valid ? spec_insn_xor_mem_addr : spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; assign spec_mem_rmask = spec_insn_add_valid ? spec_insn_add_mem_rmask : spec_insn_addi_valid ? spec_insn_addi_mem_rmask : spec_insn_addiw_valid ? spec_insn_addiw_mem_rmask : spec_insn_addw_valid ? spec_insn_addw_mem_rmask : spec_insn_and_valid ? spec_insn_and_mem_rmask : spec_insn_andi_valid ? spec_insn_andi_mem_rmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : spec_insn_beq_valid ? spec_insn_beq_mem_rmask : spec_insn_bge_valid ? spec_insn_bge_mem_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : spec_insn_blt_valid ? spec_insn_blt_mem_rmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : spec_insn_bne_valid ? spec_insn_bne_mem_rmask : spec_insn_c_add_valid ? spec_insn_c_add_mem_rmask : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_rmask : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_rmask : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_rmask : spec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_rmask : spec_insn_c_addw_valid ? spec_insn_c_addw_mem_rmask : spec_insn_c_and_valid ? spec_insn_c_and_mem_rmask : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_rmask : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_rmask : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_rmask : spec_insn_c_j_valid ? spec_insn_c_j_mem_rmask : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_rmask : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_rmask : spec_insn_c_ld_valid ? spec_insn_c_ld_mem_rmask : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_rmask : spec_insn_c_li_valid ? spec_insn_c_li_mem_rmask : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_rmask : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_rmask : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_rmask : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_rmask : spec_insn_c_or_valid ? spec_insn_c_or_mem_rmask : spec_insn_c_sd_valid ? spec_insn_c_sd_mem_rmask : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_rmask : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_rmask : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_rmask : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_rmask : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_rmask : spec_insn_c_subw_valid ? spec_insn_c_subw_mem_rmask : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_rmask : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_rmask : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_rmask : spec_insn_jal_valid ? spec_insn_jal_mem_rmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : spec_insn_lb_valid ? spec_insn_lb_mem_rmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : spec_insn_ld_valid ? spec_insn_ld_mem_rmask : spec_insn_lh_valid ? spec_insn_lh_mem_rmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : spec_insn_lui_valid ? spec_insn_lui_mem_rmask : spec_insn_lw_valid ? spec_insn_lw_mem_rmask : spec_insn_lwu_valid ? spec_insn_lwu_mem_rmask : spec_insn_or_valid ? spec_insn_or_mem_rmask : spec_insn_ori_valid ? spec_insn_ori_mem_rmask : spec_insn_sb_valid ? spec_insn_sb_mem_rmask : spec_insn_sd_valid ? spec_insn_sd_mem_rmask : spec_insn_sh_valid ? spec_insn_sh_mem_rmask : spec_insn_sll_valid ? spec_insn_sll_mem_rmask : spec_insn_slli_valid ? spec_insn_slli_mem_rmask : spec_insn_slliw_valid ? spec_insn_slliw_mem_rmask : spec_insn_sllw_valid ? spec_insn_sllw_mem_rmask : spec_insn_slt_valid ? spec_insn_slt_mem_rmask : spec_insn_slti_valid ? spec_insn_slti_mem_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : spec_insn_sra_valid ? spec_insn_sra_mem_rmask : spec_insn_srai_valid ? spec_insn_srai_mem_rmask : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_rmask : spec_insn_sraw_valid ? spec_insn_sraw_mem_rmask : spec_insn_srl_valid ? spec_insn_srl_mem_rmask : spec_insn_srli_valid ? spec_insn_srli_mem_rmask : spec_insn_srliw_valid ? spec_insn_srliw_mem_rmask : spec_insn_srlw_valid ? spec_insn_srlw_mem_rmask : spec_insn_sub_valid ? spec_insn_sub_mem_rmask : spec_insn_subw_valid ? spec_insn_subw_mem_rmask : spec_insn_sw_valid ? spec_insn_sw_mem_rmask : spec_insn_xor_valid ? spec_insn_xor_mem_rmask : spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; assign spec_mem_wmask = spec_insn_add_valid ? spec_insn_add_mem_wmask : spec_insn_addi_valid ? spec_insn_addi_mem_wmask : spec_insn_addiw_valid ? spec_insn_addiw_mem_wmask : spec_insn_addw_valid ? spec_insn_addw_mem_wmask : spec_insn_and_valid ? spec_insn_and_mem_wmask : spec_insn_andi_valid ? spec_insn_andi_mem_wmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : spec_insn_beq_valid ? spec_insn_beq_mem_wmask : spec_insn_bge_valid ? spec_insn_bge_mem_wmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : spec_insn_blt_valid ? spec_insn_blt_mem_wmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : spec_insn_bne_valid ? spec_insn_bne_mem_wmask : spec_insn_c_add_valid ? spec_insn_c_add_mem_wmask : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_wmask : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wmask : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wmask : spec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_wmask : spec_insn_c_addw_valid ? spec_insn_c_addw_mem_wmask : spec_insn_c_and_valid ? spec_insn_c_and_mem_wmask : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_wmask : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wmask : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wmask : spec_insn_c_j_valid ? spec_insn_c_j_mem_wmask : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wmask : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_wmask : spec_insn_c_ld_valid ? spec_insn_c_ld_mem_wmask : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_wmask : spec_insn_c_li_valid ? spec_insn_c_li_mem_wmask : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_wmask : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_wmask : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wmask : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_wmask : spec_insn_c_or_valid ? spec_insn_c_or_mem_wmask : spec_insn_c_sd_valid ? spec_insn_c_sd_mem_wmask : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_wmask : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_wmask : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_wmask : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_wmask : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_wmask : spec_insn_c_subw_valid ? spec_insn_c_subw_mem_wmask : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_wmask : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wmask : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_wmask : spec_insn_jal_valid ? spec_insn_jal_mem_wmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : spec_insn_lb_valid ? spec_insn_lb_mem_wmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : spec_insn_ld_valid ? spec_insn_ld_mem_wmask : spec_insn_lh_valid ? spec_insn_lh_mem_wmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : spec_insn_lui_valid ? spec_insn_lui_mem_wmask : spec_insn_lw_valid ? spec_insn_lw_mem_wmask : spec_insn_lwu_valid ? spec_insn_lwu_mem_wmask : spec_insn_or_valid ? spec_insn_or_mem_wmask : spec_insn_ori_valid ? spec_insn_ori_mem_wmask : spec_insn_sb_valid ? spec_insn_sb_mem_wmask : spec_insn_sd_valid ? spec_insn_sd_mem_wmask : spec_insn_sh_valid ? spec_insn_sh_mem_wmask : spec_insn_sll_valid ? spec_insn_sll_mem_wmask : spec_insn_slli_valid ? spec_insn_slli_mem_wmask : spec_insn_slliw_valid ? spec_insn_slliw_mem_wmask : spec_insn_sllw_valid ? spec_insn_sllw_mem_wmask : spec_insn_slt_valid ? spec_insn_slt_mem_wmask : spec_insn_slti_valid ? spec_insn_slti_mem_wmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : spec_insn_sra_valid ? spec_insn_sra_mem_wmask : spec_insn_srai_valid ? spec_insn_srai_mem_wmask : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wmask : spec_insn_sraw_valid ? spec_insn_sraw_mem_wmask : spec_insn_srl_valid ? spec_insn_srl_mem_wmask : spec_insn_srli_valid ? spec_insn_srli_mem_wmask : spec_insn_srliw_valid ? spec_insn_srliw_mem_wmask : spec_insn_srlw_valid ? spec_insn_srlw_mem_wmask : spec_insn_sub_valid ? spec_insn_sub_mem_wmask : spec_insn_subw_valid ? spec_insn_subw_mem_wmask : spec_insn_sw_valid ? spec_insn_sw_mem_wmask : spec_insn_xor_valid ? spec_insn_xor_mem_wmask : spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; assign spec_mem_wdata = spec_insn_add_valid ? spec_insn_add_mem_wdata : spec_insn_addi_valid ? spec_insn_addi_mem_wdata : spec_insn_addiw_valid ? spec_insn_addiw_mem_wdata : spec_insn_addw_valid ? spec_insn_addw_mem_wdata : spec_insn_and_valid ? spec_insn_and_mem_wdata : spec_insn_andi_valid ? spec_insn_andi_mem_wdata : spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : spec_insn_beq_valid ? spec_insn_beq_mem_wdata : spec_insn_bge_valid ? spec_insn_bge_mem_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : spec_insn_blt_valid ? spec_insn_blt_mem_wdata : spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : spec_insn_bne_valid ? spec_insn_bne_mem_wdata : spec_insn_c_add_valid ? spec_insn_c_add_mem_wdata : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_wdata : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wdata : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wdata : spec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_wdata : spec_insn_c_addw_valid ? spec_insn_c_addw_mem_wdata : spec_insn_c_and_valid ? spec_insn_c_and_mem_wdata : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_wdata : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wdata : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wdata : spec_insn_c_j_valid ? spec_insn_c_j_mem_wdata : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wdata : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_wdata : spec_insn_c_ld_valid ? spec_insn_c_ld_mem_wdata : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_wdata : spec_insn_c_li_valid ? spec_insn_c_li_mem_wdata : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_wdata : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_wdata : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wdata : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_wdata : spec_insn_c_or_valid ? spec_insn_c_or_mem_wdata : spec_insn_c_sd_valid ? spec_insn_c_sd_mem_wdata : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_wdata : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_wdata : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_wdata : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_wdata : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_wdata : spec_insn_c_subw_valid ? spec_insn_c_subw_mem_wdata : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_wdata : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wdata : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_wdata : spec_insn_jal_valid ? spec_insn_jal_mem_wdata : spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : spec_insn_lb_valid ? spec_insn_lb_mem_wdata : spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : spec_insn_ld_valid ? spec_insn_ld_mem_wdata : spec_insn_lh_valid ? spec_insn_lh_mem_wdata : spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : spec_insn_lui_valid ? spec_insn_lui_mem_wdata : spec_insn_lw_valid ? spec_insn_lw_mem_wdata : spec_insn_lwu_valid ? spec_insn_lwu_mem_wdata : spec_insn_or_valid ? spec_insn_or_mem_wdata : spec_insn_ori_valid ? spec_insn_ori_mem_wdata : spec_insn_sb_valid ? spec_insn_sb_mem_wdata : spec_insn_sd_valid ? spec_insn_sd_mem_wdata : spec_insn_sh_valid ? spec_insn_sh_mem_wdata : spec_insn_sll_valid ? spec_insn_sll_mem_wdata : spec_insn_slli_valid ? spec_insn_slli_mem_wdata : spec_insn_slliw_valid ? spec_insn_slliw_mem_wdata : spec_insn_sllw_valid ? spec_insn_sllw_mem_wdata : spec_insn_slt_valid ? spec_insn_slt_mem_wdata : spec_insn_slti_valid ? spec_insn_slti_mem_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : spec_insn_sra_valid ? spec_insn_sra_mem_wdata : spec_insn_srai_valid ? spec_insn_srai_mem_wdata : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wdata : spec_insn_sraw_valid ? spec_insn_sraw_mem_wdata : spec_insn_srl_valid ? spec_insn_srl_mem_wdata : spec_insn_srli_valid ? spec_insn_srli_mem_wdata : spec_insn_srliw_valid ? spec_insn_srliw_mem_wdata : spec_insn_srlw_valid ? spec_insn_srlw_mem_wdata : spec_insn_sub_valid ? spec_insn_sub_mem_wdata : spec_insn_subw_valid ? spec_insn_subw_mem_wdata : spec_insn_sw_valid ? spec_insn_sw_mem_wdata : spec_insn_xor_valid ? spec_insn_xor_mem_wdata : spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; `ifdef RISCV_FORMAL_CSR_MISA assign spec_csr_misa_rmask = spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : spec_insn_addiw_valid ? spec_insn_addiw_csr_misa_rmask : spec_insn_addw_valid ? spec_insn_addw_csr_misa_rmask : spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : spec_insn_c_add_valid ? spec_insn_c_add_csr_misa_rmask : spec_insn_c_addi_valid ? spec_insn_c_addi_csr_misa_rmask : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_csr_misa_rmask : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_csr_misa_rmask : spec_insn_c_addiw_valid ? spec_insn_c_addiw_csr_misa_rmask : spec_insn_c_addw_valid ? spec_insn_c_addw_csr_misa_rmask : spec_insn_c_and_valid ? spec_insn_c_and_csr_misa_rmask : spec_insn_c_andi_valid ? spec_insn_c_andi_csr_misa_rmask : spec_insn_c_beqz_valid ? spec_insn_c_beqz_csr_misa_rmask : spec_insn_c_bnez_valid ? spec_insn_c_bnez_csr_misa_rmask : spec_insn_c_j_valid ? spec_insn_c_j_csr_misa_rmask : spec_insn_c_jalr_valid ? spec_insn_c_jalr_csr_misa_rmask : spec_insn_c_jr_valid ? spec_insn_c_jr_csr_misa_rmask : spec_insn_c_ld_valid ? spec_insn_c_ld_csr_misa_rmask : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_csr_misa_rmask : spec_insn_c_li_valid ? spec_insn_c_li_csr_misa_rmask : spec_insn_c_lui_valid ? spec_insn_c_lui_csr_misa_rmask : spec_insn_c_lw_valid ? spec_insn_c_lw_csr_misa_rmask : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_csr_misa_rmask : spec_insn_c_mv_valid ? spec_insn_c_mv_csr_misa_rmask : spec_insn_c_or_valid ? spec_insn_c_or_csr_misa_rmask : spec_insn_c_sd_valid ? spec_insn_c_sd_csr_misa_rmask : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_csr_misa_rmask : spec_insn_c_slli_valid ? spec_insn_c_slli_csr_misa_rmask : spec_insn_c_srai_valid ? spec_insn_c_srai_csr_misa_rmask : spec_insn_c_srli_valid ? spec_insn_c_srli_csr_misa_rmask : spec_insn_c_sub_valid ? spec_insn_c_sub_csr_misa_rmask : spec_insn_c_subw_valid ? spec_insn_c_subw_csr_misa_rmask : spec_insn_c_sw_valid ? spec_insn_c_sw_csr_misa_rmask : spec_insn_c_swsp_valid ? spec_insn_c_swsp_csr_misa_rmask : spec_insn_c_xor_valid ? spec_insn_c_xor_csr_misa_rmask : spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : spec_insn_ld_valid ? spec_insn_ld_csr_misa_rmask : spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : spec_insn_lwu_valid ? spec_insn_lwu_csr_misa_rmask : spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : spec_insn_sd_valid ? spec_insn_sd_csr_misa_rmask : spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : spec_insn_slliw_valid ? spec_insn_slliw_csr_misa_rmask : spec_insn_sllw_valid ? spec_insn_sllw_csr_misa_rmask : spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : spec_insn_sraiw_valid ? spec_insn_sraiw_csr_misa_rmask : spec_insn_sraw_valid ? spec_insn_sraw_csr_misa_rmask : spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : spec_insn_srliw_valid ? spec_insn_srliw_csr_misa_rmask : spec_insn_srlw_valid ? spec_insn_srlw_csr_misa_rmask : spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : spec_insn_subw_valid ? spec_insn_subw_csr_misa_rmask : spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; `endif endmodule ================================================ FILE: insns/isa_rv64im.txt ================================================ add addi addiw addw and andi auipc beq bge bgeu blt bltu bne div divu divuw divw jal jalr lb lbu ld lh lhu lui lw lwu mul mulh mulhsu mulhu mulw or ori rem remu remuw remw sb sd sh sll slli slliw sllw slt slti sltiu sltu sra srai sraiw sraw srl srli srliw srlw sub subw sw xor xori ================================================ FILE: insns/isa_rv64im.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_isa_rv64im ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); wire spec_insn_add_valid; wire spec_insn_add_trap; wire [ 4 : 0] spec_insn_add_rs1_addr; wire [ 4 : 0] spec_insn_add_rs2_addr; wire [ 4 : 0] spec_insn_add_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; `endif rvfi_insn_add insn_add ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), `endif .spec_valid(spec_insn_add_valid), .spec_trap(spec_insn_add_trap), .spec_rs1_addr(spec_insn_add_rs1_addr), .spec_rs2_addr(spec_insn_add_rs2_addr), .spec_rd_addr(spec_insn_add_rd_addr), .spec_rd_wdata(spec_insn_add_rd_wdata), .spec_pc_wdata(spec_insn_add_pc_wdata), .spec_mem_addr(spec_insn_add_mem_addr), .spec_mem_rmask(spec_insn_add_mem_rmask), .spec_mem_wmask(spec_insn_add_mem_wmask), .spec_mem_wdata(spec_insn_add_mem_wdata) ); wire spec_insn_addi_valid; wire spec_insn_addi_trap; wire [ 4 : 0] spec_insn_addi_rs1_addr; wire [ 4 : 0] spec_insn_addi_rs2_addr; wire [ 4 : 0] spec_insn_addi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; `endif rvfi_insn_addi insn_addi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), `endif .spec_valid(spec_insn_addi_valid), .spec_trap(spec_insn_addi_trap), .spec_rs1_addr(spec_insn_addi_rs1_addr), .spec_rs2_addr(spec_insn_addi_rs2_addr), .spec_rd_addr(spec_insn_addi_rd_addr), .spec_rd_wdata(spec_insn_addi_rd_wdata), .spec_pc_wdata(spec_insn_addi_pc_wdata), .spec_mem_addr(spec_insn_addi_mem_addr), .spec_mem_rmask(spec_insn_addi_mem_rmask), .spec_mem_wmask(spec_insn_addi_mem_wmask), .spec_mem_wdata(spec_insn_addi_mem_wdata) ); wire spec_insn_addiw_valid; wire spec_insn_addiw_trap; wire [ 4 : 0] spec_insn_addiw_rs1_addr; wire [ 4 : 0] spec_insn_addiw_rs2_addr; wire [ 4 : 0] spec_insn_addiw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_csr_misa_rmask; `endif rvfi_insn_addiw insn_addiw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addiw_csr_misa_rmask), `endif .spec_valid(spec_insn_addiw_valid), .spec_trap(spec_insn_addiw_trap), .spec_rs1_addr(spec_insn_addiw_rs1_addr), .spec_rs2_addr(spec_insn_addiw_rs2_addr), .spec_rd_addr(spec_insn_addiw_rd_addr), .spec_rd_wdata(spec_insn_addiw_rd_wdata), .spec_pc_wdata(spec_insn_addiw_pc_wdata), .spec_mem_addr(spec_insn_addiw_mem_addr), .spec_mem_rmask(spec_insn_addiw_mem_rmask), .spec_mem_wmask(spec_insn_addiw_mem_wmask), .spec_mem_wdata(spec_insn_addiw_mem_wdata) ); wire spec_insn_addw_valid; wire spec_insn_addw_trap; wire [ 4 : 0] spec_insn_addw_rs1_addr; wire [ 4 : 0] spec_insn_addw_rs2_addr; wire [ 4 : 0] spec_insn_addw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_csr_misa_rmask; `endif rvfi_insn_addw insn_addw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addw_csr_misa_rmask), `endif .spec_valid(spec_insn_addw_valid), .spec_trap(spec_insn_addw_trap), .spec_rs1_addr(spec_insn_addw_rs1_addr), .spec_rs2_addr(spec_insn_addw_rs2_addr), .spec_rd_addr(spec_insn_addw_rd_addr), .spec_rd_wdata(spec_insn_addw_rd_wdata), .spec_pc_wdata(spec_insn_addw_pc_wdata), .spec_mem_addr(spec_insn_addw_mem_addr), .spec_mem_rmask(spec_insn_addw_mem_rmask), .spec_mem_wmask(spec_insn_addw_mem_wmask), .spec_mem_wdata(spec_insn_addw_mem_wdata) ); wire spec_insn_and_valid; wire spec_insn_and_trap; wire [ 4 : 0] spec_insn_and_rs1_addr; wire [ 4 : 0] spec_insn_and_rs2_addr; wire [ 4 : 0] spec_insn_and_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; `endif rvfi_insn_and insn_and ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), `endif .spec_valid(spec_insn_and_valid), .spec_trap(spec_insn_and_trap), .spec_rs1_addr(spec_insn_and_rs1_addr), .spec_rs2_addr(spec_insn_and_rs2_addr), .spec_rd_addr(spec_insn_and_rd_addr), .spec_rd_wdata(spec_insn_and_rd_wdata), .spec_pc_wdata(spec_insn_and_pc_wdata), .spec_mem_addr(spec_insn_and_mem_addr), .spec_mem_rmask(spec_insn_and_mem_rmask), .spec_mem_wmask(spec_insn_and_mem_wmask), .spec_mem_wdata(spec_insn_and_mem_wdata) ); wire spec_insn_andi_valid; wire spec_insn_andi_trap; wire [ 4 : 0] spec_insn_andi_rs1_addr; wire [ 4 : 0] spec_insn_andi_rs2_addr; wire [ 4 : 0] spec_insn_andi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; `endif rvfi_insn_andi insn_andi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), `endif .spec_valid(spec_insn_andi_valid), .spec_trap(spec_insn_andi_trap), .spec_rs1_addr(spec_insn_andi_rs1_addr), .spec_rs2_addr(spec_insn_andi_rs2_addr), .spec_rd_addr(spec_insn_andi_rd_addr), .spec_rd_wdata(spec_insn_andi_rd_wdata), .spec_pc_wdata(spec_insn_andi_pc_wdata), .spec_mem_addr(spec_insn_andi_mem_addr), .spec_mem_rmask(spec_insn_andi_mem_rmask), .spec_mem_wmask(spec_insn_andi_mem_wmask), .spec_mem_wdata(spec_insn_andi_mem_wdata) ); wire spec_insn_auipc_valid; wire spec_insn_auipc_trap; wire [ 4 : 0] spec_insn_auipc_rs1_addr; wire [ 4 : 0] spec_insn_auipc_rs2_addr; wire [ 4 : 0] spec_insn_auipc_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; `endif rvfi_insn_auipc insn_auipc ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), `endif .spec_valid(spec_insn_auipc_valid), .spec_trap(spec_insn_auipc_trap), .spec_rs1_addr(spec_insn_auipc_rs1_addr), .spec_rs2_addr(spec_insn_auipc_rs2_addr), .spec_rd_addr(spec_insn_auipc_rd_addr), .spec_rd_wdata(spec_insn_auipc_rd_wdata), .spec_pc_wdata(spec_insn_auipc_pc_wdata), .spec_mem_addr(spec_insn_auipc_mem_addr), .spec_mem_rmask(spec_insn_auipc_mem_rmask), .spec_mem_wmask(spec_insn_auipc_mem_wmask), .spec_mem_wdata(spec_insn_auipc_mem_wdata) ); wire spec_insn_beq_valid; wire spec_insn_beq_trap; wire [ 4 : 0] spec_insn_beq_rs1_addr; wire [ 4 : 0] spec_insn_beq_rs2_addr; wire [ 4 : 0] spec_insn_beq_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; `endif rvfi_insn_beq insn_beq ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), `endif .spec_valid(spec_insn_beq_valid), .spec_trap(spec_insn_beq_trap), .spec_rs1_addr(spec_insn_beq_rs1_addr), .spec_rs2_addr(spec_insn_beq_rs2_addr), .spec_rd_addr(spec_insn_beq_rd_addr), .spec_rd_wdata(spec_insn_beq_rd_wdata), .spec_pc_wdata(spec_insn_beq_pc_wdata), .spec_mem_addr(spec_insn_beq_mem_addr), .spec_mem_rmask(spec_insn_beq_mem_rmask), .spec_mem_wmask(spec_insn_beq_mem_wmask), .spec_mem_wdata(spec_insn_beq_mem_wdata) ); wire spec_insn_bge_valid; wire spec_insn_bge_trap; wire [ 4 : 0] spec_insn_bge_rs1_addr; wire [ 4 : 0] spec_insn_bge_rs2_addr; wire [ 4 : 0] spec_insn_bge_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; `endif rvfi_insn_bge insn_bge ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), `endif .spec_valid(spec_insn_bge_valid), .spec_trap(spec_insn_bge_trap), .spec_rs1_addr(spec_insn_bge_rs1_addr), .spec_rs2_addr(spec_insn_bge_rs2_addr), .spec_rd_addr(spec_insn_bge_rd_addr), .spec_rd_wdata(spec_insn_bge_rd_wdata), .spec_pc_wdata(spec_insn_bge_pc_wdata), .spec_mem_addr(spec_insn_bge_mem_addr), .spec_mem_rmask(spec_insn_bge_mem_rmask), .spec_mem_wmask(spec_insn_bge_mem_wmask), .spec_mem_wdata(spec_insn_bge_mem_wdata) ); wire spec_insn_bgeu_valid; wire spec_insn_bgeu_trap; wire [ 4 : 0] spec_insn_bgeu_rs1_addr; wire [ 4 : 0] spec_insn_bgeu_rs2_addr; wire [ 4 : 0] spec_insn_bgeu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; `endif rvfi_insn_bgeu insn_bgeu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), `endif .spec_valid(spec_insn_bgeu_valid), .spec_trap(spec_insn_bgeu_trap), .spec_rs1_addr(spec_insn_bgeu_rs1_addr), .spec_rs2_addr(spec_insn_bgeu_rs2_addr), .spec_rd_addr(spec_insn_bgeu_rd_addr), .spec_rd_wdata(spec_insn_bgeu_rd_wdata), .spec_pc_wdata(spec_insn_bgeu_pc_wdata), .spec_mem_addr(spec_insn_bgeu_mem_addr), .spec_mem_rmask(spec_insn_bgeu_mem_rmask), .spec_mem_wmask(spec_insn_bgeu_mem_wmask), .spec_mem_wdata(spec_insn_bgeu_mem_wdata) ); wire spec_insn_blt_valid; wire spec_insn_blt_trap; wire [ 4 : 0] spec_insn_blt_rs1_addr; wire [ 4 : 0] spec_insn_blt_rs2_addr; wire [ 4 : 0] spec_insn_blt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; `endif rvfi_insn_blt insn_blt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), `endif .spec_valid(spec_insn_blt_valid), .spec_trap(spec_insn_blt_trap), .spec_rs1_addr(spec_insn_blt_rs1_addr), .spec_rs2_addr(spec_insn_blt_rs2_addr), .spec_rd_addr(spec_insn_blt_rd_addr), .spec_rd_wdata(spec_insn_blt_rd_wdata), .spec_pc_wdata(spec_insn_blt_pc_wdata), .spec_mem_addr(spec_insn_blt_mem_addr), .spec_mem_rmask(spec_insn_blt_mem_rmask), .spec_mem_wmask(spec_insn_blt_mem_wmask), .spec_mem_wdata(spec_insn_blt_mem_wdata) ); wire spec_insn_bltu_valid; wire spec_insn_bltu_trap; wire [ 4 : 0] spec_insn_bltu_rs1_addr; wire [ 4 : 0] spec_insn_bltu_rs2_addr; wire [ 4 : 0] spec_insn_bltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; `endif rvfi_insn_bltu insn_bltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), `endif .spec_valid(spec_insn_bltu_valid), .spec_trap(spec_insn_bltu_trap), .spec_rs1_addr(spec_insn_bltu_rs1_addr), .spec_rs2_addr(spec_insn_bltu_rs2_addr), .spec_rd_addr(spec_insn_bltu_rd_addr), .spec_rd_wdata(spec_insn_bltu_rd_wdata), .spec_pc_wdata(spec_insn_bltu_pc_wdata), .spec_mem_addr(spec_insn_bltu_mem_addr), .spec_mem_rmask(spec_insn_bltu_mem_rmask), .spec_mem_wmask(spec_insn_bltu_mem_wmask), .spec_mem_wdata(spec_insn_bltu_mem_wdata) ); wire spec_insn_bne_valid; wire spec_insn_bne_trap; wire [ 4 : 0] spec_insn_bne_rs1_addr; wire [ 4 : 0] spec_insn_bne_rs2_addr; wire [ 4 : 0] spec_insn_bne_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; `endif rvfi_insn_bne insn_bne ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), `endif .spec_valid(spec_insn_bne_valid), .spec_trap(spec_insn_bne_trap), .spec_rs1_addr(spec_insn_bne_rs1_addr), .spec_rs2_addr(spec_insn_bne_rs2_addr), .spec_rd_addr(spec_insn_bne_rd_addr), .spec_rd_wdata(spec_insn_bne_rd_wdata), .spec_pc_wdata(spec_insn_bne_pc_wdata), .spec_mem_addr(spec_insn_bne_mem_addr), .spec_mem_rmask(spec_insn_bne_mem_rmask), .spec_mem_wmask(spec_insn_bne_mem_wmask), .spec_mem_wdata(spec_insn_bne_mem_wdata) ); wire spec_insn_div_valid; wire spec_insn_div_trap; wire [ 4 : 0] spec_insn_div_rs1_addr; wire [ 4 : 0] spec_insn_div_rs2_addr; wire [ 4 : 0] spec_insn_div_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_csr_misa_rmask; `endif rvfi_insn_div insn_div ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_div_csr_misa_rmask), `endif .spec_valid(spec_insn_div_valid), .spec_trap(spec_insn_div_trap), .spec_rs1_addr(spec_insn_div_rs1_addr), .spec_rs2_addr(spec_insn_div_rs2_addr), .spec_rd_addr(spec_insn_div_rd_addr), .spec_rd_wdata(spec_insn_div_rd_wdata), .spec_pc_wdata(spec_insn_div_pc_wdata), .spec_mem_addr(spec_insn_div_mem_addr), .spec_mem_rmask(spec_insn_div_mem_rmask), .spec_mem_wmask(spec_insn_div_mem_wmask), .spec_mem_wdata(spec_insn_div_mem_wdata) ); wire spec_insn_divu_valid; wire spec_insn_divu_trap; wire [ 4 : 0] spec_insn_divu_rs1_addr; wire [ 4 : 0] spec_insn_divu_rs2_addr; wire [ 4 : 0] spec_insn_divu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_csr_misa_rmask; `endif rvfi_insn_divu insn_divu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_divu_csr_misa_rmask), `endif .spec_valid(spec_insn_divu_valid), .spec_trap(spec_insn_divu_trap), .spec_rs1_addr(spec_insn_divu_rs1_addr), .spec_rs2_addr(spec_insn_divu_rs2_addr), .spec_rd_addr(spec_insn_divu_rd_addr), .spec_rd_wdata(spec_insn_divu_rd_wdata), .spec_pc_wdata(spec_insn_divu_pc_wdata), .spec_mem_addr(spec_insn_divu_mem_addr), .spec_mem_rmask(spec_insn_divu_mem_rmask), .spec_mem_wmask(spec_insn_divu_mem_wmask), .spec_mem_wdata(spec_insn_divu_mem_wdata) ); wire spec_insn_divuw_valid; wire spec_insn_divuw_trap; wire [ 4 : 0] spec_insn_divuw_rs1_addr; wire [ 4 : 0] spec_insn_divuw_rs2_addr; wire [ 4 : 0] spec_insn_divuw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divuw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divuw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divuw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divuw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divuw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divuw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divuw_csr_misa_rmask; `endif rvfi_insn_divuw insn_divuw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_divuw_csr_misa_rmask), `endif .spec_valid(spec_insn_divuw_valid), .spec_trap(spec_insn_divuw_trap), .spec_rs1_addr(spec_insn_divuw_rs1_addr), .spec_rs2_addr(spec_insn_divuw_rs2_addr), .spec_rd_addr(spec_insn_divuw_rd_addr), .spec_rd_wdata(spec_insn_divuw_rd_wdata), .spec_pc_wdata(spec_insn_divuw_pc_wdata), .spec_mem_addr(spec_insn_divuw_mem_addr), .spec_mem_rmask(spec_insn_divuw_mem_rmask), .spec_mem_wmask(spec_insn_divuw_mem_wmask), .spec_mem_wdata(spec_insn_divuw_mem_wdata) ); wire spec_insn_divw_valid; wire spec_insn_divw_trap; wire [ 4 : 0] spec_insn_divw_rs1_addr; wire [ 4 : 0] spec_insn_divw_rs2_addr; wire [ 4 : 0] spec_insn_divw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divw_csr_misa_rmask; `endif rvfi_insn_divw insn_divw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_divw_csr_misa_rmask), `endif .spec_valid(spec_insn_divw_valid), .spec_trap(spec_insn_divw_trap), .spec_rs1_addr(spec_insn_divw_rs1_addr), .spec_rs2_addr(spec_insn_divw_rs2_addr), .spec_rd_addr(spec_insn_divw_rd_addr), .spec_rd_wdata(spec_insn_divw_rd_wdata), .spec_pc_wdata(spec_insn_divw_pc_wdata), .spec_mem_addr(spec_insn_divw_mem_addr), .spec_mem_rmask(spec_insn_divw_mem_rmask), .spec_mem_wmask(spec_insn_divw_mem_wmask), .spec_mem_wdata(spec_insn_divw_mem_wdata) ); wire spec_insn_jal_valid; wire spec_insn_jal_trap; wire [ 4 : 0] spec_insn_jal_rs1_addr; wire [ 4 : 0] spec_insn_jal_rs2_addr; wire [ 4 : 0] spec_insn_jal_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; `endif rvfi_insn_jal insn_jal ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), `endif .spec_valid(spec_insn_jal_valid), .spec_trap(spec_insn_jal_trap), .spec_rs1_addr(spec_insn_jal_rs1_addr), .spec_rs2_addr(spec_insn_jal_rs2_addr), .spec_rd_addr(spec_insn_jal_rd_addr), .spec_rd_wdata(spec_insn_jal_rd_wdata), .spec_pc_wdata(spec_insn_jal_pc_wdata), .spec_mem_addr(spec_insn_jal_mem_addr), .spec_mem_rmask(spec_insn_jal_mem_rmask), .spec_mem_wmask(spec_insn_jal_mem_wmask), .spec_mem_wdata(spec_insn_jal_mem_wdata) ); wire spec_insn_jalr_valid; wire spec_insn_jalr_trap; wire [ 4 : 0] spec_insn_jalr_rs1_addr; wire [ 4 : 0] spec_insn_jalr_rs2_addr; wire [ 4 : 0] spec_insn_jalr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; `endif rvfi_insn_jalr insn_jalr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), `endif .spec_valid(spec_insn_jalr_valid), .spec_trap(spec_insn_jalr_trap), .spec_rs1_addr(spec_insn_jalr_rs1_addr), .spec_rs2_addr(spec_insn_jalr_rs2_addr), .spec_rd_addr(spec_insn_jalr_rd_addr), .spec_rd_wdata(spec_insn_jalr_rd_wdata), .spec_pc_wdata(spec_insn_jalr_pc_wdata), .spec_mem_addr(spec_insn_jalr_mem_addr), .spec_mem_rmask(spec_insn_jalr_mem_rmask), .spec_mem_wmask(spec_insn_jalr_mem_wmask), .spec_mem_wdata(spec_insn_jalr_mem_wdata) ); wire spec_insn_lb_valid; wire spec_insn_lb_trap; wire [ 4 : 0] spec_insn_lb_rs1_addr; wire [ 4 : 0] spec_insn_lb_rs2_addr; wire [ 4 : 0] spec_insn_lb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; `endif rvfi_insn_lb insn_lb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), `endif .spec_valid(spec_insn_lb_valid), .spec_trap(spec_insn_lb_trap), .spec_rs1_addr(spec_insn_lb_rs1_addr), .spec_rs2_addr(spec_insn_lb_rs2_addr), .spec_rd_addr(spec_insn_lb_rd_addr), .spec_rd_wdata(spec_insn_lb_rd_wdata), .spec_pc_wdata(spec_insn_lb_pc_wdata), .spec_mem_addr(spec_insn_lb_mem_addr), .spec_mem_rmask(spec_insn_lb_mem_rmask), .spec_mem_wmask(spec_insn_lb_mem_wmask), .spec_mem_wdata(spec_insn_lb_mem_wdata) ); wire spec_insn_lbu_valid; wire spec_insn_lbu_trap; wire [ 4 : 0] spec_insn_lbu_rs1_addr; wire [ 4 : 0] spec_insn_lbu_rs2_addr; wire [ 4 : 0] spec_insn_lbu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; `endif rvfi_insn_lbu insn_lbu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), `endif .spec_valid(spec_insn_lbu_valid), .spec_trap(spec_insn_lbu_trap), .spec_rs1_addr(spec_insn_lbu_rs1_addr), .spec_rs2_addr(spec_insn_lbu_rs2_addr), .spec_rd_addr(spec_insn_lbu_rd_addr), .spec_rd_wdata(spec_insn_lbu_rd_wdata), .spec_pc_wdata(spec_insn_lbu_pc_wdata), .spec_mem_addr(spec_insn_lbu_mem_addr), .spec_mem_rmask(spec_insn_lbu_mem_rmask), .spec_mem_wmask(spec_insn_lbu_mem_wmask), .spec_mem_wdata(spec_insn_lbu_mem_wdata) ); wire spec_insn_ld_valid; wire spec_insn_ld_trap; wire [ 4 : 0] spec_insn_ld_rs1_addr; wire [ 4 : 0] spec_insn_ld_rs2_addr; wire [ 4 : 0] spec_insn_ld_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_csr_misa_rmask; `endif rvfi_insn_ld insn_ld ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_ld_csr_misa_rmask), `endif .spec_valid(spec_insn_ld_valid), .spec_trap(spec_insn_ld_trap), .spec_rs1_addr(spec_insn_ld_rs1_addr), .spec_rs2_addr(spec_insn_ld_rs2_addr), .spec_rd_addr(spec_insn_ld_rd_addr), .spec_rd_wdata(spec_insn_ld_rd_wdata), .spec_pc_wdata(spec_insn_ld_pc_wdata), .spec_mem_addr(spec_insn_ld_mem_addr), .spec_mem_rmask(spec_insn_ld_mem_rmask), .spec_mem_wmask(spec_insn_ld_mem_wmask), .spec_mem_wdata(spec_insn_ld_mem_wdata) ); wire spec_insn_lh_valid; wire spec_insn_lh_trap; wire [ 4 : 0] spec_insn_lh_rs1_addr; wire [ 4 : 0] spec_insn_lh_rs2_addr; wire [ 4 : 0] spec_insn_lh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; `endif rvfi_insn_lh insn_lh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), `endif .spec_valid(spec_insn_lh_valid), .spec_trap(spec_insn_lh_trap), .spec_rs1_addr(spec_insn_lh_rs1_addr), .spec_rs2_addr(spec_insn_lh_rs2_addr), .spec_rd_addr(spec_insn_lh_rd_addr), .spec_rd_wdata(spec_insn_lh_rd_wdata), .spec_pc_wdata(spec_insn_lh_pc_wdata), .spec_mem_addr(spec_insn_lh_mem_addr), .spec_mem_rmask(spec_insn_lh_mem_rmask), .spec_mem_wmask(spec_insn_lh_mem_wmask), .spec_mem_wdata(spec_insn_lh_mem_wdata) ); wire spec_insn_lhu_valid; wire spec_insn_lhu_trap; wire [ 4 : 0] spec_insn_lhu_rs1_addr; wire [ 4 : 0] spec_insn_lhu_rs2_addr; wire [ 4 : 0] spec_insn_lhu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; `endif rvfi_insn_lhu insn_lhu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), `endif .spec_valid(spec_insn_lhu_valid), .spec_trap(spec_insn_lhu_trap), .spec_rs1_addr(spec_insn_lhu_rs1_addr), .spec_rs2_addr(spec_insn_lhu_rs2_addr), .spec_rd_addr(spec_insn_lhu_rd_addr), .spec_rd_wdata(spec_insn_lhu_rd_wdata), .spec_pc_wdata(spec_insn_lhu_pc_wdata), .spec_mem_addr(spec_insn_lhu_mem_addr), .spec_mem_rmask(spec_insn_lhu_mem_rmask), .spec_mem_wmask(spec_insn_lhu_mem_wmask), .spec_mem_wdata(spec_insn_lhu_mem_wdata) ); wire spec_insn_lui_valid; wire spec_insn_lui_trap; wire [ 4 : 0] spec_insn_lui_rs1_addr; wire [ 4 : 0] spec_insn_lui_rs2_addr; wire [ 4 : 0] spec_insn_lui_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; `endif rvfi_insn_lui insn_lui ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), `endif .spec_valid(spec_insn_lui_valid), .spec_trap(spec_insn_lui_trap), .spec_rs1_addr(spec_insn_lui_rs1_addr), .spec_rs2_addr(spec_insn_lui_rs2_addr), .spec_rd_addr(spec_insn_lui_rd_addr), .spec_rd_wdata(spec_insn_lui_rd_wdata), .spec_pc_wdata(spec_insn_lui_pc_wdata), .spec_mem_addr(spec_insn_lui_mem_addr), .spec_mem_rmask(spec_insn_lui_mem_rmask), .spec_mem_wmask(spec_insn_lui_mem_wmask), .spec_mem_wdata(spec_insn_lui_mem_wdata) ); wire spec_insn_lw_valid; wire spec_insn_lw_trap; wire [ 4 : 0] spec_insn_lw_rs1_addr; wire [ 4 : 0] spec_insn_lw_rs2_addr; wire [ 4 : 0] spec_insn_lw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; `endif rvfi_insn_lw insn_lw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), `endif .spec_valid(spec_insn_lw_valid), .spec_trap(spec_insn_lw_trap), .spec_rs1_addr(spec_insn_lw_rs1_addr), .spec_rs2_addr(spec_insn_lw_rs2_addr), .spec_rd_addr(spec_insn_lw_rd_addr), .spec_rd_wdata(spec_insn_lw_rd_wdata), .spec_pc_wdata(spec_insn_lw_pc_wdata), .spec_mem_addr(spec_insn_lw_mem_addr), .spec_mem_rmask(spec_insn_lw_mem_rmask), .spec_mem_wmask(spec_insn_lw_mem_wmask), .spec_mem_wdata(spec_insn_lw_mem_wdata) ); wire spec_insn_lwu_valid; wire spec_insn_lwu_trap; wire [ 4 : 0] spec_insn_lwu_rs1_addr; wire [ 4 : 0] spec_insn_lwu_rs2_addr; wire [ 4 : 0] spec_insn_lwu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_csr_misa_rmask; `endif rvfi_insn_lwu insn_lwu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lwu_csr_misa_rmask), `endif .spec_valid(spec_insn_lwu_valid), .spec_trap(spec_insn_lwu_trap), .spec_rs1_addr(spec_insn_lwu_rs1_addr), .spec_rs2_addr(spec_insn_lwu_rs2_addr), .spec_rd_addr(spec_insn_lwu_rd_addr), .spec_rd_wdata(spec_insn_lwu_rd_wdata), .spec_pc_wdata(spec_insn_lwu_pc_wdata), .spec_mem_addr(spec_insn_lwu_mem_addr), .spec_mem_rmask(spec_insn_lwu_mem_rmask), .spec_mem_wmask(spec_insn_lwu_mem_wmask), .spec_mem_wdata(spec_insn_lwu_mem_wdata) ); wire spec_insn_mul_valid; wire spec_insn_mul_trap; wire [ 4 : 0] spec_insn_mul_rs1_addr; wire [ 4 : 0] spec_insn_mul_rs2_addr; wire [ 4 : 0] spec_insn_mul_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_csr_misa_rmask; `endif rvfi_insn_mul insn_mul ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mul_csr_misa_rmask), `endif .spec_valid(spec_insn_mul_valid), .spec_trap(spec_insn_mul_trap), .spec_rs1_addr(spec_insn_mul_rs1_addr), .spec_rs2_addr(spec_insn_mul_rs2_addr), .spec_rd_addr(spec_insn_mul_rd_addr), .spec_rd_wdata(spec_insn_mul_rd_wdata), .spec_pc_wdata(spec_insn_mul_pc_wdata), .spec_mem_addr(spec_insn_mul_mem_addr), .spec_mem_rmask(spec_insn_mul_mem_rmask), .spec_mem_wmask(spec_insn_mul_mem_wmask), .spec_mem_wdata(spec_insn_mul_mem_wdata) ); wire spec_insn_mulh_valid; wire spec_insn_mulh_trap; wire [ 4 : 0] spec_insn_mulh_rs1_addr; wire [ 4 : 0] spec_insn_mulh_rs2_addr; wire [ 4 : 0] spec_insn_mulh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_csr_misa_rmask; `endif rvfi_insn_mulh insn_mulh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mulh_csr_misa_rmask), `endif .spec_valid(spec_insn_mulh_valid), .spec_trap(spec_insn_mulh_trap), .spec_rs1_addr(spec_insn_mulh_rs1_addr), .spec_rs2_addr(spec_insn_mulh_rs2_addr), .spec_rd_addr(spec_insn_mulh_rd_addr), .spec_rd_wdata(spec_insn_mulh_rd_wdata), .spec_pc_wdata(spec_insn_mulh_pc_wdata), .spec_mem_addr(spec_insn_mulh_mem_addr), .spec_mem_rmask(spec_insn_mulh_mem_rmask), .spec_mem_wmask(spec_insn_mulh_mem_wmask), .spec_mem_wdata(spec_insn_mulh_mem_wdata) ); wire spec_insn_mulhsu_valid; wire spec_insn_mulhsu_trap; wire [ 4 : 0] spec_insn_mulhsu_rs1_addr; wire [ 4 : 0] spec_insn_mulhsu_rs2_addr; wire [ 4 : 0] spec_insn_mulhsu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_csr_misa_rmask; `endif rvfi_insn_mulhsu insn_mulhsu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mulhsu_csr_misa_rmask), `endif .spec_valid(spec_insn_mulhsu_valid), .spec_trap(spec_insn_mulhsu_trap), .spec_rs1_addr(spec_insn_mulhsu_rs1_addr), .spec_rs2_addr(spec_insn_mulhsu_rs2_addr), .spec_rd_addr(spec_insn_mulhsu_rd_addr), .spec_rd_wdata(spec_insn_mulhsu_rd_wdata), .spec_pc_wdata(spec_insn_mulhsu_pc_wdata), .spec_mem_addr(spec_insn_mulhsu_mem_addr), .spec_mem_rmask(spec_insn_mulhsu_mem_rmask), .spec_mem_wmask(spec_insn_mulhsu_mem_wmask), .spec_mem_wdata(spec_insn_mulhsu_mem_wdata) ); wire spec_insn_mulhu_valid; wire spec_insn_mulhu_trap; wire [ 4 : 0] spec_insn_mulhu_rs1_addr; wire [ 4 : 0] spec_insn_mulhu_rs2_addr; wire [ 4 : 0] spec_insn_mulhu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_csr_misa_rmask; `endif rvfi_insn_mulhu insn_mulhu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mulhu_csr_misa_rmask), `endif .spec_valid(spec_insn_mulhu_valid), .spec_trap(spec_insn_mulhu_trap), .spec_rs1_addr(spec_insn_mulhu_rs1_addr), .spec_rs2_addr(spec_insn_mulhu_rs2_addr), .spec_rd_addr(spec_insn_mulhu_rd_addr), .spec_rd_wdata(spec_insn_mulhu_rd_wdata), .spec_pc_wdata(spec_insn_mulhu_pc_wdata), .spec_mem_addr(spec_insn_mulhu_mem_addr), .spec_mem_rmask(spec_insn_mulhu_mem_rmask), .spec_mem_wmask(spec_insn_mulhu_mem_wmask), .spec_mem_wdata(spec_insn_mulhu_mem_wdata) ); wire spec_insn_mulw_valid; wire spec_insn_mulw_trap; wire [ 4 : 0] spec_insn_mulw_rs1_addr; wire [ 4 : 0] spec_insn_mulw_rs2_addr; wire [ 4 : 0] spec_insn_mulw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulw_csr_misa_rmask; `endif rvfi_insn_mulw insn_mulw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mulw_csr_misa_rmask), `endif .spec_valid(spec_insn_mulw_valid), .spec_trap(spec_insn_mulw_trap), .spec_rs1_addr(spec_insn_mulw_rs1_addr), .spec_rs2_addr(spec_insn_mulw_rs2_addr), .spec_rd_addr(spec_insn_mulw_rd_addr), .spec_rd_wdata(spec_insn_mulw_rd_wdata), .spec_pc_wdata(spec_insn_mulw_pc_wdata), .spec_mem_addr(spec_insn_mulw_mem_addr), .spec_mem_rmask(spec_insn_mulw_mem_rmask), .spec_mem_wmask(spec_insn_mulw_mem_wmask), .spec_mem_wdata(spec_insn_mulw_mem_wdata) ); wire spec_insn_or_valid; wire spec_insn_or_trap; wire [ 4 : 0] spec_insn_or_rs1_addr; wire [ 4 : 0] spec_insn_or_rs2_addr; wire [ 4 : 0] spec_insn_or_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; `endif rvfi_insn_or insn_or ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), `endif .spec_valid(spec_insn_or_valid), .spec_trap(spec_insn_or_trap), .spec_rs1_addr(spec_insn_or_rs1_addr), .spec_rs2_addr(spec_insn_or_rs2_addr), .spec_rd_addr(spec_insn_or_rd_addr), .spec_rd_wdata(spec_insn_or_rd_wdata), .spec_pc_wdata(spec_insn_or_pc_wdata), .spec_mem_addr(spec_insn_or_mem_addr), .spec_mem_rmask(spec_insn_or_mem_rmask), .spec_mem_wmask(spec_insn_or_mem_wmask), .spec_mem_wdata(spec_insn_or_mem_wdata) ); wire spec_insn_ori_valid; wire spec_insn_ori_trap; wire [ 4 : 0] spec_insn_ori_rs1_addr; wire [ 4 : 0] spec_insn_ori_rs2_addr; wire [ 4 : 0] spec_insn_ori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; `endif rvfi_insn_ori insn_ori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), `endif .spec_valid(spec_insn_ori_valid), .spec_trap(spec_insn_ori_trap), .spec_rs1_addr(spec_insn_ori_rs1_addr), .spec_rs2_addr(spec_insn_ori_rs2_addr), .spec_rd_addr(spec_insn_ori_rd_addr), .spec_rd_wdata(spec_insn_ori_rd_wdata), .spec_pc_wdata(spec_insn_ori_pc_wdata), .spec_mem_addr(spec_insn_ori_mem_addr), .spec_mem_rmask(spec_insn_ori_mem_rmask), .spec_mem_wmask(spec_insn_ori_mem_wmask), .spec_mem_wdata(spec_insn_ori_mem_wdata) ); wire spec_insn_rem_valid; wire spec_insn_rem_trap; wire [ 4 : 0] spec_insn_rem_rs1_addr; wire [ 4 : 0] spec_insn_rem_rs2_addr; wire [ 4 : 0] spec_insn_rem_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_csr_misa_rmask; `endif rvfi_insn_rem insn_rem ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_rem_csr_misa_rmask), `endif .spec_valid(spec_insn_rem_valid), .spec_trap(spec_insn_rem_trap), .spec_rs1_addr(spec_insn_rem_rs1_addr), .spec_rs2_addr(spec_insn_rem_rs2_addr), .spec_rd_addr(spec_insn_rem_rd_addr), .spec_rd_wdata(spec_insn_rem_rd_wdata), .spec_pc_wdata(spec_insn_rem_pc_wdata), .spec_mem_addr(spec_insn_rem_mem_addr), .spec_mem_rmask(spec_insn_rem_mem_rmask), .spec_mem_wmask(spec_insn_rem_mem_wmask), .spec_mem_wdata(spec_insn_rem_mem_wdata) ); wire spec_insn_remu_valid; wire spec_insn_remu_trap; wire [ 4 : 0] spec_insn_remu_rs1_addr; wire [ 4 : 0] spec_insn_remu_rs2_addr; wire [ 4 : 0] spec_insn_remu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_csr_misa_rmask; `endif rvfi_insn_remu insn_remu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_remu_csr_misa_rmask), `endif .spec_valid(spec_insn_remu_valid), .spec_trap(spec_insn_remu_trap), .spec_rs1_addr(spec_insn_remu_rs1_addr), .spec_rs2_addr(spec_insn_remu_rs2_addr), .spec_rd_addr(spec_insn_remu_rd_addr), .spec_rd_wdata(spec_insn_remu_rd_wdata), .spec_pc_wdata(spec_insn_remu_pc_wdata), .spec_mem_addr(spec_insn_remu_mem_addr), .spec_mem_rmask(spec_insn_remu_mem_rmask), .spec_mem_wmask(spec_insn_remu_mem_wmask), .spec_mem_wdata(spec_insn_remu_mem_wdata) ); wire spec_insn_remuw_valid; wire spec_insn_remuw_trap; wire [ 4 : 0] spec_insn_remuw_rs1_addr; wire [ 4 : 0] spec_insn_remuw_rs2_addr; wire [ 4 : 0] spec_insn_remuw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remuw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remuw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remuw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remuw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remuw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remuw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remuw_csr_misa_rmask; `endif rvfi_insn_remuw insn_remuw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_remuw_csr_misa_rmask), `endif .spec_valid(spec_insn_remuw_valid), .spec_trap(spec_insn_remuw_trap), .spec_rs1_addr(spec_insn_remuw_rs1_addr), .spec_rs2_addr(spec_insn_remuw_rs2_addr), .spec_rd_addr(spec_insn_remuw_rd_addr), .spec_rd_wdata(spec_insn_remuw_rd_wdata), .spec_pc_wdata(spec_insn_remuw_pc_wdata), .spec_mem_addr(spec_insn_remuw_mem_addr), .spec_mem_rmask(spec_insn_remuw_mem_rmask), .spec_mem_wmask(spec_insn_remuw_mem_wmask), .spec_mem_wdata(spec_insn_remuw_mem_wdata) ); wire spec_insn_remw_valid; wire spec_insn_remw_trap; wire [ 4 : 0] spec_insn_remw_rs1_addr; wire [ 4 : 0] spec_insn_remw_rs2_addr; wire [ 4 : 0] spec_insn_remw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remw_csr_misa_rmask; `endif rvfi_insn_remw insn_remw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_remw_csr_misa_rmask), `endif .spec_valid(spec_insn_remw_valid), .spec_trap(spec_insn_remw_trap), .spec_rs1_addr(spec_insn_remw_rs1_addr), .spec_rs2_addr(spec_insn_remw_rs2_addr), .spec_rd_addr(spec_insn_remw_rd_addr), .spec_rd_wdata(spec_insn_remw_rd_wdata), .spec_pc_wdata(spec_insn_remw_pc_wdata), .spec_mem_addr(spec_insn_remw_mem_addr), .spec_mem_rmask(spec_insn_remw_mem_rmask), .spec_mem_wmask(spec_insn_remw_mem_wmask), .spec_mem_wdata(spec_insn_remw_mem_wdata) ); wire spec_insn_sb_valid; wire spec_insn_sb_trap; wire [ 4 : 0] spec_insn_sb_rs1_addr; wire [ 4 : 0] spec_insn_sb_rs2_addr; wire [ 4 : 0] spec_insn_sb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; `endif rvfi_insn_sb insn_sb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), `endif .spec_valid(spec_insn_sb_valid), .spec_trap(spec_insn_sb_trap), .spec_rs1_addr(spec_insn_sb_rs1_addr), .spec_rs2_addr(spec_insn_sb_rs2_addr), .spec_rd_addr(spec_insn_sb_rd_addr), .spec_rd_wdata(spec_insn_sb_rd_wdata), .spec_pc_wdata(spec_insn_sb_pc_wdata), .spec_mem_addr(spec_insn_sb_mem_addr), .spec_mem_rmask(spec_insn_sb_mem_rmask), .spec_mem_wmask(spec_insn_sb_mem_wmask), .spec_mem_wdata(spec_insn_sb_mem_wdata) ); wire spec_insn_sd_valid; wire spec_insn_sd_trap; wire [ 4 : 0] spec_insn_sd_rs1_addr; wire [ 4 : 0] spec_insn_sd_rs2_addr; wire [ 4 : 0] spec_insn_sd_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_csr_misa_rmask; `endif rvfi_insn_sd insn_sd ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sd_csr_misa_rmask), `endif .spec_valid(spec_insn_sd_valid), .spec_trap(spec_insn_sd_trap), .spec_rs1_addr(spec_insn_sd_rs1_addr), .spec_rs2_addr(spec_insn_sd_rs2_addr), .spec_rd_addr(spec_insn_sd_rd_addr), .spec_rd_wdata(spec_insn_sd_rd_wdata), .spec_pc_wdata(spec_insn_sd_pc_wdata), .spec_mem_addr(spec_insn_sd_mem_addr), .spec_mem_rmask(spec_insn_sd_mem_rmask), .spec_mem_wmask(spec_insn_sd_mem_wmask), .spec_mem_wdata(spec_insn_sd_mem_wdata) ); wire spec_insn_sh_valid; wire spec_insn_sh_trap; wire [ 4 : 0] spec_insn_sh_rs1_addr; wire [ 4 : 0] spec_insn_sh_rs2_addr; wire [ 4 : 0] spec_insn_sh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; `endif rvfi_insn_sh insn_sh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), `endif .spec_valid(spec_insn_sh_valid), .spec_trap(spec_insn_sh_trap), .spec_rs1_addr(spec_insn_sh_rs1_addr), .spec_rs2_addr(spec_insn_sh_rs2_addr), .spec_rd_addr(spec_insn_sh_rd_addr), .spec_rd_wdata(spec_insn_sh_rd_wdata), .spec_pc_wdata(spec_insn_sh_pc_wdata), .spec_mem_addr(spec_insn_sh_mem_addr), .spec_mem_rmask(spec_insn_sh_mem_rmask), .spec_mem_wmask(spec_insn_sh_mem_wmask), .spec_mem_wdata(spec_insn_sh_mem_wdata) ); wire spec_insn_sll_valid; wire spec_insn_sll_trap; wire [ 4 : 0] spec_insn_sll_rs1_addr; wire [ 4 : 0] spec_insn_sll_rs2_addr; wire [ 4 : 0] spec_insn_sll_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; `endif rvfi_insn_sll insn_sll ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), `endif .spec_valid(spec_insn_sll_valid), .spec_trap(spec_insn_sll_trap), .spec_rs1_addr(spec_insn_sll_rs1_addr), .spec_rs2_addr(spec_insn_sll_rs2_addr), .spec_rd_addr(spec_insn_sll_rd_addr), .spec_rd_wdata(spec_insn_sll_rd_wdata), .spec_pc_wdata(spec_insn_sll_pc_wdata), .spec_mem_addr(spec_insn_sll_mem_addr), .spec_mem_rmask(spec_insn_sll_mem_rmask), .spec_mem_wmask(spec_insn_sll_mem_wmask), .spec_mem_wdata(spec_insn_sll_mem_wdata) ); wire spec_insn_slli_valid; wire spec_insn_slli_trap; wire [ 4 : 0] spec_insn_slli_rs1_addr; wire [ 4 : 0] spec_insn_slli_rs2_addr; wire [ 4 : 0] spec_insn_slli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; `endif rvfi_insn_slli insn_slli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), `endif .spec_valid(spec_insn_slli_valid), .spec_trap(spec_insn_slli_trap), .spec_rs1_addr(spec_insn_slli_rs1_addr), .spec_rs2_addr(spec_insn_slli_rs2_addr), .spec_rd_addr(spec_insn_slli_rd_addr), .spec_rd_wdata(spec_insn_slli_rd_wdata), .spec_pc_wdata(spec_insn_slli_pc_wdata), .spec_mem_addr(spec_insn_slli_mem_addr), .spec_mem_rmask(spec_insn_slli_mem_rmask), .spec_mem_wmask(spec_insn_slli_mem_wmask), .spec_mem_wdata(spec_insn_slli_mem_wdata) ); wire spec_insn_slliw_valid; wire spec_insn_slliw_trap; wire [ 4 : 0] spec_insn_slliw_rs1_addr; wire [ 4 : 0] spec_insn_slliw_rs2_addr; wire [ 4 : 0] spec_insn_slliw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_csr_misa_rmask; `endif rvfi_insn_slliw insn_slliw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slliw_csr_misa_rmask), `endif .spec_valid(spec_insn_slliw_valid), .spec_trap(spec_insn_slliw_trap), .spec_rs1_addr(spec_insn_slliw_rs1_addr), .spec_rs2_addr(spec_insn_slliw_rs2_addr), .spec_rd_addr(spec_insn_slliw_rd_addr), .spec_rd_wdata(spec_insn_slliw_rd_wdata), .spec_pc_wdata(spec_insn_slliw_pc_wdata), .spec_mem_addr(spec_insn_slliw_mem_addr), .spec_mem_rmask(spec_insn_slliw_mem_rmask), .spec_mem_wmask(spec_insn_slliw_mem_wmask), .spec_mem_wdata(spec_insn_slliw_mem_wdata) ); wire spec_insn_sllw_valid; wire spec_insn_sllw_trap; wire [ 4 : 0] spec_insn_sllw_rs1_addr; wire [ 4 : 0] spec_insn_sllw_rs2_addr; wire [ 4 : 0] spec_insn_sllw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_csr_misa_rmask; `endif rvfi_insn_sllw insn_sllw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sllw_csr_misa_rmask), `endif .spec_valid(spec_insn_sllw_valid), .spec_trap(spec_insn_sllw_trap), .spec_rs1_addr(spec_insn_sllw_rs1_addr), .spec_rs2_addr(spec_insn_sllw_rs2_addr), .spec_rd_addr(spec_insn_sllw_rd_addr), .spec_rd_wdata(spec_insn_sllw_rd_wdata), .spec_pc_wdata(spec_insn_sllw_pc_wdata), .spec_mem_addr(spec_insn_sllw_mem_addr), .spec_mem_rmask(spec_insn_sllw_mem_rmask), .spec_mem_wmask(spec_insn_sllw_mem_wmask), .spec_mem_wdata(spec_insn_sllw_mem_wdata) ); wire spec_insn_slt_valid; wire spec_insn_slt_trap; wire [ 4 : 0] spec_insn_slt_rs1_addr; wire [ 4 : 0] spec_insn_slt_rs2_addr; wire [ 4 : 0] spec_insn_slt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; `endif rvfi_insn_slt insn_slt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), `endif .spec_valid(spec_insn_slt_valid), .spec_trap(spec_insn_slt_trap), .spec_rs1_addr(spec_insn_slt_rs1_addr), .spec_rs2_addr(spec_insn_slt_rs2_addr), .spec_rd_addr(spec_insn_slt_rd_addr), .spec_rd_wdata(spec_insn_slt_rd_wdata), .spec_pc_wdata(spec_insn_slt_pc_wdata), .spec_mem_addr(spec_insn_slt_mem_addr), .spec_mem_rmask(spec_insn_slt_mem_rmask), .spec_mem_wmask(spec_insn_slt_mem_wmask), .spec_mem_wdata(spec_insn_slt_mem_wdata) ); wire spec_insn_slti_valid; wire spec_insn_slti_trap; wire [ 4 : 0] spec_insn_slti_rs1_addr; wire [ 4 : 0] spec_insn_slti_rs2_addr; wire [ 4 : 0] spec_insn_slti_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; `endif rvfi_insn_slti insn_slti ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), `endif .spec_valid(spec_insn_slti_valid), .spec_trap(spec_insn_slti_trap), .spec_rs1_addr(spec_insn_slti_rs1_addr), .spec_rs2_addr(spec_insn_slti_rs2_addr), .spec_rd_addr(spec_insn_slti_rd_addr), .spec_rd_wdata(spec_insn_slti_rd_wdata), .spec_pc_wdata(spec_insn_slti_pc_wdata), .spec_mem_addr(spec_insn_slti_mem_addr), .spec_mem_rmask(spec_insn_slti_mem_rmask), .spec_mem_wmask(spec_insn_slti_mem_wmask), .spec_mem_wdata(spec_insn_slti_mem_wdata) ); wire spec_insn_sltiu_valid; wire spec_insn_sltiu_trap; wire [ 4 : 0] spec_insn_sltiu_rs1_addr; wire [ 4 : 0] spec_insn_sltiu_rs2_addr; wire [ 4 : 0] spec_insn_sltiu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; `endif rvfi_insn_sltiu insn_sltiu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltiu_valid), .spec_trap(spec_insn_sltiu_trap), .spec_rs1_addr(spec_insn_sltiu_rs1_addr), .spec_rs2_addr(spec_insn_sltiu_rs2_addr), .spec_rd_addr(spec_insn_sltiu_rd_addr), .spec_rd_wdata(spec_insn_sltiu_rd_wdata), .spec_pc_wdata(spec_insn_sltiu_pc_wdata), .spec_mem_addr(spec_insn_sltiu_mem_addr), .spec_mem_rmask(spec_insn_sltiu_mem_rmask), .spec_mem_wmask(spec_insn_sltiu_mem_wmask), .spec_mem_wdata(spec_insn_sltiu_mem_wdata) ); wire spec_insn_sltu_valid; wire spec_insn_sltu_trap; wire [ 4 : 0] spec_insn_sltu_rs1_addr; wire [ 4 : 0] spec_insn_sltu_rs2_addr; wire [ 4 : 0] spec_insn_sltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; `endif rvfi_insn_sltu insn_sltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltu_valid), .spec_trap(spec_insn_sltu_trap), .spec_rs1_addr(spec_insn_sltu_rs1_addr), .spec_rs2_addr(spec_insn_sltu_rs2_addr), .spec_rd_addr(spec_insn_sltu_rd_addr), .spec_rd_wdata(spec_insn_sltu_rd_wdata), .spec_pc_wdata(spec_insn_sltu_pc_wdata), .spec_mem_addr(spec_insn_sltu_mem_addr), .spec_mem_rmask(spec_insn_sltu_mem_rmask), .spec_mem_wmask(spec_insn_sltu_mem_wmask), .spec_mem_wdata(spec_insn_sltu_mem_wdata) ); wire spec_insn_sra_valid; wire spec_insn_sra_trap; wire [ 4 : 0] spec_insn_sra_rs1_addr; wire [ 4 : 0] spec_insn_sra_rs2_addr; wire [ 4 : 0] spec_insn_sra_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; `endif rvfi_insn_sra insn_sra ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), `endif .spec_valid(spec_insn_sra_valid), .spec_trap(spec_insn_sra_trap), .spec_rs1_addr(spec_insn_sra_rs1_addr), .spec_rs2_addr(spec_insn_sra_rs2_addr), .spec_rd_addr(spec_insn_sra_rd_addr), .spec_rd_wdata(spec_insn_sra_rd_wdata), .spec_pc_wdata(spec_insn_sra_pc_wdata), .spec_mem_addr(spec_insn_sra_mem_addr), .spec_mem_rmask(spec_insn_sra_mem_rmask), .spec_mem_wmask(spec_insn_sra_mem_wmask), .spec_mem_wdata(spec_insn_sra_mem_wdata) ); wire spec_insn_srai_valid; wire spec_insn_srai_trap; wire [ 4 : 0] spec_insn_srai_rs1_addr; wire [ 4 : 0] spec_insn_srai_rs2_addr; wire [ 4 : 0] spec_insn_srai_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; `endif rvfi_insn_srai insn_srai ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), `endif .spec_valid(spec_insn_srai_valid), .spec_trap(spec_insn_srai_trap), .spec_rs1_addr(spec_insn_srai_rs1_addr), .spec_rs2_addr(spec_insn_srai_rs2_addr), .spec_rd_addr(spec_insn_srai_rd_addr), .spec_rd_wdata(spec_insn_srai_rd_wdata), .spec_pc_wdata(spec_insn_srai_pc_wdata), .spec_mem_addr(spec_insn_srai_mem_addr), .spec_mem_rmask(spec_insn_srai_mem_rmask), .spec_mem_wmask(spec_insn_srai_mem_wmask), .spec_mem_wdata(spec_insn_srai_mem_wdata) ); wire spec_insn_sraiw_valid; wire spec_insn_sraiw_trap; wire [ 4 : 0] spec_insn_sraiw_rs1_addr; wire [ 4 : 0] spec_insn_sraiw_rs2_addr; wire [ 4 : 0] spec_insn_sraiw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_csr_misa_rmask; `endif rvfi_insn_sraiw insn_sraiw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sraiw_csr_misa_rmask), `endif .spec_valid(spec_insn_sraiw_valid), .spec_trap(spec_insn_sraiw_trap), .spec_rs1_addr(spec_insn_sraiw_rs1_addr), .spec_rs2_addr(spec_insn_sraiw_rs2_addr), .spec_rd_addr(spec_insn_sraiw_rd_addr), .spec_rd_wdata(spec_insn_sraiw_rd_wdata), .spec_pc_wdata(spec_insn_sraiw_pc_wdata), .spec_mem_addr(spec_insn_sraiw_mem_addr), .spec_mem_rmask(spec_insn_sraiw_mem_rmask), .spec_mem_wmask(spec_insn_sraiw_mem_wmask), .spec_mem_wdata(spec_insn_sraiw_mem_wdata) ); wire spec_insn_sraw_valid; wire spec_insn_sraw_trap; wire [ 4 : 0] spec_insn_sraw_rs1_addr; wire [ 4 : 0] spec_insn_sraw_rs2_addr; wire [ 4 : 0] spec_insn_sraw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_csr_misa_rmask; `endif rvfi_insn_sraw insn_sraw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sraw_csr_misa_rmask), `endif .spec_valid(spec_insn_sraw_valid), .spec_trap(spec_insn_sraw_trap), .spec_rs1_addr(spec_insn_sraw_rs1_addr), .spec_rs2_addr(spec_insn_sraw_rs2_addr), .spec_rd_addr(spec_insn_sraw_rd_addr), .spec_rd_wdata(spec_insn_sraw_rd_wdata), .spec_pc_wdata(spec_insn_sraw_pc_wdata), .spec_mem_addr(spec_insn_sraw_mem_addr), .spec_mem_rmask(spec_insn_sraw_mem_rmask), .spec_mem_wmask(spec_insn_sraw_mem_wmask), .spec_mem_wdata(spec_insn_sraw_mem_wdata) ); wire spec_insn_srl_valid; wire spec_insn_srl_trap; wire [ 4 : 0] spec_insn_srl_rs1_addr; wire [ 4 : 0] spec_insn_srl_rs2_addr; wire [ 4 : 0] spec_insn_srl_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; `endif rvfi_insn_srl insn_srl ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), `endif .spec_valid(spec_insn_srl_valid), .spec_trap(spec_insn_srl_trap), .spec_rs1_addr(spec_insn_srl_rs1_addr), .spec_rs2_addr(spec_insn_srl_rs2_addr), .spec_rd_addr(spec_insn_srl_rd_addr), .spec_rd_wdata(spec_insn_srl_rd_wdata), .spec_pc_wdata(spec_insn_srl_pc_wdata), .spec_mem_addr(spec_insn_srl_mem_addr), .spec_mem_rmask(spec_insn_srl_mem_rmask), .spec_mem_wmask(spec_insn_srl_mem_wmask), .spec_mem_wdata(spec_insn_srl_mem_wdata) ); wire spec_insn_srli_valid; wire spec_insn_srli_trap; wire [ 4 : 0] spec_insn_srli_rs1_addr; wire [ 4 : 0] spec_insn_srli_rs2_addr; wire [ 4 : 0] spec_insn_srli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; `endif rvfi_insn_srli insn_srli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), `endif .spec_valid(spec_insn_srli_valid), .spec_trap(spec_insn_srli_trap), .spec_rs1_addr(spec_insn_srli_rs1_addr), .spec_rs2_addr(spec_insn_srli_rs2_addr), .spec_rd_addr(spec_insn_srli_rd_addr), .spec_rd_wdata(spec_insn_srli_rd_wdata), .spec_pc_wdata(spec_insn_srli_pc_wdata), .spec_mem_addr(spec_insn_srli_mem_addr), .spec_mem_rmask(spec_insn_srli_mem_rmask), .spec_mem_wmask(spec_insn_srli_mem_wmask), .spec_mem_wdata(spec_insn_srli_mem_wdata) ); wire spec_insn_srliw_valid; wire spec_insn_srliw_trap; wire [ 4 : 0] spec_insn_srliw_rs1_addr; wire [ 4 : 0] spec_insn_srliw_rs2_addr; wire [ 4 : 0] spec_insn_srliw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_csr_misa_rmask; `endif rvfi_insn_srliw insn_srliw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srliw_csr_misa_rmask), `endif .spec_valid(spec_insn_srliw_valid), .spec_trap(spec_insn_srliw_trap), .spec_rs1_addr(spec_insn_srliw_rs1_addr), .spec_rs2_addr(spec_insn_srliw_rs2_addr), .spec_rd_addr(spec_insn_srliw_rd_addr), .spec_rd_wdata(spec_insn_srliw_rd_wdata), .spec_pc_wdata(spec_insn_srliw_pc_wdata), .spec_mem_addr(spec_insn_srliw_mem_addr), .spec_mem_rmask(spec_insn_srliw_mem_rmask), .spec_mem_wmask(spec_insn_srliw_mem_wmask), .spec_mem_wdata(spec_insn_srliw_mem_wdata) ); wire spec_insn_srlw_valid; wire spec_insn_srlw_trap; wire [ 4 : 0] spec_insn_srlw_rs1_addr; wire [ 4 : 0] spec_insn_srlw_rs2_addr; wire [ 4 : 0] spec_insn_srlw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_csr_misa_rmask; `endif rvfi_insn_srlw insn_srlw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srlw_csr_misa_rmask), `endif .spec_valid(spec_insn_srlw_valid), .spec_trap(spec_insn_srlw_trap), .spec_rs1_addr(spec_insn_srlw_rs1_addr), .spec_rs2_addr(spec_insn_srlw_rs2_addr), .spec_rd_addr(spec_insn_srlw_rd_addr), .spec_rd_wdata(spec_insn_srlw_rd_wdata), .spec_pc_wdata(spec_insn_srlw_pc_wdata), .spec_mem_addr(spec_insn_srlw_mem_addr), .spec_mem_rmask(spec_insn_srlw_mem_rmask), .spec_mem_wmask(spec_insn_srlw_mem_wmask), .spec_mem_wdata(spec_insn_srlw_mem_wdata) ); wire spec_insn_sub_valid; wire spec_insn_sub_trap; wire [ 4 : 0] spec_insn_sub_rs1_addr; wire [ 4 : 0] spec_insn_sub_rs2_addr; wire [ 4 : 0] spec_insn_sub_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; `endif rvfi_insn_sub insn_sub ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), `endif .spec_valid(spec_insn_sub_valid), .spec_trap(spec_insn_sub_trap), .spec_rs1_addr(spec_insn_sub_rs1_addr), .spec_rs2_addr(spec_insn_sub_rs2_addr), .spec_rd_addr(spec_insn_sub_rd_addr), .spec_rd_wdata(spec_insn_sub_rd_wdata), .spec_pc_wdata(spec_insn_sub_pc_wdata), .spec_mem_addr(spec_insn_sub_mem_addr), .spec_mem_rmask(spec_insn_sub_mem_rmask), .spec_mem_wmask(spec_insn_sub_mem_wmask), .spec_mem_wdata(spec_insn_sub_mem_wdata) ); wire spec_insn_subw_valid; wire spec_insn_subw_trap; wire [ 4 : 0] spec_insn_subw_rs1_addr; wire [ 4 : 0] spec_insn_subw_rs2_addr; wire [ 4 : 0] spec_insn_subw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_csr_misa_rmask; `endif rvfi_insn_subw insn_subw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_subw_csr_misa_rmask), `endif .spec_valid(spec_insn_subw_valid), .spec_trap(spec_insn_subw_trap), .spec_rs1_addr(spec_insn_subw_rs1_addr), .spec_rs2_addr(spec_insn_subw_rs2_addr), .spec_rd_addr(spec_insn_subw_rd_addr), .spec_rd_wdata(spec_insn_subw_rd_wdata), .spec_pc_wdata(spec_insn_subw_pc_wdata), .spec_mem_addr(spec_insn_subw_mem_addr), .spec_mem_rmask(spec_insn_subw_mem_rmask), .spec_mem_wmask(spec_insn_subw_mem_wmask), .spec_mem_wdata(spec_insn_subw_mem_wdata) ); wire spec_insn_sw_valid; wire spec_insn_sw_trap; wire [ 4 : 0] spec_insn_sw_rs1_addr; wire [ 4 : 0] spec_insn_sw_rs2_addr; wire [ 4 : 0] spec_insn_sw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; `endif rvfi_insn_sw insn_sw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), `endif .spec_valid(spec_insn_sw_valid), .spec_trap(spec_insn_sw_trap), .spec_rs1_addr(spec_insn_sw_rs1_addr), .spec_rs2_addr(spec_insn_sw_rs2_addr), .spec_rd_addr(spec_insn_sw_rd_addr), .spec_rd_wdata(spec_insn_sw_rd_wdata), .spec_pc_wdata(spec_insn_sw_pc_wdata), .spec_mem_addr(spec_insn_sw_mem_addr), .spec_mem_rmask(spec_insn_sw_mem_rmask), .spec_mem_wmask(spec_insn_sw_mem_wmask), .spec_mem_wdata(spec_insn_sw_mem_wdata) ); wire spec_insn_xor_valid; wire spec_insn_xor_trap; wire [ 4 : 0] spec_insn_xor_rs1_addr; wire [ 4 : 0] spec_insn_xor_rs2_addr; wire [ 4 : 0] spec_insn_xor_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; `endif rvfi_insn_xor insn_xor ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), `endif .spec_valid(spec_insn_xor_valid), .spec_trap(spec_insn_xor_trap), .spec_rs1_addr(spec_insn_xor_rs1_addr), .spec_rs2_addr(spec_insn_xor_rs2_addr), .spec_rd_addr(spec_insn_xor_rd_addr), .spec_rd_wdata(spec_insn_xor_rd_wdata), .spec_pc_wdata(spec_insn_xor_pc_wdata), .spec_mem_addr(spec_insn_xor_mem_addr), .spec_mem_rmask(spec_insn_xor_mem_rmask), .spec_mem_wmask(spec_insn_xor_mem_wmask), .spec_mem_wdata(spec_insn_xor_mem_wdata) ); wire spec_insn_xori_valid; wire spec_insn_xori_trap; wire [ 4 : 0] spec_insn_xori_rs1_addr; wire [ 4 : 0] spec_insn_xori_rs2_addr; wire [ 4 : 0] spec_insn_xori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; `endif rvfi_insn_xori insn_xori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), `endif .spec_valid(spec_insn_xori_valid), .spec_trap(spec_insn_xori_trap), .spec_rs1_addr(spec_insn_xori_rs1_addr), .spec_rs2_addr(spec_insn_xori_rs2_addr), .spec_rd_addr(spec_insn_xori_rd_addr), .spec_rd_wdata(spec_insn_xori_rd_wdata), .spec_pc_wdata(spec_insn_xori_pc_wdata), .spec_mem_addr(spec_insn_xori_mem_addr), .spec_mem_rmask(spec_insn_xori_mem_rmask), .spec_mem_wmask(spec_insn_xori_mem_wmask), .spec_mem_wdata(spec_insn_xori_mem_wdata) ); assign spec_valid = spec_insn_add_valid ? spec_insn_add_valid : spec_insn_addi_valid ? spec_insn_addi_valid : spec_insn_addiw_valid ? spec_insn_addiw_valid : spec_insn_addw_valid ? spec_insn_addw_valid : spec_insn_and_valid ? spec_insn_and_valid : spec_insn_andi_valid ? spec_insn_andi_valid : spec_insn_auipc_valid ? spec_insn_auipc_valid : spec_insn_beq_valid ? spec_insn_beq_valid : spec_insn_bge_valid ? spec_insn_bge_valid : spec_insn_bgeu_valid ? spec_insn_bgeu_valid : spec_insn_blt_valid ? spec_insn_blt_valid : spec_insn_bltu_valid ? spec_insn_bltu_valid : spec_insn_bne_valid ? spec_insn_bne_valid : spec_insn_div_valid ? spec_insn_div_valid : spec_insn_divu_valid ? spec_insn_divu_valid : spec_insn_divuw_valid ? spec_insn_divuw_valid : spec_insn_divw_valid ? spec_insn_divw_valid : spec_insn_jal_valid ? spec_insn_jal_valid : spec_insn_jalr_valid ? spec_insn_jalr_valid : spec_insn_lb_valid ? spec_insn_lb_valid : spec_insn_lbu_valid ? spec_insn_lbu_valid : spec_insn_ld_valid ? spec_insn_ld_valid : spec_insn_lh_valid ? spec_insn_lh_valid : spec_insn_lhu_valid ? spec_insn_lhu_valid : spec_insn_lui_valid ? spec_insn_lui_valid : spec_insn_lw_valid ? spec_insn_lw_valid : spec_insn_lwu_valid ? spec_insn_lwu_valid : spec_insn_mul_valid ? spec_insn_mul_valid : spec_insn_mulh_valid ? spec_insn_mulh_valid : spec_insn_mulhsu_valid ? spec_insn_mulhsu_valid : spec_insn_mulhu_valid ? spec_insn_mulhu_valid : spec_insn_mulw_valid ? spec_insn_mulw_valid : spec_insn_or_valid ? spec_insn_or_valid : spec_insn_ori_valid ? spec_insn_ori_valid : spec_insn_rem_valid ? spec_insn_rem_valid : spec_insn_remu_valid ? spec_insn_remu_valid : spec_insn_remuw_valid ? spec_insn_remuw_valid : spec_insn_remw_valid ? spec_insn_remw_valid : spec_insn_sb_valid ? spec_insn_sb_valid : spec_insn_sd_valid ? spec_insn_sd_valid : spec_insn_sh_valid ? spec_insn_sh_valid : spec_insn_sll_valid ? spec_insn_sll_valid : spec_insn_slli_valid ? spec_insn_slli_valid : spec_insn_slliw_valid ? spec_insn_slliw_valid : spec_insn_sllw_valid ? spec_insn_sllw_valid : spec_insn_slt_valid ? spec_insn_slt_valid : spec_insn_slti_valid ? spec_insn_slti_valid : spec_insn_sltiu_valid ? spec_insn_sltiu_valid : spec_insn_sltu_valid ? spec_insn_sltu_valid : spec_insn_sra_valid ? spec_insn_sra_valid : spec_insn_srai_valid ? spec_insn_srai_valid : spec_insn_sraiw_valid ? spec_insn_sraiw_valid : spec_insn_sraw_valid ? spec_insn_sraw_valid : spec_insn_srl_valid ? spec_insn_srl_valid : spec_insn_srli_valid ? spec_insn_srli_valid : spec_insn_srliw_valid ? spec_insn_srliw_valid : spec_insn_srlw_valid ? spec_insn_srlw_valid : spec_insn_sub_valid ? spec_insn_sub_valid : spec_insn_subw_valid ? spec_insn_subw_valid : spec_insn_sw_valid ? spec_insn_sw_valid : spec_insn_xor_valid ? spec_insn_xor_valid : spec_insn_xori_valid ? spec_insn_xori_valid : 0; assign spec_trap = spec_insn_add_valid ? spec_insn_add_trap : spec_insn_addi_valid ? spec_insn_addi_trap : spec_insn_addiw_valid ? spec_insn_addiw_trap : spec_insn_addw_valid ? spec_insn_addw_trap : spec_insn_and_valid ? spec_insn_and_trap : spec_insn_andi_valid ? spec_insn_andi_trap : spec_insn_auipc_valid ? spec_insn_auipc_trap : spec_insn_beq_valid ? spec_insn_beq_trap : spec_insn_bge_valid ? spec_insn_bge_trap : spec_insn_bgeu_valid ? spec_insn_bgeu_trap : spec_insn_blt_valid ? spec_insn_blt_trap : spec_insn_bltu_valid ? spec_insn_bltu_trap : spec_insn_bne_valid ? spec_insn_bne_trap : spec_insn_div_valid ? spec_insn_div_trap : spec_insn_divu_valid ? spec_insn_divu_trap : spec_insn_divuw_valid ? spec_insn_divuw_trap : spec_insn_divw_valid ? spec_insn_divw_trap : spec_insn_jal_valid ? spec_insn_jal_trap : spec_insn_jalr_valid ? spec_insn_jalr_trap : spec_insn_lb_valid ? spec_insn_lb_trap : spec_insn_lbu_valid ? spec_insn_lbu_trap : spec_insn_ld_valid ? spec_insn_ld_trap : spec_insn_lh_valid ? spec_insn_lh_trap : spec_insn_lhu_valid ? spec_insn_lhu_trap : spec_insn_lui_valid ? spec_insn_lui_trap : spec_insn_lw_valid ? spec_insn_lw_trap : spec_insn_lwu_valid ? spec_insn_lwu_trap : spec_insn_mul_valid ? spec_insn_mul_trap : spec_insn_mulh_valid ? spec_insn_mulh_trap : spec_insn_mulhsu_valid ? spec_insn_mulhsu_trap : spec_insn_mulhu_valid ? spec_insn_mulhu_trap : spec_insn_mulw_valid ? spec_insn_mulw_trap : spec_insn_or_valid ? spec_insn_or_trap : spec_insn_ori_valid ? spec_insn_ori_trap : spec_insn_rem_valid ? spec_insn_rem_trap : spec_insn_remu_valid ? spec_insn_remu_trap : spec_insn_remuw_valid ? spec_insn_remuw_trap : spec_insn_remw_valid ? spec_insn_remw_trap : spec_insn_sb_valid ? spec_insn_sb_trap : spec_insn_sd_valid ? spec_insn_sd_trap : spec_insn_sh_valid ? spec_insn_sh_trap : spec_insn_sll_valid ? spec_insn_sll_trap : spec_insn_slli_valid ? spec_insn_slli_trap : spec_insn_slliw_valid ? spec_insn_slliw_trap : spec_insn_sllw_valid ? spec_insn_sllw_trap : spec_insn_slt_valid ? spec_insn_slt_trap : spec_insn_slti_valid ? spec_insn_slti_trap : spec_insn_sltiu_valid ? spec_insn_sltiu_trap : spec_insn_sltu_valid ? spec_insn_sltu_trap : spec_insn_sra_valid ? spec_insn_sra_trap : spec_insn_srai_valid ? spec_insn_srai_trap : spec_insn_sraiw_valid ? spec_insn_sraiw_trap : spec_insn_sraw_valid ? spec_insn_sraw_trap : spec_insn_srl_valid ? spec_insn_srl_trap : spec_insn_srli_valid ? spec_insn_srli_trap : spec_insn_srliw_valid ? spec_insn_srliw_trap : spec_insn_srlw_valid ? spec_insn_srlw_trap : spec_insn_sub_valid ? spec_insn_sub_trap : spec_insn_subw_valid ? spec_insn_subw_trap : spec_insn_sw_valid ? spec_insn_sw_trap : spec_insn_xor_valid ? spec_insn_xor_trap : spec_insn_xori_valid ? spec_insn_xori_trap : 0; assign spec_rs1_addr = spec_insn_add_valid ? spec_insn_add_rs1_addr : spec_insn_addi_valid ? spec_insn_addi_rs1_addr : spec_insn_addiw_valid ? spec_insn_addiw_rs1_addr : spec_insn_addw_valid ? spec_insn_addw_rs1_addr : spec_insn_and_valid ? spec_insn_and_rs1_addr : spec_insn_andi_valid ? spec_insn_andi_rs1_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : spec_insn_beq_valid ? spec_insn_beq_rs1_addr : spec_insn_bge_valid ? spec_insn_bge_rs1_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : spec_insn_blt_valid ? spec_insn_blt_rs1_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : spec_insn_bne_valid ? spec_insn_bne_rs1_addr : spec_insn_div_valid ? spec_insn_div_rs1_addr : spec_insn_divu_valid ? spec_insn_divu_rs1_addr : spec_insn_divuw_valid ? spec_insn_divuw_rs1_addr : spec_insn_divw_valid ? spec_insn_divw_rs1_addr : spec_insn_jal_valid ? spec_insn_jal_rs1_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : spec_insn_lb_valid ? spec_insn_lb_rs1_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : spec_insn_ld_valid ? spec_insn_ld_rs1_addr : spec_insn_lh_valid ? spec_insn_lh_rs1_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : spec_insn_lui_valid ? spec_insn_lui_rs1_addr : spec_insn_lw_valid ? spec_insn_lw_rs1_addr : spec_insn_lwu_valid ? spec_insn_lwu_rs1_addr : spec_insn_mul_valid ? spec_insn_mul_rs1_addr : spec_insn_mulh_valid ? spec_insn_mulh_rs1_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rs1_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_rs1_addr : spec_insn_mulw_valid ? spec_insn_mulw_rs1_addr : spec_insn_or_valid ? spec_insn_or_rs1_addr : spec_insn_ori_valid ? spec_insn_ori_rs1_addr : spec_insn_rem_valid ? spec_insn_rem_rs1_addr : spec_insn_remu_valid ? spec_insn_remu_rs1_addr : spec_insn_remuw_valid ? spec_insn_remuw_rs1_addr : spec_insn_remw_valid ? spec_insn_remw_rs1_addr : spec_insn_sb_valid ? spec_insn_sb_rs1_addr : spec_insn_sd_valid ? spec_insn_sd_rs1_addr : spec_insn_sh_valid ? spec_insn_sh_rs1_addr : spec_insn_sll_valid ? spec_insn_sll_rs1_addr : spec_insn_slli_valid ? spec_insn_slli_rs1_addr : spec_insn_slliw_valid ? spec_insn_slliw_rs1_addr : spec_insn_sllw_valid ? spec_insn_sllw_rs1_addr : spec_insn_slt_valid ? spec_insn_slt_rs1_addr : spec_insn_slti_valid ? spec_insn_slti_rs1_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : spec_insn_sra_valid ? spec_insn_sra_rs1_addr : spec_insn_srai_valid ? spec_insn_srai_rs1_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_rs1_addr : spec_insn_sraw_valid ? spec_insn_sraw_rs1_addr : spec_insn_srl_valid ? spec_insn_srl_rs1_addr : spec_insn_srli_valid ? spec_insn_srli_rs1_addr : spec_insn_srliw_valid ? spec_insn_srliw_rs1_addr : spec_insn_srlw_valid ? spec_insn_srlw_rs1_addr : spec_insn_sub_valid ? spec_insn_sub_rs1_addr : spec_insn_subw_valid ? spec_insn_subw_rs1_addr : spec_insn_sw_valid ? spec_insn_sw_rs1_addr : spec_insn_xor_valid ? spec_insn_xor_rs1_addr : spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; assign spec_rs2_addr = spec_insn_add_valid ? spec_insn_add_rs2_addr : spec_insn_addi_valid ? spec_insn_addi_rs2_addr : spec_insn_addiw_valid ? spec_insn_addiw_rs2_addr : spec_insn_addw_valid ? spec_insn_addw_rs2_addr : spec_insn_and_valid ? spec_insn_and_rs2_addr : spec_insn_andi_valid ? spec_insn_andi_rs2_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : spec_insn_beq_valid ? spec_insn_beq_rs2_addr : spec_insn_bge_valid ? spec_insn_bge_rs2_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : spec_insn_blt_valid ? spec_insn_blt_rs2_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : spec_insn_bne_valid ? spec_insn_bne_rs2_addr : spec_insn_div_valid ? spec_insn_div_rs2_addr : spec_insn_divu_valid ? spec_insn_divu_rs2_addr : spec_insn_divuw_valid ? spec_insn_divuw_rs2_addr : spec_insn_divw_valid ? spec_insn_divw_rs2_addr : spec_insn_jal_valid ? spec_insn_jal_rs2_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : spec_insn_lb_valid ? spec_insn_lb_rs2_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : spec_insn_ld_valid ? spec_insn_ld_rs2_addr : spec_insn_lh_valid ? spec_insn_lh_rs2_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : spec_insn_lui_valid ? spec_insn_lui_rs2_addr : spec_insn_lw_valid ? spec_insn_lw_rs2_addr : spec_insn_lwu_valid ? spec_insn_lwu_rs2_addr : spec_insn_mul_valid ? spec_insn_mul_rs2_addr : spec_insn_mulh_valid ? spec_insn_mulh_rs2_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rs2_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_rs2_addr : spec_insn_mulw_valid ? spec_insn_mulw_rs2_addr : spec_insn_or_valid ? spec_insn_or_rs2_addr : spec_insn_ori_valid ? spec_insn_ori_rs2_addr : spec_insn_rem_valid ? spec_insn_rem_rs2_addr : spec_insn_remu_valid ? spec_insn_remu_rs2_addr : spec_insn_remuw_valid ? spec_insn_remuw_rs2_addr : spec_insn_remw_valid ? spec_insn_remw_rs2_addr : spec_insn_sb_valid ? spec_insn_sb_rs2_addr : spec_insn_sd_valid ? spec_insn_sd_rs2_addr : spec_insn_sh_valid ? spec_insn_sh_rs2_addr : spec_insn_sll_valid ? spec_insn_sll_rs2_addr : spec_insn_slli_valid ? spec_insn_slli_rs2_addr : spec_insn_slliw_valid ? spec_insn_slliw_rs2_addr : spec_insn_sllw_valid ? spec_insn_sllw_rs2_addr : spec_insn_slt_valid ? spec_insn_slt_rs2_addr : spec_insn_slti_valid ? spec_insn_slti_rs2_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : spec_insn_sra_valid ? spec_insn_sra_rs2_addr : spec_insn_srai_valid ? spec_insn_srai_rs2_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_rs2_addr : spec_insn_sraw_valid ? spec_insn_sraw_rs2_addr : spec_insn_srl_valid ? spec_insn_srl_rs2_addr : spec_insn_srli_valid ? spec_insn_srli_rs2_addr : spec_insn_srliw_valid ? spec_insn_srliw_rs2_addr : spec_insn_srlw_valid ? spec_insn_srlw_rs2_addr : spec_insn_sub_valid ? spec_insn_sub_rs2_addr : spec_insn_subw_valid ? spec_insn_subw_rs2_addr : spec_insn_sw_valid ? spec_insn_sw_rs2_addr : spec_insn_xor_valid ? spec_insn_xor_rs2_addr : spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; assign spec_rd_addr = spec_insn_add_valid ? spec_insn_add_rd_addr : spec_insn_addi_valid ? spec_insn_addi_rd_addr : spec_insn_addiw_valid ? spec_insn_addiw_rd_addr : spec_insn_addw_valid ? spec_insn_addw_rd_addr : spec_insn_and_valid ? spec_insn_and_rd_addr : spec_insn_andi_valid ? spec_insn_andi_rd_addr : spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : spec_insn_beq_valid ? spec_insn_beq_rd_addr : spec_insn_bge_valid ? spec_insn_bge_rd_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : spec_insn_blt_valid ? spec_insn_blt_rd_addr : spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : spec_insn_bne_valid ? spec_insn_bne_rd_addr : spec_insn_div_valid ? spec_insn_div_rd_addr : spec_insn_divu_valid ? spec_insn_divu_rd_addr : spec_insn_divuw_valid ? spec_insn_divuw_rd_addr : spec_insn_divw_valid ? spec_insn_divw_rd_addr : spec_insn_jal_valid ? spec_insn_jal_rd_addr : spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : spec_insn_lb_valid ? spec_insn_lb_rd_addr : spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : spec_insn_ld_valid ? spec_insn_ld_rd_addr : spec_insn_lh_valid ? spec_insn_lh_rd_addr : spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : spec_insn_lui_valid ? spec_insn_lui_rd_addr : spec_insn_lw_valid ? spec_insn_lw_rd_addr : spec_insn_lwu_valid ? spec_insn_lwu_rd_addr : spec_insn_mul_valid ? spec_insn_mul_rd_addr : spec_insn_mulh_valid ? spec_insn_mulh_rd_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_rd_addr : spec_insn_mulw_valid ? spec_insn_mulw_rd_addr : spec_insn_or_valid ? spec_insn_or_rd_addr : spec_insn_ori_valid ? spec_insn_ori_rd_addr : spec_insn_rem_valid ? spec_insn_rem_rd_addr : spec_insn_remu_valid ? spec_insn_remu_rd_addr : spec_insn_remuw_valid ? spec_insn_remuw_rd_addr : spec_insn_remw_valid ? spec_insn_remw_rd_addr : spec_insn_sb_valid ? spec_insn_sb_rd_addr : spec_insn_sd_valid ? spec_insn_sd_rd_addr : spec_insn_sh_valid ? spec_insn_sh_rd_addr : spec_insn_sll_valid ? spec_insn_sll_rd_addr : spec_insn_slli_valid ? spec_insn_slli_rd_addr : spec_insn_slliw_valid ? spec_insn_slliw_rd_addr : spec_insn_sllw_valid ? spec_insn_sllw_rd_addr : spec_insn_slt_valid ? spec_insn_slt_rd_addr : spec_insn_slti_valid ? spec_insn_slti_rd_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : spec_insn_sra_valid ? spec_insn_sra_rd_addr : spec_insn_srai_valid ? spec_insn_srai_rd_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_rd_addr : spec_insn_sraw_valid ? spec_insn_sraw_rd_addr : spec_insn_srl_valid ? spec_insn_srl_rd_addr : spec_insn_srli_valid ? spec_insn_srli_rd_addr : spec_insn_srliw_valid ? spec_insn_srliw_rd_addr : spec_insn_srlw_valid ? spec_insn_srlw_rd_addr : spec_insn_sub_valid ? spec_insn_sub_rd_addr : spec_insn_subw_valid ? spec_insn_subw_rd_addr : spec_insn_sw_valid ? spec_insn_sw_rd_addr : spec_insn_xor_valid ? spec_insn_xor_rd_addr : spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; assign spec_rd_wdata = spec_insn_add_valid ? spec_insn_add_rd_wdata : spec_insn_addi_valid ? spec_insn_addi_rd_wdata : spec_insn_addiw_valid ? spec_insn_addiw_rd_wdata : spec_insn_addw_valid ? spec_insn_addw_rd_wdata : spec_insn_and_valid ? spec_insn_and_rd_wdata : spec_insn_andi_valid ? spec_insn_andi_rd_wdata : spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : spec_insn_beq_valid ? spec_insn_beq_rd_wdata : spec_insn_bge_valid ? spec_insn_bge_rd_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : spec_insn_blt_valid ? spec_insn_blt_rd_wdata : spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : spec_insn_bne_valid ? spec_insn_bne_rd_wdata : spec_insn_div_valid ? spec_insn_div_rd_wdata : spec_insn_divu_valid ? spec_insn_divu_rd_wdata : spec_insn_divuw_valid ? spec_insn_divuw_rd_wdata : spec_insn_divw_valid ? spec_insn_divw_rd_wdata : spec_insn_jal_valid ? spec_insn_jal_rd_wdata : spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : spec_insn_lb_valid ? spec_insn_lb_rd_wdata : spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : spec_insn_ld_valid ? spec_insn_ld_rd_wdata : spec_insn_lh_valid ? spec_insn_lh_rd_wdata : spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : spec_insn_lui_valid ? spec_insn_lui_rd_wdata : spec_insn_lw_valid ? spec_insn_lw_rd_wdata : spec_insn_lwu_valid ? spec_insn_lwu_rd_wdata : spec_insn_mul_valid ? spec_insn_mul_rd_wdata : spec_insn_mulh_valid ? spec_insn_mulh_rd_wdata : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_wdata : spec_insn_mulhu_valid ? spec_insn_mulhu_rd_wdata : spec_insn_mulw_valid ? spec_insn_mulw_rd_wdata : spec_insn_or_valid ? spec_insn_or_rd_wdata : spec_insn_ori_valid ? spec_insn_ori_rd_wdata : spec_insn_rem_valid ? spec_insn_rem_rd_wdata : spec_insn_remu_valid ? spec_insn_remu_rd_wdata : spec_insn_remuw_valid ? spec_insn_remuw_rd_wdata : spec_insn_remw_valid ? spec_insn_remw_rd_wdata : spec_insn_sb_valid ? spec_insn_sb_rd_wdata : spec_insn_sd_valid ? spec_insn_sd_rd_wdata : spec_insn_sh_valid ? spec_insn_sh_rd_wdata : spec_insn_sll_valid ? spec_insn_sll_rd_wdata : spec_insn_slli_valid ? spec_insn_slli_rd_wdata : spec_insn_slliw_valid ? spec_insn_slliw_rd_wdata : spec_insn_sllw_valid ? spec_insn_sllw_rd_wdata : spec_insn_slt_valid ? spec_insn_slt_rd_wdata : spec_insn_slti_valid ? spec_insn_slti_rd_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : spec_insn_sra_valid ? spec_insn_sra_rd_wdata : spec_insn_srai_valid ? spec_insn_srai_rd_wdata : spec_insn_sraiw_valid ? spec_insn_sraiw_rd_wdata : spec_insn_sraw_valid ? spec_insn_sraw_rd_wdata : spec_insn_srl_valid ? spec_insn_srl_rd_wdata : spec_insn_srli_valid ? spec_insn_srli_rd_wdata : spec_insn_srliw_valid ? spec_insn_srliw_rd_wdata : spec_insn_srlw_valid ? spec_insn_srlw_rd_wdata : spec_insn_sub_valid ? spec_insn_sub_rd_wdata : spec_insn_subw_valid ? spec_insn_subw_rd_wdata : spec_insn_sw_valid ? spec_insn_sw_rd_wdata : spec_insn_xor_valid ? spec_insn_xor_rd_wdata : spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; assign spec_pc_wdata = spec_insn_add_valid ? spec_insn_add_pc_wdata : spec_insn_addi_valid ? spec_insn_addi_pc_wdata : spec_insn_addiw_valid ? spec_insn_addiw_pc_wdata : spec_insn_addw_valid ? spec_insn_addw_pc_wdata : spec_insn_and_valid ? spec_insn_and_pc_wdata : spec_insn_andi_valid ? spec_insn_andi_pc_wdata : spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : spec_insn_beq_valid ? spec_insn_beq_pc_wdata : spec_insn_bge_valid ? spec_insn_bge_pc_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : spec_insn_blt_valid ? spec_insn_blt_pc_wdata : spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : spec_insn_bne_valid ? spec_insn_bne_pc_wdata : spec_insn_div_valid ? spec_insn_div_pc_wdata : spec_insn_divu_valid ? spec_insn_divu_pc_wdata : spec_insn_divuw_valid ? spec_insn_divuw_pc_wdata : spec_insn_divw_valid ? spec_insn_divw_pc_wdata : spec_insn_jal_valid ? spec_insn_jal_pc_wdata : spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : spec_insn_lb_valid ? spec_insn_lb_pc_wdata : spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : spec_insn_ld_valid ? spec_insn_ld_pc_wdata : spec_insn_lh_valid ? spec_insn_lh_pc_wdata : spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : spec_insn_lui_valid ? spec_insn_lui_pc_wdata : spec_insn_lw_valid ? spec_insn_lw_pc_wdata : spec_insn_lwu_valid ? spec_insn_lwu_pc_wdata : spec_insn_mul_valid ? spec_insn_mul_pc_wdata : spec_insn_mulh_valid ? spec_insn_mulh_pc_wdata : spec_insn_mulhsu_valid ? spec_insn_mulhsu_pc_wdata : spec_insn_mulhu_valid ? spec_insn_mulhu_pc_wdata : spec_insn_mulw_valid ? spec_insn_mulw_pc_wdata : spec_insn_or_valid ? spec_insn_or_pc_wdata : spec_insn_ori_valid ? spec_insn_ori_pc_wdata : spec_insn_rem_valid ? spec_insn_rem_pc_wdata : spec_insn_remu_valid ? spec_insn_remu_pc_wdata : spec_insn_remuw_valid ? spec_insn_remuw_pc_wdata : spec_insn_remw_valid ? spec_insn_remw_pc_wdata : spec_insn_sb_valid ? spec_insn_sb_pc_wdata : spec_insn_sd_valid ? spec_insn_sd_pc_wdata : spec_insn_sh_valid ? spec_insn_sh_pc_wdata : spec_insn_sll_valid ? spec_insn_sll_pc_wdata : spec_insn_slli_valid ? spec_insn_slli_pc_wdata : spec_insn_slliw_valid ? spec_insn_slliw_pc_wdata : spec_insn_sllw_valid ? spec_insn_sllw_pc_wdata : spec_insn_slt_valid ? spec_insn_slt_pc_wdata : spec_insn_slti_valid ? spec_insn_slti_pc_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : spec_insn_sra_valid ? spec_insn_sra_pc_wdata : spec_insn_srai_valid ? spec_insn_srai_pc_wdata : spec_insn_sraiw_valid ? spec_insn_sraiw_pc_wdata : spec_insn_sraw_valid ? spec_insn_sraw_pc_wdata : spec_insn_srl_valid ? spec_insn_srl_pc_wdata : spec_insn_srli_valid ? spec_insn_srli_pc_wdata : spec_insn_srliw_valid ? spec_insn_srliw_pc_wdata : spec_insn_srlw_valid ? spec_insn_srlw_pc_wdata : spec_insn_sub_valid ? spec_insn_sub_pc_wdata : spec_insn_subw_valid ? spec_insn_subw_pc_wdata : spec_insn_sw_valid ? spec_insn_sw_pc_wdata : spec_insn_xor_valid ? spec_insn_xor_pc_wdata : spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; assign spec_mem_addr = spec_insn_add_valid ? spec_insn_add_mem_addr : spec_insn_addi_valid ? spec_insn_addi_mem_addr : spec_insn_addiw_valid ? spec_insn_addiw_mem_addr : spec_insn_addw_valid ? spec_insn_addw_mem_addr : spec_insn_and_valid ? spec_insn_and_mem_addr : spec_insn_andi_valid ? spec_insn_andi_mem_addr : spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : spec_insn_beq_valid ? spec_insn_beq_mem_addr : spec_insn_bge_valid ? spec_insn_bge_mem_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : spec_insn_blt_valid ? spec_insn_blt_mem_addr : spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : spec_insn_bne_valid ? spec_insn_bne_mem_addr : spec_insn_div_valid ? spec_insn_div_mem_addr : spec_insn_divu_valid ? spec_insn_divu_mem_addr : spec_insn_divuw_valid ? spec_insn_divuw_mem_addr : spec_insn_divw_valid ? spec_insn_divw_mem_addr : spec_insn_jal_valid ? spec_insn_jal_mem_addr : spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : spec_insn_lb_valid ? spec_insn_lb_mem_addr : spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : spec_insn_ld_valid ? spec_insn_ld_mem_addr : spec_insn_lh_valid ? spec_insn_lh_mem_addr : spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : spec_insn_lui_valid ? spec_insn_lui_mem_addr : spec_insn_lw_valid ? spec_insn_lw_mem_addr : spec_insn_lwu_valid ? spec_insn_lwu_mem_addr : spec_insn_mul_valid ? spec_insn_mul_mem_addr : spec_insn_mulh_valid ? spec_insn_mulh_mem_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_addr : spec_insn_mulw_valid ? spec_insn_mulw_mem_addr : spec_insn_or_valid ? spec_insn_or_mem_addr : spec_insn_ori_valid ? spec_insn_ori_mem_addr : spec_insn_rem_valid ? spec_insn_rem_mem_addr : spec_insn_remu_valid ? spec_insn_remu_mem_addr : spec_insn_remuw_valid ? spec_insn_remuw_mem_addr : spec_insn_remw_valid ? spec_insn_remw_mem_addr : spec_insn_sb_valid ? spec_insn_sb_mem_addr : spec_insn_sd_valid ? spec_insn_sd_mem_addr : spec_insn_sh_valid ? spec_insn_sh_mem_addr : spec_insn_sll_valid ? spec_insn_sll_mem_addr : spec_insn_slli_valid ? spec_insn_slli_mem_addr : spec_insn_slliw_valid ? spec_insn_slliw_mem_addr : spec_insn_sllw_valid ? spec_insn_sllw_mem_addr : spec_insn_slt_valid ? spec_insn_slt_mem_addr : spec_insn_slti_valid ? spec_insn_slti_mem_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : spec_insn_sra_valid ? spec_insn_sra_mem_addr : spec_insn_srai_valid ? spec_insn_srai_mem_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_addr : spec_insn_sraw_valid ? spec_insn_sraw_mem_addr : spec_insn_srl_valid ? spec_insn_srl_mem_addr : spec_insn_srli_valid ? spec_insn_srli_mem_addr : spec_insn_srliw_valid ? spec_insn_srliw_mem_addr : spec_insn_srlw_valid ? spec_insn_srlw_mem_addr : spec_insn_sub_valid ? spec_insn_sub_mem_addr : spec_insn_subw_valid ? spec_insn_subw_mem_addr : spec_insn_sw_valid ? spec_insn_sw_mem_addr : spec_insn_xor_valid ? spec_insn_xor_mem_addr : spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; assign spec_mem_rmask = spec_insn_add_valid ? spec_insn_add_mem_rmask : spec_insn_addi_valid ? spec_insn_addi_mem_rmask : spec_insn_addiw_valid ? spec_insn_addiw_mem_rmask : spec_insn_addw_valid ? spec_insn_addw_mem_rmask : spec_insn_and_valid ? spec_insn_and_mem_rmask : spec_insn_andi_valid ? spec_insn_andi_mem_rmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : spec_insn_beq_valid ? spec_insn_beq_mem_rmask : spec_insn_bge_valid ? spec_insn_bge_mem_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : spec_insn_blt_valid ? spec_insn_blt_mem_rmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : spec_insn_bne_valid ? spec_insn_bne_mem_rmask : spec_insn_div_valid ? spec_insn_div_mem_rmask : spec_insn_divu_valid ? spec_insn_divu_mem_rmask : spec_insn_divuw_valid ? spec_insn_divuw_mem_rmask : spec_insn_divw_valid ? spec_insn_divw_mem_rmask : spec_insn_jal_valid ? spec_insn_jal_mem_rmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : spec_insn_lb_valid ? spec_insn_lb_mem_rmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : spec_insn_ld_valid ? spec_insn_ld_mem_rmask : spec_insn_lh_valid ? spec_insn_lh_mem_rmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : spec_insn_lui_valid ? spec_insn_lui_mem_rmask : spec_insn_lw_valid ? spec_insn_lw_mem_rmask : spec_insn_lwu_valid ? spec_insn_lwu_mem_rmask : spec_insn_mul_valid ? spec_insn_mul_mem_rmask : spec_insn_mulh_valid ? spec_insn_mulh_mem_rmask : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_rmask : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_rmask : spec_insn_mulw_valid ? spec_insn_mulw_mem_rmask : spec_insn_or_valid ? spec_insn_or_mem_rmask : spec_insn_ori_valid ? spec_insn_ori_mem_rmask : spec_insn_rem_valid ? spec_insn_rem_mem_rmask : spec_insn_remu_valid ? spec_insn_remu_mem_rmask : spec_insn_remuw_valid ? spec_insn_remuw_mem_rmask : spec_insn_remw_valid ? spec_insn_remw_mem_rmask : spec_insn_sb_valid ? spec_insn_sb_mem_rmask : spec_insn_sd_valid ? spec_insn_sd_mem_rmask : spec_insn_sh_valid ? spec_insn_sh_mem_rmask : spec_insn_sll_valid ? spec_insn_sll_mem_rmask : spec_insn_slli_valid ? spec_insn_slli_mem_rmask : spec_insn_slliw_valid ? spec_insn_slliw_mem_rmask : spec_insn_sllw_valid ? spec_insn_sllw_mem_rmask : spec_insn_slt_valid ? spec_insn_slt_mem_rmask : spec_insn_slti_valid ? spec_insn_slti_mem_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : spec_insn_sra_valid ? spec_insn_sra_mem_rmask : spec_insn_srai_valid ? spec_insn_srai_mem_rmask : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_rmask : spec_insn_sraw_valid ? spec_insn_sraw_mem_rmask : spec_insn_srl_valid ? spec_insn_srl_mem_rmask : spec_insn_srli_valid ? spec_insn_srli_mem_rmask : spec_insn_srliw_valid ? spec_insn_srliw_mem_rmask : spec_insn_srlw_valid ? spec_insn_srlw_mem_rmask : spec_insn_sub_valid ? spec_insn_sub_mem_rmask : spec_insn_subw_valid ? spec_insn_subw_mem_rmask : spec_insn_sw_valid ? spec_insn_sw_mem_rmask : spec_insn_xor_valid ? spec_insn_xor_mem_rmask : spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; assign spec_mem_wmask = spec_insn_add_valid ? spec_insn_add_mem_wmask : spec_insn_addi_valid ? spec_insn_addi_mem_wmask : spec_insn_addiw_valid ? spec_insn_addiw_mem_wmask : spec_insn_addw_valid ? spec_insn_addw_mem_wmask : spec_insn_and_valid ? spec_insn_and_mem_wmask : spec_insn_andi_valid ? spec_insn_andi_mem_wmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : spec_insn_beq_valid ? spec_insn_beq_mem_wmask : spec_insn_bge_valid ? spec_insn_bge_mem_wmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : spec_insn_blt_valid ? spec_insn_blt_mem_wmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : spec_insn_bne_valid ? spec_insn_bne_mem_wmask : spec_insn_div_valid ? spec_insn_div_mem_wmask : spec_insn_divu_valid ? spec_insn_divu_mem_wmask : spec_insn_divuw_valid ? spec_insn_divuw_mem_wmask : spec_insn_divw_valid ? spec_insn_divw_mem_wmask : spec_insn_jal_valid ? spec_insn_jal_mem_wmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : spec_insn_lb_valid ? spec_insn_lb_mem_wmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : spec_insn_ld_valid ? spec_insn_ld_mem_wmask : spec_insn_lh_valid ? spec_insn_lh_mem_wmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : spec_insn_lui_valid ? spec_insn_lui_mem_wmask : spec_insn_lw_valid ? spec_insn_lw_mem_wmask : spec_insn_lwu_valid ? spec_insn_lwu_mem_wmask : spec_insn_mul_valid ? spec_insn_mul_mem_wmask : spec_insn_mulh_valid ? spec_insn_mulh_mem_wmask : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wmask : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_wmask : spec_insn_mulw_valid ? spec_insn_mulw_mem_wmask : spec_insn_or_valid ? spec_insn_or_mem_wmask : spec_insn_ori_valid ? spec_insn_ori_mem_wmask : spec_insn_rem_valid ? spec_insn_rem_mem_wmask : spec_insn_remu_valid ? spec_insn_remu_mem_wmask : spec_insn_remuw_valid ? spec_insn_remuw_mem_wmask : spec_insn_remw_valid ? spec_insn_remw_mem_wmask : spec_insn_sb_valid ? spec_insn_sb_mem_wmask : spec_insn_sd_valid ? spec_insn_sd_mem_wmask : spec_insn_sh_valid ? spec_insn_sh_mem_wmask : spec_insn_sll_valid ? spec_insn_sll_mem_wmask : spec_insn_slli_valid ? spec_insn_slli_mem_wmask : spec_insn_slliw_valid ? spec_insn_slliw_mem_wmask : spec_insn_sllw_valid ? spec_insn_sllw_mem_wmask : spec_insn_slt_valid ? spec_insn_slt_mem_wmask : spec_insn_slti_valid ? spec_insn_slti_mem_wmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : spec_insn_sra_valid ? spec_insn_sra_mem_wmask : spec_insn_srai_valid ? spec_insn_srai_mem_wmask : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wmask : spec_insn_sraw_valid ? spec_insn_sraw_mem_wmask : spec_insn_srl_valid ? spec_insn_srl_mem_wmask : spec_insn_srli_valid ? spec_insn_srli_mem_wmask : spec_insn_srliw_valid ? spec_insn_srliw_mem_wmask : spec_insn_srlw_valid ? spec_insn_srlw_mem_wmask : spec_insn_sub_valid ? spec_insn_sub_mem_wmask : spec_insn_subw_valid ? spec_insn_subw_mem_wmask : spec_insn_sw_valid ? spec_insn_sw_mem_wmask : spec_insn_xor_valid ? spec_insn_xor_mem_wmask : spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; assign spec_mem_wdata = spec_insn_add_valid ? spec_insn_add_mem_wdata : spec_insn_addi_valid ? spec_insn_addi_mem_wdata : spec_insn_addiw_valid ? spec_insn_addiw_mem_wdata : spec_insn_addw_valid ? spec_insn_addw_mem_wdata : spec_insn_and_valid ? spec_insn_and_mem_wdata : spec_insn_andi_valid ? spec_insn_andi_mem_wdata : spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : spec_insn_beq_valid ? spec_insn_beq_mem_wdata : spec_insn_bge_valid ? spec_insn_bge_mem_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : spec_insn_blt_valid ? spec_insn_blt_mem_wdata : spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : spec_insn_bne_valid ? spec_insn_bne_mem_wdata : spec_insn_div_valid ? spec_insn_div_mem_wdata : spec_insn_divu_valid ? spec_insn_divu_mem_wdata : spec_insn_divuw_valid ? spec_insn_divuw_mem_wdata : spec_insn_divw_valid ? spec_insn_divw_mem_wdata : spec_insn_jal_valid ? spec_insn_jal_mem_wdata : spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : spec_insn_lb_valid ? spec_insn_lb_mem_wdata : spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : spec_insn_ld_valid ? spec_insn_ld_mem_wdata : spec_insn_lh_valid ? spec_insn_lh_mem_wdata : spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : spec_insn_lui_valid ? spec_insn_lui_mem_wdata : spec_insn_lw_valid ? spec_insn_lw_mem_wdata : spec_insn_lwu_valid ? spec_insn_lwu_mem_wdata : spec_insn_mul_valid ? spec_insn_mul_mem_wdata : spec_insn_mulh_valid ? spec_insn_mulh_mem_wdata : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wdata : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_wdata : spec_insn_mulw_valid ? spec_insn_mulw_mem_wdata : spec_insn_or_valid ? spec_insn_or_mem_wdata : spec_insn_ori_valid ? spec_insn_ori_mem_wdata : spec_insn_rem_valid ? spec_insn_rem_mem_wdata : spec_insn_remu_valid ? spec_insn_remu_mem_wdata : spec_insn_remuw_valid ? spec_insn_remuw_mem_wdata : spec_insn_remw_valid ? spec_insn_remw_mem_wdata : spec_insn_sb_valid ? spec_insn_sb_mem_wdata : spec_insn_sd_valid ? spec_insn_sd_mem_wdata : spec_insn_sh_valid ? spec_insn_sh_mem_wdata : spec_insn_sll_valid ? spec_insn_sll_mem_wdata : spec_insn_slli_valid ? spec_insn_slli_mem_wdata : spec_insn_slliw_valid ? spec_insn_slliw_mem_wdata : spec_insn_sllw_valid ? spec_insn_sllw_mem_wdata : spec_insn_slt_valid ? spec_insn_slt_mem_wdata : spec_insn_slti_valid ? spec_insn_slti_mem_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : spec_insn_sra_valid ? spec_insn_sra_mem_wdata : spec_insn_srai_valid ? spec_insn_srai_mem_wdata : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wdata : spec_insn_sraw_valid ? spec_insn_sraw_mem_wdata : spec_insn_srl_valid ? spec_insn_srl_mem_wdata : spec_insn_srli_valid ? spec_insn_srli_mem_wdata : spec_insn_srliw_valid ? spec_insn_srliw_mem_wdata : spec_insn_srlw_valid ? spec_insn_srlw_mem_wdata : spec_insn_sub_valid ? spec_insn_sub_mem_wdata : spec_insn_subw_valid ? spec_insn_subw_mem_wdata : spec_insn_sw_valid ? spec_insn_sw_mem_wdata : spec_insn_xor_valid ? spec_insn_xor_mem_wdata : spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; `ifdef RISCV_FORMAL_CSR_MISA assign spec_csr_misa_rmask = spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : spec_insn_addiw_valid ? spec_insn_addiw_csr_misa_rmask : spec_insn_addw_valid ? spec_insn_addw_csr_misa_rmask : spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : spec_insn_div_valid ? spec_insn_div_csr_misa_rmask : spec_insn_divu_valid ? spec_insn_divu_csr_misa_rmask : spec_insn_divuw_valid ? spec_insn_divuw_csr_misa_rmask : spec_insn_divw_valid ? spec_insn_divw_csr_misa_rmask : spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : spec_insn_ld_valid ? spec_insn_ld_csr_misa_rmask : spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : spec_insn_lwu_valid ? spec_insn_lwu_csr_misa_rmask : spec_insn_mul_valid ? spec_insn_mul_csr_misa_rmask : spec_insn_mulh_valid ? spec_insn_mulh_csr_misa_rmask : spec_insn_mulhsu_valid ? spec_insn_mulhsu_csr_misa_rmask : spec_insn_mulhu_valid ? spec_insn_mulhu_csr_misa_rmask : spec_insn_mulw_valid ? spec_insn_mulw_csr_misa_rmask : spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : spec_insn_rem_valid ? spec_insn_rem_csr_misa_rmask : spec_insn_remu_valid ? spec_insn_remu_csr_misa_rmask : spec_insn_remuw_valid ? spec_insn_remuw_csr_misa_rmask : spec_insn_remw_valid ? spec_insn_remw_csr_misa_rmask : spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : spec_insn_sd_valid ? spec_insn_sd_csr_misa_rmask : spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : spec_insn_slliw_valid ? spec_insn_slliw_csr_misa_rmask : spec_insn_sllw_valid ? spec_insn_sllw_csr_misa_rmask : spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : spec_insn_sraiw_valid ? spec_insn_sraiw_csr_misa_rmask : spec_insn_sraw_valid ? spec_insn_sraw_csr_misa_rmask : spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : spec_insn_srliw_valid ? spec_insn_srliw_csr_misa_rmask : spec_insn_srlw_valid ? spec_insn_srlw_csr_misa_rmask : spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : spec_insn_subw_valid ? spec_insn_subw_csr_misa_rmask : spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; `endif endmodule ================================================ FILE: insns/isa_rv64imc.txt ================================================ add addi addiw addw and andi auipc beq bge bgeu blt bltu bne c_add c_addi c_addi16sp c_addi4spn c_addiw c_addw c_and c_andi c_beqz c_bnez c_j c_jalr c_jr c_ld c_ldsp c_li c_lui c_lw c_lwsp c_mv c_or c_sd c_sdsp c_slli c_srai c_srli c_sub c_subw c_sw c_swsp c_xor div divu divuw divw jal jalr lb lbu ld lh lhu lui lw lwu mul mulh mulhsu mulhu mulw or ori rem remu remuw remw sb sd sh sll slli slliw sllw slt slti sltiu sltu sra srai sraiw sraw srl srli srliw srlw sub subw sw xor xori ================================================ FILE: insns/isa_rv64imc.v ================================================ // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py module rvfi_isa_rv64imc ( input rvfi_valid, input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, `ifdef RISCV_FORMAL_CSR_MISA input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, `endif output spec_valid, output spec_trap, output [ 4 : 0] spec_rs1_addr, output [ 4 : 0] spec_rs2_addr, output [ 4 : 0] spec_rd_addr, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata ); wire spec_insn_add_valid; wire spec_insn_add_trap; wire [ 4 : 0] spec_insn_add_rs1_addr; wire [ 4 : 0] spec_insn_add_rs2_addr; wire [ 4 : 0] spec_insn_add_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_add_csr_misa_rmask; `endif rvfi_insn_add insn_add ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask), `endif .spec_valid(spec_insn_add_valid), .spec_trap(spec_insn_add_trap), .spec_rs1_addr(spec_insn_add_rs1_addr), .spec_rs2_addr(spec_insn_add_rs2_addr), .spec_rd_addr(spec_insn_add_rd_addr), .spec_rd_wdata(spec_insn_add_rd_wdata), .spec_pc_wdata(spec_insn_add_pc_wdata), .spec_mem_addr(spec_insn_add_mem_addr), .spec_mem_rmask(spec_insn_add_mem_rmask), .spec_mem_wmask(spec_insn_add_mem_wmask), .spec_mem_wdata(spec_insn_add_mem_wdata) ); wire spec_insn_addi_valid; wire spec_insn_addi_trap; wire [ 4 : 0] spec_insn_addi_rs1_addr; wire [ 4 : 0] spec_insn_addi_rs2_addr; wire [ 4 : 0] spec_insn_addi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addi_csr_misa_rmask; `endif rvfi_insn_addi insn_addi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask), `endif .spec_valid(spec_insn_addi_valid), .spec_trap(spec_insn_addi_trap), .spec_rs1_addr(spec_insn_addi_rs1_addr), .spec_rs2_addr(spec_insn_addi_rs2_addr), .spec_rd_addr(spec_insn_addi_rd_addr), .spec_rd_wdata(spec_insn_addi_rd_wdata), .spec_pc_wdata(spec_insn_addi_pc_wdata), .spec_mem_addr(spec_insn_addi_mem_addr), .spec_mem_rmask(spec_insn_addi_mem_rmask), .spec_mem_wmask(spec_insn_addi_mem_wmask), .spec_mem_wdata(spec_insn_addi_mem_wdata) ); wire spec_insn_addiw_valid; wire spec_insn_addiw_trap; wire [ 4 : 0] spec_insn_addiw_rs1_addr; wire [ 4 : 0] spec_insn_addiw_rs2_addr; wire [ 4 : 0] spec_insn_addiw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addiw_csr_misa_rmask; `endif rvfi_insn_addiw insn_addiw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addiw_csr_misa_rmask), `endif .spec_valid(spec_insn_addiw_valid), .spec_trap(spec_insn_addiw_trap), .spec_rs1_addr(spec_insn_addiw_rs1_addr), .spec_rs2_addr(spec_insn_addiw_rs2_addr), .spec_rd_addr(spec_insn_addiw_rd_addr), .spec_rd_wdata(spec_insn_addiw_rd_wdata), .spec_pc_wdata(spec_insn_addiw_pc_wdata), .spec_mem_addr(spec_insn_addiw_mem_addr), .spec_mem_rmask(spec_insn_addiw_mem_rmask), .spec_mem_wmask(spec_insn_addiw_mem_wmask), .spec_mem_wdata(spec_insn_addiw_mem_wdata) ); wire spec_insn_addw_valid; wire spec_insn_addw_trap; wire [ 4 : 0] spec_insn_addw_rs1_addr; wire [ 4 : 0] spec_insn_addw_rs2_addr; wire [ 4 : 0] spec_insn_addw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_addw_csr_misa_rmask; `endif rvfi_insn_addw insn_addw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_addw_csr_misa_rmask), `endif .spec_valid(spec_insn_addw_valid), .spec_trap(spec_insn_addw_trap), .spec_rs1_addr(spec_insn_addw_rs1_addr), .spec_rs2_addr(spec_insn_addw_rs2_addr), .spec_rd_addr(spec_insn_addw_rd_addr), .spec_rd_wdata(spec_insn_addw_rd_wdata), .spec_pc_wdata(spec_insn_addw_pc_wdata), .spec_mem_addr(spec_insn_addw_mem_addr), .spec_mem_rmask(spec_insn_addw_mem_rmask), .spec_mem_wmask(spec_insn_addw_mem_wmask), .spec_mem_wdata(spec_insn_addw_mem_wdata) ); wire spec_insn_and_valid; wire spec_insn_and_trap; wire [ 4 : 0] spec_insn_and_rs1_addr; wire [ 4 : 0] spec_insn_and_rs2_addr; wire [ 4 : 0] spec_insn_and_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_and_csr_misa_rmask; `endif rvfi_insn_and insn_and ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask), `endif .spec_valid(spec_insn_and_valid), .spec_trap(spec_insn_and_trap), .spec_rs1_addr(spec_insn_and_rs1_addr), .spec_rs2_addr(spec_insn_and_rs2_addr), .spec_rd_addr(spec_insn_and_rd_addr), .spec_rd_wdata(spec_insn_and_rd_wdata), .spec_pc_wdata(spec_insn_and_pc_wdata), .spec_mem_addr(spec_insn_and_mem_addr), .spec_mem_rmask(spec_insn_and_mem_rmask), .spec_mem_wmask(spec_insn_and_mem_wmask), .spec_mem_wdata(spec_insn_and_mem_wdata) ); wire spec_insn_andi_valid; wire spec_insn_andi_trap; wire [ 4 : 0] spec_insn_andi_rs1_addr; wire [ 4 : 0] spec_insn_andi_rs2_addr; wire [ 4 : 0] spec_insn_andi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_andi_csr_misa_rmask; `endif rvfi_insn_andi insn_andi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask), `endif .spec_valid(spec_insn_andi_valid), .spec_trap(spec_insn_andi_trap), .spec_rs1_addr(spec_insn_andi_rs1_addr), .spec_rs2_addr(spec_insn_andi_rs2_addr), .spec_rd_addr(spec_insn_andi_rd_addr), .spec_rd_wdata(spec_insn_andi_rd_wdata), .spec_pc_wdata(spec_insn_andi_pc_wdata), .spec_mem_addr(spec_insn_andi_mem_addr), .spec_mem_rmask(spec_insn_andi_mem_rmask), .spec_mem_wmask(spec_insn_andi_mem_wmask), .spec_mem_wdata(spec_insn_andi_mem_wdata) ); wire spec_insn_auipc_valid; wire spec_insn_auipc_trap; wire [ 4 : 0] spec_insn_auipc_rs1_addr; wire [ 4 : 0] spec_insn_auipc_rs2_addr; wire [ 4 : 0] spec_insn_auipc_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_auipc_csr_misa_rmask; `endif rvfi_insn_auipc insn_auipc ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask), `endif .spec_valid(spec_insn_auipc_valid), .spec_trap(spec_insn_auipc_trap), .spec_rs1_addr(spec_insn_auipc_rs1_addr), .spec_rs2_addr(spec_insn_auipc_rs2_addr), .spec_rd_addr(spec_insn_auipc_rd_addr), .spec_rd_wdata(spec_insn_auipc_rd_wdata), .spec_pc_wdata(spec_insn_auipc_pc_wdata), .spec_mem_addr(spec_insn_auipc_mem_addr), .spec_mem_rmask(spec_insn_auipc_mem_rmask), .spec_mem_wmask(spec_insn_auipc_mem_wmask), .spec_mem_wdata(spec_insn_auipc_mem_wdata) ); wire spec_insn_beq_valid; wire spec_insn_beq_trap; wire [ 4 : 0] spec_insn_beq_rs1_addr; wire [ 4 : 0] spec_insn_beq_rs2_addr; wire [ 4 : 0] spec_insn_beq_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_beq_csr_misa_rmask; `endif rvfi_insn_beq insn_beq ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask), `endif .spec_valid(spec_insn_beq_valid), .spec_trap(spec_insn_beq_trap), .spec_rs1_addr(spec_insn_beq_rs1_addr), .spec_rs2_addr(spec_insn_beq_rs2_addr), .spec_rd_addr(spec_insn_beq_rd_addr), .spec_rd_wdata(spec_insn_beq_rd_wdata), .spec_pc_wdata(spec_insn_beq_pc_wdata), .spec_mem_addr(spec_insn_beq_mem_addr), .spec_mem_rmask(spec_insn_beq_mem_rmask), .spec_mem_wmask(spec_insn_beq_mem_wmask), .spec_mem_wdata(spec_insn_beq_mem_wdata) ); wire spec_insn_bge_valid; wire spec_insn_bge_trap; wire [ 4 : 0] spec_insn_bge_rs1_addr; wire [ 4 : 0] spec_insn_bge_rs2_addr; wire [ 4 : 0] spec_insn_bge_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bge_csr_misa_rmask; `endif rvfi_insn_bge insn_bge ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask), `endif .spec_valid(spec_insn_bge_valid), .spec_trap(spec_insn_bge_trap), .spec_rs1_addr(spec_insn_bge_rs1_addr), .spec_rs2_addr(spec_insn_bge_rs2_addr), .spec_rd_addr(spec_insn_bge_rd_addr), .spec_rd_wdata(spec_insn_bge_rd_wdata), .spec_pc_wdata(spec_insn_bge_pc_wdata), .spec_mem_addr(spec_insn_bge_mem_addr), .spec_mem_rmask(spec_insn_bge_mem_rmask), .spec_mem_wmask(spec_insn_bge_mem_wmask), .spec_mem_wdata(spec_insn_bge_mem_wdata) ); wire spec_insn_bgeu_valid; wire spec_insn_bgeu_trap; wire [ 4 : 0] spec_insn_bgeu_rs1_addr; wire [ 4 : 0] spec_insn_bgeu_rs2_addr; wire [ 4 : 0] spec_insn_bgeu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bgeu_csr_misa_rmask; `endif rvfi_insn_bgeu insn_bgeu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask), `endif .spec_valid(spec_insn_bgeu_valid), .spec_trap(spec_insn_bgeu_trap), .spec_rs1_addr(spec_insn_bgeu_rs1_addr), .spec_rs2_addr(spec_insn_bgeu_rs2_addr), .spec_rd_addr(spec_insn_bgeu_rd_addr), .spec_rd_wdata(spec_insn_bgeu_rd_wdata), .spec_pc_wdata(spec_insn_bgeu_pc_wdata), .spec_mem_addr(spec_insn_bgeu_mem_addr), .spec_mem_rmask(spec_insn_bgeu_mem_rmask), .spec_mem_wmask(spec_insn_bgeu_mem_wmask), .spec_mem_wdata(spec_insn_bgeu_mem_wdata) ); wire spec_insn_blt_valid; wire spec_insn_blt_trap; wire [ 4 : 0] spec_insn_blt_rs1_addr; wire [ 4 : 0] spec_insn_blt_rs2_addr; wire [ 4 : 0] spec_insn_blt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_blt_csr_misa_rmask; `endif rvfi_insn_blt insn_blt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask), `endif .spec_valid(spec_insn_blt_valid), .spec_trap(spec_insn_blt_trap), .spec_rs1_addr(spec_insn_blt_rs1_addr), .spec_rs2_addr(spec_insn_blt_rs2_addr), .spec_rd_addr(spec_insn_blt_rd_addr), .spec_rd_wdata(spec_insn_blt_rd_wdata), .spec_pc_wdata(spec_insn_blt_pc_wdata), .spec_mem_addr(spec_insn_blt_mem_addr), .spec_mem_rmask(spec_insn_blt_mem_rmask), .spec_mem_wmask(spec_insn_blt_mem_wmask), .spec_mem_wdata(spec_insn_blt_mem_wdata) ); wire spec_insn_bltu_valid; wire spec_insn_bltu_trap; wire [ 4 : 0] spec_insn_bltu_rs1_addr; wire [ 4 : 0] spec_insn_bltu_rs2_addr; wire [ 4 : 0] spec_insn_bltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bltu_csr_misa_rmask; `endif rvfi_insn_bltu insn_bltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask), `endif .spec_valid(spec_insn_bltu_valid), .spec_trap(spec_insn_bltu_trap), .spec_rs1_addr(spec_insn_bltu_rs1_addr), .spec_rs2_addr(spec_insn_bltu_rs2_addr), .spec_rd_addr(spec_insn_bltu_rd_addr), .spec_rd_wdata(spec_insn_bltu_rd_wdata), .spec_pc_wdata(spec_insn_bltu_pc_wdata), .spec_mem_addr(spec_insn_bltu_mem_addr), .spec_mem_rmask(spec_insn_bltu_mem_rmask), .spec_mem_wmask(spec_insn_bltu_mem_wmask), .spec_mem_wdata(spec_insn_bltu_mem_wdata) ); wire spec_insn_bne_valid; wire spec_insn_bne_trap; wire [ 4 : 0] spec_insn_bne_rs1_addr; wire [ 4 : 0] spec_insn_bne_rs2_addr; wire [ 4 : 0] spec_insn_bne_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_bne_csr_misa_rmask; `endif rvfi_insn_bne insn_bne ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask), `endif .spec_valid(spec_insn_bne_valid), .spec_trap(spec_insn_bne_trap), .spec_rs1_addr(spec_insn_bne_rs1_addr), .spec_rs2_addr(spec_insn_bne_rs2_addr), .spec_rd_addr(spec_insn_bne_rd_addr), .spec_rd_wdata(spec_insn_bne_rd_wdata), .spec_pc_wdata(spec_insn_bne_pc_wdata), .spec_mem_addr(spec_insn_bne_mem_addr), .spec_mem_rmask(spec_insn_bne_mem_rmask), .spec_mem_wmask(spec_insn_bne_mem_wmask), .spec_mem_wdata(spec_insn_bne_mem_wdata) ); wire spec_insn_c_add_valid; wire spec_insn_c_add_trap; wire [ 4 : 0] spec_insn_c_add_rs1_addr; wire [ 4 : 0] spec_insn_c_add_rs2_addr; wire [ 4 : 0] spec_insn_c_add_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_add_csr_misa_rmask; `endif rvfi_insn_c_add insn_c_add ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_add_csr_misa_rmask), `endif .spec_valid(spec_insn_c_add_valid), .spec_trap(spec_insn_c_add_trap), .spec_rs1_addr(spec_insn_c_add_rs1_addr), .spec_rs2_addr(spec_insn_c_add_rs2_addr), .spec_rd_addr(spec_insn_c_add_rd_addr), .spec_rd_wdata(spec_insn_c_add_rd_wdata), .spec_pc_wdata(spec_insn_c_add_pc_wdata), .spec_mem_addr(spec_insn_c_add_mem_addr), .spec_mem_rmask(spec_insn_c_add_mem_rmask), .spec_mem_wmask(spec_insn_c_add_mem_wmask), .spec_mem_wdata(spec_insn_c_add_mem_wdata) ); wire spec_insn_c_addi_valid; wire spec_insn_c_addi_trap; wire [ 4 : 0] spec_insn_c_addi_rs1_addr; wire [ 4 : 0] spec_insn_c_addi_rs2_addr; wire [ 4 : 0] spec_insn_c_addi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi_csr_misa_rmask; `endif rvfi_insn_c_addi insn_c_addi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addi_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addi_valid), .spec_trap(spec_insn_c_addi_trap), .spec_rs1_addr(spec_insn_c_addi_rs1_addr), .spec_rs2_addr(spec_insn_c_addi_rs2_addr), .spec_rd_addr(spec_insn_c_addi_rd_addr), .spec_rd_wdata(spec_insn_c_addi_rd_wdata), .spec_pc_wdata(spec_insn_c_addi_pc_wdata), .spec_mem_addr(spec_insn_c_addi_mem_addr), .spec_mem_rmask(spec_insn_c_addi_mem_rmask), .spec_mem_wmask(spec_insn_c_addi_mem_wmask), .spec_mem_wdata(spec_insn_c_addi_mem_wdata) ); wire spec_insn_c_addi16sp_valid; wire spec_insn_c_addi16sp_trap; wire [ 4 : 0] spec_insn_c_addi16sp_rs1_addr; wire [ 4 : 0] spec_insn_c_addi16sp_rs2_addr; wire [ 4 : 0] spec_insn_c_addi16sp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi16sp_csr_misa_rmask; `endif rvfi_insn_c_addi16sp insn_c_addi16sp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addi16sp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addi16sp_valid), .spec_trap(spec_insn_c_addi16sp_trap), .spec_rs1_addr(spec_insn_c_addi16sp_rs1_addr), .spec_rs2_addr(spec_insn_c_addi16sp_rs2_addr), .spec_rd_addr(spec_insn_c_addi16sp_rd_addr), .spec_rd_wdata(spec_insn_c_addi16sp_rd_wdata), .spec_pc_wdata(spec_insn_c_addi16sp_pc_wdata), .spec_mem_addr(spec_insn_c_addi16sp_mem_addr), .spec_mem_rmask(spec_insn_c_addi16sp_mem_rmask), .spec_mem_wmask(spec_insn_c_addi16sp_mem_wmask), .spec_mem_wdata(spec_insn_c_addi16sp_mem_wdata) ); wire spec_insn_c_addi4spn_valid; wire spec_insn_c_addi4spn_trap; wire [ 4 : 0] spec_insn_c_addi4spn_rs1_addr; wire [ 4 : 0] spec_insn_c_addi4spn_rs2_addr; wire [ 4 : 0] spec_insn_c_addi4spn_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addi4spn_csr_misa_rmask; `endif rvfi_insn_c_addi4spn insn_c_addi4spn ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addi4spn_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addi4spn_valid), .spec_trap(spec_insn_c_addi4spn_trap), .spec_rs1_addr(spec_insn_c_addi4spn_rs1_addr), .spec_rs2_addr(spec_insn_c_addi4spn_rs2_addr), .spec_rd_addr(spec_insn_c_addi4spn_rd_addr), .spec_rd_wdata(spec_insn_c_addi4spn_rd_wdata), .spec_pc_wdata(spec_insn_c_addi4spn_pc_wdata), .spec_mem_addr(spec_insn_c_addi4spn_mem_addr), .spec_mem_rmask(spec_insn_c_addi4spn_mem_rmask), .spec_mem_wmask(spec_insn_c_addi4spn_mem_wmask), .spec_mem_wdata(spec_insn_c_addi4spn_mem_wdata) ); wire spec_insn_c_addiw_valid; wire spec_insn_c_addiw_trap; wire [ 4 : 0] spec_insn_c_addiw_rs1_addr; wire [ 4 : 0] spec_insn_c_addiw_rs2_addr; wire [ 4 : 0] spec_insn_c_addiw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addiw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addiw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addiw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addiw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addiw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addiw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addiw_csr_misa_rmask; `endif rvfi_insn_c_addiw insn_c_addiw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addiw_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addiw_valid), .spec_trap(spec_insn_c_addiw_trap), .spec_rs1_addr(spec_insn_c_addiw_rs1_addr), .spec_rs2_addr(spec_insn_c_addiw_rs2_addr), .spec_rd_addr(spec_insn_c_addiw_rd_addr), .spec_rd_wdata(spec_insn_c_addiw_rd_wdata), .spec_pc_wdata(spec_insn_c_addiw_pc_wdata), .spec_mem_addr(spec_insn_c_addiw_mem_addr), .spec_mem_rmask(spec_insn_c_addiw_mem_rmask), .spec_mem_wmask(spec_insn_c_addiw_mem_wmask), .spec_mem_wdata(spec_insn_c_addiw_mem_wdata) ); wire spec_insn_c_addw_valid; wire spec_insn_c_addw_trap; wire [ 4 : 0] spec_insn_c_addw_rs1_addr; wire [ 4 : 0] spec_insn_c_addw_rs2_addr; wire [ 4 : 0] spec_insn_c_addw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_addw_csr_misa_rmask; `endif rvfi_insn_c_addw insn_c_addw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_addw_csr_misa_rmask), `endif .spec_valid(spec_insn_c_addw_valid), .spec_trap(spec_insn_c_addw_trap), .spec_rs1_addr(spec_insn_c_addw_rs1_addr), .spec_rs2_addr(spec_insn_c_addw_rs2_addr), .spec_rd_addr(spec_insn_c_addw_rd_addr), .spec_rd_wdata(spec_insn_c_addw_rd_wdata), .spec_pc_wdata(spec_insn_c_addw_pc_wdata), .spec_mem_addr(spec_insn_c_addw_mem_addr), .spec_mem_rmask(spec_insn_c_addw_mem_rmask), .spec_mem_wmask(spec_insn_c_addw_mem_wmask), .spec_mem_wdata(spec_insn_c_addw_mem_wdata) ); wire spec_insn_c_and_valid; wire spec_insn_c_and_trap; wire [ 4 : 0] spec_insn_c_and_rs1_addr; wire [ 4 : 0] spec_insn_c_and_rs2_addr; wire [ 4 : 0] spec_insn_c_and_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_and_csr_misa_rmask; `endif rvfi_insn_c_and insn_c_and ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_and_csr_misa_rmask), `endif .spec_valid(spec_insn_c_and_valid), .spec_trap(spec_insn_c_and_trap), .spec_rs1_addr(spec_insn_c_and_rs1_addr), .spec_rs2_addr(spec_insn_c_and_rs2_addr), .spec_rd_addr(spec_insn_c_and_rd_addr), .spec_rd_wdata(spec_insn_c_and_rd_wdata), .spec_pc_wdata(spec_insn_c_and_pc_wdata), .spec_mem_addr(spec_insn_c_and_mem_addr), .spec_mem_rmask(spec_insn_c_and_mem_rmask), .spec_mem_wmask(spec_insn_c_and_mem_wmask), .spec_mem_wdata(spec_insn_c_and_mem_wdata) ); wire spec_insn_c_andi_valid; wire spec_insn_c_andi_trap; wire [ 4 : 0] spec_insn_c_andi_rs1_addr; wire [ 4 : 0] spec_insn_c_andi_rs2_addr; wire [ 4 : 0] spec_insn_c_andi_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_andi_csr_misa_rmask; `endif rvfi_insn_c_andi insn_c_andi ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_andi_csr_misa_rmask), `endif .spec_valid(spec_insn_c_andi_valid), .spec_trap(spec_insn_c_andi_trap), .spec_rs1_addr(spec_insn_c_andi_rs1_addr), .spec_rs2_addr(spec_insn_c_andi_rs2_addr), .spec_rd_addr(spec_insn_c_andi_rd_addr), .spec_rd_wdata(spec_insn_c_andi_rd_wdata), .spec_pc_wdata(spec_insn_c_andi_pc_wdata), .spec_mem_addr(spec_insn_c_andi_mem_addr), .spec_mem_rmask(spec_insn_c_andi_mem_rmask), .spec_mem_wmask(spec_insn_c_andi_mem_wmask), .spec_mem_wdata(spec_insn_c_andi_mem_wdata) ); wire spec_insn_c_beqz_valid; wire spec_insn_c_beqz_trap; wire [ 4 : 0] spec_insn_c_beqz_rs1_addr; wire [ 4 : 0] spec_insn_c_beqz_rs2_addr; wire [ 4 : 0] spec_insn_c_beqz_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_beqz_csr_misa_rmask; `endif rvfi_insn_c_beqz insn_c_beqz ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_beqz_csr_misa_rmask), `endif .spec_valid(spec_insn_c_beqz_valid), .spec_trap(spec_insn_c_beqz_trap), .spec_rs1_addr(spec_insn_c_beqz_rs1_addr), .spec_rs2_addr(spec_insn_c_beqz_rs2_addr), .spec_rd_addr(spec_insn_c_beqz_rd_addr), .spec_rd_wdata(spec_insn_c_beqz_rd_wdata), .spec_pc_wdata(spec_insn_c_beqz_pc_wdata), .spec_mem_addr(spec_insn_c_beqz_mem_addr), .spec_mem_rmask(spec_insn_c_beqz_mem_rmask), .spec_mem_wmask(spec_insn_c_beqz_mem_wmask), .spec_mem_wdata(spec_insn_c_beqz_mem_wdata) ); wire spec_insn_c_bnez_valid; wire spec_insn_c_bnez_trap; wire [ 4 : 0] spec_insn_c_bnez_rs1_addr; wire [ 4 : 0] spec_insn_c_bnez_rs2_addr; wire [ 4 : 0] spec_insn_c_bnez_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_bnez_csr_misa_rmask; `endif rvfi_insn_c_bnez insn_c_bnez ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_bnez_csr_misa_rmask), `endif .spec_valid(spec_insn_c_bnez_valid), .spec_trap(spec_insn_c_bnez_trap), .spec_rs1_addr(spec_insn_c_bnez_rs1_addr), .spec_rs2_addr(spec_insn_c_bnez_rs2_addr), .spec_rd_addr(spec_insn_c_bnez_rd_addr), .spec_rd_wdata(spec_insn_c_bnez_rd_wdata), .spec_pc_wdata(spec_insn_c_bnez_pc_wdata), .spec_mem_addr(spec_insn_c_bnez_mem_addr), .spec_mem_rmask(spec_insn_c_bnez_mem_rmask), .spec_mem_wmask(spec_insn_c_bnez_mem_wmask), .spec_mem_wdata(spec_insn_c_bnez_mem_wdata) ); wire spec_insn_c_j_valid; wire spec_insn_c_j_trap; wire [ 4 : 0] spec_insn_c_j_rs1_addr; wire [ 4 : 0] spec_insn_c_j_rs2_addr; wire [ 4 : 0] spec_insn_c_j_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_j_csr_misa_rmask; `endif rvfi_insn_c_j insn_c_j ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_j_csr_misa_rmask), `endif .spec_valid(spec_insn_c_j_valid), .spec_trap(spec_insn_c_j_trap), .spec_rs1_addr(spec_insn_c_j_rs1_addr), .spec_rs2_addr(spec_insn_c_j_rs2_addr), .spec_rd_addr(spec_insn_c_j_rd_addr), .spec_rd_wdata(spec_insn_c_j_rd_wdata), .spec_pc_wdata(spec_insn_c_j_pc_wdata), .spec_mem_addr(spec_insn_c_j_mem_addr), .spec_mem_rmask(spec_insn_c_j_mem_rmask), .spec_mem_wmask(spec_insn_c_j_mem_wmask), .spec_mem_wdata(spec_insn_c_j_mem_wdata) ); wire spec_insn_c_jalr_valid; wire spec_insn_c_jalr_trap; wire [ 4 : 0] spec_insn_c_jalr_rs1_addr; wire [ 4 : 0] spec_insn_c_jalr_rs2_addr; wire [ 4 : 0] spec_insn_c_jalr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jalr_csr_misa_rmask; `endif rvfi_insn_c_jalr insn_c_jalr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_jalr_csr_misa_rmask), `endif .spec_valid(spec_insn_c_jalr_valid), .spec_trap(spec_insn_c_jalr_trap), .spec_rs1_addr(spec_insn_c_jalr_rs1_addr), .spec_rs2_addr(spec_insn_c_jalr_rs2_addr), .spec_rd_addr(spec_insn_c_jalr_rd_addr), .spec_rd_wdata(spec_insn_c_jalr_rd_wdata), .spec_pc_wdata(spec_insn_c_jalr_pc_wdata), .spec_mem_addr(spec_insn_c_jalr_mem_addr), .spec_mem_rmask(spec_insn_c_jalr_mem_rmask), .spec_mem_wmask(spec_insn_c_jalr_mem_wmask), .spec_mem_wdata(spec_insn_c_jalr_mem_wdata) ); wire spec_insn_c_jr_valid; wire spec_insn_c_jr_trap; wire [ 4 : 0] spec_insn_c_jr_rs1_addr; wire [ 4 : 0] spec_insn_c_jr_rs2_addr; wire [ 4 : 0] spec_insn_c_jr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_jr_csr_misa_rmask; `endif rvfi_insn_c_jr insn_c_jr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_jr_csr_misa_rmask), `endif .spec_valid(spec_insn_c_jr_valid), .spec_trap(spec_insn_c_jr_trap), .spec_rs1_addr(spec_insn_c_jr_rs1_addr), .spec_rs2_addr(spec_insn_c_jr_rs2_addr), .spec_rd_addr(spec_insn_c_jr_rd_addr), .spec_rd_wdata(spec_insn_c_jr_rd_wdata), .spec_pc_wdata(spec_insn_c_jr_pc_wdata), .spec_mem_addr(spec_insn_c_jr_mem_addr), .spec_mem_rmask(spec_insn_c_jr_mem_rmask), .spec_mem_wmask(spec_insn_c_jr_mem_wmask), .spec_mem_wdata(spec_insn_c_jr_mem_wdata) ); wire spec_insn_c_ld_valid; wire spec_insn_c_ld_trap; wire [ 4 : 0] spec_insn_c_ld_rs1_addr; wire [ 4 : 0] spec_insn_c_ld_rs2_addr; wire [ 4 : 0] spec_insn_c_ld_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ld_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ld_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ld_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ld_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ld_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ld_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ld_csr_misa_rmask; `endif rvfi_insn_c_ld insn_c_ld ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_ld_csr_misa_rmask), `endif .spec_valid(spec_insn_c_ld_valid), .spec_trap(spec_insn_c_ld_trap), .spec_rs1_addr(spec_insn_c_ld_rs1_addr), .spec_rs2_addr(spec_insn_c_ld_rs2_addr), .spec_rd_addr(spec_insn_c_ld_rd_addr), .spec_rd_wdata(spec_insn_c_ld_rd_wdata), .spec_pc_wdata(spec_insn_c_ld_pc_wdata), .spec_mem_addr(spec_insn_c_ld_mem_addr), .spec_mem_rmask(spec_insn_c_ld_mem_rmask), .spec_mem_wmask(spec_insn_c_ld_mem_wmask), .spec_mem_wdata(spec_insn_c_ld_mem_wdata) ); wire spec_insn_c_ldsp_valid; wire spec_insn_c_ldsp_trap; wire [ 4 : 0] spec_insn_c_ldsp_rs1_addr; wire [ 4 : 0] spec_insn_c_ldsp_rs2_addr; wire [ 4 : 0] spec_insn_c_ldsp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ldsp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ldsp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ldsp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ldsp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ldsp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ldsp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_ldsp_csr_misa_rmask; `endif rvfi_insn_c_ldsp insn_c_ldsp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_ldsp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_ldsp_valid), .spec_trap(spec_insn_c_ldsp_trap), .spec_rs1_addr(spec_insn_c_ldsp_rs1_addr), .spec_rs2_addr(spec_insn_c_ldsp_rs2_addr), .spec_rd_addr(spec_insn_c_ldsp_rd_addr), .spec_rd_wdata(spec_insn_c_ldsp_rd_wdata), .spec_pc_wdata(spec_insn_c_ldsp_pc_wdata), .spec_mem_addr(spec_insn_c_ldsp_mem_addr), .spec_mem_rmask(spec_insn_c_ldsp_mem_rmask), .spec_mem_wmask(spec_insn_c_ldsp_mem_wmask), .spec_mem_wdata(spec_insn_c_ldsp_mem_wdata) ); wire spec_insn_c_li_valid; wire spec_insn_c_li_trap; wire [ 4 : 0] spec_insn_c_li_rs1_addr; wire [ 4 : 0] spec_insn_c_li_rs2_addr; wire [ 4 : 0] spec_insn_c_li_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_li_csr_misa_rmask; `endif rvfi_insn_c_li insn_c_li ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_li_csr_misa_rmask), `endif .spec_valid(spec_insn_c_li_valid), .spec_trap(spec_insn_c_li_trap), .spec_rs1_addr(spec_insn_c_li_rs1_addr), .spec_rs2_addr(spec_insn_c_li_rs2_addr), .spec_rd_addr(spec_insn_c_li_rd_addr), .spec_rd_wdata(spec_insn_c_li_rd_wdata), .spec_pc_wdata(spec_insn_c_li_pc_wdata), .spec_mem_addr(spec_insn_c_li_mem_addr), .spec_mem_rmask(spec_insn_c_li_mem_rmask), .spec_mem_wmask(spec_insn_c_li_mem_wmask), .spec_mem_wdata(spec_insn_c_li_mem_wdata) ); wire spec_insn_c_lui_valid; wire spec_insn_c_lui_trap; wire [ 4 : 0] spec_insn_c_lui_rs1_addr; wire [ 4 : 0] spec_insn_c_lui_rs2_addr; wire [ 4 : 0] spec_insn_c_lui_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lui_csr_misa_rmask; `endif rvfi_insn_c_lui insn_c_lui ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_lui_csr_misa_rmask), `endif .spec_valid(spec_insn_c_lui_valid), .spec_trap(spec_insn_c_lui_trap), .spec_rs1_addr(spec_insn_c_lui_rs1_addr), .spec_rs2_addr(spec_insn_c_lui_rs2_addr), .spec_rd_addr(spec_insn_c_lui_rd_addr), .spec_rd_wdata(spec_insn_c_lui_rd_wdata), .spec_pc_wdata(spec_insn_c_lui_pc_wdata), .spec_mem_addr(spec_insn_c_lui_mem_addr), .spec_mem_rmask(spec_insn_c_lui_mem_rmask), .spec_mem_wmask(spec_insn_c_lui_mem_wmask), .spec_mem_wdata(spec_insn_c_lui_mem_wdata) ); wire spec_insn_c_lw_valid; wire spec_insn_c_lw_trap; wire [ 4 : 0] spec_insn_c_lw_rs1_addr; wire [ 4 : 0] spec_insn_c_lw_rs2_addr; wire [ 4 : 0] spec_insn_c_lw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lw_csr_misa_rmask; `endif rvfi_insn_c_lw insn_c_lw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_lw_csr_misa_rmask), `endif .spec_valid(spec_insn_c_lw_valid), .spec_trap(spec_insn_c_lw_trap), .spec_rs1_addr(spec_insn_c_lw_rs1_addr), .spec_rs2_addr(spec_insn_c_lw_rs2_addr), .spec_rd_addr(spec_insn_c_lw_rd_addr), .spec_rd_wdata(spec_insn_c_lw_rd_wdata), .spec_pc_wdata(spec_insn_c_lw_pc_wdata), .spec_mem_addr(spec_insn_c_lw_mem_addr), .spec_mem_rmask(spec_insn_c_lw_mem_rmask), .spec_mem_wmask(spec_insn_c_lw_mem_wmask), .spec_mem_wdata(spec_insn_c_lw_mem_wdata) ); wire spec_insn_c_lwsp_valid; wire spec_insn_c_lwsp_trap; wire [ 4 : 0] spec_insn_c_lwsp_rs1_addr; wire [ 4 : 0] spec_insn_c_lwsp_rs2_addr; wire [ 4 : 0] spec_insn_c_lwsp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_lwsp_csr_misa_rmask; `endif rvfi_insn_c_lwsp insn_c_lwsp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_lwsp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_lwsp_valid), .spec_trap(spec_insn_c_lwsp_trap), .spec_rs1_addr(spec_insn_c_lwsp_rs1_addr), .spec_rs2_addr(spec_insn_c_lwsp_rs2_addr), .spec_rd_addr(spec_insn_c_lwsp_rd_addr), .spec_rd_wdata(spec_insn_c_lwsp_rd_wdata), .spec_pc_wdata(spec_insn_c_lwsp_pc_wdata), .spec_mem_addr(spec_insn_c_lwsp_mem_addr), .spec_mem_rmask(spec_insn_c_lwsp_mem_rmask), .spec_mem_wmask(spec_insn_c_lwsp_mem_wmask), .spec_mem_wdata(spec_insn_c_lwsp_mem_wdata) ); wire spec_insn_c_mv_valid; wire spec_insn_c_mv_trap; wire [ 4 : 0] spec_insn_c_mv_rs1_addr; wire [ 4 : 0] spec_insn_c_mv_rs2_addr; wire [ 4 : 0] spec_insn_c_mv_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_mv_csr_misa_rmask; `endif rvfi_insn_c_mv insn_c_mv ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_mv_csr_misa_rmask), `endif .spec_valid(spec_insn_c_mv_valid), .spec_trap(spec_insn_c_mv_trap), .spec_rs1_addr(spec_insn_c_mv_rs1_addr), .spec_rs2_addr(spec_insn_c_mv_rs2_addr), .spec_rd_addr(spec_insn_c_mv_rd_addr), .spec_rd_wdata(spec_insn_c_mv_rd_wdata), .spec_pc_wdata(spec_insn_c_mv_pc_wdata), .spec_mem_addr(spec_insn_c_mv_mem_addr), .spec_mem_rmask(spec_insn_c_mv_mem_rmask), .spec_mem_wmask(spec_insn_c_mv_mem_wmask), .spec_mem_wdata(spec_insn_c_mv_mem_wdata) ); wire spec_insn_c_or_valid; wire spec_insn_c_or_trap; wire [ 4 : 0] spec_insn_c_or_rs1_addr; wire [ 4 : 0] spec_insn_c_or_rs2_addr; wire [ 4 : 0] spec_insn_c_or_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_or_csr_misa_rmask; `endif rvfi_insn_c_or insn_c_or ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_or_csr_misa_rmask), `endif .spec_valid(spec_insn_c_or_valid), .spec_trap(spec_insn_c_or_trap), .spec_rs1_addr(spec_insn_c_or_rs1_addr), .spec_rs2_addr(spec_insn_c_or_rs2_addr), .spec_rd_addr(spec_insn_c_or_rd_addr), .spec_rd_wdata(spec_insn_c_or_rd_wdata), .spec_pc_wdata(spec_insn_c_or_pc_wdata), .spec_mem_addr(spec_insn_c_or_mem_addr), .spec_mem_rmask(spec_insn_c_or_mem_rmask), .spec_mem_wmask(spec_insn_c_or_mem_wmask), .spec_mem_wdata(spec_insn_c_or_mem_wdata) ); wire spec_insn_c_sd_valid; wire spec_insn_c_sd_trap; wire [ 4 : 0] spec_insn_c_sd_rs1_addr; wire [ 4 : 0] spec_insn_c_sd_rs2_addr; wire [ 4 : 0] spec_insn_c_sd_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sd_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sd_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sd_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sd_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sd_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sd_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sd_csr_misa_rmask; `endif rvfi_insn_c_sd insn_c_sd ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_sd_csr_misa_rmask), `endif .spec_valid(spec_insn_c_sd_valid), .spec_trap(spec_insn_c_sd_trap), .spec_rs1_addr(spec_insn_c_sd_rs1_addr), .spec_rs2_addr(spec_insn_c_sd_rs2_addr), .spec_rd_addr(spec_insn_c_sd_rd_addr), .spec_rd_wdata(spec_insn_c_sd_rd_wdata), .spec_pc_wdata(spec_insn_c_sd_pc_wdata), .spec_mem_addr(spec_insn_c_sd_mem_addr), .spec_mem_rmask(spec_insn_c_sd_mem_rmask), .spec_mem_wmask(spec_insn_c_sd_mem_wmask), .spec_mem_wdata(spec_insn_c_sd_mem_wdata) ); wire spec_insn_c_sdsp_valid; wire spec_insn_c_sdsp_trap; wire [ 4 : 0] spec_insn_c_sdsp_rs1_addr; wire [ 4 : 0] spec_insn_c_sdsp_rs2_addr; wire [ 4 : 0] spec_insn_c_sdsp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sdsp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sdsp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sdsp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sdsp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sdsp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sdsp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sdsp_csr_misa_rmask; `endif rvfi_insn_c_sdsp insn_c_sdsp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_sdsp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_sdsp_valid), .spec_trap(spec_insn_c_sdsp_trap), .spec_rs1_addr(spec_insn_c_sdsp_rs1_addr), .spec_rs2_addr(spec_insn_c_sdsp_rs2_addr), .spec_rd_addr(spec_insn_c_sdsp_rd_addr), .spec_rd_wdata(spec_insn_c_sdsp_rd_wdata), .spec_pc_wdata(spec_insn_c_sdsp_pc_wdata), .spec_mem_addr(spec_insn_c_sdsp_mem_addr), .spec_mem_rmask(spec_insn_c_sdsp_mem_rmask), .spec_mem_wmask(spec_insn_c_sdsp_mem_wmask), .spec_mem_wdata(spec_insn_c_sdsp_mem_wdata) ); wire spec_insn_c_slli_valid; wire spec_insn_c_slli_trap; wire [ 4 : 0] spec_insn_c_slli_rs1_addr; wire [ 4 : 0] spec_insn_c_slli_rs2_addr; wire [ 4 : 0] spec_insn_c_slli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_slli_csr_misa_rmask; `endif rvfi_insn_c_slli insn_c_slli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_slli_csr_misa_rmask), `endif .spec_valid(spec_insn_c_slli_valid), .spec_trap(spec_insn_c_slli_trap), .spec_rs1_addr(spec_insn_c_slli_rs1_addr), .spec_rs2_addr(spec_insn_c_slli_rs2_addr), .spec_rd_addr(spec_insn_c_slli_rd_addr), .spec_rd_wdata(spec_insn_c_slli_rd_wdata), .spec_pc_wdata(spec_insn_c_slli_pc_wdata), .spec_mem_addr(spec_insn_c_slli_mem_addr), .spec_mem_rmask(spec_insn_c_slli_mem_rmask), .spec_mem_wmask(spec_insn_c_slli_mem_wmask), .spec_mem_wdata(spec_insn_c_slli_mem_wdata) ); wire spec_insn_c_srai_valid; wire spec_insn_c_srai_trap; wire [ 4 : 0] spec_insn_c_srai_rs1_addr; wire [ 4 : 0] spec_insn_c_srai_rs2_addr; wire [ 4 : 0] spec_insn_c_srai_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srai_csr_misa_rmask; `endif rvfi_insn_c_srai insn_c_srai ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_srai_csr_misa_rmask), `endif .spec_valid(spec_insn_c_srai_valid), .spec_trap(spec_insn_c_srai_trap), .spec_rs1_addr(spec_insn_c_srai_rs1_addr), .spec_rs2_addr(spec_insn_c_srai_rs2_addr), .spec_rd_addr(spec_insn_c_srai_rd_addr), .spec_rd_wdata(spec_insn_c_srai_rd_wdata), .spec_pc_wdata(spec_insn_c_srai_pc_wdata), .spec_mem_addr(spec_insn_c_srai_mem_addr), .spec_mem_rmask(spec_insn_c_srai_mem_rmask), .spec_mem_wmask(spec_insn_c_srai_mem_wmask), .spec_mem_wdata(spec_insn_c_srai_mem_wdata) ); wire spec_insn_c_srli_valid; wire spec_insn_c_srli_trap; wire [ 4 : 0] spec_insn_c_srli_rs1_addr; wire [ 4 : 0] spec_insn_c_srli_rs2_addr; wire [ 4 : 0] spec_insn_c_srli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_srli_csr_misa_rmask; `endif rvfi_insn_c_srli insn_c_srli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_srli_csr_misa_rmask), `endif .spec_valid(spec_insn_c_srli_valid), .spec_trap(spec_insn_c_srli_trap), .spec_rs1_addr(spec_insn_c_srli_rs1_addr), .spec_rs2_addr(spec_insn_c_srli_rs2_addr), .spec_rd_addr(spec_insn_c_srli_rd_addr), .spec_rd_wdata(spec_insn_c_srli_rd_wdata), .spec_pc_wdata(spec_insn_c_srli_pc_wdata), .spec_mem_addr(spec_insn_c_srli_mem_addr), .spec_mem_rmask(spec_insn_c_srli_mem_rmask), .spec_mem_wmask(spec_insn_c_srli_mem_wmask), .spec_mem_wdata(spec_insn_c_srli_mem_wdata) ); wire spec_insn_c_sub_valid; wire spec_insn_c_sub_trap; wire [ 4 : 0] spec_insn_c_sub_rs1_addr; wire [ 4 : 0] spec_insn_c_sub_rs2_addr; wire [ 4 : 0] spec_insn_c_sub_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sub_csr_misa_rmask; `endif rvfi_insn_c_sub insn_c_sub ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_sub_csr_misa_rmask), `endif .spec_valid(spec_insn_c_sub_valid), .spec_trap(spec_insn_c_sub_trap), .spec_rs1_addr(spec_insn_c_sub_rs1_addr), .spec_rs2_addr(spec_insn_c_sub_rs2_addr), .spec_rd_addr(spec_insn_c_sub_rd_addr), .spec_rd_wdata(spec_insn_c_sub_rd_wdata), .spec_pc_wdata(spec_insn_c_sub_pc_wdata), .spec_mem_addr(spec_insn_c_sub_mem_addr), .spec_mem_rmask(spec_insn_c_sub_mem_rmask), .spec_mem_wmask(spec_insn_c_sub_mem_wmask), .spec_mem_wdata(spec_insn_c_sub_mem_wdata) ); wire spec_insn_c_subw_valid; wire spec_insn_c_subw_trap; wire [ 4 : 0] spec_insn_c_subw_rs1_addr; wire [ 4 : 0] spec_insn_c_subw_rs2_addr; wire [ 4 : 0] spec_insn_c_subw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_subw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_subw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_subw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_subw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_subw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_subw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_subw_csr_misa_rmask; `endif rvfi_insn_c_subw insn_c_subw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_subw_csr_misa_rmask), `endif .spec_valid(spec_insn_c_subw_valid), .spec_trap(spec_insn_c_subw_trap), .spec_rs1_addr(spec_insn_c_subw_rs1_addr), .spec_rs2_addr(spec_insn_c_subw_rs2_addr), .spec_rd_addr(spec_insn_c_subw_rd_addr), .spec_rd_wdata(spec_insn_c_subw_rd_wdata), .spec_pc_wdata(spec_insn_c_subw_pc_wdata), .spec_mem_addr(spec_insn_c_subw_mem_addr), .spec_mem_rmask(spec_insn_c_subw_mem_rmask), .spec_mem_wmask(spec_insn_c_subw_mem_wmask), .spec_mem_wdata(spec_insn_c_subw_mem_wdata) ); wire spec_insn_c_sw_valid; wire spec_insn_c_sw_trap; wire [ 4 : 0] spec_insn_c_sw_rs1_addr; wire [ 4 : 0] spec_insn_c_sw_rs2_addr; wire [ 4 : 0] spec_insn_c_sw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_sw_csr_misa_rmask; `endif rvfi_insn_c_sw insn_c_sw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_sw_csr_misa_rmask), `endif .spec_valid(spec_insn_c_sw_valid), .spec_trap(spec_insn_c_sw_trap), .spec_rs1_addr(spec_insn_c_sw_rs1_addr), .spec_rs2_addr(spec_insn_c_sw_rs2_addr), .spec_rd_addr(spec_insn_c_sw_rd_addr), .spec_rd_wdata(spec_insn_c_sw_rd_wdata), .spec_pc_wdata(spec_insn_c_sw_pc_wdata), .spec_mem_addr(spec_insn_c_sw_mem_addr), .spec_mem_rmask(spec_insn_c_sw_mem_rmask), .spec_mem_wmask(spec_insn_c_sw_mem_wmask), .spec_mem_wdata(spec_insn_c_sw_mem_wdata) ); wire spec_insn_c_swsp_valid; wire spec_insn_c_swsp_trap; wire [ 4 : 0] spec_insn_c_swsp_rs1_addr; wire [ 4 : 0] spec_insn_c_swsp_rs2_addr; wire [ 4 : 0] spec_insn_c_swsp_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_swsp_csr_misa_rmask; `endif rvfi_insn_c_swsp insn_c_swsp ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_swsp_csr_misa_rmask), `endif .spec_valid(spec_insn_c_swsp_valid), .spec_trap(spec_insn_c_swsp_trap), .spec_rs1_addr(spec_insn_c_swsp_rs1_addr), .spec_rs2_addr(spec_insn_c_swsp_rs2_addr), .spec_rd_addr(spec_insn_c_swsp_rd_addr), .spec_rd_wdata(spec_insn_c_swsp_rd_wdata), .spec_pc_wdata(spec_insn_c_swsp_pc_wdata), .spec_mem_addr(spec_insn_c_swsp_mem_addr), .spec_mem_rmask(spec_insn_c_swsp_mem_rmask), .spec_mem_wmask(spec_insn_c_swsp_mem_wmask), .spec_mem_wdata(spec_insn_c_swsp_mem_wdata) ); wire spec_insn_c_xor_valid; wire spec_insn_c_xor_trap; wire [ 4 : 0] spec_insn_c_xor_rs1_addr; wire [ 4 : 0] spec_insn_c_xor_rs2_addr; wire [ 4 : 0] spec_insn_c_xor_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_c_xor_csr_misa_rmask; `endif rvfi_insn_c_xor insn_c_xor ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_c_xor_csr_misa_rmask), `endif .spec_valid(spec_insn_c_xor_valid), .spec_trap(spec_insn_c_xor_trap), .spec_rs1_addr(spec_insn_c_xor_rs1_addr), .spec_rs2_addr(spec_insn_c_xor_rs2_addr), .spec_rd_addr(spec_insn_c_xor_rd_addr), .spec_rd_wdata(spec_insn_c_xor_rd_wdata), .spec_pc_wdata(spec_insn_c_xor_pc_wdata), .spec_mem_addr(spec_insn_c_xor_mem_addr), .spec_mem_rmask(spec_insn_c_xor_mem_rmask), .spec_mem_wmask(spec_insn_c_xor_mem_wmask), .spec_mem_wdata(spec_insn_c_xor_mem_wdata) ); wire spec_insn_div_valid; wire spec_insn_div_trap; wire [ 4 : 0] spec_insn_div_rs1_addr; wire [ 4 : 0] spec_insn_div_rs2_addr; wire [ 4 : 0] spec_insn_div_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_div_csr_misa_rmask; `endif rvfi_insn_div insn_div ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_div_csr_misa_rmask), `endif .spec_valid(spec_insn_div_valid), .spec_trap(spec_insn_div_trap), .spec_rs1_addr(spec_insn_div_rs1_addr), .spec_rs2_addr(spec_insn_div_rs2_addr), .spec_rd_addr(spec_insn_div_rd_addr), .spec_rd_wdata(spec_insn_div_rd_wdata), .spec_pc_wdata(spec_insn_div_pc_wdata), .spec_mem_addr(spec_insn_div_mem_addr), .spec_mem_rmask(spec_insn_div_mem_rmask), .spec_mem_wmask(spec_insn_div_mem_wmask), .spec_mem_wdata(spec_insn_div_mem_wdata) ); wire spec_insn_divu_valid; wire spec_insn_divu_trap; wire [ 4 : 0] spec_insn_divu_rs1_addr; wire [ 4 : 0] spec_insn_divu_rs2_addr; wire [ 4 : 0] spec_insn_divu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divu_csr_misa_rmask; `endif rvfi_insn_divu insn_divu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_divu_csr_misa_rmask), `endif .spec_valid(spec_insn_divu_valid), .spec_trap(spec_insn_divu_trap), .spec_rs1_addr(spec_insn_divu_rs1_addr), .spec_rs2_addr(spec_insn_divu_rs2_addr), .spec_rd_addr(spec_insn_divu_rd_addr), .spec_rd_wdata(spec_insn_divu_rd_wdata), .spec_pc_wdata(spec_insn_divu_pc_wdata), .spec_mem_addr(spec_insn_divu_mem_addr), .spec_mem_rmask(spec_insn_divu_mem_rmask), .spec_mem_wmask(spec_insn_divu_mem_wmask), .spec_mem_wdata(spec_insn_divu_mem_wdata) ); wire spec_insn_divuw_valid; wire spec_insn_divuw_trap; wire [ 4 : 0] spec_insn_divuw_rs1_addr; wire [ 4 : 0] spec_insn_divuw_rs2_addr; wire [ 4 : 0] spec_insn_divuw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divuw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divuw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divuw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divuw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divuw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divuw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divuw_csr_misa_rmask; `endif rvfi_insn_divuw insn_divuw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_divuw_csr_misa_rmask), `endif .spec_valid(spec_insn_divuw_valid), .spec_trap(spec_insn_divuw_trap), .spec_rs1_addr(spec_insn_divuw_rs1_addr), .spec_rs2_addr(spec_insn_divuw_rs2_addr), .spec_rd_addr(spec_insn_divuw_rd_addr), .spec_rd_wdata(spec_insn_divuw_rd_wdata), .spec_pc_wdata(spec_insn_divuw_pc_wdata), .spec_mem_addr(spec_insn_divuw_mem_addr), .spec_mem_rmask(spec_insn_divuw_mem_rmask), .spec_mem_wmask(spec_insn_divuw_mem_wmask), .spec_mem_wdata(spec_insn_divuw_mem_wdata) ); wire spec_insn_divw_valid; wire spec_insn_divw_trap; wire [ 4 : 0] spec_insn_divw_rs1_addr; wire [ 4 : 0] spec_insn_divw_rs2_addr; wire [ 4 : 0] spec_insn_divw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_divw_csr_misa_rmask; `endif rvfi_insn_divw insn_divw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_divw_csr_misa_rmask), `endif .spec_valid(spec_insn_divw_valid), .spec_trap(spec_insn_divw_trap), .spec_rs1_addr(spec_insn_divw_rs1_addr), .spec_rs2_addr(spec_insn_divw_rs2_addr), .spec_rd_addr(spec_insn_divw_rd_addr), .spec_rd_wdata(spec_insn_divw_rd_wdata), .spec_pc_wdata(spec_insn_divw_pc_wdata), .spec_mem_addr(spec_insn_divw_mem_addr), .spec_mem_rmask(spec_insn_divw_mem_rmask), .spec_mem_wmask(spec_insn_divw_mem_wmask), .spec_mem_wdata(spec_insn_divw_mem_wdata) ); wire spec_insn_jal_valid; wire spec_insn_jal_trap; wire [ 4 : 0] spec_insn_jal_rs1_addr; wire [ 4 : 0] spec_insn_jal_rs2_addr; wire [ 4 : 0] spec_insn_jal_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jal_csr_misa_rmask; `endif rvfi_insn_jal insn_jal ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask), `endif .spec_valid(spec_insn_jal_valid), .spec_trap(spec_insn_jal_trap), .spec_rs1_addr(spec_insn_jal_rs1_addr), .spec_rs2_addr(spec_insn_jal_rs2_addr), .spec_rd_addr(spec_insn_jal_rd_addr), .spec_rd_wdata(spec_insn_jal_rd_wdata), .spec_pc_wdata(spec_insn_jal_pc_wdata), .spec_mem_addr(spec_insn_jal_mem_addr), .spec_mem_rmask(spec_insn_jal_mem_rmask), .spec_mem_wmask(spec_insn_jal_mem_wmask), .spec_mem_wdata(spec_insn_jal_mem_wdata) ); wire spec_insn_jalr_valid; wire spec_insn_jalr_trap; wire [ 4 : 0] spec_insn_jalr_rs1_addr; wire [ 4 : 0] spec_insn_jalr_rs2_addr; wire [ 4 : 0] spec_insn_jalr_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_jalr_csr_misa_rmask; `endif rvfi_insn_jalr insn_jalr ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask), `endif .spec_valid(spec_insn_jalr_valid), .spec_trap(spec_insn_jalr_trap), .spec_rs1_addr(spec_insn_jalr_rs1_addr), .spec_rs2_addr(spec_insn_jalr_rs2_addr), .spec_rd_addr(spec_insn_jalr_rd_addr), .spec_rd_wdata(spec_insn_jalr_rd_wdata), .spec_pc_wdata(spec_insn_jalr_pc_wdata), .spec_mem_addr(spec_insn_jalr_mem_addr), .spec_mem_rmask(spec_insn_jalr_mem_rmask), .spec_mem_wmask(spec_insn_jalr_mem_wmask), .spec_mem_wdata(spec_insn_jalr_mem_wdata) ); wire spec_insn_lb_valid; wire spec_insn_lb_trap; wire [ 4 : 0] spec_insn_lb_rs1_addr; wire [ 4 : 0] spec_insn_lb_rs2_addr; wire [ 4 : 0] spec_insn_lb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lb_csr_misa_rmask; `endif rvfi_insn_lb insn_lb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask), `endif .spec_valid(spec_insn_lb_valid), .spec_trap(spec_insn_lb_trap), .spec_rs1_addr(spec_insn_lb_rs1_addr), .spec_rs2_addr(spec_insn_lb_rs2_addr), .spec_rd_addr(spec_insn_lb_rd_addr), .spec_rd_wdata(spec_insn_lb_rd_wdata), .spec_pc_wdata(spec_insn_lb_pc_wdata), .spec_mem_addr(spec_insn_lb_mem_addr), .spec_mem_rmask(spec_insn_lb_mem_rmask), .spec_mem_wmask(spec_insn_lb_mem_wmask), .spec_mem_wdata(spec_insn_lb_mem_wdata) ); wire spec_insn_lbu_valid; wire spec_insn_lbu_trap; wire [ 4 : 0] spec_insn_lbu_rs1_addr; wire [ 4 : 0] spec_insn_lbu_rs2_addr; wire [ 4 : 0] spec_insn_lbu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lbu_csr_misa_rmask; `endif rvfi_insn_lbu insn_lbu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask), `endif .spec_valid(spec_insn_lbu_valid), .spec_trap(spec_insn_lbu_trap), .spec_rs1_addr(spec_insn_lbu_rs1_addr), .spec_rs2_addr(spec_insn_lbu_rs2_addr), .spec_rd_addr(spec_insn_lbu_rd_addr), .spec_rd_wdata(spec_insn_lbu_rd_wdata), .spec_pc_wdata(spec_insn_lbu_pc_wdata), .spec_mem_addr(spec_insn_lbu_mem_addr), .spec_mem_rmask(spec_insn_lbu_mem_rmask), .spec_mem_wmask(spec_insn_lbu_mem_wmask), .spec_mem_wdata(spec_insn_lbu_mem_wdata) ); wire spec_insn_ld_valid; wire spec_insn_ld_trap; wire [ 4 : 0] spec_insn_ld_rs1_addr; wire [ 4 : 0] spec_insn_ld_rs2_addr; wire [ 4 : 0] spec_insn_ld_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ld_csr_misa_rmask; `endif rvfi_insn_ld insn_ld ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_ld_csr_misa_rmask), `endif .spec_valid(spec_insn_ld_valid), .spec_trap(spec_insn_ld_trap), .spec_rs1_addr(spec_insn_ld_rs1_addr), .spec_rs2_addr(spec_insn_ld_rs2_addr), .spec_rd_addr(spec_insn_ld_rd_addr), .spec_rd_wdata(spec_insn_ld_rd_wdata), .spec_pc_wdata(spec_insn_ld_pc_wdata), .spec_mem_addr(spec_insn_ld_mem_addr), .spec_mem_rmask(spec_insn_ld_mem_rmask), .spec_mem_wmask(spec_insn_ld_mem_wmask), .spec_mem_wdata(spec_insn_ld_mem_wdata) ); wire spec_insn_lh_valid; wire spec_insn_lh_trap; wire [ 4 : 0] spec_insn_lh_rs1_addr; wire [ 4 : 0] spec_insn_lh_rs2_addr; wire [ 4 : 0] spec_insn_lh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lh_csr_misa_rmask; `endif rvfi_insn_lh insn_lh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask), `endif .spec_valid(spec_insn_lh_valid), .spec_trap(spec_insn_lh_trap), .spec_rs1_addr(spec_insn_lh_rs1_addr), .spec_rs2_addr(spec_insn_lh_rs2_addr), .spec_rd_addr(spec_insn_lh_rd_addr), .spec_rd_wdata(spec_insn_lh_rd_wdata), .spec_pc_wdata(spec_insn_lh_pc_wdata), .spec_mem_addr(spec_insn_lh_mem_addr), .spec_mem_rmask(spec_insn_lh_mem_rmask), .spec_mem_wmask(spec_insn_lh_mem_wmask), .spec_mem_wdata(spec_insn_lh_mem_wdata) ); wire spec_insn_lhu_valid; wire spec_insn_lhu_trap; wire [ 4 : 0] spec_insn_lhu_rs1_addr; wire [ 4 : 0] spec_insn_lhu_rs2_addr; wire [ 4 : 0] spec_insn_lhu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lhu_csr_misa_rmask; `endif rvfi_insn_lhu insn_lhu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask), `endif .spec_valid(spec_insn_lhu_valid), .spec_trap(spec_insn_lhu_trap), .spec_rs1_addr(spec_insn_lhu_rs1_addr), .spec_rs2_addr(spec_insn_lhu_rs2_addr), .spec_rd_addr(spec_insn_lhu_rd_addr), .spec_rd_wdata(spec_insn_lhu_rd_wdata), .spec_pc_wdata(spec_insn_lhu_pc_wdata), .spec_mem_addr(spec_insn_lhu_mem_addr), .spec_mem_rmask(spec_insn_lhu_mem_rmask), .spec_mem_wmask(spec_insn_lhu_mem_wmask), .spec_mem_wdata(spec_insn_lhu_mem_wdata) ); wire spec_insn_lui_valid; wire spec_insn_lui_trap; wire [ 4 : 0] spec_insn_lui_rs1_addr; wire [ 4 : 0] spec_insn_lui_rs2_addr; wire [ 4 : 0] spec_insn_lui_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lui_csr_misa_rmask; `endif rvfi_insn_lui insn_lui ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask), `endif .spec_valid(spec_insn_lui_valid), .spec_trap(spec_insn_lui_trap), .spec_rs1_addr(spec_insn_lui_rs1_addr), .spec_rs2_addr(spec_insn_lui_rs2_addr), .spec_rd_addr(spec_insn_lui_rd_addr), .spec_rd_wdata(spec_insn_lui_rd_wdata), .spec_pc_wdata(spec_insn_lui_pc_wdata), .spec_mem_addr(spec_insn_lui_mem_addr), .spec_mem_rmask(spec_insn_lui_mem_rmask), .spec_mem_wmask(spec_insn_lui_mem_wmask), .spec_mem_wdata(spec_insn_lui_mem_wdata) ); wire spec_insn_lw_valid; wire spec_insn_lw_trap; wire [ 4 : 0] spec_insn_lw_rs1_addr; wire [ 4 : 0] spec_insn_lw_rs2_addr; wire [ 4 : 0] spec_insn_lw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lw_csr_misa_rmask; `endif rvfi_insn_lw insn_lw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask), `endif .spec_valid(spec_insn_lw_valid), .spec_trap(spec_insn_lw_trap), .spec_rs1_addr(spec_insn_lw_rs1_addr), .spec_rs2_addr(spec_insn_lw_rs2_addr), .spec_rd_addr(spec_insn_lw_rd_addr), .spec_rd_wdata(spec_insn_lw_rd_wdata), .spec_pc_wdata(spec_insn_lw_pc_wdata), .spec_mem_addr(spec_insn_lw_mem_addr), .spec_mem_rmask(spec_insn_lw_mem_rmask), .spec_mem_wmask(spec_insn_lw_mem_wmask), .spec_mem_wdata(spec_insn_lw_mem_wdata) ); wire spec_insn_lwu_valid; wire spec_insn_lwu_trap; wire [ 4 : 0] spec_insn_lwu_rs1_addr; wire [ 4 : 0] spec_insn_lwu_rs2_addr; wire [ 4 : 0] spec_insn_lwu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_lwu_csr_misa_rmask; `endif rvfi_insn_lwu insn_lwu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_lwu_csr_misa_rmask), `endif .spec_valid(spec_insn_lwu_valid), .spec_trap(spec_insn_lwu_trap), .spec_rs1_addr(spec_insn_lwu_rs1_addr), .spec_rs2_addr(spec_insn_lwu_rs2_addr), .spec_rd_addr(spec_insn_lwu_rd_addr), .spec_rd_wdata(spec_insn_lwu_rd_wdata), .spec_pc_wdata(spec_insn_lwu_pc_wdata), .spec_mem_addr(spec_insn_lwu_mem_addr), .spec_mem_rmask(spec_insn_lwu_mem_rmask), .spec_mem_wmask(spec_insn_lwu_mem_wmask), .spec_mem_wdata(spec_insn_lwu_mem_wdata) ); wire spec_insn_mul_valid; wire spec_insn_mul_trap; wire [ 4 : 0] spec_insn_mul_rs1_addr; wire [ 4 : 0] spec_insn_mul_rs2_addr; wire [ 4 : 0] spec_insn_mul_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mul_csr_misa_rmask; `endif rvfi_insn_mul insn_mul ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mul_csr_misa_rmask), `endif .spec_valid(spec_insn_mul_valid), .spec_trap(spec_insn_mul_trap), .spec_rs1_addr(spec_insn_mul_rs1_addr), .spec_rs2_addr(spec_insn_mul_rs2_addr), .spec_rd_addr(spec_insn_mul_rd_addr), .spec_rd_wdata(spec_insn_mul_rd_wdata), .spec_pc_wdata(spec_insn_mul_pc_wdata), .spec_mem_addr(spec_insn_mul_mem_addr), .spec_mem_rmask(spec_insn_mul_mem_rmask), .spec_mem_wmask(spec_insn_mul_mem_wmask), .spec_mem_wdata(spec_insn_mul_mem_wdata) ); wire spec_insn_mulh_valid; wire spec_insn_mulh_trap; wire [ 4 : 0] spec_insn_mulh_rs1_addr; wire [ 4 : 0] spec_insn_mulh_rs2_addr; wire [ 4 : 0] spec_insn_mulh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulh_csr_misa_rmask; `endif rvfi_insn_mulh insn_mulh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mulh_csr_misa_rmask), `endif .spec_valid(spec_insn_mulh_valid), .spec_trap(spec_insn_mulh_trap), .spec_rs1_addr(spec_insn_mulh_rs1_addr), .spec_rs2_addr(spec_insn_mulh_rs2_addr), .spec_rd_addr(spec_insn_mulh_rd_addr), .spec_rd_wdata(spec_insn_mulh_rd_wdata), .spec_pc_wdata(spec_insn_mulh_pc_wdata), .spec_mem_addr(spec_insn_mulh_mem_addr), .spec_mem_rmask(spec_insn_mulh_mem_rmask), .spec_mem_wmask(spec_insn_mulh_mem_wmask), .spec_mem_wdata(spec_insn_mulh_mem_wdata) ); wire spec_insn_mulhsu_valid; wire spec_insn_mulhsu_trap; wire [ 4 : 0] spec_insn_mulhsu_rs1_addr; wire [ 4 : 0] spec_insn_mulhsu_rs2_addr; wire [ 4 : 0] spec_insn_mulhsu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhsu_csr_misa_rmask; `endif rvfi_insn_mulhsu insn_mulhsu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mulhsu_csr_misa_rmask), `endif .spec_valid(spec_insn_mulhsu_valid), .spec_trap(spec_insn_mulhsu_trap), .spec_rs1_addr(spec_insn_mulhsu_rs1_addr), .spec_rs2_addr(spec_insn_mulhsu_rs2_addr), .spec_rd_addr(spec_insn_mulhsu_rd_addr), .spec_rd_wdata(spec_insn_mulhsu_rd_wdata), .spec_pc_wdata(spec_insn_mulhsu_pc_wdata), .spec_mem_addr(spec_insn_mulhsu_mem_addr), .spec_mem_rmask(spec_insn_mulhsu_mem_rmask), .spec_mem_wmask(spec_insn_mulhsu_mem_wmask), .spec_mem_wdata(spec_insn_mulhsu_mem_wdata) ); wire spec_insn_mulhu_valid; wire spec_insn_mulhu_trap; wire [ 4 : 0] spec_insn_mulhu_rs1_addr; wire [ 4 : 0] spec_insn_mulhu_rs2_addr; wire [ 4 : 0] spec_insn_mulhu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulhu_csr_misa_rmask; `endif rvfi_insn_mulhu insn_mulhu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mulhu_csr_misa_rmask), `endif .spec_valid(spec_insn_mulhu_valid), .spec_trap(spec_insn_mulhu_trap), .spec_rs1_addr(spec_insn_mulhu_rs1_addr), .spec_rs2_addr(spec_insn_mulhu_rs2_addr), .spec_rd_addr(spec_insn_mulhu_rd_addr), .spec_rd_wdata(spec_insn_mulhu_rd_wdata), .spec_pc_wdata(spec_insn_mulhu_pc_wdata), .spec_mem_addr(spec_insn_mulhu_mem_addr), .spec_mem_rmask(spec_insn_mulhu_mem_rmask), .spec_mem_wmask(spec_insn_mulhu_mem_wmask), .spec_mem_wdata(spec_insn_mulhu_mem_wdata) ); wire spec_insn_mulw_valid; wire spec_insn_mulw_trap; wire [ 4 : 0] spec_insn_mulw_rs1_addr; wire [ 4 : 0] spec_insn_mulw_rs2_addr; wire [ 4 : 0] spec_insn_mulw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_mulw_csr_misa_rmask; `endif rvfi_insn_mulw insn_mulw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_mulw_csr_misa_rmask), `endif .spec_valid(spec_insn_mulw_valid), .spec_trap(spec_insn_mulw_trap), .spec_rs1_addr(spec_insn_mulw_rs1_addr), .spec_rs2_addr(spec_insn_mulw_rs2_addr), .spec_rd_addr(spec_insn_mulw_rd_addr), .spec_rd_wdata(spec_insn_mulw_rd_wdata), .spec_pc_wdata(spec_insn_mulw_pc_wdata), .spec_mem_addr(spec_insn_mulw_mem_addr), .spec_mem_rmask(spec_insn_mulw_mem_rmask), .spec_mem_wmask(spec_insn_mulw_mem_wmask), .spec_mem_wdata(spec_insn_mulw_mem_wdata) ); wire spec_insn_or_valid; wire spec_insn_or_trap; wire [ 4 : 0] spec_insn_or_rs1_addr; wire [ 4 : 0] spec_insn_or_rs2_addr; wire [ 4 : 0] spec_insn_or_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_or_csr_misa_rmask; `endif rvfi_insn_or insn_or ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask), `endif .spec_valid(spec_insn_or_valid), .spec_trap(spec_insn_or_trap), .spec_rs1_addr(spec_insn_or_rs1_addr), .spec_rs2_addr(spec_insn_or_rs2_addr), .spec_rd_addr(spec_insn_or_rd_addr), .spec_rd_wdata(spec_insn_or_rd_wdata), .spec_pc_wdata(spec_insn_or_pc_wdata), .spec_mem_addr(spec_insn_or_mem_addr), .spec_mem_rmask(spec_insn_or_mem_rmask), .spec_mem_wmask(spec_insn_or_mem_wmask), .spec_mem_wdata(spec_insn_or_mem_wdata) ); wire spec_insn_ori_valid; wire spec_insn_ori_trap; wire [ 4 : 0] spec_insn_ori_rs1_addr; wire [ 4 : 0] spec_insn_ori_rs2_addr; wire [ 4 : 0] spec_insn_ori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_ori_csr_misa_rmask; `endif rvfi_insn_ori insn_ori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask), `endif .spec_valid(spec_insn_ori_valid), .spec_trap(spec_insn_ori_trap), .spec_rs1_addr(spec_insn_ori_rs1_addr), .spec_rs2_addr(spec_insn_ori_rs2_addr), .spec_rd_addr(spec_insn_ori_rd_addr), .spec_rd_wdata(spec_insn_ori_rd_wdata), .spec_pc_wdata(spec_insn_ori_pc_wdata), .spec_mem_addr(spec_insn_ori_mem_addr), .spec_mem_rmask(spec_insn_ori_mem_rmask), .spec_mem_wmask(spec_insn_ori_mem_wmask), .spec_mem_wdata(spec_insn_ori_mem_wdata) ); wire spec_insn_rem_valid; wire spec_insn_rem_trap; wire [ 4 : 0] spec_insn_rem_rs1_addr; wire [ 4 : 0] spec_insn_rem_rs2_addr; wire [ 4 : 0] spec_insn_rem_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_rem_csr_misa_rmask; `endif rvfi_insn_rem insn_rem ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_rem_csr_misa_rmask), `endif .spec_valid(spec_insn_rem_valid), .spec_trap(spec_insn_rem_trap), .spec_rs1_addr(spec_insn_rem_rs1_addr), .spec_rs2_addr(spec_insn_rem_rs2_addr), .spec_rd_addr(spec_insn_rem_rd_addr), .spec_rd_wdata(spec_insn_rem_rd_wdata), .spec_pc_wdata(spec_insn_rem_pc_wdata), .spec_mem_addr(spec_insn_rem_mem_addr), .spec_mem_rmask(spec_insn_rem_mem_rmask), .spec_mem_wmask(spec_insn_rem_mem_wmask), .spec_mem_wdata(spec_insn_rem_mem_wdata) ); wire spec_insn_remu_valid; wire spec_insn_remu_trap; wire [ 4 : 0] spec_insn_remu_rs1_addr; wire [ 4 : 0] spec_insn_remu_rs2_addr; wire [ 4 : 0] spec_insn_remu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remu_csr_misa_rmask; `endif rvfi_insn_remu insn_remu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_remu_csr_misa_rmask), `endif .spec_valid(spec_insn_remu_valid), .spec_trap(spec_insn_remu_trap), .spec_rs1_addr(spec_insn_remu_rs1_addr), .spec_rs2_addr(spec_insn_remu_rs2_addr), .spec_rd_addr(spec_insn_remu_rd_addr), .spec_rd_wdata(spec_insn_remu_rd_wdata), .spec_pc_wdata(spec_insn_remu_pc_wdata), .spec_mem_addr(spec_insn_remu_mem_addr), .spec_mem_rmask(spec_insn_remu_mem_rmask), .spec_mem_wmask(spec_insn_remu_mem_wmask), .spec_mem_wdata(spec_insn_remu_mem_wdata) ); wire spec_insn_remuw_valid; wire spec_insn_remuw_trap; wire [ 4 : 0] spec_insn_remuw_rs1_addr; wire [ 4 : 0] spec_insn_remuw_rs2_addr; wire [ 4 : 0] spec_insn_remuw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remuw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remuw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remuw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remuw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remuw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remuw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remuw_csr_misa_rmask; `endif rvfi_insn_remuw insn_remuw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_remuw_csr_misa_rmask), `endif .spec_valid(spec_insn_remuw_valid), .spec_trap(spec_insn_remuw_trap), .spec_rs1_addr(spec_insn_remuw_rs1_addr), .spec_rs2_addr(spec_insn_remuw_rs2_addr), .spec_rd_addr(spec_insn_remuw_rd_addr), .spec_rd_wdata(spec_insn_remuw_rd_wdata), .spec_pc_wdata(spec_insn_remuw_pc_wdata), .spec_mem_addr(spec_insn_remuw_mem_addr), .spec_mem_rmask(spec_insn_remuw_mem_rmask), .spec_mem_wmask(spec_insn_remuw_mem_wmask), .spec_mem_wdata(spec_insn_remuw_mem_wdata) ); wire spec_insn_remw_valid; wire spec_insn_remw_trap; wire [ 4 : 0] spec_insn_remw_rs1_addr; wire [ 4 : 0] spec_insn_remw_rs2_addr; wire [ 4 : 0] spec_insn_remw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_remw_csr_misa_rmask; `endif rvfi_insn_remw insn_remw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_remw_csr_misa_rmask), `endif .spec_valid(spec_insn_remw_valid), .spec_trap(spec_insn_remw_trap), .spec_rs1_addr(spec_insn_remw_rs1_addr), .spec_rs2_addr(spec_insn_remw_rs2_addr), .spec_rd_addr(spec_insn_remw_rd_addr), .spec_rd_wdata(spec_insn_remw_rd_wdata), .spec_pc_wdata(spec_insn_remw_pc_wdata), .spec_mem_addr(spec_insn_remw_mem_addr), .spec_mem_rmask(spec_insn_remw_mem_rmask), .spec_mem_wmask(spec_insn_remw_mem_wmask), .spec_mem_wdata(spec_insn_remw_mem_wdata) ); wire spec_insn_sb_valid; wire spec_insn_sb_trap; wire [ 4 : 0] spec_insn_sb_rs1_addr; wire [ 4 : 0] spec_insn_sb_rs2_addr; wire [ 4 : 0] spec_insn_sb_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sb_csr_misa_rmask; `endif rvfi_insn_sb insn_sb ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask), `endif .spec_valid(spec_insn_sb_valid), .spec_trap(spec_insn_sb_trap), .spec_rs1_addr(spec_insn_sb_rs1_addr), .spec_rs2_addr(spec_insn_sb_rs2_addr), .spec_rd_addr(spec_insn_sb_rd_addr), .spec_rd_wdata(spec_insn_sb_rd_wdata), .spec_pc_wdata(spec_insn_sb_pc_wdata), .spec_mem_addr(spec_insn_sb_mem_addr), .spec_mem_rmask(spec_insn_sb_mem_rmask), .spec_mem_wmask(spec_insn_sb_mem_wmask), .spec_mem_wdata(spec_insn_sb_mem_wdata) ); wire spec_insn_sd_valid; wire spec_insn_sd_trap; wire [ 4 : 0] spec_insn_sd_rs1_addr; wire [ 4 : 0] spec_insn_sd_rs2_addr; wire [ 4 : 0] spec_insn_sd_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sd_csr_misa_rmask; `endif rvfi_insn_sd insn_sd ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sd_csr_misa_rmask), `endif .spec_valid(spec_insn_sd_valid), .spec_trap(spec_insn_sd_trap), .spec_rs1_addr(spec_insn_sd_rs1_addr), .spec_rs2_addr(spec_insn_sd_rs2_addr), .spec_rd_addr(spec_insn_sd_rd_addr), .spec_rd_wdata(spec_insn_sd_rd_wdata), .spec_pc_wdata(spec_insn_sd_pc_wdata), .spec_mem_addr(spec_insn_sd_mem_addr), .spec_mem_rmask(spec_insn_sd_mem_rmask), .spec_mem_wmask(spec_insn_sd_mem_wmask), .spec_mem_wdata(spec_insn_sd_mem_wdata) ); wire spec_insn_sh_valid; wire spec_insn_sh_trap; wire [ 4 : 0] spec_insn_sh_rs1_addr; wire [ 4 : 0] spec_insn_sh_rs2_addr; wire [ 4 : 0] spec_insn_sh_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sh_csr_misa_rmask; `endif rvfi_insn_sh insn_sh ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask), `endif .spec_valid(spec_insn_sh_valid), .spec_trap(spec_insn_sh_trap), .spec_rs1_addr(spec_insn_sh_rs1_addr), .spec_rs2_addr(spec_insn_sh_rs2_addr), .spec_rd_addr(spec_insn_sh_rd_addr), .spec_rd_wdata(spec_insn_sh_rd_wdata), .spec_pc_wdata(spec_insn_sh_pc_wdata), .spec_mem_addr(spec_insn_sh_mem_addr), .spec_mem_rmask(spec_insn_sh_mem_rmask), .spec_mem_wmask(spec_insn_sh_mem_wmask), .spec_mem_wdata(spec_insn_sh_mem_wdata) ); wire spec_insn_sll_valid; wire spec_insn_sll_trap; wire [ 4 : 0] spec_insn_sll_rs1_addr; wire [ 4 : 0] spec_insn_sll_rs2_addr; wire [ 4 : 0] spec_insn_sll_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sll_csr_misa_rmask; `endif rvfi_insn_sll insn_sll ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask), `endif .spec_valid(spec_insn_sll_valid), .spec_trap(spec_insn_sll_trap), .spec_rs1_addr(spec_insn_sll_rs1_addr), .spec_rs2_addr(spec_insn_sll_rs2_addr), .spec_rd_addr(spec_insn_sll_rd_addr), .spec_rd_wdata(spec_insn_sll_rd_wdata), .spec_pc_wdata(spec_insn_sll_pc_wdata), .spec_mem_addr(spec_insn_sll_mem_addr), .spec_mem_rmask(spec_insn_sll_mem_rmask), .spec_mem_wmask(spec_insn_sll_mem_wmask), .spec_mem_wdata(spec_insn_sll_mem_wdata) ); wire spec_insn_slli_valid; wire spec_insn_slli_trap; wire [ 4 : 0] spec_insn_slli_rs1_addr; wire [ 4 : 0] spec_insn_slli_rs2_addr; wire [ 4 : 0] spec_insn_slli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slli_csr_misa_rmask; `endif rvfi_insn_slli insn_slli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask), `endif .spec_valid(spec_insn_slli_valid), .spec_trap(spec_insn_slli_trap), .spec_rs1_addr(spec_insn_slli_rs1_addr), .spec_rs2_addr(spec_insn_slli_rs2_addr), .spec_rd_addr(spec_insn_slli_rd_addr), .spec_rd_wdata(spec_insn_slli_rd_wdata), .spec_pc_wdata(spec_insn_slli_pc_wdata), .spec_mem_addr(spec_insn_slli_mem_addr), .spec_mem_rmask(spec_insn_slli_mem_rmask), .spec_mem_wmask(spec_insn_slli_mem_wmask), .spec_mem_wdata(spec_insn_slli_mem_wdata) ); wire spec_insn_slliw_valid; wire spec_insn_slliw_trap; wire [ 4 : 0] spec_insn_slliw_rs1_addr; wire [ 4 : 0] spec_insn_slliw_rs2_addr; wire [ 4 : 0] spec_insn_slliw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slliw_csr_misa_rmask; `endif rvfi_insn_slliw insn_slliw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slliw_csr_misa_rmask), `endif .spec_valid(spec_insn_slliw_valid), .spec_trap(spec_insn_slliw_trap), .spec_rs1_addr(spec_insn_slliw_rs1_addr), .spec_rs2_addr(spec_insn_slliw_rs2_addr), .spec_rd_addr(spec_insn_slliw_rd_addr), .spec_rd_wdata(spec_insn_slliw_rd_wdata), .spec_pc_wdata(spec_insn_slliw_pc_wdata), .spec_mem_addr(spec_insn_slliw_mem_addr), .spec_mem_rmask(spec_insn_slliw_mem_rmask), .spec_mem_wmask(spec_insn_slliw_mem_wmask), .spec_mem_wdata(spec_insn_slliw_mem_wdata) ); wire spec_insn_sllw_valid; wire spec_insn_sllw_trap; wire [ 4 : 0] spec_insn_sllw_rs1_addr; wire [ 4 : 0] spec_insn_sllw_rs2_addr; wire [ 4 : 0] spec_insn_sllw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sllw_csr_misa_rmask; `endif rvfi_insn_sllw insn_sllw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sllw_csr_misa_rmask), `endif .spec_valid(spec_insn_sllw_valid), .spec_trap(spec_insn_sllw_trap), .spec_rs1_addr(spec_insn_sllw_rs1_addr), .spec_rs2_addr(spec_insn_sllw_rs2_addr), .spec_rd_addr(spec_insn_sllw_rd_addr), .spec_rd_wdata(spec_insn_sllw_rd_wdata), .spec_pc_wdata(spec_insn_sllw_pc_wdata), .spec_mem_addr(spec_insn_sllw_mem_addr), .spec_mem_rmask(spec_insn_sllw_mem_rmask), .spec_mem_wmask(spec_insn_sllw_mem_wmask), .spec_mem_wdata(spec_insn_sllw_mem_wdata) ); wire spec_insn_slt_valid; wire spec_insn_slt_trap; wire [ 4 : 0] spec_insn_slt_rs1_addr; wire [ 4 : 0] spec_insn_slt_rs2_addr; wire [ 4 : 0] spec_insn_slt_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slt_csr_misa_rmask; `endif rvfi_insn_slt insn_slt ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask), `endif .spec_valid(spec_insn_slt_valid), .spec_trap(spec_insn_slt_trap), .spec_rs1_addr(spec_insn_slt_rs1_addr), .spec_rs2_addr(spec_insn_slt_rs2_addr), .spec_rd_addr(spec_insn_slt_rd_addr), .spec_rd_wdata(spec_insn_slt_rd_wdata), .spec_pc_wdata(spec_insn_slt_pc_wdata), .spec_mem_addr(spec_insn_slt_mem_addr), .spec_mem_rmask(spec_insn_slt_mem_rmask), .spec_mem_wmask(spec_insn_slt_mem_wmask), .spec_mem_wdata(spec_insn_slt_mem_wdata) ); wire spec_insn_slti_valid; wire spec_insn_slti_trap; wire [ 4 : 0] spec_insn_slti_rs1_addr; wire [ 4 : 0] spec_insn_slti_rs2_addr; wire [ 4 : 0] spec_insn_slti_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_slti_csr_misa_rmask; `endif rvfi_insn_slti insn_slti ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask), `endif .spec_valid(spec_insn_slti_valid), .spec_trap(spec_insn_slti_trap), .spec_rs1_addr(spec_insn_slti_rs1_addr), .spec_rs2_addr(spec_insn_slti_rs2_addr), .spec_rd_addr(spec_insn_slti_rd_addr), .spec_rd_wdata(spec_insn_slti_rd_wdata), .spec_pc_wdata(spec_insn_slti_pc_wdata), .spec_mem_addr(spec_insn_slti_mem_addr), .spec_mem_rmask(spec_insn_slti_mem_rmask), .spec_mem_wmask(spec_insn_slti_mem_wmask), .spec_mem_wdata(spec_insn_slti_mem_wdata) ); wire spec_insn_sltiu_valid; wire spec_insn_sltiu_trap; wire [ 4 : 0] spec_insn_sltiu_rs1_addr; wire [ 4 : 0] spec_insn_sltiu_rs2_addr; wire [ 4 : 0] spec_insn_sltiu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltiu_csr_misa_rmask; `endif rvfi_insn_sltiu insn_sltiu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltiu_valid), .spec_trap(spec_insn_sltiu_trap), .spec_rs1_addr(spec_insn_sltiu_rs1_addr), .spec_rs2_addr(spec_insn_sltiu_rs2_addr), .spec_rd_addr(spec_insn_sltiu_rd_addr), .spec_rd_wdata(spec_insn_sltiu_rd_wdata), .spec_pc_wdata(spec_insn_sltiu_pc_wdata), .spec_mem_addr(spec_insn_sltiu_mem_addr), .spec_mem_rmask(spec_insn_sltiu_mem_rmask), .spec_mem_wmask(spec_insn_sltiu_mem_wmask), .spec_mem_wdata(spec_insn_sltiu_mem_wdata) ); wire spec_insn_sltu_valid; wire spec_insn_sltu_trap; wire [ 4 : 0] spec_insn_sltu_rs1_addr; wire [ 4 : 0] spec_insn_sltu_rs2_addr; wire [ 4 : 0] spec_insn_sltu_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sltu_csr_misa_rmask; `endif rvfi_insn_sltu insn_sltu ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask), `endif .spec_valid(spec_insn_sltu_valid), .spec_trap(spec_insn_sltu_trap), .spec_rs1_addr(spec_insn_sltu_rs1_addr), .spec_rs2_addr(spec_insn_sltu_rs2_addr), .spec_rd_addr(spec_insn_sltu_rd_addr), .spec_rd_wdata(spec_insn_sltu_rd_wdata), .spec_pc_wdata(spec_insn_sltu_pc_wdata), .spec_mem_addr(spec_insn_sltu_mem_addr), .spec_mem_rmask(spec_insn_sltu_mem_rmask), .spec_mem_wmask(spec_insn_sltu_mem_wmask), .spec_mem_wdata(spec_insn_sltu_mem_wdata) ); wire spec_insn_sra_valid; wire spec_insn_sra_trap; wire [ 4 : 0] spec_insn_sra_rs1_addr; wire [ 4 : 0] spec_insn_sra_rs2_addr; wire [ 4 : 0] spec_insn_sra_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sra_csr_misa_rmask; `endif rvfi_insn_sra insn_sra ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask), `endif .spec_valid(spec_insn_sra_valid), .spec_trap(spec_insn_sra_trap), .spec_rs1_addr(spec_insn_sra_rs1_addr), .spec_rs2_addr(spec_insn_sra_rs2_addr), .spec_rd_addr(spec_insn_sra_rd_addr), .spec_rd_wdata(spec_insn_sra_rd_wdata), .spec_pc_wdata(spec_insn_sra_pc_wdata), .spec_mem_addr(spec_insn_sra_mem_addr), .spec_mem_rmask(spec_insn_sra_mem_rmask), .spec_mem_wmask(spec_insn_sra_mem_wmask), .spec_mem_wdata(spec_insn_sra_mem_wdata) ); wire spec_insn_srai_valid; wire spec_insn_srai_trap; wire [ 4 : 0] spec_insn_srai_rs1_addr; wire [ 4 : 0] spec_insn_srai_rs2_addr; wire [ 4 : 0] spec_insn_srai_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srai_csr_misa_rmask; `endif rvfi_insn_srai insn_srai ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask), `endif .spec_valid(spec_insn_srai_valid), .spec_trap(spec_insn_srai_trap), .spec_rs1_addr(spec_insn_srai_rs1_addr), .spec_rs2_addr(spec_insn_srai_rs2_addr), .spec_rd_addr(spec_insn_srai_rd_addr), .spec_rd_wdata(spec_insn_srai_rd_wdata), .spec_pc_wdata(spec_insn_srai_pc_wdata), .spec_mem_addr(spec_insn_srai_mem_addr), .spec_mem_rmask(spec_insn_srai_mem_rmask), .spec_mem_wmask(spec_insn_srai_mem_wmask), .spec_mem_wdata(spec_insn_srai_mem_wdata) ); wire spec_insn_sraiw_valid; wire spec_insn_sraiw_trap; wire [ 4 : 0] spec_insn_sraiw_rs1_addr; wire [ 4 : 0] spec_insn_sraiw_rs2_addr; wire [ 4 : 0] spec_insn_sraiw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraiw_csr_misa_rmask; `endif rvfi_insn_sraiw insn_sraiw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sraiw_csr_misa_rmask), `endif .spec_valid(spec_insn_sraiw_valid), .spec_trap(spec_insn_sraiw_trap), .spec_rs1_addr(spec_insn_sraiw_rs1_addr), .spec_rs2_addr(spec_insn_sraiw_rs2_addr), .spec_rd_addr(spec_insn_sraiw_rd_addr), .spec_rd_wdata(spec_insn_sraiw_rd_wdata), .spec_pc_wdata(spec_insn_sraiw_pc_wdata), .spec_mem_addr(spec_insn_sraiw_mem_addr), .spec_mem_rmask(spec_insn_sraiw_mem_rmask), .spec_mem_wmask(spec_insn_sraiw_mem_wmask), .spec_mem_wdata(spec_insn_sraiw_mem_wdata) ); wire spec_insn_sraw_valid; wire spec_insn_sraw_trap; wire [ 4 : 0] spec_insn_sraw_rs1_addr; wire [ 4 : 0] spec_insn_sraw_rs2_addr; wire [ 4 : 0] spec_insn_sraw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sraw_csr_misa_rmask; `endif rvfi_insn_sraw insn_sraw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sraw_csr_misa_rmask), `endif .spec_valid(spec_insn_sraw_valid), .spec_trap(spec_insn_sraw_trap), .spec_rs1_addr(spec_insn_sraw_rs1_addr), .spec_rs2_addr(spec_insn_sraw_rs2_addr), .spec_rd_addr(spec_insn_sraw_rd_addr), .spec_rd_wdata(spec_insn_sraw_rd_wdata), .spec_pc_wdata(spec_insn_sraw_pc_wdata), .spec_mem_addr(spec_insn_sraw_mem_addr), .spec_mem_rmask(spec_insn_sraw_mem_rmask), .spec_mem_wmask(spec_insn_sraw_mem_wmask), .spec_mem_wdata(spec_insn_sraw_mem_wdata) ); wire spec_insn_srl_valid; wire spec_insn_srl_trap; wire [ 4 : 0] spec_insn_srl_rs1_addr; wire [ 4 : 0] spec_insn_srl_rs2_addr; wire [ 4 : 0] spec_insn_srl_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srl_csr_misa_rmask; `endif rvfi_insn_srl insn_srl ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask), `endif .spec_valid(spec_insn_srl_valid), .spec_trap(spec_insn_srl_trap), .spec_rs1_addr(spec_insn_srl_rs1_addr), .spec_rs2_addr(spec_insn_srl_rs2_addr), .spec_rd_addr(spec_insn_srl_rd_addr), .spec_rd_wdata(spec_insn_srl_rd_wdata), .spec_pc_wdata(spec_insn_srl_pc_wdata), .spec_mem_addr(spec_insn_srl_mem_addr), .spec_mem_rmask(spec_insn_srl_mem_rmask), .spec_mem_wmask(spec_insn_srl_mem_wmask), .spec_mem_wdata(spec_insn_srl_mem_wdata) ); wire spec_insn_srli_valid; wire spec_insn_srli_trap; wire [ 4 : 0] spec_insn_srli_rs1_addr; wire [ 4 : 0] spec_insn_srli_rs2_addr; wire [ 4 : 0] spec_insn_srli_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srli_csr_misa_rmask; `endif rvfi_insn_srli insn_srli ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask), `endif .spec_valid(spec_insn_srli_valid), .spec_trap(spec_insn_srli_trap), .spec_rs1_addr(spec_insn_srli_rs1_addr), .spec_rs2_addr(spec_insn_srli_rs2_addr), .spec_rd_addr(spec_insn_srli_rd_addr), .spec_rd_wdata(spec_insn_srli_rd_wdata), .spec_pc_wdata(spec_insn_srli_pc_wdata), .spec_mem_addr(spec_insn_srli_mem_addr), .spec_mem_rmask(spec_insn_srli_mem_rmask), .spec_mem_wmask(spec_insn_srli_mem_wmask), .spec_mem_wdata(spec_insn_srli_mem_wdata) ); wire spec_insn_srliw_valid; wire spec_insn_srliw_trap; wire [ 4 : 0] spec_insn_srliw_rs1_addr; wire [ 4 : 0] spec_insn_srliw_rs2_addr; wire [ 4 : 0] spec_insn_srliw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srliw_csr_misa_rmask; `endif rvfi_insn_srliw insn_srliw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srliw_csr_misa_rmask), `endif .spec_valid(spec_insn_srliw_valid), .spec_trap(spec_insn_srliw_trap), .spec_rs1_addr(spec_insn_srliw_rs1_addr), .spec_rs2_addr(spec_insn_srliw_rs2_addr), .spec_rd_addr(spec_insn_srliw_rd_addr), .spec_rd_wdata(spec_insn_srliw_rd_wdata), .spec_pc_wdata(spec_insn_srliw_pc_wdata), .spec_mem_addr(spec_insn_srliw_mem_addr), .spec_mem_rmask(spec_insn_srliw_mem_rmask), .spec_mem_wmask(spec_insn_srliw_mem_wmask), .spec_mem_wdata(spec_insn_srliw_mem_wdata) ); wire spec_insn_srlw_valid; wire spec_insn_srlw_trap; wire [ 4 : 0] spec_insn_srlw_rs1_addr; wire [ 4 : 0] spec_insn_srlw_rs2_addr; wire [ 4 : 0] spec_insn_srlw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_srlw_csr_misa_rmask; `endif rvfi_insn_srlw insn_srlw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_srlw_csr_misa_rmask), `endif .spec_valid(spec_insn_srlw_valid), .spec_trap(spec_insn_srlw_trap), .spec_rs1_addr(spec_insn_srlw_rs1_addr), .spec_rs2_addr(spec_insn_srlw_rs2_addr), .spec_rd_addr(spec_insn_srlw_rd_addr), .spec_rd_wdata(spec_insn_srlw_rd_wdata), .spec_pc_wdata(spec_insn_srlw_pc_wdata), .spec_mem_addr(spec_insn_srlw_mem_addr), .spec_mem_rmask(spec_insn_srlw_mem_rmask), .spec_mem_wmask(spec_insn_srlw_mem_wmask), .spec_mem_wdata(spec_insn_srlw_mem_wdata) ); wire spec_insn_sub_valid; wire spec_insn_sub_trap; wire [ 4 : 0] spec_insn_sub_rs1_addr; wire [ 4 : 0] spec_insn_sub_rs2_addr; wire [ 4 : 0] spec_insn_sub_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sub_csr_misa_rmask; `endif rvfi_insn_sub insn_sub ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask), `endif .spec_valid(spec_insn_sub_valid), .spec_trap(spec_insn_sub_trap), .spec_rs1_addr(spec_insn_sub_rs1_addr), .spec_rs2_addr(spec_insn_sub_rs2_addr), .spec_rd_addr(spec_insn_sub_rd_addr), .spec_rd_wdata(spec_insn_sub_rd_wdata), .spec_pc_wdata(spec_insn_sub_pc_wdata), .spec_mem_addr(spec_insn_sub_mem_addr), .spec_mem_rmask(spec_insn_sub_mem_rmask), .spec_mem_wmask(spec_insn_sub_mem_wmask), .spec_mem_wdata(spec_insn_sub_mem_wdata) ); wire spec_insn_subw_valid; wire spec_insn_subw_trap; wire [ 4 : 0] spec_insn_subw_rs1_addr; wire [ 4 : 0] spec_insn_subw_rs2_addr; wire [ 4 : 0] spec_insn_subw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_subw_csr_misa_rmask; `endif rvfi_insn_subw insn_subw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_subw_csr_misa_rmask), `endif .spec_valid(spec_insn_subw_valid), .spec_trap(spec_insn_subw_trap), .spec_rs1_addr(spec_insn_subw_rs1_addr), .spec_rs2_addr(spec_insn_subw_rs2_addr), .spec_rd_addr(spec_insn_subw_rd_addr), .spec_rd_wdata(spec_insn_subw_rd_wdata), .spec_pc_wdata(spec_insn_subw_pc_wdata), .spec_mem_addr(spec_insn_subw_mem_addr), .spec_mem_rmask(spec_insn_subw_mem_rmask), .spec_mem_wmask(spec_insn_subw_mem_wmask), .spec_mem_wdata(spec_insn_subw_mem_wdata) ); wire spec_insn_sw_valid; wire spec_insn_sw_trap; wire [ 4 : 0] spec_insn_sw_rs1_addr; wire [ 4 : 0] spec_insn_sw_rs2_addr; wire [ 4 : 0] spec_insn_sw_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_sw_csr_misa_rmask; `endif rvfi_insn_sw insn_sw ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask), `endif .spec_valid(spec_insn_sw_valid), .spec_trap(spec_insn_sw_trap), .spec_rs1_addr(spec_insn_sw_rs1_addr), .spec_rs2_addr(spec_insn_sw_rs2_addr), .spec_rd_addr(spec_insn_sw_rd_addr), .spec_rd_wdata(spec_insn_sw_rd_wdata), .spec_pc_wdata(spec_insn_sw_pc_wdata), .spec_mem_addr(spec_insn_sw_mem_addr), .spec_mem_rmask(spec_insn_sw_mem_rmask), .spec_mem_wmask(spec_insn_sw_mem_wmask), .spec_mem_wdata(spec_insn_sw_mem_wdata) ); wire spec_insn_xor_valid; wire spec_insn_xor_trap; wire [ 4 : 0] spec_insn_xor_rs1_addr; wire [ 4 : 0] spec_insn_xor_rs2_addr; wire [ 4 : 0] spec_insn_xor_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xor_csr_misa_rmask; `endif rvfi_insn_xor insn_xor ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask), `endif .spec_valid(spec_insn_xor_valid), .spec_trap(spec_insn_xor_trap), .spec_rs1_addr(spec_insn_xor_rs1_addr), .spec_rs2_addr(spec_insn_xor_rs2_addr), .spec_rd_addr(spec_insn_xor_rd_addr), .spec_rd_wdata(spec_insn_xor_rd_wdata), .spec_pc_wdata(spec_insn_xor_pc_wdata), .spec_mem_addr(spec_insn_xor_mem_addr), .spec_mem_rmask(spec_insn_xor_mem_rmask), .spec_mem_wmask(spec_insn_xor_mem_wmask), .spec_mem_wdata(spec_insn_xor_mem_wdata) ); wire spec_insn_xori_valid; wire spec_insn_xori_trap; wire [ 4 : 0] spec_insn_xori_rs1_addr; wire [ 4 : 0] spec_insn_xori_rs2_addr; wire [ 4 : 0] spec_insn_xori_rd_addr; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_rd_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_pc_wdata; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_addr; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask; wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask; wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_mem_wdata; `ifdef RISCV_FORMAL_CSR_MISA wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_insn_xori_csr_misa_rmask; `endif rvfi_insn_xori insn_xori ( .rvfi_valid(rvfi_valid), .rvfi_insn(rvfi_insn), .rvfi_pc_rdata(rvfi_pc_rdata), .rvfi_rs1_rdata(rvfi_rs1_rdata), .rvfi_rs2_rdata(rvfi_rs2_rdata), .rvfi_mem_rdata(rvfi_mem_rdata), `ifdef RISCV_FORMAL_CSR_MISA .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata), .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask), `endif .spec_valid(spec_insn_xori_valid), .spec_trap(spec_insn_xori_trap), .spec_rs1_addr(spec_insn_xori_rs1_addr), .spec_rs2_addr(spec_insn_xori_rs2_addr), .spec_rd_addr(spec_insn_xori_rd_addr), .spec_rd_wdata(spec_insn_xori_rd_wdata), .spec_pc_wdata(spec_insn_xori_pc_wdata), .spec_mem_addr(spec_insn_xori_mem_addr), .spec_mem_rmask(spec_insn_xori_mem_rmask), .spec_mem_wmask(spec_insn_xori_mem_wmask), .spec_mem_wdata(spec_insn_xori_mem_wdata) ); assign spec_valid = spec_insn_add_valid ? spec_insn_add_valid : spec_insn_addi_valid ? spec_insn_addi_valid : spec_insn_addiw_valid ? spec_insn_addiw_valid : spec_insn_addw_valid ? spec_insn_addw_valid : spec_insn_and_valid ? spec_insn_and_valid : spec_insn_andi_valid ? spec_insn_andi_valid : spec_insn_auipc_valid ? spec_insn_auipc_valid : spec_insn_beq_valid ? spec_insn_beq_valid : spec_insn_bge_valid ? spec_insn_bge_valid : spec_insn_bgeu_valid ? spec_insn_bgeu_valid : spec_insn_blt_valid ? spec_insn_blt_valid : spec_insn_bltu_valid ? spec_insn_bltu_valid : spec_insn_bne_valid ? spec_insn_bne_valid : spec_insn_c_add_valid ? spec_insn_c_add_valid : spec_insn_c_addi_valid ? spec_insn_c_addi_valid : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_valid : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_valid : spec_insn_c_addiw_valid ? spec_insn_c_addiw_valid : spec_insn_c_addw_valid ? spec_insn_c_addw_valid : spec_insn_c_and_valid ? spec_insn_c_and_valid : spec_insn_c_andi_valid ? spec_insn_c_andi_valid : spec_insn_c_beqz_valid ? spec_insn_c_beqz_valid : spec_insn_c_bnez_valid ? spec_insn_c_bnez_valid : spec_insn_c_j_valid ? spec_insn_c_j_valid : spec_insn_c_jalr_valid ? spec_insn_c_jalr_valid : spec_insn_c_jr_valid ? spec_insn_c_jr_valid : spec_insn_c_ld_valid ? spec_insn_c_ld_valid : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_valid : spec_insn_c_li_valid ? spec_insn_c_li_valid : spec_insn_c_lui_valid ? spec_insn_c_lui_valid : spec_insn_c_lw_valid ? spec_insn_c_lw_valid : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_valid : spec_insn_c_mv_valid ? spec_insn_c_mv_valid : spec_insn_c_or_valid ? spec_insn_c_or_valid : spec_insn_c_sd_valid ? spec_insn_c_sd_valid : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_valid : spec_insn_c_slli_valid ? spec_insn_c_slli_valid : spec_insn_c_srai_valid ? spec_insn_c_srai_valid : spec_insn_c_srli_valid ? spec_insn_c_srli_valid : spec_insn_c_sub_valid ? spec_insn_c_sub_valid : spec_insn_c_subw_valid ? spec_insn_c_subw_valid : spec_insn_c_sw_valid ? spec_insn_c_sw_valid : spec_insn_c_swsp_valid ? spec_insn_c_swsp_valid : spec_insn_c_xor_valid ? spec_insn_c_xor_valid : spec_insn_div_valid ? spec_insn_div_valid : spec_insn_divu_valid ? spec_insn_divu_valid : spec_insn_divuw_valid ? spec_insn_divuw_valid : spec_insn_divw_valid ? spec_insn_divw_valid : spec_insn_jal_valid ? spec_insn_jal_valid : spec_insn_jalr_valid ? spec_insn_jalr_valid : spec_insn_lb_valid ? spec_insn_lb_valid : spec_insn_lbu_valid ? spec_insn_lbu_valid : spec_insn_ld_valid ? spec_insn_ld_valid : spec_insn_lh_valid ? spec_insn_lh_valid : spec_insn_lhu_valid ? spec_insn_lhu_valid : spec_insn_lui_valid ? spec_insn_lui_valid : spec_insn_lw_valid ? spec_insn_lw_valid : spec_insn_lwu_valid ? spec_insn_lwu_valid : spec_insn_mul_valid ? spec_insn_mul_valid : spec_insn_mulh_valid ? spec_insn_mulh_valid : spec_insn_mulhsu_valid ? spec_insn_mulhsu_valid : spec_insn_mulhu_valid ? spec_insn_mulhu_valid : spec_insn_mulw_valid ? spec_insn_mulw_valid : spec_insn_or_valid ? spec_insn_or_valid : spec_insn_ori_valid ? spec_insn_ori_valid : spec_insn_rem_valid ? spec_insn_rem_valid : spec_insn_remu_valid ? spec_insn_remu_valid : spec_insn_remuw_valid ? spec_insn_remuw_valid : spec_insn_remw_valid ? spec_insn_remw_valid : spec_insn_sb_valid ? spec_insn_sb_valid : spec_insn_sd_valid ? spec_insn_sd_valid : spec_insn_sh_valid ? spec_insn_sh_valid : spec_insn_sll_valid ? spec_insn_sll_valid : spec_insn_slli_valid ? spec_insn_slli_valid : spec_insn_slliw_valid ? spec_insn_slliw_valid : spec_insn_sllw_valid ? spec_insn_sllw_valid : spec_insn_slt_valid ? spec_insn_slt_valid : spec_insn_slti_valid ? spec_insn_slti_valid : spec_insn_sltiu_valid ? spec_insn_sltiu_valid : spec_insn_sltu_valid ? spec_insn_sltu_valid : spec_insn_sra_valid ? spec_insn_sra_valid : spec_insn_srai_valid ? spec_insn_srai_valid : spec_insn_sraiw_valid ? spec_insn_sraiw_valid : spec_insn_sraw_valid ? spec_insn_sraw_valid : spec_insn_srl_valid ? spec_insn_srl_valid : spec_insn_srli_valid ? spec_insn_srli_valid : spec_insn_srliw_valid ? spec_insn_srliw_valid : spec_insn_srlw_valid ? spec_insn_srlw_valid : spec_insn_sub_valid ? spec_insn_sub_valid : spec_insn_subw_valid ? spec_insn_subw_valid : spec_insn_sw_valid ? spec_insn_sw_valid : spec_insn_xor_valid ? spec_insn_xor_valid : spec_insn_xori_valid ? spec_insn_xori_valid : 0; assign spec_trap = spec_insn_add_valid ? spec_insn_add_trap : spec_insn_addi_valid ? spec_insn_addi_trap : spec_insn_addiw_valid ? spec_insn_addiw_trap : spec_insn_addw_valid ? spec_insn_addw_trap : spec_insn_and_valid ? spec_insn_and_trap : spec_insn_andi_valid ? spec_insn_andi_trap : spec_insn_auipc_valid ? spec_insn_auipc_trap : spec_insn_beq_valid ? spec_insn_beq_trap : spec_insn_bge_valid ? spec_insn_bge_trap : spec_insn_bgeu_valid ? spec_insn_bgeu_trap : spec_insn_blt_valid ? spec_insn_blt_trap : spec_insn_bltu_valid ? spec_insn_bltu_trap : spec_insn_bne_valid ? spec_insn_bne_trap : spec_insn_c_add_valid ? spec_insn_c_add_trap : spec_insn_c_addi_valid ? spec_insn_c_addi_trap : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_trap : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_trap : spec_insn_c_addiw_valid ? spec_insn_c_addiw_trap : spec_insn_c_addw_valid ? spec_insn_c_addw_trap : spec_insn_c_and_valid ? spec_insn_c_and_trap : spec_insn_c_andi_valid ? spec_insn_c_andi_trap : spec_insn_c_beqz_valid ? spec_insn_c_beqz_trap : spec_insn_c_bnez_valid ? spec_insn_c_bnez_trap : spec_insn_c_j_valid ? spec_insn_c_j_trap : spec_insn_c_jalr_valid ? spec_insn_c_jalr_trap : spec_insn_c_jr_valid ? spec_insn_c_jr_trap : spec_insn_c_ld_valid ? spec_insn_c_ld_trap : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_trap : spec_insn_c_li_valid ? spec_insn_c_li_trap : spec_insn_c_lui_valid ? spec_insn_c_lui_trap : spec_insn_c_lw_valid ? spec_insn_c_lw_trap : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_trap : spec_insn_c_mv_valid ? spec_insn_c_mv_trap : spec_insn_c_or_valid ? spec_insn_c_or_trap : spec_insn_c_sd_valid ? spec_insn_c_sd_trap : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_trap : spec_insn_c_slli_valid ? spec_insn_c_slli_trap : spec_insn_c_srai_valid ? spec_insn_c_srai_trap : spec_insn_c_srli_valid ? spec_insn_c_srli_trap : spec_insn_c_sub_valid ? spec_insn_c_sub_trap : spec_insn_c_subw_valid ? spec_insn_c_subw_trap : spec_insn_c_sw_valid ? spec_insn_c_sw_trap : spec_insn_c_swsp_valid ? spec_insn_c_swsp_trap : spec_insn_c_xor_valid ? spec_insn_c_xor_trap : spec_insn_div_valid ? spec_insn_div_trap : spec_insn_divu_valid ? spec_insn_divu_trap : spec_insn_divuw_valid ? spec_insn_divuw_trap : spec_insn_divw_valid ? spec_insn_divw_trap : spec_insn_jal_valid ? spec_insn_jal_trap : spec_insn_jalr_valid ? spec_insn_jalr_trap : spec_insn_lb_valid ? spec_insn_lb_trap : spec_insn_lbu_valid ? spec_insn_lbu_trap : spec_insn_ld_valid ? spec_insn_ld_trap : spec_insn_lh_valid ? spec_insn_lh_trap : spec_insn_lhu_valid ? spec_insn_lhu_trap : spec_insn_lui_valid ? spec_insn_lui_trap : spec_insn_lw_valid ? spec_insn_lw_trap : spec_insn_lwu_valid ? spec_insn_lwu_trap : spec_insn_mul_valid ? spec_insn_mul_trap : spec_insn_mulh_valid ? spec_insn_mulh_trap : spec_insn_mulhsu_valid ? spec_insn_mulhsu_trap : spec_insn_mulhu_valid ? spec_insn_mulhu_trap : spec_insn_mulw_valid ? spec_insn_mulw_trap : spec_insn_or_valid ? spec_insn_or_trap : spec_insn_ori_valid ? spec_insn_ori_trap : spec_insn_rem_valid ? spec_insn_rem_trap : spec_insn_remu_valid ? spec_insn_remu_trap : spec_insn_remuw_valid ? spec_insn_remuw_trap : spec_insn_remw_valid ? spec_insn_remw_trap : spec_insn_sb_valid ? spec_insn_sb_trap : spec_insn_sd_valid ? spec_insn_sd_trap : spec_insn_sh_valid ? spec_insn_sh_trap : spec_insn_sll_valid ? spec_insn_sll_trap : spec_insn_slli_valid ? spec_insn_slli_trap : spec_insn_slliw_valid ? spec_insn_slliw_trap : spec_insn_sllw_valid ? spec_insn_sllw_trap : spec_insn_slt_valid ? spec_insn_slt_trap : spec_insn_slti_valid ? spec_insn_slti_trap : spec_insn_sltiu_valid ? spec_insn_sltiu_trap : spec_insn_sltu_valid ? spec_insn_sltu_trap : spec_insn_sra_valid ? spec_insn_sra_trap : spec_insn_srai_valid ? spec_insn_srai_trap : spec_insn_sraiw_valid ? spec_insn_sraiw_trap : spec_insn_sraw_valid ? spec_insn_sraw_trap : spec_insn_srl_valid ? spec_insn_srl_trap : spec_insn_srli_valid ? spec_insn_srli_trap : spec_insn_srliw_valid ? spec_insn_srliw_trap : spec_insn_srlw_valid ? spec_insn_srlw_trap : spec_insn_sub_valid ? spec_insn_sub_trap : spec_insn_subw_valid ? spec_insn_subw_trap : spec_insn_sw_valid ? spec_insn_sw_trap : spec_insn_xor_valid ? spec_insn_xor_trap : spec_insn_xori_valid ? spec_insn_xori_trap : 0; assign spec_rs1_addr = spec_insn_add_valid ? spec_insn_add_rs1_addr : spec_insn_addi_valid ? spec_insn_addi_rs1_addr : spec_insn_addiw_valid ? spec_insn_addiw_rs1_addr : spec_insn_addw_valid ? spec_insn_addw_rs1_addr : spec_insn_and_valid ? spec_insn_and_rs1_addr : spec_insn_andi_valid ? spec_insn_andi_rs1_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs1_addr : spec_insn_beq_valid ? spec_insn_beq_rs1_addr : spec_insn_bge_valid ? spec_insn_bge_rs1_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr : spec_insn_blt_valid ? spec_insn_blt_rs1_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs1_addr : spec_insn_bne_valid ? spec_insn_bne_rs1_addr : spec_insn_c_add_valid ? spec_insn_c_add_rs1_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_rs1_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs1_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs1_addr : spec_insn_c_addiw_valid ? spec_insn_c_addiw_rs1_addr : spec_insn_c_addw_valid ? spec_insn_c_addw_rs1_addr : spec_insn_c_and_valid ? spec_insn_c_and_rs1_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_rs1_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rs1_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rs1_addr : spec_insn_c_j_valid ? spec_insn_c_j_rs1_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rs1_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_rs1_addr : spec_insn_c_ld_valid ? spec_insn_c_ld_rs1_addr : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rs1_addr : spec_insn_c_li_valid ? spec_insn_c_li_rs1_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_rs1_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_rs1_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs1_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_rs1_addr : spec_insn_c_or_valid ? spec_insn_c_or_rs1_addr : spec_insn_c_sd_valid ? spec_insn_c_sd_rs1_addr : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rs1_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_rs1_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_rs1_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_rs1_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_rs1_addr : spec_insn_c_subw_valid ? spec_insn_c_subw_rs1_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_rs1_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rs1_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_rs1_addr : spec_insn_div_valid ? spec_insn_div_rs1_addr : spec_insn_divu_valid ? spec_insn_divu_rs1_addr : spec_insn_divuw_valid ? spec_insn_divuw_rs1_addr : spec_insn_divw_valid ? spec_insn_divw_rs1_addr : spec_insn_jal_valid ? spec_insn_jal_rs1_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs1_addr : spec_insn_lb_valid ? spec_insn_lb_rs1_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs1_addr : spec_insn_ld_valid ? spec_insn_ld_rs1_addr : spec_insn_lh_valid ? spec_insn_lh_rs1_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs1_addr : spec_insn_lui_valid ? spec_insn_lui_rs1_addr : spec_insn_lw_valid ? spec_insn_lw_rs1_addr : spec_insn_lwu_valid ? spec_insn_lwu_rs1_addr : spec_insn_mul_valid ? spec_insn_mul_rs1_addr : spec_insn_mulh_valid ? spec_insn_mulh_rs1_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rs1_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_rs1_addr : spec_insn_mulw_valid ? spec_insn_mulw_rs1_addr : spec_insn_or_valid ? spec_insn_or_rs1_addr : spec_insn_ori_valid ? spec_insn_ori_rs1_addr : spec_insn_rem_valid ? spec_insn_rem_rs1_addr : spec_insn_remu_valid ? spec_insn_remu_rs1_addr : spec_insn_remuw_valid ? spec_insn_remuw_rs1_addr : spec_insn_remw_valid ? spec_insn_remw_rs1_addr : spec_insn_sb_valid ? spec_insn_sb_rs1_addr : spec_insn_sd_valid ? spec_insn_sd_rs1_addr : spec_insn_sh_valid ? spec_insn_sh_rs1_addr : spec_insn_sll_valid ? spec_insn_sll_rs1_addr : spec_insn_slli_valid ? spec_insn_slli_rs1_addr : spec_insn_slliw_valid ? spec_insn_slliw_rs1_addr : spec_insn_sllw_valid ? spec_insn_sllw_rs1_addr : spec_insn_slt_valid ? spec_insn_slt_rs1_addr : spec_insn_slti_valid ? spec_insn_slti_rs1_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs1_addr : spec_insn_sra_valid ? spec_insn_sra_rs1_addr : spec_insn_srai_valid ? spec_insn_srai_rs1_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_rs1_addr : spec_insn_sraw_valid ? spec_insn_sraw_rs1_addr : spec_insn_srl_valid ? spec_insn_srl_rs1_addr : spec_insn_srli_valid ? spec_insn_srli_rs1_addr : spec_insn_srliw_valid ? spec_insn_srliw_rs1_addr : spec_insn_srlw_valid ? spec_insn_srlw_rs1_addr : spec_insn_sub_valid ? spec_insn_sub_rs1_addr : spec_insn_subw_valid ? spec_insn_subw_rs1_addr : spec_insn_sw_valid ? spec_insn_sw_rs1_addr : spec_insn_xor_valid ? spec_insn_xor_rs1_addr : spec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0; assign spec_rs2_addr = spec_insn_add_valid ? spec_insn_add_rs2_addr : spec_insn_addi_valid ? spec_insn_addi_rs2_addr : spec_insn_addiw_valid ? spec_insn_addiw_rs2_addr : spec_insn_addw_valid ? spec_insn_addw_rs2_addr : spec_insn_and_valid ? spec_insn_and_rs2_addr : spec_insn_andi_valid ? spec_insn_andi_rs2_addr : spec_insn_auipc_valid ? spec_insn_auipc_rs2_addr : spec_insn_beq_valid ? spec_insn_beq_rs2_addr : spec_insn_bge_valid ? spec_insn_bge_rs2_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr : spec_insn_blt_valid ? spec_insn_blt_rs2_addr : spec_insn_bltu_valid ? spec_insn_bltu_rs2_addr : spec_insn_bne_valid ? spec_insn_bne_rs2_addr : spec_insn_c_add_valid ? spec_insn_c_add_rs2_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_rs2_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs2_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs2_addr : spec_insn_c_addiw_valid ? spec_insn_c_addiw_rs2_addr : spec_insn_c_addw_valid ? spec_insn_c_addw_rs2_addr : spec_insn_c_and_valid ? spec_insn_c_and_rs2_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_rs2_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rs2_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rs2_addr : spec_insn_c_j_valid ? spec_insn_c_j_rs2_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rs2_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_rs2_addr : spec_insn_c_ld_valid ? spec_insn_c_ld_rs2_addr : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rs2_addr : spec_insn_c_li_valid ? spec_insn_c_li_rs2_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_rs2_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_rs2_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs2_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_rs2_addr : spec_insn_c_or_valid ? spec_insn_c_or_rs2_addr : spec_insn_c_sd_valid ? spec_insn_c_sd_rs2_addr : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rs2_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_rs2_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_rs2_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_rs2_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_rs2_addr : spec_insn_c_subw_valid ? spec_insn_c_subw_rs2_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_rs2_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rs2_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_rs2_addr : spec_insn_div_valid ? spec_insn_div_rs2_addr : spec_insn_divu_valid ? spec_insn_divu_rs2_addr : spec_insn_divuw_valid ? spec_insn_divuw_rs2_addr : spec_insn_divw_valid ? spec_insn_divw_rs2_addr : spec_insn_jal_valid ? spec_insn_jal_rs2_addr : spec_insn_jalr_valid ? spec_insn_jalr_rs2_addr : spec_insn_lb_valid ? spec_insn_lb_rs2_addr : spec_insn_lbu_valid ? spec_insn_lbu_rs2_addr : spec_insn_ld_valid ? spec_insn_ld_rs2_addr : spec_insn_lh_valid ? spec_insn_lh_rs2_addr : spec_insn_lhu_valid ? spec_insn_lhu_rs2_addr : spec_insn_lui_valid ? spec_insn_lui_rs2_addr : spec_insn_lw_valid ? spec_insn_lw_rs2_addr : spec_insn_lwu_valid ? spec_insn_lwu_rs2_addr : spec_insn_mul_valid ? spec_insn_mul_rs2_addr : spec_insn_mulh_valid ? spec_insn_mulh_rs2_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rs2_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_rs2_addr : spec_insn_mulw_valid ? spec_insn_mulw_rs2_addr : spec_insn_or_valid ? spec_insn_or_rs2_addr : spec_insn_ori_valid ? spec_insn_ori_rs2_addr : spec_insn_rem_valid ? spec_insn_rem_rs2_addr : spec_insn_remu_valid ? spec_insn_remu_rs2_addr : spec_insn_remuw_valid ? spec_insn_remuw_rs2_addr : spec_insn_remw_valid ? spec_insn_remw_rs2_addr : spec_insn_sb_valid ? spec_insn_sb_rs2_addr : spec_insn_sd_valid ? spec_insn_sd_rs2_addr : spec_insn_sh_valid ? spec_insn_sh_rs2_addr : spec_insn_sll_valid ? spec_insn_sll_rs2_addr : spec_insn_slli_valid ? spec_insn_slli_rs2_addr : spec_insn_slliw_valid ? spec_insn_slliw_rs2_addr : spec_insn_sllw_valid ? spec_insn_sllw_rs2_addr : spec_insn_slt_valid ? spec_insn_slt_rs2_addr : spec_insn_slti_valid ? spec_insn_slti_rs2_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr : spec_insn_sltu_valid ? spec_insn_sltu_rs2_addr : spec_insn_sra_valid ? spec_insn_sra_rs2_addr : spec_insn_srai_valid ? spec_insn_srai_rs2_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_rs2_addr : spec_insn_sraw_valid ? spec_insn_sraw_rs2_addr : spec_insn_srl_valid ? spec_insn_srl_rs2_addr : spec_insn_srli_valid ? spec_insn_srli_rs2_addr : spec_insn_srliw_valid ? spec_insn_srliw_rs2_addr : spec_insn_srlw_valid ? spec_insn_srlw_rs2_addr : spec_insn_sub_valid ? spec_insn_sub_rs2_addr : spec_insn_subw_valid ? spec_insn_subw_rs2_addr : spec_insn_sw_valid ? spec_insn_sw_rs2_addr : spec_insn_xor_valid ? spec_insn_xor_rs2_addr : spec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0; assign spec_rd_addr = spec_insn_add_valid ? spec_insn_add_rd_addr : spec_insn_addi_valid ? spec_insn_addi_rd_addr : spec_insn_addiw_valid ? spec_insn_addiw_rd_addr : spec_insn_addw_valid ? spec_insn_addw_rd_addr : spec_insn_and_valid ? spec_insn_and_rd_addr : spec_insn_andi_valid ? spec_insn_andi_rd_addr : spec_insn_auipc_valid ? spec_insn_auipc_rd_addr : spec_insn_beq_valid ? spec_insn_beq_rd_addr : spec_insn_bge_valid ? spec_insn_bge_rd_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr : spec_insn_blt_valid ? spec_insn_blt_rd_addr : spec_insn_bltu_valid ? spec_insn_bltu_rd_addr : spec_insn_bne_valid ? spec_insn_bne_rd_addr : spec_insn_c_add_valid ? spec_insn_c_add_rd_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_rd_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_addr : spec_insn_c_addiw_valid ? spec_insn_c_addiw_rd_addr : spec_insn_c_addw_valid ? spec_insn_c_addw_rd_addr : spec_insn_c_and_valid ? spec_insn_c_and_rd_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_rd_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_addr : spec_insn_c_j_valid ? spec_insn_c_j_rd_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_rd_addr : spec_insn_c_ld_valid ? spec_insn_c_ld_rd_addr : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rd_addr : spec_insn_c_li_valid ? spec_insn_c_li_rd_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_rd_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_rd_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_rd_addr : spec_insn_c_or_valid ? spec_insn_c_or_rd_addr : spec_insn_c_sd_valid ? spec_insn_c_sd_rd_addr : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rd_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_rd_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_rd_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_rd_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_rd_addr : spec_insn_c_subw_valid ? spec_insn_c_subw_rd_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_rd_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_rd_addr : spec_insn_div_valid ? spec_insn_div_rd_addr : spec_insn_divu_valid ? spec_insn_divu_rd_addr : spec_insn_divuw_valid ? spec_insn_divuw_rd_addr : spec_insn_divw_valid ? spec_insn_divw_rd_addr : spec_insn_jal_valid ? spec_insn_jal_rd_addr : spec_insn_jalr_valid ? spec_insn_jalr_rd_addr : spec_insn_lb_valid ? spec_insn_lb_rd_addr : spec_insn_lbu_valid ? spec_insn_lbu_rd_addr : spec_insn_ld_valid ? spec_insn_ld_rd_addr : spec_insn_lh_valid ? spec_insn_lh_rd_addr : spec_insn_lhu_valid ? spec_insn_lhu_rd_addr : spec_insn_lui_valid ? spec_insn_lui_rd_addr : spec_insn_lw_valid ? spec_insn_lw_rd_addr : spec_insn_lwu_valid ? spec_insn_lwu_rd_addr : spec_insn_mul_valid ? spec_insn_mul_rd_addr : spec_insn_mulh_valid ? spec_insn_mulh_rd_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_rd_addr : spec_insn_mulw_valid ? spec_insn_mulw_rd_addr : spec_insn_or_valid ? spec_insn_or_rd_addr : spec_insn_ori_valid ? spec_insn_ori_rd_addr : spec_insn_rem_valid ? spec_insn_rem_rd_addr : spec_insn_remu_valid ? spec_insn_remu_rd_addr : spec_insn_remuw_valid ? spec_insn_remuw_rd_addr : spec_insn_remw_valid ? spec_insn_remw_rd_addr : spec_insn_sb_valid ? spec_insn_sb_rd_addr : spec_insn_sd_valid ? spec_insn_sd_rd_addr : spec_insn_sh_valid ? spec_insn_sh_rd_addr : spec_insn_sll_valid ? spec_insn_sll_rd_addr : spec_insn_slli_valid ? spec_insn_slli_rd_addr : spec_insn_slliw_valid ? spec_insn_slliw_rd_addr : spec_insn_sllw_valid ? spec_insn_sllw_rd_addr : spec_insn_slt_valid ? spec_insn_slt_rd_addr : spec_insn_slti_valid ? spec_insn_slti_rd_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr : spec_insn_sltu_valid ? spec_insn_sltu_rd_addr : spec_insn_sra_valid ? spec_insn_sra_rd_addr : spec_insn_srai_valid ? spec_insn_srai_rd_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_rd_addr : spec_insn_sraw_valid ? spec_insn_sraw_rd_addr : spec_insn_srl_valid ? spec_insn_srl_rd_addr : spec_insn_srli_valid ? spec_insn_srli_rd_addr : spec_insn_srliw_valid ? spec_insn_srliw_rd_addr : spec_insn_srlw_valid ? spec_insn_srlw_rd_addr : spec_insn_sub_valid ? spec_insn_sub_rd_addr : spec_insn_subw_valid ? spec_insn_subw_rd_addr : spec_insn_sw_valid ? spec_insn_sw_rd_addr : spec_insn_xor_valid ? spec_insn_xor_rd_addr : spec_insn_xori_valid ? spec_insn_xori_rd_addr : 0; assign spec_rd_wdata = spec_insn_add_valid ? spec_insn_add_rd_wdata : spec_insn_addi_valid ? spec_insn_addi_rd_wdata : spec_insn_addiw_valid ? spec_insn_addiw_rd_wdata : spec_insn_addw_valid ? spec_insn_addw_rd_wdata : spec_insn_and_valid ? spec_insn_and_rd_wdata : spec_insn_andi_valid ? spec_insn_andi_rd_wdata : spec_insn_auipc_valid ? spec_insn_auipc_rd_wdata : spec_insn_beq_valid ? spec_insn_beq_rd_wdata : spec_insn_bge_valid ? spec_insn_bge_rd_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata : spec_insn_blt_valid ? spec_insn_blt_rd_wdata : spec_insn_bltu_valid ? spec_insn_bltu_rd_wdata : spec_insn_bne_valid ? spec_insn_bne_rd_wdata : spec_insn_c_add_valid ? spec_insn_c_add_rd_wdata : spec_insn_c_addi_valid ? spec_insn_c_addi_rd_wdata : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_wdata : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_wdata : spec_insn_c_addiw_valid ? spec_insn_c_addiw_rd_wdata : spec_insn_c_addw_valid ? spec_insn_c_addw_rd_wdata : spec_insn_c_and_valid ? spec_insn_c_and_rd_wdata : spec_insn_c_andi_valid ? spec_insn_c_andi_rd_wdata : spec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_wdata : spec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_wdata : spec_insn_c_j_valid ? spec_insn_c_j_rd_wdata : spec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_wdata : spec_insn_c_jr_valid ? spec_insn_c_jr_rd_wdata : spec_insn_c_ld_valid ? spec_insn_c_ld_rd_wdata : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rd_wdata : spec_insn_c_li_valid ? spec_insn_c_li_rd_wdata : spec_insn_c_lui_valid ? spec_insn_c_lui_rd_wdata : spec_insn_c_lw_valid ? spec_insn_c_lw_rd_wdata : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_wdata : spec_insn_c_mv_valid ? spec_insn_c_mv_rd_wdata : spec_insn_c_or_valid ? spec_insn_c_or_rd_wdata : spec_insn_c_sd_valid ? spec_insn_c_sd_rd_wdata : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rd_wdata : spec_insn_c_slli_valid ? spec_insn_c_slli_rd_wdata : spec_insn_c_srai_valid ? spec_insn_c_srai_rd_wdata : spec_insn_c_srli_valid ? spec_insn_c_srli_rd_wdata : spec_insn_c_sub_valid ? spec_insn_c_sub_rd_wdata : spec_insn_c_subw_valid ? spec_insn_c_subw_rd_wdata : spec_insn_c_sw_valid ? spec_insn_c_sw_rd_wdata : spec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_wdata : spec_insn_c_xor_valid ? spec_insn_c_xor_rd_wdata : spec_insn_div_valid ? spec_insn_div_rd_wdata : spec_insn_divu_valid ? spec_insn_divu_rd_wdata : spec_insn_divuw_valid ? spec_insn_divuw_rd_wdata : spec_insn_divw_valid ? spec_insn_divw_rd_wdata : spec_insn_jal_valid ? spec_insn_jal_rd_wdata : spec_insn_jalr_valid ? spec_insn_jalr_rd_wdata : spec_insn_lb_valid ? spec_insn_lb_rd_wdata : spec_insn_lbu_valid ? spec_insn_lbu_rd_wdata : spec_insn_ld_valid ? spec_insn_ld_rd_wdata : spec_insn_lh_valid ? spec_insn_lh_rd_wdata : spec_insn_lhu_valid ? spec_insn_lhu_rd_wdata : spec_insn_lui_valid ? spec_insn_lui_rd_wdata : spec_insn_lw_valid ? spec_insn_lw_rd_wdata : spec_insn_lwu_valid ? spec_insn_lwu_rd_wdata : spec_insn_mul_valid ? spec_insn_mul_rd_wdata : spec_insn_mulh_valid ? spec_insn_mulh_rd_wdata : spec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_wdata : spec_insn_mulhu_valid ? spec_insn_mulhu_rd_wdata : spec_insn_mulw_valid ? spec_insn_mulw_rd_wdata : spec_insn_or_valid ? spec_insn_or_rd_wdata : spec_insn_ori_valid ? spec_insn_ori_rd_wdata : spec_insn_rem_valid ? spec_insn_rem_rd_wdata : spec_insn_remu_valid ? spec_insn_remu_rd_wdata : spec_insn_remuw_valid ? spec_insn_remuw_rd_wdata : spec_insn_remw_valid ? spec_insn_remw_rd_wdata : spec_insn_sb_valid ? spec_insn_sb_rd_wdata : spec_insn_sd_valid ? spec_insn_sd_rd_wdata : spec_insn_sh_valid ? spec_insn_sh_rd_wdata : spec_insn_sll_valid ? spec_insn_sll_rd_wdata : spec_insn_slli_valid ? spec_insn_slli_rd_wdata : spec_insn_slliw_valid ? spec_insn_slliw_rd_wdata : spec_insn_sllw_valid ? spec_insn_sllw_rd_wdata : spec_insn_slt_valid ? spec_insn_slt_rd_wdata : spec_insn_slti_valid ? spec_insn_slti_rd_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata : spec_insn_sltu_valid ? spec_insn_sltu_rd_wdata : spec_insn_sra_valid ? spec_insn_sra_rd_wdata : spec_insn_srai_valid ? spec_insn_srai_rd_wdata : spec_insn_sraiw_valid ? spec_insn_sraiw_rd_wdata : spec_insn_sraw_valid ? spec_insn_sraw_rd_wdata : spec_insn_srl_valid ? spec_insn_srl_rd_wdata : spec_insn_srli_valid ? spec_insn_srli_rd_wdata : spec_insn_srliw_valid ? spec_insn_srliw_rd_wdata : spec_insn_srlw_valid ? spec_insn_srlw_rd_wdata : spec_insn_sub_valid ? spec_insn_sub_rd_wdata : spec_insn_subw_valid ? spec_insn_subw_rd_wdata : spec_insn_sw_valid ? spec_insn_sw_rd_wdata : spec_insn_xor_valid ? spec_insn_xor_rd_wdata : spec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0; assign spec_pc_wdata = spec_insn_add_valid ? spec_insn_add_pc_wdata : spec_insn_addi_valid ? spec_insn_addi_pc_wdata : spec_insn_addiw_valid ? spec_insn_addiw_pc_wdata : spec_insn_addw_valid ? spec_insn_addw_pc_wdata : spec_insn_and_valid ? spec_insn_and_pc_wdata : spec_insn_andi_valid ? spec_insn_andi_pc_wdata : spec_insn_auipc_valid ? spec_insn_auipc_pc_wdata : spec_insn_beq_valid ? spec_insn_beq_pc_wdata : spec_insn_bge_valid ? spec_insn_bge_pc_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata : spec_insn_blt_valid ? spec_insn_blt_pc_wdata : spec_insn_bltu_valid ? spec_insn_bltu_pc_wdata : spec_insn_bne_valid ? spec_insn_bne_pc_wdata : spec_insn_c_add_valid ? spec_insn_c_add_pc_wdata : spec_insn_c_addi_valid ? spec_insn_c_addi_pc_wdata : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_pc_wdata : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_pc_wdata : spec_insn_c_addiw_valid ? spec_insn_c_addiw_pc_wdata : spec_insn_c_addw_valid ? spec_insn_c_addw_pc_wdata : spec_insn_c_and_valid ? spec_insn_c_and_pc_wdata : spec_insn_c_andi_valid ? spec_insn_c_andi_pc_wdata : spec_insn_c_beqz_valid ? spec_insn_c_beqz_pc_wdata : spec_insn_c_bnez_valid ? spec_insn_c_bnez_pc_wdata : spec_insn_c_j_valid ? spec_insn_c_j_pc_wdata : spec_insn_c_jalr_valid ? spec_insn_c_jalr_pc_wdata : spec_insn_c_jr_valid ? spec_insn_c_jr_pc_wdata : spec_insn_c_ld_valid ? spec_insn_c_ld_pc_wdata : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_pc_wdata : spec_insn_c_li_valid ? spec_insn_c_li_pc_wdata : spec_insn_c_lui_valid ? spec_insn_c_lui_pc_wdata : spec_insn_c_lw_valid ? spec_insn_c_lw_pc_wdata : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_pc_wdata : spec_insn_c_mv_valid ? spec_insn_c_mv_pc_wdata : spec_insn_c_or_valid ? spec_insn_c_or_pc_wdata : spec_insn_c_sd_valid ? spec_insn_c_sd_pc_wdata : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_pc_wdata : spec_insn_c_slli_valid ? spec_insn_c_slli_pc_wdata : spec_insn_c_srai_valid ? spec_insn_c_srai_pc_wdata : spec_insn_c_srli_valid ? spec_insn_c_srli_pc_wdata : spec_insn_c_sub_valid ? spec_insn_c_sub_pc_wdata : spec_insn_c_subw_valid ? spec_insn_c_subw_pc_wdata : spec_insn_c_sw_valid ? spec_insn_c_sw_pc_wdata : spec_insn_c_swsp_valid ? spec_insn_c_swsp_pc_wdata : spec_insn_c_xor_valid ? spec_insn_c_xor_pc_wdata : spec_insn_div_valid ? spec_insn_div_pc_wdata : spec_insn_divu_valid ? spec_insn_divu_pc_wdata : spec_insn_divuw_valid ? spec_insn_divuw_pc_wdata : spec_insn_divw_valid ? spec_insn_divw_pc_wdata : spec_insn_jal_valid ? spec_insn_jal_pc_wdata : spec_insn_jalr_valid ? spec_insn_jalr_pc_wdata : spec_insn_lb_valid ? spec_insn_lb_pc_wdata : spec_insn_lbu_valid ? spec_insn_lbu_pc_wdata : spec_insn_ld_valid ? spec_insn_ld_pc_wdata : spec_insn_lh_valid ? spec_insn_lh_pc_wdata : spec_insn_lhu_valid ? spec_insn_lhu_pc_wdata : spec_insn_lui_valid ? spec_insn_lui_pc_wdata : spec_insn_lw_valid ? spec_insn_lw_pc_wdata : spec_insn_lwu_valid ? spec_insn_lwu_pc_wdata : spec_insn_mul_valid ? spec_insn_mul_pc_wdata : spec_insn_mulh_valid ? spec_insn_mulh_pc_wdata : spec_insn_mulhsu_valid ? spec_insn_mulhsu_pc_wdata : spec_insn_mulhu_valid ? spec_insn_mulhu_pc_wdata : spec_insn_mulw_valid ? spec_insn_mulw_pc_wdata : spec_insn_or_valid ? spec_insn_or_pc_wdata : spec_insn_ori_valid ? spec_insn_ori_pc_wdata : spec_insn_rem_valid ? spec_insn_rem_pc_wdata : spec_insn_remu_valid ? spec_insn_remu_pc_wdata : spec_insn_remuw_valid ? spec_insn_remuw_pc_wdata : spec_insn_remw_valid ? spec_insn_remw_pc_wdata : spec_insn_sb_valid ? spec_insn_sb_pc_wdata : spec_insn_sd_valid ? spec_insn_sd_pc_wdata : spec_insn_sh_valid ? spec_insn_sh_pc_wdata : spec_insn_sll_valid ? spec_insn_sll_pc_wdata : spec_insn_slli_valid ? spec_insn_slli_pc_wdata : spec_insn_slliw_valid ? spec_insn_slliw_pc_wdata : spec_insn_sllw_valid ? spec_insn_sllw_pc_wdata : spec_insn_slt_valid ? spec_insn_slt_pc_wdata : spec_insn_slti_valid ? spec_insn_slti_pc_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata : spec_insn_sltu_valid ? spec_insn_sltu_pc_wdata : spec_insn_sra_valid ? spec_insn_sra_pc_wdata : spec_insn_srai_valid ? spec_insn_srai_pc_wdata : spec_insn_sraiw_valid ? spec_insn_sraiw_pc_wdata : spec_insn_sraw_valid ? spec_insn_sraw_pc_wdata : spec_insn_srl_valid ? spec_insn_srl_pc_wdata : spec_insn_srli_valid ? spec_insn_srli_pc_wdata : spec_insn_srliw_valid ? spec_insn_srliw_pc_wdata : spec_insn_srlw_valid ? spec_insn_srlw_pc_wdata : spec_insn_sub_valid ? spec_insn_sub_pc_wdata : spec_insn_subw_valid ? spec_insn_subw_pc_wdata : spec_insn_sw_valid ? spec_insn_sw_pc_wdata : spec_insn_xor_valid ? spec_insn_xor_pc_wdata : spec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0; assign spec_mem_addr = spec_insn_add_valid ? spec_insn_add_mem_addr : spec_insn_addi_valid ? spec_insn_addi_mem_addr : spec_insn_addiw_valid ? spec_insn_addiw_mem_addr : spec_insn_addw_valid ? spec_insn_addw_mem_addr : spec_insn_and_valid ? spec_insn_and_mem_addr : spec_insn_andi_valid ? spec_insn_andi_mem_addr : spec_insn_auipc_valid ? spec_insn_auipc_mem_addr : spec_insn_beq_valid ? spec_insn_beq_mem_addr : spec_insn_bge_valid ? spec_insn_bge_mem_addr : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr : spec_insn_blt_valid ? spec_insn_blt_mem_addr : spec_insn_bltu_valid ? spec_insn_bltu_mem_addr : spec_insn_bne_valid ? spec_insn_bne_mem_addr : spec_insn_c_add_valid ? spec_insn_c_add_mem_addr : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_addr : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_addr : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_addr : spec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_addr : spec_insn_c_addw_valid ? spec_insn_c_addw_mem_addr : spec_insn_c_and_valid ? spec_insn_c_and_mem_addr : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_addr : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_addr : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_addr : spec_insn_c_j_valid ? spec_insn_c_j_mem_addr : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_addr : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_addr : spec_insn_c_ld_valid ? spec_insn_c_ld_mem_addr : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_addr : spec_insn_c_li_valid ? spec_insn_c_li_mem_addr : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_addr : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_addr : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_addr : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_addr : spec_insn_c_or_valid ? spec_insn_c_or_mem_addr : spec_insn_c_sd_valid ? spec_insn_c_sd_mem_addr : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_addr : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_addr : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_addr : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_addr : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_addr : spec_insn_c_subw_valid ? spec_insn_c_subw_mem_addr : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_addr : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_addr : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_addr : spec_insn_div_valid ? spec_insn_div_mem_addr : spec_insn_divu_valid ? spec_insn_divu_mem_addr : spec_insn_divuw_valid ? spec_insn_divuw_mem_addr : spec_insn_divw_valid ? spec_insn_divw_mem_addr : spec_insn_jal_valid ? spec_insn_jal_mem_addr : spec_insn_jalr_valid ? spec_insn_jalr_mem_addr : spec_insn_lb_valid ? spec_insn_lb_mem_addr : spec_insn_lbu_valid ? spec_insn_lbu_mem_addr : spec_insn_ld_valid ? spec_insn_ld_mem_addr : spec_insn_lh_valid ? spec_insn_lh_mem_addr : spec_insn_lhu_valid ? spec_insn_lhu_mem_addr : spec_insn_lui_valid ? spec_insn_lui_mem_addr : spec_insn_lw_valid ? spec_insn_lw_mem_addr : spec_insn_lwu_valid ? spec_insn_lwu_mem_addr : spec_insn_mul_valid ? spec_insn_mul_mem_addr : spec_insn_mulh_valid ? spec_insn_mulh_mem_addr : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_addr : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_addr : spec_insn_mulw_valid ? spec_insn_mulw_mem_addr : spec_insn_or_valid ? spec_insn_or_mem_addr : spec_insn_ori_valid ? spec_insn_ori_mem_addr : spec_insn_rem_valid ? spec_insn_rem_mem_addr : spec_insn_remu_valid ? spec_insn_remu_mem_addr : spec_insn_remuw_valid ? spec_insn_remuw_mem_addr : spec_insn_remw_valid ? spec_insn_remw_mem_addr : spec_insn_sb_valid ? spec_insn_sb_mem_addr : spec_insn_sd_valid ? spec_insn_sd_mem_addr : spec_insn_sh_valid ? spec_insn_sh_mem_addr : spec_insn_sll_valid ? spec_insn_sll_mem_addr : spec_insn_slli_valid ? spec_insn_slli_mem_addr : spec_insn_slliw_valid ? spec_insn_slliw_mem_addr : spec_insn_sllw_valid ? spec_insn_sllw_mem_addr : spec_insn_slt_valid ? spec_insn_slt_mem_addr : spec_insn_slti_valid ? spec_insn_slti_mem_addr : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr : spec_insn_sltu_valid ? spec_insn_sltu_mem_addr : spec_insn_sra_valid ? spec_insn_sra_mem_addr : spec_insn_srai_valid ? spec_insn_srai_mem_addr : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_addr : spec_insn_sraw_valid ? spec_insn_sraw_mem_addr : spec_insn_srl_valid ? spec_insn_srl_mem_addr : spec_insn_srli_valid ? spec_insn_srli_mem_addr : spec_insn_srliw_valid ? spec_insn_srliw_mem_addr : spec_insn_srlw_valid ? spec_insn_srlw_mem_addr : spec_insn_sub_valid ? spec_insn_sub_mem_addr : spec_insn_subw_valid ? spec_insn_subw_mem_addr : spec_insn_sw_valid ? spec_insn_sw_mem_addr : spec_insn_xor_valid ? spec_insn_xor_mem_addr : spec_insn_xori_valid ? spec_insn_xori_mem_addr : 0; assign spec_mem_rmask = spec_insn_add_valid ? spec_insn_add_mem_rmask : spec_insn_addi_valid ? spec_insn_addi_mem_rmask : spec_insn_addiw_valid ? spec_insn_addiw_mem_rmask : spec_insn_addw_valid ? spec_insn_addw_mem_rmask : spec_insn_and_valid ? spec_insn_and_mem_rmask : spec_insn_andi_valid ? spec_insn_andi_mem_rmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_rmask : spec_insn_beq_valid ? spec_insn_beq_mem_rmask : spec_insn_bge_valid ? spec_insn_bge_mem_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask : spec_insn_blt_valid ? spec_insn_blt_mem_rmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_rmask : spec_insn_bne_valid ? spec_insn_bne_mem_rmask : spec_insn_c_add_valid ? spec_insn_c_add_mem_rmask : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_rmask : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_rmask : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_rmask : spec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_rmask : spec_insn_c_addw_valid ? spec_insn_c_addw_mem_rmask : spec_insn_c_and_valid ? spec_insn_c_and_mem_rmask : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_rmask : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_rmask : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_rmask : spec_insn_c_j_valid ? spec_insn_c_j_mem_rmask : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_rmask : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_rmask : spec_insn_c_ld_valid ? spec_insn_c_ld_mem_rmask : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_rmask : spec_insn_c_li_valid ? spec_insn_c_li_mem_rmask : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_rmask : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_rmask : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_rmask : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_rmask : spec_insn_c_or_valid ? spec_insn_c_or_mem_rmask : spec_insn_c_sd_valid ? spec_insn_c_sd_mem_rmask : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_rmask : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_rmask : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_rmask : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_rmask : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_rmask : spec_insn_c_subw_valid ? spec_insn_c_subw_mem_rmask : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_rmask : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_rmask : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_rmask : spec_insn_div_valid ? spec_insn_div_mem_rmask : spec_insn_divu_valid ? spec_insn_divu_mem_rmask : spec_insn_divuw_valid ? spec_insn_divuw_mem_rmask : spec_insn_divw_valid ? spec_insn_divw_mem_rmask : spec_insn_jal_valid ? spec_insn_jal_mem_rmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_rmask : spec_insn_lb_valid ? spec_insn_lb_mem_rmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_rmask : spec_insn_ld_valid ? spec_insn_ld_mem_rmask : spec_insn_lh_valid ? spec_insn_lh_mem_rmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_rmask : spec_insn_lui_valid ? spec_insn_lui_mem_rmask : spec_insn_lw_valid ? spec_insn_lw_mem_rmask : spec_insn_lwu_valid ? spec_insn_lwu_mem_rmask : spec_insn_mul_valid ? spec_insn_mul_mem_rmask : spec_insn_mulh_valid ? spec_insn_mulh_mem_rmask : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_rmask : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_rmask : spec_insn_mulw_valid ? spec_insn_mulw_mem_rmask : spec_insn_or_valid ? spec_insn_or_mem_rmask : spec_insn_ori_valid ? spec_insn_ori_mem_rmask : spec_insn_rem_valid ? spec_insn_rem_mem_rmask : spec_insn_remu_valid ? spec_insn_remu_mem_rmask : spec_insn_remuw_valid ? spec_insn_remuw_mem_rmask : spec_insn_remw_valid ? spec_insn_remw_mem_rmask : spec_insn_sb_valid ? spec_insn_sb_mem_rmask : spec_insn_sd_valid ? spec_insn_sd_mem_rmask : spec_insn_sh_valid ? spec_insn_sh_mem_rmask : spec_insn_sll_valid ? spec_insn_sll_mem_rmask : spec_insn_slli_valid ? spec_insn_slli_mem_rmask : spec_insn_slliw_valid ? spec_insn_slliw_mem_rmask : spec_insn_sllw_valid ? spec_insn_sllw_mem_rmask : spec_insn_slt_valid ? spec_insn_slt_mem_rmask : spec_insn_slti_valid ? spec_insn_slti_mem_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_rmask : spec_insn_sra_valid ? spec_insn_sra_mem_rmask : spec_insn_srai_valid ? spec_insn_srai_mem_rmask : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_rmask : spec_insn_sraw_valid ? spec_insn_sraw_mem_rmask : spec_insn_srl_valid ? spec_insn_srl_mem_rmask : spec_insn_srli_valid ? spec_insn_srli_mem_rmask : spec_insn_srliw_valid ? spec_insn_srliw_mem_rmask : spec_insn_srlw_valid ? spec_insn_srlw_mem_rmask : spec_insn_sub_valid ? spec_insn_sub_mem_rmask : spec_insn_subw_valid ? spec_insn_subw_mem_rmask : spec_insn_sw_valid ? spec_insn_sw_mem_rmask : spec_insn_xor_valid ? spec_insn_xor_mem_rmask : spec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0; assign spec_mem_wmask = spec_insn_add_valid ? spec_insn_add_mem_wmask : spec_insn_addi_valid ? spec_insn_addi_mem_wmask : spec_insn_addiw_valid ? spec_insn_addiw_mem_wmask : spec_insn_addw_valid ? spec_insn_addw_mem_wmask : spec_insn_and_valid ? spec_insn_and_mem_wmask : spec_insn_andi_valid ? spec_insn_andi_mem_wmask : spec_insn_auipc_valid ? spec_insn_auipc_mem_wmask : spec_insn_beq_valid ? spec_insn_beq_mem_wmask : spec_insn_bge_valid ? spec_insn_bge_mem_wmask : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask : spec_insn_blt_valid ? spec_insn_blt_mem_wmask : spec_insn_bltu_valid ? spec_insn_bltu_mem_wmask : spec_insn_bne_valid ? spec_insn_bne_mem_wmask : spec_insn_c_add_valid ? spec_insn_c_add_mem_wmask : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_wmask : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wmask : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wmask : spec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_wmask : spec_insn_c_addw_valid ? spec_insn_c_addw_mem_wmask : spec_insn_c_and_valid ? spec_insn_c_and_mem_wmask : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_wmask : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wmask : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wmask : spec_insn_c_j_valid ? spec_insn_c_j_mem_wmask : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wmask : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_wmask : spec_insn_c_ld_valid ? spec_insn_c_ld_mem_wmask : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_wmask : spec_insn_c_li_valid ? spec_insn_c_li_mem_wmask : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_wmask : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_wmask : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wmask : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_wmask : spec_insn_c_or_valid ? spec_insn_c_or_mem_wmask : spec_insn_c_sd_valid ? spec_insn_c_sd_mem_wmask : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_wmask : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_wmask : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_wmask : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_wmask : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_wmask : spec_insn_c_subw_valid ? spec_insn_c_subw_mem_wmask : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_wmask : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wmask : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_wmask : spec_insn_div_valid ? spec_insn_div_mem_wmask : spec_insn_divu_valid ? spec_insn_divu_mem_wmask : spec_insn_divuw_valid ? spec_insn_divuw_mem_wmask : spec_insn_divw_valid ? spec_insn_divw_mem_wmask : spec_insn_jal_valid ? spec_insn_jal_mem_wmask : spec_insn_jalr_valid ? spec_insn_jalr_mem_wmask : spec_insn_lb_valid ? spec_insn_lb_mem_wmask : spec_insn_lbu_valid ? spec_insn_lbu_mem_wmask : spec_insn_ld_valid ? spec_insn_ld_mem_wmask : spec_insn_lh_valid ? spec_insn_lh_mem_wmask : spec_insn_lhu_valid ? spec_insn_lhu_mem_wmask : spec_insn_lui_valid ? spec_insn_lui_mem_wmask : spec_insn_lw_valid ? spec_insn_lw_mem_wmask : spec_insn_lwu_valid ? spec_insn_lwu_mem_wmask : spec_insn_mul_valid ? spec_insn_mul_mem_wmask : spec_insn_mulh_valid ? spec_insn_mulh_mem_wmask : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wmask : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_wmask : spec_insn_mulw_valid ? spec_insn_mulw_mem_wmask : spec_insn_or_valid ? spec_insn_or_mem_wmask : spec_insn_ori_valid ? spec_insn_ori_mem_wmask : spec_insn_rem_valid ? spec_insn_rem_mem_wmask : spec_insn_remu_valid ? spec_insn_remu_mem_wmask : spec_insn_remuw_valid ? spec_insn_remuw_mem_wmask : spec_insn_remw_valid ? spec_insn_remw_mem_wmask : spec_insn_sb_valid ? spec_insn_sb_mem_wmask : spec_insn_sd_valid ? spec_insn_sd_mem_wmask : spec_insn_sh_valid ? spec_insn_sh_mem_wmask : spec_insn_sll_valid ? spec_insn_sll_mem_wmask : spec_insn_slli_valid ? spec_insn_slli_mem_wmask : spec_insn_slliw_valid ? spec_insn_slliw_mem_wmask : spec_insn_sllw_valid ? spec_insn_sllw_mem_wmask : spec_insn_slt_valid ? spec_insn_slt_mem_wmask : spec_insn_slti_valid ? spec_insn_slti_mem_wmask : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask : spec_insn_sltu_valid ? spec_insn_sltu_mem_wmask : spec_insn_sra_valid ? spec_insn_sra_mem_wmask : spec_insn_srai_valid ? spec_insn_srai_mem_wmask : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wmask : spec_insn_sraw_valid ? spec_insn_sraw_mem_wmask : spec_insn_srl_valid ? spec_insn_srl_mem_wmask : spec_insn_srli_valid ? spec_insn_srli_mem_wmask : spec_insn_srliw_valid ? spec_insn_srliw_mem_wmask : spec_insn_srlw_valid ? spec_insn_srlw_mem_wmask : spec_insn_sub_valid ? spec_insn_sub_mem_wmask : spec_insn_subw_valid ? spec_insn_subw_mem_wmask : spec_insn_sw_valid ? spec_insn_sw_mem_wmask : spec_insn_xor_valid ? spec_insn_xor_mem_wmask : spec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0; assign spec_mem_wdata = spec_insn_add_valid ? spec_insn_add_mem_wdata : spec_insn_addi_valid ? spec_insn_addi_mem_wdata : spec_insn_addiw_valid ? spec_insn_addiw_mem_wdata : spec_insn_addw_valid ? spec_insn_addw_mem_wdata : spec_insn_and_valid ? spec_insn_and_mem_wdata : spec_insn_andi_valid ? spec_insn_andi_mem_wdata : spec_insn_auipc_valid ? spec_insn_auipc_mem_wdata : spec_insn_beq_valid ? spec_insn_beq_mem_wdata : spec_insn_bge_valid ? spec_insn_bge_mem_wdata : spec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata : spec_insn_blt_valid ? spec_insn_blt_mem_wdata : spec_insn_bltu_valid ? spec_insn_bltu_mem_wdata : spec_insn_bne_valid ? spec_insn_bne_mem_wdata : spec_insn_c_add_valid ? spec_insn_c_add_mem_wdata : spec_insn_c_addi_valid ? spec_insn_c_addi_mem_wdata : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wdata : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wdata : spec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_wdata : spec_insn_c_addw_valid ? spec_insn_c_addw_mem_wdata : spec_insn_c_and_valid ? spec_insn_c_and_mem_wdata : spec_insn_c_andi_valid ? spec_insn_c_andi_mem_wdata : spec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wdata : spec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wdata : spec_insn_c_j_valid ? spec_insn_c_j_mem_wdata : spec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wdata : spec_insn_c_jr_valid ? spec_insn_c_jr_mem_wdata : spec_insn_c_ld_valid ? spec_insn_c_ld_mem_wdata : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_wdata : spec_insn_c_li_valid ? spec_insn_c_li_mem_wdata : spec_insn_c_lui_valid ? spec_insn_c_lui_mem_wdata : spec_insn_c_lw_valid ? spec_insn_c_lw_mem_wdata : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wdata : spec_insn_c_mv_valid ? spec_insn_c_mv_mem_wdata : spec_insn_c_or_valid ? spec_insn_c_or_mem_wdata : spec_insn_c_sd_valid ? spec_insn_c_sd_mem_wdata : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_wdata : spec_insn_c_slli_valid ? spec_insn_c_slli_mem_wdata : spec_insn_c_srai_valid ? spec_insn_c_srai_mem_wdata : spec_insn_c_srli_valid ? spec_insn_c_srli_mem_wdata : spec_insn_c_sub_valid ? spec_insn_c_sub_mem_wdata : spec_insn_c_subw_valid ? spec_insn_c_subw_mem_wdata : spec_insn_c_sw_valid ? spec_insn_c_sw_mem_wdata : spec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wdata : spec_insn_c_xor_valid ? spec_insn_c_xor_mem_wdata : spec_insn_div_valid ? spec_insn_div_mem_wdata : spec_insn_divu_valid ? spec_insn_divu_mem_wdata : spec_insn_divuw_valid ? spec_insn_divuw_mem_wdata : spec_insn_divw_valid ? spec_insn_divw_mem_wdata : spec_insn_jal_valid ? spec_insn_jal_mem_wdata : spec_insn_jalr_valid ? spec_insn_jalr_mem_wdata : spec_insn_lb_valid ? spec_insn_lb_mem_wdata : spec_insn_lbu_valid ? spec_insn_lbu_mem_wdata : spec_insn_ld_valid ? spec_insn_ld_mem_wdata : spec_insn_lh_valid ? spec_insn_lh_mem_wdata : spec_insn_lhu_valid ? spec_insn_lhu_mem_wdata : spec_insn_lui_valid ? spec_insn_lui_mem_wdata : spec_insn_lw_valid ? spec_insn_lw_mem_wdata : spec_insn_lwu_valid ? spec_insn_lwu_mem_wdata : spec_insn_mul_valid ? spec_insn_mul_mem_wdata : spec_insn_mulh_valid ? spec_insn_mulh_mem_wdata : spec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wdata : spec_insn_mulhu_valid ? spec_insn_mulhu_mem_wdata : spec_insn_mulw_valid ? spec_insn_mulw_mem_wdata : spec_insn_or_valid ? spec_insn_or_mem_wdata : spec_insn_ori_valid ? spec_insn_ori_mem_wdata : spec_insn_rem_valid ? spec_insn_rem_mem_wdata : spec_insn_remu_valid ? spec_insn_remu_mem_wdata : spec_insn_remuw_valid ? spec_insn_remuw_mem_wdata : spec_insn_remw_valid ? spec_insn_remw_mem_wdata : spec_insn_sb_valid ? spec_insn_sb_mem_wdata : spec_insn_sd_valid ? spec_insn_sd_mem_wdata : spec_insn_sh_valid ? spec_insn_sh_mem_wdata : spec_insn_sll_valid ? spec_insn_sll_mem_wdata : spec_insn_slli_valid ? spec_insn_slli_mem_wdata : spec_insn_slliw_valid ? spec_insn_slliw_mem_wdata : spec_insn_sllw_valid ? spec_insn_sllw_mem_wdata : spec_insn_slt_valid ? spec_insn_slt_mem_wdata : spec_insn_slti_valid ? spec_insn_slti_mem_wdata : spec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata : spec_insn_sltu_valid ? spec_insn_sltu_mem_wdata : spec_insn_sra_valid ? spec_insn_sra_mem_wdata : spec_insn_srai_valid ? spec_insn_srai_mem_wdata : spec_insn_sraiw_valid ? spec_insn_sraiw_mem_wdata : spec_insn_sraw_valid ? spec_insn_sraw_mem_wdata : spec_insn_srl_valid ? spec_insn_srl_mem_wdata : spec_insn_srli_valid ? spec_insn_srli_mem_wdata : spec_insn_srliw_valid ? spec_insn_srliw_mem_wdata : spec_insn_srlw_valid ? spec_insn_srlw_mem_wdata : spec_insn_sub_valid ? spec_insn_sub_mem_wdata : spec_insn_subw_valid ? spec_insn_subw_mem_wdata : spec_insn_sw_valid ? spec_insn_sw_mem_wdata : spec_insn_xor_valid ? spec_insn_xor_mem_wdata : spec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0; `ifdef RISCV_FORMAL_CSR_MISA assign spec_csr_misa_rmask = spec_insn_add_valid ? spec_insn_add_csr_misa_rmask : spec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask : spec_insn_addiw_valid ? spec_insn_addiw_csr_misa_rmask : spec_insn_addw_valid ? spec_insn_addw_csr_misa_rmask : spec_insn_and_valid ? spec_insn_and_csr_misa_rmask : spec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask : spec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask : spec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask : spec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask : spec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask : spec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask : spec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask : spec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask : spec_insn_c_add_valid ? spec_insn_c_add_csr_misa_rmask : spec_insn_c_addi_valid ? spec_insn_c_addi_csr_misa_rmask : spec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_csr_misa_rmask : spec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_csr_misa_rmask : spec_insn_c_addiw_valid ? spec_insn_c_addiw_csr_misa_rmask : spec_insn_c_addw_valid ? spec_insn_c_addw_csr_misa_rmask : spec_insn_c_and_valid ? spec_insn_c_and_csr_misa_rmask : spec_insn_c_andi_valid ? spec_insn_c_andi_csr_misa_rmask : spec_insn_c_beqz_valid ? spec_insn_c_beqz_csr_misa_rmask : spec_insn_c_bnez_valid ? spec_insn_c_bnez_csr_misa_rmask : spec_insn_c_j_valid ? spec_insn_c_j_csr_misa_rmask : spec_insn_c_jalr_valid ? spec_insn_c_jalr_csr_misa_rmask : spec_insn_c_jr_valid ? spec_insn_c_jr_csr_misa_rmask : spec_insn_c_ld_valid ? spec_insn_c_ld_csr_misa_rmask : spec_insn_c_ldsp_valid ? spec_insn_c_ldsp_csr_misa_rmask : spec_insn_c_li_valid ? spec_insn_c_li_csr_misa_rmask : spec_insn_c_lui_valid ? spec_insn_c_lui_csr_misa_rmask : spec_insn_c_lw_valid ? spec_insn_c_lw_csr_misa_rmask : spec_insn_c_lwsp_valid ? spec_insn_c_lwsp_csr_misa_rmask : spec_insn_c_mv_valid ? spec_insn_c_mv_csr_misa_rmask : spec_insn_c_or_valid ? spec_insn_c_or_csr_misa_rmask : spec_insn_c_sd_valid ? spec_insn_c_sd_csr_misa_rmask : spec_insn_c_sdsp_valid ? spec_insn_c_sdsp_csr_misa_rmask : spec_insn_c_slli_valid ? spec_insn_c_slli_csr_misa_rmask : spec_insn_c_srai_valid ? spec_insn_c_srai_csr_misa_rmask : spec_insn_c_srli_valid ? spec_insn_c_srli_csr_misa_rmask : spec_insn_c_sub_valid ? spec_insn_c_sub_csr_misa_rmask : spec_insn_c_subw_valid ? spec_insn_c_subw_csr_misa_rmask : spec_insn_c_sw_valid ? spec_insn_c_sw_csr_misa_rmask : spec_insn_c_swsp_valid ? spec_insn_c_swsp_csr_misa_rmask : spec_insn_c_xor_valid ? spec_insn_c_xor_csr_misa_rmask : spec_insn_div_valid ? spec_insn_div_csr_misa_rmask : spec_insn_divu_valid ? spec_insn_divu_csr_misa_rmask : spec_insn_divuw_valid ? spec_insn_divuw_csr_misa_rmask : spec_insn_divw_valid ? spec_insn_divw_csr_misa_rmask : spec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask : spec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask : spec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask : spec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask : spec_insn_ld_valid ? spec_insn_ld_csr_misa_rmask : spec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask : spec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask : spec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask : spec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask : spec_insn_lwu_valid ? spec_insn_lwu_csr_misa_rmask : spec_insn_mul_valid ? spec_insn_mul_csr_misa_rmask : spec_insn_mulh_valid ? spec_insn_mulh_csr_misa_rmask : spec_insn_mulhsu_valid ? spec_insn_mulhsu_csr_misa_rmask : spec_insn_mulhu_valid ? spec_insn_mulhu_csr_misa_rmask : spec_insn_mulw_valid ? spec_insn_mulw_csr_misa_rmask : spec_insn_or_valid ? spec_insn_or_csr_misa_rmask : spec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask : spec_insn_rem_valid ? spec_insn_rem_csr_misa_rmask : spec_insn_remu_valid ? spec_insn_remu_csr_misa_rmask : spec_insn_remuw_valid ? spec_insn_remuw_csr_misa_rmask : spec_insn_remw_valid ? spec_insn_remw_csr_misa_rmask : spec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask : spec_insn_sd_valid ? spec_insn_sd_csr_misa_rmask : spec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask : spec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask : spec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask : spec_insn_slliw_valid ? spec_insn_slliw_csr_misa_rmask : spec_insn_sllw_valid ? spec_insn_sllw_csr_misa_rmask : spec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask : spec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask : spec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask : spec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask : spec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask : spec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask : spec_insn_sraiw_valid ? spec_insn_sraiw_csr_misa_rmask : spec_insn_sraw_valid ? spec_insn_sraw_csr_misa_rmask : spec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask : spec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask : spec_insn_srliw_valid ? spec_insn_srliw_csr_misa_rmask : spec_insn_srlw_valid ? spec_insn_srlw_csr_misa_rmask : spec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask : spec_insn_subw_valid ? spec_insn_subw_csr_misa_rmask : spec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask : spec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask : spec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0; `endif endmodule ================================================ FILE: monitor/generate.py ================================================ #!/usr/bin/env python3 import getopt, sys from math import log2, ceil isa = "rv32i" prefix = None channels = 1 robdepth = 256 xlen = None ilen = None aligned = False compressed = False ignore_mem = False use_assert = False quiet_mode = False verbose_mode = False noregscheck = False nopccheck = False def usage(): print(""" Usage: %s [options] > outfile.v -i RISC-V ISA (default: rv32i) -p use as prefix for generated verilog modules default: riscv_formal_monitor_ -c number of RVFI channels (default: 1) -r depth of reorder buffer (must be a power of two, default: 256) setting this option to 0 will disabling reordering -a create monitor for core with aligned memory access -M do not check the mem_ RVFI signals in the monitor -R do not check consistency of reg reads and writes -P do not check consistency of pc reads and writes -A add assert(0) statements to the error handlers -Q do not generate $display() statements in error handlers -V create $display() statements for printing all insns """ % sys.argv[0]) sys.exit(1) try: opts, args = getopt.getopt(sys.argv[1:], "i:p:c:r:aMRPAQV") except: usage() for o, a in opts: if o == "-i": isa = a elif o == "-p": prefix = a elif o == "-c": channels = int(a) elif o == "-r": robdepth = int(a) elif o == "-a": aligned = True elif o == "-M": ignore_mem = True elif o == "-R": noregscheck = True elif o == "-P": nopccheck = True elif o == "-U": nocausality = True elif o == "-O": nocompleteness = True elif o == "-A": use_assert = True elif o == "-Q": quiet_mode = True elif o == "-V": verbose_mode = True else: usage() if len(args) != 0: usage() if prefix is None: prefix = "riscv_formal_monitor_%s" % isa if isa.startswith("rv32"): xlen = 32 elif isa.startswith("rv64"): xlen = 64 else: usage() if ilen is None: ilen = 32 if "c" in isa: compressed = True print("// DO NOT EDIT -- auto-generated from riscv-formal/monitor/generate.py") print("//") print("// Command line options: %s" % " ".join(sys.argv[1:])) print() print("module %s (" % prefix) print(" input clock,") print(" input reset,") print(" input [%d:0] rvfi_valid," % (channels-1)) print(" input [%d:0] rvfi_order," % (channels*64-1)) print(" input [%d:0] rvfi_insn," % (channels*32-1)) print(" input [%d:0] rvfi_trap," % (channels-1)) print(" input [%d:0] rvfi_halt," % (channels-1)) print(" input [%d:0] rvfi_intr," % (channels-1)) print(" input [%d:0] rvfi_mode," % (channels*2-1)) print(" input [%d:0] rvfi_rs1_addr," % (channels*5-1)) print(" input [%d:0] rvfi_rs2_addr," % (channels*5-1)) print(" input [%d:0] rvfi_rs1_rdata," % (channels*xlen-1)) print(" input [%d:0] rvfi_rs2_rdata," % (channels*xlen-1)) print(" input [%d:0] rvfi_rd_addr," % (channels*5-1)) print(" input [%d:0] rvfi_rd_wdata," % (channels*xlen-1)) print(" input [%d:0] rvfi_pc_rdata," % (channels*xlen-1)) print(" input [%d:0] rvfi_pc_wdata," % (channels*xlen-1)) print(" input [%d:0] rvfi_mem_addr," % (channels*xlen-1)) print(" input [%d:0] rvfi_mem_rmask," % (channels*xlen//8-1)) print(" input [%d:0] rvfi_mem_wmask," % (channels*xlen//8-1)) print(" input [%d:0] rvfi_mem_rdata," % (channels*xlen-1)) print(" input [%d:0] rvfi_mem_wdata," % (channels*xlen-1)) print(" input [%d:0] rvfi_mem_extamo," % (channels-1)) print(" output reg [15:0] errcode") print(");") errcodes = list() for chidx in range(channels): print(" wire ch%d_rvfi_valid = rvfi_valid[%d];" % (chidx, chidx)) print(" wire [63:0] ch%d_rvfi_order = rvfi_order[%d:%d];" % (chidx, 64*chidx+63, 64*chidx)) print(" wire [31:0] ch%d_rvfi_insn = rvfi_insn[%d:%d];" % (chidx, 32*chidx+31, 32*chidx)) print(" wire ch%d_rvfi_trap = rvfi_trap[%d];" % (chidx, chidx)) print(" wire ch%d_rvfi_halt = rvfi_halt[%d];" % (chidx, chidx)) print(" wire ch%d_rvfi_intr = rvfi_intr[%d];" % (chidx, chidx)) print(" wire [4:0] ch%d_rvfi_rs1_addr = rvfi_rs1_addr[%d:%d];" % (chidx, 5*chidx+4, 5*chidx)) print(" wire [4:0] ch%d_rvfi_rs2_addr = rvfi_rs2_addr[%d:%d];" % (chidx, 5*chidx+4, 5*chidx)) print(" wire [%d:0] ch%d_rvfi_rs1_rdata = rvfi_rs1_rdata[%d:%d];" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx)) print(" wire [%d:0] ch%d_rvfi_rs2_rdata = rvfi_rs2_rdata[%d:%d];" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx)) print(" wire [4:0] ch%d_rvfi_rd_addr = rvfi_rd_addr[%d:%d];" % (chidx, 5*chidx+4, 5*chidx)) print(" wire [%d:0] ch%d_rvfi_rd_wdata = rvfi_rd_wdata[%d:%d];" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx)) print(" wire [%d:0] ch%d_rvfi_pc_rdata = rvfi_pc_rdata[%d:%d];" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx)) print(" wire [%d:0] ch%d_rvfi_pc_wdata = rvfi_pc_wdata[%d:%d];" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx)) print(" wire [%d:0] ch%d_rvfi_mem_addr = rvfi_mem_addr[%d:%d];" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx)) print(" wire [%d:0] ch%d_rvfi_mem_rmask = rvfi_mem_rmask[%d:%d];" % (xlen//8-1, chidx, xlen//8*chidx+xlen//8-1, xlen//8*chidx)) print(" wire [%d:0] ch%d_rvfi_mem_wmask = rvfi_mem_wmask[%d:%d];" % (xlen//8-1, chidx, xlen//8*chidx+xlen//8-1, xlen//8*chidx)) print(" wire [%d:0] ch%d_rvfi_mem_rdata = rvfi_mem_rdata[%d:%d];" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx)) print(" wire [%d:0] ch%d_rvfi_mem_wdata = rvfi_mem_wdata[%d:%d];" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx)) print(" wire ch%d_rvfi_mem_extamo = rvfi_mem_extamo[%d];" % (chidx, chidx)) print() print(" wire ch%d_spec_valid;" % (chidx)) print(" wire ch%d_spec_trap;" % (chidx)) print(" wire [4:0] ch%d_spec_rs1_addr;" % (chidx)) print(" wire [4:0] ch%d_spec_rs2_addr;" % (chidx)) print(" wire [4:0] ch%d_spec_rd_addr;" % (chidx)) print(" wire [%d:0] ch%d_spec_rd_wdata;" % (xlen-1, chidx)) print(" wire [%d:0] ch%d_spec_pc_wdata;" % (xlen-1, chidx)) print(" wire [%d:0] ch%d_spec_mem_addr;" % (xlen-1, chidx)) print(" wire [%d:0] ch%d_spec_mem_rmask;" % (xlen//8-1, chidx)) print(" wire [%d:0] ch%d_spec_mem_wmask;" % (xlen//8-1, chidx)) print(" wire [%d:0] ch%d_spec_mem_wdata;" % (xlen-1, chidx)) print() print(" %s_isa_spec ch%d_isa_spec (" % (prefix, chidx)) for p in """rvfi_valid rvfi_insn rvfi_pc_rdata rvfi_rs1_rdata rvfi_rs2_rdata rvfi_mem_rdata spec_valid spec_trap spec_rs1_addr spec_rs2_addr spec_rd_addr spec_rd_wdata spec_pc_wdata spec_mem_addr spec_mem_rmask spec_mem_wmask spec_mem_wdata""".split(): print(" .%s(ch%d_%s)%s" % (p, chidx, p, "," if p != "spec_mem_wdata" else "")) print(" );") print() errcodes.append("ch%d_errcode" % (chidx)) print(" reg [15:0] ch%d_errcode;" % (chidx)) print() print(" task ch%d_handle_error;" % (chidx)) print(" input [15:0] code;") print(" input [511:0] msg;") print(" begin") if not quiet_mode: print(" $display(\"-------- RVFI Monitor error %%0d in channel %d: %%m at time %%0t --------\", code, $time);" % (chidx)) print(" $display(\"Error message: %0s\", msg);") for p in """rvfi_valid rvfi_order rvfi_insn rvfi_trap rvfi_halt rvfi_intr rvfi_rs1_addr rvfi_rs2_addr rvfi_rs1_rdata rvfi_rs2_rdata rvfi_rd_addr rvfi_rd_wdata rvfi_pc_rdata rvfi_pc_wdata rvfi_mem_addr rvfi_mem_rmask rvfi_mem_wmask rvfi_mem_rdata rvfi_mem_wdata spec_valid spec_trap spec_rs1_addr spec_rs2_addr spec_rd_addr spec_rd_wdata spec_pc_wdata spec_mem_addr spec_mem_rmask spec_mem_wmask spec_mem_wdata""".split(): print(" $display(\"%s = %%x\", ch%d_%s);" % (p, chidx, p)) print(" ch%d_errcode <= code;" % (chidx)) if use_assert: print(" assert(0);") print(" end") print(" endtask") print() print(" always @(posedge clock) begin") print(" ch%d_errcode <= 0;" % (chidx)) print(" if (!reset && ch%d_rvfi_valid) begin" % (chidx)) if verbose_mode: print(" $display(\"-------- RVFI Monitor insn in channel %d: %%m at time %%0t --------\", $time);" % (chidx)) for p in """rvfi_valid rvfi_order rvfi_insn rvfi_trap rvfi_halt rvfi_intr rvfi_rs1_addr rvfi_rs2_addr rvfi_rs1_rdata rvfi_rs2_rdata rvfi_rd_addr rvfi_rd_wdata rvfi_pc_rdata rvfi_pc_wdata rvfi_mem_addr rvfi_mem_rmask rvfi_mem_wmask rvfi_mem_rdata rvfi_mem_wdata spec_valid spec_trap""".split(): print(" $display(\"%s = %%x\", ch%d_%s);" % (p, chidx, p)) print(" if (ch%d_spec_valid) begin" % (chidx)) print(" if (ch%d_rvfi_trap != ch%d_spec_trap) begin" % (chidx, chidx)) print(" ch%d_handle_error(%d, \"mismatch in trap\");" % (chidx, 100*(1+chidx)+1)) print(" end") print(" if (ch%d_rvfi_rs1_addr != ch%d_spec_rs1_addr && ch%d_spec_rs1_addr != 0) begin" % (chidx, chidx, chidx)) print(" ch%d_handle_error(%d, \"mismatch in rs1_addr\");" % (chidx, 100*(1+chidx)+2)) print(" end") print(" if (ch%d_rvfi_rs2_addr != ch%d_spec_rs2_addr && ch%d_spec_rs2_addr != 0) begin" % (chidx, chidx, chidx)) print(" ch%d_handle_error(%d, \"mismatch in rs2_addr\");" % (chidx, 100*(1+chidx)+3)) print(" end") print(" if (ch%d_rvfi_rd_addr != ch%d_spec_rd_addr) begin" % (chidx, chidx)) print(" ch%d_handle_error(%d, \"mismatch in rd_addr\");" % (chidx, 100*(1+chidx)+4)) print(" end") if ignore_mem: print(" if (ch%d_rvfi_rd_wdata != ch%d_spec_rd_wdata && !ch%d_spec_mem_rmask) begin" % (chidx, chidx, chidx)) print(" ch%d_handle_error(%d, \"mismatch in rd_wdata\");" % (chidx, 100*(1+chidx)+5)) print(" end") else: print(" if (ch%d_rvfi_rd_wdata != ch%d_spec_rd_wdata) begin" % (chidx, chidx)) print(" ch%d_handle_error(%d, \"mismatch in rd_wdata\");" % (chidx, 100*(1+chidx)+5)) print(" end") print(" if (ch%d_rvfi_pc_wdata != ch%d_spec_pc_wdata) begin" % (chidx, chidx)) print(" ch%d_handle_error(%d, \"mismatch in pc_wdata\");" % (chidx, 100*(1+chidx)+6)) print(" end") if not ignore_mem: print(" if (ch%d_rvfi_mem_wmask != ch%d_spec_mem_wmask) begin" % (chidx, chidx)) print(" ch%d_handle_error(%d, \"mismatch in mem_wmask\");" % (chidx, 100*(1+chidx)+8)) print(" end") for i in range(xlen//8): print(" if (!ch%d_rvfi_mem_rmask[%d] && ch%d_spec_mem_rmask[%d]) begin" % (chidx, i, chidx, i)) print(" ch%d_handle_error(%d, \"mismatch in mem_rmask[%d]\");" % (chidx, 100*(1+chidx)+10+i, i)) print(" end") print(" if (ch%d_rvfi_mem_wmask[%d] && ch%d_rvfi_mem_wdata[%d:%d] != ch%d_spec_mem_wdata[%d:%d]) begin" % (chidx, i, chidx, 8*i+7, 8*i, chidx, 8*i+7, 8*i)) print(" ch%d_handle_error(%d, \"mismatch in mem_wdata[%d:%d]\");" % (chidx, 100*(1+chidx)+20+i, 8*i+7, 8*i)) print(" end") print(" if (ch%d_rvfi_mem_addr != ch%d_spec_mem_addr && (ch%d_rvfi_mem_wmask || ch%d_rvfi_mem_rmask)) begin" % (chidx, chidx, chidx, chidx)) print(" ch%d_handle_error(%d, \"mismatch in mem_addr\");" % (chidx, 100*(1+chidx)+7)) print(" end") print(" end") print(" end") print(" end") print() if not nopccheck or not noregscheck: for chidx in range(channels): rob_data_width = 3*5 + 5*xlen + 2 print(" wire rob_i%d_valid;" % chidx) print(" wire [63:0] rob_i%d_order;" % chidx) print(" wire [%d:0] rob_i%d_data;" % (rob_data_width-1, chidx)) print() print(" wire rob_o%d_valid;" % chidx) print(" wire [63:0] rob_o%d_order;" % chidx) print(" wire [%d:0] rob_o%d_data;" % (rob_data_width-1, chidx)) print() print(" wire ro%d_rvfi_valid = rob_o%d_valid;" % (chidx, chidx)) print(" assign rob_i%d_valid = ch%d_rvfi_valid;" % (chidx, chidx)) print() print(" wire [63:0] ro%d_rvfi_order = rob_o%d_order;" % (chidx, chidx)) print(" assign rob_i%d_order = ch%d_rvfi_order;" % (chidx, chidx)) print() cursor = 0 for n, w in [("rs1_addr", 5), ("rs2_addr", 5), ("rd_addr", 5), ("rs1_rdata", xlen), ("rs2_rdata", xlen), ("rd_wdata", xlen), ("pc_rdata", xlen), ("pc_wdata", xlen), ("intr", 1), ("trap", 1)]: print(" wire [%d:0] ro%d_rvfi_%s = rob_o%d_data[%d:%d];" % (w-1, chidx, n, chidx, cursor+w-1, cursor)) print(" assign rob_i%d_data[%d:%d] = ch%d_rvfi_%s;" % (chidx, cursor+w-1, cursor, chidx, n)) print() cursor += w errcodes.append("rob_errcode") print(" wire [15:0] rob_errcode;") print() print(" %s_rob rob (" % prefix) print(" .clock(clock),") print(" .reset(reset),") for chidx in range(channels): print(" .i%d_valid(rob_i%d_valid)," % (chidx, chidx)) print(" .i%d_order(rob_i%d_order)," % (chidx, chidx)) print(" .i%d_data(rob_i%d_data)," % (chidx, chidx)) print(" .o%d_valid(rob_o%d_valid)," % (chidx, chidx)) print(" .o%d_order(rob_o%d_order)," % (chidx, chidx)) print(" .o%d_data(rob_o%d_data)," % (chidx, chidx)) print(" .errcode(rob_errcode)") print(" );") print() if not quiet_mode or use_assert: print(" always @(posedge clock) begin") print(" if (!reset && rob_errcode) begin") if not quiet_mode: print(" $display(\"-------- RVFI Monitor ROB error %0d: %m at time %0t --------\", rob_errcode, $time);") print(" $display(\"No details on ROB errors available.\");") if use_assert: print(" assert(0);") print(" end") print(" end") print() if not nopccheck: print(" reg shadow_pc_valid;") print(" reg shadow_pc_trap;") print(" reg [%d:0] shadow_pc;" % (xlen-1)) print() for chidx in range(channels): print(" reg shadow%d_pc_valid;" % (chidx)) print(" reg shadow%d_pc_trap;" % (chidx)) print(" reg [%d:0] shadow%d_pc_rdata;" % (xlen-1, chidx)) print() errcodes.append("ro%d_errcode_p" % (chidx)) print(" reg [15:0] ro%d_errcode_p;" % (chidx)) print() print(" task ro%d_handle_error_p;" % (chidx)) print(" input [15:0] code;") print(" input [511:0] msg;") print(" begin") if not quiet_mode: print(" $display(\"-------- RVFI Monitor error %%0d in reordered channel %d: %%m at time %%0t --------\", code, $time);" % (chidx)) print(" $display(\"Error message: %0s\", msg);") for p in """rvfi_valid rvfi_order rvfi_rs1_addr rvfi_rs2_addr rvfi_rs1_rdata rvfi_rs2_rdata rvfi_rd_addr rvfi_rd_wdata rvfi_pc_rdata rvfi_pc_wdata rvfi_intr rvfi_trap""".split(): print(" $display(\"%s = %%x\", ro%d_%s);" % (p, chidx, p)) for p in """pc_valid pc_rdata""".split(): print(" $display(\"shadow_%s = %%x\", shadow%d_%s);" % (p, chidx, p)) print(" ro%d_errcode_p <= code;" % (chidx)) if use_assert: print(" assert(0);") print(" end") print(" endtask") print() print(" always @* begin") print(" shadow%d_pc_valid = shadow_pc_valid;" % (chidx)) print(" shadow%d_pc_trap = shadow_pc_trap;" % (chidx)) print(" shadow%d_pc_rdata = shadow_pc;" % (chidx)) for i in range(chidx): print(" if (!reset && ro%d_rvfi_valid) begin" % (i)) print(" shadow%d_pc_valid = !ro%d_rvfi_trap;" % (chidx, chidx)) print(" shadow%d_pc_trap = ro%d_rvfi_trap;" % (chidx, chidx)) print(" shadow%d_pc_rdata = ro%d_rvfi_pc_wdata;" % (chidx, i)) print(" end") print(" end") print() print(" always @(posedge clock) begin") for chidx in range(channels): print(" ro%d_errcode_p <= 0;" % chidx) print(" if (reset) begin") print(" shadow_pc_valid <= 0;") print(" shadow_pc_trap <= 0;") print(" end") for chidx in range(channels): print(" if (!reset && ro%d_rvfi_valid) begin" % (chidx)) print(" if (shadow%d_pc_valid && shadow%d_pc_rdata != ro%d_rvfi_pc_rdata && !ro%d_rvfi_intr) begin" % (chidx, chidx, chidx, chidx)) print(" ro%d_handle_error_p(%d, \"mismatch with shadow pc\");" % (chidx, 100*(1+chidx)+30)) print(" end") print(" if (shadow%d_pc_valid && shadow%d_pc_trap && !ro%d_rvfi_intr) begin" % (chidx, chidx, chidx)) print(" ro%d_handle_error_p(%d, \"expected intr after trap\");" % (chidx, 100*(1+chidx)+33)) print(" end") print(" shadow_pc_valid <= !ro%d_rvfi_trap;" % (chidx)) print(" shadow_pc_trap <= ro%d_rvfi_trap;" % (chidx)) print(" shadow_pc <= ro%d_rvfi_pc_wdata;" % (chidx)) print(" end") print(" end") print() if not noregscheck: print(" reg [31:0] shadow_xregs_valid;") print(" reg [%d:0] shadow_xregs [0:31];" % (xlen-1)) print() for chidx in range(channels): print(" reg shadow%d_rs1_valid;" % (chidx)) print(" reg shadow%d_rs2_valid;" % (chidx)) print(" reg [%d:0] shadow%d_rs1_rdata;" % (xlen-1, chidx)) print(" reg [%d:0] shadow%d_rs2_rdata;" % (xlen-1, chidx)) print() errcodes.append("ro%d_errcode_r" % (chidx)) print(" reg [15:0] ro%d_errcode_r;" % (chidx)) print() print(" task ro%d_handle_error_r;" % (chidx)) print(" input [15:0] code;") print(" input [511:0] msg;") print(" begin") if not quiet_mode: print(" $display(\"-------- RVFI Monitor error %%0d in reordered channel %d: %%m at time %%0t --------\", code, $time);" % (chidx)) print(" $display(\"Error message: %0s\", msg);") for p in """rvfi_valid rvfi_order rvfi_rs1_addr rvfi_rs2_addr rvfi_rs1_rdata rvfi_rs2_rdata rvfi_rd_addr rvfi_rd_wdata rvfi_pc_rdata rvfi_pc_wdata rvfi_intr rvfi_trap""".split(): print(" $display(\"%s = %%x\", ro%d_%s);" % (p, chidx, p)) for p in """rs1_valid rs1_rdata rs2_valid rs2_rdata""".split(): print(" $display(\"shadow_%s = %%x\", shadow%d_%s);" % (p, chidx, p)) print(" ro%d_errcode_r <= code;" % (chidx)) if use_assert: print(" assert(0);") print(" end") print(" endtask") print() for rs in ["rs1", "rs2"]: print(" always @* begin") print(" shadow%d_%s_valid = 0;" % (chidx, rs)) print(" shadow%d_%s_rdata = 0;" % (chidx, rs)) print(" if (!reset && ro%d_rvfi_valid) begin" % (chidx)) print(" shadow%d_%s_valid = shadow_xregs_valid[ro%d_rvfi_%s_addr];" % (chidx, rs, chidx, rs)) print(" shadow%d_%s_rdata = shadow_xregs[ro%d_rvfi_%s_addr];" % (chidx, rs, chidx, rs)) for i in range(chidx): print(" if (ro%d_rvfi_valid && ro%d_rvfi_rd_addr == ro%d_rvfi_%s_addr) begin" % (i, i, chidx, rs)) print(" shadow%d_%s_valid = 1;" % (chidx, rs)) print(" shadow%d_%s_rdata = ro%d_rvfi_rd_wdata;" % (chidx, rs, i)) print(" end") print(" end") print(" end") print() print(" always @(posedge clock) begin") for chidx in range(channels): print(" ro%d_errcode_r <= 0;" % chidx) print(" if (reset) begin") print(" shadow_xregs_valid <= 1;") print(" shadow_xregs[0] <= 0;") print(" end") for chidx in range(channels): print(" if (!reset && ro%d_rvfi_valid) begin" % (chidx)) for rs in ["rs1", "rs2"]: print(" if (shadow%d_%s_valid && shadow%d_%s_rdata != ro%d_rvfi_%s_rdata) begin" % (chidx, rs, chidx, rs, chidx, rs)) print(" ro%d_handle_error_r(%d, \"mismatch with shadow %s\");" % (chidx, 100*(1+chidx)+(31 if rs == "rs1" else 32), rs)) print(" end") print(" shadow_xregs_valid[ro%d_rvfi_rd_addr] <= 1;" % (chidx)) print(" shadow_xregs[ro%d_rvfi_rd_addr] <= ro%d_rvfi_rd_wdata;" % (chidx, chidx)) print(" end") print(" end") print() print(" always @(posedge clock) begin") print(" errcode <= 0;") print(" if (!reset) begin") for v in errcodes: print(" if (%s) errcode <= %s;" % (v, v)) print(" end") print(" end") print("endmodule") if not nopccheck or not noregscheck: print() print("module %s_rob (" % prefix) print(" input clock,") print(" input reset,") for chidx in range(channels): print(" input i%d_valid," % (chidx)) print(" input [63:0] i%d_order," % (chidx)) print(" input [%d:0] i%d_data," % (rob_data_width-1, chidx)) print(" output reg o%d_valid," % (chidx)) print(" output reg [63:0] o%d_order," % (chidx)) print(" output reg [%d:0] o%d_data," % (rob_data_width-1, chidx)) if robdepth == 0: print(" output wire [15:0] errcode") else: print(" output reg [15:0] errcode") print(");") if robdepth == 0: for chidx in range(channels): print(" always @* o%d_valid = i%d_valid;" % (chidx, chidx)) print(" always @* o%d_order = i%d_order;" % (chidx, chidx)) print(" always @* o%d_data = i%d_data;" % (chidx, chidx)) print(" assign errcode = 0;") else: orderbits = ceil(log2(robdepth)) print(" reg [%d:0] buffer [0:%d];" % (64+rob_data_width-1, robdepth-1)) print(" reg [%d:0] valid;" % (robdepth-1)) print(" reg [63:0] cursor;") print(" reg continue_flag;") print() print(" always @(posedge clock) begin") for chidx in range(channels): print(" o%d_valid <= 0;" % (chidx)) print(" errcode <= 0;") print(" continue_flag = 1;") print(" if (reset) begin") print(" valid <= 0;") print(" cursor = 0;") print(" end else begin") for chidx in range(channels): print(" if (i%d_valid) begin" % (chidx)) print(" if (valid[i%d_order[%d:0]])" % (chidx, orderbits-1)) print(" errcode <= 60000 + i%d_order[7:0];" % (chidx)) print(" buffer[i%d_order[%d:0]] <= {i%d_data, i%d_order};" % (chidx, orderbits-1, chidx, chidx)) print(" valid[i%d_order[%d:0]] <= 1;" % (chidx, orderbits-1)) print(" end") for chidx in range(channels): print(" if (continue_flag && valid[cursor[%d:0]]) begin" % (orderbits-1)) print(" if (buffer[cursor[%d:0]][63:0] != cursor)" % (orderbits-1)) print(" errcode <= 61000 + cursor[7:0];") print(" o%d_valid <= 1;" % (chidx)) print(" o%d_order <= buffer[cursor[%d:0]][63:0];" % (chidx, orderbits-1)) print(" o%d_data <= buffer[cursor[%d:0]][%d:64];" % (chidx, orderbits-1, 64+rob_data_width-1)) print(" valid[cursor[%d:0]] <= 0;" % (orderbits-1)) print(" cursor = cursor + 1;") print(" end else begin") print(" continue_flag = 0;") print(" end") print(" end") print(" end") print("endmodule") replace_db = list() replace_db.append((" rvfi_isa_%s " % isa, " %s_isa_spec " % prefix)) replace_db.append(("`RISCV_FORMAL_XLEN", str(xlen))) replace_db.append(("`RISCV_FORMAL_ILEN", str(ilen))) insn_list = list() with open("../insns/isa_%s.txt" % isa) as f: for insn in f: insn = insn.strip() insn_list.append(insn) replace_db.append((" rvfi_insn_%s " % insn, " %s_insn_%s " % (prefix, insn))) expected_flags = { "RISCV_FORMAL_COMPRESSED": compressed, "RISCV_FORMAL_ALIGNED_MEM": aligned, } def print_rewrite_file(filename): with open(filename) as f: flag_stack = [] flags = {} for line in f: if line.startswith("`ifdef "): flag_name = line.split()[1] assert flag_name not in flags, (filename, flag_name, flags) flag_stack.append(flag_name) flags[flag_name] = True continue if line.startswith("`ifndef "): flag_name = line.split()[1] assert flag_name not in flags flag_stack.append(flag_name) flags[flag_name] = False continue if line.startswith("`else"): flag_name = flag_stack[-1] flags[flag_name] = not flags[flag_name] continue if line.startswith("`endif"): flag_name = flag_stack.pop() del flags[flag_name] continue if any(expected_flags.get(name, False) != val for name, val in flags.items()): continue for a, b in replace_db: line = line.replace(a, b) print(line, end="") print() print_rewrite_file("../insns/isa_%s.v" % isa) for insn in insn_list: print() print_rewrite_file("../insns/insn_%s.v" % insn) ================================================ FILE: tests/coverage/.gitignore ================================================ /coverage_rv32 /coverage_rv64 /isa_coverage_rv32i.v /isa_coverage_rv32ic.v /isa_coverage_rv64i.v /isa_coverage_rv64ic.v ================================================ FILE: tests/coverage/coverage.sby ================================================ [tasks] rv32 rv64 [options] mode bmc depth 1 [engines] smtbmc yices [script] verilog_defines -D RISCV_FORMAL verilog_defines -D RISCV_FORMAL_NRET=1 rv32: verilog_defines -D RISCV_FORMAL_XLEN=32 rv64: verilog_defines -D RISCV_FORMAL_XLEN=64 verilog_defines -D RISCV_FORMAL_ILEN=32 verilog_defines -D RISCV_FORMAL_COMPRESSED read_verilog -sv rvfi_macros.vh --pycode-begin-- import os for filename in os.listdir("../../insns/"): if filename.startswith("insn_") and filename.endswith(".v"): output("read_verilog -sv %s" % filename) --pycode-end-- read_verilog isa_coverage_rv32i.v read_verilog isa_coverage_rv32ic.v read_verilog isa_coverage_rv64i.v read_verilog isa_coverage_rv64ic.v read_verilog riscv_rv32i_insn.v read_verilog riscv_rv32ic_insn.v read_verilog riscv_rv64i_insn.v read_verilog riscv_rv64ic_insn.v read_verilog -sv coverage.sv rv32: prep -flatten -top coverage32 rv64: prep -flatten -top coverage64 [files] coverage.sv ../../checks/rvfi_macros.vh --pycode-begin-- import os for filename in os.listdir("../../insns/"): if filename.startswith("insn_") and filename.endswith(".v"): output("../../insns/%s" % filename) --pycode-end-- isa_coverage_rv32i.v isa_coverage_rv32ic.v isa_coverage_rv64i.v isa_coverage_rv64ic.v riscv_rv32i_insn.v riscv_rv32ic_insn.v riscv_rv64i_insn.v riscv_rv64ic_insn.v ================================================ FILE: tests/coverage/coverage.sv ================================================ module coverage32(input [31:0] insn); wire [`ISA_COVERAGE_LEN_RV32I-1:0] insn_valid_rv32i; wire [`ISA_COVERAGE_LEN_RV32IC-1:0] insn_valid_rv32ic; wire riscv_rv32i_valid; wire riscv_rv32ic_valid; isa_coverage_rv32i isa_coverage_rv32i_inst (.insn(insn), .valid(insn_valid_rv32i )); isa_coverage_rv32ic isa_coverage_rv32ic_inst (.insn(insn), .valid(insn_valid_rv32ic)); riscv_rv32i_insn riscv_rv32i_insn_inst (.insn(insn), .valid(riscv_rv32i_valid )); riscv_rv32ic_insn riscv_rv32ic_insn_inst (.insn(insn), .valid(riscv_rv32ic_valid)); always_comb begin // check one-hot conditions assert(insn_valid_rv32i == (insn_valid_rv32i & -insn_valid_rv32i )); assert(insn_valid_rv32ic == (insn_valid_rv32ic & -insn_valid_rv32ic)); // check insn hierarchy if (insn_valid_rv32i) assert(insn_valid_rv32ic); // check hand-written checkers assert(riscv_rv32i_valid == |insn_valid_rv32i); assert(riscv_rv32ic_valid == |insn_valid_rv32ic); end endmodule module coverage64(input [31:0] insn); wire [`ISA_COVERAGE_LEN_RV64I-1:0] insn_valid_rv64i; wire [`ISA_COVERAGE_LEN_RV64IC-1:0] insn_valid_rv64ic; wire riscv_rv64i_valid; wire riscv_rv64ic_valid; isa_coverage_rv64i isa_coverage_rv64i_inst (.insn(insn), .valid(insn_valid_rv64i )); isa_coverage_rv64ic isa_coverage_rv64ic_inst (.insn(insn), .valid(insn_valid_rv64ic)); riscv_rv64i_insn riscv_rv64i_insn_inst (.insn(insn), .valid(riscv_rv64i_valid )); riscv_rv64ic_insn riscv_rv64ic_insn_inst (.insn(insn), .valid(riscv_rv64ic_valid)); always_comb begin // check one-hot conditions assert(insn_valid_rv64i == (insn_valid_rv64i & -insn_valid_rv64i )); assert(insn_valid_rv64ic == (insn_valid_rv64ic & -insn_valid_rv64ic)); // check insn hierarchy if (insn_valid_rv64i) assert(insn_valid_rv64ic); // check hand-written checkers assert(riscv_rv64i_valid == |insn_valid_rv64i); assert(riscv_rv64ic_valid == |insn_valid_rv64ic); end endmodule ================================================ FILE: tests/coverage/generate.py ================================================ #!/usr/bin/env python3 def handle_isa(isa): with open("../../insns/isa_%s.txt" % isa, "r") as f: insns = f.read().split() with open("isa_coverage_%s.v" % isa, "w") as f: print("// DO NOT EDIT -- auto-generated from riscv-formal/tests/coverage/generate.py", file=f) print("", file=f) print("`define ISA_COVERAGE_LEN_%s %d" % (isa.upper(), len(insns)), file=f) print("module isa_coverage_%s (input [31:0] insn, output [%d:0] valid);" % (isa, len(insns)-1), file=f) for index, insn in enumerate(sorted(insns)): print(" rvfi_insn_%s insn_%s (" % (insn, insn), file=f) print(" .rvfi_valid(1'b1),", file=f) print(" .rvfi_insn(insn),", file=f) print(" .rvfi_pc_rdata(32'h00000000),", file=f) print(" .rvfi_rs1_rdata(32'h00000000),", file=f) print(" .rvfi_rs2_rdata(32'h00000000),", file=f) print(" .rvfi_mem_rdata(32'h00000000),", file=f) print(" .spec_valid(valid[%d])" % index, file=f) print(" );", file=f) print("endmodule", file=f) handle_isa("rv32i") handle_isa("rv32ic") handle_isa("rv64i") handle_isa("rv64ic") ================================================ FILE: tests/coverage/riscv_rv32i_insn.v ================================================ // Check if a given instruction is an RV32I instruction (without SYSTEM opcode) // module riscv_rv32i_insn ( input [31:0] insn, output reg valid ); always @* begin valid = 0; if (insn[6:0] == 7'b 01_101_11) valid = 1; // LUI if (insn[6:0] == 7'b 00_101_11) valid = 1; // AUIPC if (insn[6:0] == 7'b 11_011_11) valid = 1; // JAL if (insn[6:0] == 7'b 11_001_11) begin // JALR valid = insn[14:12] == 3'b 000; end if (insn[6:0] == 7'b 11_000_11) begin // BRANCH valid = (insn[14:12] != 3'b 010) && (insn[14:12] != 3'b 011); end if (insn[6:0] == 7'b 00_000_11) begin // LOAD valid = (insn[14:12] != 3'b 011) && (insn[14:12] != 3'b 110) && (insn[14:12] != 3'b 111); end if (insn[6:0] == 7'b 01_000_11) begin // STORE valid = (insn[14:12] == 3'b 000) || (insn[14:12] == 3'b 001) || (insn[14:12] == 3'b 010); end if (insn[6:0] == 7'b 00_100_11) begin // OP-IMM case (insn[14:12]) 3'b 001: begin // SLLI valid = insn[31:25] == 7'b 0000000; end 3'b 101: begin // SRLI SRAI valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); end default: begin valid = 1; end endcase end if (insn[6:0] == 7'b 01_100_11) begin // OP case (insn[14:12]) 3'b 000, 3'b 101: begin // ADD SUB SRL SRA valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); end default: begin valid = insn[31:25] == 7'b 0000000; end endcase end end endmodule ================================================ FILE: tests/coverage/riscv_rv32ic_insn.v ================================================ // Check if a given instruction is an RV32IC instruction (without SYSTEM opcode) // module riscv_rv32ic_insn ( input [31:0] insn, output reg valid ); always @* begin valid = 0; if (insn[6:0] == 7'b 01_101_11) valid = 1; // LUI if (insn[6:0] == 7'b 00_101_11) valid = 1; // AUIPC if (insn[6:0] == 7'b 11_011_11) valid = 1; // JAL if (insn[6:0] == 7'b 11_001_11) begin // JALR valid = insn[14:12] == 3'b 000; end if (insn[6:0] == 7'b 11_000_11) begin // BRANCH valid = (insn[14:12] != 3'b 010) && (insn[14:12] != 3'b 011); end if (insn[6:0] == 7'b 00_000_11) begin // LOAD valid = (insn[14:12] != 3'b 011) && (insn[14:12] != 3'b 110) && (insn[14:12] != 3'b 111); end if (insn[6:0] == 7'b 01_000_11) begin // STORE valid = (insn[14:12] == 3'b 000) || (insn[14:12] == 3'b 001) || (insn[14:12] == 3'b 010); end if (insn[6:0] == 7'b 00_100_11) begin // OP-IMM case (insn[14:12]) 3'b 001: begin // SLLI valid = insn[31:25] == 7'b 0000000; end 3'b 101: begin // SRLI SRAI valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); end default: begin valid = 1; end endcase end if (insn[6:0] == 7'b 01_100_11) begin // OP case (insn[14:12]) 3'b 000, 3'b 101: begin // ADD SUB SRL SRA valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); end default: begin valid = insn[31:25] == 7'b 0000000; end endcase end if (insn[31:16] == 16'b0 && insn[1:0] != 2'b11) begin casez (insn[15:0]) // RVC -- Quadrant 0 16'b 000_???_???_??_???_00: valid = |insn[12:5]; // C.ADDI4SPN 16'b 010_???_???_??_???_00: valid = 1; // C.LW 16'b 110_???_???_??_???_00: valid = 1; // C.SW // RVC -- Quadrant 1 16'b 000_?_??_???_??_???_01: valid = 1; // C.NOP, C.ADDI 16'b 001_?_??_???_??_???_01: valid = 1; // C.JAL 16'b 010_?_??_???_??_???_01: valid = 1; // C.LI 16'b 011_?_??_???_??_???_01: valid = |{insn[12], insn[6:2]}; // C.ADDI16SP, C.LUI 16'b 100_?_00_???_??_???_01: valid = !insn[12]; // C.SRLI 16'b 100_?_01_???_??_???_01: valid = !insn[12]; // C.SRAI 16'b 100_?_10_???_??_???_01: valid = 1; // C.ANDI 16'b 100_0_11_???_00_???_01: valid = 1; // C.SUB 16'b 100_0_11_???_01_???_01: valid = 1; // C.XOR 16'b 100_0_11_???_10_???_01: valid = 1; // C.OR 16'b 100_0_11_???_11_???_01: valid = 1; // C.AND 16'b 101_?_??_???_??_???_01: valid = 1; // C.J 16'b 110_?_??_???_??_???_01: valid = 1; // C.BEQZ 16'b 111_?_??_???_??_???_01: valid = 1; // C.BNEZ // RVC -- Quadrant 2 16'b 000_?_?????_?????_10: valid = !insn[12]; // C.SLLI 16'b 010_?_?????_?????_10: valid = |insn[11:7]; // C.LWSP 16'b 100_0_?????_00000_10: valid = |insn[11:7]; // C.JR 16'b 100_0_?????_?????_10: valid = |insn[6:2]; // C.MV 16'b 100_1_00000_00000_10: valid = 0; // C.EBREAK (SYSTEM => valid=0) 16'b 100_1_?????_?????_10: valid = 1; // C.JALR, C.ADD 16'b 110_?_?????_?????_10: valid = 1; // C.SWSP endcase end end endmodule ================================================ FILE: tests/coverage/riscv_rv64i_insn.v ================================================ // Check if a given instruction is an RV64I instruction (without SYSTEM opcode) // module riscv_rv64i_insn ( input [31:0] insn, output reg valid ); always @* begin valid = 0; if (insn[6:0] == 7'b 01_101_11) valid = 1; // LUI if (insn[6:0] == 7'b 00_101_11) valid = 1; // AUIPC if (insn[6:0] == 7'b 11_011_11) valid = 1; // JAL if (insn[6:0] == 7'b 11_001_11) begin // JALR valid = insn[14:12] == 3'b 000; end if (insn[6:0] == 7'b 11_000_11) begin // BRANCH valid = (insn[14:12] != 3'b 010) && (insn[14:12] != 3'b 011); end if (insn[6:0] == 7'b 00_000_11) begin // LOAD valid = (insn[14:12] != 3'b 111); end if (insn[6:0] == 7'b 01_000_11) begin // STORE valid = (insn[14:12] == 3'b 000) || (insn[14:12] == 3'b 001) || (insn[14:12] == 3'b 010) || (insn[14:12] == 3'b 011); end if (insn[6:0] == 7'b 00_100_11) begin // OP-IMM case (insn[14:12]) 3'b 001: begin // SLLI valid = insn[31:26] == 6'b 000000; end 3'b 101: begin // SRLI SRAI valid = (insn[31:26] == 6'b 000000) || (insn[31:26] == 6'b 010000); end default: begin valid = 1; end endcase end if (insn[6:0] == 7'b 01_100_11) begin // OP case (insn[14:12]) 3'b 000, 3'b 101: begin // ADD SUB SRL SRA valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); end default: begin valid = insn[31:25] == 7'b 0000000; end endcase end if (insn[6:0] == 7'b 00_110_11) begin // OP-IMM-32 case (insn[14:12]) 3'b 001: begin // SLLIW valid = insn[31:25] == 7'b 0000000; end 3'b 101: begin // SRLIW SRAIW valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); end 3'b 000: begin // ADDIW valid = 1; end endcase end if (insn[6:0] == 7'b 01_110_11) begin // OP-32 case (insn[14:12]) 3'b 000, 3'b 101: begin // ADDW SUBW SRLW SRAW valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); end 3'b 001: begin // SLLW valid = insn[31:25] == 7'b 0000000; end endcase end end endmodule ================================================ FILE: tests/coverage/riscv_rv64ic_insn.v ================================================ // Check if a given instruction is an RV64IC instruction (without SYSTEM opcode) // module riscv_rv64ic_insn ( input [31:0] insn, output reg valid ); always @* begin valid = 0; if (insn[6:0] == 7'b 01_101_11) valid = 1; // LUI if (insn[6:0] == 7'b 00_101_11) valid = 1; // AUIPC if (insn[6:0] == 7'b 11_011_11) valid = 1; // JAL if (insn[6:0] == 7'b 11_001_11) begin // JALR valid = insn[14:12] == 3'b 000; end if (insn[6:0] == 7'b 11_000_11) begin // BRANCH valid = (insn[14:12] != 3'b 010) && (insn[14:12] != 3'b 011); end if (insn[6:0] == 7'b 00_000_11) begin // LOAD valid = (insn[14:12] != 3'b 111); end if (insn[6:0] == 7'b 01_000_11) begin // STORE valid = (insn[14:12] == 3'b 000) || (insn[14:12] == 3'b 001) || (insn[14:12] == 3'b 010) || (insn[14:12] == 3'b 011); end if (insn[6:0] == 7'b 00_100_11) begin // OP-IMM case (insn[14:12]) 3'b 001: begin // SLLI valid = insn[31:26] == 6'b 000000; end 3'b 101: begin // SRLI SRAI valid = (insn[31:26] == 6'b 000000) || (insn[31:26] == 6'b 010000); end default: begin valid = 1; end endcase end if (insn[6:0] == 7'b 01_100_11) begin // OP case (insn[14:12]) 3'b 000, 3'b 101: begin // ADD SUB SRL SRA valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); end default: begin valid = insn[31:25] == 7'b 0000000; end endcase end if (insn[6:0] == 7'b 00_110_11) begin // OP-IMM-32 case (insn[14:12]) 3'b 001: begin // SLLIW valid = insn[31:25] == 7'b 0000000; end 3'b 101: begin // SRLIW SRAIW valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); end 3'b 000: begin // ADDIW valid = 1; end endcase end if (insn[6:0] == 7'b 01_110_11) begin // OP-32 case (insn[14:12]) 3'b 000, 3'b 101: begin // ADDW SUBW SRLW SRAW valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); end 3'b 001: begin // SLLW valid = insn[31:25] == 7'b 0000000; end endcase end if (insn[31:16] == 16'b0 && insn[1:0] != 2'b11) begin casez (insn[15:0]) // RVC -- Quadrant 0 16'b 000_???_???_??_???_00: valid = |insn[12:5]; // C.ADDI4SPN 16'b 010_???_???_??_???_00: valid = 1; // C.LW 16'b 011_???_???_??_???_00: valid = 1; // C.LD 16'b 110_???_???_??_???_00: valid = 1; // C.SW 16'b 111_???_???_??_???_00: valid = 1; // C.SD // RVC -- Quadrant 1 16'b 000_?_??_???_??_???_01: valid = 1; // C.NOP, C.ADDI 16'b 001_?_??_???_??_???_01: valid = |insn[11:7]; // C.ADDIW 16'b 010_?_??_???_??_???_01: valid = 1; // C.LI 16'b 011_?_??_???_??_???_01: valid = |{insn[12], insn[6:2]}; // C.ADDI16SP, C.LUI 16'b 100_?_00_???_??_???_01: valid = 1; // C.SRLI 16'b 100_?_01_???_??_???_01: valid = 1; // C.SRAI 16'b 100_?_10_???_??_???_01: valid = 1; // C.ANDI 16'b 100_0_11_???_00_???_01: valid = 1; // C.SUB 16'b 100_0_11_???_01_???_01: valid = 1; // C.XOR 16'b 100_0_11_???_10_???_01: valid = 1; // C.OR 16'b 100_0_11_???_11_???_01: valid = 1; // C.AND 16'b 100_1_11_???_00_???_01: valid = 1; // C.SUBW 16'b 100_1_11_???_01_???_01: valid = 1; // C.ADDW 16'b 101_?_??_???_??_???_01: valid = 1; // C.J 16'b 110_?_??_???_??_???_01: valid = 1; // C.BEQZ 16'b 111_?_??_???_??_???_01: valid = 1; // C.BNEZ // RVC -- Quadrant 2 16'b 000_?_?????_?????_10: valid = 1; // C.SLLI 16'b 010_?_?????_?????_10: valid = |insn[11:7]; // C.LWSP 16'b 011_?_?????_?????_10: valid = |insn[11:7]; // C.LDSP 16'b 100_0_?????_00000_10: valid = |insn[11:7]; // C.JR 16'b 100_0_?????_?????_10: valid = |insn[6:2]; // C.MV 16'b 100_1_00000_00000_10: valid = 0; // C.EBREAK (SYSTEM => valid=0) 16'b 100_1_?????_?????_10: valid = 1; // C.JALR, C.ADD 16'b 110_?_?????_?????_10: valid = 1; // C.SWSP 16'b 111_?_?????_?????_10: valid = 1; // C.SDSP endcase end end endmodule ================================================ FILE: tests/semantics/.gitignore ================================================ /riscv-semantics /insn_* ================================================ FILE: tests/semantics/Makefile ================================================ define template all:: insn_$(1)/PASS insn_$(1)/PASS: insn_$(1).sby riscv-semantics/.stamp sby -f insn_$(1).sby insn_$(1).sby: makejob.py riscv-semantics/.stamp python3 makejob.py $(1) clean:: rm -rf insn_$(1) insn_$(1).sby endef $(foreach job,$(shell cat ../../insns/isa_rv32i.txt),$(eval $(call template,$(job)))) riscv-semantics/.stamp: set -ex; git clone --recursive https://github.com/mit-plv/riscv-semantics; \ cd riscv-semantics; ./install.sh; ./install-clash.sh; ./make-circuit.sh touch riscv-semantics/.stamp distclean: clean rm -rf riscv-semantics ================================================ FILE: tests/semantics/cexformat.py ================================================ #!/usr/bin/env python3 from Verilog_VCD.Verilog_VCD import parse_vcd from os import system, remove from sys import argv, exit from getopt import getopt def usage(): print("Usage: %s " % argv[0]) exit(1) try: opts, args = getopt(argv[1:], "", []) except: usage() for o, a in opts: usage() if len(args) != 1: usage() data = dict() for netinfo in parse_vcd(args[0]).values(): for net in netinfo['nets']: if net["hier"] == "top": data[net["name"]] = int(netinfo['tv'][0][1], 2) if net["hier"] == "top.rvspec_inst" and (net["name"].startswith("in_") or net["name"].startswith("out_")): data[net["name"]] = int(netinfo['tv'][0][1], 2) print() with open(".cexformat_tmp.s", "w") as f: print(".word 0x%08X" % data["insn"], file=f) system("riscv32-unknown-elf-gcc -c .cexformat_tmp.s") system("riscv32-unknown-elf-objdump -d -M numeric,no-aliases .cexformat_tmp.o > .cexformat_tmp.t") with open(".cexformat_tmp.t") as f: for line in f: if line.startswith(" 0:"): s = "%s (0x%s)" % (" ".join(line.split()[2:]), line.split()[1]) print(s) print("=" * len(s)) remove(".cexformat_tmp.s") remove(".cexformat_tmp.o") remove(".cexformat_tmp.t") print() for i in range(1, 32): print("x%-2d 0x%08X 0x%08X%s" % (i, data["x%d" % i], data["nx%d" % i], "" if data["x%d" % i] == data["nx%d" % i] else " <--")) print() def prvalue(name, nbits): if nbits == 1 or nbits == 5: print("%-20s %10d" % (name, data[name])) elif nbits == 4: print("%-20s 0b%s" % (name, format(data[name], "04b"))) elif nbits == 32: print("%-20s 0x%08X" % (name, data[name])) else: assert False prvalue("rvfi_valid", 1) prvalue("rvfi_insn", 32) prvalue("rvfi_rs1_rdata", 32) prvalue("rvfi_rs2_rdata", 32) print() prvalue("spec_valid", 1) prvalue("spec_trap", 1) prvalue("spec_rs1_addr", 5) prvalue("spec_rs2_addr", 5) prvalue("spec_rd_addr", 5) prvalue("spec_rd_wdata", 32) print() prvalue("rvfi_pc_rdata", 32) prvalue("spec_pc_wdata", 32) print() prvalue("spec_mem_rmask", 4) prvalue("spec_mem_wmask", 4) prvalue("spec_mem_addr", 32) prvalue("rvfi_mem_rdata", 32) prvalue("spec_mem_wdata", 32) print() prvalue("in_instr", 32) prvalue("in_pc", 32) prvalue("out_nextPC", 32) prvalue("out_exception", 1) print() prvalue("out_storeEnable", 4) prvalue("out_storeAddress", 32) prvalue("out_storeData", 32) print() prvalue("out_loadEnable", 4) prvalue("out_loadAddress", 32) prvalue("in_loadData", 32) print() print("--------") print() print("let in_instr = fromIntegral 0x%08X" % data["insn"]) print("let in_loadData = fromIntegral 0x%08X" % data["rdata"]) if data["spec_rs1_addr"]: print("let register_rs1 = Just (%d, fromIntegral 0x%08X)" % (data["spec_rs1_addr"], data["rvfi_rs1_rdata"])) else: print("let register_rs1 = Nothing") if data["spec_rs2_addr"]: print("let register_rs2 = Just (%d, fromIntegral 0x%08X)" % (data["spec_rs2_addr"], data["rvfi_rs2_rdata"])) else: print("let register_rs2 = Nothing") print() if data["spec_mem_wmask"]: print("let expected_out_store = Just (fromIntegral 0x%08X, fromIntegral 0x%08X)" % (data["spec_mem_addr"], data["spec_mem_wdata"])) else: print("let expected_out_store = Nothing") if data["spec_rd_addr"]: print("let expected_rd = Just (%d, fromIntegral 0x%08X)" % (data["spec_rd_addr"], data["spec_rd_wdata"])) else: print("let expected_rd = Nothing") if data["spec_mem_rmask"]: print("let expected_out_loadAddress = Just (fromIntegral 0x%08X)" % data["spec_mem_addr"]) else: print("let expected_out_loadAddress = Nothing") print("let expected_out_exception = %s" % ("True" if data["spec_trap"] else "False")) print() ================================================ FILE: tests/semantics/makejob.py ================================================ #!/usr/bin/env python3 import sys, glob, os insn = sys.argv[1] clash_files = glob.glob("riscv-semantics/src/verilog/Clash/rvspec/*.v") with open("insn_%s.sby" % insn, "w") as f: print("[options]", file=f) print("mode bmc", file=f) print("depth 1", file=f) print("", file=f) print("[engines]", file=f) print("smtbmc boolector", file=f) print("", file=f) print("[script]", file=f) print("read_verilog -sv defines.vh", file=f) print("read_verilog -sv rvfi_macros.vh", file=f) print("read_verilog -sv top.sv", file=f) print("read_verilog -sv insn_%s.v" % insn, file=f) for fn in clash_files: print("read_verilog %s" % os.path.basename(fn), file=f) print("prep -nordff -top top", file=f) print("flatten rvspec", file=f) print("hierarchy", file=f) print("opt -fast", file=f) print("[file defines.vh]", file=f) print("`define RISCV_FORMAL", file=f) print("`define RISCV_FORMAL_XLEN 32", file=f) print("`define RISCV_FORMAL_ILEN 32", file=f) print("`define RISCV_FORMAL_INSN_MODEL rvfi_insn_%s" % insn, file=f) print("`define RISCV_FORMAL_ALIGNED_MEM", file=f) # print("`define RISCV_FORMAL_COMPRESSED", file=f) print("", file=f) print("[files]", file=f) print("top.sv", file=f) print("../../checks/rvfi_macros.vh", file=f) print("../../insns/insn_%s.v" % insn, file=f) for fn in clash_files: print(fn, file=f) ================================================ FILE: tests/semantics/top.sv ================================================ module top ( input [31:0] insn, pc, rdata, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, input [31:0] x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31 ); (* keep *) wire [31:0] npc, nx1, nx2, nx3, nx4, nx5, nx6, nx7, nx8, nx9, nx10, nx11, nx12, nx13, nx14, nx15; (* keep *) wire [31:0] nx16, nx17, nx18, nx19, nx20, nx21, nx22, nx23, nx24, nx25, nx26, nx27, nx28, nx29, nx30, nx31; (* keep *) wire [ 3:0] ren; (* keep *) wire [31:0] raddr; (* keep *) wire [ 3:0] wen; (* keep *) wire [31:0] waddr; (* keep *) wire [31:0] wdata; (* keep *) wire excep; (* keep *) wire rvfi_valid = 1; (* keep *) wire [31:0] rvfi_insn = insn; (* keep *) wire [31:0] rvfi_pc_rdata = pc; (* keep *) reg [31:0] rvfi_rs1_rdata; (* keep *) reg [31:0] rvfi_rs2_rdata; (* keep *) wire [31:0] rvfi_mem_rdata = rdata; (* keep *) wire spec_valid; (* keep *) wire spec_trap; (* keep *) wire [ 4:0] spec_rs1_addr; (* keep *) wire [ 4:0] spec_rs2_addr; (* keep *) wire [ 4:0] spec_rd_addr; (* keep *) wire [31:0] spec_rd_wdata; (* keep *) wire [31:0] spec_pc_wdata; (* keep *) wire [31:0] spec_mem_addr; (* keep *) wire [ 3:0] spec_mem_rmask; (* keep *) wire [ 3:0] spec_mem_wmask; (* keep *) wire [31:0] spec_mem_wdata; always @* begin assume (pc[1:0] == 0); end always @* begin rvfi_rs1_rdata = 0; case (spec_rs1_addr) 1: rvfi_rs1_rdata = x1; 2: rvfi_rs1_rdata = x2; 3: rvfi_rs1_rdata = x3; 4: rvfi_rs1_rdata = x4; 5: rvfi_rs1_rdata = x5; 6: rvfi_rs1_rdata = x6; 7: rvfi_rs1_rdata = x7; 8: rvfi_rs1_rdata = x8; 9: rvfi_rs1_rdata = x9; 10: rvfi_rs1_rdata = x10; 11: rvfi_rs1_rdata = x11; 12: rvfi_rs1_rdata = x12; 13: rvfi_rs1_rdata = x13; 14: rvfi_rs1_rdata = x14; 15: rvfi_rs1_rdata = x15; 16: rvfi_rs1_rdata = x16; 17: rvfi_rs1_rdata = x17; 18: rvfi_rs1_rdata = x18; 19: rvfi_rs1_rdata = x19; 20: rvfi_rs1_rdata = x20; 21: rvfi_rs1_rdata = x21; 22: rvfi_rs1_rdata = x22; 23: rvfi_rs1_rdata = x23; 24: rvfi_rs1_rdata = x24; 25: rvfi_rs1_rdata = x25; 26: rvfi_rs1_rdata = x26; 27: rvfi_rs1_rdata = x27; 28: rvfi_rs1_rdata = x28; 29: rvfi_rs1_rdata = x29; 30: rvfi_rs1_rdata = x30; 31: rvfi_rs1_rdata = x31; endcase rvfi_rs2_rdata = 0; case (spec_rs2_addr) 1: rvfi_rs2_rdata = x1; 2: rvfi_rs2_rdata = x2; 3: rvfi_rs2_rdata = x3; 4: rvfi_rs2_rdata = x4; 5: rvfi_rs2_rdata = x5; 6: rvfi_rs2_rdata = x6; 7: rvfi_rs2_rdata = x7; 8: rvfi_rs2_rdata = x8; 9: rvfi_rs2_rdata = x9; 10: rvfi_rs2_rdata = x10; 11: rvfi_rs2_rdata = x11; 12: rvfi_rs2_rdata = x12; 13: rvfi_rs2_rdata = x13; 14: rvfi_rs2_rdata = x14; 15: rvfi_rs2_rdata = x15; 16: rvfi_rs2_rdata = x16; 17: rvfi_rs2_rdata = x17; 18: rvfi_rs2_rdata = x18; 19: rvfi_rs2_rdata = x19; 20: rvfi_rs2_rdata = x20; 21: rvfi_rs2_rdata = x21; 22: rvfi_rs2_rdata = x22; 23: rvfi_rs2_rdata = x23; 24: rvfi_rs2_rdata = x24; 25: rvfi_rs2_rdata = x25; 26: rvfi_rs2_rdata = x26; 27: rvfi_rs2_rdata = x27; 28: rvfi_rs2_rdata = x28; 29: rvfi_rs2_rdata = x29; 30: rvfi_rs2_rdata = x30; 31: rvfi_rs2_rdata = x31; endcase end always @* begin if (spec_valid) begin if (spec_trap) begin assert ( nx1 == x1); assert ( nx2 == x2); assert ( nx3 == x3); assert ( nx4 == x4); assert ( nx5 == x5); assert ( nx6 == x6); assert ( nx7 == x7); assert ( nx8 == x8); assert ( nx9 == x9); assert (nx10 == x10); assert (nx11 == x11); assert (nx12 == x12); assert (nx13 == x13); assert (nx14 == x14); assert (nx15 == x15); assert (nx16 == x16); assert (nx17 == x17); assert (nx18 == x18); assert (nx19 == x19); assert (nx20 == x20); assert (nx21 == x21); assert (nx22 == x22); assert (nx23 == x23); assert (nx24 == x24); assert (nx25 == x25); assert (nx26 == x26); assert (nx27 == x27); assert (nx28 == x28); assert (nx29 == x29); assert (nx30 == x30); assert (nx31 == x31); assert (npc == 32'h0); assert (ren == 1'b0); assert (wen == 1'b0); assert (excep); end else begin assert ( nx1 == (spec_rd_addr == 1 ? spec_rd_wdata : x1)); assert ( nx2 == (spec_rd_addr == 2 ? spec_rd_wdata : x2)); assert ( nx3 == (spec_rd_addr == 3 ? spec_rd_wdata : x3)); assert ( nx4 == (spec_rd_addr == 4 ? spec_rd_wdata : x4)); assert ( nx5 == (spec_rd_addr == 5 ? spec_rd_wdata : x5)); assert ( nx6 == (spec_rd_addr == 6 ? spec_rd_wdata : x6)); assert ( nx7 == (spec_rd_addr == 7 ? spec_rd_wdata : x7)); assert ( nx8 == (spec_rd_addr == 8 ? spec_rd_wdata : x8)); assert ( nx9 == (spec_rd_addr == 9 ? spec_rd_wdata : x9)); assert (nx10 == (spec_rd_addr == 10 ? spec_rd_wdata : x10)); assert (nx11 == (spec_rd_addr == 11 ? spec_rd_wdata : x11)); assert (nx12 == (spec_rd_addr == 12 ? spec_rd_wdata : x12)); assert (nx13 == (spec_rd_addr == 13 ? spec_rd_wdata : x13)); assert (nx14 == (spec_rd_addr == 14 ? spec_rd_wdata : x14)); assert (nx15 == (spec_rd_addr == 15 ? spec_rd_wdata : x15)); assert (nx16 == (spec_rd_addr == 16 ? spec_rd_wdata : x16)); assert (nx17 == (spec_rd_addr == 17 ? spec_rd_wdata : x17)); assert (nx18 == (spec_rd_addr == 18 ? spec_rd_wdata : x18)); assert (nx19 == (spec_rd_addr == 19 ? spec_rd_wdata : x19)); assert (nx20 == (spec_rd_addr == 20 ? spec_rd_wdata : x20)); assert (nx21 == (spec_rd_addr == 21 ? spec_rd_wdata : x21)); assert (nx22 == (spec_rd_addr == 22 ? spec_rd_wdata : x22)); assert (nx23 == (spec_rd_addr == 23 ? spec_rd_wdata : x23)); assert (nx24 == (spec_rd_addr == 24 ? spec_rd_wdata : x24)); assert (nx25 == (spec_rd_addr == 25 ? spec_rd_wdata : x25)); assert (nx26 == (spec_rd_addr == 26 ? spec_rd_wdata : x26)); assert (nx27 == (spec_rd_addr == 27 ? spec_rd_wdata : x27)); assert (nx28 == (spec_rd_addr == 28 ? spec_rd_wdata : x28)); assert (nx29 == (spec_rd_addr == 29 ? spec_rd_wdata : x29)); assert (nx30 == (spec_rd_addr == 30 ? spec_rd_wdata : x30)); assert (nx31 == (spec_rd_addr == 31 ? spec_rd_wdata : x31)); assert (npc == spec_pc_wdata); assert (ren == spec_mem_rmask); assert (wen == spec_mem_wmask); if (spec_mem_rmask) begin assert (raddr == spec_mem_addr); end if (spec_mem_wmask) begin assert (waddr == spec_mem_addr); if (spec_mem_wmask[0]) assert (wdata[ 7: 0] == spec_mem_wdata[ 7: 0]); if (spec_mem_wmask[1]) assert (wdata[15: 8] == spec_mem_wdata[15: 8]); if (spec_mem_wmask[2]) assert (wdata[23:16] == spec_mem_wdata[23:16]); if (spec_mem_wmask[3]) assert (wdata[31:24] == spec_mem_wdata[31:24]); end assert (!excep); end end end `RISCV_FORMAL_INSN_MODEL model ( .rvfi_valid (rvfi_valid ), .rvfi_insn (rvfi_insn ), .rvfi_pc_rdata (rvfi_pc_rdata ), .rvfi_rs1_rdata (rvfi_rs1_rdata), .rvfi_rs2_rdata (rvfi_rs2_rdata), .rvfi_mem_rdata (rvfi_mem_rdata), .spec_valid (spec_valid ), .spec_trap (spec_trap ), .spec_rs1_addr (spec_rs1_addr ), .spec_rs2_addr (spec_rs2_addr ), .spec_rd_addr (spec_rd_addr ), .spec_rd_wdata (spec_rd_wdata ), .spec_pc_wdata (spec_pc_wdata ), .spec_mem_addr (spec_mem_addr ), .spec_mem_rmask (spec_mem_rmask), .spec_mem_wmask (spec_mem_wmask), .spec_mem_wdata (spec_mem_wdata), ); rvspec rvspec_inst ( .in_instr ( insn), .in_pc ( pc), .out_nextPC ( npc), .out_exception (excep), .out_loadEnable ( ren), .out_loadAddress (raddr), .in_loadData (rdata), .out_storeEnable ( wen), .out_storeAddress (waddr), .out_storeData (wdata), .in_registers ({ x31, x30, x29, x28, x27, x26, x25, x24, x23, x22, x21, x20, x19, x18, x17, x16, x15, x14, x13, x12, x11, x10, x9, x8, x7, x6, x5, x4, x3, x2, x1 }), .out_registers ({ nx31, nx30, nx29, nx28, nx27, nx26, nx25, nx24, nx23, nx22, nx21, nx20, nx19, nx18, nx17, nx16, nx15, nx14, nx13, nx12, nx11, nx10, nx9, nx8, nx7, nx6, nx5, nx4, nx3, nx2, nx1 }) ); endmodule ================================================ FILE: tests/spike/.gitignore ================================================ test_*.cc test_*.h test_*.ok test_*.v test_*.yslog test_*.cbmc_out riscv-isa-sim makefile ================================================ FILE: tests/spike/common.h ================================================ #define require_extension(_ext) do { } while (0) #define require(_expression) do { if (!(_expression)) valid = false; } while (0) struct mmu_t { uint64_t rdata, wdata, addr; int8_t optype; // width in bytes, negative for write uint8_t load_uint8(uint64_t a) { assert(optype == 0); addr = a, optype = 1; return rdata; } uint16_t load_uint16(uint64_t a) { assert(optype == 0); addr = a, optype = 2; return rdata; } uint32_t load_uint32(uint64_t a) { assert(optype == 0); addr = a, optype = 4; return rdata; } uint64_t load_uint64(uint64_t a) { assert(optype == 0); addr = a, optype = 8; return rdata; } void store_uint8(uint64_t a, uint8_t d) { assert(optype == 0); addr = a, wdata = d, optype = -1; } void store_uint16(uint64_t a, uint16_t d) { assert(optype == 0); addr = a, wdata = d, optype = -2; } void store_uint32(uint64_t a, uint32_t d) { assert(optype == 0); addr = a, wdata = d, optype = -4; } void store_uint64(uint64_t a, uint64_t d) { assert(optype == 0); addr = a, wdata = d, optype = -8; } int8_t load_int8(uint64_t a) { return load_uint8(a); } int16_t load_int16(uint64_t a) { return load_uint16(a); } int32_t load_int32(uint64_t a) { return load_uint32(a); } int64_t load_int64(uint64_t a) { return load_uint64(a); } }; // ----- from riscv-isa-sim/riscv/decode.h with minor edits ----- typedef int64_t sreg_t; typedef uint64_t reg_t; typedef uint64_t freg_t; const int NXPR = 32; const int NFPR = 32; const int NCSR = 4096; #define X_RA 1 #define X_SP 2 #define FP_RD_NE 0 #define FP_RD_0 1 #define FP_RD_DN 2 #define FP_RD_UP 3 #define FP_RD_NMM 4 #define FSR_RD_SHIFT 5 #define FSR_RD (0x7 << FSR_RD_SHIFT) #define FPEXC_NX 0x01 #define FPEXC_UF 0x02 #define FPEXC_OF 0x04 #define FPEXC_DZ 0x08 #define FPEXC_NV 0x10 #define FSR_AEXC_SHIFT 0 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) #define insn_length(x) \ (((x) & 0x03) < 0x03 ? 2 : \ ((x) & 0x1f) < 0x1f ? 4 : \ ((x) & 0x3f) < 0x3f ? 6 : \ 8) #define MAX_INSN_LENGTH 8 #define PC_ALIGN 2 typedef uint64_t insn_bits_t; class insn_t { public: insn_t() { b = 0; } insn_t(insn_bits_t bits) : b(bits) {} insn_bits_t bits() { return b; } int length() { return insn_length(b); } int64_t i_imm() { return int64_t(b) >> 20; } int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); } int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); } int64_t u_imm() { return int64_t(b) >> 12 << 12; } int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); } uint64_t rd() { return x(7, 5); } uint64_t rs1() { return x(15, 5); } uint64_t rs2() { return x(20, 5); } uint64_t rs3() { return x(27, 5); } uint64_t rm() { return x(12, 3); } uint64_t csr() { return x(20, 12); } int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); } int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); } int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); } int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); } int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); } int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); } int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); } int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); } int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); } int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); } int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); } int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); } int64_t rvc_simm3() { return x(10, 3); } uint64_t rvc_rd() { return rd(); } uint64_t rvc_rs1() { return rd(); } uint64_t rvc_rs2() { return x(2, 5); } uint64_t rvc_rs1s() { return 8 + x(7, 3); } uint64_t rvc_rs2s() { return 8 + x(2, 3); } //private: insn_bits_t b; uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); } uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); } uint64_t imm_sign() { return xs(63, 1); } }; // helpful macros, etc #define MMU (mmu) #define STATE (post_state) #define READ_REG(reg) STATE.XPR[reg] #define READ_FREG(reg) STATE.FPR[reg] #define RS1 READ_REG(insn.rs1()) #define RS2 READ_REG(insn.rs2()) #define WRITE_RD(value) WRITE_REG(insn.rd(), value) #define WRITE_REG(reg, value) do { reg_t v = value; STATE.XPR[reg] = reg ? v : 0; } while (0) #define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, value) // RVC macros #define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value) #define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value) #define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value) #define RVC_RS1 READ_REG(insn.rvc_rs1()) #define RVC_RS2 READ_REG(insn.rvc_rs2()) #define RVC_RS1S READ_REG(insn.rvc_rs1s()) #define RVC_RS2S READ_REG(insn.rvc_rs2s()) #define RVC_FRS2 READ_FREG(insn.rvc_rs2()) #define RVC_FRS2S READ_FREG(insn.rvc_rs2s()) #define RVC_SP READ_REG(X_SP) // FPU macros #define FRS1 READ_FREG(insn.rs1()) #define FRS2 READ_FREG(insn.rs2()) #define FRS3 READ_FREG(insn.rs3()) #define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD)) #define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD)) #define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state) #define WRITE_FRD(value) WRITE_FREG(insn.rd(), value) #define SHAMT (insn.i_imm() & 0x3F) #define BRANCH_TARGET (pc + insn.sb_imm()) #define JUMP_TARGET (pc + insn.uj_imm()) #define RM ({ int rm = insn.rm(); \ if(rm == 7) rm = STATE.frm; \ if(rm > 4) throw trap_illegal_instruction(); \ rm; }) #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask))) #define sext32(x) ((sreg_t)(int32_t)(x)) #define zext32(x) ((reg_t)(uint32_t)(x)) #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen)) #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen)) #define set_pc(x) do { STATE.pc = x; } while (0) // ----- from riscv-isa-sim/riscv/processor.h with minor edits ----- typedef struct { uint8_t prv; bool step; bool ebreakm; bool ebreakh; bool ebreaks; bool ebreaku; bool halt; uint8_t cause; } dcsr_t; // typedef enum // { // ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION, // ACTION_DEBUG_MODE = MCONTROL_ACTION_DEBUG_MODE, // ACTION_TRACE_START = MCONTROL_ACTION_TRACE_START, // ACTION_TRACE_STOP = MCONTROL_ACTION_TRACE_STOP, // ACTION_TRACE_EMIT = MCONTROL_ACTION_TRACE_EMIT // } mcontrol_action_t; // // typedef enum // { // MATCH_EQUAL = MCONTROL_MATCH_EQUAL, // MATCH_NAPOT = MCONTROL_MATCH_NAPOT, // MATCH_GE = MCONTROL_MATCH_GE, // MATCH_LT = MCONTROL_MATCH_LT, // MATCH_MASK_LOW = MCONTROL_MATCH_MASK_LOW, // MATCH_MASK_HIGH = MCONTROL_MATCH_MASK_HIGH // } mcontrol_match_t; // // typedef struct // { // uint8_t type; // bool dmode; // uint8_t maskmax; // bool select; // bool timing; // mcontrol_action_t action; // bool chain; // mcontrol_match_t match; // bool m; // bool h; // bool s; // bool u; // bool execute; // bool store; // bool load; // } mcontrol_t; // architectural state of a RISC-V hart struct state_t { void reset(); static const int num_triggers = 4; reg_t pc; reg_t XPR[NXPR]; freg_t FPR[NFPR]; // control and status registers reg_t prv; // TODO: Can this be an enum instead? reg_t mstatus; reg_t mepc; reg_t mbadaddr; reg_t mscratch; reg_t mtvec; reg_t mcause; reg_t minstret; reg_t mie; reg_t mip; reg_t medeleg; reg_t mideleg; uint32_t mucounteren; uint32_t mscounteren; reg_t sepc; reg_t sbadaddr; reg_t sscratch; reg_t stvec; reg_t sptbr; reg_t scause; reg_t dpc; reg_t dscratch; dcsr_t dcsr; reg_t tselect; // mcontrol_t mcontrol[num_triggers]; // reg_t tdata2[num_triggers]; uint32_t fflags; uint32_t frm; bool serialized; // whether timer CSRs are in a well-defined state // When true, execute a single instruction and then enter debug mode. This // can only be set by executing dret. enum { STEP_NONE, STEP_STEPPING, STEP_STEPPED } single_step; reg_t load_reservation; }; ================================================ FILE: tests/spike/generate.py ================================================ #!/usr/bin/env python3 import os isa = "rv32ic" check_match = True check_pc = True check_rd = True check_regs = True check_mem = True compressed = "c" in isa xlen = 32 if "32" in isa else 64 with open("../../insns/isa_%s.txt" % isa, "r") as f: insns = f.read().split() with open("makefile", "w") as makefile: print("all::", file=makefile) print("makefile: generate.py", file=makefile) print("\tpython3 generate.py", file=makefile) print("riscv-isa-sim:", file=makefile) print("\trm -rf riscv-isa-sim.part", file=makefile) print("\tgit clone https://github.com/riscv/riscv-isa-sim.git riscv-isa-sim.part", file=makefile) print("\tmv riscv-isa-sim.part riscv-isa-sim", file=makefile) for insn in insns: with open("test_%s.v" % insn, "w") as f: print("// DO NOT EDIT -- auto-generated from riscv-formal/tests/spike/generate.py", file=f) print("`define RISCV_FORMAL_XLEN %d" % xlen, file=f) print("`define RISCV_FORMAL_ILEN 32", file=f) if compressed: print("`define RISCV_FORMAL_COMPRESSED", file=f) print("`include \"../../insns/insn_%s.v\"" % insn, file=f) with open("test_%s.cc" % insn, "w") as f: print("// DO NOT EDIT -- auto-generated from riscv-formal/tests/spike/generate.py", file=f) print("#define xlen %d" % xlen, file=f) print("#define value_xlen value_%d_0" % (xlen-1), file=f) print("#include ", file=f) print("#include ", file=f) print("#include \"test_%s.h\"" % insn, file=f) print("#include \"common.h\"", file=f) print("#include \"riscv-isa-sim/riscv/encoding.h\"", file=f) print("void test_%s(mmu_t mmu, state_t pre_state, insn_t insn)" % insn, file=f) print("{", file=f) print(" mmu.optype = 0;", file=f) print(" pre_state.pc = zext_xlen(pre_state.pc) & ~(reg_t)%d;" % (1 if compressed else 3), file=f) print(" pre_state.XPR[0] = 0;", file=f) for i in range(1, 32): print(" pre_state.XPR[%d] = sext_xlen(pre_state.XPR[%d]);" % (i, i), file=f) print(" insn.b = sext32(insn.b);", file=f) print(" const reg_t &pc = pre_state.pc;", file=f) print(" reg_t npc = pc + insn.length();", file=f) print(" state_t post_state = pre_state;", file=f) print(" post_state.pc = npc;", file=f) print(" rvfi_insn_%s_state_t model = { };" % insn, file=f) print(" bool valid = (insn.bits() & MASK_%s) == MATCH_%s;" % (insn.upper(), insn.upper()), file=f) print(" if (((insn.bits() & 3) != 3) && ((insn.bits() >> 16) != 0)) valid = false;", file=f) print(" model.rvfi_valid.value_0_0 = 1;", file=f) print(" model.rvfi_insn.value_31_0 = insn.bits();", file=f) print(" model.rvfi_pc_rdata.value_xlen = pre_state.pc;", file=f) print(" rvfi_insn_%s_init(&model);" % insn, file=f) print(" model.rvfi_rs1_rdata.value_xlen = pre_state.XPR[model.spec_rs1_addr.value_4_0];", file=f) print(" model.rvfi_rs2_rdata.value_xlen = pre_state.XPR[model.spec_rs2_addr.value_4_0];", file=f) print(" model.rvfi_mem_rdata.value_xlen = mmu.rdata;", file=f) print(" rvfi_insn_%s_eval(&model);" % insn, file=f) if insn == "c_lui": print("if (insn.rvc_rd() == 2) valid = false;", file=f) print("#include \"riscv-isa-sim/riscv/insns/c_lui.h\"", file=f) elif insn == "c_addi16sp": print("if (insn.rvc_rd() != 2) valid = false;", file=f) print("#include \"riscv-isa-sim/riscv/insns/c_lui.h\"", file=f) else: print("#include \"riscv-isa-sim/riscv/insns/%s.h\"" % insn, file=f) print(" if ((post_state.pc & %d) != 0) valid = false;" % (1 if compressed else 3), file=f) print(" printf(\"int main() {\\n\"", file=f) print(" \" insn_t insn(%u);\\n\"", file=f) print(" \" state_t state = { };\\n\"", file=f) print(" \" mmu_t mmu = { };\\n\"", file=f) print(" \" state.pc = %u;\\n\"", file=f) print(" \" state.XPR[%u] = %d;\\n\"", file=f) print(" \" state.XPR[%u] = %d;\\n\"", file=f) print(" \" mmu.rdata = %u;\\n\"", file=f) print(" \" test_%s(mmu, state, insn);\\n\"" % insn, file=f) print(" \" return 0;\\n\"", file=f) print(" \"}\\n\", int(insn.bits()), int(pre_state.pc),", file=f) print(" int(model.spec_rs1_addr.value_4_0), int(pre_state.XPR[model.spec_rs1_addr.value_4_0]),", file=f) print(" int(model.spec_rs2_addr.value_4_0), int(pre_state.XPR[model.spec_rs2_addr.value_4_0]),", file=f) print(" int(mmu.rdata));", file=f) print(" // printf(\"valid: spike=%d riscv-formal=%d\\n\", int(valid), int(model.spec_valid.value_0_0));", file=f) print(" // printf(\"rs1_addr: riscv-formal=%u\\n\", int(model.spec_rs1_addr.value_4_0));", file=f) print(" // printf(\"rs2_addr: riscv-formal=%u\\n\", int(model.spec_rs2_addr.value_4_0));", file=f) print(" // printf(\"rd_addr: riscv-formal=%u\\n\", int(model.spec_rd_addr.value_4_0));", file=f) print(" // printf(\"rs1_rdata: spike=0x%016llx\\n\", (long long)pre_state.XPR[model.spec_rs1_addr.value_4_0]);", file=f) print(" // printf(\"rs2_rdata: spike=0x%016llx\\n\", (long long)pre_state.XPR[model.spec_rs2_addr.value_4_0]);", file=f) print(" // printf(\"rd_wdata: spike=0x%016llx riscv-formal=0x%016llx\\n\", (long long)post_state.XPR[model.spec_rd_addr.value_4_0], (long long)model.spec_rd_wdata.value_xlen);", file=f) if check_match: print(" assert(valid == model.spec_valid.value_0_0);", file=f) print(" if (valid) {", file=f) if check_pc: print(" assert(zext_xlen(post_state.pc) == model.spec_pc_wdata.value_xlen);", file=f) if check_rd: print(" assert(post_state.XPR[model.spec_rd_addr.value_4_0] == (reg_t)sext_xlen(model.spec_rd_wdata.value_xlen));", file=f) if check_regs: for i in range(0, 32): print(" if (model.spec_rd_addr.value_4_0 != %d) assert(post_state.XPR[%d] == pre_state.XPR[%d]);" % (i, i, i), file=f) if check_mem: print(" int8_t model_mem_optype = 100;", file=f) print(" if (model.spec_mem_rmask.value_3_0 == 0 && model.spec_mem_wmask.value_3_0 == 0) model_mem_optype = 0;", file=f) print(" if (model.spec_mem_rmask.value_3_0 == 1 && model.spec_mem_wmask.value_3_0 == 0) model_mem_optype = 1;", file=f) print(" if (model.spec_mem_rmask.value_3_0 == 3 && model.spec_mem_wmask.value_3_0 == 0) model_mem_optype = 2;", file=f) print(" if (model.spec_mem_rmask.value_3_0 == 15 && model.spec_mem_wmask.value_3_0 == 0) model_mem_optype = 4;", file=f) print(" if (model.spec_mem_rmask.value_3_0 == 0 && model.spec_mem_wmask.value_3_0 == 1) model_mem_optype = -1;", file=f) print(" if (model.spec_mem_rmask.value_3_0 == 0 && model.spec_mem_wmask.value_3_0 == 3) model_mem_optype = -2;", file=f) print(" if (model.spec_mem_rmask.value_3_0 == 0 && model.spec_mem_wmask.value_3_0 == 15) model_mem_optype = -4;", file=f) print(" // printf(\"mem_rmask: riscv-formal=%x\\n\", (int)model.spec_mem_rmask.value_3_0);", file=f) print(" // printf(\"mem_wmask: riscv-formal=%x\\n\", (int)model.spec_mem_wmask.value_3_0);", file=f) print(" // printf(\"mem_optype: spike=%d riscv-formal=%d\\n\", (int)mmu.optype, (int)model_mem_optype);", file=f) print(" // printf(\"mem_addr: spike=0x%016llx riscv-formal=0x%016llx\\n\", (long long)mmu.addr, (long long)sext_xlen(model.spec_mem_addr.value_xlen));", file=f) print(" // printf(\"mem_rdata: spike=0x%016llx riscv-formal=0x%016llx\\n\", (long long)mmu.rdata, (long long)zext_xlen(model.rvfi_mem_rdata.value_xlen));", file=f) print(" // printf(\"mem_wdata: spike=0x%016llx riscv-formal=0x%016llx\\n\", (long long)mmu.wdata, (long long)zext_xlen(model.spec_mem_wdata.value_xlen));", file=f) print(" assert(mmu.optype == model_mem_optype);", file=f) print(" if (model_mem_optype)", file=f) print(" assert(zext_xlen(mmu.addr) == zext_xlen(model.spec_mem_addr.value_xlen));", file=f) print(" if (model_mem_optype == -1)", file=f) print(" assert((mmu.wdata & 0xff) == (model.spec_mem_wdata.value_xlen & 0xff));", file=f) print(" if (model_mem_optype == -2)", file=f) print(" assert((mmu.wdata & 0xffff) == (model.spec_mem_wdata.value_xlen & 0xffff));", file=f) print(" if (model_mem_optype == -4)", file=f) print(" assert((mmu.wdata & 0xffffffff) == (model.spec_mem_wdata.value_xlen & 0xffffffff));", file=f) print(" if (model_mem_optype == -8)", file=f) print(" assert(mmu.wdata == model.spec_mem_wdata.value_xlen);", file=f) print(" }", file=f) print("}", file=f) print("all:: test_%s.ok" % insn, file=makefile) print("test_%s.ok: test_%s.h common.h riscv-isa-sim" % (insn, insn), file=makefile) print("\ttime cbmc --trace --stop-on-fail --no-built-in-assertions --function test_%s test_%s.cc | ts -s '%%H:%%M:%%S [%s]' | tee test_%s.cbmc_out" % (insn, insn, insn, insn), file=makefile) print("\tgrep 'VERIFICATION SUCCESSFUL' test_%s.cbmc_out" % insn, file=makefile) print("\tmv test_%s.cbmc_out test_%s.ok" % (insn, insn), file=makefile) print("test_%s.h: test_%s.v ../../insns/insn_%s.v makefile" % (insn, insn, insn), file=makefile) print(("\tyosys -ql test_%s.yslog -p 'synth -top rvfi_insn_%s; opt_clean -purge; " + "write_simplec -i64 test_%s.h' test_%s.v") % (insn, insn, insn, insn), file=makefile) print("clean:", file=makefile) print("\trm -f test_*.ok test_*.h test_*.yslog test_*.cbmc_out", file=makefile) print("mrproper: clean", file=makefile) print("\trm -rf test_*.cc test_*.v riscv-isa-sim makefile", file=makefile)