[ { "path": ".clang-format", "content": "BasedOnStyle: Google\nUseTab: Never\nIndentWidth: 4\nColumnLimit: 140\nAccessModifierOffset: -4\n\n# Force pointers to the type for C++.\nDerivePointerAlignment: false\nPointerAlignment: Left\nReferenceAlignment: Left\nAllowShortFunctionsOnASingleLine: Inline\nAllowShortIfStatementsOnASingleLine: false\nAllowShortLoopsOnASingleLine: false\nAlignOperands: false\nBreakBeforeBinaryOperators: None\nCpp11BracedListStyle: true\nContinuationIndentWidth: 4\n\nBinPackArguments: false\nBinPackParameters: false\n\n" }, { "path": ".github/workflows/format.yml", "content": "name: Code Format Check\n\non:\n push:\n branches: [ main ]\n pull_request:\n branches: [ main ]\n\njobs:\n format-check:\n runs-on: ubuntu-latest\n\n steps:\n - name: Checkout source\n uses: actions/checkout@v6\n with:\n fetch-depth: 0 \n\n - name: Setup environment\n run: |\n sudo apt-get update\n sudo apt-get install -y bash\n\n - name: Run format.sh\n run: |\n bash ./format.sh\n\n # If format.sh return non-zero, GitHub Actions will mark it as failure." }, { "path": ".gitignore", "content": "compile_commands.json\n.idea\n.DS_Store\n*.pyc\nbuild/\n.cache/\n.vscode/\n*/cmake-build-*/\n" }, { "path": "LICENSE", "content": "MIT License\n\nCopyright (c) 2025 DeepSeek\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n" }, { "path": "README.md", "content": "# DeepEP\n\nDeepEP is a communication library tailored for Mixture-of-Experts (MoE) and expert parallelism (EP). It provides high-throughput and low-latency all-to-all GPU kernels, which are also known as MoE dispatch and combine. The library also supports low-precision operations, including FP8.\n\nTo align with the group-limited gating algorithm proposed in the [DeepSeek-V3](https://github.com/deepseek-ai/DeepSeek-V3) paper, DeepEP offers a set of kernels optimized for asymmetric-domain bandwidth forwarding, such as forwarding data from NVLink domain to RDMA domain. These kernels deliver high throughput, making them suitable for both training and inference prefilling tasks. Additionally, they support SM (Streaming Multiprocessors) number control.\n\nFor latency-sensitive inference decoding, DeepEP includes a set of low-latency kernels with pure RDMA to minimize delays. The library also introduces a hook-based communication-computation overlapping method that does not occupy any SM resource.\n\nNotice: the implementation in this library may have some slight differences from the [DeepSeek-V3](https://github.com/deepseek-ai/DeepSeek-V3) paper.\n\n## Performance\n\n### Normal kernels with NVLink and RDMA forwarding\n\nWe test normal kernels on H800 (~160 GB/s NVLink maximum bandwidth), with each connected to a CX7 InfiniBand 400 Gb/s RDMA network card (~50 GB/s maximum bandwidth). And we follow the DeepSeek-V3/R1 pretraining setting (4096 tokens per batch, 7168 hidden, top-4 groups, top-8 experts, FP8 dispatching and BF16 combining).\n\n| Type | Dispatch #EP | Bottleneck bandwidth | Combine #EP | Bottleneck bandwidth |\n|:---------:|:------------:|:--------------------:|:-----------:|:--------------------:|\n| Intranode | 8 | 153 GB/s (NVLink) | 8 | 158 GB/s (NVLink) |\n| Internode | 16 | 43 GB/s (RDMA) | 16 | 43 GB/s (RDMA) |\n| Internode | 32 | 58 GB/s (RDMA) | 32 | 57 GB/s (RDMA) |\n| Internode | 64 | 51 GB/s (RDMA) | 64 | 50 GB/s (RDMA) |\n\n**News (2025.04.22)**: with optimizations from Tencent Network Platform Department, performance was enhanced by up to 30%, see [#130](https://github.com/deepseek-ai/DeepEP/pull/130) for more details. Thanks for the contribution!\n\n### Low-latency kernels with pure RDMA\n\nWe test low-latency kernels on H800 with each connected to a CX7 InfiniBand 400 Gb/s RDMA network card (~50 GB/s maximum bandwidth). And we follow a typical DeepSeek-V3/R1 production setting (128 tokens per batch, 7168 hidden, top-8 experts, FP8 dispatching and BF16 combining).\n\n| Dispatch #EP | Latency | RDMA bandwidth | Combine #EP | Latency | RDMA bandwidth |\n|:------------:|:-------:|:--------------:|:-----------:|:-------:|:--------------:|\n| 8 | 77 us | 98 GB/s | 8 | 114 us | 127 GB/s |\n| 16 | 118 us | 63 GB/s | 16 | 195 us | 74 GB/s |\n| 32 | 155 us | 48 GB/s | 32 | 273 us | 53 GB/s |\n| 64 | 173 us | 43 GB/s | 64 | 314 us | 46 GB/s |\n| 128 | 192 us | 39 GB/s | 128 | 369 us | 39 GB/s |\n| 256 | 194 us | 39 GB/s | 256 | 360 us | 40 GB/s |\n\n**News (2025.06.05)**: low-latency kernels now leverage NVLink as much as possible, see [#173](https://github.com/deepseek-ai/DeepEP/pull/173) for more details. Thanks for the contribution!\n\n## Quick start\n\n### Requirements\n\n- Ampere (SM80), Hopper (SM90) GPUs, or other architectures with SM90 PTX ISA support\n- Python 3.8 and above\n- CUDA version\n - CUDA 11.0 and above for SM80 GPUs\n - CUDA 12.3 and above for SM90 GPUs\n- PyTorch 2.1 and above\n- NVLink for intranode communication\n- RDMA network for internode communication\n\n### Download and install NVSHMEM dependency\n\nDeepEP also depends on NVSHMEM. Please refer to our [NVSHMEM Installation Guide](third-party/README.md) for instructions.\n\n### Development\n\n```bash\n# Build and make symbolic links for SO files\nNVSHMEM_DIR=/path/to/installed/nvshmem python setup.py build\n# You may modify the specific SO names according to your own platform\nln -s build/lib.linux-x86_64-cpython-38/deep_ep_cpp.cpython-38-x86_64-linux-gnu.so\n\n# Run test cases\n# NOTES: you may modify the `init_dist` function in `tests/utils.py`\n# according to your own cluster settings, and launch into multiple nodes\npython tests/test_intranode.py\npython tests/test_internode.py\npython tests/test_low_latency.py\n```\n\n### Installation\n\n```bash\nNVSHMEM_DIR=/path/to/installed/nvshmem python setup.py install\n```\n\n#### Installation environment variables\n\n- `NVSHMEM_DIR`: the path to the NVSHMEM directory, disable all internode and low-latency features if not specified\n- `DISABLE_SM90_FEATURES`: 0 or 1, whether to disable SM90 features, it is required for SM90 devices or CUDA 11\n- `TORCH_CUDA_ARCH_LIST`: the list of target architectures, e.g. `TORCH_CUDA_ARCH_LIST=\"9.0\"`\n- `DISABLE_AGGRESSIVE_PTX_INSTRS`: 0 or 1, whether to disable aggressive load/store instructions, see [Undefined-behavior PTX usage](#undefined-behavior-ptx-usage) for more details\n\nThen, import `deep_ep` in your Python project, and enjoy!\n\n## Network configurations\n\nDeepEP is fully tested with InfiniBand networks. However, it is theoretically compatible with RDMA over Converged Ethernet (RoCE) as well.\n\n### Traffic isolation\n\nTraffic isolation is supported by InfiniBand through Virtual Lanes (VL).\n\nTo prevent interference between different types of traffic, we recommend segregating workloads across different virtual lanes as follows:\n\n- workloads using normal kernels\n- workloads using low-latency kernels\n- other workloads\n\nFor DeepEP, you can control the virtual lane assignment by setting the `NVSHMEM_IB_SL` environment variable.\n\n### Adaptive routing\n\nAdaptive routing is an advanced routing feature provided by InfiniBand switches that can evenly distribute traffic across multiple paths. Enabling adaptive routing can completely eliminate network congestion caused by routing conflicts, but it also introduces additional latency. We recommend the following configuration for optimal performance:\n\n- enable adaptive routing in environments with heavy network loads\n- use static routing in environments with light network loads\n\n### Congestion control\n\nCongestion control is disabled as we have not observed significant congestion in our production environment.\n\n## Interfaces and examples\n\n### Example use in model training or inference prefilling\n\nThe normal kernels can be used in model training or the inference prefilling phase (without the backward part) as the below example code shows.\n\n```python\nimport torch\nimport torch.distributed as dist\nfrom typing import List, Tuple, Optional, Union\n\nfrom deep_ep import Buffer, EventOverlap\n\n# Communication buffer (will allocate at runtime)\n_buffer: Optional[Buffer] = None\n\n# Set the number of SMs to use\n# NOTES: this is a static variable\nBuffer.set_num_sms(24)\n\n\n# You may call this function at the framework initialization\ndef get_buffer(group: dist.ProcessGroup, hidden_bytes: int) -> Buffer:\n global _buffer\n\n # NOTES: you may also replace `get_*_config` with your auto-tuned results via all the tests\n num_nvl_bytes, num_rdma_bytes = 0, 0\n for config in (Buffer.get_dispatch_config(group.size()), Buffer.get_combine_config(group.size())):\n num_nvl_bytes = max(config.get_nvl_buffer_size_hint(hidden_bytes, group.size()), num_nvl_bytes)\n num_rdma_bytes = max(config.get_rdma_buffer_size_hint(hidden_bytes, group.size()), num_rdma_bytes)\n\n # Allocate a buffer if not existed or not enough buffer size\n if _buffer is None or _buffer.group != group or _buffer.num_nvl_bytes < num_nvl_bytes or _buffer.num_rdma_bytes < num_rdma_bytes:\n _buffer = Buffer(group, num_nvl_bytes, num_rdma_bytes)\n return _buffer\n\n\ndef get_hidden_bytes(x: torch.Tensor) -> int:\n t = x[0] if isinstance(x, tuple) else x\n return t.size(1) * max(t.element_size(), 2)\n\n\ndef dispatch_forward(x: Union[torch.Tensor, Tuple[torch.Tensor, torch.Tensor]],\n topk_idx: torch.Tensor, topk_weights: torch.Tensor,\n num_experts: int, previous_event: Optional[EventOverlap] = None) -> \\\n Tuple[Union[torch.Tensor, Tuple[torch.Tensor, torch.Tensor]], torch.Tensor, torch.Tensor, List, Tuple, EventOverlap]:\n # NOTES: an optional `previous_event` means a CUDA event captured that you want to make it as a dependency\n # of the dispatch kernel, it may be useful with communication-computation overlap. For more information, please\n # refer to the docs of `Buffer.dispatch`\n global _buffer\n\n # Calculate layout before actual dispatch\n num_tokens_per_rank, num_tokens_per_rdma_rank, num_tokens_per_expert, is_token_in_rank, previous_event = \\\n _buffer.get_dispatch_layout(topk_idx, num_experts,\n previous_event=previous_event, async_finish=True,\n allocate_on_comm_stream=previous_event is not None)\n # Do MoE dispatch\n # NOTES: the CPU will wait for GPU's signal to arrive, so this is not compatible with CUDA graph\n # Unless you specify `num_worst_tokens`, but this flag is for intranode only\n # For more advanced usages, please refer to the docs of the `dispatch` function\n recv_x, recv_topk_idx, recv_topk_weights, num_recv_tokens_per_expert_list, handle, event = \\\n _buffer.dispatch(x, topk_idx=topk_idx, topk_weights=topk_weights,\n num_tokens_per_rank=num_tokens_per_rank, num_tokens_per_rdma_rank=num_tokens_per_rdma_rank,\n is_token_in_rank=is_token_in_rank, num_tokens_per_expert=num_tokens_per_expert,\n previous_event=previous_event, async_finish=True,\n allocate_on_comm_stream=True)\n # For event management, please refer to the docs of the `EventOverlap` class\n return recv_x, recv_topk_idx, recv_topk_weights, num_recv_tokens_per_expert_list, handle, event\n\n\ndef dispatch_backward(grad_recv_x: torch.Tensor, grad_recv_topk_weights: torch.Tensor, handle: Tuple) -> \\\n Tuple[torch.Tensor, torch.Tensor, EventOverlap]:\n global _buffer\n\n # The backward process of MoE dispatch is actually a combine\n # For more advanced usages, please refer to the docs of the `combine` function\n combined_grad_x, combined_grad_recv_topk_weights, event = \\\n _buffer.combine(grad_recv_x, handle, topk_weights=grad_recv_topk_weights, async_finish=True)\n\n # For event management, please refer to the docs of the `EventOverlap` class\n return combined_grad_x, combined_grad_recv_topk_weights, event\n\n\ndef combine_forward(x: torch.Tensor, handle: Tuple, previous_event: Optional[EventOverlap] = None) -> \\\n Tuple[torch.Tensor, EventOverlap]:\n global _buffer\n\n # Do MoE combine\n # For more advanced usages, please refer to the docs of the `combine` function\n combined_x, _, event = _buffer.combine(x, handle, async_finish=True, previous_event=previous_event,\n allocate_on_comm_stream=previous_event is not None)\n\n # For event management, please refer to the docs of the `EventOverlap` class\n return combined_x, event\n\n\ndef combine_backward(grad_combined_x: Union[torch.Tensor, Tuple[torch.Tensor, torch.Tensor]],\n handle: Tuple, previous_event: Optional[EventOverlap] = None) -> \\\n Tuple[Union[torch.Tensor, Tuple[torch.Tensor, torch.Tensor]], EventOverlap]:\n global _buffer\n\n # The backward process of MoE combine is actually a dispatch\n # For more advanced usages, please refer to the docs of the `dispatch` function\n grad_x, _, _, _, _, event = _buffer.dispatch(grad_combined_x, handle=handle, async_finish=True,\n previous_event=previous_event,\n allocate_on_comm_stream=previous_event is not None)\n\n # For event management, please refer to the docs of the `EventOverlap` class\n return grad_x, event\n```\n\nMoreover, inside the dispatch function, we may not know how many tokens to receive for the current rank. So an implicit CPU wait for GPU received count signal will be involved, as the following figure shows.\n\n![normal](figures/normal.png)\n\n### Example use in inference decoding\n\nThe low latency kernels can be used in the inference decoding phase as the below example code shows.\n\n```python\nimport torch\nimport torch.distributed as dist\nfrom typing import Tuple, Optional\n\nfrom deep_ep import Buffer\n\n# Communication buffer (will allocate at runtime)\n# NOTES: there is no SM control API for the low-latency kernels\n_buffer: Optional[Buffer] = None\n\n\n# You may call this function at the framework initialization\ndef get_buffer(group: dist.ProcessGroup, num_max_dispatch_tokens_per_rank: int, hidden: int, num_experts: int) -> Buffer:\n # NOTES: the low-latency mode will consume much more space than the normal mode\n # So we recommend that `num_max_dispatch_tokens_per_rank` (the actual batch size in the decoding engine) should be less than 256\n global _buffer\n num_rdma_bytes = Buffer.get_low_latency_rdma_size_hint(num_max_dispatch_tokens_per_rank, hidden, group.size(), num_experts)\n\n # Allocate a buffer if not existed or not enough buffer size\n if _buffer is None or _buffer.group != group or not _buffer.low_latency_mode or _buffer.num_rdma_bytes < num_rdma_bytes:\n # NOTES: for the best performance, the QP number **must** be equal to the number of the local experts\n assert num_experts % group.size() == 0\n _buffer = Buffer(group, 0, num_rdma_bytes, low_latency_mode=True, num_qps_per_rank=num_experts // group.size())\n return _buffer\n\n\ndef low_latency_dispatch(hidden_states: torch.Tensor, topk_idx: torch.Tensor, num_max_dispatch_tokens_per_rank: int, num_experts: int):\n global _buffer\n\n # Do MoE dispatch, compatible with CUDA graph (but you may restore some buffer status once you replay)\n recv_hidden_states, recv_expert_count, handle, event, hook = \\\n _buffer.low_latency_dispatch(hidden_states, topk_idx, num_max_dispatch_tokens_per_rank, num_experts,\n async_finish=False, return_recv_hook=True)\n\n # NOTES: the actual tensor will not be received only if you call `hook()`,\n # it is useful for double-batch overlapping, but **without any SM occupation**\n # If you don't want to overlap, please set `return_recv_hook=False`\n # Later, you can use our GEMM library to do the computation with this specific format\n return recv_hidden_states, recv_expert_count, handle, event, hook\n\n\ndef low_latency_combine(hidden_states: torch.Tensor,\n topk_idx: torch.Tensor, topk_weights: torch.Tensor, handle: Tuple):\n global _buffer\n\n # Do MoE combine, compatible with CUDA graph (but you may restore some buffer status once you replay)\n combined_hidden_states, event_overlap, hook = \\\n _buffer.low_latency_combine(hidden_states, topk_idx, topk_weights, handle,\n async_finish=False, return_recv_hook=True)\n\n # NOTES: the same behavior as described in the dispatch kernel\n return combined_hidden_states, event_overlap, hook\n```\n\nFor two-micro-batch overlapping, you can refer to the following figure. With our receiving hook interface, the RDMA network traffic is happening in the background, without costing any GPU SMs from the computation part. But notice, the overlapped parts can be adjusted, i.e., the 4 parts of attention/dispatch/MoE/combine may not have the exact same execution time. You may adjust the stage settings according to your workload.\n\n![low-latency](figures/low-latency.png)\n\n## Roadmap\n\n- [x] AR support\n- [x] Refactor low-latency mode AR code\n- [x] A100 support (intranode only)\n- [x] Support BF16 for the low-latency dispatch kernel\n- [x] Support NVLink protocol for intranode low-latency kernels\n- [ ] TMA copy instead of LD/ST\n - [x] Intranode kernels\n - [ ] Internode kernels\n - [ ] Low-latency kernels\n- [ ] SM-free kernels and refactors\n- [ ] Fully remove undefined-behavior PTX instructions\n\n## Notices\n\n#### Easier potential overall design\n\nThe current DeepEP implementation uses queues for communication buffers which save memory but introduce complexity and potential deadlocks. If you're implementing your own version based on DeepEP, consider using fixed-size buffers allocated to maximum capacity for simplicity and better performance. For a detailed discussion of this alternative approach, see https://github.com/deepseek-ai/DeepEP/issues/39.\n\n#### Undefined-behavior PTX usage\n\n- For extreme performance, we discover and use an undefined-behavior PTX usage: using read-only PTX `ld.global.nc.L1::no_allocate.L2::256B` to **read volatile data**. The PTX modifier `.nc` indicates that a non-coherent cache is used. But the correctness is tested to be guaranteed with `.L1::no_allocate` on Hopper architectures, and performance will be much better. The reason we guess may be: the non-coherent cache is unified with L1, and the L1 modifier is not just a hint but a strong option, so that the correctness can be guaranteed by no dirty data in L1.\n- Initially, because NVCC could not automatically unroll volatile read PTX, we tried using `__ldg` (i.e., `ld.nc`). Even compared to manually unrolled volatile reads, it was significantly faster (likely due to additional compiler optimizations). However, the results could be incorrect or dirty. After consulting the PTX documentation, we discovered that L1 and non-coherent cache are unified on Hopper architectures. We speculated that `.L1::no_allocate` might resolve the issue, leading to this discovery.\n- If you find kernels not working on some other platforms, you may add `DISABLE_AGGRESSIVE_PTX_INSTRS=1` to `setup.py` and disable this, or file an issue.\n\n#### Auto-tuning on your cluster\n\nFor better performance on your cluster, we recommend to run all the tests and use the best auto-tuned configuration. The default configurations are optimized on the DeepSeek's internal cluster.\n\n## License\n\nThis code repository is released under [the MIT License](LICENSE), except for codes that reference NVSHMEM (including `csrc/kernels/ibgda_device.cuh` and `third-party/nvshmem.patch`), which are subject to [NVSHMEM SLA](https://docs.nvidia.com/nvshmem/api/sla.html).\n\n## Experimental Branches\n\n- [Zero-copy](https://github.com/deepseek-ai/DeepEP/pull/453)\n - Removing the copy between PyTorch tensors and communication buffers, which reduces the SM usages significantly for normal kernels\n - This PR is authored by **Tencent Network Platform Department**\n- [Eager](https://github.com/deepseek-ai/DeepEP/pull/437)\n - Using a low-latency protocol removes the extra RTT latency introduced by RDMA atomic OPs\n- [Hybrid-EP](https://github.com/deepseek-ai/DeepEP/tree/hybrid-ep)\n - A new backend implementation using TMA instructions for minimal SM usage and larger NVLink domain support\n - Fine-grained communication-computation overlap for single-batch scenarios\n - PCIe kernel support for non-NVLink environments\n - NVFP4 data type support\n- [AntGroup-Opt](https://github.com/deepseek-ai/DeepEP/tree/antgroup-opt)\n - This optimization series is authored by **AntGroup Network Platform Department**\n - [Normal-SMFree](https://github.com/deepseek-ai/DeepEP/pull/347) Eliminating SM from RDMA path by decoupling comm-kernel execution from NIC token transfer, freeing SMs for compute\n - [LL-SBO](https://github.com/deepseek-ai/DeepEP/pull/483) Overlapping Down GEMM computation with Combine Send communication via signaling mechanism to reduce end-to-end latency\n - [LL-Layered](https://github.com/deepseek-ai/DeepEP/pull/500) Optimizing cross-node LL operator communication using rail-optimized forwarding and data merging to reduce latency\n- [Mori-EP](https://github.com/deepseek-ai/DeepEP/tree/mori-ep)\n - ROCm/AMD GPU support powered by [MORI](https://github.com/ROCm/mori) backend (low-latency mode)\n\n## Community Forks\n\n- [uccl/uccl-ep](https://github.com/uccl-project/uccl/tree/main/ep) - Enables running DeepEP on heterogeneous GPUs (e.g., Nvidia, AMD) and NICs (e.g., EFA, Broadcom, CX7)\n- [Infrawaves/DeepEP_ibrc_dual-ports_multiQP](https://github.com/Infrawaves/DeepEP_ibrc_dual-ports_multiQP) - Adds multi-QP solution and dual-port NIC support in IBRC transport\n- [antgroup/DeepXTrace](https://github.com/antgroup/DeepXTrace) - A diagnostic analyzer for efficient and precise localization of slow ranks\n- [ROCm/mori](https://github.com/ROCm/mori) - AMD's next-generation communication library for performance-critical AI workloads (e.g., Wide EP, KVCache transfer, Collectives)\n\n## Citation\n\nIf you use this codebase or otherwise find our work valuable, please cite:\n\n```bibtex\n@misc{deepep2025,\n title={DeepEP: an efficient expert-parallel communication library},\n author={Chenggang Zhao and Shangyan Zhou and Liyue Zhang and Chengqi Deng and Zhean Xu and Yuxuan Liu and Kuai Yu and Jiashi Li and Liang Zhao},\n year={2025},\n publisher = {GitHub},\n howpublished = {\\url{https://github.com/deepseek-ai/DeepEP}},\n}\n```\n" }, { "path": "csrc/CMakeLists.txt", "content": "# NOTES: this CMake is only for debugging; for setup, please use Torch extension\ncmake_minimum_required(VERSION 3.10)\nproject(deep_ep LANGUAGES CUDA CXX)\nset(CMAKE_VERBOSE_MAKEFILE ON)\n\nset(CMAKE_C_FLAGS \"${CMAKE_C_FLAGS} -O3 -fPIC\")\nset(CMAKE_CXX_FLAGS \"${CMAKE_CXX_FLAGS} -O3 -fPIC\")\nset(CUDA_SEPARABLE_COMPILATION ON)\nlist(APPEND CUDA_NVCC_FLAGS \"-DENABLE_FAST_DEBUG\")\nlist(APPEND CUDA_NVCC_FLAGS \"-O3\")\nlist(APPEND CUDA_NVCC_FLAGS \"--ptxas-options=--verbose,--register-usage-level=10,--warn-on-local-memory-usage\")\n\nset(USE_SYSTEM_NVTX on)\nset(CUDA_ARCH_LIST \"9.0\" CACHE STRING \"List of CUDA architectures to compile\")\nset(TORCH_CUDA_ARCH_LIST \"${CUDA_ARCH_LIST}\")\n\nfind_package(CUDAToolkit REQUIRED)\nfind_package(pybind11 REQUIRED)\nfind_package(Torch REQUIRED)\nfind_package(NVSHMEM REQUIRED HINTS ${NVSHMEM_ROOT_DIR}/lib/cmake/nvshmem)\n\nadd_library(nvshmem ALIAS nvshmem::nvshmem)\nadd_library(nvshmem_host ALIAS nvshmem::nvshmem_host)\nadd_library(nvshmem_device ALIAS nvshmem::nvshmem_device)\n\nset(CMAKE_CXX_STANDARD 17)\nset(CMAKE_CUDA_STANDARD 17)\n\ninclude_directories(${CUDA_TOOLKIT_ROOT_DIR}/include ${TORCH_INCLUDE_DIRS} ${PYTHON_INCLUDE_DIRS} ${NVSHMEM_INCLUDE_DIR})\nlink_directories(${TORCH_INSTALL_PREFIX}/lib ${CUDA_TOOLKIT_ROOT_DIR}/lib ${NVSHMEM_LIB_DIR})\n\nadd_subdirectory(kernels)\n\n# Link CPP and CUDA together\npybind11_add_module(deep_ep_cpp deep_ep.cpp)\ntarget_link_libraries(deep_ep_cpp PRIVATE ${EP_CUDA_LIBRARIES} ${TORCH_LIBRARIES} torch_python)\n" }, { "path": "csrc/config.hpp", "content": "#pragma once\n\n#include \"kernels/api.cuh\"\n#include \"kernels/exception.cuh\"\n\nnamespace deep_ep {\n\ntemplate \ndtype_t ceil_div(dtype_t a, dtype_t b) {\n return (a + b - 1) / b;\n}\n\ntemplate \ndtype_t align_up(dtype_t a, dtype_t b) {\n return ceil_div(a, b) * b;\n}\n\ntemplate \ndtype_t align_down(dtype_t a, dtype_t b) {\n return a / b * b;\n}\n\nstruct Config {\n int num_sms;\n int num_max_nvl_chunked_send_tokens;\n int num_max_nvl_chunked_recv_tokens;\n int num_max_rdma_chunked_send_tokens;\n int num_max_rdma_chunked_recv_tokens;\n\n Config(int num_sms,\n int num_max_nvl_chunked_send_tokens,\n int num_max_nvl_chunked_recv_tokens,\n int num_max_rdma_chunked_send_tokens,\n int num_max_rdma_chunked_recv_tokens)\n : num_sms(num_sms),\n num_max_nvl_chunked_send_tokens(num_max_nvl_chunked_send_tokens),\n num_max_nvl_chunked_recv_tokens(num_max_nvl_chunked_recv_tokens),\n num_max_rdma_chunked_send_tokens(num_max_rdma_chunked_send_tokens),\n num_max_rdma_chunked_recv_tokens(num_max_rdma_chunked_recv_tokens) {\n EP_HOST_ASSERT(num_sms >= 0);\n EP_HOST_ASSERT(num_max_nvl_chunked_send_tokens > 0 and num_max_nvl_chunked_recv_tokens > 0);\n EP_HOST_ASSERT(num_max_nvl_chunked_send_tokens < num_max_nvl_chunked_recv_tokens);\n EP_HOST_ASSERT(num_max_rdma_chunked_send_tokens > 0 and num_max_rdma_chunked_recv_tokens > 0);\n\n // Ceil up RDMA buffer size\n this->num_max_rdma_chunked_recv_tokens = align_up(num_max_rdma_chunked_recv_tokens, num_max_rdma_chunked_send_tokens);\n EP_HOST_ASSERT(num_max_rdma_chunked_send_tokens < num_max_rdma_chunked_recv_tokens);\n // NOTES: this assertion is related to RDMA lazy head update, we must ensure senders always have space to push\n EP_HOST_ASSERT(num_max_rdma_chunked_send_tokens <= num_max_rdma_chunked_recv_tokens / 2);\n }\n\n size_t get_nvl_buffer_size_hint(size_t hidden_bytes, int num_ranks) const {\n // Below are some assumptions\n // TODO: add assertions\n constexpr int kNumMaxTopK = 128;\n constexpr int kNumMaxScales = 128;\n EP_HOST_ASSERT(num_ranks < NUM_MAX_NVL_PEERS or num_ranks % NUM_MAX_NVL_PEERS == 0);\n EP_HOST_ASSERT(num_ranks <= NUM_MAX_NVL_PEERS or num_sms % 2 == 0);\n const auto num_rdma_ranks = std::max(num_ranks / NUM_MAX_NVL_PEERS, 1);\n const auto num_nvl_ranks = std::min(num_ranks, NUM_MAX_NVL_PEERS);\n const int num_channels = num_sms / 2;\n\n size_t num_bytes = 0;\n num_bytes += num_channels * num_nvl_ranks * (2 * num_rdma_ranks + 3) * sizeof(int);\n num_bytes += num_channels * num_nvl_ranks * num_max_nvl_chunked_recv_tokens * hidden_bytes;\n#ifndef DISABLE_NVSHMEM\n num_bytes += num_channels * num_nvl_ranks * num_max_nvl_chunked_recv_tokens * internode::get_source_meta_bytes();\n#endif\n num_bytes += num_channels * num_nvl_ranks * num_max_nvl_chunked_recv_tokens * kNumMaxTopK * sizeof(topk_idx_t);\n num_bytes += num_channels * num_nvl_ranks * num_max_nvl_chunked_recv_tokens * kNumMaxTopK * sizeof(float);\n num_bytes += num_channels * num_nvl_ranks * num_max_nvl_chunked_recv_tokens * kNumMaxScales * sizeof(float);\n num_bytes = ((num_bytes + 127) / 128) * 128;\n return num_bytes;\n }\n\n size_t get_rdma_buffer_size_hint(int64_t hidden_bytes, int num_ranks) const {\n#ifndef DISABLE_NVSHMEM\n // Legacy mode\n if (num_ranks <= NUM_MAX_NVL_PEERS)\n return 0;\n\n // Below are some assumptions\n // TODO: add assertions\n constexpr int kNumMaxTopK = 128;\n constexpr int kNumMaxScales = 128;\n EP_HOST_ASSERT(num_ranks % NUM_MAX_NVL_PEERS == 0);\n EP_HOST_ASSERT(num_sms % 2 == 0);\n const int num_rdma_ranks = num_ranks / NUM_MAX_NVL_PEERS;\n const int num_channels = num_sms / 2;\n\n size_t num_bytes = 0;\n num_bytes += num_channels * num_rdma_ranks * (NUM_MAX_NVL_PEERS * 2 + 2) * 2 * sizeof(int);\n num_bytes += num_channels * num_rdma_ranks * num_max_rdma_chunked_recv_tokens * hidden_bytes * 2;\n num_bytes += num_channels * num_rdma_ranks * num_max_rdma_chunked_recv_tokens * internode::get_source_meta_bytes() * 2;\n num_bytes += num_channels * num_rdma_ranks * num_max_rdma_chunked_recv_tokens * kNumMaxTopK * sizeof(topk_idx_t) * 2;\n num_bytes += num_channels * num_rdma_ranks * num_max_rdma_chunked_recv_tokens * kNumMaxTopK * sizeof(float) * 2;\n num_bytes += num_channels * num_rdma_ranks * num_max_rdma_chunked_recv_tokens * kNumMaxScales * sizeof(float) * 2;\n num_bytes += num_channels * num_rdma_ranks * num_max_rdma_chunked_recv_tokens * sizeof(int4) * 2;\n num_bytes = ((num_bytes + 127) / 128) * 128;\n return num_bytes;\n#else\n EP_HOST_ASSERT(false and \"NVSHMEM is disable during compilation\");\n#endif\n }\n};\n\nstruct LowLatencyBuffer {\n int num_clean_int = 0;\n\n void* dispatch_rdma_send_buffer = nullptr;\n void* dispatch_rdma_recv_data_buffer = nullptr;\n int* dispatch_rdma_recv_count_buffer = nullptr;\n\n void* combine_rdma_send_buffer = nullptr;\n void* combine_rdma_recv_data_buffer = nullptr;\n int* combine_rdma_recv_flag_buffer = nullptr;\n\n void* combine_rdma_send_buffer_data_start = nullptr;\n size_t num_bytes_per_combine_msg = 0;\n\n std::pair clean_meta() {\n EP_HOST_ASSERT(dispatch_rdma_recv_count_buffer == combine_rdma_recv_flag_buffer);\n return {dispatch_rdma_recv_count_buffer, num_clean_int};\n }\n};\n\nstruct LowLatencyLayout {\n size_t total_bytes = 0;\n LowLatencyBuffer buffers[2];\n\n template \n out_ptr_t advance(const in_ptr_t& ptr, size_t count) {\n return reinterpret_cast(reinterpret_cast(ptr) + count);\n }\n\n LowLatencyLayout(void* rdma_buffer, int num_max_dispatch_tokens_per_rank, int hidden, int num_ranks, int num_experts) {\n const int num_scales = hidden / 128;\n\n // Dispatch and combine layout:\n // - 2 symmetric odd/even send buffer\n // - 2 symmetric odd/even receive buffers\n // - 2 symmetric odd/even signaling buffers\n\n // Message sizes\n // NOTES: you should add a control `int4` for combine messages if you want to do data transformation\n // NOTES: `num_scales * sizeof(nv_bfloat162)` means the per-128-channel min/max\n EP_HOST_ASSERT(num_scales * sizeof(float) <= hidden);\n size_t num_bytes_per_dispatch_msg = sizeof(int4) + std::max(hidden * sizeof(nv_bfloat16), hidden + num_scales * sizeof(float));\n size_t num_bytes_per_combine_msg = num_scales * sizeof(nv_bfloat162) + hidden * sizeof(nv_bfloat16);\n\n // Send buffer\n size_t dispatch_send_buffer_bytes = num_max_dispatch_tokens_per_rank * num_bytes_per_dispatch_msg;\n size_t combine_send_buffer_bytes = num_experts * num_max_dispatch_tokens_per_rank * num_bytes_per_combine_msg;\n size_t send_buffer_bytes = std::max(dispatch_send_buffer_bytes, combine_send_buffer_bytes);\n EP_HOST_ASSERT(send_buffer_bytes % sizeof(int4) == 0);\n total_bytes += send_buffer_bytes * 2;\n\n // Symmetric receive buffers\n // TODO: optimize memory usages\n size_t dispatch_recv_data_buffer_bytes = num_experts * num_max_dispatch_tokens_per_rank * num_bytes_per_dispatch_msg;\n size_t combine_recv_buffer_bytes = num_experts * num_max_dispatch_tokens_per_rank * num_bytes_per_combine_msg;\n size_t recv_buffer_bytes = std::max(dispatch_recv_data_buffer_bytes, combine_recv_buffer_bytes);\n EP_HOST_ASSERT(recv_buffer_bytes % sizeof(int4) == 0);\n total_bytes += recv_buffer_bytes * 2;\n\n // Symmetric signaling buffers\n size_t dispatch_recv_count_buffer_bytes = num_experts * sizeof(int);\n size_t combine_recv_flag_buffer_bytes = dispatch_recv_count_buffer_bytes;\n size_t signaling_buffer_bytes = std::max(dispatch_recv_count_buffer_bytes, combine_recv_flag_buffer_bytes);\n size_t signaling_buffer_bytes_aligned = align_up(signaling_buffer_bytes, 128);\n total_bytes += signaling_buffer_bytes_aligned * 2;\n\n // Assign pointers\n // NOTES: we still leave some space for distinguishing dispatch/combine buffer,\n // so you may see some parameters are duplicated\n for (int i = 0; i < 2; ++i) {\n buffers[i] = {static_cast(signaling_buffer_bytes / sizeof(int)),\n advance(rdma_buffer, signaling_buffer_bytes_aligned * 2 + send_buffer_bytes * i),\n advance(rdma_buffer, signaling_buffer_bytes_aligned * 2 + send_buffer_bytes * 2 + recv_buffer_bytes * i),\n advance(rdma_buffer, signaling_buffer_bytes_aligned * i),\n advance(rdma_buffer, signaling_buffer_bytes_aligned * 2 + send_buffer_bytes * i),\n advance(rdma_buffer, signaling_buffer_bytes_aligned * 2 + send_buffer_bytes * 2 + recv_buffer_bytes * i),\n advance(rdma_buffer, signaling_buffer_bytes_aligned * i),\n advance(rdma_buffer, signaling_buffer_bytes_aligned * 2 + send_buffer_bytes * i),\n num_bytes_per_combine_msg};\n }\n }\n};\n\nsize_t get_low_latency_rdma_size_hint(int num_max_dispatch_tokens_per_rank, int hidden, int num_ranks, int num_experts) {\n auto num_bytes = LowLatencyLayout(nullptr, num_max_dispatch_tokens_per_rank, hidden, num_ranks, num_experts).total_bytes;\n return ((num_bytes + NUM_BUFFER_ALIGNMENT_BYTES) / NUM_BUFFER_ALIGNMENT_BYTES) * NUM_BUFFER_ALIGNMENT_BYTES;\n}\n\n} // namespace deep_ep\n" }, { "path": "csrc/deep_ep.cpp", "content": "#include \"deep_ep.hpp\"\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \"kernels/api.cuh\"\n#include \"kernels/configs.cuh\"\n\nnamespace shared_memory {\nvoid cu_mem_set_access_all(void* ptr, size_t size) {\n int device_count;\n CUDA_CHECK(cudaGetDeviceCount(&device_count));\n\n CUmemAccessDesc access_desc[device_count];\n for (int idx = 0; idx < device_count; ++idx) {\n access_desc[idx].location.type = CU_MEM_LOCATION_TYPE_DEVICE;\n access_desc[idx].location.id = idx;\n access_desc[idx].flags = CU_MEM_ACCESS_FLAGS_PROT_READWRITE;\n }\n\n CU_CHECK(cuMemSetAccess((CUdeviceptr)ptr, size, access_desc, device_count));\n}\n\nvoid cu_mem_free(void* ptr) {\n CUmemGenericAllocationHandle handle;\n CU_CHECK(cuMemRetainAllocationHandle(&handle, ptr));\n\n size_t size = 0;\n CU_CHECK(cuMemGetAddressRange(NULL, &size, (CUdeviceptr)ptr));\n\n CU_CHECK(cuMemUnmap((CUdeviceptr)ptr, size));\n CU_CHECK(cuMemAddressFree((CUdeviceptr)ptr, size));\n CU_CHECK(cuMemRelease(handle));\n}\n\nsize_t get_size_align_to_granularity(size_t size_raw, size_t granularity) {\n size_t size = (size_raw + granularity - 1) & ~(granularity - 1);\n if (size == 0)\n size = granularity;\n return size;\n}\n\nSharedMemoryAllocator::SharedMemoryAllocator(bool use_fabric) : use_fabric(use_fabric) {}\n\nvoid SharedMemoryAllocator::malloc(void** ptr, size_t size_raw) {\n if (use_fabric) {\n CUdevice device;\n CU_CHECK(cuCtxGetDevice(&device));\n\n CUmemAllocationProp prop = {};\n prop.type = CU_MEM_ALLOCATION_TYPE_PINNED;\n prop.location.type = CU_MEM_LOCATION_TYPE_DEVICE;\n prop.requestedHandleTypes = CU_MEM_HANDLE_TYPE_FABRIC;\n prop.location.id = device;\n\n size_t granularity = 0;\n CU_CHECK(cuMemGetAllocationGranularity(&granularity, &prop, CU_MEM_ALLOC_GRANULARITY_MINIMUM));\n\n size_t size = get_size_align_to_granularity(size_raw, granularity);\n\n CUmemGenericAllocationHandle handle;\n CU_CHECK(cuMemCreate(&handle, size, &prop, 0));\n\n CU_CHECK(cuMemAddressReserve((CUdeviceptr*)ptr, size, granularity, 0, 0));\n CU_CHECK(cuMemMap((CUdeviceptr)*ptr, size, 0, handle, 0));\n cu_mem_set_access_all(*ptr, size);\n } else {\n CUDA_CHECK(cudaMalloc(ptr, size_raw));\n }\n}\n\nvoid SharedMemoryAllocator::free(void* ptr) {\n if (use_fabric) {\n cu_mem_free(ptr);\n } else {\n CUDA_CHECK(cudaFree(ptr));\n }\n}\n\nvoid SharedMemoryAllocator::get_mem_handle(MemHandle* mem_handle, void* ptr) {\n size_t size = 0;\n CU_CHECK(cuMemGetAddressRange(NULL, &size, (CUdeviceptr)ptr));\n\n mem_handle->size = size;\n\n if (use_fabric) {\n CUmemGenericAllocationHandle handle;\n CU_CHECK(cuMemRetainAllocationHandle(&handle, ptr));\n\n CU_CHECK(cuMemExportToShareableHandle(&mem_handle->inner.cu_mem_fabric_handle, handle, CU_MEM_HANDLE_TYPE_FABRIC, 0));\n } else {\n CUDA_CHECK(cudaIpcGetMemHandle(&mem_handle->inner.cuda_ipc_mem_handle, ptr));\n }\n}\n\nvoid SharedMemoryAllocator::open_mem_handle(void** ptr, MemHandle* mem_handle) {\n if (use_fabric) {\n size_t size = mem_handle->size;\n\n CUmemGenericAllocationHandle handle;\n CU_CHECK(cuMemImportFromShareableHandle(&handle, &mem_handle->inner.cu_mem_fabric_handle, CU_MEM_HANDLE_TYPE_FABRIC));\n\n CU_CHECK(cuMemAddressReserve((CUdeviceptr*)ptr, size, 0, 0, 0));\n CU_CHECK(cuMemMap((CUdeviceptr)*ptr, size, 0, handle, 0));\n cu_mem_set_access_all(*ptr, size);\n } else {\n CUDA_CHECK(cudaIpcOpenMemHandle(ptr, mem_handle->inner.cuda_ipc_mem_handle, cudaIpcMemLazyEnablePeerAccess));\n }\n}\n\nvoid SharedMemoryAllocator::close_mem_handle(void* ptr) {\n if (use_fabric) {\n cu_mem_free(ptr);\n } else {\n CUDA_CHECK(cudaIpcCloseMemHandle(ptr));\n }\n}\n} // namespace shared_memory\n\nnamespace deep_ep {\n\nBuffer::Buffer(int rank,\n int num_ranks,\n int64_t num_nvl_bytes,\n int64_t num_rdma_bytes,\n bool low_latency_mode,\n bool explicitly_destroy,\n bool enable_shrink,\n bool use_fabric)\n : rank(rank),\n num_ranks(num_ranks),\n num_nvl_bytes(num_nvl_bytes),\n num_rdma_bytes(num_rdma_bytes),\n enable_shrink(enable_shrink),\n low_latency_mode(low_latency_mode),\n explicitly_destroy(explicitly_destroy),\n comm_stream(at::cuda::getStreamFromPool(true)),\n shared_memory_allocator(use_fabric) {\n // Metadata memory\n int64_t barrier_signal_bytes = NUM_MAX_NVL_PEERS * sizeof(int);\n int64_t buffer_ptr_bytes = NUM_MAX_NVL_PEERS * sizeof(void*);\n int64_t barrier_signal_ptr_bytes = NUM_MAX_NVL_PEERS * sizeof(int*);\n\n // Common checks\n EP_STATIC_ASSERT(NUM_BUFFER_ALIGNMENT_BYTES % sizeof(int4) == 0, \"Invalid alignment\");\n EP_HOST_ASSERT(num_nvl_bytes % NUM_BUFFER_ALIGNMENT_BYTES == 0 and\n (num_nvl_bytes <= std::numeric_limits::max() or num_rdma_bytes == 0));\n EP_HOST_ASSERT(num_rdma_bytes % NUM_BUFFER_ALIGNMENT_BYTES == 0 and\n (low_latency_mode or num_rdma_bytes <= std::numeric_limits::max()));\n EP_HOST_ASSERT(num_nvl_bytes / sizeof(int4) < std::numeric_limits::max());\n EP_HOST_ASSERT(num_rdma_bytes / sizeof(int4) < std::numeric_limits::max());\n EP_HOST_ASSERT(0 <= rank and rank < num_ranks and (num_ranks <= NUM_MAX_NVL_PEERS * NUM_MAX_RDMA_PEERS or low_latency_mode));\n EP_HOST_ASSERT(num_ranks < NUM_MAX_NVL_PEERS or num_ranks % NUM_MAX_NVL_PEERS == 0);\n if (num_rdma_bytes > 0)\n EP_HOST_ASSERT(num_ranks > NUM_MAX_NVL_PEERS or low_latency_mode);\n\n // Get ranks\n CUDA_CHECK(cudaGetDevice(&device_id));\n rdma_rank = rank / NUM_MAX_NVL_PEERS, nvl_rank = rank % NUM_MAX_NVL_PEERS;\n num_rdma_ranks = std::max(1, num_ranks / NUM_MAX_NVL_PEERS), num_nvl_ranks = std::min(num_ranks, NUM_MAX_NVL_PEERS);\n#ifdef DISABLE_NVSHMEM\n EP_HOST_ASSERT(num_rdma_ranks == 1 and not low_latency_mode and \"NVSHMEM is disabled during compilation\");\n#endif\n\n // Get device info\n cudaDeviceProp device_prop = {};\n CUDA_CHECK(cudaGetDeviceProperties(&device_prop, device_id));\n num_device_sms = device_prop.multiProcessorCount;\n\n // Number of per-channel bytes cannot be large\n EP_HOST_ASSERT(ceil_div(num_nvl_bytes, num_device_sms / 2) < std::numeric_limits::max());\n EP_HOST_ASSERT(ceil_div(num_rdma_bytes, num_device_sms / 2) < std::numeric_limits::max());\n\n if (num_nvl_bytes > 0) {\n // Local IPC: alloc local memory and set local IPC handles\n shared_memory_allocator.malloc(&buffer_ptrs[nvl_rank],\n num_nvl_bytes + barrier_signal_bytes + buffer_ptr_bytes + barrier_signal_ptr_bytes);\n shared_memory_allocator.get_mem_handle(&ipc_handles[nvl_rank], buffer_ptrs[nvl_rank]);\n buffer_ptrs_gpu = reinterpret_cast(static_cast(buffer_ptrs[nvl_rank]) + num_nvl_bytes + barrier_signal_bytes);\n\n // Set barrier signals\n barrier_signal_ptrs[nvl_rank] = reinterpret_cast(static_cast(buffer_ptrs[nvl_rank]) + num_nvl_bytes);\n barrier_signal_ptrs_gpu =\n reinterpret_cast(static_cast(buffer_ptrs[nvl_rank]) + num_nvl_bytes + barrier_signal_bytes + buffer_ptr_bytes);\n\n // No need to synchronize, will do a full device sync during `sync`\n CUDA_CHECK(cudaMemsetAsync(barrier_signal_ptrs[nvl_rank], 0, barrier_signal_bytes, comm_stream));\n }\n\n // Create 32 MiB workspace\n CUDA_CHECK(cudaMalloc(&workspace, NUM_WORKSPACE_BYTES));\n CUDA_CHECK(cudaMemsetAsync(workspace, 0, NUM_WORKSPACE_BYTES, comm_stream));\n\n // MoE counter\n CUDA_CHECK(cudaMallocHost(&moe_recv_counter, sizeof(int64_t), cudaHostAllocMapped));\n CUDA_CHECK(cudaHostGetDevicePointer(&moe_recv_counter_mapped, const_cast(moe_recv_counter), 0));\n *moe_recv_counter = -1;\n\n // MoE expert-level counter\n CUDA_CHECK(cudaMallocHost(&moe_recv_expert_counter, sizeof(int) * NUM_MAX_LOCAL_EXPERTS, cudaHostAllocMapped));\n CUDA_CHECK(cudaHostGetDevicePointer(&moe_recv_expert_counter_mapped, const_cast(moe_recv_expert_counter), 0));\n for (int i = 0; i < NUM_MAX_LOCAL_EXPERTS; ++i)\n moe_recv_expert_counter[i] = -1;\n\n // MoE RDMA-level counter\n if (num_rdma_ranks > 0) {\n CUDA_CHECK(cudaMallocHost(&moe_recv_rdma_counter, sizeof(int), cudaHostAllocMapped));\n CUDA_CHECK(cudaHostGetDevicePointer(&moe_recv_rdma_counter_mapped, const_cast(moe_recv_rdma_counter), 0));\n *moe_recv_rdma_counter = -1;\n }\n}\n\nBuffer::~Buffer() noexcept(false) {\n if (not explicitly_destroy) {\n destroy();\n } else if (not destroyed) {\n printf(\"WARNING: destroy() was not called before DeepEP buffer destruction, which can leak resources.\\n\");\n fflush(stdout);\n }\n}\n\nbool Buffer::is_available() const {\n return available;\n}\n\nbool Buffer::is_internode_available() const {\n return is_available() and num_ranks > NUM_MAX_NVL_PEERS;\n}\n\nint Buffer::get_num_rdma_ranks() const {\n return num_rdma_ranks;\n}\n\nint Buffer::get_rdma_rank() const {\n return rdma_rank;\n}\n\nint Buffer::get_root_rdma_rank(bool global) const {\n return global ? nvl_rank : 0;\n}\n\nint Buffer::get_local_device_id() const {\n return device_id;\n}\n\npybind11::bytearray Buffer::get_local_ipc_handle() const {\n const shared_memory::MemHandle& handle = ipc_handles[nvl_rank];\n return {reinterpret_cast(&handle), sizeof(handle)};\n}\n\npybind11::bytearray Buffer::get_local_nvshmem_unique_id() const {\n#ifndef DISABLE_NVSHMEM\n EP_HOST_ASSERT(rdma_rank == 0 and \"Only RDMA rank 0 can get NVSHMEM unique ID\");\n auto unique_id = internode::get_unique_id();\n return {reinterpret_cast(unique_id.data()), unique_id.size()};\n#else\n EP_HOST_ASSERT(false and \"NVSHMEM is disabled during compilation\");\n#endif\n}\n\ntorch::Tensor Buffer::get_local_buffer_tensor(const pybind11::object& dtype, int64_t offset, bool use_rdma_buffer) const {\n torch::ScalarType casted_dtype = torch::python::detail::py_object_to_dtype(dtype);\n auto element_bytes = static_cast(elementSize(casted_dtype));\n auto base_ptr = static_cast(use_rdma_buffer ? rdma_buffer_ptr : buffer_ptrs[nvl_rank]) + offset;\n auto num_bytes = use_rdma_buffer ? num_rdma_bytes : num_nvl_bytes;\n return torch::from_blob(base_ptr, num_bytes / element_bytes, torch::TensorOptions().dtype(casted_dtype).device(at::kCUDA));\n}\n\ntorch::Stream Buffer::get_comm_stream() const {\n return comm_stream;\n}\n\nvoid Buffer::destroy() {\n EP_HOST_ASSERT(not destroyed);\n\n // Synchronize\n CUDA_CHECK(cudaDeviceSynchronize());\n\n if (num_nvl_bytes > 0) {\n // Barrier\n intranode::barrier(barrier_signal_ptrs_gpu, nvl_rank, num_nvl_ranks, comm_stream);\n CUDA_CHECK(cudaDeviceSynchronize());\n\n // Close remote IPC\n if (is_available()) {\n for (int i = 0; i < num_nvl_ranks; ++i)\n if (i != nvl_rank)\n shared_memory_allocator.close_mem_handle(buffer_ptrs[i]);\n }\n\n // Free local buffer and error flag\n shared_memory_allocator.free(buffer_ptrs[nvl_rank]);\n }\n\n // Free NVSHMEM\n#ifndef DISABLE_NVSHMEM\n if (is_available() and num_rdma_bytes > 0) {\n CUDA_CHECK(cudaDeviceSynchronize());\n internode::barrier();\n internode::free(rdma_buffer_ptr);\n if (enable_shrink) {\n internode::free(mask_buffer_ptr);\n internode::free(sync_buffer_ptr);\n }\n internode::finalize();\n }\n#endif\n\n // Free workspace and MoE counter\n CUDA_CHECK(cudaFree(workspace));\n CUDA_CHECK(cudaFreeHost(const_cast(moe_recv_counter)));\n\n // Free chunked mode staffs\n CUDA_CHECK(cudaFreeHost(const_cast(moe_recv_expert_counter)));\n\n destroyed = true;\n available = false;\n}\n\nvoid Buffer::sync(const std::vector& device_ids,\n const std::vector>& all_gathered_handles,\n const std::optional& root_unique_id_opt) {\n EP_HOST_ASSERT(not is_available());\n\n // Sync IPC handles\n if (num_nvl_bytes > 0) {\n EP_HOST_ASSERT(num_ranks == device_ids.size());\n EP_HOST_ASSERT(device_ids.size() == all_gathered_handles.size());\n for (int i = 0, offset = rdma_rank * num_nvl_ranks; i < num_nvl_ranks; ++i) {\n EP_HOST_ASSERT(all_gathered_handles[offset + i].has_value());\n auto handle_str = std::string(all_gathered_handles[offset + i].value());\n EP_HOST_ASSERT(handle_str.size() == shared_memory::HANDLE_SIZE);\n if (offset + i != rank) {\n std::memcpy(&ipc_handles[i], handle_str.c_str(), shared_memory::HANDLE_SIZE);\n shared_memory_allocator.open_mem_handle(&buffer_ptrs[i], &ipc_handles[i]);\n barrier_signal_ptrs[i] = reinterpret_cast(static_cast(buffer_ptrs[i]) + num_nvl_bytes);\n } else {\n EP_HOST_ASSERT(std::memcmp(&ipc_handles[i], handle_str.c_str(), shared_memory::HANDLE_SIZE) == 0);\n }\n }\n\n // Copy all buffer and barrier signal pointers to GPU\n CUDA_CHECK(cudaMemcpy(buffer_ptrs_gpu, buffer_ptrs, sizeof(void*) * NUM_MAX_NVL_PEERS, cudaMemcpyHostToDevice));\n CUDA_CHECK(cudaMemcpy(barrier_signal_ptrs_gpu, barrier_signal_ptrs, sizeof(int*) * NUM_MAX_NVL_PEERS, cudaMemcpyHostToDevice));\n CUDA_CHECK(cudaDeviceSynchronize());\n }\n\n // Sync NVSHMEM handles and allocate memory\n#ifndef DISABLE_NVSHMEM\n if (num_rdma_bytes > 0) {\n // Initialize NVSHMEM\n EP_HOST_ASSERT(root_unique_id_opt.has_value());\n std::vector root_unique_id(root_unique_id_opt->size());\n auto root_unique_id_str = root_unique_id_opt->cast();\n std::memcpy(root_unique_id.data(), root_unique_id_str.c_str(), root_unique_id_opt->size());\n auto nvshmem_rank = low_latency_mode ? rank : rdma_rank;\n auto num_nvshmem_ranks = low_latency_mode ? num_ranks : num_rdma_ranks;\n EP_HOST_ASSERT(nvshmem_rank == internode::init(root_unique_id, nvshmem_rank, num_nvshmem_ranks, low_latency_mode));\n internode::barrier();\n\n // Allocate\n rdma_buffer_ptr = internode::alloc(num_rdma_bytes, NUM_BUFFER_ALIGNMENT_BYTES);\n\n // Clean buffer (mainly for low-latency mode)\n CUDA_CHECK(cudaMemset(rdma_buffer_ptr, 0, num_rdma_bytes));\n\n // Allocate and clean shrink buffer\n if (enable_shrink) {\n int num_mask_buffer_bytes = num_ranks * sizeof(int);\n int num_sync_buffer_bytes = num_ranks * sizeof(int);\n mask_buffer_ptr = reinterpret_cast(internode::alloc(num_mask_buffer_bytes, NUM_BUFFER_ALIGNMENT_BYTES));\n sync_buffer_ptr = reinterpret_cast(internode::alloc(num_sync_buffer_bytes, NUM_BUFFER_ALIGNMENT_BYTES));\n CUDA_CHECK(cudaMemset(mask_buffer_ptr, 0, num_mask_buffer_bytes));\n CUDA_CHECK(cudaMemset(sync_buffer_ptr, 0, num_sync_buffer_bytes));\n }\n\n // Barrier\n internode::barrier();\n CUDA_CHECK(cudaDeviceSynchronize());\n }\n#endif\n\n // Ready to use\n available = true;\n}\n\nstd::tuple, torch::Tensor, torch::Tensor, std::optional>\nBuffer::get_dispatch_layout(\n const torch::Tensor& topk_idx, int num_experts, std::optional& previous_event, bool async, bool allocate_on_comm_stream) {\n EP_HOST_ASSERT(topk_idx.dim() == 2);\n EP_HOST_ASSERT(topk_idx.is_contiguous());\n EP_HOST_ASSERT(num_experts > 0);\n\n // Allocate all tensors on comm stream if set\n // NOTES: do not allocate tensors upfront!\n auto compute_stream = at::cuda::getCurrentCUDAStream();\n if (allocate_on_comm_stream) {\n EP_HOST_ASSERT(previous_event.has_value() and async);\n at::cuda::setCurrentCUDAStream(comm_stream);\n }\n\n // Wait previous tasks to be finished\n if (previous_event.has_value()) {\n stream_wait(comm_stream, previous_event.value());\n } else {\n stream_wait(comm_stream, compute_stream);\n }\n\n auto num_tokens = static_cast(topk_idx.size(0)), num_topk = static_cast(topk_idx.size(1));\n auto num_tokens_per_rank = torch::empty({num_ranks}, dtype(torch::kInt32).device(torch::kCUDA));\n auto num_tokens_per_rdma_rank = std::optional();\n auto num_tokens_per_expert = torch::empty({num_experts}, dtype(torch::kInt32).device(torch::kCUDA));\n auto is_token_in_rank = torch::empty({num_tokens, num_ranks}, dtype(torch::kBool).device(torch::kCUDA));\n if (is_internode_available())\n num_tokens_per_rdma_rank = torch::empty({num_rdma_ranks}, dtype(torch::kInt32).device(torch::kCUDA));\n\n layout::get_dispatch_layout(topk_idx.data_ptr(),\n num_tokens_per_rank.data_ptr(),\n num_tokens_per_rdma_rank.has_value() ? num_tokens_per_rdma_rank.value().data_ptr() : nullptr,\n num_tokens_per_expert.data_ptr(),\n is_token_in_rank.data_ptr(),\n num_tokens,\n num_topk,\n num_ranks,\n num_experts,\n comm_stream);\n\n // Wait streams\n std::optional event;\n if (async) {\n event = EventHandle(comm_stream);\n for (auto& t : {topk_idx, num_tokens_per_rank, num_tokens_per_expert, is_token_in_rank}) {\n t.record_stream(comm_stream);\n if (allocate_on_comm_stream)\n t.record_stream(compute_stream);\n }\n for (auto& to : {num_tokens_per_rdma_rank}) {\n to.has_value() ? to->record_stream(comm_stream) : void();\n if (allocate_on_comm_stream)\n to.has_value() ? to->record_stream(compute_stream) : void();\n }\n } else {\n stream_wait(compute_stream, comm_stream);\n }\n\n // Switch back compute stream\n if (allocate_on_comm_stream)\n at::cuda::setCurrentCUDAStream(compute_stream);\n\n return {num_tokens_per_rank, num_tokens_per_rdma_rank, num_tokens_per_expert, is_token_in_rank, event};\n}\n\nstd::tuple,\n std::optional,\n std::optional,\n std::vector,\n torch::Tensor,\n torch::Tensor,\n torch::Tensor,\n torch::Tensor,\n torch::Tensor,\n std::optional>\nBuffer::intranode_dispatch(const torch::Tensor& x,\n const std::optional& x_scales,\n const std::optional& topk_idx,\n const std::optional& topk_weights,\n const std::optional& num_tokens_per_rank,\n const torch::Tensor& is_token_in_rank,\n const std::optional& num_tokens_per_expert,\n int cached_num_recv_tokens,\n const std::optional& cached_rank_prefix_matrix,\n const std::optional& cached_channel_prefix_matrix,\n int expert_alignment,\n int num_worst_tokens,\n const Config& config,\n std::optional& previous_event,\n bool async,\n bool allocate_on_comm_stream) {\n bool cached_mode = cached_rank_prefix_matrix.has_value();\n\n // One channel use two blocks, even-numbered blocks for sending, odd-numbered blocks for receiving.\n EP_HOST_ASSERT(config.num_sms % 2 == 0);\n int num_channels = config.num_sms / 2;\n if (cached_mode) {\n EP_HOST_ASSERT(cached_rank_prefix_matrix.has_value());\n EP_HOST_ASSERT(cached_channel_prefix_matrix.has_value());\n } else {\n EP_HOST_ASSERT(num_tokens_per_rank.has_value());\n EP_HOST_ASSERT(num_tokens_per_expert.has_value());\n }\n\n // Type checks\n EP_HOST_ASSERT(is_token_in_rank.scalar_type() == torch::kBool);\n if (cached_mode) {\n EP_HOST_ASSERT(cached_rank_prefix_matrix->scalar_type() == torch::kInt32);\n EP_HOST_ASSERT(cached_channel_prefix_matrix->scalar_type() == torch::kInt32);\n } else {\n EP_HOST_ASSERT(num_tokens_per_expert->scalar_type() == torch::kInt32);\n EP_HOST_ASSERT(num_tokens_per_rank->scalar_type() == torch::kInt32);\n }\n\n // Shape and contiguous checks\n EP_HOST_ASSERT(x.dim() == 2 and x.is_contiguous());\n EP_HOST_ASSERT((x.size(1) * x.element_size()) % sizeof(int4) == 0);\n EP_HOST_ASSERT(is_token_in_rank.dim() == 2 and is_token_in_rank.is_contiguous());\n EP_HOST_ASSERT(is_token_in_rank.size(0) == x.size(0) and is_token_in_rank.size(1) == num_ranks);\n if (cached_mode) {\n EP_HOST_ASSERT(cached_rank_prefix_matrix->dim() == 2 and cached_rank_prefix_matrix->is_contiguous());\n EP_HOST_ASSERT(cached_rank_prefix_matrix->size(0) == num_ranks and cached_rank_prefix_matrix->size(1) == num_ranks);\n EP_HOST_ASSERT(cached_channel_prefix_matrix->dim() == 2 and cached_channel_prefix_matrix->is_contiguous());\n EP_HOST_ASSERT(cached_channel_prefix_matrix->size(0) == num_ranks and cached_channel_prefix_matrix->size(1) == num_channels);\n } else {\n EP_HOST_ASSERT(num_tokens_per_expert->dim() == 1 and num_tokens_per_expert->is_contiguous());\n EP_HOST_ASSERT(num_tokens_per_expert->size(0) % num_ranks == 0);\n EP_HOST_ASSERT(num_tokens_per_expert->size(0) / num_ranks <= NUM_MAX_LOCAL_EXPERTS);\n EP_HOST_ASSERT(num_tokens_per_rank->dim() == 1 and num_tokens_per_rank->is_contiguous());\n EP_HOST_ASSERT(num_tokens_per_rank->size(0) == num_ranks);\n }\n\n auto num_tokens = static_cast(x.size(0)), hidden = static_cast(x.size(1));\n auto num_experts = cached_mode ? 0 : static_cast(num_tokens_per_expert->size(0)), num_local_experts = num_experts / num_ranks;\n\n // Top-k checks\n int num_topk = 0;\n topk_idx_t* topk_idx_ptr = nullptr;\n float* topk_weights_ptr = nullptr;\n EP_HOST_ASSERT(topk_idx.has_value() == topk_weights.has_value());\n if (topk_idx.has_value()) {\n num_topk = static_cast(topk_idx->size(1));\n EP_HOST_ASSERT(num_experts > 0);\n EP_HOST_ASSERT(topk_idx->dim() == 2 and topk_idx->is_contiguous());\n EP_HOST_ASSERT(topk_weights->dim() == 2 and topk_weights->is_contiguous());\n EP_HOST_ASSERT(num_tokens == topk_idx->size(0) and num_tokens == topk_weights->size(0));\n EP_HOST_ASSERT(num_topk == topk_weights->size(1));\n EP_HOST_ASSERT(topk_weights->scalar_type() == torch::kFloat32);\n topk_idx_ptr = topk_idx->data_ptr();\n topk_weights_ptr = topk_weights->data_ptr();\n }\n\n // FP8 scales checks\n float* x_scales_ptr = nullptr;\n int num_scales = 0, scale_token_stride = 0, scale_hidden_stride = 0;\n if (x_scales.has_value()) {\n EP_HOST_ASSERT(x.element_size() == 1);\n EP_HOST_ASSERT(x_scales->scalar_type() == torch::kFloat32 or x_scales->scalar_type() == torch::kInt);\n EP_HOST_ASSERT(x_scales->dim() == 2);\n EP_HOST_ASSERT(x_scales->size(0) == num_tokens);\n num_scales = x_scales->dim() == 1 ? 1 : static_cast(x_scales->size(1));\n x_scales_ptr = static_cast(x_scales->data_ptr());\n scale_token_stride = static_cast(x_scales->stride(0));\n scale_hidden_stride = static_cast(x_scales->stride(1));\n }\n\n // Allocate all tensors on comm stream if set\n // NOTES: do not allocate tensors upfront!\n auto compute_stream = at::cuda::getCurrentCUDAStream();\n if (allocate_on_comm_stream) {\n EP_HOST_ASSERT(previous_event.has_value() and async);\n at::cuda::setCurrentCUDAStream(comm_stream);\n }\n\n // Wait previous tasks to be finished\n if (previous_event.has_value()) {\n stream_wait(comm_stream, previous_event.value());\n } else {\n stream_wait(comm_stream, compute_stream);\n }\n\n // Create handles (only return for non-cached mode)\n int num_recv_tokens = -1;\n auto rank_prefix_matrix = torch::Tensor();\n auto channel_prefix_matrix = torch::Tensor();\n std::vector num_recv_tokens_per_expert_list;\n\n // Barrier or send sizes\n // To clean: channel start/end offset, head and tail\n int num_memset_int = num_channels * num_ranks * 4;\n if (cached_mode) {\n num_recv_tokens = cached_num_recv_tokens;\n rank_prefix_matrix = cached_rank_prefix_matrix.value();\n channel_prefix_matrix = cached_channel_prefix_matrix.value();\n\n // Copy rank prefix matrix and clean flags\n intranode::cached_notify_dispatch(\n rank_prefix_matrix.data_ptr(), num_memset_int, buffer_ptrs_gpu, barrier_signal_ptrs_gpu, rank, num_ranks, comm_stream);\n } else {\n rank_prefix_matrix = torch::empty({num_ranks, num_ranks}, dtype(torch::kInt32).device(torch::kCUDA));\n channel_prefix_matrix = torch::empty({num_ranks, num_channels}, dtype(torch::kInt32).device(torch::kCUDA));\n\n // Send sizes\n // Meta information:\n // - Size prefix by ranks, shaped as `[num_ranks, num_ranks]`\n // - Size prefix by experts (not used later), shaped as `[num_ranks, num_local_experts]`\n // NOTES: no more token dropping in this version\n *moe_recv_counter = -1;\n for (int i = 0; i < num_local_experts; ++i)\n moe_recv_expert_counter[i] = -1;\n EP_HOST_ASSERT(num_ranks * (num_ranks + num_local_experts) * sizeof(int) <= num_nvl_bytes);\n intranode::notify_dispatch(num_tokens_per_rank->data_ptr(),\n moe_recv_counter_mapped,\n num_ranks,\n num_tokens_per_expert->data_ptr(),\n moe_recv_expert_counter_mapped,\n num_experts,\n num_tokens,\n is_token_in_rank.data_ptr(),\n channel_prefix_matrix.data_ptr(),\n rank_prefix_matrix.data_ptr(),\n num_memset_int,\n expert_alignment,\n buffer_ptrs_gpu,\n barrier_signal_ptrs_gpu,\n rank,\n comm_stream,\n num_channels);\n\n if (num_worst_tokens > 0) {\n // No CPU sync, just allocate the worst case\n num_recv_tokens = num_worst_tokens;\n\n // Must be forward with top-k stuffs\n EP_HOST_ASSERT(topk_idx.has_value());\n EP_HOST_ASSERT(topk_weights.has_value());\n } else {\n // Synchronize total received tokens and tokens per expert\n auto start_time = std::chrono::high_resolution_clock::now();\n while (true) {\n // Read total count\n num_recv_tokens = static_cast(*moe_recv_counter);\n\n // Read per-expert count\n bool ready = (num_recv_tokens >= 0);\n for (int i = 0; i < num_local_experts and ready; ++i)\n ready &= moe_recv_expert_counter[i] >= 0;\n\n if (ready)\n break;\n\n // Timeout check\n if (std::chrono::duration_cast(std::chrono::high_resolution_clock::now() - start_time).count() >\n NUM_CPU_TIMEOUT_SECS)\n throw std::runtime_error(\"DeepEP error: CPU recv timeout\");\n }\n num_recv_tokens_per_expert_list = std::vector(moe_recv_expert_counter, moe_recv_expert_counter + num_local_experts);\n }\n }\n\n // Allocate new tensors\n auto recv_x = torch::empty({num_recv_tokens, hidden}, x.options());\n auto recv_src_idx = torch::empty({num_recv_tokens}, dtype(torch::kInt32).device(torch::kCUDA));\n auto recv_topk_idx = std::optional(), recv_topk_weights = std::optional(),\n recv_x_scales = std::optional();\n auto recv_channel_prefix_matrix = torch::empty({num_ranks, num_channels}, dtype(torch::kInt32).device(torch::kCUDA));\n auto send_head = torch::empty({num_tokens, num_ranks}, dtype(torch::kInt32).device(torch::kCUDA));\n\n // Assign pointers\n topk_idx_t* recv_topk_idx_ptr = nullptr;\n float* recv_topk_weights_ptr = nullptr;\n float* recv_x_scales_ptr = nullptr;\n if (topk_idx.has_value()) {\n recv_topk_idx = torch::empty({num_recv_tokens, num_topk}, topk_idx->options());\n recv_topk_weights = torch::empty({num_recv_tokens, num_topk}, topk_weights->options());\n recv_topk_idx_ptr = recv_topk_idx->data_ptr();\n recv_topk_weights_ptr = recv_topk_weights->data_ptr();\n }\n if (x_scales.has_value()) {\n recv_x_scales = x_scales->dim() == 1 ? torch::empty({num_recv_tokens}, x_scales->options())\n : torch::empty({num_recv_tokens, num_scales}, x_scales->options());\n recv_x_scales_ptr = static_cast(recv_x_scales->data_ptr());\n }\n\n // Dispatch\n EP_HOST_ASSERT(\n num_ranks * num_ranks * sizeof(int) + // Size prefix matrix\n num_channels * num_ranks * sizeof(int) + // Channel start offset\n num_channels * num_ranks * sizeof(int) + // Channel end offset\n num_channels * num_ranks * sizeof(int) * 2 + // Queue head and tail\n num_channels * num_ranks * config.num_max_nvl_chunked_recv_tokens * hidden * recv_x.element_size() + // Data buffer\n num_channels * num_ranks * config.num_max_nvl_chunked_recv_tokens * sizeof(int) + // Source index buffer\n num_channels * num_ranks * config.num_max_nvl_chunked_recv_tokens * num_topk * sizeof(topk_idx_t) + // Top-k index buffer\n num_channels * num_ranks * config.num_max_nvl_chunked_recv_tokens * num_topk * sizeof(float) + // Top-k weight buffer\n num_channels * num_ranks * config.num_max_nvl_chunked_recv_tokens * sizeof(float) * num_scales // FP8 scale buffer\n <= num_nvl_bytes);\n intranode::dispatch(recv_x.data_ptr(),\n recv_x_scales_ptr,\n recv_src_idx.data_ptr(),\n recv_topk_idx_ptr,\n recv_topk_weights_ptr,\n recv_channel_prefix_matrix.data_ptr(),\n send_head.data_ptr(),\n x.data_ptr(),\n x_scales_ptr,\n topk_idx_ptr,\n topk_weights_ptr,\n is_token_in_rank.data_ptr(),\n channel_prefix_matrix.data_ptr(),\n num_tokens,\n num_worst_tokens,\n static_cast(hidden * recv_x.element_size() / sizeof(int4)),\n num_topk,\n num_experts,\n num_scales,\n scale_token_stride,\n scale_hidden_stride,\n buffer_ptrs_gpu,\n rank,\n num_ranks,\n comm_stream,\n config.num_sms,\n config.num_max_nvl_chunked_send_tokens,\n config.num_max_nvl_chunked_recv_tokens);\n\n // Wait streams\n std::optional event;\n if (async) {\n event = EventHandle(comm_stream);\n for (auto& t : {x,\n is_token_in_rank,\n rank_prefix_matrix,\n channel_prefix_matrix,\n recv_x,\n recv_src_idx,\n recv_channel_prefix_matrix,\n send_head}) {\n t.record_stream(comm_stream);\n if (allocate_on_comm_stream)\n t.record_stream(compute_stream);\n }\n for (auto& to : {x_scales,\n topk_idx,\n topk_weights,\n num_tokens_per_rank,\n num_tokens_per_expert,\n cached_channel_prefix_matrix,\n cached_rank_prefix_matrix,\n recv_topk_idx,\n recv_topk_weights,\n recv_x_scales}) {\n to.has_value() ? to->record_stream(comm_stream) : void();\n if (allocate_on_comm_stream)\n to.has_value() ? to->record_stream(compute_stream) : void();\n }\n } else {\n stream_wait(compute_stream, comm_stream);\n }\n\n // Switch back compute stream\n if (allocate_on_comm_stream)\n at::cuda::setCurrentCUDAStream(compute_stream);\n\n // Return values\n return {recv_x,\n recv_x_scales,\n recv_topk_idx,\n recv_topk_weights,\n num_recv_tokens_per_expert_list,\n rank_prefix_matrix,\n channel_prefix_matrix,\n recv_channel_prefix_matrix,\n recv_src_idx,\n send_head,\n event};\n}\n\nstd::tuple, std::optional> Buffer::intranode_combine(\n const torch::Tensor& x,\n const std::optional& topk_weights,\n const std::optional& bias_0,\n const std::optional& bias_1,\n const torch::Tensor& src_idx,\n const torch::Tensor& rank_prefix_matrix,\n const torch::Tensor& channel_prefix_matrix,\n const torch::Tensor& send_head,\n const Config& config,\n std::optional& previous_event,\n bool async,\n bool allocate_on_comm_stream) {\n EP_HOST_ASSERT(x.dim() == 2 and x.is_contiguous());\n EP_HOST_ASSERT(src_idx.dim() == 1 and src_idx.is_contiguous() and src_idx.scalar_type() == torch::kInt32);\n EP_HOST_ASSERT(send_head.dim() == 2 and send_head.is_contiguous() and send_head.scalar_type() == torch::kInt32);\n EP_HOST_ASSERT(rank_prefix_matrix.dim() == 2 and rank_prefix_matrix.is_contiguous() and\n rank_prefix_matrix.scalar_type() == torch::kInt32);\n EP_HOST_ASSERT(channel_prefix_matrix.dim() == 2 and channel_prefix_matrix.is_contiguous() and\n channel_prefix_matrix.scalar_type() == torch::kInt32);\n\n // One channel use two blocks, even-numbered blocks for sending, odd-numbered blocks for receiving.\n EP_HOST_ASSERT(config.num_sms % 2 == 0);\n int num_channels = config.num_sms / 2;\n\n auto num_tokens = static_cast(x.size(0)), hidden = static_cast(x.size(1));\n auto num_recv_tokens = static_cast(send_head.size(0));\n EP_HOST_ASSERT(src_idx.size(0) == num_tokens);\n EP_HOST_ASSERT(send_head.size(1) == num_ranks);\n EP_HOST_ASSERT(rank_prefix_matrix.size(0) == num_ranks and rank_prefix_matrix.size(1) == num_ranks);\n EP_HOST_ASSERT(channel_prefix_matrix.size(0) == num_ranks and channel_prefix_matrix.size(1) == num_channels);\n EP_HOST_ASSERT((hidden * x.element_size()) % sizeof(int4) == 0);\n\n // Allocate all tensors on comm stream if set\n // NOTES: do not allocate tensors upfront!\n auto compute_stream = at::cuda::getCurrentCUDAStream();\n if (allocate_on_comm_stream) {\n EP_HOST_ASSERT(previous_event.has_value() and async);\n at::cuda::setCurrentCUDAStream(comm_stream);\n }\n\n // Wait previous tasks to be finished\n if (previous_event.has_value()) {\n stream_wait(comm_stream, previous_event.value());\n } else {\n stream_wait(comm_stream, compute_stream);\n }\n\n int num_topk = 0;\n auto recv_topk_weights = std::optional();\n float* topk_weights_ptr = nullptr;\n float* recv_topk_weights_ptr = nullptr;\n if (topk_weights.has_value()) {\n EP_HOST_ASSERT(topk_weights->dim() == 2 and topk_weights->is_contiguous());\n EP_HOST_ASSERT(topk_weights->size(0) == num_tokens);\n EP_HOST_ASSERT(topk_weights->scalar_type() == torch::kFloat32);\n num_topk = static_cast(topk_weights->size(1));\n topk_weights_ptr = topk_weights->data_ptr();\n recv_topk_weights = torch::empty({num_recv_tokens, num_topk}, topk_weights->options());\n recv_topk_weights_ptr = recv_topk_weights->data_ptr();\n }\n\n // Launch barrier and reset queue head and tail\n EP_HOST_ASSERT(num_channels * num_ranks * sizeof(int) * 2 <= num_nvl_bytes);\n intranode::cached_notify_combine(buffer_ptrs_gpu,\n send_head.data_ptr(),\n num_channels,\n num_recv_tokens,\n num_channels * num_ranks * 2,\n barrier_signal_ptrs_gpu,\n rank,\n num_ranks,\n comm_stream);\n\n // Assign bias pointers\n auto bias_opts = std::vector>({bias_0, bias_1});\n void* bias_ptrs[2] = {nullptr, nullptr};\n for (int i = 0; i < 2; ++i)\n if (bias_opts[i].has_value()) {\n auto bias = bias_opts[i].value();\n EP_HOST_ASSERT(bias.dim() == 2 and bias.is_contiguous());\n EP_HOST_ASSERT(bias.scalar_type() == x.scalar_type());\n EP_HOST_ASSERT(bias.size(0) == num_recv_tokens and bias.size(1) == hidden);\n bias_ptrs[i] = bias.data_ptr();\n }\n\n // Combine data\n auto recv_x = torch::empty({num_recv_tokens, hidden}, x.options());\n EP_HOST_ASSERT(num_channels * num_ranks * sizeof(int) * 2 + // Queue head and tail\n num_channels * num_ranks * config.num_max_nvl_chunked_recv_tokens * hidden * x.element_size() + // Data buffer\n num_channels * num_ranks * config.num_max_nvl_chunked_recv_tokens * sizeof(int) + // Source index buffer\n num_channels * num_ranks * config.num_max_nvl_chunked_recv_tokens * num_topk * sizeof(float) // Top-k weight buffer\n <= num_nvl_bytes);\n intranode::combine(at::cuda::ScalarTypeToCudaDataType(x.scalar_type()),\n recv_x.data_ptr(),\n recv_topk_weights_ptr,\n x.data_ptr(),\n topk_weights_ptr,\n bias_ptrs[0],\n bias_ptrs[1],\n src_idx.data_ptr(),\n rank_prefix_matrix.data_ptr(),\n channel_prefix_matrix.data_ptr(),\n send_head.data_ptr(),\n num_tokens,\n num_recv_tokens,\n hidden,\n num_topk,\n buffer_ptrs_gpu,\n rank,\n num_ranks,\n comm_stream,\n config.num_sms,\n config.num_max_nvl_chunked_send_tokens,\n config.num_max_nvl_chunked_recv_tokens);\n\n // Wait streams\n std::optional event;\n if (async) {\n event = EventHandle(comm_stream);\n for (auto& t : {x, src_idx, send_head, rank_prefix_matrix, channel_prefix_matrix, recv_x}) {\n t.record_stream(comm_stream);\n if (allocate_on_comm_stream)\n t.record_stream(compute_stream);\n }\n for (auto& to : {topk_weights, recv_topk_weights, bias_0, bias_1}) {\n to.has_value() ? to->record_stream(comm_stream) : void();\n if (allocate_on_comm_stream)\n to.has_value() ? to->record_stream(compute_stream) : void();\n }\n } else {\n stream_wait(compute_stream, comm_stream);\n }\n\n // Switch back compute stream\n if (allocate_on_comm_stream)\n at::cuda::setCurrentCUDAStream(compute_stream);\n\n return {recv_x, recv_topk_weights, event};\n}\n\nstd::tuple,\n std::optional,\n std::optional,\n std::vector,\n torch::Tensor,\n torch::Tensor,\n std::optional,\n torch::Tensor,\n std::optional,\n torch::Tensor,\n std::optional,\n std::optional,\n std::optional,\n std::optional>\nBuffer::internode_dispatch(const torch::Tensor& x,\n const std::optional& x_scales,\n const std::optional& topk_idx,\n const std::optional& topk_weights,\n const std::optional& num_tokens_per_rank,\n const std::optional& num_tokens_per_rdma_rank,\n const torch::Tensor& is_token_in_rank,\n const std::optional& num_tokens_per_expert,\n int cached_num_recv_tokens,\n int cached_num_rdma_recv_tokens,\n const std::optional& cached_rdma_channel_prefix_matrix,\n const std::optional& cached_recv_rdma_rank_prefix_sum,\n const std::optional& cached_gbl_channel_prefix_matrix,\n const std::optional& cached_recv_gbl_rank_prefix_sum,\n int expert_alignment,\n int num_worst_tokens,\n const Config& config,\n std::optional& previous_event,\n bool async,\n bool allocate_on_comm_stream) {\n#ifndef DISABLE_NVSHMEM\n // In dispatch, CPU will busy-wait until GPU receive tensor size metadata from other ranks, which can be quite long.\n // If users of DeepEP need to execute other Python code on other threads, such as KV transfer, their code will get stuck due to GIL\n // unless we release GIL here.\n pybind11::gil_scoped_release release;\n\n const int num_channels = config.num_sms / 2;\n EP_HOST_ASSERT(config.num_sms % 2 == 0);\n EP_HOST_ASSERT(0 < get_num_rdma_ranks() and get_num_rdma_ranks() <= NUM_MAX_RDMA_PEERS);\n\n bool cached_mode = cached_rdma_channel_prefix_matrix.has_value();\n if (cached_mode) {\n EP_HOST_ASSERT(cached_rdma_channel_prefix_matrix.has_value());\n EP_HOST_ASSERT(cached_recv_rdma_rank_prefix_sum.has_value());\n EP_HOST_ASSERT(cached_gbl_channel_prefix_matrix.has_value());\n EP_HOST_ASSERT(cached_recv_gbl_rank_prefix_sum.has_value());\n } else {\n EP_HOST_ASSERT(num_tokens_per_rank.has_value());\n EP_HOST_ASSERT(num_tokens_per_rdma_rank.has_value());\n EP_HOST_ASSERT(num_tokens_per_expert.has_value());\n }\n\n // Type checks\n if (cached_mode) {\n EP_HOST_ASSERT(cached_rdma_channel_prefix_matrix->scalar_type() == torch::kInt32);\n EP_HOST_ASSERT(cached_recv_rdma_rank_prefix_sum->scalar_type() == torch::kInt32);\n EP_HOST_ASSERT(cached_gbl_channel_prefix_matrix->scalar_type() == torch::kInt32);\n EP_HOST_ASSERT(cached_recv_gbl_rank_prefix_sum->scalar_type() == torch::kInt32);\n } else {\n EP_HOST_ASSERT(num_tokens_per_rank->scalar_type() == torch::kInt32);\n EP_HOST_ASSERT(num_tokens_per_rdma_rank->scalar_type() == torch::kInt32);\n EP_HOST_ASSERT(num_tokens_per_expert->scalar_type() == torch::kInt32);\n }\n\n // Shape and contiguous checks\n EP_HOST_ASSERT(x.dim() == 2 and x.is_contiguous());\n EP_HOST_ASSERT((x.size(1) * x.element_size()) % sizeof(int4) == 0);\n if (cached_mode) {\n EP_HOST_ASSERT(cached_rdma_channel_prefix_matrix->dim() == 2 and cached_rdma_channel_prefix_matrix->is_contiguous());\n EP_HOST_ASSERT(cached_rdma_channel_prefix_matrix->size(0) == num_rdma_ranks and\n cached_rdma_channel_prefix_matrix->size(1) == num_channels);\n EP_HOST_ASSERT(cached_recv_rdma_rank_prefix_sum->dim() == 1 and cached_recv_rdma_rank_prefix_sum->is_contiguous());\n EP_HOST_ASSERT(cached_recv_rdma_rank_prefix_sum->size(0) == num_rdma_ranks);\n EP_HOST_ASSERT(cached_gbl_channel_prefix_matrix->dim() == 2 and cached_gbl_channel_prefix_matrix->is_contiguous());\n EP_HOST_ASSERT(cached_gbl_channel_prefix_matrix->size(0) == num_ranks and\n cached_gbl_channel_prefix_matrix->size(1) == num_channels);\n EP_HOST_ASSERT(cached_recv_gbl_rank_prefix_sum->dim() == 1 and cached_recv_gbl_rank_prefix_sum->is_contiguous());\n EP_HOST_ASSERT(cached_recv_gbl_rank_prefix_sum->size(0) == num_ranks);\n } else {\n EP_HOST_ASSERT(num_tokens_per_rank->dim() == 1 and num_tokens_per_rank->is_contiguous());\n EP_HOST_ASSERT(num_tokens_per_rdma_rank->dim() == 1 and num_tokens_per_rdma_rank->is_contiguous());\n EP_HOST_ASSERT(num_tokens_per_expert->dim() == 1 and num_tokens_per_expert->is_contiguous());\n EP_HOST_ASSERT(num_tokens_per_rank->size(0) == num_ranks);\n EP_HOST_ASSERT(num_tokens_per_rdma_rank->size(0) == num_rdma_ranks);\n EP_HOST_ASSERT(num_tokens_per_expert->size(0) % num_ranks == 0);\n EP_HOST_ASSERT(num_tokens_per_expert->size(0) / num_ranks <= NUM_MAX_LOCAL_EXPERTS);\n }\n\n auto num_tokens = static_cast(x.size(0)), hidden = static_cast(x.size(1)),\n hidden_int4 = static_cast(x.size(1) * x.element_size() / sizeof(int4));\n auto num_experts = cached_mode ? 0 : static_cast(num_tokens_per_expert->size(0)), num_local_experts = num_experts / num_ranks;\n\n // Top-k checks\n int num_topk = 0;\n topk_idx_t* topk_idx_ptr = nullptr;\n float* topk_weights_ptr = nullptr;\n EP_HOST_ASSERT(topk_idx.has_value() == topk_weights.has_value());\n if (topk_idx.has_value()) {\n num_topk = static_cast(topk_idx->size(1));\n EP_HOST_ASSERT(num_experts > 0);\n EP_HOST_ASSERT(topk_idx->dim() == 2 and topk_idx->is_contiguous());\n EP_HOST_ASSERT(topk_weights->dim() == 2 and topk_weights->is_contiguous());\n EP_HOST_ASSERT(num_tokens == topk_idx->size(0) and num_tokens == topk_weights->size(0));\n EP_HOST_ASSERT(num_topk == topk_weights->size(1));\n EP_HOST_ASSERT(topk_weights->scalar_type() == torch::kFloat32);\n topk_idx_ptr = topk_idx->data_ptr();\n topk_weights_ptr = topk_weights->data_ptr();\n }\n\n // FP8 scales checks\n float* x_scales_ptr = nullptr;\n int num_scales = 0, scale_token_stride = 0, scale_hidden_stride = 0;\n if (x_scales.has_value()) {\n EP_HOST_ASSERT(x.element_size() == 1);\n EP_HOST_ASSERT(x_scales->scalar_type() == torch::kFloat32 or x_scales->scalar_type() == torch::kInt);\n EP_HOST_ASSERT(x_scales->dim() == 2);\n EP_HOST_ASSERT(x_scales->size(0) == num_tokens);\n num_scales = x_scales->dim() == 1 ? 1 : static_cast(x_scales->size(1));\n x_scales_ptr = static_cast(x_scales->data_ptr());\n scale_token_stride = static_cast(x_scales->stride(0));\n scale_hidden_stride = static_cast(x_scales->stride(1));\n }\n\n // Allocate all tensors on comm stream if set\n // NOTES: do not allocate tensors upfront!\n auto compute_stream = at::cuda::getCurrentCUDAStream();\n if (allocate_on_comm_stream) {\n EP_HOST_ASSERT(previous_event.has_value() and async);\n at::cuda::setCurrentCUDAStream(comm_stream);\n }\n\n // Wait previous tasks to be finished\n if (previous_event.has_value()) {\n stream_wait(comm_stream, previous_event.value());\n } else {\n stream_wait(comm_stream, compute_stream);\n }\n\n // Create handles (only return for non-cached mode)\n int num_recv_tokens = -1, num_rdma_recv_tokens = -1;\n auto rdma_channel_prefix_matrix = torch::Tensor();\n auto recv_rdma_rank_prefix_sum = torch::Tensor();\n auto gbl_channel_prefix_matrix = torch::Tensor();\n auto recv_gbl_rank_prefix_sum = torch::Tensor();\n std::vector num_recv_tokens_per_expert_list;\n\n // Barrier or send sizes\n if (cached_mode) {\n num_recv_tokens = cached_num_recv_tokens;\n num_rdma_recv_tokens = cached_num_rdma_recv_tokens;\n rdma_channel_prefix_matrix = cached_rdma_channel_prefix_matrix.value();\n recv_rdma_rank_prefix_sum = cached_recv_rdma_rank_prefix_sum.value();\n gbl_channel_prefix_matrix = cached_gbl_channel_prefix_matrix.value();\n recv_gbl_rank_prefix_sum = cached_recv_gbl_rank_prefix_sum.value();\n\n // Just a barrier and clean flags\n internode::cached_notify(hidden_int4,\n num_scales,\n num_topk,\n num_topk,\n num_ranks,\n num_channels,\n 0,\n nullptr,\n nullptr,\n nullptr,\n nullptr,\n rdma_buffer_ptr,\n config.num_max_rdma_chunked_recv_tokens,\n buffer_ptrs_gpu,\n config.num_max_nvl_chunked_recv_tokens,\n barrier_signal_ptrs_gpu,\n rank,\n comm_stream,\n config.get_rdma_buffer_size_hint(hidden_int4 * sizeof(int4), num_ranks),\n num_nvl_bytes,\n true,\n low_latency_mode);\n } else {\n rdma_channel_prefix_matrix = torch::empty({num_rdma_ranks, num_channels}, dtype(torch::kInt32).device(torch::kCUDA));\n recv_rdma_rank_prefix_sum = torch::empty({num_rdma_ranks}, dtype(torch::kInt32).device(torch::kCUDA));\n gbl_channel_prefix_matrix = torch::empty({num_ranks, num_channels}, dtype(torch::kInt32).device(torch::kCUDA));\n recv_gbl_rank_prefix_sum = torch::empty({num_ranks}, dtype(torch::kInt32).device(torch::kCUDA));\n\n // Send sizes\n *moe_recv_counter = -1, *moe_recv_rdma_counter = -1;\n for (int i = 0; i < num_local_experts; ++i)\n moe_recv_expert_counter[i] = -1;\n internode::notify_dispatch(num_tokens_per_rank->data_ptr(),\n moe_recv_counter_mapped,\n num_ranks,\n num_tokens_per_rdma_rank->data_ptr(),\n moe_recv_rdma_counter_mapped,\n num_tokens_per_expert->data_ptr(),\n moe_recv_expert_counter_mapped,\n num_experts,\n is_token_in_rank.data_ptr(),\n num_tokens,\n num_worst_tokens,\n num_channels,\n hidden_int4,\n num_scales,\n num_topk,\n expert_alignment,\n rdma_channel_prefix_matrix.data_ptr(),\n recv_rdma_rank_prefix_sum.data_ptr(),\n gbl_channel_prefix_matrix.data_ptr(),\n recv_gbl_rank_prefix_sum.data_ptr(),\n rdma_buffer_ptr,\n config.num_max_rdma_chunked_recv_tokens,\n buffer_ptrs_gpu,\n config.num_max_nvl_chunked_recv_tokens,\n barrier_signal_ptrs_gpu,\n rank,\n comm_stream,\n config.get_rdma_buffer_size_hint(hidden_int4 * sizeof(int4), num_ranks),\n num_nvl_bytes,\n low_latency_mode);\n\n // Synchronize total received tokens and tokens per expert\n if (num_worst_tokens > 0) {\n num_recv_tokens = num_worst_tokens;\n num_rdma_recv_tokens = num_worst_tokens;\n } else {\n auto start_time = std::chrono::high_resolution_clock::now();\n while (true) {\n // Read total count\n num_recv_tokens = static_cast(*moe_recv_counter);\n num_rdma_recv_tokens = static_cast(*moe_recv_rdma_counter);\n\n // Read per-expert count\n bool ready = (num_recv_tokens >= 0) and (num_rdma_recv_tokens >= 0);\n for (int i = 0; i < num_local_experts and ready; ++i)\n ready &= moe_recv_expert_counter[i] >= 0;\n\n if (ready)\n break;\n\n // Timeout check\n if (std::chrono::duration_cast(std::chrono::high_resolution_clock::now() - start_time).count() >\n NUM_CPU_TIMEOUT_SECS) {\n printf(\"Global rank: %d, num_recv_tokens: %d, num_rdma_recv_tokens: %d\\n\", rank, num_recv_tokens, num_rdma_recv_tokens);\n for (int i = 0; i < num_local_experts; ++i)\n printf(\"moe_recv_expert_counter[%d]: %d\\n\", i, moe_recv_expert_counter[i]);\n throw std::runtime_error(\"DeepEP error: timeout (dispatch CPU)\");\n }\n }\n num_recv_tokens_per_expert_list = std::vector(moe_recv_expert_counter, moe_recv_expert_counter + num_local_experts);\n }\n }\n\n // Allocate new tensors\n auto recv_x = torch::empty({num_recv_tokens, hidden}, x.options());\n auto recv_topk_idx = std::optional(), recv_topk_weights = std::optional(),\n recv_x_scales = std::optional();\n auto recv_src_meta = std::optional();\n auto recv_rdma_channel_prefix_matrix = std::optional();\n auto recv_gbl_channel_prefix_matrix = std::optional();\n auto send_rdma_head = std::optional();\n auto send_nvl_head = std::optional();\n if (not cached_mode) {\n recv_src_meta = torch::empty({num_recv_tokens, internode::get_source_meta_bytes()}, dtype(torch::kByte).device(torch::kCUDA));\n recv_rdma_channel_prefix_matrix = torch::empty({num_rdma_ranks, num_channels}, dtype(torch::kInt32).device(torch::kCUDA));\n recv_gbl_channel_prefix_matrix = torch::empty({num_ranks, num_channels}, dtype(torch::kInt32).device(torch::kCUDA));\n send_rdma_head = torch::empty({num_tokens, num_rdma_ranks}, dtype(torch::kInt32).device(torch::kCUDA));\n send_nvl_head = torch::empty({num_rdma_recv_tokens, NUM_MAX_NVL_PEERS}, dtype(torch::kInt32).device(torch::kCUDA));\n }\n\n // Assign pointers\n topk_idx_t* recv_topk_idx_ptr = nullptr;\n float* recv_topk_weights_ptr = nullptr;\n float* recv_x_scales_ptr = nullptr;\n if (topk_idx.has_value()) {\n recv_topk_idx = torch::empty({num_recv_tokens, num_topk}, topk_idx->options());\n recv_topk_weights = torch::empty({num_recv_tokens, num_topk}, topk_weights->options());\n recv_topk_idx_ptr = recv_topk_idx->data_ptr();\n recv_topk_weights_ptr = recv_topk_weights->data_ptr();\n }\n if (x_scales.has_value()) {\n recv_x_scales = x_scales->dim() == 1 ? torch::empty({num_recv_tokens}, x_scales->options())\n : torch::empty({num_recv_tokens, num_scales}, x_scales->options());\n recv_x_scales_ptr = static_cast(recv_x_scales->data_ptr());\n }\n\n // Launch data dispatch\n // NOTES: the buffer size checks are moved into the `.cu` file\n internode::dispatch(recv_x.data_ptr(),\n recv_x_scales_ptr,\n recv_topk_idx_ptr,\n recv_topk_weights_ptr,\n cached_mode ? nullptr : recv_src_meta->data_ptr(),\n x.data_ptr(),\n x_scales_ptr,\n topk_idx_ptr,\n topk_weights_ptr,\n cached_mode ? nullptr : send_rdma_head->data_ptr(),\n cached_mode ? nullptr : send_nvl_head->data_ptr(),\n cached_mode ? nullptr : recv_rdma_channel_prefix_matrix->data_ptr(),\n cached_mode ? nullptr : recv_gbl_channel_prefix_matrix->data_ptr(),\n rdma_channel_prefix_matrix.data_ptr(),\n recv_rdma_rank_prefix_sum.data_ptr(),\n gbl_channel_prefix_matrix.data_ptr(),\n recv_gbl_rank_prefix_sum.data_ptr(),\n is_token_in_rank.data_ptr(),\n num_tokens,\n num_worst_tokens,\n hidden_int4,\n num_scales,\n num_topk,\n num_experts,\n scale_token_stride,\n scale_hidden_stride,\n rdma_buffer_ptr,\n config.num_max_rdma_chunked_send_tokens,\n config.num_max_rdma_chunked_recv_tokens,\n buffer_ptrs_gpu,\n config.num_max_nvl_chunked_send_tokens,\n config.num_max_nvl_chunked_recv_tokens,\n rank,\n num_ranks,\n cached_mode,\n comm_stream,\n num_channels,\n low_latency_mode);\n\n // Wait streams\n std::optional event;\n if (async) {\n event = EventHandle(comm_stream);\n for (auto& t : {x,\n is_token_in_rank,\n recv_x,\n rdma_channel_prefix_matrix,\n recv_rdma_rank_prefix_sum,\n gbl_channel_prefix_matrix,\n recv_gbl_rank_prefix_sum}) {\n t.record_stream(comm_stream);\n if (allocate_on_comm_stream)\n t.record_stream(compute_stream);\n }\n for (auto& to : {x_scales,\n topk_idx,\n topk_weights,\n num_tokens_per_rank,\n num_tokens_per_rdma_rank,\n num_tokens_per_expert,\n cached_rdma_channel_prefix_matrix,\n cached_recv_rdma_rank_prefix_sum,\n cached_gbl_channel_prefix_matrix,\n cached_recv_gbl_rank_prefix_sum,\n recv_topk_idx,\n recv_topk_weights,\n recv_x_scales,\n recv_rdma_channel_prefix_matrix,\n recv_gbl_channel_prefix_matrix,\n send_rdma_head,\n send_nvl_head,\n recv_src_meta}) {\n to.has_value() ? to->record_stream(comm_stream) : void();\n if (allocate_on_comm_stream)\n to.has_value() ? to->record_stream(compute_stream) : void();\n }\n } else {\n stream_wait(compute_stream, comm_stream);\n }\n\n // Switch back compute stream\n if (allocate_on_comm_stream)\n at::cuda::setCurrentCUDAStream(compute_stream);\n\n // Return values\n return {recv_x,\n recv_x_scales,\n recv_topk_idx,\n recv_topk_weights,\n num_recv_tokens_per_expert_list,\n rdma_channel_prefix_matrix,\n gbl_channel_prefix_matrix,\n recv_rdma_channel_prefix_matrix,\n recv_rdma_rank_prefix_sum,\n recv_gbl_channel_prefix_matrix,\n recv_gbl_rank_prefix_sum,\n recv_src_meta,\n send_rdma_head,\n send_nvl_head,\n event};\n#else\n EP_HOST_ASSERT(false and \"NVSHMEM is disabled during compilation\");\n return {};\n#endif\n}\n\nstd::tuple, std::optional> Buffer::internode_combine(\n const torch::Tensor& x,\n const std::optional& topk_weights,\n const std::optional& bias_0,\n const std::optional& bias_1,\n const torch::Tensor& src_meta,\n const torch::Tensor& is_combined_token_in_rank,\n const torch::Tensor& rdma_channel_prefix_matrix,\n const torch::Tensor& rdma_rank_prefix_sum,\n const torch::Tensor& gbl_channel_prefix_matrix,\n const torch::Tensor& combined_rdma_head,\n const torch::Tensor& combined_nvl_head,\n const Config& config,\n std::optional& previous_event,\n bool async,\n bool allocate_on_comm_stream) {\n#ifndef DISABLE_NVSHMEM\n const int num_channels = config.num_sms / 2;\n EP_HOST_ASSERT(config.num_sms % 2 == 0);\n\n // Shape and contiguous checks\n EP_HOST_ASSERT(x.dim() == 2 and x.is_contiguous());\n EP_HOST_ASSERT(src_meta.dim() == 2 and src_meta.is_contiguous() and src_meta.scalar_type() == torch::kByte);\n EP_HOST_ASSERT(is_combined_token_in_rank.dim() == 2 and is_combined_token_in_rank.is_contiguous() and\n is_combined_token_in_rank.scalar_type() == torch::kBool);\n EP_HOST_ASSERT(rdma_channel_prefix_matrix.dim() == 2 and rdma_channel_prefix_matrix.is_contiguous() and\n rdma_channel_prefix_matrix.scalar_type() == torch::kInt32);\n EP_HOST_ASSERT(rdma_rank_prefix_sum.dim() == 1 and rdma_rank_prefix_sum.is_contiguous() and\n rdma_rank_prefix_sum.scalar_type() == torch::kInt32);\n EP_HOST_ASSERT(gbl_channel_prefix_matrix.dim() == 2 and gbl_channel_prefix_matrix.is_contiguous() and\n gbl_channel_prefix_matrix.scalar_type() == torch::kInt32);\n EP_HOST_ASSERT(combined_rdma_head.dim() == 2 and combined_rdma_head.is_contiguous() and\n combined_rdma_head.scalar_type() == torch::kInt32);\n EP_HOST_ASSERT(combined_nvl_head.dim() == 2 and combined_nvl_head.is_contiguous() and combined_nvl_head.scalar_type() == torch::kInt32);\n\n auto num_tokens = static_cast(x.size(0)), hidden = static_cast(x.size(1)),\n hidden_int4 = static_cast(x.size(1) * x.element_size() / sizeof(int4));\n auto num_combined_tokens = static_cast(is_combined_token_in_rank.size(0));\n EP_HOST_ASSERT((hidden * x.element_size()) % sizeof(int4) == 0);\n EP_HOST_ASSERT(src_meta.size(1) == internode::get_source_meta_bytes());\n EP_HOST_ASSERT(is_combined_token_in_rank.size(1) == num_ranks);\n EP_HOST_ASSERT(rdma_channel_prefix_matrix.size(0) == num_rdma_ranks and rdma_channel_prefix_matrix.size(1) == num_channels);\n EP_HOST_ASSERT(rdma_rank_prefix_sum.size(0) == num_rdma_ranks);\n EP_HOST_ASSERT(gbl_channel_prefix_matrix.size(0) == num_ranks and gbl_channel_prefix_matrix.size(1) == num_channels);\n EP_HOST_ASSERT(combined_rdma_head.dim() == 2 and combined_rdma_head.size(0) == num_combined_tokens and\n combined_rdma_head.size(1) == num_rdma_ranks);\n EP_HOST_ASSERT(combined_nvl_head.dim() == 2 and combined_nvl_head.size(1) == NUM_MAX_NVL_PEERS);\n\n // Allocate all tensors on comm stream if set\n // NOTES: do not allocate tensors upfront!\n auto compute_stream = at::cuda::getCurrentCUDAStream();\n if (allocate_on_comm_stream) {\n EP_HOST_ASSERT(previous_event.has_value() and async);\n at::cuda::setCurrentCUDAStream(comm_stream);\n }\n\n // Wait previous tasks to be finished\n if (previous_event.has_value()) {\n stream_wait(comm_stream, previous_event.value());\n } else {\n stream_wait(comm_stream, compute_stream);\n }\n\n // Top-k checks\n int num_topk = 0;\n auto combined_topk_weights = std::optional();\n float* topk_weights_ptr = nullptr;\n float* combined_topk_weights_ptr = nullptr;\n if (topk_weights.has_value()) {\n EP_HOST_ASSERT(topk_weights->dim() == 2 and topk_weights->is_contiguous());\n EP_HOST_ASSERT(topk_weights->size(0) == num_tokens);\n EP_HOST_ASSERT(topk_weights->scalar_type() == torch::kFloat32);\n num_topk = static_cast(topk_weights->size(1));\n topk_weights_ptr = topk_weights->data_ptr();\n combined_topk_weights = torch::empty({num_combined_tokens, num_topk}, topk_weights->options());\n combined_topk_weights_ptr = combined_topk_weights->data_ptr();\n }\n\n // Extra check for avoid-dead-lock design\n EP_HOST_ASSERT(config.num_max_nvl_chunked_recv_tokens % num_rdma_ranks == 0);\n EP_HOST_ASSERT(config.num_max_nvl_chunked_send_tokens <= config.num_max_nvl_chunked_recv_tokens / num_rdma_ranks);\n\n // Launch barrier and reset queue head and tail\n internode::cached_notify(hidden_int4,\n 0,\n 0,\n num_topk,\n num_ranks,\n num_channels,\n num_combined_tokens,\n combined_rdma_head.data_ptr(),\n rdma_channel_prefix_matrix.data_ptr(),\n rdma_rank_prefix_sum.data_ptr(),\n combined_nvl_head.data_ptr(),\n rdma_buffer_ptr,\n config.num_max_rdma_chunked_recv_tokens,\n buffer_ptrs_gpu,\n config.num_max_nvl_chunked_recv_tokens,\n barrier_signal_ptrs_gpu,\n rank,\n comm_stream,\n config.get_rdma_buffer_size_hint(hidden_int4 * sizeof(int4), num_ranks),\n num_nvl_bytes,\n false,\n low_latency_mode);\n\n // Assign bias pointers\n auto bias_opts = std::vector>({bias_0, bias_1});\n void* bias_ptrs[2] = {nullptr, nullptr};\n for (int i = 0; i < 2; ++i)\n if (bias_opts[i].has_value()) {\n auto bias = bias_opts[i].value();\n EP_HOST_ASSERT(bias.dim() == 2 and bias.is_contiguous());\n EP_HOST_ASSERT(bias.scalar_type() == x.scalar_type());\n EP_HOST_ASSERT(bias.size(0) == num_combined_tokens and bias.size(1) == hidden);\n bias_ptrs[i] = bias.data_ptr();\n }\n\n // Launch data combine\n auto combined_x = torch::empty({num_combined_tokens, hidden}, x.options());\n internode::combine(at::cuda::ScalarTypeToCudaDataType(x.scalar_type()),\n combined_x.data_ptr(),\n combined_topk_weights_ptr,\n is_combined_token_in_rank.data_ptr(),\n x.data_ptr(),\n topk_weights_ptr,\n bias_ptrs[0],\n bias_ptrs[1],\n combined_rdma_head.data_ptr(),\n combined_nvl_head.data_ptr(),\n src_meta.data_ptr(),\n rdma_channel_prefix_matrix.data_ptr(),\n rdma_rank_prefix_sum.data_ptr(),\n gbl_channel_prefix_matrix.data_ptr(),\n num_tokens,\n num_combined_tokens,\n hidden,\n num_topk,\n rdma_buffer_ptr,\n config.num_max_rdma_chunked_send_tokens,\n config.num_max_rdma_chunked_recv_tokens,\n buffer_ptrs_gpu,\n config.num_max_nvl_chunked_send_tokens,\n config.num_max_nvl_chunked_recv_tokens,\n rank,\n num_ranks,\n comm_stream,\n num_channels,\n low_latency_mode);\n\n // Wait streams\n std::optional event;\n if (async) {\n event = EventHandle(comm_stream);\n for (auto& t : {x,\n src_meta,\n is_combined_token_in_rank,\n rdma_channel_prefix_matrix,\n rdma_rank_prefix_sum,\n gbl_channel_prefix_matrix,\n combined_x,\n combined_rdma_head,\n combined_nvl_head}) {\n t.record_stream(comm_stream);\n if (allocate_on_comm_stream)\n t.record_stream(compute_stream);\n }\n for (auto& to : {topk_weights, combined_topk_weights, bias_0, bias_1}) {\n to.has_value() ? to->record_stream(comm_stream) : void();\n if (allocate_on_comm_stream)\n to.has_value() ? to->record_stream(compute_stream) : void();\n }\n } else {\n stream_wait(compute_stream, comm_stream);\n }\n\n // Switch back compute stream\n if (allocate_on_comm_stream)\n at::cuda::setCurrentCUDAStream(compute_stream);\n\n // Return values\n return {combined_x, combined_topk_weights, event};\n#else\n EP_HOST_ASSERT(false and \"NVSHMEM is disabled during compilation\");\n return {};\n#endif\n}\n\nvoid Buffer::clean_low_latency_buffer(int num_max_dispatch_tokens_per_rank, int hidden, int num_experts) {\n#ifndef DISABLE_NVSHMEM\n EP_HOST_ASSERT(low_latency_mode);\n\n auto layout = LowLatencyLayout(rdma_buffer_ptr, num_max_dispatch_tokens_per_rank, hidden, num_ranks, num_experts);\n auto clean_meta_0 = layout.buffers[0].clean_meta();\n auto clean_meta_1 = layout.buffers[1].clean_meta();\n\n auto check_boundary = [=](void* ptr, size_t num_bytes) {\n auto offset = reinterpret_cast(ptr) - reinterpret_cast(rdma_buffer_ptr);\n EP_HOST_ASSERT(0 <= offset and offset + num_bytes <= num_rdma_bytes);\n };\n check_boundary(clean_meta_0.first, clean_meta_0.second * sizeof(int));\n check_boundary(clean_meta_1.first, clean_meta_1.second * sizeof(int));\n\n internode_ll::clean_low_latency_buffer(clean_meta_0.first,\n clean_meta_0.second,\n clean_meta_1.first,\n clean_meta_1.second,\n rank,\n num_ranks,\n mask_buffer_ptr,\n sync_buffer_ptr,\n at::cuda::getCurrentCUDAStream());\n#else\n EP_HOST_ASSERT(false and \"NVSHMEM is disabled during compilation\");\n#endif\n}\n\nstd::tuple,\n torch::Tensor,\n torch::Tensor,\n torch::Tensor,\n std::optional,\n std::optional>>\nBuffer::low_latency_dispatch(const torch::Tensor& x,\n const torch::Tensor& topk_idx,\n const std::optional& cumulative_local_expert_recv_stats,\n const std::optional& dispatch_wait_recv_cost_stats,\n int num_max_dispatch_tokens_per_rank,\n int num_experts,\n bool use_fp8,\n bool round_scale,\n bool use_ue8m0,\n bool async,\n bool return_recv_hook) {\n#ifndef DISABLE_NVSHMEM\n EP_HOST_ASSERT(low_latency_mode);\n\n // Tensor checks\n // By default using `ptp128c` FP8 cast\n EP_HOST_ASSERT(x.dim() == 2 and x.is_contiguous() and x.scalar_type() == torch::kBFloat16);\n EP_HOST_ASSERT(x.size(1) % sizeof(int4) == 0 and x.size(1) % 128 == 0);\n EP_HOST_ASSERT(topk_idx.dim() == 2 and topk_idx.is_contiguous());\n EP_HOST_ASSERT(x.size(0) == topk_idx.size(0) and x.size(0) <= num_max_dispatch_tokens_per_rank);\n EP_HOST_ASSERT(topk_idx.scalar_type() == c10::CppTypeToScalarType::value);\n EP_HOST_ASSERT(num_experts % num_ranks == 0);\n\n // Diagnosis tensors\n if (cumulative_local_expert_recv_stats.has_value()) {\n EP_HOST_ASSERT(cumulative_local_expert_recv_stats->scalar_type() == torch::kInt);\n EP_HOST_ASSERT(cumulative_local_expert_recv_stats->dim() == 1 and cumulative_local_expert_recv_stats->is_contiguous());\n EP_HOST_ASSERT(cumulative_local_expert_recv_stats->size(0) == num_experts / num_ranks);\n }\n if (dispatch_wait_recv_cost_stats.has_value()) {\n EP_HOST_ASSERT(dispatch_wait_recv_cost_stats->scalar_type() == torch::kInt64);\n EP_HOST_ASSERT(dispatch_wait_recv_cost_stats->dim() == 1 and dispatch_wait_recv_cost_stats->is_contiguous());\n EP_HOST_ASSERT(dispatch_wait_recv_cost_stats->size(0) == num_ranks);\n }\n\n auto num_tokens = static_cast(x.size(0)), hidden = static_cast(x.size(1));\n auto num_topk = static_cast(topk_idx.size(1));\n auto num_local_experts = num_experts / num_ranks;\n\n // Buffer control\n LowLatencyLayout layout(rdma_buffer_ptr, num_max_dispatch_tokens_per_rank, hidden, num_ranks, num_experts);\n EP_HOST_ASSERT(layout.total_bytes <= num_rdma_bytes);\n auto buffer = layout.buffers[low_latency_buffer_idx];\n auto next_buffer = layout.buffers[low_latency_buffer_idx ^= 1];\n\n // Wait previous tasks to be finished\n // NOTES: the hook mode will always use the default stream\n auto compute_stream = at::cuda::getCurrentCUDAStream();\n auto launch_stream = return_recv_hook ? compute_stream : comm_stream;\n EP_HOST_ASSERT(not(async and return_recv_hook));\n if (not return_recv_hook)\n stream_wait(launch_stream, compute_stream);\n\n // Allocate packed tensors\n auto packed_recv_x = torch::empty({num_local_experts, num_ranks * num_max_dispatch_tokens_per_rank, hidden},\n x.options().dtype(use_fp8 ? torch::kFloat8_e4m3fn : torch::kBFloat16));\n auto packed_recv_src_info =\n torch::empty({num_local_experts, num_ranks * num_max_dispatch_tokens_per_rank}, torch::dtype(torch::kInt32).device(torch::kCUDA));\n auto packed_recv_layout_range = torch::empty({num_local_experts, num_ranks}, torch::dtype(torch::kInt64).device(torch::kCUDA));\n auto packed_recv_count = torch::empty({num_local_experts}, torch::dtype(torch::kInt32).device(torch::kCUDA));\n\n // Allocate column-majored scales\n auto packed_recv_x_scales = std::optional();\n void* packed_recv_x_scales_ptr = nullptr;\n EP_HOST_ASSERT((num_ranks * num_max_dispatch_tokens_per_rank) % 4 == 0 and \"TMA requires the number of tokens to be multiple of 4\");\n\n if (use_fp8) {\n // TODO: support unaligned cases\n EP_HOST_ASSERT(hidden % 512 == 0);\n if (not use_ue8m0) {\n packed_recv_x_scales = torch::empty({num_local_experts, hidden / 128, num_ranks * num_max_dispatch_tokens_per_rank},\n torch::dtype(torch::kFloat32).device(torch::kCUDA));\n } else {\n EP_HOST_ASSERT(round_scale);\n packed_recv_x_scales = torch::empty({num_local_experts, hidden / 512, num_ranks * num_max_dispatch_tokens_per_rank},\n torch::dtype(torch::kInt).device(torch::kCUDA));\n }\n packed_recv_x_scales = torch::transpose(packed_recv_x_scales.value(), 1, 2);\n packed_recv_x_scales_ptr = packed_recv_x_scales->data_ptr();\n }\n\n // Kernel launch\n auto next_clean_meta = next_buffer.clean_meta();\n auto launcher = [=](int phases) {\n internode_ll::dispatch(\n packed_recv_x.data_ptr(),\n packed_recv_x_scales_ptr,\n packed_recv_src_info.data_ptr(),\n packed_recv_layout_range.data_ptr(),\n packed_recv_count.data_ptr(),\n mask_buffer_ptr,\n cumulative_local_expert_recv_stats.has_value() ? cumulative_local_expert_recv_stats->data_ptr() : nullptr,\n dispatch_wait_recv_cost_stats.has_value() ? dispatch_wait_recv_cost_stats->data_ptr() : nullptr,\n buffer.dispatch_rdma_recv_data_buffer,\n buffer.dispatch_rdma_recv_count_buffer,\n buffer.dispatch_rdma_send_buffer,\n x.data_ptr(),\n topk_idx.data_ptr(),\n next_clean_meta.first,\n next_clean_meta.second,\n num_tokens,\n hidden,\n num_max_dispatch_tokens_per_rank,\n num_topk,\n num_experts,\n rank,\n num_ranks,\n use_fp8,\n round_scale,\n use_ue8m0,\n workspace,\n num_device_sms,\n launch_stream,\n phases);\n };\n launcher(return_recv_hook ? LOW_LATENCY_SEND_PHASE : (LOW_LATENCY_SEND_PHASE | LOW_LATENCY_RECV_PHASE));\n\n // Wait streams\n std::optional event;\n if (async) {\n // NOTES: we must ensure the all tensors will not be deallocated before the stream-wait happens,\n // so in Python API, we must wrap all tensors into the event handle.\n event = EventHandle(launch_stream);\n } else if (not return_recv_hook) {\n stream_wait(compute_stream, launch_stream);\n }\n\n // Receiver callback\n std::optional> recv_hook = std::nullopt;\n if (return_recv_hook)\n recv_hook = [=]() { launcher(LOW_LATENCY_RECV_PHASE); };\n\n // Return values\n return {packed_recv_x, packed_recv_x_scales, packed_recv_count, packed_recv_src_info, packed_recv_layout_range, event, recv_hook};\n#else\n EP_HOST_ASSERT(false and \"NVSHMEM is disabled during compilation\");\n return {};\n#endif\n}\n\nstd::tuple, std::optional>> Buffer::low_latency_combine(\n const torch::Tensor& x,\n const torch::Tensor& topk_idx,\n const torch::Tensor& topk_weights,\n const torch::Tensor& src_info,\n const torch::Tensor& layout_range,\n const std::optional& combine_wait_recv_cost_stats,\n int num_max_dispatch_tokens_per_rank,\n int num_experts,\n bool use_logfmt,\n bool zero_copy,\n bool async,\n bool return_recv_hook,\n const std::optional& out) {\n#ifndef DISABLE_NVSHMEM\n EP_HOST_ASSERT(low_latency_mode);\n\n // Tensor checks\n EP_HOST_ASSERT(x.dim() == 3 and x.is_contiguous() and x.scalar_type() == torch::kBFloat16);\n EP_HOST_ASSERT(x.size(0) == num_experts / num_ranks);\n EP_HOST_ASSERT(x.size(1) == num_ranks * num_max_dispatch_tokens_per_rank);\n EP_HOST_ASSERT(x.size(2) % sizeof(int4) == 0 and x.size(2) % 128 == 0);\n EP_HOST_ASSERT(topk_idx.dim() == 2 and topk_idx.is_contiguous());\n EP_HOST_ASSERT(topk_idx.size(0) == topk_weights.size(0) and topk_idx.size(1) == topk_weights.size(1));\n EP_HOST_ASSERT(topk_idx.scalar_type() == c10::CppTypeToScalarType::value);\n EP_HOST_ASSERT(topk_weights.dim() == 2 and topk_weights.is_contiguous());\n EP_HOST_ASSERT(topk_weights.size(0) <= num_max_dispatch_tokens_per_rank);\n EP_HOST_ASSERT(topk_weights.scalar_type() == torch::kFloat32);\n EP_HOST_ASSERT(src_info.dim() == 2 and src_info.is_contiguous());\n EP_HOST_ASSERT(src_info.scalar_type() == torch::kInt32 and x.size(0) == src_info.size(0));\n EP_HOST_ASSERT(layout_range.dim() == 2 and layout_range.is_contiguous());\n EP_HOST_ASSERT(layout_range.scalar_type() == torch::kInt64);\n EP_HOST_ASSERT(layout_range.size(0) == num_experts / num_ranks and layout_range.size(1) == num_ranks);\n\n if (combine_wait_recv_cost_stats.has_value()) {\n EP_HOST_ASSERT(combine_wait_recv_cost_stats->scalar_type() == torch::kInt64);\n EP_HOST_ASSERT(combine_wait_recv_cost_stats->dim() == 1 and combine_wait_recv_cost_stats->is_contiguous());\n EP_HOST_ASSERT(combine_wait_recv_cost_stats->size(0) == num_ranks);\n }\n\n auto hidden = static_cast(x.size(2));\n auto num_topk = static_cast(topk_weights.size(1));\n auto num_combined_tokens = static_cast(topk_weights.size(0));\n\n // Buffer control\n LowLatencyLayout layout(rdma_buffer_ptr, num_max_dispatch_tokens_per_rank, hidden, num_ranks, num_experts);\n EP_HOST_ASSERT(layout.total_bytes <= num_rdma_bytes);\n auto buffer = layout.buffers[low_latency_buffer_idx];\n auto next_buffer = layout.buffers[low_latency_buffer_idx ^= 1];\n\n // Wait previous tasks to be finished\n // NOTES: the hook mode will always use the default stream\n auto compute_stream = at::cuda::getCurrentCUDAStream();\n auto launch_stream = return_recv_hook ? compute_stream : comm_stream;\n EP_HOST_ASSERT(not(async and return_recv_hook));\n if (not return_recv_hook)\n stream_wait(launch_stream, compute_stream);\n\n // Allocate output tensor\n torch::Tensor combined_x;\n if (out.has_value()) {\n EP_HOST_ASSERT(out->dim() == 2 and out->is_contiguous());\n EP_HOST_ASSERT(out->size(0) == num_combined_tokens and out->size(1) == hidden);\n EP_HOST_ASSERT(out->scalar_type() == x.scalar_type());\n combined_x = out.value();\n } else {\n combined_x = torch::empty({num_combined_tokens, hidden}, x.options());\n }\n\n // Kernel launch\n auto next_clean_meta = next_buffer.clean_meta();\n auto launcher = [=](int phases) {\n internode_ll::combine(combined_x.data_ptr(),\n buffer.combine_rdma_recv_data_buffer,\n buffer.combine_rdma_recv_flag_buffer,\n buffer.combine_rdma_send_buffer,\n x.data_ptr(),\n topk_idx.data_ptr(),\n topk_weights.data_ptr(),\n src_info.data_ptr(),\n layout_range.data_ptr(),\n mask_buffer_ptr,\n combine_wait_recv_cost_stats.has_value() ? combine_wait_recv_cost_stats->data_ptr() : nullptr,\n next_clean_meta.first,\n next_clean_meta.second,\n num_combined_tokens,\n hidden,\n num_max_dispatch_tokens_per_rank,\n num_topk,\n num_experts,\n rank,\n num_ranks,\n use_logfmt,\n workspace,\n num_device_sms,\n launch_stream,\n phases,\n zero_copy);\n };\n launcher(return_recv_hook ? LOW_LATENCY_SEND_PHASE : (LOW_LATENCY_SEND_PHASE | LOW_LATENCY_RECV_PHASE));\n\n // Wait streams\n std::optional event;\n if (async) {\n // NOTES: we must ensure the all tensors will not be deallocated before the stream-wait happens,\n // so in Python API, we must wrap all tensors into the event handle.\n event = EventHandle(launch_stream);\n } else if (not return_recv_hook) {\n stream_wait(compute_stream, launch_stream);\n }\n\n // Receiver callback\n std::optional> recv_hook = std::nullopt;\n if (return_recv_hook)\n recv_hook = [=]() { launcher(LOW_LATENCY_RECV_PHASE); };\n\n // Return values\n return {combined_x, event, recv_hook};\n#else\n EP_HOST_ASSERT(false and \"NVSHMEM is disabled during compilation\");\n return {};\n#endif\n}\n\ntorch::Tensor Buffer::get_next_low_latency_combine_buffer(int num_max_dispatch_tokens_per_rank, int hidden, int num_experts) const {\n#ifndef DISABLE_NVSHMEM\n LowLatencyLayout layout(rdma_buffer_ptr, num_max_dispatch_tokens_per_rank, hidden, num_ranks, num_experts);\n\n auto buffer = layout.buffers[low_latency_buffer_idx];\n auto dtype = torch::kBFloat16;\n auto num_msg_elems = static_cast(buffer.num_bytes_per_combine_msg / elementSize(torch::kBFloat16));\n\n EP_HOST_ASSERT(buffer.num_bytes_per_combine_msg % elementSize(torch::kBFloat16) == 0);\n return torch::from_blob(buffer.combine_rdma_send_buffer_data_start,\n {num_experts / num_ranks, num_ranks * num_max_dispatch_tokens_per_rank, hidden},\n {num_ranks * num_max_dispatch_tokens_per_rank * num_msg_elems, num_msg_elems, 1},\n torch::TensorOptions().dtype(dtype).device(torch::kCUDA));\n#else\n EP_HOST_ASSERT(false and \"NVSHMEM is disabled during compilation\");\n return {};\n#endif\n}\n\nbool is_sm90_compiled() {\n#ifndef DISABLE_SM90_FEATURES\n return true;\n#else\n return false;\n#endif\n}\n\nvoid Buffer::low_latency_update_mask_buffer(int rank_to_mask, bool mask) {\n EP_HOST_ASSERT(mask_buffer_ptr != nullptr and \"Shrink mode must be enabled\");\n EP_HOST_ASSERT(rank_to_mask >= 0 and rank_to_mask < num_ranks);\n internode_ll::update_mask_buffer(mask_buffer_ptr, rank_to_mask, mask, at::cuda::getCurrentCUDAStream());\n}\n\nvoid Buffer::low_latency_query_mask_buffer(const torch::Tensor& mask_status) {\n EP_HOST_ASSERT(mask_buffer_ptr != nullptr and \"Shrink mode must be enabled\");\n EP_HOST_ASSERT(mask_status.numel() == num_ranks && mask_status.scalar_type() == torch::kInt32);\n\n internode_ll::query_mask_buffer(\n mask_buffer_ptr, num_ranks, reinterpret_cast(mask_status.data_ptr()), at::cuda::getCurrentCUDAStream());\n}\n\nvoid Buffer::low_latency_clean_mask_buffer() {\n EP_HOST_ASSERT(mask_buffer_ptr != nullptr and \"Shrink mode must be enabled\");\n internode_ll::clean_mask_buffer(mask_buffer_ptr, num_ranks, at::cuda::getCurrentCUDAStream());\n}\n\n} // namespace deep_ep\n\nPYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {\n m.doc() = \"DeepEP: an efficient expert-parallel communication library\";\n\n pybind11::class_(m, \"Config\")\n .def(pybind11::init(),\n py::arg(\"num_sms\") = 20,\n py::arg(\"num_max_nvl_chunked_send_tokens\") = 6,\n py::arg(\"num_max_nvl_chunked_recv_tokens\") = 256,\n py::arg(\"num_max_rdma_chunked_send_tokens\") = 6,\n py::arg(\"num_max_rdma_chunked_recv_tokens\") = 256)\n .def(\"get_nvl_buffer_size_hint\", &deep_ep::Config::get_nvl_buffer_size_hint)\n .def(\"get_rdma_buffer_size_hint\", &deep_ep::Config::get_rdma_buffer_size_hint);\n m.def(\"get_low_latency_rdma_size_hint\", &deep_ep::get_low_latency_rdma_size_hint);\n\n pybind11::class_(m, \"EventHandle\")\n .def(pybind11::init<>())\n .def(\"current_stream_wait\", &deep_ep::EventHandle::current_stream_wait);\n\n pybind11::class_(m, \"Buffer\")\n .def(pybind11::init())\n .def(\"is_available\", &deep_ep::Buffer::is_available)\n .def(\"get_num_rdma_ranks\", &deep_ep::Buffer::get_num_rdma_ranks)\n .def(\"get_rdma_rank\", &deep_ep::Buffer::get_rdma_rank)\n .def(\"get_root_rdma_rank\", &deep_ep::Buffer::get_root_rdma_rank)\n .def(\"get_local_device_id\", &deep_ep::Buffer::get_local_device_id)\n .def(\"get_local_ipc_handle\", &deep_ep::Buffer::get_local_ipc_handle)\n .def(\"get_local_nvshmem_unique_id\", &deep_ep::Buffer::get_local_nvshmem_unique_id)\n .def(\"get_local_buffer_tensor\", &deep_ep::Buffer::get_local_buffer_tensor)\n .def(\"get_comm_stream\", &deep_ep::Buffer::get_comm_stream)\n .def(\"sync\", &deep_ep::Buffer::sync)\n .def(\"destroy\", &deep_ep::Buffer::destroy)\n .def(\"get_dispatch_layout\", &deep_ep::Buffer::get_dispatch_layout)\n .def(\"intranode_dispatch\", &deep_ep::Buffer::intranode_dispatch)\n .def(\"intranode_combine\", &deep_ep::Buffer::intranode_combine)\n .def(\"internode_dispatch\", &deep_ep::Buffer::internode_dispatch)\n .def(\"internode_combine\", &deep_ep::Buffer::internode_combine)\n .def(\"clean_low_latency_buffer\", &deep_ep::Buffer::clean_low_latency_buffer)\n .def(\"low_latency_dispatch\", &deep_ep::Buffer::low_latency_dispatch)\n .def(\"low_latency_combine\", &deep_ep::Buffer::low_latency_combine)\n .def(\"low_latency_update_mask_buffer\", &deep_ep::Buffer::low_latency_update_mask_buffer)\n .def(\"low_latency_query_mask_buffer\", &deep_ep::Buffer::low_latency_query_mask_buffer)\n .def(\"low_latency_clean_mask_buffer\", &deep_ep::Buffer::low_latency_clean_mask_buffer)\n .def(\"get_next_low_latency_combine_buffer\", &deep_ep::Buffer::get_next_low_latency_combine_buffer);\n\n m.def(\"is_sm90_compiled\", deep_ep::is_sm90_compiled);\n m.attr(\"topk_idx_t\") =\n py::reinterpret_borrow((PyObject*)torch::getTHPDtype(c10::CppTypeToScalarType::value));\n}\n" }, { "path": "csrc/deep_ep.hpp", "content": "#pragma once\n\n// Forcibly disable NDEBUG\n#ifdef NDEBUG\n#undef NDEBUG\n#endif\n\n#include \n#include \n#include \n\n#include \n#include \n\n#include \"config.hpp\"\n#include \"event.hpp\"\n#include \"kernels/configs.cuh\"\n#include \"kernels/exception.cuh\"\n\n#ifndef TORCH_EXTENSION_NAME\n#define TORCH_EXTENSION_NAME deep_ep_cpp\n#endif\n\nnamespace shared_memory {\n\nunion MemHandleInner {\n cudaIpcMemHandle_t cuda_ipc_mem_handle;\n CUmemFabricHandle cu_mem_fabric_handle;\n};\n\nstruct MemHandle {\n MemHandleInner inner;\n size_t size;\n};\n\nconstexpr size_t HANDLE_SIZE = sizeof(MemHandle);\n\nclass SharedMemoryAllocator {\npublic:\n SharedMemoryAllocator(bool use_fabric);\n void malloc(void** ptr, size_t size);\n void free(void* ptr);\n void get_mem_handle(MemHandle* mem_handle, void* ptr);\n void open_mem_handle(void** ptr, MemHandle* mem_handle);\n void close_mem_handle(void* ptr);\n\nprivate:\n bool use_fabric;\n};\n} // namespace shared_memory\n\nnamespace deep_ep {\n\nstruct Buffer {\n EP_STATIC_ASSERT(NUM_MAX_NVL_PEERS == 8, \"The number of maximum NVLink peers must be 8\");\n\nprivate:\n // Low-latency mode buffer\n int low_latency_buffer_idx = 0;\n bool low_latency_mode = false;\n\n // NVLink Buffer\n int64_t num_nvl_bytes;\n void* buffer_ptrs[NUM_MAX_NVL_PEERS] = {nullptr};\n void** buffer_ptrs_gpu = nullptr;\n\n // NVSHMEM Buffer\n int64_t num_rdma_bytes;\n void* rdma_buffer_ptr = nullptr;\n\n // Shrink mode buffer\n bool enable_shrink = false;\n int* mask_buffer_ptr = nullptr;\n int* sync_buffer_ptr = nullptr;\n\n // Device info and communication\n int device_id;\n int num_device_sms;\n int rank, rdma_rank, nvl_rank;\n int num_ranks, num_rdma_ranks, num_nvl_ranks;\n shared_memory::MemHandle ipc_handles[NUM_MAX_NVL_PEERS];\n\n // Stream for communication\n at::cuda::CUDAStream comm_stream;\n\n // After IPC/NVSHMEM synchronization, this flag will be true\n bool available = false;\n\n // Whether explicit `destroy()` is required.\n bool explicitly_destroy;\n // After `destroy()` be called, this flag will be true\n bool destroyed = false;\n\n // Barrier signals\n int* barrier_signal_ptrs[NUM_MAX_NVL_PEERS] = {nullptr};\n int** barrier_signal_ptrs_gpu = nullptr;\n\n // Workspace\n void* workspace = nullptr;\n\n // Host-side MoE info\n volatile int* moe_recv_counter = nullptr;\n int* moe_recv_counter_mapped = nullptr;\n\n // Host-side expert-level MoE info\n volatile int* moe_recv_expert_counter = nullptr;\n int* moe_recv_expert_counter_mapped = nullptr;\n\n // Host-side RDMA-level MoE info\n volatile int* moe_recv_rdma_counter = nullptr;\n int* moe_recv_rdma_counter_mapped = nullptr;\n\n shared_memory::SharedMemoryAllocator shared_memory_allocator;\n\npublic:\n Buffer(int rank,\n int num_ranks,\n int64_t num_nvl_bytes,\n int64_t num_rdma_bytes,\n bool low_latency_mode,\n bool explicitly_destroy,\n bool enable_shrink,\n bool use_fabric);\n\n ~Buffer() noexcept(false);\n\n bool is_available() const;\n\n bool is_internode_available() const;\n\n int get_num_rdma_ranks() const;\n\n int get_rdma_rank() const;\n\n int get_root_rdma_rank(bool global) const;\n\n int get_local_device_id() const;\n\n pybind11::bytearray get_local_ipc_handle() const;\n\n pybind11::bytearray get_local_nvshmem_unique_id() const;\n\n torch::Tensor get_local_buffer_tensor(const pybind11::object& dtype, int64_t offset, bool use_rdma_buffer) const;\n\n torch::Stream get_comm_stream() const;\n\n void sync(const std::vector& device_ids,\n const std::vector>& all_gathered_handles,\n const std::optional& root_unique_id_opt);\n\n void destroy();\n\n std::tuple, torch::Tensor, torch::Tensor, std::optional> get_dispatch_layout(\n const torch::Tensor& topk_idx,\n int num_experts,\n std::optional& previous_event,\n bool async,\n bool allocate_on_comm_stream);\n\n std::tuple,\n std::optional,\n std::optional,\n std::vector,\n torch::Tensor,\n torch::Tensor,\n torch::Tensor,\n torch::Tensor,\n torch::Tensor,\n std::optional>\n intranode_dispatch(const torch::Tensor& x,\n const std::optional& x_scales,\n const std::optional& topk_idx,\n const std::optional& topk_weights,\n const std::optional& num_tokens_per_rank,\n const torch::Tensor& is_token_in_rank,\n const std::optional& num_tokens_per_expert,\n int cached_num_recv_tokens,\n const std::optional& cached_rank_prefix_matrix,\n const std::optional& cached_channel_prefix_matrix,\n int expert_alignment,\n int num_worst_tokens,\n const Config& config,\n std::optional& previous_event,\n bool async,\n bool allocate_on_comm_stream);\n\n std::tuple, std::optional> intranode_combine(\n const torch::Tensor& x,\n const std::optional& topk_weights,\n const std::optional& bias_0,\n const std::optional& bias_1,\n const torch::Tensor& src_idx,\n const torch::Tensor& rank_prefix_matrix,\n const torch::Tensor& channel_prefix_matrix,\n const torch::Tensor& send_head,\n const Config& config,\n std::optional& previous_event,\n bool async,\n bool allocate_on_comm_stream);\n\n std::tuple,\n std::optional,\n std::optional,\n std::vector,\n torch::Tensor,\n torch::Tensor,\n std::optional,\n torch::Tensor,\n std::optional,\n torch::Tensor,\n std::optional,\n std::optional,\n std::optional,\n std::optional>\n internode_dispatch(const torch::Tensor& x,\n const std::optional& x_scales,\n const std::optional& topk_idx,\n const std::optional& topk_weights,\n const std::optional& num_tokens_per_rank,\n const std::optional& num_tokens_per_rdma_rank,\n const torch::Tensor& is_token_in_rank,\n const std::optional& num_tokens_per_expert,\n int cached_num_recv_tokens,\n int cached_num_rdma_recv_tokens,\n const std::optional& cached_rdma_channel_prefix_matrix,\n const std::optional& cached_recv_rdma_rank_prefix_sum,\n const std::optional& cached_gbl_channel_prefix_matrix,\n const std::optional& cached_recv_gbl_rank_prefix_sum,\n int expert_alignment,\n int num_worst_tokens,\n const Config& config,\n std::optional& previous_event,\n bool async,\n bool allocate_on_comm_stream);\n\n std::tuple, std::optional> internode_combine(\n const torch::Tensor& x,\n const std::optional& topk_weights,\n const std::optional& bias_0,\n const std::optional& bias_1,\n const torch::Tensor& src_meta,\n const torch::Tensor& is_combined_token_in_rank,\n const torch::Tensor& rdma_channel_prefix_matrix,\n const torch::Tensor& rdma_rank_prefix_sum,\n const torch::Tensor& gbl_channel_prefix_matrix,\n const torch::Tensor& combined_rdma_head,\n const torch::Tensor& combined_nvl_head,\n const Config& config,\n std::optional& previous_event,\n bool async,\n bool allocate_on_comm_stream);\n\n void clean_low_latency_buffer(int num_max_dispatch_tokens_per_rank, int hidden, int num_experts);\n\n std::tuple,\n torch::Tensor,\n torch::Tensor,\n torch::Tensor,\n std::optional,\n std::optional>>\n low_latency_dispatch(const torch::Tensor& x,\n const torch::Tensor& topk_idx,\n const std::optional& cumulative_local_expert_recv_stats,\n const std::optional& dispatch_wait_recv_cost_stats,\n int num_max_dispatch_tokens_per_rank,\n int num_experts,\n bool use_fp8,\n bool round_scale,\n bool use_ue8m0,\n bool async,\n bool return_recv_hook);\n\n std::tuple, std::optional>> low_latency_combine(\n const torch::Tensor& x,\n const torch::Tensor& topk_idx,\n const torch::Tensor& topk_weights,\n const torch::Tensor& src_info,\n const torch::Tensor& layout_range,\n const std::optional& combine_wait_recv_cost_stats,\n int num_max_dispatch_tokens_per_rank,\n int num_experts,\n bool use_logfmt,\n bool zero_copy,\n bool async,\n bool return_recv_hook,\n const std::optional& out = std::nullopt);\n\n torch::Tensor get_next_low_latency_combine_buffer(int num_max_dispatch_tokens_per_rank, int hidden, int num_experts) const;\n\n void low_latency_update_mask_buffer(int rank_to_mask, bool mask);\n\n void low_latency_query_mask_buffer(const torch::Tensor& mask_status);\n\n void low_latency_clean_mask_buffer();\n};\n\n} // namespace deep_ep\n" }, { "path": "csrc/event.hpp", "content": "#include \n\n#include \n\n#include \"kernels/exception.cuh\"\n\nnamespace deep_ep {\n\nstruct EventHandle {\n std::shared_ptr event;\n\n EventHandle() {\n event = std::make_shared(torch::kCUDA);\n event->record(at::cuda::getCurrentCUDAStream());\n }\n\n explicit EventHandle(const at::cuda::CUDAStream& stream) {\n event = std::make_shared(torch::kCUDA);\n event->record(stream);\n }\n\n EventHandle(const EventHandle& other) = default;\n\n void current_stream_wait() const { at::cuda::getCurrentCUDAStream().unwrap().wait(*event); }\n};\n\ntorch::Event create_event(const at::cuda::CUDAStream& s) {\n auto event = torch::Event(torch::kCUDA);\n event.record(s);\n return event;\n}\n\nvoid stream_wait(const at::cuda::CUDAStream& s_0, const at::cuda::CUDAStream& s_1) {\n EP_HOST_ASSERT(s_0.id() != s_1.id());\n s_0.unwrap().wait(create_event(s_1));\n}\n\nvoid stream_wait(const at::cuda::CUDAStream& s, const EventHandle& event) {\n s.unwrap().wait(*event.event);\n}\n\n} // namespace deep_ep\n" }, { "path": "csrc/kernels/CMakeLists.txt", "content": "function(add_deep_ep_library target_name source_file)\n add_library(${target_name} STATIC ${source_file})\n set_target_properties(${target_name} PROPERTIES\n POSITION_INDEPENDENT_CODE ON\n CXX_STANDARD_REQUIRED ON\n CUDA_STANDARD_REQUIRED ON\n CXX_STANDARD 17\n CUDA_STANDARD 17\n CUDA_SEPARABLE_COMPILATION ON\n )\n target_link_libraries(${target_name} PUBLIC nvshmem cudart cudadevrt mlx5)\nendfunction()\n\nadd_deep_ep_library(runtime_cuda runtime.cu)\nadd_deep_ep_library(layout_cuda layout.cu)\nadd_deep_ep_library(intranode_cuda intranode.cu)\nadd_deep_ep_library(internode_cuda internode.cu)\nadd_deep_ep_library(internode_ll_cuda internode_ll.cu)\n\n# Later, we should link all libraries in `EP_CUDA_LIBRARIES`\nset(EP_CUDA_LIBRARIES runtime_cuda layout_cuda intranode_cuda internode_cuda internode_ll_cuda PARENT_SCOPE)\n" }, { "path": "csrc/kernels/api.cuh", "content": "#pragma once\n\n#include \n\n#include \"configs.cuh\"\n\nnamespace deep_ep {\n\n// Intranode runtime\nnamespace intranode {\n\nvoid barrier(int** barrier_signal_ptrs, int rank, int num_ranks, cudaStream_t stream);\n\n} // namespace intranode\n\n// Internode runtime\nnamespace internode {\n\nstd::vector get_unique_id();\n\nint init(const std::vector& root_unique_id_val, int rank, int num_ranks, bool low_latency_mode);\n\nvoid* alloc(size_t size, size_t alignment);\n\nvoid free(void* ptr);\n\nvoid barrier();\n\nvoid finalize();\n\n} // namespace internode\n\n// Layout kernels\nnamespace layout {\n\nvoid get_dispatch_layout(const topk_idx_t* topk_idx,\n int* num_tokens_per_rank,\n int* num_tokens_per_rdma_rank,\n int* num_tokens_per_expert,\n bool* is_token_in_rank,\n int num_tokens,\n int num_topk,\n int num_ranks,\n int num_experts,\n cudaStream_t stream);\n\n} // namespace layout\n\n// Intranode kernels\nnamespace intranode {\n\nvoid notify_dispatch(const int* num_tokens_per_rank,\n int* moe_recv_counter_mapped,\n int num_ranks,\n const int* num_tokens_per_expert,\n int* moe_recv_expert_counter_mapped,\n int num_experts,\n int num_tokens,\n const bool* is_token_in_rank,\n int* channel_prefix_matrix,\n int* rank_prefix_matrix_copy,\n int num_memset_int,\n int expert_alignment,\n void** buffer_ptrs,\n int** barrier_signal_ptrs,\n int rank,\n cudaStream_t stream,\n int num_sms);\n\nvoid cached_notify_dispatch(const int* rank_prefix_matrix,\n int num_memset_int,\n void** buffer_ptrs,\n int** barrier_signal_ptrs,\n int rank,\n int num_ranks,\n cudaStream_t stream);\n\nvoid dispatch(void* recv_x,\n float* recv_x_scales,\n int* recv_src_idx,\n topk_idx_t* recv_topk_idx,\n float* recv_topk_weights,\n int* recv_channel_offset,\n int* send_head,\n const void* x,\n const float* x_scales,\n const topk_idx_t* topk_idx,\n const float* topk_weights,\n const bool* is_token_in_rank,\n const int* channel_prefix_matrix,\n int num_tokens,\n int num_worst_tokens,\n int hidden_int4,\n int num_topk,\n int num_experts,\n int num_scales,\n int scale_token_stride,\n int scale_hidden_stride,\n void** buffer_ptrs,\n int rank,\n int num_ranks,\n cudaStream_t stream,\n int num_sms,\n int num_max_send_tokens,\n int num_recv_buffer_tokens);\n\nvoid cached_notify_combine(void** buffer_ptrs,\n int* send_head,\n int num_channels,\n int num_recv_tokens,\n int num_memset_int,\n int** barrier_signal_ptrs,\n int rank,\n int num_ranks,\n cudaStream_t stream);\n\nvoid combine(cudaDataType_t type,\n void* recv_x,\n float* recv_topk_weights,\n const void* x,\n const float* topk_weights,\n const void* bias_0,\n const void* bias_1,\n const int* src_idx,\n const int* rank_prefix_matrix,\n const int* channel_prefix_matrix,\n int* send_head,\n int num_tokens,\n int num_recv_tokens,\n int hidden,\n int num_topk,\n void** buffer_ptrs,\n int rank,\n int num_ranks,\n cudaStream_t stream,\n int num_sms,\n int num_max_send_tokens,\n int num_recv_buffer_tokens);\n\n} // namespace intranode\n\n// Internode kernels\nnamespace internode {\n\nint get_source_meta_bytes();\n\nvoid notify_dispatch(const int* num_tokens_per_rank,\n int* moe_recv_counter_mapped,\n int num_ranks,\n const int* num_tokens_per_rdma_rank,\n int* moe_recv_rdma_counter_mapped,\n const int* num_tokens_per_expert,\n int* moe_recv_expert_counter_mapped,\n int num_experts,\n const bool* is_token_in_rank,\n int num_tokens,\n int num_worst_tokens,\n int num_channels,\n int hidden_int4,\n int num_scales,\n int num_topk,\n int expert_alignment,\n int* rdma_channel_prefix_matrix,\n int* recv_rdma_rank_prefix_sum,\n int* gbl_channel_prefix_matrix,\n int* recv_gbl_rank_prefix_sum,\n void* rdma_buffer_ptr,\n int num_max_rdma_chunked_recv_tokens,\n void** buffer_ptrs,\n int num_max_nvl_chunked_recv_tokens,\n int** barrier_signal_ptrs,\n int rank,\n cudaStream_t stream,\n int64_t num_rdma_bytes,\n int64_t num_nvl_bytes,\n bool low_latency_mode);\n\nvoid dispatch(void* recv_x,\n float* recv_x_scales,\n topk_idx_t* recv_topk_idx,\n float* recv_topk_weights,\n void* recv_src_meta,\n const void* x,\n const float* x_scales,\n const topk_idx_t* topk_idx,\n const float* topk_weights,\n int* send_rdma_head,\n int* send_nvl_head,\n int* recv_rdma_channel_prefix_matrix,\n int* recv_gbl_channel_prefix_matrix,\n const int* rdma_channel_prefix_matrix,\n const int* recv_rdma_rank_prefix_sum,\n const int* gbl_channel_prefix_matrix,\n const int* recv_gbl_rank_prefix_sum,\n const bool* is_token_in_rank,\n int num_tokens,\n int num_worst_tokens,\n int hidden_int4,\n int num_scales,\n int num_topk,\n int num_experts,\n int scale_token_stride,\n int scale_hidden_stride,\n void* rdma_buffer_ptr,\n int num_max_rdma_chunked_send_tokens,\n int num_max_rdma_chunked_recv_tokens,\n void** buffer_ptrs,\n int num_max_nvl_chunked_send_tokens,\n int num_max_nvl_chunked_recv_tokens,\n int rank,\n int num_ranks,\n bool is_cached_dispatch,\n cudaStream_t stream,\n int num_channels,\n bool low_latency_mode);\n\nvoid cached_notify(int hidden_int4,\n int num_scales,\n int num_topk_idx,\n int num_topk_weights,\n int num_ranks,\n int num_channels,\n int num_combined_tokens,\n int* combined_rdma_head,\n const int* rdma_channel_prefix_matrix,\n const int* rdma_rank_prefix_sum,\n int* combined_nvl_head,\n void* rdma_buffer_ptr,\n int num_max_rdma_chunked_recv_tokens,\n void** buffer_ptrs,\n int num_max_nvl_chunked_recv_tokens,\n int** barrier_signal_ptrs,\n int rank,\n cudaStream_t stream,\n int64_t num_rdma_bytes,\n int64_t num_nvl_bytes,\n bool is_cached_dispatch,\n bool low_latency_mode);\n\nvoid combine(cudaDataType_t type,\n void* combined_x,\n float* combined_topk_weights,\n const bool* is_combined_token_in_rank,\n const void* x,\n const float* topk_weights,\n const void* bias_0,\n const void* bias_1,\n const int* combined_rdma_head,\n const int* combined_nvl_head,\n const void* src_meta,\n const int* rdma_channel_prefix_matrix,\n const int* rdma_rank_prefix_sum,\n const int* gbl_channel_prefix_matrix,\n int num_tokens,\n int num_combined_tokens,\n int hidden,\n int num_topk,\n void* rdma_buffer_ptr,\n int num_max_rdma_chunked_send_tokens,\n int num_max_rdma_chunked_recv_tokens,\n void** buffer_ptrs,\n int num_max_nvl_chunked_send_tokens,\n int num_max_nvl_chunked_recv_tokens,\n int rank,\n int num_ranks,\n cudaStream_t stream,\n int num_channels,\n bool low_latency_mode);\n\n} // namespace internode\n\n// Internode low-latency kernels\nnamespace internode_ll {\n\nvoid clean_low_latency_buffer(int* clean_0,\n int num_clean_int_0,\n int* clean_1,\n int num_clean_int_1,\n int rank,\n int num_ranks,\n int* mask_buffer,\n int* sync_buffer,\n cudaStream_t stream);\n\nvoid dispatch(void* packed_recv_x,\n void* packed_recv_x_scales,\n int* packed_recv_src_info,\n int64_t* packed_recv_layout_range,\n int* packed_recv_count,\n int* mask_buffer,\n int* cumulative_local_expert_recv_stats,\n int64_t* dispatch_wait_recv_cost_stats,\n void* rdma_recv_x,\n int* rdma_recv_count,\n void* rdma_x,\n const void* x,\n const topk_idx_t* topk_idx,\n int* next_clean,\n int num_next_clean_int,\n int num_tokens,\n int hidden,\n int num_max_dispatch_tokens_per_rank,\n int num_topk,\n int num_experts,\n int rank,\n int num_ranks,\n bool use_fp8,\n bool round_scale,\n bool use_ue8m0,\n void* workspace,\n int num_device_sms,\n cudaStream_t stream,\n int phases);\n\nvoid combine(void* combined_x,\n void* rdma_recv_x,\n int* rdma_recv_flag,\n void* rdma_send_x,\n const void* x,\n const topk_idx_t* topk_idx,\n const float* topk_weights,\n const int* src_info,\n const int64_t* layout_range,\n int* mask_buffer,\n int64_t* combine_wait_recv_cost_stats,\n int* next_clean,\n int num_next_clean_int,\n int num_combined_tokens,\n int hidden,\n int num_max_dispatch_tokens_per_rank,\n int num_topk,\n int num_experts,\n int rank,\n int num_ranks,\n bool use_logfmt,\n void* workspace,\n int num_device_sms,\n cudaStream_t stream,\n int phases,\n bool zero_copy);\n\nvoid query_mask_buffer(int* mask_buffer_ptr, int num_ranks, int* output_mask_tensor, cudaStream_t stream);\n\nvoid update_mask_buffer(int* mask_buffer_ptr, int rank_to_mask, bool mask, cudaStream_t stream);\n\nvoid clean_mask_buffer(int* mask_buffer_ptr, int num_ranks, cudaStream_t stream);\n\n} // namespace internode_ll\n\n} // namespace deep_ep\n" }, { "path": "csrc/kernels/buffer.cuh", "content": "#pragma once\n\n#include \"configs.cuh\"\n#include \"exception.cuh\"\n\nnamespace deep_ep {\n\ntemplate \nstruct Buffer {\nprivate:\n uint8_t* ptr;\n\npublic:\n int64_t total_bytes;\n\n __device__ __forceinline__ Buffer() : ptr(nullptr), total_bytes(0) {}\n\n __device__ __forceinline__ Buffer(void*& gbl_ptr, int num_elems, int offset = 0) {\n total_bytes = num_elems * sizeof(dtype_t);\n ptr = static_cast(gbl_ptr) + offset * sizeof(dtype_t);\n gbl_ptr = static_cast(gbl_ptr) + total_bytes;\n }\n\n __device__ __forceinline__ Buffer advance_also(void*& gbl_ptr) {\n gbl_ptr = static_cast(gbl_ptr) + total_bytes;\n return *this;\n }\n\n __device__ __forceinline__ dtype_t* buffer() { return reinterpret_cast(ptr); }\n\n __device__ __forceinline__ dtype_t& operator[](int idx) { return buffer()[idx]; }\n};\n\ntemplate \nstruct AsymBuffer {\nprivate:\n uint8_t* ptrs[kNumRanks];\n int64_t num_bytes;\n\npublic:\n int64_t total_bytes;\n\n __device__ __forceinline__ AsymBuffer(void*& gbl_ptr, int num_elems, int num_ranks, int sm_id = 0, int num_sms = 1, int offset = 0) {\n EP_STATIC_ASSERT(kNumRanks == 1, \"\");\n num_bytes = num_elems * sizeof(dtype_t);\n\n int64_t per_channel_bytes = num_bytes * num_ranks;\n total_bytes = per_channel_bytes * num_sms;\n ptrs[0] = static_cast(gbl_ptr) + per_channel_bytes * sm_id + num_bytes * offset;\n gbl_ptr = static_cast(gbl_ptr) + total_bytes;\n }\n\n __device__ __forceinline__ AsymBuffer(void** gbl_ptrs, int num_elems, int num_ranks, int sm_id = 0, int num_sms = 1, int offset = 0) {\n EP_STATIC_ASSERT(kNumRanks > 1, \"\");\n num_bytes = num_elems * sizeof(dtype_t);\n\n int64_t per_channel_bytes = num_bytes * num_ranks;\n total_bytes = per_channel_bytes * num_sms;\n for (int i = 0; i < kNumRanks; ++i) {\n ptrs[i] = static_cast(gbl_ptrs[i]) + per_channel_bytes * sm_id + num_bytes * offset;\n gbl_ptrs[i] = static_cast(gbl_ptrs[i]) + total_bytes;\n }\n }\n\n __device__ __forceinline__ void advance(int shift) {\n #pragma unroll\n for (int i = 0; i < kNumRanks; ++i)\n ptrs[i] = ptrs[i] + shift * sizeof(dtype_t);\n }\n\n __device__ __forceinline__ AsymBuffer advance_also(void*& gbl_ptr) {\n gbl_ptr = static_cast(gbl_ptr) + total_bytes;\n return *this;\n }\n\n template \n __device__ __forceinline__ AsymBuffer advance_also(void** gbl_ptrs) {\n for (int i = 0; i < kNumAlsoRanks; ++i)\n gbl_ptrs[i] = static_cast(gbl_ptrs[i]) + total_bytes;\n return *this;\n }\n\n __device__ __forceinline__ dtype_t* buffer(int idx = 0) {\n EP_STATIC_ASSERT(kNumRanks == 1, \"`buffer` is only available for single rank case\");\n return reinterpret_cast(ptrs[0] + num_bytes * idx);\n }\n\n __device__ __forceinline__ dtype_t* buffer_by(int rank_idx, int idx = 0) {\n EP_STATIC_ASSERT(kNumRanks > 1, \"`buffer` is only available for single rank case\");\n return reinterpret_cast(ptrs[rank_idx] + num_bytes * idx);\n }\n};\n\ntemplate \nstruct SymBuffer {\nprivate:\n // NOTES: for non-decoupled case, `recv_ptr` is not used\n uint8_t* send_ptr;\n uint8_t* recv_ptr;\n int64_t num_bytes;\n\npublic:\n int64_t total_bytes;\n\n __device__ __forceinline__ SymBuffer(void*& gbl_ptr, int num_elems, int num_ranks, int sm_id = 0, int num_sms = 1) {\n num_bytes = num_elems * sizeof(dtype_t);\n\n int64_t per_channel_bytes = num_bytes * num_ranks;\n total_bytes = per_channel_bytes * num_sms * (static_cast(kDecoupled) + 1);\n send_ptr = static_cast(gbl_ptr) + per_channel_bytes * sm_id;\n recv_ptr = static_cast(gbl_ptr) + per_channel_bytes * (sm_id + num_sms);\n gbl_ptr = static_cast(gbl_ptr) + total_bytes;\n }\n\n __device__ __forceinline__ dtype_t* send_buffer(int idx = 0) {\n EP_STATIC_ASSERT(kDecoupled, \"`send_buffer` is only available for non-decoupled case\");\n return reinterpret_cast(send_ptr + num_bytes * idx);\n }\n\n __device__ __forceinline__ dtype_t* recv_buffer(int idx = 0) {\n EP_STATIC_ASSERT(kDecoupled, \"`recv_buffer` is only available for non-decoupled case\");\n return reinterpret_cast(recv_ptr + num_bytes * idx);\n }\n\n __device__ __forceinline__ dtype_t* buffer(int idx = 0) {\n EP_STATIC_ASSERT(not kDecoupled, \"`buffer` is only available for decoupled case\");\n return reinterpret_cast(send_ptr + num_bytes * idx);\n }\n};\n\n} // namespace deep_ep\n" }, { "path": "csrc/kernels/configs.cuh", "content": "#pragma once\n\n#define NUM_MAX_NVL_PEERS 8\n#define NUM_MAX_RDMA_PEERS 20\n#define NUM_WORKSPACE_BYTES (32 * 1024 * 1024)\n#define NUM_MAX_LOCAL_EXPERTS 1024\n#define NUM_BUFFER_ALIGNMENT_BYTES 128\n\n#define FINISHED_SUM_TAG 1024\n#define NUM_WAIT_NANOSECONDS 500\n\n#ifndef ENABLE_FAST_DEBUG\n#define NUM_CPU_TIMEOUT_SECS 100\n#define NUM_TIMEOUT_CYCLES 200000000000ull // 200G cycles ~= 100s\n#else\n#define NUM_CPU_TIMEOUT_SECS 10\n#define NUM_TIMEOUT_CYCLES 20000000000ull // 20G cycles ~= 10s\n#endif\n\n#define LOW_LATENCY_SEND_PHASE 1\n#define LOW_LATENCY_RECV_PHASE 2\n\n// Make CLion CUDA indexing work\n#ifdef __CLION_IDE__\n#define __CUDA_ARCH__ 900 // NOLINT(*-reserved-identifier)\n#define __CUDACC_RDC__ // NOLINT(*-reserved-identifier)\n#endif\n\n// Define __CUDACC_RDC__ to ensure proper extern declarations for NVSHMEM device symbols\n#ifndef DISABLE_NVSHMEM\n#ifndef __CUDACC_RDC__\n#define __CUDACC_RDC__ // NOLINT(*-reserved-identifier)\n#endif\n#endif\n\n// Remove Torch restrictions\n#ifdef __CUDA_NO_HALF_CONVERSIONS__\n#undef __CUDA_NO_HALF_CONVERSIONS__\n#endif\n#ifdef __CUDA_NO_HALF_OPERATORS__\n#undef __CUDA_NO_HALF_OPERATORS__\n#endif\n#ifdef __CUDA_NO_HALF2_OPERATORS__\n#undef __CUDA_NO_HALF2_OPERATORS__\n#endif\n#ifdef __CUDA_NO_BFLOAT16_CONVERSIONS__\n#undef __CUDA_NO_BFLOAT16_CONVERSIONS__\n#endif\n#ifdef __CUDA_NO_BFLOAT162_OPERATORS__\n#undef __CUDA_NO_BFLOAT162_OPERATORS__\n#endif\n\n#include \n#include \n\n#include \n\n#ifndef DISABLE_SM90_FEATURES\n#include \n#else\n// Ampere does not support FP8 features\n#define __NV_E4M3 0\n#define __NV_E5M2 1\ntypedef int __nv_fp8_interpretation_t;\ntypedef int __nv_fp8x4_e4m3;\ntypedef uint8_t __nv_fp8_storage_t;\n#endif\n\nnamespace deep_ep {\n\n#ifndef TOPK_IDX_BITS\n#define TOPK_IDX_BITS 64\n#endif\n\n#define INT_BITS_T2(bits) int##bits##_t\n#define INT_BITS_T(bits) INT_BITS_T2(bits)\ntypedef INT_BITS_T(TOPK_IDX_BITS) topk_idx_t; // int32_t or int64_t\n#undef INT_BITS_T\n#undef INT_BITS_T2\n\n} // namespace deep_ep\n\n#ifndef DISABLE_NVSHMEM\n#include \n#include \n#include \n#include \n\n#include \n#endif\n" }, { "path": "csrc/kernels/exception.cuh", "content": "#pragma once\n\n#include \n#include \n\n#include \"configs.cuh\"\n\n#ifndef EP_STATIC_ASSERT\n#define EP_STATIC_ASSERT(cond, reason) static_assert(cond, reason)\n#endif\n\nclass EPException : public std::exception {\nprivate:\n std::string message = {};\n\npublic:\n explicit EPException(const char* name, const char* file, const int line, const std::string& error) {\n message = std::string(\"Failed: \") + name + \" error \" + file + \":\" + std::to_string(line) + \" '\" + error + \"'\";\n }\n\n const char* what() const noexcept override { return message.c_str(); }\n};\n\n#ifndef CUDA_CHECK\n#define CUDA_CHECK(cmd) \\\n do { \\\n cudaError_t e = (cmd); \\\n if (e != cudaSuccess) { \\\n throw EPException(\"CUDA\", __FILE__, __LINE__, cudaGetErrorString(e)); \\\n } \\\n } while (0)\n#endif\n\n#ifndef CU_CHECK\n#define CU_CHECK(cmd) \\\n do { \\\n CUresult e = (cmd); \\\n if (e != CUDA_SUCCESS) { \\\n const char* error_str = NULL; \\\n cuGetErrorString(e, &error_str); \\\n throw EPException(\"CU\", __FILE__, __LINE__, std::string(error_str)); \\\n } \\\n } while (0)\n#endif\n\n#ifndef EP_HOST_ASSERT\n#define EP_HOST_ASSERT(cond) \\\n do { \\\n if (not(cond)) { \\\n throw EPException(\"Assertion\", __FILE__, __LINE__, #cond); \\\n } \\\n } while (0)\n#endif\n\n#ifndef EP_DEVICE_ASSERT\n#define EP_DEVICE_ASSERT(cond) \\\n do { \\\n if (not(cond)) { \\\n printf(\"Assertion failed: %s:%d, condition: %s\\n\", __FILE__, __LINE__, #cond); \\\n asm(\"trap;\"); \\\n } \\\n } while (0)\n#endif\n" }, { "path": "csrc/kernels/ibgda_device.cuh", "content": "// Portions derived from NVSHMEM (https://developer.nvidia.com/nvshmem)\n// Copyright (c) NVIDIA Corporation.\n// Licensed under the NVSHMEM Software License Agreement (version: September 3, 2019).\n// See full license at: https://docs.nvidia.com/nvshmem/api/sla.html\n//\n// Modified from original source:\n// - nvshmem/src/include/non_abi/device/pt-to-pt/ibgda_device.cuh\n#pragma once\n\n#include \n\n#include \"configs.cuh\"\n#include \"exception.cuh\"\n#include \"utils.cuh\"\n\nnamespace deep_ep {\n\nEP_STATIC_ASSERT(NVSHMEMI_IBGDA_MIN_QP_DEPTH >= 64, \"Invalid QP minimum depth\");\n\n__device__ static __forceinline__ uint64_t HtoBE64(uint64_t x) {\n uint64_t ret;\n asm(\"{\\n\\t\"\n \".reg .b32 ign;\\n\\t\"\n \".reg .b32 lo;\\n\\t\"\n \".reg .b32 hi;\\n\\t\"\n \".reg .b32 new_lo;\\n\\t\"\n \".reg .b32 new_hi;\\n\\t\"\n \"mov.b64 {lo,hi}, %1;\\n\\t\"\n \"prmt.b32 new_hi, lo, ign, 0x0123;\\n\\t\"\n \"prmt.b32 new_lo, hi, ign, 0x0123;\\n\\t\"\n \"mov.b64 %0, {new_lo,new_hi};\\n\\t\"\n \"}\"\n : \"=l\"(ret)\n : \"l\"(x));\n return ret;\n}\n\n__device__ static __forceinline__ uint32_t HtoBE32(uint32_t x) {\n uint32_t ret;\n asm(\"{\\n\\t\"\n \".reg .b32 ign;\\n\\t\"\n \"prmt.b32 %0, %1, ign, 0x0123;\\n\\t\"\n \"}\"\n : \"=r\"(ret)\n : \"r\"(x));\n return ret;\n}\n\n__device__ static __forceinline__ uint16_t HtoBE16(uint16_t x) {\n // TODO: simplify PTX using 16-bit instructions\n auto a = static_cast(x);\n uint32_t d;\n asm volatile(\n \"{\\n\\t\"\n \".reg .b32 mask;\\n\\t\"\n \".reg .b32 ign;\\n\\t\"\n \"mov.b32 mask, 0x4401;\\n\\t\"\n \"mov.b32 ign, 0x0;\\n\\t\"\n \"prmt.b32 %0, %1, ign, mask;\\n\\t\"\n \"}\"\n : \"=r\"(d)\n : \"r\"(a));\n return static_cast(d);\n}\n\ntypedef struct mlx5_wqe_ctrl_seg __attribute__((__aligned__(8))) ibgda_ctrl_seg_t;\n\ntypedef struct {\n uint32_t add_data;\n uint32_t field_boundary;\n uint64_t reserved;\n} __attribute__((__packed__)) ibgda_atomic_32_masked_fa_seg_t;\n\n__device__ static __forceinline__ nvshmemi_ibgda_device_state_t* ibgda_get_state() {\n return &nvshmemi_ibgda_device_state_d;\n}\n\n// Template helper to get RC - uses compile-time type checking with if constexpr (C++17)\ntemplate \n__device__ static __forceinline__ nvshmemi_ibgda_device_qp_t* ibgda_get_rc_impl(StateType* state, int pe, int id) {\n const auto num_rc_per_pe = state->num_rc_per_pe;\n\n if constexpr (std::is_same_v) {\n // v1 implementation\n return &state->globalmem\n .rcs[pe * num_rc_per_pe * state->num_devices_initialized + id % (num_rc_per_pe * state->num_devices_initialized)];\n } else {\n // v2 implementation (or any other type)\n return &state->globalmem.rcs[pe + nvshmemi_device_state_d.npes * id];\n }\n}\n\n__device__ static __forceinline__ nvshmemi_ibgda_device_qp_t* ibgda_get_rc(int pe, int id) {\n auto state = ibgda_get_state();\n return ibgda_get_rc_impl(state, pe, id);\n}\n\n__device__ static __forceinline__ void ibgda_lock_acquire(int* lock) {\n while (atomicCAS(lock, 0, 1) == 1)\n ;\n\n // Prevent reordering before the lock is acquired\n memory_fence_cta();\n}\n\n__device__ static __forceinline__ void ibgda_lock_release(int* lock) {\n memory_fence_cta();\n\n // Prevent reordering before lock is released\n st_na_relaxed(lock, 0);\n}\n\n__device__ static __forceinline__ void ibgda_update_dbr(nvshmemi_ibgda_device_qp_t* qp, uint32_t dbrec_head) {\n // `DBREC` contains the index of the next empty `WQEBB`\n __be32 dbrec_val;\n __be32* dbrec_ptr = qp->tx_wq.dbrec;\n\n // This is equivalent to `WRITE_ONCE(dbrec_ptr, HtoBE32(dbrec_head & 0xffff))`\n asm(\"{\\n\\t\"\n \".reg .b32 dbrec_head_16b;\\n\\t\"\n \".reg .b32 ign;\\n\\t\"\n \"and.b32 dbrec_head_16b, %1, 0xffff;\\n\\t\"\n \"prmt.b32 %0, dbrec_head_16b, ign, 0x123;\\n\\t\"\n \"}\"\n : \"=r\"(dbrec_val)\n : \"r\"(dbrec_head));\n st_na_release(dbrec_ptr, dbrec_val);\n}\n\n__device__ static __forceinline__ void ibgda_ring_db(nvshmemi_ibgda_device_qp_t* qp, uint16_t prod_idx) {\n auto bf_ptr = reinterpret_cast(qp->tx_wq.bf);\n ibgda_ctrl_seg_t ctrl_seg = {.opmod_idx_opcode = HtoBE32(prod_idx << 8), .qpn_ds = HtoBE32(qp->qpn << 8)};\n\n EP_STATIC_ASSERT(sizeof(decltype(&ctrl_seg)) == sizeof(uint64_t), \"\");\n st_na_release(bf_ptr, *(reinterpret_cast(&ctrl_seg)));\n}\n\n__device__ static __forceinline__ void ibgda_post_send(nvshmemi_ibgda_device_qp_t* qp, uint64_t new_prod_idx) {\n nvshmemi_ibgda_device_qp_management_t* mvars = &qp->mvars;\n uint64_t old_prod_idx;\n\n // Update `prod_idx` before ringing the doorbell, so that we know which index is needed in quiet/fence\n ibgda_lock_acquire(&mvars->post_send_lock);\n\n old_prod_idx = atomicMax(reinterpret_cast(&mvars->tx_wq.prod_idx), new_prod_idx);\n if (new_prod_idx > old_prod_idx) {\n ibgda_update_dbr(qp, new_prod_idx);\n ibgda_ring_db(qp, new_prod_idx);\n }\n ibgda_lock_release(&mvars->post_send_lock);\n}\n\ntemplate \n__device__ static __forceinline__ void ibgda_submit_requests(nvshmemi_ibgda_device_qp_t* qp,\n uint64_t base_wqe_idx,\n uint32_t num_wqes,\n int message_idx = 0) {\n auto state = ibgda_get_state();\n nvshmemi_ibgda_device_qp_management_t* mvars = &qp->mvars;\n uint64_t new_wqe_idx = base_wqe_idx + num_wqes;\n\n // WQE writes must be finished first\n __threadfence();\n\n unsigned long long int* ready_idx =\n (unsigned long long int*)(state->use_async_postsend ? qp->tx_wq.prod_idx : &mvars->tx_wq.ready_head);\n\n // Wait for prior WQE slots to be filled first\n while (atomicCAS(ready_idx, base_wqe_idx, new_wqe_idx) != base_wqe_idx)\n ;\n\n // Always post, not in batch\n if (!state->use_async_postsend) {\n constexpr int kNumRequestInBatch = 4;\n if (kAlwaysDoPostSend or (message_idx + 1) % kNumRequestInBatch == 0)\n ibgda_post_send(qp, new_wqe_idx);\n }\n}\n\n__device__ static __forceinline__ void ibgda_write_rdma_write_inl_wqe(\n nvshmemi_ibgda_device_qp_t* qp, const uint32_t* val, uint64_t raddr, __be32 rkey, uint16_t wqe_idx, void** out_wqes, uint32_t imm) {\n ibgda_ctrl_seg_t ctrl_seg;\n struct mlx5_wqe_raddr_seg raddr_seg;\n struct mlx5_wqe_inl_data_seg inl_seg;\n\n auto* ctrl_seg_ptr = reinterpret_cast(out_wqes[0]);\n auto* raddr_seg_ptr = reinterpret_cast(reinterpret_cast(ctrl_seg_ptr) + sizeof(*ctrl_seg_ptr));\n auto* inl_seg_ptr = reinterpret_cast(reinterpret_cast(raddr_seg_ptr) + sizeof(*raddr_seg_ptr));\n auto* wqe_data_ptr = reinterpret_cast(reinterpret_cast(inl_seg_ptr) + sizeof(*inl_seg_ptr));\n\n raddr_seg.raddr = HtoBE64(raddr);\n raddr_seg.rkey = rkey;\n raddr_seg.reserved = 0;\n\n inl_seg.byte_count = HtoBE32(4 | MLX5_INLINE_SEG);\n\n // `imm == std::numeric_limits::max()` means no imm writes\n ctrl_seg = {0};\n ctrl_seg.qpn_ds = HtoBE32((qp->qpn << 8) | 3);\n ctrl_seg.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;\n ctrl_seg.opmod_idx_opcode =\n HtoBE32((wqe_idx << 8) | (imm != std::numeric_limits::max() ? MLX5_OPCODE_RDMA_WRITE_IMM : MLX5_OPCODE_RDMA_WRITE));\n if (imm != std::numeric_limits::max())\n ctrl_seg.imm = HtoBE32(imm);\n\n EP_STATIC_ASSERT(sizeof(*ctrl_seg_ptr) == 16, \"sizeof(*ctrl_seg_ptr) == 16\");\n EP_STATIC_ASSERT(sizeof(*raddr_seg_ptr) == 16, \"sizeof(*raddr_seg_ptr) == 16\");\n EP_STATIC_ASSERT(sizeof(*inl_seg_ptr) == 4, \"sizeof(*inl_seg_ptr) == 4\");\n st_na_relaxed(reinterpret_cast(ctrl_seg_ptr), *reinterpret_cast(&ctrl_seg));\n st_na_relaxed(reinterpret_cast(raddr_seg_ptr), *reinterpret_cast(&raddr_seg));\n st_na_relaxed(reinterpret_cast(inl_seg_ptr), *reinterpret_cast(&inl_seg));\n st_na_relaxed(reinterpret_cast(wqe_data_ptr), *reinterpret_cast(val));\n}\n\n__device__ static __forceinline__ uint64_t\nibgda_get_lkey_and_rkey(uint64_t laddr, __be32* lkey, uint64_t raddr, int dst_pe, uint64_t* out_raddr, __be32* out_rkey, uint32_t dev_idx) {\n auto state = ibgda_get_state();\n auto heap_start = reinterpret_cast(nvshmemi_device_state_d.heap_base);\n auto log2_cumem_granularity = state->log2_cumem_granularity;\n\n // Local key\n uint64_t idx = ((laddr - heap_start) >> log2_cumem_granularity) * state->num_devices_initialized + dev_idx;\n auto device_key = state->constmem.lkeys[idx];\n auto lchunk_size = device_key.next_addr - laddr;\n *lkey = device_key.key;\n\n // Remote key\n uint64_t roffset = raddr - heap_start;\n\n idx = ((roffset >> log2_cumem_granularity) * nvshmemi_device_state_d.npes) * state->num_devices_initialized +\n dst_pe * state->num_devices_initialized + dev_idx;\n if (idx < NVSHMEMI_IBGDA_MAX_CONST_RKEYS) {\n device_key = state->constmem.rkeys[idx];\n } else {\n device_key = state->globalmem.rkeys[idx - NVSHMEMI_IBGDA_MAX_CONST_RKEYS];\n }\n *out_raddr = reinterpret_cast(nvshmemi_device_state_d.peer_heap_base_remote[dst_pe]) + roffset;\n *out_rkey = device_key.key;\n\n // Return the minimum of local and remote chunk sizes\n auto rchunk_size = device_key.next_addr - roffset;\n return min(lchunk_size, rchunk_size);\n}\n\n__device__ static __forceinline__ void ibgda_get_rkey(uint64_t addr, int dst_pe, uint64_t* out_raddr, __be32* out_rkey, uint32_t dev_idx) {\n auto state = ibgda_get_state();\n auto heap_start = reinterpret_cast(nvshmemi_device_state_d.heap_base);\n\n uint64_t roffset = addr - heap_start;\n uint64_t idx = ((roffset >> state->log2_cumem_granularity) * nvshmemi_device_state_d.npes * state->num_devices_initialized) +\n dst_pe * state->num_devices_initialized + dev_idx;\n nvshmemi_ibgda_device_key_t device_key;\n if (idx < NVSHMEMI_IBGDA_MAX_CONST_RKEYS)\n device_key = state->constmem.rkeys[idx];\n else\n device_key = state->globalmem.rkeys[idx - NVSHMEMI_IBGDA_MAX_CONST_RKEYS];\n *out_raddr = reinterpret_cast(nvshmemi_device_state_d.peer_heap_base_remote[dst_pe]) + roffset;\n *out_rkey = device_key.key;\n}\n\n__device__ static __forceinline__ uint64_t ibgda_reserve_wqe_slots(nvshmemi_ibgda_device_qp_t* qp, uint32_t num_wqes) {\n auto mvars = &qp->mvars;\n return atomicAdd(reinterpret_cast(&mvars->tx_wq.resv_head), static_cast(num_wqes));\n}\n\n__device__ static __forceinline__ void* ibgda_get_wqe_ptr(nvshmemi_ibgda_device_qp_t* qp, uint16_t wqe_idx) {\n uint16_t cnt = qp->tx_wq.nwqes;\n uint16_t idx = wqe_idx & (cnt - 1);\n return reinterpret_cast(reinterpret_cast(qp->tx_wq.wqe) + (idx << MLX5_SEND_WQE_SHIFT));\n}\n\n__device__ static __forceinline__ void nvshmemi_ibgda_rma_p(\n int* rptr, const int value, int dst_pe, int qp_id, uint32_t imm = std::numeric_limits::max()) {\n // Get rkey\n // NOTES: the `p` operation will not cross multiple remote chunks\n __be32 rkey;\n uint64_t raddr;\n auto qp = ibgda_get_rc(dst_pe, qp_id);\n ibgda_get_rkey(reinterpret_cast(rptr), dst_pe, &raddr, &rkey, qp->dev_idx);\n\n // Write WQEs\n uint64_t base_wqe_idx = ibgda_reserve_wqe_slots(qp, 1);\n void* wqe_ptrs;\n wqe_ptrs = ibgda_get_wqe_ptr(qp, base_wqe_idx);\n ibgda_write_rdma_write_inl_wqe(qp, reinterpret_cast(&value), raddr, rkey, base_wqe_idx, &wqe_ptrs, imm);\n\n // Submit requests\n ibgda_submit_requests(qp, base_wqe_idx, 1);\n}\n\n__device__ static __forceinline__ void ibgda_write_rdma_write_wqe(nvshmemi_ibgda_device_qp_t* qp,\n uint64_t laddr,\n __be32 lkey,\n uint64_t raddr,\n __be32 rkey,\n uint32_t bytes,\n uint16_t wqe_idx,\n void** out_wqes) {\n ibgda_ctrl_seg_t ctrl_seg;\n struct mlx5_wqe_raddr_seg raddr_seg;\n struct mlx5_wqe_data_seg data_seg;\n\n auto* ctrl_seg_ptr = reinterpret_cast(out_wqes[0]);\n void* av_seg_ptr = reinterpret_cast(reinterpret_cast(ctrl_seg_ptr) + sizeof(*ctrl_seg_ptr));\n struct mlx5_wqe_raddr_seg* raddr_seg_ptr;\n struct mlx5_wqe_data_seg* data_seg_ptr;\n\n raddr_seg_ptr = reinterpret_cast(reinterpret_cast(av_seg_ptr));\n data_seg_ptr = reinterpret_cast(reinterpret_cast(raddr_seg_ptr) + sizeof(*raddr_seg_ptr));\n\n raddr_seg.raddr = HtoBE64(raddr);\n raddr_seg.rkey = rkey;\n raddr_seg.reserved = 0;\n\n data_seg.byte_count = HtoBE32(bytes);\n data_seg.lkey = lkey;\n data_seg.addr = HtoBE64(laddr);\n\n ctrl_seg = {0};\n ctrl_seg.qpn_ds = HtoBE32((qp->qpn << 8) | 3);\n ctrl_seg.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;\n ctrl_seg.opmod_idx_opcode = HtoBE32((wqe_idx << 8) | MLX5_OPCODE_RDMA_WRITE);\n\n EP_STATIC_ASSERT(sizeof(*ctrl_seg_ptr) == 16, \"sizeof(*ctrl_seg_ptr) == 16\");\n EP_STATIC_ASSERT(sizeof(*raddr_seg_ptr) == 16, \"sizeof(*raddr_seg_ptr) == 16\");\n EP_STATIC_ASSERT(sizeof(*data_seg_ptr) == 16, \"sizeof(*data_seg_ptr) == 16\");\n st_na_relaxed(reinterpret_cast(ctrl_seg_ptr), *reinterpret_cast(&ctrl_seg));\n st_na_relaxed(reinterpret_cast(raddr_seg_ptr), *reinterpret_cast(&raddr_seg));\n st_na_relaxed(reinterpret_cast(data_seg_ptr), *reinterpret_cast(&data_seg));\n}\n\n__device__ static __forceinline__ void ibgda_write_empty_recv_wqe(void* out_wqe) {\n auto* data_seg_ptr = reinterpret_cast(out_wqe);\n struct mlx5_wqe_data_seg data_seg;\n\n // Make the first segment in the WQE invalid, then the entire list will be invalid\n data_seg.byte_count = 0;\n data_seg.lkey = HtoBE64(MLX5_INVALID_LKEY);\n data_seg.addr = 0;\n\n EP_STATIC_ASSERT(sizeof(mlx5_wqe_data_seg) == sizeof(int4), \"Invalid data type length\");\n st_na_relaxed(reinterpret_cast(data_seg_ptr), *reinterpret_cast(&data_seg));\n}\n\ntemplate \n__device__ static __forceinline__ void nvshmemi_ibgda_put_nbi_warp(\n uint64_t req_rptr, uint64_t req_lptr, size_t bytes, int dst_pe, int qp_id, int lane_id, int message_idx) {\n // Get lkey and rkey, store them into lanes\n uint32_t num_wqes = 0;\n __be32 my_lkey = 0;\n uint64_t my_laddr = 0;\n __be32 my_rkey = 0;\n uint64_t my_raddr = 0;\n uint64_t my_chunk_size = 0;\n\n auto qp = ibgda_get_rc(dst_pe, qp_id);\n\n // Decide how many messages (theoretically 3 for maximum)\n auto remaining_bytes = bytes;\n while (remaining_bytes > 0) {\n if (lane_id == num_wqes) {\n my_chunk_size = min(remaining_bytes,\n ibgda_get_lkey_and_rkey(my_laddr = req_lptr, &my_lkey, req_rptr, dst_pe, &my_raddr, &my_rkey, qp->dev_idx));\n }\n\n // Move one more message\n auto chunk_size = __shfl_sync(0xffffffff, my_chunk_size, static_cast(num_wqes));\n remaining_bytes -= chunk_size;\n req_lptr += chunk_size;\n req_rptr += chunk_size;\n ++num_wqes;\n }\n EP_DEVICE_ASSERT(num_wqes <= 32);\n\n // Process WQE\n uint64_t base_wqe_idx = 0;\n if (lane_id == 0)\n base_wqe_idx = ibgda_reserve_wqe_slots(qp, num_wqes);\n base_wqe_idx = __shfl_sync(0xffffffff, base_wqe_idx, 0);\n if (lane_id < num_wqes) {\n auto wqe_idx = base_wqe_idx + lane_id;\n auto wqe_ptr = ibgda_get_wqe_ptr(qp, wqe_idx);\n ibgda_write_rdma_write_wqe(qp, my_laddr, my_lkey, my_raddr, my_rkey, my_chunk_size, wqe_idx, &wqe_ptr);\n }\n __syncwarp();\n\n // Submit\n if (lane_id == 0)\n ibgda_submit_requests(qp, base_wqe_idx, num_wqes, message_idx);\n __syncwarp();\n}\n\n__device__ static __forceinline__ void ibgda_write_amo_add_wqe(nvshmemi_ibgda_device_qp_t* qp,\n const int& value,\n uint64_t laddr,\n __be32 lkey,\n uint64_t raddr,\n __be32 rkey,\n uint16_t wqe_idx,\n void** out_wqes) {\n ibgda_ctrl_seg_t ctrl_seg = {0};\n struct mlx5_wqe_raddr_seg raddr_seg;\n struct mlx5_wqe_atomic_seg atomic_seg_1;\n struct mlx5_wqe_data_seg data_seg;\n\n auto ctrl_seg_ptr = reinterpret_cast(out_wqes[0]);\n auto raddr_seg_ptr = reinterpret_cast(reinterpret_cast(ctrl_seg_ptr) + sizeof(*ctrl_seg_ptr));\n auto atomic_seg_ptr = reinterpret_cast(reinterpret_cast(raddr_seg_ptr) + sizeof(*raddr_seg_ptr));\n auto data_seg_ptr = reinterpret_cast(reinterpret_cast(atomic_seg_ptr) + sizeof(*atomic_seg_ptr));\n\n raddr_seg.raddr = HtoBE64(raddr);\n raddr_seg.rkey = rkey;\n raddr_seg.reserved = 0;\n\n // NOTES: `0x08000000` means `IBGDA_4_BYTE_EXT_AMO_OPMOD`\n ctrl_seg.opmod_idx_opcode = HtoBE32(MLX5_OPCODE_ATOMIC_MASKED_FA | (wqe_idx << 8) | 0x08000000);\n auto atomic_32_masked_fa_seg = reinterpret_cast(&atomic_seg_1);\n atomic_32_masked_fa_seg->add_data = HtoBE32(value);\n atomic_32_masked_fa_seg->field_boundary = 0;\n\n ctrl_seg.qpn_ds = HtoBE32((qp->qpn << 8) | 4);\n ctrl_seg.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;\n\n data_seg.byte_count = HtoBE32(sizeof(int));\n data_seg.lkey = lkey;\n data_seg.addr = HtoBE64(laddr);\n\n EP_STATIC_ASSERT(sizeof(*ctrl_seg_ptr) == sizeof(int4), \"Invalid vectorization\");\n EP_STATIC_ASSERT(sizeof(*raddr_seg_ptr) == sizeof(int4), \"Invalid vectorization\");\n EP_STATIC_ASSERT(sizeof(*atomic_seg_ptr) == sizeof(int4), \"Invalid vectorization\");\n EP_STATIC_ASSERT(sizeof(*data_seg_ptr) == sizeof(int4), \"Invalid vectorization\");\n st_na_relaxed(reinterpret_cast(ctrl_seg_ptr), *reinterpret_cast(&ctrl_seg));\n st_na_relaxed(reinterpret_cast(raddr_seg_ptr), *reinterpret_cast(&raddr_seg));\n st_na_relaxed(reinterpret_cast(atomic_seg_ptr), *reinterpret_cast(&atomic_seg_1));\n st_na_relaxed(reinterpret_cast(data_seg_ptr), *reinterpret_cast(&data_seg));\n}\n\n__device__ __forceinline__ void nvshmemi_ibgda_amo_nonfetch_add(\n void* rptr, const int& value, int pe, int qp_id, bool is_local_copy = false) {\n if (is_local_copy) {\n atomicAdd(static_cast(rptr), value);\n } else {\n nvshmemi_ibgda_device_qp_t* qp = ibgda_get_rc(pe, qp_id);\n\n __be32 rkey;\n uint64_t raddr;\n ibgda_get_rkey(reinterpret_cast(rptr), pe, &raddr, &rkey, qp->dev_idx);\n\n uint64_t my_wqe_idx = ibgda_reserve_wqe_slots(qp, 1);\n void* wqe_ptrs = ibgda_get_wqe_ptr(qp, my_wqe_idx);\n\n ibgda_write_amo_add_wqe(qp, value, reinterpret_cast(qp->ibuf.buf), qp->ibuf.lkey, raddr, rkey, my_wqe_idx, &wqe_ptrs);\n\n ibgda_submit_requests(qp, my_wqe_idx, 1);\n }\n}\n\n__device__ __forceinline__ uint64_t nvshmemi_get_p2p_ptr(const uint64_t& ptr, const int& rank, const int& dst_rank) {\n // Local rank, no need for mapping\n if (rank == dst_rank)\n return ptr;\n auto peer_base = __ldg(reinterpret_cast(nvshmemi_device_state_d.peer_heap_base_p2p) + dst_rank);\n\n // RDMA connected\n if (peer_base == 0)\n return 0;\n\n // NVLink P2P is enabled\n return peer_base + (ptr - reinterpret_cast(nvshmemi_device_state_d.heap_base));\n}\n\n// This is a simplified version of NVSHMEM's `ibgda_poll_cq`.\n// Note that this implementation does not guarantee thread safety,\n// so we must ensure that no other threads are concurrently using the same QP.\n__device__ static __forceinline__ void ibgda_poll_cq(nvshmemi_ibgda_device_cq_t* cq, uint64_t idx) {\n const auto cqe64 = static_cast(cq->cqe);\n const uint32_t ncqes = cq->ncqes;\n memory_fence_cta();\n if (*cq->cons_idx >= idx)\n return;\n // NOTES: this while loop is part of do-while below.\n // `wqe_counter` is the HW consumer index. However, we always maintain `index + 1`.\n // To be able to compare with the index, we need to use `wqe_counter + 1`.\n // Because `wqe_counter` is `uint16_t`, it may be overflow. Still, we know for\n // sure that if `idx - wqe_counter - 1 < ncqes`, `wqe_counter + 1 is less than\n // idx, and thus we need to wait. We don't need to wait when `idx == wqe_counter + 1`\n // That's why we use `- 2` here to make this case overflow.\n uint16_t wqe_counter;\n do {\n wqe_counter = HtoBE16(ld_na_relaxed(&cqe64->wqe_counter));\n } while ((static_cast(static_cast(idx) - wqe_counter - static_cast(2)) < ncqes));\n *cq->cons_idx = idx;\n\n // Prevent reordering of this function and later instructions\n memory_fence_cta();\n}\n\n// Wait until wqe `idx - 1` is completed.\n__device__ static __forceinline__ void nvshmemi_ibgda_quiet(int dst_pe, int qp_id) {\n auto qp = ibgda_get_rc(dst_pe, qp_id);\n auto state = ibgda_get_state();\n uint64_t prod_idx = state->use_async_postsend ? ld_na_relaxed(qp->tx_wq.prod_idx) : ld_na_relaxed(&qp->mvars.tx_wq.ready_head);\n ibgda_poll_cq(qp->tx_wq.cq, prod_idx);\n}\n\n} // namespace deep_ep\n" }, { "path": "csrc/kernels/internode.cu", "content": "#include \n#include \n\n#include \"buffer.cuh\"\n#include \"configs.cuh\"\n#include \"exception.cuh\"\n#include \"ibgda_device.cuh\"\n#include \"launch.cuh\"\n#include \"utils.cuh\"\n\nnamespace deep_ep {\n\nnamespace internode {\n\nextern nvshmem_team_t cpu_rdma_team;\n\nstruct SourceMeta {\n int src_rdma_rank, is_token_in_nvl_rank_bits;\n\n EP_STATIC_ASSERT(NUM_MAX_NVL_PEERS == 8, \"Invalid number of maximum NVL peers\");\n\n __forceinline__ SourceMeta() = default;\n\n // TODO: faster encoding\n __device__ __forceinline__ SourceMeta(int rdma_rank, const bool* is_token_in_nvl_ranks) {\n src_rdma_rank = rdma_rank;\n is_token_in_nvl_rank_bits = is_token_in_nvl_ranks[0];\n #pragma unroll\n for (int i = 1; i < NUM_MAX_NVL_PEERS; ++i)\n is_token_in_nvl_rank_bits |= is_token_in_nvl_ranks[i] << i;\n }\n\n __device__ __forceinline__ bool is_token_in_nvl_rank(int nvl_rank) const { return (is_token_in_nvl_rank_bits >> nvl_rank) & 1; }\n};\n\nEP_STATIC_ASSERT(sizeof(SourceMeta) % sizeof(int) == 0, \"Invalid size of `SourceMeta`\");\n\nint get_source_meta_bytes() {\n return sizeof(SourceMeta);\n}\n\n__host__ __device__ __forceinline__ int get_num_bytes_per_token(int hidden_int4, int num_scales, int num_topk_idx, int num_topk_weights) {\n return static_cast(align_up(hidden_int4 * sizeof(int4) + sizeof(SourceMeta) + num_scales * sizeof(float) +\n num_topk_idx * sizeof(int) + num_topk_weights * sizeof(float),\n sizeof(int4)));\n}\n\n__host__ __device__ __forceinline__ std::pair get_rdma_clean_meta(int hidden_int4,\n int num_scales,\n int num_topk_idx,\n int num_topk_weights,\n int num_rdma_ranks,\n int num_rdma_recv_buffer_tokens,\n int num_channels) {\n // Return `int32_t` offset and count to clean\n return {(get_num_bytes_per_token(hidden_int4, num_scales, num_topk_idx, num_topk_weights) * num_rdma_recv_buffer_tokens *\n num_rdma_ranks * 2 * num_channels) /\n sizeof(int),\n (NUM_MAX_NVL_PEERS * 2 + 4) * num_rdma_ranks * 2 * num_channels};\n}\n\n__host__ __device__ __forceinline__ std::pair get_nvl_clean_meta(int hidden_int4,\n int num_scales,\n int num_topk_idx,\n int num_topk_weights,\n int num_rdma_ranks,\n int num_nvl_ranks,\n int num_nvl_recv_buffer_tokens,\n int num_channels,\n bool is_dispatch) {\n // Return `int32_t` offset and to clean\n EP_STATIC_ASSERT(sizeof(SourceMeta) % sizeof(int) == 0, \"Invalid size of `SourceMeta`\");\n\n return {\n (num_nvl_recv_buffer_tokens * get_num_bytes_per_token(hidden_int4, num_scales, num_topk_idx, num_topk_weights) * num_nvl_ranks *\n num_channels) /\n sizeof(int),\n num_nvl_ranks * (2 * num_rdma_ranks + 2) * num_channels,\n };\n}\n\ntemplate \n__forceinline__ __device__ int translate_dst_rdma_rank(const int dst_rdma_rank, const int nvl_rank) {\n return kLowLatencyMode ? (dst_rdma_rank * NUM_MAX_NVL_PEERS + nvl_rank) : dst_rdma_rank;\n}\n\ntemplate \n__forceinline__ __device__ void nvshmem_sync_with_same_gpu_idx(const nvshmem_team_t& rdma_team) {\n kLowLatencyMode ? void(nvshmem_sync(rdma_team)) : nvshmem_sync_all();\n}\n\ntemplate \n__global__ void notify_dispatch(const int* num_tokens_per_rank,\n int* moe_recv_counter_mapped,\n int num_ranks,\n const int* num_tokens_per_rdma_rank,\n int* moe_recv_rdma_counter_mapped,\n const int* num_tokens_per_expert,\n int* moe_recv_expert_counter_mapped,\n int num_experts,\n const bool* is_token_in_rank,\n int num_tokens,\n int num_worst_tokens,\n int num_channels,\n int expert_alignment,\n const int rdma_clean_offset,\n const int rdma_num_int_clean,\n const int nvl_clean_offset,\n const int nvl_num_int_clean,\n int* rdma_channel_prefix_matrix,\n int* recv_rdma_rank_prefix_sum,\n int* gbl_channel_prefix_matrix,\n int* recv_gbl_rank_prefix_sum,\n void* rdma_buffer_ptr,\n void** buffer_ptrs,\n int** barrier_signal_ptrs,\n int rank,\n const nvshmem_team_t rdma_team) {\n auto sm_id = static_cast(blockIdx.x);\n auto thread_id = static_cast(threadIdx.x), warp_id = thread_id / 32, lane_id = get_lane_id();\n auto num_threads = static_cast(blockDim.x), num_warps = num_threads / 32;\n\n auto rdma_rank = rank / NUM_MAX_NVL_PEERS, nvl_rank = rank % NUM_MAX_NVL_PEERS;\n auto num_rdma_experts = num_experts / kNumRDMARanks, num_nvl_experts = num_rdma_experts / NUM_MAX_NVL_PEERS;\n\n if (sm_id == 0) {\n // Communication with others\n // Global barrier: the first warp does intra-node sync, the second warp does internode sync\n EP_DEVICE_ASSERT(num_warps > 1);\n EP_DEVICE_ASSERT(kNumRDMARanks <= num_threads);\n\n // waiting for all previous inflight wrs to complete,\n // in case of rewriting cleared rdma_buffer\n auto qps_per_rdma_rank = ibgda_get_state()->num_rc_per_pe * ibgda_get_state()->num_devices_initialized;\n for (int i = thread_id; i < qps_per_rdma_rank * (kNumRDMARanks - 1); i += num_threads) {\n auto dst_rdma_rank = (i / qps_per_rdma_rank + rdma_rank + 1) % kNumRDMARanks;\n auto qp_id = i % qps_per_rdma_rank;\n nvshmemi_ibgda_quiet(translate_dst_rdma_rank(dst_rdma_rank, nvl_rank), qp_id);\n }\n __syncthreads();\n\n if (thread_id == 32)\n nvshmem_sync_with_same_gpu_idx(rdma_team);\n barrier_block(barrier_signal_ptrs, nvl_rank);\n\n // Send numbers of tokens per rank/expert to RDMA ranks\n auto rdma_buffer_ptr_int = static_cast(rdma_buffer_ptr);\n auto rdma_recv_num_tokens_mixed = SymBuffer(rdma_buffer_ptr, NUM_MAX_NVL_PEERS + num_rdma_experts + 1, kNumRDMARanks);\n\n // Clean up for later data dispatch\n EP_DEVICE_ASSERT(rdma_recv_num_tokens_mixed.total_bytes <= rdma_clean_offset * sizeof(int));\n #pragma unroll\n for (int i = thread_id; i < rdma_num_int_clean; i += num_threads)\n rdma_buffer_ptr_int[rdma_clean_offset + i] = 0;\n\n // Copy to send buffer\n #pragma unroll\n for (int i = thread_id; i < num_ranks; i += num_threads)\n rdma_recv_num_tokens_mixed.send_buffer(i / NUM_MAX_NVL_PEERS)[i % NUM_MAX_NVL_PEERS] = num_tokens_per_rank[i];\n #pragma unroll\n for (int i = thread_id; i < num_experts; i += num_threads)\n rdma_recv_num_tokens_mixed.send_buffer(i / num_rdma_experts)[NUM_MAX_NVL_PEERS + i % num_rdma_experts] =\n num_tokens_per_expert[i];\n if (thread_id < kNumRDMARanks)\n rdma_recv_num_tokens_mixed.send_buffer(thread_id)[NUM_MAX_NVL_PEERS + num_rdma_experts] = num_tokens_per_rdma_rank[thread_id];\n __syncthreads();\n\n // Issue send\n // TODO: more light fence or barrier or signaling\n // TODO: overlap EP barrier and NVL cleaning\n for (int i = warp_id; i < kNumRDMARanks; i += num_warps) {\n if (i != rdma_rank) {\n nvshmemi_ibgda_put_nbi_warp(reinterpret_cast(rdma_recv_num_tokens_mixed.recv_buffer(rdma_rank)),\n reinterpret_cast(rdma_recv_num_tokens_mixed.send_buffer(i)),\n (NUM_MAX_NVL_PEERS + num_rdma_experts + 1) * sizeof(int),\n translate_dst_rdma_rank(i, nvl_rank),\n 0,\n lane_id,\n 0);\n } else {\n UNROLLED_WARP_COPY(1,\n lane_id,\n NUM_MAX_NVL_PEERS + num_rdma_experts + 1,\n rdma_recv_num_tokens_mixed.recv_buffer(rdma_rank),\n rdma_recv_num_tokens_mixed.send_buffer(i),\n ld_volatile_global,\n st_na_global);\n }\n }\n __syncthreads();\n\n // Wait previous operations to be finished\n if (thread_id < kNumRDMARanks and thread_id != rdma_rank)\n nvshmemi_ibgda_quiet(translate_dst_rdma_rank(thread_id, nvl_rank), 0);\n __syncthreads();\n\n // Barrier\n if (thread_id == 0)\n nvshmem_sync_with_same_gpu_idx(rdma_team);\n __syncthreads();\n\n // NVL buffers\n auto nvl_send_buffer = thread_id < NUM_MAX_NVL_PEERS ? buffer_ptrs[thread_id] : nullptr;\n auto nvl_recv_buffer = buffer_ptrs[nvl_rank];\n auto nvl_reduced_num_tokens_per_expert = Buffer(nvl_recv_buffer, num_rdma_experts).advance_also(nvl_send_buffer);\n auto nvl_send_num_tokens_per_rank = AsymBuffer(nvl_send_buffer, kNumRDMARanks, NUM_MAX_NVL_PEERS);\n auto nvl_send_num_tokens_per_expert = AsymBuffer(nvl_send_buffer, num_nvl_experts, NUM_MAX_NVL_PEERS);\n auto nvl_recv_num_tokens_per_rank = AsymBuffer(nvl_recv_buffer, kNumRDMARanks, NUM_MAX_NVL_PEERS);\n auto nvl_recv_num_tokens_per_expert = AsymBuffer(nvl_recv_buffer, num_nvl_experts, NUM_MAX_NVL_PEERS);\n\n // Clean up for later data dispatch\n auto nvl_buffer_ptr_int = static_cast(buffer_ptrs[nvl_rank]);\n EP_DEVICE_ASSERT(nvl_reduced_num_tokens_per_expert.total_bytes + nvl_send_num_tokens_per_rank.total_bytes +\n nvl_send_num_tokens_per_expert.total_bytes <=\n nvl_clean_offset * sizeof(int));\n #pragma unroll\n for (int i = thread_id; i < nvl_num_int_clean; i += num_threads)\n nvl_buffer_ptr_int[nvl_clean_offset + i] = 0;\n\n // Reduce number of tokens per expert into the NVL send buffer\n // TODO: may use NVSHMEM reduction\n EP_DEVICE_ASSERT(num_rdma_experts <= num_threads);\n if (thread_id < num_rdma_experts) {\n int sum = 0;\n #pragma unroll\n for (int i = 0; i < kNumRDMARanks; ++i)\n sum += rdma_recv_num_tokens_mixed.recv_buffer(i)[NUM_MAX_NVL_PEERS + thread_id];\n nvl_reduced_num_tokens_per_expert[thread_id] = sum;\n }\n __syncthreads();\n\n // Reduce RDMA received tokens\n if (thread_id == 0) {\n int sum = 0;\n #pragma unroll\n for (int i = 0; i < kNumRDMARanks; ++i) {\n sum += rdma_recv_num_tokens_mixed.recv_buffer(i)[NUM_MAX_NVL_PEERS + num_rdma_experts];\n recv_rdma_rank_prefix_sum[i] = sum;\n }\n if (num_worst_tokens == 0) {\n while (ld_volatile_global(moe_recv_rdma_counter_mapped) != -1)\n ;\n *moe_recv_rdma_counter_mapped = sum;\n }\n }\n\n // Send numbers of tokens per rank/expert to NVL ranks\n EP_DEVICE_ASSERT(NUM_MAX_NVL_PEERS <= num_threads);\n if (thread_id < NUM_MAX_NVL_PEERS) {\n #pragma unroll\n for (int i = 0; i < kNumRDMARanks; ++i)\n nvl_send_num_tokens_per_rank.buffer(nvl_rank)[i] = rdma_recv_num_tokens_mixed.recv_buffer(i)[thread_id];\n #pragma unroll\n for (int i = 0; i < num_nvl_experts; ++i)\n nvl_send_num_tokens_per_expert.buffer(nvl_rank)[i] = nvl_reduced_num_tokens_per_expert[thread_id * num_nvl_experts + i];\n }\n barrier_block(barrier_signal_ptrs, nvl_rank);\n\n // Reduce the number of tokens per rank/expert\n EP_DEVICE_ASSERT(num_nvl_experts <= num_threads);\n if (thread_id == 0) {\n int sum = 0;\n #pragma unroll\n for (int i = 0; i < num_ranks; ++i) {\n int src_rdma_rank = i / NUM_MAX_NVL_PEERS, src_nvl_rank = i % NUM_MAX_NVL_PEERS;\n sum += nvl_recv_num_tokens_per_rank.buffer(src_nvl_rank)[src_rdma_rank];\n recv_gbl_rank_prefix_sum[i] = sum;\n }\n if (num_worst_tokens == 0) {\n while (ld_volatile_global(moe_recv_counter_mapped) != -1)\n ;\n *moe_recv_counter_mapped = sum;\n }\n }\n if (thread_id < num_nvl_experts) {\n int sum = 0;\n #pragma unroll\n for (int i = 0; i < NUM_MAX_NVL_PEERS; ++i)\n sum += nvl_recv_num_tokens_per_expert.buffer(i)[thread_id];\n sum = (sum + expert_alignment - 1) / expert_alignment * expert_alignment;\n if (num_worst_tokens == 0) {\n while (ld_volatile_global(moe_recv_expert_counter_mapped + thread_id) != -1)\n ;\n moe_recv_expert_counter_mapped[thread_id] = sum;\n }\n }\n\n // Finally barrier\n if (thread_id == 32)\n nvshmem_sync_with_same_gpu_idx(rdma_team);\n barrier_block(barrier_signal_ptrs, nvl_rank);\n } else {\n // Calculate meta data\n int dst_rdma_rank = sm_id - 1;\n for (int channel_id = warp_id; channel_id < num_channels; channel_id += num_warps) {\n int token_start_idx, token_end_idx;\n get_channel_task_range(num_tokens, num_channels, channel_id, token_start_idx, token_end_idx);\n\n // Iterate over tokens\n int total_count = 0, per_nvl_rank_count[NUM_MAX_NVL_PEERS] = {0};\n for (int64_t i = token_start_idx + lane_id; i < token_end_idx; i += 32) {\n EP_STATIC_ASSERT(NUM_MAX_NVL_PEERS * sizeof(bool) == sizeof(uint64_t), \"Invalid number of NVL peers\");\n auto is_token_in_rank_uint64 =\n *reinterpret_cast(is_token_in_rank + i * num_ranks + dst_rdma_rank * NUM_MAX_NVL_PEERS);\n auto is_token_in_rank_values = reinterpret_cast(&is_token_in_rank_uint64);\n #pragma unroll\n for (int j = 0; j < NUM_MAX_NVL_PEERS; ++j)\n per_nvl_rank_count[j] += is_token_in_rank_values[j];\n total_count += (is_token_in_rank_uint64 != 0);\n }\n\n // Warp reduce\n total_count = warp_reduce_sum(total_count);\n #pragma unroll\n for (int i = 0; i < NUM_MAX_NVL_PEERS; ++i)\n per_nvl_rank_count[i] = warp_reduce_sum(per_nvl_rank_count[i]);\n\n // Write into channel matrix\n if (elect_one_sync()) {\n #pragma unroll\n for (int i = 0; i < NUM_MAX_NVL_PEERS; ++i)\n gbl_channel_prefix_matrix[(dst_rdma_rank * NUM_MAX_NVL_PEERS + i) * num_channels + channel_id] = per_nvl_rank_count[i];\n rdma_channel_prefix_matrix[dst_rdma_rank * num_channels + channel_id] = total_count;\n }\n }\n\n // Calculate prefix sum\n __syncthreads();\n if (thread_id == 0) {\n auto prefix_row = rdma_channel_prefix_matrix + dst_rdma_rank * num_channels;\n #pragma unroll\n for (int i = 1; i < num_channels; ++i)\n prefix_row[i] += prefix_row[i - 1];\n }\n\n EP_STATIC_ASSERT(NUM_MAX_NVL_PEERS <= 32, \"Invalid number of NVL peers\");\n if (thread_id < NUM_MAX_NVL_PEERS) {\n auto prefix_row = gbl_channel_prefix_matrix + (dst_rdma_rank * NUM_MAX_NVL_PEERS + thread_id) * num_channels;\n #pragma unroll\n for (int i = 1; i < num_channels; ++i)\n prefix_row[i] += prefix_row[i - 1];\n }\n }\n}\n\nvoid notify_dispatch(const int* num_tokens_per_rank,\n int* moe_recv_counter_mapped,\n int num_ranks,\n const int* num_tokens_per_rdma_rank,\n int* moe_recv_rdma_counter_mapped,\n const int* num_tokens_per_expert,\n int* moe_recv_expert_counter_mapped,\n int num_experts,\n const bool* is_token_in_rank,\n int num_tokens,\n int num_worst_tokens,\n int num_channels,\n int hidden_int4,\n int num_scales,\n int num_topk,\n int expert_alignment,\n int* rdma_channel_prefix_matrix,\n int* recv_rdma_rank_prefix_sum,\n int* gbl_channel_prefix_matrix,\n int* recv_gbl_rank_prefix_sum,\n void* rdma_buffer_ptr,\n int num_max_rdma_chunked_recv_tokens,\n void** buffer_ptrs,\n int num_max_nvl_chunked_recv_tokens,\n int** barrier_signal_ptrs,\n int rank,\n cudaStream_t stream,\n int64_t num_rdma_bytes,\n int64_t num_nvl_bytes,\n bool low_latency_mode) {\n#define NOTIFY_DISPATCH_LAUNCH_CASE(num_rdma_ranks) \\\n { \\\n auto notify_dispatch_func = low_latency_mode ? notify_dispatch : notify_dispatch; \\\n LAUNCH_KERNEL(&cfg, \\\n notify_dispatch_func, \\\n num_tokens_per_rank, \\\n moe_recv_counter_mapped, \\\n num_ranks, \\\n num_tokens_per_rdma_rank, \\\n moe_recv_rdma_counter_mapped, \\\n num_tokens_per_expert, \\\n moe_recv_expert_counter_mapped, \\\n num_experts, \\\n is_token_in_rank, \\\n num_tokens, \\\n num_worst_tokens, \\\n num_channels, \\\n expert_alignment, \\\n rdma_clean_meta.first, \\\n rdma_clean_meta.second, \\\n nvl_clean_meta.first, \\\n nvl_clean_meta.second, \\\n rdma_channel_prefix_matrix, \\\n recv_rdma_rank_prefix_sum, \\\n gbl_channel_prefix_matrix, \\\n recv_gbl_rank_prefix_sum, \\\n rdma_buffer_ptr, \\\n buffer_ptrs, \\\n barrier_signal_ptrs, \\\n rank, \\\n cpu_rdma_team); \\\n } \\\n break\n\n constexpr int kNumThreads = 512;\n const auto num_rdma_ranks = num_ranks / NUM_MAX_NVL_PEERS;\n\n // Get clean meta\n auto rdma_clean_meta =\n get_rdma_clean_meta(hidden_int4, num_scales, num_topk, num_topk, num_rdma_ranks, num_max_rdma_chunked_recv_tokens, num_channels);\n auto nvl_clean_meta = get_nvl_clean_meta(hidden_int4,\n num_scales,\n num_topk,\n num_topk,\n num_rdma_ranks,\n NUM_MAX_NVL_PEERS,\n num_max_nvl_chunked_recv_tokens,\n num_channels,\n true);\n EP_HOST_ASSERT((rdma_clean_meta.first + rdma_clean_meta.second) * sizeof(int) <= num_rdma_bytes);\n EP_HOST_ASSERT((nvl_clean_meta.first + nvl_clean_meta.second) * sizeof(int) <= num_nvl_bytes);\n EP_HOST_ASSERT(num_rdma_bytes < std::numeric_limits::max());\n EP_HOST_ASSERT(num_nvl_bytes < std::numeric_limits::max());\n\n // Launch kernel\n SETUP_LAUNCH_CONFIG(1 + num_rdma_ranks, kNumThreads, stream);\n SWITCH_RDMA_RANKS(NOTIFY_DISPATCH_LAUNCH_CASE);\n#undef NOTIFY_DISPATCH_LAUNCH_CASE\n}\n\n// At most 8 RDMA ranks to be sent\nconstexpr int get_num_topk_rdma_ranks(int num_rdma_ranks) {\n return num_rdma_ranks < 8 ? num_rdma_ranks : 8;\n}\n\ntemplate \n__global__ void __launch_bounds__(((kNumDispatchRDMASenderWarps + 1 + NUM_MAX_NVL_PEERS) * 32), 1)\n dispatch(int4* recv_x,\n float* recv_x_scales,\n topk_idx_t* recv_topk_idx,\n float* recv_topk_weights,\n SourceMeta* recv_src_meta,\n const int4* x,\n const float* x_scales,\n const topk_idx_t* topk_idx,\n const float* topk_weights,\n int* send_rdma_head,\n int* send_nvl_head,\n int* recv_rdma_channel_prefix_matrix,\n int* recv_gbl_channel_prefix_matrix,\n const int* rdma_channel_prefix_matrix,\n const int* recv_rdma_rank_prefix_sum,\n const int* gbl_channel_prefix_matrix,\n const int* recv_gbl_rank_prefix_sum,\n const bool* is_token_in_rank,\n int num_tokens,\n int num_worst_tokens,\n int hidden_int4,\n int num_scales,\n int num_topk,\n int num_experts,\n int scale_token_stride,\n int scale_hidden_stride,\n void* rdma_buffer_ptr,\n int num_max_rdma_chunked_send_tokens,\n int num_max_rdma_chunked_recv_tokens,\n void** buffer_ptrs,\n int num_max_nvl_chunked_send_tokens,\n int num_max_nvl_chunked_recv_tokens,\n int rank,\n int num_ranks) {\n enum class WarpRole { kRDMASender, kRDMASenderCoordinator, kRDMAAndNVLForwarder, kForwarderCoordinator, kNVLReceivers };\n\n const auto num_sms = static_cast(gridDim.x);\n const auto sm_id = static_cast(blockIdx.x);\n const auto num_threads = static_cast(blockDim.x), num_warps = num_threads / 32;\n const auto thread_id = static_cast(threadIdx.x), warp_id = thread_id / 32, lane_id = get_lane_id();\n const auto num_channels = num_sms / 2, channel_id = sm_id / 2;\n const bool is_forwarder = sm_id % 2 == 0;\n const auto rdma_rank = rank / NUM_MAX_NVL_PEERS, nvl_rank = rank % NUM_MAX_NVL_PEERS;\n\n EP_DEVICE_ASSERT(ibgda_get_state()->num_rc_per_pe == num_channels or ibgda_get_state()->num_rc_per_pe >= num_sms);\n\n const auto role_meta = [=]() -> std::pair {\n if (is_forwarder) {\n if (warp_id < NUM_MAX_NVL_PEERS) {\n return {WarpRole::kRDMAAndNVLForwarder, (warp_id + channel_id) % NUM_MAX_NVL_PEERS};\n } else {\n return {WarpRole::kForwarderCoordinator, warp_id - NUM_MAX_NVL_PEERS};\n }\n } else if (warp_id < kNumDispatchRDMASenderWarps) {\n return {WarpRole::kRDMASender, -1};\n } else if (warp_id == kNumDispatchRDMASenderWarps) {\n return {WarpRole::kRDMASenderCoordinator, -1};\n } else {\n return {WarpRole::kNVLReceivers, (warp_id + channel_id - kNumDispatchRDMASenderWarps) % NUM_MAX_NVL_PEERS};\n }\n }();\n auto warp_role = role_meta.first;\n auto target_rank = role_meta.second; // Not applicable for RDMA senders\n EP_DEVICE_ASSERT(num_warps == kNumDispatchRDMASenderWarps + 1 + NUM_MAX_NVL_PEERS);\n\n // Data checks\n EP_DEVICE_ASSERT(num_topk <= 32);\n\n // RDMA symmetric layout\n EP_STATIC_ASSERT(NUM_MAX_NVL_PEERS * sizeof(bool) == sizeof(uint64_t), \"Invalid number of NVL peers\");\n auto hidden_bytes = hidden_int4 * sizeof(int4);\n auto scale_bytes = num_scales * sizeof(float);\n auto num_bytes_per_token = get_num_bytes_per_token(hidden_int4, num_scales, num_topk, num_topk);\n auto rdma_channel_data = SymBuffer(\n rdma_buffer_ptr, num_max_rdma_chunked_recv_tokens * num_bytes_per_token, kNumRDMARanks, channel_id, num_channels);\n auto rdma_channel_meta = SymBuffer(rdma_buffer_ptr, NUM_MAX_NVL_PEERS * 2 + 2, kNumRDMARanks, channel_id, num_channels);\n auto rdma_channel_head = SymBuffer(rdma_buffer_ptr, 1, kNumRDMARanks, channel_id, num_channels);\n auto rdma_channel_tail = SymBuffer(rdma_buffer_ptr, 1, kNumRDMARanks, channel_id, num_channels);\n\n // NVL buffer layouts\n // NOTES: `rs_wr_buffer_ptr` means \"Read for Senders, Write for Receivers\", `ws_rr_buffer_ptr` means \"Write for Senders, Read for\n // Receivers\"\n void *rs_wr_buffer_ptr = nullptr, *ws_rr_buffer_ptr = nullptr;\n int rs_wr_rank = 0, ws_rr_rank = 0;\n if (warp_role == WarpRole::kRDMAAndNVLForwarder)\n rs_wr_buffer_ptr = buffer_ptrs[nvl_rank], ws_rr_buffer_ptr = buffer_ptrs[target_rank], rs_wr_rank = nvl_rank,\n ws_rr_rank = target_rank;\n if (warp_role == WarpRole::kNVLReceivers)\n rs_wr_buffer_ptr = buffer_ptrs[target_rank], ws_rr_buffer_ptr = buffer_ptrs[nvl_rank], rs_wr_rank = target_rank,\n ws_rr_rank = nvl_rank;\n\n // Allocate buffers\n auto nvl_channel_x = AsymBuffer(ws_rr_buffer_ptr,\n num_max_nvl_chunked_recv_tokens * num_bytes_per_token,\n NUM_MAX_NVL_PEERS,\n channel_id,\n num_channels,\n rs_wr_rank)\n .advance_also(rs_wr_buffer_ptr);\n auto nvl_channel_prefix_start =\n AsymBuffer(ws_rr_buffer_ptr, kNumRDMARanks, NUM_MAX_NVL_PEERS, channel_id, num_channels, rs_wr_rank)\n .advance_also(rs_wr_buffer_ptr);\n auto nvl_channel_prefix_end = AsymBuffer(ws_rr_buffer_ptr, kNumRDMARanks, NUM_MAX_NVL_PEERS, channel_id, num_channels, rs_wr_rank)\n .advance_also(rs_wr_buffer_ptr);\n auto nvl_channel_head =\n AsymBuffer(rs_wr_buffer_ptr, 1, NUM_MAX_NVL_PEERS, channel_id, num_channels, ws_rr_rank).advance_also(ws_rr_buffer_ptr);\n auto nvl_channel_tail =\n AsymBuffer(ws_rr_buffer_ptr, 1, NUM_MAX_NVL_PEERS, channel_id, num_channels, rs_wr_rank).advance_also(rs_wr_buffer_ptr);\n\n // RDMA sender warp synchronization\n // NOTES: `rdma_send_channel_tail` means the latest released tail\n // NOTES: `rdma_send_channel_window` means the ongoing 32 transactions' status\n __shared__ int rdma_send_channel_lock[kNumRDMARanks];\n __shared__ int rdma_send_channel_tail[kNumRDMARanks];\n __shared__ uint32_t rdma_send_channel_window[kNumRDMARanks];\n auto sync_rdma_sender_smem = []() { asm volatile(\"barrier.sync 0, %0;\" ::\"r\"((kNumDispatchRDMASenderWarps + 1) * 32)); };\n\n // TMA stuffs\n extern __shared__ __align__(1024) uint8_t smem_tma_buffer[];\n auto tma_buffer = smem_tma_buffer + target_rank * kNumTMABytesPerWarp;\n auto tma_mbarrier = reinterpret_cast(tma_buffer + num_bytes_per_token);\n uint32_t tma_phase = 0;\n if ((warp_role == WarpRole::kRDMAAndNVLForwarder or warp_role == WarpRole::kNVLReceivers) and elect_one_sync()) {\n mbarrier_init(tma_mbarrier, 1);\n fence_barrier_init();\n EP_DEVICE_ASSERT(num_bytes_per_token + sizeof(uint64_t) <= kNumTMABytesPerWarp);\n }\n __syncwarp();\n\n // Forward warp synchronization\n __shared__ volatile int forward_channel_head[NUM_MAX_NVL_PEERS][kNumRDMARanks];\n __shared__ volatile bool forward_channel_retired[NUM_MAX_NVL_PEERS];\n auto sync_forwarder_smem = []() { asm volatile(\"barrier.sync 1, %0;\" ::\"r\"((NUM_MAX_NVL_PEERS + 1) * 32)); };\n\n if (warp_role == WarpRole::kRDMASender) {\n // Get tasks\n int token_start_idx, token_end_idx;\n get_channel_task_range(num_tokens, num_channels, channel_id, token_start_idx, token_end_idx);\n\n // Send number of tokens in this channel by `-value - 1`\n EP_STATIC_ASSERT(NUM_MAX_NVL_PEERS * 2 + 2 <= 32, \"Invalid number of NVL peers\");\n for (int dst_rdma_rank = warp_id; dst_rdma_rank < kNumRDMARanks; dst_rdma_rank += kNumDispatchRDMASenderWarps) {\n auto dst_ptr =\n dst_rdma_rank == rdma_rank ? rdma_channel_meta.recv_buffer(dst_rdma_rank) : rdma_channel_meta.send_buffer(dst_rdma_rank);\n if (lane_id < NUM_MAX_NVL_PEERS) {\n dst_ptr[lane_id] =\n -(channel_id == 0\n ? 0\n : gbl_channel_prefix_matrix[(dst_rdma_rank * NUM_MAX_NVL_PEERS + lane_id) * num_channels + channel_id - 1]) -\n 1;\n } else if (lane_id < NUM_MAX_NVL_PEERS * 2) {\n dst_ptr[lane_id] =\n -gbl_channel_prefix_matrix[(dst_rdma_rank * NUM_MAX_NVL_PEERS + lane_id - NUM_MAX_NVL_PEERS) * num_channels +\n channel_id] -\n 1;\n } else if (lane_id == NUM_MAX_NVL_PEERS * 2) {\n dst_ptr[lane_id] = -(channel_id == 0 ? 0 : rdma_channel_prefix_matrix[dst_rdma_rank * num_channels + channel_id - 1]) - 1;\n } else if (lane_id == NUM_MAX_NVL_PEERS * 2 + 1) {\n dst_ptr[lane_id] = -rdma_channel_prefix_matrix[dst_rdma_rank * num_channels + channel_id] - 1;\n }\n __syncwarp();\n\n // Issue RDMA for non-local ranks\n if (dst_rdma_rank != rdma_rank) {\n nvshmemi_ibgda_put_nbi_warp(reinterpret_cast(rdma_channel_meta.recv_buffer(rdma_rank)),\n reinterpret_cast(rdma_channel_meta.send_buffer(dst_rdma_rank)),\n sizeof(int) * (NUM_MAX_NVL_PEERS * 2 + 2),\n translate_dst_rdma_rank(dst_rdma_rank, nvl_rank),\n channel_id,\n lane_id,\n 0);\n }\n }\n sync_rdma_sender_smem();\n\n // Iterate over tokens and copy into buffer\n int64_t token_idx;\n int cached_rdma_channel_head = 0, global_rdma_tail_idx = 0;\n auto send_buffer = lane_id == rdma_rank ? rdma_channel_data.recv_buffer(lane_id) : rdma_channel_data.send_buffer(lane_id);\n for (token_idx = token_start_idx; token_idx < token_end_idx; ++token_idx) {\n // Read RDMA rank existence\n uint64_t is_token_in_rank_uint64 = 0;\n if (lane_id < kNumRDMARanks) {\n is_token_in_rank_uint64 =\n __ldg(reinterpret_cast(is_token_in_rank + token_idx * num_ranks + lane_id * NUM_MAX_NVL_PEERS));\n global_rdma_tail_idx += (is_token_in_rank_uint64 != 0);\n }\n __syncwarp();\n\n // Skip the token which does not belong to this warp\n if ((token_idx - token_start_idx) % kNumDispatchRDMASenderWarps != warp_id)\n continue;\n auto rdma_tail_idx = is_token_in_rank_uint64 == 0 ? -1 : global_rdma_tail_idx - 1;\n\n // Wait the remote buffer to be released\n auto start_time = clock64();\n while (is_token_in_rank_uint64 != 0 and rdma_tail_idx - cached_rdma_channel_head >= num_max_rdma_chunked_recv_tokens) {\n cached_rdma_channel_head = static_cast(ld_volatile_global(rdma_channel_head.buffer(lane_id)));\n\n // Timeout check\n if (clock64() - start_time >= NUM_TIMEOUT_CYCLES) {\n printf(\"DeepEP dispatch RDMA sender timeout, channel: %d, RDMA: %d, nvl: %d, dst RDMA lane: %d, head: %d, tail: %d\\n\",\n channel_id,\n rdma_rank,\n nvl_rank,\n lane_id,\n cached_rdma_channel_head,\n rdma_tail_idx);\n trap();\n }\n }\n __syncwarp();\n\n // Store RDMA head for combine\n if (lane_id < kNumRDMARanks and not kCachedMode)\n send_rdma_head[token_idx * kNumRDMARanks + lane_id] = rdma_tail_idx;\n\n // Broadcast tails\n SourceMeta src_meta;\n int num_topk_ranks = 0, topk_ranks[kNumTopkRDMARanks];\n void* dst_send_buffers[kNumTopkRDMARanks];\n #pragma unroll\n for (int i = 0, slot_idx; i < kNumRDMARanks; ++i)\n if ((slot_idx = __shfl_sync(0xffffffff, rdma_tail_idx, i)) >= 0) {\n slot_idx = slot_idx % num_max_rdma_chunked_recv_tokens;\n topk_ranks[num_topk_ranks] = i;\n auto recv_is_token_in_rank_uint64 = broadcast(is_token_in_rank_uint64, i);\n auto recv_is_token_in_rank_values = reinterpret_cast(&recv_is_token_in_rank_uint64);\n if (lane_id == num_topk_ranks)\n src_meta = SourceMeta(rdma_rank, recv_is_token_in_rank_values);\n dst_send_buffers[num_topk_ranks++] =\n reinterpret_cast(broadcast(send_buffer, i)) + slot_idx * num_bytes_per_token;\n }\n EP_DEVICE_ASSERT(num_topk_ranks <= kNumTopkRDMARanks);\n\n // Copy `x` into symmetric send buffer\n auto st_broadcast = [=](const int key, const int4& value) {\n #pragma unroll\n for (int j = 0; j < num_topk_ranks; ++j)\n st_na_global(reinterpret_cast(dst_send_buffers[j]) + key, value);\n };\n UNROLLED_WARP_COPY(5, lane_id, hidden_int4, 0, x + token_idx * hidden_int4, ld_nc_global, st_broadcast);\n #pragma unroll\n for (int i = 0; i < num_topk_ranks; ++i)\n dst_send_buffers[i] = reinterpret_cast(dst_send_buffers[i]) + hidden_int4;\n\n // Copy `x_scales` into symmetric send buffer\n #pragma unroll\n for (int i = lane_id; i < num_scales; i += 32) {\n auto offset = token_idx * scale_token_stride + i * scale_hidden_stride;\n auto value = ld_nc_global(x_scales + offset);\n #pragma unroll\n for (int j = 0; j < num_topk_ranks; ++j)\n st_na_global(reinterpret_cast(dst_send_buffers[j]) + i, value);\n }\n #pragma unroll\n for (int i = 0; i < num_topk_ranks; ++i)\n dst_send_buffers[i] = reinterpret_cast(dst_send_buffers[i]) + num_scales;\n\n // Copy source metadata into symmetric send buffer\n if (lane_id < num_topk_ranks)\n st_na_global(reinterpret_cast(dst_send_buffers[lane_id]), src_meta);\n #pragma unroll\n for (int i = 0; i < num_topk_ranks; ++i)\n dst_send_buffers[i] = reinterpret_cast(dst_send_buffers[i]) + 1;\n\n // Copy `topk_idx` and `topk_weights` into symmetric send buffer\n #pragma unroll\n for (int i = lane_id; i < num_topk * num_topk_ranks; i += 32) {\n auto rank_idx = i / num_topk, copy_idx = i % num_topk;\n auto idx_value = static_cast(ld_nc_global(topk_idx + token_idx * num_topk + copy_idx));\n auto weight_value = ld_nc_global(topk_weights + token_idx * num_topk + copy_idx);\n st_na_global(reinterpret_cast(dst_send_buffers[rank_idx]) + copy_idx, idx_value);\n st_na_global(reinterpret_cast(dst_send_buffers[rank_idx]) + num_topk + copy_idx, weight_value);\n }\n __syncwarp();\n\n // Release the transaction in the window\n if (is_token_in_rank_uint64 != 0) {\n // Acquire lock first\n acquire_lock(rdma_send_channel_lock + lane_id);\n auto latest_tail = rdma_send_channel_tail[lane_id];\n auto offset = rdma_tail_idx - latest_tail;\n while (offset >= 32) {\n release_lock(rdma_send_channel_lock + lane_id);\n acquire_lock(rdma_send_channel_lock + lane_id);\n latest_tail = rdma_send_channel_tail[lane_id];\n offset = rdma_tail_idx - latest_tail;\n }\n\n // Release the transaction slot\n // Add the bit and move the ones if possible\n auto window = rdma_send_channel_window[lane_id] | (1u << offset);\n if (offset == 0) {\n auto num_empty_slots = (~window) == 0 ? 32 : __ffs(~window) - 1;\n st_release_cta(rdma_send_channel_tail + lane_id, latest_tail + num_empty_slots);\n window >>= num_empty_slots;\n }\n rdma_send_channel_window[lane_id] = window;\n\n // Release lock\n release_lock(rdma_send_channel_lock + lane_id);\n }\n __syncwarp();\n }\n } else if (warp_role == WarpRole::kRDMASenderCoordinator) {\n // NOTES: in case of splitting, the issued put at the end of the buffer\n EP_DEVICE_ASSERT(num_max_rdma_chunked_recv_tokens % num_max_rdma_chunked_send_tokens == 0);\n\n // Clean shared memory\n EP_STATIC_ASSERT(kNumRDMARanks <= 32, \"Invalid number of RDMA ranks\");\n (lane_id < kNumRDMARanks) ? (rdma_send_channel_lock[lane_id] = 0) : 0;\n (lane_id < kNumRDMARanks) ? (rdma_send_channel_tail[lane_id] = 0) : 0;\n (lane_id < kNumRDMARanks) ? (rdma_send_channel_window[lane_id] = 0) : 0;\n\n // Synchronize shared memory\n sync_rdma_sender_smem();\n\n // Get number of tokens to send for each RDMA rank\n int num_tokens_to_send = 0;\n if (lane_id < kNumRDMARanks) {\n num_tokens_to_send = rdma_channel_prefix_matrix[lane_id * num_channels + channel_id];\n if (channel_id > 0)\n num_tokens_to_send -= rdma_channel_prefix_matrix[lane_id * num_channels + channel_id - 1];\n }\n\n // Iterate all RDMA ranks\n int last_issued_tail = 0;\n auto start_time = clock64();\n while (__any_sync(0xffffffff, num_tokens_to_send > 0)) {\n // Timeout check\n if (clock64() - start_time > NUM_TIMEOUT_CYCLES and lane_id < kNumRDMARanks) {\n printf(\"DeepEP RDMA sender coordinator timeout, channel: %d, IB: %d, nvl %d, dst IB: %d, tail: %d, remaining: %d\\n\",\n channel_id,\n rdma_rank,\n nvl_rank,\n lane_id,\n last_issued_tail,\n num_tokens_to_send);\n trap();\n }\n\n // TODO: try thread-level `put_nbi`?\n for (int i = 0, synced_num_tokens_to_send; i < kNumRDMARanks; ++i) {\n // To mitigate incast congestion, shuffle the starting index of target rank for different ranks and channels\n int dst_rdma_rank = (i + channel_id + rdma_rank) % kNumRDMARanks;\n synced_num_tokens_to_send = __shfl_sync(0xffffffff, num_tokens_to_send, dst_rdma_rank);\n if (synced_num_tokens_to_send == 0)\n continue;\n\n // Read the latest progress\n // NOTES: `rdma_send_channel_tail` does not need to be protected by lock\n auto processed_tail =\n __shfl_sync(0xffffffff, ld_acquire_cta(const_cast(rdma_send_channel_tail + dst_rdma_rank)), 0);\n auto synced_last_issued_tail = __shfl_sync(0xffffffff, last_issued_tail, dst_rdma_rank);\n auto num_tokens_processed = processed_tail - synced_last_issued_tail;\n if (num_tokens_processed != synced_num_tokens_to_send and num_tokens_processed < num_max_rdma_chunked_send_tokens)\n continue;\n\n // Issue RDMA send\n auto num_tokens_to_issue = min(num_tokens_processed, num_max_rdma_chunked_send_tokens);\n EP_DEVICE_ASSERT(num_tokens_to_issue >= 0 and num_tokens_to_issue <= synced_num_tokens_to_send);\n if (dst_rdma_rank != rdma_rank) {\n auto dst_slot_idx = synced_last_issued_tail % num_max_rdma_chunked_recv_tokens;\n EP_DEVICE_ASSERT(dst_slot_idx + num_tokens_to_issue <= num_max_rdma_chunked_recv_tokens);\n const size_t num_bytes_per_msg = num_bytes_per_token * num_tokens_to_issue;\n const auto dst_ptr =\n reinterpret_cast(rdma_channel_data.recv_buffer(rdma_rank) + dst_slot_idx * num_bytes_per_token);\n const auto src_ptr =\n reinterpret_cast(rdma_channel_data.send_buffer(dst_rdma_rank) + dst_slot_idx * num_bytes_per_token);\n nvshmemi_ibgda_put_nbi_warp(dst_ptr,\n src_ptr,\n num_bytes_per_msg,\n translate_dst_rdma_rank(dst_rdma_rank, nvl_rank),\n channel_id,\n lane_id,\n 0);\n } else {\n // Lighter fence for local RDMA rank\n memory_fence();\n }\n __syncwarp();\n\n // Update tails\n if (lane_id == dst_rdma_rank) {\n last_issued_tail += num_tokens_to_issue;\n num_tokens_to_send -= num_tokens_to_issue;\n nvshmemi_ibgda_amo_nonfetch_add(rdma_channel_tail.buffer(rdma_rank),\n num_tokens_to_issue,\n translate_dst_rdma_rank(dst_rdma_rank, nvl_rank),\n channel_id,\n dst_rdma_rank == rdma_rank);\n }\n __syncwarp();\n }\n }\n } else if (warp_role == WarpRole::kRDMAAndNVLForwarder) {\n // RDMA consumers and NVL producers\n const auto dst_nvl_rank = target_rank;\n\n // Wait counters to arrive\n int num_tokens_to_recv_from_rdma = 0, src_rdma_channel_prefix = 0;\n EP_DEVICE_ASSERT(kNumRDMARanks <= 32);\n auto start_time = clock64();\n if (lane_id < kNumRDMARanks) {\n while (true) {\n auto meta_0 = ld_volatile_global(rdma_channel_meta.recv_buffer(lane_id) + dst_nvl_rank);\n auto meta_1 = ld_volatile_global(rdma_channel_meta.recv_buffer(lane_id) + NUM_MAX_NVL_PEERS + dst_nvl_rank);\n auto meta_2 = ld_volatile_global(rdma_channel_meta.recv_buffer(lane_id) + NUM_MAX_NVL_PEERS * 2);\n auto meta_3 = ld_volatile_global(rdma_channel_meta.recv_buffer(lane_id) + NUM_MAX_NVL_PEERS * 2 + 1);\n if (meta_0 < 0 and meta_1 < 0 and meta_2 < 0 and meta_3 < 0) {\n // Notify NVL ranks\n int start_sum = -meta_0 - 1, end_sum = -meta_1 - 1;\n EP_DEVICE_ASSERT(start_sum >= 0 and end_sum >= 0 and end_sum >= start_sum);\n st_relaxed_sys_global(nvl_channel_prefix_start.buffer() + lane_id, -start_sum - 1);\n st_relaxed_sys_global(nvl_channel_prefix_end.buffer() + lane_id, -end_sum - 1);\n\n // Save RDMA channel received token count\n src_rdma_channel_prefix = -meta_2 - 1;\n auto src_rdma_channel_prefix_1 = -meta_3 - 1;\n num_tokens_to_recv_from_rdma = src_rdma_channel_prefix_1 - src_rdma_channel_prefix;\n if (not kCachedMode)\n recv_rdma_channel_prefix_matrix[lane_id * num_channels + channel_id] = src_rdma_channel_prefix_1;\n src_rdma_channel_prefix += lane_id == 0 ? 0 : recv_rdma_rank_prefix_sum[lane_id - 1];\n EP_DEVICE_ASSERT(num_tokens_to_recv_from_rdma >= 0);\n break;\n }\n\n // Timeout check\n if (clock64() - start_time > NUM_TIMEOUT_CYCLES) {\n printf(\n \"DeepEP dispatch forwarder timeout (RDMA meta), channel: %d, RDMA: %d, nvl: %d, src RDMA lane: %d, dst NVL: %d, \"\n \"meta: %d, %d, %d, %d\\n\",\n channel_id,\n rdma_rank,\n nvl_rank,\n lane_id,\n dst_nvl_rank,\n meta_0,\n meta_1,\n meta_2,\n meta_3);\n trap();\n }\n }\n }\n __syncwarp();\n\n // Shift cached head\n send_nvl_head += src_rdma_channel_prefix * NUM_MAX_NVL_PEERS + dst_nvl_rank;\n\n // Wait shared memory to be cleaned\n sync_forwarder_smem();\n\n // Forward tokens from RDMA buffer\n // NOTES: always start from the local rank\n int src_rdma_rank = sm_id % kNumRDMARanks;\n int cached_rdma_channel_head = 0, cached_rdma_channel_tail = 0;\n int cached_nvl_channel_head = 0, cached_nvl_channel_tail = 0, rdma_nvl_token_idx = 0;\n while (__any_sync(0xffffffff, num_tokens_to_recv_from_rdma > 0)) {\n // Check destination queue emptiness, or wait a buffer to be released\n start_time = clock64();\n while (true) {\n const int num_used_slots = cached_nvl_channel_tail - cached_nvl_channel_head;\n if (num_max_nvl_chunked_recv_tokens - num_used_slots >= num_max_nvl_chunked_send_tokens)\n break;\n cached_nvl_channel_head = __shfl_sync(0xffffffffu, ld_volatile_global(nvl_channel_head.buffer()), 0);\n\n // Timeout check\n if (elect_one_sync() and clock64() - start_time > NUM_TIMEOUT_CYCLES) {\n printf(\n \"DeepEP dispatch forwarder timeout (NVL check), channel: %d, RDMA: %d, nvl: %d, dst NVL: %d, head: %d, tail: %d\\n\",\n channel_id,\n rdma_rank,\n nvl_rank,\n dst_nvl_rank,\n ld_volatile_global(nvl_channel_head.buffer()),\n cached_nvl_channel_tail);\n trap();\n }\n }\n\n // Find next source RDMA rank (round-robin)\n start_time = clock64();\n while (true) {\n src_rdma_rank = (src_rdma_rank + 1) % kNumRDMARanks;\n if (__shfl_sync(0xffffffff, num_tokens_to_recv_from_rdma, src_rdma_rank) > 0) {\n if (lane_id == src_rdma_rank and cached_rdma_channel_head == cached_rdma_channel_tail)\n cached_rdma_channel_tail = static_cast(ld_acquire_sys_global(rdma_channel_tail.buffer(src_rdma_rank)));\n if (__shfl_sync(0xffffffff, cached_rdma_channel_tail > cached_rdma_channel_head, src_rdma_rank))\n break;\n }\n\n // Timeout check\n if (clock64() - start_time > NUM_TIMEOUT_CYCLES and lane_id < kNumRDMARanks) {\n printf(\n \"DeepEP dispatch forwarder timeout (RDMA check), channel: %d, RDMA: %d, nvl: %d, dst NVL: %d, src RDMA lane: %d, \"\n \"head: %d, tail: %d, expected: %d\\n\",\n channel_id,\n rdma_rank,\n nvl_rank,\n dst_nvl_rank,\n lane_id,\n cached_rdma_channel_head,\n cached_rdma_channel_tail,\n num_tokens_to_recv_from_rdma);\n trap();\n }\n }\n auto src_rdma_head = __shfl_sync(0xffffffff, cached_rdma_channel_head, src_rdma_rank);\n auto src_rdma_tail = __shfl_sync(0xffffffff, cached_rdma_channel_tail, src_rdma_rank);\n\n // Iterate over every token from the RDMA buffer\n for (int i = src_rdma_head, num_tokens_sent = 0; i < src_rdma_tail; ++i) {\n auto rdma_slot_idx = i % num_max_rdma_chunked_recv_tokens;\n auto shifted = rdma_channel_data.recv_buffer(src_rdma_rank) + rdma_slot_idx * num_bytes_per_token;\n auto src_meta = ld_nc_global(reinterpret_cast(shifted + hidden_bytes + scale_bytes));\n lane_id == src_rdma_rank ? (num_tokens_to_recv_from_rdma -= 1) : 0;\n bool is_in_dst_nvl_rank = src_meta.is_token_in_nvl_rank(dst_nvl_rank);\n if (lane_id == src_rdma_rank) {\n auto cached_head = is_in_dst_nvl_rank ? rdma_nvl_token_idx : -1;\n rdma_nvl_token_idx += is_in_dst_nvl_rank;\n if (not kCachedMode)\n send_nvl_head[i * NUM_MAX_NVL_PEERS] = cached_head;\n }\n if (not is_in_dst_nvl_rank)\n continue;\n\n // Get an empty slot\n int dst_slot_idx = (cached_nvl_channel_tail++) % num_max_nvl_chunked_recv_tokens;\n auto dst_shifted = nvl_channel_x.buffer() + dst_slot_idx * num_bytes_per_token;\n\n // Copy data\n if (elect_one_sync()) {\n tma_load_1d(tma_buffer, shifted, tma_mbarrier, num_bytes_per_token, false);\n mbarrier_arrive_and_expect_tx(tma_mbarrier, num_bytes_per_token);\n }\n __syncwarp();\n mbarrier_wait(tma_mbarrier, tma_phase);\n if (elect_one_sync())\n tma_store_1d(tma_buffer, dst_shifted, num_bytes_per_token);\n __syncwarp();\n\n // In case of insufficient NVL buffers, early stopping\n if ((++num_tokens_sent) == num_max_nvl_chunked_send_tokens)\n src_rdma_tail = i + 1;\n\n // Wait TMA to be finished\n tma_store_wait<0>();\n __syncwarp();\n }\n\n // Sync head index\n if (lane_id == src_rdma_rank)\n forward_channel_head[dst_nvl_rank][src_rdma_rank] = (cached_rdma_channel_head = src_rdma_tail);\n\n // Move tail index\n __syncwarp();\n if (elect_one_sync())\n st_release_sys_global(nvl_channel_tail.buffer(), cached_nvl_channel_tail);\n }\n\n // Retired\n __syncwarp();\n if (elect_one_sync())\n forward_channel_retired[dst_nvl_rank] = true;\n } else if (warp_role == WarpRole::kForwarderCoordinator) {\n // Extra warps for forwarder coordinator should exit directly\n if (target_rank > 0)\n return;\n\n // Forward warp coordinator\n EP_STATIC_ASSERT(kNumRDMARanks <= 32, \"Invalid number of RDMA peers\");\n\n // Clean shared memory\n EP_STATIC_ASSERT(NUM_MAX_NVL_PEERS <= 32, \"Invalid number of NVL peers\");\n #pragma unroll\n for (int i = lane_id; i < kNumRDMARanks * NUM_MAX_NVL_PEERS; i += 32)\n forward_channel_head[i % NUM_MAX_NVL_PEERS][i / NUM_MAX_NVL_PEERS] = 0;\n if (lane_id < NUM_MAX_NVL_PEERS)\n forward_channel_retired[lane_id] = false;\n sync_forwarder_smem();\n\n int last_head = 0, target_rdma = lane_id < kNumRDMARanks ? lane_id : 0;\n while (true) {\n // Find minimum head\n int min_head = std::numeric_limits::max();\n #pragma unroll\n for (int i = 0; i < NUM_MAX_NVL_PEERS; ++i)\n if (not forward_channel_retired[i])\n min_head = min(min_head, forward_channel_head[i][target_rdma]);\n if (__all_sync(0xffffffff, min_head == std::numeric_limits::max()))\n break;\n\n // Update remote head\n if (min_head != std::numeric_limits::max() and min_head >= last_head + num_max_rdma_chunked_send_tokens and\n lane_id < kNumRDMARanks) {\n nvshmemi_ibgda_amo_nonfetch_add(rdma_channel_head.buffer(rdma_rank),\n min_head - last_head,\n translate_dst_rdma_rank(lane_id, nvl_rank),\n channel_id + num_channels,\n lane_id == rdma_rank);\n last_head = min_head;\n }\n\n // Nanosleep and let other warps work\n __nanosleep(NUM_WAIT_NANOSECONDS);\n }\n } else {\n // NVL consumers\n // Retrieve rank offset from barrier results (each lane's register stores an RDMA rank)\n int src_nvl_rank = target_rank, total_offset = 0;\n const int local_expert_begin = rank * (num_experts / num_ranks);\n const int local_expert_end = local_expert_begin + (num_experts / num_ranks);\n\n EP_STATIC_ASSERT(kNumRDMARanks <= 32, \"Invalid number of RDMA peers\");\n if (lane_id < kNumRDMARanks and lane_id * NUM_MAX_NVL_PEERS + src_nvl_rank > 0)\n total_offset = recv_gbl_rank_prefix_sum[lane_id * NUM_MAX_NVL_PEERS + src_nvl_rank - 1];\n\n // Receive channel offsets\n int start_offset = 0, end_offset = 0, num_tokens_to_recv;\n auto start_time = clock64();\n while (lane_id < kNumRDMARanks) {\n start_offset = ld_volatile_global(nvl_channel_prefix_start.buffer() + lane_id);\n end_offset = ld_volatile_global(nvl_channel_prefix_end.buffer() + lane_id);\n if (start_offset < 0 and end_offset < 0) {\n start_offset = -start_offset - 1, end_offset = -end_offset - 1;\n total_offset += start_offset;\n break;\n }\n\n // Timeout check\n if (clock64() - start_time > NUM_TIMEOUT_CYCLES) {\n printf(\n \"DeepEP dispatch NVL receiver timeout, channel: %d, RDMA: %d, nvl: %d, src RDMA: %d, src nvl: %d, start: %d, end: %d\\n\",\n channel_id,\n rdma_rank,\n nvl_rank,\n lane_id,\n src_nvl_rank,\n start_offset,\n end_offset);\n trap();\n }\n }\n num_tokens_to_recv = warp_reduce_sum(end_offset - start_offset);\n\n // Save for combine usage\n if (lane_id < kNumRDMARanks and not kCachedMode)\n recv_gbl_channel_prefix_matrix[(lane_id * NUM_MAX_NVL_PEERS + src_nvl_rank) * num_channels + channel_id] = total_offset;\n __syncwarp();\n\n int cached_channel_head_idx = 0, cached_channel_tail_idx = 0;\n while (num_tokens_to_recv > 0) {\n // Check channel status by lane 0\n start_time = clock64();\n while (true) {\n // Ready to copy\n if (cached_channel_head_idx != cached_channel_tail_idx)\n break;\n cached_channel_tail_idx = __shfl_sync(0xffffffff, ld_acquire_sys_global(nvl_channel_tail.buffer()), 0);\n\n // Timeout check\n if (elect_one_sync() and clock64() - start_time > NUM_TIMEOUT_CYCLES) {\n printf(\"DeepEP dispatch NVL receiver timeout, channel: %d, RDMA: %d, nvl: %d, src NVL: %d, head: %d, tail: %d\\n\",\n channel_id,\n rdma_rank,\n nvl_rank,\n src_nvl_rank,\n cached_channel_head_idx,\n cached_channel_tail_idx);\n trap();\n }\n }\n\n // Copy data\n int num_recv_tokens = cached_channel_tail_idx - cached_channel_head_idx;\n for (int chunk_idx = 0; chunk_idx < num_recv_tokens; ++chunk_idx, --num_tokens_to_recv) {\n int token_idx_in_buffer = (cached_channel_head_idx++) % num_max_nvl_chunked_recv_tokens;\n auto shifted = nvl_channel_x.buffer() + token_idx_in_buffer * num_bytes_per_token;\n auto meta = ld_nc_global(reinterpret_cast(shifted + hidden_bytes + scale_bytes));\n int64_t recv_token_idx = __shfl_sync(0xffffffff, total_offset, meta.src_rdma_rank);\n (lane_id == meta.src_rdma_rank) ? (total_offset += 1) : 0;\n\n bool scale_aligned = (scale_bytes % 16 == 0);\n auto tma_load_bytes = hidden_bytes + (scale_aligned ? scale_bytes : 0);\n\n // Copy data\n if (elect_one_sync()) {\n tma_load_1d(tma_buffer, shifted, tma_mbarrier, tma_load_bytes);\n mbarrier_arrive_and_expect_tx(tma_mbarrier, tma_load_bytes);\n }\n __syncwarp();\n mbarrier_wait(tma_mbarrier, tma_phase);\n if (elect_one_sync()) {\n tma_store_1d(tma_buffer, recv_x + recv_token_idx * hidden_int4, hidden_bytes, false);\n if (scale_aligned)\n tma_store_1d(tma_buffer + hidden_bytes, recv_x_scales + recv_token_idx * num_scales, scale_bytes, false);\n }\n __syncwarp();\n shifted += hidden_bytes;\n\n // Copy scales\n // TODO: make it as templated\n if (not scale_aligned) {\n UNROLLED_WARP_COPY(1,\n lane_id,\n num_scales,\n recv_x_scales + recv_token_idx * num_scales,\n reinterpret_cast(shifted),\n ld_nc_global,\n st_na_global);\n }\n shifted += scale_bytes;\n\n // Copy source meta\n if (not kCachedMode and elect_one_sync())\n st_na_global(recv_src_meta + recv_token_idx, meta);\n shifted += sizeof(SourceMeta);\n\n // Copy `topk_idx` and `topk_weights`\n if (lane_id < num_topk) {\n // Read\n auto idx_value = static_cast(ld_nc_global(reinterpret_cast(shifted) + lane_id));\n auto weight_value = ld_nc_global(reinterpret_cast(shifted + sizeof(int) * num_topk) + lane_id);\n auto recv_idx = recv_token_idx * num_topk + lane_id;\n\n // Transform and write\n idx_value = (idx_value >= local_expert_begin and idx_value < local_expert_end) ? idx_value - local_expert_begin : -1;\n weight_value = idx_value >= 0 ? weight_value : 0.0f;\n st_na_global(recv_topk_idx + recv_idx, idx_value);\n st_na_global(recv_topk_weights + recv_idx, weight_value);\n }\n\n // Wait TMA to be finished\n tma_store_wait<0>();\n __syncwarp();\n }\n\n // Move queue\n if (elect_one_sync())\n st_relaxed_sys_global(nvl_channel_head.buffer(), cached_channel_head_idx);\n }\n }\n\n // Clean unused `recv_topk_idx` as -1\n if (num_worst_tokens > 0) {\n if (is_forwarder)\n return;\n // get the actual number of num_recv_tokens on the current rank\n int num_recv_tokens = recv_gbl_rank_prefix_sum[num_ranks - 1];\n // some ForwarderCoordinator threads exit early, so we only use non-forwarder in clean-up\n // channel_id * num_threads is the offset of the current non-forwarder sms\n const auto clean_start = num_recv_tokens * num_topk + channel_id * num_threads;\n const auto clean_end = num_worst_tokens * num_topk;\n const auto clean_stride = num_channels * num_threads;\n #pragma unroll\n for (int i = clean_start + thread_id; i < clean_end; i += clean_stride)\n recv_topk_idx[i] = -1;\n }\n}\n\nvoid dispatch(void* recv_x,\n float* recv_x_scales,\n topk_idx_t* recv_topk_idx,\n float* recv_topk_weights,\n void* recv_src_meta,\n const void* x,\n const float* x_scales,\n const topk_idx_t* topk_idx,\n const float* topk_weights,\n int* send_rdma_head,\n int* send_nvl_head,\n int* recv_rdma_channel_prefix_matrix,\n int* recv_gbl_channel_prefix_matrix,\n const int* rdma_channel_prefix_matrix,\n const int* recv_rdma_rank_prefix_sum,\n const int* gbl_channel_prefix_matrix,\n const int* recv_gbl_rank_prefix_sum,\n const bool* is_token_in_rank,\n int num_tokens,\n int num_worst_tokens,\n int hidden_int4,\n int num_scales,\n int num_topk,\n int num_experts,\n int scale_token_stride,\n int scale_hidden_stride,\n void* rdma_buffer_ptr,\n int num_max_rdma_chunked_send_tokens,\n int num_max_rdma_chunked_recv_tokens,\n void** buffer_ptrs,\n int num_max_nvl_chunked_send_tokens,\n int num_max_nvl_chunked_recv_tokens,\n int rank,\n int num_ranks,\n bool is_cached_dispatch,\n cudaStream_t stream,\n int num_channels,\n bool low_latency_mode) {\n constexpr int kNumDispatchRDMASenderWarps = 7;\n constexpr int kNumTMABytesPerWarp = 16384;\n constexpr int smem_size = kNumTMABytesPerWarp * NUM_MAX_NVL_PEERS;\n\n // Make sure never OOB\n EP_HOST_ASSERT(static_cast(num_scales) * scale_hidden_stride < std::numeric_limits::max());\n\n#define DISPATCH_LAUNCH_CASE(num_rdma_ranks) \\\n { \\\n auto dispatch_func = low_latency_mode \\\n ? (is_cached_dispatch ? dispatch \\\n : dispatch) \\\n : (is_cached_dispatch ? dispatch \\\n : dispatch); \\\n SET_SHARED_MEMORY_FOR_TMA(dispatch_func); \\\n LAUNCH_KERNEL(&cfg, \\\n dispatch_func, \\\n reinterpret_cast(recv_x), \\\n recv_x_scales, \\\n recv_topk_idx, \\\n recv_topk_weights, \\\n reinterpret_cast(recv_src_meta), \\\n reinterpret_cast(x), \\\n x_scales, \\\n topk_idx, \\\n topk_weights, \\\n send_rdma_head, \\\n send_nvl_head, \\\n recv_rdma_channel_prefix_matrix, \\\n recv_gbl_channel_prefix_matrix, \\\n rdma_channel_prefix_matrix, \\\n recv_rdma_rank_prefix_sum, \\\n gbl_channel_prefix_matrix, \\\n recv_gbl_rank_prefix_sum, \\\n is_token_in_rank, \\\n num_tokens, \\\n num_worst_tokens, \\\n hidden_int4, \\\n num_scales, \\\n num_topk, \\\n num_experts, \\\n scale_token_stride, \\\n scale_hidden_stride, \\\n rdma_buffer_ptr, \\\n num_max_rdma_chunked_send_tokens, \\\n num_max_rdma_chunked_recv_tokens, \\\n buffer_ptrs, \\\n num_max_nvl_chunked_send_tokens, \\\n num_max_nvl_chunked_recv_tokens, \\\n rank, \\\n num_ranks); \\\n } \\\n break\n\n EP_HOST_ASSERT((topk_idx == nullptr) == (topk_weights == nullptr));\n EP_HOST_ASSERT((recv_topk_idx == nullptr) == (recv_topk_weights == nullptr));\n\n SETUP_LAUNCH_CONFIG(num_channels * 2, (kNumDispatchRDMASenderWarps + 1 + NUM_MAX_NVL_PEERS) * 32, stream);\n SWITCH_RDMA_RANKS(DISPATCH_LAUNCH_CASE);\n#undef DISPATCH_LAUNCH_CASE\n}\n\ntemplate \n__global__ void cached_notify(const int rdma_clean_offset,\n const int rdma_num_int_clean,\n const int nvl_clean_offset,\n const int nvl_num_int_clean,\n int* combined_rdma_head,\n int num_combined_tokens,\n int num_channels,\n const int* rdma_channel_prefix_matrix,\n const int* rdma_rank_prefix_sum,\n int* combined_nvl_head,\n void* rdma_buffer_ptr,\n void** buffer_ptrs,\n int** barrier_signal_ptrs,\n int rank,\n int num_ranks,\n bool is_cached_dispatch,\n const nvshmem_team_t rdma_team) {\n auto sm_id = static_cast(blockIdx.x);\n auto thread_id = static_cast(threadIdx.x);\n auto num_threads = static_cast(blockDim.x);\n auto num_warps = num_threads / 32;\n auto warp_id = thread_id / 32;\n auto lane_id = get_lane_id();\n\n auto nvl_rank = rank % NUM_MAX_NVL_PEERS;\n auto num_rdma_ranks = num_ranks / NUM_MAX_NVL_PEERS;\n auto rdma_rank = rank / NUM_MAX_NVL_PEERS;\n\n // Using two SMs, which clean the RDMA/NVL buffer respectively\n if (sm_id == 0) {\n auto qps_per_rdma_rank = ibgda_get_state()->num_rc_per_pe * ibgda_get_state()->num_devices_initialized;\n for (int i = thread_id; i < qps_per_rdma_rank * (num_rdma_ranks - 1); i += num_threads) {\n auto dst_rdma_rank = (i / qps_per_rdma_rank + rdma_rank + 1) % num_rdma_ranks;\n auto qp_id = i % qps_per_rdma_rank;\n nvshmemi_ibgda_quiet(translate_dst_rdma_rank(dst_rdma_rank, nvl_rank), qp_id);\n }\n __syncthreads();\n\n // Barrier for RDMA\n if (thread_id == 32)\n nvshmem_sync_with_same_gpu_idx(rdma_team);\n\n // Barrier for NVL\n barrier_block(barrier_signal_ptrs, nvl_rank);\n\n // Clean RDMA buffer\n auto rdma_buffer_ptr_int = static_cast(rdma_buffer_ptr);\n #pragma unroll\n for (int i = thread_id; i < rdma_num_int_clean; i += num_threads)\n rdma_buffer_ptr_int[rdma_clean_offset + i] = 0;\n\n // Clean NVL buffer\n auto nvl_buffer_ptr_int = static_cast(buffer_ptrs[nvl_rank]);\n #pragma unroll\n for (int i = thread_id; i < nvl_num_int_clean; i += num_threads)\n nvl_buffer_ptr_int[nvl_clean_offset + i] = 0;\n __syncthreads();\n\n // Barrier again\n if (thread_id == 32)\n nvshmem_sync_with_same_gpu_idx(rdma_team);\n barrier_block(barrier_signal_ptrs, nvl_rank);\n } else if (sm_id == 1) {\n if (is_cached_dispatch)\n return;\n\n EP_DEVICE_ASSERT(num_warps >= num_channels);\n EP_DEVICE_ASSERT(num_rdma_ranks <= 32);\n\n // Iterate in reverse order\n if (lane_id < num_rdma_ranks and warp_id < num_channels) {\n int token_start_idx, token_end_idx;\n get_channel_task_range(num_combined_tokens, num_channels, warp_id, token_start_idx, token_end_idx);\n\n // NOTES: `1 << 25` is a heuristic large number\n int last_head = 1 << 25;\n for (int token_idx = token_end_idx - 1; token_idx >= token_start_idx; --token_idx) {\n auto current_head = __ldg(combined_rdma_head + token_idx * num_rdma_ranks + lane_id);\n if (current_head < 0) {\n combined_rdma_head[token_idx * num_rdma_ranks + lane_id] = -last_head - 1;\n } else {\n last_head = current_head;\n }\n }\n }\n } else {\n if (is_cached_dispatch)\n return;\n\n EP_DEVICE_ASSERT(num_warps >= num_channels);\n EP_DEVICE_ASSERT(rdma_channel_prefix_matrix != nullptr and rdma_rank_prefix_sum != nullptr);\n EP_STATIC_ASSERT(NUM_MAX_NVL_PEERS <= 32, \"Too many NVL peers\");\n\n if (warp_id < num_channels) {\n constexpr int tma_batch_size = kNumTMABytesPerWarp - sizeof(uint64_t);\n constexpr int num_bytes_per_token = sizeof(int) * NUM_MAX_NVL_PEERS;\n constexpr int num_tokens_per_batch = tma_batch_size / num_bytes_per_token;\n EP_STATIC_ASSERT(num_bytes_per_token % 16 == 0, \"num_bytes_per_token should be divisible by 16\");\n\n // TMA stuffs\n extern __shared__ __align__(1024) uint8_t smem_tma_buffer[];\n auto tma_buffer = smem_tma_buffer + warp_id * kNumTMABytesPerWarp;\n auto tma_mbarrier = reinterpret_cast(tma_buffer + tma_batch_size);\n uint32_t tma_phase = 0;\n if (elect_one_sync()) {\n mbarrier_init(tma_mbarrier, 1);\n fence_barrier_init();\n }\n __syncwarp();\n\n for (int dst_rdma_rank = sm_id - 2; dst_rdma_rank < num_rdma_ranks; dst_rdma_rank += num_channels * 2 - 2) {\n // Iterate in reverse order\n int token_start_idx = warp_id == 0 ? 0 : rdma_channel_prefix_matrix[dst_rdma_rank * num_channels + warp_id - 1];\n int token_end_idx = rdma_channel_prefix_matrix[dst_rdma_rank * num_channels + warp_id];\n int shift = dst_rdma_rank == 0 ? 0 : rdma_rank_prefix_sum[dst_rdma_rank - 1];\n token_start_idx += shift, token_end_idx += shift;\n\n // NOTES: `1 << 25` is a heuristic large number\n int last_head = 1 << 25;\n for (int batch_end_idx = token_end_idx; batch_end_idx > token_start_idx; batch_end_idx -= num_tokens_per_batch) {\n auto batch_start_idx = max(token_start_idx, batch_end_idx - num_tokens_per_batch);\n\n if (elect_one_sync()) {\n tma_load_1d(tma_buffer,\n combined_nvl_head + batch_start_idx * NUM_MAX_NVL_PEERS,\n tma_mbarrier,\n (batch_end_idx - batch_start_idx) * num_bytes_per_token);\n mbarrier_arrive_and_expect_tx(tma_mbarrier, (batch_end_idx - batch_start_idx) * num_bytes_per_token);\n }\n mbarrier_wait(tma_mbarrier, tma_phase);\n __syncwarp();\n\n for (int token_idx = batch_end_idx - 1; token_idx >= batch_start_idx; --token_idx) {\n if (lane_id < NUM_MAX_NVL_PEERS) {\n auto current_head =\n reinterpret_cast(tma_buffer)[(token_idx - batch_start_idx) * NUM_MAX_NVL_PEERS + lane_id];\n if (current_head < 0) {\n reinterpret_cast(tma_buffer)[(token_idx - batch_start_idx) * NUM_MAX_NVL_PEERS + lane_id] =\n -last_head - 1;\n } else {\n last_head = current_head;\n }\n }\n }\n tma_store_fence();\n __syncwarp();\n\n if (elect_one_sync())\n tma_store_1d(tma_buffer,\n combined_nvl_head + batch_start_idx * NUM_MAX_NVL_PEERS,\n (batch_end_idx - batch_start_idx) * num_bytes_per_token);\n tma_store_wait<0>();\n __syncwarp();\n }\n }\n }\n }\n}\n\nvoid cached_notify(int hidden_int4,\n int num_scales,\n int num_topk_idx,\n int num_topk_weights,\n int num_ranks,\n int num_channels,\n int num_combined_tokens,\n int* combined_rdma_head,\n const int* rdma_channel_prefix_matrix,\n const int* rdma_rank_prefix_sum,\n int* combined_nvl_head,\n void* rdma_buffer_ptr,\n int num_max_rdma_chunked_recv_tokens,\n void** buffer_ptrs,\n int num_max_nvl_chunked_recv_tokens,\n int** barrier_signal_ptrs,\n int rank,\n cudaStream_t stream,\n int64_t num_rdma_bytes,\n int64_t num_nvl_bytes,\n bool is_cached_dispatch,\n bool low_latency_mode) {\n const int num_threads = std::max(128, 32 * num_channels);\n const int num_warps = num_threads / 32;\n const auto num_rdma_ranks = num_ranks / NUM_MAX_NVL_PEERS;\n const int kNumTMABytesPerWarp = 8192;\n const int smem_size = kNumTMABytesPerWarp * num_warps;\n\n // Get clean meta\n auto rdma_clean_meta = get_rdma_clean_meta(\n hidden_int4, num_scales, num_topk_idx, num_topk_weights, num_rdma_ranks, num_max_rdma_chunked_recv_tokens, num_channels);\n auto nvl_clean_meta = get_nvl_clean_meta(hidden_int4,\n num_scales,\n num_topk_idx,\n num_topk_weights,\n num_rdma_ranks,\n NUM_MAX_NVL_PEERS,\n num_max_nvl_chunked_recv_tokens,\n num_channels,\n is_cached_dispatch);\n EP_HOST_ASSERT((rdma_clean_meta.first + rdma_clean_meta.second) * sizeof(int) <= num_rdma_bytes);\n EP_HOST_ASSERT((nvl_clean_meta.first + nvl_clean_meta.second) * sizeof(int) <= num_nvl_bytes);\n EP_HOST_ASSERT(num_rdma_bytes < std::numeric_limits::max());\n EP_HOST_ASSERT(num_nvl_bytes < std::numeric_limits::max());\n EP_HOST_ASSERT(num_channels * 2 > 3);\n\n // Launch kernel\n auto cached_notify_func = low_latency_mode ? cached_notify : cached_notify;\n SETUP_LAUNCH_CONFIG(num_channels * 2, num_threads, stream);\n SET_SHARED_MEMORY_FOR_TMA(cached_notify_func);\n LAUNCH_KERNEL(&cfg,\n cached_notify_func,\n rdma_clean_meta.first,\n rdma_clean_meta.second,\n nvl_clean_meta.first,\n nvl_clean_meta.second,\n combined_rdma_head,\n num_combined_tokens,\n num_channels,\n rdma_channel_prefix_matrix,\n rdma_rank_prefix_sum,\n combined_nvl_head,\n rdma_buffer_ptr,\n buffer_ptrs,\n barrier_signal_ptrs,\n rank,\n num_ranks,\n is_cached_dispatch,\n cpu_rdma_team);\n}\n\ntemplate \n__device__ int combine_token(bool is_token_in_rank,\n int head_idx,\n int lane_id,\n int hidden_int4,\n int num_topk,\n int4* combined_row,\n float* combined_topk_weights,\n const int4* bias_0_int4,\n const int4* bias_1_int4,\n int num_max_recv_tokens,\n const GetAddrFn& get_addr_fn,\n const ReceiveTWFn& recv_tw_fn,\n uint8_t* smem_ptr,\n uint32_t (&tma_phase)[kNumStages]) {\n constexpr auto kDtypePerInt4 = sizeof(int4) / sizeof(dtype_t);\n\n // Broadcast current heads\n // Lane `i` holds the head of rank `i` and `is_token_in_rank`\n EP_STATIC_ASSERT(kMaxNumRanks <= 32, \"Too many ranks\");\n int num_topk_ranks = 0, topk_ranks[kMaxNumRanks], slot_indices[kMaxNumRanks];\n #pragma unroll\n for (int i = 0; i < kNumRanks; ++i)\n if (__shfl_sync(0xffffffff, is_token_in_rank, i)) {\n slot_indices[num_topk_ranks] = __shfl_sync(0xffffffff, head_idx, i) % num_max_recv_tokens;\n topk_ranks[num_topk_ranks++] = i;\n }\n EP_DEVICE_ASSERT(num_topk_ranks <= kMaxNumRanks);\n EP_STATIC_ASSERT(not(kUseTMA and kMaybeWithBias), \"TMA cannot be used by receiver warps\");\n EP_STATIC_ASSERT(kNumStages == 2, \"Only support 2 stages now\");\n\n // Reduce data\n if constexpr (kUseTMA) {\n constexpr int kNumTMABufferBytesPerStage = kNumTMALoadBytes * (NUM_MAX_NVL_PEERS + 1) + 16;\n EP_DEVICE_ASSERT(hidden_int4 % 32 == 0);\n\n auto tma_load_buffer = [=](const int& i, const int& j) -> int4* {\n return reinterpret_cast(smem_ptr + i * kNumTMABufferBytesPerStage + j * kNumTMALoadBytes);\n };\n auto tma_store_buffer = [=](const int& i) -> int4* {\n return reinterpret_cast(smem_ptr + i * kNumTMABufferBytesPerStage + NUM_MAX_NVL_PEERS * kNumTMALoadBytes);\n };\n auto tma_mbarrier = [=](const int& i) -> uint64_t* {\n return reinterpret_cast(smem_ptr + i * kNumTMABufferBytesPerStage + (NUM_MAX_NVL_PEERS + 1) * kNumTMALoadBytes);\n };\n\n // Prefetch\n if (lane_id < num_topk_ranks)\n tma_load_1d(\n tma_load_buffer(0, lane_id), get_addr_fn(topk_ranks[lane_id], slot_indices[lane_id], 0), tma_mbarrier(0), kNumTMALoadBytes);\n mbarrier_arrive_and_expect_tx(tma_mbarrier(0), lane_id < num_topk_ranks ? kNumTMALoadBytes : 0);\n __syncwarp();\n\n for (int shifted = 0, iter = 0; shifted < hidden_int4; shifted += 32, iter += 1) {\n const int stage_idx = iter % kNumStages;\n const int next_stage_idx = (iter + 1) % kNumStages;\n\n // Prefetch next stage\n if (shifted + 32 < hidden_int4) {\n if (lane_id < num_topk_ranks)\n tma_load_1d(tma_load_buffer(next_stage_idx, lane_id),\n get_addr_fn(topk_ranks[lane_id], slot_indices[lane_id], shifted + 32),\n tma_mbarrier(next_stage_idx),\n kNumTMALoadBytes);\n mbarrier_arrive_and_expect_tx(tma_mbarrier(next_stage_idx), lane_id < num_topk_ranks ? kNumTMALoadBytes : 0);\n __syncwarp();\n }\n\n mbarrier_wait(tma_mbarrier(stage_idx), tma_phase[stage_idx]);\n float values[kDtypePerInt4] = {0};\n #pragma unroll\n for (int j = 0; j < num_topk_ranks; ++j) {\n auto recv_value_dtypes = reinterpret_cast(tma_load_buffer(stage_idx, j) + lane_id);\n #pragma unroll\n for (int k = 0; k < kDtypePerInt4; ++k)\n values[k] += static_cast(recv_value_dtypes[k]);\n }\n\n // Wait shared memory to be released\n tma_store_wait();\n\n // Copy into shared and issue TMA\n auto out_dtypes = reinterpret_cast(tma_store_buffer(stage_idx) + lane_id);\n #pragma unroll\n for (int j = 0; j < kDtypePerInt4; ++j)\n out_dtypes[j] = static_cast(values[j]);\n tma_store_fence();\n __syncwarp();\n\n if (elect_one_sync())\n tma_store_1d(tma_store_buffer(stage_idx), combined_row + shifted, kNumTMALoadBytes);\n __syncwarp();\n }\n\n // Flush all writes\n tma_store_wait<0>();\n } else {\n #pragma unroll\n for (int i = lane_id; i < hidden_int4; i += 32) {\n // Read bias\n // TODO: make it as a finer-grained template\n int4 bias_0_value_int4, bias_1_value_int4;\n if constexpr (kMaybeWithBias) {\n bias_0_value_int4 = bias_0_int4 != nullptr ? ld_nc_global(bias_0_int4 + i) : make_int4(0, 0, 0, 0);\n bias_1_value_int4 = bias_1_int4 != nullptr ? ld_nc_global(bias_1_int4 + i) : make_int4(0, 0, 0, 0);\n }\n\n // Read buffers\n // TODO: maybe too many registers here\n int4 recv_value_int4[kMaxNumRanks];\n #pragma unroll\n for (int j = 0; j < num_topk_ranks; ++j)\n recv_value_int4[j] = ld_nc_global(get_addr_fn(topk_ranks[j], slot_indices[j], i));\n\n // Clean\n // Reduce bias\n float values[kDtypePerInt4] = {0};\n if constexpr (kMaybeWithBias) {\n auto bias_0_values = reinterpret_cast(&bias_0_value_int4);\n auto bias_1_values = reinterpret_cast(&bias_1_value_int4);\n #pragma unroll\n for (int j = 0; j < kDtypePerInt4; ++j)\n values[j] = static_cast(bias_0_values[j]) + static_cast(bias_1_values[j]);\n }\n\n // Reduce all-to-all results\n #pragma unroll\n for (int j = 0; j < num_topk_ranks; ++j) {\n auto recv_value_dtypes = reinterpret_cast(&recv_value_int4[j]);\n #pragma unroll\n for (int k = 0; k < kDtypePerInt4; ++k)\n values[k] += static_cast(recv_value_dtypes[k]);\n }\n\n // Cast back to `dtype_t` and write\n int4 out_int4;\n auto out_dtypes = reinterpret_cast(&out_int4);\n #pragma unroll\n for (int j = 0; j < kDtypePerInt4; ++j)\n out_dtypes[j] = static_cast(values[j]);\n st_na_global(combined_row + i, out_int4);\n }\n }\n\n // Reduce `topk_weights`\n if (lane_id < num_topk) {\n float value = 0;\n #pragma unroll\n for (int i = 0; i < num_topk_ranks; ++i)\n value += recv_tw_fn(topk_ranks[i], slot_indices[i], lane_id);\n st_na_global(combined_topk_weights + lane_id, value);\n }\n\n // Return the minimum top-k rank\n return topk_ranks[0];\n}\n\ntemplate 0) ? kNumCombineForwarderWarps / kNumRDMARanks : 1,\n int kNumForwarders = kNumRDMARanks* kNumWarpsPerForwarder,\n int kNumRDMAReceivers = kNumForwarders - NUM_MAX_NVL_PEERS>\n__global__ void __launch_bounds__((kNumForwarders + 1) * 32, 1) combine(int4* combined_x,\n float* combined_topk_weights,\n const bool* is_combined_token_in_rank,\n const int4* x,\n const float* topk_weights,\n const int4* bias_0,\n const int4* bias_1,\n const int* combined_rdma_head,\n const int* combined_nvl_head,\n const SourceMeta* src_meta,\n const int* rdma_channel_prefix_matrix,\n const int* rdma_rank_prefix_sum,\n const int* gbl_channel_prefix_matrix,\n int num_tokens,\n int num_combined_tokens,\n int hidden,\n int num_topk,\n void* rdma_buffer_ptr,\n int num_max_rdma_chunked_send_tokens,\n int num_max_rdma_chunked_recv_tokens,\n void** buffer_ptrs,\n int num_max_nvl_chunked_send_tokens,\n int num_max_nvl_chunked_recv_tokens,\n int rank,\n int num_ranks) {\n enum class WarpRole { kNVLSender, kNVLAndRDMAForwarder, kRDMAReceiver, kCoordinator };\n\n const auto sm_id = static_cast(blockIdx.x);\n const auto num_threads = static_cast(blockDim.x), num_warps = num_threads / 32;\n const auto thread_id = static_cast(threadIdx.x), lane_id = get_lane_id();\n const auto num_channels = static_cast(gridDim.x) / 2, channel_id = sm_id / 2;\n const bool is_forwarder_sm = sm_id % 2 == 1;\n\n EP_DEVICE_ASSERT(num_topk <= 32);\n EP_DEVICE_ASSERT(hidden % (sizeof(int4) / sizeof(dtype_t)) == 0);\n const auto hidden_int4 = hidden / (sizeof(int4) / sizeof(dtype_t));\n const auto hidden_bytes = hidden_int4 * sizeof(int4);\n const auto num_bytes_per_token = get_num_bytes_per_token(hidden_int4, 0, 0, num_topk);\n\n // NOTES: we decouple a channel into 2 SMs\n const auto rdma_rank = rank / NUM_MAX_NVL_PEERS, nvl_rank = rank % NUM_MAX_NVL_PEERS;\n auto role_meta = [=]() -> std::pair {\n auto warp_id = thread_id / 32;\n if (not is_forwarder_sm) {\n if (warp_id < NUM_MAX_NVL_PEERS) {\n auto shuffled_warp_id = warp_id;\n shuffled_warp_id = (shuffled_warp_id + channel_id) % NUM_MAX_NVL_PEERS;\n return {WarpRole::kNVLSender, shuffled_warp_id};\n } else if (warp_id < kNumForwarders) {\n return {WarpRole::kRDMAReceiver, warp_id - NUM_MAX_NVL_PEERS};\n } else {\n return {WarpRole::kCoordinator, 0};\n }\n } else {\n if (warp_id < kNumForwarders) {\n auto shuffled_warp_id = (warp_id + channel_id) % kNumForwarders;\n return {WarpRole::kNVLAndRDMAForwarder, shuffled_warp_id};\n } else {\n return {WarpRole::kCoordinator, 0};\n }\n }\n }();\n auto warp_role = role_meta.first;\n auto warp_id = role_meta.second;\n\n EP_DEVICE_ASSERT(num_warps == kNumForwarders + 1);\n auto num_max_nvl_chunked_recv_tokens_per_rdma = num_max_nvl_chunked_recv_tokens / kNumRDMARanks;\n\n if (warp_role == WarpRole::kNVLSender) {\n // NVL producers\n const auto dst_nvl_rank = warp_id;\n\n // NVL layouts\n // NOTES: to avoid deadlocks, we use separate NVL buffers for different RDMA sources\n auto dst_buffer_ptr = buffer_ptrs[dst_nvl_rank], local_buffer_ptr = buffer_ptrs[nvl_rank];\n auto nvl_channel_x = AsymBuffer(dst_buffer_ptr,\n num_max_nvl_chunked_recv_tokens * num_bytes_per_token,\n NUM_MAX_NVL_PEERS,\n channel_id,\n num_channels,\n nvl_rank)\n .advance_also(local_buffer_ptr);\n auto nvl_channel_head = AsymBuffer(local_buffer_ptr, kNumRDMARanks, NUM_MAX_NVL_PEERS, channel_id, num_channels, dst_nvl_rank)\n .advance_also(dst_buffer_ptr);\n auto nvl_channel_tail = AsymBuffer(dst_buffer_ptr, kNumRDMARanks, NUM_MAX_NVL_PEERS, channel_id, num_channels, nvl_rank)\n .advance_also(local_buffer_ptr);\n\n // TMA stuffs\n extern __shared__ __align__(1024) uint8_t smem_tma_buffer[];\n auto tma_buffer = smem_tma_buffer + dst_nvl_rank * kNumTMABytesPerSenderWarp;\n auto tma_mbarrier = reinterpret_cast(tma_buffer + num_bytes_per_token);\n uint32_t tma_phase = 0;\n if (elect_one_sync()) {\n mbarrier_init(tma_mbarrier, 1);\n fence_barrier_init();\n EP_DEVICE_ASSERT(num_bytes_per_token + sizeof(uint64_t) <= kNumTMABytesPerSenderWarp);\n }\n __syncwarp();\n\n // Get tasks for each RDMA lane\n int token_start_idx = 0, token_end_idx = 0;\n if (lane_id < kNumRDMARanks) {\n int prefix_idx = (lane_id * NUM_MAX_NVL_PEERS + dst_nvl_rank) * num_channels + channel_id;\n token_start_idx = gbl_channel_prefix_matrix[prefix_idx];\n token_end_idx = (prefix_idx == num_channels * num_ranks - 1) ? num_tokens : gbl_channel_prefix_matrix[prefix_idx + 1];\n }\n __syncwarp();\n\n // NOTES: here the cached value of each lane is only responsible for a single RDMA buffer\n int cached_channel_head_idx = 0, cached_channel_tail_idx = 0;\n EP_STATIC_ASSERT(kNumRDMARanks <= 32, \"Invalid number of RDMA peers\");\n\n // Iterate over all tokens and send by chunks\n int current_rdma_idx = channel_id % kNumRDMARanks;\n while (true) {\n // Exit if possible\n if (__all_sync(0xffffffff, token_start_idx >= token_end_idx))\n break;\n\n // Decide the next RDMA buffer to send\n bool is_lane_ready = false;\n auto start_time = clock64();\n while (true) {\n int num_used_slots = cached_channel_tail_idx - cached_channel_head_idx;\n is_lane_ready = lane_id < kNumRDMARanks and token_start_idx < token_end_idx and\n num_max_nvl_chunked_recv_tokens_per_rdma - num_used_slots >= num_max_nvl_chunked_send_tokens;\n if (__any_sync(0xffffffff, is_lane_ready))\n break;\n\n // Retry\n if (lane_id < kNumRDMARanks and token_start_idx < token_end_idx)\n cached_channel_head_idx = ld_volatile_global(nvl_channel_head.buffer() + lane_id);\n\n // Timeout check\n if (clock64() - start_time > NUM_TIMEOUT_CYCLES and lane_id < kNumRDMARanks) {\n printf(\n \"DeepEP combine NVL sender timeout, channel: %d, RDMA: %d, nvl: %d, dst NVL: %d, RDMA lane: %d, head: %d, tail: \"\n \"%d, start: %d, end: %d\\n\",\n channel_id,\n rdma_rank,\n nvl_rank,\n dst_nvl_rank,\n lane_id,\n ld_volatile_global(nvl_channel_head.buffer() + lane_id),\n cached_channel_tail_idx,\n token_start_idx,\n token_end_idx);\n trap();\n }\n }\n\n // Sync token start index and count\n for (int i = 0; i < kNumRDMARanks; ++i) {\n current_rdma_idx = (current_rdma_idx + 1) % kNumRDMARanks;\n if (__shfl_sync(0xffffffff, (token_start_idx >= token_end_idx) or (not is_lane_ready), current_rdma_idx))\n continue;\n\n // Sync token start index\n auto token_idx = static_cast(__shfl_sync(0xffffffff, token_start_idx, current_rdma_idx));\n int num_tokens_in_chunk =\n __shfl_sync(0xffffffff, min(num_max_nvl_chunked_send_tokens, token_end_idx - token_start_idx), current_rdma_idx);\n\n // Send by chunk\n for (int chunk_idx = 0; chunk_idx < num_tokens_in_chunk; ++chunk_idx, ++token_idx) {\n // Get an empty slot\n int dst_slot_idx = 0;\n if (lane_id == current_rdma_idx) {\n dst_slot_idx = (cached_channel_tail_idx++) % num_max_nvl_chunked_recv_tokens_per_rdma;\n dst_slot_idx = current_rdma_idx * num_max_nvl_chunked_recv_tokens_per_rdma + dst_slot_idx;\n }\n dst_slot_idx = __shfl_sync(0xffffffff, dst_slot_idx, current_rdma_idx);\n\n // Load data\n auto shifted_x_buffers = nvl_channel_x.buffer() + dst_slot_idx * num_bytes_per_token;\n auto shifted_x = x + token_idx * hidden_int4;\n tma_store_wait<0>();\n if (elect_one_sync()) {\n tma_load_1d(tma_buffer, shifted_x, tma_mbarrier, hidden_bytes);\n mbarrier_arrive_and_expect_tx(tma_mbarrier, hidden_bytes);\n }\n __syncwarp();\n mbarrier_wait(tma_mbarrier, tma_phase);\n\n // Load source meta\n if (lane_id == num_topk)\n *reinterpret_cast(tma_buffer + hidden_bytes) = ld_nc_global(src_meta + token_idx);\n\n // Load `topk_weights`\n if (lane_id < num_topk)\n *reinterpret_cast(tma_buffer + hidden_bytes + sizeof(SourceMeta) + lane_id * sizeof(float)) =\n ld_nc_global(topk_weights + token_idx * num_topk + lane_id);\n\n // Issue TMA store\n tma_store_fence();\n __syncwarp();\n if (elect_one_sync())\n tma_store_1d(tma_buffer, shifted_x_buffers, num_bytes_per_token, false);\n }\n lane_id == current_rdma_idx ? (token_start_idx = static_cast(token_idx)) : 0;\n }\n\n // Move queue tail\n tma_store_wait<0>();\n __syncwarp();\n if (lane_id < kNumRDMARanks and is_lane_ready)\n st_release_sys_global(nvl_channel_tail.buffer() + lane_id, cached_channel_tail_idx);\n }\n } else {\n // Combiners and coordinators\n // RDMA symmetric layout\n auto rdma_channel_data = SymBuffer(\n rdma_buffer_ptr, num_max_rdma_chunked_recv_tokens * num_bytes_per_token, kNumRDMARanks, channel_id, num_channels);\n auto rdma_channel_head = SymBuffer(rdma_buffer_ptr, 1, kNumRDMARanks, channel_id, num_channels);\n auto rdma_channel_tail = SymBuffer(rdma_buffer_ptr, 1, kNumRDMARanks, channel_id, num_channels);\n\n // NVL layouts\n void* local_nvl_buffer = buffer_ptrs[nvl_rank];\n void* nvl_buffers[NUM_MAX_NVL_PEERS];\n #pragma unroll\n for (int i = 0; i < NUM_MAX_NVL_PEERS; ++i)\n nvl_buffers[i] = buffer_ptrs[i];\n auto nvl_channel_x =\n AsymBuffer(\n local_nvl_buffer, num_max_nvl_chunked_recv_tokens * num_bytes_per_token, NUM_MAX_NVL_PEERS, channel_id, num_channels)\n .advance_also(nvl_buffers);\n auto nvl_channel_head =\n AsymBuffer(nvl_buffers, kNumRDMARanks, NUM_MAX_NVL_PEERS, channel_id, num_channels, nvl_rank)\n .advance_also(local_nvl_buffer);\n auto nvl_channel_tail = AsymBuffer(local_nvl_buffer, kNumRDMARanks, NUM_MAX_NVL_PEERS, channel_id, num_channels)\n .advance_also(nvl_buffers);\n\n // Combiner warp synchronization\n __shared__ volatile int forwarder_nvl_head[kNumForwarders][NUM_MAX_NVL_PEERS];\n __shared__ volatile bool forwarder_retired[kNumForwarders];\n __shared__ volatile int rdma_receiver_rdma_head[kNumRDMAReceivers][kNumRDMARanks];\n __shared__ volatile bool rdma_receiver_retired[kNumRDMAReceivers];\n auto sync_forwarder_smem = [=]() { asm volatile(\"barrier.sync 0, %0;\" ::\"r\"((kNumForwarders + 1) * 32)); };\n auto sync_rdma_receiver_smem = [=]() { asm volatile(\"barrier.sync 1, %0;\" ::\"r\"((kNumRDMAReceivers + 1) * 32)); };\n\n if (warp_role == WarpRole::kNVLAndRDMAForwarder) {\n // Receive from NVL ranks and forward to RDMA ranks\n // NOTES: this part is using \"large warps\" for each RDMA ranks\n const auto dst_rdma_rank = warp_id / kNumWarpsPerForwarder;\n const auto sub_warp_id = warp_id % kNumWarpsPerForwarder;\n auto send_buffer =\n dst_rdma_rank == rdma_rank ? rdma_channel_data.recv_buffer(dst_rdma_rank) : rdma_channel_data.send_buffer(dst_rdma_rank);\n auto sync_large_warp = [=]() {\n if (kNumWarpsPerForwarder == 1) {\n __syncwarp();\n } else {\n asm volatile(\"bar.sync %0, %1;\" ::\"r\"(dst_rdma_rank + 2), \"r\"(kNumWarpsPerForwarder * 32));\n }\n };\n EP_STATIC_ASSERT(kNumWarpsPerForwarder == 1 or kNumRDMARanks + 2 <= 16, \"Barriers are not enough\");\n\n // TMA stuffs\n constexpr int kNumStages = 2;\n constexpr int kNumTMALoadBytes = sizeof(int4) * 32;\n constexpr int kNumTMABufferBytesPerStage = kNumTMALoadBytes * (NUM_MAX_NVL_PEERS + 1) + 16;\n EP_STATIC_ASSERT(kNumTMABufferBytesPerStage * kNumStages <= kNumTMABytesPerForwarderWarp, \"TMA buffer is not larger enough\");\n\n extern __shared__ __align__(1024) uint8_t smem_buffer[];\n auto smem_ptr = smem_buffer + warp_id * kNumStages * kNumTMABufferBytesPerStage;\n auto tma_mbarrier = [=](const int& i) {\n return reinterpret_cast(smem_ptr + i * kNumTMABufferBytesPerStage + kNumTMALoadBytes * (NUM_MAX_NVL_PEERS + 1));\n };\n uint32_t tma_phase[kNumStages] = {0};\n if (lane_id < kNumStages) {\n mbarrier_init(tma_mbarrier(lane_id), 32);\n fence_barrier_init();\n }\n __syncwarp();\n\n // Advance to the corresponding NVL buffer\n nvl_channel_x.advance(dst_rdma_rank * num_max_nvl_chunked_recv_tokens_per_rdma * num_bytes_per_token);\n nvl_channel_head.advance(dst_rdma_rank);\n nvl_channel_tail.advance(dst_rdma_rank);\n\n // Clean shared memory and sync\n EP_STATIC_ASSERT(NUM_MAX_NVL_PEERS <= 32, \"Invalid number of NVL peers\");\n lane_id < NUM_MAX_NVL_PEERS ? (forwarder_nvl_head[warp_id][lane_id] = 0) : 0;\n lane_id == 0 ? (forwarder_retired[warp_id] = false) : false;\n sync_forwarder_smem();\n\n // Get count and cached head\n int cached_nvl_channel_tail_idx = 0;\n int num_tokens_to_combine = rdma_channel_prefix_matrix[dst_rdma_rank * num_channels + channel_id];\n int num_tokens_prefix = channel_id == 0 ? 0 : rdma_channel_prefix_matrix[dst_rdma_rank * num_channels + channel_id - 1];\n num_tokens_to_combine -= num_tokens_prefix;\n num_tokens_prefix += dst_rdma_rank == 0 ? 0 : rdma_rank_prefix_sum[dst_rdma_rank - 1];\n combined_nvl_head += num_tokens_prefix * NUM_MAX_NVL_PEERS;\n\n // Iterate over all tokens and combine by chunks\n for (int token_start_idx = 0; token_start_idx < num_tokens_to_combine; token_start_idx += num_max_rdma_chunked_send_tokens) {\n // Check destination queue emptiness, or wait a buffer to be released\n auto token_end_idx = min(token_start_idx + num_max_rdma_chunked_send_tokens, num_tokens_to_combine);\n auto num_chunked_tokens = token_end_idx - token_start_idx;\n auto start_time = clock64();\n while (sub_warp_id == 0 and lane_id == 0) {\n // Inequality: `num_max_rdma_chunked_recv_tokens - (tail - head) >= num_chunked_tokens`\n // Here, `token_start_idx` is the actual tail\n int num_used_slots = token_start_idx - ld_volatile_global(rdma_channel_head.buffer(dst_rdma_rank));\n if (num_max_rdma_chunked_recv_tokens - num_used_slots >= num_chunked_tokens)\n break;\n\n // Timeout check\n if (clock64() - start_time > NUM_TIMEOUT_CYCLES) {\n printf(\n \"DeepEP combine forwarder (RDMA check) timeout, channel: %d, RDMA: %d, nvl: %d, dst RDMA: %d, head: %ld, tail: \"\n \"%d, chunked: %d\\n\",\n channel_id,\n rdma_rank,\n nvl_rank,\n dst_rdma_rank,\n ld_volatile_global(rdma_channel_head.buffer(dst_rdma_rank)),\n token_start_idx,\n num_chunked_tokens);\n trap();\n }\n }\n sync_large_warp();\n\n // Combine and write to the RDMA buffer\n for (int token_idx = token_start_idx + sub_warp_id; token_idx < token_end_idx; token_idx += kNumWarpsPerForwarder) {\n // Read expected head\n EP_STATIC_ASSERT(kNumRDMARanks <= 32, \"Invalid number of RDMA peers\");\n int expected_head = -1;\n if (lane_id < NUM_MAX_NVL_PEERS) {\n expected_head = ld_nc_global(combined_nvl_head + token_idx * NUM_MAX_NVL_PEERS + lane_id);\n expected_head < 0 ? (forwarder_nvl_head[warp_id][lane_id] = -expected_head - 1)\n : (forwarder_nvl_head[warp_id][lane_id] = expected_head);\n }\n\n // Wait lanes to be ready\n start_time = clock64();\n while (cached_nvl_channel_tail_idx <= expected_head) {\n cached_nvl_channel_tail_idx = ld_acquire_sys_global(nvl_channel_tail.buffer(lane_id));\n\n // Timeout check\n if (clock64() - start_time > NUM_TIMEOUT_CYCLES and lane_id < NUM_MAX_NVL_PEERS) {\n printf(\n \"DeepEP combine forwarder (NVL check) timeout, channel: %d, RDMA: %d, nvl: %d, src NVL: %d, dst RDMA: %d, \"\n \"tail: %d, waiting: %d, total: %d, sub: %d, large: %d, expected: %d\\n\",\n channel_id,\n rdma_rank,\n nvl_rank,\n lane_id,\n dst_rdma_rank,\n cached_nvl_channel_tail_idx,\n token_idx,\n num_tokens_to_combine,\n sub_warp_id,\n kNumWarpsPerForwarder,\n expected_head);\n trap();\n }\n }\n\n // Combine current token\n auto rdma_slot_idx = token_idx % num_max_rdma_chunked_recv_tokens;\n void* shifted = send_buffer + rdma_slot_idx * num_bytes_per_token;\n auto get_addr_fn = [&](int src_nvl_rank, int slot_idx, int hidden_int4_idx) -> int4* {\n return reinterpret_cast(nvl_channel_x.buffer(src_nvl_rank) + slot_idx * num_bytes_per_token) +\n hidden_int4_idx;\n };\n auto recv_tw_fn = [&](int src_nvl_rank, int slot_idx, int topk_idx) -> float {\n return ld_nc_global(reinterpret_cast(nvl_channel_x.buffer(src_nvl_rank) + slot_idx * num_bytes_per_token +\n hidden_bytes + sizeof(SourceMeta)) +\n topk_idx);\n };\n combine_token(\n expected_head >= 0,\n expected_head,\n lane_id,\n hidden_int4,\n num_topk,\n static_cast(shifted),\n reinterpret_cast(static_cast(shifted) + hidden_bytes + sizeof(SourceMeta)),\n nullptr,\n nullptr,\n num_max_nvl_chunked_recv_tokens_per_rdma,\n get_addr_fn,\n recv_tw_fn,\n smem_ptr,\n tma_phase);\n\n // Update head\n if (lane_id < NUM_MAX_NVL_PEERS)\n expected_head < 0 ? (forwarder_nvl_head[warp_id][lane_id] = -expected_head - 1)\n : (forwarder_nvl_head[warp_id][lane_id] = expected_head + 1);\n }\n sync_large_warp();\n\n // Issue RDMA send\n if (sub_warp_id == kNumWarpsPerForwarder - 1) {\n if (dst_rdma_rank != rdma_rank) {\n auto rdma_slot_idx = token_start_idx % num_max_rdma_chunked_recv_tokens;\n const size_t num_bytes_per_msg = num_chunked_tokens * num_bytes_per_token;\n const auto dst_ptr =\n reinterpret_cast(rdma_channel_data.recv_buffer(rdma_rank) + rdma_slot_idx * num_bytes_per_token);\n const auto src_ptr =\n reinterpret_cast(rdma_channel_data.send_buffer(dst_rdma_rank) + rdma_slot_idx * num_bytes_per_token);\n nvshmemi_ibgda_put_nbi_warp(dst_ptr,\n src_ptr,\n num_bytes_per_msg,\n translate_dst_rdma_rank(dst_rdma_rank, nvl_rank),\n channel_id,\n lane_id,\n 0);\n } else {\n memory_fence();\n }\n\n // Write new RDMA tail\n __syncwarp();\n if (elect_one_sync()) {\n nvshmemi_ibgda_amo_nonfetch_add(rdma_channel_tail.buffer(rdma_rank),\n num_chunked_tokens,\n translate_dst_rdma_rank(dst_rdma_rank, nvl_rank),\n channel_id,\n dst_rdma_rank == rdma_rank);\n }\n }\n }\n\n // Retired\n __syncwarp();\n if (elect_one_sync())\n forwarder_retired[warp_id] = true;\n } else if (warp_role == WarpRole::kRDMAReceiver) {\n // Receive from RDMA ranks and write to the output tensor\n // Clean shared memory and sync\n EP_DEVICE_ASSERT(kNumRDMARanks <= 32);\n lane_id < kNumRDMARanks ? (rdma_receiver_rdma_head[warp_id][lane_id] = 0) : 0;\n lane_id == 0 ? (rdma_receiver_retired[warp_id] = false) : 0;\n sync_rdma_receiver_smem();\n\n // The same tokens as the dispatch process\n int token_start_idx, token_end_idx;\n get_channel_task_range(num_combined_tokens, num_channels, channel_id, token_start_idx, token_end_idx);\n\n // Iterate over all tokens and combine\n int cached_channel_tail_idx = 0;\n for (int64_t token_idx = token_start_idx + warp_id; token_idx < token_end_idx; token_idx += kNumRDMAReceivers) {\n // Read expected head\n EP_STATIC_ASSERT(kNumRDMARanks <= 32, \"Invalid number of RDMA peers\");\n int expected_head = -1;\n if (lane_id < kNumRDMARanks) {\n expected_head = ld_nc_global(combined_rdma_head + token_idx * kNumRDMARanks + lane_id);\n (expected_head < 0) ? (rdma_receiver_rdma_head[warp_id][lane_id] = -expected_head - 1)\n : (rdma_receiver_rdma_head[warp_id][lane_id] = expected_head);\n }\n\n // Wait lanes to be ready\n auto start_time = clock64();\n while (cached_channel_tail_idx <= expected_head) {\n cached_channel_tail_idx = static_cast(ld_acquire_sys_global(rdma_channel_tail.buffer(lane_id)));\n\n // Timeout check\n if (clock64() - start_time > NUM_TIMEOUT_CYCLES) {\n printf(\n \"DeepEP combine RDMA receiver timeout, channel: %d, RDMA: %d, nvl: %d, src RDMA: %d, tail: %d, waiting: %ld, \"\n \"expect: %d\\n\",\n channel_id,\n rdma_rank,\n nvl_rank,\n lane_id,\n cached_channel_tail_idx,\n token_idx,\n expected_head);\n trap();\n }\n }\n __syncwarp();\n\n // Combine current token\n auto get_addr_fn = [&](int src_rdma_rank, int slot_idx, int hidden_int4_idx) -> int4* {\n return reinterpret_cast(rdma_channel_data.recv_buffer(src_rdma_rank) + slot_idx * num_bytes_per_token) +\n hidden_int4_idx;\n };\n auto recv_tw_fn = [&](int src_rdma_rank, int slot_idx, int topk_idx) -> float {\n return ld_nc_global(reinterpret_cast(rdma_channel_data.recv_buffer(src_rdma_rank) +\n slot_idx * num_bytes_per_token + hidden_bytes + sizeof(SourceMeta)) +\n topk_idx);\n };\n uint32_t dummy_tma_phases[2];\n combine_token(\n expected_head >= 0,\n expected_head,\n lane_id,\n hidden_int4,\n num_topk,\n combined_x + token_idx * hidden_int4,\n combined_topk_weights + token_idx * num_topk,\n bias_0 == nullptr ? nullptr : bias_0 + token_idx * hidden_int4,\n bias_1 == nullptr ? nullptr : bias_1 + token_idx * hidden_int4,\n num_max_rdma_chunked_recv_tokens,\n get_addr_fn,\n recv_tw_fn,\n nullptr,\n dummy_tma_phases);\n }\n\n // Retired\n __syncwarp();\n if (elect_one_sync())\n rdma_receiver_retired[warp_id] = true;\n } else {\n // Coordinator\n // Sync shared memory status\n is_forwarder_sm ? sync_forwarder_smem() : sync_rdma_receiver_smem();\n const auto num_warps_per_rdma_rank = kNumForwarders / kNumRDMARanks;\n\n int last_rdma_head = 0;\n int last_nvl_head[kNumRDMARanks] = {0};\n int dst_rdma_rank = lane_id < kNumRDMARanks ? lane_id : 0;\n int dst_nvl_rank = lane_id < NUM_MAX_NVL_PEERS ? lane_id : 0;\n EP_STATIC_ASSERT(kNumCombineForwarderWarps <= 32, \"Invalid number of forwarder warps\");\n while (true) {\n // Retired\n if (not is_forwarder_sm and __all_sync(0xffffffff, lane_id >= kNumRDMAReceivers or rdma_receiver_retired[lane_id]))\n break;\n if (is_forwarder_sm and __all_sync(0xffffffff, lane_id >= kNumForwarders or forwarder_retired[lane_id]))\n break;\n\n // Find minimum head for RDMA ranks\n if (not is_forwarder_sm) {\n int min_head = std::numeric_limits::max();\n #pragma unroll\n for (int i = 0; i < kNumRDMAReceivers; ++i)\n if (not rdma_receiver_retired[i])\n min_head = min(min_head, rdma_receiver_rdma_head[i][dst_rdma_rank]);\n if (min_head != std::numeric_limits::max() and min_head >= last_rdma_head + num_max_rdma_chunked_send_tokens and\n lane_id < kNumRDMARanks) {\n nvshmemi_ibgda_amo_nonfetch_add(rdma_channel_head.buffer(rdma_rank),\n min_head - last_rdma_head,\n translate_dst_rdma_rank(dst_rdma_rank, nvl_rank),\n channel_id + num_channels,\n dst_rdma_rank == rdma_rank);\n last_rdma_head = min_head;\n }\n } else {\n // Find minimum head for NVL ranks\n #pragma unroll\n for (int i = 0; i < kNumRDMARanks; ++i) {\n int min_head = std::numeric_limits::max();\n #pragma unroll\n for (int j = 0; j < num_warps_per_rdma_rank; ++j)\n if (not forwarder_retired[i * num_warps_per_rdma_rank + j])\n min_head = min(min_head, forwarder_nvl_head[i * num_warps_per_rdma_rank + j][dst_nvl_rank]);\n if (min_head != std::numeric_limits::max() and min_head > last_nvl_head[i] and lane_id < NUM_MAX_NVL_PEERS)\n st_relaxed_sys_global(nvl_channel_head.buffer_by(dst_nvl_rank) + i, last_nvl_head[i] = min_head);\n }\n }\n\n // Nanosleep and let other warps work\n __nanosleep(NUM_WAIT_NANOSECONDS);\n }\n }\n }\n}\n\nvoid combine(cudaDataType_t type,\n void* combined_x,\n float* combined_topk_weights,\n const bool* is_combined_token_in_rank,\n const void* x,\n const float* topk_weights,\n const void* bias_0,\n const void* bias_1,\n const int* combined_rdma_head,\n const int* combined_nvl_head,\n const void* src_meta,\n const int* rdma_channel_prefix_matrix,\n const int* rdma_rank_prefix_sum,\n const int* gbl_channel_prefix_matrix,\n int num_tokens,\n int num_combined_tokens,\n int hidden,\n int num_topk,\n void* rdma_buffer_ptr,\n int num_max_rdma_chunked_send_tokens,\n int num_max_rdma_chunked_recv_tokens,\n void** buffer_ptrs,\n int num_max_nvl_chunked_send_tokens,\n int num_max_nvl_chunked_recv_tokens,\n int rank,\n int num_ranks,\n cudaStream_t stream,\n int num_channels,\n bool low_latency_mode) {\n constexpr int kNumCombineForwarderWarps = 24;\n constexpr int kNumTMABytesPerSenderWarp = 16384;\n constexpr int kNumTMABytesPerForwarderWarp = 9248;\n constexpr int smem_size =\n std::max(kNumTMABytesPerSenderWarp * NUM_MAX_NVL_PEERS, kNumTMABytesPerForwarderWarp * kNumCombineForwarderWarps);\n\n#define COMBINE_LAUNCH_CASE(num_rdma_ranks) \\\n { \\\n auto combine_func = low_latency_mode ? combine \\\n : combine; \\\n SET_SHARED_MEMORY_FOR_TMA(combine_func); \\\n LAUNCH_KERNEL(&cfg, \\\n combine_func, \\\n reinterpret_cast(combined_x), \\\n combined_topk_weights, \\\n is_combined_token_in_rank, \\\n reinterpret_cast(x), \\\n topk_weights, \\\n reinterpret_cast(bias_0), \\\n reinterpret_cast(bias_1), \\\n combined_rdma_head, \\\n combined_nvl_head, \\\n reinterpret_cast(src_meta), \\\n rdma_channel_prefix_matrix, \\\n rdma_rank_prefix_sum, \\\n gbl_channel_prefix_matrix, \\\n num_tokens, \\\n num_combined_tokens, \\\n hidden, \\\n num_topk, \\\n rdma_buffer_ptr, \\\n num_max_rdma_chunked_send_tokens, \\\n num_max_rdma_chunked_recv_tokens, \\\n buffer_ptrs, \\\n num_max_nvl_chunked_send_tokens, \\\n num_max_nvl_chunked_recv_tokens, \\\n rank, \\\n num_ranks); \\\n } \\\n break\n\n int num_rdma_ranks = num_ranks / NUM_MAX_NVL_PEERS;\n auto num_warps_per_forwarder = std::max(kNumCombineForwarderWarps / num_rdma_ranks, 1);\n int num_forwarder_warps = num_rdma_ranks * num_warps_per_forwarder;\n EP_HOST_ASSERT(num_rdma_ranks <= kNumCombineForwarderWarps);\n EP_HOST_ASSERT(num_forwarder_warps > NUM_MAX_NVL_PEERS and num_forwarder_warps % num_rdma_ranks == 0);\n EP_HOST_ASSERT(num_max_nvl_chunked_recv_tokens % num_rdma_ranks == 0);\n EP_HOST_ASSERT(num_max_nvl_chunked_recv_tokens / num_rdma_ranks >\n std::max(num_max_rdma_chunked_send_tokens, num_max_nvl_chunked_send_tokens));\n EP_HOST_ASSERT(num_max_nvl_chunked_recv_tokens / num_rdma_ranks - num_warps_per_forwarder >= num_max_nvl_chunked_send_tokens);\n EP_HOST_ASSERT(num_max_rdma_chunked_send_tokens >= num_warps_per_forwarder);\n EP_HOST_ASSERT(type == CUDA_R_16BF);\n\n SETUP_LAUNCH_CONFIG(num_channels * 2, (num_forwarder_warps + 1) * 32, stream);\n SWITCH_RDMA_RANKS(COMBINE_LAUNCH_CASE);\n#undef COMBINE_LAUNCH_CASE\n}\n\n} // namespace internode\n\n} // namespace deep_ep\n" }, { "path": "csrc/kernels/internode_ll.cu", "content": "#include \"configs.cuh\"\n#include \"exception.cuh\"\n#include \"ibgda_device.cuh\"\n#include \"launch.cuh\"\n\nnamespace deep_ep {\n\nnamespace internode_ll {\n\ntemplate \n__forceinline__ __device__ bool is_rank_masked(int* mask_buffer_ptr, int rank) {\n if (mask_buffer_ptr == nullptr) {\n return false;\n }\n if constexpr (use_warp_sync) {\n return __shfl_sync(0xffffffff, ld_acquire_global(mask_buffer_ptr + rank), 0) != 0;\n } else {\n return ld_acquire_global(mask_buffer_ptr + rank) != 0;\n }\n}\n\ntemplate \n__forceinline__ __device__ void barrier(int thread_id, int rank, int num_ranks, int* mask_buffer_ptr, int* sync_buffer_ptr) {\n EP_DEVICE_ASSERT(kNumThreads >= num_ranks);\n\n // Quiet all QPs\n auto qps_per_rank = ibgda_get_state()->num_rc_per_pe * ibgda_get_state()->num_devices_initialized;\n\n for (int i = thread_id; i < qps_per_rank * (num_ranks - 1); i += kNumThreads) {\n auto dst_rank = (rank + 1 + i / qps_per_rank) % num_ranks;\n auto qp_id = i % qps_per_rank;\n nvshmemi_ibgda_quiet(dst_rank, qp_id);\n }\n\n // Update local counter\n if (thread_id == 0)\n atomicAdd(sync_buffer_ptr + rank, -1);\n __syncthreads();\n\n int cnt = sync_buffer_ptr[rank];\n // Update remote counter and wait for local counter to be updated\n if (thread_id < num_ranks && thread_id != rank) {\n const auto dst_rank = thread_id;\n const auto dst_ptr = reinterpret_cast(sync_buffer_ptr + rank);\n const auto dst_p2p_ptr = nvshmemi_get_p2p_ptr(dst_ptr, rank, dst_rank);\n\n if (not is_rank_masked(mask_buffer_ptr, dst_rank)) {\n if (dst_p2p_ptr == 0) {\n nvshmemi_ibgda_rma_p(reinterpret_cast(dst_ptr), cnt, dst_rank, 0);\n } else {\n st_release_sys_global(reinterpret_cast(dst_p2p_ptr), cnt);\n }\n\n auto start_time = clock64();\n uint64_t wait_recv_cost = 0;\n while (ld_acquire_sys_global(sync_buffer_ptr + dst_rank) != cnt // remote is not ready\n && (wait_recv_cost = clock64() - start_time) <= NUM_TIMEOUT_CYCLES // not timeout\n )\n ;\n // Mask rank if timeout\n if (wait_recv_cost > NUM_TIMEOUT_CYCLES) {\n printf(\"Warning: DeepEP timeout for barrier, rank %d, dst_rank %d\\n\", rank, dst_rank);\n if (mask_buffer_ptr == nullptr)\n trap();\n atomicExch(mask_buffer_ptr + dst_rank, 1);\n }\n }\n }\n __syncthreads();\n}\n\ntemplate \n__launch_bounds__(kNumThreads, 1) __global__ void clean_low_latency_buffer(int* clean_0,\n int num_clean_int_0,\n int* clean_1,\n int num_clean_int_1,\n int rank,\n int num_ranks,\n int* mask_buffer_ptr,\n int* sync_buffer_ptr) {\n auto thread_id = static_cast(threadIdx.x);\n\n // Barrier before cleaning (in case of unfinished chunked EP)\n if (sync_buffer_ptr == nullptr)\n nvshmemx_barrier_all_block();\n else\n barrier(thread_id, rank, num_ranks, mask_buffer_ptr, sync_buffer_ptr);\n\n // Clean\n #pragma unroll\n for (int i = thread_id; i < num_clean_int_0; i += kNumThreads)\n clean_0[i] = 0;\n #pragma unroll\n for (int i = thread_id; i < num_clean_int_1; i += kNumThreads)\n clean_1[i] = 0;\n\n // Barrier after cleaning (make sure the low-latency mode works fine)\n if (sync_buffer_ptr == nullptr)\n nvshmemx_barrier_all_block();\n else\n barrier(thread_id, rank, num_ranks, mask_buffer_ptr, sync_buffer_ptr);\n}\n\nvoid clean_low_latency_buffer(int* clean_0,\n int num_clean_int_0,\n int* clean_1,\n int num_clean_int_1,\n int rank,\n int num_ranks,\n int* mask_buffer_ptr,\n int* sync_buffer_ptr,\n cudaStream_t stream) {\n constexpr int kNumThreads = 256;\n\n SETUP_LAUNCH_CONFIG(1, kNumThreads, stream);\n\n LAUNCH_KERNEL(&cfg,\n clean_low_latency_buffer,\n clean_0,\n num_clean_int_0,\n clean_1,\n num_clean_int_1,\n rank,\n num_ranks,\n mask_buffer_ptr,\n sync_buffer_ptr);\n}\n\ntemplate \n__global__ __launch_bounds__(1024, 1) void dispatch(void* packed_recv_x,\n void* packed_recv_x_scales,\n int* packed_recv_src_info,\n int64_t* packed_recv_layout_range,\n int* packed_recv_count,\n int* mask_buffer_ptr,\n int* cumulative_local_expert_recv_stats,\n int64_t* dispatch_wait_recv_cost_stats,\n void* rdma_recv_x,\n int* rdma_recv_count,\n void* rdma_x,\n const void* x,\n const topk_idx_t* topk_idx,\n int* atomic_counter_per_expert,\n int* atomic_finish_counter_per_expert,\n int* next_clean,\n int num_next_clean_int,\n int num_tokens,\n int num_max_dispatch_tokens_per_rank,\n int num_topk,\n int num_experts,\n int rank,\n int num_ranks,\n int num_warp_groups,\n int num_warps_per_group,\n bool round_scale,\n int phases) {\n const auto sm_id = static_cast(blockIdx.x);\n const auto thread_id = static_cast(threadIdx.x);\n const auto warp_id = thread_id / 32, lane_id = get_lane_id();\n const auto num_sms = static_cast(gridDim.x);\n const auto num_warps = num_warp_groups * num_warps_per_group;\n const auto num_local_experts = num_experts / num_ranks;\n const auto warp_group_id = warp_id / num_warps_per_group;\n const auto sub_warp_id = warp_id % num_warps_per_group;\n const auto responsible_expert_idx = sm_id * num_warp_groups + warp_group_id;\n\n // May extract UE8M0 from the scales\n using scale_t = std::conditional_t;\n using packed_t = std::conditional_t;\n EP_STATIC_ASSERT(sizeof(packed_t) % sizeof(scale_t) == 0, \"Invalid vector length\");\n\n // FP8 staffs\n constexpr int kNumPerChannels = 128;\n const int num_scales = kHidden / kNumPerChannels;\n const size_t hidden_bytes = kHidden * (kUseFP8 ? sizeof(__nv_fp8_storage_t) : sizeof(nv_bfloat16));\n const size_t hidden_int4 = hidden_bytes / sizeof(int4);\n\n // Message package: index at source (int), 3 reserved int fields, hidden data, FP8 scales\n // NOTES: currently we have 3 reserved int fields for future use\n using vec_t = std::conditional_t;\n const size_t num_bytes_per_msg = sizeof(int4) + (kUseFP8 ? (kHidden + num_scales * sizeof(float)) : (kHidden * sizeof(nv_bfloat16)));\n const size_t num_int4_per_msg = num_bytes_per_msg / sizeof(int4);\n EP_DEVICE_ASSERT(num_bytes_per_msg % sizeof(int4) == 0);\n\n // Expert counts\n constexpr int kNumMaxWarpGroups = 32;\n __shared__ int shared_num_tokens_sent_per_expert[kNumMaxWarpGroups];\n\n // Sending phase\n if ((phases & LOW_LATENCY_SEND_PHASE) == 0)\n goto LOW_LATENCY_DISPATCH_RECV;\n\n // There are 2 kinds of warps in this part:\n // 1. The first-kind warps for FP8 cast and sending top-k tokens\n // 2. The last warp for reading `topk_idx` and count for per-expert information\n if (warp_id < num_warps - 1) {\n constexpr int kNumElemsPerRead = sizeof(int4) / sizeof(nv_bfloat16);\n EP_STATIC_ASSERT(kHidden % (32 * kNumElemsPerRead) == 0, \"Invalid hidden\");\n EP_STATIC_ASSERT(kNumElemsPerRead * 32 % kNumPerChannels == 0, \"Invalid vectorization\");\n const auto num_threads = (num_warps - 1) * 32;\n const size_t hidden_bf16_int4 = kHidden / kNumElemsPerRead;\n\n for (int token_idx = sm_id; token_idx < num_tokens; token_idx += num_sms) {\n const auto x_int4 = static_cast(x) + token_idx * hidden_bf16_int4;\n const auto rdma_x_src_idx = reinterpret_cast(static_cast(rdma_x) + token_idx * num_bytes_per_msg);\n const auto rdma_x_vec = reinterpret_cast(reinterpret_cast(rdma_x_src_idx) + sizeof(int4));\n const auto rdma_x_scales = reinterpret_cast(reinterpret_cast(rdma_x_vec) + hidden_bytes);\n\n // Overlap top-k index read and source token index writes\n auto dst_expert_idx = warp_id < num_topk ? static_cast(__ldg(topk_idx + token_idx * num_topk + warp_id)) : -1;\n thread_id == 0 ? (*rdma_x_src_idx = token_idx) : 0;\n\n // FP8 cast\n EP_STATIC_ASSERT(hidden_bf16_int4 % 32 == 0, \"Must use the full warp to reduce\");\n #pragma unroll\n for (int i = thread_id; i < hidden_bf16_int4; i += num_threads) {\n // Read\n auto int4_value = __ldg(x_int4 + i);\n\n if constexpr (kUseFP8) {\n // Calculate local amax\n auto bf16_values = reinterpret_cast(&int4_value);\n float fp32_values[kNumElemsPerRead];\n float amax = kFP8Margin, scale, scale_inv;\n #pragma unroll\n for (int j = 0; j < kNumElemsPerRead; ++j) {\n fp32_values[j] = static_cast(bf16_values[j]);\n amax = fmaxf(amax, fabsf(fp32_values[j]));\n }\n\n // Reduce amax and scale\n EP_STATIC_ASSERT(kNumElemsPerRead * 32 / kNumPerChannels == 2, \"Invalid vectorization\");\n amax = warp_reduce_max<16>(amax);\n calculate_fp8_scales(amax, scale, scale_inv, round_scale);\n if (lane_id == 0 or lane_id == 16)\n rdma_x_scales[i * kNumElemsPerRead / 128] = scale_inv;\n\n // Cast into send buffer\n vec_t int2_value;\n auto fp8x2_values = reinterpret_cast<__nv_fp8x2_storage_t*>(&int2_value);\n #pragma unroll\n for (int j = 0; j < kNumElemsPerRead; j += 2) {\n float2 fp32x2 = {fp32_values[j] * scale, fp32_values[j + 1] * scale};\n fp8x2_values[j / 2] = __nv_cvt_float2_to_fp8x2(fp32x2, __NV_SATFINITE, __NV_E4M3);\n }\n rdma_x_vec[i] = int2_value;\n } else {\n // Reinterpret-cast is for C++14 compatibility\n rdma_x_vec[i] = *reinterpret_cast(&int4_value);\n }\n }\n asm volatile(\"bar.sync 1, %0;\" ::\"r\"(num_threads));\n\n // Issue IBGDA sends\n if (dst_expert_idx >= 0) {\n int slot_idx = lane_id == 0 ? atomicAdd(atomic_counter_per_expert + dst_expert_idx, 1) : 0;\n slot_idx = __shfl_sync(0xffffffff, slot_idx, 0);\n const auto dst_rank = dst_expert_idx / num_local_experts;\n const auto dst_expert_local_idx = dst_expert_idx % num_local_experts;\n const auto src_ptr = reinterpret_cast(rdma_x_src_idx);\n const auto dst_ptr = reinterpret_cast(rdma_recv_x) +\n dst_expert_local_idx * num_ranks * num_max_dispatch_tokens_per_rank * num_bytes_per_msg +\n rank * num_max_dispatch_tokens_per_rank * num_bytes_per_msg + slot_idx * num_bytes_per_msg;\n const auto dst_p2p_ptr = nvshmemi_get_p2p_ptr(dst_ptr, rank, dst_rank);\n if (not is_rank_masked(mask_buffer_ptr, dst_rank)) {\n if (dst_p2p_ptr == 0) {\n nvshmemi_ibgda_put_nbi_warp(dst_ptr, src_ptr, num_bytes_per_msg, dst_rank, dst_expert_local_idx, lane_id, slot_idx);\n } else {\n // NOTES: only 2 load iterations for 7K hidden with 8 unrolls\n const auto* src_int4_ptr = reinterpret_cast(src_ptr);\n const auto* dst_int4_ptr = reinterpret_cast(dst_p2p_ptr);\n UNROLLED_WARP_COPY(8, lane_id, num_int4_per_msg, dst_int4_ptr, src_int4_ptr, ld_nc_global, st_na_global);\n }\n }\n\n // Increase counter after finishing\n __syncwarp();\n lane_id == 0 ? atomic_add_release_global(atomic_finish_counter_per_expert + dst_expert_idx, 1) : 0;\n }\n }\n } else if (warp_id == num_warps - 1) {\n EP_DEVICE_ASSERT(num_sms > 1);\n if (sm_id == 0) {\n // The first SM is also responsible for checking QPs\n EP_DEVICE_ASSERT(ibgda_get_state()->num_rc_per_pe >= num_local_experts);\n\n // The first SM is also responsible for cleaning the next buffer\n #pragma unroll\n for (int i = lane_id; i < num_next_clean_int; i += 32)\n next_clean[i] = 0;\n\n // Notify before executing `int_p`\n __syncwarp();\n #pragma unroll\n for (int i = lane_id; i < num_experts; i += 32)\n atomic_add_release_global(atomic_finish_counter_per_expert + i, FINISHED_SUM_TAG);\n }\n\n // This SM should be responsible for some destination experts, read `topk_idx` for them\n int expert_count[kNumMaxWarpGroups] = {0};\n const auto expert_begin_idx = sm_id * num_warp_groups;\n const auto expert_end_idx = min(expert_begin_idx + num_warp_groups, num_experts);\n\n // Per lane count\n #pragma unroll 8\n for (int i = lane_id; i < num_tokens * num_topk; i += 32) {\n auto idx = static_cast(__ldg(topk_idx + i));\n if (idx >= expert_begin_idx and idx < expert_end_idx)\n expert_count[idx - expert_begin_idx]++;\n }\n\n // Warp reduce\n #pragma unroll\n for (int i = expert_begin_idx; i < expert_end_idx; ++i) {\n auto sum = warp_reduce_sum(expert_count[i - expert_begin_idx]);\n if (lane_id == 0) {\n shared_num_tokens_sent_per_expert[i - expert_begin_idx] = sum;\n atomic_add_release_global(atomic_finish_counter_per_expert + i, FINISHED_SUM_TAG - sum);\n }\n }\n }\n __syncthreads();\n\n // Issue count sends\n if (responsible_expert_idx < num_experts and sub_warp_id == 0 and lane_id == 0) {\n const auto dst_rank = responsible_expert_idx / num_local_experts;\n const auto dst_expert_local_idx = responsible_expert_idx % num_local_experts;\n const auto num_tokens_sent = shared_num_tokens_sent_per_expert[responsible_expert_idx - sm_id * num_warp_groups];\n\n // Wait local sends issued and send expert counts\n while (ld_acquire_global(atomic_finish_counter_per_expert + responsible_expert_idx) != FINISHED_SUM_TAG * 2)\n ;\n auto dst_ptr = reinterpret_cast(rdma_recv_count + dst_expert_local_idx * num_ranks + rank);\n auto dst_p2p_ptr = nvshmemi_get_p2p_ptr(dst_ptr, rank, dst_rank);\n if (not is_rank_masked(mask_buffer_ptr, dst_rank)) {\n if (dst_p2p_ptr == 0) {\n nvshmemi_ibgda_amo_nonfetch_add(reinterpret_cast(dst_ptr), -num_tokens_sent - 1, dst_rank, dst_expert_local_idx);\n } else {\n st_release_sys_global(reinterpret_cast(dst_p2p_ptr), -num_tokens_sent - 1);\n }\n }\n\n // Clean workspace for next use\n atomic_counter_per_expert[responsible_expert_idx] = 0;\n atomic_finish_counter_per_expert[responsible_expert_idx] = 0;\n\n // Clean `packed_recv_count`\n if (dst_rank == 0)\n packed_recv_count[dst_expert_local_idx] = 0;\n }\n __syncwarp();\n\n// Receiving phase\nLOW_LATENCY_DISPATCH_RECV:\n if ((phases & LOW_LATENCY_RECV_PHASE) == 0)\n return;\n\n // For send-and-recv kernels, we need a grid sync for making `packed_recv_count` visible\n if (phases & LOW_LATENCY_SEND_PHASE)\n cg::this_grid().sync();\n\n // Receiving and packing\n if (responsible_expert_idx < num_experts) {\n const auto src_rank = responsible_expert_idx / num_local_experts;\n const auto local_expert_idx = responsible_expert_idx % num_local_experts;\n const auto rdma_recv_x_uint8 = static_cast(rdma_recv_x) +\n local_expert_idx * num_ranks * num_max_dispatch_tokens_per_rank * num_bytes_per_msg +\n src_rank * num_max_dispatch_tokens_per_rank * num_bytes_per_msg;\n const auto recv_x_int4 =\n static_cast(packed_recv_x) + local_expert_idx * num_ranks * num_max_dispatch_tokens_per_rank * hidden_int4;\n const auto recv_src_info = packed_recv_src_info + local_expert_idx * num_ranks * num_max_dispatch_tokens_per_rank;\n const auto recv_range = packed_recv_layout_range + local_expert_idx * num_ranks;\n const auto num_aligned_scales = align_up(num_scales, sizeof(float) / sizeof(scale_t));\n const auto recv_x_scales = static_cast(packed_recv_x_scales) +\n local_expert_idx * num_ranks * num_max_dispatch_tokens_per_rank * num_aligned_scales;\n\n // Shared between sub-warps in warp groups\n __shared__ int shared_num_recv_tokens[kNumMaxWarpGroups], shared_recv_token_begin_idx[kNumMaxWarpGroups];\n\n // Wait tokens to arrive\n // NOTES: using sub-warp 1 to overlap with sub-warp 0\n int num_recv_tokens = 0, recv_token_begin_idx;\n EP_DEVICE_ASSERT(num_warps_per_group > 1 and num_warp_groups < 15);\n if (sub_warp_id == 1 and lane_id == 0) {\n auto start_time = clock64();\n uint64_t wait_recv_cost = 0;\n if (not is_rank_masked(mask_buffer_ptr, src_rank)) {\n while ((num_recv_tokens = ld_acquire_sys_global(rdma_recv_count + local_expert_idx * num_ranks + src_rank)) ==\n 0 // data not arrived\n && (wait_recv_cost = clock64() - start_time) <= NUM_TIMEOUT_CYCLES // not timeout\n )\n ;\n }\n // Do not receive tokens if rank timeout or masked\n if (num_recv_tokens == 0)\n num_recv_tokens = -1;\n // Mask rank if timeout\n if (wait_recv_cost > NUM_TIMEOUT_CYCLES) {\n printf(\"Warning: DeepEP timeout for dispatch receive, rank %d, local_expert_idx %d, src_rank %d\\n\",\n rank,\n local_expert_idx,\n src_rank);\n if (mask_buffer_ptr == nullptr)\n trap();\n atomicExch(mask_buffer_ptr + src_rank, 1);\n }\n\n num_recv_tokens = -num_recv_tokens - 1;\n recv_token_begin_idx = atomicAdd(packed_recv_count + local_expert_idx, num_recv_tokens);\n shared_num_recv_tokens[warp_group_id] = num_recv_tokens;\n shared_recv_token_begin_idx[warp_group_id] = recv_token_begin_idx;\n recv_range[src_rank] = pack2(num_recv_tokens, recv_token_begin_idx);\n\n // Add stats for diagnosis\n if (cumulative_local_expert_recv_stats != nullptr)\n atomicAdd(cumulative_local_expert_recv_stats + local_expert_idx, num_recv_tokens);\n if (dispatch_wait_recv_cost_stats != nullptr)\n atomicAdd(reinterpret_cast(dispatch_wait_recv_cost_stats + src_rank), wait_recv_cost);\n }\n asm volatile(\"bar.sync %0, %1;\" ::\"r\"(warp_group_id + 2), \"r\"(num_warps_per_group * 32));\n num_recv_tokens = shared_num_recv_tokens[warp_group_id];\n recv_token_begin_idx = shared_recv_token_begin_idx[warp_group_id];\n\n // Copy tokens\n EP_DEVICE_ASSERT(num_scales <= 64);\n for (int i = sub_warp_id; i < num_recv_tokens; i += num_warps_per_group) {\n // Copy source info\n const auto src_src_idx = reinterpret_cast(rdma_recv_x_uint8 + i * num_bytes_per_msg);\n if (lane_id == 0)\n recv_src_info[recv_token_begin_idx + i] = ld_nc_global(src_src_idx);\n __syncwarp();\n\n // Copy data\n // NOTES: only 2 load iterations for 7K hidden with 7 unrolls\n const auto src_data = reinterpret_cast(reinterpret_cast(src_src_idx) + sizeof(int4));\n const auto dst_data = recv_x_int4 + (recv_token_begin_idx + i) * hidden_int4;\n UNROLLED_WARP_COPY(7, lane_id, hidden_int4, dst_data, src_data, ld_nc_global, st_na_global);\n\n // Copy scales\n if constexpr (kUseFP8) {\n // Equivalent CuTe layout:\n // (num_tokens, (num_packed, num_elems_per_pack)):(num_elems_per_pack, (num_tokens * num_elems_per_pack, 1))\n const auto src_scales = reinterpret_cast(reinterpret_cast(src_data) + hidden_bytes);\n const auto num_elems_per_pack = static_cast(sizeof(packed_t) / sizeof(scale_t));\n const auto token_idx = recv_token_begin_idx + i;\n const auto token_stride = num_elems_per_pack;\n const auto pack_stride = num_ranks * num_max_dispatch_tokens_per_rank * num_elems_per_pack;\n if (lane_id < num_scales) {\n const auto pack_idx = lane_id / num_elems_per_pack;\n const auto elem_idx = lane_id % num_elems_per_pack;\n auto scale = extract_required_scale_format(ld_nc_global(src_scales + lane_id));\n recv_x_scales[token_idx * token_stride + pack_idx * pack_stride + elem_idx] = scale;\n }\n if (lane_id + 32 < num_scales) {\n const auto pack_idx = (lane_id + 32) / num_elems_per_pack;\n const auto elem_idx = (lane_id + 32) % num_elems_per_pack;\n auto scale = extract_required_scale_format(ld_nc_global(src_scales + lane_id + 32));\n recv_x_scales[token_idx * token_stride + pack_idx * pack_stride + elem_idx] = scale;\n }\n }\n }\n }\n}\n\nvoid dispatch(void* packed_recv_x,\n void* packed_recv_x_scales,\n int* packed_recv_src_info,\n int64_t* packed_recv_layout_range,\n int* packed_recv_count,\n int* mask_buffer_ptr,\n int* cumulative_local_expert_recv_stats,\n int64_t* dispatch_wait_recv_cost_stats,\n void* rdma_recv_x,\n int* rdma_recv_count,\n void* rdma_x,\n const void* x,\n const topk_idx_t* topk_idx,\n int* next_clean,\n int num_next_clean_int,\n int num_tokens,\n int hidden,\n int num_max_dispatch_tokens_per_rank,\n int num_topk,\n int num_experts,\n int rank,\n int num_ranks,\n bool use_fp8,\n bool round_scale,\n bool use_ue8m0,\n void* workspace,\n int num_device_sms,\n cudaStream_t stream,\n int phases) {\n constexpr int kNumMaxTopK = 11;\n const int num_warp_groups = ceil_div(num_experts, num_device_sms);\n const int num_warps_per_group = 32 / num_warp_groups;\n EP_HOST_ASSERT(num_warp_groups > 0 and num_warps_per_group > 0);\n EP_HOST_ASSERT(kNumMaxTopK + 1 <= num_warp_groups * num_warps_per_group);\n\n const auto num_warps = num_warp_groups * num_warps_per_group;\n const auto num_sms = ceil_div(num_experts, num_warp_groups);\n EP_HOST_ASSERT(num_topk <= kNumMaxTopK);\n\n // Workspace checks\n auto atomic_counter_per_expert = static_cast(workspace);\n auto atomic_finish_counter_per_expert = atomic_counter_per_expert + num_experts;\n EP_HOST_ASSERT(num_experts * sizeof(int) * 2 <= NUM_WORKSPACE_BYTES);\n\n // FP8 checks\n if (use_ue8m0)\n EP_HOST_ASSERT(round_scale and \"UE8M0 SF requires `round_scale=True`\");\n\n#define DISPATCH_LAUNCH_CASE(hidden) \\\n { \\\n auto dispatch_func = dispatch