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Repository: dpretet/async_fifo
Branch: master
Commit: 38c22208d394
Files: 30
Total size: 5.1 MB
Directory structure:
gitextract_ej50xux_/
├── .github/
│ └── workflows/
│ └── ci.yaml
├── .gitignore
├── LICENSE
├── README.md
├── doc/
│ ├── specification.rst
│ └── testplan.rst
├── flow.sh
├── rtl/
│ ├── async_bidir_fifo.list
│ ├── async_bidir_fifo.v
│ ├── async_bidir_ramif_fifo.list
│ ├── async_bidir_ramif_fifo.v
│ ├── async_fifo.list
│ ├── async_fifo.v
│ ├── fifomem.v
│ ├── fifomem_dp.v
│ ├── rptr_empty.v
│ ├── sync_ptr.v
│ ├── sync_r2w.v
│ ├── sync_w2r.v
│ └── wptr_full.v
├── script/
│ └── setup.sh
├── sim/
│ ├── Makefile
│ ├── async_fifo_unit_test.sv
│ ├── files.f
│ ├── svut_h.sv
│ └── wave.gtkw
└── syn/
├── cmos.lib
├── fifo.ys
├── syn_asic.sh
└── vsclib013.lib
================================================
FILE CONTENTS
================================================
================================================
FILE: .github/workflows/ci.yaml
================================================
name: Async_FIFO
on: [push]
jobs:
Lint:
runs-on: macos-latest
steps:
- uses: actions/checkout@v2
- run: brew install verilator
- run: ./flow.sh lint
Simulation:
runs-on: macos-latest
steps:
- uses: actions/checkout@v2
- run: brew install verilator
- run: brew install icarus-verilog
- run: ./flow.sh sim
Synthesis:
runs-on: macos-latest
steps:
- uses: actions/checkout@v2
- run: brew install yosys
- run: ./flow.sh syn
================================================
FILE: .gitignore
================================================
*.out
*.vcd
*.lxt
.DS_Store
tags
lint.log script src
async_fifo_syn.v
lint.log
================================================
FILE: LICENSE
================================================
The MIT License
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and
associated documentation files (the "Software"), to deal in the Software without restriction,
including without limitation the rights to use, copy, modify, merge, publish, distribute,
sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT
NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. limitations under the License.
================================================
FILE: README.md
================================================
# Asynchronous dual clock FIFO
[](https://github.com/dpretet/async_fifo/issues)
[](https://github.com/dpretet/async_fifo/network)
[](https://github.com/dpretet/async_fifo/stargazers)
[](https://github.com/dpretet/async_fifo/blob/master/LICENSE)
# Overview
This repository stores a verilog description of dual clock FIFO. A FIFO is
a convenient circuit to exchange data between two clock domains. It manages
the RAM addressing internally, the clock domain crossing and informs the user
of the FIFO fillness with "full" and "empty" flags.
It is widely inspired by the excellent article from Clifford Cummings,
[Simulation and Synthesis Techniques for Asynchronous FIFO
Design](http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf).
The simulation testcases available use [Icarus Verilog](http://iverilog.icarus.com) and [SVUT](https://github.com/dpretet/svut) tool to run the tests.
The FIFO is fully functional and used in many successful projects.
# Usage
RTL sources are present in RTL folder under three flavors:
- `rtl/async_fifo.v`: a basic asynchronous dual-clock FIFO
- `rtl/async_bidir_fifo.v`: two instance of the first one into a single top level for full-duplex channel
- `rtl/async_bidir_ramif_fifo.v`: same than previous but with external RAM
The three FIFOs have a list file to get the associated fileset.
The testbench in `sim/` provides an example about the instance and the configuration.
All three top levels have the same parameters:
- `DSIZE`: the size in bits of the datapath
- `ASIZE`: the size in bits of the internal RAM address bus. This implies the FIFO can be configured only with power of 2 depth
- `FALLTHROUGH`: allow to reduce the inner latency and propagate faster the data through the FIFO
# License
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE. imitations under the License.
================================================
FILE: doc/specification.rst
================================================
Specification
=============
* The module is a full synchronized module, working on clock rising edge.
* It can be put under reset on both sides. For proper behavior, both sides
have to be reset at the same time before any usage.
* It can be synthetized either for ASIC or FPGAs.
* It can be configured for any data bus width, specified in bits.
* Its depth can be configured in bytes.
* If the FIFO depth is not modulo the datapath, the real FIFO depth infered
is round up to the next datapath width. For instance, if the datapath width
is 16 bytes and the depth specified being 20 bytes, the effective FIFO size
will be 32 bytes
* If the depth is modulo the datapath, the specified depth will be the
effective depth
* Write interface usage:
* A write enable control (`wren`), enabling the data recording. This control
increments the write pointer to point the next RAM address to write. `wren`
doesn't have to be asserted when "full" flag is asserted. The word passed
to the write side will be losted. `wren` can be asserted continuously, or
occasionally.
* A full flag is asserted when the FIFO is full. The flag is asserted on the
next clock cycle the last available word has been written if no data has
been read.
* Read interface usage:
* A read enable control (`rden`), enabling the data read. This control
increments the read pointer to address the next word to read. `rden`
doesn't have to be asserted when empty flag is enabled. If asserted, the
data under read can be a valid data. `rden` can be asserted continuously,
or occasionally.
* An empty flag is asserted when the FIFO is empty. The flag is asserted on
the next clock cycle last available word has been read if no further info
has been stored.
================================================
FILE: doc/testplan.rst
================================================
Testplan
========
This document describes the faetures to test,
and the general scenarios to put in place to stress
the IP behavior:
Clock frequency relationship
----------------------------
A first focus is put in write vs read frequency relation:
1. Test the same clock frequency on both sides. Phases can be equal or not.
2. Test slower clock on write side
- clock can be close to read frequency, but slower
- clock can be very regarding read frequency
3. Test higher clock on write side
- clock can be close to read frequency, but higher
- clock can be very high regarding read frequency
Read/Write enable control assertion
-----------------------------------
A second focus is put on read/write enable assertion:
1. Read enable is always enable, unless empty = 1
- Write enable is always asserted, data are not corrupted
- Write enable can be occasionaly asserted, data are not corrupted
2. Write enable is always enable, unless full = 1
- Read enable is always asserted, data are not corrupted
- Read enable can be occasionaly asserted, data are not corrupted
3. Read and Write enable can be occasionaly asserted
- Assertion frequency (either read or write) is periodic (1/2, 1/3, 1/2, ...)
- Assertion frequecy is (pseudo) random
Test coverage
-------------
To ensure a wide feature feature coverage is performed, both clock frequency scale and
read/write enable assertions have to be tested together. Big range over higher frequency
scale factor doesn't have to considered. Only few combinations can be tested for
good confidence on the IP behavior.
================================================
FILE: flow.sh
================================================
#!/usr/bin/env bash
# -e: exit if one command fails
# -u: treat unset variable as an error
# -f: disable filename expansion upon seeing *, ?, ...
# -o pipefail: causes a pipeline to fail if any command fails
set -e -o pipefail
# Current script path; doesn't support symlink
FIFO_DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
# Bash color codes
Red='\033[0;31m'
Green='\033[0;32m'
Yellow='\033[0;33m'
Blue='\033[0;34m'
# Reset
NC='\033[0m'
function printerror {
echo -e "${Red}ERROR: ${1}${NC}"
}
function printwarning {
echo -e "${Yellow}WARNING: ${1}${NC}"
}
function printinfo {
echo -e "${Blue}INFO: ${1}${NC}"
}
function printsuccess {
echo -e "${Green}SUCCESS: ${1}${NC}"
}
help() {
echo -e "${Blue}"
echo ""
echo "NAME"
echo ""
echo " Async FIFO Flow"
echo ""
echo "SYNOPSIS"
echo ""
echo " ./flow.sh -h"
echo ""
echo " ./flow.sh help"
echo ""
echo " ./flow.sh syn"
echo ""
echo " ./flow.sh sim"
echo ""
echo "DESCRIPTION"
echo ""
echo " This flow handles the different operations available"
echo ""
echo " ./flow.sh help|-h"
echo ""
echo " Print the help menu"
echo ""
echo " ./flow.sh syn"
echo ""
echo " Launch the synthesis script relying on Yosys"
echo ""
echo " ./flow.sh sim"
echo -e "${NC}"
}
run_sims() {
printinfo "Start simulation"
cd "$FIFO_DIR"/sim
svutRun -f files.f -test async_fifo_unit_test.sv -sim icarus
return $?
}
run_syn() {
printinfo "Start synthesis"
cd "$FIFO_DIR/syn"
./syn_asic.sh
return $?
}
run_lint() {
set +e
printinfo "Start lint"
verilator --lint-only +1800-2017ext+sv \
-Wall -Wpedantic \
-Wno-VARHIDDEN \
-Wno-PINCONNECTEMPTY \
-Wno-PINMISSING \
./rtl/async_fifo.v \
./rtl/fifomem.v \
./rtl/rptr_empty.v \
./rtl/sync_r2w.v \
./rtl/sync_w2r.v \
./rtl/wptr_full.v \
--top-module async_fifo 2> lint.log
set -e
ec=$(grep -c "%Error:" lint.log)
if [[ $ec -gt 1 ]]; then
printerror "Lint failed, check ./lint.log for further details"
return 1
else
printsuccess "Lint ran successfully"
return 0
fi
}
check_setup() {
source script/setup.sh
if [[ ! $(type iverilog) ]]; then
printerror "Icarus-Verilog is not installed"
exit 1
fi
if [[ ! $(type verilator) ]]; then
printerror "Verilator is not installed"
exit 1
fi
}
main() {
echo ""
printinfo "Start Aync FIFO Flow"
# If no argument provided, preint help and exit
if [[ $# -eq 0 ]]; then
help
exit 1
fi
# Print help
if [[ $1 == "-h" || $1 == "help" ]]; then
help
exit 0
fi
if [[ $1 == "lint" ]]; then
run_lint
exit $?
fi
if [[ $1 == "sim" ]]; then
check_setup
run_sims
exit $?
fi
if [[ $1 == "syn" ]]; then
run_syn
return $?
fi
}
main "$@"
================================================
FILE: rtl/async_bidir_fifo.list
================================================
async_bidir_fifo.v
fifomem.v
fifomem_dp.v
rptr_empty.v
sync_ptr.v
sync_r2w.v
sync_w2r.v
wptr_full.v
================================================
FILE: rtl/async_bidir_fifo.v
================================================
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
// Copyright 2018 Julius Baxter
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module async_bidir_fifo
#(
parameter DSIZE = 8,
parameter ASIZE = 4,
parameter FALLTHROUGH = "TRUE" // First word fall-through
) (
input wire a_clk,
input wire a_rst_n,
input wire a_winc,
input wire [DSIZE-1:0] a_wdata,
input wire a_rinc,
output wire [DSIZE-1:0] a_rdata,
output wire a_full,
output wire a_afull,
output wire a_empty,
output wire a_aempty,
input wire a_dir, // dir = 1: this side is writing, dir = 0: this side is reading
input wire b_clk,
input wire b_rst_n,
input wire b_winc,
input wire [DSIZE-1:0] b_wdata,
input wire b_rinc,
output wire [DSIZE-1:0] b_rdata,
output wire b_full,
output wire b_afull,
output wire b_empty,
output wire b_aempty,
input wire b_dir // dir = 1: this side is writing, dir = 0: this side is reading
);
wire [ASIZE-1:0] a_addr, b_addr;
wire [ASIZE-1:0] a_waddr, a_raddr, b_waddr, b_raddr;
wire [ ASIZE:0] a_wptr, b_rptr, a2b_wptr, b2a_rptr;
wire [ ASIZE:0] a_rptr, b_wptr, a2b_rptr, b2a_wptr;
assign a_addr = a_dir ? a_waddr : a_raddr;
assign b_addr = b_dir ? b_waddr : b_raddr;
//////////////////////////////////////////////////////////////////////////////
// A-side logic
//////////////////////////////////////////////////////////////////////////////
// Sync b write pointer to a domain
sync_ptr #(ASIZE)
sync_b2a_wptr
(
.dest_clk (a_clk),
.dest_rst_n (a_rst_n),
.src_ptr (b_wptr),
.dest_ptr (b2a_wptr)
);
// Sync b read pointer to a domain
sync_ptr #(ASIZE)
sync_b2a_rptr
(
.dest_clk (a_clk),
.dest_rst_n (a_rst_n),
.src_ptr (b_rptr),
.dest_ptr (b2a_rptr)
);
// The module handling the write requests
// outputs valid when dir == 0 (a is writing)
wptr_full #(ASIZE)
a_wptr_inst
(
.wclk (a_clk),
.wrst_n (a_rst_n),
.winc (a_winc),
.wq2_rptr (b2a_rptr),
.awfull (a_afull),
.wfull (a_full),
.waddr (a_waddr),
.wptr (a_wptr)
);
// dir == 1 read pointer on a side calculation
rptr_empty #(ASIZE)
a_rptr_inst
(
.rclk (a_clk),
.rrst_n (a_rst_n),
.rinc (a_rinc),
.rq2_wptr (b2a_wptr),
.arempty (a_aempty),
.rempty (a_empty),
.raddr (a_raddr),
.rptr (a_rptr)
);
//////////////////////////////////////////////////////////////////////////////
// B-side logic
//////////////////////////////////////////////////////////////////////////////
// Sync a write pointer to b domain
sync_ptr #(ASIZE)
sync_a2b_wptr
(
.dest_clk (b_clk),
.dest_rst_n (b_rst_n),
.src_ptr (a_wptr),
.dest_ptr (a2b_wptr)
);
// Sync a read pointer to b domain
sync_ptr #(ASIZE)
sync_a2b_rptr
(
.dest_clk (b_clk),
.dest_rst_n (b_rst_n),
.src_ptr (a_rptr),
.dest_ptr (a2b_rptr)
);
// The module handling the write requests
// outputs valid when dir == 0 (b is writing)
wptr_full #(ASIZE)
b_wptr_inst
(
.wclk (b_clk),
.wrst_n (b_rst_n),
.winc (b_winc),
.wq2_rptr (a2b_rptr),
.awfull (b_afull),
.wfull (b_full),
.waddr (b_waddr),
.wptr (b_wptr)
);
// dir == 1 read pointer on b side calculation
rptr_empty #(ASIZE)
b_rptr_inst
(
.rclk (b_clk),
.rrst_n (b_rst_n),
.rinc (b_rinc),
.rq2_wptr (a2b_wptr),
.arempty (b_aempty),
.rempty (b_empty),
.raddr (b_raddr),
.rptr (b_rptr)
);
//////////////////////////////////////////////////////////////////////////////
// FIFO RAM
//////////////////////////////////////////////////////////////////////////////
fifomem_dp #(DSIZE, ASIZE, FALLTHROUGH)
fifomem_dp
(
.a_clk (a_clk),
.a_wdata (a_wdata),
.a_rdata (a_rdata),
.a_addr (a_addr),
.a_rinc (a_rinc & !a_dir),
.a_winc (a_winc & a_dir),
.b_clk (b_clk),
.b_wdata (b_wdata),
.b_rdata (b_rdata),
.b_addr (b_addr),
.b_rinc (b_rinc & !b_dir),
.b_winc (b_winc & b_dir)
);
endmodule
`resetall
================================================
FILE: rtl/async_bidir_ramif_fifo.list
================================================
async_bidir_ramif_fifo.v
fifomem.v
fifomem_dp.v
rptr_empty.v
sync_ptr.v
sync_r2w.v
sync_w2r.v
wptr_full.v
================================================
FILE: rtl/async_bidir_ramif_fifo.v
================================================
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
// Copyright 2018 Julius Baxter
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module async_bidir_ramif_fifo
#(
parameter DSIZE = 8,
parameter ASIZE = 4,
parameter FALLTHROUGH = "FALSE" // First word fall-through, not sure it can be disabled for this
) (
input wire a_clk,
input wire a_rst_n,
input wire a_winc,
input wire [DSIZE-1:0] a_wdata,
input wire a_rinc,
output wire [DSIZE-1:0] a_rdata,
output wire a_full,
output wire a_afull,
output wire a_empty,
output wire a_aempty,
input wire a_dir, // dir = 1: this side is writing, dir = 0: this side is reading
input wire b_clk,
input wire b_rst_n,
input wire b_winc,
input wire [DSIZE-1:0] b_wdata,
input wire b_rinc,
output wire [DSIZE-1:0] b_rdata,
output wire b_full,
output wire b_afull,
output wire b_empty,
output wire b_aempty,
input wire b_dir, // dir = 1: this side is writing, dir = 0: this side is reading
// Dual-port RAM interface
output wire o_ram_a_clk,
output wire [DSIZE-1:0] o_ram_a_wdata,
input wire [DSIZE-1:0] i_ram_a_rdata,
output wire [ASIZE-1:0] o_ram_a_addr,
output wire o_ram_a_rinc,
output wire o_ram_a_winc,
output wire o_ram_b_clk,
output wire [DSIZE-1:0] o_ram_b_wdata,
input wire [DSIZE-1:0] i_ram_b_rdata,
output wire [ASIZE-1:0] o_ram_b_addr,
output wire o_ram_b_rinc,
output wire o_ram_b_winc
);
wire [ASIZE-1:0] a_addr, b_addr;
wire [ASIZE-1:0] a_waddr, a_raddr, b_waddr, b_raddr;
wire [ ASIZE:0] a_wptr, b_rptr, a2b_wptr, b2a_rptr;
wire [ ASIZE:0] a_rptr, b_wptr, a2b_rptr, b2a_wptr;
assign a_addr = a_dir ? a_waddr : a_raddr;
assign b_addr = b_dir ? b_waddr : b_raddr;
//////////////////////////////////////////////////////////////////////////////
// A-side logic
//////////////////////////////////////////////////////////////////////////////
// Sync b write pointer to a domain
sync_ptr #(ASIZE)
sync_b2a_wptr
(
.dest_clk (a_clk),
.dest_rst_n (a_rst_n),
.src_ptr (b_wptr),
.dest_ptr (b2a_wptr)
);
// Sync b read pointer to a domain
sync_ptr #(ASIZE)
sync_b2a_rptr
(
.dest_clk (a_clk),
.dest_rst_n (a_rst_n),
.src_ptr (b_rptr),
.dest_ptr (b2a_rptr)
);
// The module handling the write requests
// outputs valid when dir == 0 (a is writing)
wptr_full #(ASIZE)
a_wptr_inst
(
.wclk (a_clk),
.wrst_n (a_rst_n),
.winc (a_winc),
.wq2_rptr (b2a_rptr),
.awfull (a_afull),
.wfull (a_full),
.waddr (a_waddr),
.wptr (a_wptr)
);
// dir == 1 read pointer on a side calculation
rptr_empty #(ASIZE)
a_rptr_inst
(
.rclk (a_clk),
.rrst_n (a_rst_n),
.rinc (a_rinc),
.rq2_wptr (b2a_wptr),
.arempty (a_aempty),
.rempty (a_empty),
.raddr (a_raddr),
.rptr (a_rptr)
);
//////////////////////////////////////////////////////////////////////////////
// B-side logic
//////////////////////////////////////////////////////////////////////////////
// Sync a write pointer to b domain
sync_ptr #(ASIZE)
sync_a2b_wptr
(
.dest_clk (b_clk),
.dest_rst_n (b_rst_n),
.src_ptr (a_wptr),
.dest_ptr (a2b_wptr)
);
// Sync a read pointer to b domain
sync_ptr #(ASIZE)
sync_a2b_rptr
(
.dest_clk (b_clk),
.dest_rst_n (b_rst_n),
.src_ptr (a_rptr),
.dest_ptr (a2b_rptr)
);
// The module handling the write requests
// outputs valid when dir == 0 (b is writing)
wptr_full #(ASIZE)
b_wptr_inst
(
.wclk (b_clk),
.wrst_n (b_rst_n),
.winc (b_winc),
.wq2_rptr (a2b_rptr),
.awfull (b_afull),
.wfull (b_full),
.waddr (b_waddr),
.wptr (b_wptr)
);
// dir == 1 read pointer on b side calculation
rptr_empty #(ASIZE)
b_rptr_inst
(
.rclk (b_clk),
.rrst_n (b_rst_n),
.rinc (b_rinc),
.rq2_wptr (a2b_wptr),
.arempty (b_aempty),
.rempty (b_empty),
.raddr (b_raddr),
.rptr (b_rptr)
);
//////////////////////////////////////////////////////////////////////////////
// FIFO RAM interface
//////////////////////////////////////////////////////////////////////////////
assign o_ram_a_clk = a_clk;
assign o_ram_a_wdata = a_wdata;
assign a_rdata = i_ram_a_rdata;
assign o_ram_a_addr = a_addr;
assign o_ram_a_rinc = a_rinc & !a_dir;
assign o_ram_a_winc = a_winc & a_dir;
assign o_ram_b_clk = b_clk;
assign o_ram_b_wdata = b_wdata;
assign b_rdata = i_ram_b_rdata;
assign o_ram_b_addr = b_addr;
assign o_ram_b_rinc = b_rinc & !b_dir;
assign o_ram_b_winc = b_winc & b_dir;
endmodule
`resetall
================================================
FILE: rtl/async_fifo.list
================================================
async_fifo.v
fifomem.v
fifomem_dp.v
hdl.list
rptr_empty.v
sync_ptr.v
sync_r2w.v
sync_w2r.v
wptr_full.v
================================================
FILE: rtl/async_fifo.v
================================================
// distributed under the mit license
// https://opensource.org/licenses/mit-license.php
`timescale 1 ns / 1 ps
`default_nettype none
module async_fifo
#(
parameter DSIZE = 8,
parameter ASIZE = 4,
parameter FALLTHROUGH = "TRUE" // First word fall-through without latency
)(
input wire wclk,
input wire wrst_n,
input wire winc,
input wire [DSIZE-1:0] wdata,
output wire wfull,
output wire awfull,
input wire rclk,
input wire rrst_n,
input wire rinc,
output wire [DSIZE-1:0] rdata,
output wire rempty,
output wire arempty
);
wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE :0] wptr, rptr, wq2_rptr, rq2_wptr;
// The module synchronizing the read point
// from read to write domain
sync_r2w
#(ASIZE)
sync_r2w (
.wq2_rptr (wq2_rptr),
.rptr (rptr),
.wclk (wclk),
.wrst_n (wrst_n)
);
// The module synchronizing the write point
// from write to read domain
sync_w2r
#(ASIZE)
sync_w2r (
.rq2_wptr (rq2_wptr),
.wptr (wptr),
.rclk (rclk),
.rrst_n (rrst_n)
);
// The module handling the write requests
wptr_full
#(ASIZE)
wptr_full (
.awfull (awfull),
.wfull (wfull),
.waddr (waddr),
.wptr (wptr),
.wq2_rptr (wq2_rptr),
.winc (winc),
.wclk (wclk),
.wrst_n (wrst_n)
);
// The DC-RAM
fifomem
#(DSIZE, ASIZE, FALLTHROUGH)
fifomem (
.rclken (rinc),
.rclk (rclk),
.rdata (rdata),
.wdata (wdata),
.waddr (waddr),
.raddr (raddr),
.wclken (winc),
.wfull (wfull),
.wclk (wclk)
);
// The module handling read requests
rptr_empty
#(ASIZE)
rptr_empty (
.arempty (arempty),
.rempty (rempty),
.raddr (raddr),
.rptr (rptr),
.rq2_wptr (rq2_wptr),
.rinc (rinc),
.rclk (rclk),
.rrst_n (rrst_n)
);
endmodule
`resetall
================================================
FILE: rtl/fifomem.v
================================================
// distributed under the mit license
// https://opensource.org/licenses/mit-license.php
`timescale 1 ns / 1 ps
`default_nettype none
module fifomem
#(
parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 4, // Number of mem address bits
parameter FALLTHROUGH = "TRUE" // First word fall-through
) (
input wire wclk,
input wire wclken,
input wire [ADDRSIZE-1:0] waddr,
input wire [DATASIZE-1:0] wdata,
input wire wfull,
input wire rclk,
input wire rclken,
input wire [ADDRSIZE-1:0] raddr,
output wire [DATASIZE-1:0] rdata
);
localparam DEPTH = 1<<ADDRSIZE;
reg [DATASIZE-1:0] mem [0:DEPTH-1];
reg [DATASIZE-1:0] rdata_r;
always @(posedge wclk) begin
if (wclken && !wfull)
mem[waddr] <= wdata;
end
generate
if (FALLTHROUGH == "TRUE")
begin : fallthrough
assign rdata = mem[raddr];
end
else
begin : registered_read
always @(posedge rclk) begin
if (rclken)
rdata_r <= mem[raddr];
end
assign rdata = rdata_r;
end
endgenerate
endmodule
`resetall
================================================
FILE: rtl/fifomem_dp.v
================================================
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
// Copyright 2018 Julius Baxter
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module fifomem_dp
#(
parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 4, // Number of mem address bits
parameter FALLTHROUGH = "TRUE" // First word fall-through
) (
input wire a_clk,
input wire [DATASIZE-1:0] a_wdata,
output wire [DATASIZE-1:0] a_rdata,
input wire [ADDRSIZE-1:0] a_addr,
input wire a_rinc,
input wire a_winc,
input wire b_clk,
input wire [DATASIZE-1:0] b_wdata,
output wire [DATASIZE-1:0] b_rdata,
input wire [ADDRSIZE-1:0] b_addr,
input wire b_rinc,
input wire b_winc
);
reg [DATASIZE-1:0] a_rdata_r;
reg [DATASIZE-1:0] b_rdata_r;
generate
localparam DEPTH = 1<<ADDRSIZE;
reg [DATASIZE-1:0] mem [0:DEPTH-1];
if (FALLTHROUGH == "TRUE") begin : fallthrough
always @(posedge a_clk)
if (a_winc)
mem[a_addr] <= a_wdata;
assign a_rdata = mem[a_addr];
always @(posedge b_clk)
if (b_winc)
mem[b_addr] <= b_wdata;
assign b_rdata = mem[b_addr];
end else begin : registered
wire a_en = a_rinc | a_winc;
always @(posedge a_clk)
if (a_en) begin
if (a_winc)
mem[a_addr] <= a_wdata;
a_rdata_r <= mem[a_addr];
end
assign a_rdata = a_rdata_r;
wire b_en = b_rinc | b_winc;
always @(posedge b_clk)
if (b_en) begin
if (b_winc)
mem[b_addr] <= b_wdata;
b_rdata_r <= mem[b_addr];
end
assign b_rdata = b_rdata_r;
end // block: registered
endgenerate
endmodule
`resetall
================================================
FILE: rtl/rptr_empty.v
================================================
// distributed under the mit license
// https://opensource.org/licenses/mit-license.php
`timescale 1 ns / 1 ps
`default_nettype none
module rptr_empty
#(
parameter ADDRSIZE = 4
)(
input wire rclk,
input wire rrst_n,
input wire rinc,
input wire [ADDRSIZE :0] rq2_wptr,
output reg rempty,
output reg arempty,
output wire [ADDRSIZE-1:0] raddr,
output reg [ADDRSIZE :0] rptr
);
reg [ADDRSIZE:0] rbin;
wire [ADDRSIZE:0] rgraynext, rbinnext, rgraynextm1;
wire arempty_val, rempty_val;
//-------------------
// GRAYSTYLE2 pointer
//-------------------
always @(posedge rclk or negedge rrst_n) begin
if (!rrst_n)
{rbin, rptr} <= 0;
else
{rbin, rptr} <= {rbinnext, rgraynext};
end
// Memory read-address pointer (okay to use binary to address memory)
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + ((rinc & ~rempty) ? 1 : 0);
assign rgraynext = (rbinnext >> 1) ^ rbinnext;
assign rgraynextm1 = ((rbinnext + 1'b1) >> 1) ^ (rbinnext + 1'b1);
//---------------------------------------------------------------
// FIFO empty when the next rptr == synchronized wptr or on reset
//---------------------------------------------------------------
assign rempty_val = (rgraynext == rq2_wptr);
assign arempty_val = (rgraynextm1 == rq2_wptr);
always @ (posedge rclk or negedge rrst_n) begin
if (!rrst_n) begin
arempty <= 1'b0;
rempty <= 1'b1;
end
else begin
arempty <= arempty_val;
rempty <= rempty_val;
end
end
endmodule
`resetall
================================================
FILE: rtl/sync_ptr.v
================================================
// distributed under the mit license
// https://opensource.org/licenses/mit-license.php
`timescale 1 ns / 1 ps
`default_nettype none
module sync_ptr
#(
parameter ASIZE = 4
)(
input wire dest_clk,
input wire dest_rst_n,
input wire [ASIZE:0] src_ptr,
output reg [ASIZE:0] dest_ptr
);
reg [ASIZE:0] ptr_x;
always @(posedge dest_clk or negedge dest_rst_n) begin
if (!dest_rst_n)
{dest_ptr,ptr_x} <= 0;
else
{dest_ptr,ptr_x} <= {ptr_x,src_ptr};
end
endmodule
`resetall
================================================
FILE: rtl/sync_r2w.v
================================================
// distributed under the mit license
// https://opensource.org/licenses/mit-license.php
`timescale 1 ns / 1 ps
`default_nettype none
module sync_r2w
#(
parameter ASIZE = 4
)(
input wire wclk,
input wire wrst_n,
input wire [ASIZE:0] rptr,
output reg [ASIZE:0] wq2_rptr
);
reg [ASIZE:0] wq1_rptr;
always @(posedge wclk or negedge wrst_n) begin
if (!wrst_n)
{wq2_rptr,wq1_rptr} <= 0;
else
{wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};
end
endmodule
`resetall
================================================
FILE: rtl/sync_w2r.v
================================================
// distributed under the mit license
// https://opensource.org/licenses/mit-license.php
`timescale 1 ns / 1 ps
`default_nettype none
module sync_w2r
#(
parameter ASIZE = 4
)(
input wire rclk,
input wire rrst_n,
output reg [ASIZE:0] rq2_wptr,
input wire [ASIZE:0] wptr
);
reg [ASIZE:0] rq1_wptr;
always @(posedge rclk or negedge rrst_n) begin
if (!rrst_n)
{rq2_wptr,rq1_wptr} <= 0;
else
{rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};
end
endmodule
`resetall
================================================
FILE: rtl/wptr_full.v
================================================
// distributed under the mit license
// https://opensource.org/licenses/mit-license.php
`timescale 1 ns / 1 ps
`default_nettype none
module wptr_full
#(
parameter ADDRSIZE = 4
)(
input wire wclk,
input wire wrst_n,
input wire winc,
input wire [ADDRSIZE :0] wq2_rptr,
output reg wfull,
output reg awfull,
output wire [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE :0] wptr
);
reg [ADDRSIZE:0] wbin;
wire [ADDRSIZE:0] wgraynext, wbinnext, wgraynextp1;
wire awfull_val, wfull_val;
// GRAYSTYLE2 pointer
always @(posedge wclk or negedge wrst_n) begin
if (!wrst_n)
{wbin, wptr} <= 0;
else
{wbin, wptr} <= {wbinnext, wgraynext};
end
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + ((winc & ~wfull) ? 1 : 0);
assign wgraynext = (wbinnext >> 1) ^ wbinnext;
assign wgraynextp1 = ((wbinnext + 1'b1) >> 1) ^ (wbinnext + 1'b1);
//------------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//------------------------------------------------------------------
assign wfull_val = (wgraynext == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
assign awfull_val = (wgraynextp1 == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
always @(posedge wclk or negedge wrst_n) begin
if (!wrst_n) begin
awfull <= 1'b0;
wfull <= 1'b0;
end else begin
awfull <= awfull_val;
wfull <= wfull_val;
end
end
endmodule
`resetall
================================================
FILE: script/setup.sh
================================================
#!/usr/bin/env bash
# get current script path (applicable even if is a symlink)
SOURCE="${BASH_SOURCE[0]}"
while [ -h "$SOURCE" ]; do
DIR="$( cd -P "$( dirname "$SOURCE" )" >/dev/null 2>&1 && pwd )"
SOURCE="$(readlink "$SOURCE")"
[[ $SOURCE != /* ]] && SOURCE="$DIR/$SOURCE"
done
DIR="$( cd -P "$( dirname "$SOURCE" )" >/dev/null 2>&1 && pwd )"
if [[ ! $(type svutRun) ]];
then
svut_dir="$DIR/.svut"
if [[ ! -d $svut_dir ]]; then
echo "INFO: Install SVUT (https://github.com/dpretet/svut)"
git clone "https://github.com/dpretet/svut.git" "$svut_dir"
fi
echo "INFO: Enable SVUT in PATH"
export PATH=$svut_dir/:$PATH
fi
================================================
FILE: sim/Makefile
================================================
test:
@svutRun -f files.f -define "AFULL=1;AEMPTY=1"
@svutRun -f files.f -define "AFULL=3;AEMPTY=2"
test-dry-run:
@svutRun -f files.f -dry-run
gui:
@svutRun -f files.f -gui
clean:
@-rm -f *.vcd
@-rm -f *.lxt*
@-rm -f *.vvp*
@-rm -f *.out
================================================
FILE: sim/async_fifo_unit_test.sv
================================================
`include "svut_h.sv"
`timescale 1 ns / 1 ps
module async_fifo_unit_test;
`SVUT_SETUP
`ifndef AEMPTY
`define AEMPTY 1
`endif
`ifndef AFULL
`define AFULL 1
`endif
`ifndef FALLTHROUGH
`define FALLTHROUGH "TRUE"
`endif
parameter DSIZE = 32;
parameter ASIZE = 4;
parameter FALLTHROUGH = `FALLTHROUGH;
parameter MAX_TRAFFIC = 10;
integer timeout;
reg wclk;
reg wrst_n;
reg winc;
reg [DSIZE-1:0] wdata;
wire wfull;
wire awfull;
reg rclk;
reg rrst_n;
reg rinc;
wire [DSIZE-1:0] rdata;
wire rempty;
wire arempty;
async_fifo
#(
.DSIZE (DSIZE),
.ASIZE (ASIZE),
.FALLTHROUGH (FALLTHROUGH)
)
dut
(
wclk,
wrst_n,
winc,
wdata,
wfull,
awfull,
rclk,
rrst_n,
rinc,
rdata,
rempty,
arempty
);
// An example to create a clock
initial wclk = 1'b0;
always #2 wclk <= ~wclk;
initial rclk = 1'b0;
always #3 rclk <= ~rclk;
// An example to dump data for visualization
initial begin
$dumpfile("async_fifo_unit_test.vcd");
$dumpvars(0, async_fifo_unit_test);
end
task setup(msg="Setup testcase");
begin
wrst_n = 1'b0;
winc = 1'b0;
wdata = 0;
rrst_n = 1'b0;
rinc = 1'b0;
#100;
wrst_n = 1;
rrst_n = 1;
#50;
timeout = 0;
@(posedge wclk);
end
endtask
task teardown(msg="Tearing down");
begin
#50;
end
endtask
`TEST_SUITE("ASYNCFIFO")
`UNIT_TEST("TEST_IDLE")
`FAIL_IF(wfull);
`FAIL_IF(!rempty);
`UNIT_TEST_END
`UNIT_TEST("TEST_SINGLE_WRITE_THEN_READ")
@(posedge wclk)
winc = 1;
wdata = 32'hA;
@(posedge wclk)
winc = 0;
@(posedge rclk)
wait (rempty == 1'b0);
rinc = 1;
@(negedge rclk)
`FAIL_IF_NOT_EQUAL(rdata, 32'hA);
`UNIT_TEST_END
`UNIT_TEST("TEST_MULTIPLE_WRITE_THEN_READ")
for (int i=0; i<10; i=i+1) begin
@(negedge wclk);
winc = 1;
wdata = i;
end
@(negedge wclk);
winc = 0;
#100;
@(posedge rclk);
rinc = 1;
for (int i=0; i<10; i=i+1) begin
@(posedge rclk);
`FAIL_IF_NOT_EQUAL(rdata, i);
end
`UNIT_TEST_END
`UNIT_TEST("TEST_FULL_FLAG")
winc = 1;
for (int i=0; i<2**ASIZE; i=i+1) begin
@(negedge wclk)
wdata = i;
end
@(negedge wclk);
winc = 0;
@(posedge wclk)
`FAIL_IF_NOT_EQUAL(wfull, 1);
`UNIT_TEST_END
`UNIT_TEST("TEST_EMPTY_FLAG")
`FAIL_IF_NOT_EQUAL(rempty, 1);
for (int i=0; i<2**ASIZE; i=i+1) begin
@(posedge wclk)
winc = 1;
wdata = i;
end
`FAIL_IF_NOT_EQUAL(rempty, 0);
`UNIT_TEST_END
`UNIT_TEST("TEST_ALMOST_EMPTY_FLAG")
`FAIL_IF_NOT_EQUAL(arempty, 0);
winc = 1;
for (int i=0; i<1; i=i+1) begin
@(negedge wclk)
wdata = i;
end
@(negedge wclk);
winc = 0;
#100;
`FAIL_IF_NOT_EQUAL(arempty, 1);
`UNIT_TEST_END
`UNIT_TEST("TEST_ALMOST_FULL_FLAG")
winc = 1;
for (int i=0; i<2**ASIZE-1; i=i+1) begin
@(negedge wclk)
wdata = i;
end
@(negedge wclk);
winc = 0;
@(posedge wclk)
`FAIL_IF_NOT_EQUAL(awfull, 1);
`UNIT_TEST_END
`UNIT_TEST("TEST_CONCURRENT_WRITE_READ")
fork
// Concurrent accesses
begin
fork
// Write source
begin
winc = 1;
for (int i=0; i<MAX_TRAFFIC; i=i+1) begin
while (wfull)
@(negedge wclk);
@(negedge wclk);
wdata = i;
end
winc = 0;
end
// Read sink
begin
for (int i=0; i<MAX_TRAFFIC; i=i+1) begin
while (rempty)
@(posedge rclk);
rinc = 1;
@(negedge rclk);
`FAIL_IF_NOT_EQUAL(rdata, i);
end
rinc = 0;
end
join
end
// Timeout management
begin
while (timeout<10000) begin
timeout = timeout + 1;
@(posedge rclk);
end
`ERROR("Reached timeout!");
end
join_any
`UNIT_TEST_END
`TEST_SUITE_END
endmodule
================================================
FILE: sim/files.f
================================================
../rtl/async_fifo.v
../rtl/fifomem.v
../rtl/rptr_empty.v
../rtl/sync_r2w.v
../rtl/sync_w2r.v
../rtl/wptr_full.v
================================================
FILE: sim/svut_h.sv
================================================
/// Copyright 2021 The SVUT Authors
///
/// Permission is hereby granted, free of charge, to any person obtaining a copy
/// of this software and associated documentation files (the "Software"), to
/// deal in the Software without restriction, including without limitation the
/// rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
/// sell copies of the Software, and to permit persons to whom the Software is
/// furnished to do so, subject to the following conditions:
///
/// The above copyright notice and this permission notice shall be included in
/// all copies or substantial portions of the Software.
///
/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
/// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
/// IN THE SOFTWARE.
`ifndef SVUT_DEFINES
`define SVUT_DEFINES
/// Define colors for $display
/// 1 set bold
/// 2 set half-bright (simulated with color on a color display)
/// 4 set underscore (simulated with color on a color display)
/// 5 set blink
/// 7 set reverse video
`define BLACK "\033[1;30m"
`define RED "\033[1;31m"
`define GREEN "\033[1;32m"
`define BROWN "\033[1;33m"
`define BLUE "\033[1;34m"
`define PINK "\033[1;35m"
`define CYAN "\033[1;36m"
`define WHITE "\033[1;37m"
`define BG_BLACK "\033[1;40m"
`define BG_RED "\033[1;41m"
`define BG_GREEN "\033[1;42m"
`define BG_BROWN "\033[1;43m"
`define BG_BLUE "\033[1;44m"
`define BG_PINK "\033[1;45m"
`define BG_CYAN "\033[1;46m"
`define BG_WHITE "\033[1;47m"
`define NC "\033[0m"
/// Follows a set of ready to use function to print status
/// and information with an appropriate color.
`define MSG(msg) \
$display("\033[0;37m%s (@ %0t)\033[0m", msg, $realtime)
`define INFO(msg) \
$display("\033[0;34mINFO: %s (@ %0t)\033[0m", msg, $realtime)
`define SUCCESS(msg) \
$display("\033[0;32mSUCCESS: %s (@ %0t)\033[0m", msg, $realtime)
`define WARNING(msg) \
begin\
$display("\033[1;33mWARNING: %s (@ %0t)\033[0m", msg, $realtime);\
svut_warning += 1;\
end
`define CRITICAL(msg) \
begin\
$display("\033[1;35mCRITICAL: %s (@ %0t)\033[0m", msg, $realtime);\
svut_critical += 1;\
end
`define ERROR(msg)\
begin\
$display("\033[1;31mERROR: %s (@ %0t)\033[0m", msg, $realtime);\
svut_error += 1;\
end
/// SVUT_SETUP is the code portion initializing all the needed
/// variables. To call once before or after the module instance
`define SVUT_SETUP \
integer svut_test_number = 0; \
string testnum; \
integer svut_status = 0; \
integer svut_warning = 0; \
integer svut_critical = 0; \
integer svut_error = 0; \
integer svut_error_total = 0; \
integer svut_nb_test = 0; \
integer svut_nb_test_success = 0; \
string svut_test_name = ""; \
string svut_suite_name = ""; \
string svut_msg = ""; \
string svut_fail_list = "Failling test(s):";
/// LAST_STATUS is a flag asserted if check the last
/// check function failed
`define LAST_STATUS svut_status
/// This function is shared between assertions to format messages
function automatic string create_msg(input string assertion, message);
if (message != "") begin
create_msg = {message, " (", assertion, ")"};
end else begin
create_msg = assertion;
end
endfunction
/// Follows a set of macros to check an expression
/// or a signal. All use the same syntax:
/// - a signal or an expression to evaluate
/// - an optional message to print if case the
/// evaluation fails.
/// This check fails if expression is not = 0
`define FAIL_IF(exp, message="") \
svut_status = 0; \
svut_msg = create_msg("FAIL_IF", message); \
if (exp) begin \
`ERROR(svut_msg); \
svut_status = 1; \
end
/// This check fails if expression is not > 0
`define FAIL_IF_NOT(exp, message="") \
svut_status = 0; \
svut_msg = create_msg("FAIL_IF_NOT", message); \
if (!exp) begin \
`ERROR(svut_msg); \
svut_status = 1; \
end
/// This check fails if both input are equal
`define FAIL_IF_EQUAL(a,b, message="") \
svut_status = 0; \
svut_msg = create_msg("FAIL_IF_EQUAL", message); \
if (a === b) begin \
`ERROR(svut_msg); \
svut_status = 1; \
end
/// This check fails if both input are not equal
`define FAIL_IF_NOT_EQUAL(a,b, message="") \
svut_status = 0; \
svut_msg = create_msg("FAIL_IF_NOT_EQUAL", message); \
if (a !== b) begin \
`ERROR(svut_msg); \
svut_status = 1; \
end
/// This check fails if expression is not = 0
`define ASSERT(exp, message="") \
svut_status = 0; \
svut_msg = create_msg("ASSERT", message); \
if (!exp) begin \
`ERROR(svut_msg); \
svut_status = 1; \
end
/// This header must be placed to start a test suite execution
`define TEST_SUITE(name="") \
task run(msg=""); \
begin \
svut_suite_name = name; \
$display("");\
svut_msg = {"Start testsuite << ", name, " >>"}; \
`INFO(svut_msg);
/// This header must be placed to start a test execution
`define UNIT_TEST(name="") \
begin \
$display("");\
$sformat(testnum, "%0d", svut_test_number); \
svut_msg = {"Starting << ", "Test ", testnum, ": ", name, " >>"}; \
`INFO(svut_msg); \
setup(); \
svut_test_name = name; \
svut_error = 0; \
svut_nb_test = svut_nb_test + 1;
/// This footer must be placed to close a test
`define UNIT_TEST_END \
teardown(); \
if (svut_error == 0) begin \
svut_nb_test_success = svut_nb_test_success + 1; \
svut_msg = {"Test ", testnum, " pass"}; \
`SUCCESS(svut_msg); \
end else begin \
svut_msg = {"Test ", testnum, " fail"}; \
`ERROR(svut_msg); \
svut_fail_list = {svut_fail_list, " '", svut_test_name, "'"}; \
svut_error_total += svut_error; \
end \
svut_test_number = svut_test_number + 1; \
end
/// This footer must be placed to close a test suite
`define TEST_SUITE_END \
end \
endtask \
initial begin\
run(); \
$display("");\
svut_msg = {"Stop testsuite '", svut_suite_name, "'"}; \
`INFO(svut_msg); \
if (svut_error_total > 0) begin \
$display("\033[1;31m"); \
$display(svut_fail_list); \
$display(""); \
end \
$display(" \033[1;33m- Warning number: %0d\033[0m", svut_warning); \
$display(" \033[1;35m- Critical number: %0d\033[0m", svut_critical); \
$display(" \033[1;31m- Error number: %0d\033[0m", svut_error_total); \
if (svut_nb_test_success != svut_nb_test) begin \
$display(" \033[1;31m- STATUS: %0d/%0d test(s) passed\033[0m\n", svut_nb_test_success, svut_nb_test); \
end else begin \
$display(" \033[0;32m- STATUS: %0d/%0d test(s) passed\033[0m\n", svut_nb_test_success, svut_nb_test); \
end \
$finish(); \
end
`endif
================================================
FILE: sim/wave.gtkw
================================================
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Sat Mar 30 09:48:17 2024
[*]
[dumpfile] "/Users/damien/workspace/hdl/async_fifo/sim/async_fifo_unit_test.vcd"
[dumpfile_mtime] "Sat Mar 30 09:47:41 2024"
[dumpfile_size] 35394
[savefile] "wave.gtkw"
[timestart] 2131420
[size] 1440 784
[pos] -1 -1
*-13.015144 2119510 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] async_fifo_unit_test.
[treeopen] async_fifo_unit_test.dut.
[sst_width] 253
[signals_width] 150
[sst_expanded] 1
[sst_vpaned_height] 357
@200
-TB
@420
async_fifo_unit_test.svut_nb_test
@28
[color] 7
async_fifo_unit_test.dut.wclk
[color] 7
async_fifo_unit_test.dut.wrst_n
[color] 7
async_fifo_unit_test.dut.winc
@22
[color] 7
async_fifo_unit_test.wdata[31:0]
@28
[color] 7
async_fifo_unit_test.dut.wfull
[color] 7
async_fifo_unit_test.dut.awfull
@29
[color] 2
async_fifo_unit_test.dut.rclk
@28
[color] 2
async_fifo_unit_test.dut.rrst_n
[color] 2
async_fifo_unit_test.dut.rinc
@22
[color] 2
async_fifo_unit_test.rdata[31:0]
@28
[color] 2
async_fifo_unit_test.dut.rempty
[color] 2
async_fifo_unit_test.dut.arempty
@200
-DUT
@22
async_fifo_unit_test.dut.raddr[3:0]
async_fifo_unit_test.dut.rdata[31:0]
async_fifo_unit_test.dut.rptr[4:0]
async_fifo_unit_test.dut.rq2_wptr[4:0]
async_fifo_unit_test.dut.wdata[31:0]
async_fifo_unit_test.dut.wptr[4:0]
async_fifo_unit_test.dut.wq2_rptr[4:0]
@200
-FIFO MEM
@22
async_fifo_unit_test.dut.fifomem.waddr[3:0]
async_fifo_unit_test.dut.fifomem.wdata[31:0]
async_fifo_unit_test.dut.fifomem.raddr[3:0]
async_fifo_unit_test.dut.fifomem.rdata[31:0]
@200
-RD PTR EMPTY
@22
async_fifo_unit_test.dut.rptr_empty.raddr[3:0]
async_fifo_unit_test.dut.rptr_empty.rbin[4:0]
async_fifo_unit_test.dut.rptr_empty.rbinnext[4:0]
async_fifo_unit_test.dut.rptr_empty.rgraynext[4:0]
async_fifo_unit_test.dut.rptr_empty.rgraynextm1[4:0]
async_fifo_unit_test.dut.rptr_empty.rptr[4:0]
async_fifo_unit_test.dut.rptr_empty.rq2_wptr[4:0]
[pattern_trace] 1
[pattern_trace] 0
================================================
FILE: syn/cmos.lib
================================================
// test comment
/* test comment */
library(demo) {
cell(BUF) {
area: 6;
pin(A) { direction: input; }
pin(Y) { direction: output;
function: "A"; }
}
cell(NOT) {
area: 3;
pin(A) { direction: input; }
pin(Y) { direction: output;
function: "A'"; }
}
cell(NAND) {
area: 4;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output;
function: "(A*B)'"; }
}
cell(NOR) {
area: 4;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output;
function: "(A+B)'"; }
}
cell(DFF) {
area: 18;
ff(IQ, IQN) { clocked_on: C;
next_state: D; }
pin(C) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
}
cell(DFFSR) {
area: 18;
ff("IQ", "IQN") { clocked_on: C;
next_state: D;
preset: S;
clear: R; }
pin(C) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
pin(S) { direction: input; }
pin(R) { direction: input; }
; // empty statement
}
}
================================================
FILE: syn/fifo.ys
================================================
# read design modules
read -sv2012 ../rtl/async_fifo.v
read -sv2012 ../rtl/fifomem.v
read -sv2012 ../rtl/rptr_empty.v
read -sv2012 ../rtl/sync_r2w.v
read -sv2012 ../rtl/sync_w2r.v
read -sv2012 ../rtl/wptr_full.v
# synthsize the core
synth -top async_fifo
# convert design to (logical) gate-level netlists
# +/adff2dff.v convert async reset to sync reset, used to mapp FFD correctly
techmap +/adff2dff.v; opt
# dffunmap
# map internal register types to the ones from the cell library
dfflibmap -liberty cmos.lib
# use ABC to map remaining logic to cells from the cell library
abc -liberty cmos.lib
# cleanup
clean
# write synthesized design
write_verilog async_fifo_syn.v
================================================
FILE: syn/syn_asic.sh
================================================
#!/usr/bin/env bash
# -e: exit if one command fails
# -o pipefail: causes a pipeline to fail if any command fails
set -e -o pipefail
design="./fifo.ys"
# if [[ ! -f "./vsclib013.lib" ]]; then
# echo "INFO: Download library for synthesis"
# wget http://www.vlsitechnology.org/synopsys/vsclib013.lib
# fi
# Check if a design is specified
if [[ -n $1 ]]; then
echo "INFO: will start $1 synthesis"
design="$1"
fi
echo "INFO: Start synthesis flow"
yosys -V
yosys "$design"
exit 0
================================================
FILE: syn/vsclib013.lib
================================================
library (vsclib013) { /* Post layout timing */
technology (cmos) ;
/* choose one delay_model */
/* delay_model : generic_cmos ; */ /* Prop-Ramp */
delay_model : table_lookup ; /* LUT */
date : "12-Sep-08" ;
revision : 0.10.2 ;
comment : "Copyright (c) 2004-2008 Malta Open Silicon Libraries. Released under the LGPL." ;
time_unit : "1ps" ;
voltage_unit : "1mV" ;
current_unit : "1mA" ;
pulling_resistance_unit : "1kohm" ;
capacitive_load_unit (1.00,ff) ;
leakage_power_unit : "1pW" ;
nom_voltage : 1.2 ;
nom_process : 1.0 ;
nom_temperature : 27.0 ;
operating_conditions (NOM_1.2_27) {
process : 1.0 ;
voltage : 1.2 ;
temperature : 27.0 ;
tree_type : "balanced_tree" ;
}
/* Wireload tables are in fF, so capacitance attribute is 1.0 */
/* Wires are routed over the cells, so the area attribute is 0 */
wire_load ("1K") {
resistance : 0.00175 ;
capacitance : 1.0 ;
area : 0.0 ;
slope : 4.58 ;
fanout_length ( 1, 2.86 ) ;
fanout_length ( 2, 9.15 ) ;
fanout_length ( 3, 14.19 ) ;
fanout_length ( 4, 19.22 ) ;
fanout_length ( 5, 23.61 ) ;
fanout_length ( 6, 28.01 ) ;
fanout_length ( 7, 32.40 ) ;
fanout_length ( 8, 36.79 ) ;
fanout_length ( 9, 41.18 ) ;
}
wire_load ("10K") {
resistance : 0.00175 ;
capacitance : 1.0 ;
area : 0.0 ;
slope : 5.72 ;
fanout_length ( 1, 2.86 ) ;
fanout_length ( 2, 11.44 ) ;
fanout_length ( 3, 19.31 ) ;
fanout_length ( 4, 27.17 ) ;
fanout_length ( 5, 32.03 ) ;
fanout_length ( 6, 36.89 ) ;
fanout_length ( 7, 41.76 ) ;
fanout_length ( 8, 46.62 ) ;
fanout_length ( 9, 51.48 ) ;
}
wire_load ("100K") {
resistance : 0.00175 ;
capacitance : 1.0 ;
area : 0.0 ;
slope : 7.15 ;
fanout_length ( 1, 2.86 ) ;
fanout_length ( 2, 14.30 ) ;
fanout_length ( 3, 25.03 ) ;
fanout_length ( 4, 35.75 ) ;
fanout_length ( 5, 41.47 ) ;
fanout_length ( 6, 47.19 ) ;
fanout_length ( 7, 52.91 ) ;
fanout_length ( 8, 58.63 ) ;
fanout_length ( 9, 64.35 ) ;
}
wire_load ("500K") {
resistance : 0.00175 ;
capacitance : 1.0 ;
area : 0.0 ;
slope : 7.61 ;
fanout_length ( 1, 2.86 ) ;
fanout_length ( 2, 15.22 ) ;
fanout_length ( 3, 27.58 ) ;
fanout_length ( 4, 39.94 ) ;
fanout_length ( 5, 45.65 ) ;
fanout_length ( 6, 51.35 ) ;
fanout_length ( 7, 57.06 ) ;
fanout_length ( 8, 62.76 ) ;
fanout_length ( 9, 68.47 ) ;
}
wire_load ("top") {
resistance : 0.00175 ;
capacitance : 1.0 ;
area : 0.0 ;
slope : 7.61 ;
fanout_length ( 1, 22.82 ) ;
fanout_length ( 2, 28.53 ) ;
fanout_length ( 3, 34.23 ) ;
fanout_length ( 4, 39.94 ) ;
fanout_length ( 5, 45.65 ) ;
fanout_length ( 6, 51.35 ) ;
fanout_length ( 7, 57.06 ) ;
fanout_length ( 8, 62.76 ) ;
fanout_length ( 9, 68.47 ) ;
}
wire_load_selection ("by_gate_count") {
/* numbers are tracks, which are 3X bigger than gates */
wire_load_from_area ( 0, 3000,"1K") ;
wire_load_from_area ( 3000, 30000,"10K") ;
wire_load_from_area ( 30000, 300000,"100K") ;
wire_load_from_area ( 300000, 1500000,"500K") ;
wire_load_from_area ( 1500000,30000000,"top") ;
}
input_threshold_pct_rise : 50.0 ;
input_threshold_pct_fall : 50.0 ;
output_threshold_pct_rise : 50.0 ;
output_threshold_pct_fall : 50.0 ;
slew_lower_threshold_pct_rise : 0.0 ;
slew_upper_threshold_pct_rise : 100.0 ;
slew_lower_threshold_pct_fall : 0.0 ;
slew_upper_threshold_pct_fall : 100.0 ;
slew_derate_from_library : 1.0 ;
default_leakage_power_density : 36 ;
default_cell_leakage_power : 3240 ;
in_place_swap_mode : match_footprint ;
simulation : false ;
library_features (report_delay_calculation) ;
default_input_pin_cap : 5.0 ;
default_output_pin_cap : 0.0 ;
default_inout_pin_cap : 0.0 ;
default_fanout_load : 1.0 ;
default_max_fanout : 30.0 ;
default_max_transition : 1500.0 ;
default_wire_load_mode : enclosed ;
default_wire_load_capacitance : 5.0 ;
default_wire_load_resistance : 0.00175 ;
default_wire_load_area : 0.0 ;
default_wire_load_selection : "by_gate_count" ;
default_operating_conditions : NOM_1.2_27 ;
lu_table_template(x05_48_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 0.4, 1.5, 4.5, 11.2, 23.2, 48.8" ) ; }
power_lut_template(pwr_x05_48_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 0.4, 1.5, 4.5, 11.2, 23.2" ) ; }
lu_table_template(x1_97_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 0.8, 3.0, 9.0, 22.5, 46.5, 97.5" ) ; }
power_lut_template(pwr_x1_97_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 0.8, 3.0, 9.0, 22.5, 46.5" ) ; }
lu_table_template(x2_195_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 1.5, 6.0, 18.0, 45.0, 93.0, 195.0" ) ; }
power_lut_template(pwr_x2_195_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 1.5, 6.0, 18.0, 45.0, 93.0" ) ; }
lu_table_template(x3_292_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 2.2, 9.0, 27.0, 67.5, 139.5, 292.5" ) ; }
power_lut_template(pwr_x3_292_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 2.2, 9.0, 27.0, 67.5, 139.5" ) ; }
lu_table_template(x4_390_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 3.0, 12.0, 36.0, 90.0, 186.0, 390.0" ) ; }
power_lut_template(pwr_x4_390_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 3.0, 12.0, 36.0, 90.0, 186.0" ) ; }
lu_table_template(x5_487_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 3.8, 15.0, 45.0, 112.5, 232.5, 487.5" ) ; }
power_lut_template(pwr_x5_487_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 3.8, 15.0, 45.0, 112.5, 232.5" ) ; }
lu_table_template(x6_585_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 4.5, 18.0, 54.0, 135.0, 279.0, 585.0" ) ; }
power_lut_template(pwr_x6_585_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 4.5, 18.0, 54.0, 135.0, 279.0" ) ; }
lu_table_template(x7_682_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 5.2, 21.0, 63.0, 157.5, 325.5, 682.5" ) ; }
power_lut_template(pwr_x7_682_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 5.2, 21.0, 63.0, 157.5, 325.5" ) ; }
lu_table_template(x8_780_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 6.0, 24.0, 72.0, 180.0, 372.0, 780.0" ) ; }
power_lut_template(pwr_x8_780_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 6.0, 24.0, 72.0, 180.0, 372.0" ) ; }
lu_table_template(x9_877_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 6.8, 27.0, 81.0, 202.5, 418.5, 877.5" ) ; }
power_lut_template(pwr_x9_877_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 6.8, 27.0, 81.0, 202.5, 418.5" ) ; }
lu_table_template(x10_975_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 7.5, 30.0, 90.0, 225.0, 465.0, 975.0" ) ; }
power_lut_template(pwr_x10_975_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 7.5, 30.0, 90.0, 225.0, 465.0" ) ; }
lu_table_template(x11_1072_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 8.2, 33.0, 99.0, 247.5, 511.5, 1072.5" ) ; }
power_lut_template(pwr_x11_1072_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 8.2, 33.0, 99.0, 247.5, 511.5" ) ; }
lu_table_template(x12_1170_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 9.0, 36.0, 108.0, 270.0, 558.0, 1170.0" ) ; }
power_lut_template(pwr_x12_1170_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 9.0, 36.0, 108.0, 270.0, 558.0" ) ; }
lu_table_template(x05_65_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 0.5, 2.0, 6.0, 15.0, 31.0, 65.0" ) ; }
power_lut_template(pwr_x05_65_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 0.5, 2.0, 6.0, 15.0, 31.0" ) ; }
lu_table_template(x1_130_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 1.0, 4.0, 12.0, 30.0, 62.0, 130.0" ) ; }
power_lut_template(pwr_x1_130_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 1.0, 4.0, 12.0, 30.0, 62.0" ) ; }
lu_table_template(x2_260_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 2.0, 8.0, 24.0, 60.0, 124.0, 260.0" ) ; }
power_lut_template(pwr_x2_260_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 2.0, 8.0, 24.0, 60.0, 124.0" ) ; }
lu_table_template(x3_390_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 3.0, 12.0, 36.0, 90.0, 186.0, 390.0" ) ; }
power_lut_template(pwr_x3_390_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 3.0, 12.0, 36.0, 90.0, 186.0" ) ; }
lu_table_template(x4_520_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 4.0, 16.0, 48.0, 120.0, 248.0, 520.0" ) ; }
power_lut_template(pwr_x4_520_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 4.0, 16.0, 48.0, 120.0, 248.0" ) ; }
lu_table_template(x5_650_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 5.0, 20.0, 60.0, 150.0, 310.0, 650.0" ) ; }
power_lut_template(pwr_x5_650_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 5.0, 20.0, 60.0, 150.0, 310.0" ) ; }
lu_table_template(x6_780_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 6.0, 24.0, 72.0, 180.0, 372.0, 780.0" ) ; }
power_lut_template(pwr_x6_780_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 6.0, 24.0, 72.0, 180.0, 372.0" ) ; }
lu_table_template(x7_910_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 7.0, 28.0, 84.0, 210.0, 434.0, 910.0" ) ; }
power_lut_template(pwr_x7_910_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 7.0, 28.0, 84.0, 210.0, 434.0" ) ; }
lu_table_template(x8_1040_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 8.0, 32.0, 96.0, 240.0, 496.0, 1040.0" ) ; }
power_lut_template(pwr_x8_1040_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 8.0, 32.0, 96.0, 240.0, 496.0" ) ; }
lu_table_template(x9_1170_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 9.0, 36.0, 108.0, 270.0, 558.0, 1170.0" ) ; }
power_lut_template(pwr_x9_1170_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 9.0, 36.0, 108.0, 270.0, 558.0" ) ; }
lu_table_template(x10_1300_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 10.0, 40.0, 120.0, 300.0, 620.0, 1300.0" ) ; }
power_lut_template(pwr_x10_1300_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 10.0, 40.0, 120.0, 300.0, 620.0" ) ; }
lu_table_template(x11_1430_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 11.0, 44.0, 132.0, 330.0, 682.0, 1430.0" ) ; }
power_lut_template(pwr_x11_1430_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 11.0, 44.0, 132.0, 330.0, 682.0" ) ; }
lu_table_template(x12_1560_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 12.0, 48.0, 144.0, 360.0, 744.0, 1560.0" ) ; }
power_lut_template(pwr_x12_1560_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 12.0, 48.0, 144.0, 360.0, 744.0" ) ; }
lu_table_template(x05_81_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 0.6, 2.5, 7.5, 18.8, 38.8, 81.2" ) ; }
power_lut_template(pwr_x05_81_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 0.6, 2.5, 7.5, 18.8, 38.8" ) ; }
lu_table_template(x1_162_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 1.2, 5.0, 15.0, 37.5, 77.5, 162.5" ) ; }
power_lut_template(pwr_x1_162_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 1.2, 5.0, 15.0, 37.5, 77.5" ) ; }
lu_table_template(x2_325_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 2.5, 10.0, 30.0, 75.0, 155.0, 325.0" ) ; }
power_lut_template(pwr_x2_325_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 2.5, 10.0, 30.0, 75.0, 155.0" ) ; }
lu_table_template(x3_487_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 3.8, 15.0, 45.0, 112.5, 232.5, 487.5" ) ; }
power_lut_template(pwr_x3_487_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 3.8, 15.0, 45.0, 112.5, 232.5" ) ; }
lu_table_template(x4_650_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 5.0, 20.0, 60.0, 150.0, 310.0, 650.0" ) ; }
power_lut_template(pwr_x4_650_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 5.0, 20.0, 60.0, 150.0, 310.0" ) ; }
lu_table_template(x5_812_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 6.2, 25.0, 75.0, 187.5, 387.5, 812.5" ) ; }
power_lut_template(pwr_x5_812_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 6.2, 25.0, 75.0, 187.5, 387.5" ) ; }
lu_table_template(x6_975_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 7.5, 30.0, 90.0, 225.0, 465.0, 975.0" ) ; }
power_lut_template(pwr_x6_975_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 7.5, 30.0, 90.0, 225.0, 465.0" ) ; }
lu_table_template(x7_1137_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 8.8, 35.0, 105.0, 262.5, 542.5, 1137.5" ) ; }
power_lut_template(pwr_x7_1137_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 8.8, 35.0, 105.0, 262.5, 542.5" ) ; }
lu_table_template(x8_1300_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 10.0, 40.0, 120.0, 300.0, 620.0, 1300.0" ) ; }
power_lut_template(pwr_x8_1300_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 10.0, 40.0, 120.0, 300.0, 620.0" ) ; }
lu_table_template(x9_1462_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 11.2, 45.0, 135.0, 337.5, 697.5, 1462.5" ) ; }
power_lut_template(pwr_x9_1462_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 11.2, 45.0, 135.0, 337.5, 697.5" ) ; }
lu_table_template(x10_1625_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 12.5, 50.0, 150.0, 375.0, 775.0, 1625.0" ) ; }
power_lut_template(pwr_x10_1625_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 12.5, 50.0, 150.0, 375.0, 775.0" ) ; }
lu_table_template(x11_1787_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 13.8, 55.0, 165.0, 412.5, 852.5, 1787.5" ) ; }
power_lut_template(pwr_x11_1787_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 13.8, 55.0, 165.0, 412.5, 852.5" ) ; }
lu_table_template(x12_1950_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 15.0, 60.0, 180.0, 450.0, 930.0, 1950.0" ) ; }
power_lut_template(pwr_x12_1950_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 15.0, 60.0, 180.0, 450.0, 930.0" ) ; }
lu_table_template(x05_97_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 0.8, 3.0, 9.0, 22.5, 46.5, 97.5" ) ; }
power_lut_template(pwr_x05_97_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 0.8, 3.0, 9.0, 22.5, 46.5" ) ; }
lu_table_template(x1_195_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 1.5, 6.0, 18.0, 45.0, 93.0, 195.0" ) ; }
power_lut_template(pwr_x1_195_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 1.5, 6.0, 18.0, 45.0, 93.0" ) ; }
lu_table_template(x2_390_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 3.0, 12.0, 36.0, 90.0, 186.0, 390.0" ) ; }
power_lut_template(pwr_x2_390_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 3.0, 12.0, 36.0, 90.0, 186.0" ) ; }
lu_table_template(x3_585_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 4.5, 18.0, 54.0, 135.0, 279.0, 585.0" ) ; }
power_lut_template(pwr_x3_585_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 4.5, 18.0, 54.0, 135.0, 279.0" ) ; }
lu_table_template(x4_780_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 6.0, 24.0, 72.0, 180.0, 372.0, 780.0" ) ; }
power_lut_template(pwr_x4_780_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 6.0, 24.0, 72.0, 180.0, 372.0" ) ; }
lu_table_template(x5_975_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 7.5, 30.0, 90.0, 225.0, 465.0, 975.0" ) ; }
power_lut_template(pwr_x5_975_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 7.5, 30.0, 90.0, 225.0, 465.0" ) ; }
lu_table_template(x6_1170_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 9.0, 36.0, 108.0, 270.0, 558.0, 1170.0" ) ; }
power_lut_template(pwr_x6_1170_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 9.0, 36.0, 108.0, 270.0, 558.0" ) ; }
lu_table_template(x7_1365_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 10.5, 42.0, 126.0, 315.0, 651.0, 1365.0" ) ; }
power_lut_template(pwr_x7_1365_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 10.5, 42.0, 126.0, 315.0, 651.0" ) ; }
lu_table_template(x8_1560_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 12.0, 48.0, 144.0, 360.0, 744.0, 1560.0" ) ; }
power_lut_template(pwr_x8_1560_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 12.0, 48.0, 144.0, 360.0, 744.0" ) ; }
lu_table_template(x9_1755_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 13.5, 54.0, 162.0, 405.0, 837.0, 1755.0" ) ; }
power_lut_template(pwr_x9_1755_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 13.5, 54.0, 162.0, 405.0, 837.0" ) ; }
lu_table_template(x10_1950_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 15.0, 60.0, 180.0, 450.0, 930.0, 1950.0" ) ; }
power_lut_template(pwr_x10_1950_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 15.0, 60.0, 180.0, 450.0, 930.0" ) ; }
lu_table_template(x11_2145_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 16.5, 66.0, 198.0, 495.0, 1023.0, 2145.0" ) ; }
power_lut_template(pwr_x11_2145_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 16.5, 66.0, 198.0, 495.0, 1023.0" ) ; }
lu_table_template(x12_2340_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 18.0, 72.0, 216.0, 540.0, 1116.0, 2340.0" ) ; }
power_lut_template(pwr_x12_2340_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 18.0, 72.0, 216.0, 540.0, 1116.0" ) ; }
lu_table_template(x05_113_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 0.9, 3.5, 10.5, 26.2, 54.2, 113.8" ) ; }
power_lut_template(pwr_x05_113_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 0.9, 3.5, 10.5, 26.2, 54.2" ) ; }
lu_table_template(x1_227_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 1.8, 7.0, 21.0, 52.5, 108.5, 227.5" ) ; }
power_lut_template(pwr_x1_227_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 1.8, 7.0, 21.0, 52.5, 108.5" ) ; }
lu_table_template(x2_455_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 3.5, 14.0, 42.0, 105.0, 217.0, 455.0" ) ; }
power_lut_template(pwr_x2_455_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 3.5, 14.0, 42.0, 105.0, 217.0" ) ; }
lu_table_template(x3_682_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 5.2, 21.0, 63.0, 157.5, 325.5, 682.5" ) ; }
power_lut_template(pwr_x3_682_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 5.2, 21.0, 63.0, 157.5, 325.5" ) ; }
lu_table_template(x4_910_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 7.0, 28.0, 84.0, 210.0, 434.0, 910.0" ) ; }
power_lut_template(pwr_x4_910_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 7.0, 28.0, 84.0, 210.0, 434.0" ) ; }
lu_table_template(x5_1137_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 8.8, 35.0, 105.0, 262.5, 542.5, 1137.5" ) ; }
power_lut_template(pwr_x5_1137_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 8.8, 35.0, 105.0, 262.5, 542.5" ) ; }
lu_table_template(x6_1365_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 10.5, 42.0, 126.0, 315.0, 651.0, 1365.0" ) ; }
power_lut_template(pwr_x6_1365_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 10.5, 42.0, 126.0, 315.0, 651.0" ) ; }
lu_table_template(x7_1592_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 12.2, 49.0, 147.0, 367.5, 759.5, 1592.5" ) ; }
power_lut_template(pwr_x7_1592_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 12.2, 49.0, 147.0, 367.5, 759.5" ) ; }
lu_table_template(x8_1820_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 14.0, 56.0, 168.0, 420.0, 868.0, 1820.0" ) ; }
power_lut_template(pwr_x8_1820_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 14.0, 56.0, 168.0, 420.0, 868.0" ) ; }
lu_table_template(x9_2047_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 15.8, 63.0, 189.0, 472.5, 976.5, 2047.5" ) ; }
power_lut_template(pwr_x9_2047_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 15.8, 63.0, 189.0, 472.5, 976.5" ) ; }
lu_table_template(x10_2275_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 17.5, 70.0, 210.0, 525.0, 1085.0, 2275.0" ) ; }
power_lut_template(pwr_x10_2275_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 17.5, 70.0, 210.0, 525.0, 1085.0" ) ; }
lu_table_template(x11_2502_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 19.2, 77.0, 231.0, 577.5, 1193.5, 2502.5" ) ; }
power_lut_template(pwr_x11_2502_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 19.2, 77.0, 231.0, 577.5, 1193.5" ) ; }
lu_table_template(x12_2730_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 21.0, 84.0, 252.0, 630.0, 1302.0, 2730.0" ) ; }
power_lut_template(pwr_x12_2730_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 21.0, 84.0, 252.0, 630.0, 1302.0" ) ; }
lu_table_template(x05_130_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 1.0, 4.0, 12.0, 30.0, 62.0, 130.0" ) ; }
power_lut_template(pwr_x05_130_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 1.0, 4.0, 12.0, 30.0, 62.0" ) ; }
lu_table_template(x1_260_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 2.0, 8.0, 24.0, 60.0, 124.0, 260.0" ) ; }
power_lut_template(pwr_x1_260_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 2.0, 8.0, 24.0, 60.0, 124.0" ) ; }
lu_table_template(x2_520_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 4.0, 16.0, 48.0, 120.0, 248.0, 520.0" ) ; }
power_lut_template(pwr_x2_520_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 4.0, 16.0, 48.0, 120.0, 248.0" ) ; }
lu_table_template(x3_780_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 6.0, 24.0, 72.0, 180.0, 372.0, 780.0" ) ; }
power_lut_template(pwr_x3_780_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 6.0, 24.0, 72.0, 180.0, 372.0" ) ; }
lu_table_template(x4_1040_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 8.0, 32.0, 96.0, 240.0, 496.0, 1040.0" ) ; }
power_lut_template(pwr_x4_1040_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 8.0, 32.0, 96.0, 240.0, 496.0" ) ; }
lu_table_template(x5_1300_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 10.0, 40.0, 120.0, 300.0, 620.0, 1300.0" ) ; }
power_lut_template(pwr_x5_1300_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 10.0, 40.0, 120.0, 300.0, 620.0" ) ; }
lu_table_template(x6_1560_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 12.0, 48.0, 144.0, 360.0, 744.0, 1560.0" ) ; }
power_lut_template(pwr_x6_1560_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 12.0, 48.0, 144.0, 360.0, 744.0" ) ; }
lu_table_template(x7_1820_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 14.0, 56.0, 168.0, 420.0, 868.0, 1820.0" ) ; }
power_lut_template(pwr_x7_1820_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 14.0, 56.0, 168.0, 420.0, 868.0" ) ; }
lu_table_template(x8_2080_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 16.0, 64.0, 192.0, 480.0, 992.0, 2080.0" ) ; }
power_lut_template(pwr_x8_2080_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 16.0, 64.0, 192.0, 480.0, 992.0" ) ; }
lu_table_template(x9_2340_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 18.0, 72.0, 216.0, 540.0, 1116.0, 2340.0" ) ; }
power_lut_template(pwr_x9_2340_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 18.0, 72.0, 216.0, 540.0, 1116.0" ) ; }
lu_table_template(x10_2600_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 20.0, 80.0, 240.0, 600.0, 1240.0, 2600.0" ) ; }
power_lut_template(pwr_x10_2600_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 20.0, 80.0, 240.0, 600.0, 1240.0" ) ; }
lu_table_template(x11_2860_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 22.0, 88.0, 264.0, 660.0, 1364.0, 2860.0" ) ; }
power_lut_template(pwr_x11_2860_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 22.0, 88.0, 264.0, 660.0, 1364.0" ) ; }
lu_table_template(x12_3120_6x10) {
variable_1 : input_net_transition ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 24.0, 96.0, 288.0, 720.0, 1488.0, 3120.0" ) ; }
power_lut_template(pwr_x12_3120_5x10) {
variable_1 : input_transition_time ;
variable_2 : total_output_net_capacitance ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ;
index_2( " 24.0, 96.0, 288.0, 720.0, 1488.0" ) ; }
power_lut_template(pwr_intran_x10) {
variable_1 : input_transition_time ;
index_1( " 20.0, 60.0, 90.0, 130.0, 200.0, 300.0, 450.0, 670.0, 1000.0, 1500.0" ) ; }
lu_table_template(suh_4x4) {
variable_1 : related_pin_transition ;
variable_2 : constrained_pin_transition ;
index_1(" 20.0, 200.0, 670.0, 1500.0" ) ;
index_2(" 20.0, 200.0, 670.0, 1500.0" ) ; }
cell(an2v0x05) { /* 2008-01-06:07h20 */
area : 5 ; /* tracks */
cell_leakage_power : 543 ; /* an2v0x05 */
cell_footprint : an2 ;
pin(a) { /* an2v0x05 FO4 effort 1.81 */
direction : input ;
capacitance : 2.62 ;
rise_capacitance : 2.71 ;
fall_capacitance : 2.53 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin a of an2v0x05 */
}
pin(b) { /* an2v0x05 FO4 effort 1.71 */
direction : input ;
capacitance : 2.49 ;
rise_capacitance : 2.53 ;
fall_capacitance : 2.45 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin b of an2v0x05 */
}
pin(z) {
direction : output ;
min_transition : 20 ;
min_capacitance : 1 ;
max_capacitance : 107 ;
max_fanout : 2 ;
function : "(a*b)" ;
internal_power(a_z_p) { /* an2v0x05 12.47 nW/MHz */
related_pin : "a" ;
power(pwr_x05_113_5x10) {
values( " 6.19, 6.26, 6.34, 6.37, 6.38", \
" 6.07, 6.13, 6.21, 6.26, 6.27", \
" 6.07, 6.12, 6.20, 6.25, 6.26", \
" 6.12, 6.16, 6.23, 6.29, 6.31", \
" 6.32, 6.33, 6.39, 6.45, 6.47", \
" 6.71, 6.70, 6.74, 6.79, 6.81", \
" 7.44, 7.39, 7.39, 7.43, 7.46", \
" 8.66, 8.57, 8.52, 8.53, 8.55", \
" 10.66, 10.51, 10.40, 10.37, 10.37", \
" 13.84, 13.61, 13.42, 13.33, 13.30" ); }}
internal_power(b_z_p) { /* an2v0x05 11.01 nW/MHz */
related_pin : "b" ;
power(pwr_x05_113_5x10) {
values( " 5.43, 5.50, 5.58, 5.62, 5.62", \
" 5.30, 5.37, 5.45, 5.50, 5.51", \
" 5.31, 5.37, 5.45, 5.50, 5.52", \
" 5.39, 5.43, 5.50, 5.56, 5.58", \
" 5.62, 5.64, 5.70, 5.75, 5.78", \
" 6.05, 6.04, 6.07, 6.12, 6.15", \
" 6.80, 6.76, 6.76, 6.79, 6.82", \
" 8.02, 7.94, 7.89, 7.90, 7.92", \
" 9.99, 9.85, 9.75, 9.71, 9.72", \
" 13.12, 12.89, 12.71, 12.62, 12.59" ); }}
timing() { /* ring osc delay an2v0x05, path a to z 78.5 */
related_pin : "a" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 65.3 ; */
/* intrinsic_fall : 94.6 ; */
/* rise_resistance : 4.95 ; */
/* fall_resistance : 3.86 ; */
cell_rise(x05_113_6x10) { /* 50.0% of input to 50.0% of output */
values( " 56.6, 71.5, 107.1, 185.1, 323.1, 616.2", \
" 61.1, 75.9, 111.6, 189.6, 327.6, 620.7", \
" 64.0, 78.8, 114.5, 192.5, 330.5, 623.6", \
" 67.1, 82.0, 117.7, 195.7, 333.8, 626.9", \
" 70.4, 85.7, 121.8, 199.8, 337.9, 631.0", \
" 72.9, 88.5, 124.7, 203.0, 341.1, 634.2", \
" 73.6, 89.8, 126.4, 204.8, 343.0, 636.1", \
" 70.9, 87.9, 125.4, 204.0, 342.5, 635.5", \
" 62.2, 80.4, 119.5, 199.2, 337.8, 631.2", \
" 43.3, 63.0, 104.3, 186.3, 326.7, 620.2" ); }
rise_transition(x05_113_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 49.6, 82.9, 174.7, 386.0, 764.4, 1570.0", \
" 49.8, 83.0, 174.8, 386.0, 764.4, 1570.0", \
" 50.4, 83.4, 174.9, 386.0, 764.5, 1570.0", \
" 52.1, 84.8, 175.6, 386.2, 764.5, 1570.0", \
" 54.6, 87.2, 177.2, 386.9, 764.6, 1570.0", \
" 57.9, 90.0, 179.3, 388.0, 765.2, 1570.0", \
" 62.9, 94.6, 182.5, 389.7, 766.0, 1570.5", \
" 69.9, 101.6, 188.0, 393.1, 767.7, 1571.2", \
" 79.3, 111.5, 197.2, 399.6, 771.8, 1573.0", \
" 92.0, 125.0, 210.8, 411.8, 780.7, 1578.5" ); }
cell_fall(x05_113_6x10) { /* 50.0% of input to 50.0% of output */
values( " 70.1, 84.0, 113.7, 174.5, 280.9, 506.4", \
" 77.5, 91.5, 121.2, 182.0, 288.4, 513.9", \
" 83.9, 97.8, 127.5, 188.3, 294.7, 520.3", \
" 92.6, 106.5, 136.2, 197.1, 303.5, 529.1", \
" 107.3, 121.4, 151.3, 212.1, 318.6, 544.1", \
" 125.1, 140.1, 170.8, 231.7, 338.1, 563.7", \
" 148.1, 164.2, 195.9, 257.5, 363.9, 589.4", \
" 178.2, 195.4, 228.5, 290.7, 397.4, 622.9", \
" 219.2, 237.8, 272.8, 335.8, 442.8, 668.5", \
" 275.8, 296.2, 334.1, 399.1, 506.4, 732.5" ); }
fall_transition(x05_113_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 43.3, 66.2, 126.7, 267.8, 524.3, 1074.0", \
" 43.3, 66.3, 126.7, 267.8, 524.3, 1074.0", \
" 43.5, 66.4, 126.8, 267.8, 524.3, 1074.0", \
" 44.1, 66.9, 127.0, 267.9, 524.3, 1074.0", \
" 47.2, 69.3, 128.2, 268.3, 524.4, 1074.0", \
" 52.0, 74.1, 131.7, 269.8, 524.8, 1074.0", \
" 57.8, 80.0, 136.8, 272.9, 526.3, 1074.3", \
" 64.7, 87.3, 143.0, 276.9, 528.4, 1075.3", \
" 73.7, 97.0, 151.8, 282.7, 531.6, 1076.7", \
" 86.0, 110.4, 165.0, 292.4, 537.5, 1079.4" ); }}
timing() { /* ring osc delay an2v0x05, path b to z 72.8 */
related_pin : "b" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 65.2 ; */
/* intrinsic_fall : 84.9 ; */
/* rise_resistance : 4.96 ; */
/* fall_resistance : 3.85 ; */
cell_rise(x05_113_6x10) { /* 50.0% of input to 50.0% of output */
values( " 52.9, 67.8, 103.4, 181.4, 319.4, 612.5", \
" 58.8, 73.6, 109.3, 187.3, 325.4, 618.5", \
" 63.0, 77.7, 113.4, 191.4, 329.5, 622.7", \
" 67.0, 82.0, 117.6, 195.6, 333.8, 626.9", \
" 71.2, 86.4, 122.6, 200.6, 338.7, 631.9", \
" 74.9, 90.2, 126.4, 204.9, 342.9, 636.1", \
" 77.3, 93.1, 129.4, 208.0, 346.3, 639.4", \
" 77.1, 93.6, 130.5, 209.0, 347.8, 640.9", \
" 72.0, 89.7, 127.8, 207.1, 345.8, 639.4", \
" 58.4, 77.7, 117.8, 198.8, 338.8, 632.6" ); }
rise_transition(x05_113_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 49.7, 82.9, 174.7, 386.0, 764.4, 1570.0", \
" 49.9, 83.1, 174.8, 386.0, 764.4, 1570.0", \
" 50.8, 83.7, 175.0, 386.0, 764.5, 1570.0", \
" 52.7, 85.3, 175.9, 386.2, 764.5, 1570.0", \
" 55.1, 87.9, 177.7, 387.2, 764.6, 1570.0", \
" 58.3, 90.4, 179.8, 388.5, 765.6, 1570.0", \
" 63.3, 94.6, 182.7, 390.2, 766.6, 1570.9", \
" 70.3, 101.2, 187.4, 393.3, 768.3, 1571.9", \
" 80.1, 111.0, 196.0, 398.9, 772.0, 1573.7", \
" 93.4, 124.9, 209.3, 409.8, 779.8, 1578.7" ); }
cell_fall(x05_113_6x10) { /* 50.0% of input to 50.0% of output */
values( " 61.7, 75.1, 104.2, 164.6, 270.9, 496.3", \
" 69.0, 82.3, 111.5, 172.0, 278.2, 503.7", \
" 75.3, 88.6, 117.8, 178.3, 284.6, 510.0", \
" 83.7, 97.1, 126.3, 186.8, 293.1, 518.6", \
" 96.9, 110.8, 140.3, 200.9, 307.1, 532.6", \
" 112.6, 127.2, 157.8, 218.6, 324.8, 550.2", \
" 133.1, 148.6, 180.1, 241.7, 347.9, 573.3", \
" 160.0, 176.6, 209.4, 271.5, 378.3, 603.5", \
" 196.2, 214.2, 249.2, 312.5, 419.3, 645.0", \
" 245.7, 265.5, 303.7, 369.7, 477.3, 703.3" ); }
fall_transition(x05_113_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 39.7, 63.0, 124.4, 266.4, 523.4, 1073.4", \
" 40.0, 63.2, 124.5, 266.4, 523.4, 1073.4", \
" 40.2, 63.4, 124.6, 266.4, 523.5, 1073.4", \
" 41.3, 64.2, 125.0, 266.6, 523.5, 1073.4", \
" 45.2, 67.4, 126.9, 267.2, 523.6, 1073.4", \
" 49.6, 72.1, 130.5, 269.2, 524.3, 1073.4", \
" 54.8, 77.5, 135.4, 272.2, 525.9, 1073.9", \
" 61.9, 84.7, 141.4, 276.4, 528.1, 1075.0", \
" 71.5, 94.9, 151.0, 282.9, 531.9, 1076.5", \
" 84.5, 109.2, 165.7, 294.6, 539.5, 1080.1" ); }}
}
}
cell(an2v0x1) { /* 2008-01-06:07h20 */
area : 5 ; /* tracks */
cell_leakage_power : 739 ; /* an2v0x1 */
cell_footprint : an2 ;
pin(a) { /* an2v0x1 FO4 effort 1.71 */
direction : input ;
capacitance : 3.19 ;
rise_capacitance : 3.30 ;
fall_capacitance : 3.07 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin a of an2v0x1 */
}
pin(b) { /* an2v0x1 FO4 effort 1.61 */
direction : input ;
capacitance : 3.00 ;
rise_capacitance : 3.04 ;
fall_capacitance : 2.96 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin b of an2v0x1 */
}
pin(z) {
direction : output ;
min_transition : 20 ;
min_capacitance : 2 ;
max_capacitance : 161 ;
max_fanout : 4 ;
function : "(a*b)" ;
internal_power(a_z_p) { /* an2v0x1 17.03 nW/MHz */
related_pin : "a" ;
power(pwr_x1_195_5x10) {
values( " 8.43, 8.55, 8.68, 8.74, 8.74", \
" 8.27, 8.37, 8.51, 8.58, 8.59", \
" 8.25, 8.34, 8.48, 8.56, 8.57", \
" 8.32, 8.39, 8.51, 8.60, 8.62", \
" 8.57, 8.60, 8.70, 8.79, 8.82", \
" 9.08, 9.05, 9.12, 9.20, 9.24", \
" 10.01, 9.93, 9.94, 10.00, 10.04", \
" 11.58, 11.42, 11.35, 11.38, 11.41", \
" 14.16, 13.89, 13.72, 13.69, 13.70", \
" 18.27, 17.86, 17.56, 17.42, 17.39" ); }}
internal_power(b_z_p) { /* an2v0x1 15.21 nW/MHz */
related_pin : "b" ;
power(pwr_x1_195_5x10) {
values( " 7.44, 7.57, 7.70, 7.76, 7.76", \
" 7.30, 7.41, 7.55, 7.62, 7.63", \
" 7.31, 7.40, 7.54, 7.62, 7.64", \
" 7.41, 7.48, 7.60, 7.69, 7.72", \
" 7.71, 7.74, 7.84, 7.93, 7.96", \
" 8.26, 8.24, 8.30, 8.38, 8.43", \
" 9.23, 9.14, 9.15, 9.21, 9.26", \
" 10.80, 10.64, 10.57, 10.60, 10.63", \
" 13.34, 13.07, 12.91, 12.87, 12.88", \
" 17.38, 16.96, 16.66, 16.52, 16.49" ); }}
timing() { /* ring osc delay an2v0x1, path a to z 76.3 */
related_pin : "a" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 68.3 ; */
/* intrinsic_fall : 95.5 ; */
/* rise_resistance : 3.30 ; */
/* fall_resistance : 2.57 ; */
cell_rise(x1_195_6x10) { /* 50.0% of input to 50.0% of output */
values( " 59.6, 76.8, 117.5, 206.6, 364.4, 699.3", \
" 64.0, 81.2, 122.0, 211.1, 368.8, 703.8", \
" 67.0, 84.1, 124.8, 214.0, 371.8, 706.8", \
" 70.3, 87.5, 128.3, 217.4, 375.2, 710.2", \
" 74.0, 91.6, 132.7, 221.8, 379.6, 714.6", \
" 77.1, 95.0, 136.3, 225.7, 383.5, 718.5", \
" 78.7, 97.2, 138.8, 228.4, 386.2, 721.1", \
" 77.4, 96.7, 139.2, 228.8, 386.9, 721.8", \
" 70.7, 91.3, 135.3, 225.9, 384.1, 719.1", \
" 54.6, 76.8, 123.1, 216.0, 375.5, 710.9" ); }
rise_transition(x1_195_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 51.1, 89.1, 194.1, 435.6, 868.2, 1788.8", \
" 51.2, 89.2, 194.1, 435.6, 868.2, 1788.8", \
" 51.8, 89.5, 194.2, 435.6, 868.2, 1788.8", \
" 53.5, 90.8, 194.7, 435.7, 868.2, 1788.8", \
" 56.0, 93.3, 196.3, 436.3, 868.3, 1788.8", \
" 59.4, 96.2, 198.4, 437.4, 868.8, 1788.8", \
" 64.5, 100.8, 201.7, 439.0, 869.6, 1789.3", \
" 71.6, 107.8, 206.9, 442.2, 871.0, 1789.9", \
" 81.4, 117.9, 216.0, 448.3, 874.7, 1791.4", \
" 94.5, 131.9, 230.0, 460.1, 883.1, 1796.2" ); }
cell_fall(x1_195_6x10) { /* 50.0% of input to 50.0% of output */
values( " 71.1, 87.0, 120.5, 189.7, 311.3, 569.0", \
" 78.6, 94.4, 128.0, 197.2, 318.7, 576.5", \
" 84.8, 100.7, 134.3, 203.5, 325.1, 582.8", \
" 93.5, 109.3, 142.9, 212.2, 333.8, 591.6", \
" 108.2, 124.2, 157.9, 227.2, 348.8, 606.5", \
" 125.9, 143.0, 177.3, 246.7, 368.2, 626.0", \
" 148.8, 166.9, 202.4, 272.3, 393.8, 651.5", \
" 178.5, 197.9, 234.8, 305.1, 426.9, 684.5", \
" 218.7, 239.7, 278.5, 349.6, 471.6, 729.3", \
" 274.1, 297.0, 338.9, 411.7, 533.9, 792.1" ); }
fall_transition(x1_195_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 44.0, 70.1, 139.5, 301.4, 595.2, 1223.7", \
" 44.0, 70.3, 139.6, 301.4, 595.2, 1223.7", \
" 44.2, 70.4, 139.6, 301.5, 595.2, 1223.7", \
" 44.7, 70.8, 139.8, 301.5, 595.2, 1223.7", \
" 47.8, 73.1, 140.9, 301.8, 595.3, 1223.7", \
" 53.1, 78.2, 144.2, 303.2, 595.6, 1223.8", \
" 59.2, 84.4, 149.4, 306.0, 596.9, 1223.9", \
" 66.5, 92.0, 155.7, 310.0, 598.8, 1224.9", \
" 76.1, 102.3, 164.7, 315.6, 601.8, 1226.1", \
" 89.1, 116.5, 178.2, 325.0, 607.3, 1228.5" ); }}
timing() { /* ring osc delay an2v0x1, path b to z 70.3 */
related_pin : "b" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 68.0 ; */
/* intrinsic_fall : 85.9 ; */
/* rise_resistance : 3.30 ; */
/* fall_resistance : 2.56 ; */
cell_rise(x1_195_6x10) { /* 50.0% of input to 50.0% of output */
values( " 55.2, 72.3, 113.1, 202.2, 359.9, 694.9", \
" 61.2, 78.3, 119.0, 208.2, 366.0, 701.0", \
" 65.5, 82.6, 123.3, 212.5, 370.3, 705.3", \
" 70.0, 87.2, 127.9, 217.0, 374.9, 709.9", \
" 75.0, 92.4, 133.5, 222.6, 380.5, 715.5", \
" 79.5, 97.1, 138.3, 227.7, 385.5, 720.5", \
" 83.0, 101.1, 142.3, 232.1, 389.8, 724.8", \
" 84.4, 103.3, 145.1, 234.5, 392.8, 727.6", \
" 81.6, 101.7, 144.7, 234.7, 392.9, 728.1", \
" 71.3, 93.0, 138.0, 229.7, 388.8, 724.4" ); }
rise_transition(x1_195_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 51.1, 89.1, 194.1, 435.6, 868.2, 1788.8", \
" 51.3, 89.3, 194.1, 435.6, 868.2, 1788.8", \
" 52.0, 89.7, 194.3, 435.6, 868.2, 1788.8", \
" 54.0, 91.2, 194.9, 435.8, 868.2, 1788.8", \
" 56.6, 93.8, 196.7, 436.5, 868.3, 1788.8", \
" 60.0, 96.6, 198.8, 437.7, 869.1, 1788.8", \
" 65.2, 100.9, 201.9, 439.3, 870.0, 1789.5", \
" 72.6, 107.7, 206.4, 442.2, 871.4, 1790.3", \
" 82.8, 117.9, 214.9, 447.6, 874.7, 1791.8", \
" 96.9, 132.5, 228.6, 458.1, 882.1, 1796.1" ); }
cell_fall(x1_195_6x10) { /* 50.0% of input to 50.0% of output */
values( " 62.5, 77.8, 110.8, 179.8, 301.1, 558.8", \
" 70.0, 85.2, 118.2, 187.2, 308.6, 566.2", \
" 76.2, 91.4, 124.5, 193.5, 314.9, 572.6", \
" 84.6, 99.9, 133.0, 202.0, 323.5, 581.1", \
" 97.9, 113.7, 147.0, 216.0, 337.5, 595.1", \
" 113.7, 130.4, 164.6, 233.7, 355.1, 612.8", \
" 134.3, 151.8, 187.1, 256.9, 378.1, 635.7", \
" 160.9, 179.7, 216.3, 286.5, 408.1, 665.6", \
" 196.6, 216.9, 255.7, 327.0, 448.8, 706.3", \
" 245.0, 267.4, 309.6, 383.3, 505.6, 763.6" ); }
fall_transition(x1_195_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 40.7, 67.2, 137.5, 300.3, 594.5, 1223.2", \
" 40.8, 67.3, 137.6, 300.3, 594.5, 1223.2", \
" 41.1, 67.6, 137.7, 300.3, 594.5, 1223.2", \
" 42.2, 68.3, 138.0, 300.4, 594.5, 1223.2", \
" 46.1, 71.4, 139.6, 300.9, 594.6, 1223.2", \
" 50.7, 76.3, 143.1, 302.6, 595.0, 1223.2", \
" 56.5, 82.0, 148.0, 305.4, 596.4, 1223.4", \
" 64.0, 89.7, 154.3, 309.4, 598.3, 1224.4", \
" 74.2, 100.6, 164.1, 315.7, 601.8, 1225.7", \
" 88.3, 115.8, 179.3, 327.1, 608.9, 1228.7" ); }}
}
}
cell(an2v0x2) { /* 2008-01-06:07h20 */
area : 5 ; /* tracks */
cell_leakage_power : 1074 ; /* an2v0x2 */
cell_footprint : an2 ;
pin(a) { /* an2v0x2 FO4 effort 1.61 */
direction : input ;
capacitance : 4.08 ;
rise_capacitance : 4.20 ;
fall_capacitance : 3.96 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin a of an2v0x2 */
}
pin(b) { /* an2v0x2 FO4 effort 1.53 */
direction : input ;
capacitance : 3.88 ;
rise_capacitance : 3.91 ;
fall_capacitance : 3.85 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin b of an2v0x2 */
}
pin(z) {
direction : output ;
min_transition : 20 ;
min_capacitance : 2 ;
max_capacitance : 252 ;
max_fanout : 6 ;
function : "(a*b)" ;
internal_power(a_z_p) { /* an2v0x2 23.39 nW/MHz */
related_pin : "a" ;
power(pwr_x2_260_5x10) {
values( " 11.58, 11.73, 11.92, 12.02, 12.04", \
" 11.37, 11.50, 11.69, 11.81, 11.84", \
" 11.36, 11.46, 11.65, 11.78, 11.82", \
" 11.46, 11.53, 11.70, 11.83, 11.88", \
" 11.82, 11.82, 11.94, 12.07, 12.13", \
" 12.52, 12.45, 12.50, 12.62, 12.68", \
" 13.81, 13.64, 13.60, 13.67, 13.74", \
" 15.97, 15.67, 15.51, 15.51, 15.56", \
" 19.51, 19.04, 18.72, 18.61, 18.60", \
" 25.15, 24.46, 23.91, 23.62, 23.53" ); }}
internal_power(b_z_p) { /* an2v0x2 21.29 nW/MHz */
related_pin : "b" ;
power(pwr_x2_260_5x10) {
values( " 10.44, 10.60, 10.79, 10.89, 10.91", \
" 10.26, 10.39, 10.59, 10.71, 10.74", \
" 10.27, 10.38, 10.57, 10.70, 10.74", \
" 10.42, 10.49, 10.65, 10.78, 10.84", \
" 10.84, 10.83, 10.95, 11.08, 11.14", \
" 11.59, 11.51, 11.56, 11.67, 11.73", \
" 12.90, 12.72, 12.68, 12.75, 12.81", \
" 15.05, 14.74, 14.58, 14.57, 14.61", \
" 18.51, 18.03, 17.70, 17.58, 17.57", \
" 24.03, 23.30, 22.74, 22.45, 22.35" ); }}
timing() { /* ring osc delay an2v0x2, path a to z 73.2 */
related_pin : "a" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 72.9 ; */
/* intrinsic_fall : 89.7 ; */
/* rise_resistance : 2.13 ; */
/* fall_resistance : 1.66 ; */
cell_rise(x2_260_6x10) { /* 50.0% of input to 50.0% of output */
values( " 62.5, 78.1, 113.7, 190.3, 325.6, 612.7", \
" 66.9, 82.4, 118.0, 194.6, 329.9, 617.1", \
" 69.9, 85.3, 121.0, 197.6, 332.9, 620.1", \
" 73.6, 89.0, 124.7, 201.3, 336.6, 623.8", \
" 78.1, 93.9, 129.9, 206.5, 341.8, 629.0", \
" 82.3, 98.5, 134.8, 211.6, 346.9, 634.1", \
" 85.9, 102.7, 139.3, 216.3, 351.7, 638.8", \
" 87.7, 105.2, 142.8, 219.9, 355.6, 642.6", \
" 85.7, 104.2, 143.5, 221.8, 357.4, 644.7", \
" 76.7, 96.7, 138.1, 218.8, 356.1, 643.6" ); }
rise_transition(x2_260_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 50.1, 82.5, 171.4, 377.2, 747.3, 1536.2", \
" 50.1, 82.6, 171.4, 377.2, 747.3, 1536.2", \
" 50.4, 82.8, 171.5, 377.2, 747.3, 1536.2", \
" 52.0, 84.0, 172.1, 377.3, 747.3, 1536.2", \
" 54.7, 86.6, 173.8, 378.1, 747.4, 1536.2", \
" 58.0, 89.8, 176.3, 379.4, 748.1, 1536.2", \
" 62.9, 94.4, 179.8, 381.5, 749.1, 1536.8", \
" 69.9, 101.5, 185.5, 385.1, 750.9, 1537.5", \
" 79.5, 111.6, 195.1, 391.9, 755.2, 1539.4", \
" 92.7, 125.6, 209.5, 404.7, 764.5, 1544.8" ); }
cell_fall(x2_260_6x10) { /* 50.0% of input to 50.0% of output */
values( " 65.1, 79.0, 108.2, 167.8, 272.0, 492.9", \
" 72.8, 86.6, 115.8, 175.4, 279.6, 500.6", \
" 79.0, 92.9, 122.1, 181.7, 285.9, 506.9", \
" 87.6, 101.4, 130.6, 190.2, 294.5, 515.5", \
" 101.4, 115.6, 145.0, 204.6, 308.9, 529.9", \
" 117.8, 132.9, 163.2, 222.9, 327.2, 548.1", \
" 138.7, 154.9, 186.3, 246.7, 350.8, 571.7", \
" 165.6, 182.9, 215.8, 276.7, 381.2, 602.0", \
" 201.4, 220.2, 255.2, 317.1, 421.7, 642.7", \
" 250.1, 270.6, 308.8, 372.8, 477.8, 699.1" ); }
fall_transition(x2_260_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 40.1, 62.7, 122.1, 260.5, 511.9, 1050.4", \
" 40.2, 62.8, 122.2, 260.5, 511.9, 1050.4", \
" 40.3, 63.0, 122.3, 260.5, 511.9, 1050.4", \
" 41.2, 63.6, 122.5, 260.6, 511.9, 1050.4", \
" 44.8, 66.5, 124.1, 261.1, 512.1, 1050.4", \
" 49.9, 71.7, 127.9, 263.0, 512.6, 1050.5", \
" 56.1, 78.1, 133.4, 266.2, 514.2, 1050.9", \
" 63.7, 86.1, 140.2, 270.6, 516.4, 1051.9", \
" 73.9, 96.9, 150.1, 277.1, 520.1, 1053.4", \
" 87.6, 111.6, 164.8, 288.2, 526.8, 1056.5" ); }}
timing() { /* ring osc delay an2v0x2, path b to z 68.2 */
related_pin : "b" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 73.3 ; */
/* intrinsic_fall : 82.1 ; */
/* rise_resistance : 2.13 ; */
/* fall_resistance : 1.65 ; */
cell_rise(x2_260_6x10) { /* 50.0% of input to 50.0% of output */
values( " 58.3, 73.8, 109.4, 186.0, 321.3, 608.4", \
" 64.2, 79.7, 115.3, 191.9, 327.2, 614.4", \
" 68.9, 84.2, 119.8, 196.4, 331.8, 619.0", \
" 74.2, 89.5, 125.1, 201.7, 337.0, 624.2", \
" 80.4, 96.2, 132.0, 208.6, 343.9, 631.1", \
" 86.5, 102.4, 138.6, 215.4, 350.6, 637.8", \
" 92.5, 108.8, 145.1, 222.1, 357.4, 644.5", \
" 97.4, 114.4, 151.3, 228.1, 363.9, 650.9", \
" 99.8, 118.0, 156.1, 233.6, 369.2, 656.6", \
" 97.3, 116.9, 157.2, 236.4, 373.0, 660.6" ); }
rise_transition(x2_260_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 50.1, 82.5, 171.4, 377.2, 747.3, 1536.2", \
" 50.2, 82.7, 171.4, 377.2, 747.3, 1536.2", \
" 50.6, 82.9, 171.6, 377.2, 747.3, 1536.2", \
" 52.4, 84.3, 172.2, 377.4, 747.3, 1536.2", \
" 55.5, 87.2, 174.2, 378.3, 747.5, 1536.2", \
" 58.8, 90.3, 176.7, 379.7, 748.3, 1536.2", \
" 64.0, 94.9, 180.1, 381.7, 749.4, 1537.0", \
" 71.4, 101.9, 185.2, 385.0, 751.1, 1537.9", \
" 81.7, 112.3, 194.3, 390.9, 754.8, 1539.6", \
" 95.9, 127.2, 208.6, 402.5, 762.9, 1544.3" ); }
cell_fall(x2_260_6x10) { /* 50.0% of input to 50.0% of output */
values( " 58.5, 71.9, 100.7, 160.0, 264.0, 484.9", \
" 66.1, 79.4, 108.2, 167.6, 271.7, 492.5", \
" 72.3, 85.6, 114.4, 173.8, 277.9, 498.8", \
" 80.5, 93.9, 122.7, 182.1, 286.2, 507.1", \
" 93.0, 107.0, 136.1, 195.5, 299.7, 520.6", \
" 107.7, 122.5, 152.6, 212.2, 316.3, 537.1", \
" 126.4, 142.2, 173.3, 233.6, 337.7, 558.4", \
" 150.3, 167.2, 199.8, 260.7, 365.1, 585.7", \
" 181.6, 200.0, 234.9, 297.1, 401.6, 622.5", \
" 223.2, 243.4, 281.8, 346.8, 452.1, 673.2" ); }
fall_transition(x2_260_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 37.4, 60.3, 120.4, 259.5, 511.3, 1050.0", \
" 37.6, 60.5, 120.5, 259.5, 511.3, 1050.0", \
" 37.9, 60.7, 120.6, 259.5, 511.3, 1050.0", \
" 39.3, 61.6, 121.0, 259.7, 511.3, 1050.0", \
" 43.4, 65.2, 123.1, 260.4, 511.5, 1050.0", \
" 48.2, 70.1, 127.0, 262.5, 512.2, 1050.1", \
" 54.2, 76.2, 132.2, 265.7, 513.8, 1050.6", \
" 62.1, 84.4, 139.2, 270.3, 516.2, 1051.6", \
" 72.8, 95.9, 150.0, 277.6, 520.4, 1053.2", \
" 87.5, 111.6, 166.2, 290.6, 528.8, 1057.2" ); }}
}
}
cell(an2v0x3) { /* 2008-01-06:07h20 */
area : 7 ; /* tracks */
cell_leakage_power : 1351 ; /* an2v0x3 */
cell_footprint : an2 ;
pin(a) { /* an2v0x3 FO4 effort 1.55 */
direction : input ;
capacitance : 4.58 ;
rise_capacitance : 4.75 ;
fall_capacitance : 4.40 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin a of an2v0x3 */
}
pin(b) { /* an2v0x3 FO4 effort 1.47 */
direction : input ;
capacitance : 4.42 ;
rise_capacitance : 4.48 ;
fall_capacitance : 4.35 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin b of an2v0x3 */
}
pin(z) {
direction : output ;
min_transition : 20 ;
min_capacitance : 3 ;
max_capacitance : 361 ;
max_fanout : 8 ;
function : "(a*b)" ;
internal_power(a_z_p) { /* an2v0x3 29.19 nW/MHz */
related_pin : "a" ;
power(pwr_x3_390_5x10) {
values( " 14.44, 14.58, 14.84, 14.97, 15.00", \
" 14.22, 14.34, 14.59, 14.75, 14.79", \
" 14.22, 14.31, 14.55, 14.71, 14.76", \
" 14.35, 14.38, 14.60, 14.77, 14.83", \
" 14.80, 14.73, 14.87, 15.04, 15.11", \
" 15.68, 15.48, 15.52, 15.66, 15.73", \
" 17.27, 16.89, 16.78, 16.86, 16.92", \
" 19.89, 19.29, 18.99, 18.96, 18.99", \
" 24.15, 23.27, 22.72, 22.51, 22.48", \
" 30.92, 29.69, 28.78, 28.32, 28.16" ); }}
internal_power(b_z_p) { /* an2v0x3 26.45 nW/MHz */
related_pin : "b" ;
power(pwr_x3_390_5x10) {
values( " 12.97, 13.16, 13.42, 13.55, 13.58", \
" 12.76, 12.91, 13.17, 13.33, 13.37", \
" 12.79, 12.90, 13.14, 13.31, 13.36", \
" 12.98, 13.02, 13.22, 13.40, 13.47", \
" 13.50, 13.43, 13.56, 13.73, 13.81", \
" 14.45, 14.25, 14.27, 14.40, 14.48", \
" 16.08, 15.70, 15.58, 15.65, 15.71", \
" 18.71, 18.11, 17.80, 17.75, 17.78", \
" 22.94, 22.03, 21.47, 21.25, 21.21", \
" 29.64, 28.34, 27.40, 26.94, 26.77" ); }}
timing() { /* ring osc delay an2v0x3, path a to z 71.9 */
related_pin : "a" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 69.4 ; */
/* intrinsic_fall : 98.1 ; */
/* rise_resistance : 1.49 ; */
/* fall_resistance : 1.17 ; */
cell_rise(x3_390_6x10) { /* 50.0% of input to 50.0% of output */
values( " 58.8, 75.2, 112.6, 192.9, 334.9, 636.3", \
" 63.3, 79.7, 117.0, 197.4, 339.4, 640.9", \
" 66.4, 82.7, 120.0, 200.4, 342.4, 643.9", \
" 70.0, 86.4, 123.7, 204.0, 346.1, 647.6", \
" 74.2, 91.0, 128.6, 208.9, 351.0, 652.5", \
" 77.8, 95.0, 133.0, 213.5, 355.5, 657.0", \
" 80.2, 98.0, 136.4, 217.0, 359.0, 660.5", \
" 79.8, 98.4, 137.7, 218.5, 360.7, 662.0", \
" 74.1, 93.9, 134.9, 216.7, 358.9, 660.4", \
" 59.3, 80.6, 123.8, 207.8, 351.5, 653.2" ); }
rise_transition(x3_390_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 46.2, 80.4, 173.8, 390.1, 778.9, 1607.3", \
" 46.3, 80.4, 173.8, 390.1, 778.9, 1607.3", \
" 46.7, 80.7, 173.9, 390.1, 778.9, 1607.3", \
" 48.2, 81.9, 174.5, 390.3, 778.9, 1607.3", \
" 50.8, 84.5, 176.2, 391.0, 779.0, 1607.3", \
" 54.2, 87.7, 178.6, 392.2, 779.6, 1607.4", \
" 59.3, 92.5, 182.2, 394.1, 780.5, 1607.8", \
" 66.4, 99.7, 187.9, 397.6, 782.1, 1608.5", \
" 76.2, 110.1, 197.4, 404.2, 786.1, 1610.1", \
" 89.6, 124.3, 211.7, 416.5, 794.9, 1615.1" ); }
cell_fall(x3_390_6x10) { /* 50.0% of input to 50.0% of output */
values( " 71.4, 87.4, 119.1, 182.0, 291.5, 523.5", \
" 79.0, 94.9, 126.6, 189.5, 299.0, 531.0", \
" 85.3, 101.2, 132.9, 195.8, 305.3, 537.3", \
" 94.0, 109.9, 141.6, 204.5, 314.0, 546.1", \
" 109.0, 125.0, 156.8, 219.7, 329.2, 561.3", \
" 127.5, 144.5, 176.9, 239.9, 349.4, 581.4", \
" 151.0, 169.2, 203.1, 266.6, 376.0, 608.0", \
" 181.5, 200.9, 236.4, 300.7, 410.3, 642.2", \
" 222.7, 243.5, 281.3, 346.6, 456.4, 688.3", \
" 279.4, 302.0, 342.9, 410.3, 520.4, 752.6" ); }
fall_transition(x3_390_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 41.9, 66.2, 128.0, 272.1, 535.3, 1100.3", \
" 42.0, 66.3, 128.0, 272.1, 535.3, 1100.3", \
" 42.1, 66.4, 128.1, 272.1, 535.3, 1100.3", \
" 42.5, 66.7, 128.3, 272.2, 535.3, 1100.3", \
" 45.3, 68.8, 129.3, 272.6, 535.4, 1100.3", \
" 50.8, 74.1, 132.9, 274.0, 535.8, 1100.3", \
" 57.2, 81.0, 138.8, 277.4, 537.3, 1100.6", \
" 64.9, 89.2, 146.1, 282.2, 539.7, 1101.6", \
" 74.9, 99.9, 156.1, 288.9, 543.3, 1103.1", \
" 88.5, 114.4, 170.6, 299.6, 549.7, 1105.8" ); }}
timing() { /* ring osc delay an2v0x3, path b to z 66.2 */
related_pin : "b" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 69.8 ; */
/* intrinsic_fall : 89.0 ; */
/* rise_resistance : 1.49 ; */
/* fall_resistance : 1.16 ; */
cell_rise(x3_390_6x10) { /* 50.0% of input to 50.0% of output */
values( " 54.8, 71.2, 108.5, 188.9, 330.9, 632.4", \
" 60.9, 77.2, 114.5, 194.9, 337.0, 638.5", \
" 65.5, 81.8, 119.0, 199.4, 341.5, 643.0", \
" 70.6, 86.9, 124.1, 204.4, 346.5, 648.0", \
" 76.3, 93.0, 130.6, 210.8, 352.9, 654.4", \
" 81.6, 98.5, 136.3, 216.8, 358.8, 660.3", \
" 86.1, 103.5, 141.4, 222.1, 364.1, 665.5", \
" 88.5, 106.8, 145.3, 225.8, 368.2, 669.5", \
" 87.0, 106.4, 146.3, 227.3, 369.5, 671.2", \
" 78.1, 99.1, 141.2, 223.8, 366.9, 668.7" ); }
rise_transition(x3_390_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 46.2, 80.4, 173.8, 390.1, 778.9, 1607.3", \
" 46.3, 80.5, 173.9, 390.1, 778.9, 1607.3", \
" 46.8, 80.9, 174.0, 390.2, 778.9, 1607.3", \
" 48.7, 82.3, 174.6, 390.3, 779.0, 1607.3", \
" 51.6, 85.2, 176.6, 391.2, 779.1, 1607.3", \
" 55.3, 88.4, 179.1, 392.6, 779.9, 1607.4", \
" 60.7, 93.2, 182.6, 394.5, 780.9, 1608.1", \
" 68.4, 100.4, 187.7, 397.7, 782.5, 1609.0", \
" 79.0, 111.2, 196.9, 403.5, 786.0, 1610.5", \
" 93.4, 126.4, 211.2, 414.8, 793.7, 1615.0" ); }
cell_fall(x3_390_6x10) { /* 50.0% of input to 50.0% of output */
values( " 63.7, 78.9, 110.0, 172.6, 281.9, 513.8", \
" 71.1, 86.3, 117.4, 180.0, 289.4, 521.2", \
" 77.4, 92.5, 123.6, 186.3, 295.6, 527.5", \
" 85.9, 101.1, 132.2, 194.8, 304.2, 536.1", \
" 99.9, 115.4, 146.7, 209.4, 318.7, 550.6", \
" 116.5, 133.0, 165.2, 228.0, 337.3, 569.2", \
" 137.9, 155.4, 188.8, 252.4, 361.5, 593.3", \
" 165.5, 184.2, 219.2, 283.4, 392.9, 624.5", \
" 202.4, 222.5, 259.9, 325.3, 435.0, 666.7", \
" 252.4, 274.4, 315.2, 383.3, 493.5, 725.6" ); }
fall_transition(x3_390_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 38.6, 63.0, 125.7, 270.8, 534.5, 1099.8", \
" 38.7, 63.1, 125.7, 270.8, 534.5, 1099.8", \
" 38.9, 63.3, 125.8, 270.8, 534.5, 1099.8", \
" 39.7, 63.9, 126.1, 270.9, 534.5, 1099.8", \
" 43.5, 66.8, 127.6, 271.4, 534.6, 1099.8", \
" 48.6, 72.2, 131.6, 273.3, 535.1, 1099.8", \
" 54.8, 78.6, 137.3, 276.7, 536.8, 1100.1", \
" 62.7, 86.8, 144.4, 281.5, 539.2, 1101.2", \
" 73.4, 98.0, 155.0, 288.7, 543.3, 1102.7", \
" 88.1, 113.5, 170.9, 301.1, 551.2, 1106.2" ); }}
}
}
cell(an2v0x4) { /* 2008-01-06:07h20 */
area : 7 ; /* tracks */
cell_leakage_power : 1779 ; /* an2v0x4 */
cell_footprint : an2 ;
pin(a) { /* an2v0x4 FO4 effort 1.53 */
direction : input ;
capacitance : 5.49 ;
rise_capacitance : 5.70 ;
fall_capacitance : 5.29 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin a of an2v0x4 */
}
pin(b) { /* an2v0x4 FO4 effort 1.46 */
direction : input ;
capacitance : 5.26 ;
rise_capacitance : 5.33 ;
fall_capacitance : 5.19 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin b of an2v0x4 */
}
pin(z) {
direction : output ;
min_transition : 20 ;
min_capacitance : 4 ;
max_capacitance : 506 ;
max_fanout : 10 ;
function : "(a*b)" ;
internal_power(a_z_p) { /* an2v0x4 37.77 nW/MHz */
related_pin : "a" ;
power(pwr_x4_520_5x10) {
values( " 18.72, 18.85, 19.20, 19.41, 19.46", \
" 18.47, 18.56, 18.91, 19.14, 19.20", \
" 18.46, 18.52, 18.84, 19.08, 19.16", \
" 18.63, 18.61, 18.88, 19.14, 19.23", \
" 19.22, 19.04, 19.21, 19.45, 19.56", \
" 20.37, 19.98, 19.99, 20.17, 20.29", \
" 22.40, 21.75, 21.53, 21.61, 21.71", \
" 25.74, 24.75, 24.24, 24.15, 24.19", \
" 31.15, 29.73, 28.83, 28.48, 28.42", \
" 39.71, 37.77, 36.32, 35.60, 35.34" ); }}
internal_power(b_z_p) { /* an2v0x4 34.55 nW/MHz */
related_pin : "b" ;
power(pwr_x4_520_5x10) {
values( " 16.98, 17.18, 17.54, 17.75, 17.79", \
" 16.73, 16.89, 17.24, 17.48, 17.54", \
" 16.77, 16.86, 17.19, 17.44, 17.53", \
" 17.02, 17.01, 17.28, 17.53, 17.63", \
" 17.71, 17.53, 17.68, 17.91, 18.02", \
" 18.94, 18.55, 18.53, 18.70, 18.82", \
" 21.04, 20.36, 20.12, 20.18, 20.28", \
" 24.39, 23.37, 22.84, 22.73, 22.76", \
" 29.77, 28.28, 27.35, 26.98, 26.90", \
" 38.27, 36.19, 34.68, 33.93, 33.65" ); }}
timing() { /* ring osc delay an2v0x4, path a to z 71.8 */
related_pin : "a" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 72.6 ; */
/* intrinsic_fall : 98.7 ; */
/* rise_resistance : 1.07 ; */
/* fall_resistance : 0.84 ; */
cell_rise(x4_520_6x10) { /* 50.0% of input to 50.0% of output */
values( " 60.9, 77.2, 113.3, 190.0, 325.2, 612.4", \
" 65.4, 81.6, 117.8, 194.5, 329.8, 616.9", \
" 68.6, 84.7, 120.8, 197.5, 332.8, 620.0", \
" 72.3, 88.5, 124.6, 201.2, 336.6, 623.8", \
" 77.0, 93.6, 129.9, 206.6, 341.9, 629.1", \
" 81.3, 98.2, 135.0, 211.8, 347.1, 634.2", \
" 84.6, 102.1, 139.3, 216.3, 351.6, 638.7", \
" 85.5, 103.8, 142.0, 219.1, 354.6, 641.5", \
" 81.9, 101.3, 141.0, 219.2, 354.6, 641.8", \
" 69.9, 90.6, 132.7, 213.1, 349.9, 637.2" ); }
rise_transition(x4_520_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 46.2, 78.8, 167.3, 372.5, 742.4, 1531.2", \
" 46.3, 78.9, 167.3, 372.5, 742.4, 1531.2", \
" 46.5, 79.1, 167.4, 372.6, 742.4, 1531.2", \
" 48.0, 80.2, 167.9, 372.7, 742.4, 1531.2", \
" 50.7, 82.9, 169.7, 373.4, 742.5, 1531.2", \
" 54.1, 86.2, 172.3, 374.8, 743.1, 1531.2", \
" 59.2, 91.2, 176.1, 376.9, 744.1, 1531.7", \
" 66.4, 98.5, 182.0, 380.7, 745.9, 1532.4", \
" 76.5, 109.0, 191.8, 387.6, 750.1, 1534.1", \
" 90.4, 123.6, 206.5, 400.2, 759.1, 1539.3" ); }
cell_fall(x4_520_6x10) { /* 50.0% of input to 50.0% of output */
values( " 71.4, 87.2, 118.0, 178.2, 282.6, 503.5", \
" 79.0, 94.8, 125.6, 185.8, 290.1, 511.1", \
" 85.3, 101.0, 131.8, 192.1, 296.4, 517.4", \
" 94.0, 109.7, 140.5, 200.8, 305.1, 526.1", \
" 109.0, 124.8, 155.6, 215.9, 320.3, 541.3", \
" 127.4, 144.2, 175.8, 236.1, 340.4, 561.4", \
" 150.9, 168.8, 201.8, 262.7, 366.9, 587.8", \
" 181.0, 200.1, 234.8, 296.6, 401.0, 621.7", \
" 221.5, 242.0, 279.0, 341.9, 446.5, 667.3", \
" 277.0, 299.1, 339.4, 404.4, 509.4, 730.4" ); }
fall_transition(x4_520_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 41.4, 64.8, 123.6, 260.3, 510.5, 1048.3", \
" 41.4, 64.9, 123.6, 260.4, 510.5, 1048.3", \
" 41.5, 65.0, 123.7, 260.4, 510.5, 1048.3", \
" 41.9, 65.3, 123.9, 260.4, 510.5, 1048.3", \
" 44.7, 67.4, 124.9, 260.8, 510.6, 1048.3", \
" 50.4, 72.9, 128.7, 262.4, 511.1, 1048.4", \
" 57.1, 80.1, 135.0, 266.0, 512.7, 1048.7", \
" 65.1, 88.7, 142.8, 271.3, 515.4, 1049.8", \
" 75.7, 99.8, 153.4, 278.6, 519.5, 1051.4", \
" 89.9, 114.9, 168.6, 290.1, 526.5, 1054.5" ); }}
timing() { /* ring osc delay an2v0x4, path b to z 66.4 */
related_pin : "b" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 73.3 ; */
/* intrinsic_fall : 90.3 ; */
/* rise_resistance : 1.07 ; */
/* fall_resistance : 0.83 ; */
cell_rise(x4_520_6x10) { /* 50.0% of input to 50.0% of output */
values( " 56.9, 73.2, 109.3, 185.9, 321.2, 608.4", \
" 63.0, 79.2, 115.3, 192.0, 327.3, 614.5", \
" 67.7, 83.8, 119.9, 196.6, 331.9, 619.1", \
" 73.2, 89.3, 125.3, 201.9, 337.3, 624.5", \
" 79.7, 96.2, 132.5, 209.0, 344.4, 631.6", \
" 85.9, 102.6, 139.2, 215.9, 351.2, 638.3", \
" 91.6, 108.8, 145.5, 222.5, 357.7, 644.7", \
" 95.6, 113.6, 150.9, 227.7, 363.3, 650.2", \
" 96.3, 115.4, 154.1, 231.4, 366.7, 654.0", \
" 90.6, 111.1, 152.1, 230.9, 367.0, 654.4" ); }
rise_transition(x4_520_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 46.2, 78.8, 167.3, 372.5, 742.4, 1531.2", \
" 46.3, 79.0, 167.3, 372.5, 742.4, 1531.2", \
" 46.6, 79.2, 167.5, 372.6, 742.4, 1531.2", \
" 48.4, 80.6, 168.0, 372.7, 742.4, 1531.2", \
" 51.6, 83.6, 170.1, 373.6, 742.5, 1531.2", \
" 55.4, 87.1, 172.9, 375.2, 743.4, 1531.2", \
" 61.1, 92.1, 176.6, 377.3, 744.5, 1531.9", \
" 69.0, 99.7, 182.1, 380.8, 746.2, 1532.8", \
" 80.0, 110.8, 191.7, 386.9, 749.9, 1534.5", \
" 95.2, 126.5, 206.5, 398.6, 757.8, 1538.9" ); }
cell_fall(x4_520_6x10) { /* 50.0% of input to 50.0% of output */
values( " 64.3, 79.4, 109.6, 169.5, 273.7, 494.5", \
" 71.7, 86.8, 117.0, 176.9, 281.1, 502.0", \
" 77.9, 92.9, 123.2, 183.1, 287.3, 508.2", \
" 86.5, 101.5, 131.7, 191.7, 295.9, 516.8", \
" 100.6, 115.9, 146.2, 206.2, 310.4, 531.3", \
" 117.3, 133.5, 164.9, 224.9, 329.1, 550.0", \
" 138.7, 155.9, 188.5, 249.3, 353.4, 574.1", \
" 166.0, 184.4, 218.6, 280.2, 384.6, 605.1", \
" 202.4, 222.2, 258.7, 321.7, 426.2, 646.9", \
" 251.4, 272.9, 312.8, 378.6, 483.7, 704.6" ); }
fall_transition(x4_520_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 38.3, 61.8, 121.3, 259.0, 509.7, 1047.8", \
" 38.3, 61.8, 121.4, 259.0, 509.7, 1047.8", \
" 38.4, 62.0, 121.5, 259.0, 509.7, 1047.8", \
" 39.2, 62.5, 121.7, 259.1, 509.7, 1047.8", \
" 43.0, 65.5, 123.3, 259.7, 509.9, 1047.8", \
" 48.4, 71.1, 127.4, 261.7, 510.4, 1047.9", \
" 55.1, 77.9, 133.5, 265.3, 512.3, 1048.2", \
" 63.3, 86.5, 141.2, 270.6, 515.0, 1049.4", \
" 74.6, 98.2, 152.3, 278.4, 519.5, 1051.1", \
" 90.1, 114.3, 169.0, 291.6, 527.8, 1054.8" ); }}
}
}
cell(an2v0x6) { /* 2008-01-06:07h20 */
area : 10 ; /* tracks */
cell_leakage_power : 2437 ; /* an2v0x6 */
cell_footprint : an2 ;
pin(a) { /* an2v0x6 FO4 effort 1.53 */
direction : input ;
capacitance : 7.06 ;
rise_capacitance : 7.33 ;
fall_capacitance : 6.79 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin a of an2v0x6 */
}
pin(b) { /* an2v0x6 FO4 effort 1.47 */
direction : input ;
capacitance : 6.82 ;
rise_capacitance : 6.92 ;
fall_capacitance : 6.72 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin b of an2v0x6 */
}
pin(z) {
direction : output ;
min_transition : 20 ;
min_capacitance : 6 ;
max_capacitance : 731 ;
max_fanout : 15 ;
function : "(a*b)" ;
internal_power(a_z_p) { /* an2v0x6 52.24 nW/MHz */
related_pin : "a" ;
power(pwr_x6_780_5x10) {
values( " 25.92, 26.06, 26.53, 26.83, 26.89", \
" 25.60, 25.70, 26.16, 26.48, 26.57", \
" 25.60, 25.63, 26.07, 26.41, 26.52", \
" 25.82, 25.75, 26.12, 26.48, 26.60", \
" 26.59, 26.31, 26.53, 26.86, 27.00", \
" 28.13, 27.53, 27.52, 27.77, 27.93", \
" 30.85, 29.84, 29.50, 29.60, 29.73", \
" 35.29, 33.76, 32.99, 32.85, 32.90", \
" 42.45, 40.28, 38.93, 38.42, 38.31", \
" 53.79, 50.82, 48.66, 47.60, 47.21" ); }}
internal_power(b_z_p) { /* an2v0x6 48.01 nW/MHz */
related_pin : "b" ;
power(pwr_x6_780_5x10) {
values( " 23.64, 23.88, 24.38, 24.66, 24.72", \
" 23.32, 23.50, 23.99, 24.31, 24.40", \
" 23.36, 23.45, 23.91, 24.26, 24.37", \
" 23.68, 23.64, 24.01, 24.36, 24.50", \
" 24.61, 24.31, 24.50, 24.83, 24.98", \
" 26.27, 25.64, 25.59, 25.83, 25.98", \
" 29.07, 28.02, 27.65, 27.72, 27.84", \
" 33.55, 31.96, 31.16, 30.98, 31.01", \
" 40.69, 38.41, 37.01, 36.45, 36.32", \
" 51.98, 48.80, 46.54, 45.43, 45.01" ); }}
timing() { /* ring osc delay an2v0x6, path a to z 73.2 */
related_pin : "a" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 74.2 ; */
/* intrinsic_fall : 101.9 ; */
/* rise_resistance : 0.74 ; */
/* fall_resistance : 0.59 ; */
cell_rise(x6_780_6x10) { /* 50.0% of input to 50.0% of output */
values( " 62.4, 79.2, 116.7, 196.2, 336.5, 634.2", \
" 67.0, 83.8, 121.2, 200.7, 341.0, 638.8", \
" 70.1, 86.9, 124.3, 203.8, 344.1, 641.9", \
" 74.0, 90.7, 128.1, 207.6, 347.9, 645.7", \
" 78.8, 96.0, 133.6, 213.1, 353.4, 651.2", \
" 83.3, 100.9, 138.9, 218.5, 358.7, 656.5", \
" 86.9, 105.0, 143.5, 223.2, 363.4, 661.2", \
" 88.1, 107.0, 146.4, 226.2, 366.6, 664.2", \
" 84.8, 104.7, 145.7, 226.5, 366.8, 664.5", \
" 73.0, 94.4, 137.6, 220.6, 362.2, 660.0" ); }
rise_transition(x6_780_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 47.8, 81.7, 173.4, 386.2, 769.8, 1587.8", \
" 47.9, 81.8, 173.4, 386.3, 769.8, 1587.8", \
" 48.2, 82.0, 173.5, 386.3, 769.8, 1587.8", \
" 49.6, 83.0, 173.9, 386.4, 769.8, 1587.8", \
" 52.3, 85.6, 175.7, 387.1, 769.9, 1587.8", \
" 55.8, 89.1, 178.3, 388.4, 770.5, 1587.8", \
" 61.0, 94.0, 182.2, 390.5, 771.4, 1588.3", \
" 68.4, 101.5, 188.0, 394.2, 773.2, 1588.9", \
" 78.8, 112.2, 197.9, 401.0, 777.2, 1590.5", \
" 93.2, 127.1, 212.7, 413.5, 786.0, 1595.4" ); }
cell_fall(x6_780_6x10) { /* 50.0% of input to 50.0% of output */
values( " 74.5, 91.0, 123.4, 186.5, 296.1, 528.1", \
" 82.0, 98.6, 130.9, 194.1, 303.7, 535.7", \
" 88.3, 104.8, 137.1, 200.4, 309.9, 542.0", \
" 97.0, 113.5, 145.8, 209.1, 318.6, 550.7", \
" 112.2, 128.7, 161.1, 224.3, 333.9, 565.9", \
" 131.2, 148.6, 181.5, 244.8, 354.3, 586.3", \
" 155.3, 173.9, 208.2, 272.0, 381.4, 613.3", \
" 186.2, 206.0, 242.1, 306.7, 416.2, 648.0", \
" 227.6, 248.8, 287.2, 352.9, 462.6, 694.4", \
" 284.4, 307.3, 348.9, 416.7, 526.6, 758.6" ); }
fall_transition(x6_780_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 43.6, 68.2, 129.9, 273.5, 536.1, 1100.8", \
" 43.7, 68.3, 129.9, 273.5, 536.1, 1100.8", \
" 43.7, 68.4, 130.0, 273.5, 536.1, 1100.8", \
" 44.1, 68.7, 130.2, 273.6, 536.2, 1100.8", \
" 46.5, 70.5, 131.1, 273.9, 536.2, 1100.8", \
" 52.2, 75.9, 134.6, 275.3, 536.6, 1100.9", \
" 59.4, 83.4, 140.9, 278.8, 538.1, 1101.1", \
" 67.7, 92.3, 149.0, 284.1, 540.7, 1102.1", \
" 78.6, 103.7, 159.7, 291.5, 544.8, 1103.7", \
" 93.3, 119.1, 175.1, 302.9, 551.7, 1106.6" ); }}
timing() { /* ring osc delay an2v0x6, path b to z 67.8 */
related_pin : "b" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 75.0 ; */
/* intrinsic_fall : 93.4 ; */
/* rise_resistance : 0.74 ; */
/* fall_resistance : 0.58 ; */
cell_rise(x6_780_6x10) { /* 50.0% of input to 50.0% of output */
values( " 58.4, 75.3, 112.7, 192.2, 332.5, 630.3", \
" 64.5, 81.3, 118.7, 198.2, 338.6, 636.4", \
" 69.3, 86.0, 123.3, 202.9, 343.2, 641.0", \
" 75.0, 91.6, 128.9, 208.4, 348.7, 646.5", \
" 81.8, 98.8, 136.3, 215.7, 356.0, 653.8", \
" 88.2, 105.5, 143.3, 222.8, 363.0, 660.8", \
" 94.2, 111.9, 149.9, 229.6, 369.8, 667.5", \
" 98.6, 117.0, 155.6, 235.1, 375.6, 673.1", \
" 99.6, 119.1, 159.1, 239.0, 379.2, 677.0", \
" 94.2, 115.2, 157.3, 238.7, 379.6, 677.5" ); }
rise_transition(x6_780_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 47.8, 81.7, 173.4, 386.2, 769.8, 1587.8", \
" 47.9, 81.8, 173.4, 386.3, 769.8, 1587.8", \
" 48.2, 82.1, 173.6, 386.3, 769.8, 1587.8", \
" 49.8, 83.3, 174.1, 386.4, 769.8, 1587.8", \
" 53.3, 86.3, 176.1, 387.2, 769.9, 1587.8", \
" 57.2, 90.0, 178.9, 388.8, 770.7, 1587.8", \
" 63.0, 95.1, 182.8, 390.9, 771.8, 1588.5", \
" 71.2, 102.9, 188.3, 394.3, 773.5, 1589.4", \
" 82.6, 114.3, 197.9, 400.4, 777.0, 1590.9", \
" 98.3, 130.4, 212.9, 412.0, 784.8, 1595.2" ); }
cell_fall(x6_780_6x10) { /* 50.0% of input to 50.0% of output */
values( " 67.2, 83.0, 114.8, 177.6, 287.0, 519.0", \
" 74.6, 90.4, 122.1, 185.0, 294.5, 526.4", \
" 80.8, 96.6, 128.3, 191.3, 300.7, 532.6", \
" 89.4, 105.1, 136.9, 199.8, 309.3, 541.2", \
" 103.9, 119.8, 151.6, 214.5, 323.9, 555.9", \
" 121.1, 138.0, 170.6, 233.6, 343.0, 574.9", \
" 143.1, 161.0, 195.0, 258.6, 367.9, 599.7", \
" 171.3, 190.3, 225.9, 290.3, 399.8, 631.4", \
" 208.7, 229.1, 267.0, 332.7, 442.3, 673.9", \
" 259.1, 281.3, 322.6, 390.9, 501.0, 732.8" ); }
fall_transition(x6_780_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 40.5, 65.1, 127.6, 272.1, 535.3, 1100.3", \
" 40.4, 65.2, 127.6, 272.1, 535.3, 1100.3", \
" 40.6, 65.3, 127.7, 272.1, 535.3, 1100.3", \
" 41.2, 65.8, 127.9, 272.2, 535.3, 1100.3", \
" 44.7, 68.4, 129.2, 272.6, 535.5, 1100.3", \
" 50.5, 74.1, 133.2, 274.5, 535.9, 1100.4", \
" 57.3, 81.2, 139.5, 278.1, 537.7, 1100.6", \
" 65.9, 90.0, 147.3, 283.4, 540.3, 1101.7", \
" 77.5, 102.0, 158.6, 291.2, 544.7, 1103.4", \
" 93.4, 118.4, 175.4, 304.2, 552.9, 1106.9" ); }}
}
}
cell(an2v0x8) { /* 2008-01-06:07h20 */
area : 12 ; /* tracks */
cell_leakage_power : 3269 ; /* an2v0x8 */
cell_footprint : an2 ;
pin(a) { /* an2v0x8 FO4 effort 1.53 */
direction : input ;
capacitance : 8.88 ;
rise_capacitance : 9.25 ;
fall_capacitance : 8.52 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin a of an2v0x8 */
}
pin(b) { /* an2v0x8 FO4 effort 1.47 */
direction : input ;
capacitance : 8.57 ;
rise_capacitance : 8.71 ;
fall_capacitance : 8.43 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin b of an2v0x8 */
}
pin(z) {
direction : output ;
min_transition : 20 ;
min_capacitance : 8 ;
max_capacitance : 1012 ;
max_fanout : 20 ;
function : "(a*b)" ;
internal_power(a_z_p) { /* an2v0x8 69.97 nW/MHz */
related_pin : "a" ;
power(pwr_x8_1040_5x10) {
values( " 34.90, 34.91, 35.51, 35.93, 36.04", \
" 34.52, 34.46, 35.05, 35.50, 35.63", \
" 34.52, 34.38, 34.93, 35.40, 35.56", \
" 34.82, 34.54, 34.99, 35.47, 35.66", \
" 35.84, 35.27, 35.49, 35.94, 36.15", \
" 37.92, 36.90, 36.77, 37.09, 37.31", \
" 41.58, 39.94, 39.33, 39.41, 39.57", \
" 47.47, 45.09, 43.84, 43.54, 43.58", \
" 56.91, 53.62, 51.50, 50.66, 50.45", \
" 71.80, 67.39, 64.08, 62.43, 61.80" ); }}
internal_power(b_z_p) { /* an2v0x8 64.46 nW/MHz */
related_pin : "b" ;
power(pwr_x8_1040_5x10) {
values( " 31.90, 32.08, 32.74, 33.15, 33.25", \
" 31.51, 31.60, 32.23, 32.69, 32.83", \
" 31.55, 31.53, 32.12, 32.61, 32.78", \
" 31.99, 31.78, 32.23, 32.72, 32.93", \
" 33.24, 32.68, 32.87, 33.29, 33.52", \
" 35.51, 34.45, 34.27, 34.56, 34.77", \
" 39.28, 37.59, 36.92, 36.96, 37.11", \
" 45.25, 42.77, 41.46, 41.11, 41.13", \
" 54.72, 51.24, 49.04, 48.13, 47.89", \
" 69.61, 64.87, 61.40, 59.67, 58.99" ); }}
timing() { /* ring osc delay an2v0x8, path a to z 74.0 */
related_pin : "a" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 74.8 ; */
/* intrinsic_fall : 105.0 ; */
/* rise_resistance : 0.53 ; */
/* fall_resistance : 0.41 ; */
cell_rise(x8_1040_6x10) { /* 50.0% of input to 50.0% of output */
values( " 62.6, 79.1, 115.4, 192.2, 327.5, 614.7", \
" 67.2, 83.7, 120.0, 196.8, 332.1, 619.3", \
" 70.4, 86.8, 123.1, 199.8, 335.2, 622.4", \
" 74.3, 90.7, 126.9, 203.7, 339.0, 626.2", \
" 79.2, 96.0, 132.5, 209.2, 344.6, 631.7", \
" 83.8, 101.0, 137.9, 214.7, 350.0, 637.1", \
" 87.5, 105.1, 142.5, 219.4, 354.7, 641.8", \
" 88.6, 107.0, 145.2, 222.3, 357.7, 644.6", \
" 84.9, 104.3, 144.1, 222.2, 357.5, 644.5", \
" 72.6, 93.3, 135.3, 215.4, 352.0, 639.0" ); }
rise_transition(x8_1040_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 47.3, 80.1, 168.3, 373.3, 742.9, 1531.6", \
" 47.4, 80.2, 168.4, 373.3, 742.9, 1531.6", \
" 47.6, 80.4, 168.5, 373.3, 742.9, 1531.6", \
" 48.9, 81.3, 168.9, 373.4, 742.9, 1531.6", \
" 51.7, 84.0, 170.6, 374.1, 743.0, 1531.6", \
" 55.2, 87.4, 173.3, 375.5, 743.6, 1531.6", \
" 60.4, 92.4, 177.3, 377.7, 744.6, 1532.1", \
" 67.8, 99.9, 183.3, 381.5, 746.4, 1532.8", \
" 78.3, 110.7, 193.2, 388.4, 750.5, 1534.4", \
" 92.8, 125.7, 208.1, 401.1, 759.4, 1539.4" ); }
cell_fall(x8_1040_6x10) { /* 50.0% of input to 50.0% of output */
values( " 76.6, 93.0, 124.3, 184.0, 286.6, 503.7", \
" 84.2, 100.5, 131.8, 191.5, 294.1, 511.3", \
" 90.4, 106.8, 138.0, 197.7, 300.4, 517.5", \
" 99.2, 115.4, 146.7, 206.4, 309.1, 526.2", \
" 114.6, 130.8, 162.1, 221.8, 324.5, 541.6", \
" 134.2, 151.3, 183.0, 242.8, 345.3, 562.5", \
" 159.1, 177.2, 210.6, 270.8, 373.3, 590.4", \
" 190.9, 210.2, 245.4, 306.7, 409.3, 626.1", \
" 233.7, 254.3, 291.8, 354.4, 457.2, 674.1", \
" 292.4, 314.6, 355.2, 420.1, 523.3, 740.3" ); }
fall_transition(x8_1040_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 44.4, 67.9, 125.4, 258.8, 503.7, 1031.4", \
" 44.5, 68.0, 125.5, 258.8, 503.7, 1031.4", \
" 44.5, 68.1, 125.5, 258.9, 503.7, 1031.4", \
" 44.8, 68.4, 125.7, 258.9, 503.7, 1031.4", \
" 46.9, 69.9, 126.6, 259.2, 503.8, 1031.4", \
" 52.8, 75.2, 130.0, 260.6, 504.2, 1031.5", \
" 60.2, 83.0, 136.8, 264.5, 505.9, 1031.7", \
" 68.9, 92.2, 145.4, 270.3, 508.8, 1032.9", \
" 79.9, 103.8, 156.6, 278.4, 513.4, 1034.7", \
" 94.9, 119.3, 172.3, 290.5, 520.9, 1037.9" ); }}
timing() { /* ring osc delay an2v0x8, path b to z 68.5 */
related_pin : "b" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 75.8 ; */
/* intrinsic_fall : 96.3 ; */
/* rise_resistance : 0.53 ; */
/* fall_resistance : 0.41 ; */
cell_rise(x8_1040_6x10) { /* 50.0% of input to 50.0% of output */
values( " 58.7, 75.2, 111.6, 188.3, 323.6, 610.8", \
" 64.9, 81.3, 117.6, 194.4, 329.7, 616.9", \
" 69.7, 86.0, 122.3, 199.0, 334.4, 621.6", \
" 75.4, 91.7, 127.8, 204.6, 339.9, 627.2", \
" 82.4, 99.0, 135.4, 212.0, 347.3, 634.5", \
" 88.9, 105.8, 142.5, 219.2, 354.5, 641.6", \
" 94.9, 112.2, 149.1, 226.0, 361.2, 648.3", \
" 99.2, 117.2, 154.7, 231.4, 366.9, 653.7", \
" 99.9, 119.0, 157.8, 234.9, 370.1, 657.2", \
" 93.9, 114.3, 155.3, 233.8, 369.6, 656.8" ); }
rise_transition(x8_1040_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 47.4, 80.1, 168.3, 373.3, 742.9, 1531.6", \
" 47.4, 80.2, 168.4, 373.3, 742.9, 1531.6", \
" 47.6, 80.4, 168.5, 373.3, 742.9, 1531.6", \
" 49.2, 81.6, 169.0, 373.5, 742.9, 1531.6", \
" 52.7, 84.7, 171.1, 374.3, 743.0, 1531.6", \
" 56.7, 88.4, 174.0, 375.9, 743.8, 1531.6", \
" 62.6, 93.7, 178.0, 378.1, 745.0, 1532.3", \
" 70.9, 101.6, 183.7, 381.7, 746.8, 1533.2", \
" 82.5, 113.1, 193.5, 387.9, 750.4, 1534.8", \
" 98.5, 129.4, 208.7, 399.8, 758.2, 1539.1" ); }
cell_fall(x8_1040_6x10) { /* 50.0% of input to 50.0% of output */
values( " 69.3, 84.9, 115.5, 174.8, 277.3, 494.3", \
" 76.6, 92.2, 122.8, 182.2, 284.6, 501.7", \
" 82.9, 98.4, 129.0, 188.3, 290.8, 507.9", \
" 91.5, 106.9, 137.5, 196.9, 299.4, 516.5", \
" 106.3, 121.8, 152.5, 211.9, 314.3, 531.4", \
" 124.2, 140.7, 172.1, 231.6, 334.0, 551.0", \
" 147.0, 164.5, 197.3, 257.5, 359.7, 576.6", \
" 176.1, 194.7, 229.2, 290.3, 392.9, 609.5", \
" 215.0, 234.9, 271.7, 334.2, 436.9, 653.6", \
" 267.6, 289.0, 329.1, 394.4, 497.7, 714.6" ); }
fall_transition(x8_1040_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 41.1, 64.5, 122.9, 257.3, 502.7, 1030.8", \
" 41.2, 64.6, 122.9, 257.3, 502.7, 1030.8", \
" 41.3, 64.7, 123.0, 257.3, 502.7, 1030.8", \
" 41.7, 65.1, 123.2, 257.4, 502.8, 1030.8", \
" 45.0, 67.5, 124.4, 257.8, 502.9, 1030.8", \
" 51.0, 73.3, 128.5, 259.7, 503.4, 1030.9", \
" 58.2, 80.7, 135.2, 263.7, 505.3, 1031.2", \
" 67.0, 89.8, 143.5, 269.5, 508.4, 1032.5", \
" 78.9, 101.9, 155.1, 277.8, 513.2, 1034.3", \
" 95.1, 118.6, 172.2, 291.4, 521.9, 1038.2" ); }}
}
}
cell(an2v2x2) { /* 2008-01-06:07h21 */
area : 5 ; /* tracks */
cell_leakage_power : 1040 ; /* an2v2x2 */
cell_footprint : an2 ;
pin(a) { /* an2v2x2 FO4 effort 1.61 */
direction : input ;
capacitance : 3.94 ;
rise_capacitance : 4.09 ;
fall_capacitance : 3.80 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin a of an2v2x2 */
}
pin(b) { /* an2v2x2 FO4 effort 1.52 */
direction : input ;
capacitance : 3.75 ;
rise_capacitance : 3.80 ;
fall_capacitance : 3.70 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin b of an2v2x2 */
}
pin(z) {
direction : output ;
min_transition : 20 ;
min_capacitance : 2 ;
max_capacitance : 252 ;
max_fanout : 6 ;
function : "(a*b)" ;
internal_power(a_z_p) { /* an2v2x2 23.36 nW/MHz */
related_pin : "a" ;
power(pwr_x2_260_5x10) {
values( " 11.55, 11.69, 11.89, 11.99, 12.01", \
" 11.35, 11.48, 11.67, 11.79, 11.83", \
" 11.35, 11.45, 11.64, 11.77, 11.81", \
" 11.44, 11.51, 11.68, 11.82, 11.87", \
" 11.79, 11.79, 11.92, 12.06, 12.11", \
" 12.48, 12.41, 12.46, 12.58, 12.65", \
" 13.75, 13.56, 13.53, 13.61, 13.67", \
" 15.85, 15.54, 15.38, 15.39, 15.43", \
" 19.30, 18.81, 18.49, 18.38, 18.38", \
" 24.78, 24.08, 23.53, 23.25, 23.16" ); }}
internal_power(b_z_p) { /* an2v2x2 21.08 nW/MHz */
related_pin : "b" ;
power(pwr_x2_260_5x10) {
values( " 10.32, 10.49, 10.68, 10.79, 10.81", \
" 10.14, 10.28, 10.48, 10.60, 10.64", \
" 10.16, 10.27, 10.46, 10.60, 10.64", \
" 10.31, 10.37, 10.54, 10.68, 10.74", \
" 10.72, 10.72, 10.83, 10.97, 11.03", \
" 11.46, 11.38, 11.43, 11.55, 11.62", \
" 12.76, 12.58, 12.54, 12.61, 12.67", \
" 14.87, 14.55, 14.39, 14.39, 14.43", \
" 18.27, 17.77, 17.45, 17.34, 17.33", \
" 23.67, 22.93, 22.37, 22.09, 22.00" ); }}
timing() { /* ring osc delay an2v2x2, path a to z 73.8 */
related_pin : "a" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 69.2 ; */
/* intrinsic_fall : 95.3 ; */
/* rise_resistance : 2.13 ; */
/* fall_resistance : 1.66 ; */
cell_rise(x2_260_6x10) { /* 50.0% of input to 50.0% of output */
values( " 59.2, 74.5, 109.9, 186.4, 321.7, 608.8", \
" 63.7, 78.9, 114.3, 190.9, 326.2, 613.3", \
" 66.7, 81.9, 117.3, 193.9, 329.2, 616.3", \
" 70.1, 85.4, 120.8, 197.4, 332.7, 619.9", \
" 74.1, 89.7, 125.5, 202.1, 337.4, 624.6", \
" 77.5, 93.5, 129.5, 206.3, 341.6, 628.8", \
" 79.7, 96.2, 132.6, 209.5, 344.9, 632.0", \
" 79.1, 96.4, 133.7, 210.7, 346.3, 633.3", \
" 73.3, 91.7, 130.6, 208.8, 344.4, 631.7", \
" 58.6, 78.4, 119.5, 199.9, 337.2, 624.6" ); }
rise_transition(x2_260_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 48.8, 81.2, 170.5, 376.7, 747.1, 1536.0", \
" 48.9, 81.3, 170.5, 376.7, 747.1, 1536.0", \
" 49.4, 81.6, 170.6, 376.7, 747.1, 1536.0", \
" 51.0, 82.9, 171.2, 376.9, 747.1, 1536.0", \
" 53.6, 85.5, 172.9, 377.6, 747.2, 1536.0", \
" 57.0, 88.6, 175.3, 378.9, 747.8, 1536.1", \
" 62.1, 93.4, 178.8, 380.8, 748.7, 1536.6", \
" 69.3, 100.6, 184.6, 384.4, 750.5, 1537.3", \
" 79.1, 110.9, 194.1, 391.1, 754.7, 1539.1", \
" 92.5, 125.0, 208.4, 403.7, 763.8, 1544.6" ); }
cell_fall(x2_260_6x10) { /* 50.0% of input to 50.0% of output */
values( " 70.0, 84.3, 114.0, 173.8, 278.0, 499.0", \
" 77.5, 91.8, 121.5, 181.3, 285.6, 506.6", \
" 83.8, 98.1, 127.8, 187.6, 291.9, 512.9", \
" 92.5, 106.8, 136.5, 196.3, 300.6, 521.6", \
" 107.2, 121.7, 151.5, 211.3, 315.6, 536.6", \
" 125.0, 140.4, 171.0, 230.9, 335.1, 556.1", \
" 147.8, 164.3, 196.0, 256.6, 360.8, 581.7", \
" 177.4, 195.0, 228.3, 289.4, 393.9, 614.7", \
" 217.4, 236.4, 271.7, 333.8, 438.5, 659.5", \
" 272.4, 293.1, 331.4, 395.5, 500.5, 721.8" ); }
fall_transition(x2_260_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 42.4, 65.1, 124.2, 262.0, 512.9, 1051.2", \
" 42.4, 65.2, 124.2, 262.0, 512.9, 1051.2", \
" 42.6, 65.3, 124.3, 262.0, 512.9, 1051.2", \
" 43.1, 65.8, 124.5, 262.1, 512.9, 1051.2", \
" 46.3, 68.2, 125.7, 262.5, 513.0, 1051.2", \
" 51.6, 73.4, 129.4, 264.1, 513.5, 1051.2", \
" 57.8, 79.9, 135.1, 267.4, 515.1, 1051.5", \
" 65.3, 87.9, 142.1, 272.0, 517.4, 1052.6", \
" 75.2, 98.4, 151.8, 278.5, 521.1, 1054.1", \
" 88.7, 112.8, 166.0, 289.2, 527.5, 1057.0" ); }}
timing() { /* ring osc delay an2v2x2, path b to z 68.0 */
related_pin : "b" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 69.2 ; */
/* intrinsic_fall : 86.3 ; */
/* rise_resistance : 2.13 ; */
/* fall_resistance : 1.66 ; */
cell_rise(x2_260_6x10) { /* 50.0% of input to 50.0% of output */
values( " 55.0, 70.3, 105.7, 182.2, 317.5, 604.6", \
" 61.0, 76.2, 111.7, 188.2, 323.5, 610.7", \
" 65.5, 80.6, 116.0, 192.6, 328.0, 615.1", \
" 70.3, 85.5, 120.9, 197.4, 332.8, 620.0", \
" 75.7, 91.2, 127.0, 203.5, 338.8, 626.0", \
" 80.7, 96.4, 132.2, 209.1, 344.3, 631.5", \
" 84.9, 101.0, 137.0, 213.9, 349.3, 636.4", \
" 87.1, 104.0, 140.6, 217.3, 353.1, 640.1", \
" 85.5, 103.4, 141.3, 218.7, 354.3, 641.7", \
" 76.7, 96.1, 136.0, 215.1, 351.7, 639.3" ); }
rise_transition(x2_260_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 48.8, 81.2, 170.5, 376.7, 747.1, 1536.0", \
" 48.9, 81.4, 170.5, 376.7, 747.1, 1536.0", \
" 49.5, 81.8, 170.7, 376.7, 747.1, 1536.0", \
" 51.5, 83.3, 171.4, 376.9, 747.1, 1536.0", \
" 54.3, 86.2, 173.4, 377.8, 747.2, 1536.0", \
" 57.9, 89.2, 175.8, 379.2, 748.1, 1536.1", \
" 63.2, 93.8, 179.1, 381.1, 749.2, 1536.9", \
" 70.7, 101.0, 184.2, 384.4, 750.8, 1537.8", \
" 81.2, 111.5, 193.4, 390.3, 754.5, 1539.5", \
" 95.6, 126.5, 207.5, 401.7, 762.5, 1544.3" ); }
cell_fall(x2_260_6x10) { /* 50.0% of input to 50.0% of output */
values( " 62.0, 75.8, 105.0, 164.4, 268.6, 489.4", \
" 69.5, 83.2, 112.4, 171.9, 276.0, 496.9", \
" 75.7, 89.4, 118.6, 178.2, 282.3, 503.2", \
" 84.2, 97.9, 127.1, 186.7, 290.9, 511.7", \
" 97.6, 111.8, 141.2, 200.8, 305.0, 525.9", \
" 113.6, 128.6, 159.0, 218.7, 322.8, 543.7", \
" 134.2, 150.1, 181.5, 242.0, 346.0, 566.8", \
" 160.8, 177.8, 210.6, 271.7, 376.1, 596.7", \
" 196.3, 214.7, 249.8, 312.1, 416.6, 637.5", \
" 244.4, 264.6, 303.0, 367.9, 473.2, 694.3" ); }
fall_transition(x2_260_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 39.1, 62.1, 122.1, 260.7, 512.1, 1050.6", \
" 39.3, 62.3, 122.1, 260.7, 512.1, 1050.6", \
" 39.6, 62.5, 122.2, 260.7, 512.1, 1050.6", \
" 40.6, 63.2, 122.6, 260.8, 512.2, 1050.6", \
" 44.5, 66.4, 124.4, 261.4, 512.3, 1050.7", \
" 49.4, 71.5, 128.2, 263.5, 512.9, 1050.7", \
" 55.4, 77.6, 133.7, 266.7, 514.6, 1051.1", \
" 63.1, 85.6, 140.5, 271.4, 517.0, 1052.2", \
" 73.7, 96.7, 150.9, 278.5, 521.1, 1053.8", \
" 88.2, 112.1, 166.8, 291.1, 529.2, 1057.5" ); }}
}
}
cell(an2v4x1) { /* 2008-01-06:07h21 */
area : 5 ; /* tracks */
cell_leakage_power : 520 ; /* an2v4x1 */
cell_footprint : an2 ;
pin(a) { /* an2v4x1 FO4 effort 1.81 */
direction : input ;
capacitance : 1.75 ;
rise_capacitance : 1.84 ;
fall_capacitance : 1.67 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin a of an2v4x1 */
}
pin(b) { /* an2v4x1 FO4 effort 1.69 */
direction : input ;
capacitance : 1.58 ;
rise_capacitance : 1.61 ;
fall_capacitance : 1.54 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin b of an2v4x1 */
}
pin(z) {
direction : output ;
min_transition : 20 ;
min_capacitance : 2 ;
max_capacitance : 161 ;
max_fanout : 4 ;
function : "(a*b)" ;
internal_power(a_z_p) { /* an2v4x1 14.13 nW/MHz */
related_pin : "a" ;
power(pwr_x1_195_5x10) {
values( " 7.08, 7.09, 7.19, 7.26, 7.27", \
" 7.00, 7.00, 7.10, 7.17, 7.19", \
" 6.98, 6.98, 7.07, 7.15, 7.17", \
" 7.01, 6.98, 7.07, 7.15, 7.18", \
" 7.12, 7.06, 7.12, 7.20, 7.24", \
" 7.41, 7.29, 7.30, 7.36, 7.40", \
" 7.94, 7.74, 7.67, 7.70, 7.73", \
" 8.83, 8.51, 8.35, 8.32, 8.34", \
" 10.28, 9.81, 9.52, 9.41, 9.39", \
" 12.58, 11.94, 11.47, 11.23, 11.16" ); }}
internal_power(b_z_p) { /* an2v4x1 13.04 nW/MHz */
related_pin : "b" ;
power(pwr_x1_195_5x10) {
values( " 6.47, 6.51, 6.62, 6.69, 6.71", \
" 6.40, 6.43, 6.54, 6.61, 6.64", \
" 6.39, 6.41, 6.51, 6.60, 6.62", \
" 6.44, 6.43, 6.52, 6.61, 6.64", \
" 6.60, 6.55, 6.60, 6.68, 6.72", \
" 6.93, 6.80, 6.80, 6.87, 6.91", \
" 7.49, 7.28, 7.20, 7.23, 7.26", \
" 8.40, 8.07, 7.89, 7.86, 7.88", \
" 9.85, 9.37, 9.06, 8.95, 8.92", \
" 12.17, 11.49, 10.99, 10.75, 10.66" ); }}
timing() { /* ring osc delay an2v4x1, path a to z 91.5 */
related_pin : "a" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 83.4 ; */
/* intrinsic_fall : 126.9 ; */
/* rise_resistance : 3.31 ; */
/* fall_resistance : 2.62 ; */
cell_rise(x1_195_6x10) { /* 50.0% of input to 50.0% of output */
values( " 72.0, 90.4, 132.2, 221.6, 379.4, 714.4", \
" 76.7, 95.0, 136.9, 226.3, 384.1, 719.2", \
" 79.9, 98.2, 140.0, 229.4, 387.3, 722.3", \
" 83.9, 102.1, 143.9, 233.3, 391.2, 726.2", \
" 89.1, 107.7, 149.6, 239.0, 396.9, 731.9", \
" 93.9, 112.9, 155.3, 244.7, 402.5, 737.5", \
" 97.6, 117.1, 159.8, 249.5, 407.2, 742.1", \
" 98.5, 118.6, 162.0, 251.7, 409.6, 744.4", \
" 93.8, 114.9, 159.8, 250.0, 407.9, 742.7", \
" 79.1, 101.7, 148.7, 240.7, 399.2, 734.2" ); }
rise_transition(x1_195_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 58.9, 96.9, 200.3, 439.9, 871.5, 1791.7", \
" 59.0, 96.9, 200.3, 439.9, 871.5, 1791.7", \
" 59.1, 97.1, 200.4, 439.9, 871.5, 1791.7", \
" 60.1, 97.8, 200.7, 440.0, 871.5, 1791.7", \
" 63.1, 100.3, 202.2, 440.5, 871.5, 1791.7", \
" 66.6, 104.0, 204.8, 441.9, 872.0, 1791.8", \
" 71.9, 108.8, 208.7, 443.9, 873.0, 1792.1", \
" 79.6, 116.3, 214.3, 447.3, 874.5, 1792.8", \
" 90.6, 127.4, 223.8, 453.6, 877.9, 1794.1", \
" 105.8, 143.0, 238.7, 465.1, 885.6, 1798.0" ); }
cell_fall(x1_195_6x10) { /* 50.0% of input to 50.0% of output */
values( " 98.6, 117.5, 154.7, 225.8, 347.7, 605.6", \
" 105.7, 124.6, 161.9, 233.0, 354.9, 612.8", \
" 111.8, 130.7, 167.9, 239.1, 361.0, 618.8", \
" 120.4, 139.3, 176.5, 247.6, 369.6, 627.4", \
" 136.1, 154.9, 192.1, 263.2, 385.2, 643.1", \
" 158.0, 176.9, 214.2, 285.4, 407.3, 665.2", \
" 186.3, 206.4, 245.0, 316.3, 438.1, 695.9", \
" 222.2, 243.6, 284.1, 356.5, 478.2, 735.9", \
" 270.2, 293.1, 335.9, 409.7, 531.8, 789.2", \
" 336.5, 360.9, 406.9, 482.6, 605.0, 862.6" ); }
fall_transition(x1_195_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 59.4, 87.0, 155.2, 313.0, 603.2, 1229.3", \
" 59.3, 87.0, 155.2, 313.0, 603.2, 1229.3", \
" 59.4, 87.1, 155.3, 313.0, 603.2, 1229.3", \
" 59.5, 87.2, 155.3, 313.1, 603.2, 1229.3", \
" 60.2, 87.9, 155.8, 313.2, 603.2, 1229.4", \
" 64.9, 91.4, 157.8, 314.0, 603.5, 1229.4", \
" 73.2, 99.7, 164.0, 317.1, 604.5, 1229.6", \
" 82.8, 109.8, 173.4, 323.1, 607.5, 1230.3", \
" 94.4, 122.0, 185.1, 331.6, 612.1, 1232.2", \
" 109.7, 137.9, 200.8, 343.4, 619.3, 1235.2" ); }}
timing() { /* ring osc delay an2v4x1, path b to z 84.0 */
related_pin : "b" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 83.2 ; */
/* intrinsic_fall : 115.1 ; */
/* rise_resistance : 3.31 ; */
/* fall_resistance : 2.61 ; */
cell_rise(x1_195_6x10) { /* 50.0% of input to 50.0% of output */
values( " 67.0, 85.3, 127.2, 216.6, 374.4, 709.4", \
" 73.2, 91.5, 133.3, 222.7, 380.6, 715.6", \
" 78.0, 96.2, 138.0, 227.4, 385.3, 720.4", \
" 83.8, 102.0, 143.7, 233.1, 391.0, 726.1", \
" 91.3, 109.8, 151.5, 240.8, 398.7, 733.8", \
" 98.2, 116.8, 159.0, 248.3, 406.1, 741.1", \
" 104.2, 123.3, 165.5, 255.1, 412.7, 747.6", \
" 108.1, 127.8, 170.5, 259.7, 417.7, 752.4", \
" 107.6, 128.4, 172.2, 261.6, 419.3, 754.2", \
" 99.0, 121.2, 167.1, 257.6, 415.5, 750.5" ); }
rise_transition(x1_195_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 58.9, 96.9, 200.3, 439.9, 871.5, 1791.7", \
" 59.0, 97.0, 200.3, 439.9, 871.5, 1791.7", \
" 59.2, 97.2, 200.4, 439.9, 871.5, 1791.7", \
" 60.4, 98.0, 200.8, 440.0, 871.5, 1791.7", \
" 63.8, 100.9, 202.5, 440.6, 871.6, 1791.7", \
" 68.0, 104.9, 205.3, 442.1, 872.1, 1791.8", \
" 74.1, 110.0, 209.3, 444.2, 873.2, 1792.1", \
" 82.7, 117.9, 214.7, 447.4, 874.7, 1793.1", \
" 94.8, 129.8, 224.2, 453.2, 877.8, 1794.3", \
" 111.5, 146.7, 239.4, 464.1, 884.7, 1797.8" ); }
cell_fall(x1_195_6x10) { /* 50.0% of input to 50.0% of output */
values( " 88.0, 106.1, 142.5, 213.2, 334.9, 592.7", \
" 95.2, 113.2, 149.6, 220.3, 342.0, 599.8", \
" 101.2, 119.2, 155.7, 226.4, 348.1, 605.9", \
" 109.8, 127.8, 164.2, 235.0, 356.7, 614.5", \
" 125.3, 143.2, 179.6, 250.3, 372.1, 629.9", \
" 145.9, 164.2, 200.8, 271.6, 393.3, 651.1", \
" 171.9, 191.4, 229.5, 300.5, 422.1, 679.8", \
" 205.2, 225.8, 265.6, 337.8, 459.3, 716.7", \
" 249.6, 271.5, 313.5, 387.0, 509.0, 766.1", \
" 310.2, 333.8, 378.9, 454.8, 577.0, 834.4" ); }
fall_transition(x1_195_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 55.1, 82.7, 151.9, 311.0, 601.9, 1228.6", \
" 55.1, 82.7, 151.9, 311.0, 601.9, 1228.6", \
" 55.2, 82.8, 151.9, 311.0, 602.0, 1228.6", \
" 55.3, 83.0, 152.1, 311.1, 602.0, 1228.6", \
" 56.9, 84.1, 152.7, 311.3, 602.0, 1228.6", \
" 62.5, 88.8, 155.5, 312.4, 602.4, 1228.7", \
" 70.6, 96.9, 162.0, 316.0, 603.7, 1228.8", \
" 80.1, 106.6, 171.0, 321.8, 606.7, 1229.7", \
" 92.2, 119.0, 182.6, 330.3, 611.4, 1231.5", \
" 108.7, 135.9, 199.3, 343.0, 619.3, 1234.7" ); }}
}
}
cell(an2v4x2) { /* 2008-01-06:07h21 */
area : 5 ; /* tracks */
cell_leakage_power : 751 ; /* an2v4x2 */
cell_footprint : an2 ;
pin(a) { /* an2v4x2 FO4 effort 1.78 */
direction : input ;
capacitance : 2.08 ;
rise_capacitance : 2.18 ;
fall_capacitance : 1.99 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin a of an2v4x2 */
}
pin(b) { /* an2v4x2 FO4 effort 1.69 */
direction : input ;
capacitance : 1.88 ;
rise_capacitance : 1.91 ;
fall_capacitance : 1.85 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin b of an2v4x2 */
}
pin(z) {
direction : output ;
min_transition : 20 ;
min_capacitance : 2 ;
max_capacitance : 251 ;
max_fanout : 6 ;
function : "(a*b)" ;
internal_power(a_z_p) { /* an2v4x2 19.57 nW/MHz */
related_pin : "a" ;
power(pwr_x2_260_5x10) {
values( " 9.91, 9.83, 9.93, 10.04, 10.07", \
" 9.82, 9.73, 9.83, 9.94, 9.98", \
" 9.80, 9.70, 9.79, 9.91, 9.95", \
" 9.84, 9.71, 9.79, 9.90, 9.95", \
" 10.01, 9.83, 9.86, 9.96, 10.02", \
" 10.42, 10.15, 10.09, 10.16, 10.21", \
" 11.19, 10.78, 10.58, 10.58, 10.62", \
" 12.45, 11.84, 11.48, 11.37, 11.37", \
" 14.45, 13.62, 13.03, 12.77, 12.70", \
" 17.62, 16.52, 15.61, 15.14, 14.95" ); }}
internal_power(b_z_p) { /* an2v4x2 18.32 nW/MHz */
related_pin : "b" ;
power(pwr_x2_260_5x10) {
values( " 9.20, 9.16, 9.29, 9.39, 9.43", \
" 9.12, 9.07, 9.19, 9.31, 9.35", \
" 9.11, 9.05, 9.16, 9.28, 9.33", \
" 9.18, 9.08, 9.16, 9.28, 9.34", \
" 9.41, 9.25, 9.26, 9.37, 9.43", \
" 9.89, 9.61, 9.53, 9.59, 9.65", \
" 10.71, 10.27, 10.06, 10.04, 10.08", \
" 11.99, 11.36, 10.97, 10.85, 10.84", \
" 14.02, 13.14, 12.52, 12.24, 12.16", \
" 17.22, 16.04, 15.08, 14.57, 14.36" ); }}
timing() { /* ring osc delay an2v4x2, path a to z 92.2 */
related_pin : "a" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 90.3 ; */
/* intrinsic_fall : 125.9 ; */
/* rise_resistance : 2.14 ; */
/* fall_resistance : 1.71 ; */
cell_rise(x2_260_6x10) { /* 50.0% of input to 50.0% of output */
values( " 77.0, 93.9, 131.1, 208.3, 343.7, 630.9", \
" 81.7, 98.5, 135.7, 212.9, 348.3, 635.5", \
" 84.9, 101.7, 138.9, 216.0, 351.5, 638.7", \
" 89.1, 105.8, 142.9, 220.1, 355.5, 642.7", \
" 95.1, 112.1, 149.3, 226.4, 361.8, 649.0", \
" 101.1, 118.4, 156.1, 233.3, 368.6, 655.8", \
" 106.6, 124.3, 162.5, 240.0, 375.2, 662.3", \
" 110.1, 128.4, 167.3, 244.9, 380.4, 667.3", \
" 109.3, 128.4, 168.8, 247.1, 382.4, 669.4", \
" 100.4, 120.7, 163.0, 243.3, 379.3, 666.3" ); }
rise_transition(x2_260_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 59.2, 92.2, 179.8, 383.3, 751.7, 1539.8", \
" 59.2, 92.3, 179.8, 383.3, 751.7, 1539.8", \
" 59.3, 92.4, 179.9, 383.3, 751.7, 1539.8", \
" 59.9, 92.8, 180.2, 383.4, 751.7, 1539.8", \
" 62.8, 95.2, 181.7, 383.9, 751.8, 1539.8", \
" 66.4, 99.1, 184.6, 385.6, 752.5, 1539.9", \
" 71.7, 104.1, 189.0, 388.2, 753.8, 1540.3", \
" 79.4, 111.7, 195.2, 392.3, 755.8, 1541.1", \
" 90.6, 122.9, 205.3, 399.3, 759.9, 1542.7", \
" 106.3, 138.9, 220.9, 412.0, 768.6, 1547.3" ); }
cell_fall(x2_260_6x10) { /* 50.0% of input to 50.0% of output */
values( " 96.7, 113.9, 147.4, 209.5, 314.3, 535.4", \
" 104.1, 121.2, 154.7, 216.9, 321.6, 542.8", \
" 110.2, 127.3, 160.8, 222.9, 327.7, 548.8", \
" 118.7, 135.8, 169.3, 231.4, 336.3, 557.4", \
" 134.3, 151.3, 184.7, 246.9, 351.7, 572.8", \
" 155.9, 173.1, 206.6, 268.7, 373.5, 594.6", \
" 183.7, 202.0, 236.8, 299.2, 403.9, 624.9", \
" 218.7, 238.1, 274.9, 338.6, 443.3, 664.1", \
" 265.0, 285.6, 324.9, 390.2, 495.4, 716.0", \
" 328.4, 350.4, 392.6, 460.4, 566.1, 786.9" ); }
fall_transition(x2_260_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 57.7, 82.0, 140.7, 274.8, 521.9, 1057.3", \
" 57.8, 82.1, 140.7, 274.8, 521.9, 1057.3", \
" 57.8, 82.1, 140.8, 274.8, 521.9, 1057.3", \
" 57.9, 82.3, 140.9, 274.8, 521.9, 1057.3", \
" 58.6, 83.0, 141.4, 275.1, 522.0, 1057.3", \
" 63.4, 86.8, 143.6, 276.0, 522.3, 1057.3", \
" 72.2, 95.5, 150.6, 279.8, 523.8, 1057.6", \
" 82.5, 106.1, 160.8, 286.8, 527.5, 1058.8", \
" 94.9, 119.0, 173.6, 296.7, 533.3, 1061.2", \
" 111.3, 135.7, 190.6, 310.4, 542.1, 1065.1" ); }}
timing() { /* ring osc delay an2v4x2, path b to z 85.8 */
related_pin : "b" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 90.6 ; */
/* intrinsic_fall : 115.9 ; */
/* rise_resistance : 2.14 ; */
/* fall_resistance : 1.70 ; */
cell_rise(x2_260_6x10) { /* 50.0% of input to 50.0% of output */
values( " 72.2, 89.0, 126.2, 203.4, 338.8, 626.0", \
" 78.4, 95.2, 132.3, 209.5, 345.0, 632.2", \
" 83.2, 99.9, 137.1, 214.3, 349.7, 637.0", \
" 89.5, 106.2, 143.2, 220.4, 355.8, 643.1", \
" 98.5, 115.3, 152.3, 229.3, 364.7, 652.0", \
" 107.1, 124.2, 161.7, 238.6, 373.9, 661.1", \
" 115.5, 132.9, 170.6, 247.9, 383.0, 670.0", \
" 122.5, 140.4, 178.7, 255.8, 391.1, 677.9", \
" 126.4, 145.3, 184.7, 262.1, 397.1, 684.0", \
" 124.1, 144.2, 185.7, 264.4, 399.5, 686.4" ); }
rise_transition(x2_260_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 59.3, 92.2, 179.8, 383.3, 751.7, 1539.8", \
" 59.3, 92.3, 179.9, 383.3, 751.7, 1539.8", \
" 59.4, 92.4, 179.9, 383.3, 751.7, 1539.8", \
" 60.0, 92.9, 180.3, 383.4, 751.7, 1539.8", \
" 63.4, 95.6, 181.9, 384.0, 751.9, 1539.8", \
" 68.0, 100.1, 185.2, 385.8, 752.5, 1539.9", \
" 74.4, 105.8, 189.9, 388.5, 754.0, 1540.4", \
" 83.3, 114.2, 196.1, 392.5, 755.9, 1541.4", \
" 95.9, 126.5, 206.5, 399.2, 759.7, 1542.9", \
" 113.5, 144.1, 222.8, 411.4, 767.6, 1546.8" ); }
cell_fall(x2_260_6x10) { /* 50.0% of input to 50.0% of output */
values( " 87.9, 104.4, 137.2, 198.9, 303.5, 524.5", \
" 95.2, 111.7, 144.4, 206.1, 310.8, 531.8", \
" 101.3, 117.7, 150.4, 212.2, 316.8, 537.8", \
" 109.8, 126.2, 158.9, 220.7, 325.3, 546.3", \
" 125.2, 141.4, 174.1, 235.9, 340.5, 561.6", \
" 145.7, 162.4, 195.3, 257.0, 361.6, 582.6", \
" 171.5, 189.2, 223.6, 285.7, 390.2, 611.1", \
" 204.0, 222.7, 258.9, 322.4, 426.9, 647.5", \
" 246.9, 266.8, 305.2, 370.3, 475.3, 695.7", \
" 304.7, 326.1, 367.5, 435.3, 541.0, 761.6" ); }
fall_transition(x2_260_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 54.1, 78.3, 137.6, 272.8, 520.7, 1056.6", \
" 54.1, 78.3, 137.6, 272.8, 520.7, 1056.6", \
" 54.2, 78.4, 137.7, 272.8, 520.7, 1056.6", \
" 54.3, 78.6, 137.8, 272.9, 520.7, 1056.6", \
" 55.7, 79.6, 138.5, 273.2, 520.8, 1056.6", \
" 61.6, 84.4, 141.5, 274.4, 521.3, 1056.7", \
" 70.3, 93.1, 148.7, 278.6, 523.0, 1057.0", \
" 80.4, 103.5, 158.6, 285.6, 526.8, 1058.3", \
" 93.5, 116.7, 171.5, 295.5, 532.6, 1060.6", \
" 111.1, 134.6, 189.5, 310.1, 542.3, 1064.9" ); }}
}
}
cell(an2v4x4) { /* 2008-01-06:07h21 */
area : 7 ; /* tracks */
cell_leakage_power : 1455 ; /* an2v4x4 */
cell_footprint : an2 ;
pin(a) { /* an2v4x4 FO4 effort 1.69 */
direction : input ;
capacitance : 3.33 ;
rise_capacitance : 3.47 ;
fall_capacitance : 3.18 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin a of an2v4x4 */
}
pin(b) { /* an2v4x4 FO4 effort 1.63 */
direction : input ;
capacitance : 3.15 ;
rise_capacitance : 3.19 ;
fall_capacitance : 3.10 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin b of an2v4x4 */
}
pin(z) {
direction : output ;
min_transition : 20 ;
min_capacitance : 4 ;
max_capacitance : 505 ;
max_fanout : 10 ;
function : "(a*b)" ;
internal_power(a_z_p) { /* an2v4x4 33.49 nW/MHz */
related_pin : "a" ;
power(pwr_x4_520_5x10) {
values( " 17.15, 16.82, 16.97, 17.16, 17.22", \
" 17.01, 16.67, 16.81, 17.00, 17.07", \
" 16.99, 16.63, 16.75, 16.95, 17.03", \
" 17.08, 16.67, 16.75, 16.95, 17.04", \
" 17.46, 16.93, 16.90, 17.07, 17.17", \
" 18.32, 17.57, 17.35, 17.44, 17.53", \
" 19.87, 18.78, 18.28, 18.23, 18.27", \
" 22.33, 20.83, 19.96, 19.68, 19.65", \
" 26.20, 24.21, 22.84, 22.26, 22.07", \
" 32.27, 29.68, 27.64, 26.60, 26.17" ); }}
internal_power(b_z_p) { /* an2v4x4 31.46 nW/MHz */
related_pin : "b" ;
power(pwr_x4_520_5x10) {
values( " 16.00, 15.76, 15.95, 16.14, 16.20", \
" 15.87, 15.61, 15.78, 15.99, 16.06", \
" 15.86, 15.57, 15.72, 15.94, 16.02", \
" 15.99, 15.63, 15.73, 15.94, 16.04", \
" 16.49, 15.98, 15.94, 16.10, 16.20", \
" 17.48, 16.71, 16.45, 16.52, 16.60", \
" 19.12, 17.98, 17.44, 17.34, 17.38", \
" 21.65, 20.06, 19.14, 18.82, 18.76", \
" 25.58, 23.45, 22.01, 21.36, 21.14", \
" 31.71, 28.93, 26.76, 25.63, 25.15" ); }}
timing() { /* ring osc delay an2v4x4, path a to z 86.2 */
related_pin : "a" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 90.1 ; */
/* intrinsic_fall : 119.8 ; */
/* rise_resistance : 1.07 ; */
/* fall_resistance : 0.85 ; */
cell_rise(x4_520_6x10) { /* 50.0% of input to 50.0% of output */
values( " 75.7, 93.4, 131.2, 208.5, 343.9, 631.1", \
" 80.4, 98.0, 135.8, 213.1, 348.5, 635.7", \
" 83.6, 101.2, 138.9, 216.3, 351.7, 638.9", \
" 87.9, 105.4, 143.1, 220.4, 355.8, 643.0", \
" 94.2, 111.9, 149.7, 226.9, 362.3, 649.5", \
" 100.6, 118.7, 157.0, 234.3, 369.6, 656.8", \
" 106.9, 125.4, 164.2, 241.8, 377.0, 664.1", \
" 111.5, 130.6, 170.3, 248.1, 383.4, 670.3", \
" 112.5, 132.5, 173.6, 252.3, 387.4, 674.3", \
" 106.3, 127.5, 170.8, 251.4, 387.4, 674.2" ); }
rise_transition(x4_520_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 54.7, 88.3, 175.6, 378.5, 746.5, 1534.4", \
" 54.8, 88.3, 175.7, 378.5, 746.5, 1534.4", \
" 54.8, 88.4, 175.7, 378.6, 746.5, 1534.4", \
" 55.3, 88.8, 176.0, 378.6, 746.6, 1534.4", \
" 58.1, 91.1, 177.4, 379.1, 746.7, 1534.5", \
" 61.7, 94.9, 180.4, 380.8, 747.3, 1534.5", \
" 66.9, 100.1, 184.9, 383.4, 748.6, 1534.9", \
" 74.5, 107.6, 191.2, 387.6, 750.6, 1535.7", \
" 85.7, 118.8, 201.4, 394.8, 754.8, 1537.3", \
" 101.6, 134.6, 217.0, 407.7, 763.6, 1541.8" ); }
cell_fall(x4_520_6x10) { /* 50.0% of input to 50.0% of output */
values( " 89.6, 107.4, 141.1, 203.1, 307.8, 528.9", \
" 97.2, 115.0, 148.6, 210.6, 315.3, 536.4", \
" 103.3, 121.1, 154.8, 216.8, 321.5, 542.6", \
" 111.9, 129.6, 163.3, 225.3, 330.0, 551.1", \
" 127.4, 145.0, 178.7, 240.7, 345.4, 566.5", \
" 148.6, 166.5, 200.2, 262.3, 366.9, 588.0", \
" 175.4, 194.4, 229.7, 292.0, 396.6, 617.6", \
" 209.0, 229.2, 266.6, 330.3, 434.8, 655.6", \
" 253.4, 274.9, 314.8, 380.1, 485.2, 705.7", \
" 313.8, 336.8, 379.8, 447.8, 553.3, 773.9" ); }
fall_transition(x4_520_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 52.2, 76.9, 135.6, 269.7, 517.1, 1052.7", \
" 52.2, 76.9, 135.6, 269.7, 517.1, 1052.7", \
" 52.2, 77.0, 135.6, 269.7, 517.1, 1052.7", \
" 52.3, 77.1, 135.8, 269.8, 517.1, 1052.7", \
" 53.2, 77.9, 136.3, 270.0, 517.2, 1052.8", \
" 58.6, 82.2, 138.9, 271.1, 517.5, 1052.8", \
" 67.4, 91.0, 146.0, 275.0, 519.1, 1053.1", \
" 77.5, 101.6, 156.3, 282.0, 522.7, 1054.3", \
" 90.1, 114.5, 169.2, 291.9, 528.4, 1056.5", \
" 106.7, 131.4, 186.5, 305.8, 537.3, 1060.4" ); }}
timing() { /* ring osc delay an2v4x4, path b to z 80.8 */
related_pin : "b" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 91.2 ; */
/* intrinsic_fall : 111.4 ; */
/* rise_resistance : 1.07 ; */
/* fall_resistance : 0.85 ; */
cell_rise(x4_520_6x10) { /* 50.0% of input to 50.0% of output */
values( " 71.6, 89.2, 127.0, 204.3, 339.7, 626.9", \
" 77.7, 95.3, 133.1, 210.4, 345.8, 633.0", \
" 82.6, 100.1, 137.8, 215.2, 350.6, 637.8", \
" 89.0, 106.5, 144.1, 221.4, 356.8, 644.1", \
" 98.5, 116.1, 153.6, 230.8, 366.1, 653.4", \
" 107.8, 125.7, 163.7, 240.8, 376.0, 663.2", \
" 117.1, 135.3, 173.7, 251.1, 386.2, 673.2", \
" 125.4, 144.2, 183.2, 260.5, 395.8, 682.5", \
" 131.4, 151.1, 191.4, 269.0, 403.9, 690.8", \
" 132.1, 153.2, 195.6, 274.6, 409.6, 696.4" ); }
rise_transition(x4_520_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 54.7, 88.3, 175.7, 378.5, 746.5, 1534.4", \
" 54.7, 88.3, 175.7, 378.5, 746.5, 1534.4", \
" 54.8, 88.4, 175.8, 378.6, 746.5, 1534.4", \
" 55.2, 88.9, 176.1, 378.7, 746.6, 1534.4", \
" 58.7, 91.5, 177.6, 379.2, 746.7, 1534.5", \
" 63.3, 96.1, 181.0, 381.0, 747.3, 1534.5", \
" 69.8, 102.0, 185.9, 383.9, 748.8, 1535.0", \
" 78.9, 110.4, 192.3, 388.0, 750.9, 1536.0", \
" 91.6, 122.8, 202.8, 394.9, 754.7, 1537.5", \
" 109.4, 140.3, 219.2, 407.2, 762.6, 1541.4" ); }
cell_fall(x4_520_6x10) { /* 50.0% of input to 50.0% of output */
values( " 82.5, 99.6, 132.6, 194.2, 298.8, 519.7", \
" 89.9, 107.0, 140.0, 201.6, 306.1, 527.1", \
" 96.0, 113.1, 146.0, 207.6, 312.2, 533.2", \
" 104.6, 121.5, 154.5, 216.1, 320.7, 541.7", \
" 119.8, 136.7, 169.6, 231.2, 335.8, 556.8", \
" 139.8, 157.2, 190.4, 252.1, 356.6, 577.6", \
" 164.7, 183.2, 218.0, 280.1, 384.5, 605.4", \
" 195.9, 215.5, 252.2, 315.7, 420.2, 640.7", \
" 236.9, 257.7, 296.8, 362.0, 466.9, 687.2", \
" 291.8, 314.1, 356.4, 424.4, 530.0, 750.5" ); }
fall_transition(x4_520_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 49.0, 73.5, 132.8, 268.0, 516.0, 1052.1", \
" 49.0, 73.5, 132.8, 268.0, 516.0, 1052.1", \
" 49.0, 73.6, 132.9, 268.0, 516.0, 1052.1", \
" 49.2, 73.8, 133.0, 268.1, 516.1, 1052.1", \
" 50.9, 75.0, 133.7, 268.4, 516.2, 1052.2", \
" 57.1, 80.2, 137.1, 269.7, 516.6, 1052.2", \
" 65.7, 89.0, 144.4, 274.1, 518.4, 1052.5", \
" 76.0, 99.4, 154.4, 281.0, 522.2, 1053.8", \
" 89.2, 112.7, 167.5, 291.0, 528.0, 1056.1", \
" 107.1, 130.9, 186.0, 305.9, 537.8, 1060.4" ); }}
}
}
cell(an2v4x8) { /* 2008-01-06:07h21 */
area : 10 ; /* tracks */
cell_leakage_power : 2680 ; /* an2v4x8 */
cell_footprint : an2 ;
pin(a) { /* an2v4x8 FO4 effort 1.65 */
direction : input ;
capacitance : 5.98 ;
rise_capacitance : 6.23 ;
fall_capacitance : 5.72 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin a of an2v4x8 */
}
pin(b) { /* an2v4x8 FO4 effort 1.59 */
direction : input ;
capacitance : 5.61 ;
rise_capacitance : 5.68 ;
fall_capacitance : 5.53 ;
fanout_load : 1 ;
max_transition : 1500.0 ; /* pin b of an2v4x8 */
}
pin(z) {
direction : output ;
min_transition : 20 ;
min_capacitance : 8 ;
max_capacitance : 929 ;
max_fanout : 20 ;
function : "(a*b)" ;
internal_power(a_z_p) { /* an2v4x8 59.72 nW/MHz */
related_pin : "a" ;
power(pwr_x8_1040_5x10) {
values( " 30.37, 29.90, 30.25, 30.58, 30.66", \
" 30.13, 29.63, 29.96, 30.31, 30.40", \
" 30.10, 29.55, 29.86, 30.22, 30.34", \
" 30.29, 29.63, 29.86, 30.23, 30.36", \
" 31.00, 30.11, 30.14, 30.47, 30.62", \
" 32.56, 31.26, 30.95, 31.15, 31.30", \
" 35.38, 33.44, 32.64, 32.59, 32.68", \
" 39.85, 37.11, 35.66, 35.24, 35.20", \
" 46.90, 43.21, 40.87, 39.91, 39.62", \
" 57.93, 53.09, 49.52, 47.76, 47.07" ); }}
internal_power(b_z_p) { /* an2v4x8 56.00 nW/MHz */
related_pin : "b" ;
power(pwr_x8_1040_5x10) {
values( " 28.27, 27.97, 28.38, 28.72, 28.80", \
" 28.04, 27.68, 28.08, 28.44, 28.54", \
" 28.04, 27.62, 27.98, 28.36, 28.49", \
" 28.30, 27.75, 28.00, 28.39, 28.54", \
" 29.23, 28.37, 28.38, 28.69, 28.85", \
" 31.01, 29.67, 29.30, 29.46, 29.60", \
" 33.99, 31.95, 31.07, 30.97, 31.04", \
" 38.58, 35.69, 34.14, 33.64, 33.56", \
" 45.74, 41.80, 39.32, 38.26, 37.92", \
" 56.88, 51.67, 47.88, 45.98, 45.20" ); }}
timing() { /* ring osc delay an2v4x8, path a to z 83.9 */
related_pin : "a" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 87.2 ; */
/* intrinsic_fall : 118.3 ; */
/* rise_resistance : 0.58 ; */
/* fall_resistance : 0.46 ; */
cell_rise(x8_1040_6x10) { /* 50.0% of input to 50.0% of output */
values( " 73.6, 92.2, 132.5, 216.1, 363.3, 675.5", \
" 78.2, 96.8, 137.1, 220.8, 368.0, 680.2", \
" 81.4, 100.0, 140.2, 223.9, 371.1, 683.4", \
" 85.7, 104.2, 144.3, 228.0, 375.2, 687.5", \
" 91.8, 110.6, 150.8, 234.4, 381.5, 693.8", \
" 97.9, 117.1, 157.8, 241.4, 388.5, 700.7", \
" 103.7, 123.3, 164.5, 248.4, 395.3, 707.5", \
" 107.7, 128.0, 170.1, 254.0, 401.0, 713.0", \
" 107.9, 129.1, 172.6, 257.3, 404.2, 716.1", \
" 100.6, 123.1, 168.8, 255.4, 403.0, 714.9" ); }
rise_transition(x8_1040_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 54.7, 90.9, 186.2, 407.8, 808.9, 1666.1", \
" 54.8, 90.9, 186.2, 407.8, 808.9, 1666.1", \
" 54.9, 91.0, 186.3, 407.9, 808.9, 1666.1", \
" 55.5, 91.5, 186.5, 407.9, 808.9, 1666.1", \
" 58.3, 93.9, 188.0, 408.4, 809.0, 1666.2", \
" 62.0, 97.7, 190.8, 409.9, 809.5, 1666.2", \
" 67.3, 102.8, 195.1, 412.3, 810.6, 1666.5", \
" 75.0, 110.5, 201.2, 416.1, 812.4, 1667.2", \
" 86.4, 121.7, 211.3, 423.0, 816.2, 1668.6", \
" 102.3, 137.7, 226.9, 435.5, 824.6, 1672.7" ); }
cell_fall(x8_1040_6x10) { /* 50.0% of input to 50.0% of output */
values( " 88.6, 107.4, 143.0, 210.1, 324.9, 567.5", \
" 96.1, 114.9, 150.6, 217.7, 332.4, 575.1", \
" 102.3, 121.1, 156.7, 223.8, 338.6, 581.3", \
" 111.0, 129.7, 165.3, 232.4, 347.2, 589.9", \
" 126.5, 145.1, 180.7, 247.8, 362.6, 605.3", \
" 147.6, 166.5, 202.3, 269.4, 384.1, 626.8", \
" 174.3, 194.5, 231.7, 299.0, 413.6, 656.2", \
" 207.9, 229.4, 268.6, 337.1, 451.5, 693.9", \
" 252.5, 275.3, 317.0, 386.9, 501.7, 743.7", \
" 313.2, 337.6, 382.5, 454.7, 569.7, 811.9" ); }
fall_transition(x8_1040_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 52.5, 79.1, 143.3, 291.5, 564.4, 1153.7", \
" 52.6, 79.1, 143.3, 291.5, 564.4, 1153.7", \
" 52.6, 79.2, 143.3, 291.5, 564.4, 1153.7", \
" 52.7, 79.4, 143.4, 291.6, 564.4, 1153.7", \
" 53.7, 80.2, 144.0, 291.8, 564.5, 1153.7", \
" 59.2, 84.5, 146.5, 292.7, 564.8, 1153.7", \
" 67.9, 93.3, 153.3, 296.3, 566.1, 1153.9", \
" 78.1, 103.8, 163.2, 302.7, 569.2, 1154.8", \
" 90.5, 116.7, 175.7, 311.8, 574.1, 1156.7", \
" 107.1, 133.6, 192.8, 324.8, 582.0, 1159.9" ); }}
timing() { /* ring osc delay an2v4x8, path b to z 78.4 */
related_pin : "b" ;
timing_sense : positive_unate ;
/* intrinsic_rise : 88.2 ; */
/* intrinsic_fall : 109.7 ; */
/* rise_resistance : 0.58 ; */
/* fall_resistance : 0.46 ; */
cell_rise(x8_1040_6x10) { /* 50.0% of input to 50.0% of output */
values( " 69.4, 88.0, 128.3, 212.0, 359.1, 671.4", \
" 75.6, 94.1, 134.4, 218.1, 365.2, 677.5", \
" 80.4, 98.9, 139.1, 222.8, 370.0, 682.3", \
" 86.8, 105.2, 145.3, 229.0, 376.2, 688.5", \
" 95.9, 114.4, 154.4, 238.0, 385.1, 697.4", \
" 104.7, 123.5, 164.0, 247.4, 394.5, 706.7", \
" 113.4, 132.6, 173.4, 257.1, 403.9, 716.0", \
" 121.0, 140.9, 182.2, 265.7, 412.7, 724.5", \
" 126.0, 146.9, 189.5, 273.1, 419.9, 731.7", \
" 125.5, 147.8, 192.5, 277.5, 424.3, 736.2" ); }
rise_transition(x8_1040_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 54.8, 90.9, 186.2, 407.8, 808.9, 1666.1", \
" 54.7, 90.9, 186.3, 407.9, 808.9, 1666.1", \
" 54.8, 91.1, 186.3, 407.9, 808.9, 1666.1", \
" 55.5, 91.6, 186.6, 408.0, 808.9, 1666.1", \
" 59.0, 94.3, 188.2, 408.5, 809.0, 1666.2", \
" 63.7, 98.8, 191.4, 410.2, 809.5, 1666.2", \
" 70.2, 104.6, 196.0, 412.7, 810.9, 1666.5", \
" 79.3, 113.0, 202.2, 416.5, 812.7, 1667.5", \
" 92.0, 125.4, 212.4, 422.9, 816.1, 1668.9", \
" 109.9, 143.0, 228.6, 434.7, 823.5, 1672.4" ); }
cell_fall(x8_1040_6x10) { /* 50.0% of input to 50.0% of output */
values( " 81.3, 99.3, 134.3, 201.0, 315.6, 558.2", \
" 88.7, 106.7, 141.7, 208.4, 323.0, 565.6", \
" 94.8, 112.8, 147.7, 214.5, 329.1, 571.7", \
" 103.4, 121.3, 156.2, 223.0, 337.6, 580.2", \
" 118.6, 136.5, 171.4, 238.2, 352.8, 595.4", \
" 138.5, 156.9, 192.1, 258.9, 373.4, 616.0", \
" 163.3, 182.8, 219.6, 286.7, 401.1, 643.5", \
" 194.5, 215.2, 253.8, 322.0, 436.4, 678.6", \
" 235.5, 257.5, 298.5, 368.2, 482.9, 724.8", \
" 290.6, 314.2, 358.5, 430.8, 545.9, 787.9" ); }
fall_transition(x8_1040_6x10) { /* 10%-90%, scaled to 0%-100% */
values( " 49.3, 75.7, 140.5, 289.9, 563.4, 1153.1", \
" 49.3, 75.7, 140.6, 289.9, 563.4, 1153.1", \
" 49.4, 75.8, 140.6, 289.9, 563.4, 1153.1", \
" 49.6, 76.0, 140.8, 290.0, 563.5, 1153.1", \
" 51.4, 77.3, 141.5, 290.2, 563.5, 1153.1", \
" 57.7, 82.6, 144.7, 291.5, 563.9, 1153.2", \
" 66.2, 91.2, 151.8, 295.4, 565.5, 1153.4", \
" 76.5, 101.6, 161.4, 301.7, 568.7, 1154.4", \
" 89.6, 114.9, 174.1, 311.0, 573.8, 1156.3", \
" 107.5, 133.0, 192.3, 325.0, 582.6, 1159.9" ); }}
}
}
cell(an3v0x05) { /* 2008-01-06:07h21 *
gitextract_ej50xux_/
├── .github/
│ └── workflows/
│ └── ci.yaml
├── .gitignore
├── LICENSE
├── README.md
├── doc/
│ ├── specification.rst
│ └── testplan.rst
├── flow.sh
├── rtl/
│ ├── async_bidir_fifo.list
│ ├── async_bidir_fifo.v
│ ├── async_bidir_ramif_fifo.list
│ ├── async_bidir_ramif_fifo.v
│ ├── async_fifo.list
│ ├── async_fifo.v
│ ├── fifomem.v
│ ├── fifomem_dp.v
│ ├── rptr_empty.v
│ ├── sync_ptr.v
│ ├── sync_r2w.v
│ ├── sync_w2r.v
│ └── wptr_full.v
├── script/
│ └── setup.sh
├── sim/
│ ├── Makefile
│ ├── async_fifo_unit_test.sv
│ ├── files.f
│ ├── svut_h.sv
│ └── wave.gtkw
└── syn/
├── cmos.lib
├── fifo.ys
├── syn_asic.sh
└── vsclib013.lib
Condensed preview — 30 files, each showing path, character count, and a content snippet. Download the .json file or copy for the full structured content (5,667K chars).
[
{
"path": ".github/workflows/ci.yaml",
"chars": 509,
"preview": "name: Async_FIFO\non: [push]\njobs:\n Lint:\n runs-on: macos-latest\n steps:\n - uses: actions/checkout@v2\n -"
},
{
"path": ".gitignore",
"chars": 79,
"preview": "*.out\n*.vcd\n*.lxt\n.DS_Store\ntags\nlint.log script src\nasync_fifo_syn.v\nlint.log\n"
},
{
"path": "LICENSE",
"chars": 1072,
"preview": "The MIT License\n\n\nPermission is hereby granted, free of charge, to any person obtaining a copy of this software and\nasso"
},
{
"path": "README.md",
"chars": 3198,
"preview": "# Asynchronous dual clock FIFO\n\n![CI](https://github.com/dpretet/async_fifo/actions/workflows/ci.yaml/badge.svg?branch=m"
},
{
"path": "doc/specification.rst",
"chars": 1805,
"preview": "Specification\n=============\n\n* The module is a full synchronized module, working on clock rising edge.\n\n* It can be put "
},
{
"path": "doc/testplan.rst",
"chars": 1611,
"preview": "Testplan\n========\n\nThis document describes the faetures to test,\nand the general scenarios to put in place to stress\nthe"
},
{
"path": "flow.sh",
"chars": 2990,
"preview": "#!/usr/bin/env bash\n\n# -e: exit if one command fails\n# -u: treat unset variable as an error\n# -f: disable filename expan"
},
{
"path": "rtl/async_bidir_fifo.list",
"chars": 100,
"preview": "async_bidir_fifo.v\nfifomem.v\nfifomem_dp.v\nrptr_empty.v\nsync_ptr.v\nsync_r2w.v\nsync_w2r.v\nwptr_full.v\n"
},
{
"path": "rtl/async_bidir_fifo.v",
"chars": 5398,
"preview": "//-----------------------------------------------------------------------------\n// Copyright 2017 Damien Pretet ThotIP\n/"
},
{
"path": "rtl/async_bidir_ramif_fifo.list",
"chars": 106,
"preview": "async_bidir_ramif_fifo.v\nfifomem.v\nfifomem_dp.v\nrptr_empty.v\nsync_ptr.v\nsync_r2w.v\nsync_w2r.v\nwptr_full.v\n"
},
{
"path": "rtl/async_bidir_ramif_fifo.v",
"chars": 6071,
"preview": "//-----------------------------------------------------------------------------\n// Copyright 2017 Damien Pretet ThotIP\n/"
},
{
"path": "rtl/async_fifo.list",
"chars": 103,
"preview": "async_fifo.v\nfifomem.v\nfifomem_dp.v\nhdl.list\nrptr_empty.v\nsync_ptr.v\nsync_r2w.v\nsync_w2r.v\nwptr_full.v\n"
},
{
"path": "rtl/async_fifo.v",
"chars": 2172,
"preview": "// distributed under the mit license\n// https://opensource.org/licenses/mit-license.php\n\n`timescale 1 ns / 1 ps\n`default"
},
{
"path": "rtl/fifomem.v",
"chars": 1347,
"preview": "// distributed under the mit license\n// https://opensource.org/licenses/mit-license.php\n\n`timescale 1 ns / 1 ps\n`default"
},
{
"path": "rtl/fifomem_dp.v",
"chars": 2839,
"preview": "//-----------------------------------------------------------------------------\n// Copyright 2017 Damien Pretet ThotIP\n/"
},
{
"path": "rtl/rptr_empty.v",
"chars": 1789,
"preview": "// distributed under the mit license\n// https://opensource.org/licenses/mit-license.php\n\n`timescale 1 ns / 1 ps\n`default"
},
{
"path": "rtl/sync_ptr.v",
"chars": 586,
"preview": "// distributed under the mit license\n// https://opensource.org/licenses/mit-license.php\n\n`timescale 1 ns / 1 ps\n`default"
},
{
"path": "rtl/sync_r2w.v",
"chars": 573,
"preview": "// distributed under the mit license\n// https://opensource.org/licenses/mit-license.php\n\n`timescale 1 ns / 1 ps\n`default"
},
{
"path": "rtl/sync_w2r.v",
"chars": 573,
"preview": "// distributed under the mit license\n// https://opensource.org/licenses/mit-license.php\n\n`timescale 1 ns / 1 ps\n`default"
},
{
"path": "rtl/wptr_full.v",
"chars": 1939,
"preview": "// distributed under the mit license\n// https://opensource.org/licenses/mit-license.php\n\n`timescale 1 ns / 1 ps\n`default"
},
{
"path": "script/setup.sh",
"chars": 662,
"preview": "#!/usr/bin/env bash\n\n# get current script path (applicable even if is a symlink)\nSOURCE=\"${BASH_SOURCE[0]}\"\nwhile [ -h \""
},
{
"path": "sim/Makefile",
"chars": 250,
"preview": "test:\n\t@svutRun -f files.f -define \"AFULL=1;AEMPTY=1\"\n\t@svutRun -f files.f -define \"AFULL=3;AEMPTY=2\"\n\ntest-dry-run:\n\t@s"
},
{
"path": "sim/async_fifo_unit_test.sv",
"chars": 4962,
"preview": "`include \"svut_h.sv\"\n`timescale 1 ns / 1 ps\n\nmodule async_fifo_unit_test;\n\n `SVUT_SETUP\n\n `ifndef AEMPTY\n `defi"
},
{
"path": "sim/files.f",
"chars": 112,
"preview": "../rtl/async_fifo.v\n../rtl/fifomem.v\n../rtl/rptr_empty.v\n../rtl/sync_r2w.v\n../rtl/sync_w2r.v\n../rtl/wptr_full.v\n"
},
{
"path": "sim/svut_h.sv",
"chars": 7413,
"preview": "/// Copyright 2021 The SVUT Authors\n///\n/// Permission is hereby granted, free of charge, to any person obtaining a copy"
},
{
"path": "sim/wave.gtkw",
"chars": 1990,
"preview": "[*]\n[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI\n[*] Sat Mar 30 09:48:17 2024\n[*]\n[dumpfile] \"/Users/damien/workspace/hd"
},
{
"path": "syn/cmos.lib",
"chars": 1320,
"preview": "// test comment\n/* test comment */\nlibrary(demo) {\n cell(BUF) {\n area: 6;\n pin(A) { direction: input; }\n pin(Y"
},
{
"path": "syn/fifo.ys",
"chars": 676,
"preview": "# read design modules\nread -sv2012 ../rtl/async_fifo.v\nread -sv2012 ../rtl/fifomem.v\nread -sv2012 ../rtl/rptr_empty.v\nre"
},
{
"path": "syn/syn_asic.sh",
"chars": 498,
"preview": "#!/usr/bin/env bash\n\n# -e: exit if one command fails\n# -o pipefail: causes a pipeline to fail if any command fails\nset -"
},
{
"path": "syn/vsclib013.lib",
"chars": 5307374,
"preview": "library (vsclib013) { /* Post layout timing */\ntechnology (cmos) ;\n/* choose one delay_model */\n/* delay_model : ge"
}
]
About this extraction
This page contains the full source code of the dpretet/async_fifo GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 30 files (5.1 MB), approximately 1.3M tokens. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.