[ { "path": ".gitignore", "content": "bin/knockles\n.output/\n.vscode/\n" }, { "path": ".gitmodules", "content": "[submodule \"libbpf\"]\n\tpath = libbpf\n\turl = https://github.com/libbpf/libbpf/\n" }, { "path": "LICENSE", "content": " Apache License\n Version 2.0, January 2004\n http://www.apache.org/licenses/\n\n TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION\n\n 1. Definitions.\n\n \"License\" shall mean the terms and conditions for use, reproduction,\n and distribution as defined by Sections 1 through 9 of this document.\n\n \"Licensor\" shall mean the copyright owner or entity authorized by\n the copyright owner that is granting the License.\n\n \"Legal Entity\" shall mean the union of the acting entity and all\n other entities that control, are controlled by, or are under common\n control with that entity. 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Unless required by applicable law or\n agreed to in writing, Licensor provides the Work (and each\n Contributor provides its Contributions) on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or\n implied, including, without limitation, any warranties or conditions\n of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A\n PARTICULAR PURPOSE. You are solely responsible for determining the\n appropriateness of using or redistributing the Work and assume any\n risks associated with Your exercise of permissions under this License.\n\n 8. Limitation of Liability. In no event and under no legal theory,\n whether in tort (including negligence), contract, or otherwise,\n unless required by applicable law (such as deliberate and grossly\n negligent acts) or agreed to in writing, shall any Contributor be\n liable to You for damages, including any direct, indirect, special,\n incidental, or consequential damages of any character arising as a\n result of this License or out of the use or inability to use the\n Work (including but not limited to damages for loss of goodwill,\n work stoppage, computer failure or malfunction, or any and all\n other commercial damages or losses), even if such Contributor\n has been advised of the possibility of such damages.\n\n 9. Accepting Warranty or Additional Liability. While redistributing\n the Work or Derivative Works thereof, You may choose to offer,\n and charge a fee for, acceptance of support, warranty, indemnity,\n or other liability obligations and/or rights consistent with this\n License. However, in accepting such obligations, You may act only\n on Your own behalf and on Your sole responsibility, not on behalf\n of any other Contributor, and only if You agree to indemnify,\n defend, and hold each Contributor harmless for any liability\n incurred by, or claims asserted against, such Contributor by reason\n of your accepting any such warranty or additional liability.\n\n END OF TERMS AND CONDITIONS\n" }, { "path": "README.md", "content": "> **Warning**\n> This git repository was meant to be a small (and fun) demonstration of what can be done with eBPF. It was clearly over-engineered as it was not developped nor optimized for any kind of use.\n\n# Knockles - eBPF Port Knocking Tool 🚪🐝\n\nKnockles, is a port knocking tool based on [eBPF](https://ebpf.io/what-is-ebpf) 🐝.\nIt allows to remotely open a TCP connection while being completely invisible to port scanners.\n\n- A single SYN request is sent on an opened || closed port 📨 📫\n- It carries an OTP for authentication so you can be the only one to open a port 🔐 \n- Once authentified, a random (HMAC based) port is opened for a TCP connection 🎲\n- Then, the port is closed as soon as a connection has been established 🚪\n\n## Server configuration\n\n> Modify the following macros/variables\n\n```\n./knockles/src/knockles.bpf.c\n```\n- `PORT`: Port monitored for knocks *[default: `80`]*\n\n```\n./knockles/src/knockles.c\n```\n- `HMAC_DURATION`: Time range between two different OTP (in seconds) *[default: `30`]*\n- `LISTENING_DURATION`: Timeout of the opened port if no connection occurs (in seconds) *[default: `30`]*\n- `SECRET`: HMAC secret key *[default: `MY_SECRET_KEY`]*\n\n## Server compilation\n\n### Requirements\n\n#### Debian\n\n```bash\nsudo apt install git make pkg-config libelf-dev clang-11 libc6-dev-i386 bpftool libssl-dev -y\npip install scapy\n```\n\n#### Ubuntu\n\n```bash\nsudo apt install git make pkg-config libelf-dev clang-11 libc6-dev-i386 linux-tools-common linux-tools-$(uname -r) libssl-dev -y\npip install scapy\n```\n\n### Build\n\n```bash\ncd ./knockles/src\nmake\n```\n\n## Usage\n\n### Server side\n\n```text\nUsage: ./knockles [OPTION]...\neBPF port knocking tool - Server.\n --help display this help and exit\n --daemon run program as daemon\n```\n\n### Client side\n\n```text\nusage: knuckknock.py [-h] -s KEY -t TIME -d IP -p PORT\n\neBPF port knocking tool - Client.\n\noptional arguments:\n -h, --help show this help message and exit\n -s KEY , --secret KEY \n HMAC secret key\n -t TIME, --time TIME generated HMAC duration\n -d IP, --dst IP destination IP address\n -p PORT, --port PORT monitored port\n```\n" }, { "path": "src/Makefile", "content": "# SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause)\nOUTPUT := .output\nCLANG ?= clang-11\nLLVM_STRIP ?= llvm-strip-11\nBPFTOOL ?= /usr/sbin/bpftool\nLIBBPF_SRC := $(abspath ../libbpf/src)\nLIBBPF_OBJ := $(abspath $(OUTPUT)/libbpf.a)\nINCLUDES := -I$(OUTPUT)\nCFLAGS := -g -Wall\nARCH := $(shell uname -m | sed 's/x86_64/x86/')\nAPPS = knockles\n\n# Get Clang's default includes on this system. We'll explicitly add these dirs\n# to the includes list when compiling with `-target bpf` because otherwise some\n# architecture-specific dirs will be \"missing\" on some architectures/distros -\n# headers such as asm/types.h, asm/byteorder.h, asm/socket.h, asm/sockios.h,\n# sys/cdefs.h etc. might be missing.\n#\n# Use '-idirafter': Don't interfere with include mechanics except where the\n# build would have failed anyways.\nCLANG_BPF_SYS_INCLUDES = $(shell $(CLANG) -v -E - &1 \\\n\t| sed -n '/<...> search starts here:/,/End of search list./{ s| \\(/.*\\)|-idirafter \\1|p }')\n\nifeq ($(V),1)\n\tQ =\n\tmsg =\nelse\n\tQ = @\n\tmsg = @printf ' %-8s %s%s\\n'\t\t\t\t\t\\\n\t\t \"$(1)\"\t\t\t\t\t\t\\\n\t\t \"$(patsubst $(abspath $(OUTPUT))/%,%,$(2))\"\t\\\n\t\t \"$(if $(3), $(3))\";\n\tMAKEFLAGS += --no-print-directory\nendif\n\n.PHONY: all\nall: $(APPS)\n\n.PHONY: clean\nclean:\n\t$(call msg,CLEAN)\n\t$(Q)rm -rf $(OUTPUT) $(APPS)\n\t$(Q)cd bin && rm -f $(APPS) $(HELPERS)\n\n$(OUTPUT) $(OUTPUT)/libbpf:\n\t$(call msg,MKDIR,$@)\n\t$(Q)mkdir -p $@\n\n# Build libbpf\n$(LIBBPF_OBJ): $(wildcard $(LIBBPF_SRC)/*.[ch] $(LIBBPF_SRC)/Makefile) | $(OUTPUT)/libbpf\n\t$(call msg,LIB,$@)\n\t$(Q)$(MAKE) -C $(LIBBPF_SRC) BUILD_STATIC_ONLY=1\t\t \\\n\t\t OBJDIR=$(dir $@)/libbpf DESTDIR=$(dir $@)\t\t \\\n\t\t INCLUDEDIR= LIBDIR= UAPIDIR=\t\t\t \\\n\t\t install\n\n# Build BPF code\n$(OUTPUT)/%.bpf.o: %.bpf.c $(LIBBPF_OBJ) $(wildcard %.h) vmlinux.h | $(OUTPUT)\n\t$(call msg,BPF,$@)\n\t$(Q)$(CLANG) -g -O2 -target bpf -D__TARGET_ARCH_$(ARCH) $(INCLUDES) $(CLANG_BPF_SYS_INCLUDES) -c $(filter %.c,$^) -o $@\n\t$(Q)$(LLVM_STRIP) -g $@ # strip useless DWARF info\n\n# Generate BPF skeletons\n$(OUTPUT)/%.skel.h: $(OUTPUT)/%.bpf.o | $(OUTPUT)\n\t$(call msg,GEN-SKEL,$@)\n\t$(Q)$(BPFTOOL) gen skeleton $< > $@\n\n# Build user-space code\n$(patsubst %,$(OUTPUT)/%.o,$(APPS)): %.o: %.skel.h\n\n$(OUTPUT)/%.o: %.c $(wildcard %.h) | $(OUTPUT)\n\t$(call msg,CC,$@)\n\t$(Q)$(CC) $(CFLAGS) $(INCLUDES) -c $(filter %.c,$^) -o $@\n\n# Build application binary\n$(APPS): %: $(OUTPUT)/%.o $(LIBBPF_OBJ) | $(OUTPUT)\n\t$(call msg,BINARY,$@)\n\t$(Q)$(CC) $(CFLAGS) $^ -l:libz.a -l:libelf.a -l:libcrypto.a -l:libdl.a -Wl,--whole-archive -lpthread -Wl,--no-whole-archive --static -o bin/$@ \n\n# Build helpers\n$(HELPERS):\n\t$(call msg,BINARY,$@)\n\t$(Q)$(CC) $(CFLAGS) $@.c -o bin/$@\n\n# delete failed targets\n.DELETE_ON_ERROR:\n\n# keep intermediate (.skel.h, .bpf.o, etc) targets\n.SECONDARY:\n\n" }, { "path": "src/bin/.gitkeep", "content": "" }, { "path": "src/knockles.bpf.c", "content": "#include \"vmlinux.h\"\n#include \"knockles_event.h\"\n#include \n#include \n#include \n#define PORT 80\n\nchar LICENSE[] SEC(\"license\") = \"Dual BSD/GPL\";\n\n/****************************************************/\n/*!\n * \\brief Ring buffer map use to send event\n * to the userland program\n */\nstruct {\n __uint(type, BPF_MAP_TYPE_RINGBUF);\n __uint(max_entries, 1);\n} rb SEC(\".maps\");\n\nstruct netif_receive_skb_format{\n unsigned long long h;\n void *skbaddr;\n unsigned int len;\n};\n\nSEC(\"tp/net/netif_receive_skb\")\nint trace_net_netif_receive_skb(struct netif_receive_skb_format *ctx){\n struct sk_buff *skb = ctx->skbaddr;\n unsigned char *head;\n u16 transport_header, dst;\n struct tcphdr tcp_hdr;\n \n bpf_probe_read(&head, sizeof(unsigned char *), &skb->head);\n bpf_probe_read(&transport_header, sizeof(u16), &skb->transport_header);\n bpf_probe_read(&tcp_hdr, sizeof(tcp_hdr), (struct tcphdr *)(head+transport_header));\n dst = ((tcp_hdr.dest & 0xff) << 8) | (tcp_hdr.dest >> 8);\n if(dst != PORT) return 0;\n if(tcp_hdr.syn != 1) return 0;\n \n u16 network_header;\n struct iphdr ip_hdr;\n bpf_probe_read(&network_header, sizeof(u16), &skb->network_header);\n bpf_probe_read(&ip_hdr, sizeof(ip_hdr), (struct iphdr *)(head+network_header));\n \n event_t* event;\n event = bpf_ringbuf_reserve(&rb, sizeof(event_t), 0);\n if(!event) return 0;\n \n event->id = (uint16_t) ((ip_hdr.id & 0xff) << 8) | (ip_hdr.id >> 8);\n event->seq = (uint32_t) __builtin_bswap32(tcp_hdr.seq);\n event->win = (uint16_t) ((tcp_hdr.window & 0xff) << 8) | (tcp_hdr.window >> 8);\n \n bpf_ringbuf_submit(event, 0);\n \n return 0;\n};\n" }, { "path": "src/knockles.c", "content": "#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \"knockles_event.h\"\n#include \"knockles.skel.h\"\n#define HMAC_DURATION 30\n#define LISTENING_DURATION 30\nstatic char SECRET[] = \"MY_SECRET_KEY\";\nstatic int SECRET_SIZE = sizeof(SECRET);\n\n/****************************************************/\n/*!\n * \\brief Use to maintain state when the program\n * is use in interactive mode\n */\nstatic volatile sig_atomic_t exiting;\n\n/****************************************************/\n/*!\n * \\brief Signal hanlder\n */\nvoid sig_int(int signo){\n exiting = 1;\n}\n\n/****************************************************/\n/*!\n * \\brief Display LibBPF logs\n */\nstatic int libbpf_print_fn(enum libbpf_print_level level, const char *format, va_list args){\n return vfprintf(stderr, format, args);\n}\n\n/****************************************************/\n/*!\n * \\brief HMAC generation and comparison\n */\nstatic uint16_t hmac_cmp(event_t *e){\n unsigned char clear[sizeof(uint64_t)], enc[16];\n unsigned int l_enc;\n uint64_t timestamp = time(NULL)/HMAC_DURATION;\n for(int i=0;i>= 8;\n }\n \n HMAC(EVP_md5(), SECRET, SECRET_SIZE, clear, sizeof(clear), enc, &l_enc);\n \n unsigned char rcv[8];\n uint16_t id = e->id;\n uint32_t seq = e->seq;\n uint16_t win = e->win;\n for(int i=0;i>= 8;\n }\n else if(i<6){\n rcv[i] = seq&0xFF;\n seq >>= 8;\n }\n else{\n rcv[i] = win&0xFF;\n win >>= 8;\n }\n }\n if(memcmp((char *)enc, (char *)rcv, sizeof(rcv))) return 1;\n \n uint16_t port = (((uint16_t)(enc[9]))<<8)|enc[8];\n \n return port;\n}\n\n/****************************************************/\n/*!\n * \\brief Socket handler\n */\nstatic int sock_handler(uint16_t port){\n int s, c;\n struct sockaddr_in serv, client;\n struct timeval timeout = {\n .tv_sec = LISTENING_DURATION\n };\n fd_set readfds;\n \n socklen_t l_client = sizeof(client);\n \n s = socket(AF_INET, SOCK_STREAM, 0);\n if(s == -1) return 1;\n \n serv.sin_family = AF_INET;\n serv.sin_addr.s_addr = htonl(INADDR_ANY);\n serv.sin_port = htons(port);\n \n if ((bind(s, (struct sockaddr *)&serv, sizeof(serv))) != 0) return 1;\n if ((listen(s, 1)) != 0) return 1;\n \n FD_ZERO(&readfds);\n FD_SET(s, &readfds);\n \n if(!select(s+1, &readfds, 0, 0, &timeout)){\n close(s);\n return 1;\n }\n c = accept(s, (struct sockaddr *)&client, &l_client);\n close(s);\n if(c<0)return 1;\n \n return 0;\n}\n\n/****************************************************/\n/*!\n * \\brief Event handler, debugging mode\n */\nstatic int handle_event_dbg(void *ctx, void *data, size_t data_sz){\n event_t *e = data;\n uint16_t port = hmac_cmp(e);\n \n printf(\"%-15u | %-15u | %-15u | \", (unsigned int)e->id, (unsigned int)e->seq, (unsigned int)e->win);\n \n if(port<=1024){\n printf(\"%-15s | %-15s | %-15s\\n\",\"FAIL\",\"N/A\",\"N/A\");\n return 0;\n };\n \n printf(\"%-15s | %-15u | %-15s\\n\", \"VALID\", (unsigned int)port, \"OPEN\");\n \n if(sock_handler(port)){\n printf(\"%-15u | %-15u | %-15u | %-15s | %-15u | %-15s\\n\", (unsigned int)e->id, (unsigned int)e->seq, (unsigned int)e->win, \"VALID\", (unsigned int)port, \"CLOSED\");\n }\n else{\n printf(\"%-15u | %-15u | %-15u | %-15s | %-15u | %-15s\\n\", (unsigned int)e->id, (unsigned int)e->seq, (unsigned int)e->win, \"VALID\", (unsigned int)port, \"CONNECTED\");\n }\n \n return 0;\n}\n\n/****************************************************/\n/*!\n * \\brief Event handler\n */\nstatic int handle_event(void *ctx, void *data, size_t data_sz){\n event_t *e = data;\n uint16_t port = hmac_cmp(e);\n \n if(port<=1024)return 0;\n if(sock_handler(port)) return 0;\n \n return 0;\n}\n\n/****************************************************/\n/*!\n * \\brief Continue the program as a daemon\n */\nstatic void start_daemon(void){\n pid_t child = fork();\n if (child < 0) exit(child);\n if (child > 0) exit(0);\n \n setsid();\n \n child = fork();\n if (child < 0) exit(child);\n if (child > 0) exit(0);\n \n umask(0);\n \n close(0);\n close(1);\n close(2);\n \n int fd_0 = open(\"/dev/null\", O_RDWR);\n if (fd_0 != 0) exit(1);\n int fd_1 = dup(fd_0);\n if (fd_1 != 1) exit(1);\n int fd_2 = dup(fd_0);\n if (fd_2 != 2) exit(1);\n}\n\n/****************************************************/\nint main(int argc, char *argv[]){\n struct ring_buffer *rb = NULL;\n struct knockles_bpf *skel;\n int err;\n \n char dmn_flag[] = \"--daemon\";\n char hlp_flag[] = \"--help\";\n int dmn_mode = 0;\n \n // Parse arguments\n if(argc>1){\n for(int i=1;imaps.rb), handle_event, NULL, NULL);\n \n // Set up ring buffer\n if(dmn_mode){\n rb = ring_buffer__new(bpf_map__fd(skel->maps.rb), handle_event, NULL, NULL);\n }\n else{\n rb = ring_buffer__new(bpf_map__fd(skel->maps.rb), handle_event_dbg, NULL, NULL);\n }\n if (!rb){\n err = -1;\n fprintf(stderr, \"Failed to create ring buffer\\n\");\n goto cleanup;\n }\n \n // Display user readable events\n if(!dmn_mode){\n printf(\"\\n\\e[1meBPF Port Knocking Tool.\\e[0m\\n\\n\");\n printf(\"%-15s | %-15s | %-15s | %-15s | %-15s | %-15s\\n\", \"ID\", \"SEQ\", \"WIN\", \"HMAC\", \"PORT\", \"STATUS\");\n printf(\"%-15s | %-15s | %-15s | %-15s | %-15s | %-15s\\n\", \"-\", \"-\", \"-\", \"-\", \"-\", \"-\");\n }\n if(dmn_mode){\n start_daemon();\n }\n \n while (!exiting){\n err = ring_buffer__poll(rb, 100);\n if (err == -EINTR){\n err = 0;\n break;\n }\n if (err < 0){\n printf(\"Error polling perf buffer: %d\\n\", err);\n break;\n }\n }\n \n cleanup:\n knockles_bpf__destroy(skel);\n return -err;\n}\n" }, { "path": "src/knockles_event.h", "content": "#ifndef __KNOCKLES_EVENT_H__\n#define __KNOCKLES_EVENT_H__\n\n/****************************************************/\n/*!\n * \\brief Event share between CO-RE code and userland\n */\ntypedef struct _event_t{\n uint16_t id;\n uint32_t seq;\n uint16_t win;\n} event_t;\n\n#endif\n" }, { "path": "src/knuckknock.py", "content": "#!/usr/bin/env python3\nfrom scapy.layers.inet import IP, TCP\nfrom scapy.sendrecv import send\nfrom time import time\nimport hmac, hashlib\nimport argparse\n\np = argparse.ArgumentParser(description='eBPF port knocking tool - Client.', formatter_class=argparse.RawTextHelpFormatter)\np.add_argument('-s', '--secret', metavar='KEY ', type=str, help='HMAC secret key', required=True)\np.add_argument('-t', '--time', metavar='TIME', type=int, help='generated HMAC duration', required=True)\np.add_argument('-d', '--dst', metavar='IP', type=str, help='destination IP address', required=True)\np.add_argument('-p', '--port', metavar='PORT', type=str, help='monitored port', required=True)\n\nargs = p.parse_args()\n\ntimestamp = int(time()//args.time)\n\nh = hmac.new(args.secret.encode(), int.to_bytes(timestamp, 8, byteorder='little'), hashlib.md5)\nh = h.digest()\n\nid = int.from_bytes(h[0:2], byteorder='little')\nseq = int.from_bytes(h[2:6], byteorder='little')\nwin = int.from_bytes(h[6:8], byteorder='little')\ntcp_port = int.from_bytes(h[8:10], byteorder='little')\n\nprint(tcp_port)\n\nsyn = TCP(dport=int(args.port), flags='S', seq=seq, window=win)\nip = IP(dst=args.dst, id=id)\nsend(ip/syn, verbose=False)\n\n" }, { "path": "src/vmlinux.h", "content": "#ifndef __VMLINUX_H__\n#define __VMLINUX_H__\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute push (__attribute__((preserve_access_index)), apply_to = record)\n#endif\n\ntypedef signed char __s8;\n\ntypedef unsigned char __u8;\n\ntypedef short int __s16;\n\ntypedef short unsigned int __u16;\n\ntypedef int __s32;\n\ntypedef unsigned int __u32;\n\ntypedef long long int __s64;\n\ntypedef long long unsigned int __u64;\n\ntypedef __s8 s8;\n\ntypedef __u8 u8;\n\ntypedef __s16 s16;\n\ntypedef __u16 u16;\n\ntypedef __s32 s32;\n\ntypedef __u32 u32;\n\ntypedef __s64 s64;\n\ntypedef __u64 u64;\n\nenum {\n\tfalse = 0,\n\ttrue = 1,\n};\n\ntypedef long int __kernel_long_t;\n\ntypedef long unsigned int __kernel_ulong_t;\n\ntypedef int __kernel_pid_t;\n\ntypedef unsigned int __kernel_uid32_t;\n\ntypedef unsigned int __kernel_gid32_t;\n\ntypedef __kernel_ulong_t __kernel_size_t;\n\ntypedef __kernel_long_t __kernel_ssize_t;\n\ntypedef long long int __kernel_loff_t;\n\ntypedef long long int __kernel_time64_t;\n\ntypedef __kernel_long_t __kernel_clock_t;\n\ntypedef int __kernel_timer_t;\n\ntypedef int __kernel_clockid_t;\n\ntypedef unsigned int __poll_t;\n\ntypedef u32 __kernel_dev_t;\n\ntypedef __kernel_dev_t dev_t;\n\ntypedef short unsigned int umode_t;\n\ntypedef __kernel_pid_t pid_t;\n\ntypedef __kernel_clockid_t clockid_t;\n\ntypedef _Bool bool;\n\ntypedef __kernel_uid32_t uid_t;\n\ntypedef __kernel_gid32_t gid_t;\n\ntypedef __kernel_loff_t loff_t;\n\ntypedef __kernel_size_t size_t;\n\ntypedef __kernel_ssize_t ssize_t;\n\ntypedef s32 int32_t;\n\ntypedef u32 uint32_t;\n\ntypedef u64 sector_t;\n\ntypedef u64 blkcnt_t;\n\ntypedef u64 dma_addr_t;\n\ntypedef unsigned int gfp_t;\n\ntypedef unsigned int fmode_t;\n\ntypedef u64 phys_addr_t;\n\ntypedef phys_addr_t resource_size_t;\n\ntypedef struct {\n\tint counter;\n} atomic_t;\n\ntypedef struct {\n\ts64 counter;\n} atomic64_t;\n\nstruct list_head {\n\tstruct list_head *next;\n\tstruct list_head *prev;\n};\n\nstruct hlist_node;\n\nstruct hlist_head {\n\tstruct hlist_node *first;\n};\n\nstruct hlist_node {\n\tstruct hlist_node *next;\n\tstruct hlist_node **pprev;\n};\n\nstruct callback_head {\n\tstruct callback_head *next;\n\tvoid (*func)(struct callback_head *);\n};\n\ntypedef int initcall_entry_t;\n\nstruct lock_class_key {};\n\nstruct fs_context;\n\nstruct fs_parameter_spec;\n\nstruct dentry;\n\nstruct super_block;\n\nstruct module;\n\nstruct file_system_type {\n\tconst char *name;\n\tint fs_flags;\n\tint (*init_fs_context)(struct fs_context *);\n\tconst struct fs_parameter_spec *parameters;\n\tstruct dentry * (*mount)(struct file_system_type *, int, const char *, void *);\n\tvoid (*kill_sb)(struct super_block *);\n\tstruct module *owner;\n\tstruct file_system_type *next;\n\tstruct hlist_head fs_supers;\n\tstruct lock_class_key s_lock_key;\n\tstruct lock_class_key s_umount_key;\n\tstruct lock_class_key s_vfs_rename_key;\n\tstruct lock_class_key s_writers_key[3];\n\tstruct lock_class_key i_lock_key;\n\tstruct lock_class_key i_mutex_key;\n\tstruct lock_class_key i_mutex_dir_key;\n};\n\ntypedef void *fl_owner_t;\n\nstruct file;\n\nstruct kiocb;\n\nstruct iov_iter;\n\nstruct dir_context;\n\nstruct poll_table_struct;\n\nstruct vm_area_struct;\n\nstruct inode;\n\nstruct file_lock;\n\nstruct page;\n\nstruct pipe_inode_info;\n\nstruct seq_file;\n\nstruct file_operations {\n\tstruct module *owner;\n\tloff_t (*llseek)(struct file *, loff_t, int);\n\tssize_t (*read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*write)(struct file *, const char *, size_t, loff_t *);\n\tssize_t (*read_iter)(struct kiocb *, struct iov_iter *);\n\tssize_t (*write_iter)(struct kiocb *, struct iov_iter *);\n\tint (*iopoll)(struct kiocb *, bool);\n\tint (*iterate)(struct file *, struct dir_context *);\n\tint (*iterate_shared)(struct file *, struct dir_context *);\n\t__poll_t (*poll)(struct file *, struct poll_table_struct *);\n\tlong int (*unlocked_ioctl)(struct file *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct file *, struct vm_area_struct *);\n\tlong unsigned int mmap_supported_flags;\n\tint (*open)(struct inode *, struct file *);\n\tint (*flush)(struct file *, fl_owner_t);\n\tint (*release)(struct inode *, struct file *);\n\tint (*fsync)(struct file *, loff_t, loff_t, int);\n\tint (*fasync)(int, struct file *, int);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tssize_t (*sendpage)(struct file *, struct page *, int, size_t, loff_t *, int);\n\tlong unsigned int (*get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tint (*check_flags)(int);\n\tint (*flock)(struct file *, int, struct file_lock *);\n\tssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t, unsigned int);\n\tssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tint (*setlease)(struct file *, long int, struct file_lock **, void **);\n\tlong int (*fallocate)(struct file *, int, loff_t, loff_t);\n\tvoid (*show_fdinfo)(struct seq_file *, struct file *);\n\tssize_t (*copy_file_range)(struct file *, loff_t, struct file *, loff_t, size_t, unsigned int);\n\tloff_t (*remap_file_range)(struct file *, loff_t, struct file *, loff_t, loff_t, unsigned int);\n\tint (*fadvise)(struct file *, loff_t, loff_t, int);\n};\n\nstruct qspinlock {\n\tunion {\n\t\tatomic_t val;\n\t\tstruct {\n\t\t\tu8 locked;\n\t\t\tu8 pending;\n\t\t};\n\t\tstruct {\n\t\t\tu16 locked_pending;\n\t\t\tu16 tail;\n\t\t};\n\t};\n};\n\ntypedef struct qspinlock arch_spinlock_t;\n\nstruct raw_spinlock {\n\tarch_spinlock_t raw_lock;\n};\n\nstruct spinlock {\n\tunion {\n\t\tstruct raw_spinlock rlock;\n\t};\n};\n\ntypedef struct spinlock spinlock_t;\n\nstruct notifier_block;\n\nstruct atomic_notifier_head {\n\tspinlock_t lock;\n\tstruct notifier_block *head;\n};\n\nenum system_states {\n\tSYSTEM_BOOTING = 0,\n\tSYSTEM_SCHEDULING = 1,\n\tSYSTEM_RUNNING = 2,\n\tSYSTEM_HALT = 3,\n\tSYSTEM_POWER_OFF = 4,\n\tSYSTEM_RESTART = 5,\n\tSYSTEM_SUSPEND = 6,\n};\n\nstruct taint_flag {\n\tchar c_true;\n\tchar c_false;\n\tbool module;\n};\n\nstruct jump_entry {\n\ts32 code;\n\ts32 target;\n\tlong int key;\n};\n\nstruct static_key_mod;\n\nstruct static_key {\n\tatomic_t enabled;\n\tunion {\n\t\tlong unsigned int type;\n\t\tstruct jump_entry *entries;\n\t\tstruct static_key_mod *next;\n\t};\n};\n\nstruct static_key_true {\n\tstruct static_key key;\n};\n\nstruct static_key_false {\n\tstruct static_key key;\n};\n\ntypedef __s64 time64_t;\n\nstruct __kernel_timespec {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_nsec;\n};\n\nstruct timezone {\n\tint tz_minuteswest;\n\tint tz_dsttime;\n};\n\nstruct timespec64 {\n\ttime64_t tv_sec;\n\tlong int tv_nsec;\n};\n\nenum timespec_type {\n\tTT_NONE = 0,\n\tTT_NATIVE = 1,\n\tTT_COMPAT = 2,\n};\n\ntypedef s32 old_time32_t;\n\nstruct old_timespec32 {\n\told_time32_t tv_sec;\n\ts32 tv_nsec;\n};\n\nstruct pollfd;\n\nstruct restart_block {\n\tlong int (*fn)(struct restart_block *);\n\tunion {\n\t\tstruct {\n\t\t\tu32 *uaddr;\n\t\t\tu32 val;\n\t\t\tu32 flags;\n\t\t\tu32 bitset;\n\t\t\tu64 time;\n\t\t\tu32 *uaddr2;\n\t\t} futex;\n\t\tstruct {\n\t\t\tclockid_t clockid;\n\t\t\tenum timespec_type type;\n\t\t\tunion {\n\t\t\t\tstruct __kernel_timespec *rmtp;\n\t\t\t\tstruct old_timespec32 *compat_rmtp;\n\t\t\t};\n\t\t\tu64 expires;\n\t\t} nanosleep;\n\t\tstruct {\n\t\t\tstruct pollfd *ufds;\n\t\t\tint nfds;\n\t\t\tint has_timeout;\n\t\t\tlong unsigned int tv_sec;\n\t\t\tlong unsigned int tv_nsec;\n\t\t} poll;\n\t};\n};\n\nstruct thread_info {\n\tlong unsigned int flags;\n\tu32 status;\n};\n\nstruct refcount_struct {\n\tatomic_t refs;\n};\n\ntypedef struct refcount_struct refcount_t;\n\nstruct llist_node {\n\tstruct llist_node *next;\n};\n\nstruct __call_single_node {\n\tstruct llist_node llist;\n\tunion {\n\t\tunsigned int u_flags;\n\t\tatomic_t a_flags;\n\t};\n};\n\nstruct load_weight {\n\tlong unsigned int weight;\n\tu32 inv_weight;\n};\n\nstruct rb_node {\n\tlong unsigned int __rb_parent_color;\n\tstruct rb_node *rb_right;\n\tstruct rb_node *rb_left;\n};\n\nstruct sched_statistics {\n\tu64 wait_start;\n\tu64 wait_max;\n\tu64 wait_count;\n\tu64 wait_sum;\n\tu64 iowait_count;\n\tu64 iowait_sum;\n\tu64 sleep_start;\n\tu64 sleep_max;\n\ts64 sum_sleep_runtime;\n\tu64 block_start;\n\tu64 block_max;\n\tu64 exec_max;\n\tu64 slice_max;\n\tu64 nr_migrations_cold;\n\tu64 nr_failed_migrations_affine;\n\tu64 nr_failed_migrations_running;\n\tu64 nr_failed_migrations_hot;\n\tu64 nr_forced_migrations;\n\tu64 nr_wakeups;\n\tu64 nr_wakeups_sync;\n\tu64 nr_wakeups_migrate;\n\tu64 nr_wakeups_local;\n\tu64 nr_wakeups_remote;\n\tu64 nr_wakeups_affine;\n\tu64 nr_wakeups_affine_attempts;\n\tu64 nr_wakeups_passive;\n\tu64 nr_wakeups_idle;\n};\n\nstruct util_est {\n\tunsigned int enqueued;\n\tunsigned int ewma;\n};\n\nstruct sched_avg {\n\tu64 last_update_time;\n\tu64 load_sum;\n\tu64 runnable_sum;\n\tu32 util_sum;\n\tu32 period_contrib;\n\tlong unsigned int load_avg;\n\tlong unsigned int runnable_avg;\n\tlong unsigned int util_avg;\n\tstruct util_est util_est;\n};\n\nstruct cfs_rq;\n\nstruct sched_entity {\n\tstruct load_weight load;\n\tstruct rb_node run_node;\n\tstruct list_head group_node;\n\tunsigned int on_rq;\n\tu64 exec_start;\n\tu64 sum_exec_runtime;\n\tu64 vruntime;\n\tu64 prev_sum_exec_runtime;\n\tu64 nr_migrations;\n\tstruct sched_statistics statistics;\n\tint depth;\n\tstruct sched_entity *parent;\n\tstruct cfs_rq *cfs_rq;\n\tstruct cfs_rq *my_q;\n\tlong unsigned int runnable_weight;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg;\n};\n\nstruct sched_rt_entity {\n\tstruct list_head run_list;\n\tlong unsigned int timeout;\n\tlong unsigned int watchdog_stamp;\n\tunsigned int time_slice;\n\tshort unsigned int on_rq;\n\tshort unsigned int on_list;\n\tstruct sched_rt_entity *back;\n};\n\ntypedef s64 ktime_t;\n\nstruct timerqueue_node {\n\tstruct rb_node node;\n\tktime_t expires;\n};\n\nenum hrtimer_restart {\n\tHRTIMER_NORESTART = 0,\n\tHRTIMER_RESTART = 1,\n};\n\nstruct hrtimer_clock_base;\n\nstruct hrtimer {\n\tstruct timerqueue_node node;\n\tktime_t _softexpires;\n\tenum hrtimer_restart (*function)(struct hrtimer *);\n\tstruct hrtimer_clock_base *base;\n\tu8 state;\n\tu8 is_rel;\n\tu8 is_soft;\n\tu8 is_hard;\n};\n\nstruct sched_dl_entity {\n\tstruct rb_node rb_node;\n\tu64 dl_runtime;\n\tu64 dl_deadline;\n\tu64 dl_period;\n\tu64 dl_bw;\n\tu64 dl_density;\n\ts64 runtime;\n\tu64 deadline;\n\tunsigned int flags;\n\tunsigned int dl_throttled: 1;\n\tunsigned int dl_boosted: 1;\n\tunsigned int dl_yielded: 1;\n\tunsigned int dl_non_contending: 1;\n\tunsigned int dl_overrun: 1;\n\tstruct hrtimer dl_timer;\n\tstruct hrtimer inactive_timer;\n};\n\nstruct cpumask {\n\tlong unsigned int bits[1];\n};\n\ntypedef struct cpumask cpumask_t;\n\nstruct sched_info {\n\tlong unsigned int pcount;\n\tlong long unsigned int run_delay;\n\tlong long unsigned int last_arrival;\n\tlong long unsigned int last_queued;\n};\n\nstruct plist_node {\n\tint prio;\n\tstruct list_head prio_list;\n\tstruct list_head node_list;\n};\n\nstruct vmacache {\n\tu64 seqnum;\n\tstruct vm_area_struct *vmas[4];\n};\n\nstruct task_rss_stat {\n\tint events;\n\tint count[4];\n};\n\ntypedef struct raw_spinlock raw_spinlock_t;\n\nstruct prev_cputime {\n\tu64 utime;\n\tu64 stime;\n\traw_spinlock_t lock;\n};\n\nstruct rb_root {\n\tstruct rb_node *rb_node;\n};\n\nstruct rb_root_cached {\n\tstruct rb_root rb_root;\n\tstruct rb_node *rb_leftmost;\n};\n\nstruct timerqueue_head {\n\tstruct rb_root_cached rb_root;\n};\n\nstruct posix_cputimer_base {\n\tu64 nextevt;\n\tstruct timerqueue_head tqhead;\n};\n\nstruct posix_cputimers {\n\tstruct posix_cputimer_base bases[3];\n\tunsigned int timers_active;\n\tunsigned int expiry_active;\n};\n\nstruct sem_undo_list;\n\nstruct sysv_sem {\n\tstruct sem_undo_list *undo_list;\n};\n\nstruct sysv_shm {\n\tstruct list_head shm_clist;\n};\n\ntypedef struct {\n\tlong unsigned int sig[1];\n} sigset_t;\n\nstruct sigpending {\n\tstruct list_head list;\n\tsigset_t signal;\n};\n\ntypedef struct {\n\tuid_t val;\n} kuid_t;\n\nstruct seccomp_filter;\n\nstruct seccomp {\n\tint mode;\n\tstruct seccomp_filter *filter;\n};\n\nstruct wake_q_node {\n\tstruct wake_q_node *next;\n};\n\nstruct task_io_accounting {\n\tu64 rchar;\n\tu64 wchar;\n\tu64 syscr;\n\tu64 syscw;\n\tu64 read_bytes;\n\tu64 write_bytes;\n\tu64 cancelled_write_bytes;\n};\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} nodemask_t;\n\nstruct seqcount {\n\tunsigned int sequence;\n};\n\ntypedef struct seqcount seqcount_t;\n\ntypedef atomic64_t atomic_long_t;\n\nstruct optimistic_spin_queue {\n\tatomic_t tail;\n};\n\nstruct mutex {\n\tatomic_long_t owner;\n\tspinlock_t wait_lock;\n\tstruct optimistic_spin_queue osq;\n\tstruct list_head wait_list;\n};\n\nstruct arch_tlbflush_unmap_batch {\n\tstruct cpumask cpumask;\n};\n\nstruct tlbflush_unmap_batch {\n\tstruct arch_tlbflush_unmap_batch arch;\n\tbool flush_required;\n\tbool writable;\n};\n\nstruct page_frag {\n\tstruct page *page;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct desc_struct {\n\tu16 limit0;\n\tu16 base0;\n\tu16 base1: 8;\n\tu16 type: 4;\n\tu16 s: 1;\n\tu16 dpl: 2;\n\tu16 p: 1;\n\tu16 limit1: 4;\n\tu16 avl: 1;\n\tu16 l: 1;\n\tu16 d: 1;\n\tu16 g: 1;\n\tu16 base2: 8;\n};\n\ntypedef struct {\n\tlong unsigned int seg;\n} mm_segment_t;\n\nstruct fregs_state {\n\tu32 cwd;\n\tu32 swd;\n\tu32 twd;\n\tu32 fip;\n\tu32 fcs;\n\tu32 foo;\n\tu32 fos;\n\tu32 st_space[20];\n\tu32 status;\n};\n\nstruct fxregs_state {\n\tu16 cwd;\n\tu16 swd;\n\tu16 twd;\n\tu16 fop;\n\tunion {\n\t\tstruct {\n\t\t\tu64 rip;\n\t\t\tu64 rdp;\n\t\t};\n\t\tstruct {\n\t\t\tu32 fip;\n\t\t\tu32 fcs;\n\t\t\tu32 foo;\n\t\t\tu32 fos;\n\t\t};\n\t};\n\tu32 mxcsr;\n\tu32 mxcsr_mask;\n\tu32 st_space[32];\n\tu32 xmm_space[64];\n\tu32 padding[12];\n\tunion {\n\t\tu32 padding1[12];\n\t\tu32 sw_reserved[12];\n\t};\n};\n\nstruct math_emu_info;\n\nstruct swregs_state {\n\tu32 cwd;\n\tu32 swd;\n\tu32 twd;\n\tu32 fip;\n\tu32 fcs;\n\tu32 foo;\n\tu32 fos;\n\tu32 st_space[20];\n\tu8 ftop;\n\tu8 changed;\n\tu8 lookahead;\n\tu8 no_update;\n\tu8 rm;\n\tu8 alimit;\n\tstruct math_emu_info *info;\n\tu32 entry_eip;\n};\n\nstruct xstate_header {\n\tu64 xfeatures;\n\tu64 xcomp_bv;\n\tu64 reserved[6];\n};\n\nstruct xregs_state {\n\tstruct fxregs_state i387;\n\tstruct xstate_header header;\n\tu8 extended_state_area[0];\n};\n\nunion fpregs_state {\n\tstruct fregs_state fsave;\n\tstruct fxregs_state fxsave;\n\tstruct swregs_state soft;\n\tstruct xregs_state xsave;\n\tu8 __padding[4096];\n};\n\nstruct fpu {\n\tunsigned int last_cpu;\n\tlong unsigned int avx512_timestamp;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion fpregs_state state;\n};\n\nstruct perf_event;\n\nstruct io_bitmap;\n\nstruct thread_struct {\n\tstruct desc_struct tls_array[3];\n\tlong unsigned int sp;\n\tshort unsigned int es;\n\tshort unsigned int ds;\n\tshort unsigned int fsindex;\n\tshort unsigned int gsindex;\n\tlong unsigned int fsbase;\n\tlong unsigned int gsbase;\n\tstruct perf_event *ptrace_bps[4];\n\tlong unsigned int debugreg6;\n\tlong unsigned int ptrace_dr7;\n\tlong unsigned int cr2;\n\tlong unsigned int trap_nr;\n\tlong unsigned int error_code;\n\tstruct io_bitmap *io_bitmap;\n\tlong unsigned int iopl_emul;\n\tmm_segment_t addr_limit;\n\tunsigned int sig_on_uaccess_err: 1;\n\tlong: 63;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct fpu fpu;\n};\n\nstruct sched_class;\n\nstruct task_group;\n\nstruct mm_struct;\n\nstruct pid;\n\nstruct completion;\n\nstruct cred;\n\nstruct key;\n\nstruct nameidata;\n\nstruct fs_struct;\n\nstruct files_struct;\n\nstruct nsproxy;\n\nstruct signal_struct;\n\nstruct sighand_struct;\n\nstruct audit_context;\n\nstruct rt_mutex_waiter;\n\nstruct bio_list;\n\nstruct blk_plug;\n\nstruct reclaim_state;\n\nstruct backing_dev_info;\n\nstruct io_context;\n\nstruct capture_control;\n\nstruct kernel_siginfo;\n\ntypedef struct kernel_siginfo kernel_siginfo_t;\n\nstruct css_set;\n\nstruct robust_list_head;\n\nstruct compat_robust_list_head;\n\nstruct futex_pi_state;\n\nstruct perf_event_context;\n\nstruct mempolicy;\n\nstruct rseq;\n\nstruct task_delay_info;\n\nstruct uprobe_task;\n\nstruct vm_struct;\n\nstruct task_struct {\n\tstruct thread_info thread_info;\n\tvolatile long int state;\n\tvoid *stack;\n\trefcount_t usage;\n\tunsigned int flags;\n\tunsigned int ptrace;\n\tint on_cpu;\n\tstruct __call_single_node wake_entry;\n\tunsigned int cpu;\n\tunsigned int wakee_flips;\n\tlong unsigned int wakee_flip_decay_ts;\n\tstruct task_struct *last_wakee;\n\tint recent_used_cpu;\n\tint wake_cpu;\n\tint on_rq;\n\tint prio;\n\tint static_prio;\n\tint normal_prio;\n\tunsigned int rt_priority;\n\tconst struct sched_class *sched_class;\n\tstruct sched_entity se;\n\tstruct sched_rt_entity rt;\n\tstruct task_group *sched_task_group;\n\tstruct sched_dl_entity dl;\n\tunsigned int btrace_seq;\n\tunsigned int policy;\n\tint nr_cpus_allowed;\n\tconst cpumask_t *cpus_ptr;\n\tcpumask_t cpus_mask;\n\tstruct sched_info sched_info;\n\tstruct list_head tasks;\n\tstruct plist_node pushable_tasks;\n\tstruct rb_node pushable_dl_tasks;\n\tstruct mm_struct *mm;\n\tstruct mm_struct *active_mm;\n\tstruct vmacache vmacache;\n\tstruct task_rss_stat rss_stat;\n\tint exit_state;\n\tint exit_code;\n\tint exit_signal;\n\tint pdeath_signal;\n\tlong unsigned int jobctl;\n\tunsigned int personality;\n\tunsigned int sched_reset_on_fork: 1;\n\tunsigned int sched_contributes_to_load: 1;\n\tunsigned int sched_migrated: 1;\n\tunsigned int sched_remote_wakeup: 1;\n\tint: 28;\n\tunsigned int in_execve: 1;\n\tunsigned int in_iowait: 1;\n\tunsigned int restore_sigmask: 1;\n\tunsigned int no_cgroup_migration: 1;\n\tunsigned int frozen: 1;\n\tlong unsigned int atomic_flags;\n\tstruct restart_block restart_block;\n\tpid_t pid;\n\tpid_t tgid;\n\tlong unsigned int stack_canary;\n\tstruct task_struct *real_parent;\n\tstruct task_struct *parent;\n\tstruct list_head children;\n\tstruct list_head sibling;\n\tstruct task_struct *group_leader;\n\tstruct list_head ptraced;\n\tstruct list_head ptrace_entry;\n\tstruct pid *thread_pid;\n\tstruct hlist_node pid_links[4];\n\tstruct list_head thread_group;\n\tstruct list_head thread_node;\n\tstruct completion *vfork_done;\n\tint *set_child_tid;\n\tint *clear_child_tid;\n\tu64 utime;\n\tu64 stime;\n\tu64 gtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tu64 start_time;\n\tu64 start_boottime;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tstruct posix_cputimers posix_cputimers;\n\tconst struct cred *ptracer_cred;\n\tconst struct cred *real_cred;\n\tconst struct cred *cred;\n\tstruct key *cached_requested_key;\n\tchar comm[16];\n\tstruct nameidata *nameidata;\n\tstruct sysv_sem sysvsem;\n\tstruct sysv_shm sysvshm;\n\tstruct fs_struct *fs;\n\tstruct files_struct *files;\n\tstruct nsproxy *nsproxy;\n\tstruct signal_struct *signal;\n\tstruct sighand_struct *sighand;\n\tsigset_t blocked;\n\tsigset_t real_blocked;\n\tsigset_t saved_sigmask;\n\tstruct sigpending pending;\n\tlong unsigned int sas_ss_sp;\n\tsize_t sas_ss_size;\n\tunsigned int sas_ss_flags;\n\tstruct callback_head *task_works;\n\tstruct audit_context *audit_context;\n\tkuid_t loginuid;\n\tunsigned int sessionid;\n\tstruct seccomp seccomp;\n\tu64 parent_exec_id;\n\tu64 self_exec_id;\n\tspinlock_t alloc_lock;\n\traw_spinlock_t pi_lock;\n\tstruct wake_q_node wake_q;\n\tstruct rb_root_cached pi_waiters;\n\tstruct task_struct *pi_top_task;\n\tstruct rt_mutex_waiter *pi_blocked_on;\n\tvoid *journal_info;\n\tstruct bio_list *bio_list;\n\tstruct blk_plug *plug;\n\tstruct reclaim_state *reclaim_state;\n\tstruct backing_dev_info *backing_dev_info;\n\tstruct io_context *io_context;\n\tstruct capture_control *capture_control;\n\tlong unsigned int ptrace_message;\n\tkernel_siginfo_t *last_siginfo;\n\tstruct task_io_accounting ioac;\n\tu64 acct_rss_mem1;\n\tu64 acct_vm_mem1;\n\tu64 acct_timexpd;\n\tnodemask_t mems_allowed;\n\tseqcount_t mems_allowed_seq;\n\tint cpuset_mem_spread_rotor;\n\tint cpuset_slab_spread_rotor;\n\tstruct css_set *cgroups;\n\tstruct list_head cg_list;\n\tstruct robust_list_head *robust_list;\n\tstruct compat_robust_list_head *compat_robust_list;\n\tstruct list_head pi_state_list;\n\tstruct futex_pi_state *pi_state_cache;\n\tstruct mutex futex_exit_mutex;\n\tunsigned int futex_state;\n\tstruct perf_event_context *perf_event_ctxp[2];\n\tstruct mutex perf_event_mutex;\n\tstruct list_head perf_event_list;\n\tstruct mempolicy *mempolicy;\n\tshort int il_prev;\n\tshort int pref_node_fork;\n\tstruct rseq *rseq;\n\tu32 rseq_sig;\n\tlong unsigned int rseq_event_mask;\n\tstruct tlbflush_unmap_batch tlb_ubc;\n\tunion {\n\t\trefcount_t rcu_users;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct pipe_inode_info *splice_pipe;\n\tstruct page_frag task_frag;\n\tstruct task_delay_info *delays;\n\tint nr_dirtied;\n\tint nr_dirtied_pause;\n\tlong unsigned int dirty_paused_when;\n\tu64 timer_slack_ns;\n\tu64 default_timer_slack_ns;\n\tlong unsigned int trace;\n\tlong unsigned int trace_recursion;\n\tstruct uprobe_task *utask;\n\tint pagefault_disabled;\n\tstruct task_struct *oom_reaper_list;\n\tstruct vm_struct *stack_vm_area;\n\trefcount_t stack_refcount;\n\tvoid *security;\n\tu64 mce_addr;\n\t__u64 mce_ripv: 1;\n\t__u64 mce_whole_page: 1;\n\t__u64 __mce_reserved: 62;\n\tstruct callback_head mce_kill_me;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct thread_struct thread;\n};\n\nstruct screen_info {\n\t__u8 orig_x;\n\t__u8 orig_y;\n\t__u16 ext_mem_k;\n\t__u16 orig_video_page;\n\t__u8 orig_video_mode;\n\t__u8 orig_video_cols;\n\t__u8 flags;\n\t__u8 unused2;\n\t__u16 orig_video_ega_bx;\n\t__u16 unused3;\n\t__u8 orig_video_lines;\n\t__u8 orig_video_isVGA;\n\t__u16 orig_video_points;\n\t__u16 lfb_width;\n\t__u16 lfb_height;\n\t__u16 lfb_depth;\n\t__u32 lfb_base;\n\t__u32 lfb_size;\n\t__u16 cl_magic;\n\t__u16 cl_offset;\n\t__u16 lfb_linelength;\n\t__u8 red_size;\n\t__u8 red_pos;\n\t__u8 green_size;\n\t__u8 green_pos;\n\t__u8 blue_size;\n\t__u8 blue_pos;\n\t__u8 rsvd_size;\n\t__u8 rsvd_pos;\n\t__u16 vesapm_seg;\n\t__u16 vesapm_off;\n\t__u16 pages;\n\t__u16 vesa_attributes;\n\t__u32 capabilities;\n\t__u32 ext_lfb_base;\n\t__u8 _reserved[2];\n} __attribute__((packed));\n\nstruct apm_bios_info {\n\t__u16 version;\n\t__u16 cseg;\n\t__u32 offset;\n\t__u16 cseg_16;\n\t__u16 dseg;\n\t__u16 flags;\n\t__u16 cseg_len;\n\t__u16 cseg_16_len;\n\t__u16 dseg_len;\n};\n\nstruct apm_info {\n\tstruct apm_bios_info bios;\n\tshort unsigned int connection_version;\n\tint get_power_status_broken;\n\tint get_power_status_swabinminutes;\n\tint allow_ints;\n\tint forbid_idle;\n\tint realmode_power_off;\n\tint disabled;\n};\n\nstruct edd_device_params {\n\t__u16 length;\n\t__u16 info_flags;\n\t__u32 num_default_cylinders;\n\t__u32 num_default_heads;\n\t__u32 sectors_per_track;\n\t__u64 number_of_sectors;\n\t__u16 bytes_per_sector;\n\t__u32 dpte_ptr;\n\t__u16 key;\n\t__u8 device_path_info_length;\n\t__u8 reserved2;\n\t__u16 reserved3;\n\t__u8 host_bus_type[4];\n\t__u8 interface_type[8];\n\tunion {\n\t\tstruct {\n\t\t\t__u16 base_address;\n\t\t\t__u16 reserved1;\n\t\t\t__u32 reserved2;\n\t\t} isa;\n\t\tstruct {\n\t\t\t__u8 bus;\n\t\t\t__u8 slot;\n\t\t\t__u8 function;\n\t\t\t__u8 channel;\n\t\t\t__u32 reserved;\n\t\t} pci;\n\t\tstruct {\n\t\t\t__u64 reserved;\n\t\t} ibnd;\n\t\tstruct {\n\t\t\t__u64 reserved;\n\t\t} xprs;\n\t\tstruct {\n\t\t\t__u64 reserved;\n\t\t} htpt;\n\t\tstruct {\n\t\t\t__u64 reserved;\n\t\t} unknown;\n\t} interface_path;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 device;\n\t\t\t__u8 reserved1;\n\t\t\t__u16 reserved2;\n\t\t\t__u32 reserved3;\n\t\t\t__u64 reserved4;\n\t\t} ata;\n\t\tstruct {\n\t\t\t__u8 device;\n\t\t\t__u8 lun;\n\t\t\t__u8 reserved1;\n\t\t\t__u8 reserved2;\n\t\t\t__u32 reserved3;\n\t\t\t__u64 reserved4;\n\t\t} atapi;\n\t\tstruct {\n\t\t\t__u16 id;\n\t\t\t__u64 lun;\n\t\t\t__u16 reserved1;\n\t\t\t__u32 reserved2;\n\t\t} __attribute__((packed)) scsi;\n\t\tstruct {\n\t\t\t__u64 serial_number;\n\t\t\t__u64 reserved;\n\t\t} usb;\n\t\tstruct {\n\t\t\t__u64 eui;\n\t\t\t__u64 reserved;\n\t\t} i1394;\n\t\tstruct {\n\t\t\t__u64 wwid;\n\t\t\t__u64 lun;\n\t\t} fibre;\n\t\tstruct {\n\t\t\t__u64 identity_tag;\n\t\t\t__u64 reserved;\n\t\t} i2o;\n\t\tstruct {\n\t\t\t__u32 array_number;\n\t\t\t__u32 reserved1;\n\t\t\t__u64 reserved2;\n\t\t} raid;\n\t\tstruct {\n\t\t\t__u8 device;\n\t\t\t__u8 reserved1;\n\t\t\t__u16 reserved2;\n\t\t\t__u32 reserved3;\n\t\t\t__u64 reserved4;\n\t\t} sata;\n\t\tstruct {\n\t\t\t__u64 reserved1;\n\t\t\t__u64 reserved2;\n\t\t} unknown;\n\t} device_path;\n\t__u8 reserved4;\n\t__u8 checksum;\n} __attribute__((packed));\n\nstruct edd_info {\n\t__u8 device;\n\t__u8 version;\n\t__u16 interface_support;\n\t__u16 legacy_max_cylinder;\n\t__u8 legacy_max_head;\n\t__u8 legacy_sectors_per_track;\n\tstruct edd_device_params params;\n} __attribute__((packed));\n\nstruct edd {\n\tunsigned int mbr_signature[16];\n\tstruct edd_info edd_info[6];\n\tunsigned char mbr_signature_nr;\n\tunsigned char edd_info_nr;\n};\n\nstruct ist_info {\n\t__u32 signature;\n\t__u32 command;\n\t__u32 event;\n\t__u32 perf_level;\n};\n\nstruct edid_info {\n\tunsigned char dummy[128];\n};\n\nstruct setup_header {\n\t__u8 setup_sects;\n\t__u16 root_flags;\n\t__u32 syssize;\n\t__u16 ram_size;\n\t__u16 vid_mode;\n\t__u16 root_dev;\n\t__u16 boot_flag;\n\t__u16 jump;\n\t__u32 header;\n\t__u16 version;\n\t__u32 realmode_swtch;\n\t__u16 start_sys_seg;\n\t__u16 kernel_version;\n\t__u8 type_of_loader;\n\t__u8 loadflags;\n\t__u16 setup_move_size;\n\t__u32 code32_start;\n\t__u32 ramdisk_image;\n\t__u32 ramdisk_size;\n\t__u32 bootsect_kludge;\n\t__u16 heap_end_ptr;\n\t__u8 ext_loader_ver;\n\t__u8 ext_loader_type;\n\t__u32 cmd_line_ptr;\n\t__u32 initrd_addr_max;\n\t__u32 kernel_alignment;\n\t__u8 relocatable_kernel;\n\t__u8 min_alignment;\n\t__u16 xloadflags;\n\t__u32 cmdline_size;\n\t__u32 hardware_subarch;\n\t__u64 hardware_subarch_data;\n\t__u32 payload_offset;\n\t__u32 payload_length;\n\t__u64 setup_data;\n\t__u64 pref_address;\n\t__u32 init_size;\n\t__u32 handover_offset;\n\t__u32 kernel_info_offset;\n} __attribute__((packed));\n\nstruct sys_desc_table {\n\t__u16 length;\n\t__u8 table[14];\n};\n\nstruct olpc_ofw_header {\n\t__u32 ofw_magic;\n\t__u32 ofw_version;\n\t__u32 cif_handler;\n\t__u32 irq_desc_table;\n};\n\nstruct efi_info {\n\t__u32 efi_loader_signature;\n\t__u32 efi_systab;\n\t__u32 efi_memdesc_size;\n\t__u32 efi_memdesc_version;\n\t__u32 efi_memmap;\n\t__u32 efi_memmap_size;\n\t__u32 efi_systab_hi;\n\t__u32 efi_memmap_hi;\n};\n\nstruct boot_e820_entry {\n\t__u64 addr;\n\t__u64 size;\n\t__u32 type;\n} __attribute__((packed));\n\nstruct boot_params {\n\tstruct screen_info screen_info;\n\tstruct apm_bios_info apm_bios_info;\n\t__u8 _pad2[4];\n\t__u64 tboot_addr;\n\tstruct ist_info ist_info;\n\t__u64 acpi_rsdp_addr;\n\t__u8 _pad3[8];\n\t__u8 hd0_info[16];\n\t__u8 hd1_info[16];\n\tstruct sys_desc_table sys_desc_table;\n\tstruct olpc_ofw_header olpc_ofw_header;\n\t__u32 ext_ramdisk_image;\n\t__u32 ext_ramdisk_size;\n\t__u32 ext_cmd_line_ptr;\n\t__u8 _pad4[116];\n\tstruct edid_info edid_info;\n\tstruct efi_info efi_info;\n\t__u32 alt_mem_k;\n\t__u32 scratch;\n\t__u8 e820_entries;\n\t__u8 eddbuf_entries;\n\t__u8 edd_mbr_sig_buf_entries;\n\t__u8 kbd_status;\n\t__u8 secure_boot;\n\t__u8 _pad5[2];\n\t__u8 sentinel;\n\t__u8 _pad6[1];\n\tstruct setup_header hdr;\n\t__u8 _pad7[36];\n\t__u32 edd_mbr_sig_buffer[16];\n\tstruct boot_e820_entry e820_table[128];\n\t__u8 _pad8[48];\n\tstruct edd_info eddbuf[6];\n\t__u8 _pad9[276];\n} __attribute__((packed));\n\nenum x86_hardware_subarch {\n\tX86_SUBARCH_PC = 0,\n\tX86_SUBARCH_LGUEST = 1,\n\tX86_SUBARCH_XEN = 2,\n\tX86_SUBARCH_INTEL_MID = 3,\n\tX86_SUBARCH_CE4100 = 4,\n\tX86_NR_SUBARCHS = 5,\n};\n\nstruct range {\n\tu64 start;\n\tu64 end;\n};\n\nstruct pt_regs {\n\tlong unsigned int r15;\n\tlong unsigned int r14;\n\tlong unsigned int r13;\n\tlong unsigned int r12;\n\tlong unsigned int bp;\n\tlong unsigned int bx;\n\tlong unsigned int r11;\n\tlong unsigned int r10;\n\tlong unsigned int r9;\n\tlong unsigned int r8;\n\tlong unsigned int ax;\n\tlong unsigned int cx;\n\tlong unsigned int dx;\n\tlong unsigned int si;\n\tlong unsigned int di;\n\tlong unsigned int orig_ax;\n\tlong unsigned int ip;\n\tlong unsigned int cs;\n\tlong unsigned int flags;\n\tlong unsigned int sp;\n\tlong unsigned int ss;\n};\n\nstruct math_emu_info {\n\tlong int ___orig_eip;\n\tstruct pt_regs *regs;\n};\n\ntypedef long unsigned int pteval_t;\n\ntypedef long unsigned int pmdval_t;\n\ntypedef long unsigned int pudval_t;\n\ntypedef long unsigned int p4dval_t;\n\ntypedef long unsigned int pgdval_t;\n\ntypedef long unsigned int pgprotval_t;\n\ntypedef struct {\n\tpteval_t pte;\n} pte_t;\n\nstruct pgprot {\n\tpgprotval_t pgprot;\n};\n\ntypedef struct pgprot pgprot_t;\n\ntypedef struct {\n\tpgdval_t pgd;\n} pgd_t;\n\ntypedef struct {\n\tp4dval_t p4d;\n} p4d_t;\n\ntypedef struct {\n\tpudval_t pud;\n} pud_t;\n\ntypedef struct {\n\tpmdval_t pmd;\n} pmd_t;\n\ntypedef struct page *pgtable_t;\n\nstruct address_space;\n\nstruct kmem_cache;\n\nstruct dev_pagemap;\n\nstruct page {\n\tlong unsigned int flags;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head lru;\n\t\t\tstruct address_space *mapping;\n\t\t\tlong unsigned int index;\n\t\t\tlong unsigned int private;\n\t\t};\n\t\tstruct {\n\t\t\tdma_addr_t dma_addr;\n\t\t};\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct list_head slab_list;\n\t\t\t\tstruct {\n\t\t\t\t\tstruct page *next;\n\t\t\t\t\tint pages;\n\t\t\t\t\tint pobjects;\n\t\t\t\t};\n\t\t\t};\n\t\t\tstruct kmem_cache *slab_cache;\n\t\t\tvoid *freelist;\n\t\t\tunion {\n\t\t\t\tvoid *s_mem;\n\t\t\t\tlong unsigned int counters;\n\t\t\t\tstruct {\n\t\t\t\t\tunsigned int inuse: 16;\n\t\t\t\t\tunsigned int objects: 15;\n\t\t\t\t\tunsigned int frozen: 1;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int compound_head;\n\t\t\tunsigned char compound_dtor;\n\t\t\tunsigned char compound_order;\n\t\t\tatomic_t compound_mapcount;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int _compound_pad_1;\n\t\t\tatomic_t hpage_pinned_refcount;\n\t\t\tstruct list_head deferred_list;\n\t\t};\n\t\tstruct {\n\t\t\tlong unsigned int _pt_pad_1;\n\t\t\tpgtable_t pmd_huge_pte;\n\t\t\tlong unsigned int _pt_pad_2;\n\t\t\tunion {\n\t\t\t\tstruct mm_struct *pt_mm;\n\t\t\t\tatomic_t pt_frag_refcount;\n\t\t\t};\n\t\t\tspinlock_t ptl;\n\t\t};\n\t\tstruct {\n\t\t\tstruct dev_pagemap *pgmap;\n\t\t\tvoid *zone_device_data;\n\t\t};\n\t\tstruct callback_head callback_head;\n\t};\n\tunion {\n\t\tatomic_t _mapcount;\n\t\tunsigned int page_type;\n\t\tunsigned int active;\n\t\tint units;\n\t};\n\tatomic_t _refcount;\n\tlong: 64;\n};\n\ntypedef struct cpumask cpumask_var_t[1];\n\nstruct tracepoint_func {\n\tvoid *func;\n\tvoid *data;\n\tint prio;\n};\n\nstruct tracepoint {\n\tconst char *name;\n\tstruct static_key key;\n\tint (*regfunc)();\n\tvoid (*unregfunc)();\n\tstruct tracepoint_func *funcs;\n};\n\nstruct desc_ptr {\n\tshort unsigned int size;\n\tlong unsigned int address;\n} __attribute__((packed));\n\nstruct cpuinfo_x86 {\n\t__u8 x86;\n\t__u8 x86_vendor;\n\t__u8 x86_model;\n\t__u8 x86_stepping;\n\tint x86_tlbsize;\n\t__u32 vmx_capability[3];\n\t__u8 x86_virt_bits;\n\t__u8 x86_phys_bits;\n\t__u8 x86_coreid_bits;\n\t__u8 cu_id;\n\t__u32 extended_cpuid_level;\n\tint cpuid_level;\n\tunion {\n\t\t__u32 x86_capability[20];\n\t\tlong unsigned int x86_capability_alignment;\n\t};\n\tchar x86_vendor_id[16];\n\tchar x86_model_id[64];\n\tunsigned int x86_cache_size;\n\tint x86_cache_alignment;\n\tint x86_cache_max_rmid;\n\tint x86_cache_occ_scale;\n\tint x86_cache_mbm_width_offset;\n\tint x86_power;\n\tlong unsigned int loops_per_jiffy;\n\tu16 x86_max_cores;\n\tu16 apicid;\n\tu16 initial_apicid;\n\tu16 x86_clflush_size;\n\tu16 booted_cores;\n\tu16 phys_proc_id;\n\tu16 logical_proc_id;\n\tu16 cpu_core_id;\n\tu16 cpu_die_id;\n\tu16 logical_die_id;\n\tu16 cpu_index;\n\tu32 microcode;\n\tu8 x86_cache_bits;\n\tunsigned int initialized: 1;\n};\n\nstruct seq_operations {\n\tvoid * (*start)(struct seq_file *, loff_t *);\n\tvoid (*stop)(struct seq_file *, void *);\n\tvoid * (*next)(struct seq_file *, void *, loff_t *);\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct x86_hw_tss {\n\tu32 reserved1;\n\tu64 sp0;\n\tu64 sp1;\n\tu64 sp2;\n\tu64 reserved2;\n\tu64 ist[7];\n\tu32 reserved3;\n\tu32 reserved4;\n\tu16 reserved5;\n\tu16 io_bitmap_base;\n} __attribute__((packed));\n\nstruct entry_stack {\n\tchar stack[4096];\n};\n\nstruct entry_stack_page {\n\tstruct entry_stack stack;\n};\n\nstruct x86_io_bitmap {\n\tu64 prev_sequence;\n\tunsigned int prev_max;\n\tlong unsigned int bitmap[1025];\n\tlong unsigned int mapall[1025];\n};\n\nstruct tss_struct {\n\tstruct x86_hw_tss x86_tss;\n\tstruct x86_io_bitmap io_bitmap;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct irq_stack {\n\tchar stack[16384];\n};\n\nstruct fixed_percpu_data {\n\tchar gs_base[40];\n\tlong unsigned int stack_canary;\n};\n\nenum l1tf_mitigations {\n\tL1TF_MITIGATION_OFF = 0,\n\tL1TF_MITIGATION_FLUSH_NOWARN = 1,\n\tL1TF_MITIGATION_FLUSH = 2,\n\tL1TF_MITIGATION_FLUSH_NOSMT = 3,\n\tL1TF_MITIGATION_FULL = 4,\n\tL1TF_MITIGATION_FULL_FORCE = 5,\n};\n\nstruct mpc_table {\n\tchar signature[4];\n\tshort unsigned int length;\n\tchar spec;\n\tchar checksum;\n\tchar oem[8];\n\tchar productid[12];\n\tunsigned int oemptr;\n\tshort unsigned int oemsize;\n\tshort unsigned int oemcount;\n\tunsigned int lapic;\n\tunsigned int reserved;\n};\n\nstruct mpc_cpu {\n\tunsigned char type;\n\tunsigned char apicid;\n\tunsigned char apicver;\n\tunsigned char cpuflag;\n\tunsigned int cpufeature;\n\tunsigned int featureflag;\n\tunsigned int reserved[2];\n};\n\nstruct mpc_bus {\n\tunsigned char type;\n\tunsigned char busid;\n\tunsigned char bustype[6];\n};\n\nstruct mpc_intsrc {\n\tunsigned char type;\n\tunsigned char irqtype;\n\tshort unsigned int irqflag;\n\tunsigned char srcbus;\n\tunsigned char srcbusirq;\n\tunsigned char dstapic;\n\tunsigned char dstirq;\n};\n\nstruct x86_init_mpparse {\n\tvoid (*mpc_record)(unsigned int);\n\tvoid (*setup_ioapic_ids)();\n\tint (*mpc_apic_id)(struct mpc_cpu *);\n\tvoid (*smp_read_mpc_oem)(struct mpc_table *);\n\tvoid (*mpc_oem_pci_bus)(struct mpc_bus *);\n\tvoid (*mpc_oem_bus_info)(struct mpc_bus *, char *);\n\tvoid (*find_smp_config)();\n\tvoid (*get_smp_config)(unsigned int);\n};\n\nstruct x86_init_resources {\n\tvoid (*probe_roms)();\n\tvoid (*reserve_resources)();\n\tchar * (*memory_setup)();\n};\n\nstruct x86_init_irqs {\n\tvoid (*pre_vector_init)();\n\tvoid (*intr_init)();\n\tvoid (*intr_mode_select)();\n\tvoid (*intr_mode_init)();\n};\n\nstruct x86_init_oem {\n\tvoid (*arch_setup)();\n\tvoid (*banner)();\n};\n\nstruct x86_init_paging {\n\tvoid (*pagetable_init)();\n};\n\nstruct x86_init_timers {\n\tvoid (*setup_percpu_clockev)();\n\tvoid (*timer_init)();\n\tvoid (*wallclock_init)();\n};\n\nstruct x86_init_iommu {\n\tint (*iommu_init)();\n};\n\nstruct x86_init_pci {\n\tint (*arch_init)();\n\tint (*init)();\n\tvoid (*init_irq)();\n\tvoid (*fixup_irqs)();\n};\n\nstruct x86_hyper_init {\n\tvoid (*init_platform)();\n\tvoid (*guest_late_init)();\n\tbool (*x2apic_available)();\n\tvoid (*init_mem_mapping)();\n\tvoid (*init_after_bootmem)();\n};\n\nstruct x86_init_acpi {\n\tvoid (*set_root_pointer)(u64);\n\tu64 (*get_root_pointer)();\n\tvoid (*reduced_hw_early_init)();\n};\n\nstruct x86_init_ops {\n\tstruct x86_init_resources resources;\n\tstruct x86_init_mpparse mpparse;\n\tstruct x86_init_irqs irqs;\n\tstruct x86_init_oem oem;\n\tstruct x86_init_paging paging;\n\tstruct x86_init_timers timers;\n\tstruct x86_init_iommu iommu;\n\tstruct x86_init_pci pci;\n\tstruct x86_hyper_init hyper;\n\tstruct x86_init_acpi acpi;\n};\n\nstruct x86_cpuinit_ops {\n\tvoid (*setup_percpu_clockev)();\n\tvoid (*early_percpu_clock_init)();\n\tvoid (*fixup_cpu_id)(struct cpuinfo_x86 *, int);\n};\n\nstruct x86_legacy_devices {\n\tint pnpbios;\n};\n\nenum x86_legacy_i8042_state {\n\tX86_LEGACY_I8042_PLATFORM_ABSENT = 0,\n\tX86_LEGACY_I8042_FIRMWARE_ABSENT = 1,\n\tX86_LEGACY_I8042_EXPECTED_PRESENT = 2,\n};\n\nstruct x86_legacy_features {\n\tenum x86_legacy_i8042_state i8042;\n\tint rtc;\n\tint warm_reset;\n\tint no_vga;\n\tint reserve_bios_regions;\n\tstruct x86_legacy_devices devices;\n};\n\nstruct x86_hyper_runtime {\n\tvoid (*pin_vcpu)(int);\n};\n\nstruct x86_platform_ops {\n\tlong unsigned int (*calibrate_cpu)();\n\tlong unsigned int (*calibrate_tsc)();\n\tvoid (*get_wallclock)(struct timespec64 *);\n\tint (*set_wallclock)(const struct timespec64 *);\n\tvoid (*iommu_shutdown)();\n\tbool (*is_untracked_pat_range)(u64, u64);\n\tvoid (*nmi_init)();\n\tunsigned char (*get_nmi_reason)();\n\tvoid (*save_sched_clock_state)();\n\tvoid (*restore_sched_clock_state)();\n\tvoid (*apic_post_init)();\n\tstruct x86_legacy_features legacy;\n\tvoid (*set_legacy_features)();\n\tstruct x86_hyper_runtime hyper;\n};\n\nstruct pci_dev;\n\nstruct x86_msi_ops {\n\tint (*setup_msi_irqs)(struct pci_dev *, int, int);\n\tvoid (*teardown_msi_irq)(unsigned int);\n\tvoid (*teardown_msi_irqs)(struct pci_dev *);\n\tvoid (*restore_msi_irqs)(struct pci_dev *);\n};\n\nstruct x86_apic_ops {\n\tunsigned int (*io_apic_read)(unsigned int, unsigned int);\n\tvoid (*restore)();\n};\n\nstruct physid_mask {\n\tlong unsigned int mask[512];\n};\n\ntypedef struct physid_mask physid_mask_t;\n\nstruct qrwlock {\n\tunion {\n\t\tatomic_t cnts;\n\t\tstruct {\n\t\t\tu8 wlocked;\n\t\t\tu8 __lstate[3];\n\t\t};\n\t};\n\tarch_spinlock_t wait_lock;\n};\n\ntypedef struct qrwlock arch_rwlock_t;\n\ntypedef struct {\n\tarch_rwlock_t raw_lock;\n} rwlock_t;\n\nstruct rw_semaphore {\n\tatomic_long_t count;\n\tatomic_long_t owner;\n\tstruct optimistic_spin_queue osq;\n\traw_spinlock_t wait_lock;\n\tstruct list_head wait_list;\n};\n\nstruct vdso_image {\n\tvoid *data;\n\tlong unsigned int size;\n\tlong unsigned int alt;\n\tlong unsigned int alt_len;\n\tlong int sym_vvar_start;\n\tlong int sym_vvar_page;\n\tlong int sym_pvclock_page;\n\tlong int sym_hvclock_page;\n\tlong int sym_timens_page;\n\tlong int sym_VDSO32_NOTE_MASK;\n\tlong int sym___kernel_sigreturn;\n\tlong int sym___kernel_rt_sigreturn;\n\tlong int sym___kernel_vsyscall;\n\tlong int sym_int80_landing_pad;\n};\n\nstruct ldt_struct;\n\ntypedef struct {\n\tu64 ctx_id;\n\tatomic64_t tlb_gen;\n\tstruct rw_semaphore ldt_usr_sem;\n\tstruct ldt_struct *ldt;\n\tshort unsigned int ia32_compat;\n\tstruct mutex lock;\n\tvoid *vdso;\n\tconst struct vdso_image *vdso_image;\n\tatomic_t perf_rdpmc_allowed;\n\tu16 pkey_allocation_map;\n\ts16 execute_only_pkey;\n} mm_context_t;\n\nstruct kref {\n\trefcount_t refcount;\n};\n\nstruct kset;\n\nstruct kobj_type;\n\nstruct kernfs_node;\n\nstruct kobject {\n\tconst char *name;\n\tstruct list_head entry;\n\tstruct kobject *parent;\n\tstruct kset *kset;\n\tstruct kobj_type *ktype;\n\tstruct kernfs_node *sd;\n\tstruct kref kref;\n\tunsigned int state_initialized: 1;\n\tunsigned int state_in_sysfs: 1;\n\tunsigned int state_add_uevent_sent: 1;\n\tunsigned int state_remove_uevent_sent: 1;\n\tunsigned int uevent_suppress: 1;\n};\n\nenum dl_dev_state {\n\tDL_DEV_NO_DRIVER = 0,\n\tDL_DEV_PROBING = 1,\n\tDL_DEV_DRIVER_BOUND = 2,\n\tDL_DEV_UNBINDING = 3,\n};\n\nstruct dev_links_info {\n\tstruct list_head suppliers;\n\tstruct list_head consumers;\n\tstruct list_head needs_suppliers;\n\tstruct list_head defer_hook;\n\tbool need_for_probe;\n\tenum dl_dev_state status;\n};\n\nstruct pm_message {\n\tint event;\n};\n\ntypedef struct pm_message pm_message_t;\n\nstruct swait_queue_head {\n\traw_spinlock_t lock;\n\tstruct list_head task_list;\n};\n\nstruct completion {\n\tunsigned int done;\n\tstruct swait_queue_head wait;\n};\n\nstruct work_struct;\n\ntypedef void (*work_func_t)(struct work_struct *);\n\nstruct work_struct {\n\tatomic_long_t data;\n\tstruct list_head entry;\n\twork_func_t func;\n};\n\nstruct wait_queue_head {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\ntypedef struct wait_queue_head wait_queue_head_t;\n\nenum rpm_request {\n\tRPM_REQ_NONE = 0,\n\tRPM_REQ_IDLE = 1,\n\tRPM_REQ_SUSPEND = 2,\n\tRPM_REQ_AUTOSUSPEND = 3,\n\tRPM_REQ_RESUME = 4,\n};\n\nenum rpm_status {\n\tRPM_ACTIVE = 0,\n\tRPM_RESUMING = 1,\n\tRPM_SUSPENDED = 2,\n\tRPM_SUSPENDING = 3,\n};\n\nstruct wakeup_source;\n\nstruct wake_irq;\n\nstruct pm_subsys_data;\n\nstruct device;\n\nstruct dev_pm_qos;\n\nstruct dev_pm_info {\n\tpm_message_t power_state;\n\tunsigned int can_wakeup: 1;\n\tunsigned int async_suspend: 1;\n\tbool in_dpm_list: 1;\n\tbool is_prepared: 1;\n\tbool is_suspended: 1;\n\tbool is_noirq_suspended: 1;\n\tbool is_late_suspended: 1;\n\tbool no_pm: 1;\n\tbool early_init: 1;\n\tbool direct_complete: 1;\n\tu32 driver_flags;\n\tspinlock_t lock;\n\tstruct list_head entry;\n\tstruct completion completion;\n\tstruct wakeup_source *wakeup;\n\tbool wakeup_path: 1;\n\tbool syscore: 1;\n\tbool no_pm_callbacks: 1;\n\tunsigned int must_resume: 1;\n\tunsigned int may_skip_resume: 1;\n\tstruct hrtimer suspend_timer;\n\tlong unsigned int timer_expires;\n\tstruct work_struct work;\n\twait_queue_head_t wait_queue;\n\tstruct wake_irq *wakeirq;\n\tatomic_t usage_count;\n\tatomic_t child_count;\n\tunsigned int disable_depth: 3;\n\tunsigned int idle_notification: 1;\n\tunsigned int request_pending: 1;\n\tunsigned int deferred_resume: 1;\n\tunsigned int runtime_auto: 1;\n\tbool ignore_children: 1;\n\tunsigned int no_callbacks: 1;\n\tunsigned int irq_safe: 1;\n\tunsigned int use_autosuspend: 1;\n\tunsigned int timer_autosuspends: 1;\n\tunsigned int memalloc_noio: 1;\n\tunsigned int links_count;\n\tenum rpm_request request;\n\tenum rpm_status runtime_status;\n\tint runtime_error;\n\tint autosuspend_delay;\n\tu64 last_busy;\n\tu64 active_time;\n\tu64 suspended_time;\n\tu64 accounting_timestamp;\n\tstruct pm_subsys_data *subsys_data;\n\tvoid (*set_latency_tolerance)(struct device *, s32);\n\tstruct dev_pm_qos *qos;\n};\n\nstruct dev_archdata {\n\tvoid *iommu;\n};\n\nstruct device_private;\n\nstruct device_type;\n\nstruct bus_type;\n\nstruct device_driver;\n\nstruct dev_pm_domain;\n\nstruct irq_domain;\n\nstruct dma_map_ops;\n\nstruct device_dma_parameters;\n\nstruct device_node;\n\nstruct fwnode_handle;\n\nstruct class;\n\nstruct attribute_group;\n\nstruct iommu_group;\n\nstruct dev_iommu;\n\nstruct device {\n\tstruct kobject kobj;\n\tstruct device *parent;\n\tstruct device_private *p;\n\tconst char *init_name;\n\tconst struct device_type *type;\n\tstruct bus_type *bus;\n\tstruct device_driver *driver;\n\tvoid *platform_data;\n\tvoid *driver_data;\n\tstruct mutex mutex;\n\tstruct dev_links_info links;\n\tstruct dev_pm_info power;\n\tstruct dev_pm_domain *pm_domain;\n\tstruct irq_domain *msi_domain;\n\tstruct list_head msi_list;\n\tconst struct dma_map_ops *dma_ops;\n\tu64 *dma_mask;\n\tu64 coherent_dma_mask;\n\tu64 bus_dma_limit;\n\tlong unsigned int dma_pfn_offset;\n\tstruct device_dma_parameters *dma_parms;\n\tstruct list_head dma_pools;\n\tstruct dev_archdata archdata;\n\tstruct device_node *of_node;\n\tstruct fwnode_handle *fwnode;\n\tint numa_node;\n\tdev_t devt;\n\tu32 id;\n\tspinlock_t devres_lock;\n\tstruct list_head devres_head;\n\tstruct class *class;\n\tconst struct attribute_group **groups;\n\tvoid (*release)(struct device *);\n\tstruct iommu_group *iommu_group;\n\tstruct dev_iommu *iommu;\n\tbool offline_disabled: 1;\n\tbool offline: 1;\n\tbool of_node_reused: 1;\n\tbool state_synced: 1;\n};\n\nenum fixed_addresses {\n\tVSYSCALL_PAGE = 511,\n\tFIX_DBGP_BASE = 512,\n\tFIX_EARLYCON_MEM_BASE = 513,\n\tFIX_OHCI1394_BASE = 514,\n\tFIX_APIC_BASE = 515,\n\tFIX_IO_APIC_BASE_0 = 516,\n\tFIX_IO_APIC_BASE_END = 643,\n\t__end_of_permanent_fixed_addresses = 644,\n\tFIX_BTMAP_END = 1024,\n\tFIX_BTMAP_BEGIN = 1535,\n\t__end_of_fixed_addresses = 1536,\n};\n\nstruct vm_userfaultfd_ctx {};\n\nstruct anon_vma;\n\nstruct vm_operations_struct;\n\nstruct vm_area_struct {\n\tlong unsigned int vm_start;\n\tlong unsigned int vm_end;\n\tstruct vm_area_struct *vm_next;\n\tstruct vm_area_struct *vm_prev;\n\tstruct rb_node vm_rb;\n\tlong unsigned int rb_subtree_gap;\n\tstruct mm_struct *vm_mm;\n\tpgprot_t vm_page_prot;\n\tlong unsigned int vm_flags;\n\tstruct {\n\t\tstruct rb_node rb;\n\t\tlong unsigned int rb_subtree_last;\n\t} shared;\n\tstruct list_head anon_vma_chain;\n\tstruct anon_vma *anon_vma;\n\tconst struct vm_operations_struct *vm_ops;\n\tlong unsigned int vm_pgoff;\n\tstruct file *vm_file;\n\tvoid *vm_private_data;\n\tatomic_long_t swap_readahead_info;\n\tstruct mempolicy *vm_policy;\n\tstruct vm_userfaultfd_ctx vm_userfaultfd_ctx;\n};\n\nstruct mm_rss_stat {\n\tatomic_long_t count[4];\n};\n\nstruct xol_area;\n\nstruct uprobes_state {\n\tstruct xol_area *xol_area;\n};\n\nstruct linux_binfmt;\n\nstruct core_state;\n\nstruct kioctx_table;\n\nstruct user_namespace;\n\nstruct mmu_notifier_subscriptions;\n\nstruct mm_struct {\n\tstruct {\n\t\tstruct vm_area_struct *mmap;\n\t\tstruct rb_root mm_rb;\n\t\tu64 vmacache_seqnum;\n\t\tlong unsigned int (*get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\t\tlong unsigned int mmap_base;\n\t\tlong unsigned int mmap_legacy_base;\n\t\tlong unsigned int mmap_compat_base;\n\t\tlong unsigned int mmap_compat_legacy_base;\n\t\tlong unsigned int task_size;\n\t\tlong unsigned int highest_vm_end;\n\t\tpgd_t *pgd;\n\t\tatomic_t membarrier_state;\n\t\tatomic_t mm_users;\n\t\tatomic_t mm_count;\n\t\tatomic_long_t pgtables_bytes;\n\t\tint map_count;\n\t\tspinlock_t page_table_lock;\n\t\tstruct rw_semaphore mmap_lock;\n\t\tstruct list_head mmlist;\n\t\tlong unsigned int hiwater_rss;\n\t\tlong unsigned int hiwater_vm;\n\t\tlong unsigned int total_vm;\n\t\tlong unsigned int locked_vm;\n\t\tatomic64_t pinned_vm;\n\t\tlong unsigned int data_vm;\n\t\tlong unsigned int exec_vm;\n\t\tlong unsigned int stack_vm;\n\t\tlong unsigned int def_flags;\n\t\tspinlock_t arg_lock;\n\t\tlong unsigned int start_code;\n\t\tlong unsigned int end_code;\n\t\tlong unsigned int start_data;\n\t\tlong unsigned int end_data;\n\t\tlong unsigned int start_brk;\n\t\tlong unsigned int brk;\n\t\tlong unsigned int start_stack;\n\t\tlong unsigned int arg_start;\n\t\tlong unsigned int arg_end;\n\t\tlong unsigned int env_start;\n\t\tlong unsigned int env_end;\n\t\tlong unsigned int saved_auxv[46];\n\t\tstruct mm_rss_stat rss_stat;\n\t\tstruct linux_binfmt *binfmt;\n\t\tmm_context_t context;\n\t\tlong unsigned int flags;\n\t\tstruct core_state *core_state;\n\t\tspinlock_t ioctx_lock;\n\t\tstruct kioctx_table *ioctx_table;\n\t\tstruct user_namespace *user_ns;\n\t\tstruct file *exe_file;\n\t\tstruct mmu_notifier_subscriptions *notifier_subscriptions;\n\t\tatomic_t tlb_flush_pending;\n\t\tbool tlb_flush_batched;\n\t\tstruct uprobes_state uprobes_state;\n\t\tatomic_long_t hugetlb_usage;\n\t\tstruct work_struct async_put_work;\n\t};\n\tlong unsigned int cpu_bitmap[0];\n};\n\ntypedef struct {\n\tstruct seqcount seqcount;\n\tspinlock_t lock;\n} seqlock_t;\n\nstruct timer_list {\n\tstruct hlist_node entry;\n\tlong unsigned int expires;\n\tvoid (*function)(struct timer_list *);\n\tu32 flags;\n};\n\ntypedef int (*notifier_fn_t)(struct notifier_block *, long unsigned int, void *);\n\nstruct notifier_block {\n\tnotifier_fn_t notifier_call;\n\tstruct notifier_block *next;\n\tint priority;\n};\n\nstruct blocking_notifier_head {\n\tstruct rw_semaphore rwsem;\n\tstruct notifier_block *head;\n};\n\nstruct arch_uprobe_task {\n\tlong unsigned int saved_scratch_register;\n\tunsigned int saved_trap_nr;\n\tunsigned int saved_tf;\n};\n\nenum uprobe_task_state {\n\tUTASK_RUNNING = 0,\n\tUTASK_SSTEP = 1,\n\tUTASK_SSTEP_ACK = 2,\n\tUTASK_SSTEP_TRAPPED = 3,\n};\n\nstruct uprobe;\n\nstruct return_instance;\n\nstruct uprobe_task {\n\tenum uprobe_task_state state;\n\tunion {\n\t\tstruct {\n\t\t\tstruct arch_uprobe_task autask;\n\t\t\tlong unsigned int vaddr;\n\t\t};\n\t\tstruct {\n\t\t\tstruct callback_head dup_xol_work;\n\t\t\tlong unsigned int dup_xol_addr;\n\t\t};\n\t};\n\tstruct uprobe *active_uprobe;\n\tlong unsigned int xol_vaddr;\n\tstruct return_instance *return_instances;\n\tunsigned int depth;\n};\n\nstruct return_instance {\n\tstruct uprobe *uprobe;\n\tlong unsigned int func;\n\tlong unsigned int stack;\n\tlong unsigned int orig_ret_vaddr;\n\tbool chained;\n\tstruct return_instance *next;\n};\n\nstruct xarray {\n\tspinlock_t xa_lock;\n\tgfp_t xa_flags;\n\tvoid *xa_head;\n};\n\ntypedef u32 errseq_t;\n\nstruct address_space_operations;\n\nstruct address_space {\n\tstruct inode *host;\n\tstruct xarray i_pages;\n\tgfp_t gfp_mask;\n\tatomic_t i_mmap_writable;\n\tstruct rb_root_cached i_mmap;\n\tstruct rw_semaphore i_mmap_rwsem;\n\tlong unsigned int nrpages;\n\tlong unsigned int nrexceptional;\n\tlong unsigned int writeback_index;\n\tconst struct address_space_operations *a_ops;\n\tlong unsigned int flags;\n\terrseq_t wb_err;\n\tspinlock_t private_lock;\n\tstruct list_head private_list;\n\tvoid *private_data;\n};\n\nstruct vmem_altmap {\n\tconst long unsigned int base_pfn;\n\tconst long unsigned int end_pfn;\n\tconst long unsigned int reserve;\n\tlong unsigned int free;\n\tlong unsigned int align;\n\tlong unsigned int alloc;\n};\n\nstruct resource {\n\tresource_size_t start;\n\tresource_size_t end;\n\tconst char *name;\n\tlong unsigned int flags;\n\tlong unsigned int desc;\n\tstruct resource *parent;\n\tstruct resource *sibling;\n\tstruct resource *child;\n};\n\nstruct percpu_ref;\n\ntypedef void percpu_ref_func_t(struct percpu_ref *);\n\nstruct percpu_ref {\n\tatomic_long_t count;\n\tlong unsigned int percpu_count_ptr;\n\tpercpu_ref_func_t *release;\n\tpercpu_ref_func_t *confirm_switch;\n\tbool force_atomic: 1;\n\tbool allow_reinit: 1;\n\tstruct callback_head rcu;\n};\n\nenum memory_type {\n\tMEMORY_DEVICE_PRIVATE = 1,\n\tMEMORY_DEVICE_FS_DAX = 2,\n\tMEMORY_DEVICE_DEVDAX = 3,\n\tMEMORY_DEVICE_PCI_P2PDMA = 4,\n};\n\nstruct dev_pagemap_ops;\n\nstruct dev_pagemap {\n\tstruct vmem_altmap altmap;\n\tstruct resource res;\n\tstruct percpu_ref *ref;\n\tstruct percpu_ref internal_ref;\n\tstruct completion done;\n\tenum memory_type type;\n\tunsigned int flags;\n\tconst struct dev_pagemap_ops *ops;\n\tvoid *owner;\n};\n\nstruct vfsmount;\n\nstruct path {\n\tstruct vfsmount *mnt;\n\tstruct dentry *dentry;\n};\n\nenum rw_hint {\n\tWRITE_LIFE_NOT_SET = 0,\n\tWRITE_LIFE_NONE = 1,\n\tWRITE_LIFE_SHORT = 2,\n\tWRITE_LIFE_MEDIUM = 3,\n\tWRITE_LIFE_LONG = 4,\n\tWRITE_LIFE_EXTREME = 5,\n};\n\nenum pid_type {\n\tPIDTYPE_PID = 0,\n\tPIDTYPE_TGID = 1,\n\tPIDTYPE_PGID = 2,\n\tPIDTYPE_SID = 3,\n\tPIDTYPE_MAX = 4,\n};\n\nstruct fown_struct {\n\trwlock_t lock;\n\tstruct pid *pid;\n\tenum pid_type pid_type;\n\tkuid_t uid;\n\tkuid_t euid;\n\tint signum;\n};\n\nstruct file_ra_state {\n\tlong unsigned int start;\n\tunsigned int size;\n\tunsigned int async_size;\n\tunsigned int ra_pages;\n\tunsigned int mmap_miss;\n\tloff_t prev_pos;\n};\n\nstruct file {\n\tunion {\n\t\tstruct llist_node fu_llist;\n\t\tstruct callback_head fu_rcuhead;\n\t} f_u;\n\tstruct path f_path;\n\tstruct inode *f_inode;\n\tconst struct file_operations *f_op;\n\tspinlock_t f_lock;\n\tenum rw_hint f_write_hint;\n\tatomic_long_t f_count;\n\tunsigned int f_flags;\n\tfmode_t f_mode;\n\tstruct mutex f_pos_lock;\n\tloff_t f_pos;\n\tstruct fown_struct f_owner;\n\tconst struct cred *f_cred;\n\tstruct file_ra_state f_ra;\n\tu64 f_version;\n\tvoid *f_security;\n\tvoid *private_data;\n\tstruct list_head f_ep_links;\n\tstruct list_head f_tfile_llink;\n\tstruct address_space *f_mapping;\n\terrseq_t f_wb_err;\n\terrseq_t f_sb_err;\n};\n\ntypedef unsigned int vm_fault_t;\n\nenum page_entry_size {\n\tPE_SIZE_PTE = 0,\n\tPE_SIZE_PMD = 1,\n\tPE_SIZE_PUD = 2,\n};\n\nstruct vm_fault;\n\nstruct vm_operations_struct {\n\tvoid (*open)(struct vm_area_struct *);\n\tvoid (*close)(struct vm_area_struct *);\n\tint (*split)(struct vm_area_struct *, long unsigned int);\n\tint (*mremap)(struct vm_area_struct *);\n\tvm_fault_t (*fault)(struct vm_fault *);\n\tvm_fault_t (*huge_fault)(struct vm_fault *, enum page_entry_size);\n\tvoid (*map_pages)(struct vm_fault *, long unsigned int, long unsigned int);\n\tlong unsigned int (*pagesize)(struct vm_area_struct *);\n\tvm_fault_t (*page_mkwrite)(struct vm_fault *);\n\tvm_fault_t (*pfn_mkwrite)(struct vm_fault *);\n\tint (*access)(struct vm_area_struct *, long unsigned int, void *, int, int);\n\tconst char * (*name)(struct vm_area_struct *);\n\tint (*set_policy)(struct vm_area_struct *, struct mempolicy *);\n\tstruct mempolicy * (*get_policy)(struct vm_area_struct *, long unsigned int);\n\tstruct page * (*find_special_page)(struct vm_area_struct *, long unsigned int);\n};\n\nstruct core_thread {\n\tstruct task_struct *task;\n\tstruct core_thread *next;\n};\n\nstruct core_state {\n\tatomic_t nr_threads;\n\tstruct core_thread dumper;\n\tstruct completion startup;\n};\n\nstruct vm_fault {\n\tstruct vm_area_struct *vma;\n\tunsigned int flags;\n\tgfp_t gfp_mask;\n\tlong unsigned int pgoff;\n\tlong unsigned int address;\n\tpmd_t *pmd;\n\tpud_t *pud;\n\tpte_t orig_pte;\n\tstruct page *cow_page;\n\tstruct page *page;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tpgtable_t prealloc_pte;\n};\n\ntypedef struct {\n\tu16 __softirq_pending;\n\tunsigned int __nmi_count;\n\tunsigned int apic_timer_irqs;\n\tunsigned int irq_spurious_count;\n\tunsigned int icr_read_retry_count;\n\tunsigned int kvm_posted_intr_ipis;\n\tunsigned int kvm_posted_intr_wakeup_ipis;\n\tunsigned int kvm_posted_intr_nested_ipis;\n\tunsigned int x86_platform_ipis;\n\tunsigned int apic_perf_irqs;\n\tunsigned int apic_irq_work_irqs;\n\tunsigned int irq_resched_count;\n\tunsigned int irq_call_count;\n\tunsigned int irq_tlb_count;\n\tunsigned int irq_thermal_count;\n\tunsigned int irq_threshold_count;\n\tunsigned int irq_deferred_error_count;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n} irq_cpustat_t;\n\nenum apic_intr_mode_id {\n\tAPIC_PIC = 0,\n\tAPIC_VIRTUAL_WIRE = 1,\n\tAPIC_VIRTUAL_WIRE_NO_CONFIG = 2,\n\tAPIC_SYMMETRIC_IO = 3,\n\tAPIC_SYMMETRIC_IO_NO_ROUTING = 4,\n};\n\nstruct apic {\n\tvoid (*eoi_write)(u32, u32);\n\tvoid (*native_eoi_write)(u32, u32);\n\tvoid (*write)(u32, u32);\n\tu32 (*read)(u32);\n\tvoid (*wait_icr_idle)();\n\tu32 (*safe_wait_icr_idle)();\n\tvoid (*send_IPI)(int, int);\n\tvoid (*send_IPI_mask)(const struct cpumask *, int);\n\tvoid (*send_IPI_mask_allbutself)(const struct cpumask *, int);\n\tvoid (*send_IPI_allbutself)(int);\n\tvoid (*send_IPI_all)(int);\n\tvoid (*send_IPI_self)(int);\n\tu32 dest_logical;\n\tu32 disable_esr;\n\tu32 irq_delivery_mode;\n\tu32 irq_dest_mode;\n\tu32 (*calc_dest_apicid)(unsigned int);\n\tu64 (*icr_read)();\n\tvoid (*icr_write)(u32, u32);\n\tint (*probe)();\n\tint (*acpi_madt_oem_check)(char *, char *);\n\tint (*apic_id_valid)(u32);\n\tint (*apic_id_registered)();\n\tbool (*check_apicid_used)(physid_mask_t *, int);\n\tvoid (*init_apic_ldr)();\n\tvoid (*ioapic_phys_id_map)(physid_mask_t *, physid_mask_t *);\n\tvoid (*setup_apic_routing)();\n\tint (*cpu_present_to_apicid)(int);\n\tvoid (*apicid_to_cpu_present)(int, physid_mask_t *);\n\tint (*check_phys_apicid_present)(int);\n\tint (*phys_pkg_id)(int, int);\n\tu32 (*get_apic_id)(long unsigned int);\n\tu32 (*set_apic_id)(unsigned int);\n\tint (*wakeup_secondary_cpu)(int, long unsigned int);\n\tvoid (*inquire_remote_apic)(int);\n\tchar *name;\n};\n\nstruct smp_ops {\n\tvoid (*smp_prepare_boot_cpu)();\n\tvoid (*smp_prepare_cpus)(unsigned int);\n\tvoid (*smp_cpus_done)(unsigned int);\n\tvoid (*stop_other_cpus)(int);\n\tvoid (*crash_stop_other_cpus)();\n\tvoid (*smp_send_reschedule)(int);\n\tint (*cpu_up)(unsigned int, struct task_struct *);\n\tint (*cpu_disable)();\n\tvoid (*cpu_die)(unsigned int);\n\tvoid (*play_dead)();\n\tvoid (*send_call_func_ipi)(const struct cpumask *);\n\tvoid (*send_call_func_single_ipi)(int);\n};\n\nenum pcpu_fc {\n\tPCPU_FC_AUTO = 0,\n\tPCPU_FC_EMBED = 1,\n\tPCPU_FC_PAGE = 2,\n\tPCPU_FC_NR = 3,\n};\n\nstruct fwnode_operations;\n\nstruct fwnode_handle {\n\tstruct fwnode_handle *secondary;\n\tconst struct fwnode_operations *ops;\n\tstruct device *dev;\n};\n\nstruct fwnode_reference_args;\n\nstruct fwnode_endpoint;\n\nstruct fwnode_operations {\n\tstruct fwnode_handle * (*get)(struct fwnode_handle *);\n\tvoid (*put)(struct fwnode_handle *);\n\tbool (*device_is_available)(const struct fwnode_handle *);\n\tconst void * (*device_get_match_data)(const struct fwnode_handle *, const struct device *);\n\tbool (*property_present)(const struct fwnode_handle *, const char *);\n\tint (*property_read_int_array)(const struct fwnode_handle *, const char *, unsigned int, void *, size_t);\n\tint (*property_read_string_array)(const struct fwnode_handle *, const char *, const char **, size_t);\n\tconst char * (*get_name)(const struct fwnode_handle *);\n\tconst char * (*get_name_prefix)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_parent)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_next_child_node)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*get_named_child_node)(const struct fwnode_handle *, const char *);\n\tint (*get_reference_args)(const struct fwnode_handle *, const char *, const char *, unsigned int, unsigned int, struct fwnode_reference_args *);\n\tstruct fwnode_handle * (*graph_get_next_endpoint)(const struct fwnode_handle *, struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_remote_endpoint)(const struct fwnode_handle *);\n\tstruct fwnode_handle * (*graph_get_port_parent)(struct fwnode_handle *);\n\tint (*graph_parse_endpoint)(const struct fwnode_handle *, struct fwnode_endpoint *);\n\tint (*add_links)(const struct fwnode_handle *, struct device *);\n};\n\nstruct fwnode_endpoint {\n\tunsigned int port;\n\tunsigned int id;\n\tconst struct fwnode_handle *local_fwnode;\n};\n\nstruct fwnode_reference_args {\n\tstruct fwnode_handle *fwnode;\n\tunsigned int nargs;\n\tu64 args[8];\n};\n\nstruct vm_struct {\n\tstruct vm_struct *next;\n\tvoid *addr;\n\tlong unsigned int size;\n\tlong unsigned int flags;\n\tstruct page **pages;\n\tunsigned int nr_pages;\n\tphys_addr_t phys_addr;\n\tconst void *caller;\n};\n\nstruct free_area {\n\tstruct list_head free_list[4];\n\tlong unsigned int nr_free;\n};\n\nstruct zone_padding {\n\tchar x[0];\n};\n\nenum numa_stat_item {\n\tNUMA_HIT = 0,\n\tNUMA_MISS = 1,\n\tNUMA_FOREIGN = 2,\n\tNUMA_INTERLEAVE_HIT = 3,\n\tNUMA_LOCAL = 4,\n\tNUMA_OTHER = 5,\n\tNR_VM_NUMA_STAT_ITEMS = 6,\n};\n\nenum zone_stat_item {\n\tNR_FREE_PAGES = 0,\n\tNR_ZONE_LRU_BASE = 1,\n\tNR_ZONE_INACTIVE_ANON = 1,\n\tNR_ZONE_ACTIVE_ANON = 2,\n\tNR_ZONE_INACTIVE_FILE = 3,\n\tNR_ZONE_ACTIVE_FILE = 4,\n\tNR_ZONE_UNEVICTABLE = 5,\n\tNR_ZONE_WRITE_PENDING = 6,\n\tNR_MLOCK = 7,\n\tNR_PAGETABLE = 8,\n\tNR_KERNEL_STACK_KB = 9,\n\tNR_BOUNCE = 10,\n\tNR_FREE_CMA_PAGES = 11,\n\tNR_VM_ZONE_STAT_ITEMS = 12,\n};\n\nenum node_stat_item {\n\tNR_LRU_BASE = 0,\n\tNR_INACTIVE_ANON = 0,\n\tNR_ACTIVE_ANON = 1,\n\tNR_INACTIVE_FILE = 2,\n\tNR_ACTIVE_FILE = 3,\n\tNR_UNEVICTABLE = 4,\n\tNR_SLAB_RECLAIMABLE = 5,\n\tNR_SLAB_UNRECLAIMABLE = 6,\n\tNR_ISOLATED_ANON = 7,\n\tNR_ISOLATED_FILE = 8,\n\tWORKINGSET_NODES = 9,\n\tWORKINGSET_REFAULT = 10,\n\tWORKINGSET_ACTIVATE = 11,\n\tWORKINGSET_RESTORE = 12,\n\tWORKINGSET_NODERECLAIM = 13,\n\tNR_ANON_MAPPED = 14,\n\tNR_FILE_MAPPED = 15,\n\tNR_FILE_PAGES = 16,\n\tNR_FILE_DIRTY = 17,\n\tNR_WRITEBACK = 18,\n\tNR_WRITEBACK_TEMP = 19,\n\tNR_SHMEM = 20,\n\tNR_SHMEM_THPS = 21,\n\tNR_SHMEM_PMDMAPPED = 22,\n\tNR_FILE_THPS = 23,\n\tNR_FILE_PMDMAPPED = 24,\n\tNR_ANON_THPS = 25,\n\tNR_VMSCAN_WRITE = 26,\n\tNR_VMSCAN_IMMEDIATE = 27,\n\tNR_DIRTIED = 28,\n\tNR_WRITTEN = 29,\n\tNR_KERNEL_MISC_RECLAIMABLE = 30,\n\tNR_FOLL_PIN_ACQUIRED = 31,\n\tNR_FOLL_PIN_RELEASED = 32,\n\tNR_VM_NODE_STAT_ITEMS = 33,\n};\n\nstruct lruvec {\n\tstruct list_head lists[5];\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tatomic_long_t nonresident_age;\n\tlong unsigned int refaults;\n\tlong unsigned int flags;\n};\n\ntypedef unsigned int isolate_mode_t;\n\nstruct per_cpu_pages {\n\tint count;\n\tint high;\n\tint batch;\n\tstruct list_head lists[3];\n};\n\nstruct per_cpu_pageset {\n\tstruct per_cpu_pages pcp;\n\ts8 expire;\n\tu16 vm_numa_stat_diff[6];\n\ts8 stat_threshold;\n\ts8 vm_stat_diff[12];\n};\n\nstruct per_cpu_nodestat {\n\ts8 stat_threshold;\n\ts8 vm_node_stat_diff[33];\n};\n\nenum zone_type {\n\tZONE_DMA = 0,\n\tZONE_DMA32 = 1,\n\tZONE_NORMAL = 2,\n\tZONE_MOVABLE = 3,\n\t__MAX_NR_ZONES = 4,\n};\n\nstruct pglist_data;\n\nstruct zone {\n\tlong unsigned int _watermark[3];\n\tlong unsigned int watermark_boost;\n\tlong unsigned int nr_reserved_highatomic;\n\tlong int lowmem_reserve[4];\n\tint node;\n\tstruct pglist_data *zone_pgdat;\n\tstruct per_cpu_pageset *pageset;\n\tlong unsigned int zone_start_pfn;\n\tatomic_long_t managed_pages;\n\tlong unsigned int spanned_pages;\n\tlong unsigned int present_pages;\n\tconst char *name;\n\tint initialized;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct zone_padding _pad1_;\n\tstruct free_area free_area[11];\n\tlong unsigned int flags;\n\tspinlock_t lock;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct zone_padding _pad2_;\n\tlong unsigned int percpu_drift_mark;\n\tlong unsigned int compact_cached_free_pfn;\n\tlong unsigned int compact_cached_migrate_pfn[2];\n\tlong unsigned int compact_init_migrate_pfn;\n\tlong unsigned int compact_init_free_pfn;\n\tunsigned int compact_considered;\n\tunsigned int compact_defer_shift;\n\tint compact_order_failed;\n\tbool compact_blockskip_flush;\n\tbool contiguous;\n\tshort: 16;\n\tstruct zone_padding _pad3_;\n\tatomic_long_t vm_stat[12];\n\tatomic_long_t vm_numa_stat[6];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct zoneref {\n\tstruct zone *zone;\n\tint zone_idx;\n};\n\nstruct zonelist {\n\tstruct zoneref _zonerefs[257];\n};\n\nstruct pglist_data {\n\tstruct zone node_zones[4];\n\tstruct zonelist node_zonelists[2];\n\tint nr_zones;\n\tlong unsigned int node_start_pfn;\n\tlong unsigned int node_present_pages;\n\tlong unsigned int node_spanned_pages;\n\tint node_id;\n\twait_queue_head_t kswapd_wait;\n\twait_queue_head_t pfmemalloc_wait;\n\tstruct task_struct *kswapd;\n\tint kswapd_order;\n\tenum zone_type kswapd_highest_zoneidx;\n\tint kswapd_failures;\n\tint kcompactd_max_order;\n\tenum zone_type kcompactd_highest_zoneidx;\n\twait_queue_head_t kcompactd_wait;\n\tstruct task_struct *kcompactd;\n\tlong unsigned int totalreserve_pages;\n\tlong unsigned int min_unmapped_pages;\n\tlong unsigned int min_slab_pages;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct zone_padding _pad1_;\n\tspinlock_t lru_lock;\n\tstruct lruvec __lruvec;\n\tlong unsigned int flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct zone_padding _pad2_;\n\tstruct per_cpu_nodestat *per_cpu_nodestats;\n\tatomic_long_t vm_stat[33];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mem_section_usage {\n\tlong unsigned int subsection_map[1];\n\tlong unsigned int pageblock_flags[0];\n};\n\nstruct mem_section {\n\tlong unsigned int section_mem_map;\n\tstruct mem_section_usage *usage;\n};\n\nstruct mem_cgroup;\n\nstruct shrink_control {\n\tgfp_t gfp_mask;\n\tint nid;\n\tlong unsigned int nr_to_scan;\n\tlong unsigned int nr_scanned;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct shrinker {\n\tlong unsigned int (*count_objects)(struct shrinker *, struct shrink_control *);\n\tlong unsigned int (*scan_objects)(struct shrinker *, struct shrink_control *);\n\tlong int batch;\n\tint seeks;\n\tunsigned int flags;\n\tstruct list_head list;\n\tatomic_long_t *nr_deferred;\n};\n\nstruct rlimit {\n\t__kernel_ulong_t rlim_cur;\n\t__kernel_ulong_t rlim_max;\n};\n\nstruct dev_pagemap_ops {\n\tvoid (*page_free)(struct page *);\n\tvoid (*kill)(struct dev_pagemap *);\n\tvoid (*cleanup)(struct dev_pagemap *);\n\tvm_fault_t (*migrate_to_ram)(struct vm_fault *);\n};\n\nstruct pid_namespace;\n\nstruct upid {\n\tint nr;\n\tstruct pid_namespace *ns;\n};\n\nstruct pid {\n\trefcount_t count;\n\tunsigned int level;\n\tspinlock_t lock;\n\tstruct hlist_head tasks[4];\n\tstruct hlist_head inodes;\n\twait_queue_head_t wait_pidfd;\n\tstruct callback_head rcu;\n\tstruct upid numbers[1];\n};\n\ntypedef struct {\n\tgid_t val;\n} kgid_t;\n\nstruct hrtimer_cpu_base;\n\nstruct hrtimer_clock_base {\n\tstruct hrtimer_cpu_base *cpu_base;\n\tunsigned int index;\n\tclockid_t clockid;\n\tseqcount_t seq;\n\tstruct hrtimer *running;\n\tstruct timerqueue_head active;\n\tktime_t (*get_time)();\n\tktime_t offset;\n};\n\nstruct hrtimer_cpu_base {\n\traw_spinlock_t lock;\n\tunsigned int cpu;\n\tunsigned int active_bases;\n\tunsigned int clock_was_set_seq;\n\tunsigned int hres_active: 1;\n\tunsigned int in_hrtirq: 1;\n\tunsigned int hang_detected: 1;\n\tunsigned int softirq_activated: 1;\n\tunsigned int nr_events;\n\tshort unsigned int nr_retries;\n\tshort unsigned int nr_hangs;\n\tunsigned int max_hang_time;\n\tktime_t expires_next;\n\tstruct hrtimer *next_timer;\n\tktime_t softirq_expires_next;\n\tstruct hrtimer *softirq_next_timer;\n\tstruct hrtimer_clock_base clock_base[8];\n};\n\nstruct tick_device;\n\ntypedef void __signalfn_t(int);\n\ntypedef __signalfn_t *__sighandler_t;\n\ntypedef void __restorefn_t();\n\ntypedef __restorefn_t *__sigrestore_t;\n\nunion sigval {\n\tint sival_int;\n\tvoid *sival_ptr;\n};\n\ntypedef union sigval sigval_t;\n\nunion __sifields {\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t} _kill;\n\tstruct {\n\t\t__kernel_timer_t _tid;\n\t\tint _overrun;\n\t\tsigval_t _sigval;\n\t\tint _sys_private;\n\t} _timer;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tsigval_t _sigval;\n\t} _rt;\n\tstruct {\n\t\t__kernel_pid_t _pid;\n\t\t__kernel_uid32_t _uid;\n\t\tint _status;\n\t\t__kernel_clock_t _utime;\n\t\t__kernel_clock_t _stime;\n\t} _sigchld;\n\tstruct {\n\t\tvoid *_addr;\n\t\tunion {\n\t\t\tshort int _addr_lsb;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_bnd[8];\n\t\t\t\tvoid *_lower;\n\t\t\t\tvoid *_upper;\n\t\t\t} _addr_bnd;\n\t\t\tstruct {\n\t\t\t\tchar _dummy_pkey[8];\n\t\t\t\t__u32 _pkey;\n\t\t\t} _addr_pkey;\n\t\t};\n\t} _sigfault;\n\tstruct {\n\t\tlong int _band;\n\t\tint _fd;\n\t} _sigpoll;\n\tstruct {\n\t\tvoid *_call_addr;\n\t\tint _syscall;\n\t\tunsigned int _arch;\n\t} _sigsys;\n};\n\nstruct kernel_siginfo {\n\tstruct {\n\t\tint si_signo;\n\t\tint si_errno;\n\t\tint si_code;\n\t\tunion __sifields _sifields;\n\t};\n};\n\nstruct ratelimit_state {\n\traw_spinlock_t lock;\n\tint interval;\n\tint burst;\n\tint printed;\n\tint missed;\n\tlong unsigned int begin;\n\tlong unsigned int flags;\n};\n\nstruct user_struct {\n\trefcount_t __count;\n\tatomic_t processes;\n\tatomic_t sigpending;\n\tatomic_long_t epoll_watches;\n\tlong unsigned int mq_bytes;\n\tlong unsigned int locked_shm;\n\tlong unsigned int unix_inflight;\n\tatomic_long_t pipe_bufs;\n\tstruct hlist_node uidhash_node;\n\tkuid_t uid;\n\tatomic_long_t locked_vm;\n\tstruct ratelimit_state ratelimit;\n};\n\nstruct sigaction {\n\t__sighandler_t sa_handler;\n\tlong unsigned int sa_flags;\n\t__sigrestore_t sa_restorer;\n\tsigset_t sa_mask;\n};\n\nstruct k_sigaction {\n\tstruct sigaction sa;\n};\n\nstruct cpu_itimer {\n\tu64 expires;\n\tu64 incr;\n};\n\nstruct task_cputime_atomic {\n\tatomic64_t utime;\n\tatomic64_t stime;\n\tatomic64_t sum_exec_runtime;\n};\n\nstruct thread_group_cputimer {\n\tstruct task_cputime_atomic cputime_atomic;\n};\n\nstruct pacct_struct {\n\tint ac_flag;\n\tlong int ac_exitcode;\n\tlong unsigned int ac_mem;\n\tu64 ac_utime;\n\tu64 ac_stime;\n\tlong unsigned int ac_minflt;\n\tlong unsigned int ac_majflt;\n};\n\nstruct tty_struct;\n\nstruct taskstats;\n\nstruct tty_audit_buf;\n\nstruct signal_struct {\n\trefcount_t sigcnt;\n\tatomic_t live;\n\tint nr_threads;\n\tstruct list_head thread_head;\n\twait_queue_head_t wait_chldexit;\n\tstruct task_struct *curr_target;\n\tstruct sigpending shared_pending;\n\tstruct hlist_head multiprocess;\n\tint group_exit_code;\n\tint notify_count;\n\tstruct task_struct *group_exit_task;\n\tint group_stop_count;\n\tunsigned int flags;\n\tunsigned int is_child_subreaper: 1;\n\tunsigned int has_child_subreaper: 1;\n\tint posix_timer_id;\n\tstruct list_head posix_timers;\n\tstruct hrtimer real_timer;\n\tktime_t it_real_incr;\n\tstruct cpu_itimer it[2];\n\tstruct thread_group_cputimer cputimer;\n\tstruct posix_cputimers posix_cputimers;\n\tstruct pid *pids[4];\n\tstruct pid *tty_old_pgrp;\n\tint leader;\n\tstruct tty_struct *tty;\n\tseqlock_t stats_lock;\n\tu64 utime;\n\tu64 stime;\n\tu64 cutime;\n\tu64 cstime;\n\tu64 gtime;\n\tu64 cgtime;\n\tstruct prev_cputime prev_cputime;\n\tlong unsigned int nvcsw;\n\tlong unsigned int nivcsw;\n\tlong unsigned int cnvcsw;\n\tlong unsigned int cnivcsw;\n\tlong unsigned int min_flt;\n\tlong unsigned int maj_flt;\n\tlong unsigned int cmin_flt;\n\tlong unsigned int cmaj_flt;\n\tlong unsigned int inblock;\n\tlong unsigned int oublock;\n\tlong unsigned int cinblock;\n\tlong unsigned int coublock;\n\tlong unsigned int maxrss;\n\tlong unsigned int cmaxrss;\n\tstruct task_io_accounting ioac;\n\tlong long unsigned int sum_sched_runtime;\n\tstruct rlimit rlim[16];\n\tstruct pacct_struct pacct;\n\tstruct taskstats *stats;\n\tunsigned int audit_tty;\n\tstruct tty_audit_buf *tty_audit_buf;\n\tbool oom_flag_origin;\n\tshort int oom_score_adj;\n\tshort int oom_score_adj_min;\n\tstruct mm_struct *oom_mm;\n\tstruct mutex cred_guard_mutex;\n\tstruct mutex exec_update_mutex;\n};\n\nstruct rseq {\n\t__u32 cpu_id_start;\n\t__u32 cpu_id;\n\tunion {\n\t\t__u64 ptr64;\n\t\t__u64 ptr;\n\t} rseq_cs;\n\t__u32 flags;\n\tlong: 32;\n\tlong: 64;\n};\n\nstruct root_domain;\n\nstruct rq;\n\nstruct rq_flags;\n\nstruct sched_class {\n\tconst struct sched_class *next;\n\tvoid (*enqueue_task)(struct rq *, struct task_struct *, int);\n\tvoid (*dequeue_task)(struct rq *, struct task_struct *, int);\n\tvoid (*yield_task)(struct rq *);\n\tbool (*yield_to_task)(struct rq *, struct task_struct *, bool);\n\tvoid (*check_preempt_curr)(struct rq *, struct task_struct *, int);\n\tstruct task_struct * (*pick_next_task)(struct rq *);\n\tvoid (*put_prev_task)(struct rq *, struct task_struct *);\n\tvoid (*set_next_task)(struct rq *, struct task_struct *, bool);\n\tint (*balance)(struct rq *, struct task_struct *, struct rq_flags *);\n\tint (*select_task_rq)(struct task_struct *, int, int, int);\n\tvoid (*migrate_task_rq)(struct task_struct *, int);\n\tvoid (*task_woken)(struct rq *, struct task_struct *);\n\tvoid (*set_cpus_allowed)(struct task_struct *, const struct cpumask *);\n\tvoid (*rq_online)(struct rq *);\n\tvoid (*rq_offline)(struct rq *);\n\tvoid (*task_tick)(struct rq *, struct task_struct *, int);\n\tvoid (*task_fork)(struct task_struct *);\n\tvoid (*task_dead)(struct task_struct *);\n\tvoid (*switched_from)(struct rq *, struct task_struct *);\n\tvoid (*switched_to)(struct rq *, struct task_struct *);\n\tvoid (*prio_changed)(struct rq *, struct task_struct *, int);\n\tunsigned int (*get_rr_interval)(struct rq *, struct task_struct *);\n\tvoid (*update_curr)(struct rq *);\n\tvoid (*task_change_group)(struct task_struct *, int);\n};\n\nstruct kernel_cap_struct {\n\t__u32 cap[2];\n};\n\ntypedef struct kernel_cap_struct kernel_cap_t;\n\nstruct group_info;\n\nstruct cred {\n\tatomic_t usage;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t suid;\n\tkgid_t sgid;\n\tkuid_t euid;\n\tkgid_t egid;\n\tkuid_t fsuid;\n\tkgid_t fsgid;\n\tunsigned int securebits;\n\tkernel_cap_t cap_inheritable;\n\tkernel_cap_t cap_permitted;\n\tkernel_cap_t cap_effective;\n\tkernel_cap_t cap_bset;\n\tkernel_cap_t cap_ambient;\n\tunsigned char jit_keyring;\n\tstruct key *session_keyring;\n\tstruct key *process_keyring;\n\tstruct key *thread_keyring;\n\tstruct key *request_key_auth;\n\tvoid *security;\n\tstruct user_struct *user;\n\tstruct user_namespace *user_ns;\n\tstruct group_info *group_info;\n\tunion {\n\t\tint non_rcu;\n\t\tstruct callback_head rcu;\n\t};\n};\n\ntypedef int32_t key_serial_t;\n\ntypedef uint32_t key_perm_t;\n\nstruct key_type;\n\nstruct key_tag;\n\nstruct keyring_index_key {\n\tlong unsigned int hash;\n\tunion {\n\t\tstruct {\n\t\t\tu16 desc_len;\n\t\t\tchar desc[6];\n\t\t};\n\t\tlong unsigned int x;\n\t};\n\tstruct key_type *type;\n\tstruct key_tag *domain_tag;\n\tconst char *description;\n};\n\nunion key_payload {\n\tvoid *rcu_data0;\n\tvoid *data[4];\n};\n\nstruct assoc_array_ptr;\n\nstruct assoc_array {\n\tstruct assoc_array_ptr *root;\n\tlong unsigned int nr_leaves_on_tree;\n};\n\nstruct key_user;\n\nstruct key_restriction;\n\nstruct key {\n\trefcount_t usage;\n\tkey_serial_t serial;\n\tunion {\n\t\tstruct list_head graveyard_link;\n\t\tstruct rb_node serial_node;\n\t};\n\tstruct rw_semaphore sem;\n\tstruct key_user *user;\n\tvoid *security;\n\tunion {\n\t\ttime64_t expiry;\n\t\ttime64_t revoked_at;\n\t};\n\ttime64_t last_used_at;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkey_perm_t perm;\n\tshort unsigned int quotalen;\n\tshort unsigned int datalen;\n\tshort int state;\n\tlong unsigned int flags;\n\tunion {\n\t\tstruct keyring_index_key index_key;\n\t\tstruct {\n\t\t\tlong unsigned int hash;\n\t\t\tlong unsigned int len_desc;\n\t\t\tstruct key_type *type;\n\t\t\tstruct key_tag *domain_tag;\n\t\t\tchar *description;\n\t\t};\n\t};\n\tunion {\n\t\tunion key_payload payload;\n\t\tstruct {\n\t\t\tstruct list_head name_link;\n\t\t\tstruct assoc_array keys;\n\t\t};\n\t};\n\tstruct key_restriction *restrict_link;\n};\n\nstruct sighand_struct {\n\tspinlock_t siglock;\n\trefcount_t count;\n\twait_queue_head_t signalfd_wqh;\n\tstruct k_sigaction action[64];\n};\n\nstruct io_cq;\n\nstruct io_context {\n\tatomic_long_t refcount;\n\tatomic_t active_ref;\n\tatomic_t nr_tasks;\n\tspinlock_t lock;\n\tshort unsigned int ioprio;\n\tint nr_batch_requests;\n\tlong unsigned int last_waited;\n\tstruct xarray icq_tree;\n\tstruct io_cq *icq_hint;\n\tstruct hlist_head icq_list;\n\tstruct work_struct release_work;\n};\n\nunion thread_union {\n\tstruct task_struct task;\n\tlong unsigned int stack[2048];\n};\n\nstruct hlist_bl_node;\n\nstruct hlist_bl_head {\n\tstruct hlist_bl_node *first;\n};\n\nstruct hlist_bl_node {\n\tstruct hlist_bl_node *next;\n\tstruct hlist_bl_node **pprev;\n};\n\nstruct lockref {\n\tunion {\n\t\t__u64 lock_count;\n\t\tstruct {\n\t\t\tspinlock_t lock;\n\t\t\tint count;\n\t\t};\n\t};\n};\n\nstruct qstr {\n\tunion {\n\t\tstruct {\n\t\t\tu32 hash;\n\t\t\tu32 len;\n\t\t};\n\t\tu64 hash_len;\n\t};\n\tconst unsigned char *name;\n};\n\nstruct dentry_stat_t {\n\tlong int nr_dentry;\n\tlong int nr_unused;\n\tlong int age_limit;\n\tlong int want_pages;\n\tlong int nr_negative;\n\tlong int dummy;\n};\n\nstruct dentry_operations;\n\nstruct dentry {\n\tunsigned int d_flags;\n\tseqcount_t d_seq;\n\tstruct hlist_bl_node d_hash;\n\tstruct dentry *d_parent;\n\tstruct qstr d_name;\n\tstruct inode *d_inode;\n\tunsigned char d_iname[32];\n\tstruct lockref d_lockref;\n\tconst struct dentry_operations *d_op;\n\tstruct super_block *d_sb;\n\tlong unsigned int d_time;\n\tvoid *d_fsdata;\n\tunion {\n\t\tstruct list_head d_lru;\n\t\twait_queue_head_t *d_wait;\n\t};\n\tstruct list_head d_child;\n\tstruct list_head d_subdirs;\n\tunion {\n\t\tstruct hlist_node d_alias;\n\t\tstruct hlist_bl_node d_in_lookup_hash;\n\t\tstruct callback_head d_rcu;\n\t} d_u;\n};\n\nstruct posix_acl;\n\nstruct inode_operations;\n\nstruct file_lock_context;\n\nstruct block_device;\n\nstruct cdev;\n\nstruct fsnotify_mark_connector;\n\nstruct inode {\n\tumode_t i_mode;\n\tshort unsigned int i_opflags;\n\tkuid_t i_uid;\n\tkgid_t i_gid;\n\tunsigned int i_flags;\n\tstruct posix_acl *i_acl;\n\tstruct posix_acl *i_default_acl;\n\tconst struct inode_operations *i_op;\n\tstruct super_block *i_sb;\n\tstruct address_space *i_mapping;\n\tvoid *i_security;\n\tlong unsigned int i_ino;\n\tunion {\n\t\tconst unsigned int i_nlink;\n\t\tunsigned int __i_nlink;\n\t};\n\tdev_t i_rdev;\n\tloff_t i_size;\n\tstruct timespec64 i_atime;\n\tstruct timespec64 i_mtime;\n\tstruct timespec64 i_ctime;\n\tspinlock_t i_lock;\n\tshort unsigned int i_bytes;\n\tu8 i_blkbits;\n\tu8 i_write_hint;\n\tblkcnt_t i_blocks;\n\tlong unsigned int i_state;\n\tstruct rw_semaphore i_rwsem;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int dirtied_time_when;\n\tstruct hlist_node i_hash;\n\tstruct list_head i_io_list;\n\tstruct list_head i_lru;\n\tstruct list_head i_sb_list;\n\tstruct list_head i_wb_list;\n\tunion {\n\t\tstruct hlist_head i_dentry;\n\t\tstruct callback_head i_rcu;\n\t};\n\tatomic64_t i_version;\n\tatomic64_t i_sequence;\n\tatomic_t i_count;\n\tatomic_t i_dio_count;\n\tatomic_t i_writecount;\n\tatomic_t i_readcount;\n\tunion {\n\t\tconst struct file_operations *i_fop;\n\t\tvoid (*free_inode)(struct inode *);\n\t};\n\tstruct file_lock_context *i_flctx;\n\tstruct address_space i_data;\n\tstruct list_head i_devices;\n\tunion {\n\t\tstruct pipe_inode_info *i_pipe;\n\t\tstruct block_device *i_bdev;\n\t\tstruct cdev *i_cdev;\n\t\tchar *i_link;\n\t\tunsigned int i_dir_seq;\n\t};\n\t__u32 i_generation;\n\t__u32 i_fsnotify_mask;\n\tstruct fsnotify_mark_connector *i_fsnotify_marks;\n\tvoid *i_private;\n};\n\nstruct dentry_operations {\n\tint (*d_revalidate)(struct dentry *, unsigned int);\n\tint (*d_weak_revalidate)(struct dentry *, unsigned int);\n\tint (*d_hash)(const struct dentry *, struct qstr *);\n\tint (*d_compare)(const struct dentry *, unsigned int, const char *, const struct qstr *);\n\tint (*d_delete)(const struct dentry *);\n\tint (*d_init)(struct dentry *);\n\tvoid (*d_release)(struct dentry *);\n\tvoid (*d_prune)(struct dentry *);\n\tvoid (*d_iput)(struct dentry *, struct inode *);\n\tchar * (*d_dname)(struct dentry *, char *, int);\n\tstruct vfsmount * (*d_automount)(struct path *);\n\tint (*d_manage)(const struct path *, bool);\n\tstruct dentry * (*d_real)(struct dentry *, const struct inode *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct mtd_info;\n\ntypedef long long int qsize_t;\n\nstruct quota_format_type;\n\nstruct mem_dqinfo {\n\tstruct quota_format_type *dqi_format;\n\tint dqi_fmt_id;\n\tstruct list_head dqi_dirty_list;\n\tlong unsigned int dqi_flags;\n\tunsigned int dqi_bgrace;\n\tunsigned int dqi_igrace;\n\tqsize_t dqi_max_spc_limit;\n\tqsize_t dqi_max_ino_limit;\n\tvoid *dqi_priv;\n};\n\nstruct quota_format_ops;\n\nstruct quota_info {\n\tunsigned int flags;\n\tstruct rw_semaphore dqio_sem;\n\tstruct inode *files[3];\n\tstruct mem_dqinfo info[3];\n\tconst struct quota_format_ops *ops[3];\n};\n\nstruct rcu_sync {\n\tint gp_state;\n\tint gp_count;\n\twait_queue_head_t gp_wait;\n\tstruct callback_head cb_head;\n};\n\nstruct rcuwait {\n\tstruct task_struct *task;\n};\n\nstruct percpu_rw_semaphore {\n\tstruct rcu_sync rss;\n\tunsigned int *read_count;\n\tstruct rcuwait writer;\n\twait_queue_head_t waiters;\n\tatomic_t block;\n};\n\nstruct sb_writers {\n\tint frozen;\n\twait_queue_head_t wait_unfrozen;\n\tstruct percpu_rw_semaphore rw_sem[3];\n};\n\ntypedef struct {\n\t__u8 b[16];\n} uuid_t;\n\nstruct list_lru_node;\n\nstruct list_lru {\n\tstruct list_lru_node *node;\n};\n\nstruct super_operations;\n\nstruct dquot_operations;\n\nstruct quotactl_ops;\n\nstruct export_operations;\n\nstruct xattr_handler;\n\nstruct workqueue_struct;\n\nstruct super_block {\n\tstruct list_head s_list;\n\tdev_t s_dev;\n\tunsigned char s_blocksize_bits;\n\tlong unsigned int s_blocksize;\n\tloff_t s_maxbytes;\n\tstruct file_system_type *s_type;\n\tconst struct super_operations *s_op;\n\tconst struct dquot_operations *dq_op;\n\tconst struct quotactl_ops *s_qcop;\n\tconst struct export_operations *s_export_op;\n\tlong unsigned int s_flags;\n\tlong unsigned int s_iflags;\n\tlong unsigned int s_magic;\n\tstruct dentry *s_root;\n\tstruct rw_semaphore s_umount;\n\tint s_count;\n\tatomic_t s_active;\n\tvoid *s_security;\n\tconst struct xattr_handler **s_xattr;\n\tstruct hlist_bl_head s_roots;\n\tstruct list_head s_mounts;\n\tstruct block_device *s_bdev;\n\tstruct backing_dev_info *s_bdi;\n\tstruct mtd_info *s_mtd;\n\tstruct hlist_node s_instances;\n\tunsigned int s_quota_types;\n\tstruct quota_info s_dquot;\n\tstruct sb_writers s_writers;\n\tvoid *s_fs_info;\n\tu32 s_time_gran;\n\ttime64_t s_time_min;\n\ttime64_t s_time_max;\n\t__u32 s_fsnotify_mask;\n\tstruct fsnotify_mark_connector *s_fsnotify_marks;\n\tchar s_id[32];\n\tuuid_t s_uuid;\n\tunsigned int s_max_links;\n\tfmode_t s_mode;\n\tstruct mutex s_vfs_rename_mutex;\n\tconst char *s_subtype;\n\tconst struct dentry_operations *s_d_op;\n\tint cleancache_poolid;\n\tstruct shrinker s_shrink;\n\tatomic_long_t s_remove_count;\n\tatomic_long_t s_fsnotify_inode_refs;\n\tint s_readonly_remount;\n\terrseq_t s_wb_err;\n\tstruct workqueue_struct *s_dio_done_wq;\n\tstruct hlist_head s_pins;\n\tstruct user_namespace *s_user_ns;\n\tstruct list_lru s_dentry_lru;\n\tstruct list_lru s_inode_lru;\n\tstruct callback_head rcu;\n\tstruct work_struct destroy_work;\n\tstruct mutex s_sync_lock;\n\tint s_stack_depth;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t s_inode_list_lock;\n\tstruct list_head s_inodes;\n\tspinlock_t s_inode_wblist_lock;\n\tstruct list_head s_inodes_wb;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kstat {\n\tu32 result_mask;\n\tumode_t mode;\n\tunsigned int nlink;\n\tuint32_t blksize;\n\tu64 attributes;\n\tu64 attributes_mask;\n\tu64 ino;\n\tdev_t dev;\n\tdev_t rdev;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\tstruct timespec64 btime;\n\tu64 blocks;\n\tu64 mnt_id;\n};\n\nstruct list_lru_one {\n\tstruct list_head list;\n\tlong int nr_items;\n};\n\nstruct list_lru_node {\n\tspinlock_t lock;\n\tstruct list_lru_one lru;\n\tlong int nr_items;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xa_node {\n\tunsigned char shift;\n\tunsigned char offset;\n\tunsigned char count;\n\tunsigned char nr_values;\n\tstruct xa_node *parent;\n\tstruct xarray *array;\n\tunion {\n\t\tstruct list_head private_list;\n\t\tstruct callback_head callback_head;\n\t};\n\tvoid *slots[64];\n\tunion {\n\t\tlong unsigned int tags[3];\n\t\tlong unsigned int marks[3];\n\t};\n};\n\ntypedef struct {} local_lock_t;\n\nstruct radix_tree_preload {\n\tlocal_lock_t lock;\n\tunsigned int nr;\n\tstruct xa_node *nodes;\n};\n\nenum migrate_mode {\n\tMIGRATE_ASYNC = 0,\n\tMIGRATE_SYNC_LIGHT = 1,\n\tMIGRATE_SYNC = 2,\n\tMIGRATE_SYNC_NO_COPY = 3,\n};\n\nstruct ctl_table;\n\ntypedef int proc_handler(struct ctl_table *, int, void *, size_t *, loff_t *);\n\nstruct ctl_table_poll;\n\nstruct ctl_table {\n\tconst char *procname;\n\tvoid *data;\n\tint maxlen;\n\tumode_t mode;\n\tstruct ctl_table *child;\n\tproc_handler *proc_handler;\n\tstruct ctl_table_poll *poll;\n\tvoid *extra1;\n\tvoid *extra2;\n};\n\nstruct ctl_table_poll {\n\tatomic_t event;\n\twait_queue_head_t wait;\n};\n\nstruct key_tag {\n\tstruct callback_head rcu;\n\trefcount_t usage;\n\tbool removed;\n};\n\ntypedef int (*request_key_actor_t)(struct key *, void *);\n\nstruct key_preparsed_payload;\n\nstruct key_match_data;\n\nstruct kernel_pkey_params;\n\nstruct kernel_pkey_query;\n\nstruct key_type {\n\tconst char *name;\n\tsize_t def_datalen;\n\tunsigned int flags;\n\tint (*vet_description)(const char *);\n\tint (*preparse)(struct key_preparsed_payload *);\n\tvoid (*free_preparse)(struct key_preparsed_payload *);\n\tint (*instantiate)(struct key *, struct key_preparsed_payload *);\n\tint (*update)(struct key *, struct key_preparsed_payload *);\n\tint (*match_preparse)(struct key_match_data *);\n\tvoid (*match_free)(struct key_match_data *);\n\tvoid (*revoke)(struct key *);\n\tvoid (*destroy)(struct key *);\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tlong int (*read)(const struct key *, char *, size_t);\n\trequest_key_actor_t request_key;\n\tstruct key_restriction * (*lookup_restriction)(const char *);\n\tint (*asym_query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*asym_eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*asym_verify_signature)(struct kernel_pkey_params *, const void *, const void *);\n\tstruct list_head link;\n\tstruct lock_class_key lock_class;\n};\n\ntypedef int (*key_restrict_link_func_t)(struct key *, const struct key_type *, const union key_payload *, struct key *);\n\nstruct key_restriction {\n\tkey_restrict_link_func_t check;\n\tstruct key *key;\n\tstruct key_type *keytype;\n};\n\nstruct group_info {\n\tatomic_t usage;\n\tint ngroups;\n\tkgid_t gid[0];\n};\n\nstruct delayed_call {\n\tvoid (*fn)(void *);\n\tvoid *arg;\n};\n\ntypedef struct {\n\t__u8 b[16];\n} guid_t;\n\nstruct request_queue;\n\nstruct io_cq {\n\tstruct request_queue *q;\n\tstruct io_context *ioc;\n\tunion {\n\t\tstruct list_head q_node;\n\t\tstruct kmem_cache *__rcu_icq_cache;\n\t};\n\tunion {\n\t\tstruct hlist_node ioc_node;\n\t\tstruct callback_head __rcu_head;\n\t};\n\tunsigned int flags;\n};\n\nstruct files_stat_struct {\n\tlong unsigned int nr_files;\n\tlong unsigned int nr_free_files;\n\tlong unsigned int max_files;\n};\n\nstruct inodes_stat_t {\n\tlong int nr_inodes;\n\tlong int nr_unused;\n\tlong int dummy[5];\n};\n\nstruct kiocb {\n\tstruct file *ki_filp;\n\tloff_t ki_pos;\n\tvoid (*ki_complete)(struct kiocb *, long int, long int);\n\tvoid *private;\n\tint ki_flags;\n\tu16 ki_hint;\n\tu16 ki_ioprio;\n\tunsigned int ki_cookie;\n};\n\nstruct iattr {\n\tunsigned int ia_valid;\n\tumode_t ia_mode;\n\tkuid_t ia_uid;\n\tkgid_t ia_gid;\n\tloff_t ia_size;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct file *ia_file;\n};\n\nstruct percpu_counter {\n\traw_spinlock_t lock;\n\ts64 count;\n\tstruct list_head list;\n\ts32 *counters;\n};\n\ntypedef __kernel_uid32_t projid_t;\n\ntypedef struct {\n\tprojid_t val;\n} kprojid_t;\n\nenum quota_type {\n\tUSRQUOTA = 0,\n\tGRPQUOTA = 1,\n\tPRJQUOTA = 2,\n};\n\nstruct kqid {\n\tunion {\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tkprojid_t projid;\n\t};\n\tenum quota_type type;\n};\n\nstruct mem_dqblk {\n\tqsize_t dqb_bhardlimit;\n\tqsize_t dqb_bsoftlimit;\n\tqsize_t dqb_curspace;\n\tqsize_t dqb_rsvspace;\n\tqsize_t dqb_ihardlimit;\n\tqsize_t dqb_isoftlimit;\n\tqsize_t dqb_curinodes;\n\ttime64_t dqb_btime;\n\ttime64_t dqb_itime;\n};\n\nstruct dquot {\n\tstruct hlist_node dq_hash;\n\tstruct list_head dq_inuse;\n\tstruct list_head dq_free;\n\tstruct list_head dq_dirty;\n\tstruct mutex dq_lock;\n\tspinlock_t dq_dqb_lock;\n\tatomic_t dq_count;\n\tstruct super_block *dq_sb;\n\tstruct kqid dq_id;\n\tloff_t dq_off;\n\tlong unsigned int dq_flags;\n\tstruct mem_dqblk dq_dqb;\n};\n\nstruct quota_format_type {\n\tint qf_fmt_id;\n\tconst struct quota_format_ops *qf_ops;\n\tstruct module *qf_owner;\n\tstruct quota_format_type *qf_next;\n};\n\nstruct dqstats {\n\tlong unsigned int stat[8];\n\tstruct percpu_counter counter[8];\n};\n\nstruct quota_format_ops {\n\tint (*check_quota_file)(struct super_block *, int);\n\tint (*read_file_info)(struct super_block *, int);\n\tint (*write_file_info)(struct super_block *, int);\n\tint (*free_file_info)(struct super_block *, int);\n\tint (*read_dqblk)(struct dquot *);\n\tint (*commit_dqblk)(struct dquot *);\n\tint (*release_dqblk)(struct dquot *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct dquot_operations {\n\tint (*write_dquot)(struct dquot *);\n\tstruct dquot * (*alloc_dquot)(struct super_block *, int);\n\tvoid (*destroy_dquot)(struct dquot *);\n\tint (*acquire_dquot)(struct dquot *);\n\tint (*release_dquot)(struct dquot *);\n\tint (*mark_dirty)(struct dquot *);\n\tint (*write_info)(struct super_block *, int);\n\tqsize_t * (*get_reserved_space)(struct inode *);\n\tint (*get_projid)(struct inode *, kprojid_t *);\n\tint (*get_inode_usage)(struct inode *, qsize_t *);\n\tint (*get_next_id)(struct super_block *, struct kqid *);\n};\n\nstruct qc_dqblk {\n\tint d_fieldmask;\n\tu64 d_spc_hardlimit;\n\tu64 d_spc_softlimit;\n\tu64 d_ino_hardlimit;\n\tu64 d_ino_softlimit;\n\tu64 d_space;\n\tu64 d_ino_count;\n\ts64 d_ino_timer;\n\ts64 d_spc_timer;\n\tint d_ino_warns;\n\tint d_spc_warns;\n\tu64 d_rt_spc_hardlimit;\n\tu64 d_rt_spc_softlimit;\n\tu64 d_rt_space;\n\ts64 d_rt_spc_timer;\n\tint d_rt_spc_warns;\n};\n\nstruct qc_type_state {\n\tunsigned int flags;\n\tunsigned int spc_timelimit;\n\tunsigned int ino_timelimit;\n\tunsigned int rt_spc_timelimit;\n\tunsigned int spc_warnlimit;\n\tunsigned int ino_warnlimit;\n\tunsigned int rt_spc_warnlimit;\n\tlong long unsigned int ino;\n\tblkcnt_t blocks;\n\tblkcnt_t nextents;\n};\n\nstruct qc_state {\n\tunsigned int s_incoredqs;\n\tstruct qc_type_state s_state[3];\n};\n\nstruct qc_info {\n\tint i_fieldmask;\n\tunsigned int i_flags;\n\tunsigned int i_spc_timelimit;\n\tunsigned int i_ino_timelimit;\n\tunsigned int i_rt_spc_timelimit;\n\tunsigned int i_spc_warnlimit;\n\tunsigned int i_ino_warnlimit;\n\tunsigned int i_rt_spc_warnlimit;\n};\n\nstruct quotactl_ops {\n\tint (*quota_on)(struct super_block *, int, int, const struct path *);\n\tint (*quota_off)(struct super_block *, int);\n\tint (*quota_enable)(struct super_block *, unsigned int);\n\tint (*quota_disable)(struct super_block *, unsigned int);\n\tint (*quota_sync)(struct super_block *, int);\n\tint (*set_info)(struct super_block *, int, struct qc_info *);\n\tint (*get_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_nextdqblk)(struct super_block *, struct kqid *, struct qc_dqblk *);\n\tint (*set_dqblk)(struct super_block *, struct kqid, struct qc_dqblk *);\n\tint (*get_state)(struct super_block *, struct qc_state *);\n\tint (*rm_xquota)(struct super_block *, unsigned int);\n};\n\nstruct writeback_control;\n\nstruct readahead_control;\n\nstruct swap_info_struct;\n\nstruct address_space_operations {\n\tint (*writepage)(struct page *, struct writeback_control *);\n\tint (*readpage)(struct file *, struct page *);\n\tint (*writepages)(struct address_space *, struct writeback_control *);\n\tint (*set_page_dirty)(struct page *);\n\tint (*readpages)(struct file *, struct address_space *, struct list_head *, unsigned int);\n\tvoid (*readahead)(struct readahead_control *);\n\tint (*write_begin)(struct file *, struct address_space *, loff_t, unsigned int, unsigned int, struct page **, void **);\n\tint (*write_end)(struct file *, struct address_space *, loff_t, unsigned int, unsigned int, struct page *, void *);\n\tsector_t (*bmap)(struct address_space *, sector_t);\n\tvoid (*invalidatepage)(struct page *, unsigned int, unsigned int);\n\tint (*releasepage)(struct page *, gfp_t);\n\tvoid (*freepage)(struct page *);\n\tssize_t (*direct_IO)(struct kiocb *, struct iov_iter *);\n\tint (*migratepage)(struct address_space *, struct page *, struct page *, enum migrate_mode);\n\tbool (*isolate_page)(struct page *, isolate_mode_t);\n\tvoid (*putback_page)(struct page *);\n\tint (*launder_page)(struct page *);\n\tint (*is_partially_uptodate)(struct page *, long unsigned int, long unsigned int);\n\tvoid (*is_dirty_writeback)(struct page *, bool *, bool *);\n\tint (*error_remove_page)(struct address_space *, struct page *);\n\tint (*swap_activate)(struct swap_info_struct *, struct file *, sector_t *);\n\tvoid (*swap_deactivate)(struct file *);\n};\n\nstruct hd_struct;\n\nstruct gendisk;\n\nstruct block_device {\n\tdev_t bd_dev;\n\tint bd_openers;\n\tstruct inode *bd_inode;\n\tstruct super_block *bd_super;\n\tstruct mutex bd_mutex;\n\tvoid *bd_claiming;\n\tvoid *bd_holder;\n\tint bd_holders;\n\tbool bd_write_holder;\n\tstruct list_head bd_holder_disks;\n\tstruct block_device *bd_contains;\n\tunsigned int bd_block_size;\n\tu8 bd_partno;\n\tstruct hd_struct *bd_part;\n\tunsigned int bd_part_count;\n\tint bd_invalidated;\n\tstruct gendisk *bd_disk;\n\tstruct request_queue *bd_queue;\n\tstruct backing_dev_info *bd_bdi;\n\tstruct list_head bd_list;\n\tlong unsigned int bd_private;\n\tint bd_fsfreeze_count;\n\tstruct mutex bd_fsfreeze_mutex;\n};\n\nstruct fiemap_extent_info;\n\nstruct inode_operations {\n\tstruct dentry * (*lookup)(struct inode *, struct dentry *, unsigned int);\n\tconst char * (*get_link)(struct dentry *, struct inode *, struct delayed_call *);\n\tint (*permission)(struct inode *, int);\n\tstruct posix_acl * (*get_acl)(struct inode *, int);\n\tint (*readlink)(struct dentry *, char *, int);\n\tint (*create)(struct inode *, struct dentry *, umode_t, bool);\n\tint (*link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*unlink)(struct inode *, struct dentry *);\n\tint (*symlink)(struct inode *, struct dentry *, const char *);\n\tint (*mkdir)(struct inode *, struct dentry *, umode_t);\n\tint (*rmdir)(struct inode *, struct dentry *);\n\tint (*mknod)(struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*rename)(struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int);\n\tint (*setattr)(struct dentry *, struct iattr *);\n\tint (*getattr)(const struct path *, struct kstat *, u32, unsigned int);\n\tssize_t (*listxattr)(struct dentry *, char *, size_t);\n\tint (*fiemap)(struct inode *, struct fiemap_extent_info *, u64, u64);\n\tint (*update_time)(struct inode *, struct timespec64 *, int);\n\tint (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned int, umode_t);\n\tint (*tmpfile)(struct inode *, struct dentry *, umode_t);\n\tint (*set_acl)(struct inode *, struct posix_acl *, int);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct file_lock_context {\n\tspinlock_t flc_lock;\n\tstruct list_head flc_flock;\n\tstruct list_head flc_posix;\n\tstruct list_head flc_lease;\n};\n\nstruct file_lock_operations {\n\tvoid (*fl_copy_lock)(struct file_lock *, struct file_lock *);\n\tvoid (*fl_release_private)(struct file_lock *);\n};\n\nstruct nlm_lockowner;\n\nstruct nfs_lock_info {\n\tu32 state;\n\tstruct nlm_lockowner *owner;\n\tstruct list_head list;\n};\n\nstruct nfs4_lock_state;\n\nstruct nfs4_lock_info {\n\tstruct nfs4_lock_state *owner;\n};\n\nstruct fasync_struct;\n\nstruct lock_manager_operations;\n\nstruct file_lock {\n\tstruct file_lock *fl_blocker;\n\tstruct list_head fl_list;\n\tstruct hlist_node fl_link;\n\tstruct list_head fl_blocked_requests;\n\tstruct list_head fl_blocked_member;\n\tfl_owner_t fl_owner;\n\tunsigned int fl_flags;\n\tunsigned char fl_type;\n\tunsigned int fl_pid;\n\tint fl_link_cpu;\n\twait_queue_head_t fl_wait;\n\tstruct file *fl_file;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tstruct fasync_struct *fl_fasync;\n\tlong unsigned int fl_break_time;\n\tlong unsigned int fl_downgrade_time;\n\tconst struct file_lock_operations *fl_ops;\n\tconst struct lock_manager_operations *fl_lmops;\n\tunion {\n\t\tstruct nfs_lock_info nfs_fl;\n\t\tstruct nfs4_lock_info nfs4_fl;\n\t\tstruct {\n\t\t\tstruct list_head link;\n\t\t\tint state;\n\t\t\tunsigned int debug_id;\n\t\t} afs;\n\t} fl_u;\n};\n\nstruct lock_manager_operations {\n\tfl_owner_t (*lm_get_owner)(fl_owner_t);\n\tvoid (*lm_put_owner)(fl_owner_t);\n\tvoid (*lm_notify)(struct file_lock *);\n\tint (*lm_grant)(struct file_lock *, int);\n\tbool (*lm_break)(struct file_lock *);\n\tint (*lm_change)(struct file_lock *, int, struct list_head *);\n\tvoid (*lm_setup)(struct file_lock *, void **);\n\tbool (*lm_breaker_owns_lease)(struct file_lock *);\n};\n\nstruct fasync_struct {\n\trwlock_t fa_lock;\n\tint magic;\n\tint fa_fd;\n\tstruct fasync_struct *fa_next;\n\tstruct file *fa_file;\n\tstruct callback_head fa_rcu;\n};\n\nstruct kstatfs;\n\nstruct super_operations {\n\tstruct inode * (*alloc_inode)(struct super_block *);\n\tvoid (*destroy_inode)(struct inode *);\n\tvoid (*free_inode)(struct inode *);\n\tvoid (*dirty_inode)(struct inode *, int);\n\tint (*write_inode)(struct inode *, struct writeback_control *);\n\tint (*drop_inode)(struct inode *);\n\tvoid (*evict_inode)(struct inode *);\n\tvoid (*put_super)(struct super_block *);\n\tint (*sync_fs)(struct super_block *, int);\n\tint (*freeze_super)(struct super_block *);\n\tint (*freeze_fs)(struct super_block *);\n\tint (*thaw_super)(struct super_block *);\n\tint (*unfreeze_fs)(struct super_block *);\n\tint (*statfs)(struct dentry *, struct kstatfs *);\n\tint (*remount_fs)(struct super_block *, int *, char *);\n\tvoid (*umount_begin)(struct super_block *);\n\tint (*show_options)(struct seq_file *, struct dentry *);\n\tint (*show_devname)(struct seq_file *, struct dentry *);\n\tint (*show_path)(struct seq_file *, struct dentry *);\n\tint (*show_stats)(struct seq_file *, struct dentry *);\n\tssize_t (*quota_read)(struct super_block *, int, char *, size_t, loff_t);\n\tssize_t (*quota_write)(struct super_block *, int, const char *, size_t, loff_t);\n\tstruct dquot ** (*get_dquots)(struct inode *);\n\tint (*bdev_try_to_free_page)(struct super_block *, struct page *, gfp_t);\n\tlong int (*nr_cached_objects)(struct super_block *, struct shrink_control *);\n\tlong int (*free_cached_objects)(struct super_block *, struct shrink_control *);\n};\n\nstruct iomap;\n\nstruct fid;\n\nstruct export_operations {\n\tint (*encode_fh)(struct inode *, __u32 *, int *, struct inode *);\n\tstruct dentry * (*fh_to_dentry)(struct super_block *, struct fid *, int, int);\n\tstruct dentry * (*fh_to_parent)(struct super_block *, struct fid *, int, int);\n\tint (*get_name)(struct dentry *, char *, struct dentry *);\n\tstruct dentry * (*get_parent)(struct dentry *);\n\tint (*commit_metadata)(struct inode *);\n\tint (*get_uuid)(struct super_block *, u8 *, u32 *, u64 *);\n\tint (*map_blocks)(struct inode *, loff_t, u64, struct iomap *, bool, u32 *);\n\tint (*commit_blocks)(struct inode *, struct iomap *, int, struct iattr *);\n};\n\nstruct xattr_handler {\n\tconst char *name;\n\tconst char *prefix;\n\tint flags;\n\tbool (*list)(struct dentry *);\n\tint (*get)(const struct xattr_handler *, struct dentry *, struct inode *, const char *, void *, size_t);\n\tint (*set)(const struct xattr_handler *, struct dentry *, struct inode *, const char *, const void *, size_t, int);\n};\n\ntypedef int (*filldir_t)(struct dir_context *, const char *, int, loff_t, u64, unsigned int);\n\nstruct dir_context {\n\tfilldir_t actor;\n\tloff_t pos;\n};\n\nstruct p_log;\n\nstruct fs_parameter;\n\nstruct fs_parse_result;\n\ntypedef int fs_param_type(struct p_log *, const struct fs_parameter_spec *, struct fs_parameter *, struct fs_parse_result *);\n\nstruct fs_parameter_spec {\n\tconst char *name;\n\tfs_param_type *type;\n\tu8 opt;\n\tshort unsigned int flags;\n\tconst void *data;\n};\n\nstruct attribute {\n\tconst char *name;\n\tumode_t mode;\n};\n\nstruct kobj_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct kobj_attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct kobj_attribute *, const char *, size_t);\n};\n\ntypedef void compound_page_dtor(struct page *);\n\nenum compound_dtor_id {\n\tNULL_COMPOUND_DTOR = 0,\n\tCOMPOUND_PAGE_DTOR = 1,\n\tHUGETLB_PAGE_DTOR = 2,\n\tNR_COMPOUND_DTORS = 3,\n};\n\nenum vm_event_item {\n\tPGPGIN = 0,\n\tPGPGOUT = 1,\n\tPSWPIN = 2,\n\tPSWPOUT = 3,\n\tPGALLOC_DMA = 4,\n\tPGALLOC_DMA32 = 5,\n\tPGALLOC_NORMAL = 6,\n\tPGALLOC_MOVABLE = 7,\n\tALLOCSTALL_DMA = 8,\n\tALLOCSTALL_DMA32 = 9,\n\tALLOCSTALL_NORMAL = 10,\n\tALLOCSTALL_MOVABLE = 11,\n\tPGSCAN_SKIP_DMA = 12,\n\tPGSCAN_SKIP_DMA32 = 13,\n\tPGSCAN_SKIP_NORMAL = 14,\n\tPGSCAN_SKIP_MOVABLE = 15,\n\tPGFREE = 16,\n\tPGACTIVATE = 17,\n\tPGDEACTIVATE = 18,\n\tPGLAZYFREE = 19,\n\tPGFAULT = 20,\n\tPGMAJFAULT = 21,\n\tPGLAZYFREED = 22,\n\tPGREFILL = 23,\n\tPGSTEAL_KSWAPD = 24,\n\tPGSTEAL_DIRECT = 25,\n\tPGSCAN_KSWAPD = 26,\n\tPGSCAN_DIRECT = 27,\n\tPGSCAN_DIRECT_THROTTLE = 28,\n\tPGSCAN_ANON = 29,\n\tPGSCAN_FILE = 30,\n\tPGSTEAL_ANON = 31,\n\tPGSTEAL_FILE = 32,\n\tPGSCAN_ZONE_RECLAIM_FAILED = 33,\n\tPGINODESTEAL = 34,\n\tSLABS_SCANNED = 35,\n\tKSWAPD_INODESTEAL = 36,\n\tKSWAPD_LOW_WMARK_HIT_QUICKLY = 37,\n\tKSWAPD_HIGH_WMARK_HIT_QUICKLY = 38,\n\tPAGEOUTRUN = 39,\n\tPGROTATED = 40,\n\tDROP_PAGECACHE = 41,\n\tDROP_SLAB = 42,\n\tOOM_KILL = 43,\n\tPGMIGRATE_SUCCESS = 44,\n\tPGMIGRATE_FAIL = 45,\n\tCOMPACTMIGRATE_SCANNED = 46,\n\tCOMPACTFREE_SCANNED = 47,\n\tCOMPACTISOLATED = 48,\n\tCOMPACTSTALL = 49,\n\tCOMPACTFAIL = 50,\n\tCOMPACTSUCCESS = 51,\n\tKCOMPACTD_WAKE = 52,\n\tKCOMPACTD_MIGRATE_SCANNED = 53,\n\tKCOMPACTD_FREE_SCANNED = 54,\n\tHTLB_BUDDY_PGALLOC = 55,\n\tHTLB_BUDDY_PGALLOC_FAIL = 56,\n\tUNEVICTABLE_PGCULLED = 57,\n\tUNEVICTABLE_PGSCANNED = 58,\n\tUNEVICTABLE_PGRESCUED = 59,\n\tUNEVICTABLE_PGMLOCKED = 60,\n\tUNEVICTABLE_PGMUNLOCKED = 61,\n\tUNEVICTABLE_PGCLEARED = 62,\n\tUNEVICTABLE_PGSTRANDED = 63,\n\tSWAP_RA = 64,\n\tSWAP_RA_HIT = 65,\n\tNR_VM_EVENT_ITEMS = 66,\n};\n\nstruct vm_event_state {\n\tlong unsigned int event[66];\n};\n\nenum memblock_flags {\n\tMEMBLOCK_NONE = 0,\n\tMEMBLOCK_HOTPLUG = 1,\n\tMEMBLOCK_MIRROR = 2,\n\tMEMBLOCK_NOMAP = 4,\n};\n\nstruct memblock_region {\n\tphys_addr_t base;\n\tphys_addr_t size;\n\tenum memblock_flags flags;\n\tint nid;\n};\n\nstruct memblock_type {\n\tlong unsigned int cnt;\n\tlong unsigned int max;\n\tphys_addr_t total_size;\n\tstruct memblock_region *regions;\n\tchar *name;\n};\n\nstruct memblock {\n\tbool bottom_up;\n\tphys_addr_t current_limit;\n\tstruct memblock_type memory;\n\tstruct memblock_type reserved;\n};\n\nstruct debug_store {\n\tu64 bts_buffer_base;\n\tu64 bts_index;\n\tu64 bts_absolute_maximum;\n\tu64 bts_interrupt_threshold;\n\tu64 pebs_buffer_base;\n\tu64 pebs_index;\n\tu64 pebs_absolute_maximum;\n\tu64 pebs_interrupt_threshold;\n\tu64 pebs_event_reset[12];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct debug_store_buffers {\n\tchar bts_buffer[65536];\n\tchar pebs_buffer[65536];\n};\n\nstruct cea_exception_stacks {\n\tchar DF_stack_guard[4096];\n\tchar DF_stack[4096];\n\tchar NMI_stack_guard[4096];\n\tchar NMI_stack[4096];\n\tchar DB_stack_guard[4096];\n\tchar DB_stack[4096];\n\tchar MCE_stack_guard[4096];\n\tchar MCE_stack[4096];\n\tchar IST_top_guard[4096];\n};\n\nstruct cpu_entry_area {\n\tchar gdt[4096];\n\tstruct entry_stack_page entry_stack_page;\n\tstruct tss_struct tss;\n\tstruct cea_exception_stacks estacks;\n\tstruct debug_store cpu_debug_store;\n\tstruct debug_store_buffers cpu_debug_buffers;\n};\n\nstruct gdt_page {\n\tstruct desc_struct gdt[16];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tlb_context {\n\tu64 ctx_id;\n\tu64 tlb_gen;\n};\n\nstruct tlb_state {\n\tstruct mm_struct *loaded_mm;\n\tunion {\n\t\tstruct mm_struct *last_user_mm;\n\t\tlong unsigned int last_user_mm_ibpb;\n\t};\n\tu16 loaded_mm_asid;\n\tu16 next_asid;\n\tbool is_lazy;\n\tbool invalidate_other;\n\tshort unsigned int user_pcid_flush_mask;\n\tlong unsigned int cr4;\n\tstruct tlb_context ctxs[6];\n};\n\nenum e820_type {\n\tE820_TYPE_RAM = 1,\n\tE820_TYPE_RESERVED = 2,\n\tE820_TYPE_ACPI = 3,\n\tE820_TYPE_NVS = 4,\n\tE820_TYPE_UNUSABLE = 5,\n\tE820_TYPE_PMEM = 7,\n\tE820_TYPE_PRAM = 12,\n\tE820_TYPE_SOFT_RESERVED = 4026531839,\n\tE820_TYPE_RESERVED_KERN = 128,\n};\n\nstruct e820_entry {\n\tu64 addr;\n\tu64 size;\n\tenum e820_type type;\n} __attribute__((packed));\n\nstruct e820_table {\n\t__u32 nr_entries;\n\tstruct e820_entry entries[320];\n} __attribute__((packed));\n\nstruct boot_params_to_save {\n\tunsigned int start;\n\tunsigned int len;\n};\n\nstruct idr {\n\tstruct xarray idr_rt;\n\tunsigned int idr_base;\n\tunsigned int idr_next;\n};\n\nstruct kernfs_root;\n\nstruct kernfs_elem_dir {\n\tlong unsigned int subdirs;\n\tstruct rb_root children;\n\tstruct kernfs_root *root;\n};\n\nstruct kernfs_syscall_ops;\n\nstruct kernfs_root {\n\tstruct kernfs_node *kn;\n\tunsigned int flags;\n\tstruct idr ino_idr;\n\tu32 last_id_lowbits;\n\tu32 id_highbits;\n\tstruct kernfs_syscall_ops *syscall_ops;\n\tstruct list_head supers;\n\twait_queue_head_t deactivate_waitq;\n};\n\nstruct kernfs_elem_symlink {\n\tstruct kernfs_node *target_kn;\n};\n\nstruct kernfs_ops;\n\nstruct kernfs_open_node;\n\nstruct kernfs_elem_attr {\n\tconst struct kernfs_ops *ops;\n\tstruct kernfs_open_node *open;\n\tloff_t size;\n\tstruct kernfs_node *notify_next;\n};\n\nstruct kernfs_iattrs;\n\nstruct kernfs_node {\n\tatomic_t count;\n\tatomic_t active;\n\tstruct kernfs_node *parent;\n\tconst char *name;\n\tstruct rb_node rb;\n\tconst void *ns;\n\tunsigned int hash;\n\tunion {\n\t\tstruct kernfs_elem_dir dir;\n\t\tstruct kernfs_elem_symlink symlink;\n\t\tstruct kernfs_elem_attr attr;\n\t};\n\tvoid *priv;\n\tu64 id;\n\tshort unsigned int flags;\n\tumode_t mode;\n\tstruct kernfs_iattrs *iattr;\n};\n\nstruct kernfs_open_file;\n\nstruct kernfs_ops {\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tssize_t (*read)(struct kernfs_open_file *, char *, size_t, loff_t);\n\tsize_t atomic_write_len;\n\tbool prealloc;\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n\tint (*mmap)(struct kernfs_open_file *, struct vm_area_struct *);\n};\n\nstruct kernfs_syscall_ops {\n\tint (*show_options)(struct seq_file *, struct kernfs_root *);\n\tint (*mkdir)(struct kernfs_node *, const char *, umode_t);\n\tint (*rmdir)(struct kernfs_node *);\n\tint (*rename)(struct kernfs_node *, struct kernfs_node *, const char *);\n\tint (*show_path)(struct seq_file *, struct kernfs_node *, struct kernfs_root *);\n};\n\nstruct kernfs_open_file {\n\tstruct kernfs_node *kn;\n\tstruct file *file;\n\tstruct seq_file *seq_file;\n\tvoid *priv;\n\tstruct mutex mutex;\n\tstruct mutex prealloc_mutex;\n\tint event;\n\tstruct list_head list;\n\tchar *prealloc_buf;\n\tsize_t atomic_write_len;\n\tbool mmapped: 1;\n\tbool released: 1;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nenum kobj_ns_type {\n\tKOBJ_NS_TYPE_NONE = 0,\n\tKOBJ_NS_TYPE_NET = 1,\n\tKOBJ_NS_TYPES = 2,\n};\n\nstruct sock;\n\nstruct kobj_ns_type_operations {\n\tenum kobj_ns_type type;\n\tbool (*current_may_mount)();\n\tvoid * (*grab_current_ns)();\n\tconst void * (*netlink_ns)(struct sock *);\n\tconst void * (*initial_ns)();\n\tvoid (*drop_ns)(void *);\n};\n\nstruct bin_attribute;\n\nstruct attribute_group {\n\tconst char *name;\n\tumode_t (*is_visible)(struct kobject *, struct attribute *, int);\n\tumode_t (*is_bin_visible)(struct kobject *, struct bin_attribute *, int);\n\tstruct attribute **attrs;\n\tstruct bin_attribute **bin_attrs;\n};\n\nstruct bin_attribute {\n\tstruct attribute attr;\n\tsize_t size;\n\tvoid *private;\n\tssize_t (*read)(struct file *, struct kobject *, struct bin_attribute *, char *, loff_t, size_t);\n\tssize_t (*write)(struct file *, struct kobject *, struct bin_attribute *, char *, loff_t, size_t);\n\tint (*mmap)(struct file *, struct kobject *, struct bin_attribute *, struct vm_area_struct *);\n};\n\nstruct sysfs_ops {\n\tssize_t (*show)(struct kobject *, struct attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t);\n};\n\nstruct kset_uevent_ops;\n\nstruct kset {\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tstruct kobject kobj;\n\tconst struct kset_uevent_ops *uevent_ops;\n};\n\nstruct kobj_type {\n\tvoid (*release)(struct kobject *);\n\tconst struct sysfs_ops *sysfs_ops;\n\tstruct attribute **default_attrs;\n\tconst struct attribute_group **default_groups;\n\tconst struct kobj_ns_type_operations * (*child_ns_type)(struct kobject *);\n\tconst void * (*namespace)(struct kobject *);\n\tvoid (*get_ownership)(struct kobject *, kuid_t *, kgid_t *);\n};\n\nstruct kobj_uevent_env {\n\tchar *argv[3];\n\tchar *envp[64];\n\tint envp_idx;\n\tchar buf[2048];\n\tint buflen;\n};\n\nstruct kset_uevent_ops {\n\tint (* const filter)(struct kset *, struct kobject *);\n\tconst char * (* const name)(struct kset *, struct kobject *);\n\tint (* const uevent)(struct kset *, struct kobject *, struct kobj_uevent_env *);\n};\n\nstruct dev_pm_ops {\n\tint (*prepare)(struct device *);\n\tvoid (*complete)(struct device *);\n\tint (*suspend)(struct device *);\n\tint (*resume)(struct device *);\n\tint (*freeze)(struct device *);\n\tint (*thaw)(struct device *);\n\tint (*poweroff)(struct device *);\n\tint (*restore)(struct device *);\n\tint (*suspend_late)(struct device *);\n\tint (*resume_early)(struct device *);\n\tint (*freeze_late)(struct device *);\n\tint (*thaw_early)(struct device *);\n\tint (*poweroff_late)(struct device *);\n\tint (*restore_early)(struct device *);\n\tint (*suspend_noirq)(struct device *);\n\tint (*resume_noirq)(struct device *);\n\tint (*freeze_noirq)(struct device *);\n\tint (*thaw_noirq)(struct device *);\n\tint (*poweroff_noirq)(struct device *);\n\tint (*restore_noirq)(struct device *);\n\tint (*runtime_suspend)(struct device *);\n\tint (*runtime_resume)(struct device *);\n\tint (*runtime_idle)(struct device *);\n};\n\nstruct pm_subsys_data {\n\tspinlock_t lock;\n\tunsigned int refcount;\n\tstruct list_head clock_list;\n};\n\nstruct wakeup_source {\n\tconst char *name;\n\tint id;\n\tstruct list_head entry;\n\tspinlock_t lock;\n\tstruct wake_irq *wakeirq;\n\tstruct timer_list timer;\n\tlong unsigned int timer_expires;\n\tktime_t total_time;\n\tktime_t max_time;\n\tktime_t last_time;\n\tktime_t start_prevent_time;\n\tktime_t prevent_sleep_time;\n\tlong unsigned int event_count;\n\tlong unsigned int active_count;\n\tlong unsigned int relax_count;\n\tlong unsigned int expire_count;\n\tlong unsigned int wakeup_count;\n\tstruct device *dev;\n\tbool active: 1;\n\tbool autosleep_enabled: 1;\n};\n\nstruct dev_pm_domain {\n\tstruct dev_pm_ops ops;\n\tint (*start)(struct device *);\n\tvoid (*detach)(struct device *, bool);\n\tint (*activate)(struct device *);\n\tvoid (*sync)(struct device *);\n\tvoid (*dismiss)(struct device *);\n};\n\nstruct iommu_ops;\n\nstruct subsys_private;\n\nstruct bus_type {\n\tconst char *name;\n\tconst char *dev_name;\n\tstruct device *dev_root;\n\tconst struct attribute_group **bus_groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct attribute_group **drv_groups;\n\tint (*match)(struct device *, struct device_driver *);\n\tint (*uevent)(struct device *, struct kobj_uevent_env *);\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tint (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tint (*online)(struct device *);\n\tint (*offline)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tint (*num_vf)(struct device *);\n\tint (*dma_configure)(struct device *);\n\tconst struct dev_pm_ops *pm;\n\tconst struct iommu_ops *iommu_ops;\n\tstruct subsys_private *p;\n\tstruct lock_class_key lock_key;\n\tbool need_parent_lock;\n};\n\nenum probe_type {\n\tPROBE_DEFAULT_STRATEGY = 0,\n\tPROBE_PREFER_ASYNCHRONOUS = 1,\n\tPROBE_FORCE_SYNCHRONOUS = 2,\n};\n\nstruct of_device_id;\n\nstruct acpi_device_id;\n\nstruct driver_private;\n\nstruct device_driver {\n\tconst char *name;\n\tstruct bus_type *bus;\n\tstruct module *owner;\n\tconst char *mod_name;\n\tbool suppress_bind_attrs;\n\tenum probe_type probe_type;\n\tconst struct of_device_id *of_match_table;\n\tconst struct acpi_device_id *acpi_match_table;\n\tint (*probe)(struct device *);\n\tvoid (*sync_state)(struct device *);\n\tint (*remove)(struct device *);\n\tvoid (*shutdown)(struct device *);\n\tint (*suspend)(struct device *, pm_message_t);\n\tint (*resume)(struct device *);\n\tconst struct attribute_group **groups;\n\tconst struct attribute_group **dev_groups;\n\tconst struct dev_pm_ops *pm;\n\tvoid (*coredump)(struct device *);\n\tstruct driver_private *p;\n};\n\nenum iommu_cap {\n\tIOMMU_CAP_CACHE_COHERENCY = 0,\n\tIOMMU_CAP_INTR_REMAP = 1,\n\tIOMMU_CAP_NOEXEC = 2,\n};\n\nenum iommu_attr {\n\tDOMAIN_ATTR_GEOMETRY = 0,\n\tDOMAIN_ATTR_PAGING = 1,\n\tDOMAIN_ATTR_WINDOWS = 2,\n\tDOMAIN_ATTR_FSL_PAMU_STASH = 3,\n\tDOMAIN_ATTR_FSL_PAMU_ENABLE = 4,\n\tDOMAIN_ATTR_FSL_PAMUV1 = 5,\n\tDOMAIN_ATTR_NESTING = 6,\n\tDOMAIN_ATTR_DMA_USE_FLUSH_QUEUE = 7,\n\tDOMAIN_ATTR_MAX = 8,\n};\n\nenum iommu_dev_features {\n\tIOMMU_DEV_FEAT_AUX = 0,\n\tIOMMU_DEV_FEAT_SVA = 1,\n};\n\nstruct iommu_domain;\n\nstruct iommu_iotlb_gather;\n\nstruct iommu_device;\n\nstruct iommu_resv_region;\n\nstruct of_phandle_args;\n\nstruct iommu_sva;\n\nstruct iommu_fault_event;\n\nstruct iommu_page_response;\n\nstruct iommu_cache_invalidate_info;\n\nstruct iommu_gpasid_bind_data;\n\nstruct iommu_ops {\n\tbool (*capable)(enum iommu_cap);\n\tstruct iommu_domain * (*domain_alloc)(unsigned int);\n\tvoid (*domain_free)(struct iommu_domain *);\n\tint (*attach_dev)(struct iommu_domain *, struct device *);\n\tvoid (*detach_dev)(struct iommu_domain *, struct device *);\n\tint (*map)(struct iommu_domain *, long unsigned int, phys_addr_t, size_t, int, gfp_t);\n\tsize_t (*unmap)(struct iommu_domain *, long unsigned int, size_t, struct iommu_iotlb_gather *);\n\tvoid (*flush_iotlb_all)(struct iommu_domain *);\n\tvoid (*iotlb_sync_map)(struct iommu_domain *);\n\tvoid (*iotlb_sync)(struct iommu_domain *, struct iommu_iotlb_gather *);\n\tphys_addr_t (*iova_to_phys)(struct iommu_domain *, dma_addr_t);\n\tstruct iommu_device * (*probe_device)(struct device *);\n\tvoid (*release_device)(struct device *);\n\tvoid (*probe_finalize)(struct device *);\n\tstruct iommu_group * (*device_group)(struct device *);\n\tint (*domain_get_attr)(struct iommu_domain *, enum iommu_attr, void *);\n\tint (*domain_set_attr)(struct iommu_domain *, enum iommu_attr, void *);\n\tvoid (*get_resv_regions)(struct device *, struct list_head *);\n\tvoid (*put_resv_regions)(struct device *, struct list_head *);\n\tvoid (*apply_resv_region)(struct device *, struct iommu_domain *, struct iommu_resv_region *);\n\tint (*domain_window_enable)(struct iommu_domain *, u32, phys_addr_t, u64, int);\n\tvoid (*domain_window_disable)(struct iommu_domain *, u32);\n\tint (*of_xlate)(struct device *, struct of_phandle_args *);\n\tbool (*is_attach_deferred)(struct iommu_domain *, struct device *);\n\tbool (*dev_has_feat)(struct device *, enum iommu_dev_features);\n\tbool (*dev_feat_enabled)(struct device *, enum iommu_dev_features);\n\tint (*dev_enable_feat)(struct device *, enum iommu_dev_features);\n\tint (*dev_disable_feat)(struct device *, enum iommu_dev_features);\n\tint (*aux_attach_dev)(struct iommu_domain *, struct device *);\n\tvoid (*aux_detach_dev)(struct iommu_domain *, struct device *);\n\tint (*aux_get_pasid)(struct iommu_domain *, struct device *);\n\tstruct iommu_sva * (*sva_bind)(struct device *, struct mm_struct *, void *);\n\tvoid (*sva_unbind)(struct iommu_sva *);\n\tint (*sva_get_pasid)(struct iommu_sva *);\n\tint (*page_response)(struct device *, struct iommu_fault_event *, struct iommu_page_response *);\n\tint (*cache_invalidate)(struct iommu_domain *, struct device *, struct iommu_cache_invalidate_info *);\n\tint (*sva_bind_gpasid)(struct iommu_domain *, struct device *, struct iommu_gpasid_bind_data *);\n\tint (*sva_unbind_gpasid)(struct device *, int);\n\tint (*def_domain_type)(struct device *);\n\tlong unsigned int pgsize_bitmap;\n\tstruct module *owner;\n};\n\nstruct device_type {\n\tconst char *name;\n\tconst struct attribute_group **groups;\n\tint (*uevent)(struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(struct device *, umode_t *, kuid_t *, kgid_t *);\n\tvoid (*release)(struct device *);\n\tconst struct dev_pm_ops *pm;\n};\n\nstruct class {\n\tconst char *name;\n\tstruct module *owner;\n\tconst struct attribute_group **class_groups;\n\tconst struct attribute_group **dev_groups;\n\tstruct kobject *dev_kobj;\n\tint (*dev_uevent)(struct device *, struct kobj_uevent_env *);\n\tchar * (*devnode)(struct device *, umode_t *);\n\tvoid (*class_release)(struct class *);\n\tvoid (*dev_release)(struct device *);\n\tint (*shutdown_pre)(struct device *);\n\tconst struct kobj_ns_type_operations *ns_type;\n\tconst void * (*namespace)(struct device *);\n\tvoid (*get_ownership)(struct device *, kuid_t *, kgid_t *);\n\tconst struct dev_pm_ops *pm;\n\tstruct subsys_private *p;\n};\n\nstruct of_device_id {\n\tchar name[32];\n\tchar type[32];\n\tchar compatible[128];\n\tconst void *data;\n};\n\ntypedef long unsigned int kernel_ulong_t;\n\nstruct acpi_device_id {\n\t__u8 id[9];\n\tkernel_ulong_t driver_data;\n\t__u32 cls;\n\t__u32 cls_msk;\n};\n\nstruct device_dma_parameters {\n\tunsigned int max_segment_size;\n\tlong unsigned int segment_boundary_mask;\n};\n\nenum dma_data_direction {\n\tDMA_BIDIRECTIONAL = 0,\n\tDMA_TO_DEVICE = 1,\n\tDMA_FROM_DEVICE = 2,\n\tDMA_NONE = 3,\n};\n\nstruct sg_table;\n\nstruct scatterlist;\n\nstruct dma_map_ops {\n\tvoid * (*alloc)(struct device *, size_t, dma_addr_t *, gfp_t, long unsigned int);\n\tvoid (*free)(struct device *, size_t, void *, dma_addr_t, long unsigned int);\n\tint (*mmap)(struct device *, struct vm_area_struct *, void *, dma_addr_t, size_t, long unsigned int);\n\tint (*get_sgtable)(struct device *, struct sg_table *, void *, dma_addr_t, size_t, long unsigned int);\n\tdma_addr_t (*map_page)(struct device *, struct page *, long unsigned int, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_page)(struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tint (*map_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_sg)(struct device *, struct scatterlist *, int, enum dma_data_direction, long unsigned int);\n\tdma_addr_t (*map_resource)(struct device *, phys_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*unmap_resource)(struct device *, dma_addr_t, size_t, enum dma_data_direction, long unsigned int);\n\tvoid (*sync_single_for_cpu)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_single_for_device)(struct device *, dma_addr_t, size_t, enum dma_data_direction);\n\tvoid (*sync_sg_for_cpu)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*sync_sg_for_device)(struct device *, struct scatterlist *, int, enum dma_data_direction);\n\tvoid (*cache_sync)(struct device *, void *, size_t, enum dma_data_direction);\n\tint (*dma_supported)(struct device *, u64);\n\tu64 (*get_required_mask)(struct device *);\n\tsize_t (*max_mapping_size)(struct device *);\n\tlong unsigned int (*get_merge_boundary)(struct device *);\n};\n\nstruct node {\n\tstruct device dev;\n\tstruct list_head access_list;\n};\n\nenum cpuhp_smt_control {\n\tCPU_SMT_ENABLED = 0,\n\tCPU_SMT_DISABLED = 1,\n\tCPU_SMT_FORCE_DISABLED = 2,\n\tCPU_SMT_NOT_SUPPORTED = 3,\n\tCPU_SMT_NOT_IMPLEMENTED = 4,\n};\n\nstruct cpu_signature {\n\tunsigned int sig;\n\tunsigned int pf;\n\tunsigned int rev;\n};\n\nstruct ucode_cpu_info {\n\tstruct cpu_signature cpu_sig;\n\tint valid;\n\tvoid *mc;\n};\n\ntypedef long unsigned int pto_T__;\n\nstruct kobj_attribute___2;\n\nstruct file_system_type___2;\n\nstruct atomic_notifier_head___2;\n\ntypedef long unsigned int irq_hw_number_t;\n\nstruct kernel_symbol {\n\tint value_offset;\n\tint name_offset;\n\tint namespace_offset;\n};\n\ntypedef int (*initcall_t)();\n\nstruct obs_kernel_param {\n\tconst char *str;\n\tint (*setup_func)(char *);\n\tint early;\n};\n\nenum ftrace_dump_mode {\n\tDUMP_NONE = 0,\n\tDUMP_ALL = 1,\n\tDUMP_ORIG = 2,\n};\n\nstruct bug_entry {\n\tint bug_addr_disp;\n\tint file_disp;\n\tshort unsigned int line;\n\tshort unsigned int flags;\n};\n\nstruct pollfd {\n\tint fd;\n\tshort int events;\n\tshort int revents;\n};\n\ntypedef const int tracepoint_ptr_t;\n\nstruct bpf_raw_event_map {\n\tstruct tracepoint *tp;\n\tvoid *bpf_func;\n\tu32 num_args;\n\tu32 writable_size;\n\tlong: 64;\n};\n\nstruct orc_entry {\n\ts16 sp_offset;\n\ts16 bp_offset;\n\tunsigned int sp_reg: 4;\n\tunsigned int bp_reg: 4;\n\tunsigned int type: 2;\n\tunsigned int end: 1;\n} __attribute__((packed));\n\nenum perf_event_state {\n\tPERF_EVENT_STATE_DEAD = 4294967292,\n\tPERF_EVENT_STATE_EXIT = 4294967293,\n\tPERF_EVENT_STATE_ERROR = 4294967294,\n\tPERF_EVENT_STATE_OFF = 4294967295,\n\tPERF_EVENT_STATE_INACTIVE = 0,\n\tPERF_EVENT_STATE_ACTIVE = 1,\n};\n\ntypedef struct {\n\tatomic_long_t a;\n} local_t;\n\ntypedef struct {\n\tlocal_t a;\n} local64_t;\n\nstruct perf_event_attr {\n\t__u32 type;\n\t__u32 size;\n\t__u64 config;\n\tunion {\n\t\t__u64 sample_period;\n\t\t__u64 sample_freq;\n\t};\n\t__u64 sample_type;\n\t__u64 read_format;\n\t__u64 disabled: 1;\n\t__u64 inherit: 1;\n\t__u64 pinned: 1;\n\t__u64 exclusive: 1;\n\t__u64 exclude_user: 1;\n\t__u64 exclude_kernel: 1;\n\t__u64 exclude_hv: 1;\n\t__u64 exclude_idle: 1;\n\t__u64 mmap: 1;\n\t__u64 comm: 1;\n\t__u64 freq: 1;\n\t__u64 inherit_stat: 1;\n\t__u64 enable_on_exec: 1;\n\t__u64 task: 1;\n\t__u64 watermark: 1;\n\t__u64 precise_ip: 2;\n\t__u64 mmap_data: 1;\n\t__u64 sample_id_all: 1;\n\t__u64 exclude_host: 1;\n\t__u64 exclude_guest: 1;\n\t__u64 exclude_callchain_kernel: 1;\n\t__u64 exclude_callchain_user: 1;\n\t__u64 mmap2: 1;\n\t__u64 comm_exec: 1;\n\t__u64 use_clockid: 1;\n\t__u64 context_switch: 1;\n\t__u64 write_backward: 1;\n\t__u64 namespaces: 1;\n\t__u64 ksymbol: 1;\n\t__u64 bpf_event: 1;\n\t__u64 aux_output: 1;\n\t__u64 cgroup: 1;\n\t__u64 __reserved_1: 31;\n\tunion {\n\t\t__u32 wakeup_events;\n\t\t__u32 wakeup_watermark;\n\t};\n\t__u32 bp_type;\n\tunion {\n\t\t__u64 bp_addr;\n\t\t__u64 kprobe_func;\n\t\t__u64 uprobe_path;\n\t\t__u64 config1;\n\t};\n\tunion {\n\t\t__u64 bp_len;\n\t\t__u64 kprobe_addr;\n\t\t__u64 probe_offset;\n\t\t__u64 config2;\n\t};\n\t__u64 branch_sample_type;\n\t__u64 sample_regs_user;\n\t__u32 sample_stack_user;\n\t__s32 clockid;\n\t__u64 sample_regs_intr;\n\t__u32 aux_watermark;\n\t__u16 sample_max_stack;\n\t__u16 __reserved_2;\n\t__u32 aux_sample_size;\n\t__u32 __reserved_3;\n};\n\nstruct hw_perf_event_extra {\n\tu64 config;\n\tunsigned int reg;\n\tint alloc;\n\tint idx;\n};\n\nstruct arch_hw_breakpoint {\n\tlong unsigned int address;\n\tlong unsigned int mask;\n\tu8 len;\n\tu8 type;\n};\n\nstruct hw_perf_event {\n\tunion {\n\t\tstruct {\n\t\t\tu64 config;\n\t\t\tu64 last_tag;\n\t\t\tlong unsigned int config_base;\n\t\t\tlong unsigned int event_base;\n\t\t\tint event_base_rdpmc;\n\t\t\tint idx;\n\t\t\tint last_cpu;\n\t\t\tint flags;\n\t\t\tstruct hw_perf_event_extra extra_reg;\n\t\t\tstruct hw_perf_event_extra branch_reg;\n\t\t};\n\t\tstruct {\n\t\t\tstruct hrtimer hrtimer;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head tp_list;\n\t\t};\n\t\tstruct {\n\t\t\tu64 pwr_acc;\n\t\t\tu64 ptsc;\n\t\t};\n\t\tstruct {\n\t\t\tstruct arch_hw_breakpoint info;\n\t\t\tstruct list_head bp_list;\n\t\t};\n\t\tstruct {\n\t\t\tu8 iommu_bank;\n\t\t\tu8 iommu_cntr;\n\t\t\tu16 padding;\n\t\t\tu64 conf;\n\t\t\tu64 conf1;\n\t\t};\n\t};\n\tstruct task_struct *target;\n\tvoid *addr_filters;\n\tlong unsigned int addr_filters_gen;\n\tint state;\n\tlocal64_t prev_count;\n\tu64 sample_period;\n\tu64 last_period;\n\tlocal64_t period_left;\n\tu64 interrupts_seq;\n\tu64 interrupts;\n\tu64 freq_time_stamp;\n\tu64 freq_count_stamp;\n};\n\nstruct irq_work {\n\tunion {\n\t\tstruct __call_single_node node;\n\t\tstruct {\n\t\t\tstruct llist_node llnode;\n\t\t\tatomic_t flags;\n\t\t};\n\t};\n\tvoid (*func)(struct irq_work *);\n};\n\nstruct perf_addr_filters_head {\n\tstruct list_head list;\n\traw_spinlock_t lock;\n\tunsigned int nr_file_filters;\n};\n\nstruct perf_sample_data;\n\ntypedef void (*perf_overflow_handler_t)(struct perf_event *, struct perf_sample_data *, struct pt_regs *);\n\nstruct pmu;\n\nstruct perf_buffer;\n\nstruct perf_addr_filter_range;\n\nstruct bpf_prog;\n\nstruct trace_event_call;\n\nstruct event_filter;\n\nstruct perf_event {\n\tstruct list_head event_entry;\n\tstruct list_head sibling_list;\n\tstruct list_head active_list;\n\tstruct rb_node group_node;\n\tu64 group_index;\n\tstruct list_head migrate_entry;\n\tstruct hlist_node hlist_entry;\n\tstruct list_head active_entry;\n\tint nr_siblings;\n\tint event_caps;\n\tint group_caps;\n\tstruct perf_event *group_leader;\n\tstruct pmu *pmu;\n\tvoid *pmu_private;\n\tenum perf_event_state state;\n\tunsigned int attach_state;\n\tlocal64_t count;\n\tatomic64_t child_count;\n\tu64 total_time_enabled;\n\tu64 total_time_running;\n\tu64 tstamp;\n\tu64 shadow_ctx_time;\n\tstruct perf_event_attr attr;\n\tu16 header_size;\n\tu16 id_header_size;\n\tu16 read_size;\n\tstruct hw_perf_event hw;\n\tstruct perf_event_context *ctx;\n\tatomic_long_t refcount;\n\tatomic64_t child_total_time_enabled;\n\tatomic64_t child_total_time_running;\n\tstruct mutex child_mutex;\n\tstruct list_head child_list;\n\tstruct perf_event *parent;\n\tint oncpu;\n\tint cpu;\n\tstruct list_head owner_entry;\n\tstruct task_struct *owner;\n\tstruct mutex mmap_mutex;\n\tatomic_t mmap_count;\n\tstruct perf_buffer *rb;\n\tstruct list_head rb_entry;\n\tlong unsigned int rcu_batches;\n\tint rcu_pending;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n\tint pending_wakeup;\n\tint pending_kill;\n\tint pending_disable;\n\tstruct irq_work pending;\n\tatomic_t event_limit;\n\tstruct perf_addr_filters_head addr_filters;\n\tstruct perf_addr_filter_range *addr_filter_ranges;\n\tlong unsigned int addr_filters_gen;\n\tstruct perf_event *aux_event;\n\tvoid (*destroy)(struct perf_event *);\n\tstruct callback_head callback_head;\n\tstruct pid_namespace *ns;\n\tu64 id;\n\tu64 (*clock)();\n\tperf_overflow_handler_t overflow_handler;\n\tvoid *overflow_handler_context;\n\tperf_overflow_handler_t orig_overflow_handler;\n\tstruct bpf_prog *prog;\n\tstruct trace_event_call *tp_event;\n\tstruct event_filter *filter;\n\tvoid *security;\n\tstruct list_head sb_list;\n};\n\nstruct lockdep_map {};\n\nstruct uid_gid_extent {\n\tu32 first;\n\tu32 lower_first;\n\tu32 count;\n};\n\nstruct uid_gid_map {\n\tu32 nr_extents;\n\tunion {\n\t\tstruct uid_gid_extent extent[5];\n\t\tstruct {\n\t\t\tstruct uid_gid_extent *forward;\n\t\t\tstruct uid_gid_extent *reverse;\n\t\t};\n\t};\n};\n\nstruct proc_ns_operations;\n\nstruct ns_common {\n\tatomic_long_t stashed;\n\tconst struct proc_ns_operations *ops;\n\tunsigned int inum;\n};\n\nstruct ctl_table_root;\n\nstruct ctl_table_set;\n\nstruct ctl_dir;\n\nstruct ctl_node;\n\nstruct ctl_table_header {\n\tunion {\n\t\tstruct {\n\t\t\tstruct ctl_table *ctl_table;\n\t\t\tint used;\n\t\t\tint count;\n\t\t\tint nreg;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\tstruct completion *unregistering;\n\tstruct ctl_table *ctl_table_arg;\n\tstruct ctl_table_root *root;\n\tstruct ctl_table_set *set;\n\tstruct ctl_dir *parent;\n\tstruct ctl_node *node;\n\tstruct hlist_head inodes;\n};\n\nstruct ctl_dir {\n\tstruct ctl_table_header header;\n\tstruct rb_root root;\n};\n\nstruct ctl_table_set {\n\tint (*is_seen)(struct ctl_table_set *);\n\tstruct ctl_dir dir;\n};\n\nstruct ucounts;\n\nstruct user_namespace {\n\tstruct uid_gid_map uid_map;\n\tstruct uid_gid_map gid_map;\n\tstruct uid_gid_map projid_map;\n\tatomic_t count;\n\tstruct user_namespace *parent;\n\tint level;\n\tkuid_t owner;\n\tkgid_t group;\n\tstruct ns_common ns;\n\tlong unsigned int flags;\n\tstruct list_head keyring_name_list;\n\tstruct key *user_keyring_register;\n\tstruct rw_semaphore keyring_sem;\n\tstruct work_struct work;\n\tstruct ctl_table_set set;\n\tstruct ctl_table_header *sysctls;\n\tstruct ucounts *ucounts;\n\tint ucount_max[10];\n};\n\nenum node_states {\n\tN_POSSIBLE = 0,\n\tN_ONLINE = 1,\n\tN_NORMAL_MEMORY = 2,\n\tN_HIGH_MEMORY = 2,\n\tN_MEMORY = 3,\n\tN_CPU = 4,\n\tNR_NODE_STATES = 5,\n};\n\nstruct delayed_work {\n\tstruct work_struct work;\n\tstruct timer_list timer;\n\tstruct workqueue_struct *wq;\n\tint cpu;\n};\n\nstruct rcu_work {\n\tstruct work_struct work;\n\tstruct callback_head rcu;\n\tstruct workqueue_struct *wq;\n};\n\nstruct rcu_segcblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tails[4];\n\tlong unsigned int gp_seq[4];\n\tlong int len;\n\tu8 enabled;\n\tu8 offloaded;\n};\n\nstruct srcu_node;\n\nstruct srcu_struct;\n\nstruct srcu_data {\n\tlong unsigned int srcu_lock_count[2];\n\tlong unsigned int srcu_unlock_count[2];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t lock;\n\tstruct rcu_segcblist srcu_cblist;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tbool srcu_cblist_invoking;\n\tstruct timer_list delay_work;\n\tstruct work_struct work;\n\tstruct callback_head srcu_barrier_head;\n\tstruct srcu_node *mynode;\n\tlong unsigned int grpmask;\n\tint cpu;\n\tstruct srcu_struct *ssp;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct srcu_node {\n\tspinlock_t lock;\n\tlong unsigned int srcu_have_cbs[4];\n\tlong unsigned int srcu_data_have_cbs[4];\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tstruct srcu_node *srcu_parent;\n\tint grplo;\n\tint grphi;\n};\n\nstruct srcu_struct {\n\tstruct srcu_node node[5];\n\tstruct srcu_node *level[3];\n\tstruct mutex srcu_cb_mutex;\n\tspinlock_t lock;\n\tstruct mutex srcu_gp_mutex;\n\tunsigned int srcu_idx;\n\tlong unsigned int srcu_gp_seq;\n\tlong unsigned int srcu_gp_seq_needed;\n\tlong unsigned int srcu_gp_seq_needed_exp;\n\tlong unsigned int srcu_last_gp_end;\n\tstruct srcu_data *sda;\n\tlong unsigned int srcu_barrier_seq;\n\tstruct mutex srcu_barrier_mutex;\n\tstruct completion srcu_barrier_completion;\n\tatomic_t srcu_barrier_cpu_cnt;\n\tstruct delayed_work work;\n};\n\nstruct anon_vma {\n\tstruct anon_vma *root;\n\tstruct rw_semaphore rwsem;\n\tatomic_t refcount;\n\tunsigned int degree;\n\tstruct anon_vma *parent;\n\tstruct rb_root_cached rb_root;\n};\n\nstruct mempolicy {\n\tatomic_t refcnt;\n\tshort unsigned int mode;\n\tshort unsigned int flags;\n\tunion {\n\t\tshort int preferred_node;\n\t\tnodemask_t nodes;\n\t} v;\n\tunion {\n\t\tnodemask_t cpuset_mems_allowed;\n\t\tnodemask_t user_nodemask;\n\t} w;\n};\n\nstruct linux_binprm;\n\nstruct coredump_params;\n\nstruct linux_binfmt {\n\tstruct list_head lh;\n\tstruct module *module;\n\tint (*load_binary)(struct linux_binprm *);\n\tint (*load_shlib)(struct file *);\n\tint (*core_dump)(struct coredump_params *);\n\tlong unsigned int min_coredump;\n};\n\ntypedef void (*smp_call_func_t)(void *);\n\nstruct __call_single_data {\n\tunion {\n\t\tstruct __call_single_node node;\n\t\tstruct {\n\t\t\tstruct llist_node llist;\n\t\t\tunsigned int flags;\n\t\t};\n\t};\n\tsmp_call_func_t func;\n\tvoid *info;\n};\n\nstruct ctl_node {\n\tstruct rb_node node;\n\tstruct ctl_table_header *header;\n};\n\nstruct ctl_table_root {\n\tstruct ctl_table_set default_set;\n\tstruct ctl_table_set * (*lookup)(struct ctl_table_root *);\n\tvoid (*set_ownership)(struct ctl_table_header *, struct ctl_table *, kuid_t *, kgid_t *);\n\tint (*permissions)(struct ctl_table_header *, struct ctl_table *);\n};\n\nenum umh_disable_depth {\n\tUMH_ENABLED = 0,\n\tUMH_FREEZING = 1,\n\tUMH_DISABLED = 2,\n};\n\nstruct va_alignment {\n\tint flags;\n\tlong unsigned int mask;\n\tlong unsigned int bits;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef __u64 Elf64_Addr;\n\ntypedef __u16 Elf64_Half;\n\ntypedef __u32 Elf64_Word;\n\ntypedef __u64 Elf64_Xword;\n\ntypedef __s64 Elf64_Sxword;\n\ntypedef struct {\n\tElf64_Sxword d_tag;\n\tunion {\n\t\tElf64_Xword d_val;\n\t\tElf64_Addr d_ptr;\n\t} d_un;\n} Elf64_Dyn;\n\nstruct elf64_sym {\n\tElf64_Word st_name;\n\tunsigned char st_info;\n\tunsigned char st_other;\n\tElf64_Half st_shndx;\n\tElf64_Addr st_value;\n\tElf64_Xword st_size;\n};\n\ntypedef struct elf64_sym Elf64_Sym;\n\nstruct seq_file {\n\tchar *buf;\n\tsize_t size;\n\tsize_t from;\n\tsize_t count;\n\tsize_t pad_until;\n\tloff_t index;\n\tloff_t read_pos;\n\tstruct mutex lock;\n\tconst struct seq_operations *op;\n\tint poll_event;\n\tconst struct file *file;\n\tvoid *private;\n};\n\ntypedef void (*poll_queue_proc)(struct file *, wait_queue_head_t *, struct poll_table_struct *);\n\nstruct poll_table_struct {\n\tpoll_queue_proc _qproc;\n\t__poll_t _key;\n};\n\nstruct kernel_param;\n\nstruct kernel_param_ops {\n\tunsigned int flags;\n\tint (*set)(const char *, const struct kernel_param *);\n\tint (*get)(char *, const struct kernel_param *);\n\tvoid (*free)(void *);\n};\n\nstruct kparam_string;\n\nstruct kparam_array;\n\nstruct kernel_param {\n\tconst char *name;\n\tstruct module *mod;\n\tconst struct kernel_param_ops *ops;\n\tconst u16 perm;\n\ts8 level;\n\tu8 flags;\n\tunion {\n\t\tvoid *arg;\n\t\tconst struct kparam_string *str;\n\t\tconst struct kparam_array *arr;\n\t};\n};\n\nstruct kparam_string {\n\tunsigned int maxlen;\n\tchar *string;\n};\n\nstruct kparam_array {\n\tunsigned int max;\n\tunsigned int elemsize;\n\tunsigned int *num;\n\tconst struct kernel_param_ops *ops;\n\tvoid *elem;\n};\n\nenum module_state {\n\tMODULE_STATE_LIVE = 0,\n\tMODULE_STATE_COMING = 1,\n\tMODULE_STATE_GOING = 2,\n\tMODULE_STATE_UNFORMED = 3,\n};\n\nstruct module_param_attrs;\n\nstruct module_kobject {\n\tstruct kobject kobj;\n\tstruct module *mod;\n\tstruct kobject *drivers_dir;\n\tstruct module_param_attrs *mp;\n\tstruct completion *kobj_completion;\n};\n\nstruct latch_tree_node {\n\tstruct rb_node node[2];\n};\n\nstruct mod_tree_node {\n\tstruct module *mod;\n\tstruct latch_tree_node node;\n};\n\nstruct module_layout {\n\tvoid *base;\n\tunsigned int size;\n\tunsigned int text_size;\n\tunsigned int ro_size;\n\tunsigned int ro_after_init_size;\n\tstruct mod_tree_node mtn;\n};\n\nstruct mod_arch_specific {\n\tunsigned int num_orcs;\n\tint *orc_unwind_ip;\n\tstruct orc_entry *orc_unwind;\n};\n\nstruct mod_kallsyms {\n\tElf64_Sym *symtab;\n\tunsigned int num_symtab;\n\tchar *strtab;\n\tchar *typetab;\n};\n\nstruct module_attribute;\n\nstruct exception_table_entry;\n\nstruct module_sect_attrs;\n\nstruct module_notes_attrs;\n\nstruct trace_eval_map;\n\nstruct error_injection_entry;\n\nstruct module {\n\tenum module_state state;\n\tstruct list_head list;\n\tchar name[56];\n\tstruct module_kobject mkobj;\n\tstruct module_attribute *modinfo_attrs;\n\tconst char *version;\n\tconst char *srcversion;\n\tstruct kobject *holders_dir;\n\tconst struct kernel_symbol *syms;\n\tconst s32 *crcs;\n\tunsigned int num_syms;\n\tstruct mutex param_lock;\n\tstruct kernel_param *kp;\n\tunsigned int num_kp;\n\tunsigned int num_gpl_syms;\n\tconst struct kernel_symbol *gpl_syms;\n\tconst s32 *gpl_crcs;\n\tbool async_probe_requested;\n\tconst struct kernel_symbol *gpl_future_syms;\n\tconst s32 *gpl_future_crcs;\n\tunsigned int num_gpl_future_syms;\n\tunsigned int num_exentries;\n\tstruct exception_table_entry *extable;\n\tint (*init)();\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct module_layout core_layout;\n\tstruct module_layout init_layout;\n\tstruct mod_arch_specific arch;\n\tlong unsigned int taints;\n\tunsigned int num_bugs;\n\tstruct list_head bug_list;\n\tstruct bug_entry *bug_table;\n\tstruct mod_kallsyms *kallsyms;\n\tstruct mod_kallsyms core_kallsyms;\n\tstruct module_sect_attrs *sect_attrs;\n\tstruct module_notes_attrs *notes_attrs;\n\tchar *args;\n\tvoid *percpu;\n\tunsigned int percpu_size;\n\tvoid *noinstr_text_start;\n\tunsigned int noinstr_text_size;\n\tunsigned int num_tracepoints;\n\ttracepoint_ptr_t *tracepoints_ptrs;\n\tunsigned int num_srcu_structs;\n\tstruct srcu_struct **srcu_struct_ptrs;\n\tunsigned int num_bpf_raw_events;\n\tstruct bpf_raw_event_map *bpf_raw_events;\n\tstruct jump_entry *jump_entries;\n\tunsigned int num_jump_entries;\n\tunsigned int num_trace_bprintk_fmt;\n\tconst char **trace_bprintk_fmt_start;\n\tstruct trace_event_call **trace_events;\n\tunsigned int num_trace_events;\n\tstruct trace_eval_map **trace_evals;\n\tunsigned int num_trace_evals;\n\tvoid *kprobes_text_start;\n\tunsigned int kprobes_text_size;\n\tlong unsigned int *kprobe_blacklist;\n\tunsigned int num_kprobe_blacklist;\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tvoid (*exit)();\n\tatomic_t refcnt;\n\tstruct error_injection_entry *ei_funcs;\n\tunsigned int num_ei_funcs;\n};\n\nstruct error_injection_entry {\n\tlong unsigned int addr;\n\tint etype;\n};\n\nstruct module_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct module_attribute *, struct module_kobject *, char *);\n\tssize_t (*store)(struct module_attribute *, struct module_kobject *, const char *, size_t);\n\tvoid (*setup)(struct module *, const char *);\n\tint (*test)(struct module *);\n\tvoid (*free)(struct module *);\n};\n\nstruct exception_table_entry {\n\tint insn;\n\tint fixup;\n\tint handler;\n};\n\nstruct trace_event_functions;\n\nstruct trace_event {\n\tstruct hlist_node node;\n\tstruct list_head list;\n\tint type;\n\tstruct trace_event_functions *funcs;\n};\n\nstruct trace_event_class;\n\nstruct bpf_prog_array;\n\nstruct trace_event_call {\n\tstruct list_head list;\n\tstruct trace_event_class *class;\n\tunion {\n\t\tchar *name;\n\t\tstruct tracepoint *tp;\n\t};\n\tstruct trace_event event;\n\tchar *print_fmt;\n\tstruct event_filter *filter;\n\tvoid *mod;\n\tvoid *data;\n\tint flags;\n\tint perf_refcount;\n\tstruct hlist_head *perf_events;\n\tstruct bpf_prog_array *prog_array;\n\tint (*perf_perm)(struct trace_event_call *, struct perf_event *);\n};\n\nstruct trace_eval_map {\n\tconst char *system;\n\tconst char *eval_string;\n\tlong unsigned int eval_value;\n};\n\nstruct fs_pin;\n\nstruct pid_namespace {\n\tstruct kref kref;\n\tstruct idr idr;\n\tstruct callback_head rcu;\n\tunsigned int pid_allocated;\n\tstruct task_struct *child_reaper;\n\tstruct kmem_cache *pid_cachep;\n\tunsigned int level;\n\tstruct pid_namespace *parent;\n\tstruct fs_pin *bacct;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tint reboot;\n\tstruct ns_common ns;\n};\n\nstruct task_cputime {\n\tu64 stime;\n\tu64 utime;\n\tlong long unsigned int sum_exec_runtime;\n};\n\nstruct uts_namespace;\n\nstruct ipc_namespace;\n\nstruct mnt_namespace;\n\nstruct net;\n\nstruct time_namespace;\n\nstruct cgroup_namespace;\n\nstruct nsproxy {\n\tatomic_t count;\n\tstruct uts_namespace *uts_ns;\n\tstruct ipc_namespace *ipc_ns;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct pid_namespace *pid_ns_for_children;\n\tstruct net *net_ns;\n\tstruct time_namespace *time_ns;\n\tstruct time_namespace *time_ns_for_children;\n\tstruct cgroup_namespace *cgroup_ns;\n};\n\nstruct bio;\n\nstruct bio_list {\n\tstruct bio *head;\n\tstruct bio *tail;\n};\n\nstruct blk_plug {\n\tstruct list_head mq_list;\n\tstruct list_head cb_list;\n\tshort unsigned int rq_count;\n\tbool multiple_queues;\n};\n\nstruct reclaim_state {\n\tlong unsigned int reclaimed_slab;\n};\n\ntypedef int congested_fn(void *, int);\n\nstruct fprop_local_percpu {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\traw_spinlock_t lock;\n};\n\nenum wb_reason {\n\tWB_REASON_BACKGROUND = 0,\n\tWB_REASON_VMSCAN = 1,\n\tWB_REASON_SYNC = 2,\n\tWB_REASON_PERIODIC = 3,\n\tWB_REASON_LAPTOP_TIMER = 4,\n\tWB_REASON_FS_FREE_SPACE = 5,\n\tWB_REASON_FORKER_THREAD = 6,\n\tWB_REASON_FOREIGN_FLUSH = 7,\n\tWB_REASON_MAX = 8,\n};\n\nstruct bdi_writeback_congested;\n\nstruct bdi_writeback {\n\tstruct backing_dev_info *bdi;\n\tlong unsigned int state;\n\tlong unsigned int last_old_flush;\n\tstruct list_head b_dirty;\n\tstruct list_head b_io;\n\tstruct list_head b_more_io;\n\tstruct list_head b_dirty_time;\n\tspinlock_t list_lock;\n\tstruct percpu_counter stat[4];\n\tstruct bdi_writeback_congested *congested;\n\tlong unsigned int bw_time_stamp;\n\tlong unsigned int dirtied_stamp;\n\tlong unsigned int written_stamp;\n\tlong unsigned int write_bandwidth;\n\tlong unsigned int avg_write_bandwidth;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tstruct fprop_local_percpu completions;\n\tint dirty_exceeded;\n\tenum wb_reason start_all_reason;\n\tspinlock_t work_lock;\n\tstruct list_head work_list;\n\tstruct delayed_work dwork;\n\tlong unsigned int dirty_sleep;\n\tstruct list_head bdi_node;\n};\n\nstruct backing_dev_info {\n\tu64 id;\n\tstruct rb_node rb_node;\n\tstruct list_head bdi_list;\n\tlong unsigned int ra_pages;\n\tlong unsigned int io_pages;\n\tcongested_fn *congested_fn;\n\tvoid *congested_data;\n\tstruct kref refcnt;\n\tunsigned int capabilities;\n\tunsigned int min_ratio;\n\tunsigned int max_ratio;\n\tunsigned int max_prop_frac;\n\tatomic_long_t tot_write_bandwidth;\n\tstruct bdi_writeback wb;\n\tstruct list_head wb_list;\n\tstruct bdi_writeback_congested *wb_congested;\n\twait_queue_head_t wb_waitq;\n\tstruct device *dev;\n\tchar dev_name[64];\n\tstruct device *owner;\n\tstruct timer_list laptop_mode_wb_timer;\n\tstruct dentry *debug_dir;\n};\n\nstruct cgroup_subsys_state;\n\nstruct cgroup;\n\nstruct css_set {\n\tstruct cgroup_subsys_state *subsys[4];\n\trefcount_t refcount;\n\tstruct css_set *dom_cset;\n\tstruct cgroup *dfl_cgrp;\n\tint nr_tasks;\n\tstruct list_head tasks;\n\tstruct list_head mg_tasks;\n\tstruct list_head dying_tasks;\n\tstruct list_head task_iters;\n\tstruct list_head e_cset_node[4];\n\tstruct list_head threaded_csets;\n\tstruct list_head threaded_csets_node;\n\tstruct hlist_node hlist;\n\tstruct list_head cgrp_links;\n\tstruct list_head mg_preload_node;\n\tstruct list_head mg_node;\n\tstruct cgroup *mg_src_cgrp;\n\tstruct cgroup *mg_dst_cgrp;\n\tstruct css_set *mg_dst_cset;\n\tbool dead;\n\tstruct callback_head callback_head;\n};\n\nstruct perf_event_groups {\n\tstruct rb_root tree;\n\tu64 index;\n};\n\nstruct perf_event_context {\n\tstruct pmu *pmu;\n\traw_spinlock_t lock;\n\tstruct mutex mutex;\n\tstruct list_head active_ctx_list;\n\tstruct perf_event_groups pinned_groups;\n\tstruct perf_event_groups flexible_groups;\n\tstruct list_head event_list;\n\tstruct list_head pinned_active;\n\tstruct list_head flexible_active;\n\tint nr_events;\n\tint nr_active;\n\tint is_active;\n\tint nr_stat;\n\tint nr_freq;\n\tint rotate_disable;\n\tint rotate_necessary;\n\trefcount_t refcount;\n\tstruct task_struct *task;\n\tu64 time;\n\tu64 timestamp;\n\tstruct perf_event_context *parent_ctx;\n\tu64 parent_gen;\n\tu64 generation;\n\tint pin_count;\n\tvoid *task_ctx_data;\n\tstruct callback_head callback_head;\n};\n\nstruct task_delay_info {\n\traw_spinlock_t lock;\n\tunsigned int flags;\n\tu64 blkio_start;\n\tu64 blkio_delay;\n\tu64 swapin_delay;\n\tu32 blkio_count;\n\tu32 swapin_count;\n\tu64 freepages_start;\n\tu64 freepages_delay;\n\tu64 thrashing_start;\n\tu64 thrashing_delay;\n\tu32 freepages_count;\n\tu32 thrashing_count;\n};\n\nstruct cgroup_subsys;\n\nstruct cgroup_subsys_state {\n\tstruct cgroup *cgroup;\n\tstruct cgroup_subsys *ss;\n\tstruct percpu_ref refcnt;\n\tstruct list_head sibling;\n\tstruct list_head children;\n\tstruct list_head rstat_css_node;\n\tint id;\n\tunsigned int flags;\n\tu64 serial_nr;\n\tatomic_t online_cnt;\n\tstruct work_struct destroy_work;\n\tstruct rcu_work destroy_rwork;\n\tstruct cgroup_subsys_state *parent;\n};\n\nstruct cgroup_file {\n\tstruct kernfs_node *kn;\n\tlong unsigned int notified_at;\n\tstruct timer_list notify_timer;\n};\n\nstruct cgroup_base_stat {\n\tstruct task_cputime cputime;\n};\n\nstruct psi_group {};\n\nstruct cgroup_bpf {\n\tstruct bpf_prog_array *effective[34];\n\tstruct list_head progs[34];\n\tu32 flags[34];\n\tstruct bpf_prog_array *inactive;\n\tstruct percpu_ref refcnt;\n\tstruct work_struct release_work;\n};\n\nstruct cgroup_freezer_state {\n\tbool freeze;\n\tint e_freeze;\n\tint nr_frozen_descendants;\n\tint nr_frozen_tasks;\n};\n\nstruct cgroup_root;\n\nstruct cgroup_rstat_cpu;\n\nstruct cgroup {\n\tstruct cgroup_subsys_state self;\n\tlong unsigned int flags;\n\tint level;\n\tint max_depth;\n\tint nr_descendants;\n\tint nr_dying_descendants;\n\tint max_descendants;\n\tint nr_populated_csets;\n\tint nr_populated_domain_children;\n\tint nr_populated_threaded_children;\n\tint nr_threaded_children;\n\tstruct kernfs_node *kn;\n\tstruct cgroup_file procs_file;\n\tstruct cgroup_file events_file;\n\tu16 subtree_control;\n\tu16 subtree_ss_mask;\n\tu16 old_subtree_control;\n\tu16 old_subtree_ss_mask;\n\tstruct cgroup_subsys_state *subsys[4];\n\tstruct cgroup_root *root;\n\tstruct list_head cset_links;\n\tstruct list_head e_csets[4];\n\tstruct cgroup *dom_cgrp;\n\tstruct cgroup *old_dom_cgrp;\n\tstruct cgroup_rstat_cpu *rstat_cpu;\n\tstruct list_head rstat_css_list;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup_base_stat bstat;\n\tstruct prev_cputime prev_cputime;\n\tstruct list_head pidlists;\n\tstruct mutex pidlist_mutex;\n\twait_queue_head_t offline_waitq;\n\tstruct work_struct release_agent_work;\n\tstruct psi_group psi;\n\tstruct cgroup_bpf bpf;\n\tatomic_t congestion_count;\n\tstruct cgroup_freezer_state freezer;\n\tu64 ancestor_ids[0];\n};\n\nstruct taskstats {\n\t__u16 version;\n\t__u32 ac_exitcode;\n\t__u8 ac_flag;\n\t__u8 ac_nice;\n\t__u64 cpu_count;\n\t__u64 cpu_delay_total;\n\t__u64 blkio_count;\n\t__u64 blkio_delay_total;\n\t__u64 swapin_count;\n\t__u64 swapin_delay_total;\n\t__u64 cpu_run_real_total;\n\t__u64 cpu_run_virtual_total;\n\tchar ac_comm[32];\n\t__u8 ac_sched;\n\t__u8 ac_pad[3];\n\tint: 32;\n\t__u32 ac_uid;\n\t__u32 ac_gid;\n\t__u32 ac_pid;\n\t__u32 ac_ppid;\n\t__u32 ac_btime;\n\t__u64 ac_etime;\n\t__u64 ac_utime;\n\t__u64 ac_stime;\n\t__u64 ac_minflt;\n\t__u64 ac_majflt;\n\t__u64 coremem;\n\t__u64 virtmem;\n\t__u64 hiwater_rss;\n\t__u64 hiwater_vm;\n\t__u64 read_char;\n\t__u64 write_char;\n\t__u64 read_syscalls;\n\t__u64 write_syscalls;\n\t__u64 read_bytes;\n\t__u64 write_bytes;\n\t__u64 cancelled_write_bytes;\n\t__u64 nvcsw;\n\t__u64 nivcsw;\n\t__u64 ac_utimescaled;\n\t__u64 ac_stimescaled;\n\t__u64 cpu_scaled_run_real_total;\n\t__u64 freepages_count;\n\t__u64 freepages_delay_total;\n\t__u64 thrashing_count;\n\t__u64 thrashing_delay_total;\n\t__u64 ac_btime64;\n};\n\ntypedef unsigned int blk_qc_t;\n\ntypedef blk_qc_t make_request_fn(struct request_queue *, struct bio *);\n\nstruct blk_rq_stat {\n\tu64 mean;\n\tu64 min;\n\tu64 max;\n\tu32 nr_samples;\n\tu64 batch;\n};\n\nenum blk_zoned_model {\n\tBLK_ZONED_NONE = 0,\n\tBLK_ZONED_HA = 1,\n\tBLK_ZONED_HM = 2,\n};\n\nstruct queue_limits {\n\tlong unsigned int bounce_pfn;\n\tlong unsigned int seg_boundary_mask;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int max_hw_sectors;\n\tunsigned int max_dev_sectors;\n\tunsigned int chunk_sectors;\n\tunsigned int max_sectors;\n\tunsigned int max_segment_size;\n\tunsigned int physical_block_size;\n\tunsigned int logical_block_size;\n\tunsigned int alignment_offset;\n\tunsigned int io_min;\n\tunsigned int io_opt;\n\tunsigned int max_discard_sectors;\n\tunsigned int max_hw_discard_sectors;\n\tunsigned int max_write_same_sectors;\n\tunsigned int max_write_zeroes_sectors;\n\tunsigned int max_zone_append_sectors;\n\tunsigned int discard_granularity;\n\tunsigned int discard_alignment;\n\tshort unsigned int max_segments;\n\tshort unsigned int max_integrity_segments;\n\tshort unsigned int max_discard_segments;\n\tunsigned char misaligned;\n\tunsigned char discard_misaligned;\n\tunsigned char raid_partial_stripes_expensive;\n\tenum blk_zoned_model zoned;\n};\n\nstruct bsg_ops;\n\nstruct bsg_class_device {\n\tstruct device *class_dev;\n\tint minor;\n\tstruct request_queue *queue;\n\tconst struct bsg_ops *ops;\n};\n\ntypedef void *mempool_alloc_t(gfp_t, void *);\n\ntypedef void mempool_free_t(void *, void *);\n\nstruct mempool_s {\n\tspinlock_t lock;\n\tint min_nr;\n\tint curr_nr;\n\tvoid **elements;\n\tvoid *pool_data;\n\tmempool_alloc_t *alloc;\n\tmempool_free_t *free;\n\twait_queue_head_t wait;\n};\n\ntypedef struct mempool_s mempool_t;\n\nstruct bio_set {\n\tstruct kmem_cache *bio_slab;\n\tunsigned int front_pad;\n\tmempool_t bio_pool;\n\tmempool_t bvec_pool;\n\tspinlock_t rescue_lock;\n\tstruct bio_list rescue_list;\n\tstruct work_struct rescue_work;\n\tstruct workqueue_struct *rescue_workqueue;\n};\n\nstruct request;\n\nstruct elevator_queue;\n\nstruct blk_queue_stats;\n\nstruct rq_qos;\n\nstruct blk_mq_ops;\n\nstruct blk_mq_ctx;\n\nstruct blk_mq_hw_ctx;\n\nstruct blk_stat_callback;\n\nstruct blk_trace;\n\nstruct blk_flush_queue;\n\nstruct blk_mq_tag_set;\n\nstruct request_queue {\n\tstruct request *last_merge;\n\tstruct elevator_queue *elevator;\n\tstruct blk_queue_stats *stats;\n\tstruct rq_qos *rq_qos;\n\tmake_request_fn *make_request_fn;\n\tconst struct blk_mq_ops *mq_ops;\n\tstruct blk_mq_ctx *queue_ctx;\n\tunsigned int queue_depth;\n\tstruct blk_mq_hw_ctx **queue_hw_ctx;\n\tunsigned int nr_hw_queues;\n\tstruct backing_dev_info *backing_dev_info;\n\tvoid *queuedata;\n\tlong unsigned int queue_flags;\n\tatomic_t pm_only;\n\tint id;\n\tgfp_t bounce_gfp;\n\tspinlock_t queue_lock;\n\tstruct kobject kobj;\n\tstruct kobject *mq_kobj;\n\tstruct device *dev;\n\tint rpm_status;\n\tunsigned int nr_pending;\n\tlong unsigned int nr_requests;\n\tunsigned int dma_pad_mask;\n\tunsigned int dma_alignment;\n\tunsigned int rq_timeout;\n\tint poll_nsec;\n\tstruct blk_stat_callback *poll_cb;\n\tstruct blk_rq_stat poll_stat[16];\n\tstruct timer_list timeout;\n\tstruct work_struct timeout_work;\n\tstruct list_head icq_list;\n\tstruct queue_limits limits;\n\tunsigned int required_elevator_features;\n\tunsigned int sg_timeout;\n\tunsigned int sg_reserved_size;\n\tint node;\n\tstruct blk_trace *blk_trace;\n\tstruct mutex blk_trace_mutex;\n\tstruct blk_flush_queue *fq;\n\tstruct list_head requeue_list;\n\tspinlock_t requeue_lock;\n\tstruct delayed_work requeue_work;\n\tstruct mutex sysfs_lock;\n\tstruct mutex sysfs_dir_lock;\n\tstruct list_head unused_hctx_list;\n\tspinlock_t unused_hctx_lock;\n\tint mq_freeze_depth;\n\tstruct bsg_class_device bsg_dev;\n\tstruct callback_head callback_head;\n\twait_queue_head_t mq_freeze_wq;\n\tstruct mutex mq_freeze_lock;\n\tstruct percpu_ref q_usage_counter;\n\tstruct blk_mq_tag_set *tag_set;\n\tstruct list_head tag_set_list;\n\tstruct bio_set bio_split;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct dentry *rqos_debugfs_dir;\n\tbool mq_sysfs_init_done;\n\tsize_t cmd_size;\n\tstruct work_struct release_work;\n\tu64 write_hints[5];\n};\n\nenum writeback_sync_modes {\n\tWB_SYNC_NONE = 0,\n\tWB_SYNC_ALL = 1,\n};\n\nstruct writeback_control {\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int for_kupdate: 1;\n\tunsigned int for_background: 1;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int for_reclaim: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int no_cgroup_owner: 1;\n\tunsigned int punt_to_cgroup: 1;\n};\n\nstruct readahead_control {\n\tstruct file *file;\n\tstruct address_space *mapping;\n\tlong unsigned int _index;\n\tunsigned int _nr_pages;\n\tunsigned int _batch_count;\n};\n\nstruct swap_cluster_info {\n\tspinlock_t lock;\n\tunsigned int data: 24;\n\tunsigned int flags: 8;\n};\n\nstruct swap_cluster_list {\n\tstruct swap_cluster_info head;\n\tstruct swap_cluster_info tail;\n};\n\nstruct percpu_cluster;\n\nstruct swap_info_struct {\n\tlong unsigned int flags;\n\tshort int prio;\n\tstruct plist_node list;\n\tsigned char type;\n\tunsigned int max;\n\tunsigned char *swap_map;\n\tstruct swap_cluster_info *cluster_info;\n\tstruct swap_cluster_list free_clusters;\n\tunsigned int lowest_bit;\n\tunsigned int highest_bit;\n\tunsigned int pages;\n\tunsigned int inuse_pages;\n\tunsigned int cluster_next;\n\tunsigned int cluster_nr;\n\tunsigned int *cluster_next_cpu;\n\tstruct percpu_cluster *percpu_cluster;\n\tstruct rb_root swap_extent_root;\n\tstruct block_device *bdev;\n\tstruct file *swap_file;\n\tunsigned int old_block_size;\n\tspinlock_t lock;\n\tspinlock_t cont_lock;\n\tstruct work_struct discard_work;\n\tstruct swap_cluster_list discard_clusters;\n\tstruct plist_node avail_lists[0];\n};\n\nstruct disk_stats;\n\nstruct partition_meta_info;\n\nstruct hd_struct {\n\tsector_t start_sect;\n\tsector_t nr_sects;\n\tlong unsigned int stamp;\n\tstruct disk_stats *dkstats;\n\tstruct percpu_ref ref;\n\tsector_t alignment_offset;\n\tunsigned int discard_alignment;\n\tstruct device __dev;\n\tstruct kobject *holder_dir;\n\tint policy;\n\tint partno;\n\tstruct partition_meta_info *info;\n\tstruct rcu_work rcu_work;\n};\n\nstruct disk_part_tbl;\n\nstruct block_device_operations;\n\nstruct timer_rand_state;\n\nstruct disk_events;\n\nstruct cdrom_device_info;\n\nstruct badblocks;\n\nstruct gendisk {\n\tint major;\n\tint first_minor;\n\tint minors;\n\tchar disk_name[32];\n\tshort unsigned int events;\n\tshort unsigned int event_flags;\n\tstruct disk_part_tbl *part_tbl;\n\tstruct hd_struct part0;\n\tconst struct block_device_operations *fops;\n\tstruct request_queue *queue;\n\tvoid *private_data;\n\tint flags;\n\tstruct rw_semaphore lookup_sem;\n\tstruct kobject *slave_dir;\n\tstruct timer_rand_state *random;\n\tatomic_t sync_io;\n\tstruct disk_events *ev;\n\tstruct cdrom_device_info *cdi;\n\tint node_id;\n\tstruct badblocks *bb;\n\tstruct lockdep_map lockdep_map;\n};\n\nstruct cdev {\n\tstruct kobject kobj;\n\tstruct module *owner;\n\tconst struct file_operations *ops;\n\tstruct list_head list;\n\tdev_t dev;\n\tunsigned int count;\n};\n\nstruct fc_log;\n\nstruct p_log {\n\tconst char *prefix;\n\tstruct fc_log *log;\n};\n\nenum fs_context_purpose {\n\tFS_CONTEXT_FOR_MOUNT = 0,\n\tFS_CONTEXT_FOR_SUBMOUNT = 1,\n\tFS_CONTEXT_FOR_RECONFIGURE = 2,\n};\n\nenum fs_context_phase {\n\tFS_CONTEXT_CREATE_PARAMS = 0,\n\tFS_CONTEXT_CREATING = 1,\n\tFS_CONTEXT_AWAITING_MOUNT = 2,\n\tFS_CONTEXT_AWAITING_RECONF = 3,\n\tFS_CONTEXT_RECONF_PARAMS = 4,\n\tFS_CONTEXT_RECONFIGURING = 5,\n\tFS_CONTEXT_FAILED = 6,\n};\n\nstruct fs_context_operations;\n\nstruct fs_context {\n\tconst struct fs_context_operations *ops;\n\tstruct mutex uapi_mutex;\n\tstruct file_system_type *fs_type;\n\tvoid *fs_private;\n\tvoid *sget_key;\n\tstruct dentry *root;\n\tstruct user_namespace *user_ns;\n\tstruct net *net_ns;\n\tconst struct cred *cred;\n\tstruct p_log log;\n\tconst char *source;\n\tvoid *security;\n\tvoid *s_fs_info;\n\tunsigned int sb_flags;\n\tunsigned int sb_flags_mask;\n\tunsigned int s_iflags;\n\tunsigned int lsm_flags;\n\tenum fs_context_purpose purpose: 8;\n\tenum fs_context_phase phase: 8;\n\tbool need_free: 1;\n\tbool global: 1;\n\tbool oldapi: 1;\n};\n\nstruct audit_names;\n\nstruct filename {\n\tconst char *name;\n\tconst char *uptr;\n\tint refcnt;\n\tstruct audit_names *aname;\n\tconst char iname[0];\n};\n\ntypedef u8 blk_status_t;\n\nstruct bvec_iter {\n\tsector_t bi_sector;\n\tunsigned int bi_size;\n\tunsigned int bi_idx;\n\tunsigned int bi_bvec_done;\n};\n\ntypedef void bio_end_io_t(struct bio *);\n\nstruct bio_vec {\n\tstruct page *bv_page;\n\tunsigned int bv_len;\n\tunsigned int bv_offset;\n};\n\nstruct bio {\n\tstruct bio *bi_next;\n\tstruct gendisk *bi_disk;\n\tunsigned int bi_opf;\n\tshort unsigned int bi_flags;\n\tshort unsigned int bi_ioprio;\n\tshort unsigned int bi_write_hint;\n\tblk_status_t bi_status;\n\tu8 bi_partno;\n\tatomic_t __bi_remaining;\n\tstruct bvec_iter bi_iter;\n\tbio_end_io_t *bi_end_io;\n\tvoid *bi_private;\n\tunion {\t};\n\tshort unsigned int bi_vcnt;\n\tshort unsigned int bi_max_vecs;\n\tatomic_t __bi_cnt;\n\tstruct bio_vec *bi_io_vec;\n\tstruct bio_set *bi_pool;\n\tstruct bio_vec bi_inline_vecs[0];\n};\n\nstruct linux_binprm {\n\tstruct vm_area_struct *vma;\n\tlong unsigned int vma_pages;\n\tstruct mm_struct *mm;\n\tlong unsigned int p;\n\tlong unsigned int argmin;\n\tunsigned int have_execfd: 1;\n\tunsigned int execfd_creds: 1;\n\tunsigned int secureexec: 1;\n\tunsigned int point_of_no_return: 1;\n\tstruct file *executable;\n\tstruct file *interpreter;\n\tstruct file *file;\n\tstruct cred *cred;\n\tint unsafe;\n\tunsigned int per_clear;\n\tint argc;\n\tint envc;\n\tconst char *filename;\n\tconst char *interp;\n\tunsigned int interp_flags;\n\tint execfd;\n\tlong unsigned int loader;\n\tlong unsigned int exec;\n\tstruct rlimit rlim_stack;\n\tchar buf[256];\n};\n\nstruct coredump_params {\n\tconst kernel_siginfo_t *siginfo;\n\tstruct pt_regs *regs;\n\tstruct file *file;\n\tlong unsigned int limit;\n\tlong unsigned int mm_flags;\n\tloff_t written;\n\tloff_t pos;\n};\n\nstruct ring_buffer_event {\n\tu32 type_len: 5;\n\tu32 time_delta: 27;\n\tu32 array[0];\n};\n\nstruct seq_buf {\n\tchar *buffer;\n\tsize_t size;\n\tsize_t len;\n\tloff_t readpos;\n};\n\nstruct trace_seq {\n\tunsigned char buffer[4096];\n\tstruct seq_buf seq;\n\tint full;\n};\n\nenum perf_sw_ids {\n\tPERF_COUNT_SW_CPU_CLOCK = 0,\n\tPERF_COUNT_SW_TASK_CLOCK = 1,\n\tPERF_COUNT_SW_PAGE_FAULTS = 2,\n\tPERF_COUNT_SW_CONTEXT_SWITCHES = 3,\n\tPERF_COUNT_SW_CPU_MIGRATIONS = 4,\n\tPERF_COUNT_SW_PAGE_FAULTS_MIN = 5,\n\tPERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,\n\tPERF_COUNT_SW_ALIGNMENT_FAULTS = 7,\n\tPERF_COUNT_SW_EMULATION_FAULTS = 8,\n\tPERF_COUNT_SW_DUMMY = 9,\n\tPERF_COUNT_SW_BPF_OUTPUT = 10,\n\tPERF_COUNT_SW_MAX = 11,\n};\n\nunion perf_mem_data_src {\n\t__u64 val;\n\tstruct {\n\t\t__u64 mem_op: 5;\n\t\t__u64 mem_lvl: 14;\n\t\t__u64 mem_snoop: 5;\n\t\t__u64 mem_lock: 2;\n\t\t__u64 mem_dtlb: 7;\n\t\t__u64 mem_lvl_num: 4;\n\t\t__u64 mem_remote: 1;\n\t\t__u64 mem_snoopx: 2;\n\t\t__u64 mem_rsvd: 24;\n\t};\n};\n\nstruct perf_branch_entry {\n\t__u64 from;\n\t__u64 to;\n\t__u64 mispred: 1;\n\t__u64 predicted: 1;\n\t__u64 in_tx: 1;\n\t__u64 abort: 1;\n\t__u64 cycles: 16;\n\t__u64 type: 4;\n\t__u64 reserved: 40;\n};\n\nstruct new_utsname {\n\tchar sysname[65];\n\tchar nodename[65];\n\tchar release[65];\n\tchar version[65];\n\tchar machine[65];\n\tchar domainname[65];\n};\n\nstruct uts_namespace {\n\tstruct kref kref;\n\tstruct new_utsname name;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct ns_common ns;\n};\n\nstruct cgroup_namespace {\n\trefcount_t count;\n\tstruct ns_common ns;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct css_set *root_cset;\n};\n\nstruct nsset {\n\tunsigned int flags;\n\tstruct nsproxy *nsproxy;\n\tstruct fs_struct *fs;\n\tconst struct cred *cred;\n};\n\nstruct proc_ns_operations {\n\tconst char *name;\n\tconst char *real_ns_name;\n\tint type;\n\tstruct ns_common * (*get)(struct task_struct *);\n\tvoid (*put)(struct ns_common *);\n\tint (*install)(struct nsset *, struct ns_common *);\n\tstruct user_namespace * (*owner)(struct ns_common *);\n\tstruct ns_common * (*get_parent)(struct ns_common *);\n};\n\nstruct ucounts {\n\tstruct hlist_node node;\n\tstruct user_namespace *ns;\n\tkuid_t uid;\n\tint count;\n\tatomic_t ucount[10];\n};\n\nstruct perf_guest_info_callbacks {\n\tint (*is_in_guest)();\n\tint (*is_user_mode)();\n\tlong unsigned int (*get_guest_ip)();\n\tvoid (*handle_intel_pt_intr)();\n};\n\nstruct perf_cpu_context;\n\nstruct perf_output_handle;\n\nstruct pmu {\n\tstruct list_head entry;\n\tstruct module *module;\n\tstruct device *dev;\n\tconst struct attribute_group **attr_groups;\n\tconst struct attribute_group **attr_update;\n\tconst char *name;\n\tint type;\n\tint capabilities;\n\tint *pmu_disable_count;\n\tstruct perf_cpu_context *pmu_cpu_context;\n\tatomic_t exclusive_cnt;\n\tint task_ctx_nr;\n\tint hrtimer_interval_ms;\n\tunsigned int nr_addr_filters;\n\tvoid (*pmu_enable)(struct pmu *);\n\tvoid (*pmu_disable)(struct pmu *);\n\tint (*event_init)(struct perf_event *);\n\tvoid (*event_mapped)(struct perf_event *, struct mm_struct *);\n\tvoid (*event_unmapped)(struct perf_event *, struct mm_struct *);\n\tint (*add)(struct perf_event *, int);\n\tvoid (*del)(struct perf_event *, int);\n\tvoid (*start)(struct perf_event *, int);\n\tvoid (*stop)(struct perf_event *, int);\n\tvoid (*read)(struct perf_event *);\n\tvoid (*start_txn)(struct pmu *, unsigned int);\n\tint (*commit_txn)(struct pmu *);\n\tvoid (*cancel_txn)(struct pmu *);\n\tint (*event_idx)(struct perf_event *);\n\tvoid (*sched_task)(struct perf_event_context *, bool);\n\tsize_t task_ctx_size;\n\tvoid (*swap_task_ctx)(struct perf_event_context *, struct perf_event_context *);\n\tvoid * (*setup_aux)(struct perf_event *, void **, int, bool);\n\tvoid (*free_aux)(void *);\n\tlong int (*snapshot_aux)(struct perf_event *, struct perf_output_handle *, long unsigned int);\n\tint (*addr_filters_validate)(struct list_head *);\n\tvoid (*addr_filters_sync)(struct perf_event *);\n\tint (*aux_output_match)(struct perf_event *);\n\tint (*filter_match)(struct perf_event *);\n\tint (*check_period)(struct perf_event *, u64);\n};\n\nenum irq_domain_bus_token {\n\tDOMAIN_BUS_ANY = 0,\n\tDOMAIN_BUS_WIRED = 1,\n\tDOMAIN_BUS_GENERIC_MSI = 2,\n\tDOMAIN_BUS_PCI_MSI = 3,\n\tDOMAIN_BUS_PLATFORM_MSI = 4,\n\tDOMAIN_BUS_NEXUS = 5,\n\tDOMAIN_BUS_IPI = 6,\n\tDOMAIN_BUS_FSL_MC_MSI = 7,\n\tDOMAIN_BUS_TI_SCI_INTA_MSI = 8,\n\tDOMAIN_BUS_WAKEUP = 9,\n};\n\nstruct irq_domain_ops;\n\nstruct irq_domain_chip_generic;\n\nstruct irq_domain {\n\tstruct list_head link;\n\tconst char *name;\n\tconst struct irq_domain_ops *ops;\n\tvoid *host_data;\n\tunsigned int flags;\n\tunsigned int mapcount;\n\tstruct fwnode_handle *fwnode;\n\tenum irq_domain_bus_token bus_token;\n\tstruct irq_domain_chip_generic *gc;\n\tstruct irq_domain *parent;\n\tirq_hw_number_t hwirq_max;\n\tunsigned int revmap_direct_max_irq;\n\tunsigned int revmap_size;\n\tstruct xarray revmap_tree;\n\tstruct mutex revmap_tree_mutex;\n\tunsigned int linear_revmap[0];\n};\n\ntypedef u32 phandle;\n\nstruct property;\n\nstruct device_node {\n\tconst char *name;\n\tphandle phandle;\n\tconst char *full_name;\n\tstruct fwnode_handle fwnode;\n\tstruct property *properties;\n\tstruct property *deadprops;\n\tstruct device_node *parent;\n\tstruct device_node *child;\n\tstruct device_node *sibling;\n\tlong unsigned int _flags;\n\tvoid *data;\n};\n\nenum cpuhp_state {\n\tCPUHP_INVALID = 4294967295,\n\tCPUHP_OFFLINE = 0,\n\tCPUHP_CREATE_THREADS = 1,\n\tCPUHP_PERF_PREPARE = 2,\n\tCPUHP_PERF_X86_PREPARE = 3,\n\tCPUHP_PERF_X86_AMD_UNCORE_PREP = 4,\n\tCPUHP_PERF_POWER = 5,\n\tCPUHP_PERF_SUPERH = 6,\n\tCPUHP_X86_HPET_DEAD = 7,\n\tCPUHP_X86_APB_DEAD = 8,\n\tCPUHP_X86_MCE_DEAD = 9,\n\tCPUHP_VIRT_NET_DEAD = 10,\n\tCPUHP_SLUB_DEAD = 11,\n\tCPUHP_MM_WRITEBACK_DEAD = 12,\n\tCPUHP_MM_VMSTAT_DEAD = 13,\n\tCPUHP_SOFTIRQ_DEAD = 14,\n\tCPUHP_NET_MVNETA_DEAD = 15,\n\tCPUHP_CPUIDLE_DEAD = 16,\n\tCPUHP_ARM64_FPSIMD_DEAD = 17,\n\tCPUHP_ARM_OMAP_WAKE_DEAD = 18,\n\tCPUHP_IRQ_POLL_DEAD = 19,\n\tCPUHP_BLOCK_SOFTIRQ_DEAD = 20,\n\tCPUHP_ACPI_CPUDRV_DEAD = 21,\n\tCPUHP_S390_PFAULT_DEAD = 22,\n\tCPUHP_BLK_MQ_DEAD = 23,\n\tCPUHP_FS_BUFF_DEAD = 24,\n\tCPUHP_PRINTK_DEAD = 25,\n\tCPUHP_MM_MEMCQ_DEAD = 26,\n\tCPUHP_PERCPU_CNT_DEAD = 27,\n\tCPUHP_RADIX_DEAD = 28,\n\tCPUHP_PAGE_ALLOC_DEAD = 29,\n\tCPUHP_NET_DEV_DEAD = 30,\n\tCPUHP_PCI_XGENE_DEAD = 31,\n\tCPUHP_IOMMU_INTEL_DEAD = 32,\n\tCPUHP_LUSTRE_CFS_DEAD = 33,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DEAD = 34,\n\tCPUHP_PADATA_DEAD = 35,\n\tCPUHP_WORKQUEUE_PREP = 36,\n\tCPUHP_POWER_NUMA_PREPARE = 37,\n\tCPUHP_HRTIMERS_PREPARE = 38,\n\tCPUHP_PROFILE_PREPARE = 39,\n\tCPUHP_X2APIC_PREPARE = 40,\n\tCPUHP_SMPCFD_PREPARE = 41,\n\tCPUHP_RELAY_PREPARE = 42,\n\tCPUHP_SLAB_PREPARE = 43,\n\tCPUHP_MD_RAID5_PREPARE = 44,\n\tCPUHP_RCUTREE_PREP = 45,\n\tCPUHP_CPUIDLE_COUPLED_PREPARE = 46,\n\tCPUHP_POWERPC_PMAC_PREPARE = 47,\n\tCPUHP_POWERPC_MMU_CTX_PREPARE = 48,\n\tCPUHP_XEN_PREPARE = 49,\n\tCPUHP_XEN_EVTCHN_PREPARE = 50,\n\tCPUHP_ARM_SHMOBILE_SCU_PREPARE = 51,\n\tCPUHP_SH_SH3X_PREPARE = 52,\n\tCPUHP_NET_FLOW_PREPARE = 53,\n\tCPUHP_TOPOLOGY_PREPARE = 54,\n\tCPUHP_NET_IUCV_PREPARE = 55,\n\tCPUHP_ARM_BL_PREPARE = 56,\n\tCPUHP_TRACE_RB_PREPARE = 57,\n\tCPUHP_MM_ZS_PREPARE = 58,\n\tCPUHP_MM_ZSWP_MEM_PREPARE = 59,\n\tCPUHP_MM_ZSWP_POOL_PREPARE = 60,\n\tCPUHP_KVM_PPC_BOOK3S_PREPARE = 61,\n\tCPUHP_ZCOMP_PREPARE = 62,\n\tCPUHP_TIMERS_PREPARE = 63,\n\tCPUHP_MIPS_SOC_PREPARE = 64,\n\tCPUHP_BP_PREPARE_DYN = 65,\n\tCPUHP_BP_PREPARE_DYN_END = 85,\n\tCPUHP_BRINGUP_CPU = 86,\n\tCPUHP_AP_IDLE_DEAD = 87,\n\tCPUHP_AP_OFFLINE = 88,\n\tCPUHP_AP_SCHED_STARTING = 89,\n\tCPUHP_AP_RCUTREE_DYING = 90,\n\tCPUHP_AP_CPU_PM_STARTING = 91,\n\tCPUHP_AP_IRQ_GIC_STARTING = 92,\n\tCPUHP_AP_IRQ_HIP04_STARTING = 93,\n\tCPUHP_AP_IRQ_ARMADA_XP_STARTING = 94,\n\tCPUHP_AP_IRQ_BCM2836_STARTING = 95,\n\tCPUHP_AP_IRQ_MIPS_GIC_STARTING = 96,\n\tCPUHP_AP_IRQ_RISCV_STARTING = 97,\n\tCPUHP_AP_IRQ_SIFIVE_PLIC_STARTING = 98,\n\tCPUHP_AP_ARM_MVEBU_COHERENCY = 99,\n\tCPUHP_AP_MICROCODE_LOADER = 100,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_STARTING = 101,\n\tCPUHP_AP_PERF_X86_STARTING = 102,\n\tCPUHP_AP_PERF_X86_AMD_IBS_STARTING = 103,\n\tCPUHP_AP_PERF_X86_CQM_STARTING = 104,\n\tCPUHP_AP_PERF_X86_CSTATE_STARTING = 105,\n\tCPUHP_AP_PERF_XTENSA_STARTING = 106,\n\tCPUHP_AP_MIPS_OP_LOONGSON3_STARTING = 107,\n\tCPUHP_AP_ARM_SDEI_STARTING = 108,\n\tCPUHP_AP_ARM_VFP_STARTING = 109,\n\tCPUHP_AP_ARM64_DEBUG_MONITORS_STARTING = 110,\n\tCPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING = 111,\n\tCPUHP_AP_PERF_ARM_ACPI_STARTING = 112,\n\tCPUHP_AP_PERF_ARM_STARTING = 113,\n\tCPUHP_AP_ARM_L2X0_STARTING = 114,\n\tCPUHP_AP_EXYNOS4_MCT_TIMER_STARTING = 115,\n\tCPUHP_AP_ARM_ARCH_TIMER_STARTING = 116,\n\tCPUHP_AP_ARM_GLOBAL_TIMER_STARTING = 117,\n\tCPUHP_AP_JCORE_TIMER_STARTING = 118,\n\tCPUHP_AP_ARM_TWD_STARTING = 119,\n\tCPUHP_AP_QCOM_TIMER_STARTING = 120,\n\tCPUHP_AP_TEGRA_TIMER_STARTING = 121,\n\tCPUHP_AP_ARMADA_TIMER_STARTING = 122,\n\tCPUHP_AP_MARCO_TIMER_STARTING = 123,\n\tCPUHP_AP_MIPS_GIC_TIMER_STARTING = 124,\n\tCPUHP_AP_ARC_TIMER_STARTING = 125,\n\tCPUHP_AP_RISCV_TIMER_STARTING = 126,\n\tCPUHP_AP_CSKY_TIMER_STARTING = 127,\n\tCPUHP_AP_HYPERV_TIMER_STARTING = 128,\n\tCPUHP_AP_KVM_STARTING = 129,\n\tCPUHP_AP_KVM_ARM_VGIC_INIT_STARTING = 130,\n\tCPUHP_AP_KVM_ARM_VGIC_STARTING = 131,\n\tCPUHP_AP_KVM_ARM_TIMER_STARTING = 132,\n\tCPUHP_AP_DUMMY_TIMER_STARTING = 133,\n\tCPUHP_AP_ARM_XEN_STARTING = 134,\n\tCPUHP_AP_ARM_KVMPV_STARTING = 135,\n\tCPUHP_AP_ARM_CORESIGHT_STARTING = 136,\n\tCPUHP_AP_ARM_CORESIGHT_CTI_STARTING = 137,\n\tCPUHP_AP_ARM64_ISNDEP_STARTING = 138,\n\tCPUHP_AP_SMPCFD_DYING = 139,\n\tCPUHP_AP_X86_TBOOT_DYING = 140,\n\tCPUHP_AP_ARM_CACHE_B15_RAC_DYING = 141,\n\tCPUHP_AP_ONLINE = 142,\n\tCPUHP_TEARDOWN_CPU = 143,\n\tCPUHP_AP_ONLINE_IDLE = 144,\n\tCPUHP_AP_SMPBOOT_THREADS = 145,\n\tCPUHP_AP_X86_VDSO_VMA_ONLINE = 146,\n\tCPUHP_AP_IRQ_AFFINITY_ONLINE = 147,\n\tCPUHP_AP_BLK_MQ_ONLINE = 148,\n\tCPUHP_AP_ARM_MVEBU_SYNC_CLOCKS = 149,\n\tCPUHP_AP_X86_INTEL_EPB_ONLINE = 150,\n\tCPUHP_AP_PERF_ONLINE = 151,\n\tCPUHP_AP_PERF_X86_ONLINE = 152,\n\tCPUHP_AP_PERF_X86_UNCORE_ONLINE = 153,\n\tCPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE = 154,\n\tCPUHP_AP_PERF_X86_AMD_POWER_ONLINE = 155,\n\tCPUHP_AP_PERF_X86_RAPL_ONLINE = 156,\n\tCPUHP_AP_PERF_X86_CQM_ONLINE = 157,\n\tCPUHP_AP_PERF_X86_CSTATE_ONLINE = 158,\n\tCPUHP_AP_PERF_S390_CF_ONLINE = 159,\n\tCPUHP_AP_PERF_S390_SF_ONLINE = 160,\n\tCPUHP_AP_PERF_ARM_CCI_ONLINE = 161,\n\tCPUHP_AP_PERF_ARM_CCN_ONLINE = 162,\n\tCPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE = 163,\n\tCPUHP_AP_PERF_ARM_HISI_HHA_ONLINE = 164,\n\tCPUHP_AP_PERF_ARM_HISI_L3_ONLINE = 165,\n\tCPUHP_AP_PERF_ARM_L2X0_ONLINE = 166,\n\tCPUHP_AP_PERF_ARM_QCOM_L2_ONLINE = 167,\n\tCPUHP_AP_PERF_ARM_QCOM_L3_ONLINE = 168,\n\tCPUHP_AP_PERF_ARM_APM_XGENE_ONLINE = 169,\n\tCPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE = 170,\n\tCPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE = 171,\n\tCPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE = 172,\n\tCPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE = 173,\n\tCPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE = 174,\n\tCPUHP_AP_WATCHDOG_ONLINE = 175,\n\tCPUHP_AP_WORKQUEUE_ONLINE = 176,\n\tCPUHP_AP_RCUTREE_ONLINE = 177,\n\tCPUHP_AP_BASE_CACHEINFO_ONLINE = 178,\n\tCPUHP_AP_ONLINE_DYN = 179,\n\tCPUHP_AP_ONLINE_DYN_END = 209,\n\tCPUHP_AP_X86_HPET_ONLINE = 210,\n\tCPUHP_AP_X86_KVM_CLK_ONLINE = 211,\n\tCPUHP_AP_ACTIVE = 212,\n\tCPUHP_ONLINE = 213,\n};\n\nstruct perf_regs {\n\t__u64 abi;\n\tstruct pt_regs *regs;\n};\n\nstruct kernel_cpustat {\n\tu64 cpustat[10];\n};\n\nstruct kernel_stat {\n\tlong unsigned int irqs_sum;\n\tunsigned int softirqs[10];\n};\n\nstruct u64_stats_sync {};\n\nstruct bpf_insn {\n\t__u8 code;\n\t__u8 dst_reg: 4;\n\t__u8 src_reg: 4;\n\t__s16 off;\n\t__s32 imm;\n};\n\nstruct bpf_cgroup_storage_key {\n\t__u64 cgroup_inode_id;\n\t__u32 attach_type;\n};\n\nenum bpf_map_type {\n\tBPF_MAP_TYPE_UNSPEC = 0,\n\tBPF_MAP_TYPE_HASH = 1,\n\tBPF_MAP_TYPE_ARRAY = 2,\n\tBPF_MAP_TYPE_PROG_ARRAY = 3,\n\tBPF_MAP_TYPE_PERF_EVENT_ARRAY = 4,\n\tBPF_MAP_TYPE_PERCPU_HASH = 5,\n\tBPF_MAP_TYPE_PERCPU_ARRAY = 6,\n\tBPF_MAP_TYPE_STACK_TRACE = 7,\n\tBPF_MAP_TYPE_CGROUP_ARRAY = 8,\n\tBPF_MAP_TYPE_LRU_HASH = 9,\n\tBPF_MAP_TYPE_LRU_PERCPU_HASH = 10,\n\tBPF_MAP_TYPE_LPM_TRIE = 11,\n\tBPF_MAP_TYPE_ARRAY_OF_MAPS = 12,\n\tBPF_MAP_TYPE_HASH_OF_MAPS = 13,\n\tBPF_MAP_TYPE_DEVMAP = 14,\n\tBPF_MAP_TYPE_SOCKMAP = 15,\n\tBPF_MAP_TYPE_CPUMAP = 16,\n\tBPF_MAP_TYPE_XSKMAP = 17,\n\tBPF_MAP_TYPE_SOCKHASH = 18,\n\tBPF_MAP_TYPE_CGROUP_STORAGE = 19,\n\tBPF_MAP_TYPE_REUSEPORT_SOCKARRAY = 20,\n\tBPF_MAP_TYPE_PERCPU_CGROUP_STORAGE = 21,\n\tBPF_MAP_TYPE_QUEUE = 22,\n\tBPF_MAP_TYPE_STACK = 23,\n\tBPF_MAP_TYPE_SK_STORAGE = 24,\n\tBPF_MAP_TYPE_DEVMAP_HASH = 25,\n\tBPF_MAP_TYPE_STRUCT_OPS = 26,\n\tBPF_MAP_TYPE_RINGBUF = 27,\n};\n\nunion bpf_attr {\n\tstruct {\n\t\t__u32 map_type;\n\t\t__u32 key_size;\n\t\t__u32 value_size;\n\t\t__u32 max_entries;\n\t\t__u32 map_flags;\n\t\t__u32 inner_map_fd;\n\t\t__u32 numa_node;\n\t\tchar map_name[16];\n\t\t__u32 map_ifindex;\n\t\t__u32 btf_fd;\n\t\t__u32 btf_key_type_id;\n\t\t__u32 btf_value_type_id;\n\t\t__u32 btf_vmlinux_value_type_id;\n\t};\n\tstruct {\n\t\t__u32 map_fd;\n\t\t__u64 key;\n\t\tunion {\n\t\t\t__u64 value;\n\t\t\t__u64 next_key;\n\t\t};\n\t\t__u64 flags;\n\t};\n\tstruct {\n\t\t__u64 in_batch;\n\t\t__u64 out_batch;\n\t\t__u64 keys;\n\t\t__u64 values;\n\t\t__u32 count;\n\t\t__u32 map_fd;\n\t\t__u64 elem_flags;\n\t\t__u64 flags;\n\t} batch;\n\tstruct {\n\t\t__u32 prog_type;\n\t\t__u32 insn_cnt;\n\t\t__u64 insns;\n\t\t__u64 license;\n\t\t__u32 log_level;\n\t\t__u32 log_size;\n\t\t__u64 log_buf;\n\t\t__u32 kern_version;\n\t\t__u32 prog_flags;\n\t\tchar prog_name[16];\n\t\t__u32 prog_ifindex;\n\t\t__u32 expected_attach_type;\n\t\t__u32 prog_btf_fd;\n\t\t__u32 func_info_rec_size;\n\t\t__u64 func_info;\n\t\t__u32 func_info_cnt;\n\t\t__u32 line_info_rec_size;\n\t\t__u64 line_info;\n\t\t__u32 line_info_cnt;\n\t\t__u32 attach_btf_id;\n\t\t__u32 attach_prog_fd;\n\t};\n\tstruct {\n\t\t__u64 pathname;\n\t\t__u32 bpf_fd;\n\t\t__u32 file_flags;\n\t};\n\tstruct {\n\t\t__u32 target_fd;\n\t\t__u32 attach_bpf_fd;\n\t\t__u32 attach_type;\n\t\t__u32 attach_flags;\n\t\t__u32 replace_bpf_fd;\n\t};\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 retval;\n\t\t__u32 data_size_in;\n\t\t__u32 data_size_out;\n\t\t__u64 data_in;\n\t\t__u64 data_out;\n\t\t__u32 repeat;\n\t\t__u32 duration;\n\t\t__u32 ctx_size_in;\n\t\t__u32 ctx_size_out;\n\t\t__u64 ctx_in;\n\t\t__u64 ctx_out;\n\t} test;\n\tstruct {\n\t\tunion {\n\t\t\t__u32 start_id;\n\t\t\t__u32 prog_id;\n\t\t\t__u32 map_id;\n\t\t\t__u32 btf_id;\n\t\t\t__u32 link_id;\n\t\t};\n\t\t__u32 next_id;\n\t\t__u32 open_flags;\n\t};\n\tstruct {\n\t\t__u32 bpf_fd;\n\t\t__u32 info_len;\n\t\t__u64 info;\n\t} info;\n\tstruct {\n\t\t__u32 target_fd;\n\t\t__u32 attach_type;\n\t\t__u32 query_flags;\n\t\t__u32 attach_flags;\n\t\t__u64 prog_ids;\n\t\t__u32 prog_cnt;\n\t} query;\n\tstruct {\n\t\t__u64 name;\n\t\t__u32 prog_fd;\n\t} raw_tracepoint;\n\tstruct {\n\t\t__u64 btf;\n\t\t__u64 btf_log_buf;\n\t\t__u32 btf_size;\n\t\t__u32 btf_log_size;\n\t\t__u32 btf_log_level;\n\t};\n\tstruct {\n\t\t__u32 pid;\n\t\t__u32 fd;\n\t\t__u32 flags;\n\t\t__u32 buf_len;\n\t\t__u64 buf;\n\t\t__u32 prog_id;\n\t\t__u32 fd_type;\n\t\t__u64 probe_offset;\n\t\t__u64 probe_addr;\n\t} task_fd_query;\n\tstruct {\n\t\t__u32 prog_fd;\n\t\t__u32 target_fd;\n\t\t__u32 attach_type;\n\t\t__u32 flags;\n\t} link_create;\n\tstruct {\n\t\t__u32 link_fd;\n\t\t__u32 new_prog_fd;\n\t\t__u32 flags;\n\t\t__u32 old_prog_fd;\n\t} link_update;\n\tstruct {\n\t\t__u32 type;\n\t} enable_stats;\n\tstruct {\n\t\t__u32 link_fd;\n\t\t__u32 flags;\n\t} iter_create;\n};\n\nenum bpf_func_id {\n\tBPF_FUNC_unspec = 0,\n\tBPF_FUNC_map_lookup_elem = 1,\n\tBPF_FUNC_map_update_elem = 2,\n\tBPF_FUNC_map_delete_elem = 3,\n\tBPF_FUNC_probe_read = 4,\n\tBPF_FUNC_ktime_get_ns = 5,\n\tBPF_FUNC_trace_printk = 6,\n\tBPF_FUNC_get_prandom_u32 = 7,\n\tBPF_FUNC_get_smp_processor_id = 8,\n\tBPF_FUNC_skb_store_bytes = 9,\n\tBPF_FUNC_l3_csum_replace = 10,\n\tBPF_FUNC_l4_csum_replace = 11,\n\tBPF_FUNC_tail_call = 12,\n\tBPF_FUNC_clone_redirect = 13,\n\tBPF_FUNC_get_current_pid_tgid = 14,\n\tBPF_FUNC_get_current_uid_gid = 15,\n\tBPF_FUNC_get_current_comm = 16,\n\tBPF_FUNC_get_cgroup_classid = 17,\n\tBPF_FUNC_skb_vlan_push = 18,\n\tBPF_FUNC_skb_vlan_pop = 19,\n\tBPF_FUNC_skb_get_tunnel_key = 20,\n\tBPF_FUNC_skb_set_tunnel_key = 21,\n\tBPF_FUNC_perf_event_read = 22,\n\tBPF_FUNC_redirect = 23,\n\tBPF_FUNC_get_route_realm = 24,\n\tBPF_FUNC_perf_event_output = 25,\n\tBPF_FUNC_skb_load_bytes = 26,\n\tBPF_FUNC_get_stackid = 27,\n\tBPF_FUNC_csum_diff = 28,\n\tBPF_FUNC_skb_get_tunnel_opt = 29,\n\tBPF_FUNC_skb_set_tunnel_opt = 30,\n\tBPF_FUNC_skb_change_proto = 31,\n\tBPF_FUNC_skb_change_type = 32,\n\tBPF_FUNC_skb_under_cgroup = 33,\n\tBPF_FUNC_get_hash_recalc = 34,\n\tBPF_FUNC_get_current_task = 35,\n\tBPF_FUNC_probe_write_user = 36,\n\tBPF_FUNC_current_task_under_cgroup = 37,\n\tBPF_FUNC_skb_change_tail = 38,\n\tBPF_FUNC_skb_pull_data = 39,\n\tBPF_FUNC_csum_update = 40,\n\tBPF_FUNC_set_hash_invalid = 41,\n\tBPF_FUNC_get_numa_node_id = 42,\n\tBPF_FUNC_skb_change_head = 43,\n\tBPF_FUNC_xdp_adjust_head = 44,\n\tBPF_FUNC_probe_read_str = 45,\n\tBPF_FUNC_get_socket_cookie = 46,\n\tBPF_FUNC_get_socket_uid = 47,\n\tBPF_FUNC_set_hash = 48,\n\tBPF_FUNC_setsockopt = 49,\n\tBPF_FUNC_skb_adjust_room = 50,\n\tBPF_FUNC_redirect_map = 51,\n\tBPF_FUNC_sk_redirect_map = 52,\n\tBPF_FUNC_sock_map_update = 53,\n\tBPF_FUNC_xdp_adjust_meta = 54,\n\tBPF_FUNC_perf_event_read_value = 55,\n\tBPF_FUNC_perf_prog_read_value = 56,\n\tBPF_FUNC_getsockopt = 57,\n\tBPF_FUNC_override_return = 58,\n\tBPF_FUNC_sock_ops_cb_flags_set = 59,\n\tBPF_FUNC_msg_redirect_map = 60,\n\tBPF_FUNC_msg_apply_bytes = 61,\n\tBPF_FUNC_msg_cork_bytes = 62,\n\tBPF_FUNC_msg_pull_data = 63,\n\tBPF_FUNC_bind = 64,\n\tBPF_FUNC_xdp_adjust_tail = 65,\n\tBPF_FUNC_skb_get_xfrm_state = 66,\n\tBPF_FUNC_get_stack = 67,\n\tBPF_FUNC_skb_load_bytes_relative = 68,\n\tBPF_FUNC_fib_lookup = 69,\n\tBPF_FUNC_sock_hash_update = 70,\n\tBPF_FUNC_msg_redirect_hash = 71,\n\tBPF_FUNC_sk_redirect_hash = 72,\n\tBPF_FUNC_lwt_push_encap = 73,\n\tBPF_FUNC_lwt_seg6_store_bytes = 74,\n\tBPF_FUNC_lwt_seg6_adjust_srh = 75,\n\tBPF_FUNC_lwt_seg6_action = 76,\n\tBPF_FUNC_rc_repeat = 77,\n\tBPF_FUNC_rc_keydown = 78,\n\tBPF_FUNC_skb_cgroup_id = 79,\n\tBPF_FUNC_get_current_cgroup_id = 80,\n\tBPF_FUNC_get_local_storage = 81,\n\tBPF_FUNC_sk_select_reuseport = 82,\n\tBPF_FUNC_skb_ancestor_cgroup_id = 83,\n\tBPF_FUNC_sk_lookup_tcp = 84,\n\tBPF_FUNC_sk_lookup_udp = 85,\n\tBPF_FUNC_sk_release = 86,\n\tBPF_FUNC_map_push_elem = 87,\n\tBPF_FUNC_map_pop_elem = 88,\n\tBPF_FUNC_map_peek_elem = 89,\n\tBPF_FUNC_msg_push_data = 90,\n\tBPF_FUNC_msg_pop_data = 91,\n\tBPF_FUNC_rc_pointer_rel = 92,\n\tBPF_FUNC_spin_lock = 93,\n\tBPF_FUNC_spin_unlock = 94,\n\tBPF_FUNC_sk_fullsock = 95,\n\tBPF_FUNC_tcp_sock = 96,\n\tBPF_FUNC_skb_ecn_set_ce = 97,\n\tBPF_FUNC_get_listener_sock = 98,\n\tBPF_FUNC_skc_lookup_tcp = 99,\n\tBPF_FUNC_tcp_check_syncookie = 100,\n\tBPF_FUNC_sysctl_get_name = 101,\n\tBPF_FUNC_sysctl_get_current_value = 102,\n\tBPF_FUNC_sysctl_get_new_value = 103,\n\tBPF_FUNC_sysctl_set_new_value = 104,\n\tBPF_FUNC_strtol = 105,\n\tBPF_FUNC_strtoul = 106,\n\tBPF_FUNC_sk_storage_get = 107,\n\tBPF_FUNC_sk_storage_delete = 108,\n\tBPF_FUNC_send_signal = 109,\n\tBPF_FUNC_tcp_gen_syncookie = 110,\n\tBPF_FUNC_skb_output = 111,\n\tBPF_FUNC_probe_read_user = 112,\n\tBPF_FUNC_probe_read_kernel = 113,\n\tBPF_FUNC_probe_read_user_str = 114,\n\tBPF_FUNC_probe_read_kernel_str = 115,\n\tBPF_FUNC_tcp_send_ack = 116,\n\tBPF_FUNC_send_signal_thread = 117,\n\tBPF_FUNC_jiffies64 = 118,\n\tBPF_FUNC_read_branch_records = 119,\n\tBPF_FUNC_get_ns_current_pid_tgid = 120,\n\tBPF_FUNC_xdp_output = 121,\n\tBPF_FUNC_get_netns_cookie = 122,\n\tBPF_FUNC_get_current_ancestor_cgroup_id = 123,\n\tBPF_FUNC_sk_assign = 124,\n\tBPF_FUNC_ktime_get_boot_ns = 125,\n\tBPF_FUNC_seq_printf = 126,\n\tBPF_FUNC_seq_write = 127,\n\tBPF_FUNC_sk_cgroup_id = 128,\n\tBPF_FUNC_sk_ancestor_cgroup_id = 129,\n\tBPF_FUNC_ringbuf_output = 130,\n\tBPF_FUNC_ringbuf_reserve = 131,\n\tBPF_FUNC_ringbuf_submit = 132,\n\tBPF_FUNC_ringbuf_discard = 133,\n\tBPF_FUNC_ringbuf_query = 134,\n\tBPF_FUNC_csum_level = 135,\n\t__BPF_FUNC_MAX_ID = 136,\n};\n\nstruct bpf_func_info {\n\t__u32 insn_off;\n\t__u32 type_id;\n};\n\nstruct bpf_line_info {\n\t__u32 insn_off;\n\t__u32 file_name_off;\n\t__u32 line_off;\n\t__u32 line_col;\n};\n\nstruct bpf_map;\n\nstruct btf;\n\nstruct btf_type;\n\nstruct bpf_prog_aux;\n\nstruct bpf_map_ops {\n\tint (*map_alloc_check)(union bpf_attr *);\n\tstruct bpf_map * (*map_alloc)(union bpf_attr *);\n\tvoid (*map_release)(struct bpf_map *, struct file *);\n\tvoid (*map_free)(struct bpf_map *);\n\tint (*map_get_next_key)(struct bpf_map *, void *, void *);\n\tvoid (*map_release_uref)(struct bpf_map *);\n\tvoid * (*map_lookup_elem_sys_only)(struct bpf_map *, void *);\n\tint (*map_lookup_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_lookup_and_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_update_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tint (*map_delete_batch)(struct bpf_map *, const union bpf_attr *, union bpf_attr *);\n\tvoid * (*map_lookup_elem)(struct bpf_map *, void *);\n\tint (*map_update_elem)(struct bpf_map *, void *, void *, u64);\n\tint (*map_delete_elem)(struct bpf_map *, void *);\n\tint (*map_push_elem)(struct bpf_map *, void *, u64);\n\tint (*map_pop_elem)(struct bpf_map *, void *);\n\tint (*map_peek_elem)(struct bpf_map *, void *);\n\tvoid * (*map_fd_get_ptr)(struct bpf_map *, struct file *, int);\n\tvoid (*map_fd_put_ptr)(void *);\n\tu32 (*map_gen_lookup)(struct bpf_map *, struct bpf_insn *);\n\tu32 (*map_fd_sys_lookup_elem)(void *);\n\tvoid (*map_seq_show_elem)(struct bpf_map *, void *, struct seq_file *);\n\tint (*map_check_btf)(const struct bpf_map *, const struct btf *, const struct btf_type *, const struct btf_type *);\n\tint (*map_poke_track)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_untrack)(struct bpf_map *, struct bpf_prog_aux *);\n\tvoid (*map_poke_run)(struct bpf_map *, u32, struct bpf_prog *, struct bpf_prog *);\n\tint (*map_direct_value_addr)(const struct bpf_map *, u64 *, u32);\n\tint (*map_direct_value_meta)(const struct bpf_map *, u64, u32 *);\n\tint (*map_mmap)(struct bpf_map *, struct vm_area_struct *);\n\t__poll_t (*map_poll)(struct bpf_map *, struct file *, struct poll_table_struct *);\n};\n\nstruct bpf_map_memory {\n\tu32 pages;\n\tstruct user_struct *user;\n};\n\nstruct bpf_map {\n\tconst struct bpf_map_ops *ops;\n\tstruct bpf_map *inner_map_meta;\n\tvoid *security;\n\tenum bpf_map_type map_type;\n\tu32 key_size;\n\tu32 value_size;\n\tu32 max_entries;\n\tu32 map_flags;\n\tint spin_lock_off;\n\tu32 id;\n\tint numa_node;\n\tu32 btf_key_type_id;\n\tu32 btf_value_type_id;\n\tstruct btf *btf;\n\tstruct bpf_map_memory memory;\n\tchar name[16];\n\tu32 btf_vmlinux_value_type_id;\n\tbool bypass_spec_v1;\n\tbool frozen;\n\tlong: 16;\n\tlong: 64;\n\tlong: 64;\n\tatomic64_t refcnt;\n\tatomic64_t usercnt;\n\tstruct work_struct work;\n\tstruct mutex freeze_mutex;\n\tu64 writecnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct btf_header {\n\t__u16 magic;\n\t__u8 version;\n\t__u8 flags;\n\t__u32 hdr_len;\n\t__u32 type_off;\n\t__u32 type_len;\n\t__u32 str_off;\n\t__u32 str_len;\n};\n\nstruct btf {\n\tvoid *data;\n\tstruct btf_type **types;\n\tu32 *resolved_ids;\n\tu32 *resolved_sizes;\n\tconst char *strings;\n\tvoid *nohdr_data;\n\tstruct btf_header hdr;\n\tu32 nr_types;\n\tu32 types_size;\n\tu32 data_size;\n\trefcount_t refcnt;\n\tu32 id;\n\tstruct callback_head rcu;\n};\n\nstruct btf_type {\n\t__u32 name_off;\n\t__u32 info;\n\tunion {\n\t\t__u32 size;\n\t\t__u32 type;\n\t};\n};\n\nenum bpf_tramp_prog_type {\n\tBPF_TRAMP_FENTRY = 0,\n\tBPF_TRAMP_FEXIT = 1,\n\tBPF_TRAMP_MODIFY_RETURN = 2,\n\tBPF_TRAMP_MAX = 3,\n\tBPF_TRAMP_REPLACE = 4,\n};\n\nstruct bpf_ksym {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tchar name[128];\n\tstruct list_head lnode;\n\tstruct latch_tree_node tnode;\n\tbool prog;\n};\n\nstruct bpf_ctx_arg_aux;\n\nstruct bpf_trampoline;\n\nstruct bpf_jit_poke_descriptor;\n\nstruct bpf_prog_ops;\n\nstruct bpf_prog_offload;\n\nstruct bpf_func_info_aux;\n\nstruct bpf_prog_stats;\n\nstruct bpf_prog_aux {\n\tatomic64_t refcnt;\n\tu32 used_map_cnt;\n\tu32 max_ctx_offset;\n\tu32 max_pkt_offset;\n\tu32 max_tp_access;\n\tu32 stack_depth;\n\tu32 id;\n\tu32 func_cnt;\n\tu32 func_idx;\n\tu32 attach_btf_id;\n\tu32 ctx_arg_info_size;\n\tconst struct bpf_ctx_arg_aux *ctx_arg_info;\n\tstruct bpf_prog *linked_prog;\n\tbool verifier_zext;\n\tbool offload_requested;\n\tbool attach_btf_trace;\n\tbool func_proto_unreliable;\n\tenum bpf_tramp_prog_type trampoline_prog_type;\n\tstruct bpf_trampoline *trampoline;\n\tstruct hlist_node tramp_hlist;\n\tconst struct btf_type *attach_func_proto;\n\tconst char *attach_func_name;\n\tstruct bpf_prog **func;\n\tvoid *jit_data;\n\tstruct bpf_jit_poke_descriptor *poke_tab;\n\tu32 size_poke_tab;\n\tstruct bpf_ksym ksym;\n\tconst struct bpf_prog_ops *ops;\n\tstruct bpf_map **used_maps;\n\tstruct bpf_prog *prog;\n\tstruct user_struct *user;\n\tu64 load_time;\n\tstruct bpf_map *cgroup_storage[2];\n\tchar name[16];\n\tvoid *security;\n\tstruct bpf_prog_offload *offload;\n\tstruct btf *btf;\n\tstruct bpf_func_info *func_info;\n\tstruct bpf_func_info_aux *func_info_aux;\n\tstruct bpf_line_info *linfo;\n\tvoid **jited_linfo;\n\tu32 func_info_cnt;\n\tu32 nr_linfo;\n\tu32 linfo_idx;\n\tu32 num_exentries;\n\tstruct exception_table_entry *extable;\n\tstruct bpf_prog_stats *stats;\n\tunion {\n\t\tstruct work_struct work;\n\t\tstruct callback_head rcu;\n\t};\n};\n\nenum bpf_prog_type {\n\tBPF_PROG_TYPE_UNSPEC = 0,\n\tBPF_PROG_TYPE_SOCKET_FILTER = 1,\n\tBPF_PROG_TYPE_KPROBE = 2,\n\tBPF_PROG_TYPE_SCHED_CLS = 3,\n\tBPF_PROG_TYPE_SCHED_ACT = 4,\n\tBPF_PROG_TYPE_TRACEPOINT = 5,\n\tBPF_PROG_TYPE_XDP = 6,\n\tBPF_PROG_TYPE_PERF_EVENT = 7,\n\tBPF_PROG_TYPE_CGROUP_SKB = 8,\n\tBPF_PROG_TYPE_CGROUP_SOCK = 9,\n\tBPF_PROG_TYPE_LWT_IN = 10,\n\tBPF_PROG_TYPE_LWT_OUT = 11,\n\tBPF_PROG_TYPE_LWT_XMIT = 12,\n\tBPF_PROG_TYPE_SOCK_OPS = 13,\n\tBPF_PROG_TYPE_SK_SKB = 14,\n\tBPF_PROG_TYPE_CGROUP_DEVICE = 15,\n\tBPF_PROG_TYPE_SK_MSG = 16,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT = 17,\n\tBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 18,\n\tBPF_PROG_TYPE_LWT_SEG6LOCAL = 19,\n\tBPF_PROG_TYPE_LIRC_MODE2 = 20,\n\tBPF_PROG_TYPE_SK_REUSEPORT = 21,\n\tBPF_PROG_TYPE_FLOW_DISSECTOR = 22,\n\tBPF_PROG_TYPE_CGROUP_SYSCTL = 23,\n\tBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 24,\n\tBPF_PROG_TYPE_CGROUP_SOCKOPT = 25,\n\tBPF_PROG_TYPE_TRACING = 26,\n\tBPF_PROG_TYPE_STRUCT_OPS = 27,\n\tBPF_PROG_TYPE_EXT = 28,\n\tBPF_PROG_TYPE_LSM = 29,\n};\n\nenum bpf_attach_type {\n\tBPF_CGROUP_INET_INGRESS = 0,\n\tBPF_CGROUP_INET_EGRESS = 1,\n\tBPF_CGROUP_INET_SOCK_CREATE = 2,\n\tBPF_CGROUP_SOCK_OPS = 3,\n\tBPF_SK_SKB_STREAM_PARSER = 4,\n\tBPF_SK_SKB_STREAM_VERDICT = 5,\n\tBPF_CGROUP_DEVICE = 6,\n\tBPF_SK_MSG_VERDICT = 7,\n\tBPF_CGROUP_INET4_BIND = 8,\n\tBPF_CGROUP_INET6_BIND = 9,\n\tBPF_CGROUP_INET4_CONNECT = 10,\n\tBPF_CGROUP_INET6_CONNECT = 11,\n\tBPF_CGROUP_INET4_POST_BIND = 12,\n\tBPF_CGROUP_INET6_POST_BIND = 13,\n\tBPF_CGROUP_UDP4_SENDMSG = 14,\n\tBPF_CGROUP_UDP6_SENDMSG = 15,\n\tBPF_LIRC_MODE2 = 16,\n\tBPF_FLOW_DISSECTOR = 17,\n\tBPF_CGROUP_SYSCTL = 18,\n\tBPF_CGROUP_UDP4_RECVMSG = 19,\n\tBPF_CGROUP_UDP6_RECVMSG = 20,\n\tBPF_CGROUP_GETSOCKOPT = 21,\n\tBPF_CGROUP_SETSOCKOPT = 22,\n\tBPF_TRACE_RAW_TP = 23,\n\tBPF_TRACE_FENTRY = 24,\n\tBPF_TRACE_FEXIT = 25,\n\tBPF_MODIFY_RETURN = 26,\n\tBPF_LSM_MAC = 27,\n\tBPF_TRACE_ITER = 28,\n\tBPF_CGROUP_INET4_GETPEERNAME = 29,\n\tBPF_CGROUP_INET6_GETPEERNAME = 30,\n\tBPF_CGROUP_INET4_GETSOCKNAME = 31,\n\tBPF_CGROUP_INET6_GETSOCKNAME = 32,\n\tBPF_XDP_DEVMAP = 33,\n\t__MAX_BPF_ATTACH_TYPE = 34,\n};\n\nstruct sock_filter {\n\t__u16 code;\n\t__u8 jt;\n\t__u8 jf;\n\t__u32 k;\n};\n\nstruct sock_fprog_kern;\n\nstruct bpf_prog {\n\tu16 pages;\n\tu16 jited: 1;\n\tu16 jit_requested: 1;\n\tu16 gpl_compatible: 1;\n\tu16 cb_access: 1;\n\tu16 dst_needed: 1;\n\tu16 blinded: 1;\n\tu16 is_func: 1;\n\tu16 kprobe_override: 1;\n\tu16 has_callchain_buf: 1;\n\tu16 enforce_expected_attach_type: 1;\n\tenum bpf_prog_type type;\n\tenum bpf_attach_type expected_attach_type;\n\tu32 len;\n\tu32 jited_len;\n\tu8 tag[8];\n\tstruct bpf_prog_aux *aux;\n\tstruct sock_fprog_kern *orig_prog;\n\tunsigned int (*bpf_func)(const void *, const struct bpf_insn *);\n\tstruct sock_filter insns[0];\n\tstruct bpf_insn insnsi[0];\n};\n\nenum bpf_arg_type {\n\tARG_DONTCARE = 0,\n\tARG_CONST_MAP_PTR = 1,\n\tARG_PTR_TO_MAP_KEY = 2,\n\tARG_PTR_TO_MAP_VALUE = 3,\n\tARG_PTR_TO_UNINIT_MAP_VALUE = 4,\n\tARG_PTR_TO_MAP_VALUE_OR_NULL = 5,\n\tARG_PTR_TO_MEM = 6,\n\tARG_PTR_TO_MEM_OR_NULL = 7,\n\tARG_PTR_TO_UNINIT_MEM = 8,\n\tARG_CONST_SIZE = 9,\n\tARG_CONST_SIZE_OR_ZERO = 10,\n\tARG_PTR_TO_CTX = 11,\n\tARG_PTR_TO_CTX_OR_NULL = 12,\n\tARG_ANYTHING = 13,\n\tARG_PTR_TO_SPIN_LOCK = 14,\n\tARG_PTR_TO_SOCK_COMMON = 15,\n\tARG_PTR_TO_INT = 16,\n\tARG_PTR_TO_LONG = 17,\n\tARG_PTR_TO_SOCKET = 18,\n\tARG_PTR_TO_BTF_ID = 19,\n\tARG_PTR_TO_ALLOC_MEM = 20,\n\tARG_PTR_TO_ALLOC_MEM_OR_NULL = 21,\n\tARG_CONST_ALLOC_SIZE_OR_ZERO = 22,\n};\n\nenum bpf_return_type {\n\tRET_INTEGER = 0,\n\tRET_VOID = 1,\n\tRET_PTR_TO_MAP_VALUE = 2,\n\tRET_PTR_TO_MAP_VALUE_OR_NULL = 3,\n\tRET_PTR_TO_SOCKET_OR_NULL = 4,\n\tRET_PTR_TO_TCP_SOCK_OR_NULL = 5,\n\tRET_PTR_TO_SOCK_COMMON_OR_NULL = 6,\n\tRET_PTR_TO_ALLOC_MEM_OR_NULL = 7,\n};\n\nstruct bpf_func_proto {\n\tu64 (*func)(u64, u64, u64, u64, u64);\n\tbool gpl_only;\n\tbool pkt_access;\n\tenum bpf_return_type ret_type;\n\tunion {\n\t\tstruct {\n\t\t\tenum bpf_arg_type arg1_type;\n\t\t\tenum bpf_arg_type arg2_type;\n\t\t\tenum bpf_arg_type arg3_type;\n\t\t\tenum bpf_arg_type arg4_type;\n\t\t\tenum bpf_arg_type arg5_type;\n\t\t};\n\t\tenum bpf_arg_type arg_type[5];\n\t};\n\tint *btf_id;\n};\n\nenum bpf_access_type {\n\tBPF_READ = 1,\n\tBPF_WRITE = 2,\n};\n\nenum bpf_reg_type {\n\tNOT_INIT = 0,\n\tSCALAR_VALUE = 1,\n\tPTR_TO_CTX = 2,\n\tCONST_PTR_TO_MAP = 3,\n\tPTR_TO_MAP_VALUE = 4,\n\tPTR_TO_MAP_VALUE_OR_NULL = 5,\n\tPTR_TO_STACK = 6,\n\tPTR_TO_PACKET_META = 7,\n\tPTR_TO_PACKET = 8,\n\tPTR_TO_PACKET_END = 9,\n\tPTR_TO_FLOW_KEYS = 10,\n\tPTR_TO_SOCKET = 11,\n\tPTR_TO_SOCKET_OR_NULL = 12,\n\tPTR_TO_SOCK_COMMON = 13,\n\tPTR_TO_SOCK_COMMON_OR_NULL = 14,\n\tPTR_TO_TCP_SOCK = 15,\n\tPTR_TO_TCP_SOCK_OR_NULL = 16,\n\tPTR_TO_TP_BUFFER = 17,\n\tPTR_TO_XDP_SOCK = 18,\n\tPTR_TO_BTF_ID = 19,\n\tPTR_TO_BTF_ID_OR_NULL = 20,\n\tPTR_TO_MEM = 21,\n\tPTR_TO_MEM_OR_NULL = 22,\n};\n\nstruct bpf_verifier_log;\n\nstruct bpf_insn_access_aux {\n\tenum bpf_reg_type reg_type;\n\tunion {\n\t\tint ctx_field_size;\n\t\tu32 btf_id;\n\t};\n\tstruct bpf_verifier_log *log;\n};\n\nstruct bpf_prog_ops {\n\tint (*test_run)(struct bpf_prog *, const union bpf_attr *, union bpf_attr *);\n};\n\nstruct bpf_verifier_ops {\n\tconst struct bpf_func_proto * (*get_func_proto)(enum bpf_func_id, const struct bpf_prog *);\n\tbool (*is_valid_access)(int, int, enum bpf_access_type, const struct bpf_prog *, struct bpf_insn_access_aux *);\n\tint (*gen_prologue)(struct bpf_insn *, bool, const struct bpf_prog *);\n\tint (*gen_ld_abs)(const struct bpf_insn *, struct bpf_insn *);\n\tu32 (*convert_ctx_access)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\tint (*btf_struct_access)(struct bpf_verifier_log *, const struct btf_type *, int, int, enum bpf_access_type, u32 *);\n};\n\nstruct net_device;\n\nstruct bpf_offload_dev;\n\nstruct bpf_prog_offload {\n\tstruct bpf_prog *prog;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n\tbool dev_state;\n\tbool opt_failed;\n\tvoid *jited_image;\n\tu32 jited_len;\n};\n\nstruct bpf_prog_stats {\n\tu64 cnt;\n\tu64 nsecs;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct btf_func_model {\n\tu8 ret_size;\n\tu8 nr_args;\n\tu8 arg_size[12];\n};\n\nstruct bpf_trampoline {\n\tstruct hlist_node hlist;\n\tstruct mutex mutex;\n\trefcount_t refcnt;\n\tu64 key;\n\tstruct {\n\t\tstruct btf_func_model model;\n\t\tvoid *addr;\n\t\tbool ftrace_managed;\n\t} func;\n\tstruct bpf_prog *extension_prog;\n\tstruct hlist_head progs_hlist[3];\n\tint progs_cnt[3];\n\tvoid *image;\n\tu64 selector;\n\tstruct bpf_ksym ksym;\n};\n\nstruct bpf_func_info_aux {\n\tu16 linkage;\n\tbool unreliable;\n};\n\nstruct bpf_jit_poke_descriptor {\n\tvoid *ip;\n\tunion {\n\t\tstruct {\n\t\t\tstruct bpf_map *map;\n\t\t\tu32 key;\n\t\t} tail_call;\n\t};\n\tbool ip_stable;\n\tu8 adj_off;\n\tu16 reason;\n};\n\nstruct bpf_ctx_arg_aux {\n\tu32 offset;\n\tenum bpf_reg_type reg_type;\n};\n\nstruct bpf_cgroup_storage;\n\nstruct bpf_prog_array_item {\n\tstruct bpf_prog *prog;\n\tstruct bpf_cgroup_storage *cgroup_storage[2];\n};\n\nstruct bpf_storage_buffer;\n\nstruct bpf_cgroup_storage_map;\n\nstruct bpf_cgroup_storage {\n\tunion {\n\t\tstruct bpf_storage_buffer *buf;\n\t\tvoid *percpu_buf;\n\t};\n\tstruct bpf_cgroup_storage_map *map;\n\tstruct bpf_cgroup_storage_key key;\n\tstruct list_head list;\n\tstruct rb_node node;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_prog_array {\n\tstruct callback_head rcu;\n\tstruct bpf_prog_array_item items[0];\n};\n\nstruct bpf_storage_buffer {\n\tstruct callback_head rcu;\n\tchar data[0];\n};\n\nstruct cgroup_taskset;\n\nstruct cftype;\n\nstruct cgroup_subsys {\n\tstruct cgroup_subsys_state * (*css_alloc)(struct cgroup_subsys_state *);\n\tint (*css_online)(struct cgroup_subsys_state *);\n\tvoid (*css_offline)(struct cgroup_subsys_state *);\n\tvoid (*css_released)(struct cgroup_subsys_state *);\n\tvoid (*css_free)(struct cgroup_subsys_state *);\n\tvoid (*css_reset)(struct cgroup_subsys_state *);\n\tvoid (*css_rstat_flush)(struct cgroup_subsys_state *, int);\n\tint (*css_extra_stat_show)(struct seq_file *, struct cgroup_subsys_state *);\n\tint (*can_attach)(struct cgroup_taskset *);\n\tvoid (*cancel_attach)(struct cgroup_taskset *);\n\tvoid (*attach)(struct cgroup_taskset *);\n\tvoid (*post_attach)();\n\tint (*can_fork)(struct task_struct *, struct css_set *);\n\tvoid (*cancel_fork)(struct task_struct *, struct css_set *);\n\tvoid (*fork)(struct task_struct *);\n\tvoid (*exit)(struct task_struct *);\n\tvoid (*release)(struct task_struct *);\n\tvoid (*bind)(struct cgroup_subsys_state *);\n\tbool early_init: 1;\n\tbool implicit_on_dfl: 1;\n\tbool threaded: 1;\n\tbool broken_hierarchy: 1;\n\tbool warned_broken_hierarchy: 1;\n\tint id;\n\tconst char *name;\n\tconst char *legacy_name;\n\tstruct cgroup_root *root;\n\tstruct idr css_idr;\n\tstruct list_head cfts;\n\tstruct cftype *dfl_cftypes;\n\tstruct cftype *legacy_cftypes;\n\tunsigned int depends_on;\n};\n\nstruct cgroup_rstat_cpu {\n\tstruct u64_stats_sync bsync;\n\tstruct cgroup_base_stat bstat;\n\tstruct cgroup_base_stat last_bstat;\n\tstruct cgroup *updated_children;\n\tstruct cgroup *updated_next;\n};\n\nstruct cgroup_root {\n\tstruct kernfs_root *kf_root;\n\tunsigned int subsys_mask;\n\tint hierarchy_id;\n\tstruct cgroup cgrp;\n\tu64 cgrp_ancestor_id_storage;\n\tatomic_t nr_cgrps;\n\tstruct list_head root_list;\n\tunsigned int flags;\n\tchar release_agent_path[4096];\n\tchar name[64];\n};\n\nstruct cftype {\n\tchar name[64];\n\tlong unsigned int private;\n\tsize_t max_write_len;\n\tunsigned int flags;\n\tunsigned int file_offset;\n\tstruct cgroup_subsys *ss;\n\tstruct list_head node;\n\tstruct kernfs_ops *kf_ops;\n\tint (*open)(struct kernfs_open_file *);\n\tvoid (*release)(struct kernfs_open_file *);\n\tu64 (*read_u64)(struct cgroup_subsys_state *, struct cftype *);\n\ts64 (*read_s64)(struct cgroup_subsys_state *, struct cftype *);\n\tint (*seq_show)(struct seq_file *, void *);\n\tvoid * (*seq_start)(struct seq_file *, loff_t *);\n\tvoid * (*seq_next)(struct seq_file *, void *, loff_t *);\n\tvoid (*seq_stop)(struct seq_file *, void *);\n\tint (*write_u64)(struct cgroup_subsys_state *, struct cftype *, u64);\n\tint (*write_s64)(struct cgroup_subsys_state *, struct cftype *, s64);\n\tssize_t (*write)(struct kernfs_open_file *, char *, size_t, loff_t);\n\t__poll_t (*poll)(struct kernfs_open_file *, struct poll_table_struct *);\n};\n\nenum kmalloc_cache_type {\n\tKMALLOC_NORMAL = 0,\n\tKMALLOC_RECLAIM = 1,\n\tKMALLOC_DMA = 2,\n\tNR_KMALLOC_TYPES = 3,\n};\n\nstruct perf_callchain_entry {\n\t__u64 nr;\n\t__u64 ip[0];\n};\n\ntypedef long unsigned int (*perf_copy_f)(void *, const void *, long unsigned int, long unsigned int);\n\nstruct perf_raw_frag {\n\tunion {\n\t\tstruct perf_raw_frag *next;\n\t\tlong unsigned int pad;\n\t};\n\tperf_copy_f copy;\n\tvoid *data;\n\tu32 size;\n} __attribute__((packed));\n\nstruct perf_raw_record {\n\tstruct perf_raw_frag frag;\n\tu32 size;\n};\n\nstruct perf_branch_stack {\n\t__u64 nr;\n\t__u64 hw_idx;\n\tstruct perf_branch_entry entries[0];\n};\n\nstruct perf_cpu_context {\n\tstruct perf_event_context ctx;\n\tstruct perf_event_context *task_ctx;\n\tint active_oncpu;\n\tint exclusive;\n\traw_spinlock_t hrtimer_lock;\n\tstruct hrtimer hrtimer;\n\tktime_t hrtimer_interval;\n\tunsigned int hrtimer_active;\n\tstruct list_head sched_cb_entry;\n\tint sched_cb_usage;\n\tint online;\n\tint heap_size;\n\tstruct perf_event **heap;\n\tstruct perf_event *heap_default[2];\n};\n\nstruct perf_output_handle {\n\tstruct perf_event *event;\n\tstruct perf_buffer *rb;\n\tlong unsigned int wakeup;\n\tlong unsigned int size;\n\tu64 aux_flags;\n\tunion {\n\t\tvoid *addr;\n\t\tlong unsigned int head;\n\t};\n\tint page;\n};\n\nstruct perf_addr_filter_range {\n\tlong unsigned int start;\n\tlong unsigned int size;\n};\n\nstruct perf_sample_data {\n\tu64 addr;\n\tstruct perf_raw_record *raw;\n\tstruct perf_branch_stack *br_stack;\n\tu64 period;\n\tu64 weight;\n\tu64 txn;\n\tunion perf_mem_data_src data_src;\n\tu64 type;\n\tu64 ip;\n\tstruct {\n\t\tu32 pid;\n\t\tu32 tid;\n\t} tid_entry;\n\tu64 time;\n\tu64 id;\n\tu64 stream_id;\n\tstruct {\n\t\tu32 cpu;\n\t\tu32 reserved;\n\t} cpu_entry;\n\tstruct perf_callchain_entry *callchain;\n\tu64 aux_size;\n\tstruct perf_regs regs_user;\n\tstruct pt_regs regs_user_copy;\n\tstruct perf_regs regs_intr;\n\tu64 stack_user_size;\n\tu64 phys_addr;\n\tu64 cgroup;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct trace_entry {\n\tshort unsigned int type;\n\tunsigned char flags;\n\tunsigned char preempt_count;\n\tint pid;\n};\n\nstruct trace_array;\n\nstruct tracer;\n\nstruct array_buffer;\n\nstruct ring_buffer_iter;\n\nstruct trace_iterator {\n\tstruct trace_array *tr;\n\tstruct tracer *trace;\n\tstruct array_buffer *array_buffer;\n\tvoid *private;\n\tint cpu_file;\n\tstruct mutex mutex;\n\tstruct ring_buffer_iter **buffer_iter;\n\tlong unsigned int iter_flags;\n\tvoid *temp;\n\tunsigned int temp_size;\n\tstruct trace_seq tmp_seq;\n\tcpumask_var_t started;\n\tbool snapshot;\n\tstruct trace_seq seq;\n\tstruct trace_entry *ent;\n\tlong unsigned int lost_events;\n\tint leftover;\n\tint ent_size;\n\tint cpu;\n\tu64 ts;\n\tloff_t pos;\n\tlong int idx;\n};\n\nenum print_line_t {\n\tTRACE_TYPE_PARTIAL_LINE = 0,\n\tTRACE_TYPE_HANDLED = 1,\n\tTRACE_TYPE_UNHANDLED = 2,\n\tTRACE_TYPE_NO_CONSUME = 3,\n};\n\ntypedef enum print_line_t (*trace_print_func)(struct trace_iterator *, int, struct trace_event *);\n\nstruct trace_event_functions {\n\ttrace_print_func trace;\n\ttrace_print_func raw;\n\ttrace_print_func hex;\n\ttrace_print_func binary;\n};\n\nenum trace_reg {\n\tTRACE_REG_REGISTER = 0,\n\tTRACE_REG_UNREGISTER = 1,\n\tTRACE_REG_PERF_REGISTER = 2,\n\tTRACE_REG_PERF_UNREGISTER = 3,\n\tTRACE_REG_PERF_OPEN = 4,\n\tTRACE_REG_PERF_CLOSE = 5,\n\tTRACE_REG_PERF_ADD = 6,\n\tTRACE_REG_PERF_DEL = 7,\n};\n\nstruct trace_event_fields {\n\tconst char *type;\n\tunion {\n\t\tstruct {\n\t\t\tconst char *name;\n\t\t\tconst int size;\n\t\t\tconst int align;\n\t\t\tconst int is_signed;\n\t\t\tconst int filter_type;\n\t\t};\n\t\tint (*define_fields)(struct trace_event_call *);\n\t};\n};\n\nstruct trace_event_class {\n\tconst char *system;\n\tvoid *probe;\n\tvoid *perf_probe;\n\tint (*reg)(struct trace_event_call *, enum trace_reg, void *);\n\tstruct trace_event_fields *fields_array;\n\tstruct list_head * (*get_fields)(struct trace_event_call *);\n\tstruct list_head fields;\n\tint (*raw_init)(struct trace_event_call *);\n};\n\nstruct trace_buffer;\n\nstruct trace_event_file;\n\nstruct trace_event_buffer {\n\tstruct trace_buffer *buffer;\n\tstruct ring_buffer_event *event;\n\tstruct trace_event_file *trace_file;\n\tvoid *entry;\n\tlong unsigned int flags;\n\tint pc;\n\tstruct pt_regs *regs;\n};\n\nstruct trace_subsystem_dir;\n\nstruct trace_event_file {\n\tstruct list_head list;\n\tstruct trace_event_call *event_call;\n\tstruct event_filter *filter;\n\tstruct dentry *dir;\n\tstruct trace_array *tr;\n\tstruct trace_subsystem_dir *system;\n\tstruct list_head triggers;\n\tlong unsigned int flags;\n\tatomic_t sm_ref;\n\tatomic_t tm_ref;\n};\n\nenum {\n\tTRACE_EVENT_FL_FILTERED_BIT = 0,\n\tTRACE_EVENT_FL_CAP_ANY_BIT = 1,\n\tTRACE_EVENT_FL_NO_SET_FILTER_BIT = 2,\n\tTRACE_EVENT_FL_IGNORE_ENABLE_BIT = 3,\n\tTRACE_EVENT_FL_TRACEPOINT_BIT = 4,\n\tTRACE_EVENT_FL_KPROBE_BIT = 5,\n\tTRACE_EVENT_FL_UPROBE_BIT = 6,\n};\n\nenum {\n\tTRACE_EVENT_FL_FILTERED = 1,\n\tTRACE_EVENT_FL_CAP_ANY = 2,\n\tTRACE_EVENT_FL_NO_SET_FILTER = 4,\n\tTRACE_EVENT_FL_IGNORE_ENABLE = 8,\n\tTRACE_EVENT_FL_TRACEPOINT = 16,\n\tTRACE_EVENT_FL_KPROBE = 32,\n\tTRACE_EVENT_FL_UPROBE = 64,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED_BIT = 0,\n\tEVENT_FILE_FL_RECORDED_CMD_BIT = 1,\n\tEVENT_FILE_FL_RECORDED_TGID_BIT = 2,\n\tEVENT_FILE_FL_FILTERED_BIT = 3,\n\tEVENT_FILE_FL_NO_SET_FILTER_BIT = 4,\n\tEVENT_FILE_FL_SOFT_MODE_BIT = 5,\n\tEVENT_FILE_FL_SOFT_DISABLED_BIT = 6,\n\tEVENT_FILE_FL_TRIGGER_MODE_BIT = 7,\n\tEVENT_FILE_FL_TRIGGER_COND_BIT = 8,\n\tEVENT_FILE_FL_PID_FILTER_BIT = 9,\n\tEVENT_FILE_FL_WAS_ENABLED_BIT = 10,\n};\n\nenum {\n\tEVENT_FILE_FL_ENABLED = 1,\n\tEVENT_FILE_FL_RECORDED_CMD = 2,\n\tEVENT_FILE_FL_RECORDED_TGID = 4,\n\tEVENT_FILE_FL_FILTERED = 8,\n\tEVENT_FILE_FL_NO_SET_FILTER = 16,\n\tEVENT_FILE_FL_SOFT_MODE = 32,\n\tEVENT_FILE_FL_SOFT_DISABLED = 64,\n\tEVENT_FILE_FL_TRIGGER_MODE = 128,\n\tEVENT_FILE_FL_TRIGGER_COND = 256,\n\tEVENT_FILE_FL_PID_FILTER = 512,\n\tEVENT_FILE_FL_WAS_ENABLED = 1024,\n};\n\nenum {\n\tFILTER_OTHER = 0,\n\tFILTER_STATIC_STRING = 1,\n\tFILTER_DYN_STRING = 2,\n\tFILTER_PTR_STRING = 3,\n\tFILTER_TRACE_FN = 4,\n\tFILTER_COMM = 5,\n\tFILTER_CPU = 6,\n};\n\nstruct rnd_state {\n\t__u32 s1;\n\t__u32 s2;\n\t__u32 s3;\n\t__u32 s4;\n};\n\nstruct property {\n\tchar *name;\n\tint length;\n\tvoid *value;\n\tstruct property *next;\n};\n\nstruct irq_fwspec {\n\tstruct fwnode_handle *fwnode;\n\tint param_count;\n\tu32 param[16];\n};\n\nstruct irq_data;\n\nstruct irq_domain_ops {\n\tint (*match)(struct irq_domain *, struct device_node *, enum irq_domain_bus_token);\n\tint (*select)(struct irq_domain *, struct irq_fwspec *, enum irq_domain_bus_token);\n\tint (*map)(struct irq_domain *, unsigned int, irq_hw_number_t);\n\tvoid (*unmap)(struct irq_domain *, unsigned int);\n\tint (*xlate)(struct irq_domain *, struct device_node *, const u32 *, unsigned int, long unsigned int *, unsigned int *);\n\tint (*alloc)(struct irq_domain *, unsigned int, unsigned int, void *);\n\tvoid (*free)(struct irq_domain *, unsigned int, unsigned int);\n\tint (*activate)(struct irq_domain *, struct irq_data *, bool);\n\tvoid (*deactivate)(struct irq_domain *, struct irq_data *);\n\tint (*translate)(struct irq_domain *, struct irq_fwspec *, long unsigned int *, unsigned int *);\n};\n\nstruct acpi_table_header {\n\tchar signature[4];\n\tu32 length;\n\tu8 revision;\n\tu8 checksum;\n\tchar oem_id[6];\n\tchar oem_table_id[8];\n\tu32 oem_revision;\n\tchar asl_compiler_id[4];\n\tu32 asl_compiler_revision;\n};\n\nstruct acpi_generic_address {\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_width;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_table_fadt {\n\tstruct acpi_table_header header;\n\tu32 facs;\n\tu32 dsdt;\n\tu8 model;\n\tu8 preferred_profile;\n\tu16 sci_interrupt;\n\tu32 smi_command;\n\tu8 acpi_enable;\n\tu8 acpi_disable;\n\tu8 s4_bios_request;\n\tu8 pstate_control;\n\tu32 pm1a_event_block;\n\tu32 pm1b_event_block;\n\tu32 pm1a_control_block;\n\tu32 pm1b_control_block;\n\tu32 pm2_control_block;\n\tu32 pm_timer_block;\n\tu32 gpe0_block;\n\tu32 gpe1_block;\n\tu8 pm1_event_length;\n\tu8 pm1_control_length;\n\tu8 pm2_control_length;\n\tu8 pm_timer_length;\n\tu8 gpe0_block_length;\n\tu8 gpe1_block_length;\n\tu8 gpe1_base;\n\tu8 cst_control;\n\tu16 c2_latency;\n\tu16 c3_latency;\n\tu16 flush_size;\n\tu16 flush_stride;\n\tu8 duty_offset;\n\tu8 duty_width;\n\tu8 day_alarm;\n\tu8 month_alarm;\n\tu8 century;\n\tu16 boot_flags;\n\tu8 reserved;\n\tu32 flags;\n\tstruct acpi_generic_address reset_register;\n\tu8 reset_value;\n\tu16 arm_boot_flags;\n\tu8 minor_revision;\n\tu64 Xfacs;\n\tu64 Xdsdt;\n\tstruct acpi_generic_address xpm1a_event_block;\n\tstruct acpi_generic_address xpm1b_event_block;\n\tstruct acpi_generic_address xpm1a_control_block;\n\tstruct acpi_generic_address xpm1b_control_block;\n\tstruct acpi_generic_address xpm2_control_block;\n\tstruct acpi_generic_address xpm_timer_block;\n\tstruct acpi_generic_address xgpe0_block;\n\tstruct acpi_generic_address xgpe1_block;\n\tstruct acpi_generic_address sleep_control;\n\tstruct acpi_generic_address sleep_status;\n\tu64 hypervisor_id;\n} __attribute__((packed));\n\nenum acpi_irq_model_id {\n\tACPI_IRQ_MODEL_PIC = 0,\n\tACPI_IRQ_MODEL_IOAPIC = 1,\n\tACPI_IRQ_MODEL_IOSAPIC = 2,\n\tACPI_IRQ_MODEL_PLATFORM = 3,\n\tACPI_IRQ_MODEL_GIC = 4,\n\tACPI_IRQ_MODEL_COUNT = 5,\n};\n\nenum con_scroll {\n\tSM_UP = 0,\n\tSM_DOWN = 1,\n};\n\nstruct vc_data;\n\nstruct console_font;\n\nstruct consw {\n\tstruct module *owner;\n\tconst char * (*con_startup)();\n\tvoid (*con_init)(struct vc_data *, int);\n\tvoid (*con_deinit)(struct vc_data *);\n\tvoid (*con_clear)(struct vc_data *, int, int, int, int);\n\tvoid (*con_putc)(struct vc_data *, int, int, int);\n\tvoid (*con_putcs)(struct vc_data *, const short unsigned int *, int, int, int);\n\tvoid (*con_cursor)(struct vc_data *, int);\n\tbool (*con_scroll)(struct vc_data *, unsigned int, unsigned int, enum con_scroll, unsigned int);\n\tint (*con_switch)(struct vc_data *);\n\tint (*con_blank)(struct vc_data *, int, int);\n\tint (*con_font_set)(struct vc_data *, struct console_font *, unsigned int);\n\tint (*con_font_get)(struct vc_data *, struct console_font *);\n\tint (*con_font_default)(struct vc_data *, struct console_font *, char *);\n\tint (*con_font_copy)(struct vc_data *, int);\n\tint (*con_resize)(struct vc_data *, unsigned int, unsigned int, unsigned int);\n\tvoid (*con_set_palette)(struct vc_data *, const unsigned char *);\n\tvoid (*con_scrolldelta)(struct vc_data *, int);\n\tint (*con_set_origin)(struct vc_data *);\n\tvoid (*con_save_screen)(struct vc_data *);\n\tu8 (*con_build_attr)(struct vc_data *, u8, u8, u8, u8, u8, u8);\n\tvoid (*con_invert_region)(struct vc_data *, u16 *, int);\n\tu16 * (*con_screen_pos)(struct vc_data *, int);\n\tlong unsigned int (*con_getxy)(struct vc_data *, long unsigned int, int *, int *);\n\tvoid (*con_flush_scrollback)(struct vc_data *);\n\tint (*con_debug_enter)(struct vc_data *);\n\tint (*con_debug_leave)(struct vc_data *);\n};\n\nstruct tty_driver;\n\nstruct console {\n\tchar name[16];\n\tvoid (*write)(struct console *, const char *, unsigned int);\n\tint (*read)(struct console *, char *, unsigned int);\n\tstruct tty_driver * (*device)(struct console *, int *);\n\tvoid (*unblank)();\n\tint (*setup)(struct console *, char *);\n\tint (*exit)(struct console *);\n\tint (*match)(struct console *, char *, int, char *);\n\tshort int flags;\n\tshort int index;\n\tint cflag;\n\tvoid *data;\n\tstruct console *next;\n};\n\nstruct fprop_global {\n\tstruct percpu_counter events;\n\tunsigned int period;\n\tseqcount_t sequence;\n};\n\nenum wb_stat_item {\n\tWB_RECLAIMABLE = 0,\n\tWB_WRITEBACK = 1,\n\tWB_DIRTIED = 2,\n\tWB_WRITTEN = 3,\n\tNR_WB_STAT_ITEMS = 4,\n};\n\nstruct bdi_writeback_congested {\n\tlong unsigned int state;\n\trefcount_t refcnt;\n};\n\nstruct partition_meta_info {\n\tchar uuid[37];\n\tu8 volname[64];\n};\n\nstruct disk_part_tbl {\n\tstruct callback_head callback_head;\n\tint len;\n\tstruct hd_struct *last_lookup;\n\tstruct hd_struct *part[0];\n};\n\nstruct blk_zone;\n\ntypedef int (*report_zones_cb)(struct blk_zone *, unsigned int, void *);\n\nstruct hd_geometry;\n\nstruct pr_ops;\n\nstruct block_device_operations {\n\tint (*open)(struct block_device *, fmode_t);\n\tvoid (*release)(struct gendisk *, fmode_t);\n\tint (*rw_page)(struct block_device *, sector_t, struct page *, unsigned int);\n\tint (*ioctl)(struct block_device *, fmode_t, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct block_device *, fmode_t, unsigned int, long unsigned int);\n\tunsigned int (*check_events)(struct gendisk *, unsigned int);\n\tint (*media_changed)(struct gendisk *);\n\tvoid (*unlock_native_capacity)(struct gendisk *);\n\tint (*revalidate_disk)(struct gendisk *);\n\tint (*getgeo)(struct block_device *, struct hd_geometry *);\n\tvoid (*swap_slot_free_notify)(struct block_device *, long unsigned int);\n\tint (*report_zones)(struct gendisk *, sector_t, unsigned int, report_zones_cb, void *);\n\tchar * (*devnode)(struct gendisk *, umode_t *);\n\tstruct module *owner;\n\tconst struct pr_ops *pr_ops;\n};\n\nstruct sg_io_v4 {\n\t__s32 guard;\n\t__u32 protocol;\n\t__u32 subprotocol;\n\t__u32 request_len;\n\t__u64 request;\n\t__u64 request_tag;\n\t__u32 request_attr;\n\t__u32 request_priority;\n\t__u32 request_extra;\n\t__u32 max_response_len;\n\t__u64 response;\n\t__u32 dout_iovec_count;\n\t__u32 dout_xfer_len;\n\t__u32 din_iovec_count;\n\t__u32 din_xfer_len;\n\t__u64 dout_xferp;\n\t__u64 din_xferp;\n\t__u32 timeout;\n\t__u32 flags;\n\t__u64 usr_ptr;\n\t__u32 spare_in;\n\t__u32 driver_status;\n\t__u32 transport_status;\n\t__u32 device_status;\n\t__u32 retry_delay;\n\t__u32 info;\n\t__u32 duration;\n\t__u32 response_len;\n\t__s32 din_resid;\n\t__s32 dout_resid;\n\t__u64 generated_tag;\n\t__u32 spare_out;\n\t__u32 padding;\n};\n\nstruct bsg_ops {\n\tint (*check_proto)(struct sg_io_v4 *);\n\tint (*fill_hdr)(struct request *, struct sg_io_v4 *, fmode_t);\n\tint (*complete_rq)(struct request *, struct sg_io_v4 *);\n\tvoid (*free_rq)(struct request *);\n};\n\ntypedef __u32 req_flags_t;\n\ntypedef void rq_end_io_fn(struct request *, blk_status_t);\n\nenum mq_rq_state {\n\tMQ_RQ_IDLE = 0,\n\tMQ_RQ_IN_FLIGHT = 1,\n\tMQ_RQ_COMPLETE = 2,\n};\n\nstruct request {\n\tstruct request_queue *q;\n\tstruct blk_mq_ctx *mq_ctx;\n\tstruct blk_mq_hw_ctx *mq_hctx;\n\tunsigned int cmd_flags;\n\treq_flags_t rq_flags;\n\tint tag;\n\tint internal_tag;\n\tunsigned int __data_len;\n\tsector_t __sector;\n\tstruct bio *bio;\n\tstruct bio *biotail;\n\tstruct list_head queuelist;\n\tunion {\n\t\tstruct hlist_node hash;\n\t\tstruct list_head ipi_list;\n\t};\n\tunion {\n\t\tstruct rb_node rb_node;\n\t\tstruct bio_vec special_vec;\n\t\tvoid *completion_data;\n\t\tint error_count;\n\t};\n\tunion {\n\t\tstruct {\n\t\t\tstruct io_cq *icq;\n\t\t\tvoid *priv[2];\n\t\t} elv;\n\t\tstruct {\n\t\t\tunsigned int seq;\n\t\t\tstruct list_head list;\n\t\t\trq_end_io_fn *saved_end_io;\n\t\t} flush;\n\t};\n\tstruct gendisk *rq_disk;\n\tstruct hd_struct *part;\n\tu64 start_time_ns;\n\tu64 io_start_time_ns;\n\tshort unsigned int stats_sectors;\n\tshort unsigned int nr_phys_segments;\n\tshort unsigned int write_hint;\n\tshort unsigned int ioprio;\n\tenum mq_rq_state state;\n\trefcount_t ref;\n\tunsigned int timeout;\n\tlong unsigned int deadline;\n\tunion {\n\t\tstruct __call_single_data csd;\n\t\tu64 fifo_time;\n\t};\n\trq_end_io_fn *end_io;\n\tvoid *end_io_data;\n};\n\nstruct blk_zone {\n\t__u64 start;\n\t__u64 len;\n\t__u64 wp;\n\t__u8 type;\n\t__u8 cond;\n\t__u8 non_seq;\n\t__u8 reset;\n\t__u8 reserved[36];\n};\n\nenum elv_merge {\n\tELEVATOR_NO_MERGE = 0,\n\tELEVATOR_FRONT_MERGE = 1,\n\tELEVATOR_BACK_MERGE = 2,\n\tELEVATOR_DISCARD_MERGE = 3,\n};\n\nstruct elevator_type;\n\nstruct blk_mq_alloc_data;\n\nstruct elevator_mq_ops {\n\tint (*init_sched)(struct request_queue *, struct elevator_type *);\n\tvoid (*exit_sched)(struct elevator_queue *);\n\tint (*init_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*exit_hctx)(struct blk_mq_hw_ctx *, unsigned int);\n\tvoid (*depth_updated)(struct blk_mq_hw_ctx *);\n\tbool (*allow_merge)(struct request_queue *, struct request *, struct bio *);\n\tbool (*bio_merge)(struct blk_mq_hw_ctx *, struct bio *, unsigned int);\n\tint (*request_merge)(struct request_queue *, struct request **, struct bio *);\n\tvoid (*request_merged)(struct request_queue *, struct request *, enum elv_merge);\n\tvoid (*requests_merged)(struct request_queue *, struct request *, struct request *);\n\tvoid (*limit_depth)(unsigned int, struct blk_mq_alloc_data *);\n\tvoid (*prepare_request)(struct request *);\n\tvoid (*finish_request)(struct request *);\n\tvoid (*insert_requests)(struct blk_mq_hw_ctx *, struct list_head *, bool);\n\tstruct request * (*dispatch_request)(struct blk_mq_hw_ctx *);\n\tbool (*has_work)(struct blk_mq_hw_ctx *);\n\tvoid (*completed_request)(struct request *, u64);\n\tvoid (*requeue_request)(struct request *);\n\tstruct request * (*former_request)(struct request_queue *, struct request *);\n\tstruct request * (*next_request)(struct request_queue *, struct request *);\n\tvoid (*init_icq)(struct io_cq *);\n\tvoid (*exit_icq)(struct io_cq *);\n};\n\nstruct elv_fs_entry;\n\nstruct blk_mq_debugfs_attr;\n\nstruct elevator_type {\n\tstruct kmem_cache *icq_cache;\n\tstruct elevator_mq_ops ops;\n\tsize_t icq_size;\n\tsize_t icq_align;\n\tstruct elv_fs_entry *elevator_attrs;\n\tconst char *elevator_name;\n\tconst char *elevator_alias;\n\tconst unsigned int elevator_features;\n\tstruct module *elevator_owner;\n\tconst struct blk_mq_debugfs_attr *queue_debugfs_attrs;\n\tconst struct blk_mq_debugfs_attr *hctx_debugfs_attrs;\n\tchar icq_cache_name[22];\n\tstruct list_head list;\n};\n\nstruct elevator_queue {\n\tstruct elevator_type *type;\n\tvoid *elevator_data;\n\tstruct kobject kobj;\n\tstruct mutex sysfs_lock;\n\tunsigned int registered: 1;\n\tstruct hlist_head hash[64];\n};\n\nstruct elv_fs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct elevator_queue *, char *);\n\tssize_t (*store)(struct elevator_queue *, const char *, size_t);\n};\n\nstruct blk_mq_debugfs_attr {\n\tconst char *name;\n\tumode_t mode;\n\tint (*show)(void *, struct seq_file *);\n\tssize_t (*write)(void *, const char *, size_t, loff_t *);\n\tconst struct seq_operations *seq_ops;\n};\n\nstruct blk_mq_queue_data;\n\ntypedef blk_status_t queue_rq_fn(struct blk_mq_hw_ctx *, const struct blk_mq_queue_data *);\n\ntypedef void commit_rqs_fn(struct blk_mq_hw_ctx *);\n\ntypedef bool get_budget_fn(struct blk_mq_hw_ctx *);\n\ntypedef void put_budget_fn(struct blk_mq_hw_ctx *);\n\nenum blk_eh_timer_return {\n\tBLK_EH_DONE = 0,\n\tBLK_EH_RESET_TIMER = 1,\n};\n\ntypedef enum blk_eh_timer_return timeout_fn(struct request *, bool);\n\ntypedef int poll_fn(struct blk_mq_hw_ctx *);\n\ntypedef void complete_fn(struct request *);\n\ntypedef int init_hctx_fn(struct blk_mq_hw_ctx *, void *, unsigned int);\n\ntypedef void exit_hctx_fn(struct blk_mq_hw_ctx *, unsigned int);\n\ntypedef int init_request_fn(struct blk_mq_tag_set *, struct request *, unsigned int, unsigned int);\n\ntypedef void exit_request_fn(struct blk_mq_tag_set *, struct request *, unsigned int);\n\ntypedef void cleanup_rq_fn(struct request *);\n\ntypedef bool busy_fn(struct request_queue *);\n\ntypedef int map_queues_fn(struct blk_mq_tag_set *);\n\nstruct blk_mq_ops {\n\tqueue_rq_fn *queue_rq;\n\tcommit_rqs_fn *commit_rqs;\n\tget_budget_fn *get_budget;\n\tput_budget_fn *put_budget;\n\ttimeout_fn *timeout;\n\tpoll_fn *poll;\n\tcomplete_fn *complete;\n\tinit_hctx_fn *init_hctx;\n\texit_hctx_fn *exit_hctx;\n\tinit_request_fn *init_request;\n\texit_request_fn *exit_request;\n\tvoid (*initialize_rq_fn)(struct request *);\n\tcleanup_rq_fn *cleanup_rq;\n\tbusy_fn *busy;\n\tmap_queues_fn *map_queues;\n\tvoid (*show_rq)(struct seq_file *, struct request *);\n};\n\nenum pr_type {\n\tPR_WRITE_EXCLUSIVE = 1,\n\tPR_EXCLUSIVE_ACCESS = 2,\n\tPR_WRITE_EXCLUSIVE_REG_ONLY = 3,\n\tPR_EXCLUSIVE_ACCESS_REG_ONLY = 4,\n\tPR_WRITE_EXCLUSIVE_ALL_REGS = 5,\n\tPR_EXCLUSIVE_ACCESS_ALL_REGS = 6,\n};\n\nstruct pr_ops {\n\tint (*pr_register)(struct block_device *, u64, u64, u32);\n\tint (*pr_reserve)(struct block_device *, u64, enum pr_type, u32);\n\tint (*pr_release)(struct block_device *, u64, enum pr_type);\n\tint (*pr_preempt)(struct block_device *, u64, u64, enum pr_type, bool);\n\tint (*pr_clear)(struct block_device *, u64);\n};\n\nstruct wb_domain {\n\tspinlock_t lock;\n\tstruct fprop_global completions;\n\tstruct timer_list period_timer;\n\tlong unsigned int period_time;\n\tlong unsigned int dirty_limit_tstamp;\n\tlong unsigned int dirty_limit;\n};\n\nenum cpu_idle_type {\n\tCPU_IDLE = 0,\n\tCPU_NOT_IDLE = 1,\n\tCPU_NEWLY_IDLE = 2,\n\tCPU_MAX_IDLE_TYPES = 3,\n};\n\nenum reboot_mode {\n\tREBOOT_UNDEFINED = 4294967295,\n\tREBOOT_COLD = 0,\n\tREBOOT_WARM = 1,\n\tREBOOT_HARD = 2,\n\tREBOOT_SOFT = 3,\n\tREBOOT_GPIO = 4,\n};\n\nenum reboot_type {\n\tBOOT_TRIPLE = 116,\n\tBOOT_KBD = 107,\n\tBOOT_BIOS = 98,\n\tBOOT_ACPI = 97,\n\tBOOT_EFI = 101,\n\tBOOT_CF9_FORCE = 112,\n\tBOOT_CF9_SAFE = 113,\n};\n\ntypedef long unsigned int efi_status_t;\n\ntypedef u8 efi_bool_t;\n\ntypedef u16 efi_char16_t;\n\ntypedef guid_t efi_guid_t;\n\ntypedef struct {\n\tu64 signature;\n\tu32 revision;\n\tu32 headersize;\n\tu32 crc32;\n\tu32 reserved;\n} efi_table_hdr_t;\n\ntypedef struct {\n\tu32 type;\n\tu32 pad;\n\tu64 phys_addr;\n\tu64 virt_addr;\n\tu64 num_pages;\n\tu64 attribute;\n} efi_memory_desc_t;\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu32 headersize;\n\tu32 flags;\n\tu32 imagesize;\n} efi_capsule_header_t;\n\ntypedef struct {\n\tu16 year;\n\tu8 month;\n\tu8 day;\n\tu8 hour;\n\tu8 minute;\n\tu8 second;\n\tu8 pad1;\n\tu32 nanosecond;\n\ts16 timezone;\n\tu8 daylight;\n\tu8 pad2;\n} efi_time_t;\n\ntypedef struct {\n\tu32 resolution;\n\tu32 accuracy;\n\tu8 sets_to_zero;\n} efi_time_cap_t;\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu32 get_time;\n\tu32 set_time;\n\tu32 get_wakeup_time;\n\tu32 set_wakeup_time;\n\tu32 set_virtual_address_map;\n\tu32 convert_pointer;\n\tu32 get_variable;\n\tu32 get_next_variable;\n\tu32 set_variable;\n\tu32 get_next_high_mono_count;\n\tu32 reset_system;\n\tu32 update_capsule;\n\tu32 query_capsule_caps;\n\tu32 query_variable_info;\n} efi_runtime_services_32_t;\n\ntypedef efi_status_t efi_get_time_t(efi_time_t *, efi_time_cap_t *);\n\ntypedef efi_status_t efi_set_time_t(efi_time_t *);\n\ntypedef efi_status_t efi_get_wakeup_time_t(efi_bool_t *, efi_bool_t *, efi_time_t *);\n\ntypedef efi_status_t efi_set_wakeup_time_t(efi_bool_t, efi_time_t *);\n\ntypedef efi_status_t efi_get_variable_t(efi_char16_t *, efi_guid_t *, u32 *, long unsigned int *, void *);\n\ntypedef efi_status_t efi_get_next_variable_t(long unsigned int *, efi_char16_t *, efi_guid_t *);\n\ntypedef efi_status_t efi_set_variable_t(efi_char16_t *, efi_guid_t *, u32, long unsigned int, void *);\n\ntypedef efi_status_t efi_get_next_high_mono_count_t(u32 *);\n\ntypedef void efi_reset_system_t(int, efi_status_t, long unsigned int, efi_char16_t *);\n\ntypedef efi_status_t efi_query_variable_info_t(u32, u64 *, u64 *, u64 *);\n\ntypedef efi_status_t efi_update_capsule_t(efi_capsule_header_t **, long unsigned int, long unsigned int);\n\ntypedef efi_status_t efi_query_capsule_caps_t(efi_capsule_header_t **, long unsigned int, u64 *, int *);\n\ntypedef union {\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tefi_status_t (*get_time)(efi_time_t *, efi_time_cap_t *);\n\t\tefi_status_t (*set_time)(efi_time_t *);\n\t\tefi_status_t (*get_wakeup_time)(efi_bool_t *, efi_bool_t *, efi_time_t *);\n\t\tefi_status_t (*set_wakeup_time)(efi_bool_t, efi_time_t *);\n\t\tefi_status_t (*set_virtual_address_map)(long unsigned int, long unsigned int, u32, efi_memory_desc_t *);\n\t\tvoid *convert_pointer;\n\t\tefi_status_t (*get_variable)(efi_char16_t *, efi_guid_t *, u32 *, long unsigned int *, void *);\n\t\tefi_status_t (*get_next_variable)(long unsigned int *, efi_char16_t *, efi_guid_t *);\n\t\tefi_status_t (*set_variable)(efi_char16_t *, efi_guid_t *, u32, long unsigned int, void *);\n\t\tefi_status_t (*get_next_high_mono_count)(u32 *);\n\t\tvoid (*reset_system)(int, efi_status_t, long unsigned int, efi_char16_t *);\n\t\tefi_status_t (*update_capsule)(efi_capsule_header_t **, long unsigned int, long unsigned int);\n\t\tefi_status_t (*query_capsule_caps)(efi_capsule_header_t **, long unsigned int, u64 *, int *);\n\t\tefi_status_t (*query_variable_info)(u32, u64 *, u64 *, u64 *);\n\t};\n\tefi_runtime_services_32_t mixed_mode;\n} efi_runtime_services_t;\n\nstruct efi_memory_map {\n\tphys_addr_t phys_map;\n\tvoid *map;\n\tvoid *map_end;\n\tint nr_map;\n\tlong unsigned int desc_version;\n\tlong unsigned int desc_size;\n\tlong unsigned int flags;\n};\n\nstruct efi {\n\tconst efi_runtime_services_t *runtime;\n\tunsigned int runtime_version;\n\tunsigned int runtime_supported_mask;\n\tlong unsigned int acpi;\n\tlong unsigned int acpi20;\n\tlong unsigned int smbios;\n\tlong unsigned int smbios3;\n\tlong unsigned int esrt;\n\tlong unsigned int tpm_log;\n\tlong unsigned int tpm_final_log;\n\tefi_get_time_t *get_time;\n\tefi_set_time_t *set_time;\n\tefi_get_wakeup_time_t *get_wakeup_time;\n\tefi_set_wakeup_time_t *set_wakeup_time;\n\tefi_get_variable_t *get_variable;\n\tefi_get_next_variable_t *get_next_variable;\n\tefi_set_variable_t *set_variable;\n\tefi_set_variable_t *set_variable_nonblocking;\n\tefi_query_variable_info_t *query_variable_info;\n\tefi_query_variable_info_t *query_variable_info_nonblocking;\n\tefi_update_capsule_t *update_capsule;\n\tefi_query_capsule_caps_t *query_capsule_caps;\n\tefi_get_next_high_mono_count_t *get_next_high_mono_count;\n\tefi_reset_system_t *reset_system;\n\tstruct efi_memory_map memmap;\n\tlong unsigned int flags;\n};\n\nenum efi_rts_ids {\n\tEFI_NONE = 0,\n\tEFI_GET_TIME = 1,\n\tEFI_SET_TIME = 2,\n\tEFI_GET_WAKEUP_TIME = 3,\n\tEFI_SET_WAKEUP_TIME = 4,\n\tEFI_GET_VARIABLE = 5,\n\tEFI_GET_NEXT_VARIABLE = 6,\n\tEFI_SET_VARIABLE = 7,\n\tEFI_QUERY_VARIABLE_INFO = 8,\n\tEFI_GET_NEXT_HIGH_MONO_COUNT = 9,\n\tEFI_RESET_SYSTEM = 10,\n\tEFI_UPDATE_CAPSULE = 11,\n\tEFI_QUERY_CAPSULE_CAPS = 12,\n};\n\nstruct efi_runtime_work {\n\tvoid *arg1;\n\tvoid *arg2;\n\tvoid *arg3;\n\tvoid *arg4;\n\tvoid *arg5;\n\tefi_status_t status;\n\tstruct work_struct work;\n\tenum efi_rts_ids efi_rts_id;\n\tstruct completion efi_rts_comp;\n};\n\nstruct percpu_cluster {\n\tstruct swap_cluster_info index;\n\tunsigned int next;\n};\n\nenum fs_value_type {\n\tfs_value_is_undefined = 0,\n\tfs_value_is_flag = 1,\n\tfs_value_is_string = 2,\n\tfs_value_is_blob = 3,\n\tfs_value_is_filename = 4,\n\tfs_value_is_file = 5,\n};\n\nstruct fs_parameter {\n\tconst char *key;\n\tenum fs_value_type type: 8;\n\tunion {\n\t\tchar *string;\n\t\tvoid *blob;\n\t\tstruct filename *name;\n\t\tstruct file *file;\n\t};\n\tsize_t size;\n\tint dirfd;\n};\n\nstruct fc_log {\n\trefcount_t usage;\n\tu8 head;\n\tu8 tail;\n\tu8 need_free;\n\tstruct module *owner;\n\tchar *buffer[8];\n};\n\nstruct fs_context_operations {\n\tvoid (*free)(struct fs_context *);\n\tint (*dup)(struct fs_context *, struct fs_context *);\n\tint (*parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*parse_monolithic)(struct fs_context *, void *);\n\tint (*get_tree)(struct fs_context *);\n\tint (*reconfigure)(struct fs_context *);\n};\n\nstruct fs_parse_result {\n\tbool negated;\n\tunion {\n\t\tbool boolean;\n\t\tint int_32;\n\t\tunsigned int uint_32;\n\t\tu64 uint_64;\n\t};\n};\n\nstruct trace_event_raw_initcall_level {\n\tstruct trace_entry ent;\n\tu32 __data_loc_level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_start {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_initcall_finish {\n\tstruct trace_entry ent;\n\tinitcall_t func;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_initcall_level {\n\tu32 level;\n};\n\nstruct trace_event_data_offsets_initcall_start {};\n\nstruct trace_event_data_offsets_initcall_finish {};\n\ntypedef void (*btf_trace_initcall_level)(void *, const char *);\n\ntypedef void (*btf_trace_initcall_start)(void *, initcall_t);\n\ntypedef void (*btf_trace_initcall_finish)(void *, initcall_t, int);\n\nstruct blacklist_entry {\n\tstruct list_head next;\n\tchar *buf;\n};\n\ntypedef __u32 Elf32_Word;\n\nstruct elf32_note {\n\tElf32_Word n_namesz;\n\tElf32_Word n_descsz;\n\tElf32_Word n_type;\n};\n\nenum {\n\tUNAME26 = 131072,\n\tADDR_NO_RANDOMIZE = 262144,\n\tFDPIC_FUNCPTRS = 524288,\n\tMMAP_PAGE_ZERO = 1048576,\n\tADDR_COMPAT_LAYOUT = 2097152,\n\tREAD_IMPLIES_EXEC = 4194304,\n\tADDR_LIMIT_32BIT = 8388608,\n\tSHORT_INODE = 16777216,\n\tWHOLE_SECONDS = 33554432,\n\tSTICKY_TIMEOUTS = 67108864,\n\tADDR_LIMIT_3GB = 134217728,\n};\n\nenum tlb_infos {\n\tENTRIES = 0,\n\tNR_INFO = 1,\n};\n\nenum {\n\tMM_FILEPAGES = 0,\n\tMM_ANONPAGES = 1,\n\tMM_SWAPENTS = 2,\n\tMM_SHMEMPAGES = 3,\n\tNR_MM_COUNTERS = 4,\n};\n\nenum hrtimer_base_type {\n\tHRTIMER_BASE_MONOTONIC = 0,\n\tHRTIMER_BASE_REALTIME = 1,\n\tHRTIMER_BASE_BOOTTIME = 2,\n\tHRTIMER_BASE_TAI = 3,\n\tHRTIMER_BASE_MONOTONIC_SOFT = 4,\n\tHRTIMER_BASE_REALTIME_SOFT = 5,\n\tHRTIMER_BASE_BOOTTIME_SOFT = 6,\n\tHRTIMER_BASE_TAI_SOFT = 7,\n\tHRTIMER_MAX_CLOCK_BASES = 8,\n};\n\nenum rseq_cs_flags_bit {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT_BIT = 0,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT = 2,\n};\n\nenum perf_event_task_context {\n\tperf_invalid_context = 4294967295,\n\tperf_hw_context = 0,\n\tperf_sw_context = 1,\n\tperf_nr_task_contexts = 2,\n};\n\nenum rseq_event_mask_bits {\n\tRSEQ_EVENT_PREEMPT_BIT = 0,\n\tRSEQ_EVENT_SIGNAL_BIT = 1,\n\tRSEQ_EVENT_MIGRATE_BIT = 2,\n};\n\nenum {\n\tPROC_ROOT_INO = 1,\n\tPROC_IPC_INIT_INO = 4026531839,\n\tPROC_UTS_INIT_INO = 4026531838,\n\tPROC_USER_INIT_INO = 4026531837,\n\tPROC_PID_INIT_INO = 4026531836,\n\tPROC_CGROUP_INIT_INO = 4026531835,\n\tPROC_TIME_INIT_INO = 4026531834,\n};\n\ntypedef __u16 __le16;\n\ntypedef __u16 __be16;\n\ntypedef __u32 __be32;\n\ntypedef __u64 __be64;\n\ntypedef __u32 __wsum;\n\ntypedef u64 uint64_t;\n\ntypedef unsigned int slab_flags_t;\n\nstruct raw_notifier_head {\n\tstruct notifier_block *head;\n};\n\nstruct llist_head {\n\tstruct llist_node *first;\n};\n\ntypedef struct __call_single_data call_single_data_t;\n\nstruct ida {\n\tstruct xarray xa;\n};\n\ntypedef __u64 __addrpair;\n\ntypedef __u32 __portpair;\n\ntypedef struct {\n\tstruct net *net;\n} possible_net_t;\n\nstruct in6_addr {\n\tunion {\n\t\t__u8 u6_addr8[16];\n\t\t__be16 u6_addr16[8];\n\t\t__be32 u6_addr32[4];\n\t} in6_u;\n};\n\nstruct hlist_nulls_node {\n\tstruct hlist_nulls_node *next;\n\tstruct hlist_nulls_node **pprev;\n};\n\nstruct proto;\n\nstruct inet_timewait_death_row;\n\nstruct sock_common {\n\tunion {\n\t\t__addrpair skc_addrpair;\n\t\tstruct {\n\t\t\t__be32 skc_daddr;\n\t\t\t__be32 skc_rcv_saddr;\n\t\t};\n\t};\n\tunion {\n\t\tunsigned int skc_hash;\n\t\t__u16 skc_u16hashes[2];\n\t};\n\tunion {\n\t\t__portpair skc_portpair;\n\t\tstruct {\n\t\t\t__be16 skc_dport;\n\t\t\t__u16 skc_num;\n\t\t};\n\t};\n\tshort unsigned int skc_family;\n\tvolatile unsigned char skc_state;\n\tunsigned char skc_reuse: 4;\n\tunsigned char skc_reuseport: 1;\n\tunsigned char skc_ipv6only: 1;\n\tunsigned char skc_net_refcnt: 1;\n\tint skc_bound_dev_if;\n\tunion {\n\t\tstruct hlist_node skc_bind_node;\n\t\tstruct hlist_node skc_portaddr_node;\n\t};\n\tstruct proto *skc_prot;\n\tpossible_net_t skc_net;\n\tstruct in6_addr skc_v6_daddr;\n\tstruct in6_addr skc_v6_rcv_saddr;\n\tatomic64_t skc_cookie;\n\tunion {\n\t\tlong unsigned int skc_flags;\n\t\tstruct sock *skc_listener;\n\t\tstruct inet_timewait_death_row *skc_tw_dr;\n\t};\n\tint skc_dontcopy_begin[0];\n\tunion {\n\t\tstruct hlist_node skc_node;\n\t\tstruct hlist_nulls_node skc_nulls_node;\n\t};\n\tshort unsigned int skc_tx_queue_mapping;\n\tshort unsigned int skc_rx_queue_mapping;\n\tunion {\n\t\tint skc_incoming_cpu;\n\t\tu32 skc_rcv_wnd;\n\t\tu32 skc_tw_rcv_nxt;\n\t};\n\trefcount_t skc_refcnt;\n\tint skc_dontcopy_end[0];\n\tunion {\n\t\tu32 skc_rxhash;\n\t\tu32 skc_window_clamp;\n\t\tu32 skc_tw_snd_nxt;\n\t};\n};\n\ntypedef struct {\n\tspinlock_t slock;\n\tint owned;\n\twait_queue_head_t wq;\n} socket_lock_t;\n\nstruct sk_buff;\n\nstruct sk_buff_head {\n\tstruct sk_buff *next;\n\tstruct sk_buff *prev;\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\ntypedef u64 netdev_features_t;\n\nstruct sock_cgroup_data {\n\tunion {\n\t\tstruct {\n\t\t\tu8 is_data: 1;\n\t\t\tu8 no_refcnt: 1;\n\t\t\tu8 unused: 6;\n\t\t\tu8 padding;\n\t\t\tu16 prioidx;\n\t\t\tu32 classid;\n\t\t};\n\t\tu64 val;\n\t};\n};\n\nstruct sk_filter;\n\nstruct socket_wq;\n\nstruct xfrm_policy;\n\nstruct dst_entry;\n\nstruct socket;\n\nstruct sock_reuseport;\n\nstruct bpf_sk_storage;\n\nstruct sock {\n\tstruct sock_common __sk_common;\n\tsocket_lock_t sk_lock;\n\tatomic_t sk_drops;\n\tint sk_rcvlowat;\n\tstruct sk_buff_head sk_error_queue;\n\tstruct sk_buff *sk_rx_skb_cache;\n\tstruct sk_buff_head sk_receive_queue;\n\tstruct {\n\t\tatomic_t rmem_alloc;\n\t\tint len;\n\t\tstruct sk_buff *head;\n\t\tstruct sk_buff *tail;\n\t} sk_backlog;\n\tint sk_forward_alloc;\n\tunsigned int sk_ll_usec;\n\tunsigned int sk_napi_id;\n\tint sk_rcvbuf;\n\tstruct sk_filter *sk_filter;\n\tunion {\n\t\tstruct socket_wq *sk_wq;\n\t\tstruct socket_wq *sk_wq_raw;\n\t};\n\tstruct xfrm_policy *sk_policy[2];\n\tstruct dst_entry *sk_rx_dst;\n\tstruct dst_entry *sk_dst_cache;\n\tatomic_t sk_omem_alloc;\n\tint sk_sndbuf;\n\tint sk_wmem_queued;\n\trefcount_t sk_wmem_alloc;\n\tlong unsigned int sk_tsq_flags;\n\tunion {\n\t\tstruct sk_buff *sk_send_head;\n\t\tstruct rb_root tcp_rtx_queue;\n\t};\n\tstruct sk_buff *sk_tx_skb_cache;\n\tstruct sk_buff_head sk_write_queue;\n\t__s32 sk_peek_off;\n\tint sk_write_pending;\n\t__u32 sk_dst_pending_confirm;\n\tu32 sk_pacing_status;\n\tlong int sk_sndtimeo;\n\tstruct timer_list sk_timer;\n\t__u32 sk_priority;\n\t__u32 sk_mark;\n\tlong unsigned int sk_pacing_rate;\n\tlong unsigned int sk_max_pacing_rate;\n\tstruct page_frag sk_frag;\n\tnetdev_features_t sk_route_caps;\n\tnetdev_features_t sk_route_nocaps;\n\tnetdev_features_t sk_route_forced_caps;\n\tint sk_gso_type;\n\tunsigned int sk_gso_max_size;\n\tgfp_t sk_allocation;\n\t__u32 sk_txhash;\n\tu8 sk_padding: 1;\n\tu8 sk_kern_sock: 1;\n\tu8 sk_no_check_tx: 1;\n\tu8 sk_no_check_rx: 1;\n\tu8 sk_userlocks: 4;\n\tu8 sk_pacing_shift;\n\tu16 sk_type;\n\tu16 sk_protocol;\n\tu16 sk_gso_max_segs;\n\tlong unsigned int sk_lingertime;\n\tstruct proto *sk_prot_creator;\n\trwlock_t sk_callback_lock;\n\tint sk_err;\n\tint sk_err_soft;\n\tu32 sk_ack_backlog;\n\tu32 sk_max_ack_backlog;\n\tkuid_t sk_uid;\n\tstruct pid *sk_peer_pid;\n\tconst struct cred *sk_peer_cred;\n\tlong int sk_rcvtimeo;\n\tktime_t sk_stamp;\n\tu16 sk_tsflags;\n\tu8 sk_shutdown;\n\tu32 sk_tskey;\n\tatomic_t sk_zckey;\n\tu8 sk_clockid;\n\tu8 sk_txtime_deadline_mode: 1;\n\tu8 sk_txtime_report_errors: 1;\n\tu8 sk_txtime_unused: 6;\n\tstruct socket *sk_socket;\n\tvoid *sk_user_data;\n\tvoid *sk_security;\n\tstruct sock_cgroup_data sk_cgrp_data;\n\tstruct mem_cgroup *sk_memcg;\n\tvoid (*sk_state_change)(struct sock *);\n\tvoid (*sk_data_ready)(struct sock *);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid (*sk_error_report)(struct sock *);\n\tint (*sk_backlog_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*sk_destruct)(struct sock *);\n\tstruct sock_reuseport *sk_reuseport_cb;\n\tstruct bpf_sk_storage *sk_bpf_storage;\n\tstruct callback_head sk_rcu;\n};\n\nstruct rhash_head {\n\tstruct rhash_head *next;\n};\n\nstruct rhashtable;\n\nstruct rhashtable_compare_arg {\n\tstruct rhashtable *ht;\n\tconst void *key;\n};\n\ntypedef u32 (*rht_hashfn_t)(const void *, u32, u32);\n\ntypedef u32 (*rht_obj_hashfn_t)(const void *, u32, u32);\n\ntypedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *, const void *);\n\nstruct rhashtable_params {\n\tu16 nelem_hint;\n\tu16 key_len;\n\tu16 key_offset;\n\tu16 head_offset;\n\tunsigned int max_size;\n\tu16 min_size;\n\tbool automatic_shrinking;\n\trht_hashfn_t hashfn;\n\trht_obj_hashfn_t obj_hashfn;\n\trht_obj_cmpfn_t obj_cmpfn;\n};\n\nstruct bucket_table;\n\nstruct rhashtable {\n\tstruct bucket_table *tbl;\n\tunsigned int key_len;\n\tunsigned int max_elems;\n\tstruct rhashtable_params p;\n\tbool rhlist;\n\tstruct work_struct run_work;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tatomic_t nelems;\n};\n\nstruct fs_struct {\n\tint users;\n\tspinlock_t lock;\n\tseqcount_t seq;\n\tint umask;\n\tint in_exec;\n\tstruct path root;\n\tstruct path pwd;\n};\n\ntypedef u32 compat_uptr_t;\n\nstruct compat_robust_list {\n\tcompat_uptr_t next;\n};\n\ntypedef s32 compat_long_t;\n\nstruct compat_robust_list_head {\n\tstruct compat_robust_list list;\n\tcompat_long_t futex_offset;\n\tcompat_uptr_t list_op_pending;\n};\n\nstruct pipe_buffer;\n\nstruct pipe_inode_info {\n\tstruct mutex mutex;\n\twait_queue_head_t rd_wait;\n\twait_queue_head_t wr_wait;\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int max_usage;\n\tunsigned int ring_size;\n\tunsigned int nr_accounted;\n\tunsigned int readers;\n\tunsigned int writers;\n\tunsigned int files;\n\tunsigned int r_counter;\n\tunsigned int w_counter;\n\tstruct page *tmp_page;\n\tstruct fasync_struct *fasync_readers;\n\tstruct fasync_struct *fasync_writers;\n\tstruct pipe_buffer *bufs;\n\tstruct user_struct *user;\n};\n\nstruct scatterlist {\n\tlong unsigned int page_link;\n\tunsigned int offset;\n\tunsigned int length;\n\tdma_addr_t dma_address;\n\tunsigned int dma_length;\n};\n\nstruct iovec {\n\tvoid *iov_base;\n\t__kernel_size_t iov_len;\n};\n\nstruct kvec {\n\tvoid *iov_base;\n\tsize_t iov_len;\n};\n\nstruct iov_iter {\n\tunsigned int type;\n\tsize_t iov_offset;\n\tsize_t count;\n\tunion {\n\t\tconst struct iovec *iov;\n\t\tconst struct kvec *kvec;\n\t\tconst struct bio_vec *bvec;\n\t\tstruct pipe_inode_info *pipe;\n\t};\n\tunion {\n\t\tlong unsigned int nr_segs;\n\t\tstruct {\n\t\t\tunsigned int head;\n\t\t\tunsigned int start_head;\n\t\t};\n\t};\n};\n\ntypedef short unsigned int __kernel_sa_family_t;\n\nstruct __kernel_sockaddr_storage {\n\tunion {\n\t\tstruct {\n\t\t\t__kernel_sa_family_t ss_family;\n\t\t\tchar __data[126];\n\t\t};\n\t\tvoid *__align;\n\t};\n};\n\ntypedef __kernel_sa_family_t sa_family_t;\n\nstruct sockaddr {\n\tsa_family_t sa_family;\n\tchar sa_data[14];\n};\n\nstruct msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tstruct iov_iter msg_iter;\n\tunion {\n\t\tvoid *msg_control;\n\t\tvoid *msg_control_user;\n\t};\n\tbool msg_control_is_user: 1;\n\t__kernel_size_t msg_controllen;\n\tunsigned int msg_flags;\n\tstruct kiocb *msg_iocb;\n};\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n} sync_serial_settings;\n\ntypedef struct {\n\tunsigned int clock_rate;\n\tunsigned int clock_type;\n\tshort unsigned int loopback;\n\tunsigned int slot_map;\n} te1_settings;\n\ntypedef struct {\n\tshort unsigned int encoding;\n\tshort unsigned int parity;\n} raw_hdlc_proto;\n\ntypedef struct {\n\tunsigned int t391;\n\tunsigned int t392;\n\tunsigned int n391;\n\tunsigned int n392;\n\tunsigned int n393;\n\tshort unsigned int lmi;\n\tshort unsigned int dce;\n} fr_proto;\n\ntypedef struct {\n\tunsigned int dlci;\n} fr_proto_pvc;\n\ntypedef struct {\n\tunsigned int dlci;\n\tchar master[16];\n} fr_proto_pvc_info;\n\ntypedef struct {\n\tunsigned int interval;\n\tunsigned int timeout;\n} cisco_proto;\n\ntypedef struct {\n\tshort unsigned int dce;\n\tunsigned int modulo;\n\tunsigned int window;\n\tunsigned int t1;\n\tunsigned int t2;\n\tunsigned int n2;\n} x25_hdlc_proto;\n\nstruct ifmap {\n\tlong unsigned int mem_start;\n\tlong unsigned int mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tunion {\n\t\traw_hdlc_proto *raw_hdlc;\n\t\tcisco_proto *cisco;\n\t\tfr_proto *fr;\n\t\tfr_proto_pvc *fr_pvc;\n\t\tfr_proto_pvc_info *fr_pvc_info;\n\t\tx25_hdlc_proto *x25;\n\t\tsync_serial_settings *sync;\n\t\tte1_settings *te1;\n\t} ifs_ifsu;\n};\n\nstruct ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tint ifru_ivalue;\n\t\tint ifru_mtu;\n\t\tstruct ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tvoid *ifru_data;\n\t\tstruct if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct vfsmount {\n\tstruct dentry *mnt_root;\n\tstruct super_block *mnt_sb;\n\tint mnt_flags;\n};\n\nstruct ld_semaphore {\n\tatomic_long_t count;\n\traw_spinlock_t wait_lock;\n\tunsigned int wait_readers;\n\tstruct list_head read_wait;\n\tstruct list_head write_wait;\n};\n\ntypedef unsigned int tcflag_t;\n\ntypedef unsigned char cc_t;\n\ntypedef unsigned int speed_t;\n\nstruct ktermios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct winsize {\n\tshort unsigned int ws_row;\n\tshort unsigned int ws_col;\n\tshort unsigned int ws_xpixel;\n\tshort unsigned int ws_ypixel;\n};\n\nstruct tty_operations;\n\nstruct tty_ldisc;\n\nstruct termiox;\n\nstruct tty_port;\n\nstruct tty_struct {\n\tint magic;\n\tstruct kref kref;\n\tstruct device *dev;\n\tstruct tty_driver *driver;\n\tconst struct tty_operations *ops;\n\tint index;\n\tstruct ld_semaphore ldisc_sem;\n\tstruct tty_ldisc *ldisc;\n\tstruct mutex atomic_write_lock;\n\tstruct mutex legacy_mutex;\n\tstruct mutex throttle_mutex;\n\tstruct rw_semaphore termios_rwsem;\n\tstruct mutex winsize_mutex;\n\tspinlock_t ctrl_lock;\n\tspinlock_t flow_lock;\n\tstruct ktermios termios;\n\tstruct ktermios termios_locked;\n\tstruct termiox *termiox;\n\tchar name[64];\n\tstruct pid *pgrp;\n\tstruct pid *session;\n\tlong unsigned int flags;\n\tint count;\n\tstruct winsize winsize;\n\tlong unsigned int stopped: 1;\n\tlong unsigned int flow_stopped: 1;\n\tint: 30;\n\tlong unsigned int unused: 62;\n\tint hw_stopped;\n\tlong unsigned int ctrl_status: 8;\n\tlong unsigned int packet: 1;\n\tint: 23;\n\tlong unsigned int unused_ctrl: 55;\n\tunsigned int receive_room;\n\tint flow_change;\n\tstruct tty_struct *link;\n\tstruct fasync_struct *fasync;\n\twait_queue_head_t write_wait;\n\twait_queue_head_t read_wait;\n\tstruct work_struct hangup_work;\n\tvoid *disc_data;\n\tvoid *driver_data;\n\tspinlock_t files_lock;\n\tstruct list_head tty_files;\n\tint closing;\n\tunsigned char *write_buf;\n\tint write_cnt;\n\tstruct work_struct SAK_work;\n\tstruct tty_port *port;\n};\n\ntypedef struct {\n\tsize_t written;\n\tsize_t count;\n\tunion {\n\t\tchar *buf;\n\t\tvoid *data;\n\t} arg;\n\tint error;\n} read_descriptor_t;\n\nstruct posix_acl_entry {\n\tshort int e_tag;\n\tshort unsigned int e_perm;\n\tunion {\n\t\tkuid_t e_uid;\n\t\tkgid_t e_gid;\n\t};\n};\n\nstruct posix_acl {\n\trefcount_t a_refcount;\n\tstruct callback_head a_rcu;\n\tunsigned int a_count;\n\tstruct posix_acl_entry a_entries[0];\n};\n\nstruct termiox {\n\t__u16 x_hflag;\n\t__u16 x_cflag;\n\t__u16 x_rflag[5];\n\t__u16 x_sflag;\n};\n\nstruct serial_icounter_struct;\n\nstruct serial_struct;\n\nstruct tty_operations {\n\tstruct tty_struct * (*lookup)(struct tty_driver *, struct file *, int);\n\tint (*install)(struct tty_driver *, struct tty_struct *);\n\tvoid (*remove)(struct tty_driver *, struct tty_struct *);\n\tint (*open)(struct tty_struct *, struct file *);\n\tvoid (*close)(struct tty_struct *, struct file *);\n\tvoid (*shutdown)(struct tty_struct *);\n\tvoid (*cleanup)(struct tty_struct *);\n\tint (*write)(struct tty_struct *, const unsigned char *, int);\n\tint (*put_char)(struct tty_struct *, unsigned char);\n\tvoid (*flush_chars)(struct tty_struct *);\n\tint (*write_room)(struct tty_struct *);\n\tint (*chars_in_buffer)(struct tty_struct *);\n\tint (*ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tlong int (*compat_ioctl)(struct tty_struct *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, struct ktermios *);\n\tvoid (*throttle)(struct tty_struct *);\n\tvoid (*unthrottle)(struct tty_struct *);\n\tvoid (*stop)(struct tty_struct *);\n\tvoid (*start)(struct tty_struct *);\n\tvoid (*hangup)(struct tty_struct *);\n\tint (*break_ctl)(struct tty_struct *, int);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tvoid (*set_ldisc)(struct tty_struct *);\n\tvoid (*wait_until_sent)(struct tty_struct *, int);\n\tvoid (*send_xchar)(struct tty_struct *, char);\n\tint (*tiocmget)(struct tty_struct *);\n\tint (*tiocmset)(struct tty_struct *, unsigned int, unsigned int);\n\tint (*resize)(struct tty_struct *, struct winsize *);\n\tint (*set_termiox)(struct tty_struct *, struct termiox *);\n\tint (*get_icount)(struct tty_struct *, struct serial_icounter_struct *);\n\tint (*get_serial)(struct tty_struct *, struct serial_struct *);\n\tint (*set_serial)(struct tty_struct *, struct serial_struct *);\n\tvoid (*show_fdinfo)(struct tty_struct *, struct seq_file *);\n\tint (*proc_show)(struct seq_file *, void *);\n};\n\nstruct proc_dir_entry;\n\nstruct tty_driver {\n\tint magic;\n\tstruct kref kref;\n\tstruct cdev **cdevs;\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *name;\n\tint name_base;\n\tint major;\n\tint minor_start;\n\tunsigned int num;\n\tshort int type;\n\tshort int subtype;\n\tstruct ktermios init_termios;\n\tlong unsigned int flags;\n\tstruct proc_dir_entry *proc_entry;\n\tstruct tty_driver *other;\n\tstruct tty_struct **ttys;\n\tstruct tty_port **ports;\n\tstruct ktermios **termios;\n\tvoid *driver_state;\n\tconst struct tty_operations *ops;\n\tstruct list_head tty_drivers;\n};\n\nstruct tty_buffer {\n\tunion {\n\t\tstruct tty_buffer *next;\n\t\tstruct llist_node free;\n\t};\n\tint used;\n\tint size;\n\tint commit;\n\tint read;\n\tint flags;\n\tlong unsigned int data[0];\n};\n\nstruct tty_bufhead {\n\tstruct tty_buffer *head;\n\tstruct work_struct work;\n\tstruct mutex lock;\n\tatomic_t priority;\n\tstruct tty_buffer sentinel;\n\tstruct llist_head free;\n\tatomic_t mem_used;\n\tint mem_limit;\n\tstruct tty_buffer *tail;\n};\n\nstruct tty_port_operations;\n\nstruct tty_port_client_operations;\n\nstruct tty_port {\n\tstruct tty_bufhead buf;\n\tstruct tty_struct *tty;\n\tstruct tty_struct *itty;\n\tconst struct tty_port_operations *ops;\n\tconst struct tty_port_client_operations *client_ops;\n\tspinlock_t lock;\n\tint blocked_open;\n\tint count;\n\twait_queue_head_t open_wait;\n\twait_queue_head_t delta_msr_wait;\n\tlong unsigned int flags;\n\tlong unsigned int iflags;\n\tunsigned char console: 1;\n\tunsigned char low_latency: 1;\n\tstruct mutex mutex;\n\tstruct mutex buf_mutex;\n\tunsigned char *xmit_buf;\n\tunsigned int close_delay;\n\tunsigned int closing_wait;\n\tint drain_delay;\n\tstruct kref kref;\n\tvoid *client_data;\n};\n\nstruct tty_ldisc_ops {\n\tint magic;\n\tchar *name;\n\tint num;\n\tint flags;\n\tint (*open)(struct tty_struct *);\n\tvoid (*close)(struct tty_struct *);\n\tvoid (*flush_buffer)(struct tty_struct *);\n\tssize_t (*read)(struct tty_struct *, struct file *, unsigned char *, size_t);\n\tssize_t (*write)(struct tty_struct *, struct file *, const unsigned char *, size_t);\n\tint (*ioctl)(struct tty_struct *, struct file *, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct tty_struct *, struct file *, unsigned int, long unsigned int);\n\tvoid (*set_termios)(struct tty_struct *, struct ktermios *);\n\t__poll_t (*poll)(struct tty_struct *, struct file *, struct poll_table_struct *);\n\tint (*hangup)(struct tty_struct *);\n\tvoid (*receive_buf)(struct tty_struct *, const unsigned char *, char *, int);\n\tvoid (*write_wakeup)(struct tty_struct *);\n\tvoid (*dcd_change)(struct tty_struct *, unsigned int);\n\tint (*receive_buf2)(struct tty_struct *, const unsigned char *, char *, int);\n\tstruct module *owner;\n\tint refcount;\n};\n\nstruct tty_ldisc {\n\tstruct tty_ldisc_ops *ops;\n\tstruct tty_struct *tty;\n};\n\nstruct tty_port_operations {\n\tint (*carrier_raised)(struct tty_port *);\n\tvoid (*dtr_rts)(struct tty_port *, int);\n\tvoid (*shutdown)(struct tty_port *);\n\tint (*activate)(struct tty_port *, struct tty_struct *);\n\tvoid (*destruct)(struct tty_port *);\n};\n\nstruct tty_port_client_operations {\n\tint (*receive_buf)(struct tty_port *, const unsigned char *, const unsigned char *, size_t);\n\tvoid (*write_wakeup)(struct tty_port *);\n};\n\nstruct prot_inuse;\n\nstruct netns_core {\n\tstruct ctl_table_header *sysctl_hdr;\n\tint sysctl_somaxconn;\n\tint *sock_inuse;\n\tstruct prot_inuse *prot_inuse;\n};\n\nstruct tcp_mib;\n\nstruct ipstats_mib;\n\nstruct linux_mib;\n\nstruct udp_mib;\n\nstruct icmp_mib;\n\nstruct icmpmsg_mib;\n\nstruct icmpv6_mib;\n\nstruct icmpv6msg_mib;\n\nstruct netns_mib {\n\tstruct tcp_mib *tcp_statistics;\n\tstruct ipstats_mib *ip_statistics;\n\tstruct linux_mib *net_statistics;\n\tstruct udp_mib *udp_statistics;\n\tstruct udp_mib *udplite_statistics;\n\tstruct icmp_mib *icmp_statistics;\n\tstruct icmpmsg_mib *icmpmsg_statistics;\n\tstruct proc_dir_entry *proc_net_devsnmp6;\n\tstruct udp_mib *udp_stats_in6;\n\tstruct udp_mib *udplite_stats_in6;\n\tstruct ipstats_mib *ipv6_statistics;\n\tstruct icmpv6_mib *icmpv6_statistics;\n\tstruct icmpv6msg_mib *icmpv6msg_statistics;\n};\n\nstruct netns_packet {\n\tstruct mutex sklist_lock;\n\tstruct hlist_head sklist;\n};\n\nstruct netns_unix {\n\tint sysctl_max_dgram_qlen;\n\tstruct ctl_table_header *ctl;\n};\n\nstruct netns_nexthop {\n\tstruct rb_root rb_root;\n\tstruct hlist_head *devhash;\n\tunsigned int seq;\n\tu32 last_id_allocated;\n\tstruct atomic_notifier_head notifier_chain;\n};\n\nstruct local_ports {\n\tseqlock_t lock;\n\tint range[2];\n\tbool warned;\n};\n\nstruct inet_hashinfo;\n\nstruct inet_timewait_death_row {\n\tatomic_t tw_count;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct inet_hashinfo *hashinfo;\n\tint sysctl_max_tw_buckets;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ping_group_range {\n\tseqlock_t lock;\n\tkgid_t range[2];\n};\n\ntypedef struct {\n\tu64 key[2];\n} siphash_key_t;\n\nstruct ipv4_devconf;\n\nstruct ip_ra_chain;\n\nstruct fib_rules_ops;\n\nstruct fib_table;\n\nstruct inet_peer_base;\n\nstruct fqdir;\n\nstruct xt_table;\n\nstruct tcp_congestion_ops;\n\nstruct tcp_fastopen_context;\n\nstruct mr_table;\n\nstruct fib_notifier_ops;\n\nstruct netns_ipv4 {\n\tstruct ctl_table_header *forw_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *ipv4_hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *xfrm4_hdr;\n\tstruct ipv4_devconf *devconf_all;\n\tstruct ipv4_devconf *devconf_dflt;\n\tstruct ip_ra_chain *ra_chain;\n\tstruct mutex ra_mutex;\n\tstruct fib_rules_ops *rules_ops;\n\tbool fib_has_custom_rules;\n\tunsigned int fib_rules_require_fldissect;\n\tstruct fib_table *fib_main;\n\tstruct fib_table *fib_default;\n\tbool fib_has_custom_local_routes;\n\tstruct hlist_head *fib_table_hash;\n\tbool fib_offload_disabled;\n\tstruct sock *fibnl;\n\tstruct sock **icmp_sk;\n\tstruct sock *mc_autojoin_sk;\n\tstruct inet_peer_base *peers;\n\tstruct sock **tcp_sk;\n\tstruct fqdir *fqdir;\n\tstruct xt_table *iptable_filter;\n\tstruct xt_table *iptable_mangle;\n\tstruct xt_table *iptable_raw;\n\tstruct xt_table *arptable_filter;\n\tstruct xt_table *iptable_security;\n\tstruct xt_table *nat_table;\n\tint sysctl_icmp_echo_ignore_all;\n\tint sysctl_icmp_echo_ignore_broadcasts;\n\tint sysctl_icmp_ignore_bogus_error_responses;\n\tint sysctl_icmp_ratelimit;\n\tint sysctl_icmp_ratemask;\n\tint sysctl_icmp_errors_use_inbound_ifaddr;\n\tstruct local_ports ip_local_ports;\n\tint sysctl_tcp_ecn;\n\tint sysctl_tcp_ecn_fallback;\n\tint sysctl_ip_default_ttl;\n\tint sysctl_ip_no_pmtu_disc;\n\tint sysctl_ip_fwd_use_pmtu;\n\tint sysctl_ip_fwd_update_priority;\n\tint sysctl_ip_nonlocal_bind;\n\tint sysctl_ip_autobind_reuse;\n\tint sysctl_ip_dynaddr;\n\tint sysctl_ip_early_demux;\n\tint sysctl_tcp_early_demux;\n\tint sysctl_udp_early_demux;\n\tint sysctl_nexthop_compat_mode;\n\tint sysctl_fwmark_reflect;\n\tint sysctl_tcp_fwmark_accept;\n\tint sysctl_tcp_mtu_probing;\n\tint sysctl_tcp_mtu_probe_floor;\n\tint sysctl_tcp_base_mss;\n\tint sysctl_tcp_min_snd_mss;\n\tint sysctl_tcp_probe_threshold;\n\tu32 sysctl_tcp_probe_interval;\n\tint sysctl_tcp_keepalive_time;\n\tint sysctl_tcp_keepalive_probes;\n\tint sysctl_tcp_keepalive_intvl;\n\tint sysctl_tcp_syn_retries;\n\tint sysctl_tcp_synack_retries;\n\tint sysctl_tcp_syncookies;\n\tint sysctl_tcp_reordering;\n\tint sysctl_tcp_retries1;\n\tint sysctl_tcp_retries2;\n\tint sysctl_tcp_orphan_retries;\n\tint sysctl_tcp_fin_timeout;\n\tunsigned int sysctl_tcp_notsent_lowat;\n\tint sysctl_tcp_tw_reuse;\n\tint sysctl_tcp_sack;\n\tint sysctl_tcp_window_scaling;\n\tint sysctl_tcp_timestamps;\n\tint sysctl_tcp_early_retrans;\n\tint sysctl_tcp_recovery;\n\tint sysctl_tcp_thin_linear_timeouts;\n\tint sysctl_tcp_slow_start_after_idle;\n\tint sysctl_tcp_retrans_collapse;\n\tint sysctl_tcp_stdurg;\n\tint sysctl_tcp_rfc1337;\n\tint sysctl_tcp_abort_on_overflow;\n\tint sysctl_tcp_fack;\n\tint sysctl_tcp_max_reordering;\n\tint sysctl_tcp_dsack;\n\tint sysctl_tcp_app_win;\n\tint sysctl_tcp_adv_win_scale;\n\tint sysctl_tcp_frto;\n\tint sysctl_tcp_nometrics_save;\n\tint sysctl_tcp_no_ssthresh_metrics_save;\n\tint sysctl_tcp_moderate_rcvbuf;\n\tint sysctl_tcp_tso_win_divisor;\n\tint sysctl_tcp_workaround_signed_windows;\n\tint sysctl_tcp_limit_output_bytes;\n\tint sysctl_tcp_challenge_ack_limit;\n\tint sysctl_tcp_min_tso_segs;\n\tint sysctl_tcp_min_rtt_wlen;\n\tint sysctl_tcp_autocorking;\n\tint sysctl_tcp_invalid_ratelimit;\n\tint sysctl_tcp_pacing_ss_ratio;\n\tint sysctl_tcp_pacing_ca_ratio;\n\tint sysctl_tcp_wmem[3];\n\tint sysctl_tcp_rmem[3];\n\tint sysctl_tcp_comp_sack_nr;\n\tlong unsigned int sysctl_tcp_comp_sack_delay_ns;\n\tlong unsigned int sysctl_tcp_comp_sack_slack_ns;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct inet_timewait_death_row tcp_death_row;\n\tint sysctl_max_syn_backlog;\n\tint sysctl_tcp_fastopen;\n\tconst struct tcp_congestion_ops *tcp_congestion_control;\n\tstruct tcp_fastopen_context *tcp_fastopen_ctx;\n\tspinlock_t tcp_fastopen_ctx_lock;\n\tunsigned int sysctl_tcp_fastopen_blackhole_timeout;\n\tatomic_t tfo_active_disable_times;\n\tlong unsigned int tfo_active_disable_stamp;\n\tint sysctl_udp_wmem_min;\n\tint sysctl_udp_rmem_min;\n\tint sysctl_igmp_max_memberships;\n\tint sysctl_igmp_max_msf;\n\tint sysctl_igmp_llm_reports;\n\tint sysctl_igmp_qrv;\n\tstruct ping_group_range ping_group_range;\n\tatomic_t dev_addr_genid;\n\tlong unsigned int *sysctl_local_reserved_ports;\n\tint sysctl_ip_prot_sock;\n\tstruct mr_table *mrt;\n\tint sysctl_fib_multipath_use_neigh;\n\tint sysctl_fib_multipath_hash_policy;\n\tstruct fib_notifier_ops *notifier_ops;\n\tunsigned int fib_seq;\n\tstruct fib_notifier_ops *ipmr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tatomic_t rt_genid;\n\tsiphash_key_t ip_id_key;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netns_sysctl_ipv6 {\n\tstruct ctl_table_header *hdr;\n\tstruct ctl_table_header *route_hdr;\n\tstruct ctl_table_header *icmp_hdr;\n\tstruct ctl_table_header *frags_hdr;\n\tstruct ctl_table_header *xfrm6_hdr;\n\tint bindv6only;\n\tint flush_delay;\n\tint ip6_rt_max_size;\n\tint ip6_rt_gc_min_interval;\n\tint ip6_rt_gc_timeout;\n\tint ip6_rt_gc_interval;\n\tint ip6_rt_gc_elasticity;\n\tint ip6_rt_mtu_expires;\n\tint ip6_rt_min_advmss;\n\tint multipath_hash_policy;\n\tint flowlabel_consistency;\n\tint auto_flowlabels;\n\tint icmpv6_time;\n\tint icmpv6_echo_ignore_all;\n\tint icmpv6_echo_ignore_multicast;\n\tint icmpv6_echo_ignore_anycast;\n\tlong unsigned int icmpv6_ratemask[4];\n\tlong unsigned int *icmpv6_ratemask_ptr;\n\tint anycast_src_echo_reply;\n\tint ip_nonlocal_bind;\n\tint fwmark_reflect;\n\tint idgen_retries;\n\tint idgen_delay;\n\tint flowlabel_state_ranges;\n\tint flowlabel_reflect;\n\tint max_dst_opts_cnt;\n\tint max_hbh_opts_cnt;\n\tint max_dst_opts_len;\n\tint max_hbh_opts_len;\n\tint seg6_flowlabel;\n\tbool skip_notify_on_dev_down;\n};\n\nstruct neighbour;\n\nstruct dst_ops {\n\tshort unsigned int family;\n\tunsigned int gc_thresh;\n\tint (*gc)(struct dst_ops *);\n\tstruct dst_entry * (*check)(struct dst_entry *, __u32);\n\tunsigned int (*default_advmss)(const struct dst_entry *);\n\tunsigned int (*mtu)(const struct dst_entry *);\n\tu32 * (*cow_metrics)(struct dst_entry *, long unsigned int);\n\tvoid (*destroy)(struct dst_entry *);\n\tvoid (*ifdown)(struct dst_entry *, struct net_device *, int);\n\tstruct dst_entry * (*negative_advice)(struct dst_entry *);\n\tvoid (*link_failure)(struct sk_buff *);\n\tvoid (*update_pmtu)(struct dst_entry *, struct sock *, struct sk_buff *, u32, bool);\n\tvoid (*redirect)(struct dst_entry *, struct sock *, struct sk_buff *);\n\tint (*local_out)(struct net *, struct sock *, struct sk_buff *);\n\tstruct neighbour * (*neigh_lookup)(const struct dst_entry *, struct sk_buff *, const void *);\n\tvoid (*confirm_neigh)(const struct dst_entry *, const void *);\n\tstruct kmem_cache *kmem_cachep;\n\tstruct percpu_counter pcpuc_entries;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ipv6_devconf;\n\nstruct fib6_info;\n\nstruct rt6_info;\n\nstruct rt6_statistics;\n\nstruct fib6_table;\n\nstruct seg6_pernet_data;\n\nstruct netns_ipv6 {\n\tstruct netns_sysctl_ipv6 sysctl;\n\tstruct ipv6_devconf *devconf_all;\n\tstruct ipv6_devconf *devconf_dflt;\n\tstruct inet_peer_base *peers;\n\tstruct fqdir *fqdir;\n\tstruct xt_table *ip6table_filter;\n\tstruct xt_table *ip6table_mangle;\n\tstruct xt_table *ip6table_raw;\n\tstruct xt_table *ip6table_security;\n\tstruct xt_table *ip6table_nat;\n\tstruct fib6_info *fib6_null_entry;\n\tstruct rt6_info *ip6_null_entry;\n\tstruct rt6_statistics *rt6_stats;\n\tstruct timer_list ip6_fib_timer;\n\tstruct hlist_head *fib_table_hash;\n\tstruct fib6_table *fib6_main_tbl;\n\tstruct list_head fib6_walkers;\n\tlong: 64;\n\tlong: 64;\n\tstruct dst_ops ip6_dst_ops;\n\trwlock_t fib6_walker_lock;\n\tspinlock_t fib6_gc_lock;\n\tunsigned int ip6_rt_gc_expire;\n\tlong unsigned int ip6_rt_last_gc;\n\tunsigned int fib6_rules_require_fldissect;\n\tbool fib6_has_custom_rules;\n\tstruct rt6_info *ip6_prohibit_entry;\n\tstruct rt6_info *ip6_blk_hole_entry;\n\tstruct fib6_table *fib6_local_tbl;\n\tstruct fib_rules_ops *fib6_rules_ops;\n\tstruct sock **icmp_sk;\n\tstruct sock *ndisc_sk;\n\tstruct sock *tcp_sk;\n\tstruct sock *igmp_sk;\n\tstruct sock *mc_autojoin_sk;\n\tatomic_t dev_addr_genid;\n\tatomic_t fib6_sernum;\n\tstruct seg6_pernet_data *seg6_data;\n\tstruct fib_notifier_ops *notifier_ops;\n\tstruct fib_notifier_ops *ip6mr_notifier_ops;\n\tunsigned int ipmr_seq;\n\tstruct {\n\t\tstruct hlist_head head;\n\t\tspinlock_t lock;\n\t\tu32 seq;\n\t} ip6addrlbl_table;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct nf_queue_handler;\n\nstruct nf_logger;\n\nstruct nf_hook_entries;\n\nstruct netns_nf {\n\tstruct proc_dir_entry *proc_netfilter;\n\tconst struct nf_queue_handler *queue_handler;\n\tconst struct nf_logger *nf_loggers[13];\n\tstruct ctl_table_header *nf_log_dir_header;\n\tstruct nf_hook_entries *hooks_ipv4[5];\n\tstruct nf_hook_entries *hooks_ipv6[5];\n\tbool defrag_ipv4;\n\tbool defrag_ipv6;\n};\n\nstruct netns_xt {\n\tstruct list_head tables[13];\n\tbool notrack_deprecated_warning;\n\tbool clusterip_deprecated_warning;\n};\n\nstruct nf_ct_event_notifier;\n\nstruct nf_exp_event_notifier;\n\nstruct nf_generic_net {\n\tunsigned int timeout;\n};\n\nstruct nf_tcp_net {\n\tunsigned int timeouts[14];\n\tint tcp_loose;\n\tint tcp_be_liberal;\n\tint tcp_max_retrans;\n};\n\nstruct nf_udp_net {\n\tunsigned int timeouts[2];\n};\n\nstruct nf_icmp_net {\n\tunsigned int timeout;\n};\n\nstruct nf_dccp_net {\n\tint dccp_loose;\n\tunsigned int dccp_timeout[10];\n};\n\nstruct nf_sctp_net {\n\tunsigned int timeouts[10];\n};\n\nstruct nf_ip_net {\n\tstruct nf_generic_net generic;\n\tstruct nf_tcp_net tcp;\n\tstruct nf_udp_net udp;\n\tstruct nf_icmp_net icmp;\n\tstruct nf_icmp_net icmpv6;\n\tstruct nf_dccp_net dccp;\n\tstruct nf_sctp_net sctp;\n};\n\nstruct ct_pcpu;\n\nstruct ip_conntrack_stat;\n\nstruct netns_ct {\n\tatomic_t count;\n\tunsigned int expect_count;\n\tbool auto_assign_helper_warned;\n\tstruct ctl_table_header *sysctl_header;\n\tunsigned int sysctl_log_invalid;\n\tint sysctl_events;\n\tint sysctl_acct;\n\tint sysctl_auto_assign_helper;\n\tint sysctl_tstamp;\n\tint sysctl_checksum;\n\tstruct ct_pcpu *pcpu_lists;\n\tstruct ip_conntrack_stat *stat;\n\tstruct nf_ct_event_notifier *nf_conntrack_event_cb;\n\tstruct nf_exp_event_notifier *nf_expect_event_cb;\n\tstruct nf_ip_net nf_ct_proto;\n};\n\nstruct netns_nf_frag {\n\tstruct fqdir *fqdir;\n};\n\nstruct netns_bpf {\n\tstruct bpf_prog_array *run_array[1];\n\tstruct bpf_prog *progs[1];\n\tstruct list_head links[1];\n};\n\nstruct xfrm_policy_hash {\n\tstruct hlist_head *table;\n\tunsigned int hmask;\n\tu8 dbits4;\n\tu8 sbits4;\n\tu8 dbits6;\n\tu8 sbits6;\n};\n\nstruct xfrm_policy_hthresh {\n\tstruct work_struct work;\n\tseqlock_t lock;\n\tu8 lbits4;\n\tu8 rbits4;\n\tu8 lbits6;\n\tu8 rbits6;\n};\n\nstruct netns_xfrm {\n\tstruct list_head state_all;\n\tstruct hlist_head *state_bydst;\n\tstruct hlist_head *state_bysrc;\n\tstruct hlist_head *state_byspi;\n\tunsigned int state_hmask;\n\tunsigned int state_num;\n\tstruct work_struct state_hash_work;\n\tstruct list_head policy_all;\n\tstruct hlist_head *policy_byidx;\n\tunsigned int policy_idx_hmask;\n\tstruct hlist_head policy_inexact[3];\n\tstruct xfrm_policy_hash policy_bydst[3];\n\tunsigned int policy_count[6];\n\tstruct work_struct policy_hash_work;\n\tstruct xfrm_policy_hthresh policy_hthresh;\n\tstruct list_head inexact_bins;\n\tstruct sock *nlsk;\n\tstruct sock *nlsk_stash;\n\tu32 sysctl_aevent_etime;\n\tu32 sysctl_aevent_rseqth;\n\tint sysctl_larval_drop;\n\tu32 sysctl_acq_expires;\n\tstruct ctl_table_header *sysctl_hdr;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct dst_ops xfrm4_dst_ops;\n\tstruct dst_ops xfrm6_dst_ops;\n\tspinlock_t xfrm_state_lock;\n\tspinlock_t xfrm_policy_lock;\n\tstruct mutex xfrm_cfg_mutex;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct netns_xdp {\n\tstruct mutex lock;\n\tstruct hlist_head list;\n};\n\nstruct uevent_sock;\n\nstruct net_generic;\n\nstruct net {\n\trefcount_t passive;\n\trefcount_t count;\n\tspinlock_t rules_mod_lock;\n\tunsigned int dev_unreg_count;\n\tunsigned int dev_base_seq;\n\tint ifindex;\n\tspinlock_t nsid_lock;\n\tatomic_t fnhe_genid;\n\tstruct list_head list;\n\tstruct list_head exit_list;\n\tstruct llist_node cleanup_list;\n\tstruct key_tag *key_domain;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct idr netns_ids;\n\tstruct ns_common ns;\n\tstruct list_head dev_base_head;\n\tstruct proc_dir_entry *proc_net;\n\tstruct proc_dir_entry *proc_net_stat;\n\tstruct ctl_table_set sysctls;\n\tstruct sock *rtnl;\n\tstruct sock *genl_sock;\n\tstruct uevent_sock *uevent_sock;\n\tstruct hlist_head *dev_name_head;\n\tstruct hlist_head *dev_index_head;\n\tstruct raw_notifier_head netdev_chain;\n\tu32 hash_mix;\n\tstruct net_device *loopback_dev;\n\tstruct list_head rules_ops;\n\tstruct netns_core core;\n\tstruct netns_mib mib;\n\tstruct netns_packet packet;\n\tstruct netns_unix unx;\n\tstruct netns_nexthop nexthop;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct netns_ipv4 ipv4;\n\tstruct netns_ipv6 ipv6;\n\tstruct netns_nf nf;\n\tstruct netns_xt xt;\n\tstruct netns_ct ct;\n\tstruct netns_nf_frag nf_frag;\n\tstruct ctl_table_header *nf_frag_frags_hdr;\n\tstruct sock *nfnl;\n\tstruct sock *nfnl_stash;\n\tstruct net_generic *gen;\n\tstruct netns_bpf bpf;\n\tlong: 64;\n\tstruct netns_xfrm xfrm;\n\tatomic64_t net_cookie;\n\tstruct netns_xdp xdp;\n\tstruct sock *diag_nlsk;\n\tlong: 64;\n};\n\ntypedef struct {\n\tlocal64_t v;\n} u64_stats_t;\n\nstruct bpf_offloaded_map;\n\nstruct bpf_map_dev_ops {\n\tint (*map_get_next_key)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_lookup_elem)(struct bpf_offloaded_map *, void *, void *);\n\tint (*map_update_elem)(struct bpf_offloaded_map *, void *, void *, u64);\n\tint (*map_delete_elem)(struct bpf_offloaded_map *, void *);\n};\n\nstruct bpf_offloaded_map {\n\tstruct bpf_map map;\n\tstruct net_device *netdev;\n\tconst struct bpf_map_dev_ops *dev_ops;\n\tvoid *dev_priv;\n\tstruct list_head offloads;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct net_device_stats {\n\tlong unsigned int rx_packets;\n\tlong unsigned int tx_packets;\n\tlong unsigned int rx_bytes;\n\tlong unsigned int tx_bytes;\n\tlong unsigned int rx_errors;\n\tlong unsigned int tx_errors;\n\tlong unsigned int rx_dropped;\n\tlong unsigned int tx_dropped;\n\tlong unsigned int multicast;\n\tlong unsigned int collisions;\n\tlong unsigned int rx_length_errors;\n\tlong unsigned int rx_over_errors;\n\tlong unsigned int rx_crc_errors;\n\tlong unsigned int rx_frame_errors;\n\tlong unsigned int rx_fifo_errors;\n\tlong unsigned int rx_missed_errors;\n\tlong unsigned int tx_aborted_errors;\n\tlong unsigned int tx_carrier_errors;\n\tlong unsigned int tx_fifo_errors;\n\tlong unsigned int tx_heartbeat_errors;\n\tlong unsigned int tx_window_errors;\n\tlong unsigned int rx_compressed;\n\tlong unsigned int tx_compressed;\n};\n\nstruct netdev_hw_addr_list {\n\tstruct list_head list;\n\tint count;\n};\n\nenum rx_handler_result {\n\tRX_HANDLER_CONSUMED = 0,\n\tRX_HANDLER_ANOTHER = 1,\n\tRX_HANDLER_EXACT = 2,\n\tRX_HANDLER_PASS = 3,\n};\n\ntypedef enum rx_handler_result rx_handler_result_t;\n\ntypedef rx_handler_result_t rx_handler_func_t(struct sk_buff **);\n\nstruct pcpu_dstats;\n\nstruct netdev_tc_txq {\n\tu16 count;\n\tu16 offset;\n};\n\nstruct sfp_bus;\n\nstruct netdev_name_node;\n\nstruct dev_ifalias;\n\nstruct net_device_ops;\n\nstruct ethtool_ops;\n\nstruct ndisc_ops;\n\nstruct header_ops;\n\nstruct in_device;\n\nstruct inet6_dev;\n\nstruct wireless_dev;\n\nstruct wpan_dev;\n\nstruct netdev_rx_queue;\n\nstruct mini_Qdisc;\n\nstruct netdev_queue;\n\nstruct cpu_rmap;\n\nstruct Qdisc;\n\nstruct xdp_dev_bulk_queue;\n\nstruct xps_dev_maps;\n\nstruct netpoll_info;\n\nstruct pcpu_lstats;\n\nstruct pcpu_sw_netstats;\n\nstruct rtnl_link_ops;\n\nstruct phy_device;\n\nstruct net_device {\n\tchar name[16];\n\tstruct netdev_name_node *name_node;\n\tstruct dev_ifalias *ifalias;\n\tlong unsigned int mem_end;\n\tlong unsigned int mem_start;\n\tlong unsigned int base_addr;\n\tint irq;\n\tlong unsigned int state;\n\tstruct list_head dev_list;\n\tstruct list_head napi_list;\n\tstruct list_head unreg_list;\n\tstruct list_head close_list;\n\tstruct list_head ptype_all;\n\tstruct list_head ptype_specific;\n\tstruct {\n\t\tstruct list_head upper;\n\t\tstruct list_head lower;\n\t} adj_list;\n\tnetdev_features_t features;\n\tnetdev_features_t hw_features;\n\tnetdev_features_t wanted_features;\n\tnetdev_features_t vlan_features;\n\tnetdev_features_t hw_enc_features;\n\tnetdev_features_t mpls_features;\n\tnetdev_features_t gso_partial_features;\n\tint ifindex;\n\tint group;\n\tstruct net_device_stats stats;\n\tatomic_long_t rx_dropped;\n\tatomic_long_t tx_dropped;\n\tatomic_long_t rx_nohandler;\n\tatomic_t carrier_up_count;\n\tatomic_t carrier_down_count;\n\tconst struct net_device_ops *netdev_ops;\n\tconst struct ethtool_ops *ethtool_ops;\n\tconst struct ndisc_ops *ndisc_ops;\n\tconst struct header_ops *header_ops;\n\tunsigned int flags;\n\tunsigned int priv_flags;\n\tshort unsigned int gflags;\n\tshort unsigned int padded;\n\tunsigned char operstate;\n\tunsigned char link_mode;\n\tunsigned char if_port;\n\tunsigned char dma;\n\tunsigned int mtu;\n\tunsigned int min_mtu;\n\tunsigned int max_mtu;\n\tshort unsigned int type;\n\tshort unsigned int hard_header_len;\n\tunsigned char min_header_len;\n\tshort unsigned int needed_headroom;\n\tshort unsigned int needed_tailroom;\n\tunsigned char perm_addr[32];\n\tunsigned char addr_assign_type;\n\tunsigned char addr_len;\n\tunsigned char upper_level;\n\tunsigned char lower_level;\n\tshort unsigned int neigh_priv_len;\n\tshort unsigned int dev_id;\n\tshort unsigned int dev_port;\n\tspinlock_t addr_list_lock;\n\tunsigned char name_assign_type;\n\tbool uc_promisc;\n\tstruct netdev_hw_addr_list uc;\n\tstruct netdev_hw_addr_list mc;\n\tstruct netdev_hw_addr_list dev_addrs;\n\tstruct kset *queues_kset;\n\tunsigned int promiscuity;\n\tunsigned int allmulti;\n\tstruct in_device *ip_ptr;\n\tstruct inet6_dev *ip6_ptr;\n\tstruct wireless_dev *ieee80211_ptr;\n\tstruct wpan_dev *ieee802154_ptr;\n\tunsigned char *dev_addr;\n\tstruct netdev_rx_queue *_rx;\n\tunsigned int num_rx_queues;\n\tunsigned int real_num_rx_queues;\n\tstruct bpf_prog *xdp_prog;\n\tlong unsigned int gro_flush_timeout;\n\tint napi_defer_hard_irqs;\n\trx_handler_func_t *rx_handler;\n\tvoid *rx_handler_data;\n\tstruct mini_Qdisc *miniq_ingress;\n\tstruct netdev_queue *ingress_queue;\n\tstruct nf_hook_entries *nf_hooks_ingress;\n\tunsigned char broadcast[32];\n\tstruct cpu_rmap *rx_cpu_rmap;\n\tstruct hlist_node index_hlist;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct netdev_queue *_tx;\n\tunsigned int num_tx_queues;\n\tunsigned int real_num_tx_queues;\n\tstruct Qdisc *qdisc;\n\tunsigned int tx_queue_len;\n\tspinlock_t tx_global_lock;\n\tstruct xdp_dev_bulk_queue *xdp_bulkq;\n\tstruct xps_dev_maps *xps_cpus_map;\n\tstruct xps_dev_maps *xps_rxqs_map;\n\tstruct mini_Qdisc *miniq_egress;\n\tstruct hlist_head qdisc_hash[16];\n\tstruct timer_list watchdog_timer;\n\tint watchdog_timeo;\n\tstruct list_head todo_list;\n\tint *pcpu_refcnt;\n\tstruct list_head link_watch_list;\n\tenum {\n\t\tNETREG_UNINITIALIZED = 0,\n\t\tNETREG_REGISTERED = 1,\n\t\tNETREG_UNREGISTERING = 2,\n\t\tNETREG_UNREGISTERED = 3,\n\t\tNETREG_RELEASED = 4,\n\t\tNETREG_DUMMY = 5,\n\t} reg_state: 8;\n\tbool dismantle;\n\tenum {\n\t\tRTNL_LINK_INITIALIZED = 0,\n\t\tRTNL_LINK_INITIALIZING = 1,\n\t} rtnl_link_state: 16;\n\tbool needs_free_netdev;\n\tvoid (*priv_destructor)(struct net_device *);\n\tstruct netpoll_info *npinfo;\n\tpossible_net_t nd_net;\n\tunion {\n\t\tvoid *ml_priv;\n\t\tstruct pcpu_lstats *lstats;\n\t\tstruct pcpu_sw_netstats *tstats;\n\t\tstruct pcpu_dstats *dstats;\n\t};\n\tstruct device dev;\n\tconst struct attribute_group *sysfs_groups[4];\n\tconst struct attribute_group *sysfs_rx_queue_group;\n\tconst struct rtnl_link_ops *rtnl_link_ops;\n\tunsigned int gso_max_size;\n\tu16 gso_max_segs;\n\ts16 num_tc;\n\tstruct netdev_tc_txq tc_to_txq[16];\n\tu8 prio_tc_map[16];\n\tstruct phy_device *phydev;\n\tstruct sfp_bus *sfp_bus;\n\tstruct lock_class_key *qdisc_tx_busylock;\n\tstruct lock_class_key *qdisc_running_key;\n\tbool proto_down;\n\tunsigned int wol_enabled: 1;\n\tstruct list_head net_notifier_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_dispatcher_prog {\n\tstruct bpf_prog *prog;\n\trefcount_t users;\n};\n\nstruct bpf_dispatcher {\n\tstruct mutex mutex;\n\tvoid *func;\n\tstruct bpf_dispatcher_prog progs[48];\n\tint num_progs;\n\tvoid *image;\n\tu32 image_off;\n\tstruct bpf_ksym ksym;\n};\n\ntypedef unsigned int sk_buff_data_t;\n\nstruct skb_ext;\n\nstruct sk_buff {\n\tunion {\n\t\tstruct {\n\t\t\tstruct sk_buff *next;\n\t\t\tstruct sk_buff *prev;\n\t\t\tunion {\n\t\t\t\tstruct net_device *dev;\n\t\t\t\tlong unsigned int dev_scratch;\n\t\t\t};\n\t\t};\n\t\tstruct rb_node rbnode;\n\t\tstruct list_head list;\n\t};\n\tunion {\n\t\tstruct sock *sk;\n\t\tint ip_defrag_offset;\n\t};\n\tunion {\n\t\tktime_t tstamp;\n\t\tu64 skb_mstamp_ns;\n\t};\n\tchar cb[48];\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int _skb_refdst;\n\t\t\tvoid (*destructor)(struct sk_buff *);\n\t\t};\n\t\tstruct list_head tcp_tsorted_anchor;\n\t};\n\tlong unsigned int _nfct;\n\tunsigned int len;\n\tunsigned int data_len;\n\t__u16 mac_len;\n\t__u16 hdr_len;\n\t__u16 queue_mapping;\n\t__u8 __cloned_offset[0];\n\t__u8 cloned: 1;\n\t__u8 nohdr: 1;\n\t__u8 fclone: 2;\n\t__u8 peeked: 1;\n\t__u8 head_frag: 1;\n\t__u8 pfmemalloc: 1;\n\t__u8 active_extensions;\n\t__u32 headers_start[0];\n\t__u8 __pkt_type_offset[0];\n\t__u8 pkt_type: 3;\n\t__u8 ignore_df: 1;\n\t__u8 nf_trace: 1;\n\t__u8 ip_summed: 2;\n\t__u8 ooo_okay: 1;\n\t__u8 l4_hash: 1;\n\t__u8 sw_hash: 1;\n\t__u8 wifi_acked_valid: 1;\n\t__u8 wifi_acked: 1;\n\t__u8 no_fcs: 1;\n\t__u8 encapsulation: 1;\n\t__u8 encap_hdr_csum: 1;\n\t__u8 csum_valid: 1;\n\t__u8 __pkt_vlan_present_offset[0];\n\t__u8 vlan_present: 1;\n\t__u8 csum_complete_sw: 1;\n\t__u8 csum_level: 2;\n\t__u8 csum_not_inet: 1;\n\t__u8 dst_pending_confirm: 1;\n\t__u8 ndisc_nodetype: 2;\n\t__u8 ipvs_property: 1;\n\t__u8 inner_protocol_type: 1;\n\t__u8 remcsum_offload: 1;\n\t__u8 tc_skip_classify: 1;\n\t__u8 tc_at_ingress: 1;\n\t__u16 tc_index;\n\tunion {\n\t\t__wsum csum;\n\t\tstruct {\n\t\t\t__u16 csum_start;\n\t\t\t__u16 csum_offset;\n\t\t};\n\t};\n\t__u32 priority;\n\tint skb_iif;\n\t__u32 hash;\n\t__be16 vlan_proto;\n\t__u16 vlan_tci;\n\tunion {\n\t\tunsigned int napi_id;\n\t\tunsigned int sender_cpu;\n\t};\n\t__u32 secmark;\n\tunion {\n\t\t__u32 mark;\n\t\t__u32 reserved_tailroom;\n\t};\n\tunion {\n\t\t__be16 inner_protocol;\n\t\t__u8 inner_ipproto;\n\t};\n\t__u16 inner_transport_header;\n\t__u16 inner_network_header;\n\t__u16 inner_mac_header;\n\t__be16 protocol;\n\t__u16 transport_header;\n\t__u16 network_header;\n\t__u16 mac_header;\n\t__u32 headers_end[0];\n\tsk_buff_data_t tail;\n\tsk_buff_data_t end;\n\tunsigned char *head;\n\tunsigned char *data;\n\tunsigned int truesize;\n\trefcount_t users;\n\tstruct skb_ext *extensions;\n};\n\nstruct sg_table {\n\tstruct scatterlist *sgl;\n\tunsigned int nents;\n\tunsigned int orig_nents;\n};\n\ntypedef int suspend_state_t;\n\nenum suspend_stat_step {\n\tSUSPEND_FREEZE = 1,\n\tSUSPEND_PREPARE = 2,\n\tSUSPEND_SUSPEND = 3,\n\tSUSPEND_SUSPEND_LATE = 4,\n\tSUSPEND_SUSPEND_NOIRQ = 5,\n\tSUSPEND_RESUME_NOIRQ = 6,\n\tSUSPEND_RESUME_EARLY = 7,\n\tSUSPEND_RESUME = 8,\n};\n\nstruct suspend_stats {\n\tint success;\n\tint fail;\n\tint failed_freeze;\n\tint failed_prepare;\n\tint failed_suspend;\n\tint failed_suspend_late;\n\tint failed_suspend_noirq;\n\tint failed_resume;\n\tint failed_resume_early;\n\tint failed_resume_noirq;\n\tint last_failed_dev;\n\tchar failed_devs[80];\n\tint last_failed_errno;\n\tint errno[2];\n\tint last_failed_step;\n\tenum suspend_stat_step failed_steps[2];\n};\n\nenum s2idle_states {\n\tS2IDLE_STATE_NONE = 0,\n\tS2IDLE_STATE_ENTER = 1,\n\tS2IDLE_STATE_WAKE = 2,\n};\n\nstruct pbe {\n\tvoid *address;\n\tvoid *orig_address;\n\tstruct pbe *next;\n};\n\nenum {\n\tRoot_NFS = 255,\n\tRoot_CIFS = 254,\n\tRoot_RAM0 = 1048576,\n\tRoot_RAM1 = 1048577,\n\tRoot_FD0 = 2097152,\n\tRoot_HDA1 = 3145729,\n\tRoot_HDA2 = 3145730,\n\tRoot_SDA1 = 8388609,\n\tRoot_SDA2 = 8388610,\n\tRoot_HDC1 = 23068673,\n\tRoot_SR0 = 11534336,\n};\n\nstruct xdr_buf {\n\tstruct kvec head[1];\n\tstruct kvec tail[1];\n\tstruct bio_vec *bvec;\n\tstruct page **pages;\n\tunsigned int page_base;\n\tunsigned int page_len;\n\tunsigned int flags;\n\tunsigned int buflen;\n\tunsigned int len;\n};\n\nstruct rpc_rqst;\n\nstruct xdr_stream {\n\t__be32 *p;\n\tstruct xdr_buf *buf;\n\t__be32 *end;\n\tstruct kvec *iov;\n\tstruct kvec scratch;\n\tstruct page **page_ptr;\n\tunsigned int nwords;\n\tstruct rpc_rqst *rqst;\n};\n\nstruct rpc_xprt;\n\nstruct rpc_task;\n\nstruct rpc_cred;\n\nstruct rpc_rqst {\n\tstruct rpc_xprt *rq_xprt;\n\tstruct xdr_buf rq_snd_buf;\n\tstruct xdr_buf rq_rcv_buf;\n\tstruct rpc_task *rq_task;\n\tstruct rpc_cred *rq_cred;\n\t__be32 rq_xid;\n\tint rq_cong;\n\tu32 rq_seqno;\n\tint rq_enc_pages_num;\n\tstruct page **rq_enc_pages;\n\tvoid (*rq_release_snd_buf)(struct rpc_rqst *);\n\tunion {\n\t\tstruct list_head rq_list;\n\t\tstruct rb_node rq_recv;\n\t};\n\tstruct list_head rq_xmit;\n\tstruct list_head rq_xmit2;\n\tvoid *rq_buffer;\n\tsize_t rq_callsize;\n\tvoid *rq_rbuffer;\n\tsize_t rq_rcvsize;\n\tsize_t rq_xmit_bytes_sent;\n\tsize_t rq_reply_bytes_recvd;\n\tstruct xdr_buf rq_private_buf;\n\tlong unsigned int rq_majortimeo;\n\tlong unsigned int rq_timeout;\n\tktime_t rq_rtt;\n\tunsigned int rq_retries;\n\tunsigned int rq_connect_cookie;\n\tatomic_t rq_pin;\n\tu32 rq_bytes_sent;\n\tktime_t rq_xtime;\n\tint rq_ntrans;\n};\n\ntypedef void (*kxdreproc_t)(struct rpc_rqst *, struct xdr_stream *, const void *);\n\ntypedef int (*kxdrdproc_t)(struct rpc_rqst *, struct xdr_stream *, void *);\n\nstruct rpc_procinfo;\n\nstruct rpc_message {\n\tconst struct rpc_procinfo *rpc_proc;\n\tvoid *rpc_argp;\n\tvoid *rpc_resp;\n\tconst struct cred *rpc_cred;\n};\n\nstruct rpc_procinfo {\n\tu32 p_proc;\n\tkxdreproc_t p_encode;\n\tkxdrdproc_t p_decode;\n\tunsigned int p_arglen;\n\tunsigned int p_replen;\n\tunsigned int p_timer;\n\tu32 p_statidx;\n\tconst char *p_name;\n};\n\nstruct rpc_wait {\n\tstruct list_head list;\n\tstruct list_head links;\n\tstruct list_head timer_list;\n};\n\nstruct rpc_wait_queue;\n\nstruct rpc_call_ops;\n\nstruct rpc_clnt;\n\nstruct rpc_task {\n\tatomic_t tk_count;\n\tint tk_status;\n\tstruct list_head tk_task;\n\tvoid (*tk_callback)(struct rpc_task *);\n\tvoid (*tk_action)(struct rpc_task *);\n\tlong unsigned int tk_timeout;\n\tlong unsigned int tk_runstate;\n\tstruct rpc_wait_queue *tk_waitqueue;\n\tunion {\n\t\tstruct work_struct tk_work;\n\t\tstruct rpc_wait tk_wait;\n\t} u;\n\tint tk_rpc_status;\n\tstruct rpc_message tk_msg;\n\tvoid *tk_calldata;\n\tconst struct rpc_call_ops *tk_ops;\n\tstruct rpc_clnt *tk_client;\n\tstruct rpc_xprt *tk_xprt;\n\tstruct rpc_cred *tk_op_cred;\n\tstruct rpc_rqst *tk_rqstp;\n\tstruct workqueue_struct *tk_workqueue;\n\tktime_t tk_start;\n\tpid_t tk_owner;\n\tshort unsigned int tk_flags;\n\tshort unsigned int tk_timeouts;\n\tshort unsigned int tk_pid;\n\tunsigned char tk_priority: 2;\n\tunsigned char tk_garb_retry: 2;\n\tunsigned char tk_cred_retry: 2;\n\tunsigned char tk_rebind_retry: 2;\n};\n\nstruct rpc_timer {\n\tstruct list_head list;\n\tlong unsigned int expires;\n\tstruct delayed_work dwork;\n};\n\nstruct rpc_wait_queue {\n\tspinlock_t lock;\n\tstruct list_head tasks[4];\n\tunsigned char maxpriority;\n\tunsigned char priority;\n\tunsigned char nr;\n\tshort unsigned int qlen;\n\tstruct rpc_timer timer_list;\n\tconst char *name;\n};\n\nstruct rpc_call_ops {\n\tvoid (*rpc_call_prepare)(struct rpc_task *, void *);\n\tvoid (*rpc_call_done)(struct rpc_task *, void *);\n\tvoid (*rpc_count_stats)(struct rpc_task *, void *);\n\tvoid (*rpc_release)(void *);\n};\n\nstruct rpc_pipe_dir_head {\n\tstruct list_head pdh_entries;\n\tstruct dentry *pdh_dentry;\n};\n\nstruct rpc_rtt {\n\tlong unsigned int timeo;\n\tlong unsigned int srtt[5];\n\tlong unsigned int sdrtt[5];\n\tint ntimeouts[5];\n};\n\nstruct rpc_timeout {\n\tlong unsigned int to_initval;\n\tlong unsigned int to_maxval;\n\tlong unsigned int to_increment;\n\tunsigned int to_retries;\n\tunsigned char to_exponential;\n};\n\nstruct rpc_xprt_switch;\n\nstruct rpc_xprt_iter_ops;\n\nstruct rpc_xprt_iter {\n\tstruct rpc_xprt_switch *xpi_xpswitch;\n\tstruct rpc_xprt *xpi_cursor;\n\tconst struct rpc_xprt_iter_ops *xpi_ops;\n};\n\nstruct rpc_auth;\n\nstruct rpc_stat;\n\nstruct rpc_iostats;\n\nstruct rpc_program;\n\nstruct rpc_clnt {\n\tatomic_t cl_count;\n\tunsigned int cl_clid;\n\tstruct list_head cl_clients;\n\tstruct list_head cl_tasks;\n\tspinlock_t cl_lock;\n\tstruct rpc_xprt *cl_xprt;\n\tconst struct rpc_procinfo *cl_procinfo;\n\tu32 cl_prog;\n\tu32 cl_vers;\n\tu32 cl_maxproc;\n\tstruct rpc_auth *cl_auth;\n\tstruct rpc_stat *cl_stats;\n\tstruct rpc_iostats *cl_metrics;\n\tunsigned int cl_softrtry: 1;\n\tunsigned int cl_softerr: 1;\n\tunsigned int cl_discrtry: 1;\n\tunsigned int cl_noretranstimeo: 1;\n\tunsigned int cl_autobind: 1;\n\tunsigned int cl_chatty: 1;\n\tstruct rpc_rtt *cl_rtt;\n\tconst struct rpc_timeout *cl_timeout;\n\tatomic_t cl_swapper;\n\tint cl_nodelen;\n\tchar cl_nodename[65];\n\tstruct rpc_pipe_dir_head cl_pipedir_objects;\n\tstruct rpc_clnt *cl_parent;\n\tstruct rpc_rtt cl_rtt_default;\n\tstruct rpc_timeout cl_timeout_default;\n\tconst struct rpc_program *cl_program;\n\tconst char *cl_principal;\n\tunion {\n\t\tstruct rpc_xprt_iter cl_xpi;\n\t\tstruct work_struct cl_work;\n\t};\n\tconst struct cred *cl_cred;\n};\n\nstruct rpc_xprt_ops;\n\nstruct svc_xprt;\n\nstruct rpc_xprt {\n\tstruct kref kref;\n\tconst struct rpc_xprt_ops *ops;\n\tconst struct rpc_timeout *timeout;\n\tstruct __kernel_sockaddr_storage addr;\n\tsize_t addrlen;\n\tint prot;\n\tlong unsigned int cong;\n\tlong unsigned int cwnd;\n\tsize_t max_payload;\n\tstruct rpc_wait_queue binding;\n\tstruct rpc_wait_queue sending;\n\tstruct rpc_wait_queue pending;\n\tstruct rpc_wait_queue backlog;\n\tstruct list_head free;\n\tunsigned int max_reqs;\n\tunsigned int min_reqs;\n\tunsigned int num_reqs;\n\tlong unsigned int state;\n\tunsigned char resvport: 1;\n\tunsigned char reuseport: 1;\n\tatomic_t swapper;\n\tunsigned int bind_index;\n\tstruct list_head xprt_switch;\n\tlong unsigned int bind_timeout;\n\tlong unsigned int reestablish_timeout;\n\tunsigned int connect_cookie;\n\tstruct work_struct task_cleanup;\n\tstruct timer_list timer;\n\tlong unsigned int last_used;\n\tlong unsigned int idle_timeout;\n\tlong unsigned int connect_timeout;\n\tlong unsigned int max_reconnect_timeout;\n\tatomic_long_t queuelen;\n\tspinlock_t transport_lock;\n\tspinlock_t reserve_lock;\n\tspinlock_t queue_lock;\n\tu32 xid;\n\tstruct rpc_task *snd_task;\n\tstruct list_head xmit_queue;\n\tstruct svc_xprt *bc_xprt;\n\tstruct rb_root recv_queue;\n\tstruct {\n\t\tlong unsigned int bind_count;\n\t\tlong unsigned int connect_count;\n\t\tlong unsigned int connect_start;\n\t\tlong unsigned int connect_time;\n\t\tlong unsigned int sends;\n\t\tlong unsigned int recvs;\n\t\tlong unsigned int bad_xids;\n\t\tlong unsigned int max_slots;\n\t\tlong long unsigned int req_u;\n\t\tlong long unsigned int bklog_u;\n\t\tlong long unsigned int sending_u;\n\t\tlong long unsigned int pending_u;\n\t} stat;\n\tstruct net *xprt_net;\n\tconst char *servername;\n\tconst char *address_strings[6];\n\tstruct callback_head rcu;\n};\n\nstruct rpc_credops;\n\nstruct rpc_cred {\n\tstruct hlist_node cr_hash;\n\tstruct list_head cr_lru;\n\tstruct callback_head cr_rcu;\n\tstruct rpc_auth *cr_auth;\n\tconst struct rpc_credops *cr_ops;\n\tlong unsigned int cr_expire;\n\tlong unsigned int cr_flags;\n\trefcount_t cr_count;\n\tconst struct cred *cr_cred;\n};\n\ntypedef u32 rpc_authflavor_t;\n\nstruct ethhdr {\n\tunsigned char h_dest[6];\n\tunsigned char h_source[6];\n\t__be16 h_proto;\n};\n\nstruct flow_dissector {\n\tunsigned int used_keys;\n\tshort unsigned int offset[27];\n};\n\nstruct flowi_tunnel {\n\t__be64 tun_id;\n};\n\nstruct flowi_common {\n\tint flowic_oif;\n\tint flowic_iif;\n\t__u32 flowic_mark;\n\t__u8 flowic_tos;\n\t__u8 flowic_scope;\n\t__u8 flowic_proto;\n\t__u8 flowic_flags;\n\t__u32 flowic_secid;\n\tkuid_t flowic_uid;\n\tstruct flowi_tunnel flowic_tun_key;\n\t__u32 flowic_multipath_hash;\n};\n\nunion flowi_uli {\n\tstruct {\n\t\t__be16 dport;\n\t\t__be16 sport;\n\t} ports;\n\tstruct {\n\t\t__u8 type;\n\t\t__u8 code;\n\t} icmpt;\n\tstruct {\n\t\t__le16 dport;\n\t\t__le16 sport;\n\t} dnports;\n\t__be32 spi;\n\t__be32 gre_key;\n\tstruct {\n\t\t__u8 type;\n\t} mht;\n};\n\nstruct flowi4 {\n\tstruct flowi_common __fl_common;\n\t__be32 saddr;\n\t__be32 daddr;\n\tunion flowi_uli uli;\n};\n\nstruct flowi6 {\n\tstruct flowi_common __fl_common;\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\t__be32 flowlabel;\n\tunion flowi_uli uli;\n\t__u32 mp_hash;\n};\n\nstruct flowidn {\n\tstruct flowi_common __fl_common;\n\t__le16 daddr;\n\t__le16 saddr;\n\tunion flowi_uli uli;\n};\n\nstruct flowi {\n\tunion {\n\t\tstruct flowi_common __fl_common;\n\t\tstruct flowi4 ip4;\n\t\tstruct flowi6 ip6;\n\t\tstruct flowidn dn;\n\t} u;\n};\n\nstruct ipstats_mib {\n\tu64 mibs[37];\n\tstruct u64_stats_sync syncp;\n};\n\nstruct icmp_mib {\n\tlong unsigned int mibs[28];\n};\n\nstruct icmpmsg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6_mib {\n\tlong unsigned int mibs[6];\n};\n\nstruct icmpv6_mib_device {\n\tatomic_long_t mibs[6];\n};\n\nstruct icmpv6msg_mib {\n\tatomic_long_t mibs[512];\n};\n\nstruct icmpv6msg_mib_device {\n\tatomic_long_t mibs[512];\n};\n\nstruct tcp_mib {\n\tlong unsigned int mibs[16];\n};\n\nstruct udp_mib {\n\tlong unsigned int mibs[9];\n};\n\nstruct linux_mib {\n\tlong unsigned int mibs[122];\n};\n\nstruct inet_frags;\n\nstruct fqdir {\n\tlong int high_thresh;\n\tlong int low_thresh;\n\tint timeout;\n\tint max_dist;\n\tstruct inet_frags *f;\n\tstruct net *net;\n\tbool dead;\n\tlong: 56;\n\tlong: 64;\n\tlong: 64;\n\tstruct rhashtable rhashtable;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t mem;\n\tstruct work_struct destroy_work;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct inet_frag_queue;\n\nstruct inet_frags {\n\tunsigned int qsize;\n\tvoid (*constructor)(struct inet_frag_queue *, const void *);\n\tvoid (*destructor)(struct inet_frag_queue *);\n\tvoid (*frag_expire)(struct timer_list *);\n\tstruct kmem_cache *frags_cachep;\n\tconst char *frags_cache_name;\n\tstruct rhashtable_params rhash_params;\n\trefcount_t refcnt;\n\tstruct completion completion;\n};\n\nstruct frag_v4_compare_key {\n\t__be32 saddr;\n\t__be32 daddr;\n\tu32 user;\n\tu32 vif;\n\t__be16 id;\n\tu16 protocol;\n};\n\nstruct frag_v6_compare_key {\n\tstruct in6_addr saddr;\n\tstruct in6_addr daddr;\n\tu32 user;\n\t__be32 id;\n\tu32 iif;\n};\n\nstruct inet_frag_queue {\n\tstruct rhash_head node;\n\tunion {\n\t\tstruct frag_v4_compare_key v4;\n\t\tstruct frag_v6_compare_key v6;\n\t} key;\n\tstruct timer_list timer;\n\tspinlock_t lock;\n\trefcount_t refcnt;\n\tstruct rb_root rb_fragments;\n\tstruct sk_buff *fragments_tail;\n\tstruct sk_buff *last_run_head;\n\tktime_t stamp;\n\tint len;\n\tint meat;\n\t__u8 flags;\n\tu16 max_size;\n\tstruct fqdir *fqdir;\n\tstruct callback_head rcu;\n};\n\nstruct fib_rule;\n\nstruct fib_lookup_arg;\n\nstruct fib_rule_hdr;\n\nstruct nlattr;\n\nstruct netlink_ext_ack;\n\nstruct nla_policy;\n\nstruct fib_rules_ops {\n\tint family;\n\tstruct list_head list;\n\tint rule_size;\n\tint addr_size;\n\tint unresolved_rules;\n\tint nr_goto_rules;\n\tunsigned int fib_rules_seq;\n\tint (*action)(struct fib_rule *, struct flowi *, int, struct fib_lookup_arg *);\n\tbool (*suppress)(struct fib_rule *, struct fib_lookup_arg *);\n\tint (*match)(struct fib_rule *, struct flowi *, int);\n\tint (*configure)(struct fib_rule *, struct sk_buff *, struct fib_rule_hdr *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*delete)(struct fib_rule *);\n\tint (*compare)(struct fib_rule *, struct fib_rule_hdr *, struct nlattr **);\n\tint (*fill)(struct fib_rule *, struct sk_buff *, struct fib_rule_hdr *);\n\tsize_t (*nlmsg_payload)(struct fib_rule *);\n\tvoid (*flush_cache)(struct fib_rules_ops *);\n\tint nlgroup;\n\tconst struct nla_policy *policy;\n\tstruct list_head rules_list;\n\tstruct module *owner;\n\tstruct net *fro_net;\n\tstruct callback_head rcu;\n};\n\nenum tcp_ca_event {\n\tCA_EVENT_TX_START = 0,\n\tCA_EVENT_CWND_RESTART = 1,\n\tCA_EVENT_COMPLETE_CWR = 2,\n\tCA_EVENT_LOSS = 3,\n\tCA_EVENT_ECN_NO_CE = 4,\n\tCA_EVENT_ECN_IS_CE = 5,\n};\n\nstruct ack_sample;\n\nstruct rate_sample;\n\nunion tcp_cc_info;\n\nstruct tcp_congestion_ops {\n\tstruct list_head list;\n\tu32 key;\n\tu32 flags;\n\tvoid (*init)(struct sock *);\n\tvoid (*release)(struct sock *);\n\tu32 (*ssthresh)(struct sock *);\n\tvoid (*cong_avoid)(struct sock *, u32, u32);\n\tvoid (*set_state)(struct sock *, u8);\n\tvoid (*cwnd_event)(struct sock *, enum tcp_ca_event);\n\tvoid (*in_ack_event)(struct sock *, u32);\n\tu32 (*undo_cwnd)(struct sock *);\n\tvoid (*pkts_acked)(struct sock *, const struct ack_sample *);\n\tu32 (*min_tso_segs)(struct sock *);\n\tu32 (*sndbuf_expand)(struct sock *);\n\tvoid (*cong_control)(struct sock *, const struct rate_sample *);\n\tsize_t (*get_info)(struct sock *, u32, int *, union tcp_cc_info *);\n\tchar name[16];\n\tstruct module *owner;\n};\n\nstruct fib_notifier_ops {\n\tint family;\n\tstruct list_head list;\n\tunsigned int (*fib_seq_read)(struct net *);\n\tint (*fib_dump)(struct net *, struct notifier_block *, struct netlink_ext_ack *);\n\tstruct module *owner;\n\tstruct callback_head rcu;\n};\n\nstruct xfrm_state;\n\nstruct lwtunnel_state;\n\nstruct dst_entry {\n\tstruct net_device *dev;\n\tstruct dst_ops *ops;\n\tlong unsigned int _metrics;\n\tlong unsigned int expires;\n\tstruct xfrm_state *xfrm;\n\tint (*input)(struct sk_buff *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tshort unsigned int flags;\n\tshort int obsolete;\n\tshort unsigned int header_len;\n\tshort unsigned int trailer_len;\n\tatomic_t __refcnt;\n\tint __use;\n\tlong unsigned int lastuse;\n\tstruct lwtunnel_state *lwtstate;\n\tstruct callback_head callback_head;\n\tshort int error;\n\tshort int __pad;\n\t__u32 tclassid;\n};\n\nstruct hh_cache {\n\tunsigned int hh_len;\n\tseqlock_t hh_lock;\n\tlong unsigned int hh_data[12];\n};\n\nstruct neigh_table;\n\nstruct neigh_parms;\n\nstruct neigh_ops;\n\nstruct neighbour {\n\tstruct neighbour *next;\n\tstruct neigh_table *tbl;\n\tstruct neigh_parms *parms;\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tunsigned int arp_queue_len_bytes;\n\tstruct sk_buff_head arp_queue;\n\tstruct timer_list timer;\n\tlong unsigned int used;\n\tatomic_t probes;\n\t__u8 flags;\n\t__u8 nud_state;\n\t__u8 type;\n\t__u8 dead;\n\tu8 protocol;\n\tseqlock_t ha_lock;\n\tint: 32;\n\tunsigned char ha[32];\n\tstruct hh_cache hh;\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tconst struct neigh_ops *ops;\n\tstruct list_head gc_list;\n\tstruct callback_head rcu;\n\tstruct net_device *dev;\n\tu8 primary_key[0];\n};\n\nstruct ipv6_stable_secret {\n\tbool initialized;\n\tstruct in6_addr secret;\n};\n\nstruct ipv6_devconf {\n\t__s32 forwarding;\n\t__s32 hop_limit;\n\t__s32 mtu6;\n\t__s32 accept_ra;\n\t__s32 accept_redirects;\n\t__s32 autoconf;\n\t__s32 dad_transmits;\n\t__s32 rtr_solicits;\n\t__s32 rtr_solicit_interval;\n\t__s32 rtr_solicit_max_interval;\n\t__s32 rtr_solicit_delay;\n\t__s32 force_mld_version;\n\t__s32 mldv1_unsolicited_report_interval;\n\t__s32 mldv2_unsolicited_report_interval;\n\t__s32 use_tempaddr;\n\t__s32 temp_valid_lft;\n\t__s32 temp_prefered_lft;\n\t__s32 regen_max_retry;\n\t__s32 max_desync_factor;\n\t__s32 max_addresses;\n\t__s32 accept_ra_defrtr;\n\t__s32 accept_ra_min_hop_limit;\n\t__s32 accept_ra_pinfo;\n\t__s32 ignore_routes_with_linkdown;\n\t__s32 proxy_ndp;\n\t__s32 accept_source_route;\n\t__s32 accept_ra_from_local;\n\t__s32 disable_ipv6;\n\t__s32 drop_unicast_in_l2_multicast;\n\t__s32 accept_dad;\n\t__s32 force_tllao;\n\t__s32 ndisc_notify;\n\t__s32 suppress_frag_ndisc;\n\t__s32 accept_ra_mtu;\n\t__s32 drop_unsolicited_na;\n\tstruct ipv6_stable_secret stable_secret;\n\t__s32 use_oif_addrs_only;\n\t__s32 keep_addr_on_down;\n\t__s32 seg6_enabled;\n\t__u32 enhanced_dad;\n\t__u32 addr_gen_mode;\n\t__s32 disable_policy;\n\t__s32 ndisc_tclass;\n\t__s32 rpl_seg_enabled;\n\tstruct ctl_table_header *sysctl_header;\n};\n\nstruct nf_queue_entry;\n\nstruct nf_queue_handler {\n\tint (*outfn)(struct nf_queue_entry *, unsigned int);\n\tvoid (*nf_hook_drop)(struct net *);\n};\n\nenum nf_log_type {\n\tNF_LOG_TYPE_LOG = 0,\n\tNF_LOG_TYPE_ULOG = 1,\n\tNF_LOG_TYPE_MAX = 2,\n};\n\ntypedef u8 u_int8_t;\n\nstruct nf_loginfo;\n\ntypedef void nf_logfn(struct net *, u_int8_t, unsigned int, const struct sk_buff *, const struct net_device *, const struct net_device *, const struct nf_loginfo *, const char *);\n\nstruct nf_logger {\n\tchar *name;\n\tenum nf_log_type type;\n\tnf_logfn *logfn;\n\tstruct module *me;\n};\n\nstruct hlist_nulls_head {\n\tstruct hlist_nulls_node *first;\n};\n\nstruct ip_conntrack_stat {\n\tunsigned int found;\n\tunsigned int invalid;\n\tunsigned int ignore;\n\tunsigned int insert;\n\tunsigned int insert_failed;\n\tunsigned int drop;\n\tunsigned int early_drop;\n\tunsigned int error;\n\tunsigned int expect_new;\n\tunsigned int expect_create;\n\tunsigned int expect_delete;\n\tunsigned int search_restart;\n};\n\nstruct ct_pcpu {\n\tspinlock_t lock;\n\tstruct hlist_nulls_head unconfirmed;\n\tstruct hlist_nulls_head dying;\n};\n\ntypedef enum {\n\tSS_FREE = 0,\n\tSS_UNCONNECTED = 1,\n\tSS_CONNECTING = 2,\n\tSS_CONNECTED = 3,\n\tSS_DISCONNECTING = 4,\n} socket_state;\n\nstruct socket_wq {\n\twait_queue_head_t wait;\n\tstruct fasync_struct *fasync_list;\n\tlong unsigned int flags;\n\tstruct callback_head rcu;\n\tlong: 64;\n};\n\nstruct proto_ops;\n\nstruct socket {\n\tsocket_state state;\n\tshort int type;\n\tlong unsigned int flags;\n\tstruct file *file;\n\tstruct sock *sk;\n\tconst struct proto_ops *ops;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct socket_wq wq;\n};\n\ntypedef int (*sk_read_actor_t)(read_descriptor_t *, struct sk_buff *, unsigned int, size_t);\n\nstruct proto_ops {\n\tint family;\n\tstruct module *owner;\n\tint (*release)(struct socket *);\n\tint (*bind)(struct socket *, struct sockaddr *, int);\n\tint (*connect)(struct socket *, struct sockaddr *, int, int);\n\tint (*socketpair)(struct socket *, struct socket *);\n\tint (*accept)(struct socket *, struct socket *, int, bool);\n\tint (*getname)(struct socket *, struct sockaddr *, int);\n\t__poll_t (*poll)(struct file *, struct socket *, struct poll_table_struct *);\n\tint (*ioctl)(struct socket *, unsigned int, long unsigned int);\n\tint (*compat_ioctl)(struct socket *, unsigned int, long unsigned int);\n\tint (*gettstamp)(struct socket *, void *, bool, bool);\n\tint (*listen)(struct socket *, int);\n\tint (*shutdown)(struct socket *, int);\n\tint (*setsockopt)(struct socket *, int, int, char *, unsigned int);\n\tint (*getsockopt)(struct socket *, int, int, char *, int *);\n\tint (*compat_setsockopt)(struct socket *, int, int, char *, unsigned int);\n\tint (*compat_getsockopt)(struct socket *, int, int, char *, int *);\n\tvoid (*show_fdinfo)(struct seq_file *, struct socket *);\n\tint (*sendmsg)(struct socket *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct socket *, struct msghdr *, size_t, int);\n\tint (*mmap)(struct file *, struct socket *, struct vm_area_struct *);\n\tssize_t (*sendpage)(struct socket *, struct page *, int, size_t, int);\n\tssize_t (*splice_read)(struct socket *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tint (*set_peek_off)(struct sock *, int);\n\tint (*peek_len)(struct socket *);\n\tint (*read_sock)(struct sock *, read_descriptor_t *, sk_read_actor_t);\n\tint (*sendpage_locked)(struct sock *, struct page *, int, size_t, int);\n\tint (*sendmsg_locked)(struct sock *, struct msghdr *, size_t);\n\tint (*set_rcvlowat)(struct sock *, int);\n};\n\nenum swiotlb_force {\n\tSWIOTLB_NORMAL = 0,\n\tSWIOTLB_FORCE = 1,\n\tSWIOTLB_NO_FORCE = 2,\n};\n\nstruct pipe_buf_operations;\n\nstruct pipe_buffer {\n\tstruct page *page;\n\tunsigned int offset;\n\tunsigned int len;\n\tconst struct pipe_buf_operations *ops;\n\tunsigned int flags;\n\tlong unsigned int private;\n};\n\nstruct pipe_buf_operations {\n\tint (*confirm)(struct pipe_inode_info *, struct pipe_buffer *);\n\tvoid (*release)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*try_steal)(struct pipe_inode_info *, struct pipe_buffer *);\n\tbool (*get)(struct pipe_inode_info *, struct pipe_buffer *);\n};\n\nstruct skb_ext {\n\trefcount_t refcnt;\n\tu8 offset[1];\n\tu8 chunks;\n\tshort: 16;\n\tchar data[0];\n};\n\nstruct skb_checksum_ops {\n\t__wsum (*update)(const void *, int, __wsum);\n\t__wsum (*combine)(__wsum, __wsum, int, int);\n};\n\nstruct pernet_operations {\n\tstruct list_head list;\n\tint (*init)(struct net *);\n\tvoid (*pre_exit)(struct net *);\n\tvoid (*exit)(struct net *);\n\tvoid (*exit_batch)(struct list_head *);\n\tunsigned int *id;\n\tsize_t size;\n};\n\nstruct auth_cred {\n\tconst struct cred *cred;\n\tconst char *principal;\n};\n\nstruct rpc_authops;\n\nstruct rpc_cred_cache;\n\nstruct rpc_auth {\n\tunsigned int au_cslack;\n\tunsigned int au_rslack;\n\tunsigned int au_verfsize;\n\tunsigned int au_ralign;\n\tlong unsigned int au_flags;\n\tconst struct rpc_authops *au_ops;\n\trpc_authflavor_t au_flavor;\n\trefcount_t au_count;\n\tstruct rpc_cred_cache *au_credcache;\n};\n\nstruct rpc_credops {\n\tconst char *cr_name;\n\tint (*cr_init)(struct rpc_auth *, struct rpc_cred *);\n\tvoid (*crdestroy)(struct rpc_cred *);\n\tint (*crmatch)(struct auth_cred *, struct rpc_cred *, int);\n\tint (*crmarshal)(struct rpc_task *, struct xdr_stream *);\n\tint (*crrefresh)(struct rpc_task *);\n\tint (*crvalidate)(struct rpc_task *, struct xdr_stream *);\n\tint (*crwrap_req)(struct rpc_task *, struct xdr_stream *);\n\tint (*crunwrap_resp)(struct rpc_task *, struct xdr_stream *);\n\tint (*crkey_timeout)(struct rpc_cred *);\n\tchar * (*crstringify_acceptor)(struct rpc_cred *);\n\tbool (*crneed_reencode)(struct rpc_task *);\n};\n\nstruct rpc_auth_create_args;\n\nstruct rpcsec_gss_info;\n\nstruct rpc_authops {\n\tstruct module *owner;\n\trpc_authflavor_t au_flavor;\n\tchar *au_name;\n\tstruct rpc_auth * (*create)(const struct rpc_auth_create_args *, struct rpc_clnt *);\n\tvoid (*destroy)(struct rpc_auth *);\n\tint (*hash_cred)(struct auth_cred *, unsigned int);\n\tstruct rpc_cred * (*lookup_cred)(struct rpc_auth *, struct auth_cred *, int);\n\tstruct rpc_cred * (*crcreate)(struct rpc_auth *, struct auth_cred *, int, gfp_t);\n\trpc_authflavor_t (*info2flavor)(struct rpcsec_gss_info *);\n\tint (*flavor2info)(rpc_authflavor_t, struct rpcsec_gss_info *);\n\tint (*key_timeout)(struct rpc_auth *, struct rpc_cred *);\n};\n\nstruct rpc_auth_create_args {\n\trpc_authflavor_t pseudoflavor;\n\tconst char *target_name;\n};\n\nstruct rpcsec_gss_oid {\n\tunsigned int len;\n\tu8 data[32];\n};\n\nstruct rpcsec_gss_info {\n\tstruct rpcsec_gss_oid oid;\n\tu32 qop;\n\tu32 service;\n};\n\nstruct rpc_xprt_ops {\n\tvoid (*set_buffer_size)(struct rpc_xprt *, size_t, size_t);\n\tint (*reserve_xprt)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*release_xprt)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*alloc_slot)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*free_slot)(struct rpc_xprt *, struct rpc_rqst *);\n\tvoid (*rpcbind)(struct rpc_task *);\n\tvoid (*set_port)(struct rpc_xprt *, short unsigned int);\n\tvoid (*connect)(struct rpc_xprt *, struct rpc_task *);\n\tint (*buf_alloc)(struct rpc_task *);\n\tvoid (*buf_free)(struct rpc_task *);\n\tvoid (*prepare_request)(struct rpc_rqst *);\n\tint (*send_request)(struct rpc_rqst *);\n\tvoid (*wait_for_reply_request)(struct rpc_task *);\n\tvoid (*timer)(struct rpc_xprt *, struct rpc_task *);\n\tvoid (*release_request)(struct rpc_task *);\n\tvoid (*close)(struct rpc_xprt *);\n\tvoid (*destroy)(struct rpc_xprt *);\n\tvoid (*set_connect_timeout)(struct rpc_xprt *, long unsigned int, long unsigned int);\n\tvoid (*print_stats)(struct rpc_xprt *, struct seq_file *);\n\tint (*enable_swap)(struct rpc_xprt *);\n\tvoid (*disable_swap)(struct rpc_xprt *);\n\tvoid (*inject_disconnect)(struct rpc_xprt *);\n\tint (*bc_setup)(struct rpc_xprt *, unsigned int);\n\tsize_t (*bc_maxpayload)(struct rpc_xprt *);\n\tunsigned int (*bc_num_slots)(struct rpc_xprt *);\n\tvoid (*bc_free_rqst)(struct rpc_rqst *);\n\tvoid (*bc_destroy)(struct rpc_xprt *, unsigned int);\n};\n\nstruct rpc_xprt_switch {\n\tspinlock_t xps_lock;\n\tstruct kref xps_kref;\n\tunsigned int xps_nxprts;\n\tunsigned int xps_nactive;\n\tatomic_long_t xps_queuelen;\n\tstruct list_head xps_xprt_list;\n\tstruct net *xps_net;\n\tconst struct rpc_xprt_iter_ops *xps_iter_ops;\n\tstruct callback_head xps_rcu;\n};\n\nstruct rpc_stat {\n\tconst struct rpc_program *program;\n\tunsigned int netcnt;\n\tunsigned int netudpcnt;\n\tunsigned int nettcpcnt;\n\tunsigned int nettcpconn;\n\tunsigned int netreconn;\n\tunsigned int rpccnt;\n\tunsigned int rpcretrans;\n\tunsigned int rpcauthrefresh;\n\tunsigned int rpcgarbage;\n};\n\nstruct rpc_version;\n\nstruct rpc_program {\n\tconst char *name;\n\tu32 number;\n\tunsigned int nrvers;\n\tconst struct rpc_version **version;\n\tstruct rpc_stat *stats;\n\tconst char *pipe_dir_name;\n};\n\nstruct ipv6_params {\n\t__s32 disable_ipv6;\n\t__s32 autoconf;\n};\n\nstruct dql {\n\tunsigned int num_queued;\n\tunsigned int adj_limit;\n\tunsigned int last_obj_cnt;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int limit;\n\tunsigned int num_completed;\n\tunsigned int prev_ovlimit;\n\tunsigned int prev_num_queued;\n\tunsigned int prev_last_obj_cnt;\n\tunsigned int lowest_slack;\n\tlong unsigned int slack_start_time;\n\tunsigned int max_limit;\n\tunsigned int min_limit;\n\tunsigned int slack_hold_time;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ethtool_drvinfo {\n\t__u32 cmd;\n\tchar driver[32];\n\tchar version[32];\n\tchar fw_version[32];\n\tchar bus_info[32];\n\tchar erom_version[32];\n\tchar reserved2[12];\n\t__u32 n_priv_flags;\n\t__u32 n_stats;\n\t__u32 testinfo_len;\n\t__u32 eedump_len;\n\t__u32 regdump_len;\n};\n\nstruct ethtool_wolinfo {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 wolopts;\n\t__u8 sopass[6];\n};\n\nstruct ethtool_tunable {\n\t__u32 cmd;\n\t__u32 id;\n\t__u32 type_id;\n\t__u32 len;\n\tvoid *data[0];\n};\n\nstruct ethtool_regs {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eeprom {\n\t__u32 cmd;\n\t__u32 magic;\n\t__u32 offset;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_eee {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertised;\n\t__u32 lp_advertised;\n\t__u32 eee_active;\n\t__u32 eee_enabled;\n\t__u32 tx_lpi_enabled;\n\t__u32 tx_lpi_timer;\n\t__u32 reserved[2];\n};\n\nstruct ethtool_modinfo {\n\t__u32 cmd;\n\t__u32 type;\n\t__u32 eeprom_len;\n\t__u32 reserved[8];\n};\n\nstruct ethtool_coalesce {\n\t__u32 cmd;\n\t__u32 rx_coalesce_usecs;\n\t__u32 rx_max_coalesced_frames;\n\t__u32 rx_coalesce_usecs_irq;\n\t__u32 rx_max_coalesced_frames_irq;\n\t__u32 tx_coalesce_usecs;\n\t__u32 tx_max_coalesced_frames;\n\t__u32 tx_coalesce_usecs_irq;\n\t__u32 tx_max_coalesced_frames_irq;\n\t__u32 stats_block_coalesce_usecs;\n\t__u32 use_adaptive_rx_coalesce;\n\t__u32 use_adaptive_tx_coalesce;\n\t__u32 pkt_rate_low;\n\t__u32 rx_coalesce_usecs_low;\n\t__u32 rx_max_coalesced_frames_low;\n\t__u32 tx_coalesce_usecs_low;\n\t__u32 tx_max_coalesced_frames_low;\n\t__u32 pkt_rate_high;\n\t__u32 rx_coalesce_usecs_high;\n\t__u32 rx_max_coalesced_frames_high;\n\t__u32 tx_coalesce_usecs_high;\n\t__u32 tx_max_coalesced_frames_high;\n\t__u32 rate_sample_interval;\n};\n\nstruct ethtool_ringparam {\n\t__u32 cmd;\n\t__u32 rx_max_pending;\n\t__u32 rx_mini_max_pending;\n\t__u32 rx_jumbo_max_pending;\n\t__u32 tx_max_pending;\n\t__u32 rx_pending;\n\t__u32 rx_mini_pending;\n\t__u32 rx_jumbo_pending;\n\t__u32 tx_pending;\n};\n\nstruct ethtool_channels {\n\t__u32 cmd;\n\t__u32 max_rx;\n\t__u32 max_tx;\n\t__u32 max_other;\n\t__u32 max_combined;\n\t__u32 rx_count;\n\t__u32 tx_count;\n\t__u32 other_count;\n\t__u32 combined_count;\n};\n\nstruct ethtool_pauseparam {\n\t__u32 cmd;\n\t__u32 autoneg;\n\t__u32 rx_pause;\n\t__u32 tx_pause;\n};\n\nstruct ethtool_test {\n\t__u32 cmd;\n\t__u32 flags;\n\t__u32 reserved;\n\t__u32 len;\n\t__u64 data[0];\n};\n\nstruct ethtool_stats {\n\t__u32 cmd;\n\t__u32 n_stats;\n\t__u64 data[0];\n};\n\nstruct ethtool_tcpip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tos;\n};\n\nstruct ethtool_ah_espip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 spi;\n\t__u8 tos;\n};\n\nstruct ethtool_usrip4_spec {\n\t__be32 ip4src;\n\t__be32 ip4dst;\n\t__be32 l4_4_bytes;\n\t__u8 tos;\n\t__u8 ip_ver;\n\t__u8 proto;\n};\n\nstruct ethtool_tcpip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be16 psrc;\n\t__be16 pdst;\n\t__u8 tclass;\n};\n\nstruct ethtool_ah_espip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 spi;\n\t__u8 tclass;\n};\n\nstruct ethtool_usrip6_spec {\n\t__be32 ip6src[4];\n\t__be32 ip6dst[4];\n\t__be32 l4_4_bytes;\n\t__u8 tclass;\n\t__u8 l4_proto;\n};\n\nunion ethtool_flow_union {\n\tstruct ethtool_tcpip4_spec tcp_ip4_spec;\n\tstruct ethtool_tcpip4_spec udp_ip4_spec;\n\tstruct ethtool_tcpip4_spec sctp_ip4_spec;\n\tstruct ethtool_ah_espip4_spec ah_ip4_spec;\n\tstruct ethtool_ah_espip4_spec esp_ip4_spec;\n\tstruct ethtool_usrip4_spec usr_ip4_spec;\n\tstruct ethtool_tcpip6_spec tcp_ip6_spec;\n\tstruct ethtool_tcpip6_spec udp_ip6_spec;\n\tstruct ethtool_tcpip6_spec sctp_ip6_spec;\n\tstruct ethtool_ah_espip6_spec ah_ip6_spec;\n\tstruct ethtool_ah_espip6_spec esp_ip6_spec;\n\tstruct ethtool_usrip6_spec usr_ip6_spec;\n\tstruct ethhdr ether_spec;\n\t__u8 hdata[52];\n};\n\nstruct ethtool_flow_ext {\n\t__u8 padding[2];\n\tunsigned char h_dest[6];\n\t__be16 vlan_etype;\n\t__be16 vlan_tci;\n\t__be32 data[2];\n};\n\nstruct ethtool_rx_flow_spec {\n\t__u32 flow_type;\n\tunion ethtool_flow_union h_u;\n\tstruct ethtool_flow_ext h_ext;\n\tunion ethtool_flow_union m_u;\n\tstruct ethtool_flow_ext m_ext;\n\t__u64 ring_cookie;\n\t__u32 location;\n};\n\nstruct ethtool_rxnfc {\n\t__u32 cmd;\n\t__u32 flow_type;\n\t__u64 data;\n\tstruct ethtool_rx_flow_spec fs;\n\tunion {\n\t\t__u32 rule_cnt;\n\t\t__u32 rss_context;\n\t};\n\t__u32 rule_locs[0];\n};\n\nstruct ethtool_flash {\n\t__u32 cmd;\n\t__u32 region;\n\tchar data[128];\n};\n\nstruct ethtool_dump {\n\t__u32 cmd;\n\t__u32 version;\n\t__u32 flag;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_ts_info {\n\t__u32 cmd;\n\t__u32 so_timestamping;\n\t__s32 phc_index;\n\t__u32 tx_types;\n\t__u32 tx_reserved[3];\n\t__u32 rx_filters;\n\t__u32 rx_reserved[3];\n};\n\nstruct ethtool_fecparam {\n\t__u32 cmd;\n\t__u32 active_fec;\n\t__u32 fec;\n\t__u32 reserved;\n};\n\nstruct ethtool_link_settings {\n\t__u32 cmd;\n\t__u32 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__s8 link_mode_masks_nwords;\n\t__u8 transceiver;\n\t__u8 master_slave_cfg;\n\t__u8 master_slave_state;\n\t__u8 reserved1[1];\n\t__u32 reserved[7];\n\t__u32 link_mode_masks[0];\n};\n\nenum ethtool_phys_id_state {\n\tETHTOOL_ID_INACTIVE = 0,\n\tETHTOOL_ID_ACTIVE = 1,\n\tETHTOOL_ID_ON = 2,\n\tETHTOOL_ID_OFF = 3,\n};\n\nstruct ethtool_link_ksettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\tlong unsigned int supported[2];\n\t\tlong unsigned int advertising[2];\n\t\tlong unsigned int lp_advertising[2];\n\t} link_modes;\n};\n\nstruct ethtool_ops {\n\tu32 supported_coalesce_params;\n\tvoid (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);\n\tint (*get_regs_len)(struct net_device *);\n\tvoid (*get_regs)(struct net_device *, struct ethtool_regs *, void *);\n\tvoid (*get_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tint (*set_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tu32 (*get_msglevel)(struct net_device *);\n\tvoid (*set_msglevel)(struct net_device *, u32);\n\tint (*nway_reset)(struct net_device *);\n\tu32 (*get_link)(struct net_device *);\n\tint (*get_eeprom_len)(struct net_device *);\n\tint (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_coalesce)(struct net_device *, struct ethtool_coalesce *);\n\tint (*set_coalesce)(struct net_device *, struct ethtool_coalesce *);\n\tvoid (*get_ringparam)(struct net_device *, struct ethtool_ringparam *);\n\tint (*set_ringparam)(struct net_device *, struct ethtool_ringparam *);\n\tvoid (*get_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tint (*set_pauseparam)(struct net_device *, struct ethtool_pauseparam *);\n\tvoid (*self_test)(struct net_device *, struct ethtool_test *, u64 *);\n\tvoid (*get_strings)(struct net_device *, u32, u8 *);\n\tint (*set_phys_id)(struct net_device *, enum ethtool_phys_id_state);\n\tvoid (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n\tint (*begin)(struct net_device *);\n\tvoid (*complete)(struct net_device *);\n\tu32 (*get_priv_flags)(struct net_device *);\n\tint (*set_priv_flags)(struct net_device *, u32);\n\tint (*get_sset_count)(struct net_device *, int);\n\tint (*get_rxnfc)(struct net_device *, struct ethtool_rxnfc *, u32 *);\n\tint (*set_rxnfc)(struct net_device *, struct ethtool_rxnfc *);\n\tint (*flash_device)(struct net_device *, struct ethtool_flash *);\n\tint (*reset)(struct net_device *, u32 *);\n\tu32 (*get_rxfh_key_size)(struct net_device *);\n\tu32 (*get_rxfh_indir_size)(struct net_device *);\n\tint (*get_rxfh)(struct net_device *, u32 *, u8 *, u8 *);\n\tint (*set_rxfh)(struct net_device *, const u32 *, const u8 *, const u8);\n\tint (*get_rxfh_context)(struct net_device *, u32 *, u8 *, u8 *, u32);\n\tint (*set_rxfh_context)(struct net_device *, const u32 *, const u8 *, const u8, u32 *, bool);\n\tvoid (*get_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*set_channels)(struct net_device *, struct ethtool_channels *);\n\tint (*get_dump_flag)(struct net_device *, struct ethtool_dump *);\n\tint (*get_dump_data)(struct net_device *, struct ethtool_dump *, void *);\n\tint (*set_dump)(struct net_device *, struct ethtool_dump *);\n\tint (*get_ts_info)(struct net_device *, struct ethtool_ts_info *);\n\tint (*get_module_info)(struct net_device *, struct ethtool_modinfo *);\n\tint (*get_module_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_eee)(struct net_device *, struct ethtool_eee *);\n\tint (*set_eee)(struct net_device *, struct ethtool_eee *);\n\tint (*get_tunable)(struct net_device *, const struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct net_device *, const struct ethtool_tunable *, const void *);\n\tint (*get_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*set_per_queue_coalesce)(struct net_device *, u32, struct ethtool_coalesce *);\n\tint (*get_link_ksettings)(struct net_device *, struct ethtool_link_ksettings *);\n\tint (*set_link_ksettings)(struct net_device *, const struct ethtool_link_ksettings *);\n\tint (*get_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tint (*set_fecparam)(struct net_device *, struct ethtool_fecparam *);\n\tvoid (*get_ethtool_phy_stats)(struct net_device *, struct ethtool_stats *, u64 *);\n};\n\nstruct xdp_mem_info {\n\tu32 type;\n\tu32 id;\n};\n\nstruct xdp_rxq_info {\n\tstruct net_device *dev;\n\tu32 queue_index;\n\tu32 reg_state;\n\tstruct xdp_mem_info mem;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xdp_frame {\n\tvoid *data;\n\tu16 len;\n\tu16 headroom;\n\tu32 metasize: 8;\n\tu32 frame_sz: 24;\n\tstruct xdp_mem_info mem;\n\tstruct net_device *dev_rx;\n};\n\nstruct nlmsghdr {\n\t__u32 nlmsg_len;\n\t__u16 nlmsg_type;\n\t__u16 nlmsg_flags;\n\t__u32 nlmsg_seq;\n\t__u32 nlmsg_pid;\n};\n\nstruct nlattr {\n\t__u16 nla_len;\n\t__u16 nla_type;\n};\n\nstruct netlink_ext_ack {\n\tconst char *_msg;\n\tconst struct nlattr *bad_attr;\n\tu8 cookie[20];\n\tu8 cookie_len;\n};\n\nstruct netlink_callback {\n\tstruct sk_buff *skb;\n\tconst struct nlmsghdr *nlh;\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tvoid *data;\n\tstruct module *module;\n\tstruct netlink_ext_ack *extack;\n\tu16 family;\n\tu16 answer_flags;\n\tu32 min_dump_alloc;\n\tunsigned int prev_seq;\n\tunsigned int seq;\n\tbool strict_check;\n\tunion {\n\t\tu8 ctx[48];\n\t\tlong int args[6];\n\t};\n};\n\nstruct ndmsg {\n\t__u8 ndm_family;\n\t__u8 ndm_pad1;\n\t__u16 ndm_pad2;\n\t__s32 ndm_ifindex;\n\t__u16 ndm_state;\n\t__u8 ndm_flags;\n\t__u8 ndm_type;\n};\n\nstruct rtnl_link_stats64 {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 rx_errors;\n\t__u64 tx_errors;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n\t__u64 multicast;\n\t__u64 collisions;\n\t__u64 rx_length_errors;\n\t__u64 rx_over_errors;\n\t__u64 rx_crc_errors;\n\t__u64 rx_frame_errors;\n\t__u64 rx_fifo_errors;\n\t__u64 rx_missed_errors;\n\t__u64 tx_aborted_errors;\n\t__u64 tx_carrier_errors;\n\t__u64 tx_fifo_errors;\n\t__u64 tx_heartbeat_errors;\n\t__u64 tx_window_errors;\n\t__u64 rx_compressed;\n\t__u64 tx_compressed;\n\t__u64 rx_nohandler;\n};\n\nstruct ifla_vf_guid {\n\t__u32 vf;\n\t__u64 guid;\n};\n\nstruct ifla_vf_stats {\n\t__u64 rx_packets;\n\t__u64 tx_packets;\n\t__u64 rx_bytes;\n\t__u64 tx_bytes;\n\t__u64 broadcast;\n\t__u64 multicast;\n\t__u64 rx_dropped;\n\t__u64 tx_dropped;\n};\n\nstruct ifla_vf_info {\n\t__u32 vf;\n\t__u8 mac[32];\n\t__u32 vlan;\n\t__u32 qos;\n\t__u32 spoofchk;\n\t__u32 linkstate;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n\t__u32 rss_query_en;\n\t__u32 trusted;\n\t__be16 vlan_proto;\n};\n\nstruct tc_stats {\n\t__u64 bytes;\n\t__u32 packets;\n\t__u32 drops;\n\t__u32 overlimits;\n\t__u32 bps;\n\t__u32 pps;\n\t__u32 qlen;\n\t__u32 backlog;\n};\n\nstruct tc_sizespec {\n\tunsigned char cell_log;\n\tunsigned char size_log;\n\tshort int cell_align;\n\tint overhead;\n\tunsigned int linklayer;\n\tunsigned int mpu;\n\tunsigned int mtu;\n\tunsigned int tsize;\n};\n\nenum netdev_tx {\n\t__NETDEV_TX_MIN = 2147483648,\n\tNETDEV_TX_OK = 0,\n\tNETDEV_TX_BUSY = 16,\n};\n\ntypedef enum netdev_tx netdev_tx_t;\n\nstruct header_ops {\n\tint (*create)(struct sk_buff *, struct net_device *, short unsigned int, const void *, const void *, unsigned int);\n\tint (*parse)(const struct sk_buff *, unsigned char *);\n\tint (*cache)(const struct neighbour *, struct hh_cache *, __be16);\n\tvoid (*cache_update)(struct hh_cache *, const struct net_device *, const unsigned char *);\n\tbool (*validate)(const char *, unsigned int);\n\t__be16 (*parse_protocol)(const struct sk_buff *);\n};\n\nstruct gro_list {\n\tstruct list_head list;\n\tint count;\n};\n\nstruct napi_struct {\n\tstruct list_head poll_list;\n\tlong unsigned int state;\n\tint weight;\n\tint defer_hard_irqs_count;\n\tlong unsigned int gro_bitmask;\n\tint (*poll)(struct napi_struct *, int);\n\tint poll_owner;\n\tstruct net_device *dev;\n\tstruct gro_list gro_hash[8];\n\tstruct sk_buff *skb;\n\tstruct list_head rx_list;\n\tint rx_count;\n\tstruct hrtimer timer;\n\tstruct list_head dev_list;\n\tstruct hlist_node napi_hash_node;\n\tunsigned int napi_id;\n};\n\nstruct xdp_umem;\n\nstruct netdev_queue {\n\tstruct net_device *dev;\n\tstruct Qdisc *qdisc;\n\tstruct Qdisc *qdisc_sleeping;\n\tstruct kobject kobj;\n\tint numa_node;\n\tlong unsigned int tx_maxrate;\n\tlong unsigned int trans_timeout;\n\tstruct net_device *sb_dev;\n\tstruct xdp_umem *umem;\n\tspinlock_t _xmit_lock;\n\tint xmit_lock_owner;\n\tlong unsigned int trans_start;\n\tlong unsigned int state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct dql dql;\n};\n\nstruct qdisc_skb_head {\n\tstruct sk_buff *head;\n\tstruct sk_buff *tail;\n\t__u32 qlen;\n\tspinlock_t lock;\n};\n\nstruct gnet_stats_basic_packed {\n\t__u64 bytes;\n\t__u64 packets;\n};\n\nstruct gnet_stats_queue {\n\t__u32 qlen;\n\t__u32 backlog;\n\t__u32 drops;\n\t__u32 requeues;\n\t__u32 overlimits;\n};\n\nstruct Qdisc_ops;\n\nstruct qdisc_size_table;\n\nstruct net_rate_estimator;\n\nstruct gnet_stats_basic_cpu;\n\nstruct Qdisc {\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tunsigned int flags;\n\tu32 limit;\n\tconst struct Qdisc_ops *ops;\n\tstruct qdisc_size_table *stab;\n\tstruct hlist_node hash;\n\tu32 handle;\n\tu32 parent;\n\tstruct netdev_queue *dev_queue;\n\tstruct net_rate_estimator *rate_est;\n\tstruct gnet_stats_basic_cpu *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tint padded;\n\trefcount_t refcnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sk_buff_head gso_skb;\n\tstruct qdisc_skb_head q;\n\tstruct gnet_stats_basic_packed bstats;\n\tseqcount_t running;\n\tstruct gnet_stats_queue qstats;\n\tlong unsigned int state;\n\tstruct Qdisc *next_sched;\n\tstruct sk_buff_head skb_bad_txq;\n\tspinlock_t busylock;\n\tspinlock_t seqlock;\n\tbool empty;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rps_map {\n\tunsigned int len;\n\tstruct callback_head rcu;\n\tu16 cpus[0];\n};\n\nstruct rps_dev_flow {\n\tu16 cpu;\n\tu16 filter;\n\tunsigned int last_qtail;\n};\n\nstruct rps_dev_flow_table {\n\tunsigned int mask;\n\tstruct callback_head rcu;\n\tstruct rps_dev_flow flows[0];\n};\n\nstruct rps_sock_flow_table {\n\tu32 mask;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 ents[0];\n};\n\nstruct netdev_rx_queue {\n\tstruct rps_map *rps_map;\n\tstruct rps_dev_flow_table *rps_flow_table;\n\tstruct kobject kobj;\n\tstruct net_device *dev;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct xdp_rxq_info xdp_rxq;\n\tstruct xdp_umem *umem;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xps_map {\n\tunsigned int len;\n\tunsigned int alloc_len;\n\tstruct callback_head rcu;\n\tu16 queues[0];\n};\n\nstruct xps_dev_maps {\n\tstruct callback_head rcu;\n\tstruct xps_map *attr_map[0];\n};\n\nstruct netdev_phys_item_id {\n\tunsigned char id[32];\n\tunsigned char id_len;\n};\n\nenum tc_setup_type {\n\tTC_SETUP_QDISC_MQPRIO = 0,\n\tTC_SETUP_CLSU32 = 1,\n\tTC_SETUP_CLSFLOWER = 2,\n\tTC_SETUP_CLSMATCHALL = 3,\n\tTC_SETUP_CLSBPF = 4,\n\tTC_SETUP_BLOCK = 5,\n\tTC_SETUP_QDISC_CBS = 6,\n\tTC_SETUP_QDISC_RED = 7,\n\tTC_SETUP_QDISC_PRIO = 8,\n\tTC_SETUP_QDISC_MQ = 9,\n\tTC_SETUP_QDISC_ETF = 10,\n\tTC_SETUP_ROOT_QDISC = 11,\n\tTC_SETUP_QDISC_GRED = 12,\n\tTC_SETUP_QDISC_TAPRIO = 13,\n\tTC_SETUP_FT = 14,\n\tTC_SETUP_QDISC_ETS = 15,\n\tTC_SETUP_QDISC_TBF = 16,\n\tTC_SETUP_QDISC_FIFO = 17,\n};\n\nenum bpf_netdev_command {\n\tXDP_SETUP_PROG = 0,\n\tXDP_SETUP_PROG_HW = 1,\n\tXDP_QUERY_PROG = 2,\n\tXDP_QUERY_PROG_HW = 3,\n\tBPF_OFFLOAD_MAP_ALLOC = 4,\n\tBPF_OFFLOAD_MAP_FREE = 5,\n\tXDP_SETUP_XSK_UMEM = 6,\n};\n\nstruct netdev_bpf {\n\tenum bpf_netdev_command command;\n\tunion {\n\t\tstruct {\n\t\t\tu32 flags;\n\t\t\tstruct bpf_prog *prog;\n\t\t\tstruct netlink_ext_ack *extack;\n\t\t};\n\t\tstruct {\n\t\t\tu32 prog_id;\n\t\t\tu32 prog_flags;\n\t\t};\n\t\tstruct {\n\t\t\tstruct bpf_offloaded_map *offmap;\n\t\t};\n\t\tstruct {\n\t\t\tstruct xdp_umem *umem;\n\t\t\tu16 queue_id;\n\t\t} xsk;\n\t};\n};\n\nstruct dev_ifalias {\n\tstruct callback_head rcuhead;\n\tchar ifalias[0];\n};\n\nstruct netdev_name_node {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tconst char *name;\n};\n\nstruct udp_tunnel_info;\n\nstruct devlink_port;\n\nstruct ip_tunnel_parm;\n\nstruct net_device_ops {\n\tint (*ndo_init)(struct net_device *);\n\tvoid (*ndo_uninit)(struct net_device *);\n\tint (*ndo_open)(struct net_device *);\n\tint (*ndo_stop)(struct net_device *);\n\tnetdev_tx_t (*ndo_start_xmit)(struct sk_buff *, struct net_device *);\n\tnetdev_features_t (*ndo_features_check)(struct sk_buff *, struct net_device *, netdev_features_t);\n\tu16 (*ndo_select_queue)(struct net_device *, struct sk_buff *, struct net_device *);\n\tvoid (*ndo_change_rx_flags)(struct net_device *, int);\n\tvoid (*ndo_set_rx_mode)(struct net_device *);\n\tint (*ndo_set_mac_address)(struct net_device *, void *);\n\tint (*ndo_validate_addr)(struct net_device *);\n\tint (*ndo_do_ioctl)(struct net_device *, struct ifreq *, int);\n\tint (*ndo_set_config)(struct net_device *, struct ifmap *);\n\tint (*ndo_change_mtu)(struct net_device *, int);\n\tint (*ndo_neigh_setup)(struct net_device *, struct neigh_parms *);\n\tvoid (*ndo_tx_timeout)(struct net_device *, unsigned int);\n\tvoid (*ndo_get_stats64)(struct net_device *, struct rtnl_link_stats64 *);\n\tbool (*ndo_has_offload_stats)(const struct net_device *, int);\n\tint (*ndo_get_offload_stats)(int, const struct net_device *, void *);\n\tstruct net_device_stats * (*ndo_get_stats)(struct net_device *);\n\tint (*ndo_vlan_rx_add_vid)(struct net_device *, __be16, u16);\n\tint (*ndo_vlan_rx_kill_vid)(struct net_device *, __be16, u16);\n\tvoid (*ndo_poll_controller)(struct net_device *);\n\tint (*ndo_netpoll_setup)(struct net_device *, struct netpoll_info *);\n\tvoid (*ndo_netpoll_cleanup)(struct net_device *);\n\tint (*ndo_set_vf_mac)(struct net_device *, int, u8 *);\n\tint (*ndo_set_vf_vlan)(struct net_device *, int, u16, u8, __be16);\n\tint (*ndo_set_vf_rate)(struct net_device *, int, int, int);\n\tint (*ndo_set_vf_spoofchk)(struct net_device *, int, bool);\n\tint (*ndo_set_vf_trust)(struct net_device *, int, bool);\n\tint (*ndo_get_vf_config)(struct net_device *, int, struct ifla_vf_info *);\n\tint (*ndo_set_vf_link_state)(struct net_device *, int, int);\n\tint (*ndo_get_vf_stats)(struct net_device *, int, struct ifla_vf_stats *);\n\tint (*ndo_set_vf_port)(struct net_device *, int, struct nlattr **);\n\tint (*ndo_get_vf_port)(struct net_device *, int, struct sk_buff *);\n\tint (*ndo_get_vf_guid)(struct net_device *, int, struct ifla_vf_guid *, struct ifla_vf_guid *);\n\tint (*ndo_set_vf_guid)(struct net_device *, int, u64, int);\n\tint (*ndo_set_vf_rss_query_en)(struct net_device *, int, bool);\n\tint (*ndo_setup_tc)(struct net_device *, enum tc_setup_type, void *);\n\tint (*ndo_rx_flow_steer)(struct net_device *, const struct sk_buff *, u16, u32);\n\tint (*ndo_add_slave)(struct net_device *, struct net_device *, struct netlink_ext_ack *);\n\tint (*ndo_del_slave)(struct net_device *, struct net_device *);\n\tstruct net_device * (*ndo_get_xmit_slave)(struct net_device *, struct sk_buff *, bool);\n\tnetdev_features_t (*ndo_fix_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_set_features)(struct net_device *, netdev_features_t);\n\tint (*ndo_neigh_construct)(struct net_device *, struct neighbour *);\n\tvoid (*ndo_neigh_destroy)(struct net_device *, struct neighbour *);\n\tint (*ndo_fdb_add)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16, u16, struct netlink_ext_ack *);\n\tint (*ndo_fdb_del)(struct ndmsg *, struct nlattr **, struct net_device *, const unsigned char *, u16);\n\tint (*ndo_fdb_dump)(struct sk_buff *, struct netlink_callback *, struct net_device *, struct net_device *, int *);\n\tint (*ndo_fdb_get)(struct sk_buff *, struct nlattr **, struct net_device *, const unsigned char *, u16, u32, u32, struct netlink_ext_ack *);\n\tint (*ndo_bridge_setlink)(struct net_device *, struct nlmsghdr *, u16, struct netlink_ext_ack *);\n\tint (*ndo_bridge_getlink)(struct sk_buff *, u32, u32, struct net_device *, u32, int);\n\tint (*ndo_bridge_dellink)(struct net_device *, struct nlmsghdr *, u16);\n\tint (*ndo_change_carrier)(struct net_device *, bool);\n\tint (*ndo_get_phys_port_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_port_parent_id)(struct net_device *, struct netdev_phys_item_id *);\n\tint (*ndo_get_phys_port_name)(struct net_device *, char *, size_t);\n\tvoid (*ndo_udp_tunnel_add)(struct net_device *, struct udp_tunnel_info *);\n\tvoid (*ndo_udp_tunnel_del)(struct net_device *, struct udp_tunnel_info *);\n\tvoid * (*ndo_dfwd_add_station)(struct net_device *, struct net_device *);\n\tvoid (*ndo_dfwd_del_station)(struct net_device *, void *);\n\tint (*ndo_set_tx_maxrate)(struct net_device *, int, u32);\n\tint (*ndo_get_iflink)(const struct net_device *);\n\tint (*ndo_change_proto_down)(struct net_device *, bool);\n\tint (*ndo_fill_metadata_dst)(struct net_device *, struct sk_buff *);\n\tvoid (*ndo_set_rx_headroom)(struct net_device *, int);\n\tint (*ndo_bpf)(struct net_device *, struct netdev_bpf *);\n\tint (*ndo_xdp_xmit)(struct net_device *, int, struct xdp_frame **, u32);\n\tint (*ndo_xsk_wakeup)(struct net_device *, u32, u32);\n\tstruct devlink_port * (*ndo_get_devlink_port)(struct net_device *);\n\tint (*ndo_tunnel_ctl)(struct net_device *, struct ip_tunnel_parm *, int);\n};\n\nstruct neigh_parms {\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tstruct list_head list;\n\tint (*neigh_setup)(struct neighbour *);\n\tstruct neigh_table *tbl;\n\tvoid *sysctl_table;\n\tint dead;\n\trefcount_t refcnt;\n\tstruct callback_head callback_head;\n\tint reachable_time;\n\tint data[13];\n\tlong unsigned int data_state[1];\n};\n\nstruct pcpu_lstats {\n\tu64_stats_t packets;\n\tu64_stats_t bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct pcpu_sw_netstats {\n\tu64 rx_packets;\n\tu64 rx_bytes;\n\tu64 tx_packets;\n\tu64 tx_bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct nd_opt_hdr;\n\nstruct ndisc_options;\n\nstruct prefix_info;\n\nstruct ndisc_ops {\n\tint (*is_useropt)(u8);\n\tint (*parse_options)(const struct net_device *, struct nd_opt_hdr *, struct ndisc_options *);\n\tvoid (*update)(const struct net_device *, struct neighbour *, u32, u8, const struct ndisc_options *);\n\tint (*opt_addr_space)(const struct net_device *, u8, struct neighbour *, u8 *, u8 **);\n\tvoid (*fill_addr_option)(const struct net_device *, struct sk_buff *, u8, const u8 *);\n\tvoid (*prefix_rcv_add_addr)(struct net *, struct net_device *, const struct prefix_info *, struct inet6_dev *, struct in6_addr *, int, u32, bool, bool, __u32, u32, bool);\n};\n\nstruct ipv6_devstat {\n\tstruct proc_dir_entry *proc_dir_entry;\n\tstruct ipstats_mib *ipv6;\n\tstruct icmpv6_mib_device *icmpv6dev;\n\tstruct icmpv6msg_mib_device *icmpv6msgdev;\n};\n\nstruct ifmcaddr6;\n\nstruct ifacaddr6;\n\nstruct inet6_dev {\n\tstruct net_device *dev;\n\tstruct list_head addr_list;\n\tstruct ifmcaddr6 *mc_list;\n\tstruct ifmcaddr6 *mc_tomb;\n\tspinlock_t mc_lock;\n\tunsigned char mc_qrv;\n\tunsigned char mc_gq_running;\n\tunsigned char mc_ifc_count;\n\tunsigned char mc_dad_count;\n\tlong unsigned int mc_v1_seen;\n\tlong unsigned int mc_qi;\n\tlong unsigned int mc_qri;\n\tlong unsigned int mc_maxdelay;\n\tstruct timer_list mc_gq_timer;\n\tstruct timer_list mc_ifc_timer;\n\tstruct timer_list mc_dad_timer;\n\tstruct ifacaddr6 *ac_list;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\t__u32 if_flags;\n\tint dead;\n\tu32 desync_factor;\n\tstruct list_head tempaddr_list;\n\tstruct in6_addr token;\n\tstruct neigh_parms *nd_parms;\n\tstruct ipv6_devconf cnf;\n\tstruct ipv6_devstat stats;\n\tstruct timer_list rs_timer;\n\t__s32 rs_interval;\n\t__u8 rs_probes;\n\tlong unsigned int tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_proto;\n\nstruct tcf_block;\n\nstruct mini_Qdisc {\n\tstruct tcf_proto *filter_list;\n\tstruct tcf_block *block;\n\tstruct gnet_stats_basic_cpu *cpu_bstats;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tstruct callback_head rcu;\n};\n\nstruct rtnl_link_ops {\n\tstruct list_head list;\n\tconst char *kind;\n\tsize_t priv_size;\n\tvoid (*setup)(struct net_device *);\n\tunsigned int maxtype;\n\tconst struct nla_policy *policy;\n\tint (*validate)(struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tint (*newlink)(struct net *, struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tint (*changelink)(struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*dellink)(struct net_device *, struct list_head *);\n\tsize_t (*get_size)(const struct net_device *);\n\tint (*fill_info)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_xstats_size)(const struct net_device *);\n\tint (*fill_xstats)(struct sk_buff *, const struct net_device *);\n\tunsigned int (*get_num_tx_queues)();\n\tunsigned int (*get_num_rx_queues)();\n\tunsigned int slave_maxtype;\n\tconst struct nla_policy *slave_policy;\n\tint (*slave_changelink)(struct net_device *, struct net_device *, struct nlattr **, struct nlattr **, struct netlink_ext_ack *);\n\tsize_t (*get_slave_size)(const struct net_device *, const struct net_device *);\n\tint (*fill_slave_info)(struct sk_buff *, const struct net_device *, const struct net_device *);\n\tstruct net * (*get_link_net)(const struct net_device *);\n\tsize_t (*get_linkxstats_size)(const struct net_device *, int);\n\tint (*fill_linkxstats)(struct sk_buff *, const struct net_device *, int *, int);\n};\n\nstruct sd_flow_limit {\n\tu64 count;\n\tunsigned int num_buckets;\n\tunsigned int history_head;\n\tu16 history[128];\n\tu8 buckets[0];\n};\n\nstruct softnet_data {\n\tstruct list_head poll_list;\n\tstruct sk_buff_head process_queue;\n\tunsigned int processed;\n\tunsigned int time_squeeze;\n\tunsigned int received_rps;\n\tstruct softnet_data *rps_ipi_list;\n\tstruct sd_flow_limit *flow_limit;\n\tstruct Qdisc *output_queue;\n\tstruct Qdisc **output_queue_tailp;\n\tstruct sk_buff *completion_queue;\n\tstruct {\n\t\tu16 recursion;\n\t\tu8 more;\n\t} xmit;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int input_queue_head;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t csd;\n\tstruct softnet_data *rps_ipi_next;\n\tunsigned int cpu;\n\tunsigned int input_queue_tail;\n\tunsigned int dropped;\n\tstruct sk_buff_head input_pkt_queue;\n\tstruct napi_struct backlog;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nenum {\n\tRTAX_UNSPEC = 0,\n\tRTAX_LOCK = 1,\n\tRTAX_MTU = 2,\n\tRTAX_WINDOW = 3,\n\tRTAX_RTT = 4,\n\tRTAX_RTTVAR = 5,\n\tRTAX_SSTHRESH = 6,\n\tRTAX_CWND = 7,\n\tRTAX_ADVMSS = 8,\n\tRTAX_REORDERING = 9,\n\tRTAX_HOPLIMIT = 10,\n\tRTAX_INITCWND = 11,\n\tRTAX_FEATURES = 12,\n\tRTAX_RTO_MIN = 13,\n\tRTAX_INITRWND = 14,\n\tRTAX_QUICKACK = 15,\n\tRTAX_CC_ALGO = 16,\n\tRTAX_FASTOPEN_NO_COOKIE = 17,\n\t__RTAX_MAX = 18,\n};\n\nstruct tcmsg {\n\tunsigned char tcm_family;\n\tunsigned char tcm__pad1;\n\tshort unsigned int tcm__pad2;\n\tint tcm_ifindex;\n\t__u32 tcm_handle;\n\t__u32 tcm_parent;\n\t__u32 tcm_info;\n};\n\nstruct gnet_stats_basic_cpu {\n\tstruct gnet_stats_basic_packed bstats;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct gnet_dump {\n\tspinlock_t *lock;\n\tstruct sk_buff *skb;\n\tstruct nlattr *tail;\n\tint compat_tc_stats;\n\tint compat_xstats;\n\tint padattr;\n\tvoid *xstats;\n\tint xstats_len;\n\tstruct tc_stats tc_stats;\n};\n\nstruct netlink_range_validation {\n\tu64 min;\n\tu64 max;\n};\n\nstruct netlink_range_validation_signed {\n\ts64 min;\n\ts64 max;\n};\n\nstruct nla_policy {\n\tu8 type;\n\tu8 validation_type;\n\tu16 len;\n\tunion {\n\t\tconst u32 bitfield32_valid;\n\t\tconst char *reject_message;\n\t\tconst struct nla_policy *nested_policy;\n\t\tstruct netlink_range_validation *range;\n\t\tstruct netlink_range_validation_signed *range_signed;\n\t\tstruct {\n\t\t\ts16 min;\n\t\t\ts16 max;\n\t\t};\n\t\tint (*validate)(const struct nlattr *, struct netlink_ext_ack *);\n\t\tu16 strict_start_type;\n\t};\n};\n\nstruct nl_info {\n\tstruct nlmsghdr *nlh;\n\tstruct net *nl_net;\n\tu32 portid;\n\tu8 skip_notify: 1;\n\tu8 skip_notify_kernel: 1;\n};\n\nenum flow_action_hw_stats_bit {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE_BIT = 0,\n\tFLOW_ACTION_HW_STATS_DELAYED_BIT = 1,\n\tFLOW_ACTION_HW_STATS_DISABLED_BIT = 2,\n\tFLOW_ACTION_HW_STATS_NUM_BITS = 3,\n};\n\nstruct flow_block {\n\tstruct list_head cb_list;\n};\n\ntypedef int flow_setup_cb_t(enum tc_setup_type, void *, void *);\n\nstruct qdisc_size_table {\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct tc_sizespec szopts;\n\tint refcnt;\n\tu16 data[0];\n};\n\nstruct Qdisc_class_ops;\n\nstruct Qdisc_ops {\n\tstruct Qdisc_ops *next;\n\tconst struct Qdisc_class_ops *cl_ops;\n\tchar id[16];\n\tint priv_size;\n\tunsigned int static_flags;\n\tint (*enqueue)(struct sk_buff *, struct Qdisc *, struct sk_buff **);\n\tstruct sk_buff * (*dequeue)(struct Qdisc *);\n\tstruct sk_buff * (*peek)(struct Qdisc *);\n\tint (*init)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*reset)(struct Qdisc *);\n\tvoid (*destroy)(struct Qdisc *);\n\tint (*change)(struct Qdisc *, struct nlattr *, struct netlink_ext_ack *);\n\tvoid (*attach)(struct Qdisc *);\n\tint (*change_tx_queue_len)(struct Qdisc *, unsigned int);\n\tint (*dump)(struct Qdisc *, struct sk_buff *);\n\tint (*dump_stats)(struct Qdisc *, struct gnet_dump *);\n\tvoid (*ingress_block_set)(struct Qdisc *, u32);\n\tvoid (*egress_block_set)(struct Qdisc *, u32);\n\tu32 (*ingress_block_get)(struct Qdisc *);\n\tu32 (*egress_block_get)(struct Qdisc *);\n\tstruct module *owner;\n};\n\nstruct qdisc_walker;\n\nstruct Qdisc_class_ops {\n\tunsigned int flags;\n\tstruct netdev_queue * (*select_queue)(struct Qdisc *, struct tcmsg *);\n\tint (*graft)(struct Qdisc *, long unsigned int, struct Qdisc *, struct Qdisc **, struct netlink_ext_ack *);\n\tstruct Qdisc * (*leaf)(struct Qdisc *, long unsigned int);\n\tvoid (*qlen_notify)(struct Qdisc *, long unsigned int);\n\tlong unsigned int (*find)(struct Qdisc *, u32);\n\tint (*change)(struct Qdisc *, u32, u32, struct nlattr **, long unsigned int *, struct netlink_ext_ack *);\n\tint (*delete)(struct Qdisc *, long unsigned int);\n\tvoid (*walk)(struct Qdisc *, struct qdisc_walker *);\n\tstruct tcf_block * (*tcf_block)(struct Qdisc *, long unsigned int, struct netlink_ext_ack *);\n\tlong unsigned int (*bind_tcf)(struct Qdisc *, long unsigned int, u32);\n\tvoid (*unbind_tcf)(struct Qdisc *, long unsigned int);\n\tint (*dump)(struct Qdisc *, long unsigned int, struct sk_buff *, struct tcmsg *);\n\tint (*dump_stats)(struct Qdisc *, long unsigned int, struct gnet_dump *);\n};\n\nstruct tcf_chain;\n\nstruct tcf_block {\n\tstruct mutex lock;\n\tstruct list_head chain_list;\n\tu32 index;\n\tu32 classid;\n\trefcount_t refcnt;\n\tstruct net *net;\n\tstruct Qdisc *q;\n\tstruct rw_semaphore cb_lock;\n\tstruct flow_block flow_block;\n\tstruct list_head owner_list;\n\tbool keep_dst;\n\tatomic_t offloadcnt;\n\tunsigned int nooffloaddevcnt;\n\tunsigned int lockeddevcnt;\n\tstruct {\n\t\tstruct tcf_chain *chain;\n\t\tstruct list_head filter_chain_list;\n\t} chain0;\n\tstruct callback_head rcu;\n\tstruct hlist_head proto_destroy_ht[128];\n\tstruct mutex proto_destroy_lock;\n};\n\nstruct tcf_result;\n\nstruct tcf_proto_ops;\n\nstruct tcf_proto {\n\tstruct tcf_proto *next;\n\tvoid *root;\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\t__be16 protocol;\n\tu32 prio;\n\tvoid *data;\n\tconst struct tcf_proto_ops *ops;\n\tstruct tcf_chain *chain;\n\tspinlock_t lock;\n\tbool deleting;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct hlist_node destroy_ht_node;\n};\n\nstruct tcf_result {\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int class;\n\t\t\tu32 classid;\n\t\t};\n\t\tconst struct tcf_proto *goto_tp;\n\t\tstruct {\n\t\t\tbool ingress;\n\t\t\tstruct gnet_stats_queue *qstats;\n\t\t};\n\t};\n};\n\nstruct tcf_walker;\n\nstruct tcf_proto_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tint (*classify)(struct sk_buff *, const struct tcf_proto *, struct tcf_result *);\n\tint (*init)(struct tcf_proto *);\n\tvoid (*destroy)(struct tcf_proto *, bool, struct netlink_ext_ack *);\n\tvoid * (*get)(struct tcf_proto *, u32);\n\tvoid (*put)(struct tcf_proto *, void *);\n\tint (*change)(struct net *, struct sk_buff *, struct tcf_proto *, long unsigned int, u32, struct nlattr **, void **, bool, bool, struct netlink_ext_ack *);\n\tint (*delete)(struct tcf_proto *, void *, bool *, bool, struct netlink_ext_ack *);\n\tbool (*delete_empty)(struct tcf_proto *);\n\tvoid (*walk)(struct tcf_proto *, struct tcf_walker *, bool);\n\tint (*reoffload)(struct tcf_proto *, bool, flow_setup_cb_t *, void *, struct netlink_ext_ack *);\n\tvoid (*hw_add)(struct tcf_proto *, void *);\n\tvoid (*hw_del)(struct tcf_proto *, void *);\n\tvoid (*bind_class)(void *, u32, long unsigned int, void *, long unsigned int);\n\tvoid * (*tmplt_create)(struct net *, struct tcf_chain *, struct nlattr **, struct netlink_ext_ack *);\n\tvoid (*tmplt_destroy)(void *);\n\tint (*dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*terse_dump)(struct net *, struct tcf_proto *, void *, struct sk_buff *, struct tcmsg *, bool);\n\tint (*tmplt_dump)(struct sk_buff *, struct net *, void *);\n\tstruct module *owner;\n\tint flags;\n};\n\nstruct tcf_chain {\n\tstruct mutex filter_chain_lock;\n\tstruct tcf_proto *filter_chain;\n\tstruct list_head list;\n\tstruct tcf_block *block;\n\tu32 index;\n\tunsigned int refcnt;\n\tunsigned int action_refcnt;\n\tbool explicitly_created;\n\tbool flushing;\n\tconst struct tcf_proto_ops *tmplt_ops;\n\tvoid *tmplt_priv;\n\tstruct callback_head rcu;\n};\n\nstruct sock_fprog_kern {\n\tu16 len;\n\tstruct sock_filter *filter;\n};\n\nstruct sk_filter {\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tstruct bpf_prog *prog;\n};\n\nstruct bpf_redirect_info {\n\tu32 flags;\n\tu32 tgt_index;\n\tvoid *tgt_value;\n\tstruct bpf_map *map;\n\tu32 kern_flags;\n};\n\nenum {\n\tNEIGH_VAR_MCAST_PROBES = 0,\n\tNEIGH_VAR_UCAST_PROBES = 1,\n\tNEIGH_VAR_APP_PROBES = 2,\n\tNEIGH_VAR_MCAST_REPROBES = 3,\n\tNEIGH_VAR_RETRANS_TIME = 4,\n\tNEIGH_VAR_BASE_REACHABLE_TIME = 5,\n\tNEIGH_VAR_DELAY_PROBE_TIME = 6,\n\tNEIGH_VAR_GC_STALETIME = 7,\n\tNEIGH_VAR_QUEUE_LEN_BYTES = 8,\n\tNEIGH_VAR_PROXY_QLEN = 9,\n\tNEIGH_VAR_ANYCAST_DELAY = 10,\n\tNEIGH_VAR_PROXY_DELAY = 11,\n\tNEIGH_VAR_LOCKTIME = 12,\n\tNEIGH_VAR_QUEUE_LEN = 13,\n\tNEIGH_VAR_RETRANS_TIME_MS = 14,\n\tNEIGH_VAR_BASE_REACHABLE_TIME_MS = 15,\n\tNEIGH_VAR_GC_INTERVAL = 16,\n\tNEIGH_VAR_GC_THRESH1 = 17,\n\tNEIGH_VAR_GC_THRESH2 = 18,\n\tNEIGH_VAR_GC_THRESH3 = 19,\n\tNEIGH_VAR_MAX = 20,\n};\n\nstruct pneigh_entry;\n\nstruct neigh_statistics;\n\nstruct neigh_hash_table;\n\nstruct neigh_table {\n\tint family;\n\tunsigned int entry_size;\n\tunsigned int key_len;\n\t__be16 protocol;\n\t__u32 (*hash)(const void *, const struct net_device *, __u32 *);\n\tbool (*key_eq)(const struct neighbour *, const void *);\n\tint (*constructor)(struct neighbour *);\n\tint (*pconstructor)(struct pneigh_entry *);\n\tvoid (*pdestructor)(struct pneigh_entry *);\n\tvoid (*proxy_redo)(struct sk_buff *);\n\tbool (*allow_add)(const struct net_device *, struct netlink_ext_ack *);\n\tchar *id;\n\tstruct neigh_parms parms;\n\tstruct list_head parms_list;\n\tint gc_interval;\n\tint gc_thresh1;\n\tint gc_thresh2;\n\tint gc_thresh3;\n\tlong unsigned int last_flush;\n\tstruct delayed_work gc_work;\n\tstruct timer_list proxy_timer;\n\tstruct sk_buff_head proxy_queue;\n\tatomic_t entries;\n\tatomic_t gc_entries;\n\tstruct list_head gc_list;\n\trwlock_t lock;\n\tlong unsigned int last_rand;\n\tstruct neigh_statistics *stats;\n\tstruct neigh_hash_table *nht;\n\tstruct pneigh_entry **phash_buckets;\n};\n\nstruct neigh_statistics {\n\tlong unsigned int allocs;\n\tlong unsigned int destroys;\n\tlong unsigned int hash_grows;\n\tlong unsigned int res_failed;\n\tlong unsigned int lookups;\n\tlong unsigned int hits;\n\tlong unsigned int rcv_probes_mcast;\n\tlong unsigned int rcv_probes_ucast;\n\tlong unsigned int periodic_gc_runs;\n\tlong unsigned int forced_gc_runs;\n\tlong unsigned int unres_discards;\n\tlong unsigned int table_fulls;\n};\n\nstruct neigh_ops {\n\tint family;\n\tvoid (*solicit)(struct neighbour *, struct sk_buff *);\n\tvoid (*error_report)(struct neighbour *, struct sk_buff *);\n\tint (*output)(struct neighbour *, struct sk_buff *);\n\tint (*connected_output)(struct neighbour *, struct sk_buff *);\n};\n\nstruct pneigh_entry {\n\tstruct pneigh_entry *next;\n\tpossible_net_t net;\n\tstruct net_device *dev;\n\tu8 flags;\n\tu8 protocol;\n\tu8 key[0];\n};\n\nstruct neigh_hash_table {\n\tstruct neighbour **hash_buckets;\n\tunsigned int hash_shift;\n\t__u32 hash_rnd[4];\n\tstruct callback_head rcu;\n};\n\nstruct dst_metrics {\n\tu32 metrics[17];\n\trefcount_t refcnt;\n};\n\nenum {\n\tTCP_ESTABLISHED = 1,\n\tTCP_SYN_SENT = 2,\n\tTCP_SYN_RECV = 3,\n\tTCP_FIN_WAIT1 = 4,\n\tTCP_FIN_WAIT2 = 5,\n\tTCP_TIME_WAIT = 6,\n\tTCP_CLOSE = 7,\n\tTCP_CLOSE_WAIT = 8,\n\tTCP_LAST_ACK = 9,\n\tTCP_LISTEN = 10,\n\tTCP_CLOSING = 11,\n\tTCP_NEW_SYN_RECV = 12,\n\tTCP_MAX_STATES = 13,\n};\n\nstruct fib_rule_hdr {\n\t__u8 family;\n\t__u8 dst_len;\n\t__u8 src_len;\n\t__u8 tos;\n\t__u8 table;\n\t__u8 res1;\n\t__u8 res2;\n\t__u8 action;\n\t__u32 flags;\n};\n\nstruct fib_rule_port_range {\n\t__u16 start;\n\t__u16 end;\n};\n\nstruct fib_kuid_range {\n\tkuid_t start;\n\tkuid_t end;\n};\n\nstruct fib_rule {\n\tstruct list_head list;\n\tint iifindex;\n\tint oifindex;\n\tu32 mark;\n\tu32 mark_mask;\n\tu32 flags;\n\tu32 table;\n\tu8 action;\n\tu8 l3mdev;\n\tu8 proto;\n\tu8 ip_proto;\n\tu32 target;\n\t__be64 tun_id;\n\tstruct fib_rule *ctarget;\n\tstruct net *fr_net;\n\trefcount_t refcnt;\n\tu32 pref;\n\tint suppress_ifgroup;\n\tint suppress_prefixlen;\n\tchar iifname[16];\n\tchar oifname[16];\n\tstruct fib_kuid_range uid_range;\n\tstruct fib_rule_port_range sport_range;\n\tstruct fib_rule_port_range dport_range;\n\tstruct callback_head rcu;\n};\n\nstruct fib_lookup_arg {\n\tvoid *lookup_ptr;\n\tconst void *lookup_data;\n\tvoid *result;\n\tstruct fib_rule *rule;\n\tu32 table;\n\tint flags;\n};\n\nstruct smc_hashinfo;\n\nstruct request_sock_ops;\n\nstruct timewait_sock_ops;\n\nstruct udp_table;\n\nstruct raw_hashinfo;\n\nstruct proto {\n\tvoid (*close)(struct sock *, long int);\n\tint (*pre_connect)(struct sock *, struct sockaddr *, int);\n\tint (*connect)(struct sock *, struct sockaddr *, int);\n\tint (*disconnect)(struct sock *, int);\n\tstruct sock * (*accept)(struct sock *, int, int *, bool);\n\tint (*ioctl)(struct sock *, int, long unsigned int);\n\tint (*init)(struct sock *);\n\tvoid (*destroy)(struct sock *);\n\tvoid (*shutdown)(struct sock *, int);\n\tint (*setsockopt)(struct sock *, int, int, char *, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*keepalive)(struct sock *, int);\n\tint (*compat_setsockopt)(struct sock *, int, int, char *, unsigned int);\n\tint (*compat_getsockopt)(struct sock *, int, int, char *, int *);\n\tint (*compat_ioctl)(struct sock *, unsigned int, long unsigned int);\n\tint (*sendmsg)(struct sock *, struct msghdr *, size_t);\n\tint (*recvmsg)(struct sock *, struct msghdr *, size_t, int, int, int *);\n\tint (*sendpage)(struct sock *, struct page *, int, size_t, int);\n\tint (*bind)(struct sock *, struct sockaddr *, int);\n\tint (*bind_add)(struct sock *, struct sockaddr *, int);\n\tint (*backlog_rcv)(struct sock *, struct sk_buff *);\n\tvoid (*release_cb)(struct sock *);\n\tint (*hash)(struct sock *);\n\tvoid (*unhash)(struct sock *);\n\tvoid (*rehash)(struct sock *);\n\tint (*get_port)(struct sock *, short unsigned int);\n\tunsigned int inuse_idx;\n\tbool (*stream_memory_free)(const struct sock *, int);\n\tbool (*stream_memory_read)(const struct sock *);\n\tvoid (*enter_memory_pressure)(struct sock *);\n\tvoid (*leave_memory_pressure)(struct sock *);\n\tatomic_long_t *memory_allocated;\n\tstruct percpu_counter *sockets_allocated;\n\tlong unsigned int *memory_pressure;\n\tlong int *sysctl_mem;\n\tint *sysctl_wmem;\n\tint *sysctl_rmem;\n\tu32 sysctl_wmem_offset;\n\tu32 sysctl_rmem_offset;\n\tint max_header;\n\tbool no_autobind;\n\tstruct kmem_cache *slab;\n\tunsigned int obj_size;\n\tslab_flags_t slab_flags;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tstruct percpu_counter *orphan_count;\n\tstruct request_sock_ops *rsk_prot;\n\tstruct timewait_sock_ops *twsk_prot;\n\tunion {\n\t\tstruct inet_hashinfo *hashinfo;\n\t\tstruct udp_table *udp_table;\n\t\tstruct raw_hashinfo *raw_hash;\n\t\tstruct smc_hashinfo *smc_hash;\n\t} h;\n\tstruct module *owner;\n\tchar name[32];\n\tstruct list_head node;\n\tint (*diag_destroy)(struct sock *, int);\n};\n\nstruct request_sock;\n\nstruct request_sock_ops {\n\tint family;\n\tunsigned int obj_size;\n\tstruct kmem_cache *slab;\n\tchar *slab_name;\n\tint (*rtx_syn_ack)(const struct sock *, struct request_sock *);\n\tvoid (*send_ack)(const struct sock *, struct sk_buff *, struct request_sock *);\n\tvoid (*send_reset)(const struct sock *, struct sk_buff *);\n\tvoid (*destructor)(struct request_sock *);\n\tvoid (*syn_ack_timeout)(const struct request_sock *);\n};\n\nstruct timewait_sock_ops {\n\tstruct kmem_cache *twsk_slab;\n\tchar *twsk_slab_name;\n\tunsigned int twsk_obj_size;\n\tint (*twsk_unique)(struct sock *, struct sock *, void *);\n\tvoid (*twsk_destructor)(struct sock *);\n};\n\nstruct request_sock {\n\tstruct sock_common __req_common;\n\tstruct request_sock *dl_next;\n\tu16 mss;\n\tu8 num_retrans;\n\tu8 cookie_ts: 1;\n\tu8 num_timeout: 7;\n\tu32 ts_recent;\n\tstruct timer_list rsk_timer;\n\tconst struct request_sock_ops *rsk_ops;\n\tstruct sock *sk;\n\tu32 *saved_syn;\n\tu32 secid;\n\tu32 peer_secid;\n};\n\nenum tsq_enum {\n\tTSQ_THROTTLED = 0,\n\tTSQ_QUEUED = 1,\n\tTCP_TSQ_DEFERRED = 2,\n\tTCP_WRITE_TIMER_DEFERRED = 3,\n\tTCP_DELACK_TIMER_DEFERRED = 4,\n\tTCP_MTU_REDUCED_DEFERRED = 5,\n};\n\nstruct static_key_false_deferred {\n\tstruct static_key_false key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nstruct ip6_sf_list {\n\tstruct ip6_sf_list *sf_next;\n\tstruct in6_addr sf_addr;\n\tlong unsigned int sf_count[2];\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n};\n\nstruct ifmcaddr6 {\n\tstruct in6_addr mca_addr;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *next;\n\tstruct ip6_sf_list *mca_sources;\n\tstruct ip6_sf_list *mca_tomb;\n\tunsigned int mca_sfmode;\n\tunsigned char mca_crcount;\n\tlong unsigned int mca_sfcount[2];\n\tstruct timer_list mca_timer;\n\tunsigned int mca_flags;\n\tint mca_users;\n\trefcount_t mca_refcnt;\n\tspinlock_t mca_lock;\n\tlong unsigned int mca_cstamp;\n\tlong unsigned int mca_tstamp;\n};\n\nstruct ifacaddr6 {\n\tstruct in6_addr aca_addr;\n\tstruct fib6_info *aca_rt;\n\tstruct ifacaddr6 *aca_next;\n\tstruct hlist_node aca_addr_lst;\n\tint aca_users;\n\trefcount_t aca_refcnt;\n\tlong unsigned int aca_cstamp;\n\tlong unsigned int aca_tstamp;\n\tstruct callback_head rcu;\n};\n\nstruct fib6_result;\n\nstruct fib6_nh;\n\nstruct fib6_config;\n\nstruct ipv6_stub {\n\tint (*ipv6_sock_mc_join)(struct sock *, int, const struct in6_addr *);\n\tint (*ipv6_sock_mc_drop)(struct sock *, int, const struct in6_addr *);\n\tstruct dst_entry * (*ipv6_dst_lookup_flow)(struct net *, const struct sock *, struct flowi6 *, const struct in6_addr *);\n\tint (*ipv6_route_input)(struct sk_buff *);\n\tstruct fib6_table * (*fib6_get_table)(struct net *, u32);\n\tint (*fib6_lookup)(struct net *, int, struct flowi6 *, struct fib6_result *, int);\n\tint (*fib6_table_lookup)(struct net *, struct fib6_table *, int, struct flowi6 *, struct fib6_result *, int);\n\tvoid (*fib6_select_path)(const struct net *, struct fib6_result *, struct flowi6 *, int, bool, const struct sk_buff *, int);\n\tu32 (*ip6_mtu_from_fib6)(const struct fib6_result *, const struct in6_addr *, const struct in6_addr *);\n\tint (*fib6_nh_init)(struct net *, struct fib6_nh *, struct fib6_config *, gfp_t, struct netlink_ext_ack *);\n\tvoid (*fib6_nh_release)(struct fib6_nh *);\n\tvoid (*fib6_update_sernum)(struct net *, struct fib6_info *);\n\tint (*ip6_del_rt)(struct net *, struct fib6_info *, bool);\n\tvoid (*fib6_rt_update)(struct net *, struct fib6_info *, struct nl_info *);\n\tvoid (*udpv6_encap_enable)();\n\tvoid (*ndisc_send_na)(struct net_device *, const struct in6_addr *, const struct in6_addr *, bool, bool, bool, bool);\n\tvoid (*xfrm6_local_rxpmtu)(struct sk_buff *, u32);\n\tint (*xfrm6_udp_encap_rcv)(struct sock *, struct sk_buff *);\n\tint (*xfrm6_rcv_encap)(struct sk_buff *, int, __be32, int);\n\tstruct neigh_table *nd_tbl;\n};\n\nstruct fib6_result {\n\tstruct fib6_nh *nh;\n\tstruct fib6_info *f6i;\n\tu32 fib6_flags;\n\tu8 fib6_type;\n\tstruct rt6_info *rt6;\n};\n\nstruct ipv6_bpf_stub {\n\tint (*inet6_bind)(struct sock *, struct sockaddr *, int, u32);\n\tstruct sock * (*udp6_lib_lookup)(struct net *, const struct in6_addr *, __be16, const struct in6_addr *, __be16, int, int, struct udp_table *, struct sk_buff *);\n};\n\nenum {\n\t__ND_OPT_PREFIX_INFO_END = 0,\n\tND_OPT_SOURCE_LL_ADDR = 1,\n\tND_OPT_TARGET_LL_ADDR = 2,\n\tND_OPT_PREFIX_INFO = 3,\n\tND_OPT_REDIRECT_HDR = 4,\n\tND_OPT_MTU = 5,\n\tND_OPT_NONCE = 14,\n\t__ND_OPT_ARRAY_MAX = 15,\n\tND_OPT_ROUTE_INFO = 24,\n\tND_OPT_RDNSS = 25,\n\tND_OPT_DNSSL = 31,\n\tND_OPT_6CO = 34,\n\tND_OPT_CAPTIVE_PORTAL = 37,\n\tND_OPT_PREF64 = 38,\n\t__ND_OPT_MAX = 39,\n};\n\nstruct nd_opt_hdr {\n\t__u8 nd_opt_type;\n\t__u8 nd_opt_len;\n};\n\nstruct ndisc_options {\n\tstruct nd_opt_hdr *nd_opt_array[15];\n\tstruct nd_opt_hdr *nd_useropts;\n\tstruct nd_opt_hdr *nd_useropts_end;\n};\n\nstruct prefix_info {\n\t__u8 type;\n\t__u8 length;\n\t__u8 prefix_len;\n\t__u8 reserved: 6;\n\t__u8 autoconf: 1;\n\t__u8 onlink: 1;\n\t__be32 valid;\n\t__be32 prefered;\n\t__be32 reserved2;\n\tstruct in6_addr prefix;\n};\n\nstruct ip6_ra_chain {\n\tstruct ip6_ra_chain *next;\n\tstruct sock *sk;\n\tint sel;\n\tvoid (*destructor)(struct sock *);\n};\n\nstruct rpc_xprt_iter_ops {\n\tvoid (*xpi_rewind)(struct rpc_xprt_iter *);\n\tstruct rpc_xprt * (*xpi_xprt)(struct rpc_xprt_iter *);\n\tstruct rpc_xprt * (*xpi_next)(struct rpc_xprt_iter *);\n};\n\nstruct rpc_version {\n\tu32 number;\n\tunsigned int nrprocs;\n\tconst struct rpc_procinfo *procs;\n\tunsigned int *counts;\n};\n\nstruct nfs_fh {\n\tshort unsigned int size;\n\tunsigned char data[128];\n};\n\nenum nfs3_stable_how {\n\tNFS_UNSTABLE = 0,\n\tNFS_DATA_SYNC = 1,\n\tNFS_FILE_SYNC = 2,\n\tNFS_INVALID_STABLE_HOW = 4294967295,\n};\n\nstruct nfs4_label {\n\tuint32_t lfs;\n\tuint32_t pi;\n\tu32 len;\n\tchar *label;\n};\n\ntypedef struct {\n\tchar data[8];\n} nfs4_verifier;\n\nstruct nfs4_stateid_struct {\n\tunion {\n\t\tchar data[16];\n\t\tstruct {\n\t\t\t__be32 seqid;\n\t\t\tchar other[12];\n\t\t};\n\t};\n\tenum {\n\t\tNFS4_INVALID_STATEID_TYPE = 0,\n\t\tNFS4_SPECIAL_STATEID_TYPE = 1,\n\t\tNFS4_OPEN_STATEID_TYPE = 2,\n\t\tNFS4_LOCK_STATEID_TYPE = 3,\n\t\tNFS4_DELEGATION_STATEID_TYPE = 4,\n\t\tNFS4_LAYOUT_STATEID_TYPE = 5,\n\t\tNFS4_PNFS_DS_STATEID_TYPE = 6,\n\t\tNFS4_REVOKED_STATEID_TYPE = 7,\n\t} type;\n};\n\ntypedef struct nfs4_stateid_struct nfs4_stateid;\n\nenum nfs_opnum4 {\n\tOP_ACCESS = 3,\n\tOP_CLOSE = 4,\n\tOP_COMMIT = 5,\n\tOP_CREATE = 6,\n\tOP_DELEGPURGE = 7,\n\tOP_DELEGRETURN = 8,\n\tOP_GETATTR = 9,\n\tOP_GETFH = 10,\n\tOP_LINK = 11,\n\tOP_LOCK = 12,\n\tOP_LOCKT = 13,\n\tOP_LOCKU = 14,\n\tOP_LOOKUP = 15,\n\tOP_LOOKUPP = 16,\n\tOP_NVERIFY = 17,\n\tOP_OPEN = 18,\n\tOP_OPENATTR = 19,\n\tOP_OPEN_CONFIRM = 20,\n\tOP_OPEN_DOWNGRADE = 21,\n\tOP_PUTFH = 22,\n\tOP_PUTPUBFH = 23,\n\tOP_PUTROOTFH = 24,\n\tOP_READ = 25,\n\tOP_READDIR = 26,\n\tOP_READLINK = 27,\n\tOP_REMOVE = 28,\n\tOP_RENAME = 29,\n\tOP_RENEW = 30,\n\tOP_RESTOREFH = 31,\n\tOP_SAVEFH = 32,\n\tOP_SECINFO = 33,\n\tOP_SETATTR = 34,\n\tOP_SETCLIENTID = 35,\n\tOP_SETCLIENTID_CONFIRM = 36,\n\tOP_VERIFY = 37,\n\tOP_WRITE = 38,\n\tOP_RELEASE_LOCKOWNER = 39,\n\tOP_BACKCHANNEL_CTL = 40,\n\tOP_BIND_CONN_TO_SESSION = 41,\n\tOP_EXCHANGE_ID = 42,\n\tOP_CREATE_SESSION = 43,\n\tOP_DESTROY_SESSION = 44,\n\tOP_FREE_STATEID = 45,\n\tOP_GET_DIR_DELEGATION = 46,\n\tOP_GETDEVICEINFO = 47,\n\tOP_GETDEVICELIST = 48,\n\tOP_LAYOUTCOMMIT = 49,\n\tOP_LAYOUTGET = 50,\n\tOP_LAYOUTRETURN = 51,\n\tOP_SECINFO_NO_NAME = 52,\n\tOP_SEQUENCE = 53,\n\tOP_SET_SSV = 54,\n\tOP_TEST_STATEID = 55,\n\tOP_WANT_DELEGATION = 56,\n\tOP_DESTROY_CLIENTID = 57,\n\tOP_RECLAIM_COMPLETE = 58,\n\tOP_ALLOCATE = 59,\n\tOP_COPY = 60,\n\tOP_COPY_NOTIFY = 61,\n\tOP_DEALLOCATE = 62,\n\tOP_IO_ADVISE = 63,\n\tOP_LAYOUTERROR = 64,\n\tOP_LAYOUTSTATS = 65,\n\tOP_OFFLOAD_CANCEL = 66,\n\tOP_OFFLOAD_STATUS = 67,\n\tOP_READ_PLUS = 68,\n\tOP_SEEK = 69,\n\tOP_WRITE_SAME = 70,\n\tOP_CLONE = 71,\n\tOP_ILLEGAL = 10044,\n};\n\nstruct nfs4_string {\n\tunsigned int len;\n\tchar *data;\n};\n\nstruct nfs_fsid {\n\tuint64_t major;\n\tuint64_t minor;\n};\n\nstruct nfs4_threshold {\n\t__u32 bm;\n\t__u32 l_type;\n\t__u64 rd_sz;\n\t__u64 wr_sz;\n\t__u64 rd_io_sz;\n\t__u64 wr_io_sz;\n};\n\nstruct nfs_fattr {\n\tunsigned int valid;\n\tumode_t mode;\n\t__u32 nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tdev_t rdev;\n\t__u64 size;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 blocksize;\n\t\t\t__u32 blocks;\n\t\t} nfs2;\n\t\tstruct {\n\t\t\t__u64 used;\n\t\t} nfs3;\n\t} du;\n\tstruct nfs_fsid fsid;\n\t__u64 fileid;\n\t__u64 mounted_on_fileid;\n\tstruct timespec64 atime;\n\tstruct timespec64 mtime;\n\tstruct timespec64 ctime;\n\t__u64 change_attr;\n\t__u64 pre_change_attr;\n\t__u64 pre_size;\n\tstruct timespec64 pre_mtime;\n\tstruct timespec64 pre_ctime;\n\tlong unsigned int time_start;\n\tlong unsigned int gencount;\n\tstruct nfs4_string *owner_name;\n\tstruct nfs4_string *group_name;\n\tstruct nfs4_threshold *mdsthreshold;\n\tstruct nfs4_label *label;\n};\n\nstruct nfs_fsinfo {\n\tstruct nfs_fattr *fattr;\n\t__u32 rtmax;\n\t__u32 rtpref;\n\t__u32 rtmult;\n\t__u32 wtmax;\n\t__u32 wtpref;\n\t__u32 wtmult;\n\t__u32 dtpref;\n\t__u64 maxfilesize;\n\tstruct timespec64 time_delta;\n\t__u32 lease_time;\n\t__u32 nlayouttypes;\n\t__u32 layouttype[8];\n\t__u32 blksize;\n\t__u32 clone_blksize;\n};\n\nstruct nfs_fsstat {\n\tstruct nfs_fattr *fattr;\n\t__u64 tbytes;\n\t__u64 fbytes;\n\t__u64 abytes;\n\t__u64 tfiles;\n\t__u64 ffiles;\n\t__u64 afiles;\n};\n\nstruct nfs_pathconf {\n\tstruct nfs_fattr *fattr;\n\t__u32 max_link;\n\t__u32 max_namelen;\n};\n\nstruct nfs4_change_info {\n\tu32 atomic;\n\tu64 before;\n\tu64 after;\n};\n\nstruct nfs4_slot;\n\nstruct nfs4_sequence_args {\n\tstruct nfs4_slot *sa_slot;\n\tu8 sa_cache_this: 1;\n\tu8 sa_privileged: 1;\n};\n\nstruct nfs4_sequence_res {\n\tstruct nfs4_slot *sr_slot;\n\tlong unsigned int sr_timestamp;\n\tint sr_status;\n\tu32 sr_status_flags;\n\tu32 sr_highest_slotid;\n\tu32 sr_target_highest_slotid;\n};\n\nstruct nfs_open_context;\n\nstruct nfs_lock_context {\n\trefcount_t count;\n\tstruct list_head list;\n\tstruct nfs_open_context *open_context;\n\tfl_owner_t lockowner;\n\tatomic_t io_count;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs4_state;\n\nstruct nfs_open_context {\n\tstruct nfs_lock_context lock_context;\n\tfl_owner_t flock_owner;\n\tstruct dentry *dentry;\n\tconst struct cred *cred;\n\tstruct rpc_cred *ll_cred;\n\tstruct nfs4_state *state;\n\tfmode_t mode;\n\tlong unsigned int flags;\n\tint error;\n\tstruct list_head list;\n\tstruct nfs4_threshold *mdsthreshold;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_auth_info {\n\tunsigned int flavor_len;\n\trpc_authflavor_t flavors[12];\n};\n\nstruct pnfs_layoutdriver_type;\n\nstruct nfs_client;\n\nstruct nlm_host;\n\nstruct nfs_iostats;\n\nstruct nfs_server {\n\tstruct nfs_client *nfs_client;\n\tstruct list_head client_link;\n\tstruct list_head master_link;\n\tstruct rpc_clnt *client;\n\tstruct rpc_clnt *client_acl;\n\tstruct nlm_host *nlm_host;\n\tstruct nfs_iostats *io_stats;\n\tatomic_long_t writeback;\n\tint flags;\n\tunsigned int caps;\n\tunsigned int rsize;\n\tunsigned int rpages;\n\tunsigned int wsize;\n\tunsigned int wpages;\n\tunsigned int wtmult;\n\tunsigned int dtsize;\n\tshort unsigned int port;\n\tunsigned int bsize;\n\tunsigned int acregmin;\n\tunsigned int acregmax;\n\tunsigned int acdirmin;\n\tunsigned int acdirmax;\n\tunsigned int namelen;\n\tunsigned int options;\n\tunsigned int clone_blksize;\n\tstruct nfs_fsid fsid;\n\t__u64 maxfilesize;\n\tstruct timespec64 time_delta;\n\tlong unsigned int mount_time;\n\tstruct super_block *super;\n\tdev_t s_dev;\n\tstruct nfs_auth_info auth_info;\n\tu32 pnfs_blksize;\n\tu32 attr_bitmask[3];\n\tu32 attr_bitmask_nl[3];\n\tu32 exclcreat_bitmask[3];\n\tu32 cache_consistency_bitmask[3];\n\tu32 acl_bitmask;\n\tu32 fh_expire_type;\n\tstruct pnfs_layoutdriver_type *pnfs_curr_ld;\n\tstruct rpc_wait_queue roc_rpcwaitq;\n\tvoid *pnfs_ld_data;\n\tstruct rb_root state_owners;\n\tstruct ida openowner_id;\n\tstruct ida lockowner_id;\n\tstruct list_head state_owners_lru;\n\tstruct list_head layouts;\n\tstruct list_head delegations;\n\tstruct list_head ss_copies;\n\tlong unsigned int mig_gen;\n\tlong unsigned int mig_status;\n\tvoid (*destroy)(struct nfs_server *);\n\tatomic_t active;\n\tstruct __kernel_sockaddr_storage mountd_address;\n\tsize_t mountd_addrlen;\n\tu32 mountd_version;\n\tshort unsigned int mountd_port;\n\tshort unsigned int mountd_protocol;\n\tstruct rpc_wait_queue uoc_rpcwaitq;\n\tunsigned int read_hdrsize;\n\tconst struct cred *cred;\n};\n\nstruct nfs41_server_owner;\n\nstruct nfs41_server_scope;\n\nstruct nfs41_impl_id;\n\nstruct nfs_rpc_ops;\n\nstruct nfs_subversion;\n\nstruct idmap;\n\nstruct nfs4_minor_version_ops;\n\nstruct nfs4_slot_table;\n\nstruct nfs4_session;\n\nstruct nfs_client {\n\trefcount_t cl_count;\n\tatomic_t cl_mds_count;\n\tint cl_cons_state;\n\tlong unsigned int cl_res_state;\n\tlong unsigned int cl_flags;\n\tstruct __kernel_sockaddr_storage cl_addr;\n\tsize_t cl_addrlen;\n\tchar *cl_hostname;\n\tchar *cl_acceptor;\n\tstruct list_head cl_share_link;\n\tstruct list_head cl_superblocks;\n\tstruct rpc_clnt *cl_rpcclient;\n\tconst struct nfs_rpc_ops *rpc_ops;\n\tint cl_proto;\n\tstruct nfs_subversion *cl_nfs_mod;\n\tu32 cl_minorversion;\n\tunsigned int cl_nconnect;\n\tconst char *cl_principal;\n\tstruct list_head cl_ds_clients;\n\tu64 cl_clientid;\n\tnfs4_verifier cl_confirm;\n\tlong unsigned int cl_state;\n\tspinlock_t cl_lock;\n\tlong unsigned int cl_lease_time;\n\tlong unsigned int cl_last_renewal;\n\tstruct delayed_work cl_renewd;\n\tstruct rpc_wait_queue cl_rpcwaitq;\n\tstruct idmap *cl_idmap;\n\tconst char *cl_owner_id;\n\tu32 cl_cb_ident;\n\tconst struct nfs4_minor_version_ops *cl_mvops;\n\tlong unsigned int cl_mig_gen;\n\tstruct nfs4_slot_table *cl_slot_tbl;\n\tu32 cl_seqid;\n\tu32 cl_exchange_flags;\n\tstruct nfs4_session *cl_session;\n\tbool cl_preserve_clid;\n\tstruct nfs41_server_owner *cl_serverowner;\n\tstruct nfs41_server_scope *cl_serverscope;\n\tstruct nfs41_impl_id *cl_implid;\n\tlong unsigned int cl_sp4_flags;\n\tchar cl_ipaddr[48];\n\tstruct net *cl_net;\n\tstruct list_head pending_cb_stateids;\n};\n\nstruct nfs_write_verifier {\n\tchar data[8];\n};\n\nstruct nfs_writeverf {\n\tstruct nfs_write_verifier verifier;\n\tenum nfs3_stable_how committed;\n};\n\nstruct nfs_pgio_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct nfs_open_context *context;\n\tstruct nfs_lock_context *lock_context;\n\tnfs4_stateid stateid;\n\t__u64 offset;\n\t__u32 count;\n\tunsigned int pgbase;\n\tstruct page **pages;\n\tunion {\n\t\tunsigned int replen;\n\t\tstruct {\n\t\t\tconst u32 *bitmask;\n\t\t\tenum nfs3_stable_how stable;\n\t\t};\n\t};\n};\n\nstruct nfs_pgio_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\t__u32 count;\n\t__u32 op_status;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int replen;\n\t\t\tint eof;\n\t\t};\n\t\tstruct {\n\t\t\tstruct nfs_writeverf *verf;\n\t\t\tconst struct nfs_server *server;\n\t\t};\n\t};\n};\n\nstruct nfs_commitargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\t__u64 offset;\n\t__u32 count;\n\tconst u32 *bitmask;\n};\n\nstruct nfs_commitres {\n\tstruct nfs4_sequence_res seq_res;\n\t__u32 op_status;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_writeverf *verf;\n\tconst struct nfs_server *server;\n};\n\nstruct nfs_removeargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tstruct qstr name;\n};\n\nstruct nfs_removeres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_server *server;\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs4_change_info cinfo;\n};\n\nstruct nfs_renameargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *old_dir;\n\tconst struct nfs_fh *new_dir;\n\tconst struct qstr *old_name;\n\tconst struct qstr *new_name;\n};\n\nstruct nfs_renameres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_server *server;\n\tstruct nfs4_change_info old_cinfo;\n\tstruct nfs_fattr *old_fattr;\n\tstruct nfs4_change_info new_cinfo;\n\tstruct nfs_fattr *new_fattr;\n};\n\nstruct nfs_entry {\n\t__u64 ino;\n\t__u64 cookie;\n\t__u64 prev_cookie;\n\tconst char *name;\n\tunsigned int len;\n\tint eof;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_label *label;\n\tunsigned char d_type;\n\tstruct nfs_server *server;\n};\n\nstruct pnfs_ds_commit_info {};\n\nstruct nfs_page_array {\n\tstruct page **pagevec;\n\tunsigned int npages;\n\tstruct page *page_array[8];\n};\n\nstruct nfs_page;\n\nstruct pnfs_layout_segment;\n\nstruct nfs_pgio_completion_ops;\n\nstruct nfs_rw_ops;\n\nstruct nfs_io_completion;\n\nstruct nfs_direct_req;\n\nstruct nfs_pgio_header {\n\tstruct inode *inode;\n\tconst struct cred *cred;\n\tstruct list_head pages;\n\tstruct nfs_page *req;\n\tstruct nfs_writeverf verf;\n\tfmode_t rw_mode;\n\tstruct pnfs_layout_segment *lseg;\n\tloff_t io_start;\n\tconst struct rpc_call_ops *mds_ops;\n\tvoid (*release)(struct nfs_pgio_header *);\n\tconst struct nfs_pgio_completion_ops *completion_ops;\n\tconst struct nfs_rw_ops *rw_ops;\n\tstruct nfs_io_completion *io_completion;\n\tstruct nfs_direct_req *dreq;\n\tint pnfs_error;\n\tint error;\n\tunsigned int good_bytes;\n\tlong unsigned int flags;\n\tstruct rpc_task task;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_pgio_args args;\n\tstruct nfs_pgio_res res;\n\tlong unsigned int timestamp;\n\tint (*pgio_done_cb)(struct rpc_task *, struct nfs_pgio_header *);\n\t__u64 mds_offset;\n\tstruct nfs_page_array page_array;\n\tstruct nfs_client *ds_clp;\n\tint ds_commit_idx;\n\tint pgio_mirror_idx;\n};\n\nstruct nfs_pgio_completion_ops {\n\tvoid (*error_cleanup)(struct list_head *, int);\n\tvoid (*init_hdr)(struct nfs_pgio_header *);\n\tvoid (*completion)(struct nfs_pgio_header *);\n\tvoid (*reschedule_io)(struct nfs_pgio_header *);\n};\n\nstruct rpc_task_setup;\n\nstruct nfs_rw_ops {\n\tstruct nfs_pgio_header * (*rw_alloc_header)();\n\tvoid (*rw_free_header)(struct nfs_pgio_header *);\n\tint (*rw_done)(struct rpc_task *, struct nfs_pgio_header *, struct inode *);\n\tvoid (*rw_result)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*rw_initiate)(struct nfs_pgio_header *, struct rpc_message *, const struct nfs_rpc_ops *, struct rpc_task_setup *, int);\n};\n\nstruct nfs_mds_commit_info {\n\tatomic_t rpcs_out;\n\tatomic_long_t ncommit;\n\tstruct list_head list;\n};\n\nstruct nfs_commit_data;\n\nstruct nfs_commit_info;\n\nstruct nfs_commit_completion_ops {\n\tvoid (*completion)(struct nfs_commit_data *);\n\tvoid (*resched_write)(struct nfs_commit_info *, struct nfs_page *);\n};\n\nstruct nfs_commit_data {\n\tstruct rpc_task task;\n\tstruct inode *inode;\n\tconst struct cred *cred;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_writeverf verf;\n\tstruct list_head pages;\n\tstruct list_head list;\n\tstruct nfs_direct_req *dreq;\n\tstruct nfs_commitargs args;\n\tstruct nfs_commitres res;\n\tstruct nfs_open_context *context;\n\tstruct pnfs_layout_segment *lseg;\n\tstruct nfs_client *ds_clp;\n\tint ds_commit_index;\n\tloff_t lwb;\n\tconst struct rpc_call_ops *mds_ops;\n\tconst struct nfs_commit_completion_ops *completion_ops;\n\tint (*commit_done_cb)(struct rpc_task *, struct nfs_commit_data *);\n\tlong unsigned int flags;\n};\n\nstruct nfs_commit_info {\n\tstruct inode *inode;\n\tstruct nfs_mds_commit_info *mds;\n\tstruct pnfs_ds_commit_info *ds;\n\tstruct nfs_direct_req *dreq;\n\tconst struct nfs_commit_completion_ops *completion_ops;\n};\n\nstruct nfs_unlinkdata {\n\tstruct nfs_removeargs args;\n\tstruct nfs_removeres res;\n\tstruct dentry *dentry;\n\twait_queue_head_t wq;\n\tconst struct cred *cred;\n\tstruct nfs_fattr dir_attr;\n\tlong int timeout;\n};\n\nstruct nfs_renamedata {\n\tstruct nfs_renameargs args;\n\tstruct nfs_renameres res;\n\tconst struct cred *cred;\n\tstruct inode *old_dir;\n\tstruct dentry *old_dentry;\n\tstruct nfs_fattr old_fattr;\n\tstruct inode *new_dir;\n\tstruct dentry *new_dentry;\n\tstruct nfs_fattr new_fattr;\n\tvoid (*complete)(struct rpc_task *, struct nfs_renamedata *);\n\tlong int timeout;\n\tbool cancelled;\n};\n\nstruct nlmclnt_operations;\n\nstruct nfs_access_entry;\n\nstruct nfs_client_initdata;\n\nstruct nfs_rpc_ops {\n\tu32 version;\n\tconst struct dentry_operations *dentry_ops;\n\tconst struct inode_operations *dir_inode_ops;\n\tconst struct inode_operations *file_inode_ops;\n\tconst struct file_operations *file_ops;\n\tconst struct nlmclnt_operations *nlmclnt_ops;\n\tint (*getroot)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tint (*submount)(struct fs_context *, struct nfs_server *);\n\tint (*try_get_tree)(struct fs_context *);\n\tint (*getattr)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *, struct nfs4_label *, struct inode *);\n\tint (*setattr)(struct dentry *, struct nfs_fattr *, struct iattr *);\n\tint (*lookup)(struct inode *, struct dentry *, struct nfs_fh *, struct nfs_fattr *, struct nfs4_label *);\n\tint (*lookupp)(struct inode *, struct nfs_fh *, struct nfs_fattr *, struct nfs4_label *);\n\tint (*access)(struct inode *, struct nfs_access_entry *);\n\tint (*readlink)(struct inode *, struct page *, unsigned int, unsigned int);\n\tint (*create)(struct inode *, struct dentry *, struct iattr *, int);\n\tint (*remove)(struct inode *, struct dentry *);\n\tvoid (*unlink_setup)(struct rpc_message *, struct dentry *, struct inode *);\n\tvoid (*unlink_rpc_prepare)(struct rpc_task *, struct nfs_unlinkdata *);\n\tint (*unlink_done)(struct rpc_task *, struct inode *);\n\tvoid (*rename_setup)(struct rpc_message *, struct dentry *, struct dentry *);\n\tvoid (*rename_rpc_prepare)(struct rpc_task *, struct nfs_renamedata *);\n\tint (*rename_done)(struct rpc_task *, struct inode *, struct inode *);\n\tint (*link)(struct inode *, struct inode *, const struct qstr *);\n\tint (*symlink)(struct inode *, struct dentry *, struct page *, unsigned int, struct iattr *);\n\tint (*mkdir)(struct inode *, struct dentry *, struct iattr *);\n\tint (*rmdir)(struct inode *, const struct qstr *);\n\tint (*readdir)(struct dentry *, const struct cred *, u64, struct page **, unsigned int, bool);\n\tint (*mknod)(struct inode *, struct dentry *, struct iattr *, dev_t);\n\tint (*statfs)(struct nfs_server *, struct nfs_fh *, struct nfs_fsstat *);\n\tint (*fsinfo)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tint (*pathconf)(struct nfs_server *, struct nfs_fh *, struct nfs_pathconf *);\n\tint (*set_capabilities)(struct nfs_server *, struct nfs_fh *);\n\tint (*decode_dirent)(struct xdr_stream *, struct nfs_entry *, bool);\n\tint (*pgio_rpc_prepare)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*read_setup)(struct nfs_pgio_header *, struct rpc_message *);\n\tint (*read_done)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*write_setup)(struct nfs_pgio_header *, struct rpc_message *, struct rpc_clnt **);\n\tint (*write_done)(struct rpc_task *, struct nfs_pgio_header *);\n\tvoid (*commit_setup)(struct nfs_commit_data *, struct rpc_message *, struct rpc_clnt **);\n\tvoid (*commit_rpc_prepare)(struct rpc_task *, struct nfs_commit_data *);\n\tint (*commit_done)(struct rpc_task *, struct nfs_commit_data *);\n\tint (*lock)(struct file *, int, struct file_lock *);\n\tint (*lock_check_bounds)(const struct file_lock *);\n\tvoid (*clear_acl_cache)(struct inode *);\n\tvoid (*close_context)(struct nfs_open_context *, int);\n\tstruct inode * (*open_context)(struct inode *, struct nfs_open_context *, int, struct iattr *, int *);\n\tint (*have_delegation)(struct inode *, fmode_t);\n\tstruct nfs_client * (*alloc_client)(const struct nfs_client_initdata *);\n\tstruct nfs_client * (*init_client)(struct nfs_client *, const struct nfs_client_initdata *);\n\tvoid (*free_client)(struct nfs_client *);\n\tstruct nfs_server * (*create_server)(struct fs_context *);\n\tstruct nfs_server * (*clone_server)(struct nfs_server *, struct nfs_fh *, struct nfs_fattr *, rpc_authflavor_t);\n};\n\nstruct nlmclnt_operations {\n\tvoid (*nlmclnt_alloc_call)(void *);\n\tbool (*nlmclnt_unlock_prepare)(struct rpc_task *, void *);\n\tvoid (*nlmclnt_release_call)(void *);\n};\n\nstruct nfs_access_entry {\n\tstruct rb_node rb_node;\n\tstruct list_head lru;\n\tconst struct cred *cred;\n\t__u32 mask;\n\tstruct callback_head callback_head;\n};\n\nstruct nfs_client_initdata {\n\tlong unsigned int init_flags;\n\tconst char *hostname;\n\tconst struct sockaddr *addr;\n\tconst char *nodename;\n\tconst char *ip_addr;\n\tsize_t addrlen;\n\tstruct nfs_subversion *nfs_mod;\n\tint proto;\n\tu32 minorversion;\n\tunsigned int nconnect;\n\tstruct net *net;\n\tconst struct rpc_timeout *timeparms;\n\tconst struct cred *cred;\n};\n\nstruct nfs_seqid;\n\nstruct nfs_seqid_counter;\n\nstruct nfs4_state_recovery_ops;\n\nstruct nfs4_state_maintenance_ops;\n\nstruct nfs4_mig_recovery_ops;\n\nstruct nfs4_minor_version_ops {\n\tu32 minor_version;\n\tunsigned int init_caps;\n\tint (*init_client)(struct nfs_client *);\n\tvoid (*shutdown_client)(struct nfs_client *);\n\tbool (*match_stateid)(const nfs4_stateid *, const nfs4_stateid *);\n\tint (*find_root_sec)(struct nfs_server *, struct nfs_fh *, struct nfs_fsinfo *);\n\tvoid (*free_lock_state)(struct nfs_server *, struct nfs4_lock_state *);\n\tint (*test_and_free_expired)(struct nfs_server *, nfs4_stateid *, const struct cred *);\n\tstruct nfs_seqid * (*alloc_seqid)(struct nfs_seqid_counter *, gfp_t);\n\tvoid (*session_trunk)(struct rpc_clnt *, struct rpc_xprt *, void *);\n\tconst struct rpc_call_ops *call_sync_ops;\n\tconst struct nfs4_state_recovery_ops *reboot_recovery_ops;\n\tconst struct nfs4_state_recovery_ops *nograce_recovery_ops;\n\tconst struct nfs4_state_maintenance_ops *state_renewal_ops;\n\tconst struct nfs4_mig_recovery_ops *mig_recovery_ops;\n};\n\nenum perf_branch_sample_type_shift {\n\tPERF_SAMPLE_BRANCH_USER_SHIFT = 0,\n\tPERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1,\n\tPERF_SAMPLE_BRANCH_HV_SHIFT = 2,\n\tPERF_SAMPLE_BRANCH_ANY_SHIFT = 3,\n\tPERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5,\n\tPERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6,\n\tPERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7,\n\tPERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8,\n\tPERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9,\n\tPERF_SAMPLE_BRANCH_COND_SHIFT = 10,\n\tPERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11,\n\tPERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12,\n\tPERF_SAMPLE_BRANCH_CALL_SHIFT = 13,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16,\n\tPERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17,\n\tPERF_SAMPLE_BRANCH_MAX_SHIFT = 18,\n};\n\nenum exception_stack_ordering {\n\tESTACK_DF = 0,\n\tESTACK_NMI = 1,\n\tESTACK_DB = 2,\n\tESTACK_MCE = 3,\n\tN_EXCEPTION_STACKS = 4,\n};\n\nenum {\n\tTSK_TRACE_FL_TRACE_BIT = 0,\n\tTSK_TRACE_FL_GRAPH_BIT = 1,\n};\n\nstruct uuidcmp {\n\tconst char *uuid;\n\tint len;\n};\n\nstruct subprocess_info {\n\tstruct work_struct work;\n\tstruct completion *complete;\n\tconst char *path;\n\tchar **argv;\n\tchar **envp;\n\tstruct file *file;\n\tint wait;\n\tint retval;\n\tpid_t pid;\n\tint (*init)(struct subprocess_info *, struct cred *);\n\tvoid (*cleanup)(struct subprocess_info *);\n\tvoid *data;\n};\n\nstruct mdu_array_info_s {\n\tint major_version;\n\tint minor_version;\n\tint patch_version;\n\tunsigned int ctime;\n\tint level;\n\tint size;\n\tint nr_disks;\n\tint raid_disks;\n\tint md_minor;\n\tint not_persistent;\n\tunsigned int utime;\n\tint state;\n\tint active_disks;\n\tint working_disks;\n\tint failed_disks;\n\tint spare_disks;\n\tint layout;\n\tint chunk_size;\n};\n\ntypedef struct mdu_array_info_s mdu_array_info_t;\n\nstruct mdu_disk_info_s {\n\tint number;\n\tint major;\n\tint minor;\n\tint raid_disk;\n\tint state;\n};\n\ntypedef struct mdu_disk_info_s mdu_disk_info_t;\n\nstruct hash {\n\tint ino;\n\tint minor;\n\tint major;\n\tumode_t mode;\n\tstruct hash *next;\n\tchar name[4098];\n};\n\nstruct dir_entry {\n\tstruct list_head list;\n\tchar *name;\n\ttime64_t mtime;\n};\n\nenum state {\n\tStart = 0,\n\tCollect = 1,\n\tGotHeader = 2,\n\tSkipIt = 3,\n\tGotName = 4,\n\tCopyFile = 5,\n\tGotSymlink = 6,\n\tReset = 7,\n};\n\ntypedef int (*decompress_fn)(unsigned char *, long int, long int (*)(void *, long unsigned int), long int (*)(void *, long unsigned int), unsigned char *, long int *, void (*)(char *));\n\ntypedef u32 note_buf_t[92];\n\nstruct kimage_arch {\n\tp4d_t *p4d;\n\tpud_t *pud;\n\tpmd_t *pmd;\n\tpte_t *pte;\n\tvoid *elf_headers;\n\tlong unsigned int elf_headers_sz;\n\tlong unsigned int elf_load_addr;\n};\n\ntypedef void crash_vmclear_fn();\n\ntypedef long unsigned int kimage_entry_t;\n\nstruct kexec_segment {\n\tunion {\n\t\tvoid *buf;\n\t\tvoid *kbuf;\n\t};\n\tsize_t bufsz;\n\tlong unsigned int mem;\n\tsize_t memsz;\n};\n\nstruct kimage {\n\tkimage_entry_t head;\n\tkimage_entry_t *entry;\n\tkimage_entry_t *last_entry;\n\tlong unsigned int start;\n\tstruct page *control_code_page;\n\tstruct page *swap_page;\n\tvoid *vmcoreinfo_data_copy;\n\tlong unsigned int nr_segments;\n\tstruct kexec_segment segment[16];\n\tstruct list_head control_pages;\n\tstruct list_head dest_pages;\n\tstruct list_head unusable_pages;\n\tlong unsigned int control_page;\n\tunsigned int type: 1;\n\tunsigned int preserve_context: 1;\n\tunsigned int file_mode: 1;\n\tstruct kimage_arch arch;\n};\n\nenum ucount_type {\n\tUCOUNT_USER_NAMESPACES = 0,\n\tUCOUNT_PID_NAMESPACES = 1,\n\tUCOUNT_UTS_NAMESPACES = 2,\n\tUCOUNT_IPC_NAMESPACES = 3,\n\tUCOUNT_NET_NAMESPACES = 4,\n\tUCOUNT_MNT_NAMESPACES = 5,\n\tUCOUNT_CGROUP_NAMESPACES = 6,\n\tUCOUNT_TIME_NAMESPACES = 7,\n\tUCOUNT_INOTIFY_INSTANCES = 8,\n\tUCOUNT_INOTIFY_WATCHES = 9,\n\tUCOUNT_COUNTS = 10,\n};\n\nenum flow_dissector_key_id {\n\tFLOW_DISSECTOR_KEY_CONTROL = 0,\n\tFLOW_DISSECTOR_KEY_BASIC = 1,\n\tFLOW_DISSECTOR_KEY_IPV4_ADDRS = 2,\n\tFLOW_DISSECTOR_KEY_IPV6_ADDRS = 3,\n\tFLOW_DISSECTOR_KEY_PORTS = 4,\n\tFLOW_DISSECTOR_KEY_PORTS_RANGE = 5,\n\tFLOW_DISSECTOR_KEY_ICMP = 6,\n\tFLOW_DISSECTOR_KEY_ETH_ADDRS = 7,\n\tFLOW_DISSECTOR_KEY_TIPC = 8,\n\tFLOW_DISSECTOR_KEY_ARP = 9,\n\tFLOW_DISSECTOR_KEY_VLAN = 10,\n\tFLOW_DISSECTOR_KEY_FLOW_LABEL = 11,\n\tFLOW_DISSECTOR_KEY_GRE_KEYID = 12,\n\tFLOW_DISSECTOR_KEY_MPLS_ENTROPY = 13,\n\tFLOW_DISSECTOR_KEY_ENC_KEYID = 14,\n\tFLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS = 15,\n\tFLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS = 16,\n\tFLOW_DISSECTOR_KEY_ENC_CONTROL = 17,\n\tFLOW_DISSECTOR_KEY_ENC_PORTS = 18,\n\tFLOW_DISSECTOR_KEY_MPLS = 19,\n\tFLOW_DISSECTOR_KEY_TCP = 20,\n\tFLOW_DISSECTOR_KEY_IP = 21,\n\tFLOW_DISSECTOR_KEY_CVLAN = 22,\n\tFLOW_DISSECTOR_KEY_ENC_IP = 23,\n\tFLOW_DISSECTOR_KEY_ENC_OPTS = 24,\n\tFLOW_DISSECTOR_KEY_META = 25,\n\tFLOW_DISSECTOR_KEY_CT = 26,\n\tFLOW_DISSECTOR_KEY_MAX = 27,\n};\n\nenum {\n\tIPSTATS_MIB_NUM = 0,\n\tIPSTATS_MIB_INPKTS = 1,\n\tIPSTATS_MIB_INOCTETS = 2,\n\tIPSTATS_MIB_INDELIVERS = 3,\n\tIPSTATS_MIB_OUTFORWDATAGRAMS = 4,\n\tIPSTATS_MIB_OUTPKTS = 5,\n\tIPSTATS_MIB_OUTOCTETS = 6,\n\tIPSTATS_MIB_INHDRERRORS = 7,\n\tIPSTATS_MIB_INTOOBIGERRORS = 8,\n\tIPSTATS_MIB_INNOROUTES = 9,\n\tIPSTATS_MIB_INADDRERRORS = 10,\n\tIPSTATS_MIB_INUNKNOWNPROTOS = 11,\n\tIPSTATS_MIB_INTRUNCATEDPKTS = 12,\n\tIPSTATS_MIB_INDISCARDS = 13,\n\tIPSTATS_MIB_OUTDISCARDS = 14,\n\tIPSTATS_MIB_OUTNOROUTES = 15,\n\tIPSTATS_MIB_REASMTIMEOUT = 16,\n\tIPSTATS_MIB_REASMREQDS = 17,\n\tIPSTATS_MIB_REASMOKS = 18,\n\tIPSTATS_MIB_REASMFAILS = 19,\n\tIPSTATS_MIB_FRAGOKS = 20,\n\tIPSTATS_MIB_FRAGFAILS = 21,\n\tIPSTATS_MIB_FRAGCREATES = 22,\n\tIPSTATS_MIB_INMCASTPKTS = 23,\n\tIPSTATS_MIB_OUTMCASTPKTS = 24,\n\tIPSTATS_MIB_INBCASTPKTS = 25,\n\tIPSTATS_MIB_OUTBCASTPKTS = 26,\n\tIPSTATS_MIB_INMCASTOCTETS = 27,\n\tIPSTATS_MIB_OUTMCASTOCTETS = 28,\n\tIPSTATS_MIB_INBCASTOCTETS = 29,\n\tIPSTATS_MIB_OUTBCASTOCTETS = 30,\n\tIPSTATS_MIB_CSUMERRORS = 31,\n\tIPSTATS_MIB_NOECTPKTS = 32,\n\tIPSTATS_MIB_ECT1PKTS = 33,\n\tIPSTATS_MIB_ECT0PKTS = 34,\n\tIPSTATS_MIB_CEPKTS = 35,\n\tIPSTATS_MIB_REASM_OVERLAPS = 36,\n\t__IPSTATS_MIB_MAX = 37,\n};\n\nenum {\n\tICMP_MIB_NUM = 0,\n\tICMP_MIB_INMSGS = 1,\n\tICMP_MIB_INERRORS = 2,\n\tICMP_MIB_INDESTUNREACHS = 3,\n\tICMP_MIB_INTIMEEXCDS = 4,\n\tICMP_MIB_INPARMPROBS = 5,\n\tICMP_MIB_INSRCQUENCHS = 6,\n\tICMP_MIB_INREDIRECTS = 7,\n\tICMP_MIB_INECHOS = 8,\n\tICMP_MIB_INECHOREPS = 9,\n\tICMP_MIB_INTIMESTAMPS = 10,\n\tICMP_MIB_INTIMESTAMPREPS = 11,\n\tICMP_MIB_INADDRMASKS = 12,\n\tICMP_MIB_INADDRMASKREPS = 13,\n\tICMP_MIB_OUTMSGS = 14,\n\tICMP_MIB_OUTERRORS = 15,\n\tICMP_MIB_OUTDESTUNREACHS = 16,\n\tICMP_MIB_OUTTIMEEXCDS = 17,\n\tICMP_MIB_OUTPARMPROBS = 18,\n\tICMP_MIB_OUTSRCQUENCHS = 19,\n\tICMP_MIB_OUTREDIRECTS = 20,\n\tICMP_MIB_OUTECHOS = 21,\n\tICMP_MIB_OUTECHOREPS = 22,\n\tICMP_MIB_OUTTIMESTAMPS = 23,\n\tICMP_MIB_OUTTIMESTAMPREPS = 24,\n\tICMP_MIB_OUTADDRMASKS = 25,\n\tICMP_MIB_OUTADDRMASKREPS = 26,\n\tICMP_MIB_CSUMERRORS = 27,\n\t__ICMP_MIB_MAX = 28,\n};\n\nenum {\n\tICMP6_MIB_NUM = 0,\n\tICMP6_MIB_INMSGS = 1,\n\tICMP6_MIB_INERRORS = 2,\n\tICMP6_MIB_OUTMSGS = 3,\n\tICMP6_MIB_OUTERRORS = 4,\n\tICMP6_MIB_CSUMERRORS = 5,\n\t__ICMP6_MIB_MAX = 6,\n};\n\nenum {\n\tTCP_MIB_NUM = 0,\n\tTCP_MIB_RTOALGORITHM = 1,\n\tTCP_MIB_RTOMIN = 2,\n\tTCP_MIB_RTOMAX = 3,\n\tTCP_MIB_MAXCONN = 4,\n\tTCP_MIB_ACTIVEOPENS = 5,\n\tTCP_MIB_PASSIVEOPENS = 6,\n\tTCP_MIB_ATTEMPTFAILS = 7,\n\tTCP_MIB_ESTABRESETS = 8,\n\tTCP_MIB_CURRESTAB = 9,\n\tTCP_MIB_INSEGS = 10,\n\tTCP_MIB_OUTSEGS = 11,\n\tTCP_MIB_RETRANSSEGS = 12,\n\tTCP_MIB_INERRS = 13,\n\tTCP_MIB_OUTRSTS = 14,\n\tTCP_MIB_CSUMERRORS = 15,\n\t__TCP_MIB_MAX = 16,\n};\n\nenum {\n\tUDP_MIB_NUM = 0,\n\tUDP_MIB_INDATAGRAMS = 1,\n\tUDP_MIB_NOPORTS = 2,\n\tUDP_MIB_INERRORS = 3,\n\tUDP_MIB_OUTDATAGRAMS = 4,\n\tUDP_MIB_RCVBUFERRORS = 5,\n\tUDP_MIB_SNDBUFERRORS = 6,\n\tUDP_MIB_CSUMERRORS = 7,\n\tUDP_MIB_IGNOREDMULTI = 8,\n\t__UDP_MIB_MAX = 9,\n};\n\nenum {\n\tLINUX_MIB_NUM = 0,\n\tLINUX_MIB_SYNCOOKIESSENT = 1,\n\tLINUX_MIB_SYNCOOKIESRECV = 2,\n\tLINUX_MIB_SYNCOOKIESFAILED = 3,\n\tLINUX_MIB_EMBRYONICRSTS = 4,\n\tLINUX_MIB_PRUNECALLED = 5,\n\tLINUX_MIB_RCVPRUNED = 6,\n\tLINUX_MIB_OFOPRUNED = 7,\n\tLINUX_MIB_OUTOFWINDOWICMPS = 8,\n\tLINUX_MIB_LOCKDROPPEDICMPS = 9,\n\tLINUX_MIB_ARPFILTER = 10,\n\tLINUX_MIB_TIMEWAITED = 11,\n\tLINUX_MIB_TIMEWAITRECYCLED = 12,\n\tLINUX_MIB_TIMEWAITKILLED = 13,\n\tLINUX_MIB_PAWSACTIVEREJECTED = 14,\n\tLINUX_MIB_PAWSESTABREJECTED = 15,\n\tLINUX_MIB_DELAYEDACKS = 16,\n\tLINUX_MIB_DELAYEDACKLOCKED = 17,\n\tLINUX_MIB_DELAYEDACKLOST = 18,\n\tLINUX_MIB_LISTENOVERFLOWS = 19,\n\tLINUX_MIB_LISTENDROPS = 20,\n\tLINUX_MIB_TCPHPHITS = 21,\n\tLINUX_MIB_TCPPUREACKS = 22,\n\tLINUX_MIB_TCPHPACKS = 23,\n\tLINUX_MIB_TCPRENORECOVERY = 24,\n\tLINUX_MIB_TCPSACKRECOVERY = 25,\n\tLINUX_MIB_TCPSACKRENEGING = 26,\n\tLINUX_MIB_TCPSACKREORDER = 27,\n\tLINUX_MIB_TCPRENOREORDER = 28,\n\tLINUX_MIB_TCPTSREORDER = 29,\n\tLINUX_MIB_TCPFULLUNDO = 30,\n\tLINUX_MIB_TCPPARTIALUNDO = 31,\n\tLINUX_MIB_TCPDSACKUNDO = 32,\n\tLINUX_MIB_TCPLOSSUNDO = 33,\n\tLINUX_MIB_TCPLOSTRETRANSMIT = 34,\n\tLINUX_MIB_TCPRENOFAILURES = 35,\n\tLINUX_MIB_TCPSACKFAILURES = 36,\n\tLINUX_MIB_TCPLOSSFAILURES = 37,\n\tLINUX_MIB_TCPFASTRETRANS = 38,\n\tLINUX_MIB_TCPSLOWSTARTRETRANS = 39,\n\tLINUX_MIB_TCPTIMEOUTS = 40,\n\tLINUX_MIB_TCPLOSSPROBES = 41,\n\tLINUX_MIB_TCPLOSSPROBERECOVERY = 42,\n\tLINUX_MIB_TCPRENORECOVERYFAIL = 43,\n\tLINUX_MIB_TCPSACKRECOVERYFAIL = 44,\n\tLINUX_MIB_TCPRCVCOLLAPSED = 45,\n\tLINUX_MIB_TCPDSACKOLDSENT = 46,\n\tLINUX_MIB_TCPDSACKOFOSENT = 47,\n\tLINUX_MIB_TCPDSACKRECV = 48,\n\tLINUX_MIB_TCPDSACKOFORECV = 49,\n\tLINUX_MIB_TCPABORTONDATA = 50,\n\tLINUX_MIB_TCPABORTONCLOSE = 51,\n\tLINUX_MIB_TCPABORTONMEMORY = 52,\n\tLINUX_MIB_TCPABORTONTIMEOUT = 53,\n\tLINUX_MIB_TCPABORTONLINGER = 54,\n\tLINUX_MIB_TCPABORTFAILED = 55,\n\tLINUX_MIB_TCPMEMORYPRESSURES = 56,\n\tLINUX_MIB_TCPMEMORYPRESSURESCHRONO = 57,\n\tLINUX_MIB_TCPSACKDISCARD = 58,\n\tLINUX_MIB_TCPDSACKIGNOREDOLD = 59,\n\tLINUX_MIB_TCPDSACKIGNOREDNOUNDO = 60,\n\tLINUX_MIB_TCPSPURIOUSRTOS = 61,\n\tLINUX_MIB_TCPMD5NOTFOUND = 62,\n\tLINUX_MIB_TCPMD5UNEXPECTED = 63,\n\tLINUX_MIB_TCPMD5FAILURE = 64,\n\tLINUX_MIB_SACKSHIFTED = 65,\n\tLINUX_MIB_SACKMERGED = 66,\n\tLINUX_MIB_SACKSHIFTFALLBACK = 67,\n\tLINUX_MIB_TCPBACKLOGDROP = 68,\n\tLINUX_MIB_PFMEMALLOCDROP = 69,\n\tLINUX_MIB_TCPMINTTLDROP = 70,\n\tLINUX_MIB_TCPDEFERACCEPTDROP = 71,\n\tLINUX_MIB_IPRPFILTER = 72,\n\tLINUX_MIB_TCPTIMEWAITOVERFLOW = 73,\n\tLINUX_MIB_TCPREQQFULLDOCOOKIES = 74,\n\tLINUX_MIB_TCPREQQFULLDROP = 75,\n\tLINUX_MIB_TCPRETRANSFAIL = 76,\n\tLINUX_MIB_TCPRCVCOALESCE = 77,\n\tLINUX_MIB_TCPBACKLOGCOALESCE = 78,\n\tLINUX_MIB_TCPOFOQUEUE = 79,\n\tLINUX_MIB_TCPOFODROP = 80,\n\tLINUX_MIB_TCPOFOMERGE = 81,\n\tLINUX_MIB_TCPCHALLENGEACK = 82,\n\tLINUX_MIB_TCPSYNCHALLENGE = 83,\n\tLINUX_MIB_TCPFASTOPENACTIVE = 84,\n\tLINUX_MIB_TCPFASTOPENACTIVEFAIL = 85,\n\tLINUX_MIB_TCPFASTOPENPASSIVE = 86,\n\tLINUX_MIB_TCPFASTOPENPASSIVEFAIL = 87,\n\tLINUX_MIB_TCPFASTOPENLISTENOVERFLOW = 88,\n\tLINUX_MIB_TCPFASTOPENCOOKIEREQD = 89,\n\tLINUX_MIB_TCPFASTOPENBLACKHOLE = 90,\n\tLINUX_MIB_TCPSPURIOUS_RTX_HOSTQUEUES = 91,\n\tLINUX_MIB_BUSYPOLLRXPACKETS = 92,\n\tLINUX_MIB_TCPAUTOCORKING = 93,\n\tLINUX_MIB_TCPFROMZEROWINDOWADV = 94,\n\tLINUX_MIB_TCPTOZEROWINDOWADV = 95,\n\tLINUX_MIB_TCPWANTZEROWINDOWADV = 96,\n\tLINUX_MIB_TCPSYNRETRANS = 97,\n\tLINUX_MIB_TCPORIGDATASENT = 98,\n\tLINUX_MIB_TCPHYSTARTTRAINDETECT = 99,\n\tLINUX_MIB_TCPHYSTARTTRAINCWND = 100,\n\tLINUX_MIB_TCPHYSTARTDELAYDETECT = 101,\n\tLINUX_MIB_TCPHYSTARTDELAYCWND = 102,\n\tLINUX_MIB_TCPACKSKIPPEDSYNRECV = 103,\n\tLINUX_MIB_TCPACKSKIPPEDPAWS = 104,\n\tLINUX_MIB_TCPACKSKIPPEDSEQ = 105,\n\tLINUX_MIB_TCPACKSKIPPEDFINWAIT2 = 106,\n\tLINUX_MIB_TCPACKSKIPPEDTIMEWAIT = 107,\n\tLINUX_MIB_TCPACKSKIPPEDCHALLENGE = 108,\n\tLINUX_MIB_TCPWINPROBE = 109,\n\tLINUX_MIB_TCPKEEPALIVE = 110,\n\tLINUX_MIB_TCPMTUPFAIL = 111,\n\tLINUX_MIB_TCPMTUPSUCCESS = 112,\n\tLINUX_MIB_TCPDELIVERED = 113,\n\tLINUX_MIB_TCPDELIVEREDCE = 114,\n\tLINUX_MIB_TCPACKCOMPRESSED = 115,\n\tLINUX_MIB_TCPZEROWINDOWDROP = 116,\n\tLINUX_MIB_TCPRCVQDROP = 117,\n\tLINUX_MIB_TCPWQUEUETOOBIG = 118,\n\tLINUX_MIB_TCPFASTOPENPASSIVEALTKEY = 119,\n\tLINUX_MIB_TCPTIMEOUTREHASH = 120,\n\tLINUX_MIB_TCPDUPLICATEDATAREHASH = 121,\n\t__LINUX_MIB_MAX = 122,\n};\n\nenum {\n\tLINUX_MIB_XFRMNUM = 0,\n\tLINUX_MIB_XFRMINERROR = 1,\n\tLINUX_MIB_XFRMINBUFFERERROR = 2,\n\tLINUX_MIB_XFRMINHDRERROR = 3,\n\tLINUX_MIB_XFRMINNOSTATES = 4,\n\tLINUX_MIB_XFRMINSTATEPROTOERROR = 5,\n\tLINUX_MIB_XFRMINSTATEMODEERROR = 6,\n\tLINUX_MIB_XFRMINSTATESEQERROR = 7,\n\tLINUX_MIB_XFRMINSTATEEXPIRED = 8,\n\tLINUX_MIB_XFRMINSTATEMISMATCH = 9,\n\tLINUX_MIB_XFRMINSTATEINVALID = 10,\n\tLINUX_MIB_XFRMINTMPLMISMATCH = 11,\n\tLINUX_MIB_XFRMINNOPOLS = 12,\n\tLINUX_MIB_XFRMINPOLBLOCK = 13,\n\tLINUX_MIB_XFRMINPOLERROR = 14,\n\tLINUX_MIB_XFRMOUTERROR = 15,\n\tLINUX_MIB_XFRMOUTBUNDLEGENERROR = 16,\n\tLINUX_MIB_XFRMOUTBUNDLECHECKERROR = 17,\n\tLINUX_MIB_XFRMOUTNOSTATES = 18,\n\tLINUX_MIB_XFRMOUTSTATEPROTOERROR = 19,\n\tLINUX_MIB_XFRMOUTSTATEMODEERROR = 20,\n\tLINUX_MIB_XFRMOUTSTATESEQERROR = 21,\n\tLINUX_MIB_XFRMOUTSTATEEXPIRED = 22,\n\tLINUX_MIB_XFRMOUTPOLBLOCK = 23,\n\tLINUX_MIB_XFRMOUTPOLDEAD = 24,\n\tLINUX_MIB_XFRMOUTPOLERROR = 25,\n\tLINUX_MIB_XFRMFWDHDRERROR = 26,\n\tLINUX_MIB_XFRMOUTSTATEINVALID = 27,\n\tLINUX_MIB_XFRMACQUIREERROR = 28,\n\t__LINUX_MIB_XFRMMAX = 29,\n};\n\nenum {\n\tLINUX_MIB_TLSNUM = 0,\n\tLINUX_MIB_TLSCURRTXSW = 1,\n\tLINUX_MIB_TLSCURRRXSW = 2,\n\tLINUX_MIB_TLSCURRTXDEVICE = 3,\n\tLINUX_MIB_TLSCURRRXDEVICE = 4,\n\tLINUX_MIB_TLSTXSW = 5,\n\tLINUX_MIB_TLSRXSW = 6,\n\tLINUX_MIB_TLSTXDEVICE = 7,\n\tLINUX_MIB_TLSRXDEVICE = 8,\n\tLINUX_MIB_TLSDECRYPTERROR = 9,\n\tLINUX_MIB_TLSRXDEVICERESYNC = 10,\n\t__LINUX_MIB_TLSMAX = 11,\n};\n\nenum nf_inet_hooks {\n\tNF_INET_PRE_ROUTING = 0,\n\tNF_INET_LOCAL_IN = 1,\n\tNF_INET_FORWARD = 2,\n\tNF_INET_LOCAL_OUT = 3,\n\tNF_INET_POST_ROUTING = 4,\n\tNF_INET_NUMHOOKS = 5,\n};\n\nenum {\n\tNFPROTO_UNSPEC = 0,\n\tNFPROTO_INET = 1,\n\tNFPROTO_IPV4 = 2,\n\tNFPROTO_ARP = 3,\n\tNFPROTO_NETDEV = 5,\n\tNFPROTO_BRIDGE = 7,\n\tNFPROTO_IPV6 = 10,\n\tNFPROTO_DECNET = 12,\n\tNFPROTO_NUMPROTO = 13,\n};\n\nenum tcp_conntrack {\n\tTCP_CONNTRACK_NONE = 0,\n\tTCP_CONNTRACK_SYN_SENT = 1,\n\tTCP_CONNTRACK_SYN_RECV = 2,\n\tTCP_CONNTRACK_ESTABLISHED = 3,\n\tTCP_CONNTRACK_FIN_WAIT = 4,\n\tTCP_CONNTRACK_CLOSE_WAIT = 5,\n\tTCP_CONNTRACK_LAST_ACK = 6,\n\tTCP_CONNTRACK_TIME_WAIT = 7,\n\tTCP_CONNTRACK_CLOSE = 8,\n\tTCP_CONNTRACK_LISTEN = 9,\n\tTCP_CONNTRACK_MAX = 10,\n\tTCP_CONNTRACK_IGNORE = 11,\n\tTCP_CONNTRACK_RETRANS = 12,\n\tTCP_CONNTRACK_UNACK = 13,\n\tTCP_CONNTRACK_TIMEOUT_MAX = 14,\n};\n\nenum ct_dccp_states {\n\tCT_DCCP_NONE = 0,\n\tCT_DCCP_REQUEST = 1,\n\tCT_DCCP_RESPOND = 2,\n\tCT_DCCP_PARTOPEN = 3,\n\tCT_DCCP_OPEN = 4,\n\tCT_DCCP_CLOSEREQ = 5,\n\tCT_DCCP_CLOSING = 6,\n\tCT_DCCP_TIMEWAIT = 7,\n\tCT_DCCP_IGNORE = 8,\n\tCT_DCCP_INVALID = 9,\n\t__CT_DCCP_MAX = 10,\n};\n\nenum ip_conntrack_dir {\n\tIP_CT_DIR_ORIGINAL = 0,\n\tIP_CT_DIR_REPLY = 1,\n\tIP_CT_DIR_MAX = 2,\n};\n\nenum sctp_conntrack {\n\tSCTP_CONNTRACK_NONE = 0,\n\tSCTP_CONNTRACK_CLOSED = 1,\n\tSCTP_CONNTRACK_COOKIE_WAIT = 2,\n\tSCTP_CONNTRACK_COOKIE_ECHOED = 3,\n\tSCTP_CONNTRACK_ESTABLISHED = 4,\n\tSCTP_CONNTRACK_SHUTDOWN_SENT = 5,\n\tSCTP_CONNTRACK_SHUTDOWN_RECD = 6,\n\tSCTP_CONNTRACK_SHUTDOWN_ACK_SENT = 7,\n\tSCTP_CONNTRACK_HEARTBEAT_SENT = 8,\n\tSCTP_CONNTRACK_HEARTBEAT_ACKED = 9,\n\tSCTP_CONNTRACK_MAX = 10,\n};\n\nenum udp_conntrack {\n\tUDP_CT_UNREPLIED = 0,\n\tUDP_CT_REPLIED = 1,\n\tUDP_CT_MAX = 2,\n};\n\nenum {\n\tXFRM_POLICY_IN = 0,\n\tXFRM_POLICY_OUT = 1,\n\tXFRM_POLICY_FWD = 2,\n\tXFRM_POLICY_MASK = 3,\n\tXFRM_POLICY_MAX = 3,\n};\n\nenum netns_bpf_attach_type {\n\tNETNS_BPF_INVALID = 4294967295,\n\tNETNS_BPF_FLOW_DISSECTOR = 0,\n\tMAX_NETNS_BPF_ATTACH_TYPE = 1,\n};\n\nenum skb_ext_id {\n\tSKB_EXT_SEC_PATH = 0,\n\tSKB_EXT_NUM = 1,\n};\n\nenum sched_tunable_scaling {\n\tSCHED_TUNABLESCALING_NONE = 0,\n\tSCHED_TUNABLESCALING_LOG = 1,\n\tSCHED_TUNABLESCALING_LINEAR = 2,\n\tSCHED_TUNABLESCALING_END = 3,\n};\n\nenum audit_ntp_type {\n\tAUDIT_NTP_OFFSET = 0,\n\tAUDIT_NTP_FREQ = 1,\n\tAUDIT_NTP_STATUS = 2,\n\tAUDIT_NTP_TAI = 3,\n\tAUDIT_NTP_TICK = 4,\n\tAUDIT_NTP_ADJUST = 5,\n\tAUDIT_NTP_NVALS = 6,\n};\n\ntypedef long int (*sys_call_ptr_t)(const struct pt_regs *);\n\nstruct io_bitmap {\n\tu64 sequence;\n\trefcount_t refcnt;\n\tunsigned int max;\n\tlong unsigned int bitmap[1024];\n};\n\nstruct seccomp_data {\n\tint nr;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 args[6];\n};\n\nstruct ksignal {\n\tstruct k_sigaction ka;\n\tkernel_siginfo_t info;\n\tint sig;\n};\n\nstruct __large_struct {\n\tlong unsigned int buf[100];\n};\n\nenum {\n\tTASKSTATS_CMD_UNSPEC = 0,\n\tTASKSTATS_CMD_GET = 1,\n\tTASKSTATS_CMD_NEW = 2,\n\t__TASKSTATS_CMD_MAX = 3,\n};\n\nenum ctx_state {\n\tCONTEXT_DISABLED = 4294967295,\n\tCONTEXT_KERNEL = 0,\n\tCONTEXT_USER = 1,\n\tCONTEXT_GUEST = 2,\n};\n\nenum {\n\tHI_SOFTIRQ = 0,\n\tTIMER_SOFTIRQ = 1,\n\tNET_TX_SOFTIRQ = 2,\n\tNET_RX_SOFTIRQ = 3,\n\tBLOCK_SOFTIRQ = 4,\n\tIRQ_POLL_SOFTIRQ = 5,\n\tTASKLET_SOFTIRQ = 6,\n\tSCHED_SOFTIRQ = 7,\n\tHRTIMER_SOFTIRQ = 8,\n\tRCU_SOFTIRQ = 9,\n\tNR_SOFTIRQS = 10,\n};\n\nenum cpu_usage_stat {\n\tCPUTIME_USER = 0,\n\tCPUTIME_NICE = 1,\n\tCPUTIME_SYSTEM = 2,\n\tCPUTIME_SOFTIRQ = 3,\n\tCPUTIME_IRQ = 4,\n\tCPUTIME_IDLE = 5,\n\tCPUTIME_IOWAIT = 6,\n\tCPUTIME_STEAL = 7,\n\tCPUTIME_GUEST = 8,\n\tCPUTIME_GUEST_NICE = 9,\n\tNR_STATS = 10,\n};\n\nenum {\n\tEI_ETYPE_NONE = 0,\n\tEI_ETYPE_NULL = 1,\n\tEI_ETYPE_ERRNO = 2,\n\tEI_ETYPE_ERRNO_NULL = 3,\n\tEI_ETYPE_TRUE = 4,\n};\n\nenum bpf_cgroup_storage_type {\n\tBPF_CGROUP_STORAGE_SHARED = 0,\n\tBPF_CGROUP_STORAGE_PERCPU = 1,\n\t__BPF_CGROUP_STORAGE_MAX = 2,\n};\n\nenum cgroup_subsys_id {\n\tcpuset_cgrp_id = 0,\n\tcpu_cgrp_id = 1,\n\tcpuacct_cgrp_id = 2,\n\tfreezer_cgrp_id = 3,\n\tCGROUP_SUBSYS_COUNT = 4,\n};\n\ntypedef u8 kprobe_opcode_t;\n\nstruct arch_specific_insn {\n\tkprobe_opcode_t *insn;\n\tbool boostable;\n\tbool if_modifier;\n};\n\nstruct kprobe;\n\nstruct prev_kprobe {\n\tstruct kprobe *kp;\n\tlong unsigned int status;\n\tlong unsigned int old_flags;\n\tlong unsigned int saved_flags;\n};\n\ntypedef int (*kprobe_pre_handler_t)(struct kprobe *, struct pt_regs *);\n\ntypedef void (*kprobe_post_handler_t)(struct kprobe *, struct pt_regs *, long unsigned int);\n\ntypedef int (*kprobe_fault_handler_t)(struct kprobe *, struct pt_regs *, int);\n\nstruct kprobe {\n\tstruct hlist_node hlist;\n\tstruct list_head list;\n\tlong unsigned int nmissed;\n\tkprobe_opcode_t *addr;\n\tconst char *symbol_name;\n\tunsigned int offset;\n\tkprobe_pre_handler_t pre_handler;\n\tkprobe_post_handler_t post_handler;\n\tkprobe_fault_handler_t fault_handler;\n\tkprobe_opcode_t opcode;\n\tstruct arch_specific_insn ainsn;\n\tu32 flags;\n};\n\nstruct kprobe_ctlblk {\n\tlong unsigned int kprobe_status;\n\tlong unsigned int kprobe_old_flags;\n\tlong unsigned int kprobe_saved_flags;\n\tstruct prev_kprobe prev_kprobe;\n};\n\nstruct kretprobe_blackpoint {\n\tconst char *name;\n\tvoid *addr;\n};\n\nstruct kprobe_insn_cache {\n\tstruct mutex mutex;\n\tvoid * (*alloc)();\n\tvoid (*free)(void *);\n\tstruct list_head pages;\n\tsize_t insn_size;\n\tint nr_garbage;\n};\n\nstruct trace_event_raw_sys_enter {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong unsigned int args[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sys_exit {\n\tstruct trace_entry ent;\n\tlong int id;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_sys_enter {};\n\nstruct trace_event_data_offsets_sys_exit {};\n\ntypedef void (*btf_trace_sys_enter)(void *, struct pt_regs *, long int);\n\ntypedef void (*btf_trace_sys_exit)(void *, struct pt_regs *, long int);\n\nstruct alt_instr {\n\ts32 instr_offset;\n\ts32 repl_offset;\n\tu16 cpuid;\n\tu8 instrlen;\n\tu8 replacementlen;\n\tu8 padlen;\n} __attribute__((packed));\n\nstruct timens_offset {\n\ts64 sec;\n\tu64 nsec;\n};\n\nenum vm_fault_reason {\n\tVM_FAULT_OOM = 1,\n\tVM_FAULT_SIGBUS = 2,\n\tVM_FAULT_MAJOR = 4,\n\tVM_FAULT_WRITE = 8,\n\tVM_FAULT_HWPOISON = 16,\n\tVM_FAULT_HWPOISON_LARGE = 32,\n\tVM_FAULT_SIGSEGV = 64,\n\tVM_FAULT_NOPAGE = 256,\n\tVM_FAULT_LOCKED = 512,\n\tVM_FAULT_RETRY = 1024,\n\tVM_FAULT_FALLBACK = 2048,\n\tVM_FAULT_DONE_COW = 4096,\n\tVM_FAULT_NEEDDSYNC = 8192,\n\tVM_FAULT_HINDEX_MASK = 983040,\n};\n\nstruct vm_special_mapping {\n\tconst char *name;\n\tstruct page **pages;\n\tvm_fault_t (*fault)(const struct vm_special_mapping *, struct vm_area_struct *, struct vm_fault *);\n\tint (*mremap)(const struct vm_special_mapping *, struct vm_area_struct *);\n};\n\nstruct timens_offsets {\n\tstruct timespec64 monotonic;\n\tstruct timespec64 boottime;\n};\n\nstruct time_namespace {\n\tstruct kref kref;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct ns_common ns;\n\tstruct timens_offsets offsets;\n\tstruct page *vvar_page;\n\tbool frozen_offsets;\n};\n\nstruct pvclock_vcpu_time_info {\n\tu32 version;\n\tu32 pad0;\n\tu64 tsc_timestamp;\n\tu64 system_time;\n\tu32 tsc_to_system_mul;\n\ts8 tsc_shift;\n\tu8 flags;\n\tu8 pad[2];\n};\n\nstruct pvclock_vsyscall_time_info {\n\tstruct pvclock_vcpu_time_info pvti;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nenum vdso_clock_mode {\n\tVDSO_CLOCKMODE_NONE = 0,\n\tVDSO_CLOCKMODE_TSC = 1,\n\tVDSO_CLOCKMODE_PVCLOCK = 2,\n\tVDSO_CLOCKMODE_HVCLOCK = 3,\n\tVDSO_CLOCKMODE_MAX = 4,\n\tVDSO_CLOCKMODE_TIMENS = 2147483647,\n};\n\nstruct vdso_timestamp {\n\tu64 sec;\n\tu64 nsec;\n};\n\nstruct vdso_data {\n\tu32 seq;\n\ts32 clock_mode;\n\tu64 cycle_last;\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tunion {\n\t\tstruct vdso_timestamp basetime[12];\n\t\tstruct timens_offset offset[12];\n\t};\n\ts32 tz_minuteswest;\n\ts32 tz_dsttime;\n\tu32 hrtimer_res;\n\tu32 __unused;\n};\n\nstruct irq_desc;\n\ntypedef struct irq_desc *vector_irq_t[256];\n\nstruct ms_hyperv_tsc_page {\n\tvolatile u32 tsc_sequence;\n\tu32 reserved1;\n\tvolatile u64 tsc_scale;\n\tvolatile s64 tsc_offset;\n};\n\nstruct ms_hyperv_info {\n\tu32 features;\n\tu32 misc_features;\n\tu32 hints;\n\tu32 nested_features;\n\tu32 max_vp_index;\n\tu32 max_lp_index;\n};\n\nenum x86_pf_error_code {\n\tX86_PF_PROT = 1,\n\tX86_PF_WRITE = 2,\n\tX86_PF_USER = 4,\n\tX86_PF_RSVD = 8,\n\tX86_PF_INSTR = 16,\n\tX86_PF_PK = 32,\n};\n\nstruct trace_event_raw_emulate_vsyscall {\n\tstruct trace_entry ent;\n\tint nr;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_emulate_vsyscall {};\n\ntypedef void (*btf_trace_emulate_vsyscall)(void *, int);\n\nenum {\n\tEMULATE = 0,\n\tXONLY = 1,\n\tNONE = 2,\n};\n\nenum perf_type_id {\n\tPERF_TYPE_HARDWARE = 0,\n\tPERF_TYPE_SOFTWARE = 1,\n\tPERF_TYPE_TRACEPOINT = 2,\n\tPERF_TYPE_HW_CACHE = 3,\n\tPERF_TYPE_RAW = 4,\n\tPERF_TYPE_BREAKPOINT = 5,\n\tPERF_TYPE_MAX = 6,\n};\n\nenum perf_hw_id {\n\tPERF_COUNT_HW_CPU_CYCLES = 0,\n\tPERF_COUNT_HW_INSTRUCTIONS = 1,\n\tPERF_COUNT_HW_CACHE_REFERENCES = 2,\n\tPERF_COUNT_HW_CACHE_MISSES = 3,\n\tPERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,\n\tPERF_COUNT_HW_BRANCH_MISSES = 5,\n\tPERF_COUNT_HW_BUS_CYCLES = 6,\n\tPERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,\n\tPERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,\n\tPERF_COUNT_HW_REF_CPU_CYCLES = 9,\n\tPERF_COUNT_HW_MAX = 10,\n};\n\nenum perf_hw_cache_id {\n\tPERF_COUNT_HW_CACHE_L1D = 0,\n\tPERF_COUNT_HW_CACHE_L1I = 1,\n\tPERF_COUNT_HW_CACHE_LL = 2,\n\tPERF_COUNT_HW_CACHE_DTLB = 3,\n\tPERF_COUNT_HW_CACHE_ITLB = 4,\n\tPERF_COUNT_HW_CACHE_BPU = 5,\n\tPERF_COUNT_HW_CACHE_NODE = 6,\n\tPERF_COUNT_HW_CACHE_MAX = 7,\n};\n\nenum perf_hw_cache_op_id {\n\tPERF_COUNT_HW_CACHE_OP_READ = 0,\n\tPERF_COUNT_HW_CACHE_OP_WRITE = 1,\n\tPERF_COUNT_HW_CACHE_OP_PREFETCH = 2,\n\tPERF_COUNT_HW_CACHE_OP_MAX = 3,\n};\n\nenum perf_hw_cache_op_result_id {\n\tPERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,\n\tPERF_COUNT_HW_CACHE_RESULT_MISS = 1,\n\tPERF_COUNT_HW_CACHE_RESULT_MAX = 2,\n};\n\nenum perf_event_sample_format {\n\tPERF_SAMPLE_IP = 1,\n\tPERF_SAMPLE_TID = 2,\n\tPERF_SAMPLE_TIME = 4,\n\tPERF_SAMPLE_ADDR = 8,\n\tPERF_SAMPLE_READ = 16,\n\tPERF_SAMPLE_CALLCHAIN = 32,\n\tPERF_SAMPLE_ID = 64,\n\tPERF_SAMPLE_CPU = 128,\n\tPERF_SAMPLE_PERIOD = 256,\n\tPERF_SAMPLE_STREAM_ID = 512,\n\tPERF_SAMPLE_RAW = 1024,\n\tPERF_SAMPLE_BRANCH_STACK = 2048,\n\tPERF_SAMPLE_REGS_USER = 4096,\n\tPERF_SAMPLE_STACK_USER = 8192,\n\tPERF_SAMPLE_WEIGHT = 16384,\n\tPERF_SAMPLE_DATA_SRC = 32768,\n\tPERF_SAMPLE_IDENTIFIER = 65536,\n\tPERF_SAMPLE_TRANSACTION = 131072,\n\tPERF_SAMPLE_REGS_INTR = 262144,\n\tPERF_SAMPLE_PHYS_ADDR = 524288,\n\tPERF_SAMPLE_AUX = 1048576,\n\tPERF_SAMPLE_CGROUP = 2097152,\n\tPERF_SAMPLE_MAX = 4194304,\n\t__PERF_SAMPLE_CALLCHAIN_EARLY = 0,\n};\n\nenum perf_branch_sample_type {\n\tPERF_SAMPLE_BRANCH_USER = 1,\n\tPERF_SAMPLE_BRANCH_KERNEL = 2,\n\tPERF_SAMPLE_BRANCH_HV = 4,\n\tPERF_SAMPLE_BRANCH_ANY = 8,\n\tPERF_SAMPLE_BRANCH_ANY_CALL = 16,\n\tPERF_SAMPLE_BRANCH_ANY_RETURN = 32,\n\tPERF_SAMPLE_BRANCH_IND_CALL = 64,\n\tPERF_SAMPLE_BRANCH_ABORT_TX = 128,\n\tPERF_SAMPLE_BRANCH_IN_TX = 256,\n\tPERF_SAMPLE_BRANCH_NO_TX = 512,\n\tPERF_SAMPLE_BRANCH_COND = 1024,\n\tPERF_SAMPLE_BRANCH_CALL_STACK = 2048,\n\tPERF_SAMPLE_BRANCH_IND_JUMP = 4096,\n\tPERF_SAMPLE_BRANCH_CALL = 8192,\n\tPERF_SAMPLE_BRANCH_NO_FLAGS = 16384,\n\tPERF_SAMPLE_BRANCH_NO_CYCLES = 32768,\n\tPERF_SAMPLE_BRANCH_TYPE_SAVE = 65536,\n\tPERF_SAMPLE_BRANCH_HW_INDEX = 131072,\n\tPERF_SAMPLE_BRANCH_MAX = 262144,\n};\n\nstruct perf_event_mmap_page {\n\t__u32 version;\n\t__u32 compat_version;\n\t__u32 lock;\n\t__u32 index;\n\t__s64 offset;\n\t__u64 time_enabled;\n\t__u64 time_running;\n\tunion {\n\t\t__u64 capabilities;\n\t\tstruct {\n\t\t\t__u64 cap_bit0: 1;\n\t\t\t__u64 cap_bit0_is_deprecated: 1;\n\t\t\t__u64 cap_user_rdpmc: 1;\n\t\t\t__u64 cap_user_time: 1;\n\t\t\t__u64 cap_user_time_zero: 1;\n\t\t\t__u64 cap_____res: 59;\n\t\t};\n\t};\n\t__u16 pmc_width;\n\t__u16 time_shift;\n\t__u32 time_mult;\n\t__u64 time_offset;\n\t__u64 time_zero;\n\t__u32 size;\n\t__u8 __reserved[948];\n\t__u64 data_head;\n\t__u64 data_tail;\n\t__u64 data_offset;\n\t__u64 data_size;\n\t__u64 aux_head;\n\t__u64 aux_tail;\n\t__u64 aux_offset;\n\t__u64 aux_size;\n};\n\nstruct ldt_struct {\n\tstruct desc_struct *entries;\n\tunsigned int nr_entries;\n\tint slot;\n};\n\nstruct x86_pmu_capability {\n\tint version;\n\tint num_counters_gp;\n\tint num_counters_fixed;\n\tint bit_width_gp;\n\tint bit_width_fixed;\n\tunsigned int events_mask;\n\tint events_mask_len;\n};\n\nenum stack_type {\n\tSTACK_TYPE_UNKNOWN = 0,\n\tSTACK_TYPE_TASK = 1,\n\tSTACK_TYPE_IRQ = 2,\n\tSTACK_TYPE_SOFTIRQ = 3,\n\tSTACK_TYPE_ENTRY = 4,\n\tSTACK_TYPE_EXCEPTION = 5,\n\tSTACK_TYPE_EXCEPTION_LAST = 8,\n};\n\nstruct stack_info {\n\tenum stack_type type;\n\tlong unsigned int *begin;\n\tlong unsigned int *end;\n\tlong unsigned int *next_sp;\n};\n\nstruct stack_frame {\n\tstruct stack_frame *next_frame;\n\tlong unsigned int return_address;\n};\n\nstruct stack_frame_ia32 {\n\tu32 next_frame;\n\tu32 return_address;\n};\n\nstruct perf_guest_switch_msr {\n\tunsigned int msr;\n\tu64 host;\n\tu64 guest;\n};\n\nstruct device_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device *, struct device_attribute *, char *);\n\tssize_t (*store)(struct device *, struct device_attribute *, const char *, size_t);\n};\n\nenum perf_event_x86_regs {\n\tPERF_REG_X86_AX = 0,\n\tPERF_REG_X86_BX = 1,\n\tPERF_REG_X86_CX = 2,\n\tPERF_REG_X86_DX = 3,\n\tPERF_REG_X86_SI = 4,\n\tPERF_REG_X86_DI = 5,\n\tPERF_REG_X86_BP = 6,\n\tPERF_REG_X86_SP = 7,\n\tPERF_REG_X86_IP = 8,\n\tPERF_REG_X86_FLAGS = 9,\n\tPERF_REG_X86_CS = 10,\n\tPERF_REG_X86_SS = 11,\n\tPERF_REG_X86_DS = 12,\n\tPERF_REG_X86_ES = 13,\n\tPERF_REG_X86_FS = 14,\n\tPERF_REG_X86_GS = 15,\n\tPERF_REG_X86_R8 = 16,\n\tPERF_REG_X86_R9 = 17,\n\tPERF_REG_X86_R10 = 18,\n\tPERF_REG_X86_R11 = 19,\n\tPERF_REG_X86_R12 = 20,\n\tPERF_REG_X86_R13 = 21,\n\tPERF_REG_X86_R14 = 22,\n\tPERF_REG_X86_R15 = 23,\n\tPERF_REG_X86_32_MAX = 16,\n\tPERF_REG_X86_64_MAX = 24,\n\tPERF_REG_X86_XMM0 = 32,\n\tPERF_REG_X86_XMM1 = 34,\n\tPERF_REG_X86_XMM2 = 36,\n\tPERF_REG_X86_XMM3 = 38,\n\tPERF_REG_X86_XMM4 = 40,\n\tPERF_REG_X86_XMM5 = 42,\n\tPERF_REG_X86_XMM6 = 44,\n\tPERF_REG_X86_XMM7 = 46,\n\tPERF_REG_X86_XMM8 = 48,\n\tPERF_REG_X86_XMM9 = 50,\n\tPERF_REG_X86_XMM10 = 52,\n\tPERF_REG_X86_XMM11 = 54,\n\tPERF_REG_X86_XMM12 = 56,\n\tPERF_REG_X86_XMM13 = 58,\n\tPERF_REG_X86_XMM14 = 60,\n\tPERF_REG_X86_XMM15 = 62,\n\tPERF_REG_X86_XMM_MAX = 64,\n};\n\nstruct perf_callchain_entry_ctx {\n\tstruct perf_callchain_entry *entry;\n\tu32 max_stack;\n\tu32 nr;\n\tshort int contexts;\n\tbool contexts_maxed;\n};\n\nstruct perf_pmu_events_attr {\n\tstruct device_attribute attr;\n\tu64 id;\n\tconst char *event_str;\n};\n\nstruct perf_pmu_events_ht_attr {\n\tstruct device_attribute attr;\n\tu64 id;\n\tconst char *event_str_ht;\n\tconst char *event_str_noht;\n};\n\nenum {\n\tNMI_LOCAL = 0,\n\tNMI_UNKNOWN = 1,\n\tNMI_SERR = 2,\n\tNMI_IO_CHECK = 3,\n\tNMI_MAX = 4,\n};\n\ntypedef int (*nmi_handler_t)(unsigned int, struct pt_regs *);\n\nstruct nmiaction {\n\tstruct list_head list;\n\tnmi_handler_t handler;\n\tu64 max_duration;\n\tlong unsigned int flags;\n\tconst char *name;\n};\n\nstruct cyc2ns_data {\n\tu32 cyc2ns_mul;\n\tu32 cyc2ns_shift;\n\tu64 cyc2ns_offset;\n};\n\nstruct unwind_state {\n\tstruct stack_info stack_info;\n\tlong unsigned int stack_mask;\n\tstruct task_struct *task;\n\tint graph_idx;\n\tbool error;\n\tbool signal;\n\tbool full_regs;\n\tlong unsigned int sp;\n\tlong unsigned int bp;\n\tlong unsigned int ip;\n\tstruct pt_regs *regs;\n\tstruct pt_regs *prev_regs;\n};\n\nenum extra_reg_type {\n\tEXTRA_REG_NONE = 4294967295,\n\tEXTRA_REG_RSP_0 = 0,\n\tEXTRA_REG_RSP_1 = 1,\n\tEXTRA_REG_LBR = 2,\n\tEXTRA_REG_LDLAT = 3,\n\tEXTRA_REG_FE = 4,\n\tEXTRA_REG_MAX = 5,\n};\n\nstruct event_constraint {\n\tunion {\n\t\tlong unsigned int idxmsk[1];\n\t\tu64 idxmsk64;\n\t};\n\tu64 code;\n\tu64 cmask;\n\tint weight;\n\tint overlap;\n\tint flags;\n\tunsigned int size;\n};\n\nstruct amd_nb {\n\tint nb_id;\n\tint refcnt;\n\tstruct perf_event *owners[64];\n\tstruct event_constraint event_constraints[64];\n};\n\nstruct er_account {\n\traw_spinlock_t lock;\n\tu64 config;\n\tu64 reg;\n\tatomic_t ref;\n};\n\nstruct intel_shared_regs {\n\tstruct er_account regs[5];\n\tint refcnt;\n\tunsigned int core_id;\n};\n\nenum intel_excl_state_type {\n\tINTEL_EXCL_UNUSED = 0,\n\tINTEL_EXCL_SHARED = 1,\n\tINTEL_EXCL_EXCLUSIVE = 2,\n};\n\nstruct intel_excl_states {\n\tenum intel_excl_state_type state[64];\n\tbool sched_started;\n};\n\nstruct intel_excl_cntrs {\n\traw_spinlock_t lock;\n\tstruct intel_excl_states states[2];\n\tunion {\n\t\tu16 has_exclusive[2];\n\t\tu32 exclusive_present;\n\t};\n\tint refcnt;\n\tunsigned int core_id;\n};\n\nenum {\n\tX86_PERF_KFREE_SHARED = 0,\n\tX86_PERF_KFREE_EXCL = 1,\n\tX86_PERF_KFREE_MAX = 2,\n};\n\nstruct x86_perf_task_context;\n\nstruct cpu_hw_events {\n\tstruct perf_event *events[64];\n\tlong unsigned int active_mask[1];\n\tlong unsigned int running[1];\n\tint enabled;\n\tint n_events;\n\tint n_added;\n\tint n_txn;\n\tint assign[64];\n\tu64 tags[64];\n\tstruct perf_event *event_list[64];\n\tstruct event_constraint *event_constraint[64];\n\tint n_excl;\n\tunsigned int txn_flags;\n\tint is_fake;\n\tstruct debug_store *ds;\n\tvoid *ds_pebs_vaddr;\n\tvoid *ds_bts_vaddr;\n\tu64 pebs_enabled;\n\tint n_pebs;\n\tint n_large_pebs;\n\tint n_pebs_via_pt;\n\tint pebs_output;\n\tu64 pebs_data_cfg;\n\tu64 active_pebs_data_cfg;\n\tint pebs_record_size;\n\tint lbr_users;\n\tint lbr_pebs_users;\n\tstruct perf_branch_stack lbr_stack;\n\tstruct perf_branch_entry lbr_entries[32];\n\tstruct er_account *lbr_sel;\n\tu64 br_sel;\n\tstruct x86_perf_task_context *last_task_ctx;\n\tint last_log_id;\n\tu64 intel_ctrl_guest_mask;\n\tu64 intel_ctrl_host_mask;\n\tstruct perf_guest_switch_msr guest_switch_msrs[64];\n\tu64 intel_cp_status;\n\tstruct intel_shared_regs *shared_regs;\n\tstruct event_constraint *constraint_list;\n\tstruct intel_excl_cntrs *excl_cntrs;\n\tint excl_thread_id;\n\tu64 tfa_shadow;\n\tstruct amd_nb *amd_nb;\n\tu64 perf_ctr_virt_mask;\n\tint n_pair;\n\tvoid *kfree_on_online[2];\n};\n\nstruct x86_perf_task_context {\n\tu64 lbr_from[32];\n\tu64 lbr_to[32];\n\tu64 lbr_info[32];\n\tint tos;\n\tint valid_lbrs;\n\tint lbr_callstack_users;\n\tint lbr_stack_state;\n\tint log_id;\n};\n\nstruct extra_reg {\n\tunsigned int event;\n\tunsigned int msr;\n\tu64 config_mask;\n\tu64 valid_mask;\n\tint idx;\n\tbool extra_msr_access;\n};\n\nunion perf_capabilities {\n\tstruct {\n\t\tu64 lbr_format: 6;\n\t\tu64 pebs_trap: 1;\n\t\tu64 pebs_arch_reg: 1;\n\t\tu64 pebs_format: 4;\n\t\tu64 smm_freeze: 1;\n\t\tu64 full_width_write: 1;\n\t\tu64 pebs_baseline: 1;\n\t\tu64 pebs_metrics_available: 1;\n\t\tu64 pebs_output_pt_available: 1;\n\t};\n\tu64 capabilities;\n};\n\nstruct x86_pmu_quirk {\n\tstruct x86_pmu_quirk *next;\n\tvoid (*func)();\n};\n\nenum {\n\tx86_lbr_exclusive_lbr = 0,\n\tx86_lbr_exclusive_bts = 1,\n\tx86_lbr_exclusive_pt = 2,\n\tx86_lbr_exclusive_max = 3,\n};\n\nstruct x86_pmu {\n\tconst char *name;\n\tint version;\n\tint (*handle_irq)(struct pt_regs *);\n\tvoid (*disable_all)();\n\tvoid (*enable_all)(int);\n\tvoid (*enable)(struct perf_event *);\n\tvoid (*disable)(struct perf_event *);\n\tvoid (*add)(struct perf_event *);\n\tvoid (*del)(struct perf_event *);\n\tvoid (*read)(struct perf_event *);\n\tint (*hw_config)(struct perf_event *);\n\tint (*schedule_events)(struct cpu_hw_events *, int, int *);\n\tunsigned int eventsel;\n\tunsigned int perfctr;\n\tint (*addr_offset)(int, bool);\n\tint (*rdpmc_index)(int);\n\tu64 (*event_map)(int);\n\tint max_events;\n\tint num_counters;\n\tint num_counters_fixed;\n\tint cntval_bits;\n\tu64 cntval_mask;\n\tunion {\n\t\tlong unsigned int events_maskl;\n\t\tlong unsigned int events_mask[1];\n\t};\n\tint events_mask_len;\n\tint apic;\n\tu64 max_period;\n\tstruct event_constraint * (*get_event_constraints)(struct cpu_hw_events *, int, struct perf_event *);\n\tvoid (*put_event_constraints)(struct cpu_hw_events *, struct perf_event *);\n\tvoid (*start_scheduling)(struct cpu_hw_events *);\n\tvoid (*commit_scheduling)(struct cpu_hw_events *, int, int);\n\tvoid (*stop_scheduling)(struct cpu_hw_events *);\n\tstruct event_constraint *event_constraints;\n\tstruct x86_pmu_quirk *quirks;\n\tint perfctr_second_write;\n\tu64 (*limit_period)(struct perf_event *, u64);\n\tunsigned int late_ack: 1;\n\tunsigned int enabled_ack: 1;\n\tunsigned int counter_freezing: 1;\n\tint attr_rdpmc_broken;\n\tint attr_rdpmc;\n\tstruct attribute **format_attrs;\n\tssize_t (*events_sysfs_show)(char *, u64);\n\tconst struct attribute_group **attr_update;\n\tlong unsigned int attr_freeze_on_smi;\n\tint (*cpu_prepare)(int);\n\tvoid (*cpu_starting)(int);\n\tvoid (*cpu_dying)(int);\n\tvoid (*cpu_dead)(int);\n\tvoid (*check_microcode)();\n\tvoid (*sched_task)(struct perf_event_context *, bool);\n\tu64 intel_ctrl;\n\tunion perf_capabilities intel_cap;\n\tunsigned int bts: 1;\n\tunsigned int bts_active: 1;\n\tunsigned int pebs: 1;\n\tunsigned int pebs_active: 1;\n\tunsigned int pebs_broken: 1;\n\tunsigned int pebs_prec_dist: 1;\n\tunsigned int pebs_no_tlb: 1;\n\tunsigned int pebs_no_isolation: 1;\n\tint pebs_record_size;\n\tint pebs_buffer_size;\n\tint max_pebs_events;\n\tvoid (*drain_pebs)(struct pt_regs *);\n\tstruct event_constraint *pebs_constraints;\n\tvoid (*pebs_aliases)(struct perf_event *);\n\tlong unsigned int large_pebs_flags;\n\tu64 rtm_abort_event;\n\tlong unsigned int lbr_tos;\n\tlong unsigned int lbr_from;\n\tlong unsigned int lbr_to;\n\tint lbr_nr;\n\tu64 lbr_sel_mask;\n\tconst int *lbr_sel_map;\n\tbool lbr_double_abort;\n\tbool lbr_pt_coexist;\n\tatomic_t lbr_exclusive[3];\n\tvoid (*swap_task_ctx)(struct perf_event_context *, struct perf_event_context *);\n\tunsigned int amd_nb_constraints: 1;\n\tu64 perf_ctr_pair_en;\n\tstruct extra_reg *extra_regs;\n\tunsigned int flags;\n\tstruct perf_guest_switch_msr * (*guest_get_msrs)(int *);\n\tint (*check_period)(struct perf_event *, u64);\n\tint (*aux_output_match)(struct perf_event *);\n};\n\nstruct sched_state {\n\tint weight;\n\tint event;\n\tint counter;\n\tint unassigned;\n\tint nr_gp;\n\tu64 used;\n};\n\nstruct perf_sched {\n\tint max_weight;\n\tint max_events;\n\tint max_gp;\n\tint saved_states;\n\tstruct event_constraint **constraints;\n\tstruct sched_state state;\n\tstruct sched_state saved[2];\n};\n\ntypedef int pao_T__;\n\ntypedef int pto_T_____2;\n\ntypedef unsigned int pao_T_____2;\n\nenum migratetype {\n\tMIGRATE_UNMOVABLE = 0,\n\tMIGRATE_MOVABLE = 1,\n\tMIGRATE_RECLAIMABLE = 2,\n\tMIGRATE_PCPTYPES = 3,\n\tMIGRATE_HIGHATOMIC = 3,\n\tMIGRATE_TYPES = 4,\n};\n\nenum lru_list {\n\tLRU_INACTIVE_ANON = 0,\n\tLRU_ACTIVE_ANON = 1,\n\tLRU_INACTIVE_FILE = 2,\n\tLRU_ACTIVE_FILE = 3,\n\tLRU_UNEVICTABLE = 4,\n\tNR_LRU_LISTS = 5,\n};\n\nenum zone_watermarks {\n\tWMARK_MIN = 0,\n\tWMARK_LOW = 1,\n\tWMARK_HIGH = 2,\n\tNR_WMARK = 3,\n};\n\nenum {\n\tZONELIST_FALLBACK = 0,\n\tZONELIST_NOFALLBACK = 1,\n\tMAX_ZONELISTS = 2,\n};\n\nstruct perf_msr {\n\tu64 msr;\n\tstruct attribute_group *grp;\n\tbool (*test)(int, void *);\n\tbool no_check;\n};\n\ntypedef void (*exitcall_t)();\n\nenum hrtimer_mode {\n\tHRTIMER_MODE_ABS = 0,\n\tHRTIMER_MODE_REL = 1,\n\tHRTIMER_MODE_PINNED = 2,\n\tHRTIMER_MODE_SOFT = 4,\n\tHRTIMER_MODE_HARD = 8,\n\tHRTIMER_MODE_ABS_PINNED = 2,\n\tHRTIMER_MODE_REL_PINNED = 3,\n\tHRTIMER_MODE_ABS_SOFT = 4,\n\tHRTIMER_MODE_REL_SOFT = 5,\n\tHRTIMER_MODE_ABS_PINNED_SOFT = 6,\n\tHRTIMER_MODE_REL_PINNED_SOFT = 7,\n\tHRTIMER_MODE_ABS_HARD = 8,\n\tHRTIMER_MODE_REL_HARD = 9,\n\tHRTIMER_MODE_ABS_PINNED_HARD = 10,\n\tHRTIMER_MODE_REL_PINNED_HARD = 11,\n};\n\nstruct x86_cpu_id {\n\t__u16 vendor;\n\t__u16 family;\n\t__u16 model;\n\t__u16 steppings;\n\t__u16 feature;\n\tkernel_ulong_t driver_data;\n};\n\nenum perf_rapl_events {\n\tPERF_RAPL_PP0 = 0,\n\tPERF_RAPL_PKG = 1,\n\tPERF_RAPL_RAM = 2,\n\tPERF_RAPL_PP1 = 3,\n\tPERF_RAPL_PSYS = 4,\n\tPERF_RAPL_MAX = 5,\n\tNR_RAPL_DOMAINS = 5,\n};\n\nstruct rapl_pmu {\n\traw_spinlock_t lock;\n\tint n_active;\n\tint cpu;\n\tstruct list_head active_list;\n\tstruct pmu *pmu;\n\tktime_t timer_interval;\n\tstruct hrtimer hrtimer;\n};\n\nstruct rapl_pmus {\n\tstruct pmu pmu;\n\tunsigned int maxdie;\n\tstruct rapl_pmu *pmus[0];\n};\n\nstruct rapl_model {\n\tstruct perf_msr *rapl_msrs;\n\tlong unsigned int events;\n\tunsigned int msr_power_unit;\n\tbool apply_quirk;\n};\n\nstruct amd_uncore {\n\tint id;\n\tint refcnt;\n\tint cpu;\n\tint num_counters;\n\tint rdpmc_base;\n\tu32 msr_base;\n\tcpumask_t *active_mask;\n\tstruct pmu *pmu;\n\tstruct perf_event *events[6];\n\tstruct hlist_node node;\n};\n\ntypedef int pci_power_t;\n\ntypedef unsigned int pci_channel_state_t;\n\ntypedef short unsigned int pci_dev_flags_t;\n\nstruct pci_bus;\n\nstruct pci_slot;\n\nstruct aer_stats;\n\nstruct pci_driver;\n\nstruct pcie_link_state;\n\nstruct pci_vpd;\n\nstruct pci_sriov;\n\nstruct pci_dev {\n\tstruct list_head bus_list;\n\tstruct pci_bus *bus;\n\tstruct pci_bus *subordinate;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procent;\n\tstruct pci_slot *slot;\n\tunsigned int devfn;\n\tshort unsigned int vendor;\n\tshort unsigned int device;\n\tshort unsigned int subsystem_vendor;\n\tshort unsigned int subsystem_device;\n\tunsigned int class;\n\tu8 revision;\n\tu8 hdr_type;\n\tu16 aer_cap;\n\tstruct aer_stats *aer_stats;\n\tu8 pcie_cap;\n\tu8 msi_cap;\n\tu8 msix_cap;\n\tu8 pcie_mpss: 3;\n\tu8 rom_base_reg;\n\tu8 pin;\n\tu16 pcie_flags_reg;\n\tlong unsigned int *dma_alias_mask;\n\tstruct pci_driver *driver;\n\tu64 dma_mask;\n\tstruct device_dma_parameters dma_parms;\n\tpci_power_t current_state;\n\tunsigned int imm_ready: 1;\n\tu8 pm_cap;\n\tunsigned int pme_support: 5;\n\tunsigned int pme_poll: 1;\n\tunsigned int d1_support: 1;\n\tunsigned int d2_support: 1;\n\tunsigned int no_d1d2: 1;\n\tunsigned int no_d3cold: 1;\n\tunsigned int bridge_d3: 1;\n\tunsigned int d3cold_allowed: 1;\n\tunsigned int mmio_always_on: 1;\n\tunsigned int wakeup_prepared: 1;\n\tunsigned int runtime_d3cold: 1;\n\tunsigned int skip_bus_pm: 1;\n\tunsigned int ignore_hotplug: 1;\n\tunsigned int hotplug_user_indicators: 1;\n\tunsigned int clear_retrain_link: 1;\n\tunsigned int d3_delay;\n\tunsigned int d3cold_delay;\n\tstruct pcie_link_state *link_state;\n\tunsigned int ltr_path: 1;\n\tunsigned int eetlp_prefix_path: 1;\n\tpci_channel_state_t error_state;\n\tstruct device dev;\n\tint cfg_size;\n\tunsigned int irq;\n\tstruct resource resource[11];\n\tbool match_driver;\n\tunsigned int transparent: 1;\n\tunsigned int io_window: 1;\n\tunsigned int pref_window: 1;\n\tunsigned int pref_64_window: 1;\n\tunsigned int multifunction: 1;\n\tunsigned int is_busmaster: 1;\n\tunsigned int no_msi: 1;\n\tunsigned int no_64bit_msi: 1;\n\tunsigned int block_cfg_access: 1;\n\tunsigned int broken_parity_status: 1;\n\tunsigned int irq_reroute_variant: 2;\n\tunsigned int msi_enabled: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int ari_enabled: 1;\n\tunsigned int ats_enabled: 1;\n\tunsigned int pasid_enabled: 1;\n\tunsigned int pri_enabled: 1;\n\tunsigned int is_managed: 1;\n\tunsigned int needs_freset: 1;\n\tunsigned int state_saved: 1;\n\tunsigned int is_physfn: 1;\n\tunsigned int is_virtfn: 1;\n\tunsigned int reset_fn: 1;\n\tunsigned int is_hotplug_bridge: 1;\n\tunsigned int shpc_managed: 1;\n\tunsigned int is_thunderbolt: 1;\n\tunsigned int untrusted: 1;\n\tunsigned int broken_intx_masking: 1;\n\tunsigned int io_window_1k: 1;\n\tunsigned int irq_managed: 1;\n\tunsigned int non_compliant_bars: 1;\n\tunsigned int is_probed: 1;\n\tunsigned int link_active_reporting: 1;\n\tunsigned int no_vf_scan: 1;\n\tpci_dev_flags_t dev_flags;\n\tatomic_t enable_cnt;\n\tu32 saved_config_space[16];\n\tstruct hlist_head saved_cap_space;\n\tstruct bin_attribute *rom_attr;\n\tint rom_attr_enabled;\n\tstruct bin_attribute *res_attr[11];\n\tstruct bin_attribute *res_attr_wc[11];\n\tconst struct attribute_group **msi_irq_groups;\n\tstruct pci_vpd *vpd;\n\tunion {\n\t\tstruct pci_sriov *sriov;\n\t\tstruct pci_dev *physfn;\n\t};\n\tu16 ats_cap;\n\tu8 ats_stu;\n\tu16 pri_cap;\n\tu32 pri_reqs_alloc;\n\tunsigned int pasid_required: 1;\n\tu16 pasid_cap;\n\tu16 pasid_features;\n\tphys_addr_t rom;\n\tsize_t romlen;\n\tchar *driver_override;\n\tlong unsigned int priv_flags;\n};\n\nstruct pci_device_id {\n\t__u32 vendor;\n\t__u32 device;\n\t__u32 subvendor;\n\t__u32 subdevice;\n\t__u32 class;\n\t__u32 class_mask;\n\tkernel_ulong_t driver_data;\n};\n\nstruct hotplug_slot;\n\nstruct pci_slot {\n\tstruct pci_bus *bus;\n\tstruct list_head list;\n\tstruct hotplug_slot *hotplug;\n\tunsigned char number;\n\tstruct kobject kobj;\n};\n\ntypedef short unsigned int pci_bus_flags_t;\n\nstruct pci_ops;\n\nstruct msi_controller;\n\nstruct pci_bus {\n\tstruct list_head node;\n\tstruct pci_bus *parent;\n\tstruct list_head children;\n\tstruct list_head devices;\n\tstruct pci_dev *self;\n\tstruct list_head slots;\n\tstruct resource *resource[4];\n\tstruct list_head resources;\n\tstruct resource busn_res;\n\tstruct pci_ops *ops;\n\tstruct msi_controller *msi;\n\tvoid *sysdata;\n\tstruct proc_dir_entry *procdir;\n\tunsigned char number;\n\tunsigned char primary;\n\tunsigned char max_bus_speed;\n\tunsigned char cur_bus_speed;\n\tchar name[48];\n\tshort unsigned int bridge_ctl;\n\tpci_bus_flags_t bus_flags;\n\tstruct device *bridge;\n\tstruct device dev;\n\tstruct bin_attribute *legacy_io;\n\tstruct bin_attribute *legacy_mem;\n\tunsigned int is_added: 1;\n};\n\nenum {\n\tPCI_STD_RESOURCES = 0,\n\tPCI_STD_RESOURCE_END = 5,\n\tPCI_ROM_RESOURCE = 6,\n\tPCI_BRIDGE_RESOURCES = 7,\n\tPCI_BRIDGE_RESOURCE_END = 10,\n\tPCI_NUM_RESOURCES = 11,\n\tDEVICE_COUNT_RESOURCE = 11,\n};\n\nenum pci_channel_state {\n\tpci_channel_io_normal = 1,\n\tpci_channel_io_frozen = 2,\n\tpci_channel_io_perm_failure = 3,\n};\n\ntypedef unsigned int pcie_reset_state_t;\n\nstruct pci_dynids {\n\tspinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct pci_error_handlers;\n\nstruct pci_driver {\n\tstruct list_head node;\n\tconst char *name;\n\tconst struct pci_device_id *id_table;\n\tint (*probe)(struct pci_dev *, const struct pci_device_id *);\n\tvoid (*remove)(struct pci_dev *);\n\tint (*suspend)(struct pci_dev *, pm_message_t);\n\tint (*resume)(struct pci_dev *);\n\tvoid (*shutdown)(struct pci_dev *);\n\tint (*sriov_configure)(struct pci_dev *, int);\n\tconst struct pci_error_handlers *err_handler;\n\tconst struct attribute_group **groups;\n\tstruct device_driver driver;\n\tstruct pci_dynids dynids;\n};\n\nstruct pci_ops {\n\tint (*add_bus)(struct pci_bus *);\n\tvoid (*remove_bus)(struct pci_bus *);\n\tvoid * (*map_bus)(struct pci_bus *, unsigned int, int);\n\tint (*read)(struct pci_bus *, unsigned int, int, int, u32 *);\n\tint (*write)(struct pci_bus *, unsigned int, int, int, u32);\n};\n\ntypedef unsigned int pci_ers_result_t;\n\nstruct pci_error_handlers {\n\tpci_ers_result_t (*error_detected)(struct pci_dev *, enum pci_channel_state);\n\tpci_ers_result_t (*mmio_enabled)(struct pci_dev *);\n\tpci_ers_result_t (*slot_reset)(struct pci_dev *);\n\tvoid (*reset_prepare)(struct pci_dev *);\n\tvoid (*reset_done)(struct pci_dev *);\n\tvoid (*resume)(struct pci_dev *);\n};\n\nenum pcie_bus_config_types {\n\tPCIE_BUS_TUNE_OFF = 0,\n\tPCIE_BUS_DEFAULT = 1,\n\tPCIE_BUS_SAFE = 2,\n\tPCIE_BUS_PERFORMANCE = 3,\n\tPCIE_BUS_PEER2PEER = 4,\n};\n\nstruct syscore_ops {\n\tstruct list_head node;\n\tint (*suspend)();\n\tvoid (*resume)();\n\tvoid (*shutdown)();\n};\n\nenum ibs_states {\n\tIBS_ENABLED = 0,\n\tIBS_STARTED = 1,\n\tIBS_STOPPING = 2,\n\tIBS_STOPPED = 3,\n\tIBS_MAX_STATES = 4,\n};\n\nstruct cpu_perf_ibs {\n\tstruct perf_event *event;\n\tlong unsigned int state[1];\n};\n\nstruct perf_ibs {\n\tstruct pmu pmu;\n\tunsigned int msr;\n\tu64 config_mask;\n\tu64 cnt_mask;\n\tu64 enable_mask;\n\tu64 valid_mask;\n\tu64 max_period;\n\tlong unsigned int offset_mask[1];\n\tint offset_max;\n\tstruct cpu_perf_ibs *pcpu;\n\tstruct attribute **format_attrs;\n\tstruct attribute_group format_group;\n\tconst struct attribute_group *attr_groups[2];\n\tu64 (*get_count)(u64);\n};\n\nstruct perf_ibs_data {\n\tu32 size;\n\tunion {\n\t\tu32 data[0];\n\t\tu32 caps;\n\t};\n\tu64 regs[8];\n};\n\nstruct amd_iommu;\n\nstruct perf_amd_iommu {\n\tstruct list_head list;\n\tstruct pmu pmu;\n\tstruct amd_iommu *iommu;\n\tchar name[16];\n\tu8 max_banks;\n\tu8 max_counters;\n\tu64 cntr_assign_mask;\n\traw_spinlock_t lock;\n};\n\nstruct amd_iommu_event_desc {\n\tstruct kobj_attribute attr;\n\tconst char *event;\n};\n\nenum perf_msr_id {\n\tPERF_MSR_TSC = 0,\n\tPERF_MSR_APERF = 1,\n\tPERF_MSR_MPERF = 2,\n\tPERF_MSR_PPERF = 3,\n\tPERF_MSR_SMI = 4,\n\tPERF_MSR_PTSC = 5,\n\tPERF_MSR_IRPERF = 6,\n\tPERF_MSR_THERM = 7,\n\tPERF_MSR_EVENT_MAX = 8,\n};\n\nstruct x86_cpu_desc {\n\tu8 x86_family;\n\tu8 x86_vendor;\n\tu8 x86_model;\n\tu8 x86_stepping;\n\tu32 x86_microcode_rev;\n};\n\nunion cpuid10_eax {\n\tstruct {\n\t\tunsigned int version_id: 8;\n\t\tunsigned int num_counters: 8;\n\t\tunsigned int bit_width: 8;\n\t\tunsigned int mask_length: 8;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid10_ebx {\n\tstruct {\n\t\tunsigned int no_unhalted_core_cycles: 1;\n\t\tunsigned int no_instructions_retired: 1;\n\t\tunsigned int no_unhalted_reference_cycles: 1;\n\t\tunsigned int no_llc_reference: 1;\n\t\tunsigned int no_llc_misses: 1;\n\t\tunsigned int no_branch_instruction_retired: 1;\n\t\tunsigned int no_branch_misses_retired: 1;\n\t} split;\n\tunsigned int full;\n};\n\nunion cpuid10_edx {\n\tstruct {\n\t\tunsigned int num_counters_fixed: 5;\n\t\tunsigned int bit_width_fixed: 8;\n\t\tunsigned int reserved: 19;\n\t} split;\n\tunsigned int full;\n};\n\nunion x86_pmu_config {\n\tstruct {\n\t\tu64 event: 8;\n\t\tu64 umask: 8;\n\t\tu64 usr: 1;\n\t\tu64 os: 1;\n\t\tu64 edge: 1;\n\t\tu64 pc: 1;\n\t\tu64 interrupt: 1;\n\t\tu64 __reserved1: 1;\n\t\tu64 en: 1;\n\t\tu64 inv: 1;\n\t\tu64 cmask: 8;\n\t\tu64 event2: 4;\n\t\tu64 __reserved2: 4;\n\t\tu64 go: 1;\n\t\tu64 ho: 1;\n\t} bits;\n\tu64 value;\n};\n\nenum pageflags {\n\tPG_locked = 0,\n\tPG_referenced = 1,\n\tPG_uptodate = 2,\n\tPG_dirty = 3,\n\tPG_lru = 4,\n\tPG_active = 5,\n\tPG_workingset = 6,\n\tPG_waiters = 7,\n\tPG_error = 8,\n\tPG_slab = 9,\n\tPG_owner_priv_1 = 10,\n\tPG_arch_1 = 11,\n\tPG_reserved = 12,\n\tPG_private = 13,\n\tPG_private_2 = 14,\n\tPG_writeback = 15,\n\tPG_head = 16,\n\tPG_mappedtodisk = 17,\n\tPG_reclaim = 18,\n\tPG_swapbacked = 19,\n\tPG_unevictable = 20,\n\tPG_mlocked = 21,\n\tPG_uncached = 22,\n\t__NR_PAGEFLAGS = 23,\n\tPG_checked = 10,\n\tPG_swapcache = 10,\n\tPG_fscache = 14,\n\tPG_pinned = 10,\n\tPG_savepinned = 3,\n\tPG_foreign = 10,\n\tPG_xen_remapped = 10,\n\tPG_slob_free = 13,\n\tPG_double_map = 14,\n\tPG_isolated = 18,\n\tPG_reported = 2,\n};\n\nstruct bts_ctx {\n\tstruct perf_output_handle handle;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct debug_store ds_back;\n\tint state;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nenum {\n\tBTS_STATE_STOPPED = 0,\n\tBTS_STATE_INACTIVE = 1,\n\tBTS_STATE_ACTIVE = 2,\n};\n\nstruct bts_phys {\n\tstruct page *page;\n\tlong unsigned int size;\n\tlong unsigned int offset;\n\tlong unsigned int displacement;\n};\n\nstruct bts_buffer {\n\tsize_t real_size;\n\tunsigned int nr_pages;\n\tunsigned int nr_bufs;\n\tunsigned int cur_buf;\n\tbool snapshot;\n\tlocal_t data_size;\n\tlocal_t head;\n\tlong unsigned int end;\n\tvoid **data_pages;\n\tstruct bts_phys buf[0];\n};\n\nstruct pebs_basic {\n\tu64 format_size;\n\tu64 ip;\n\tu64 applicable_counters;\n\tu64 tsc;\n};\n\nstruct pebs_meminfo {\n\tu64 address;\n\tu64 aux;\n\tu64 latency;\n\tu64 tsx_tuning;\n};\n\nstruct pebs_gprs {\n\tu64 flags;\n\tu64 ip;\n\tu64 ax;\n\tu64 cx;\n\tu64 dx;\n\tu64 bx;\n\tu64 sp;\n\tu64 bp;\n\tu64 si;\n\tu64 di;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n};\n\nstruct pebs_xmm {\n\tu64 xmm[32];\n};\n\nstruct pebs_lbr_entry {\n\tu64 from;\n\tu64 to;\n\tu64 info;\n};\n\nstruct pebs_lbr {\n\tstruct pebs_lbr_entry lbr[0];\n};\n\nstruct x86_perf_regs {\n\tstruct pt_regs regs;\n\tu64 *xmm_regs;\n};\n\ntypedef unsigned int insn_attr_t;\n\ntypedef unsigned char insn_byte_t;\n\ntypedef int insn_value_t;\n\nstruct insn_field {\n\tunion {\n\t\tinsn_value_t value;\n\t\tinsn_byte_t bytes[4];\n\t};\n\tunsigned char got;\n\tunsigned char nbytes;\n};\n\nstruct insn {\n\tstruct insn_field prefixes;\n\tstruct insn_field rex_prefix;\n\tstruct insn_field vex_prefix;\n\tstruct insn_field opcode;\n\tstruct insn_field modrm;\n\tstruct insn_field sib;\n\tstruct insn_field displacement;\n\tunion {\n\t\tstruct insn_field immediate;\n\t\tstruct insn_field moffset1;\n\t\tstruct insn_field immediate1;\n\t};\n\tunion {\n\t\tstruct insn_field moffset2;\n\t\tstruct insn_field immediate2;\n\t};\n\tint emulate_prefix_size;\n\tinsn_attr_t attr;\n\tunsigned char opnd_bytes;\n\tunsigned char addr_bytes;\n\tunsigned char length;\n\tunsigned char x86_64;\n\tconst insn_byte_t *kaddr;\n\tconst insn_byte_t *end_kaddr;\n\tconst insn_byte_t *next_byte;\n};\n\nenum {\n\tPERF_TXN_ELISION = 1,\n\tPERF_TXN_TRANSACTION = 2,\n\tPERF_TXN_SYNC = 4,\n\tPERF_TXN_ASYNC = 8,\n\tPERF_TXN_RETRY = 16,\n\tPERF_TXN_CONFLICT = 32,\n\tPERF_TXN_CAPACITY_WRITE = 64,\n\tPERF_TXN_CAPACITY_READ = 128,\n\tPERF_TXN_MAX = 256,\n\tPERF_TXN_ABORT_MASK = 0,\n\tPERF_TXN_ABORT_SHIFT = 32,\n};\n\nstruct perf_event_header {\n\t__u32 type;\n\t__u16 misc;\n\t__u16 size;\n};\n\nunion intel_x86_pebs_dse {\n\tu64 val;\n\tstruct {\n\t\tunsigned int ld_dse: 4;\n\t\tunsigned int ld_stlb_miss: 1;\n\t\tunsigned int ld_locked: 1;\n\t\tunsigned int ld_reserved: 26;\n\t};\n\tstruct {\n\t\tunsigned int st_l1d_hit: 1;\n\t\tunsigned int st_reserved1: 3;\n\t\tunsigned int st_stlb_miss: 1;\n\t\tunsigned int st_locked: 1;\n\t\tunsigned int st_reserved2: 26;\n\t};\n};\n\nstruct pebs_record_core {\n\tu64 flags;\n\tu64 ip;\n\tu64 ax;\n\tu64 bx;\n\tu64 cx;\n\tu64 dx;\n\tu64 si;\n\tu64 di;\n\tu64 bp;\n\tu64 sp;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n};\n\nstruct pebs_record_nhm {\n\tu64 flags;\n\tu64 ip;\n\tu64 ax;\n\tu64 bx;\n\tu64 cx;\n\tu64 dx;\n\tu64 si;\n\tu64 di;\n\tu64 bp;\n\tu64 sp;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n\tu64 status;\n\tu64 dla;\n\tu64 dse;\n\tu64 lat;\n};\n\nunion hsw_tsx_tuning {\n\tstruct {\n\t\tu32 cycles_last_block: 32;\n\t\tu32 hle_abort: 1;\n\t\tu32 rtm_abort: 1;\n\t\tu32 instruction_abort: 1;\n\t\tu32 non_instruction_abort: 1;\n\t\tu32 retry: 1;\n\t\tu32 data_conflict: 1;\n\t\tu32 capacity_writes: 1;\n\t\tu32 capacity_reads: 1;\n\t};\n\tu64 value;\n};\n\nstruct pebs_record_skl {\n\tu64 flags;\n\tu64 ip;\n\tu64 ax;\n\tu64 bx;\n\tu64 cx;\n\tu64 dx;\n\tu64 si;\n\tu64 di;\n\tu64 bp;\n\tu64 sp;\n\tu64 r8;\n\tu64 r9;\n\tu64 r10;\n\tu64 r11;\n\tu64 r12;\n\tu64 r13;\n\tu64 r14;\n\tu64 r15;\n\tu64 status;\n\tu64 dla;\n\tu64 dse;\n\tu64 lat;\n\tu64 real_ip;\n\tu64 tsx_tuning;\n\tu64 tsc;\n};\n\nstruct bts_record {\n\tu64 from;\n\tu64 to;\n\tu64 flags;\n};\n\nenum {\n\tPERF_BR_UNKNOWN = 0,\n\tPERF_BR_COND = 1,\n\tPERF_BR_UNCOND = 2,\n\tPERF_BR_IND = 3,\n\tPERF_BR_CALL = 4,\n\tPERF_BR_IND_CALL = 5,\n\tPERF_BR_RET = 6,\n\tPERF_BR_SYSCALL = 7,\n\tPERF_BR_SYSRET = 8,\n\tPERF_BR_COND_CALL = 9,\n\tPERF_BR_COND_RET = 10,\n\tPERF_BR_MAX = 11,\n};\n\nenum {\n\tLBR_FORMAT_32 = 0,\n\tLBR_FORMAT_LIP = 1,\n\tLBR_FORMAT_EIP = 2,\n\tLBR_FORMAT_EIP_FLAGS = 3,\n\tLBR_FORMAT_EIP_FLAGS2 = 4,\n\tLBR_FORMAT_INFO = 5,\n\tLBR_FORMAT_TIME = 6,\n\tLBR_FORMAT_MAX_KNOWN = 6,\n};\n\nenum {\n\tX86_BR_NONE = 0,\n\tX86_BR_USER = 1,\n\tX86_BR_KERNEL = 2,\n\tX86_BR_CALL = 4,\n\tX86_BR_RET = 8,\n\tX86_BR_SYSCALL = 16,\n\tX86_BR_SYSRET = 32,\n\tX86_BR_INT = 64,\n\tX86_BR_IRET = 128,\n\tX86_BR_JCC = 256,\n\tX86_BR_JMP = 512,\n\tX86_BR_IRQ = 1024,\n\tX86_BR_IND_CALL = 2048,\n\tX86_BR_ABORT = 4096,\n\tX86_BR_IN_TX = 8192,\n\tX86_BR_NO_TX = 16384,\n\tX86_BR_ZERO_CALL = 32768,\n\tX86_BR_CALL_STACK = 65536,\n\tX86_BR_IND_JMP = 131072,\n\tX86_BR_TYPE_SAVE = 262144,\n};\n\nenum {\n\tLBR_NONE = 0,\n\tLBR_VALID = 1,\n};\n\nenum P4_EVENTS {\n\tP4_EVENT_TC_DELIVER_MODE = 0,\n\tP4_EVENT_BPU_FETCH_REQUEST = 1,\n\tP4_EVENT_ITLB_REFERENCE = 2,\n\tP4_EVENT_MEMORY_CANCEL = 3,\n\tP4_EVENT_MEMORY_COMPLETE = 4,\n\tP4_EVENT_LOAD_PORT_REPLAY = 5,\n\tP4_EVENT_STORE_PORT_REPLAY = 6,\n\tP4_EVENT_MOB_LOAD_REPLAY = 7,\n\tP4_EVENT_PAGE_WALK_TYPE = 8,\n\tP4_EVENT_BSQ_CACHE_REFERENCE = 9,\n\tP4_EVENT_IOQ_ALLOCATION = 10,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES = 11,\n\tP4_EVENT_FSB_DATA_ACTIVITY = 12,\n\tP4_EVENT_BSQ_ALLOCATION = 13,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES = 14,\n\tP4_EVENT_SSE_INPUT_ASSIST = 15,\n\tP4_EVENT_PACKED_SP_UOP = 16,\n\tP4_EVENT_PACKED_DP_UOP = 17,\n\tP4_EVENT_SCALAR_SP_UOP = 18,\n\tP4_EVENT_SCALAR_DP_UOP = 19,\n\tP4_EVENT_64BIT_MMX_UOP = 20,\n\tP4_EVENT_128BIT_MMX_UOP = 21,\n\tP4_EVENT_X87_FP_UOP = 22,\n\tP4_EVENT_TC_MISC = 23,\n\tP4_EVENT_GLOBAL_POWER_EVENTS = 24,\n\tP4_EVENT_TC_MS_XFER = 25,\n\tP4_EVENT_UOP_QUEUE_WRITES = 26,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE = 27,\n\tP4_EVENT_RETIRED_BRANCH_TYPE = 28,\n\tP4_EVENT_RESOURCE_STALL = 29,\n\tP4_EVENT_WC_BUFFER = 30,\n\tP4_EVENT_B2B_CYCLES = 31,\n\tP4_EVENT_BNR = 32,\n\tP4_EVENT_SNOOP = 33,\n\tP4_EVENT_RESPONSE = 34,\n\tP4_EVENT_FRONT_END_EVENT = 35,\n\tP4_EVENT_EXECUTION_EVENT = 36,\n\tP4_EVENT_REPLAY_EVENT = 37,\n\tP4_EVENT_INSTR_RETIRED = 38,\n\tP4_EVENT_UOPS_RETIRED = 39,\n\tP4_EVENT_UOP_TYPE = 40,\n\tP4_EVENT_BRANCH_RETIRED = 41,\n\tP4_EVENT_MISPRED_BRANCH_RETIRED = 42,\n\tP4_EVENT_X87_ASSIST = 43,\n\tP4_EVENT_MACHINE_CLEAR = 44,\n\tP4_EVENT_INSTR_COMPLETED = 45,\n};\n\nenum P4_EVENT_OPCODES {\n\tP4_EVENT_TC_DELIVER_MODE_OPCODE = 257,\n\tP4_EVENT_BPU_FETCH_REQUEST_OPCODE = 768,\n\tP4_EVENT_ITLB_REFERENCE_OPCODE = 6147,\n\tP4_EVENT_MEMORY_CANCEL_OPCODE = 517,\n\tP4_EVENT_MEMORY_COMPLETE_OPCODE = 2050,\n\tP4_EVENT_LOAD_PORT_REPLAY_OPCODE = 1026,\n\tP4_EVENT_STORE_PORT_REPLAY_OPCODE = 1282,\n\tP4_EVENT_MOB_LOAD_REPLAY_OPCODE = 770,\n\tP4_EVENT_PAGE_WALK_TYPE_OPCODE = 260,\n\tP4_EVENT_BSQ_CACHE_REFERENCE_OPCODE = 3079,\n\tP4_EVENT_IOQ_ALLOCATION_OPCODE = 774,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES_OPCODE = 6662,\n\tP4_EVENT_FSB_DATA_ACTIVITY_OPCODE = 5894,\n\tP4_EVENT_BSQ_ALLOCATION_OPCODE = 1287,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES_OPCODE = 1543,\n\tP4_EVENT_SSE_INPUT_ASSIST_OPCODE = 13313,\n\tP4_EVENT_PACKED_SP_UOP_OPCODE = 2049,\n\tP4_EVENT_PACKED_DP_UOP_OPCODE = 3073,\n\tP4_EVENT_SCALAR_SP_UOP_OPCODE = 2561,\n\tP4_EVENT_SCALAR_DP_UOP_OPCODE = 3585,\n\tP4_EVENT_64BIT_MMX_UOP_OPCODE = 513,\n\tP4_EVENT_128BIT_MMX_UOP_OPCODE = 6657,\n\tP4_EVENT_X87_FP_UOP_OPCODE = 1025,\n\tP4_EVENT_TC_MISC_OPCODE = 1537,\n\tP4_EVENT_GLOBAL_POWER_EVENTS_OPCODE = 4870,\n\tP4_EVENT_TC_MS_XFER_OPCODE = 1280,\n\tP4_EVENT_UOP_QUEUE_WRITES_OPCODE = 2304,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE_OPCODE = 1282,\n\tP4_EVENT_RETIRED_BRANCH_TYPE_OPCODE = 1026,\n\tP4_EVENT_RESOURCE_STALL_OPCODE = 257,\n\tP4_EVENT_WC_BUFFER_OPCODE = 1285,\n\tP4_EVENT_B2B_CYCLES_OPCODE = 5635,\n\tP4_EVENT_BNR_OPCODE = 2051,\n\tP4_EVENT_SNOOP_OPCODE = 1539,\n\tP4_EVENT_RESPONSE_OPCODE = 1027,\n\tP4_EVENT_FRONT_END_EVENT_OPCODE = 2053,\n\tP4_EVENT_EXECUTION_EVENT_OPCODE = 3077,\n\tP4_EVENT_REPLAY_EVENT_OPCODE = 2309,\n\tP4_EVENT_INSTR_RETIRED_OPCODE = 516,\n\tP4_EVENT_UOPS_RETIRED_OPCODE = 260,\n\tP4_EVENT_UOP_TYPE_OPCODE = 514,\n\tP4_EVENT_BRANCH_RETIRED_OPCODE = 1541,\n\tP4_EVENT_MISPRED_BRANCH_RETIRED_OPCODE = 772,\n\tP4_EVENT_X87_ASSIST_OPCODE = 773,\n\tP4_EVENT_MACHINE_CLEAR_OPCODE = 517,\n\tP4_EVENT_INSTR_COMPLETED_OPCODE = 1796,\n};\n\nenum P4_ESCR_EMASKS {\n\tP4_EVENT_TC_DELIVER_MODE__DD = 512,\n\tP4_EVENT_TC_DELIVER_MODE__DB = 1024,\n\tP4_EVENT_TC_DELIVER_MODE__DI = 2048,\n\tP4_EVENT_TC_DELIVER_MODE__BD = 4096,\n\tP4_EVENT_TC_DELIVER_MODE__BB = 8192,\n\tP4_EVENT_TC_DELIVER_MODE__BI = 16384,\n\tP4_EVENT_TC_DELIVER_MODE__ID = 32768,\n\tP4_EVENT_BPU_FETCH_REQUEST__TCMISS = 512,\n\tP4_EVENT_ITLB_REFERENCE__HIT = 512,\n\tP4_EVENT_ITLB_REFERENCE__MISS = 1024,\n\tP4_EVENT_ITLB_REFERENCE__HIT_UK = 2048,\n\tP4_EVENT_MEMORY_CANCEL__ST_RB_FULL = 2048,\n\tP4_EVENT_MEMORY_CANCEL__64K_CONF = 4096,\n\tP4_EVENT_MEMORY_COMPLETE__LSC = 512,\n\tP4_EVENT_MEMORY_COMPLETE__SSC = 1024,\n\tP4_EVENT_LOAD_PORT_REPLAY__SPLIT_LD = 1024,\n\tP4_EVENT_STORE_PORT_REPLAY__SPLIT_ST = 1024,\n\tP4_EVENT_MOB_LOAD_REPLAY__NO_STA = 1024,\n\tP4_EVENT_MOB_LOAD_REPLAY__NO_STD = 4096,\n\tP4_EVENT_MOB_LOAD_REPLAY__PARTIAL_DATA = 8192,\n\tP4_EVENT_MOB_LOAD_REPLAY__UNALGN_ADDR = 16384,\n\tP4_EVENT_PAGE_WALK_TYPE__DTMISS = 512,\n\tP4_EVENT_PAGE_WALK_TYPE__ITMISS = 1024,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_HITS = 512,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_HITE = 1024,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_HITM = 2048,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_HITS = 4096,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_HITE = 8192,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_HITM = 16384,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_2ndL_MISS = 131072,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__RD_3rdL_MISS = 262144,\n\tP4_EVENT_BSQ_CACHE_REFERENCE__WR_2ndL_MISS = 524288,\n\tP4_EVENT_IOQ_ALLOCATION__DEFAULT = 512,\n\tP4_EVENT_IOQ_ALLOCATION__ALL_READ = 16384,\n\tP4_EVENT_IOQ_ALLOCATION__ALL_WRITE = 32768,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_UC = 65536,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_WC = 131072,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_WT = 262144,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_WP = 524288,\n\tP4_EVENT_IOQ_ALLOCATION__MEM_WB = 1048576,\n\tP4_EVENT_IOQ_ALLOCATION__OWN = 4194304,\n\tP4_EVENT_IOQ_ALLOCATION__OTHER = 8388608,\n\tP4_EVENT_IOQ_ALLOCATION__PREFETCH = 16777216,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__DEFAULT = 512,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__ALL_READ = 16384,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__ALL_WRITE = 32768,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_UC = 65536,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WC = 131072,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WT = 262144,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WP = 524288,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__MEM_WB = 1048576,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__OWN = 4194304,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__OTHER = 8388608,\n\tP4_EVENT_IOQ_ACTIVE_ENTRIES__PREFETCH = 16777216,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DRDY_DRV = 512,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DRDY_OWN = 1024,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DRDY_OTHER = 2048,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DBSY_DRV = 4096,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DBSY_OWN = 8192,\n\tP4_EVENT_FSB_DATA_ACTIVITY__DBSY_OTHER = 16384,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_TYPE0 = 512,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_TYPE1 = 1024,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_LEN0 = 2048,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_LEN1 = 4096,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_IO_TYPE = 16384,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_LOCK_TYPE = 32768,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_CACHE_TYPE = 65536,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_SPLIT_TYPE = 131072,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_DEM_TYPE = 262144,\n\tP4_EVENT_BSQ_ALLOCATION__REQ_ORD_TYPE = 524288,\n\tP4_EVENT_BSQ_ALLOCATION__MEM_TYPE0 = 1048576,\n\tP4_EVENT_BSQ_ALLOCATION__MEM_TYPE1 = 2097152,\n\tP4_EVENT_BSQ_ALLOCATION__MEM_TYPE2 = 4194304,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_TYPE0 = 512,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_TYPE1 = 1024,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_LEN0 = 2048,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_LEN1 = 4096,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_IO_TYPE = 16384,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_LOCK_TYPE = 32768,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_CACHE_TYPE = 65536,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_SPLIT_TYPE = 131072,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_DEM_TYPE = 262144,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__REQ_ORD_TYPE = 524288,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__MEM_TYPE0 = 1048576,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__MEM_TYPE1 = 2097152,\n\tP4_EVENT_BSQ_ACTIVE_ENTRIES__MEM_TYPE2 = 4194304,\n\tP4_EVENT_SSE_INPUT_ASSIST__ALL = 16777216,\n\tP4_EVENT_PACKED_SP_UOP__ALL = 16777216,\n\tP4_EVENT_PACKED_DP_UOP__ALL = 16777216,\n\tP4_EVENT_SCALAR_SP_UOP__ALL = 16777216,\n\tP4_EVENT_SCALAR_DP_UOP__ALL = 16777216,\n\tP4_EVENT_64BIT_MMX_UOP__ALL = 16777216,\n\tP4_EVENT_128BIT_MMX_UOP__ALL = 16777216,\n\tP4_EVENT_X87_FP_UOP__ALL = 16777216,\n\tP4_EVENT_TC_MISC__FLUSH = 8192,\n\tP4_EVENT_GLOBAL_POWER_EVENTS__RUNNING = 512,\n\tP4_EVENT_TC_MS_XFER__CISC = 512,\n\tP4_EVENT_UOP_QUEUE_WRITES__FROM_TC_BUILD = 512,\n\tP4_EVENT_UOP_QUEUE_WRITES__FROM_TC_DELIVER = 1024,\n\tP4_EVENT_UOP_QUEUE_WRITES__FROM_ROM = 2048,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__CONDITIONAL = 1024,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__CALL = 2048,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__RETURN = 4096,\n\tP4_EVENT_RETIRED_MISPRED_BRANCH_TYPE__INDIRECT = 8192,\n\tP4_EVENT_RETIRED_BRANCH_TYPE__CONDITIONAL = 1024,\n\tP4_EVENT_RETIRED_BRANCH_TYPE__CALL = 2048,\n\tP4_EVENT_RETIRED_BRANCH_TYPE__RETURN = 4096,\n\tP4_EVENT_RETIRED_BRANCH_TYPE__INDIRECT = 8192,\n\tP4_EVENT_RESOURCE_STALL__SBFULL = 16384,\n\tP4_EVENT_WC_BUFFER__WCB_EVICTS = 512,\n\tP4_EVENT_WC_BUFFER__WCB_FULL_EVICTS = 1024,\n\tP4_EVENT_FRONT_END_EVENT__NBOGUS = 512,\n\tP4_EVENT_FRONT_END_EVENT__BOGUS = 1024,\n\tP4_EVENT_EXECUTION_EVENT__NBOGUS0 = 512,\n\tP4_EVENT_EXECUTION_EVENT__NBOGUS1 = 1024,\n\tP4_EVENT_EXECUTION_EVENT__NBOGUS2 = 2048,\n\tP4_EVENT_EXECUTION_EVENT__NBOGUS3 = 4096,\n\tP4_EVENT_EXECUTION_EVENT__BOGUS0 = 8192,\n\tP4_EVENT_EXECUTION_EVENT__BOGUS1 = 16384,\n\tP4_EVENT_EXECUTION_EVENT__BOGUS2 = 32768,\n\tP4_EVENT_EXECUTION_EVENT__BOGUS3 = 65536,\n\tP4_EVENT_REPLAY_EVENT__NBOGUS = 512,\n\tP4_EVENT_REPLAY_EVENT__BOGUS = 1024,\n\tP4_EVENT_INSTR_RETIRED__NBOGUSNTAG = 512,\n\tP4_EVENT_INSTR_RETIRED__NBOGUSTAG = 1024,\n\tP4_EVENT_INSTR_RETIRED__BOGUSNTAG = 2048,\n\tP4_EVENT_INSTR_RETIRED__BOGUSTAG = 4096,\n\tP4_EVENT_UOPS_RETIRED__NBOGUS = 512,\n\tP4_EVENT_UOPS_RETIRED__BOGUS = 1024,\n\tP4_EVENT_UOP_TYPE__TAGLOADS = 1024,\n\tP4_EVENT_UOP_TYPE__TAGSTORES = 2048,\n\tP4_EVENT_BRANCH_RETIRED__MMNP = 512,\n\tP4_EVENT_BRANCH_RETIRED__MMNM = 1024,\n\tP4_EVENT_BRANCH_RETIRED__MMTP = 2048,\n\tP4_EVENT_BRANCH_RETIRED__MMTM = 4096,\n\tP4_EVENT_MISPRED_BRANCH_RETIRED__NBOGUS = 512,\n\tP4_EVENT_X87_ASSIST__FPSU = 512,\n\tP4_EVENT_X87_ASSIST__FPSO = 1024,\n\tP4_EVENT_X87_ASSIST__POAO = 2048,\n\tP4_EVENT_X87_ASSIST__POAU = 4096,\n\tP4_EVENT_X87_ASSIST__PREA = 8192,\n\tP4_EVENT_MACHINE_CLEAR__CLEAR = 512,\n\tP4_EVENT_MACHINE_CLEAR__MOCLEAR = 1024,\n\tP4_EVENT_MACHINE_CLEAR__SMCLEAR = 2048,\n\tP4_EVENT_INSTR_COMPLETED__NBOGUS = 512,\n\tP4_EVENT_INSTR_COMPLETED__BOGUS = 1024,\n};\n\nenum P4_PEBS_METRIC {\n\tP4_PEBS_METRIC__none = 0,\n\tP4_PEBS_METRIC__1stl_cache_load_miss_retired = 1,\n\tP4_PEBS_METRIC__2ndl_cache_load_miss_retired = 2,\n\tP4_PEBS_METRIC__dtlb_load_miss_retired = 3,\n\tP4_PEBS_METRIC__dtlb_store_miss_retired = 4,\n\tP4_PEBS_METRIC__dtlb_all_miss_retired = 5,\n\tP4_PEBS_METRIC__tagged_mispred_branch = 6,\n\tP4_PEBS_METRIC__mob_load_replay_retired = 7,\n\tP4_PEBS_METRIC__split_load_retired = 8,\n\tP4_PEBS_METRIC__split_store_retired = 9,\n\tP4_PEBS_METRIC__max = 10,\n};\n\nstruct p4_event_bind {\n\tunsigned int opcode;\n\tunsigned int escr_msr[2];\n\tunsigned int escr_emask;\n\tunsigned int shared;\n\tchar cntr[6];\n};\n\nstruct p4_pebs_bind {\n\tunsigned int metric_pebs;\n\tunsigned int metric_vert;\n};\n\nstruct p4_event_alias {\n\tu64 original;\n\tu64 alternative;\n};\n\nenum cpuid_regs_idx {\n\tCPUID_EAX = 0,\n\tCPUID_EBX = 1,\n\tCPUID_ECX = 2,\n\tCPUID_EDX = 3,\n};\n\nstruct dev_ext_attribute {\n\tstruct device_attribute attr;\n\tvoid *var;\n};\n\nenum pt_capabilities {\n\tPT_CAP_max_subleaf = 0,\n\tPT_CAP_cr3_filtering = 1,\n\tPT_CAP_psb_cyc = 2,\n\tPT_CAP_ip_filtering = 3,\n\tPT_CAP_mtc = 4,\n\tPT_CAP_ptwrite = 5,\n\tPT_CAP_power_event_trace = 6,\n\tPT_CAP_topa_output = 7,\n\tPT_CAP_topa_multiple_entries = 8,\n\tPT_CAP_single_range_output = 9,\n\tPT_CAP_output_subsys = 10,\n\tPT_CAP_payloads_lip = 11,\n\tPT_CAP_num_address_ranges = 12,\n\tPT_CAP_mtc_periods = 13,\n\tPT_CAP_cycle_thresholds = 14,\n\tPT_CAP_psb_periods = 15,\n};\n\nenum perf_addr_filter_action_t {\n\tPERF_ADDR_FILTER_ACTION_STOP = 0,\n\tPERF_ADDR_FILTER_ACTION_START = 1,\n\tPERF_ADDR_FILTER_ACTION_FILTER = 2,\n};\n\nstruct perf_addr_filter {\n\tstruct list_head entry;\n\tstruct path path;\n\tlong unsigned int offset;\n\tlong unsigned int size;\n\tenum perf_addr_filter_action_t action;\n};\n\nstruct topa_entry {\n\tu64 end: 1;\n\tu64 rsvd0: 1;\n\tu64 intr: 1;\n\tu64 rsvd1: 1;\n\tu64 stop: 1;\n\tu64 rsvd2: 1;\n\tu64 size: 4;\n\tu64 rsvd3: 2;\n\tu64 base: 36;\n\tu64 rsvd4: 16;\n};\n\nstruct pt_pmu {\n\tstruct pmu pmu;\n\tu32 caps[8];\n\tbool vmx;\n\tbool branch_en_always_on;\n\tlong unsigned int max_nonturbo_ratio;\n\tunsigned int tsc_art_num;\n\tunsigned int tsc_art_den;\n};\n\nstruct topa;\n\nstruct pt_buffer {\n\tstruct list_head tables;\n\tstruct topa *first;\n\tstruct topa *last;\n\tstruct topa *cur;\n\tunsigned int cur_idx;\n\tsize_t output_off;\n\tlong unsigned int nr_pages;\n\tlocal_t data_size;\n\tlocal64_t head;\n\tbool snapshot;\n\tbool single;\n\tlong int stop_pos;\n\tlong int intr_pos;\n\tstruct topa_entry *stop_te;\n\tstruct topa_entry *intr_te;\n\tvoid **data_pages;\n};\n\nstruct topa {\n\tstruct list_head list;\n\tu64 offset;\n\tsize_t size;\n\tint last;\n\tunsigned int z_count;\n};\n\nstruct pt_filter {\n\tlong unsigned int msr_a;\n\tlong unsigned int msr_b;\n\tlong unsigned int config;\n};\n\nstruct pt_filters {\n\tstruct pt_filter filter[4];\n\tunsigned int nr_filters;\n};\n\nstruct pt {\n\tstruct perf_output_handle handle;\n\tstruct pt_filters filters;\n\tint handle_nmi;\n\tint vmx_on;\n\tu64 output_base;\n\tu64 output_mask;\n};\n\nstruct pt_cap_desc {\n\tconst char *name;\n\tu32 leaf;\n\tu8 reg;\n\tu32 mask;\n};\n\nstruct pt_address_range {\n\tlong unsigned int msr_a;\n\tlong unsigned int msr_b;\n\tunsigned int reg_off;\n};\n\nstruct topa_page {\n\tstruct topa_entry table[507];\n\tstruct topa topa;\n};\n\nstruct acpi_device;\n\nstruct pci_sysdata {\n\tint domain;\n\tint node;\n\tstruct acpi_device *companion;\n\tvoid *iommu;\n\tvoid *fwnode;\n};\n\nstruct pci_extra_dev {\n\tstruct pci_dev *dev[4];\n};\n\nstruct intel_uncore_pmu;\n\nstruct intel_uncore_ops;\n\nstruct uncore_event_desc;\n\nstruct freerunning_counters;\n\nstruct intel_uncore_type {\n\tconst char *name;\n\tint num_counters;\n\tint num_boxes;\n\tint perf_ctr_bits;\n\tint fixed_ctr_bits;\n\tint num_freerunning_types;\n\tunsigned int perf_ctr;\n\tunsigned int event_ctl;\n\tunsigned int event_mask;\n\tunsigned int event_mask_ext;\n\tunsigned int fixed_ctr;\n\tunsigned int fixed_ctl;\n\tunsigned int box_ctl;\n\tunion {\n\t\tunsigned int msr_offset;\n\t\tunsigned int mmio_offset;\n\t};\n\tunsigned int num_shared_regs: 8;\n\tunsigned int single_fixed: 1;\n\tunsigned int pair_ctr_ctl: 1;\n\tunsigned int *msr_offsets;\n\tstruct event_constraint unconstrainted;\n\tstruct event_constraint *constraints;\n\tstruct intel_uncore_pmu *pmus;\n\tstruct intel_uncore_ops *ops;\n\tstruct uncore_event_desc *event_descs;\n\tstruct freerunning_counters *freerunning;\n\tconst struct attribute_group *attr_groups[4];\n\tstruct pmu *pmu;\n};\n\nstruct intel_uncore_box;\n\nstruct intel_uncore_pmu {\n\tstruct pmu pmu;\n\tchar name[32];\n\tint pmu_idx;\n\tint func_id;\n\tbool registered;\n\tatomic_t activeboxes;\n\tstruct intel_uncore_type *type;\n\tstruct intel_uncore_box **boxes;\n};\n\nstruct intel_uncore_ops {\n\tvoid (*init_box)(struct intel_uncore_box *);\n\tvoid (*exit_box)(struct intel_uncore_box *);\n\tvoid (*disable_box)(struct intel_uncore_box *);\n\tvoid (*enable_box)(struct intel_uncore_box *);\n\tvoid (*disable_event)(struct intel_uncore_box *, struct perf_event *);\n\tvoid (*enable_event)(struct intel_uncore_box *, struct perf_event *);\n\tu64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);\n\tint (*hw_config)(struct intel_uncore_box *, struct perf_event *);\n\tstruct event_constraint * (*get_constraint)(struct intel_uncore_box *, struct perf_event *);\n\tvoid (*put_constraint)(struct intel_uncore_box *, struct perf_event *);\n};\n\nstruct uncore_event_desc {\n\tstruct kobj_attribute attr;\n\tconst char *config;\n};\n\nstruct freerunning_counters {\n\tunsigned int counter_base;\n\tunsigned int counter_offset;\n\tunsigned int box_offset;\n\tunsigned int num_counters;\n\tunsigned int bits;\n\tunsigned int *box_offsets;\n};\n\nstruct intel_uncore_extra_reg {\n\traw_spinlock_t lock;\n\tu64 config;\n\tu64 config1;\n\tu64 config2;\n\tatomic_t ref;\n};\n\nstruct intel_uncore_box {\n\tint pci_phys_id;\n\tint dieid;\n\tint n_active;\n\tint n_events;\n\tint cpu;\n\tlong unsigned int flags;\n\tatomic_t refcnt;\n\tstruct perf_event *events[10];\n\tstruct perf_event *event_list[10];\n\tstruct event_constraint *event_constraint[10];\n\tlong unsigned int active_mask[1];\n\tu64 tags[10];\n\tstruct pci_dev *pci_dev;\n\tstruct intel_uncore_pmu *pmu;\n\tu64 hrtimer_duration;\n\tstruct hrtimer hrtimer;\n\tstruct list_head list;\n\tstruct list_head active_list;\n\tvoid *io_addr;\n\tstruct intel_uncore_extra_reg shared_regs[0];\n};\n\nstruct pci2phy_map {\n\tstruct list_head list;\n\tint segment;\n\tint pbus_to_physid[256];\n};\n\nstruct intel_uncore_init_fun {\n\tvoid (*cpu_init)();\n\tint (*pci_init)();\n\tvoid (*mmio_init)();\n};\n\nenum {\n\tEXTRA_REG_NHMEX_M_FILTER = 0,\n\tEXTRA_REG_NHMEX_M_DSP = 1,\n\tEXTRA_REG_NHMEX_M_ISS = 2,\n\tEXTRA_REG_NHMEX_M_MAP = 3,\n\tEXTRA_REG_NHMEX_M_MSC_THR = 4,\n\tEXTRA_REG_NHMEX_M_PGT = 5,\n\tEXTRA_REG_NHMEX_M_PLD = 6,\n\tEXTRA_REG_NHMEX_M_ZDP_CTL_FVC = 7,\n};\n\nenum {\n\tSNB_PCI_UNCORE_IMC = 0,\n};\n\nenum perf_snb_uncore_imc_freerunning_types {\n\tSNB_PCI_UNCORE_IMC_DATA = 0,\n\tSNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX = 1,\n};\n\nstruct imc_uncore_pci_dev {\n\t__u32 pci_id;\n\tstruct pci_driver *driver;\n};\n\nenum perf_tgl_uncore_imc_freerunning_types {\n\tTGL_MMIO_UNCORE_IMC_DATA_TOTAL = 0,\n\tTGL_MMIO_UNCORE_IMC_DATA_READ = 1,\n\tTGL_MMIO_UNCORE_IMC_DATA_WRITE = 2,\n\tTGL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX = 3,\n};\n\nenum {\n\tSNBEP_PCI_QPI_PORT0_FILTER = 0,\n\tSNBEP_PCI_QPI_PORT1_FILTER = 1,\n\tBDX_PCI_QPI_PORT2_FILTER = 2,\n\tHSWEP_PCI_PCU_3 = 3,\n};\n\nenum {\n\tSNBEP_PCI_UNCORE_HA = 0,\n\tSNBEP_PCI_UNCORE_IMC = 1,\n\tSNBEP_PCI_UNCORE_QPI = 2,\n\tSNBEP_PCI_UNCORE_R2PCIE = 3,\n\tSNBEP_PCI_UNCORE_R3QPI = 4,\n};\n\nenum {\n\tIVBEP_PCI_UNCORE_HA = 0,\n\tIVBEP_PCI_UNCORE_IMC = 1,\n\tIVBEP_PCI_UNCORE_IRP = 2,\n\tIVBEP_PCI_UNCORE_QPI = 3,\n\tIVBEP_PCI_UNCORE_R2PCIE = 4,\n\tIVBEP_PCI_UNCORE_R3QPI = 5,\n};\n\nenum {\n\tKNL_PCI_UNCORE_MC_UCLK = 0,\n\tKNL_PCI_UNCORE_MC_DCLK = 1,\n\tKNL_PCI_UNCORE_EDC_UCLK = 2,\n\tKNL_PCI_UNCORE_EDC_ECLK = 3,\n\tKNL_PCI_UNCORE_M2PCIE = 4,\n\tKNL_PCI_UNCORE_IRP = 5,\n};\n\nenum {\n\tHSWEP_PCI_UNCORE_HA = 0,\n\tHSWEP_PCI_UNCORE_IMC = 1,\n\tHSWEP_PCI_UNCORE_IRP = 2,\n\tHSWEP_PCI_UNCORE_QPI = 3,\n\tHSWEP_PCI_UNCORE_R2PCIE = 4,\n\tHSWEP_PCI_UNCORE_R3QPI = 5,\n};\n\nenum {\n\tBDX_PCI_UNCORE_HA = 0,\n\tBDX_PCI_UNCORE_IMC = 1,\n\tBDX_PCI_UNCORE_IRP = 2,\n\tBDX_PCI_UNCORE_QPI = 3,\n\tBDX_PCI_UNCORE_R2PCIE = 4,\n\tBDX_PCI_UNCORE_R3QPI = 5,\n};\n\nenum perf_uncore_iio_freerunning_type_id {\n\tSKX_IIO_MSR_IOCLK = 0,\n\tSKX_IIO_MSR_BW = 1,\n\tSKX_IIO_MSR_UTIL = 2,\n\tSKX_IIO_FREERUNNING_TYPE_MAX = 3,\n};\n\nenum {\n\tSKX_PCI_UNCORE_IMC = 0,\n\tSKX_PCI_UNCORE_M2M = 1,\n\tSKX_PCI_UNCORE_UPI = 2,\n\tSKX_PCI_UNCORE_M2PCIE = 3,\n\tSKX_PCI_UNCORE_M3UPI = 4,\n};\n\nenum perf_uncore_snr_iio_freerunning_type_id {\n\tSNR_IIO_MSR_IOCLK = 0,\n\tSNR_IIO_MSR_BW_IN = 1,\n\tSNR_IIO_FREERUNNING_TYPE_MAX = 2,\n};\n\nenum {\n\tSNR_PCI_UNCORE_M2M = 0,\n};\n\nenum perf_uncore_snr_imc_freerunning_type_id {\n\tSNR_IMC_DCLK = 0,\n\tSNR_IMC_DDR = 1,\n\tSNR_IMC_FREERUNNING_TYPE_MAX = 2,\n};\n\nenum perf_uncore_icx_iio_freerunning_type_id {\n\tICX_IIO_MSR_IOCLK = 0,\n\tICX_IIO_MSR_BW_IN = 1,\n\tICX_IIO_FREERUNNING_TYPE_MAX = 2,\n};\n\nenum {\n\tICX_PCI_UNCORE_M2M = 0,\n\tICX_PCI_UNCORE_UPI = 1,\n\tICX_PCI_UNCORE_M3UPI = 2,\n};\n\nenum perf_uncore_icx_imc_freerunning_type_id {\n\tICX_IMC_DCLK = 0,\n\tICX_IMC_DDR = 1,\n\tICX_IMC_DDRT = 2,\n\tICX_IMC_FREERUNNING_TYPE_MAX = 3,\n};\n\nstruct cstate_model {\n\tlong unsigned int core_events;\n\tlong unsigned int pkg_events;\n\tlong unsigned int quirks;\n};\n\nenum perf_cstate_core_events {\n\tPERF_CSTATE_CORE_C1_RES = 0,\n\tPERF_CSTATE_CORE_C3_RES = 1,\n\tPERF_CSTATE_CORE_C6_RES = 2,\n\tPERF_CSTATE_CORE_C7_RES = 3,\n\tPERF_CSTATE_CORE_EVENT_MAX = 4,\n};\n\nenum perf_cstate_pkg_events {\n\tPERF_CSTATE_PKG_C2_RES = 0,\n\tPERF_CSTATE_PKG_C3_RES = 1,\n\tPERF_CSTATE_PKG_C6_RES = 2,\n\tPERF_CSTATE_PKG_C7_RES = 3,\n\tPERF_CSTATE_PKG_C8_RES = 4,\n\tPERF_CSTATE_PKG_C9_RES = 5,\n\tPERF_CSTATE_PKG_C10_RES = 6,\n\tPERF_CSTATE_PKG_EVENT_MAX = 7,\n};\n\nstruct real_mode_header {\n\tu32 text_start;\n\tu32 ro_end;\n\tu32 trampoline_start;\n\tu32 trampoline_header;\n\tu32 trampoline_pgd;\n\tu32 wakeup_start;\n\tu32 wakeup_header;\n\tu32 machine_real_restart_asm;\n\tu32 machine_real_restart_seg;\n};\n\nstruct trampoline_header {\n\tu64 start;\n\tu64 efer;\n\tu32 cr4;\n\tu32 flags;\n};\n\nenum xfeature {\n\tXFEATURE_FP = 0,\n\tXFEATURE_SSE = 1,\n\tXFEATURE_YMM = 2,\n\tXFEATURE_BNDREGS = 3,\n\tXFEATURE_BNDCSR = 4,\n\tXFEATURE_OPMASK = 5,\n\tXFEATURE_ZMM_Hi256 = 6,\n\tXFEATURE_Hi16_ZMM = 7,\n\tXFEATURE_PT_UNIMPLEMENTED_SO_FAR = 8,\n\tXFEATURE_PKRU = 9,\n\tXFEATURE_MAX = 10,\n};\n\nstruct pkru_state {\n\tu32 pkru;\n\tu32 pad;\n};\n\nenum show_regs_mode {\n\tSHOW_REGS_SHORT = 0,\n\tSHOW_REGS_USER = 1,\n\tSHOW_REGS_ALL = 2,\n};\n\nstruct shared_info;\n\nstruct start_info;\n\nenum which_selector {\n\tFS = 0,\n\tGS = 1,\n};\n\ntypedef struct task_struct *pto_T_____3;\n\ntypedef u64 pto_T_____4;\n\nstruct sigcontext_64 {\n\t__u64 r8;\n\t__u64 r9;\n\t__u64 r10;\n\t__u64 r11;\n\t__u64 r12;\n\t__u64 r13;\n\t__u64 r14;\n\t__u64 r15;\n\t__u64 di;\n\t__u64 si;\n\t__u64 bp;\n\t__u64 bx;\n\t__u64 dx;\n\t__u64 ax;\n\t__u64 cx;\n\t__u64 sp;\n\t__u64 ip;\n\t__u64 flags;\n\t__u16 cs;\n\t__u16 gs;\n\t__u16 fs;\n\t__u16 ss;\n\t__u64 err;\n\t__u64 trapno;\n\t__u64 oldmask;\n\t__u64 cr2;\n\t__u64 fpstate;\n\t__u64 reserved1[8];\n};\n\nstruct sigaltstack {\n\tvoid *ss_sp;\n\tint ss_flags;\n\tsize_t ss_size;\n};\n\ntypedef struct sigaltstack stack_t;\n\nstruct siginfo {\n\tunion {\n\t\tstruct {\n\t\t\tint si_signo;\n\t\t\tint si_errno;\n\t\t\tint si_code;\n\t\t\tunion __sifields _sifields;\n\t\t};\n\t\tint _si_pad[32];\n\t};\n};\n\nstruct ucontext {\n\tlong unsigned int uc_flags;\n\tstruct ucontext *uc_link;\n\tstack_t uc_stack;\n\tstruct sigcontext_64 uc_mcontext;\n\tsigset_t uc_sigmask;\n};\n\ntypedef u32 compat_sigset_word;\n\ntypedef struct {\n\tcompat_sigset_word sig[2];\n} compat_sigset_t;\n\nstruct mce {\n\t__u64 status;\n\t__u64 misc;\n\t__u64 addr;\n\t__u64 mcgstatus;\n\t__u64 ip;\n\t__u64 tsc;\n\t__u64 time;\n\t__u8 cpuvendor;\n\t__u8 inject_flags;\n\t__u8 severity;\n\t__u8 pad;\n\t__u32 cpuid;\n\t__u8 cs;\n\t__u8 bank;\n\t__u8 cpu;\n\t__u8 finished;\n\t__u32 extcpu;\n\t__u32 socketid;\n\t__u32 apicid;\n\t__u64 mcgcap;\n\t__u64 synd;\n\t__u64 ipid;\n\t__u64 ppin;\n\t__u32 microcode;\n\t__u64 kflags;\n};\n\ntypedef long unsigned int mce_banks_t[1];\n\nstruct smca_hwid {\n\tunsigned int bank_type;\n\tu32 hwid_mcatype;\n\tu32 xec_bitmap;\n\tu8 count;\n};\n\nstruct smca_bank {\n\tstruct smca_hwid *hwid;\n\tu32 id;\n\tu8 sysfs_id;\n};\n\nstruct kernel_vm86_regs {\n\tstruct pt_regs pt;\n\tshort unsigned int es;\n\tshort unsigned int __esh;\n\tshort unsigned int ds;\n\tshort unsigned int __dsh;\n\tshort unsigned int fs;\n\tshort unsigned int __fsh;\n\tshort unsigned int gs;\n\tshort unsigned int __gsh;\n};\n\nstruct rt_sigframe {\n\tchar *pretcode;\n\tstruct ucontext uc;\n\tstruct siginfo info;\n};\n\ntypedef struct siginfo siginfo_t;\n\ntypedef s32 compat_clock_t;\n\ntypedef s32 compat_pid_t;\n\ntypedef s32 compat_timer_t;\n\ntypedef s32 compat_int_t;\n\ntypedef u32 __compat_uid32_t;\n\nunion compat_sigval {\n\tcompat_int_t sival_int;\n\tcompat_uptr_t sival_ptr;\n};\n\ntypedef union compat_sigval compat_sigval_t;\n\nstruct compat_siginfo {\n\tint si_signo;\n\tint si_errno;\n\tint si_code;\n\tunion {\n\t\tint _pad[29];\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t} _kill;\n\t\tstruct {\n\t\t\tcompat_timer_t _tid;\n\t\t\tint _overrun;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _timer;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tcompat_sigval_t _sigval;\n\t\t} _rt;\n\t\tstruct {\n\t\t\tcompat_pid_t _pid;\n\t\t\t__compat_uid32_t _uid;\n\t\t\tint _status;\n\t\t\tcompat_clock_t _utime;\n\t\t\tcompat_clock_t _stime;\n\t\t} _sigchld;\n\t\tstruct {\n\t\t\tcompat_uptr_t _addr;\n\t\t\tunion {\n\t\t\t\tshort int _addr_lsb;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_bnd[4];\n\t\t\t\t\tcompat_uptr_t _lower;\n\t\t\t\t\tcompat_uptr_t _upper;\n\t\t\t\t} _addr_bnd;\n\t\t\t\tstruct {\n\t\t\t\t\tchar _dummy_pkey[4];\n\t\t\t\t\tu32 _pkey;\n\t\t\t\t} _addr_pkey;\n\t\t\t};\n\t\t} _sigfault;\n\t\tstruct {\n\t\t\tcompat_long_t _band;\n\t\t\tint _fd;\n\t\t} _sigpoll;\n\t\tstruct {\n\t\t\tcompat_uptr_t _call_addr;\n\t\t\tint _syscall;\n\t\t\tunsigned int _arch;\n\t\t} _sigsys;\n\t} _sifields;\n};\n\ntypedef struct compat_siginfo compat_siginfo_t;\n\nenum bug_trap_type {\n\tBUG_TRAP_TYPE_NONE = 0,\n\tBUG_TRAP_TYPE_WARN = 1,\n\tBUG_TRAP_TYPE_BUG = 2,\n};\n\nenum die_val {\n\tDIE_OOPS = 1,\n\tDIE_INT3 = 2,\n\tDIE_DEBUG = 3,\n\tDIE_PANIC = 4,\n\tDIE_NMI = 5,\n\tDIE_DIE = 6,\n\tDIE_KERNELDEBUG = 7,\n\tDIE_TRAP = 8,\n\tDIE_GPF = 9,\n\tDIE_CALL = 10,\n\tDIE_PAGE_FAULT = 11,\n\tDIE_NMIUNKNOWN = 12,\n};\n\nenum kernel_gp_hint {\n\tGP_NO_HINT = 0,\n\tGP_NON_CANONICAL = 1,\n\tGP_CANONICAL = 2,\n};\n\nstruct bad_iret_stack {\n\tvoid *error_entry_ret;\n\tstruct pt_regs regs;\n};\n\nenum {\n\tGATE_INTERRUPT = 14,\n\tGATE_TRAP = 15,\n\tGATE_CALL = 12,\n\tGATE_TASK = 5,\n};\n\nstruct idt_bits {\n\tu16 ist: 3;\n\tu16 zero: 5;\n\tu16 type: 5;\n\tu16 dpl: 2;\n\tu16 p: 1;\n};\n\nstruct gate_struct {\n\tu16 offset_low;\n\tu16 segment;\n\tstruct idt_bits bits;\n\tu16 offset_middle;\n\tu32 offset_high;\n\tu32 reserved;\n};\n\ntypedef struct gate_struct gate_desc;\n\nstruct idt_data {\n\tunsigned int vector;\n\tunsigned int segment;\n\tstruct idt_bits bits;\n\tconst void *addr;\n};\n\nenum irqreturn {\n\tIRQ_NONE = 0,\n\tIRQ_HANDLED = 1,\n\tIRQ_WAKE_THREAD = 2,\n};\n\ntypedef enum irqreturn irqreturn_t;\n\ntypedef irqreturn_t (*irq_handler_t)(int, void *);\n\nstruct irqaction {\n\tirq_handler_t handler;\n\tvoid *dev_id;\n\tvoid *percpu_dev_id;\n\tstruct irqaction *next;\n\tirq_handler_t thread_fn;\n\tstruct task_struct *thread;\n\tstruct irqaction *secondary;\n\tunsigned int irq;\n\tunsigned int flags;\n\tlong unsigned int thread_flags;\n\tlong unsigned int thread_mask;\n\tconst char *name;\n\tstruct proc_dir_entry *dir;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct irq_affinity_notify {\n\tunsigned int irq;\n\tstruct kref kref;\n\tstruct work_struct work;\n\tvoid (*notify)(struct irq_affinity_notify *, const cpumask_t *);\n\tvoid (*release)(struct kref *);\n};\n\nenum irqchip_irq_state {\n\tIRQCHIP_STATE_PENDING = 0,\n\tIRQCHIP_STATE_ACTIVE = 1,\n\tIRQCHIP_STATE_MASKED = 2,\n\tIRQCHIP_STATE_LINE_LEVEL = 3,\n};\n\nstruct irq_desc___2;\n\ntypedef void (*irq_flow_handler_t)(struct irq_desc___2 *);\n\nstruct msi_desc;\n\nstruct irq_common_data {\n\tunsigned int state_use_accessors;\n\tunsigned int node;\n\tvoid *handler_data;\n\tstruct msi_desc *msi_desc;\n\tcpumask_var_t affinity;\n\tcpumask_var_t effective_affinity;\n};\n\nstruct irq_chip;\n\nstruct irq_data {\n\tu32 mask;\n\tunsigned int irq;\n\tlong unsigned int hwirq;\n\tstruct irq_common_data *common;\n\tstruct irq_chip *chip;\n\tstruct irq_domain *domain;\n\tstruct irq_data *parent_data;\n\tvoid *chip_data;\n};\n\nstruct irq_desc___2 {\n\tstruct irq_common_data irq_common_data;\n\tstruct irq_data irq_data;\n\tunsigned int *kstat_irqs;\n\tirq_flow_handler_t handle_irq;\n\tstruct irqaction *action;\n\tunsigned int status_use_accessors;\n\tunsigned int core_internal_state__do_not_mess_with_it;\n\tunsigned int depth;\n\tunsigned int wake_depth;\n\tunsigned int tot_count;\n\tunsigned int irq_count;\n\tlong unsigned int last_unhandled;\n\tunsigned int irqs_unhandled;\n\tatomic_t threads_handled;\n\tint threads_handled_last;\n\traw_spinlock_t lock;\n\tstruct cpumask *percpu_enabled;\n\tconst struct cpumask *percpu_affinity;\n\tconst struct cpumask *affinity_hint;\n\tstruct irq_affinity_notify *affinity_notify;\n\tcpumask_var_t pending_mask;\n\tlong unsigned int threads_oneshot;\n\tatomic_t threads_active;\n\twait_queue_head_t wait_for_threads;\n\tunsigned int nr_actions;\n\tunsigned int no_suspend_depth;\n\tunsigned int cond_suspend_depth;\n\tunsigned int force_resume_depth;\n\tstruct proc_dir_entry *dir;\n\tstruct callback_head rcu;\n\tstruct kobject kobj;\n\tstruct mutex request_mutex;\n\tint parent_irq;\n\tstruct module *owner;\n\tconst char *name;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct msi_msg;\n\nstruct irq_chip {\n\tstruct device *parent_device;\n\tconst char *name;\n\tunsigned int (*irq_startup)(struct irq_data *);\n\tvoid (*irq_shutdown)(struct irq_data *);\n\tvoid (*irq_enable)(struct irq_data *);\n\tvoid (*irq_disable)(struct irq_data *);\n\tvoid (*irq_ack)(struct irq_data *);\n\tvoid (*irq_mask)(struct irq_data *);\n\tvoid (*irq_mask_ack)(struct irq_data *);\n\tvoid (*irq_unmask)(struct irq_data *);\n\tvoid (*irq_eoi)(struct irq_data *);\n\tint (*irq_set_affinity)(struct irq_data *, const struct cpumask *, bool);\n\tint (*irq_retrigger)(struct irq_data *);\n\tint (*irq_set_type)(struct irq_data *, unsigned int);\n\tint (*irq_set_wake)(struct irq_data *, unsigned int);\n\tvoid (*irq_bus_lock)(struct irq_data *);\n\tvoid (*irq_bus_sync_unlock)(struct irq_data *);\n\tvoid (*irq_cpu_online)(struct irq_data *);\n\tvoid (*irq_cpu_offline)(struct irq_data *);\n\tvoid (*irq_suspend)(struct irq_data *);\n\tvoid (*irq_resume)(struct irq_data *);\n\tvoid (*irq_pm_shutdown)(struct irq_data *);\n\tvoid (*irq_calc_mask)(struct irq_data *);\n\tvoid (*irq_print_chip)(struct irq_data *, struct seq_file *);\n\tint (*irq_request_resources)(struct irq_data *);\n\tvoid (*irq_release_resources)(struct irq_data *);\n\tvoid (*irq_compose_msi_msg)(struct irq_data *, struct msi_msg *);\n\tvoid (*irq_write_msi_msg)(struct irq_data *, struct msi_msg *);\n\tint (*irq_get_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool *);\n\tint (*irq_set_irqchip_state)(struct irq_data *, enum irqchip_irq_state, bool);\n\tint (*irq_set_vcpu_affinity)(struct irq_data *, void *);\n\tvoid (*ipi_send_single)(struct irq_data *, unsigned int);\n\tvoid (*ipi_send_mask)(struct irq_data *, const struct cpumask *);\n\tint (*irq_nmi_setup)(struct irq_data *);\n\tvoid (*irq_nmi_teardown)(struct irq_data *);\n\tlong unsigned int flags;\n};\n\ntypedef struct irq_desc___2 *vector_irq_t___2[256];\n\nstruct trace_event_raw_x86_irq_vector {\n\tstruct trace_entry ent;\n\tint vector;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_config {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int vector;\n\tunsigned int cpu;\n\tunsigned int apicdest;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_mod {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int vector;\n\tunsigned int cpu;\n\tunsigned int prev_vector;\n\tunsigned int prev_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_reserve {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_alloc {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int vector;\n\tbool reserved;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_alloc_managed {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int vector;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_activate {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tbool is_managed;\n\tbool can_reserve;\n\tbool reserve;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_teardown {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tbool is_managed;\n\tbool has_reserved;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_setup {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tbool is_legacy;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vector_free_moved {\n\tstruct trace_entry ent;\n\tunsigned int irq;\n\tunsigned int cpu;\n\tunsigned int vector;\n\tbool is_managed;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_x86_irq_vector {};\n\nstruct trace_event_data_offsets_vector_config {};\n\nstruct trace_event_data_offsets_vector_mod {};\n\nstruct trace_event_data_offsets_vector_reserve {};\n\nstruct trace_event_data_offsets_vector_alloc {};\n\nstruct trace_event_data_offsets_vector_alloc_managed {};\n\nstruct trace_event_data_offsets_vector_activate {};\n\nstruct trace_event_data_offsets_vector_teardown {};\n\nstruct trace_event_data_offsets_vector_setup {};\n\nstruct trace_event_data_offsets_vector_free_moved {};\n\ntypedef void (*btf_trace_local_timer_entry)(void *, int);\n\ntypedef void (*btf_trace_local_timer_exit)(void *, int);\n\ntypedef void (*btf_trace_spurious_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_spurious_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_error_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_error_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_x86_platform_ipi_entry)(void *, int);\n\ntypedef void (*btf_trace_x86_platform_ipi_exit)(void *, int);\n\ntypedef void (*btf_trace_irq_work_entry)(void *, int);\n\ntypedef void (*btf_trace_irq_work_exit)(void *, int);\n\ntypedef void (*btf_trace_reschedule_entry)(void *, int);\n\ntypedef void (*btf_trace_reschedule_exit)(void *, int);\n\ntypedef void (*btf_trace_call_function_entry)(void *, int);\n\ntypedef void (*btf_trace_call_function_exit)(void *, int);\n\ntypedef void (*btf_trace_call_function_single_entry)(void *, int);\n\ntypedef void (*btf_trace_call_function_single_exit)(void *, int);\n\ntypedef void (*btf_trace_threshold_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_threshold_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_deferred_error_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_deferred_error_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_thermal_apic_entry)(void *, int);\n\ntypedef void (*btf_trace_thermal_apic_exit)(void *, int);\n\ntypedef void (*btf_trace_vector_config)(void *, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_vector_update)(void *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_vector_clear)(void *, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_vector_reserve_managed)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_vector_reserve)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_vector_alloc)(void *, unsigned int, unsigned int, bool, int);\n\ntypedef void (*btf_trace_vector_alloc_managed)(void *, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_vector_activate)(void *, unsigned int, bool, bool, bool);\n\ntypedef void (*btf_trace_vector_deactivate)(void *, unsigned int, bool, bool, bool);\n\ntypedef void (*btf_trace_vector_teardown)(void *, unsigned int, bool, bool);\n\ntypedef void (*btf_trace_vector_setup)(void *, unsigned int, bool, int);\n\ntypedef void (*btf_trace_vector_free_moved)(void *, unsigned int, unsigned int, unsigned int, bool);\n\ntypedef struct irq_desc___2 *pto_T_____5;\n\ntypedef struct pt_regs *pto_T_____6;\n\nstruct estack_pages {\n\tu32 offs;\n\tu16 size;\n\tu16 type;\n};\n\nstruct clocksource {\n\tu64 (*read)(struct clocksource *);\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n\tu64 max_idle_ns;\n\tu32 maxadj;\n\tu64 max_cycles;\n\tconst char *name;\n\tstruct list_head list;\n\tint rating;\n\tenum vdso_clock_mode vdso_clock_mode;\n\tlong unsigned int flags;\n\tint (*enable)(struct clocksource *);\n\tvoid (*disable)(struct clocksource *);\n\tvoid (*suspend)(struct clocksource *);\n\tvoid (*resume)(struct clocksource *);\n\tvoid (*mark_unstable)(struct clocksource *);\n\tvoid (*tick_stable)(struct clocksource *);\n\tstruct list_head wd_list;\n\tu64 cs_last;\n\tu64 wd_last;\n\tstruct module *owner;\n};\n\nenum clock_event_state {\n\tCLOCK_EVT_STATE_DETACHED = 0,\n\tCLOCK_EVT_STATE_SHUTDOWN = 1,\n\tCLOCK_EVT_STATE_PERIODIC = 2,\n\tCLOCK_EVT_STATE_ONESHOT = 3,\n\tCLOCK_EVT_STATE_ONESHOT_STOPPED = 4,\n};\n\nstruct clock_event_device {\n\tvoid (*event_handler)(struct clock_event_device *);\n\tint (*set_next_event)(long unsigned int, struct clock_event_device *);\n\tint (*set_next_ktime)(ktime_t, struct clock_event_device *);\n\tktime_t next_event;\n\tu64 max_delta_ns;\n\tu64 min_delta_ns;\n\tu32 mult;\n\tu32 shift;\n\tenum clock_event_state state_use_accessors;\n\tunsigned int features;\n\tlong unsigned int retries;\n\tint (*set_state_periodic)(struct clock_event_device *);\n\tint (*set_state_oneshot)(struct clock_event_device *);\n\tint (*set_state_oneshot_stopped)(struct clock_event_device *);\n\tint (*set_state_shutdown)(struct clock_event_device *);\n\tint (*tick_resume)(struct clock_event_device *);\n\tvoid (*broadcast)(const struct cpumask *);\n\tvoid (*suspend)(struct clock_event_device *);\n\tvoid (*resume)(struct clock_event_device *);\n\tlong unsigned int min_delta_ticks;\n\tlong unsigned int max_delta_ticks;\n\tconst char *name;\n\tint rating;\n\tint irq;\n\tint bound_on;\n\tconst struct cpumask *cpumask;\n\tstruct list_head list;\n\tstruct module *owner;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct irq_affinity_desc {\n\tstruct cpumask mask;\n\tunsigned int is_managed: 1;\n};\n\nstruct msi_msg {\n\tu32 address_lo;\n\tu32 address_hi;\n\tu32 data;\n};\n\nstruct platform_msi_priv_data;\n\nstruct platform_msi_desc {\n\tstruct platform_msi_priv_data *msi_priv_data;\n\tu16 msi_index;\n};\n\nstruct fsl_mc_msi_desc {\n\tu16 msi_index;\n};\n\nstruct ti_sci_inta_msi_desc {\n\tu16 dev_index;\n};\n\nstruct msi_desc {\n\tstruct list_head list;\n\tunsigned int irq;\n\tunsigned int nvec_used;\n\tstruct device *dev;\n\tstruct msi_msg msg;\n\tstruct irq_affinity_desc *affinity;\n\tconst void *iommu_cookie;\n\tvoid (*write_msi_msg)(struct msi_desc *, void *);\n\tvoid *write_msi_msg_data;\n\tunion {\n\t\tstruct {\n\t\t\tu32 masked;\n\t\t\tstruct {\n\t\t\t\tu8 is_msix: 1;\n\t\t\t\tu8 multiple: 3;\n\t\t\t\tu8 multi_cap: 3;\n\t\t\t\tu8 maskbit: 1;\n\t\t\t\tu8 is_64: 1;\n\t\t\t\tu8 is_virtual: 1;\n\t\t\t\tu16 entry_nr;\n\t\t\t\tunsigned int default_irq;\n\t\t\t} msi_attrib;\n\t\t\tunion {\n\t\t\t\tu8 mask_pos;\n\t\t\t\tvoid *mask_base;\n\t\t\t};\n\t\t};\n\t\tstruct platform_msi_desc platform;\n\t\tstruct fsl_mc_msi_desc fsl_mc;\n\t\tstruct ti_sci_inta_msi_desc inta;\n\t};\n};\n\nstruct irq_chip_regs {\n\tlong unsigned int enable;\n\tlong unsigned int disable;\n\tlong unsigned int mask;\n\tlong unsigned int ack;\n\tlong unsigned int eoi;\n\tlong unsigned int type;\n\tlong unsigned int polarity;\n};\n\nstruct irq_chip_type {\n\tstruct irq_chip chip;\n\tstruct irq_chip_regs regs;\n\tirq_flow_handler_t handler;\n\tu32 type;\n\tu32 mask_cache_priv;\n\tu32 *mask_cache;\n};\n\nstruct irq_chip_generic {\n\traw_spinlock_t lock;\n\tvoid *reg_base;\n\tu32 (*reg_readl)(void *);\n\tvoid (*reg_writel)(u32, void *);\n\tvoid (*suspend)(struct irq_chip_generic *);\n\tvoid (*resume)(struct irq_chip_generic *);\n\tunsigned int irq_base;\n\tunsigned int irq_cnt;\n\tu32 mask_cache;\n\tu32 type_cache;\n\tu32 polarity_cache;\n\tu32 wake_enabled;\n\tu32 wake_active;\n\tunsigned int num_ct;\n\tvoid *private;\n\tlong unsigned int installed;\n\tlong unsigned int unused;\n\tstruct irq_domain *domain;\n\tstruct list_head list;\n\tstruct irq_chip_type chip_types[0];\n};\n\nenum irq_gc_flags {\n\tIRQ_GC_INIT_MASK_CACHE = 1,\n\tIRQ_GC_INIT_NESTED_LOCK = 2,\n\tIRQ_GC_MASK_CACHE_PER_TYPE = 4,\n\tIRQ_GC_NO_MASK = 8,\n\tIRQ_GC_BE_IO = 16,\n};\n\nstruct irq_domain_chip_generic {\n\tunsigned int irqs_per_chip;\n\tunsigned int num_chips;\n\tunsigned int irq_flags_to_clear;\n\tunsigned int irq_flags_to_set;\n\tenum irq_gc_flags gc_flags;\n\tstruct irq_chip_generic *gc[0];\n};\n\nstruct legacy_pic {\n\tint nr_legacy_irqs;\n\tstruct irq_chip *chip;\n\tvoid (*mask)(unsigned int);\n\tvoid (*unmask)(unsigned int);\n\tvoid (*mask_all)();\n\tvoid (*restore_mask)();\n\tvoid (*init)(int);\n\tint (*probe)();\n\tint (*irq_pending)(unsigned int);\n\tvoid (*make_irq)(unsigned int);\n};\n\nenum refcount_saturation_type {\n\tREFCOUNT_ADD_NOT_ZERO_OVF = 0,\n\tREFCOUNT_ADD_OVF = 1,\n\tREFCOUNT_ADD_UAF = 2,\n\tREFCOUNT_SUB_UAF = 3,\n\tREFCOUNT_DEC_LEAK = 4,\n};\n\nenum lockdown_reason {\n\tLOCKDOWN_NONE = 0,\n\tLOCKDOWN_MODULE_SIGNATURE = 1,\n\tLOCKDOWN_DEV_MEM = 2,\n\tLOCKDOWN_EFI_TEST = 3,\n\tLOCKDOWN_KEXEC = 4,\n\tLOCKDOWN_HIBERNATION = 5,\n\tLOCKDOWN_PCI_ACCESS = 6,\n\tLOCKDOWN_IOPORT = 7,\n\tLOCKDOWN_MSR = 8,\n\tLOCKDOWN_ACPI_TABLES = 9,\n\tLOCKDOWN_PCMCIA_CIS = 10,\n\tLOCKDOWN_TIOCSSERIAL = 11,\n\tLOCKDOWN_MODULE_PARAMETERS = 12,\n\tLOCKDOWN_MMIOTRACE = 13,\n\tLOCKDOWN_DEBUGFS = 14,\n\tLOCKDOWN_XMON_WR = 15,\n\tLOCKDOWN_INTEGRITY_MAX = 16,\n\tLOCKDOWN_KCORE = 17,\n\tLOCKDOWN_KPROBES = 18,\n\tLOCKDOWN_BPF_READ = 19,\n\tLOCKDOWN_PERF = 20,\n\tLOCKDOWN_TRACEFS = 21,\n\tLOCKDOWN_XMON_RW = 22,\n\tLOCKDOWN_CONFIDENTIALITY_MAX = 23,\n};\n\nenum lockdep_ok {\n\tLOCKDEP_STILL_OK = 0,\n\tLOCKDEP_NOW_UNRELIABLE = 1,\n};\n\ntypedef unsigned int uintptr_t;\n\nstruct machine_ops {\n\tvoid (*restart)(char *);\n\tvoid (*halt)();\n\tvoid (*power_off)();\n\tvoid (*shutdown)();\n\tvoid (*crash_shutdown)(struct pt_regs *);\n\tvoid (*emergency_restart)();\n};\n\nstruct trace_event_raw_nmi_handler {\n\tstruct trace_entry ent;\n\tvoid *handler;\n\ts64 delta_ns;\n\tint handled;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_nmi_handler {};\n\ntypedef void (*btf_trace_nmi_handler)(void *, void *, s64, int);\n\nstruct nmi_desc {\n\traw_spinlock_t lock;\n\tstruct list_head head;\n};\n\nstruct nmi_stats {\n\tunsigned int normal;\n\tunsigned int unknown;\n\tunsigned int external;\n\tunsigned int swallow;\n};\n\nenum nmi_states {\n\tNMI_NOT_RUNNING = 0,\n\tNMI_EXECUTING = 1,\n\tNMI_LATCHED = 2,\n};\n\ntypedef enum nmi_states pto_T_____7;\n\ntypedef bool pto_T_____8;\n\nenum {\n\tDESC_TSS = 9,\n\tDESC_LDT = 2,\n\tDESCTYPE_S = 16,\n};\n\nstruct ldttss_desc {\n\tu16 limit0;\n\tu16 base0;\n\tu16 base1: 8;\n\tu16 type: 5;\n\tu16 dpl: 2;\n\tu16 p: 1;\n\tu16 limit1: 4;\n\tu16 zero0: 3;\n\tu16 g: 1;\n\tu16 base2: 8;\n\tu32 base3;\n\tu32 zero1;\n};\n\ntypedef struct ldttss_desc ldt_desc;\n\nstruct user_desc {\n\tunsigned int entry_number;\n\tunsigned int base_addr;\n\tunsigned int limit;\n\tunsigned int seg_32bit: 1;\n\tunsigned int contents: 2;\n\tunsigned int read_exec_only: 1;\n\tunsigned int limit_in_pages: 1;\n\tunsigned int seg_not_present: 1;\n\tunsigned int useable: 1;\n\tunsigned int lm: 1;\n};\n\nstruct mmu_gather_batch {\n\tstruct mmu_gather_batch *next;\n\tunsigned int nr;\n\tunsigned int max;\n\tstruct page *pages[0];\n};\n\nstruct mmu_gather {\n\tstruct mm_struct *mm;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int fullmm: 1;\n\tunsigned int need_flush_all: 1;\n\tunsigned int freed_tables: 1;\n\tunsigned int cleared_ptes: 1;\n\tunsigned int cleared_pmds: 1;\n\tunsigned int cleared_puds: 1;\n\tunsigned int cleared_p4ds: 1;\n\tunsigned int vma_exec: 1;\n\tunsigned int vma_huge: 1;\n\tunsigned int batch_count;\n\tstruct mmu_gather_batch *active;\n\tstruct mmu_gather_batch local;\n\tstruct page *__pages[8];\n};\n\nstruct hvm_start_info {\n\tuint32_t magic;\n\tuint32_t version;\n\tuint32_t flags;\n\tuint32_t nr_modules;\n\tuint64_t modlist_paddr;\n\tuint64_t cmdline_paddr;\n\tuint64_t rsdp_paddr;\n\tuint64_t memmap_paddr;\n\tuint32_t memmap_entries;\n\tuint32_t reserved;\n};\n\nstruct setup_data {\n\t__u64 next;\n\t__u32 type;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct setup_indirect {\n\t__u32 type;\n\t__u32 reserved;\n\t__u64 len;\n\t__u64 addr;\n};\n\nenum efi_secureboot_mode {\n\tefi_secureboot_mode_unset = 0,\n\tefi_secureboot_mode_unknown = 1,\n\tefi_secureboot_mode_disabled = 2,\n\tefi_secureboot_mode_enabled = 3,\n};\n\nstruct acpi_table_ibft {\n\tstruct acpi_table_header header;\n\tu8 reserved[12];\n};\n\nstruct hstate {\n\tint next_nid_to_alloc;\n\tint next_nid_to_free;\n\tunsigned int order;\n\tlong unsigned int mask;\n\tlong unsigned int max_huge_pages;\n\tlong unsigned int nr_huge_pages;\n\tlong unsigned int free_huge_pages;\n\tlong unsigned int resv_huge_pages;\n\tlong unsigned int surplus_huge_pages;\n\tlong unsigned int nr_overcommit_huge_pages;\n\tstruct list_head hugepage_activelist;\n\tstruct list_head hugepage_freelists[64];\n\tunsigned int nr_huge_pages_node[64];\n\tunsigned int free_huge_pages_node[64];\n\tunsigned int surplus_huge_pages_node[64];\n\tchar name[32];\n};\n\nenum xen_domain_type {\n\tXEN_NATIVE = 0,\n\tXEN_PV_DOMAIN = 1,\n\tXEN_HVM_DOMAIN = 2,\n};\n\nstruct efi_scratch {\n\tu64 phys_stack;\n\tstruct mm_struct *prev_mm;\n};\n\nstruct msi_controller {\n\tstruct module *owner;\n\tstruct device *dev;\n\tstruct device_node *of_node;\n\tstruct list_head list;\n\tint (*setup_irq)(struct msi_controller *, struct pci_dev *, struct msi_desc *);\n\tint (*setup_irqs)(struct msi_controller *, struct pci_dev *, int, int);\n\tvoid (*teardown_irq)(struct msi_controller *, unsigned int);\n};\n\nstruct pci_raw_ops {\n\tint (*read)(unsigned int, unsigned int, unsigned int, int, int, u32 *);\n\tint (*write)(unsigned int, unsigned int, unsigned int, int, int, u32);\n};\n\nstruct clock_event_device___2;\n\nenum jump_label_type {\n\tJUMP_LABEL_NOP = 0,\n\tJUMP_LABEL_JMP = 1,\n};\n\nunion text_poke_insn {\n\tu8 text[5];\n\tstruct {\n\t\tu8 opcode;\n\t\ts32 disp;\n\t} __attribute__((packed));\n};\n\nenum {\n\tJL_STATE_START = 0,\n\tJL_STATE_NO_UPDATE = 1,\n\tJL_STATE_UPDATE = 2,\n};\n\ntypedef short unsigned int __kernel_old_uid_t;\n\ntypedef short unsigned int __kernel_old_gid_t;\n\ntypedef struct {\n\tint val[2];\n} __kernel_fsid_t;\n\ntypedef __kernel_old_uid_t old_uid_t;\n\ntypedef __kernel_old_gid_t old_gid_t;\n\nstruct kernel_clone_args {\n\tu64 flags;\n\tint *pidfd;\n\tint *child_tid;\n\tint *parent_tid;\n\tint exit_signal;\n\tlong unsigned int stack;\n\tlong unsigned int stack_size;\n\tlong unsigned int tls;\n\tpid_t *set_tid;\n\tsize_t set_tid_size;\n\tint cgroup;\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n};\n\nstruct kstatfs {\n\tlong int f_type;\n\tlong int f_bsize;\n\tu64 f_blocks;\n\tu64 f_bfree;\n\tu64 f_bavail;\n\tu64 f_files;\n\tu64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\tlong int f_namelen;\n\tlong int f_frsize;\n\tlong int f_flags;\n\tlong int f_spare[4];\n};\n\nstruct stat64 {\n\tlong long unsigned int st_dev;\n\tunsigned char __pad0[4];\n\tunsigned int __st_ino;\n\tunsigned int st_mode;\n\tunsigned int st_nlink;\n\tunsigned int st_uid;\n\tunsigned int st_gid;\n\tlong long unsigned int st_rdev;\n\tunsigned char __pad3[4];\n\tlong long int st_size;\n\tunsigned int st_blksize;\n\tlong long int st_blocks;\n\tunsigned int st_atime;\n\tunsigned int st_atime_nsec;\n\tunsigned int st_mtime;\n\tunsigned int st_mtime_nsec;\n\tunsigned int st_ctime;\n\tunsigned int st_ctime_nsec;\n\tlong long unsigned int st_ino;\n} __attribute__((packed));\n\nstruct mmap_arg_struct32 {\n\tunsigned int addr;\n\tunsigned int len;\n\tunsigned int prot;\n\tunsigned int flags;\n\tunsigned int fd;\n\tunsigned int offset;\n};\n\nstruct vm_unmapped_area_info {\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n};\n\nenum align_flags {\n\tALIGN_VA_32 = 1,\n\tALIGN_VA_64 = 2,\n};\n\nenum {\n\tMEMREMAP_WB = 1,\n\tMEMREMAP_WT = 2,\n\tMEMREMAP_WC = 4,\n\tMEMREMAP_ENC = 8,\n\tMEMREMAP_DEC = 16,\n};\n\nenum {\n\tIORES_DESC_NONE = 0,\n\tIORES_DESC_CRASH_KERNEL = 1,\n\tIORES_DESC_ACPI_TABLES = 2,\n\tIORES_DESC_ACPI_NV_STORAGE = 3,\n\tIORES_DESC_PERSISTENT_MEMORY = 4,\n\tIORES_DESC_PERSISTENT_MEMORY_LEGACY = 5,\n\tIORES_DESC_DEVICE_PRIVATE_MEMORY = 6,\n\tIORES_DESC_RESERVED = 7,\n\tIORES_DESC_SOFT_RESERVED = 8,\n};\n\nstruct change_member {\n\tstruct e820_entry *entry;\n\tlong long unsigned int addr;\n};\n\nstruct iommu_fault_param;\n\nstruct iommu_fwspec;\n\nstruct dev_iommu {\n\tstruct mutex lock;\n\tstruct iommu_fault_param *fault_param;\n\tstruct iommu_fwspec *fwspec;\n\tstruct iommu_device *iommu_dev;\n\tvoid *priv;\n};\n\nstruct of_phandle_args {\n\tstruct device_node *np;\n\tint args_count;\n\tuint32_t args[16];\n};\n\nstruct iommu_fault_unrecoverable {\n\t__u32 reason;\n\t__u32 flags;\n\t__u32 pasid;\n\t__u32 perm;\n\t__u64 addr;\n\t__u64 fetch_addr;\n};\n\nstruct iommu_fault_page_request {\n\t__u32 flags;\n\t__u32 pasid;\n\t__u32 grpid;\n\t__u32 perm;\n\t__u64 addr;\n\t__u64 private_data[2];\n};\n\nstruct iommu_fault {\n\t__u32 type;\n\t__u32 padding;\n\tunion {\n\t\tstruct iommu_fault_unrecoverable event;\n\t\tstruct iommu_fault_page_request prm;\n\t\t__u8 padding2[56];\n\t};\n};\n\nstruct iommu_page_response {\n\t__u32 version;\n\t__u32 flags;\n\t__u32 pasid;\n\t__u32 grpid;\n\t__u32 code;\n};\n\nstruct iommu_inv_addr_info {\n\t__u32 flags;\n\t__u32 archid;\n\t__u64 pasid;\n\t__u64 addr;\n\t__u64 granule_size;\n\t__u64 nb_granules;\n};\n\nstruct iommu_inv_pasid_info {\n\t__u32 flags;\n\t__u32 archid;\n\t__u64 pasid;\n};\n\nstruct iommu_cache_invalidate_info {\n\t__u32 version;\n\t__u8 cache;\n\t__u8 granularity;\n\t__u8 padding[2];\n\tunion {\n\t\tstruct iommu_inv_pasid_info pasid_info;\n\t\tstruct iommu_inv_addr_info addr_info;\n\t};\n};\n\nstruct iommu_gpasid_bind_data_vtd {\n\t__u64 flags;\n\t__u32 pat;\n\t__u32 emt;\n};\n\nstruct iommu_gpasid_bind_data {\n\t__u32 version;\n\t__u32 format;\n\t__u64 flags;\n\t__u64 gpgd;\n\t__u64 hpasid;\n\t__u64 gpasid;\n\t__u32 addr_width;\n\t__u8 padding[12];\n\tunion {\n\t\tstruct iommu_gpasid_bind_data_vtd vtd;\n\t};\n};\n\ntypedef int (*iommu_fault_handler_t)(struct iommu_domain *, struct device *, long unsigned int, int, void *);\n\nstruct iommu_domain_geometry {\n\tdma_addr_t aperture_start;\n\tdma_addr_t aperture_end;\n\tbool force_aperture;\n};\n\nstruct iommu_domain {\n\tunsigned int type;\n\tconst struct iommu_ops *ops;\n\tlong unsigned int pgsize_bitmap;\n\tiommu_fault_handler_t handler;\n\tvoid *handler_token;\n\tstruct iommu_domain_geometry geometry;\n\tvoid *iova_cookie;\n};\n\ntypedef int (*iommu_dev_fault_handler_t)(struct iommu_fault *, void *);\n\nenum iommu_resv_type {\n\tIOMMU_RESV_DIRECT = 0,\n\tIOMMU_RESV_DIRECT_RELAXABLE = 1,\n\tIOMMU_RESV_RESERVED = 2,\n\tIOMMU_RESV_MSI = 3,\n\tIOMMU_RESV_SW_MSI = 4,\n};\n\nstruct iommu_resv_region {\n\tstruct list_head list;\n\tphys_addr_t start;\n\tsize_t length;\n\tint prot;\n\tenum iommu_resv_type type;\n};\n\nstruct iommu_iotlb_gather {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tsize_t pgsize;\n};\n\nstruct iommu_device {\n\tstruct list_head list;\n\tconst struct iommu_ops *ops;\n\tstruct fwnode_handle *fwnode;\n\tstruct device *dev;\n};\n\nstruct iommu_sva {\n\tstruct device *dev;\n};\n\nstruct iommu_fault_event {\n\tstruct iommu_fault fault;\n\tstruct list_head list;\n};\n\nstruct iommu_fault_param {\n\tiommu_dev_fault_handler_t handler;\n\tvoid *data;\n\tstruct list_head faults;\n\tstruct mutex lock;\n};\n\nstruct iommu_fwspec {\n\tconst struct iommu_ops *ops;\n\tstruct fwnode_handle *iommu_fwnode;\n\tu32 flags;\n\tu32 num_pasid_bits;\n\tunsigned int num_ids;\n\tu32 ids[0];\n};\n\nstruct iommu_table_entry {\n\tinitcall_t detect;\n\tinitcall_t depend;\n\tvoid (*early_init)();\n\tvoid (*late_init)();\n\tint flags;\n};\n\nenum dmi_field {\n\tDMI_NONE = 0,\n\tDMI_BIOS_VENDOR = 1,\n\tDMI_BIOS_VERSION = 2,\n\tDMI_BIOS_DATE = 3,\n\tDMI_BIOS_RELEASE = 4,\n\tDMI_EC_FIRMWARE_RELEASE = 5,\n\tDMI_SYS_VENDOR = 6,\n\tDMI_PRODUCT_NAME = 7,\n\tDMI_PRODUCT_VERSION = 8,\n\tDMI_PRODUCT_SERIAL = 9,\n\tDMI_PRODUCT_UUID = 10,\n\tDMI_PRODUCT_SKU = 11,\n\tDMI_PRODUCT_FAMILY = 12,\n\tDMI_BOARD_VENDOR = 13,\n\tDMI_BOARD_NAME = 14,\n\tDMI_BOARD_VERSION = 15,\n\tDMI_BOARD_SERIAL = 16,\n\tDMI_BOARD_ASSET_TAG = 17,\n\tDMI_CHASSIS_VENDOR = 18,\n\tDMI_CHASSIS_TYPE = 19,\n\tDMI_CHASSIS_VERSION = 20,\n\tDMI_CHASSIS_SERIAL = 21,\n\tDMI_CHASSIS_ASSET_TAG = 22,\n\tDMI_STRING_MAX = 23,\n\tDMI_OEM_STRING = 24,\n};\n\nenum {\n\tNONE_FORCE_HPET_RESUME = 0,\n\tOLD_ICH_FORCE_HPET_RESUME = 1,\n\tICH_FORCE_HPET_RESUME = 2,\n\tVT8237_FORCE_HPET_RESUME = 3,\n\tNVIDIA_FORCE_HPET_RESUME = 4,\n\tATI_FORCE_HPET_RESUME = 5,\n};\n\nstruct cpu {\n\tint node_id;\n\tint hotpluggable;\n\tstruct device dev;\n};\n\nstruct x86_cpu {\n\tstruct cpu cpu;\n};\n\nstruct debugfs_blob_wrapper {\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct setup_data_node {\n\tu64 paddr;\n\tu32 type;\n\tu32 len;\n};\n\ntypedef int (*cmp_func_t)(const void *, const void *);\n\nstruct die_args {\n\tstruct pt_regs *regs;\n\tconst char *str;\n\tlong int err;\n\tint trapnr;\n\tint signr;\n};\n\nstruct smp_alt_module {\n\tstruct module *mod;\n\tchar *name;\n\tconst s32 *locks;\n\tconst s32 *locks_end;\n\tu8 *text;\n\tu8 *text_end;\n\tstruct list_head next;\n};\n\ntypedef struct {\n\tstruct mm_struct *mm;\n} temp_mm_state_t;\n\nstruct text_poke_loc {\n\ts32 rel_addr;\n\ts32 rel32;\n\tu8 opcode;\n\tconst u8 text[5];\n};\n\nstruct bp_patching_desc {\n\tstruct text_poke_loc *vec;\n\tint nr_entries;\n\tatomic_t refs;\n};\n\nstruct paravirt_patch_site;\n\nstruct user_i387_struct {\n\tshort unsigned int cwd;\n\tshort unsigned int swd;\n\tshort unsigned int twd;\n\tshort unsigned int fop;\n\t__u64 rip;\n\t__u64 rdp;\n\t__u32 mxcsr;\n\t__u32 mxcsr_mask;\n\t__u32 st_space[32];\n\t__u32 xmm_space[64];\n\t__u32 padding[24];\n};\n\nstruct user_regs_struct {\n\tlong unsigned int r15;\n\tlong unsigned int r14;\n\tlong unsigned int r13;\n\tlong unsigned int r12;\n\tlong unsigned int bp;\n\tlong unsigned int bx;\n\tlong unsigned int r11;\n\tlong unsigned int r10;\n\tlong unsigned int r9;\n\tlong unsigned int r8;\n\tlong unsigned int ax;\n\tlong unsigned int cx;\n\tlong unsigned int dx;\n\tlong unsigned int si;\n\tlong unsigned int di;\n\tlong unsigned int orig_ax;\n\tlong unsigned int ip;\n\tlong unsigned int cs;\n\tlong unsigned int flags;\n\tlong unsigned int sp;\n\tlong unsigned int ss;\n\tlong unsigned int fs_base;\n\tlong unsigned int gs_base;\n\tlong unsigned int ds;\n\tlong unsigned int es;\n\tlong unsigned int fs;\n\tlong unsigned int gs;\n};\n\nstruct user {\n\tstruct user_regs_struct regs;\n\tint u_fpvalid;\n\tint pad0;\n\tstruct user_i387_struct i387;\n\tlong unsigned int u_tsize;\n\tlong unsigned int u_dsize;\n\tlong unsigned int u_ssize;\n\tlong unsigned int start_code;\n\tlong unsigned int start_stack;\n\tlong int signal;\n\tint reserved;\n\tint pad1;\n\tlong unsigned int u_ar0;\n\tstruct user_i387_struct *u_fpstate;\n\tlong unsigned int magic;\n\tchar u_comm[32];\n\tlong unsigned int u_debugreg[8];\n\tlong unsigned int error_code;\n\tlong unsigned int fault_address;\n};\n\nenum {\n\tHW_BREAKPOINT_LEN_1 = 1,\n\tHW_BREAKPOINT_LEN_2 = 2,\n\tHW_BREAKPOINT_LEN_3 = 3,\n\tHW_BREAKPOINT_LEN_4 = 4,\n\tHW_BREAKPOINT_LEN_5 = 5,\n\tHW_BREAKPOINT_LEN_6 = 6,\n\tHW_BREAKPOINT_LEN_7 = 7,\n\tHW_BREAKPOINT_LEN_8 = 8,\n};\n\nenum {\n\tHW_BREAKPOINT_EMPTY = 0,\n\tHW_BREAKPOINT_R = 1,\n\tHW_BREAKPOINT_W = 2,\n\tHW_BREAKPOINT_RW = 3,\n\tHW_BREAKPOINT_X = 4,\n\tHW_BREAKPOINT_INVALID = 7,\n};\n\ntypedef unsigned int u_int;\n\ntypedef long long unsigned int cycles_t;\n\nstruct system_counterval_t {\n\tu64 cycles;\n\tstruct clocksource *cs;\n};\n\nenum {\n\tWORK_STRUCT_PENDING_BIT = 0,\n\tWORK_STRUCT_DELAYED_BIT = 1,\n\tWORK_STRUCT_PWQ_BIT = 2,\n\tWORK_STRUCT_LINKED_BIT = 3,\n\tWORK_STRUCT_COLOR_SHIFT = 4,\n\tWORK_STRUCT_COLOR_BITS = 4,\n\tWORK_STRUCT_PENDING = 1,\n\tWORK_STRUCT_DELAYED = 2,\n\tWORK_STRUCT_PWQ = 4,\n\tWORK_STRUCT_LINKED = 8,\n\tWORK_STRUCT_STATIC = 0,\n\tWORK_NR_COLORS = 15,\n\tWORK_NO_COLOR = 15,\n\tWORK_CPU_UNBOUND = 64,\n\tWORK_STRUCT_FLAG_BITS = 8,\n\tWORK_OFFQ_FLAG_BASE = 4,\n\t__WORK_OFFQ_CANCELING = 4,\n\tWORK_OFFQ_CANCELING = 16,\n\tWORK_OFFQ_FLAG_BITS = 1,\n\tWORK_OFFQ_POOL_SHIFT = 5,\n\tWORK_OFFQ_LEFT = 59,\n\tWORK_OFFQ_POOL_BITS = 31,\n\tWORK_OFFQ_POOL_NONE = 2147483647,\n\tWORK_STRUCT_FLAG_MASK = 255,\n\tWORK_STRUCT_WQ_DATA_MASK = 4294967040,\n\tWORK_STRUCT_NO_POOL = 4294967264,\n\tWORK_BUSY_PENDING = 1,\n\tWORK_BUSY_RUNNING = 2,\n\tWORKER_DESC_LEN = 24,\n};\n\nstruct plist_head {\n\tstruct list_head node_list;\n};\n\nenum pm_qos_type {\n\tPM_QOS_UNITIALIZED = 0,\n\tPM_QOS_MAX = 1,\n\tPM_QOS_MIN = 2,\n};\n\nstruct pm_qos_constraints {\n\tstruct plist_head list;\n\ts32 target_value;\n\ts32 default_value;\n\ts32 no_constraint_value;\n\tenum pm_qos_type type;\n\tstruct blocking_notifier_head *notifiers;\n};\n\nstruct freq_constraints {\n\tstruct pm_qos_constraints min_freq;\n\tstruct blocking_notifier_head min_freq_notifiers;\n\tstruct pm_qos_constraints max_freq;\n\tstruct blocking_notifier_head max_freq_notifiers;\n};\n\nstruct pm_qos_flags {\n\tstruct list_head list;\n\ts32 effective_flags;\n};\n\nstruct dev_pm_qos_request;\n\nstruct dev_pm_qos {\n\tstruct pm_qos_constraints resume_latency;\n\tstruct pm_qos_constraints latency_tolerance;\n\tstruct freq_constraints freq;\n\tstruct pm_qos_flags flags;\n\tstruct dev_pm_qos_request *resume_latency_req;\n\tstruct dev_pm_qos_request *latency_tolerance_req;\n\tstruct dev_pm_qos_request *flags_req;\n};\n\nstruct pm_qos_flags_request {\n\tstruct list_head node;\n\ts32 flags;\n};\n\nenum freq_qos_req_type {\n\tFREQ_QOS_MIN = 1,\n\tFREQ_QOS_MAX = 2,\n};\n\nstruct freq_qos_request {\n\tenum freq_qos_req_type type;\n\tstruct plist_node pnode;\n\tstruct freq_constraints *qos;\n};\n\nenum dev_pm_qos_req_type {\n\tDEV_PM_QOS_RESUME_LATENCY = 1,\n\tDEV_PM_QOS_LATENCY_TOLERANCE = 2,\n\tDEV_PM_QOS_MIN_FREQUENCY = 3,\n\tDEV_PM_QOS_MAX_FREQUENCY = 4,\n\tDEV_PM_QOS_FLAGS = 5,\n};\n\nstruct dev_pm_qos_request {\n\tenum dev_pm_qos_req_type type;\n\tunion {\n\t\tstruct plist_node pnode;\n\t\tstruct pm_qos_flags_request flr;\n\t\tstruct freq_qos_request freq;\n\t} data;\n\tstruct device *dev;\n};\n\nenum cpufreq_table_sorting {\n\tCPUFREQ_TABLE_UNSORTED = 0,\n\tCPUFREQ_TABLE_SORTED_ASCENDING = 1,\n\tCPUFREQ_TABLE_SORTED_DESCENDING = 2,\n};\n\nstruct cpufreq_cpuinfo {\n\tunsigned int max_freq;\n\tunsigned int min_freq;\n\tunsigned int transition_latency;\n};\n\nstruct cpufreq_stats;\n\nstruct clk;\n\nstruct cpufreq_governor;\n\nstruct cpufreq_frequency_table;\n\nstruct thermal_cooling_device;\n\nstruct cpufreq_policy {\n\tcpumask_var_t cpus;\n\tcpumask_var_t related_cpus;\n\tcpumask_var_t real_cpus;\n\tunsigned int shared_type;\n\tunsigned int cpu;\n\tstruct clk *clk;\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int cur;\n\tunsigned int restore_freq;\n\tunsigned int suspend_freq;\n\tunsigned int policy;\n\tunsigned int last_policy;\n\tstruct cpufreq_governor *governor;\n\tvoid *governor_data;\n\tchar last_governor[16];\n\tstruct work_struct update;\n\tstruct freq_constraints constraints;\n\tstruct freq_qos_request *min_freq_req;\n\tstruct freq_qos_request *max_freq_req;\n\tstruct cpufreq_frequency_table *freq_table;\n\tenum cpufreq_table_sorting freq_table_sorted;\n\tstruct list_head policy_list;\n\tstruct kobject kobj;\n\tstruct completion kobj_unregister;\n\tstruct rw_semaphore rwsem;\n\tbool fast_switch_possible;\n\tbool fast_switch_enabled;\n\tunsigned int transition_delay_us;\n\tbool dvfs_possible_from_any_cpu;\n\tunsigned int cached_target_freq;\n\tint cached_resolved_idx;\n\tbool transition_ongoing;\n\tspinlock_t transition_lock;\n\twait_queue_head_t transition_wait;\n\tstruct task_struct *transition_task;\n\tstruct cpufreq_stats *stats;\n\tvoid *driver_data;\n\tstruct thermal_cooling_device *cdev;\n\tstruct notifier_block nb_min;\n\tstruct notifier_block nb_max;\n};\n\nstruct cpufreq_governor {\n\tchar name[16];\n\tint (*init)(struct cpufreq_policy *);\n\tvoid (*exit)(struct cpufreq_policy *);\n\tint (*start)(struct cpufreq_policy *);\n\tvoid (*stop)(struct cpufreq_policy *);\n\tvoid (*limits)(struct cpufreq_policy *);\n\tssize_t (*show_setspeed)(struct cpufreq_policy *, char *);\n\tint (*store_setspeed)(struct cpufreq_policy *, unsigned int);\n\tbool dynamic_switching;\n\tstruct list_head governor_list;\n\tstruct module *owner;\n};\n\nstruct cpufreq_frequency_table {\n\tunsigned int flags;\n\tunsigned int driver_data;\n\tunsigned int frequency;\n};\n\nstruct cpufreq_freqs {\n\tstruct cpufreq_policy *policy;\n\tunsigned int old;\n\tunsigned int new;\n\tu8 flags;\n};\n\nstruct freq_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpufreq_policy *, char *);\n\tssize_t (*store)(struct cpufreq_policy *, const char *, size_t);\n};\n\nstruct cyc2ns {\n\tstruct cyc2ns_data data[2];\n\tseqcount_t seq;\n};\n\nstruct muldiv {\n\tu32 multiplier;\n\tu32 divider;\n};\n\nstruct freq_desc {\n\tbool use_msr_plat;\n\tstruct muldiv muldiv[16];\n\tu32 freqs[16];\n\tu32 mask;\n};\n\nstruct dmi_strmatch {\n\tunsigned char slot: 7;\n\tunsigned char exact_match: 1;\n\tchar substr[79];\n};\n\nstruct dmi_system_id {\n\tint (*callback)(const struct dmi_system_id *);\n\tconst char *ident;\n\tstruct dmi_strmatch matches[4];\n\tvoid *driver_data;\n};\n\nstruct pdev_archdata {};\n\nstruct mfd_cell;\n\nstruct platform_device_id;\n\nstruct platform_device {\n\tconst char *name;\n\tint id;\n\tbool id_auto;\n\tstruct device dev;\n\tu64 platform_dma_mask;\n\tstruct device_dma_parameters dma_parms;\n\tu32 num_resources;\n\tstruct resource *resource;\n\tconst struct platform_device_id *id_entry;\n\tchar *driver_override;\n\tstruct mfd_cell *mfd_cell;\n\tstruct pdev_archdata archdata;\n};\n\nstruct platform_device_id {\n\tchar name[20];\n\tkernel_ulong_t driver_data;\n};\n\nstruct rtc_time {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tint tm_year;\n\tint tm_wday;\n\tint tm_yday;\n\tint tm_isdst;\n};\n\nstruct pnp_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n};\n\nstruct pnp_card_device_id {\n\t__u8 id[8];\n\tkernel_ulong_t driver_data;\n\tstruct {\n\t\t__u8 id[8];\n\t} devs[8];\n};\n\nstruct pnp_protocol;\n\nstruct pnp_id;\n\nstruct pnp_card {\n\tstruct device dev;\n\tunsigned char number;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head devices;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_id *id;\n\tchar name[50];\n\tunsigned char pnpver;\n\tunsigned char productver;\n\tunsigned int serial;\n\tunsigned char checksum;\n\tstruct proc_dir_entry *procdir;\n};\n\nstruct pnp_dev;\n\nstruct pnp_protocol {\n\tstruct list_head protocol_list;\n\tchar *name;\n\tint (*get)(struct pnp_dev *);\n\tint (*set)(struct pnp_dev *);\n\tint (*disable)(struct pnp_dev *);\n\tbool (*can_wakeup)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tunsigned char number;\n\tstruct device dev;\n\tstruct list_head cards;\n\tstruct list_head devices;\n};\n\nstruct pnp_id {\n\tchar id[8];\n\tstruct pnp_id *next;\n};\n\nstruct pnp_card_driver;\n\nstruct pnp_card_link {\n\tstruct pnp_card *card;\n\tstruct pnp_card_driver *driver;\n\tvoid *driver_data;\n\tpm_message_t pm_state;\n};\n\nstruct pnp_driver {\n\tconst char *name;\n\tconst struct pnp_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_dev *, const struct pnp_device_id *);\n\tvoid (*remove)(struct pnp_dev *);\n\tvoid (*shutdown)(struct pnp_dev *);\n\tint (*suspend)(struct pnp_dev *, pm_message_t);\n\tint (*resume)(struct pnp_dev *);\n\tstruct device_driver driver;\n};\n\nstruct pnp_card_driver {\n\tstruct list_head global_list;\n\tchar *name;\n\tconst struct pnp_card_device_id *id_table;\n\tunsigned int flags;\n\tint (*probe)(struct pnp_card_link *, const struct pnp_card_device_id *);\n\tvoid (*remove)(struct pnp_card_link *);\n\tint (*suspend)(struct pnp_card_link *, pm_message_t);\n\tint (*resume)(struct pnp_card_link *);\n\tstruct pnp_driver link;\n};\n\nstruct pnp_dev {\n\tstruct device dev;\n\tu64 dma_mask;\n\tunsigned int number;\n\tint status;\n\tstruct list_head global_list;\n\tstruct list_head protocol_list;\n\tstruct list_head card_list;\n\tstruct list_head rdev_list;\n\tstruct pnp_protocol *protocol;\n\tstruct pnp_card *card;\n\tstruct pnp_driver *driver;\n\tstruct pnp_card_link *card_link;\n\tstruct pnp_id *id;\n\tint active;\n\tint capabilities;\n\tunsigned int num_dependent_sets;\n\tstruct list_head resources;\n\tstruct list_head options;\n\tchar name[50];\n\tint flags;\n\tstruct proc_dir_entry *procent;\n\tvoid *data;\n};\n\nstruct sfi_rtc_table_entry {\n\tu64 phys_addr;\n\tu32 irq;\n} __attribute__((packed));\n\nenum intel_mid_cpu_type {\n\tINTEL_MID_CPU_CHIP_PENWELL = 2,\n\tINTEL_MID_CPU_CHIP_CLOVERVIEW = 3,\n\tINTEL_MID_CPU_CHIP_TANGIER = 4,\n};\n\nenum intel_mid_timer_options {\n\tINTEL_MID_TIMER_DEFAULT = 0,\n\tINTEL_MID_TIMER_APBT_ONLY = 1,\n\tINTEL_MID_TIMER_LAPIC_APBT = 2,\n};\n\ntypedef struct ldttss_desc tss_desc;\n\nenum idle_boot_override {\n\tIDLE_NO_OVERRIDE = 0,\n\tIDLE_HALT = 1,\n\tIDLE_NOMWAIT = 2,\n\tIDLE_POLL = 3,\n};\n\nenum tick_broadcast_mode {\n\tTICK_BROADCAST_OFF = 0,\n\tTICK_BROADCAST_ON = 1,\n\tTICK_BROADCAST_FORCE = 2,\n};\n\nenum tick_broadcast_state {\n\tTICK_BROADCAST_EXIT = 0,\n\tTICK_BROADCAST_ENTER = 1,\n};\n\nstruct cpuidle_state_usage {\n\tlong long unsigned int disable;\n\tlong long unsigned int usage;\n\tu64 time_ns;\n\tlong long unsigned int above;\n\tlong long unsigned int below;\n\tlong long unsigned int s2idle_usage;\n\tlong long unsigned int s2idle_time;\n};\n\nstruct cpuidle_driver_kobj;\n\nstruct cpuidle_state_kobj;\n\nstruct cpuidle_device_kobj;\n\nstruct cpuidle_device {\n\tunsigned int registered: 1;\n\tunsigned int enabled: 1;\n\tunsigned int poll_time_limit: 1;\n\tunsigned int cpu;\n\tktime_t next_hrtimer;\n\tint last_state_idx;\n\tu64 last_residency_ns;\n\tu64 poll_limit_ns;\n\tu64 forced_idle_latency_limit_ns;\n\tstruct cpuidle_state_usage states_usage[10];\n\tstruct cpuidle_state_kobj *kobjs[10];\n\tstruct cpuidle_driver_kobj *kobj_driver;\n\tstruct cpuidle_device_kobj *kobj_dev;\n\tstruct list_head device_list;\n};\n\nstruct inactive_task_frame {\n\tlong unsigned int r15;\n\tlong unsigned int r14;\n\tlong unsigned int r13;\n\tlong unsigned int r12;\n\tlong unsigned int bx;\n\tlong unsigned int bp;\n\tlong unsigned int ret_addr;\n};\n\nstruct fork_frame {\n\tstruct inactive_task_frame frame;\n\tstruct pt_regs regs;\n};\n\nstruct ssb_state {\n\tstruct ssb_state *shared_state;\n\traw_spinlock_t lock;\n\tunsigned int disable_state;\n\tlong unsigned int local_state;\n};\n\ntypedef u16 pto_T_____9;\n\nstruct trace_event_raw_x86_fpu {\n\tstruct trace_entry ent;\n\tstruct fpu *fpu;\n\tbool load_fpu;\n\tu64 xfeatures;\n\tu64 xcomp_bv;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_x86_fpu {};\n\ntypedef void (*btf_trace_x86_fpu_before_save)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_after_save)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_before_restore)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_after_restore)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_regs_activated)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_regs_deactivated)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_init_state)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_dropped)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_copy_src)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_copy_dst)(void *, struct fpu *);\n\ntypedef void (*btf_trace_x86_fpu_xstate_check_failed)(void *, struct fpu *);\n\ntypedef struct fpu *pto_T_____10;\n\nstruct _fpreg {\n\t__u16 significand[4];\n\t__u16 exponent;\n};\n\nstruct _fpxreg {\n\t__u16 significand[4];\n\t__u16 exponent;\n\t__u16 padding[3];\n};\n\nstruct user_i387_ia32_struct {\n\tu32 cwd;\n\tu32 swd;\n\tu32 twd;\n\tu32 fip;\n\tu32 fcs;\n\tu32 foo;\n\tu32 fos;\n\tu32 st_space[20];\n};\n\nstruct user_regset;\n\ntypedef int user_regset_active_fn(struct task_struct *, const struct user_regset *);\n\ntypedef int user_regset_get_fn(struct task_struct *, const struct user_regset *, unsigned int, unsigned int, void *, void *);\n\ntypedef int user_regset_set_fn(struct task_struct *, const struct user_regset *, unsigned int, unsigned int, const void *, const void *);\n\ntypedef int user_regset_writeback_fn(struct task_struct *, const struct user_regset *, int);\n\ntypedef unsigned int user_regset_get_size_fn(struct task_struct *, const struct user_regset *);\n\nstruct user_regset {\n\tuser_regset_get_fn *get;\n\tuser_regset_set_fn *set;\n\tuser_regset_active_fn *active;\n\tuser_regset_writeback_fn *writeback;\n\tuser_regset_get_size_fn *get_size;\n\tunsigned int n;\n\tunsigned int size;\n\tunsigned int align;\n\tunsigned int bias;\n\tunsigned int core_note_type;\n};\n\nstruct _fpx_sw_bytes {\n\t__u32 magic1;\n\t__u32 extended_size;\n\t__u64 xfeatures;\n\t__u32 xstate_size;\n\t__u32 padding[7];\n};\n\nstruct _xmmreg {\n\t__u32 element[4];\n};\n\nstruct _fpstate_32 {\n\t__u32 cw;\n\t__u32 sw;\n\t__u32 tag;\n\t__u32 ipoff;\n\t__u32 cssel;\n\t__u32 dataoff;\n\t__u32 datasel;\n\tstruct _fpreg _st[8];\n\t__u16 status;\n\t__u16 magic;\n\t__u32 _fxsr_env[6];\n\t__u32 mxcsr;\n\t__u32 reserved;\n\tstruct _fpxreg _fxsr_st[8];\n\tstruct _xmmreg _xmm[8];\n\tunion {\n\t\t__u32 padding1[44];\n\t\t__u32 padding[44];\n\t};\n\tunion {\n\t\t__u32 padding2[12];\n\t\tstruct _fpx_sw_bytes sw_reserved;\n\t};\n};\n\ntypedef u32 compat_ulong_t;\n\nstruct user_regset_view {\n\tconst char *name;\n\tconst struct user_regset *regsets;\n\tunsigned int n;\n\tu32 e_flags;\n\tu16 e_machine;\n\tu8 ei_osabi;\n};\n\nenum x86_regset {\n\tREGSET_GENERAL = 0,\n\tREGSET_FP = 1,\n\tREGSET_XFP = 2,\n\tREGSET_IOPERM64 = 2,\n\tREGSET_XSTATE = 3,\n\tREGSET_TLS = 4,\n\tREGSET_IOPERM32 = 5,\n};\n\nstruct pt_regs_offset {\n\tconst char *name;\n\tint offset;\n};\n\ntypedef bool (*stack_trace_consume_fn)(void *, long unsigned int, bool);\n\nstruct stack_frame_user {\n\tconst void *next_fp;\n\tlong unsigned int ret_addr;\n};\n\nenum cache_type {\n\tCACHE_TYPE_NOCACHE = 0,\n\tCACHE_TYPE_INST = 1,\n\tCACHE_TYPE_DATA = 2,\n\tCACHE_TYPE_SEPARATE = 3,\n\tCACHE_TYPE_UNIFIED = 4,\n};\n\nstruct cacheinfo {\n\tunsigned int id;\n\tenum cache_type type;\n\tunsigned int level;\n\tunsigned int coherency_line_size;\n\tunsigned int number_of_sets;\n\tunsigned int ways_of_associativity;\n\tunsigned int physical_line_partition;\n\tunsigned int size;\n\tcpumask_t shared_cpu_map;\n\tunsigned int attributes;\n\tvoid *fw_token;\n\tbool disable_sysfs;\n\tvoid *priv;\n};\n\nstruct cpu_cacheinfo {\n\tstruct cacheinfo *info_list;\n\tunsigned int num_levels;\n\tunsigned int num_leaves;\n\tbool cpu_map_populated;\n};\n\nstruct amd_nb_bus_dev_range {\n\tu8 bus;\n\tu8 dev_base;\n\tu8 dev_limit;\n};\n\nstruct amd_l3_cache {\n\tunsigned int indices;\n\tu8 subcaches[4];\n};\n\nstruct threshold_block {\n\tunsigned int block;\n\tunsigned int bank;\n\tunsigned int cpu;\n\tu32 address;\n\tu16 interrupt_enable;\n\tbool interrupt_capable;\n\tu16 threshold_limit;\n\tstruct kobject kobj;\n\tstruct list_head miscj;\n};\n\nstruct threshold_bank {\n\tstruct kobject *kobj;\n\tstruct threshold_block *blocks;\n\trefcount_t cpus;\n\tunsigned int shared;\n};\n\nstruct amd_northbridge {\n\tstruct pci_dev *root;\n\tstruct pci_dev *misc;\n\tstruct pci_dev *link;\n\tstruct amd_l3_cache l3_cache;\n\tstruct threshold_bank *bank4;\n};\n\nstruct cpu_dev {\n\tconst char *c_vendor;\n\tconst char *c_ident[2];\n\tvoid (*c_early_init)(struct cpuinfo_x86 *);\n\tvoid (*c_bsp_init)(struct cpuinfo_x86 *);\n\tvoid (*c_init)(struct cpuinfo_x86 *);\n\tvoid (*c_identify)(struct cpuinfo_x86 *);\n\tvoid (*c_detect_tlb)(struct cpuinfo_x86 *);\n\tint c_x86_vendor;\n};\n\nenum tsx_ctrl_states {\n\tTSX_CTRL_ENABLE = 0,\n\tTSX_CTRL_DISABLE = 1,\n\tTSX_CTRL_NOT_SUPPORTED = 2,\n};\n\nstruct _cache_table {\n\tunsigned char descriptor;\n\tchar cache_type;\n\tshort int size;\n};\n\nenum _cache_type {\n\tCTYPE_NULL = 0,\n\tCTYPE_DATA = 1,\n\tCTYPE_INST = 2,\n\tCTYPE_UNIFIED = 3,\n};\n\nunion _cpuid4_leaf_eax {\n\tstruct {\n\t\tenum _cache_type type: 5;\n\t\tunsigned int level: 3;\n\t\tunsigned int is_self_initializing: 1;\n\t\tunsigned int is_fully_associative: 1;\n\t\tunsigned int reserved: 4;\n\t\tunsigned int num_threads_sharing: 12;\n\t\tunsigned int num_cores_on_die: 6;\n\t} split;\n\tu32 full;\n};\n\nunion _cpuid4_leaf_ebx {\n\tstruct {\n\t\tunsigned int coherency_line_size: 12;\n\t\tunsigned int physical_line_partition: 10;\n\t\tunsigned int ways_of_associativity: 10;\n\t} split;\n\tu32 full;\n};\n\nunion _cpuid4_leaf_ecx {\n\tstruct {\n\t\tunsigned int number_of_sets: 32;\n\t} split;\n\tu32 full;\n};\n\nstruct _cpuid4_info_regs {\n\tunion _cpuid4_leaf_eax eax;\n\tunion _cpuid4_leaf_ebx ebx;\n\tunion _cpuid4_leaf_ecx ecx;\n\tunsigned int id;\n\tlong unsigned int size;\n\tstruct amd_northbridge *nb;\n};\n\nunion l1_cache {\n\tstruct {\n\t\tunsigned int line_size: 8;\n\t\tunsigned int lines_per_tag: 8;\n\t\tunsigned int assoc: 8;\n\t\tunsigned int size_in_kb: 8;\n\t};\n\tunsigned int val;\n};\n\nunion l2_cache {\n\tstruct {\n\t\tunsigned int line_size: 8;\n\t\tunsigned int lines_per_tag: 4;\n\t\tunsigned int assoc: 4;\n\t\tunsigned int size_in_kb: 16;\n\t};\n\tunsigned int val;\n};\n\nunion l3_cache {\n\tstruct {\n\t\tunsigned int line_size: 8;\n\t\tunsigned int lines_per_tag: 4;\n\t\tunsigned int assoc: 4;\n\t\tunsigned int res: 2;\n\t\tunsigned int size_encoded: 14;\n\t};\n\tunsigned int val;\n};\n\nstruct cpuid_bit {\n\tu16 feature;\n\tu8 reg;\n\tu8 bit;\n\tu32 level;\n\tu32 sub_leaf;\n};\n\nenum cpuid_leafs {\n\tCPUID_1_EDX = 0,\n\tCPUID_8000_0001_EDX = 1,\n\tCPUID_8086_0001_EDX = 2,\n\tCPUID_LNX_1 = 3,\n\tCPUID_1_ECX = 4,\n\tCPUID_C000_0001_EDX = 5,\n\tCPUID_8000_0001_ECX = 6,\n\tCPUID_LNX_2 = 7,\n\tCPUID_LNX_3 = 8,\n\tCPUID_7_0_EBX = 9,\n\tCPUID_D_1_EAX = 10,\n\tCPUID_LNX_4 = 11,\n\tCPUID_7_1_EAX = 12,\n\tCPUID_8000_0008_EBX = 13,\n\tCPUID_6_EAX = 14,\n\tCPUID_8000_000A_EDX = 15,\n\tCPUID_7_ECX = 16,\n\tCPUID_8000_0007_EBX = 17,\n\tCPUID_7_EDX = 18,\n};\n\nstruct cpuid_dependent_feature {\n\tu32 feature;\n\tu32 level;\n};\n\nenum spectre_v2_mitigation {\n\tSPECTRE_V2_NONE = 0,\n\tSPECTRE_V2_RETPOLINE_GENERIC = 1,\n\tSPECTRE_V2_RETPOLINE_AMD = 2,\n\tSPECTRE_V2_IBRS_ENHANCED = 3,\n};\n\nenum spectre_v2_user_mitigation {\n\tSPECTRE_V2_USER_NONE = 0,\n\tSPECTRE_V2_USER_STRICT = 1,\n\tSPECTRE_V2_USER_STRICT_PREFERRED = 2,\n\tSPECTRE_V2_USER_PRCTL = 3,\n\tSPECTRE_V2_USER_SECCOMP = 4,\n};\n\nenum ssb_mitigation {\n\tSPEC_STORE_BYPASS_NONE = 0,\n\tSPEC_STORE_BYPASS_DISABLE = 1,\n\tSPEC_STORE_BYPASS_PRCTL = 2,\n\tSPEC_STORE_BYPASS_SECCOMP = 3,\n};\n\nenum mds_mitigations {\n\tMDS_MITIGATION_OFF = 0,\n\tMDS_MITIGATION_FULL = 1,\n\tMDS_MITIGATION_VMWERV = 2,\n};\n\nenum vmx_l1d_flush_state {\n\tVMENTER_L1D_FLUSH_AUTO = 0,\n\tVMENTER_L1D_FLUSH_NEVER = 1,\n\tVMENTER_L1D_FLUSH_COND = 2,\n\tVMENTER_L1D_FLUSH_ALWAYS = 3,\n\tVMENTER_L1D_FLUSH_EPT_DISABLED = 4,\n\tVMENTER_L1D_FLUSH_NOT_REQUIRED = 5,\n};\n\nenum x86_hypervisor_type {\n\tX86_HYPER_NATIVE = 0,\n\tX86_HYPER_VMWARE = 1,\n\tX86_HYPER_MS_HYPERV = 2,\n\tX86_HYPER_XEN_PV = 3,\n\tX86_HYPER_XEN_HVM = 4,\n\tX86_HYPER_KVM = 5,\n\tX86_HYPER_JAILHOUSE = 6,\n\tX86_HYPER_ACRN = 7,\n};\n\nenum taa_mitigations {\n\tTAA_MITIGATION_OFF = 0,\n\tTAA_MITIGATION_UCODE_NEEDED = 1,\n\tTAA_MITIGATION_VERW = 2,\n\tTAA_MITIGATION_TSX_DISABLED = 3,\n};\n\nenum srbds_mitigations {\n\tSRBDS_MITIGATION_OFF = 0,\n\tSRBDS_MITIGATION_UCODE_NEEDED = 1,\n\tSRBDS_MITIGATION_FULL = 2,\n\tSRBDS_MITIGATION_TSX_OFF = 3,\n\tSRBDS_MITIGATION_HYPERVISOR = 4,\n};\n\nenum spectre_v1_mitigation {\n\tSPECTRE_V1_MITIGATION_NONE = 0,\n\tSPECTRE_V1_MITIGATION_AUTO = 1,\n};\n\nenum spectre_v2_mitigation_cmd {\n\tSPECTRE_V2_CMD_NONE = 0,\n\tSPECTRE_V2_CMD_AUTO = 1,\n\tSPECTRE_V2_CMD_FORCE = 2,\n\tSPECTRE_V2_CMD_RETPOLINE = 3,\n\tSPECTRE_V2_CMD_RETPOLINE_GENERIC = 4,\n\tSPECTRE_V2_CMD_RETPOLINE_AMD = 5,\n};\n\nenum spectre_v2_user_cmd {\n\tSPECTRE_V2_USER_CMD_NONE = 0,\n\tSPECTRE_V2_USER_CMD_AUTO = 1,\n\tSPECTRE_V2_USER_CMD_FORCE = 2,\n\tSPECTRE_V2_USER_CMD_PRCTL = 3,\n\tSPECTRE_V2_USER_CMD_PRCTL_IBPB = 4,\n\tSPECTRE_V2_USER_CMD_SECCOMP = 5,\n\tSPECTRE_V2_USER_CMD_SECCOMP_IBPB = 6,\n};\n\nenum ssb_mitigation_cmd {\n\tSPEC_STORE_BYPASS_CMD_NONE = 0,\n\tSPEC_STORE_BYPASS_CMD_AUTO = 1,\n\tSPEC_STORE_BYPASS_CMD_ON = 2,\n\tSPEC_STORE_BYPASS_CMD_PRCTL = 3,\n\tSPEC_STORE_BYPASS_CMD_SECCOMP = 4,\n};\n\nenum hk_flags {\n\tHK_FLAG_TIMER = 1,\n\tHK_FLAG_RCU = 2,\n\tHK_FLAG_MISC = 4,\n\tHK_FLAG_SCHED = 8,\n\tHK_FLAG_TICK = 16,\n\tHK_FLAG_DOMAIN = 32,\n\tHK_FLAG_WQ = 64,\n\tHK_FLAG_MANAGED_IRQ = 128,\n};\n\nstruct aperfmperf_sample {\n\tunsigned int khz;\n\tktime_t time;\n\tu64 aperf;\n\tu64 mperf;\n};\n\nstruct cpuid_dep {\n\tunsigned int feature;\n\tunsigned int depends;\n};\n\nenum vmx_feature_leafs {\n\tMISC_FEATURES = 0,\n\tPRIMARY_CTLS = 1,\n\tSECONDARY_CTLS = 2,\n\tNR_VMX_FEATURE_WORDS = 3,\n};\n\nstruct _tlb_table {\n\tunsigned char descriptor;\n\tchar tlb_type;\n\tunsigned int entries;\n\tchar info[128];\n};\n\nenum split_lock_detect_state {\n\tsld_off = 0,\n\tsld_warn = 1,\n\tsld_fatal = 2,\n};\n\nstruct sku_microcode {\n\tu8 model;\n\tu8 stepping;\n\tu32 microcode;\n};\n\nstruct cpuid_regs {\n\tu32 eax;\n\tu32 ebx;\n\tu32 ecx;\n\tu32 edx;\n};\n\nenum pconfig_target {\n\tINVALID_TARGET = 0,\n\tMKTME_TARGET = 1,\n\tPCONFIG_TARGET_NR = 2,\n};\n\nenum {\n\tPCONFIG_CPUID_SUBLEAF_INVALID = 0,\n\tPCONFIG_CPUID_SUBLEAF_TARGETID = 1,\n};\n\ntypedef u8 pto_T_____11;\n\nenum mf_flags {\n\tMF_COUNT_INCREASED = 1,\n\tMF_ACTION_REQUIRED = 2,\n\tMF_MUST_KILL = 4,\n\tMF_SOFT_OFFLINE = 8,\n};\n\nenum mce_notifier_prios {\n\tMCE_PRIO_LOWEST = 0,\n\tMCE_PRIO_MCELOG = 1,\n\tMCE_PRIO_EDAC = 2,\n\tMCE_PRIO_NFIT = 3,\n\tMCE_PRIO_EXTLOG = 4,\n\tMCE_PRIO_UC = 5,\n\tMCE_PRIO_EARLY = 6,\n\tMCE_PRIO_CEC = 7,\n};\n\nenum mcp_flags {\n\tMCP_TIMESTAMP = 1,\n\tMCP_UC = 2,\n\tMCP_DONTLOG = 4,\n};\n\nenum severity_level {\n\tMCE_NO_SEVERITY = 0,\n\tMCE_DEFERRED_SEVERITY = 1,\n\tMCE_UCNA_SEVERITY = 1,\n\tMCE_KEEP_SEVERITY = 2,\n\tMCE_SOME_SEVERITY = 3,\n\tMCE_AO_SEVERITY = 4,\n\tMCE_UC_SEVERITY = 5,\n\tMCE_AR_SEVERITY = 6,\n\tMCE_PANIC_SEVERITY = 7,\n};\n\nstruct mce_evt_llist {\n\tstruct llist_node llnode;\n\tstruct mce mce;\n};\n\nstruct mca_config {\n\tbool dont_log_ce;\n\tbool cmci_disabled;\n\tbool ignore_ce;\n\tbool print_all;\n\t__u64 lmce_disabled: 1;\n\t__u64 disabled: 1;\n\t__u64 ser: 1;\n\t__u64 recovery: 1;\n\t__u64 bios_cmci_threshold: 1;\n\tint: 27;\n\t__u64 __reserved: 59;\n\ts8 bootlog;\n\tint tolerant;\n\tint monarch_timeout;\n\tint panic_timeout;\n\tu32 rip_msr;\n};\n\nstruct mce_vendor_flags {\n\t__u64 overflow_recov: 1;\n\t__u64 succor: 1;\n\t__u64 smca: 1;\n\t__u64 amd_threshold: 1;\n\t__u64 __reserved_0: 60;\n};\n\nstruct mca_msr_regs {\n\tu32 (*ctl)(int);\n\tu32 (*status)(int);\n\tu32 (*addr)(int);\n\tu32 (*misc)(int);\n};\n\nstruct trace_event_raw_mce_record {\n\tstruct trace_entry ent;\n\tu64 mcgcap;\n\tu64 mcgstatus;\n\tu64 status;\n\tu64 addr;\n\tu64 misc;\n\tu64 synd;\n\tu64 ipid;\n\tu64 ip;\n\tu64 tsc;\n\tu64 walltime;\n\tu32 cpu;\n\tu32 cpuid;\n\tu32 apicid;\n\tu32 socketid;\n\tu8 cs;\n\tu8 bank;\n\tu8 cpuvendor;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_mce_record {};\n\ntypedef void (*btf_trace_mce_record)(void *, struct mce *);\n\nstruct mce_bank {\n\tu64 ctl;\n\tbool init;\n};\n\nstruct mce_bank_dev {\n\tstruct device_attribute attr;\n\tchar attrname[16];\n\tu8 bank;\n};\n\ntypedef unsigned int pto_T_____12;\n\nenum context {\n\tIN_KERNEL = 1,\n\tIN_USER = 2,\n\tIN_KERNEL_RECOV = 3,\n};\n\nenum ser {\n\tSER_REQUIRED = 1,\n\tNO_SER = 2,\n};\n\nenum exception {\n\tEXCP_CONTEXT = 1,\n\tNO_EXCP = 2,\n};\n\nstruct severity {\n\tu64 mask;\n\tu64 result;\n\tunsigned char sev;\n\tunsigned char mcgmask;\n\tunsigned char mcgres;\n\tunsigned char ser;\n\tunsigned char context;\n\tunsigned char excp;\n\tunsigned char covered;\n\tchar *msg;\n};\n\nstruct gen_pool;\n\ntypedef long unsigned int (*genpool_algo_t)(long unsigned int *, long unsigned int, long unsigned int, unsigned int, void *, struct gen_pool *, long unsigned int);\n\nstruct gen_pool {\n\tspinlock_t lock;\n\tstruct list_head chunks;\n\tint min_alloc_order;\n\tgenpool_algo_t algo;\n\tvoid *data;\n\tconst char *name;\n};\n\nenum {\n\tCMCI_STORM_NONE = 0,\n\tCMCI_STORM_ACTIVE = 1,\n\tCMCI_STORM_SUBSIDED = 2,\n};\n\nenum kobject_action {\n\tKOBJ_ADD = 0,\n\tKOBJ_REMOVE = 1,\n\tKOBJ_CHANGE = 2,\n\tKOBJ_MOVE = 3,\n\tKOBJ_ONLINE = 4,\n\tKOBJ_OFFLINE = 5,\n\tKOBJ_BIND = 6,\n\tKOBJ_UNBIND = 7,\n\tKOBJ_MAX = 8,\n};\n\nenum smca_bank_types {\n\tSMCA_LS = 0,\n\tSMCA_LS_V2 = 1,\n\tSMCA_IF = 2,\n\tSMCA_L2_CACHE = 3,\n\tSMCA_DE = 4,\n\tSMCA_RESERVED = 5,\n\tSMCA_EX = 6,\n\tSMCA_FP = 7,\n\tSMCA_L3_CACHE = 8,\n\tSMCA_CS = 9,\n\tSMCA_CS_V2 = 10,\n\tSMCA_PIE = 11,\n\tSMCA_UMC = 12,\n\tSMCA_PB = 13,\n\tSMCA_PSP = 14,\n\tSMCA_PSP_V2 = 15,\n\tSMCA_SMU = 16,\n\tSMCA_SMU_V2 = 17,\n\tSMCA_MP5 = 18,\n\tSMCA_NBIO = 19,\n\tSMCA_PCIE = 20,\n\tN_SMCA_BANK_TYPES = 21,\n};\n\nstruct smca_bank_name {\n\tconst char *name;\n\tconst char *long_name;\n};\n\nstruct thresh_restart {\n\tstruct threshold_block *b;\n\tint reset;\n\tint set_lvt_off;\n\tint lvt_off;\n\tu16 old_limit;\n};\n\nstruct threshold_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct threshold_block *, char *);\n\tssize_t (*store)(struct threshold_block *, const char *, size_t);\n};\n\ntypedef struct threshold_bank **pto_T_____13;\n\nstruct _thermal_state {\n\tu64 next_check;\n\tu64 last_interrupt_time;\n\tstruct delayed_work therm_work;\n\tlong unsigned int count;\n\tlong unsigned int last_count;\n\tlong unsigned int max_time_ms;\n\tlong unsigned int total_time_ms;\n\tbool rate_control_active;\n\tbool new_event;\n\tu8 level;\n\tu8 sample_index;\n\tu8 sample_count;\n\tu8 average;\n\tu8 baseline_temp;\n\tu8 temp_samples[3];\n};\n\nstruct thermal_state {\n\tstruct _thermal_state core_throttle;\n\tstruct _thermal_state core_power_limit;\n\tstruct _thermal_state package_throttle;\n\tstruct _thermal_state package_power_limit;\n\tstruct _thermal_state core_thresh0;\n\tstruct _thermal_state core_thresh1;\n\tstruct _thermal_state pkg_thresh0;\n\tstruct _thermal_state pkg_thresh1;\n};\n\nstruct mtrr_var_range {\n\t__u32 base_lo;\n\t__u32 base_hi;\n\t__u32 mask_lo;\n\t__u32 mask_hi;\n};\n\ntypedef __u8 mtrr_type;\n\nstruct mtrr_state_type {\n\tstruct mtrr_var_range var_ranges[256];\n\tmtrr_type fixed_ranges[88];\n\tunsigned char enabled;\n\tunsigned char have_fixed;\n\tmtrr_type def_type;\n};\n\nstruct mtrr_ops {\n\tu32 vendor;\n\tu32 use_intel_if;\n\tvoid (*set)(unsigned int, long unsigned int, long unsigned int, mtrr_type);\n\tvoid (*set_all)();\n\tvoid (*get)(unsigned int, long unsigned int *, long unsigned int *, mtrr_type *);\n\tint (*get_free_region)(long unsigned int, long unsigned int, int);\n\tint (*validate_add_page)(long unsigned int, long unsigned int, unsigned int);\n\tint (*have_wrcomb)();\n};\n\nstruct set_mtrr_data {\n\tlong unsigned int smp_base;\n\tlong unsigned int smp_size;\n\tunsigned int smp_reg;\n\tmtrr_type smp_type;\n};\n\nstruct mtrr_value {\n\tmtrr_type ltype;\n\tlong unsigned int lbase;\n\tlong unsigned int lsize;\n};\n\nstruct proc_ops {\n\tunsigned int proc_flags;\n\tint (*proc_open)(struct inode *, struct file *);\n\tssize_t (*proc_read)(struct file *, char *, size_t, loff_t *);\n\tssize_t (*proc_write)(struct file *, const char *, size_t, loff_t *);\n\tloff_t (*proc_lseek)(struct file *, loff_t, int);\n\tint (*proc_release)(struct inode *, struct file *);\n\t__poll_t (*proc_poll)(struct file *, struct poll_table_struct *);\n\tlong int (*proc_ioctl)(struct file *, unsigned int, long unsigned int);\n\tlong int (*proc_compat_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*proc_mmap)(struct file *, struct vm_area_struct *);\n\tlong unsigned int (*proc_get_unmapped_area)(struct file *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n};\n\nstruct mtrr_sentry {\n\t__u64 base;\n\t__u32 size;\n\t__u32 type;\n};\n\nstruct mtrr_gentry {\n\t__u64 base;\n\t__u32 size;\n\t__u32 regnum;\n\t__u32 type;\n\t__u32 _pad;\n};\n\ntypedef u32 compat_uint_t;\n\nstruct mtrr_sentry32 {\n\tcompat_ulong_t base;\n\tcompat_uint_t size;\n\tcompat_uint_t type;\n};\n\nstruct mtrr_gentry32 {\n\tcompat_ulong_t regnum;\n\tcompat_uint_t base;\n\tcompat_uint_t size;\n\tcompat_uint_t type;\n};\n\nstruct fixed_range_block {\n\tint base_msr;\n\tint ranges;\n};\n\nstruct var_mtrr_range_state {\n\tlong unsigned int base_pfn;\n\tlong unsigned int size_pfn;\n\tmtrr_type type;\n};\n\nstruct subsys_interface {\n\tconst char *name;\n\tstruct bus_type *subsys;\n\tstruct list_head node;\n\tint (*add_dev)(struct device *, struct subsys_interface *);\n\tvoid (*remove_dev)(struct device *, struct subsys_interface *);\n};\n\nstruct property_entry;\n\nstruct platform_device_info {\n\tstruct device *parent;\n\tstruct fwnode_handle *fwnode;\n\tbool of_node_reused;\n\tconst char *name;\n\tint id;\n\tconst struct resource *res;\n\tunsigned int num_res;\n\tconst void *data;\n\tsize_t size_data;\n\tu64 dma_mask;\n\tconst struct property_entry *properties;\n};\n\nenum dev_prop_type {\n\tDEV_PROP_U8 = 0,\n\tDEV_PROP_U16 = 1,\n\tDEV_PROP_U32 = 2,\n\tDEV_PROP_U64 = 3,\n\tDEV_PROP_STRING = 4,\n\tDEV_PROP_REF = 5,\n};\n\nstruct property_entry {\n\tconst char *name;\n\tsize_t length;\n\tbool is_inline;\n\tenum dev_prop_type type;\n\tunion {\n\t\tconst void *pointer;\n\t\tunion {\n\t\t\tu8 u8_data[8];\n\t\t\tu16 u16_data[4];\n\t\t\tu32 u32_data[2];\n\t\t\tu64 u64_data[1];\n\t\t\tconst char *str[1];\n\t\t} value;\n\t};\n};\n\nstruct builtin_fw {\n\tchar *name;\n\tvoid *data;\n\tlong unsigned int size;\n};\n\nstruct cpio_data {\n\tvoid *data;\n\tsize_t size;\n\tchar name[18];\n};\n\nenum ucode_state {\n\tUCODE_OK = 0,\n\tUCODE_NEW = 1,\n\tUCODE_UPDATED = 2,\n\tUCODE_NFOUND = 3,\n\tUCODE_ERROR = 4,\n};\n\nstruct microcode_ops {\n\tenum ucode_state (*request_microcode_user)(int, const void *, size_t);\n\tenum ucode_state (*request_microcode_fw)(int, struct device *, bool);\n\tvoid (*microcode_fini_cpu)(int);\n\tenum ucode_state (*apply_microcode)(int);\n\tint (*collect_cpu_info)(int, struct cpu_signature *);\n};\n\nstruct cpu_info_ctx {\n\tstruct cpu_signature *cpu_sig;\n\tint err;\n};\n\nstruct firmware {\n\tsize_t size;\n\tconst u8 *data;\n\tvoid *priv;\n};\n\nstruct ucode_patch {\n\tstruct list_head plist;\n\tvoid *data;\n\tu32 patch_id;\n\tu16 equiv_cpu;\n};\n\nstruct microcode_header_intel {\n\tunsigned int hdrver;\n\tunsigned int rev;\n\tunsigned int date;\n\tunsigned int sig;\n\tunsigned int cksum;\n\tunsigned int ldrver;\n\tunsigned int pf;\n\tunsigned int datasize;\n\tunsigned int totalsize;\n\tunsigned int reserved[3];\n};\n\nstruct microcode_intel {\n\tstruct microcode_header_intel hdr;\n\tunsigned int bits[0];\n};\n\nstruct extended_signature {\n\tunsigned int sig;\n\tunsigned int pf;\n\tunsigned int cksum;\n};\n\nstruct extended_sigtable {\n\tunsigned int count;\n\tunsigned int cksum;\n\tunsigned int reserved[3];\n\tstruct extended_signature sigs[0];\n};\n\nstruct equiv_cpu_entry {\n\tu32 installed_cpu;\n\tu32 fixed_errata_mask;\n\tu32 fixed_errata_compare;\n\tu16 equiv_cpu;\n\tu16 res;\n};\n\nstruct microcode_header_amd {\n\tu32 data_code;\n\tu32 patch_id;\n\tu16 mc_patch_data_id;\n\tu8 mc_patch_data_len;\n\tu8 init_flag;\n\tu32 mc_patch_data_checksum;\n\tu32 nb_dev_id;\n\tu32 sb_dev_id;\n\tu16 processor_rev_id;\n\tu8 nb_rev_id;\n\tu8 sb_rev_id;\n\tu8 bios_api_rev;\n\tu8 reserved1[3];\n\tu32 match_reg[8];\n};\n\nstruct microcode_amd {\n\tstruct microcode_header_amd hdr;\n\tunsigned int mpb[0];\n};\n\nstruct equiv_cpu_table {\n\tunsigned int num_entries;\n\tstruct equiv_cpu_entry *entry;\n};\n\nstruct cont_desc {\n\tstruct microcode_amd *mc;\n\tu32 cpuid_1_eax;\n\tu32 psize;\n\tu8 *data;\n\tsize_t size;\n};\n\nenum mp_irq_source_types {\n\tmp_INT = 0,\n\tmp_NMI = 1,\n\tmp_SMI = 2,\n\tmp_ExtINT = 3,\n};\n\nstruct IO_APIC_route_entry {\n\t__u32 vector: 8;\n\t__u32 delivery_mode: 3;\n\t__u32 dest_mode: 1;\n\t__u32 delivery_status: 1;\n\t__u32 polarity: 1;\n\t__u32 irr: 1;\n\t__u32 trigger: 1;\n\t__u32 mask: 1;\n\t__u32 __reserved_2: 15;\n\t__u32 __reserved_3: 24;\n\t__u32 dest: 8;\n};\n\ntypedef u64 acpi_physical_address;\n\ntypedef u32 acpi_status;\n\ntypedef void *acpi_handle;\n\ntypedef u8 acpi_adr_space_type;\n\nstruct acpi_subtable_header {\n\tu8 type;\n\tu8 length;\n};\n\nstruct acpi_table_bgrt {\n\tstruct acpi_table_header header;\n\tu16 version;\n\tu8 status;\n\tu8 image_type;\n\tu64 image_address;\n\tu32 image_offset_x;\n\tu32 image_offset_y;\n};\n\nstruct acpi_table_boot {\n\tstruct acpi_table_header header;\n\tu8 cmos_index;\n\tu8 reserved[3];\n};\n\nstruct acpi_hmat_structure {\n\tu16 type;\n\tu16 reserved;\n\tu32 length;\n};\n\nstruct acpi_table_hpet {\n\tstruct acpi_table_header header;\n\tu32 id;\n\tstruct acpi_generic_address address;\n\tu8 sequence;\n\tu16 minimum_tick;\n\tu8 flags;\n} __attribute__((packed));\n\nstruct acpi_table_madt {\n\tstruct acpi_table_header header;\n\tu32 address;\n\tu32 flags;\n};\n\nenum acpi_madt_type {\n\tACPI_MADT_TYPE_LOCAL_APIC = 0,\n\tACPI_MADT_TYPE_IO_APIC = 1,\n\tACPI_MADT_TYPE_INTERRUPT_OVERRIDE = 2,\n\tACPI_MADT_TYPE_NMI_SOURCE = 3,\n\tACPI_MADT_TYPE_LOCAL_APIC_NMI = 4,\n\tACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE = 5,\n\tACPI_MADT_TYPE_IO_SAPIC = 6,\n\tACPI_MADT_TYPE_LOCAL_SAPIC = 7,\n\tACPI_MADT_TYPE_INTERRUPT_SOURCE = 8,\n\tACPI_MADT_TYPE_LOCAL_X2APIC = 9,\n\tACPI_MADT_TYPE_LOCAL_X2APIC_NMI = 10,\n\tACPI_MADT_TYPE_GENERIC_INTERRUPT = 11,\n\tACPI_MADT_TYPE_GENERIC_DISTRIBUTOR = 12,\n\tACPI_MADT_TYPE_GENERIC_MSI_FRAME = 13,\n\tACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14,\n\tACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15,\n\tACPI_MADT_TYPE_RESERVED = 16,\n};\n\nstruct acpi_madt_local_apic {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu8 id;\n\tu32 lapic_flags;\n};\n\nstruct acpi_madt_io_apic {\n\tstruct acpi_subtable_header header;\n\tu8 id;\n\tu8 reserved;\n\tu32 address;\n\tu32 global_irq_base;\n};\n\nstruct acpi_madt_interrupt_override {\n\tstruct acpi_subtable_header header;\n\tu8 bus;\n\tu8 source_irq;\n\tu32 global_irq;\n\tu16 inti_flags;\n} __attribute__((packed));\n\nstruct acpi_madt_nmi_source {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu32 global_irq;\n};\n\nstruct acpi_madt_local_apic_nmi {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu16 inti_flags;\n\tu8 lint;\n} __attribute__((packed));\n\nstruct acpi_madt_local_apic_override {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_madt_local_sapic {\n\tstruct acpi_subtable_header header;\n\tu8 processor_id;\n\tu8 id;\n\tu8 eid;\n\tu8 reserved[3];\n\tu32 lapic_flags;\n\tu32 uid;\n\tchar uid_string[1];\n} __attribute__((packed));\n\nstruct acpi_madt_local_x2apic {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 local_apic_id;\n\tu32 lapic_flags;\n\tu32 uid;\n};\n\nstruct acpi_madt_local_x2apic_nmi {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu32 uid;\n\tu8 lint;\n\tu8 reserved[3];\n};\n\nunion acpi_subtable_headers {\n\tstruct acpi_subtable_header common;\n\tstruct acpi_hmat_structure hmat;\n};\n\ntypedef int (*acpi_tbl_entry_handler)(union acpi_subtable_headers *, const long unsigned int);\n\nstruct acpi_subtable_proc {\n\tint id;\n\tacpi_tbl_entry_handler handler;\n\tint count;\n};\n\ntypedef u32 phys_cpuid_t;\n\nstruct gpio_desc;\n\nenum irq_alloc_type {\n\tX86_IRQ_ALLOC_TYPE_IOAPIC = 1,\n\tX86_IRQ_ALLOC_TYPE_HPET = 2,\n\tX86_IRQ_ALLOC_TYPE_MSI = 3,\n\tX86_IRQ_ALLOC_TYPE_MSIX = 4,\n\tX86_IRQ_ALLOC_TYPE_DMAR = 5,\n\tX86_IRQ_ALLOC_TYPE_UV = 6,\n};\n\nstruct irq_alloc_info {\n\tenum irq_alloc_type type;\n\tu32 flags;\n\tconst struct cpumask *mask;\n\tunion {\n\t\tint unused;\n\t\tstruct {\n\t\t\tint hpet_id;\n\t\t\tint hpet_index;\n\t\t\tvoid *hpet_data;\n\t\t};\n\t\tstruct {\n\t\t\tstruct pci_dev *msi_dev;\n\t\t\tirq_hw_number_t msi_hwirq;\n\t\t};\n\t\tstruct {\n\t\t\tint ioapic_id;\n\t\t\tint ioapic_pin;\n\t\t\tint ioapic_node;\n\t\t\tu32 ioapic_trigger: 1;\n\t\t\tu32 ioapic_polarity: 1;\n\t\t\tu32 ioapic_valid: 1;\n\t\t\tstruct IO_APIC_route_entry *ioapic_entry;\n\t\t};\n\t\tstruct {\n\t\t\tint dmar_id;\n\t\t\tvoid *dmar_data;\n\t\t};\n\t};\n};\n\nstruct circ_buf {\n\tchar *buf;\n\tint head;\n\tint tail;\n};\n\nstruct serial_icounter_struct {\n\tint cts;\n\tint dsr;\n\tint rng;\n\tint dcd;\n\tint rx;\n\tint tx;\n\tint frame;\n\tint overrun;\n\tint parity;\n\tint brk;\n\tint buf_overrun;\n\tint reserved[9];\n};\n\nstruct serial_struct {\n\tint type;\n\tint line;\n\tunsigned int port;\n\tint irq;\n\tint flags;\n\tint xmit_fifo_size;\n\tint custom_divisor;\n\tint baud_base;\n\tshort unsigned int close_delay;\n\tchar io_type;\n\tchar reserved_char[1];\n\tint hub6;\n\tshort unsigned int closing_wait;\n\tshort unsigned int closing_wait2;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tunsigned int port_high;\n\tlong unsigned int iomap_base;\n};\n\nstruct sysrq_key_op {\n\tvoid (* const handler)(int);\n\tconst char * const help_msg;\n\tconst char * const action_msg;\n\tconst int enable_mask;\n};\n\nstruct serial_rs485 {\n\t__u32 flags;\n\t__u32 delay_rts_before_send;\n\t__u32 delay_rts_after_send;\n\t__u32 padding[5];\n};\n\nstruct serial_iso7816 {\n\t__u32 flags;\n\t__u32 tg;\n\t__u32 sc_fi;\n\t__u32 sc_di;\n\t__u32 clk;\n\t__u32 reserved[5];\n};\n\nstruct uart_port;\n\nstruct uart_ops {\n\tunsigned int (*tx_empty)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*stop_tx)(struct uart_port *);\n\tvoid (*start_tx)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tvoid (*send_xchar)(struct uart_port *, char);\n\tvoid (*stop_rx)(struct uart_port *);\n\tvoid (*enable_ms)(struct uart_port *);\n\tvoid (*break_ctl)(struct uart_port *, int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*flush_buffer)(struct uart_port *);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tconst char * (*type)(struct uart_port *);\n\tvoid (*release_port)(struct uart_port *);\n\tint (*request_port)(struct uart_port *);\n\tvoid (*config_port)(struct uart_port *, int);\n\tint (*verify_port)(struct uart_port *, struct serial_struct *);\n\tint (*ioctl)(struct uart_port *, unsigned int, long unsigned int);\n};\n\nstruct uart_icount {\n\t__u32 cts;\n\t__u32 dsr;\n\t__u32 rng;\n\t__u32 dcd;\n\t__u32 rx;\n\t__u32 tx;\n\t__u32 frame;\n\t__u32 overrun;\n\t__u32 parity;\n\t__u32 brk;\n\t__u32 buf_overrun;\n};\n\ntypedef unsigned int upf_t;\n\ntypedef unsigned int upstat_t;\n\nstruct uart_state;\n\nstruct uart_port {\n\tspinlock_t lock;\n\tlong unsigned int iobase;\n\tunsigned char *membase;\n\tunsigned int (*serial_in)(struct uart_port *, int);\n\tvoid (*serial_out)(struct uart_port *, int, int);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tvoid (*set_mctrl)(struct uart_port *, unsigned int);\n\tunsigned int (*get_divisor)(struct uart_port *, unsigned int, unsigned int *);\n\tvoid (*set_divisor)(struct uart_port *, unsigned int, unsigned int, unsigned int);\n\tint (*startup)(struct uart_port *);\n\tvoid (*shutdown)(struct uart_port *);\n\tvoid (*throttle)(struct uart_port *);\n\tvoid (*unthrottle)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n\tint (*rs485_config)(struct uart_port *, struct serial_rs485 *);\n\tint (*iso7816_config)(struct uart_port *, struct serial_iso7816 *);\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tunsigned int uartclk;\n\tunsigned int fifosize;\n\tunsigned char x_char;\n\tunsigned char regshift;\n\tunsigned char iotype;\n\tunsigned char quirks;\n\tunsigned int read_status_mask;\n\tunsigned int ignore_status_mask;\n\tstruct uart_state *state;\n\tstruct uart_icount icount;\n\tstruct console *cons;\n\tupf_t flags;\n\tupstat_t status;\n\tint hw_stopped;\n\tunsigned int mctrl;\n\tunsigned int timeout;\n\tunsigned int type;\n\tconst struct uart_ops *ops;\n\tunsigned int custom_divisor;\n\tunsigned int line;\n\tunsigned int minor;\n\tresource_size_t mapbase;\n\tresource_size_t mapsize;\n\tstruct device *dev;\n\tlong unsigned int sysrq;\n\tunsigned int sysrq_ch;\n\tunsigned char has_sysrq;\n\tunsigned char sysrq_seq;\n\tunsigned char hub6;\n\tunsigned char suspended;\n\tconst char *name;\n\tstruct attribute_group *attr_group;\n\tconst struct attribute_group **tty_groups;\n\tstruct serial_rs485 rs485;\n\tstruct gpio_desc *rs485_term_gpio;\n\tstruct serial_iso7816 iso7816;\n\tvoid *private_data;\n};\n\nenum uart_pm_state {\n\tUART_PM_STATE_ON = 0,\n\tUART_PM_STATE_OFF = 3,\n\tUART_PM_STATE_UNDEFINED = 4,\n};\n\nstruct uart_state {\n\tstruct tty_port port;\n\tenum uart_pm_state pm_state;\n\tstruct circ_buf xmit;\n\tatomic_t refcount;\n\twait_queue_head_t remove_wait;\n\tstruct uart_port *uart_port;\n};\n\nstruct earlycon_device {\n\tstruct console *con;\n\tstruct uart_port port;\n\tchar options[16];\n\tunsigned int baud;\n};\n\nstruct earlycon_id {\n\tchar name[15];\n\tchar name_term;\n\tchar compatible[128];\n\tint (*setup)(struct earlycon_device *, const char *);\n};\n\nenum ioapic_domain_type {\n\tIOAPIC_DOMAIN_INVALID = 0,\n\tIOAPIC_DOMAIN_LEGACY = 1,\n\tIOAPIC_DOMAIN_STRICT = 2,\n\tIOAPIC_DOMAIN_DYNAMIC = 3,\n};\n\nstruct ioapic_domain_cfg {\n\tenum ioapic_domain_type type;\n\tconst struct irq_domain_ops *ops;\n\tstruct device_node *dev;\n};\n\nstruct thermal_cooling_device_ops;\n\nstruct thermal_cooling_device {\n\tint id;\n\tchar type[20];\n\tstruct device device;\n\tstruct device_node *np;\n\tvoid *devdata;\n\tvoid *stats;\n\tconst struct thermal_cooling_device_ops *ops;\n\tbool updated;\n\tstruct mutex lock;\n\tstruct list_head thermal_instances;\n\tstruct list_head node;\n};\n\nenum thermal_device_mode {\n\tTHERMAL_DEVICE_DISABLED = 0,\n\tTHERMAL_DEVICE_ENABLED = 1,\n};\n\nenum thermal_trip_type {\n\tTHERMAL_TRIP_ACTIVE = 0,\n\tTHERMAL_TRIP_PASSIVE = 1,\n\tTHERMAL_TRIP_HOT = 2,\n\tTHERMAL_TRIP_CRITICAL = 3,\n};\n\nenum thermal_trend {\n\tTHERMAL_TREND_STABLE = 0,\n\tTHERMAL_TREND_RAISING = 1,\n\tTHERMAL_TREND_DROPPING = 2,\n\tTHERMAL_TREND_RAISE_FULL = 3,\n\tTHERMAL_TREND_DROP_FULL = 4,\n};\n\nenum thermal_notify_event {\n\tTHERMAL_EVENT_UNSPECIFIED = 0,\n\tTHERMAL_EVENT_TEMP_SAMPLE = 1,\n\tTHERMAL_TRIP_VIOLATED = 2,\n\tTHERMAL_TRIP_CHANGED = 3,\n\tTHERMAL_DEVICE_DOWN = 4,\n\tTHERMAL_DEVICE_UP = 5,\n\tTHERMAL_DEVICE_POWER_CAPABILITY_CHANGED = 6,\n\tTHERMAL_TABLE_CHANGED = 7,\n};\n\nstruct thermal_zone_device;\n\nstruct thermal_zone_device_ops {\n\tint (*bind)(struct thermal_zone_device *, struct thermal_cooling_device *);\n\tint (*unbind)(struct thermal_zone_device *, struct thermal_cooling_device *);\n\tint (*get_temp)(struct thermal_zone_device *, int *);\n\tint (*set_trips)(struct thermal_zone_device *, int, int);\n\tint (*get_mode)(struct thermal_zone_device *, enum thermal_device_mode *);\n\tint (*set_mode)(struct thermal_zone_device *, enum thermal_device_mode);\n\tint (*get_trip_type)(struct thermal_zone_device *, int, enum thermal_trip_type *);\n\tint (*get_trip_temp)(struct thermal_zone_device *, int, int *);\n\tint (*set_trip_temp)(struct thermal_zone_device *, int, int);\n\tint (*get_trip_hyst)(struct thermal_zone_device *, int, int *);\n\tint (*set_trip_hyst)(struct thermal_zone_device *, int, int);\n\tint (*get_crit_temp)(struct thermal_zone_device *, int *);\n\tint (*set_emul_temp)(struct thermal_zone_device *, int);\n\tint (*get_trend)(struct thermal_zone_device *, int, enum thermal_trend *);\n\tint (*notify)(struct thermal_zone_device *, int, enum thermal_trip_type);\n};\n\nstruct thermal_attr;\n\nstruct thermal_zone_params;\n\nstruct thermal_governor;\n\nstruct thermal_zone_device {\n\tint id;\n\tchar type[20];\n\tstruct device device;\n\tstruct attribute_group trips_attribute_group;\n\tstruct thermal_attr *trip_temp_attrs;\n\tstruct thermal_attr *trip_type_attrs;\n\tstruct thermal_attr *trip_hyst_attrs;\n\tvoid *devdata;\n\tint trips;\n\tlong unsigned int trips_disabled;\n\tint passive_delay;\n\tint polling_delay;\n\tint temperature;\n\tint last_temperature;\n\tint emul_temperature;\n\tint passive;\n\tint prev_low_trip;\n\tint prev_high_trip;\n\tunsigned int forced_passive;\n\tatomic_t need_update;\n\tstruct thermal_zone_device_ops *ops;\n\tstruct thermal_zone_params *tzp;\n\tstruct thermal_governor *governor;\n\tvoid *governor_data;\n\tstruct list_head thermal_instances;\n\tstruct ida ida;\n\tstruct mutex lock;\n\tstruct list_head node;\n\tstruct delayed_work poll_queue;\n\tenum thermal_notify_event notify_event;\n};\n\nstruct thermal_cooling_device_ops {\n\tint (*get_max_state)(struct thermal_cooling_device *, long unsigned int *);\n\tint (*get_cur_state)(struct thermal_cooling_device *, long unsigned int *);\n\tint (*set_cur_state)(struct thermal_cooling_device *, long unsigned int);\n\tint (*get_requested_power)(struct thermal_cooling_device *, struct thermal_zone_device *, u32 *);\n\tint (*state2power)(struct thermal_cooling_device *, struct thermal_zone_device *, long unsigned int, u32 *);\n\tint (*power2state)(struct thermal_cooling_device *, struct thermal_zone_device *, u32, long unsigned int *);\n};\n\nstruct thermal_bind_params;\n\nstruct thermal_zone_params {\n\tchar governor_name[20];\n\tbool no_hwmon;\n\tint num_tbps;\n\tstruct thermal_bind_params *tbp;\n\tu32 sustainable_power;\n\ts32 k_po;\n\ts32 k_pu;\n\ts32 k_i;\n\ts32 k_d;\n\ts32 integral_cutoff;\n\tint slope;\n\tint offset;\n};\n\nstruct thermal_governor {\n\tchar name[20];\n\tint (*bind_to_tz)(struct thermal_zone_device *);\n\tvoid (*unbind_from_tz)(struct thermal_zone_device *);\n\tint (*throttle)(struct thermal_zone_device *, int);\n\tstruct list_head governor_list;\n};\n\nstruct thermal_bind_params {\n\tstruct thermal_cooling_device *cdev;\n\tint weight;\n\tint trip_mask;\n\tlong unsigned int *binding_limits;\n\tint (*match)(struct thermal_zone_device *, struct thermal_cooling_device *);\n};\n\nstruct acpi_processor_cx {\n\tu8 valid;\n\tu8 type;\n\tu32 address;\n\tu8 entry_method;\n\tu8 index;\n\tu32 latency;\n\tu8 bm_sts_skip;\n\tchar desc[32];\n};\n\nstruct acpi_lpi_state {\n\tu32 min_residency;\n\tu32 wake_latency;\n\tu32 flags;\n\tu32 arch_flags;\n\tu32 res_cnt_freq;\n\tu32 enable_parent_state;\n\tu64 address;\n\tu8 index;\n\tu8 entry_method;\n\tchar desc[32];\n};\n\nstruct acpi_processor_power {\n\tint count;\n\tunion {\n\t\tstruct acpi_processor_cx states[8];\n\t\tstruct acpi_lpi_state lpi_states[8];\n\t};\n\tint timer_broadcast_on_state;\n};\n\nstruct acpi_psd_package {\n\tu64 num_entries;\n\tu64 revision;\n\tu64 domain;\n\tu64 coord_type;\n\tu64 num_processors;\n};\n\nstruct acpi_pct_register {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 reserved;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_processor_px {\n\tu64 core_frequency;\n\tu64 power;\n\tu64 transition_latency;\n\tu64 bus_master_latency;\n\tu64 control;\n\tu64 status;\n};\n\nstruct acpi_processor_performance {\n\tunsigned int state;\n\tunsigned int platform_limit;\n\tstruct acpi_pct_register control_register;\n\tstruct acpi_pct_register status_register;\n\tshort: 16;\n\tunsigned int state_count;\n\tint: 32;\n\tstruct acpi_processor_px *states;\n\tstruct acpi_psd_package domain_info;\n\tcpumask_var_t shared_cpu_map;\n\tunsigned int shared_type;\n\tint: 32;\n} __attribute__((packed));\n\nstruct acpi_tsd_package {\n\tu64 num_entries;\n\tu64 revision;\n\tu64 domain;\n\tu64 coord_type;\n\tu64 num_processors;\n};\n\nstruct acpi_processor_tx_tss {\n\tu64 freqpercentage;\n\tu64 power;\n\tu64 transition_latency;\n\tu64 control;\n\tu64 status;\n};\n\nstruct acpi_processor_tx {\n\tu16 power;\n\tu16 performance;\n};\n\nstruct acpi_processor;\n\nstruct acpi_processor_throttling {\n\tunsigned int state;\n\tunsigned int platform_limit;\n\tstruct acpi_pct_register control_register;\n\tstruct acpi_pct_register status_register;\n\tshort: 16;\n\tunsigned int state_count;\n\tint: 32;\n\tstruct acpi_processor_tx_tss *states_tss;\n\tstruct acpi_tsd_package domain_info;\n\tcpumask_var_t shared_cpu_map;\n\tint (*acpi_processor_get_throttling)(struct acpi_processor *);\n\tint (*acpi_processor_set_throttling)(struct acpi_processor *, int, bool);\n\tu32 address;\n\tu8 duty_offset;\n\tu8 duty_width;\n\tu8 tsd_valid_flag;\n\tchar: 8;\n\tunsigned int shared_type;\n\tstruct acpi_processor_tx states[16];\n\tint: 32;\n} __attribute__((packed));\n\nstruct acpi_processor_flags {\n\tu8 power: 1;\n\tu8 performance: 1;\n\tu8 throttling: 1;\n\tu8 limit: 1;\n\tu8 bm_control: 1;\n\tu8 bm_check: 1;\n\tu8 has_cst: 1;\n\tu8 has_lpi: 1;\n\tu8 power_setup_done: 1;\n\tu8 bm_rld_set: 1;\n\tu8 need_hotplug_init: 1;\n};\n\nstruct acpi_processor_lx {\n\tint px;\n\tint tx;\n};\n\nstruct acpi_processor_limit {\n\tstruct acpi_processor_lx state;\n\tstruct acpi_processor_lx thermal;\n\tstruct acpi_processor_lx user;\n};\n\nstruct acpi_processor {\n\tacpi_handle handle;\n\tu32 acpi_id;\n\tphys_cpuid_t phys_id;\n\tu32 id;\n\tu32 pblk;\n\tint performance_platform_limit;\n\tint throttling_platform_limit;\n\tstruct acpi_processor_flags flags;\n\tstruct acpi_processor_power power;\n\tstruct acpi_processor_performance *performance;\n\tstruct acpi_processor_throttling throttling;\n\tstruct acpi_processor_limit limit;\n\tstruct thermal_cooling_device *cdev;\n\tstruct device *dev;\n\tstruct freq_qos_request perflib_req;\n\tstruct freq_qos_request thermal_req;\n};\n\nstruct acpi_processor_errata {\n\tu8 smp;\n\tstruct {\n\t\tu8 throttle: 1;\n\t\tu8 fdma: 1;\n\t\tu8 reserved: 6;\n\t\tu32 bmisx;\n\t} piix4;\n};\n\nstruct cpuidle_driver;\n\nstruct wakeup_header {\n\tu16 video_mode;\n\tu32 pmode_entry;\n\tu16 pmode_cs;\n\tu32 pmode_cr0;\n\tu32 pmode_cr3;\n\tu32 pmode_cr4;\n\tu32 pmode_efer_low;\n\tu32 pmode_efer_high;\n\tu64 pmode_gdt;\n\tu32 pmode_misc_en_low;\n\tu32 pmode_misc_en_high;\n\tu32 pmode_behavior;\n\tu32 realmode_flags;\n\tu32 real_magic;\n\tu32 signature;\n} __attribute__((packed));\n\nstruct cpc_reg {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_width;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_power_register {\n\tu8 descriptor;\n\tu16 length;\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct cstate_entry {\n\tstruct {\n\t\tunsigned int eax;\n\t\tunsigned int ecx;\n\t} states[8];\n};\n\ntypedef void (*nmi_shootdown_cb)(int, struct pt_regs *);\n\nstruct pci_ops___2;\n\nstruct cpuid_regs_done {\n\tstruct cpuid_regs regs;\n\tstruct completion done;\n};\n\nstruct intel_early_ops {\n\tresource_size_t (*stolen_size)(int, int, int);\n\tresource_size_t (*stolen_base)(int, int, int, resource_size_t);\n};\n\nstruct chipset {\n\tu32 vendor;\n\tu32 device;\n\tu32 class;\n\tu32 class_mask;\n\tu32 flags;\n\tvoid (*f)(int, int, int);\n};\n\nstruct sched_domain_shared {\n\tatomic_t ref;\n\tatomic_t nr_busy_cpus;\n\tint has_idle_cores;\n};\n\nstruct sched_group;\n\nstruct sched_domain {\n\tstruct sched_domain *parent;\n\tstruct sched_domain *child;\n\tstruct sched_group *groups;\n\tlong unsigned int min_interval;\n\tlong unsigned int max_interval;\n\tunsigned int busy_factor;\n\tunsigned int imbalance_pct;\n\tunsigned int cache_nice_tries;\n\tint nohz_idle;\n\tint flags;\n\tint level;\n\tlong unsigned int last_balance;\n\tunsigned int balance_interval;\n\tunsigned int nr_balance_failed;\n\tu64 max_newidle_lb_cost;\n\tlong unsigned int next_decay_max_lb_cost;\n\tu64 avg_scan_cost;\n\tunsigned int lb_count[3];\n\tunsigned int lb_failed[3];\n\tunsigned int lb_balanced[3];\n\tunsigned int lb_imbalance[3];\n\tunsigned int lb_gained[3];\n\tunsigned int lb_hot_gained[3];\n\tunsigned int lb_nobusyg[3];\n\tunsigned int lb_nobusyq[3];\n\tunsigned int alb_count;\n\tunsigned int alb_failed;\n\tunsigned int alb_pushed;\n\tunsigned int sbe_count;\n\tunsigned int sbe_balanced;\n\tunsigned int sbe_pushed;\n\tunsigned int sbf_count;\n\tunsigned int sbf_balanced;\n\tunsigned int sbf_pushed;\n\tunsigned int ttwu_wake_remote;\n\tunsigned int ttwu_move_affine;\n\tunsigned int ttwu_move_balance;\n\tunion {\n\t\tvoid *private;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct sched_domain_shared *shared;\n\tunsigned int span_weight;\n\tlong unsigned int span[0];\n};\n\ntypedef const struct cpumask * (*sched_domain_mask_f)(int);\n\ntypedef int (*sched_domain_flags_f)();\n\nstruct sched_group_capacity;\n\nstruct sd_data {\n\tstruct sched_domain **sd;\n\tstruct sched_domain_shared **sds;\n\tstruct sched_group **sg;\n\tstruct sched_group_capacity **sgc;\n};\n\nstruct sched_domain_topology_level {\n\tsched_domain_mask_f mask;\n\tsched_domain_flags_f sd_flags;\n\tint flags;\n\tint numa_level;\n\tstruct sd_data data;\n};\n\nstruct tsc_adjust {\n\ts64 bootval;\n\ts64 adjusted;\n\tlong unsigned int nextcheck;\n\tbool warned;\n};\n\nenum {\n\tDUMP_PREFIX_NONE = 0,\n\tDUMP_PREFIX_ADDRESS = 1,\n\tDUMP_PREFIX_OFFSET = 2,\n};\n\nstruct mpf_intel {\n\tchar signature[4];\n\tunsigned int physptr;\n\tunsigned char length;\n\tunsigned char specification;\n\tunsigned char checksum;\n\tunsigned char feature1;\n\tunsigned char feature2;\n\tunsigned char feature3;\n\tunsigned char feature4;\n\tunsigned char feature5;\n};\n\nstruct mpc_ioapic {\n\tunsigned char type;\n\tunsigned char apicid;\n\tunsigned char apicver;\n\tunsigned char flags;\n\tunsigned int apicaddr;\n};\n\nstruct mpc_lintsrc {\n\tunsigned char type;\n\tunsigned char irqtype;\n\tshort unsigned int irqflag;\n\tunsigned char srcbusid;\n\tunsigned char srcbusirq;\n\tunsigned char destapic;\n\tunsigned char destapiclint;\n};\n\nenum page_cache_mode {\n\t_PAGE_CACHE_MODE_WB = 0,\n\t_PAGE_CACHE_MODE_WC = 1,\n\t_PAGE_CACHE_MODE_UC_MINUS = 2,\n\t_PAGE_CACHE_MODE_UC = 3,\n\t_PAGE_CACHE_MODE_WT = 4,\n\t_PAGE_CACHE_MODE_WP = 5,\n\t_PAGE_CACHE_MODE_NUM = 8,\n};\n\nunion apic_ir {\n\tlong unsigned int map[4];\n\tu32 regs[8];\n};\n\nenum ioapic_irq_destination_types {\n\tdest_Fixed = 0,\n\tdest_LowestPrio = 1,\n\tdest_SMI = 2,\n\tdest__reserved_1 = 3,\n\tdest_NMI = 4,\n\tdest_INIT = 5,\n\tdest__reserved_2 = 6,\n\tdest_ExtINT = 7,\n};\n\nenum {\n\tIRQ_SET_MASK_OK = 0,\n\tIRQ_SET_MASK_OK_NOCOPY = 1,\n\tIRQ_SET_MASK_OK_DONE = 2,\n};\n\nenum {\n\tIRQD_TRIGGER_MASK = 15,\n\tIRQD_SETAFFINITY_PENDING = 256,\n\tIRQD_ACTIVATED = 512,\n\tIRQD_NO_BALANCING = 1024,\n\tIRQD_PER_CPU = 2048,\n\tIRQD_AFFINITY_SET = 4096,\n\tIRQD_LEVEL = 8192,\n\tIRQD_WAKEUP_STATE = 16384,\n\tIRQD_MOVE_PCNTXT = 32768,\n\tIRQD_IRQ_DISABLED = 65536,\n\tIRQD_IRQ_MASKED = 131072,\n\tIRQD_IRQ_INPROGRESS = 262144,\n\tIRQD_WAKEUP_ARMED = 524288,\n\tIRQD_FORWARDED_TO_VCPU = 1048576,\n\tIRQD_AFFINITY_MANAGED = 2097152,\n\tIRQD_IRQ_STARTED = 4194304,\n\tIRQD_MANAGED_SHUTDOWN = 8388608,\n\tIRQD_SINGLE_TARGET = 16777216,\n\tIRQD_DEFAULT_TRIGGER_SET = 33554432,\n\tIRQD_CAN_RESERVE = 67108864,\n\tIRQD_MSI_NOMASK_QUIRK = 134217728,\n\tIRQD_HANDLE_ENFORCE_IRQCTX = 268435456,\n};\n\nstruct irq_cfg {\n\tunsigned int dest_apicid;\n\tunsigned int vector;\n};\n\nenum {\n\tIRQCHIP_FWNODE_REAL = 0,\n\tIRQCHIP_FWNODE_NAMED = 1,\n\tIRQCHIP_FWNODE_NAMED_ID = 2,\n};\n\nenum {\n\tX86_IRQ_ALLOC_CONTIGUOUS_VECTORS = 1,\n\tX86_IRQ_ALLOC_LEGACY = 2,\n};\n\nstruct apic_chip_data {\n\tstruct irq_cfg hw_irq_cfg;\n\tunsigned int vector;\n\tunsigned int prev_vector;\n\tunsigned int cpu;\n\tunsigned int prev_cpu;\n\tunsigned int irq;\n\tstruct hlist_node clist;\n\tunsigned int move_in_progress: 1;\n\tunsigned int is_managed: 1;\n\tunsigned int can_reserve: 1;\n\tunsigned int has_reserved: 1;\n};\n\nstruct irq_matrix;\n\nunion IO_APIC_reg_00 {\n\tu32 raw;\n\tstruct {\n\t\tu32 __reserved_2: 14;\n\t\tu32 LTS: 1;\n\t\tu32 delivery_type: 1;\n\t\tu32 __reserved_1: 8;\n\t\tu32 ID: 8;\n\t} bits;\n};\n\nunion IO_APIC_reg_01 {\n\tu32 raw;\n\tstruct {\n\t\tu32 version: 8;\n\t\tu32 __reserved_2: 7;\n\t\tu32 PRQ: 1;\n\t\tu32 entries: 8;\n\t\tu32 __reserved_1: 8;\n\t} bits;\n};\n\nunion IO_APIC_reg_02 {\n\tu32 raw;\n\tstruct {\n\t\tu32 __reserved_2: 24;\n\t\tu32 arbitration: 4;\n\t\tu32 __reserved_1: 4;\n\t} bits;\n};\n\nunion IO_APIC_reg_03 {\n\tu32 raw;\n\tstruct {\n\t\tu32 boot_DT: 1;\n\t\tu32 __reserved_1: 31;\n\t} bits;\n};\n\nstruct IR_IO_APIC_route_entry {\n\t__u64 vector: 8;\n\t__u64 zero: 3;\n\t__u64 index2: 1;\n\t__u64 delivery_status: 1;\n\t__u64 polarity: 1;\n\t__u64 irr: 1;\n\t__u64 trigger: 1;\n\t__u64 mask: 1;\n\t__u64 reserved: 31;\n\t__u64 format: 1;\n\t__u64 index: 15;\n};\n\nenum {\n\tIRQ_TYPE_NONE = 0,\n\tIRQ_TYPE_EDGE_RISING = 1,\n\tIRQ_TYPE_EDGE_FALLING = 2,\n\tIRQ_TYPE_EDGE_BOTH = 3,\n\tIRQ_TYPE_LEVEL_HIGH = 4,\n\tIRQ_TYPE_LEVEL_LOW = 8,\n\tIRQ_TYPE_LEVEL_MASK = 12,\n\tIRQ_TYPE_SENSE_MASK = 15,\n\tIRQ_TYPE_DEFAULT = 15,\n\tIRQ_TYPE_PROBE = 16,\n\tIRQ_LEVEL = 256,\n\tIRQ_PER_CPU = 512,\n\tIRQ_NOPROBE = 1024,\n\tIRQ_NOREQUEST = 2048,\n\tIRQ_NOAUTOEN = 4096,\n\tIRQ_NO_BALANCING = 8192,\n\tIRQ_MOVE_PCNTXT = 16384,\n\tIRQ_NESTED_THREAD = 32768,\n\tIRQ_NOTHREAD = 65536,\n\tIRQ_PER_CPU_DEVID = 131072,\n\tIRQ_IS_POLLED = 262144,\n\tIRQ_DISABLE_UNLAZY = 524288,\n};\n\nenum {\n\tIRQCHIP_SET_TYPE_MASKED = 1,\n\tIRQCHIP_EOI_IF_HANDLED = 2,\n\tIRQCHIP_MASK_ON_SUSPEND = 4,\n\tIRQCHIP_ONOFFLINE_ENABLED = 8,\n\tIRQCHIP_SKIP_SET_WAKE = 16,\n\tIRQCHIP_ONESHOT_SAFE = 32,\n\tIRQCHIP_EOI_THREADED = 64,\n\tIRQCHIP_SUPPORTS_LEVEL_MSI = 128,\n\tIRQCHIP_SUPPORTS_NMI = 256,\n};\n\nstruct irq_pin_list {\n\tstruct list_head list;\n\tint apic;\n\tint pin;\n};\n\nstruct mp_chip_data {\n\tstruct list_head irq_2_pin;\n\tstruct IO_APIC_route_entry entry;\n\tint trigger;\n\tint polarity;\n\tu32 count;\n\tbool isa_irq;\n};\n\nstruct mp_ioapic_gsi {\n\tu32 gsi_base;\n\tu32 gsi_end;\n};\n\nstruct ioapic {\n\tint nr_registers;\n\tstruct IO_APIC_route_entry *saved_registers;\n\tstruct mpc_ioapic mp_config;\n\tstruct mp_ioapic_gsi gsi_config;\n\tstruct ioapic_domain_cfg irqdomain_cfg;\n\tstruct irq_domain *irqdomain;\n\tstruct resource *iomem_res;\n};\n\nstruct io_apic {\n\tunsigned int index;\n\tunsigned int unused[3];\n\tunsigned int data;\n\tunsigned int unused2[11];\n\tunsigned int eoi;\n};\n\nunion entry_union {\n\tstruct {\n\t\tu32 w1;\n\t\tu32 w2;\n\t};\n\tstruct IO_APIC_route_entry entry;\n};\n\nenum {\n\tIRQ_DOMAIN_FLAG_HIERARCHY = 1,\n\tIRQ_DOMAIN_NAME_ALLOCATED = 2,\n\tIRQ_DOMAIN_FLAG_IPI_PER_CPU = 4,\n\tIRQ_DOMAIN_FLAG_IPI_SINGLE = 8,\n\tIRQ_DOMAIN_FLAG_MSI = 16,\n\tIRQ_DOMAIN_FLAG_MSI_REMAP = 32,\n\tIRQ_DOMAIN_MSI_NOMASK_QUIRK = 64,\n\tIRQ_DOMAIN_FLAG_NONCORE = 65536,\n};\n\ntypedef struct irq_alloc_info msi_alloc_info_t;\n\nstruct msi_domain_info;\n\nstruct msi_domain_ops {\n\tirq_hw_number_t (*get_hwirq)(struct msi_domain_info *, msi_alloc_info_t *);\n\tint (*msi_init)(struct irq_domain *, struct msi_domain_info *, unsigned int, irq_hw_number_t, msi_alloc_info_t *);\n\tvoid (*msi_free)(struct irq_domain *, struct msi_domain_info *, unsigned int);\n\tint (*msi_check)(struct irq_domain *, struct msi_domain_info *, struct device *);\n\tint (*msi_prepare)(struct irq_domain *, struct device *, int, msi_alloc_info_t *);\n\tvoid (*msi_finish)(msi_alloc_info_t *, int);\n\tvoid (*set_desc)(msi_alloc_info_t *, struct msi_desc *);\n\tint (*handle_error)(struct irq_domain *, struct msi_desc *, int);\n};\n\nstruct msi_domain_info {\n\tu32 flags;\n\tstruct msi_domain_ops *ops;\n\tstruct irq_chip *chip;\n\tvoid *chip_data;\n\tirq_flow_handler_t handler;\n\tvoid *handler_data;\n\tconst char *handler_name;\n\tvoid *data;\n};\n\nenum {\n\tMSI_FLAG_USE_DEF_DOM_OPS = 1,\n\tMSI_FLAG_USE_DEF_CHIP_OPS = 2,\n\tMSI_FLAG_MULTI_PCI_MSI = 4,\n\tMSI_FLAG_PCI_MSIX = 8,\n\tMSI_FLAG_ACTIVATE_EARLY = 16,\n\tMSI_FLAG_MUST_REACTIVATE = 32,\n\tMSI_FLAG_LEVEL_CAPABLE = 64,\n};\n\nstruct hpet_channel;\n\nstruct x86_mapping_info {\n\tvoid * (*alloc_pgt_page)(void *);\n\tvoid *context;\n\tlong unsigned int page_flag;\n\tlong unsigned int offset;\n\tbool direct_gbpages;\n\tlong unsigned int kernpg_flag;\n};\n\nstruct kexec_file_ops;\n\nstruct init_pgtable_data {\n\tstruct x86_mapping_info *info;\n\tpgd_t *level4p;\n};\n\nstruct kretprobe_instance;\n\ntypedef int (*kretprobe_handler_t)(struct kretprobe_instance *, struct pt_regs *);\n\nstruct kretprobe;\n\nstruct kretprobe_instance {\n\tstruct hlist_node hlist;\n\tstruct kretprobe *rp;\n\tkprobe_opcode_t *ret_addr;\n\tstruct task_struct *task;\n\tvoid *fp;\n\tchar data[0];\n};\n\nstruct kretprobe {\n\tstruct kprobe kp;\n\tkretprobe_handler_t handler;\n\tkretprobe_handler_t entry_handler;\n\tint maxactive;\n\tint nmissed;\n\tsize_t data_size;\n\tstruct hlist_head free_instances;\n\traw_spinlock_t lock;\n};\n\ntypedef struct kprobe *pto_T_____14;\n\nstruct __arch_relative_insn {\n\tu8 op;\n\ts32 raddr;\n} __attribute__((packed));\n\nstruct arch_optimized_insn {\n\tkprobe_opcode_t copied_insn[4];\n\tkprobe_opcode_t *insn;\n\tsize_t size;\n};\n\nstruct optimized_kprobe {\n\tstruct kprobe kp;\n\tstruct list_head list;\n\tstruct arch_optimized_insn optinsn;\n};\n\ntypedef __u64 Elf64_Off;\n\nstruct elf64_rela {\n\tElf64_Addr r_offset;\n\tElf64_Xword r_info;\n\tElf64_Sxword r_addend;\n};\n\ntypedef struct elf64_rela Elf64_Rela;\n\nstruct elf64_hdr {\n\tunsigned char e_ident[16];\n\tElf64_Half e_type;\n\tElf64_Half e_machine;\n\tElf64_Word e_version;\n\tElf64_Addr e_entry;\n\tElf64_Off e_phoff;\n\tElf64_Off e_shoff;\n\tElf64_Word e_flags;\n\tElf64_Half e_ehsize;\n\tElf64_Half e_phentsize;\n\tElf64_Half e_phnum;\n\tElf64_Half e_shentsize;\n\tElf64_Half e_shnum;\n\tElf64_Half e_shstrndx;\n};\n\ntypedef struct elf64_hdr Elf64_Ehdr;\n\nstruct elf64_shdr {\n\tElf64_Word sh_name;\n\tElf64_Word sh_type;\n\tElf64_Xword sh_flags;\n\tElf64_Addr sh_addr;\n\tElf64_Off sh_offset;\n\tElf64_Xword sh_size;\n\tElf64_Word sh_link;\n\tElf64_Word sh_info;\n\tElf64_Xword sh_addralign;\n\tElf64_Xword sh_entsize;\n};\n\ntypedef struct elf64_shdr Elf64_Shdr;\n\nstruct hpet_data {\n\tlong unsigned int hd_phys_address;\n\tvoid *hd_address;\n\tshort unsigned int hd_nirqs;\n\tunsigned int hd_state;\n\tunsigned int hd_irq[32];\n};\n\ntypedef irqreturn_t (*rtc_irq_handler)(int, void *);\n\nenum hpet_mode {\n\tHPET_MODE_UNUSED = 0,\n\tHPET_MODE_LEGACY = 1,\n\tHPET_MODE_CLOCKEVT = 2,\n\tHPET_MODE_DEVICE = 3,\n};\n\nstruct hpet_channel___2 {\n\tstruct clock_event_device evt;\n\tunsigned int num;\n\tunsigned int cpu;\n\tunsigned int irq;\n\tunsigned int in_use;\n\tenum hpet_mode mode;\n\tunsigned int boot_cfg;\n\tchar name[10];\n\tlong: 48;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct hpet_base {\n\tunsigned int nr_channels;\n\tunsigned int nr_clockevents;\n\tunsigned int boot_cfg;\n\tstruct hpet_channel___2 *channels;\n};\n\nunion hpet_lock {\n\tstruct {\n\t\tarch_spinlock_t lock;\n\t\tu32 value;\n\t};\n\tu64 lockval;\n};\n\nstruct amd_northbridge_info {\n\tu16 num;\n\tu64 flags;\n\tstruct amd_northbridge *nb;\n};\n\nstruct scan_area {\n\tu64 addr;\n\tu64 size;\n};\n\nstruct uprobe_xol_ops;\n\nstruct arch_uprobe {\n\tunion {\n\t\tu8 insn[16];\n\t\tu8 ixol[16];\n\t};\n\tconst struct uprobe_xol_ops *ops;\n\tunion {\n\t\tstruct {\n\t\t\ts32 offs;\n\t\t\tu8 ilen;\n\t\t\tu8 opc1;\n\t\t} branch;\n\t\tstruct {\n\t\t\tu8 fixups;\n\t\t\tu8 ilen;\n\t\t} defparam;\n\t\tstruct {\n\t\t\tu8 reg_offset;\n\t\t\tu8 ilen;\n\t\t} push;\n\t};\n};\n\nstruct uprobe_xol_ops {\n\tbool (*emulate)(struct arch_uprobe *, struct pt_regs *);\n\tint (*pre_xol)(struct arch_uprobe *, struct pt_regs *);\n\tint (*post_xol)(struct arch_uprobe *, struct pt_regs *);\n\tvoid (*abort)(struct arch_uprobe *, struct pt_regs *);\n};\n\nenum rp_check {\n\tRP_CHECK_CALL = 0,\n\tRP_CHECK_CHAIN_CALL = 1,\n\tRP_CHECK_RET = 2,\n};\n\nstruct fb_fix_screeninfo {\n\tchar id[16];\n\tlong unsigned int smem_start;\n\t__u32 smem_len;\n\t__u32 type;\n\t__u32 type_aux;\n\t__u32 visual;\n\t__u16 xpanstep;\n\t__u16 ypanstep;\n\t__u16 ywrapstep;\n\t__u32 line_length;\n\tlong unsigned int mmio_start;\n\t__u32 mmio_len;\n\t__u32 accel;\n\t__u16 capabilities;\n\t__u16 reserved[2];\n};\n\nstruct fb_bitfield {\n\t__u32 offset;\n\t__u32 length;\n\t__u32 msb_right;\n};\n\nstruct fb_var_screeninfo {\n\t__u32 xres;\n\t__u32 yres;\n\t__u32 xres_virtual;\n\t__u32 yres_virtual;\n\t__u32 xoffset;\n\t__u32 yoffset;\n\t__u32 bits_per_pixel;\n\t__u32 grayscale;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\t__u32 nonstd;\n\t__u32 activate;\n\t__u32 height;\n\t__u32 width;\n\t__u32 accel_flags;\n\t__u32 pixclock;\n\t__u32 left_margin;\n\t__u32 right_margin;\n\t__u32 upper_margin;\n\t__u32 lower_margin;\n\t__u32 hsync_len;\n\t__u32 vsync_len;\n\t__u32 sync;\n\t__u32 vmode;\n\t__u32 rotate;\n\t__u32 colorspace;\n\t__u32 reserved[4];\n};\n\nstruct fb_cmap {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_copyarea {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 sx;\n\t__u32 sy;\n};\n\nstruct fb_fillrect {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 color;\n\t__u32 rop;\n};\n\nstruct fb_image {\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 fg_color;\n\t__u32 bg_color;\n\t__u8 depth;\n\tconst char *data;\n\tstruct fb_cmap cmap;\n};\n\nstruct fbcurpos {\n\t__u16 x;\n\t__u16 y;\n};\n\nstruct fb_cursor {\n\t__u16 set;\n\t__u16 enable;\n\t__u16 rop;\n\tconst char *mask;\n\tstruct fbcurpos hot;\n\tstruct fb_image image;\n};\n\nstruct fb_chroma {\n\t__u32 redx;\n\t__u32 greenx;\n\t__u32 bluex;\n\t__u32 whitex;\n\t__u32 redy;\n\t__u32 greeny;\n\t__u32 bluey;\n\t__u32 whitey;\n};\n\nstruct fb_videomode;\n\nstruct fb_monspecs {\n\tstruct fb_chroma chroma;\n\tstruct fb_videomode *modedb;\n\t__u8 manufacturer[4];\n\t__u8 monitor[14];\n\t__u8 serial_no[14];\n\t__u8 ascii[14];\n\t__u32 modedb_len;\n\t__u32 model;\n\t__u32 serial;\n\t__u32 year;\n\t__u32 week;\n\t__u32 hfmin;\n\t__u32 hfmax;\n\t__u32 dclkmin;\n\t__u32 dclkmax;\n\t__u16 input;\n\t__u16 dpms;\n\t__u16 signal;\n\t__u16 vfmin;\n\t__u16 vfmax;\n\t__u16 gamma;\n\t__u16 gtf: 1;\n\t__u16 misc;\n\t__u8 version;\n\t__u8 revision;\n\t__u8 max_x;\n\t__u8 max_y;\n};\n\nstruct fb_info;\n\nstruct fb_pixmap {\n\tu8 *addr;\n\tu32 size;\n\tu32 offset;\n\tu32 buf_align;\n\tu32 scan_align;\n\tu32 access_align;\n\tu32 flags;\n\tu32 blit_x;\n\tu32 blit_y;\n\tvoid (*writeio)(struct fb_info *, void *, void *, unsigned int);\n\tvoid (*readio)(struct fb_info *, void *, void *, unsigned int);\n};\n\nstruct fb_deferred_io;\n\nstruct fb_ops;\n\nstruct fb_tile_ops;\n\nstruct apertures_struct;\n\nstruct fb_info {\n\tatomic_t count;\n\tint node;\n\tint flags;\n\tint fbcon_rotate_hint;\n\tstruct mutex lock;\n\tstruct mutex mm_lock;\n\tstruct fb_var_screeninfo var;\n\tstruct fb_fix_screeninfo fix;\n\tstruct fb_monspecs monspecs;\n\tstruct work_struct queue;\n\tstruct fb_pixmap pixmap;\n\tstruct fb_pixmap sprite;\n\tstruct fb_cmap cmap;\n\tstruct list_head modelist;\n\tstruct fb_videomode *mode;\n\tstruct delayed_work deferred_work;\n\tstruct fb_deferred_io *fbdefio;\n\tconst struct fb_ops *fbops;\n\tstruct device *device;\n\tstruct device *dev;\n\tint class_flag;\n\tstruct fb_tile_ops *tileops;\n\tunion {\n\t\tchar *screen_base;\n\t\tchar *screen_buffer;\n\t};\n\tlong unsigned int screen_size;\n\tvoid *pseudo_palette;\n\tu32 state;\n\tvoid *fbcon_par;\n\tvoid *par;\n\tstruct apertures_struct *apertures;\n\tbool skip_vt_switch;\n};\n\nstruct fb_videomode {\n\tconst char *name;\n\tu32 refresh;\n\tu32 xres;\n\tu32 yres;\n\tu32 pixclock;\n\tu32 left_margin;\n\tu32 right_margin;\n\tu32 upper_margin;\n\tu32 lower_margin;\n\tu32 hsync_len;\n\tu32 vsync_len;\n\tu32 sync;\n\tu32 vmode;\n\tu32 flag;\n};\n\nstruct fb_blit_caps {\n\tu32 x;\n\tu32 y;\n\tu32 len;\n\tu32 flags;\n};\n\nstruct fb_deferred_io {\n\tlong unsigned int delay;\n\tstruct mutex lock;\n\tstruct list_head pagelist;\n\tvoid (*first_io)(struct fb_info *);\n\tvoid (*deferred_io)(struct fb_info *, struct list_head *);\n};\n\nstruct fb_ops {\n\tstruct module *owner;\n\tint (*fb_open)(struct fb_info *, int);\n\tint (*fb_release)(struct fb_info *, int);\n\tssize_t (*fb_read)(struct fb_info *, char *, size_t, loff_t *);\n\tssize_t (*fb_write)(struct fb_info *, const char *, size_t, loff_t *);\n\tint (*fb_check_var)(struct fb_var_screeninfo *, struct fb_info *);\n\tint (*fb_set_par)(struct fb_info *);\n\tint (*fb_setcolreg)(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, struct fb_info *);\n\tint (*fb_setcmap)(struct fb_cmap *, struct fb_info *);\n\tint (*fb_blank)(int, struct fb_info *);\n\tint (*fb_pan_display)(struct fb_var_screeninfo *, struct fb_info *);\n\tvoid (*fb_fillrect)(struct fb_info *, const struct fb_fillrect *);\n\tvoid (*fb_copyarea)(struct fb_info *, const struct fb_copyarea *);\n\tvoid (*fb_imageblit)(struct fb_info *, const struct fb_image *);\n\tint (*fb_cursor)(struct fb_info *, struct fb_cursor *);\n\tint (*fb_sync)(struct fb_info *);\n\tint (*fb_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_compat_ioctl)(struct fb_info *, unsigned int, long unsigned int);\n\tint (*fb_mmap)(struct fb_info *, struct vm_area_struct *);\n\tvoid (*fb_get_caps)(struct fb_info *, struct fb_blit_caps *, struct fb_var_screeninfo *);\n\tvoid (*fb_destroy)(struct fb_info *);\n\tint (*fb_debug_enter)(struct fb_info *);\n\tint (*fb_debug_leave)(struct fb_info *);\n};\n\nstruct fb_tilemap {\n\t__u32 width;\n\t__u32 height;\n\t__u32 depth;\n\t__u32 length;\n\tconst __u8 *data;\n};\n\nstruct fb_tilerect {\n\t__u32 sx;\n\t__u32 sy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 index;\n\t__u32 fg;\n\t__u32 bg;\n\t__u32 rop;\n};\n\nstruct fb_tilearea {\n\t__u32 sx;\n\t__u32 sy;\n\t__u32 dx;\n\t__u32 dy;\n\t__u32 width;\n\t__u32 height;\n};\n\nstruct fb_tileblit {\n\t__u32 sx;\n\t__u32 sy;\n\t__u32 width;\n\t__u32 height;\n\t__u32 fg;\n\t__u32 bg;\n\t__u32 length;\n\t__u32 *indices;\n};\n\nstruct fb_tilecursor {\n\t__u32 sx;\n\t__u32 sy;\n\t__u32 mode;\n\t__u32 shape;\n\t__u32 fg;\n\t__u32 bg;\n};\n\nstruct fb_tile_ops {\n\tvoid (*fb_settile)(struct fb_info *, struct fb_tilemap *);\n\tvoid (*fb_tilecopy)(struct fb_info *, struct fb_tilearea *);\n\tvoid (*fb_tilefill)(struct fb_info *, struct fb_tilerect *);\n\tvoid (*fb_tileblit)(struct fb_info *, struct fb_tileblit *);\n\tvoid (*fb_tilecursor)(struct fb_info *, struct fb_tilecursor *);\n\tint (*fb_get_tilemax)(struct fb_info *);\n};\n\nstruct aperture {\n\tresource_size_t base;\n\tresource_size_t size;\n};\n\nstruct apertures_struct {\n\tunsigned int count;\n\tstruct aperture ranges[0];\n};\n\nstruct dmt_videomode {\n\tu32 dmt_id;\n\tu32 std_2byte_code;\n\tu32 cvt_3byte_code;\n\tconst struct fb_videomode *mode;\n};\n\nstruct simplefb_platform_data {\n\tu32 width;\n\tu32 height;\n\tu32 stride;\n\tconst char *format;\n};\n\nstruct efifb_dmi_info {\n\tchar *optname;\n\tlong unsigned int base;\n\tint stride;\n\tint width;\n\tint height;\n\tint flags;\n};\n\nenum {\n\tM_I17 = 0,\n\tM_I20 = 1,\n\tM_I20_SR = 2,\n\tM_I24 = 3,\n\tM_I24_8_1 = 4,\n\tM_I24_10_1 = 5,\n\tM_I27_11_1 = 6,\n\tM_MINI = 7,\n\tM_MINI_3_1 = 8,\n\tM_MINI_4_1 = 9,\n\tM_MB = 10,\n\tM_MB_2 = 11,\n\tM_MB_3 = 12,\n\tM_MB_5_1 = 13,\n\tM_MB_6_1 = 14,\n\tM_MB_7_1 = 15,\n\tM_MB_SR = 16,\n\tM_MBA = 17,\n\tM_MBA_3 = 18,\n\tM_MBP = 19,\n\tM_MBP_2 = 20,\n\tM_MBP_2_2 = 21,\n\tM_MBP_SR = 22,\n\tM_MBP_4 = 23,\n\tM_MBP_5_1 = 24,\n\tM_MBP_5_2 = 25,\n\tM_MBP_5_3 = 26,\n\tM_MBP_6_1 = 27,\n\tM_MBP_6_2 = 28,\n\tM_MBP_7_1 = 29,\n\tM_MBP_8_2 = 30,\n\tM_UNKNOWN = 31,\n};\n\nenum {\n\tOVERRIDE_NONE = 0,\n\tOVERRIDE_BASE = 1,\n\tOVERRIDE_STRIDE = 2,\n\tOVERRIDE_HEIGHT = 4,\n\tOVERRIDE_WIDTH = 8,\n};\n\nenum perf_sample_regs_abi {\n\tPERF_SAMPLE_REGS_ABI_NONE = 0,\n\tPERF_SAMPLE_REGS_ABI_32 = 1,\n\tPERF_SAMPLE_REGS_ABI_64 = 2,\n};\n\nstruct __va_list_tag {\n\tunsigned int gp_offset;\n\tunsigned int fp_offset;\n\tvoid *overflow_arg_area;\n\tvoid *reg_save_area;\n};\n\ntypedef __builtin_va_list __gnuc_va_list;\n\ntypedef __gnuc_va_list va_list;\n\nstruct va_format {\n\tconst char *fmt;\n\tva_list *va;\n};\n\nstruct pci_hostbridge_probe {\n\tu32 bus;\n\tu32 slot;\n\tu32 vendor;\n\tu32 device;\n};\n\ntypedef u8 uint8_t;\n\ntypedef u16 uint16_t;\n\nenum pg_level {\n\tPG_LEVEL_NONE = 0,\n\tPG_LEVEL_4K = 1,\n\tPG_LEVEL_2M = 2,\n\tPG_LEVEL_1G = 3,\n\tPG_LEVEL_512G = 4,\n\tPG_LEVEL_NUM = 5,\n};\n\nstruct trace_print_flags {\n\tlong unsigned int mask;\n\tconst char *name;\n};\n\nenum tlb_flush_reason {\n\tTLB_FLUSH_ON_TASK_SWITCH = 0,\n\tTLB_REMOTE_SHOOTDOWN = 1,\n\tTLB_LOCAL_SHOOTDOWN = 2,\n\tTLB_LOCAL_MM_SHOOTDOWN = 3,\n\tTLB_REMOTE_SEND_IPI = 4,\n\tNR_TLB_FLUSH_REASONS = 5,\n};\n\nenum {\n\tREGION_INTERSECTS = 0,\n\tREGION_DISJOINT = 1,\n\tREGION_MIXED = 2,\n};\n\nstruct trace_event_raw_tlb_flush {\n\tstruct trace_entry ent;\n\tint reason;\n\tlong unsigned int pages;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_tlb_flush {};\n\ntypedef void (*btf_trace_tlb_flush)(void *, int, long unsigned int);\n\nstruct map_range {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int page_size_mask;\n};\n\nenum kcore_type {\n\tKCORE_TEXT = 0,\n\tKCORE_VMALLOC = 1,\n\tKCORE_RAM = 2,\n\tKCORE_VMEMMAP = 3,\n\tKCORE_USER = 4,\n\tKCORE_OTHER = 5,\n\tKCORE_REMAP = 6,\n};\n\nstruct kcore_list {\n\tstruct list_head list;\n\tlong unsigned int addr;\n\tlong unsigned int vaddr;\n\tsize_t size;\n\tint type;\n};\n\nstruct trace_event_raw_x86_exceptions {\n\tstruct trace_entry ent;\n\tlong unsigned int address;\n\tlong unsigned int ip;\n\tlong unsigned int error_code;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_x86_exceptions {};\n\ntypedef void (*btf_trace_page_fault_user)(void *, long unsigned int, struct pt_regs *, long unsigned int);\n\ntypedef void (*btf_trace_page_fault_kernel)(void *, long unsigned int, struct pt_regs *, long unsigned int);\n\nenum {\n\tIORES_MAP_SYSTEM_RAM = 1,\n\tIORES_MAP_ENCRYPTED = 2,\n};\n\nstruct ioremap_desc {\n\tunsigned int flags;\n};\n\ntypedef bool (*ex_handler_t)(const struct exception_table_entry *, struct pt_regs *, int, long unsigned int, long unsigned int);\n\nstruct flush_tlb_info {\n\tstruct mm_struct *mm;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tu64 new_tlb_gen;\n\tunsigned int stride_shift;\n\tbool freed_tables;\n};\n\ntypedef struct mm_struct *pto_T_____15;\n\nstruct exception_stacks {\n\tchar DF_stack_guard[0];\n\tchar DF_stack[4096];\n\tchar NMI_stack_guard[0];\n\tchar NMI_stack[4096];\n\tchar DB_stack_guard[0];\n\tchar DB_stack[4096];\n\tchar MCE_stack_guard[0];\n\tchar MCE_stack[4096];\n\tchar IST_top_guard[0];\n};\n\nstruct cpa_data {\n\tlong unsigned int *vaddr;\n\tpgd_t *pgd;\n\tpgprot_t mask_set;\n\tpgprot_t mask_clr;\n\tlong unsigned int numpages;\n\tlong unsigned int curpage;\n\tlong unsigned int pfn;\n\tunsigned int flags;\n\tunsigned int force_split: 1;\n\tunsigned int force_static_prot: 1;\n\tunsigned int force_flush_all: 1;\n\tstruct page **pages;\n};\n\nenum cpa_warn {\n\tCPA_CONFLICT = 0,\n\tCPA_PROTECT = 1,\n\tCPA_DETECT = 2,\n};\n\ntypedef struct {\n\tu64 val;\n} pfn_t;\n\nstruct memtype {\n\tu64 start;\n\tu64 end;\n\tu64 subtree_max_end;\n\tenum page_cache_mode type;\n\tstruct rb_node rb;\n};\n\nenum {\n\tPAT_UC = 0,\n\tPAT_WC = 1,\n\tPAT_WT = 4,\n\tPAT_WP = 5,\n\tPAT_WB = 6,\n\tPAT_UC_MINUS = 7,\n};\n\nstruct pagerange_state {\n\tlong unsigned int cur_pfn;\n\tint ram;\n\tint not_ram;\n};\n\nstruct rb_augment_callbacks {\n\tvoid (*propagate)(struct rb_node *, struct rb_node *);\n\tvoid (*copy)(struct rb_node *, struct rb_node *);\n\tvoid (*rotate)(struct rb_node *, struct rb_node *);\n};\n\nenum {\n\tMEMTYPE_EXACT_MATCH = 0,\n\tMEMTYPE_END_MATCH = 1,\n};\n\nstruct hugepage_subpool {\n\tspinlock_t lock;\n\tlong int count;\n\tlong int max_hpages;\n\tlong int used_hpages;\n\tstruct hstate *hstate;\n\tlong int min_hpages;\n\tlong int rsv_hpages;\n};\n\nstruct hugetlbfs_sb_info {\n\tlong int max_inodes;\n\tlong int free_inodes;\n\tspinlock_t stat_lock;\n\tstruct hstate *hstate;\n\tstruct hugepage_subpool *spool;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nstruct numa_memblk {\n\tu64 start;\n\tu64 end;\n\tint nid;\n};\n\nstruct numa_meminfo {\n\tint nr_blks;\n\tstruct numa_memblk blk[128];\n};\n\nstruct acpi_srat_cpu_affinity {\n\tstruct acpi_subtable_header header;\n\tu8 proximity_domain_lo;\n\tu8 apic_id;\n\tu32 flags;\n\tu8 local_sapic_eid;\n\tu8 proximity_domain_hi[3];\n\tu32 clock_domain;\n};\n\nstruct acpi_srat_x2apic_cpu_affinity {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 proximity_domain;\n\tu32 apic_id;\n\tu32 flags;\n\tu32 clock_domain;\n\tu32 reserved2;\n};\n\nenum uv_system_type {\n\tUV_NONE = 0,\n\tUV_LEGACY_APIC = 1,\n\tUV_X2APIC = 2,\n\tUV_NON_UNIQUE_APIC = 3,\n};\n\nstruct kaslr_memory_region {\n\tlong unsigned int *base;\n\tlong unsigned int size_tb;\n};\n\nenum pti_mode {\n\tPTI_AUTO = 0,\n\tPTI_FORCE_OFF = 1,\n\tPTI_FORCE_ON = 2,\n};\n\nenum pti_clone_level {\n\tPTI_CLONE_PMD = 0,\n\tPTI_CLONE_PTE = 1,\n};\n\nstruct sigcontext_32 {\n\t__u16 gs;\n\t__u16 __gsh;\n\t__u16 fs;\n\t__u16 __fsh;\n\t__u16 es;\n\t__u16 __esh;\n\t__u16 ds;\n\t__u16 __dsh;\n\t__u32 di;\n\t__u32 si;\n\t__u32 bp;\n\t__u32 sp;\n\t__u32 bx;\n\t__u32 dx;\n\t__u32 cx;\n\t__u32 ax;\n\t__u32 trapno;\n\t__u32 err;\n\t__u32 ip;\n\t__u16 cs;\n\t__u16 __csh;\n\t__u32 flags;\n\t__u32 sp_at_signal;\n\t__u16 ss;\n\t__u16 __ssh;\n\t__u32 fpstate;\n\t__u32 oldmask;\n\t__u32 cr2;\n};\n\ntypedef u32 compat_size_t;\n\nstruct compat_sigaltstack {\n\tcompat_uptr_t ss_sp;\n\tint ss_flags;\n\tcompat_size_t ss_size;\n};\n\ntypedef struct compat_sigaltstack compat_stack_t;\n\nstruct ucontext_ia32 {\n\tunsigned int uc_flags;\n\tunsigned int uc_link;\n\tcompat_stack_t uc_stack;\n\tstruct sigcontext_32 uc_mcontext;\n\tcompat_sigset_t uc_sigmask;\n};\n\nstruct sigframe_ia32 {\n\tu32 pretcode;\n\tint sig;\n\tstruct sigcontext_32 sc;\n\tstruct _fpstate_32 fpstate_unused;\n\tunsigned int extramask[1];\n\tchar retcode[8];\n};\n\nstruct rt_sigframe_ia32 {\n\tu32 pretcode;\n\tint sig;\n\tu32 pinfo;\n\tu32 puc;\n\tcompat_siginfo_t info;\n\tstruct ucontext_ia32 uc;\n\tchar retcode[8];\n};\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu64 table;\n} efi_config_table_64_t;\n\nstruct efi_memory_map_data {\n\tphys_addr_t phys_map;\n\tlong unsigned int size;\n\tlong unsigned int desc_version;\n\tlong unsigned int desc_size;\n\tlong unsigned int flags;\n};\n\nstruct efi_mem_range {\n\tstruct range range;\n\tu64 attribute;\n};\n\nstruct efi_setup_data {\n\tu64 fw_vendor;\n\tu64 __unused;\n\tu64 tables;\n\tu64 smbios;\n\tu64 reserved[8];\n};\n\ntypedef struct {\n\tefi_guid_t guid;\n\tlong unsigned int *ptr;\n\tconst char name[16];\n} efi_config_table_type_t;\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu64 fw_vendor;\n\tu32 fw_revision;\n\tu32 __pad1;\n\tu64 con_in_handle;\n\tu64 con_in;\n\tu64 con_out_handle;\n\tu64 con_out;\n\tu64 stderr_handle;\n\tu64 stderr;\n\tu64 runtime;\n\tu64 boottime;\n\tu32 nr_tables;\n\tu32 __pad2;\n\tu64 tables;\n} efi_system_table_64_t;\n\ntypedef struct {\n\tefi_table_hdr_t hdr;\n\tu32 fw_vendor;\n\tu32 fw_revision;\n\tu32 con_in_handle;\n\tu32 con_in;\n\tu32 con_out_handle;\n\tu32 con_out;\n\tu32 stderr_handle;\n\tu32 stderr;\n\tu32 runtime;\n\tu32 boottime;\n\tu32 nr_tables;\n\tu32 tables;\n} efi_system_table_32_t;\n\ntypedef struct {\n\tu32 version;\n\tu32 length;\n\tu64 memory_protection_attribute;\n} efi_properties_table_t;\n\nunion efi_boot_services;\n\ntypedef union efi_boot_services efi_boot_services_t;\n\nunion efi_simple_text_input_protocol;\n\ntypedef union efi_simple_text_input_protocol efi_simple_text_input_protocol_t;\n\nunion efi_simple_text_output_protocol;\n\ntypedef union efi_simple_text_output_protocol efi_simple_text_output_protocol_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_table_hdr_t hdr;\n\t\tlong unsigned int fw_vendor;\n\t\tu32 fw_revision;\n\t\tlong unsigned int con_in_handle;\n\t\tefi_simple_text_input_protocol_t *con_in;\n\t\tlong unsigned int con_out_handle;\n\t\tefi_simple_text_output_protocol_t *con_out;\n\t\tlong unsigned int stderr_handle;\n\t\tlong unsigned int stderr;\n\t\tefi_runtime_services_t *runtime;\n\t\tefi_boot_services_t *boottime;\n\t\tlong unsigned int nr_tables;\n\t\tlong unsigned int tables;\n\t};\n\tefi_system_table_32_t mixed_mode;\n} efi_system_table_t;\n\nstruct wait_queue_entry;\n\ntypedef int (*wait_queue_func_t)(struct wait_queue_entry *, unsigned int, int, void *);\n\nstruct wait_queue_entry {\n\tunsigned int flags;\n\tvoid *private;\n\twait_queue_func_t func;\n\tstruct list_head entry;\n};\n\nstruct pm_qos_request {\n\tstruct plist_node node;\n\tstruct pm_qos_constraints *qos;\n};\n\nenum {\n\tBPF_REG_0 = 0,\n\tBPF_REG_1 = 1,\n\tBPF_REG_2 = 2,\n\tBPF_REG_3 = 3,\n\tBPF_REG_4 = 4,\n\tBPF_REG_5 = 5,\n\tBPF_REG_6 = 6,\n\tBPF_REG_7 = 7,\n\tBPF_REG_8 = 8,\n\tBPF_REG_9 = 9,\n\tBPF_REG_10 = 10,\n\t__MAX_BPF_REG = 11,\n};\n\nstruct bpf_tramp_progs {\n\tstruct bpf_prog *progs[40];\n\tint nr_progs;\n};\n\nenum bpf_jit_poke_reason {\n\tBPF_POKE_REASON_TAIL_CALL = 0,\n};\n\nstruct bpf_array_aux {\n\tenum bpf_prog_type type;\n\tbool jited;\n\tstruct list_head poke_progs;\n\tstruct bpf_map *map;\n\tstruct mutex poke_mutex;\n\tstruct work_struct work;\n};\n\nstruct bpf_array {\n\tstruct bpf_map map;\n\tu32 elem_size;\n\tu32 index_mask;\n\tstruct bpf_array_aux *aux;\n\tunion {\n\t\tchar value[0];\n\t\tvoid *ptrs[0];\n\t\tvoid *pptrs[0];\n\t};\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nenum bpf_text_poke_type {\n\tBPF_MOD_CALL = 0,\n\tBPF_MOD_JUMP = 1,\n};\n\nstruct bpf_binary_header {\n\tu32 pages;\n\tint: 32;\n\tu8 image[0];\n};\n\nstruct jit_context {\n\tint cleanup_addr;\n};\n\nstruct x64_jit_data {\n\tstruct bpf_binary_header *header;\n\tint *addrs;\n\tu8 *image;\n\tint proglen;\n\tstruct jit_context ctx;\n};\n\nenum tk_offsets {\n\tTK_OFFS_REAL = 0,\n\tTK_OFFS_BOOT = 1,\n\tTK_OFFS_TAI = 2,\n\tTK_OFFS_MAX = 3,\n};\n\nstruct clone_args {\n\t__u64 flags;\n\t__u64 pidfd;\n\t__u64 child_tid;\n\t__u64 parent_tid;\n\t__u64 exit_signal;\n\t__u64 stack;\n\t__u64 stack_size;\n\t__u64 tls;\n\t__u64 set_tid;\n\t__u64 set_tid_size;\n\t__u64 cgroup;\n};\n\nstruct fdtable {\n\tunsigned int max_fds;\n\tstruct file **fd;\n\tlong unsigned int *close_on_exec;\n\tlong unsigned int *open_fds;\n\tlong unsigned int *full_fds_bits;\n\tstruct callback_head rcu;\n};\n\nstruct files_struct {\n\tatomic_t count;\n\tbool resize_in_progress;\n\twait_queue_head_t resize_wait;\n\tstruct fdtable *fdt;\n\tstruct fdtable fdtab;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t file_lock;\n\tunsigned int next_fd;\n\tlong unsigned int close_on_exec_init[1];\n\tlong unsigned int open_fds_init[1];\n\tlong unsigned int full_fds_bits_init[1];\n\tstruct file *fd_array[64];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct robust_list {\n\tstruct robust_list *next;\n};\n\nstruct robust_list_head {\n\tstruct robust_list list;\n\tlong int futex_offset;\n\tstruct robust_list *list_op_pending;\n};\n\nstruct multiprocess_signals {\n\tsigset_t signal;\n\tstruct hlist_node node;\n};\n\ntypedef int (*proc_visitor)(struct task_struct *, void *);\n\nenum {\n\tIOPRIO_CLASS_NONE = 0,\n\tIOPRIO_CLASS_RT = 1,\n\tIOPRIO_CLASS_BE = 2,\n\tIOPRIO_CLASS_IDLE = 3,\n};\n\nenum memcg_stat_item {\n\tMEMCG_SWAP = 33,\n\tMEMCG_SOCK = 34,\n\tMEMCG_KERNEL_STACK_KB = 35,\n\tMEMCG_NR_STAT = 36,\n};\n\ntypedef struct poll_table_struct poll_table;\n\nenum {\n\tFUTEX_STATE_OK = 0,\n\tFUTEX_STATE_EXITING = 1,\n\tFUTEX_STATE_DEAD = 2,\n};\n\nenum proc_hidepid {\n\tHIDEPID_OFF = 0,\n\tHIDEPID_NO_ACCESS = 1,\n\tHIDEPID_INVISIBLE = 2,\n\tHIDEPID_NOT_PTRACEABLE = 4,\n};\n\nenum proc_pidonly {\n\tPROC_PIDONLY_OFF = 0,\n\tPROC_PIDONLY_ON = 1,\n};\n\nstruct proc_fs_info {\n\tstruct pid_namespace *pid_ns;\n\tstruct dentry *proc_self;\n\tstruct dentry *proc_thread_self;\n\tkgid_t pid_gid;\n\tenum proc_hidepid hide_pid;\n\tenum proc_pidonly pidonly;\n};\n\nstruct trace_event_raw_task_newtask {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tlong unsigned int clone_flags;\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_task_rename {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar oldcomm[16];\n\tchar newcomm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_task_newtask {};\n\nstruct trace_event_data_offsets_task_rename {};\n\ntypedef void (*btf_trace_task_newtask)(void *, struct task_struct *, long unsigned int);\n\ntypedef void (*btf_trace_task_rename)(void *, struct task_struct *, const char *);\n\ntypedef long unsigned int pao_T_____3;\n\nenum kmsg_dump_reason {\n\tKMSG_DUMP_UNDEF = 0,\n\tKMSG_DUMP_PANIC = 1,\n\tKMSG_DUMP_OOPS = 2,\n\tKMSG_DUMP_EMERG = 3,\n\tKMSG_DUMP_SHUTDOWN = 4,\n\tKMSG_DUMP_MAX = 5,\n};\n\nstruct vt_mode {\n\tchar mode;\n\tchar waitv;\n\tshort int relsig;\n\tshort int acqsig;\n\tshort int frsig;\n};\n\nstruct console_font {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct uni_pagedir;\n\nstruct uni_screen;\n\nstruct vc_data {\n\tstruct tty_port port;\n\tshort unsigned int vc_num;\n\tunsigned int vc_cols;\n\tunsigned int vc_rows;\n\tunsigned int vc_size_row;\n\tunsigned int vc_scan_lines;\n\tlong unsigned int vc_origin;\n\tlong unsigned int vc_scr_end;\n\tlong unsigned int vc_visible_origin;\n\tunsigned int vc_top;\n\tunsigned int vc_bottom;\n\tconst struct consw *vc_sw;\n\tshort unsigned int *vc_screenbuf;\n\tunsigned int vc_screenbuf_size;\n\tunsigned char vc_mode;\n\tunsigned char vc_attr;\n\tunsigned char vc_def_color;\n\tunsigned char vc_color;\n\tunsigned char vc_s_color;\n\tunsigned char vc_ulcolor;\n\tunsigned char vc_itcolor;\n\tunsigned char vc_halfcolor;\n\tunsigned int vc_cursor_type;\n\tshort unsigned int vc_complement_mask;\n\tshort unsigned int vc_s_complement_mask;\n\tunsigned int vc_x;\n\tunsigned int vc_y;\n\tunsigned int vc_saved_x;\n\tunsigned int vc_saved_y;\n\tlong unsigned int vc_pos;\n\tshort unsigned int vc_hi_font_mask;\n\tstruct console_font vc_font;\n\tshort unsigned int vc_video_erase_char;\n\tunsigned int vc_state;\n\tunsigned int vc_npar;\n\tunsigned int vc_par[16];\n\tstruct vt_mode vt_mode;\n\tstruct pid *vt_pid;\n\tint vt_newvt;\n\twait_queue_head_t paste_wait;\n\tunsigned int vc_charset: 1;\n\tunsigned int vc_s_charset: 1;\n\tunsigned int vc_disp_ctrl: 1;\n\tunsigned int vc_toggle_meta: 1;\n\tunsigned int vc_decscnm: 1;\n\tunsigned int vc_decom: 1;\n\tunsigned int vc_decawm: 1;\n\tunsigned int vc_deccm: 1;\n\tunsigned int vc_decim: 1;\n\tunsigned int vc_intensity: 2;\n\tunsigned int vc_italic: 1;\n\tunsigned int vc_underline: 1;\n\tunsigned int vc_blink: 1;\n\tunsigned int vc_reverse: 1;\n\tunsigned int vc_s_intensity: 2;\n\tunsigned int vc_s_italic: 1;\n\tunsigned int vc_s_underline: 1;\n\tunsigned int vc_s_blink: 1;\n\tunsigned int vc_s_reverse: 1;\n\tunsigned int vc_priv: 3;\n\tunsigned int vc_need_wrap: 1;\n\tunsigned int vc_can_do_color: 1;\n\tunsigned int vc_report_mouse: 2;\n\tunsigned char vc_utf: 1;\n\tunsigned char vc_utf_count;\n\tint vc_utf_char;\n\tunsigned int vc_tab_stop[8];\n\tunsigned char vc_palette[48];\n\tshort unsigned int *vc_translate;\n\tunsigned char vc_G0_charset;\n\tunsigned char vc_G1_charset;\n\tunsigned char vc_saved_G0;\n\tunsigned char vc_saved_G1;\n\tunsigned int vc_resize_user;\n\tunsigned int vc_bell_pitch;\n\tunsigned int vc_bell_duration;\n\tshort unsigned int vc_cur_blink_ms;\n\tstruct vc_data **vc_display_fg;\n\tstruct uni_pagedir *vc_uni_pagedir;\n\tstruct uni_pagedir **vc_uni_pagedir_loc;\n\tstruct uni_screen *vc_uni_screen;\n};\n\nstruct vc {\n\tstruct vc_data *d;\n\tstruct work_struct SAK_work;\n};\n\nstruct vt_spawn_console {\n\tspinlock_t lock;\n\tstruct pid *pid;\n\tint sig;\n};\n\nenum con_flush_mode {\n\tCONSOLE_FLUSH_PENDING = 0,\n\tCONSOLE_REPLAY_ALL = 1,\n};\n\nstruct warn_args {\n\tconst char *fmt;\n\tva_list args;\n};\n\nstruct smp_hotplug_thread {\n\tstruct task_struct **store;\n\tstruct list_head list;\n\tint (*thread_should_run)(unsigned int);\n\tvoid (*thread_fn)(unsigned int);\n\tvoid (*create)(unsigned int);\n\tvoid (*setup)(unsigned int);\n\tvoid (*cleanup)(unsigned int, bool);\n\tvoid (*park)(unsigned int);\n\tvoid (*unpark)(unsigned int);\n\tbool selfparking;\n\tconst char *thread_comm;\n};\n\nstruct trace_event_raw_cpuhp_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_multi_enter {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint target;\n\tint idx;\n\tvoid *fun;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpuhp_exit {\n\tstruct trace_entry ent;\n\tunsigned int cpu;\n\tint state;\n\tint idx;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_cpuhp_enter {};\n\nstruct trace_event_data_offsets_cpuhp_multi_enter {};\n\nstruct trace_event_data_offsets_cpuhp_exit {};\n\ntypedef void (*btf_trace_cpuhp_enter)(void *, unsigned int, int, int, int (*)(unsigned int));\n\ntypedef void (*btf_trace_cpuhp_multi_enter)(void *, unsigned int, int, int, int (*)(unsigned int, struct hlist_node *), struct hlist_node *);\n\ntypedef void (*btf_trace_cpuhp_exit)(void *, unsigned int, int, int, int);\n\nstruct cpuhp_cpu_state {\n\tenum cpuhp_state state;\n\tenum cpuhp_state target;\n\tenum cpuhp_state fail;\n\tstruct task_struct *thread;\n\tbool should_run;\n\tbool rollback;\n\tbool single;\n\tbool bringup;\n\tstruct hlist_node *node;\n\tstruct hlist_node *last;\n\tenum cpuhp_state cb_state;\n\tint result;\n\tstruct completion done_up;\n\tstruct completion done_down;\n};\n\nstruct cpuhp_step {\n\tconst char *name;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} startup;\n\tunion {\n\t\tint (*single)(unsigned int);\n\t\tint (*multi)(unsigned int, struct hlist_node *);\n\t} teardown;\n\tstruct hlist_head list;\n\tbool cant_stop;\n\tbool multi_instance;\n};\n\nenum cpu_mitigations {\n\tCPU_MITIGATIONS_OFF = 0,\n\tCPU_MITIGATIONS_AUTO = 1,\n\tCPU_MITIGATIONS_AUTO_NOSMT = 2,\n};\n\ntypedef enum cpuhp_state pto_T_____16;\n\nstruct __kernel_old_timeval {\n\t__kernel_long_t tv_sec;\n\t__kernel_long_t tv_usec;\n};\n\ntypedef struct wait_queue_entry wait_queue_entry_t;\n\nstruct old_timeval32 {\n\told_time32_t tv_sec;\n\ts32 tv_usec;\n};\n\nstruct rusage {\n\tstruct __kernel_old_timeval ru_utime;\n\tstruct __kernel_old_timeval ru_stime;\n\t__kernel_long_t ru_maxrss;\n\t__kernel_long_t ru_ixrss;\n\t__kernel_long_t ru_idrss;\n\t__kernel_long_t ru_isrss;\n\t__kernel_long_t ru_minflt;\n\t__kernel_long_t ru_majflt;\n\t__kernel_long_t ru_nswap;\n\t__kernel_long_t ru_inblock;\n\t__kernel_long_t ru_oublock;\n\t__kernel_long_t ru_msgsnd;\n\t__kernel_long_t ru_msgrcv;\n\t__kernel_long_t ru_nsignals;\n\t__kernel_long_t ru_nvcsw;\n\t__kernel_long_t ru_nivcsw;\n};\n\nstruct fd {\n\tstruct file *file;\n\tunsigned int flags;\n};\n\nstruct compat_rusage {\n\tstruct old_timeval32 ru_utime;\n\tstruct old_timeval32 ru_stime;\n\tcompat_long_t ru_maxrss;\n\tcompat_long_t ru_ixrss;\n\tcompat_long_t ru_idrss;\n\tcompat_long_t ru_isrss;\n\tcompat_long_t ru_minflt;\n\tcompat_long_t ru_majflt;\n\tcompat_long_t ru_nswap;\n\tcompat_long_t ru_inblock;\n\tcompat_long_t ru_oublock;\n\tcompat_long_t ru_msgsnd;\n\tcompat_long_t ru_msgrcv;\n\tcompat_long_t ru_nsignals;\n\tcompat_long_t ru_nvcsw;\n\tcompat_long_t ru_nivcsw;\n};\n\nstruct waitid_info {\n\tpid_t pid;\n\tuid_t uid;\n\tint status;\n\tint cause;\n};\n\nstruct wait_opts {\n\tenum pid_type wo_type;\n\tint wo_flags;\n\tstruct pid *wo_pid;\n\tstruct waitid_info *wo_info;\n\tint wo_stat;\n\tstruct rusage *wo_rusage;\n\twait_queue_entry_t child_wait;\n\tint notask_error;\n};\n\nstruct softirq_action {\n\tvoid (*action)(struct softirq_action *);\n};\n\nstruct tasklet_struct {\n\tstruct tasklet_struct *next;\n\tlong unsigned int state;\n\tatomic_t count;\n\tvoid (*func)(long unsigned int);\n\tlong unsigned int data;\n};\n\nenum {\n\tTASKLET_STATE_SCHED = 0,\n\tTASKLET_STATE_RUN = 1,\n};\n\nstruct trace_event_raw_irq_handler_entry {\n\tstruct trace_entry ent;\n\tint irq;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_handler_exit {\n\tstruct trace_entry ent;\n\tint irq;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_softirq {\n\tstruct trace_entry ent;\n\tunsigned int vec;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_irq_handler_entry {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_irq_handler_exit {};\n\nstruct trace_event_data_offsets_softirq {};\n\ntypedef void (*btf_trace_irq_handler_entry)(void *, int, struct irqaction *);\n\ntypedef void (*btf_trace_irq_handler_exit)(void *, int, struct irqaction *, int);\n\ntypedef void (*btf_trace_softirq_entry)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_exit)(void *, unsigned int);\n\ntypedef void (*btf_trace_softirq_raise)(void *, unsigned int);\n\nstruct tasklet_head {\n\tstruct tasklet_struct *head;\n\tstruct tasklet_struct **tail;\n};\n\ntypedef struct tasklet_struct **pto_T_____17;\n\nstruct resource_entry {\n\tstruct list_head node;\n\tstruct resource *res;\n\tresource_size_t offset;\n\tstruct resource __res;\n};\n\nstruct resource_constraint {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_size_t (*alignf)(void *, const struct resource *, resource_size_t, resource_size_t);\n\tvoid *alignf_data;\n};\n\nenum {\n\tMAX_IORES_LEVEL = 5,\n};\n\nstruct region_devres {\n\tstruct resource *parent;\n\tresource_size_t start;\n\tresource_size_t n;\n};\n\nenum sysctl_writes_mode {\n\tSYSCTL_WRITES_LEGACY = 4294967295,\n\tSYSCTL_WRITES_WARN = 0,\n\tSYSCTL_WRITES_STRICT = 1,\n};\n\nstruct do_proc_dointvec_minmax_conv_param {\n\tint *min;\n\tint *max;\n};\n\nstruct do_proc_douintvec_minmax_conv_param {\n\tunsigned int *min;\n\tunsigned int *max;\n};\n\nstruct __sysctl_args {\n\tint *name;\n\tint nlen;\n\tvoid *oldval;\n\tsize_t *oldlenp;\n\tvoid *newval;\n\tsize_t newlen;\n\tlong unsigned int __unused[4];\n};\n\nenum {\n\tCTL_KERN = 1,\n\tCTL_VM = 2,\n\tCTL_NET = 3,\n\tCTL_PROC = 4,\n\tCTL_FS = 5,\n\tCTL_DEBUG = 6,\n\tCTL_DEV = 7,\n\tCTL_BUS = 8,\n\tCTL_ABI = 9,\n\tCTL_CPU = 10,\n\tCTL_ARLAN = 254,\n\tCTL_S390DBF = 5677,\n\tCTL_SUNRPC = 7249,\n\tCTL_PM = 9899,\n\tCTL_FRV = 9898,\n};\n\nenum {\n\tKERN_OSTYPE = 1,\n\tKERN_OSRELEASE = 2,\n\tKERN_OSREV = 3,\n\tKERN_VERSION = 4,\n\tKERN_SECUREMASK = 5,\n\tKERN_PROF = 6,\n\tKERN_NODENAME = 7,\n\tKERN_DOMAINNAME = 8,\n\tKERN_PANIC = 15,\n\tKERN_REALROOTDEV = 16,\n\tKERN_SPARC_REBOOT = 21,\n\tKERN_CTLALTDEL = 22,\n\tKERN_PRINTK = 23,\n\tKERN_NAMETRANS = 24,\n\tKERN_PPC_HTABRECLAIM = 25,\n\tKERN_PPC_ZEROPAGED = 26,\n\tKERN_PPC_POWERSAVE_NAP = 27,\n\tKERN_MODPROBE = 28,\n\tKERN_SG_BIG_BUFF = 29,\n\tKERN_ACCT = 30,\n\tKERN_PPC_L2CR = 31,\n\tKERN_RTSIGNR = 32,\n\tKERN_RTSIGMAX = 33,\n\tKERN_SHMMAX = 34,\n\tKERN_MSGMAX = 35,\n\tKERN_MSGMNB = 36,\n\tKERN_MSGPOOL = 37,\n\tKERN_SYSRQ = 38,\n\tKERN_MAX_THREADS = 39,\n\tKERN_RANDOM = 40,\n\tKERN_SHMALL = 41,\n\tKERN_MSGMNI = 42,\n\tKERN_SEM = 43,\n\tKERN_SPARC_STOP_A = 44,\n\tKERN_SHMMNI = 45,\n\tKERN_OVERFLOWUID = 46,\n\tKERN_OVERFLOWGID = 47,\n\tKERN_SHMPATH = 48,\n\tKERN_HOTPLUG = 49,\n\tKERN_IEEE_EMULATION_WARNINGS = 50,\n\tKERN_S390_USER_DEBUG_LOGGING = 51,\n\tKERN_CORE_USES_PID = 52,\n\tKERN_TAINTED = 53,\n\tKERN_CADPID = 54,\n\tKERN_PIDMAX = 55,\n\tKERN_CORE_PATTERN = 56,\n\tKERN_PANIC_ON_OOPS = 57,\n\tKERN_HPPA_PWRSW = 58,\n\tKERN_HPPA_UNALIGNED = 59,\n\tKERN_PRINTK_RATELIMIT = 60,\n\tKERN_PRINTK_RATELIMIT_BURST = 61,\n\tKERN_PTY = 62,\n\tKERN_NGROUPS_MAX = 63,\n\tKERN_SPARC_SCONS_PWROFF = 64,\n\tKERN_HZ_TIMER = 65,\n\tKERN_UNKNOWN_NMI_PANIC = 66,\n\tKERN_BOOTLOADER_TYPE = 67,\n\tKERN_RANDOMIZE = 68,\n\tKERN_SETUID_DUMPABLE = 69,\n\tKERN_SPIN_RETRY = 70,\n\tKERN_ACPI_VIDEO_FLAGS = 71,\n\tKERN_IA64_UNALIGNED = 72,\n\tKERN_COMPAT_LOG = 73,\n\tKERN_MAX_LOCK_DEPTH = 74,\n\tKERN_NMI_WATCHDOG = 75,\n\tKERN_PANIC_ON_NMI = 76,\n\tKERN_PANIC_ON_WARN = 77,\n\tKERN_PANIC_PRINT = 78,\n};\n\nstruct xfs_sysctl_val {\n\tint min;\n\tint val;\n\tint max;\n};\n\ntypedef struct xfs_sysctl_val xfs_sysctl_val_t;\n\nstruct xfs_param {\n\txfs_sysctl_val_t sgid_inherit;\n\txfs_sysctl_val_t symlink_mode;\n\txfs_sysctl_val_t panic_mask;\n\txfs_sysctl_val_t error_level;\n\txfs_sysctl_val_t syncd_timer;\n\txfs_sysctl_val_t stats_clear;\n\txfs_sysctl_val_t inherit_sync;\n\txfs_sysctl_val_t inherit_nodump;\n\txfs_sysctl_val_t inherit_noatim;\n\txfs_sysctl_val_t xfs_buf_timer;\n\txfs_sysctl_val_t xfs_buf_age;\n\txfs_sysctl_val_t inherit_nosym;\n\txfs_sysctl_val_t rotorstep;\n\txfs_sysctl_val_t inherit_nodfrg;\n\txfs_sysctl_val_t fstrm_timer;\n\txfs_sysctl_val_t eofb_timer;\n\txfs_sysctl_val_t cowb_timer;\n};\n\ntypedef struct xfs_param xfs_param_t;\n\nstruct xfs_globals {\n\tint log_recovery_delay;\n\tint mount_delay;\n\tbool bug_on_assert;\n\tbool always_cow;\n};\n\nenum ethtool_link_mode_bit_indices {\n\tETHTOOL_LINK_MODE_10baseT_Half_BIT = 0,\n\tETHTOOL_LINK_MODE_10baseT_Full_BIT = 1,\n\tETHTOOL_LINK_MODE_100baseT_Half_BIT = 2,\n\tETHTOOL_LINK_MODE_100baseT_Full_BIT = 3,\n\tETHTOOL_LINK_MODE_1000baseT_Half_BIT = 4,\n\tETHTOOL_LINK_MODE_1000baseT_Full_BIT = 5,\n\tETHTOOL_LINK_MODE_Autoneg_BIT = 6,\n\tETHTOOL_LINK_MODE_TP_BIT = 7,\n\tETHTOOL_LINK_MODE_AUI_BIT = 8,\n\tETHTOOL_LINK_MODE_MII_BIT = 9,\n\tETHTOOL_LINK_MODE_FIBRE_BIT = 10,\n\tETHTOOL_LINK_MODE_BNC_BIT = 11,\n\tETHTOOL_LINK_MODE_10000baseT_Full_BIT = 12,\n\tETHTOOL_LINK_MODE_Pause_BIT = 13,\n\tETHTOOL_LINK_MODE_Asym_Pause_BIT = 14,\n\tETHTOOL_LINK_MODE_2500baseX_Full_BIT = 15,\n\tETHTOOL_LINK_MODE_Backplane_BIT = 16,\n\tETHTOOL_LINK_MODE_1000baseKX_Full_BIT = 17,\n\tETHTOOL_LINK_MODE_10000baseKX4_Full_BIT = 18,\n\tETHTOOL_LINK_MODE_10000baseKR_Full_BIT = 19,\n\tETHTOOL_LINK_MODE_10000baseR_FEC_BIT = 20,\n\tETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT = 21,\n\tETHTOOL_LINK_MODE_20000baseKR2_Full_BIT = 22,\n\tETHTOOL_LINK_MODE_40000baseKR4_Full_BIT = 23,\n\tETHTOOL_LINK_MODE_40000baseCR4_Full_BIT = 24,\n\tETHTOOL_LINK_MODE_40000baseSR4_Full_BIT = 25,\n\tETHTOOL_LINK_MODE_40000baseLR4_Full_BIT = 26,\n\tETHTOOL_LINK_MODE_56000baseKR4_Full_BIT = 27,\n\tETHTOOL_LINK_MODE_56000baseCR4_Full_BIT = 28,\n\tETHTOOL_LINK_MODE_56000baseSR4_Full_BIT = 29,\n\tETHTOOL_LINK_MODE_56000baseLR4_Full_BIT = 30,\n\tETHTOOL_LINK_MODE_25000baseCR_Full_BIT = 31,\n\tETHTOOL_LINK_MODE_25000baseKR_Full_BIT = 32,\n\tETHTOOL_LINK_MODE_25000baseSR_Full_BIT = 33,\n\tETHTOOL_LINK_MODE_50000baseCR2_Full_BIT = 34,\n\tETHTOOL_LINK_MODE_50000baseKR2_Full_BIT = 35,\n\tETHTOOL_LINK_MODE_100000baseKR4_Full_BIT = 36,\n\tETHTOOL_LINK_MODE_100000baseSR4_Full_BIT = 37,\n\tETHTOOL_LINK_MODE_100000baseCR4_Full_BIT = 38,\n\tETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT = 39,\n\tETHTOOL_LINK_MODE_50000baseSR2_Full_BIT = 40,\n\tETHTOOL_LINK_MODE_1000baseX_Full_BIT = 41,\n\tETHTOOL_LINK_MODE_10000baseCR_Full_BIT = 42,\n\tETHTOOL_LINK_MODE_10000baseSR_Full_BIT = 43,\n\tETHTOOL_LINK_MODE_10000baseLR_Full_BIT = 44,\n\tETHTOOL_LINK_MODE_10000baseLRM_Full_BIT = 45,\n\tETHTOOL_LINK_MODE_10000baseER_Full_BIT = 46,\n\tETHTOOL_LINK_MODE_2500baseT_Full_BIT = 47,\n\tETHTOOL_LINK_MODE_5000baseT_Full_BIT = 48,\n\tETHTOOL_LINK_MODE_FEC_NONE_BIT = 49,\n\tETHTOOL_LINK_MODE_FEC_RS_BIT = 50,\n\tETHTOOL_LINK_MODE_FEC_BASER_BIT = 51,\n\tETHTOOL_LINK_MODE_50000baseKR_Full_BIT = 52,\n\tETHTOOL_LINK_MODE_50000baseSR_Full_BIT = 53,\n\tETHTOOL_LINK_MODE_50000baseCR_Full_BIT = 54,\n\tETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT = 55,\n\tETHTOOL_LINK_MODE_50000baseDR_Full_BIT = 56,\n\tETHTOOL_LINK_MODE_100000baseKR2_Full_BIT = 57,\n\tETHTOOL_LINK_MODE_100000baseSR2_Full_BIT = 58,\n\tETHTOOL_LINK_MODE_100000baseCR2_Full_BIT = 59,\n\tETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT = 60,\n\tETHTOOL_LINK_MODE_100000baseDR2_Full_BIT = 61,\n\tETHTOOL_LINK_MODE_200000baseKR4_Full_BIT = 62,\n\tETHTOOL_LINK_MODE_200000baseSR4_Full_BIT = 63,\n\tETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64,\n\tETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65,\n\tETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66,\n\tETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67,\n\tETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68,\n\tETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69,\n\tETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70,\n\tETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,\n\tETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72,\n\tETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73,\n\tETHTOOL_LINK_MODE_FEC_LLRS_BIT = 74,\n\t__ETHTOOL_LINK_MODE_MASK_NBITS = 75,\n};\n\nenum {\n\tNAPI_STATE_SCHED = 0,\n\tNAPI_STATE_MISSED = 1,\n\tNAPI_STATE_DISABLE = 2,\n\tNAPI_STATE_NPSVC = 3,\n\tNAPI_STATE_HASHED = 4,\n\tNAPI_STATE_NO_BUSY_POLL = 5,\n\tNAPI_STATE_IN_BUSY_POLL = 6,\n};\n\nenum {\n\tNETIF_MSG_DRV_BIT = 0,\n\tNETIF_MSG_PROBE_BIT = 1,\n\tNETIF_MSG_LINK_BIT = 2,\n\tNETIF_MSG_TIMER_BIT = 3,\n\tNETIF_MSG_IFDOWN_BIT = 4,\n\tNETIF_MSG_IFUP_BIT = 5,\n\tNETIF_MSG_RX_ERR_BIT = 6,\n\tNETIF_MSG_TX_ERR_BIT = 7,\n\tNETIF_MSG_TX_QUEUED_BIT = 8,\n\tNETIF_MSG_INTR_BIT = 9,\n\tNETIF_MSG_TX_DONE_BIT = 10,\n\tNETIF_MSG_RX_STATUS_BIT = 11,\n\tNETIF_MSG_PKTDATA_BIT = 12,\n\tNETIF_MSG_HW_BIT = 13,\n\tNETIF_MSG_WOL_BIT = 14,\n\tNETIF_MSG_CLASS_COUNT = 15,\n};\n\nstruct compat_sysctl_args {\n\tcompat_uptr_t name;\n\tint nlen;\n\tcompat_uptr_t oldval;\n\tcompat_uptr_t oldlenp;\n\tcompat_uptr_t newval;\n\tcompat_size_t newlen;\n\tcompat_ulong_t __unused[4];\n};\n\nstruct __user_cap_header_struct {\n\t__u32 version;\n\tint pid;\n};\n\ntypedef struct __user_cap_header_struct *cap_user_header_t;\n\nstruct __user_cap_data_struct {\n\t__u32 effective;\n\t__u32 permitted;\n\t__u32 inheritable;\n};\n\ntypedef struct __user_cap_data_struct *cap_user_data_t;\n\nstruct sigqueue {\n\tstruct list_head list;\n\tint flags;\n\tkernel_siginfo_t info;\n\tstruct user_struct *user;\n};\n\nstruct ptrace_peeksiginfo_args {\n\t__u64 off;\n\t__u32 flags;\n\t__s32 nr;\n};\n\nstruct ptrace_syscall_info {\n\t__u8 op;\n\t__u32 arch;\n\t__u64 instruction_pointer;\n\t__u64 stack_pointer;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t} entry;\n\t\tstruct {\n\t\t\t__s64 rval;\n\t\t\t__u8 is_error;\n\t\t} exit;\n\t\tstruct {\n\t\t\t__u64 nr;\n\t\t\t__u64 args[6];\n\t\t\t__u32 ret_data;\n\t\t} seccomp;\n\t};\n};\n\nstruct compat_iovec {\n\tcompat_uptr_t iov_base;\n\tcompat_size_t iov_len;\n};\n\ntypedef long unsigned int old_sigset_t;\n\nenum siginfo_layout {\n\tSIL_KILL = 0,\n\tSIL_TIMER = 1,\n\tSIL_POLL = 2,\n\tSIL_FAULT = 3,\n\tSIL_FAULT_MCEERR = 4,\n\tSIL_FAULT_BNDERR = 5,\n\tSIL_FAULT_PKUERR = 6,\n\tSIL_CHLD = 7,\n\tSIL_RT = 8,\n\tSIL_SYS = 9,\n};\n\ntypedef u32 compat_old_sigset_t;\n\nstruct compat_sigaction {\n\tcompat_uptr_t sa_handler;\n\tcompat_ulong_t sa_flags;\n\tcompat_uptr_t sa_restorer;\n\tcompat_sigset_t sa_mask;\n};\n\nstruct compat_old_sigaction {\n\tcompat_uptr_t sa_handler;\n\tcompat_old_sigset_t sa_mask;\n\tcompat_ulong_t sa_flags;\n\tcompat_uptr_t sa_restorer;\n};\n\nenum {\n\tTRACE_SIGNAL_DELIVERED = 0,\n\tTRACE_SIGNAL_IGNORED = 1,\n\tTRACE_SIGNAL_ALREADY_PENDING = 2,\n\tTRACE_SIGNAL_OVERFLOW_FAIL = 3,\n\tTRACE_SIGNAL_LOSE_INFO = 4,\n};\n\nstruct trace_event_raw_signal_generate {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tchar comm[16];\n\tpid_t pid;\n\tint group;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_signal_deliver {\n\tstruct trace_entry ent;\n\tint sig;\n\tint errno;\n\tint code;\n\tlong unsigned int sa_handler;\n\tlong unsigned int sa_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_signal_generate {};\n\nstruct trace_event_data_offsets_signal_deliver {};\n\ntypedef void (*btf_trace_signal_generate)(void *, int, struct kernel_siginfo *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_signal_deliver)(void *, int, struct kernel_siginfo *, struct k_sigaction *);\n\ntypedef __kernel_clock_t clock_t;\n\nstruct sysinfo {\n\t__kernel_long_t uptime;\n\t__kernel_ulong_t loads[3];\n\t__kernel_ulong_t totalram;\n\t__kernel_ulong_t freeram;\n\t__kernel_ulong_t sharedram;\n\t__kernel_ulong_t bufferram;\n\t__kernel_ulong_t totalswap;\n\t__kernel_ulong_t freeswap;\n\t__u16 procs;\n\t__u16 pad;\n\t__kernel_ulong_t totalhigh;\n\t__kernel_ulong_t freehigh;\n\t__u32 mem_unit;\n\tchar _f[0];\n};\n\nenum {\n\tPER_LINUX = 0,\n\tPER_LINUX_32BIT = 8388608,\n\tPER_LINUX_FDPIC = 524288,\n\tPER_SVR4 = 68157441,\n\tPER_SVR3 = 83886082,\n\tPER_SCOSVR3 = 117440515,\n\tPER_OSR5 = 100663299,\n\tPER_WYSEV386 = 83886084,\n\tPER_ISCR4 = 67108869,\n\tPER_BSD = 6,\n\tPER_SUNOS = 67108870,\n\tPER_XENIX = 83886087,\n\tPER_LINUX32 = 8,\n\tPER_LINUX32_3GB = 134217736,\n\tPER_IRIX32 = 67108873,\n\tPER_IRIXN32 = 67108874,\n\tPER_IRIX64 = 67108875,\n\tPER_RISCOS = 12,\n\tPER_SOLARIS = 67108877,\n\tPER_UW7 = 68157454,\n\tPER_OSF4 = 15,\n\tPER_HPUX = 16,\n\tPER_MASK = 255,\n};\n\nstruct rlimit64 {\n\t__u64 rlim_cur;\n\t__u64 rlim_max;\n};\n\nstruct oldold_utsname {\n\tchar sysname[9];\n\tchar nodename[9];\n\tchar release[9];\n\tchar version[9];\n\tchar machine[9];\n};\n\nstruct old_utsname {\n\tchar sysname[65];\n\tchar nodename[65];\n\tchar release[65];\n\tchar version[65];\n\tchar machine[65];\n};\n\nenum uts_proc {\n\tUTS_PROC_OSTYPE = 0,\n\tUTS_PROC_OSRELEASE = 1,\n\tUTS_PROC_VERSION = 2,\n\tUTS_PROC_HOSTNAME = 3,\n\tUTS_PROC_DOMAINNAME = 4,\n};\n\nstruct prctl_mm_map {\n\t__u64 start_code;\n\t__u64 end_code;\n\t__u64 start_data;\n\t__u64 end_data;\n\t__u64 start_brk;\n\t__u64 brk;\n\t__u64 start_stack;\n\t__u64 arg_start;\n\t__u64 arg_end;\n\t__u64 env_start;\n\t__u64 env_end;\n\t__u64 *auxv;\n\t__u32 auxv_size;\n\t__u32 exe_fd;\n};\n\nstruct tms {\n\t__kernel_clock_t tms_utime;\n\t__kernel_clock_t tms_stime;\n\t__kernel_clock_t tms_cutime;\n\t__kernel_clock_t tms_cstime;\n};\n\nstruct getcpu_cache {\n\tlong unsigned int blob[16];\n};\n\nstruct compat_tms {\n\tcompat_clock_t tms_utime;\n\tcompat_clock_t tms_stime;\n\tcompat_clock_t tms_cutime;\n\tcompat_clock_t tms_cstime;\n};\n\nstruct compat_rlimit {\n\tcompat_ulong_t rlim_cur;\n\tcompat_ulong_t rlim_max;\n};\n\nstruct compat_sysinfo {\n\ts32 uptime;\n\tu32 loads[3];\n\tu32 totalram;\n\tu32 freeram;\n\tu32 sharedram;\n\tu32 bufferram;\n\tu32 totalswap;\n\tu32 freeswap;\n\tu16 procs;\n\tu16 pad;\n\tu32 totalhigh;\n\tu32 freehigh;\n\tu32 mem_unit;\n\tchar _f[8];\n};\n\nstruct umh_info {\n\tconst char *cmdline;\n\tstruct file *pipe_to_umh;\n\tstruct file *pipe_from_umh;\n\tstruct list_head list;\n\tvoid (*cleanup)(struct umh_info *);\n\tpid_t pid;\n};\n\nstruct wq_flusher;\n\nstruct worker;\n\nstruct workqueue_attrs;\n\nstruct pool_workqueue;\n\nstruct wq_device;\n\nstruct workqueue_struct {\n\tstruct list_head pwqs;\n\tstruct list_head list;\n\tstruct mutex mutex;\n\tint work_color;\n\tint flush_color;\n\tatomic_t nr_pwqs_to_flush;\n\tstruct wq_flusher *first_flusher;\n\tstruct list_head flusher_queue;\n\tstruct list_head flusher_overflow;\n\tstruct list_head maydays;\n\tstruct worker *rescuer;\n\tint nr_drainers;\n\tint saved_max_active;\n\tstruct workqueue_attrs *unbound_attrs;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct wq_device *wq_dev;\n\tchar name[24];\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunsigned int flags;\n\tstruct pool_workqueue *cpu_pwqs;\n\tstruct pool_workqueue *numa_pwq_tbl[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct workqueue_attrs {\n\tint nice;\n\tcpumask_var_t cpumask;\n\tbool no_numa;\n};\n\nstruct execute_work {\n\tstruct work_struct work;\n};\n\nenum {\n\tWQ_UNBOUND = 2,\n\tWQ_FREEZABLE = 4,\n\tWQ_MEM_RECLAIM = 8,\n\tWQ_HIGHPRI = 16,\n\tWQ_CPU_INTENSIVE = 32,\n\tWQ_SYSFS = 64,\n\tWQ_POWER_EFFICIENT = 128,\n\t__WQ_DRAINING = 65536,\n\t__WQ_ORDERED = 131072,\n\t__WQ_LEGACY = 262144,\n\t__WQ_ORDERED_EXPLICIT = 524288,\n\tWQ_MAX_ACTIVE = 512,\n\tWQ_MAX_UNBOUND_PER_CPU = 4,\n\tWQ_DFL_ACTIVE = 256,\n};\n\ntypedef unsigned int xa_mark_t;\n\nenum xa_lock_type {\n\tXA_LOCK_IRQ = 1,\n\tXA_LOCK_BH = 2,\n};\n\nstruct __una_u32 {\n\tu32 x;\n};\n\nstruct worker_pool;\n\nstruct worker {\n\tunion {\n\t\tstruct list_head entry;\n\t\tstruct hlist_node hentry;\n\t};\n\tstruct work_struct *current_work;\n\twork_func_t current_func;\n\tstruct pool_workqueue *current_pwq;\n\tstruct list_head scheduled;\n\tstruct task_struct *task;\n\tstruct worker_pool *pool;\n\tstruct list_head node;\n\tlong unsigned int last_active;\n\tunsigned int flags;\n\tint id;\n\tint sleeping;\n\tchar desc[24];\n\tstruct workqueue_struct *rescue_wq;\n\twork_func_t last_func;\n};\n\nstruct pool_workqueue {\n\tstruct worker_pool *pool;\n\tstruct workqueue_struct *wq;\n\tint work_color;\n\tint flush_color;\n\tint refcnt;\n\tint nr_in_flight[15];\n\tint nr_active;\n\tint max_active;\n\tstruct list_head delayed_works;\n\tstruct list_head pwqs_node;\n\tstruct list_head mayday_node;\n\tstruct work_struct unbound_release_work;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct worker_pool {\n\traw_spinlock_t lock;\n\tint cpu;\n\tint node;\n\tint id;\n\tunsigned int flags;\n\tlong unsigned int watchdog_ts;\n\tstruct list_head worklist;\n\tint nr_workers;\n\tint nr_idle;\n\tstruct list_head idle_list;\n\tstruct timer_list idle_timer;\n\tstruct timer_list mayday_timer;\n\tstruct hlist_head busy_hash[64];\n\tstruct worker *manager;\n\tstruct list_head workers;\n\tstruct completion *detach_completion;\n\tstruct ida worker_ida;\n\tstruct workqueue_attrs *attrs;\n\tstruct hlist_node hash_node;\n\tint refcnt;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_t nr_running;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nenum {\n\tPOOL_MANAGER_ACTIVE = 1,\n\tPOOL_DISASSOCIATED = 4,\n\tWORKER_DIE = 2,\n\tWORKER_IDLE = 4,\n\tWORKER_PREP = 8,\n\tWORKER_CPU_INTENSIVE = 64,\n\tWORKER_UNBOUND = 128,\n\tWORKER_REBOUND = 256,\n\tWORKER_NOT_RUNNING = 456,\n\tNR_STD_WORKER_POOLS = 2,\n\tUNBOUND_POOL_HASH_ORDER = 6,\n\tBUSY_WORKER_HASH_ORDER = 6,\n\tMAX_IDLE_WORKERS_RATIO = 4,\n\tIDLE_WORKER_TIMEOUT = 300000,\n\tMAYDAY_INITIAL_TIMEOUT = 10,\n\tMAYDAY_INTERVAL = 100,\n\tCREATE_COOLDOWN = 1000,\n\tRESCUER_NICE_LEVEL = 4294967276,\n\tHIGHPRI_NICE_LEVEL = 4294967276,\n\tWQ_NAME_LEN = 24,\n};\n\nstruct wq_flusher {\n\tstruct list_head list;\n\tint flush_color;\n\tstruct completion done;\n};\n\nstruct wq_device {\n\tstruct workqueue_struct *wq;\n\tstruct device dev;\n};\n\nstruct trace_event_raw_workqueue_queue_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tvoid *workqueue;\n\tunsigned int req_cpu;\n\tunsigned int cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_activate_work {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_start {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_workqueue_execute_end {\n\tstruct trace_entry ent;\n\tvoid *work;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_workqueue_queue_work {};\n\nstruct trace_event_data_offsets_workqueue_activate_work {};\n\nstruct trace_event_data_offsets_workqueue_execute_start {};\n\nstruct trace_event_data_offsets_workqueue_execute_end {};\n\ntypedef void (*btf_trace_workqueue_queue_work)(void *, unsigned int, struct pool_workqueue *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_activate_work)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_execute_start)(void *, struct work_struct *);\n\ntypedef void (*btf_trace_workqueue_execute_end)(void *, struct work_struct *, work_func_t);\n\nstruct wq_barrier {\n\tstruct work_struct work;\n\tstruct completion done;\n\tstruct task_struct *task;\n};\n\nstruct cwt_wait {\n\twait_queue_entry_t wait;\n\tstruct work_struct *work;\n};\n\nstruct apply_wqattrs_ctx {\n\tstruct workqueue_struct *wq;\n\tstruct workqueue_attrs *attrs;\n\tstruct list_head list;\n\tstruct pool_workqueue *dfl_pwq;\n\tstruct pool_workqueue *pwq_tbl[0];\n};\n\nstruct work_for_cpu {\n\tstruct work_struct work;\n\tlong int (*fn)(void *);\n\tvoid *arg;\n\tlong int ret;\n};\n\ntypedef void (*task_work_func_t)(struct callback_head *);\n\nenum {\n\tKERNEL_PARAM_OPS_FL_NOARG = 1,\n};\n\nenum {\n\tKERNEL_PARAM_FL_UNSAFE = 1,\n\tKERNEL_PARAM_FL_HWPARAM = 2,\n};\n\nstruct param_attribute {\n\tstruct module_attribute mattr;\n\tconst struct kernel_param *param;\n};\n\nstruct module_param_attrs {\n\tunsigned int num;\n\tstruct attribute_group grp;\n\tstruct param_attribute attrs[0];\n};\n\nstruct module_version_attribute {\n\tstruct module_attribute mattr;\n\tconst char *module_name;\n\tconst char *version;\n};\n\nstruct kmalloced_param {\n\tstruct list_head list;\n\tchar val[0];\n};\n\nstruct sched_param {\n\tint sched_priority;\n};\n\nstruct kthread_work;\n\ntypedef void (*kthread_work_func_t)(struct kthread_work *);\n\nstruct kthread_worker;\n\nstruct kthread_work {\n\tstruct list_head node;\n\tkthread_work_func_t func;\n\tstruct kthread_worker *worker;\n\tint canceling;\n};\n\nenum {\n\tKTW_FREEZABLE = 1,\n};\n\nstruct kthread_worker {\n\tunsigned int flags;\n\traw_spinlock_t lock;\n\tstruct list_head work_list;\n\tstruct list_head delayed_work_list;\n\tstruct task_struct *task;\n\tstruct kthread_work *current_work;\n};\n\nstruct kthread_delayed_work {\n\tstruct kthread_work work;\n\tstruct timer_list timer;\n};\n\nstruct kthread_create_info {\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tint node;\n\tstruct task_struct *result;\n\tstruct completion *done;\n\tstruct list_head list;\n};\n\nstruct kthread {\n\tlong unsigned int flags;\n\tunsigned int cpu;\n\tint (*threadfn)(void *);\n\tvoid *data;\n\tmm_segment_t oldfs;\n\tstruct completion parked;\n\tstruct completion exited;\n};\n\nenum KTHREAD_BITS {\n\tKTHREAD_IS_PER_CPU = 0,\n\tKTHREAD_SHOULD_STOP = 1,\n\tKTHREAD_SHOULD_PARK = 2,\n};\n\nstruct kthread_flush_work {\n\tstruct kthread_work work;\n\tstruct completion done;\n};\n\nstruct pt_regs___2;\n\nstruct ipc_ids {\n\tint in_use;\n\tshort unsigned int seq;\n\tstruct rw_semaphore rwsem;\n\tstruct idr ipcs_idr;\n\tint max_idx;\n\tint last_idx;\n\tstruct rhashtable key_ht;\n};\n\nstruct ipc_namespace {\n\trefcount_t count;\n\tstruct ipc_ids ids[3];\n\tint sem_ctls[4];\n\tint used_sems;\n\tunsigned int msg_ctlmax;\n\tunsigned int msg_ctlmnb;\n\tunsigned int msg_ctlmni;\n\tatomic_t msg_bytes;\n\tatomic_t msg_hdrs;\n\tsize_t shm_ctlmax;\n\tsize_t shm_ctlall;\n\tlong unsigned int shm_tot;\n\tint shm_ctlmni;\n\tint shm_rmid_forced;\n\tstruct notifier_block ipcns_nb;\n\tstruct vfsmount *mq_mnt;\n\tunsigned int mq_queues_count;\n\tunsigned int mq_queues_max;\n\tunsigned int mq_msg_max;\n\tunsigned int mq_msgsize_max;\n\tunsigned int mq_msg_default;\n\tunsigned int mq_msgsize_default;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tstruct llist_node mnt_llist;\n\tstruct ns_common ns;\n};\n\nstruct srcu_notifier_head {\n\tstruct mutex mutex;\n\tstruct srcu_struct srcu;\n\tstruct notifier_block *head;\n};\n\nenum what {\n\tPROC_EVENT_NONE = 0,\n\tPROC_EVENT_FORK = 1,\n\tPROC_EVENT_EXEC = 2,\n\tPROC_EVENT_UID = 4,\n\tPROC_EVENT_GID = 64,\n\tPROC_EVENT_SID = 128,\n\tPROC_EVENT_PTRACE = 256,\n\tPROC_EVENT_COMM = 512,\n\tPROC_EVENT_COREDUMP = 1073741824,\n\tPROC_EVENT_EXIT = 2147483648,\n};\n\ntypedef u64 async_cookie_t;\n\ntypedef void (*async_func_t)(void *, async_cookie_t);\n\nstruct async_domain {\n\tstruct list_head pending;\n\tunsigned int registered: 1;\n};\n\nstruct async_entry {\n\tstruct list_head domain_list;\n\tstruct list_head global_list;\n\tstruct work_struct work;\n\tasync_cookie_t cookie;\n\tasync_func_t func;\n\tvoid *data;\n\tstruct async_domain *domain;\n};\n\nstruct smpboot_thread_data {\n\tunsigned int cpu;\n\tunsigned int status;\n\tstruct smp_hotplug_thread *ht;\n};\n\nenum {\n\tHP_THREAD_NONE = 0,\n\tHP_THREAD_ACTIVE = 1,\n\tHP_THREAD_PARKED = 2,\n};\n\nstruct pin_cookie {};\n\nenum {\n\tCSD_FLAG_LOCK = 1,\n\tIRQ_WORK_PENDING = 1,\n\tIRQ_WORK_BUSY = 2,\n\tIRQ_WORK_LAZY = 4,\n\tIRQ_WORK_HARD_IRQ = 8,\n\tIRQ_WORK_CLAIMED = 3,\n\tCSD_TYPE_ASYNC = 0,\n\tCSD_TYPE_SYNC = 16,\n\tCSD_TYPE_IRQ_WORK = 32,\n\tCSD_TYPE_TTWU = 48,\n\tCSD_FLAG_TYPE_MASK = 240,\n};\n\nstruct dl_bw {\n\traw_spinlock_t lock;\n\tu64 bw;\n\tu64 total_bw;\n};\n\nstruct cpudl_item;\n\nstruct cpudl {\n\traw_spinlock_t lock;\n\tint size;\n\tcpumask_var_t free_cpus;\n\tstruct cpudl_item *elements;\n};\n\nstruct cpupri_vec {\n\tatomic_t count;\n\tcpumask_var_t mask;\n};\n\nstruct cpupri {\n\tstruct cpupri_vec pri_to_cpu[102];\n\tint *cpu_to_pri;\n};\n\nstruct perf_domain;\n\nstruct root_domain___2 {\n\tatomic_t refcount;\n\tatomic_t rto_count;\n\tstruct callback_head rcu;\n\tcpumask_var_t span;\n\tcpumask_var_t online;\n\tint overload;\n\tint overutilized;\n\tcpumask_var_t dlo_mask;\n\tatomic_t dlo_count;\n\tstruct dl_bw dl_bw;\n\tstruct cpudl cpudl;\n\tstruct irq_work rto_push_work;\n\traw_spinlock_t rto_lock;\n\tint rto_loop;\n\tint rto_cpu;\n\tatomic_t rto_loop_next;\n\tatomic_t rto_loop_start;\n\tcpumask_var_t rto_mask;\n\tstruct cpupri cpupri;\n\tlong unsigned int max_cpu_capacity;\n\tstruct perf_domain *pd;\n};\n\nstruct cfs_rq {\n\tstruct load_weight load;\n\tunsigned int nr_running;\n\tunsigned int h_nr_running;\n\tunsigned int idle_h_nr_running;\n\tu64 exec_clock;\n\tu64 min_vruntime;\n\tstruct rb_root_cached tasks_timeline;\n\tstruct sched_entity *curr;\n\tstruct sched_entity *next;\n\tstruct sched_entity *last;\n\tstruct sched_entity *skip;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg;\n\tstruct {\n\t\traw_spinlock_t lock;\n\t\tint nr;\n\t\tlong unsigned int load_avg;\n\t\tlong unsigned int util_avg;\n\t\tlong unsigned int runnable_avg;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t} removed;\n\tlong unsigned int tg_load_avg_contrib;\n\tlong int propagate;\n\tlong int prop_runnable_sum;\n\tlong unsigned int h_load;\n\tu64 last_h_load_update;\n\tstruct sched_entity *h_load_next;\n\tstruct rq *rq;\n\tint on_list;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct task_group *tg;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct cfs_bandwidth {};\n\nstruct task_group {\n\tstruct cgroup_subsys_state css;\n\tstruct sched_entity **se;\n\tstruct cfs_rq **cfs_rq;\n\tlong unsigned int shares;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tatomic_long_t load_avg;\n\tstruct callback_head rcu;\n\tstruct list_head list;\n\tstruct task_group *parent;\n\tstruct list_head siblings;\n\tstruct list_head children;\n\tstruct cfs_bandwidth cfs_bandwidth;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct update_util_data {\n\tvoid (*func)(struct update_util_data *, u64, unsigned int);\n};\n\nenum {\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_READY = 1,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED = 2,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED_READY = 4,\n\tMEMBARRIER_STATE_GLOBAL_EXPEDITED = 8,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY = 16,\n\tMEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n};\n\nstruct sched_group {\n\tstruct sched_group *next;\n\tatomic_t ref;\n\tunsigned int group_weight;\n\tstruct sched_group_capacity *sgc;\n\tint asym_prefer_cpu;\n\tlong unsigned int cpumask[0];\n};\n\nstruct sched_group_capacity {\n\tatomic_t ref;\n\tlong unsigned int capacity;\n\tlong unsigned int min_capacity;\n\tlong unsigned int max_capacity;\n\tlong unsigned int next_update;\n\tint imbalance;\n\tlong unsigned int cpumask[0];\n};\n\nstruct wake_q_head {\n\tstruct wake_q_node *first;\n\tstruct wake_q_node **lastp;\n};\n\nstruct sched_attr {\n\t__u32 size;\n\t__u32 sched_policy;\n\t__u64 sched_flags;\n\t__s32 sched_nice;\n\t__u32 sched_priority;\n\t__u64 sched_runtime;\n\t__u64 sched_deadline;\n\t__u64 sched_period;\n\t__u32 sched_util_min;\n\t__u32 sched_util_max;\n};\n\nstruct cpuidle_driver___2;\n\nstruct cpuidle_state {\n\tchar name[16];\n\tchar desc[32];\n\tu64 exit_latency_ns;\n\tu64 target_residency_ns;\n\tunsigned int flags;\n\tunsigned int exit_latency;\n\tint power_usage;\n\tunsigned int target_residency;\n\tint (*enter)(struct cpuidle_device *, struct cpuidle_driver___2 *, int);\n\tint (*enter_dead)(struct cpuidle_device *, int);\n\tvoid (*enter_s2idle)(struct cpuidle_device *, struct cpuidle_driver___2 *, int);\n};\n\nstruct cpuidle_driver___2 {\n\tconst char *name;\n\tstruct module *owner;\n\tunsigned int bctimer: 1;\n\tstruct cpuidle_state states[10];\n\tint state_count;\n\tint safe_state_index;\n\tstruct cpumask *cpumask;\n\tconst char *governor;\n};\n\nstruct em_cap_state {\n\tlong unsigned int frequency;\n\tlong unsigned int power;\n\tlong unsigned int cost;\n};\n\nstruct em_perf_domain {\n\tstruct em_cap_state *table;\n\tint nr_cap_states;\n\tlong unsigned int cpus[0];\n};\n\nenum {\n\tCFTYPE_ONLY_ON_ROOT = 1,\n\tCFTYPE_NOT_ON_ROOT = 2,\n\tCFTYPE_NS_DELEGATABLE = 4,\n\tCFTYPE_NO_PREFIX = 8,\n\tCFTYPE_WORLD_WRITABLE = 16,\n\tCFTYPE_DEBUG = 32,\n\t__CFTYPE_ONLY_ON_DFL = 65536,\n\t__CFTYPE_NOT_ON_DFL = 131072,\n};\n\ntypedef int (*cpu_stop_fn_t)(void *);\n\nstruct cpu_stop_done;\n\nstruct cpu_stop_work {\n\tstruct list_head list;\n\tcpu_stop_fn_t fn;\n\tvoid *arg;\n\tstruct cpu_stop_done *done;\n};\n\nstruct cpudl_item {\n\tu64 dl;\n\tint cpu;\n\tint idx;\n};\n\nstruct rt_prio_array {\n\tlong unsigned int bitmap[2];\n\tstruct list_head queue[100];\n};\n\nstruct rt_bandwidth {\n\traw_spinlock_t rt_runtime_lock;\n\tktime_t rt_period;\n\tu64 rt_runtime;\n\tstruct hrtimer rt_period_timer;\n\tunsigned int rt_period_active;\n};\n\nstruct dl_bandwidth {\n\traw_spinlock_t dl_runtime_lock;\n\tu64 dl_runtime;\n\tu64 dl_period;\n};\n\ntypedef int (*tg_visitor)(struct task_group *, void *);\n\nstruct rt_rq {\n\tstruct rt_prio_array active;\n\tunsigned int rt_nr_running;\n\tunsigned int rr_nr_running;\n\tstruct {\n\t\tint curr;\n\t\tint next;\n\t} highest_prio;\n\tlong unsigned int rt_nr_migratory;\n\tlong unsigned int rt_nr_total;\n\tint overloaded;\n\tstruct plist_head pushable_tasks;\n\tint rt_queued;\n\tint rt_throttled;\n\tu64 rt_time;\n\tu64 rt_runtime;\n\traw_spinlock_t rt_runtime_lock;\n};\n\nstruct dl_rq {\n\tstruct rb_root_cached root;\n\tlong unsigned int dl_nr_running;\n\tstruct {\n\t\tu64 curr;\n\t\tu64 next;\n\t} earliest_dl;\n\tlong unsigned int dl_nr_migratory;\n\tint overloaded;\n\tstruct rb_root_cached pushable_dl_tasks_root;\n\tu64 running_bw;\n\tu64 this_bw;\n\tu64 extra_bw;\n\tu64 bw_ratio;\n};\n\nstruct rq {\n\traw_spinlock_t lock;\n\tunsigned int nr_running;\n\tlong unsigned int last_blocked_load_update_tick;\n\tunsigned int has_blocked_load;\n\tlong: 32;\n\tlong: 64;\n\tcall_single_data_t nohz_csd;\n\tunsigned int nohz_tick_stopped;\n\tatomic_t nohz_flags;\n\tunsigned int ttwu_pending;\n\tu64 nr_switches;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct cfs_rq cfs;\n\tstruct rt_rq rt;\n\tstruct dl_rq dl;\n\tstruct list_head leaf_cfs_rq_list;\n\tstruct list_head *tmp_alone_branch;\n\tlong unsigned int nr_uninterruptible;\n\tstruct task_struct *curr;\n\tstruct task_struct *idle;\n\tstruct task_struct *stop;\n\tlong unsigned int next_balance;\n\tstruct mm_struct *prev_mm;\n\tunsigned int clock_update_flags;\n\tu64 clock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu64 clock_task;\n\tu64 clock_pelt;\n\tlong unsigned int lost_idle_time;\n\tatomic_t nr_iowait;\n\tint membarrier_state;\n\tstruct root_domain___2 *rd;\n\tstruct sched_domain *sd;\n\tlong unsigned int cpu_capacity;\n\tlong unsigned int cpu_capacity_orig;\n\tstruct callback_head *balance_callback;\n\tunsigned char nohz_idle_balance;\n\tunsigned char idle_balance;\n\tlong unsigned int misfit_task_load;\n\tint active_balance;\n\tint push_cpu;\n\tstruct cpu_stop_work active_balance_work;\n\tint cpu;\n\tint online;\n\tstruct list_head cfs_tasks;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sched_avg avg_rt;\n\tstruct sched_avg avg_dl;\n\tu64 idle_stamp;\n\tu64 avg_idle;\n\tu64 max_idle_balance_cost;\n\tlong unsigned int calc_load_update;\n\tlong int calc_load_active;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tcall_single_data_t hrtick_csd;\n\tstruct hrtimer hrtick_timer;\n\tstruct sched_info rq_sched_info;\n\tlong long unsigned int rq_cpu_time;\n\tunsigned int yld_count;\n\tunsigned int sched_count;\n\tunsigned int sched_goidle;\n\tunsigned int ttwu_count;\n\tunsigned int ttwu_local;\n\tstruct cpuidle_state *idle_state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct perf_domain {\n\tstruct em_perf_domain *em_pd;\n\tstruct perf_domain *next;\n\tstruct callback_head rcu;\n};\n\nstruct rq_flags {\n\tlong unsigned int flags;\n\tstruct pin_cookie cookie;\n};\n\nenum numa_topology_type {\n\tNUMA_DIRECT = 0,\n\tNUMA_GLUELESS_MESH = 1,\n\tNUMA_BACKPLANE = 2,\n};\n\nenum {\n\t__SCHED_FEAT_GENTLE_FAIR_SLEEPERS = 0,\n\t__SCHED_FEAT_START_DEBIT = 1,\n\t__SCHED_FEAT_NEXT_BUDDY = 2,\n\t__SCHED_FEAT_LAST_BUDDY = 3,\n\t__SCHED_FEAT_CACHE_HOT_BUDDY = 4,\n\t__SCHED_FEAT_WAKEUP_PREEMPTION = 5,\n\t__SCHED_FEAT_HRTICK = 6,\n\t__SCHED_FEAT_DOUBLE_TICK = 7,\n\t__SCHED_FEAT_NONTASK_CAPACITY = 8,\n\t__SCHED_FEAT_TTWU_QUEUE = 9,\n\t__SCHED_FEAT_SIS_AVG_CPU = 10,\n\t__SCHED_FEAT_SIS_PROP = 11,\n\t__SCHED_FEAT_WARN_DOUBLE_CLOCK = 12,\n\t__SCHED_FEAT_RT_PUSH_IPI = 13,\n\t__SCHED_FEAT_RT_RUNTIME_SHARE = 14,\n\t__SCHED_FEAT_LB_MIN = 15,\n\t__SCHED_FEAT_ATTACH_AGE_LOAD = 16,\n\t__SCHED_FEAT_WA_IDLE = 17,\n\t__SCHED_FEAT_WA_WEIGHT = 18,\n\t__SCHED_FEAT_WA_BIAS = 19,\n\t__SCHED_FEAT_UTIL_EST = 20,\n\t__SCHED_FEAT_UTIL_EST_FASTUP = 21,\n\t__SCHED_FEAT_NR = 22,\n};\n\nstruct trace_event_raw_sched_kthread_stop {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_kthread_stop_ret {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wakeup_template {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tint success;\n\tint target_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_switch {\n\tstruct trace_entry ent;\n\tchar prev_comm[16];\n\tpid_t prev_pid;\n\tint prev_prio;\n\tlong int prev_state;\n\tchar next_comm[16];\n\tpid_t next_pid;\n\tint next_prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_migrate_task {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tint orig_cpu;\n\tint dest_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_template {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_wait {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_fork {\n\tstruct trace_entry ent;\n\tchar parent_comm[16];\n\tpid_t parent_pid;\n\tchar child_comm[16];\n\tpid_t child_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_process_exec {\n\tstruct trace_entry ent;\n\tu32 __data_loc_filename;\n\tpid_t pid;\n\tpid_t old_pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_stat_template {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tu64 delay;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_stat_runtime {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tu64 runtime;\n\tu64 vruntime;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_pi_setprio {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tpid_t pid;\n\tint oldprio;\n\tint newprio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_move_numa {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tpid_t tgid;\n\tpid_t ngid;\n\tint src_cpu;\n\tint src_nid;\n\tint dst_cpu;\n\tint dst_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_numa_pair_template {\n\tstruct trace_entry ent;\n\tpid_t src_pid;\n\tpid_t src_tgid;\n\tpid_t src_ngid;\n\tint src_cpu;\n\tint src_nid;\n\tpid_t dst_pid;\n\tpid_t dst_tgid;\n\tpid_t dst_ngid;\n\tint dst_cpu;\n\tint dst_nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sched_wake_idle_without_ipi {\n\tstruct trace_entry ent;\n\tint cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_sched_kthread_stop {};\n\nstruct trace_event_data_offsets_sched_kthread_stop_ret {};\n\nstruct trace_event_data_offsets_sched_wakeup_template {};\n\nstruct trace_event_data_offsets_sched_switch {};\n\nstruct trace_event_data_offsets_sched_migrate_task {};\n\nstruct trace_event_data_offsets_sched_process_template {};\n\nstruct trace_event_data_offsets_sched_process_wait {};\n\nstruct trace_event_data_offsets_sched_process_fork {};\n\nstruct trace_event_data_offsets_sched_process_exec {\n\tu32 filename;\n};\n\nstruct trace_event_data_offsets_sched_stat_template {};\n\nstruct trace_event_data_offsets_sched_stat_runtime {};\n\nstruct trace_event_data_offsets_sched_pi_setprio {};\n\nstruct trace_event_data_offsets_sched_move_numa {};\n\nstruct trace_event_data_offsets_sched_numa_pair_template {};\n\nstruct trace_event_data_offsets_sched_wake_idle_without_ipi {};\n\ntypedef void (*btf_trace_sched_kthread_stop)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_kthread_stop_ret)(void *, int);\n\ntypedef void (*btf_trace_sched_waking)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wakeup)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wakeup_new)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_switch)(void *, bool, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_migrate_task)(void *, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_process_free)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_exit)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_wait_task)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_wait)(void *, struct pid *);\n\ntypedef void (*btf_trace_sched_process_fork)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_process_exec)(void *, struct task_struct *, pid_t, struct linux_binprm *);\n\ntypedef void (*btf_trace_sched_stat_wait)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_sleep)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_iowait)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_blocked)(void *, struct task_struct *, u64);\n\ntypedef void (*btf_trace_sched_stat_runtime)(void *, struct task_struct *, u64, u64);\n\ntypedef void (*btf_trace_sched_pi_setprio)(void *, struct task_struct *, struct task_struct *);\n\ntypedef void (*btf_trace_sched_move_numa)(void *, struct task_struct *, int, int);\n\ntypedef void (*btf_trace_sched_stick_numa)(void *, struct task_struct *, int, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_swap_numa)(void *, struct task_struct *, int, struct task_struct *, int);\n\ntypedef void (*btf_trace_sched_wake_idle_without_ipi)(void *, int);\n\nstruct migration_arg {\n\tstruct task_struct *task;\n\tint dest_cpu;\n};\n\nenum {\n\tcpuset = 0,\n\tpossible = 1,\n\tfail = 2,\n};\n\nenum tick_dep_bits {\n\tTICK_DEP_BIT_POSIX_TIMER = 0,\n\tTICK_DEP_BIT_PERF_EVENTS = 1,\n\tTICK_DEP_BIT_SCHED = 2,\n\tTICK_DEP_BIT_CLOCK_UNSTABLE = 3,\n\tTICK_DEP_BIT_RCU = 4,\n\tTICK_DEP_BIT_RCU_EXP = 5,\n};\n\nstruct sched_clock_data {\n\tu64 tick_raw;\n\tu64 tick_gtod;\n\tu64 clock;\n};\n\ntypedef u64 pao_T_____4;\n\nstruct idle_timer {\n\tstruct hrtimer timer;\n\tint done;\n};\n\nenum schedutil_type {\n\tFREQUENCY_UTIL = 0,\n\tENERGY_UTIL = 1,\n};\n\nenum fbq_type {\n\tregular = 0,\n\tremote = 1,\n\tall = 2,\n};\n\nenum group_type {\n\tgroup_has_spare = 0,\n\tgroup_fully_busy = 1,\n\tgroup_misfit_task = 2,\n\tgroup_asym_packing = 3,\n\tgroup_imbalanced = 4,\n\tgroup_overloaded = 5,\n};\n\nenum migration_type {\n\tmigrate_load = 0,\n\tmigrate_util = 1,\n\tmigrate_task = 2,\n\tmigrate_misfit = 3,\n};\n\nstruct lb_env {\n\tstruct sched_domain *sd;\n\tstruct rq *src_rq;\n\tint src_cpu;\n\tint dst_cpu;\n\tstruct rq *dst_rq;\n\tstruct cpumask *dst_grpmask;\n\tint new_dst_cpu;\n\tenum cpu_idle_type idle;\n\tlong int imbalance;\n\tstruct cpumask *cpus;\n\tunsigned int flags;\n\tunsigned int loop;\n\tunsigned int loop_break;\n\tunsigned int loop_max;\n\tenum fbq_type fbq_type;\n\tenum migration_type migration_type;\n\tstruct list_head tasks;\n};\n\nstruct sg_lb_stats {\n\tlong unsigned int avg_load;\n\tlong unsigned int group_load;\n\tlong unsigned int group_capacity;\n\tlong unsigned int group_util;\n\tlong unsigned int group_runnable;\n\tunsigned int sum_nr_running;\n\tunsigned int sum_h_nr_running;\n\tunsigned int idle_cpus;\n\tunsigned int group_weight;\n\tenum group_type group_type;\n\tunsigned int group_asym_packing;\n\tlong unsigned int group_misfit_task_load;\n};\n\nstruct sd_lb_stats {\n\tstruct sched_group *busiest;\n\tstruct sched_group *local;\n\tlong unsigned int total_load;\n\tlong unsigned int total_capacity;\n\tlong unsigned int avg_load;\n\tunsigned int prefer_sibling;\n\tstruct sg_lb_stats busiest_stat;\n\tstruct sg_lb_stats local_stat;\n};\n\ntypedef struct rt_rq *rt_rq_iter_t;\n\nstruct wait_bit_key {\n\tvoid *flags;\n\tint bit_nr;\n\tlong unsigned int timeout;\n};\n\nstruct wait_bit_queue_entry {\n\tstruct wait_bit_key key;\n\tstruct wait_queue_entry wq_entry;\n};\n\ntypedef int wait_bit_action_f(struct wait_bit_key *, int);\n\nstruct swait_queue {\n\tstruct task_struct *task;\n\tstruct list_head task_list;\n};\n\nstruct sched_domain_attr {\n\tint relax_domain_level;\n};\n\nstruct s_data {\n\tstruct sched_domain **sd;\n\tstruct root_domain___2 *rd;\n};\n\nenum s_alloc {\n\tsa_rootdomain = 0,\n\tsa_sd = 1,\n\tsa_sd_storage = 2,\n\tsa_none = 3,\n};\n\nenum cpuacct_stat_index {\n\tCPUACCT_STAT_USER = 0,\n\tCPUACCT_STAT_SYSTEM = 1,\n\tCPUACCT_STAT_NSTATS = 2,\n};\n\nstruct cpuacct_usage {\n\tu64 usages[2];\n};\n\nstruct cpuacct {\n\tstruct cgroup_subsys_state css;\n\tstruct cpuacct_usage *cpuusage;\n\tstruct kernel_cpustat *cpustat;\n};\n\nstruct gov_attr_set {\n\tstruct kobject kobj;\n\tstruct list_head policy_list;\n\tstruct mutex update_lock;\n\tint usage_count;\n};\n\nstruct governor_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct gov_attr_set *, char *);\n\tssize_t (*store)(struct gov_attr_set *, const char *, size_t);\n};\n\nstruct sugov_tunables {\n\tstruct gov_attr_set attr_set;\n\tunsigned int rate_limit_us;\n};\n\nstruct sugov_policy {\n\tstruct cpufreq_policy *policy;\n\tstruct sugov_tunables *tunables;\n\tstruct list_head tunables_hook;\n\traw_spinlock_t update_lock;\n\tu64 last_freq_update_time;\n\ts64 freq_update_delay_ns;\n\tunsigned int next_freq;\n\tunsigned int cached_raw_freq;\n\tstruct irq_work irq_work;\n\tstruct kthread_work work;\n\tstruct mutex work_lock;\n\tstruct kthread_worker worker;\n\tstruct task_struct *thread;\n\tbool work_in_progress;\n\tbool limits_changed;\n\tbool need_freq_update;\n};\n\nstruct sugov_cpu {\n\tstruct update_util_data update_util;\n\tstruct sugov_policy *sg_policy;\n\tunsigned int cpu;\n\tbool iowait_boost_pending;\n\tunsigned int iowait_boost;\n\tu64 last_update;\n\tlong unsigned int bw_dl;\n\tlong unsigned int max;\n\tlong unsigned int saved_idle_calls;\n};\n\nenum {\n\tMEMBARRIER_FLAG_SYNC_CORE = 1,\n};\n\nenum membarrier_cmd {\n\tMEMBARRIER_CMD_QUERY = 0,\n\tMEMBARRIER_CMD_GLOBAL = 1,\n\tMEMBARRIER_CMD_GLOBAL_EXPEDITED = 2,\n\tMEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED = 4,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED = 8,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED = 16,\n\tMEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE = 32,\n\tMEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE = 64,\n\tMEMBARRIER_CMD_SHARED = 1,\n};\n\nstruct ww_acquire_ctx;\n\nstruct mutex_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tstruct ww_acquire_ctx *ww_ctx;\n};\n\nstruct ww_acquire_ctx {\n\tstruct task_struct *task;\n\tlong unsigned int stamp;\n\tunsigned int acquired;\n\tshort unsigned int wounded;\n\tshort unsigned int is_wait_die;\n};\n\nenum mutex_trylock_recursive_enum {\n\tMUTEX_TRYLOCK_FAILED = 0,\n\tMUTEX_TRYLOCK_SUCCESS = 1,\n\tMUTEX_TRYLOCK_RECURSIVE = 2,\n};\n\nstruct ww_mutex {\n\tstruct mutex base;\n\tstruct ww_acquire_ctx *ctx;\n};\n\nstruct semaphore {\n\traw_spinlock_t lock;\n\tunsigned int count;\n\tstruct list_head wait_list;\n};\n\nstruct semaphore_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tbool up;\n};\n\nenum rwsem_waiter_type {\n\tRWSEM_WAITING_FOR_WRITE = 0,\n\tRWSEM_WAITING_FOR_READ = 1,\n};\n\nstruct rwsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n\tenum rwsem_waiter_type type;\n\tlong unsigned int timeout;\n\tlong unsigned int last_rowner;\n};\n\nenum rwsem_wake_type {\n\tRWSEM_WAKE_ANY = 0,\n\tRWSEM_WAKE_READERS = 1,\n\tRWSEM_WAKE_READ_OWNED = 2,\n};\n\nenum writer_wait_state {\n\tWRITER_NOT_FIRST = 0,\n\tWRITER_FIRST = 1,\n\tWRITER_HANDOFF = 2,\n};\n\nenum owner_state {\n\tOWNER_NULL = 1,\n\tOWNER_WRITER = 2,\n\tOWNER_READER = 4,\n\tOWNER_NONSPINNABLE = 8,\n};\n\nstruct optimistic_spin_node {\n\tstruct optimistic_spin_node *next;\n\tstruct optimistic_spin_node *prev;\n\tint locked;\n\tint cpu;\n};\n\nstruct mcs_spinlock {\n\tstruct mcs_spinlock *next;\n\tint locked;\n\tint count;\n};\n\nstruct qnode {\n\tstruct mcs_spinlock mcs;\n};\n\nstruct hrtimer_sleeper {\n\tstruct hrtimer timer;\n\tstruct task_struct *task;\n};\n\nstruct rt_mutex;\n\nstruct rt_mutex_waiter {\n\tstruct rb_node tree_entry;\n\tstruct rb_node pi_tree_entry;\n\tstruct task_struct *task;\n\tstruct rt_mutex *lock;\n\tint prio;\n\tu64 deadline;\n};\n\nstruct rt_mutex {\n\traw_spinlock_t wait_lock;\n\tstruct rb_root_cached waiters;\n\tstruct task_struct *owner;\n};\n\nenum rtmutex_chainwalk {\n\tRT_MUTEX_MIN_CHAINWALK = 0,\n\tRT_MUTEX_FULL_CHAINWALK = 1,\n};\n\nenum pm_qos_req_action {\n\tPM_QOS_ADD_REQ = 0,\n\tPM_QOS_UPDATE_REQ = 1,\n\tPM_QOS_REMOVE_REQ = 2,\n};\n\nstruct miscdevice {\n\tint minor;\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tstruct list_head list;\n\tstruct device *parent;\n\tstruct device *this_device;\n\tconst struct attribute_group **groups;\n\tconst char *nodename;\n\tumode_t mode;\n};\n\nenum {\n\tTEST_NONE = 0,\n\tTEST_CORE = 1,\n\tTEST_CPUS = 2,\n\tTEST_PLATFORM = 3,\n\tTEST_DEVICES = 4,\n\tTEST_FREEZER = 5,\n\t__TEST_AFTER_LAST = 6,\n};\n\nstruct pm_vt_switch {\n\tstruct list_head head;\n\tstruct device *dev;\n\tbool required;\n};\n\nstruct platform_suspend_ops {\n\tint (*valid)(suspend_state_t);\n\tint (*begin)(suspend_state_t);\n\tint (*prepare)();\n\tint (*prepare_late)();\n\tint (*enter)(suspend_state_t);\n\tvoid (*wake)();\n\tvoid (*finish)();\n\tbool (*suspend_again)();\n\tvoid (*end)();\n\tvoid (*recover)();\n};\n\nstruct platform_s2idle_ops {\n\tint (*begin)();\n\tint (*prepare)();\n\tint (*prepare_late)();\n\tbool (*wake)();\n\tvoid (*restore_early)();\n\tvoid (*restore)();\n\tvoid (*end)();\n};\n\nstruct platform_hibernation_ops {\n\tint (*begin)(pm_message_t);\n\tvoid (*end)();\n\tint (*pre_snapshot)();\n\tvoid (*finish)();\n\tint (*prepare)();\n\tint (*enter)();\n\tvoid (*leave)();\n\tint (*pre_restore)();\n\tvoid (*restore_cleanup)();\n\tvoid (*recover)();\n};\n\nenum {\n\tHIBERNATION_INVALID = 0,\n\tHIBERNATION_PLATFORM = 1,\n\tHIBERNATION_SHUTDOWN = 2,\n\tHIBERNATION_REBOOT = 3,\n\tHIBERNATION_SUSPEND = 4,\n\tHIBERNATION_TEST_RESUME = 5,\n\t__HIBERNATION_AFTER_LAST = 6,\n};\n\nstruct swsusp_info {\n\tstruct new_utsname uts;\n\tu32 version_code;\n\tlong unsigned int num_physpages;\n\tint cpus;\n\tlong unsigned int image_pages;\n\tlong unsigned int pages;\n\tlong unsigned int size;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct snapshot_handle {\n\tunsigned int cur;\n\tvoid *buffer;\n\tint sync_read;\n};\n\nstruct linked_page {\n\tstruct linked_page *next;\n\tchar data[4088];\n};\n\nstruct chain_allocator {\n\tstruct linked_page *chain;\n\tunsigned int used_space;\n\tgfp_t gfp_mask;\n\tint safe_needed;\n};\n\nstruct rtree_node {\n\tstruct list_head list;\n\tlong unsigned int *data;\n};\n\nstruct mem_zone_bm_rtree {\n\tstruct list_head list;\n\tstruct list_head nodes;\n\tstruct list_head leaves;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tstruct rtree_node *rtree;\n\tint levels;\n\tunsigned int blocks;\n};\n\nstruct bm_position {\n\tstruct mem_zone_bm_rtree *zone;\n\tstruct rtree_node *node;\n\tlong unsigned int node_pfn;\n\tint node_bit;\n};\n\nstruct memory_bitmap {\n\tstruct list_head zones;\n\tstruct linked_page *p_list;\n\tstruct bm_position cur;\n};\n\nstruct mem_extent {\n\tstruct list_head hook;\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct nosave_region {\n\tstruct list_head list;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n};\n\ntypedef struct {\n\tlong unsigned int val;\n} swp_entry_t;\n\nenum {\n\tBIO_NO_PAGE_REF = 0,\n\tBIO_CLONED = 1,\n\tBIO_BOUNCED = 2,\n\tBIO_USER_MAPPED = 3,\n\tBIO_NULL_MAPPED = 4,\n\tBIO_WORKINGSET = 5,\n\tBIO_QUIET = 6,\n\tBIO_CHAIN = 7,\n\tBIO_REFFED = 8,\n\tBIO_THROTTLED = 9,\n\tBIO_TRACE_COMPLETION = 10,\n\tBIO_CGROUP_ACCT = 11,\n\tBIO_TRACKED = 12,\n\tBIO_FLAG_LAST = 13,\n};\n\nenum req_opf {\n\tREQ_OP_READ = 0,\n\tREQ_OP_WRITE = 1,\n\tREQ_OP_FLUSH = 2,\n\tREQ_OP_DISCARD = 3,\n\tREQ_OP_SECURE_ERASE = 5,\n\tREQ_OP_ZONE_RESET = 6,\n\tREQ_OP_WRITE_SAME = 7,\n\tREQ_OP_ZONE_RESET_ALL = 8,\n\tREQ_OP_WRITE_ZEROES = 9,\n\tREQ_OP_ZONE_OPEN = 10,\n\tREQ_OP_ZONE_CLOSE = 11,\n\tREQ_OP_ZONE_FINISH = 12,\n\tREQ_OP_ZONE_APPEND = 13,\n\tREQ_OP_SCSI_IN = 32,\n\tREQ_OP_SCSI_OUT = 33,\n\tREQ_OP_DRV_IN = 34,\n\tREQ_OP_DRV_OUT = 35,\n\tREQ_OP_LAST = 36,\n};\n\nenum req_flag_bits {\n\t__REQ_FAILFAST_DEV = 8,\n\t__REQ_FAILFAST_TRANSPORT = 9,\n\t__REQ_FAILFAST_DRIVER = 10,\n\t__REQ_SYNC = 11,\n\t__REQ_META = 12,\n\t__REQ_PRIO = 13,\n\t__REQ_NOMERGE = 14,\n\t__REQ_IDLE = 15,\n\t__REQ_INTEGRITY = 16,\n\t__REQ_FUA = 17,\n\t__REQ_PREFLUSH = 18,\n\t__REQ_RAHEAD = 19,\n\t__REQ_BACKGROUND = 20,\n\t__REQ_NOWAIT = 21,\n\t__REQ_CGROUP_PUNT = 22,\n\t__REQ_NOUNMAP = 23,\n\t__REQ_HIPRI = 24,\n\t__REQ_DRV = 25,\n\t__REQ_SWAP = 26,\n\t__REQ_NR_BITS = 27,\n};\n\nstruct swap_map_page {\n\tsector_t entries[511];\n\tsector_t next_swap;\n};\n\nstruct swap_map_page_list {\n\tstruct swap_map_page *map;\n\tstruct swap_map_page_list *next;\n};\n\nstruct swap_map_handle {\n\tstruct swap_map_page *cur;\n\tstruct swap_map_page_list *maps;\n\tsector_t cur_swap;\n\tsector_t first_sector;\n\tunsigned int k;\n\tlong unsigned int reqd_free_pages;\n\tu32 crc32;\n};\n\nstruct swsusp_header {\n\tchar reserved[4060];\n\tu32 crc32;\n\tsector_t image;\n\tunsigned int flags;\n\tchar orig_sig[10];\n\tchar sig[10];\n};\n\nstruct swsusp_extent {\n\tstruct rb_node node;\n\tlong unsigned int start;\n\tlong unsigned int end;\n};\n\nstruct hib_bio_batch {\n\tatomic_t count;\n\twait_queue_head_t wait;\n\tblk_status_t error;\n};\n\nstruct crc_data {\n\tstruct task_struct *thr;\n\tatomic_t ready;\n\tatomic_t stop;\n\tunsigned int run_threads;\n\twait_queue_head_t go;\n\twait_queue_head_t done;\n\tu32 *crc32;\n\tsize_t *unc_len[3];\n\tunsigned char *unc[3];\n};\n\nstruct cmp_data {\n\tstruct task_struct *thr;\n\tatomic_t ready;\n\tatomic_t stop;\n\tint ret;\n\twait_queue_head_t go;\n\twait_queue_head_t done;\n\tsize_t unc_len;\n\tsize_t cmp_len;\n\tunsigned char unc[131072];\n\tunsigned char cmp[143360];\n\tunsigned char wrk[16384];\n};\n\nstruct dec_data {\n\tstruct task_struct *thr;\n\tatomic_t ready;\n\tatomic_t stop;\n\tint ret;\n\twait_queue_head_t go;\n\twait_queue_head_t done;\n\tsize_t unc_len;\n\tsize_t cmp_len;\n\tunsigned char unc[131072];\n\tunsigned char cmp[143360];\n};\n\ntypedef s64 compat_loff_t;\n\nstruct resume_swap_area {\n\t__kernel_loff_t offset;\n\t__u32 dev;\n} __attribute__((packed));\n\nstruct snapshot_data {\n\tstruct snapshot_handle handle;\n\tint swap;\n\tint mode;\n\tbool frozen;\n\tbool ready;\n\tbool platform_support;\n\tbool free_bitmaps;\n\tstruct inode *bd_inode;\n};\n\nstruct compat_resume_swap_area {\n\tcompat_loff_t offset;\n\tu32 dev;\n} __attribute__((packed));\n\nstruct kmsg_dumper {\n\tstruct list_head list;\n\tvoid (*dump)(struct kmsg_dumper *, enum kmsg_dump_reason);\n\tenum kmsg_dump_reason max_reason;\n\tbool active;\n\tbool registered;\n\tu32 cur_idx;\n\tu32 next_idx;\n\tu64 cur_seq;\n\tu64 next_seq;\n};\n\nstruct trace_event_raw_console {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_console {\n\tu32 msg;\n};\n\ntypedef void (*btf_trace_console)(void *, const char *, size_t);\n\nstruct console_cmdline {\n\tchar name[16];\n\tint index;\n\tbool user_specified;\n\tchar *options;\n};\n\nenum devkmsg_log_bits {\n\t__DEVKMSG_LOG_BIT_ON = 0,\n\t__DEVKMSG_LOG_BIT_OFF = 1,\n\t__DEVKMSG_LOG_BIT_LOCK = 2,\n};\n\nenum devkmsg_log_masks {\n\tDEVKMSG_LOG_MASK_ON = 1,\n\tDEVKMSG_LOG_MASK_OFF = 2,\n\tDEVKMSG_LOG_MASK_LOCK = 4,\n};\n\nenum con_msg_format_flags {\n\tMSG_FORMAT_DEFAULT = 0,\n\tMSG_FORMAT_SYSLOG = 1,\n};\n\nenum log_flags {\n\tLOG_NEWLINE = 2,\n\tLOG_CONT = 8,\n};\n\nstruct printk_log {\n\tu64 ts_nsec;\n\tu16 len;\n\tu16 text_len;\n\tu16 dict_len;\n\tu8 facility;\n\tu8 flags: 5;\n\tu8 level: 3;\n};\n\nstruct devkmsg_user {\n\tu64 seq;\n\tu32 idx;\n\tstruct ratelimit_state rs;\n\tstruct mutex lock;\n\tchar buf[8192];\n};\n\nstruct cont {\n\tchar buf[992];\n\tsize_t len;\n\tu32 caller_id;\n\tu64 ts_nsec;\n\tu8 level;\n\tu8 facility;\n\tenum log_flags flags;\n};\n\nstruct printk_safe_seq_buf {\n\tatomic_t len;\n\tatomic_t message_lost;\n\tstruct irq_work work;\n\tunsigned char buffer[8160];\n};\n\nenum {\n\tIRQS_AUTODETECT = 1,\n\tIRQS_SPURIOUS_DISABLED = 2,\n\tIRQS_POLL_INPROGRESS = 8,\n\tIRQS_ONESHOT = 32,\n\tIRQS_REPLAY = 64,\n\tIRQS_WAITING = 128,\n\tIRQS_PENDING = 512,\n\tIRQS_SUSPENDED = 2048,\n\tIRQS_TIMINGS = 4096,\n\tIRQS_NMI = 8192,\n};\n\nenum {\n\t_IRQ_DEFAULT_INIT_FLAGS = 0,\n\t_IRQ_PER_CPU = 512,\n\t_IRQ_LEVEL = 256,\n\t_IRQ_NOPROBE = 1024,\n\t_IRQ_NOREQUEST = 2048,\n\t_IRQ_NOTHREAD = 65536,\n\t_IRQ_NOAUTOEN = 4096,\n\t_IRQ_MOVE_PCNTXT = 16384,\n\t_IRQ_NO_BALANCING = 8192,\n\t_IRQ_NESTED_THREAD = 32768,\n\t_IRQ_PER_CPU_DEVID = 131072,\n\t_IRQ_IS_POLLED = 262144,\n\t_IRQ_DISABLE_UNLAZY = 524288,\n\t_IRQF_MODIFY_MASK = 1048335,\n};\n\nenum {\n\tIRQTF_RUNTHREAD = 0,\n\tIRQTF_WARNED = 1,\n\tIRQTF_AFFINITY = 2,\n\tIRQTF_FORCED_THREAD = 3,\n};\n\nenum {\n\tIRQC_IS_HARDIRQ = 0,\n\tIRQC_IS_NESTED = 1,\n};\n\nenum {\n\tIRQ_STARTUP_NORMAL = 0,\n\tIRQ_STARTUP_MANAGED = 1,\n\tIRQ_STARTUP_ABORT = 2,\n};\n\nstruct irq_devres {\n\tunsigned int irq;\n\tvoid *dev_id;\n};\n\nstruct irq_desc_devres {\n\tunsigned int from;\n\tunsigned int cnt;\n};\n\nstruct irqchip_fwid {\n\tstruct fwnode_handle fwnode;\n\tunsigned int type;\n\tchar *name;\n\tphys_addr_t *pa;\n};\n\nenum {\n\tAFFINITY = 0,\n\tAFFINITY_LIST = 1,\n\tEFFECTIVE = 2,\n\tEFFECTIVE_LIST = 3,\n};\n\nstruct irq_affinity {\n\tunsigned int pre_vectors;\n\tunsigned int post_vectors;\n\tunsigned int nr_sets;\n\tunsigned int set_size[4];\n\tvoid (*calc_sets)(struct irq_affinity *, unsigned int);\n\tvoid *priv;\n};\n\nstruct node_vectors {\n\tunsigned int id;\n\tunion {\n\t\tunsigned int nvectors;\n\t\tunsigned int ncpus;\n\t};\n};\n\nstruct cpumap {\n\tunsigned int available;\n\tunsigned int allocated;\n\tunsigned int managed;\n\tunsigned int managed_allocated;\n\tbool initialized;\n\tbool online;\n\tlong unsigned int alloc_map[4];\n\tlong unsigned int managed_map[4];\n};\n\nstruct irq_matrix___2 {\n\tunsigned int matrix_bits;\n\tunsigned int alloc_start;\n\tunsigned int alloc_end;\n\tunsigned int alloc_size;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int systembits_inalloc;\n\tunsigned int total_allocated;\n\tunsigned int online_maps;\n\tstruct cpumap *maps;\n\tlong unsigned int scratch_map[4];\n\tlong unsigned int system_map[4];\n};\n\nstruct trace_event_raw_irq_matrix_global {\n\tstruct trace_entry ent;\n\tunsigned int online_maps;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int total_allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_matrix_global_update {\n\tstruct trace_entry ent;\n\tint bit;\n\tunsigned int online_maps;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int total_allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_irq_matrix_cpu {\n\tstruct trace_entry ent;\n\tint bit;\n\tunsigned int cpu;\n\tbool online;\n\tunsigned int available;\n\tunsigned int allocated;\n\tunsigned int managed;\n\tunsigned int online_maps;\n\tunsigned int global_available;\n\tunsigned int global_reserved;\n\tunsigned int total_allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_irq_matrix_global {};\n\nstruct trace_event_data_offsets_irq_matrix_global_update {};\n\nstruct trace_event_data_offsets_irq_matrix_cpu {};\n\ntypedef void (*btf_trace_irq_matrix_online)(void *, struct irq_matrix___2 *);\n\ntypedef void (*btf_trace_irq_matrix_offline)(void *, struct irq_matrix___2 *);\n\ntypedef void (*btf_trace_irq_matrix_reserve)(void *, struct irq_matrix___2 *);\n\ntypedef void (*btf_trace_irq_matrix_remove_reserved)(void *, struct irq_matrix___2 *);\n\ntypedef void (*btf_trace_irq_matrix_assign_system)(void *, int, struct irq_matrix___2 *);\n\ntypedef void (*btf_trace_irq_matrix_alloc_reserved)(void *, int, unsigned int, struct irq_matrix___2 *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_reserve_managed)(void *, int, unsigned int, struct irq_matrix___2 *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_remove_managed)(void *, int, unsigned int, struct irq_matrix___2 *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_alloc_managed)(void *, int, unsigned int, struct irq_matrix___2 *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_assign)(void *, int, unsigned int, struct irq_matrix___2 *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_alloc)(void *, int, unsigned int, struct irq_matrix___2 *, struct cpumap *);\n\ntypedef void (*btf_trace_irq_matrix_free)(void *, int, unsigned int, struct irq_matrix___2 *, struct cpumap *);\n\ntypedef void (*rcu_callback_t)(struct callback_head *);\n\ntypedef void (*call_rcu_func_t)(struct callback_head *, rcu_callback_t);\n\nstruct rcu_synchronize {\n\tstruct callback_head head;\n\tstruct completion completion;\n};\n\nstruct trace_event_raw_rcu_utilization {\n\tstruct trace_entry ent;\n\tconst char *s;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int gp_seq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_future_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_req;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_grace_period_init {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int gp_seq;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tlong unsigned int qsmask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_grace_period {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int gpseq;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_exp_funnel_lock {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tconst char *gpevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_preempt_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_unlock_preempted_task {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int gp_seq;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_quiescent_state_report {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int gp_seq;\n\tlong unsigned int mask;\n\tlong unsigned int qsmask;\n\tu8 level;\n\tint grplo;\n\tint grphi;\n\tu8 gp_tasks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_fqs {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int gp_seq;\n\tint cpu;\n\tconst char *qsevent;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_dyntick {\n\tstruct trace_entry ent;\n\tconst char *polarity;\n\tlong int oldnesting;\n\tlong int newnesting;\n\tint dynticks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tlong int qlen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_kfree_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tlong unsigned int offset;\n\tlong int qlen;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_start {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong int qlen;\n\tlong int blimit;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tvoid *func;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kfree_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tvoid *rhp;\n\tlong unsigned int offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_invoke_kfree_bulk_callback {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tlong unsigned int nr_records;\n\tvoid **p;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_batch_end {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tint callbacks_invoked;\n\tchar cb;\n\tchar nr;\n\tchar iit;\n\tchar risk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_torture_read {\n\tstruct trace_entry ent;\n\tchar rcutorturename[8];\n\tstruct callback_head *rhp;\n\tlong unsigned int secs;\n\tlong unsigned int c_old;\n\tlong unsigned int c;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rcu_barrier {\n\tstruct trace_entry ent;\n\tconst char *rcuname;\n\tconst char *s;\n\tint cpu;\n\tint cnt;\n\tlong unsigned int done;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_rcu_utilization {};\n\nstruct trace_event_data_offsets_rcu_grace_period {};\n\nstruct trace_event_data_offsets_rcu_future_grace_period {};\n\nstruct trace_event_data_offsets_rcu_grace_period_init {};\n\nstruct trace_event_data_offsets_rcu_exp_grace_period {};\n\nstruct trace_event_data_offsets_rcu_exp_funnel_lock {};\n\nstruct trace_event_data_offsets_rcu_preempt_task {};\n\nstruct trace_event_data_offsets_rcu_unlock_preempted_task {};\n\nstruct trace_event_data_offsets_rcu_quiescent_state_report {};\n\nstruct trace_event_data_offsets_rcu_fqs {};\n\nstruct trace_event_data_offsets_rcu_dyntick {};\n\nstruct trace_event_data_offsets_rcu_callback {};\n\nstruct trace_event_data_offsets_rcu_kfree_callback {};\n\nstruct trace_event_data_offsets_rcu_batch_start {};\n\nstruct trace_event_data_offsets_rcu_invoke_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kfree_callback {};\n\nstruct trace_event_data_offsets_rcu_invoke_kfree_bulk_callback {};\n\nstruct trace_event_data_offsets_rcu_batch_end {};\n\nstruct trace_event_data_offsets_rcu_torture_read {};\n\nstruct trace_event_data_offsets_rcu_barrier {};\n\ntypedef void (*btf_trace_rcu_utilization)(void *, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_future_grace_period)(void *, const char *, long unsigned int, long unsigned int, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_grace_period_init)(void *, const char *, long unsigned int, u8, int, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_exp_grace_period)(void *, const char *, long unsigned int, const char *);\n\ntypedef void (*btf_trace_rcu_exp_funnel_lock)(void *, const char *, u8, int, int, const char *);\n\ntypedef void (*btf_trace_rcu_preempt_task)(void *, const char *, int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_unlock_preempted_task)(void *, const char *, long unsigned int, int);\n\ntypedef void (*btf_trace_rcu_quiescent_state_report)(void *, const char *, long unsigned int, long unsigned int, long unsigned int, u8, int, int, int);\n\ntypedef void (*btf_trace_rcu_fqs)(void *, const char *, long unsigned int, int, const char *);\n\ntypedef void (*btf_trace_rcu_dyntick)(void *, const char *, long int, long int, int);\n\ntypedef void (*btf_trace_rcu_callback)(void *, const char *, struct callback_head *, long int);\n\ntypedef void (*btf_trace_rcu_kfree_callback)(void *, const char *, struct callback_head *, long unsigned int, long int);\n\ntypedef void (*btf_trace_rcu_batch_start)(void *, const char *, long int, long int);\n\ntypedef void (*btf_trace_rcu_invoke_callback)(void *, const char *, struct callback_head *);\n\ntypedef void (*btf_trace_rcu_invoke_kfree_callback)(void *, const char *, struct callback_head *, long unsigned int);\n\ntypedef void (*btf_trace_rcu_invoke_kfree_bulk_callback)(void *, const char *, long unsigned int, void **);\n\ntypedef void (*btf_trace_rcu_batch_end)(void *, const char *, int, char, char, char, char);\n\ntypedef void (*btf_trace_rcu_torture_read)(void *, const char *, struct callback_head *, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_rcu_barrier)(void *, const char *, const char *, int, int, long unsigned int);\n\nenum {\n\tGP_IDLE = 0,\n\tGP_ENTER = 1,\n\tGP_PASSED = 2,\n\tGP_EXIT = 3,\n\tGP_REPLAY = 4,\n};\n\ntypedef long unsigned int ulong;\n\nstruct rcu_cblist {\n\tstruct callback_head *head;\n\tstruct callback_head **tail;\n\tlong int len;\n};\n\nenum rcutorture_type {\n\tRCU_FLAVOR = 0,\n\tRCU_TASKS_FLAVOR = 1,\n\tRCU_TASKS_RUDE_FLAVOR = 2,\n\tRCU_TASKS_TRACING_FLAVOR = 3,\n\tRCU_TRIVIAL_FLAVOR = 4,\n\tSRCU_FLAVOR = 5,\n\tINVALID_RCU_FLAVOR = 6,\n};\n\nenum tick_device_mode {\n\tTICKDEV_MODE_PERIODIC = 0,\n\tTICKDEV_MODE_ONESHOT = 1,\n};\n\nstruct tick_device___2 {\n\tstruct clock_event_device *evtdev;\n\tenum tick_device_mode mode;\n};\n\nstruct rcu_exp_work {\n\tlong unsigned int rew_s;\n\tstruct work_struct rew_work;\n};\n\nstruct rcu_node {\n\traw_spinlock_t lock;\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tlong unsigned int completedqs;\n\tlong unsigned int qsmask;\n\tlong unsigned int rcu_gp_init_mask;\n\tlong unsigned int qsmaskinit;\n\tlong unsigned int qsmaskinitnext;\n\tlong unsigned int expmask;\n\tlong unsigned int expmaskinit;\n\tlong unsigned int expmaskinitnext;\n\tlong unsigned int cbovldmask;\n\tlong unsigned int ffmask;\n\tlong unsigned int grpmask;\n\tint grplo;\n\tint grphi;\n\tu8 grpnum;\n\tu8 level;\n\tbool wait_blkd_tasks;\n\tstruct rcu_node *parent;\n\tstruct list_head blkd_tasks;\n\tstruct list_head *gp_tasks;\n\tstruct list_head *exp_tasks;\n\tstruct list_head *boost_tasks;\n\tstruct rt_mutex boost_mtx;\n\tlong unsigned int boost_time;\n\tstruct task_struct *boost_kthread_task;\n\tunsigned int boost_kthread_status;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\traw_spinlock_t fqslock;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t exp_lock;\n\tlong unsigned int exp_seq_rq;\n\twait_queue_head_t exp_wq[4];\n\tstruct rcu_exp_work rew;\n\tbool exp_need_flush;\n\tlong: 56;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nunion rcu_noqs {\n\tstruct {\n\t\tu8 norm;\n\t\tu8 exp;\n\t} b;\n\tu16 s;\n};\n\nstruct rcu_data {\n\tlong unsigned int gp_seq;\n\tlong unsigned int gp_seq_needed;\n\tunion rcu_noqs cpu_no_qs;\n\tbool core_needs_qs;\n\tbool beenonline;\n\tbool gpwrap;\n\tbool exp_deferred_qs;\n\tstruct rcu_node *mynode;\n\tlong unsigned int grpmask;\n\tlong unsigned int ticks_this_gp;\n\tstruct irq_work defer_qs_iw;\n\tbool defer_qs_iw_pending;\n\tstruct rcu_segcblist cblist;\n\tlong int qlen_last_fqs_check;\n\tlong unsigned int n_force_qs_snap;\n\tlong int blimit;\n\tint dynticks_snap;\n\tlong int dynticks_nesting;\n\tlong int dynticks_nmi_nesting;\n\tatomic_t dynticks;\n\tbool rcu_need_heavy_qs;\n\tbool rcu_urgent_qs;\n\tbool rcu_forced_tick;\n\tbool rcu_forced_tick_exp;\n\tstruct callback_head barrier_head;\n\tint exp_dynticks_snap;\n\tstruct task_struct *rcu_cpu_kthread_task;\n\tunsigned int rcu_cpu_kthread_status;\n\tchar rcu_cpu_has_work;\n\tunsigned int softirq_snap;\n\tstruct irq_work rcu_iw;\n\tbool rcu_iw_pending;\n\tlong unsigned int rcu_iw_gp_seq;\n\tlong unsigned int rcu_ofl_gp_seq;\n\tshort int rcu_ofl_gp_flags;\n\tlong unsigned int rcu_onl_gp_seq;\n\tshort int rcu_onl_gp_flags;\n\tlong unsigned int last_fqs_resched;\n\tint cpu;\n};\n\nstruct rcu_state {\n\tstruct rcu_node node[5];\n\tstruct rcu_node *level[3];\n\tint ncpus;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu8 boost;\n\tlong unsigned int gp_seq;\n\tstruct task_struct *gp_kthread;\n\tstruct swait_queue_head gp_wq;\n\tshort int gp_flags;\n\tshort int gp_state;\n\tlong unsigned int gp_wake_time;\n\tlong unsigned int gp_wake_seq;\n\tstruct mutex barrier_mutex;\n\tatomic_t barrier_cpu_count;\n\tstruct completion barrier_completion;\n\tlong unsigned int barrier_sequence;\n\tstruct mutex exp_mutex;\n\tstruct mutex exp_wake_mutex;\n\tlong unsigned int expedited_sequence;\n\tatomic_t expedited_need_qs;\n\tstruct swait_queue_head expedited_wq;\n\tint ncpus_snap;\n\tu8 cbovld;\n\tu8 cbovldnext;\n\tlong unsigned int jiffies_force_qs;\n\tlong unsigned int jiffies_kick_kthreads;\n\tlong unsigned int n_force_qs;\n\tlong unsigned int gp_start;\n\tlong unsigned int gp_end;\n\tlong unsigned int gp_activity;\n\tlong unsigned int gp_req_activity;\n\tlong unsigned int jiffies_stall;\n\tlong unsigned int jiffies_resched;\n\tlong unsigned int n_force_qs_gpstart;\n\tlong unsigned int gp_max;\n\tconst char *name;\n\tchar abbr;\n\tlong: 56;\n\tlong: 64;\n\tlong: 64;\n\traw_spinlock_t ofl_lock;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kfree_rcu_bulk_data {\n\tlong unsigned int nr_records;\n\tvoid *records[509];\n\tstruct kfree_rcu_bulk_data *next;\n\tstruct callback_head *head_free_debug;\n};\n\nstruct kfree_rcu_cpu;\n\nstruct kfree_rcu_cpu_work {\n\tstruct rcu_work rcu_work;\n\tstruct callback_head *head_free;\n\tstruct kfree_rcu_bulk_data *bhead_free;\n\tstruct kfree_rcu_cpu *krcp;\n};\n\nstruct kfree_rcu_cpu {\n\tstruct callback_head *head;\n\tstruct kfree_rcu_bulk_data *bhead;\n\tstruct kfree_rcu_bulk_data *bcached;\n\tstruct kfree_rcu_cpu_work krw_arr[2];\n\tspinlock_t lock;\n\tstruct delayed_work monitor_work;\n\tbool monitor_todo;\n\tbool initialized;\n\tint count;\n};\n\ntypedef char pto_T_____18;\n\nstruct dma_devres {\n\tsize_t size;\n\tvoid *vaddr;\n\tdma_addr_t dma_handle;\n\tlong unsigned int attrs;\n};\n\nenum dma_sync_target {\n\tSYNC_FOR_CPU = 0,\n\tSYNC_FOR_DEVICE = 1,\n};\n\nstruct trace_event_raw_swiotlb_bounced {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu64 dma_mask;\n\tdma_addr_t dev_addr;\n\tsize_t size;\n\tenum swiotlb_force swiotlb_force;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_swiotlb_bounced {\n\tu32 dev_name;\n};\n\ntypedef void (*btf_trace_swiotlb_bounced)(void *, struct device *, dma_addr_t, size_t, enum swiotlb_force);\n\nenum profile_type {\n\tPROFILE_TASK_EXIT = 0,\n\tPROFILE_MUNMAP = 1,\n};\n\nstruct profile_hit {\n\tu32 pc;\n\tu32 hits;\n};\n\nstruct stacktrace_cookie {\n\tlong unsigned int *store;\n\tunsigned int size;\n\tunsigned int skip;\n\tunsigned int len;\n};\n\ntypedef __kernel_long_t __kernel_suseconds_t;\n\ntypedef __kernel_long_t __kernel_old_time_t;\n\ntypedef __kernel_suseconds_t suseconds_t;\n\ntypedef __u64 timeu64_t;\n\nstruct __kernel_itimerspec {\n\tstruct __kernel_timespec it_interval;\n\tstruct __kernel_timespec it_value;\n};\n\nstruct itimerspec64 {\n\tstruct timespec64 it_interval;\n\tstruct timespec64 it_value;\n};\n\nstruct old_itimerspec32 {\n\tstruct old_timespec32 it_interval;\n\tstruct old_timespec32 it_value;\n};\n\nstruct old_timex32 {\n\tu32 modes;\n\ts32 offset;\n\ts32 freq;\n\ts32 maxerror;\n\ts32 esterror;\n\ts32 status;\n\ts32 constant;\n\ts32 precision;\n\ts32 tolerance;\n\tstruct old_timeval32 time;\n\ts32 tick;\n\ts32 ppsfreq;\n\ts32 jitter;\n\ts32 shift;\n\ts32 stabil;\n\ts32 jitcnt;\n\ts32 calcnt;\n\ts32 errcnt;\n\ts32 stbcnt;\n\ts32 tai;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct __kernel_timex_timeval {\n\t__kernel_time64_t tv_sec;\n\tlong long int tv_usec;\n};\n\nstruct __kernel_timex {\n\tunsigned int modes;\n\tlong long int offset;\n\tlong long int freq;\n\tlong long int maxerror;\n\tlong long int esterror;\n\tint status;\n\tlong long int constant;\n\tlong long int precision;\n\tlong long int tolerance;\n\tstruct __kernel_timex_timeval time;\n\tlong long int tick;\n\tlong long int ppsfreq;\n\tlong long int jitter;\n\tint shift;\n\tlong long int stabil;\n\tlong long int jitcnt;\n\tlong long int calcnt;\n\tlong long int errcnt;\n\tlong long int stbcnt;\n\tint tai;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct trace_event_raw_timer_class {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_start {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tvoid *function;\n\tlong unsigned int expires;\n\tlong unsigned int now;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_timer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *timer;\n\tlong unsigned int now;\n\tvoid *function;\n\tlong unsigned int baseclk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_init {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tclockid_t clockid;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_start {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tvoid *function;\n\ts64 expires;\n\ts64 softexpires;\n\tenum hrtimer_mode mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_expire_entry {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\ts64 now;\n\tvoid *function;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hrtimer_class {\n\tstruct trace_entry ent;\n\tvoid *hrtimer;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_state {\n\tstruct trace_entry ent;\n\tint which;\n\tlong long unsigned int expires;\n\tlong int value_sec;\n\tlong int value_nsec;\n\tlong int interval_sec;\n\tlong int interval_nsec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_itimer_expire {\n\tstruct trace_entry ent;\n\tint which;\n\tpid_t pid;\n\tlong long unsigned int now;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tick_stop {\n\tstruct trace_entry ent;\n\tint success;\n\tint dependency;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_timer_class {};\n\nstruct trace_event_data_offsets_timer_start {};\n\nstruct trace_event_data_offsets_timer_expire_entry {};\n\nstruct trace_event_data_offsets_hrtimer_init {};\n\nstruct trace_event_data_offsets_hrtimer_start {};\n\nstruct trace_event_data_offsets_hrtimer_expire_entry {};\n\nstruct trace_event_data_offsets_hrtimer_class {};\n\nstruct trace_event_data_offsets_itimer_state {};\n\nstruct trace_event_data_offsets_itimer_expire {};\n\nstruct trace_event_data_offsets_tick_stop {};\n\ntypedef void (*btf_trace_timer_init)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_start)(void *, struct timer_list *, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_timer_expire_entry)(void *, struct timer_list *, long unsigned int);\n\ntypedef void (*btf_trace_timer_expire_exit)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_timer_cancel)(void *, struct timer_list *);\n\ntypedef void (*btf_trace_hrtimer_init)(void *, struct hrtimer *, clockid_t, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hrtimer_start)(void *, struct hrtimer *, enum hrtimer_mode);\n\ntypedef void (*btf_trace_hrtimer_expire_entry)(void *, struct hrtimer *, ktime_t *);\n\ntypedef void (*btf_trace_hrtimer_expire_exit)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_hrtimer_cancel)(void *, struct hrtimer *);\n\ntypedef void (*btf_trace_itimer_state)(void *, int, const struct itimerspec64 * const, long long unsigned int);\n\ntypedef void (*btf_trace_itimer_expire)(void *, int, struct pid *, long long unsigned int);\n\ntypedef void (*btf_trace_tick_stop)(void *, int, int);\n\nstruct timer_base {\n\traw_spinlock_t lock;\n\tstruct timer_list *running_timer;\n\tlong unsigned int clk;\n\tlong unsigned int next_expiry;\n\tunsigned int cpu;\n\tbool is_idle;\n\tbool must_forward_clk;\n\tlong unsigned int pending_map[9];\n\tstruct hlist_head vectors[576];\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct process_timer {\n\tstruct timer_list timer;\n\tstruct task_struct *task;\n};\n\ntypedef __u32 pao_T_____5;\n\nstruct system_time_snapshot {\n\tu64 cycles;\n\tktime_t real;\n\tktime_t raw;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n};\n\nstruct system_device_crosststamp {\n\tktime_t device;\n\tktime_t sys_realtime;\n\tktime_t sys_monoraw;\n};\n\nstruct tk_read_base {\n\tstruct clocksource *clock;\n\tu64 mask;\n\tu64 cycle_last;\n\tu32 mult;\n\tu32 shift;\n\tu64 xtime_nsec;\n\tktime_t base;\n\tu64 base_real;\n};\n\nstruct timekeeper {\n\tstruct tk_read_base tkr_mono;\n\tstruct tk_read_base tkr_raw;\n\tu64 xtime_sec;\n\tlong unsigned int ktime_sec;\n\tstruct timespec64 wall_to_monotonic;\n\tktime_t offs_real;\n\tktime_t offs_boot;\n\tktime_t offs_tai;\n\ts32 tai_offset;\n\tunsigned int clock_was_set_seq;\n\tu8 cs_was_changed_seq;\n\tktime_t next_leap_ktime;\n\tu64 raw_sec;\n\tstruct timespec64 monotonic_to_boot;\n\tu64 cycle_interval;\n\tu64 xtime_interval;\n\ts64 xtime_remainder;\n\tu64 raw_interval;\n\tu64 ntp_tick;\n\ts64 ntp_error;\n\tu32 ntp_error_shift;\n\tu32 ntp_err_mult;\n\tu32 skip_second_overflow;\n};\n\nstruct audit_ntp_val {\n\tlong long int oldval;\n\tlong long int newval;\n};\n\nstruct audit_ntp_data {\n\tstruct audit_ntp_val vals[6];\n};\n\nenum timekeeping_adv_mode {\n\tTK_ADV_TICK = 0,\n\tTK_ADV_FREQ = 1,\n};\n\nstruct tk_fast {\n\tseqcount_t seq;\n\tstruct tk_read_base base[2];\n};\n\ntypedef s64 int64_t;\n\nenum tick_nohz_mode {\n\tNOHZ_MODE_INACTIVE = 0,\n\tNOHZ_MODE_LOWRES = 1,\n\tNOHZ_MODE_HIGHRES = 2,\n};\n\nstruct tick_sched {\n\tstruct hrtimer sched_timer;\n\tlong unsigned int check_clocks;\n\tenum tick_nohz_mode nohz_mode;\n\tunsigned int inidle: 1;\n\tunsigned int tick_stopped: 1;\n\tunsigned int idle_active: 1;\n\tunsigned int do_timer_last: 1;\n\tunsigned int got_idle_tick: 1;\n\tktime_t last_tick;\n\tktime_t next_tick;\n\tlong unsigned int idle_jiffies;\n\tlong unsigned int idle_calls;\n\tlong unsigned int idle_sleeps;\n\tktime_t idle_entrytime;\n\tktime_t idle_waketime;\n\tktime_t idle_exittime;\n\tktime_t idle_sleeptime;\n\tktime_t iowait_sleeptime;\n\tlong unsigned int last_jiffies;\n\tu64 timer_expires;\n\tu64 timer_expires_base;\n\tu64 next_timer;\n\tktime_t idle_expires;\n\tatomic_t tick_dep_mask;\n};\n\nstruct timer_list_iter {\n\tint cpu;\n\tbool second_pass;\n\tu64 now;\n};\n\nstruct tm {\n\tint tm_sec;\n\tint tm_min;\n\tint tm_hour;\n\tint tm_mday;\n\tint tm_mon;\n\tlong int tm_year;\n\tint tm_wday;\n\tint tm_yday;\n};\n\nstruct cyclecounter {\n\tu64 (*read)(const struct cyclecounter *);\n\tu64 mask;\n\tu32 mult;\n\tu32 shift;\n};\n\nstruct timecounter {\n\tconst struct cyclecounter *cc;\n\tu64 cycle_last;\n\tu64 nsec;\n\tu64 mask;\n\tu64 frac;\n};\n\ntypedef __kernel_timer_t timer_t;\n\nstruct rtc_wkalrm {\n\tunsigned char enabled;\n\tunsigned char pending;\n\tstruct rtc_time time;\n};\n\nenum alarmtimer_type {\n\tALARM_REALTIME = 0,\n\tALARM_BOOTTIME = 1,\n\tALARM_NUMTYPE = 2,\n\tALARM_REALTIME_FREEZER = 3,\n\tALARM_BOOTTIME_FREEZER = 4,\n};\n\nenum alarmtimer_restart {\n\tALARMTIMER_NORESTART = 0,\n\tALARMTIMER_RESTART = 1,\n};\n\nstruct alarm {\n\tstruct timerqueue_node node;\n\tstruct hrtimer timer;\n\tenum alarmtimer_restart (*function)(struct alarm *, ktime_t);\n\tenum alarmtimer_type type;\n\tint state;\n\tvoid *data;\n};\n\nstruct cpu_timer {\n\tstruct timerqueue_node node;\n\tstruct timerqueue_head *head;\n\tstruct pid *pid;\n\tstruct list_head elist;\n\tint firing;\n};\n\nstruct k_clock;\n\nstruct k_itimer {\n\tstruct list_head list;\n\tstruct hlist_node t_hash;\n\tspinlock_t it_lock;\n\tconst struct k_clock *kclock;\n\tclockid_t it_clock;\n\ttimer_t it_id;\n\tint it_active;\n\ts64 it_overrun;\n\ts64 it_overrun_last;\n\tint it_requeue_pending;\n\tint it_sigev_notify;\n\tktime_t it_interval;\n\tstruct signal_struct *it_signal;\n\tunion {\n\t\tstruct pid *it_pid;\n\t\tstruct task_struct *it_process;\n\t};\n\tstruct sigqueue *sigq;\n\tunion {\n\t\tstruct {\n\t\t\tstruct hrtimer timer;\n\t\t} real;\n\t\tstruct cpu_timer cpu;\n\t\tstruct {\n\t\t\tstruct alarm alarmtimer;\n\t\t} alarm;\n\t} it;\n\tstruct callback_head rcu;\n};\n\nstruct k_clock {\n\tint (*clock_getres)(const clockid_t, struct timespec64 *);\n\tint (*clock_set)(const clockid_t, const struct timespec64 *);\n\tint (*clock_get_timespec)(const clockid_t, struct timespec64 *);\n\tktime_t (*clock_get_ktime)(const clockid_t);\n\tint (*clock_adj)(const clockid_t, struct __kernel_timex *);\n\tint (*timer_create)(struct k_itimer *);\n\tint (*nsleep)(const clockid_t, int, const struct timespec64 *);\n\tint (*timer_set)(struct k_itimer *, int, struct itimerspec64 *, struct itimerspec64 *);\n\tint (*timer_del)(struct k_itimer *);\n\tvoid (*timer_get)(struct k_itimer *, struct itimerspec64 *);\n\tvoid (*timer_rearm)(struct k_itimer *);\n\ts64 (*timer_forward)(struct k_itimer *, ktime_t);\n\tktime_t (*timer_remaining)(struct k_itimer *, ktime_t);\n\tint (*timer_try_to_cancel)(struct k_itimer *);\n\tvoid (*timer_arm)(struct k_itimer *, ktime_t, bool, bool);\n\tvoid (*timer_wait_running)(struct k_itimer *);\n};\n\nstruct class_interface {\n\tstruct list_head node;\n\tstruct class *class;\n\tint (*add_dev)(struct device *, struct class_interface *);\n\tvoid (*remove_dev)(struct device *, struct class_interface *);\n};\n\nstruct rtc_class_ops {\n\tint (*ioctl)(struct device *, unsigned int, long unsigned int);\n\tint (*read_time)(struct device *, struct rtc_time *);\n\tint (*set_time)(struct device *, struct rtc_time *);\n\tint (*read_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*set_alarm)(struct device *, struct rtc_wkalrm *);\n\tint (*proc)(struct device *, struct seq_file *);\n\tint (*alarm_irq_enable)(struct device *, unsigned int);\n\tint (*read_offset)(struct device *, long int *);\n\tint (*set_offset)(struct device *, long int);\n};\n\nstruct rtc_device;\n\nstruct rtc_timer {\n\tstruct timerqueue_node node;\n\tktime_t period;\n\tvoid (*func)(struct rtc_device *);\n\tstruct rtc_device *rtc;\n\tint enabled;\n};\n\nstruct rtc_device {\n\tstruct device dev;\n\tstruct module *owner;\n\tint id;\n\tconst struct rtc_class_ops *ops;\n\tstruct mutex ops_lock;\n\tstruct cdev char_dev;\n\tlong unsigned int flags;\n\tlong unsigned int irq_data;\n\tspinlock_t irq_lock;\n\twait_queue_head_t irq_queue;\n\tstruct fasync_struct *async_queue;\n\tint irq_freq;\n\tint max_user_freq;\n\tstruct timerqueue_head timerqueue;\n\tstruct rtc_timer aie_timer;\n\tstruct rtc_timer uie_rtctimer;\n\tstruct hrtimer pie_timer;\n\tint pie_enabled;\n\tstruct work_struct irqwork;\n\tint uie_unsupported;\n\tlong int set_offset_nsec;\n\tbool registered;\n\tbool nvram_old_abi;\n\tstruct bin_attribute *nvram;\n\ttime64_t range_min;\n\ttimeu64_t range_max;\n\ttime64_t start_secs;\n\ttime64_t offset_secs;\n\tbool set_start_time;\n};\n\nstruct platform_driver {\n\tint (*probe)(struct platform_device *);\n\tint (*remove)(struct platform_device *);\n\tvoid (*shutdown)(struct platform_device *);\n\tint (*suspend)(struct platform_device *, pm_message_t);\n\tint (*resume)(struct platform_device *);\n\tstruct device_driver driver;\n\tconst struct platform_device_id *id_table;\n\tbool prevent_deferred_probe;\n};\n\nstruct trace_event_raw_alarmtimer_suspend {\n\tstruct trace_entry ent;\n\ts64 expires;\n\tunsigned char alarm_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_alarm_class {\n\tstruct trace_entry ent;\n\tvoid *alarm;\n\tunsigned char alarm_type;\n\ts64 expires;\n\ts64 now;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_alarmtimer_suspend {};\n\nstruct trace_event_data_offsets_alarm_class {};\n\ntypedef void (*btf_trace_alarmtimer_suspend)(void *, ktime_t, int);\n\ntypedef void (*btf_trace_alarmtimer_fired)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_start)(void *, struct alarm *, ktime_t);\n\ntypedef void (*btf_trace_alarmtimer_cancel)(void *, struct alarm *, ktime_t);\n\nstruct alarm_base {\n\tspinlock_t lock;\n\tstruct timerqueue_head timerqueue;\n\tktime_t (*get_ktime)();\n\tvoid (*get_timespec)(struct timespec64 *);\n\tclockid_t base_clockid;\n};\n\nstruct sigevent {\n\tsigval_t sigev_value;\n\tint sigev_signo;\n\tint sigev_notify;\n\tunion {\n\t\tint _pad[12];\n\t\tint _tid;\n\t\tstruct {\n\t\t\tvoid (*_function)(sigval_t);\n\t\t\tvoid *_attribute;\n\t\t} _sigev_thread;\n\t} _sigev_un;\n};\n\ntypedef struct sigevent sigevent_t;\n\nstruct compat_sigevent {\n\tcompat_sigval_t sigev_value;\n\tcompat_int_t sigev_signo;\n\tcompat_int_t sigev_notify;\n\tunion {\n\t\tcompat_int_t _pad[13];\n\t\tcompat_int_t _tid;\n\t\tstruct {\n\t\t\tcompat_uptr_t _function;\n\t\t\tcompat_uptr_t _attribute;\n\t\t} _sigev_thread;\n\t} _sigev_un;\n};\n\ntypedef unsigned int uint;\n\nstruct posix_clock;\n\nstruct posix_clock_operations {\n\tstruct module *owner;\n\tint (*clock_adjtime)(struct posix_clock *, struct __kernel_timex *);\n\tint (*clock_gettime)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_getres)(struct posix_clock *, struct timespec64 *);\n\tint (*clock_settime)(struct posix_clock *, const struct timespec64 *);\n\tlong int (*ioctl)(struct posix_clock *, unsigned int, long unsigned int);\n\tint (*open)(struct posix_clock *, fmode_t);\n\t__poll_t (*poll)(struct posix_clock *, struct file *, poll_table *);\n\tint (*release)(struct posix_clock *);\n\tssize_t (*read)(struct posix_clock *, uint, char *, size_t);\n};\n\nstruct posix_clock {\n\tstruct posix_clock_operations ops;\n\tstruct cdev cdev;\n\tstruct device *dev;\n\tstruct rw_semaphore rwsem;\n\tbool zombie;\n};\n\nstruct posix_clock_desc {\n\tstruct file *fp;\n\tstruct posix_clock *clk;\n};\n\nstruct __kernel_old_itimerval {\n\tstruct __kernel_old_timeval it_interval;\n\tstruct __kernel_old_timeval it_value;\n};\n\nstruct old_itimerval32 {\n\tstruct old_timeval32 it_interval;\n\tstruct old_timeval32 it_value;\n};\n\nstruct ce_unbind {\n\tstruct clock_event_device *ce;\n\tint res;\n};\n\ntypedef ktime_t pto_T_____19;\n\nstruct proc_timens_offset {\n\tint clockid;\n\tstruct timespec64 val;\n};\n\nunion futex_key {\n\tstruct {\n\t\tu64 i_seq;\n\t\tlong unsigned int pgoff;\n\t\tunsigned int offset;\n\t} shared;\n\tstruct {\n\t\tunion {\n\t\t\tstruct mm_struct *mm;\n\t\t\tu64 __tmp;\n\t\t};\n\t\tlong unsigned int address;\n\t\tunsigned int offset;\n\t} private;\n\tstruct {\n\t\tu64 ptr;\n\t\tlong unsigned int word;\n\t\tunsigned int offset;\n\t} both;\n};\n\nstruct futex_pi_state {\n\tstruct list_head list;\n\tstruct rt_mutex pi_mutex;\n\tstruct task_struct *owner;\n\trefcount_t refcount;\n\tunion futex_key key;\n};\n\nstruct futex_q {\n\tstruct plist_node list;\n\tstruct task_struct *task;\n\tspinlock_t *lock_ptr;\n\tunion futex_key key;\n\tstruct futex_pi_state *pi_state;\n\tstruct rt_mutex_waiter *rt_waiter;\n\tunion futex_key *requeue_pi_key;\n\tu32 bitset;\n};\n\nstruct futex_hash_bucket {\n\tatomic_t waiters;\n\tspinlock_t lock;\n\tstruct plist_head chain;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nenum futex_access {\n\tFUTEX_READ = 0,\n\tFUTEX_WRITE = 1,\n};\n\nstruct dma_chan {\n\tint lock;\n\tconst char *device_id;\n};\n\ntypedef bool (*smp_cond_func_t)(int, void *);\n\nstruct call_function_data {\n\tcall_single_data_t *csd;\n\tcpumask_var_t cpumask;\n\tcpumask_var_t cpumask_ipi;\n};\n\nstruct smp_call_on_cpu_struct {\n\tstruct work_struct work;\n\tstruct completion done;\n\tint (*func)(void *);\n\tvoid *data;\n\tint ret;\n\tint cpu;\n};\n\nstruct latch_tree_root {\n\tseqcount_t seq;\n\tstruct rb_root tree[2];\n};\n\nstruct latch_tree_ops {\n\tbool (*less)(struct latch_tree_node *, struct latch_tree_node *);\n\tint (*comp)(void *, struct latch_tree_node *);\n};\n\nstruct module_use {\n\tstruct list_head source_list;\n\tstruct list_head target_list;\n\tstruct module *source;\n\tstruct module *target;\n};\n\nstruct module_sect_attr {\n\tstruct bin_attribute battr;\n\tlong unsigned int address;\n};\n\nstruct module_sect_attrs {\n\tstruct attribute_group grp;\n\tunsigned int nsections;\n\tstruct module_sect_attr attrs[0];\n};\n\nstruct module_notes_attrs {\n\tstruct kobject *dir;\n\tunsigned int notes;\n\tstruct bin_attribute attrs[0];\n};\n\nstruct symsearch {\n\tconst struct kernel_symbol *start;\n\tconst struct kernel_symbol *stop;\n\tconst s32 *crcs;\n\tenum {\n\t\tNOT_GPL_ONLY = 0,\n\t\tGPL_ONLY = 1,\n\t\tWILL_BE_GPL_ONLY = 2,\n\t} licence;\n\tbool unused;\n};\n\nenum kernel_read_file_id {\n\tREADING_UNKNOWN = 0,\n\tREADING_FIRMWARE = 1,\n\tREADING_FIRMWARE_PREALLOC_BUFFER = 2,\n\tREADING_FIRMWARE_EFI_EMBEDDED = 3,\n\tREADING_MODULE = 4,\n\tREADING_KEXEC_IMAGE = 5,\n\tREADING_KEXEC_INITRAMFS = 6,\n\tREADING_POLICY = 7,\n\tREADING_X509_CERTIFICATE = 8,\n\tREADING_MAX_ID = 9,\n};\n\nenum kernel_load_data_id {\n\tLOADING_UNKNOWN = 0,\n\tLOADING_FIRMWARE = 1,\n\tLOADING_FIRMWARE_PREALLOC_BUFFER = 2,\n\tLOADING_FIRMWARE_EFI_EMBEDDED = 3,\n\tLOADING_MODULE = 4,\n\tLOADING_KEXEC_IMAGE = 5,\n\tLOADING_KEXEC_INITRAMFS = 6,\n\tLOADING_POLICY = 7,\n\tLOADING_X509_CERTIFICATE = 8,\n\tLOADING_MAX_ID = 9,\n};\n\nenum {\n\tPROC_ENTRY_PERMANENT = 1,\n};\n\nstruct _ddebug {\n\tconst char *modname;\n\tconst char *function;\n\tconst char *filename;\n\tconst char *format;\n\tunsigned int lineno: 18;\n\tunsigned int flags: 8;\n\tunion {\n\t\tstruct static_key_true dd_key_true;\n\t\tstruct static_key_false dd_key_false;\n\t} key;\n};\n\nstruct load_info {\n\tconst char *name;\n\tstruct module *mod;\n\tElf64_Ehdr *hdr;\n\tlong unsigned int len;\n\tElf64_Shdr *sechdrs;\n\tchar *secstrings;\n\tchar *strtab;\n\tlong unsigned int symoffs;\n\tlong unsigned int stroffs;\n\tlong unsigned int init_typeoffs;\n\tlong unsigned int core_typeoffs;\n\tstruct _ddebug *debug;\n\tunsigned int num_debug;\n\tbool sig_ok;\n\tlong unsigned int mod_kallsyms_init_off;\n\tstruct {\n\t\tunsigned int sym;\n\t\tunsigned int str;\n\t\tunsigned int mod;\n\t\tunsigned int vers;\n\t\tunsigned int info;\n\t\tunsigned int pcpu;\n\t} index;\n};\n\nstruct trace_event_raw_module_load {\n\tstruct trace_entry ent;\n\tunsigned int taints;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_free {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_refcnt {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tint refcnt;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_module_request {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tbool wait;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_module_load {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_module_free {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_module_refcnt {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_module_request {\n\tu32 name;\n};\n\ntypedef void (*btf_trace_module_load)(void *, struct module *);\n\ntypedef void (*btf_trace_module_free)(void *, struct module *);\n\ntypedef void (*btf_trace_module_get)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_put)(void *, struct module *, long unsigned int);\n\ntypedef void (*btf_trace_module_request)(void *, char *, bool, long unsigned int);\n\nstruct mod_tree_root {\n\tstruct latch_tree_root root;\n\tlong unsigned int addr_min;\n\tlong unsigned int addr_max;\n};\n\nstruct find_symbol_arg {\n\tconst char *name;\n\tbool gplok;\n\tbool warn;\n\tstruct module *owner;\n\tconst s32 *crc;\n\tconst struct kernel_symbol *sym;\n};\n\nstruct mod_initfree {\n\tstruct llist_node node;\n\tvoid *module_init;\n};\n\nstruct kallsym_iter {\n\tloff_t pos;\n\tloff_t pos_arch_end;\n\tloff_t pos_mod_end;\n\tloff_t pos_ftrace_mod_end;\n\tlong unsigned int value;\n\tunsigned int nameoff;\n\tchar type;\n\tchar name[128];\n\tchar module_name[56];\n\tint exported;\n\tint show_value;\n};\n\nenum {\n\tSB_UNFROZEN = 0,\n\tSB_FREEZE_WRITE = 1,\n\tSB_FREEZE_PAGEFAULT = 2,\n\tSB_FREEZE_FS = 3,\n\tSB_FREEZE_COMPLETE = 4,\n};\n\ntypedef __u16 comp_t;\n\ntypedef __u32 comp2_t;\n\nstruct acct {\n\tchar ac_flag;\n\tchar ac_version;\n\t__u16 ac_uid16;\n\t__u16 ac_gid16;\n\t__u16 ac_tty;\n\t__u32 ac_btime;\n\tcomp_t ac_utime;\n\tcomp_t ac_stime;\n\tcomp_t ac_etime;\n\tcomp_t ac_mem;\n\tcomp_t ac_io;\n\tcomp_t ac_rw;\n\tcomp_t ac_minflt;\n\tcomp_t ac_majflt;\n\tcomp_t ac_swaps;\n\t__u16 ac_ahz;\n\t__u32 ac_exitcode;\n\tchar ac_comm[17];\n\t__u8 ac_etime_hi;\n\t__u16 ac_etime_lo;\n\t__u32 ac_uid;\n\t__u32 ac_gid;\n};\n\ntypedef struct acct acct_t;\n\nstruct fs_pin {\n\twait_queue_head_t wait;\n\tint done;\n\tstruct hlist_node s_list;\n\tstruct hlist_node m_list;\n\tvoid (*kill)(struct fs_pin *);\n};\n\nstruct bsd_acct_struct {\n\tstruct fs_pin pin;\n\tatomic_long_t count;\n\tstruct callback_head rcu;\n\tstruct mutex lock;\n\tint active;\n\tlong unsigned int needcheck;\n\tstruct file *file;\n\tstruct pid_namespace *ns;\n\tstruct work_struct work;\n\tstruct completion done;\n};\n\nstruct elf64_note {\n\tElf64_Word n_namesz;\n\tElf64_Word n_descsz;\n\tElf64_Word n_type;\n};\n\ntypedef long unsigned int elf_greg_t;\n\ntypedef elf_greg_t elf_gregset_t[27];\n\nstruct elf_siginfo {\n\tint si_signo;\n\tint si_code;\n\tint si_errno;\n};\n\nstruct elf_prstatus {\n\tstruct elf_siginfo pr_info;\n\tshort int pr_cursig;\n\tlong unsigned int pr_sigpend;\n\tlong unsigned int pr_sighold;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tstruct __kernel_old_timeval pr_utime;\n\tstruct __kernel_old_timeval pr_stime;\n\tstruct __kernel_old_timeval pr_cutime;\n\tstruct __kernel_old_timeval pr_cstime;\n\telf_gregset_t pr_reg;\n\tint pr_fpvalid;\n};\n\nstruct compat_kexec_segment {\n\tcompat_uptr_t buf;\n\tcompat_size_t bufsz;\n\tcompat_ulong_t mem;\n\tcompat_size_t memsz;\n};\n\nenum migrate_reason {\n\tMR_COMPACTION = 0,\n\tMR_MEMORY_FAILURE = 1,\n\tMR_MEMORY_HOTPLUG = 2,\n\tMR_SYSCALL = 3,\n\tMR_MEMPOLICY_MBIND = 4,\n\tMR_NUMA_MISPLACED = 5,\n\tMR_CONTIG_RANGE = 6,\n\tMR_TYPES = 7,\n};\n\ntypedef __kernel_ulong_t __kernel_ino_t;\n\ntypedef __kernel_ino_t ino_t;\n\nenum kernfs_node_type {\n\tKERNFS_DIR = 1,\n\tKERNFS_FILE = 2,\n\tKERNFS_LINK = 4,\n};\n\nenum kernfs_root_flag {\n\tKERNFS_ROOT_CREATE_DEACTIVATED = 1,\n\tKERNFS_ROOT_EXTRA_OPEN_PERM_CHECK = 2,\n\tKERNFS_ROOT_SUPPORT_EXPORTOP = 4,\n\tKERNFS_ROOT_SUPPORT_USER_XATTR = 8,\n};\n\nstruct kernfs_fs_context {\n\tstruct kernfs_root *root;\n\tvoid *ns_tag;\n\tlong unsigned int magic;\n\tbool new_sb_created;\n};\n\nenum {\n\t__PERCPU_REF_ATOMIC = 1,\n\t__PERCPU_REF_DEAD = 2,\n\t__PERCPU_REF_ATOMIC_DEAD = 3,\n\t__PERCPU_REF_FLAG_BITS = 2,\n};\n\nenum bpf_link_type {\n\tBPF_LINK_TYPE_UNSPEC = 0,\n\tBPF_LINK_TYPE_RAW_TRACEPOINT = 1,\n\tBPF_LINK_TYPE_TRACING = 2,\n\tBPF_LINK_TYPE_CGROUP = 3,\n\tBPF_LINK_TYPE_ITER = 4,\n\tBPF_LINK_TYPE_NETNS = 5,\n\tMAX_BPF_LINK_TYPE = 6,\n};\n\nstruct bpf_link_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 prog_id;\n\tunion {\n\t\tstruct {\n\t\t\t__u64 tp_name;\n\t\t\t__u32 tp_name_len;\n\t\t} raw_tracepoint;\n\t\tstruct {\n\t\t\t__u32 attach_type;\n\t\t} tracing;\n\t\tstruct {\n\t\t\t__u64 cgroup_id;\n\t\t\t__u32 attach_type;\n\t\t} cgroup;\n\t\tstruct {\n\t\t\t__u32 netns_ino;\n\t\t\t__u32 attach_type;\n\t\t} netns;\n\t};\n};\n\nstruct bpf_link_ops;\n\nstruct bpf_link {\n\tatomic64_t refcnt;\n\tu32 id;\n\tenum bpf_link_type type;\n\tconst struct bpf_link_ops *ops;\n\tstruct bpf_prog *prog;\n\tstruct work_struct work;\n};\n\nstruct bpf_link_ops {\n\tvoid (*release)(struct bpf_link *);\n\tvoid (*dealloc)(struct bpf_link *);\n\tint (*update_prog)(struct bpf_link *, struct bpf_prog *, struct bpf_prog *);\n\tvoid (*show_fdinfo)(const struct bpf_link *, struct seq_file *);\n\tint (*fill_link_info)(const struct bpf_link *, struct bpf_link_info *);\n};\n\nstruct bpf_cgroup_link {\n\tstruct bpf_link link;\n\tstruct cgroup *cgroup;\n\tenum bpf_attach_type type;\n};\n\nenum {\n\tCSS_NO_REF = 1,\n\tCSS_ONLINE = 2,\n\tCSS_RELEASED = 4,\n\tCSS_VISIBLE = 8,\n\tCSS_DYING = 16,\n};\n\nenum {\n\tCGRP_NOTIFY_ON_RELEASE = 0,\n\tCGRP_CPUSET_CLONE_CHILDREN = 1,\n\tCGRP_FREEZE = 2,\n\tCGRP_FROZEN = 3,\n};\n\nenum {\n\tCGRP_ROOT_NOPREFIX = 2,\n\tCGRP_ROOT_XATTR = 4,\n\tCGRP_ROOT_NS_DELEGATE = 8,\n\tCGRP_ROOT_CPUSET_V2_MODE = 16,\n\tCGRP_ROOT_MEMORY_LOCAL_EVENTS = 32,\n\tCGRP_ROOT_MEMORY_RECURSIVE_PROT = 64,\n};\n\nstruct cgroup_taskset {\n\tstruct list_head src_csets;\n\tstruct list_head dst_csets;\n\tint nr_tasks;\n\tint ssid;\n\tstruct list_head *csets;\n\tstruct css_set *cur_cset;\n\tstruct task_struct *cur_task;\n};\n\nstruct css_task_iter {\n\tstruct cgroup_subsys *ss;\n\tunsigned int flags;\n\tstruct list_head *cset_pos;\n\tstruct list_head *cset_head;\n\tstruct list_head *tcset_pos;\n\tstruct list_head *tcset_head;\n\tstruct list_head *task_pos;\n\tstruct list_head *cur_tasks_head;\n\tstruct css_set *cur_cset;\n\tstruct css_set *cur_dcset;\n\tstruct task_struct *cur_task;\n\tstruct list_head iters_node;\n};\n\nstruct cgroup_fs_context {\n\tstruct kernfs_fs_context kfc;\n\tstruct cgroup_root *root;\n\tstruct cgroup_namespace *ns;\n\tunsigned int flags;\n\tbool cpuset_clone_children;\n\tbool none;\n\tbool all_ss;\n\tu16 subsys_mask;\n\tchar *name;\n\tchar *release_agent;\n};\n\nstruct cgrp_cset_link {\n\tstruct cgroup *cgrp;\n\tstruct css_set *cset;\n\tstruct list_head cset_link;\n\tstruct list_head cgrp_link;\n};\n\nstruct cgroup_mgctx {\n\tstruct list_head preloaded_src_csets;\n\tstruct list_head preloaded_dst_csets;\n\tstruct cgroup_taskset tset;\n\tu16 ss_mask;\n};\n\nstruct trace_event_raw_cgroup_root {\n\tstruct trace_entry ent;\n\tint root;\n\tu16 ss_mask;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup {\n\tstruct trace_entry ent;\n\tint root;\n\tint id;\n\tint level;\n\tu32 __data_loc_path;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_migrate {\n\tstruct trace_entry ent;\n\tint dst_root;\n\tint dst_id;\n\tint dst_level;\n\tint pid;\n\tu32 __data_loc_dst_path;\n\tu32 __data_loc_comm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cgroup_event {\n\tstruct trace_entry ent;\n\tint root;\n\tint id;\n\tint level;\n\tu32 __data_loc_path;\n\tint val;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_cgroup_root {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_cgroup {\n\tu32 path;\n};\n\nstruct trace_event_data_offsets_cgroup_migrate {\n\tu32 dst_path;\n\tu32 comm;\n};\n\nstruct trace_event_data_offsets_cgroup_event {\n\tu32 path;\n};\n\ntypedef void (*btf_trace_cgroup_setup_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_destroy_root)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_remount)(void *, struct cgroup_root *);\n\ntypedef void (*btf_trace_cgroup_mkdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rmdir)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_release)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_rename)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_freeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_unfreeze)(void *, struct cgroup *, const char *);\n\ntypedef void (*btf_trace_cgroup_attach_task)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_transfer_tasks)(void *, struct cgroup *, const char *, struct task_struct *, bool);\n\ntypedef void (*btf_trace_cgroup_notify_populated)(void *, struct cgroup *, const char *, int);\n\ntypedef void (*btf_trace_cgroup_notify_frozen)(void *, struct cgroup *, const char *, int);\n\nenum cgroup2_param {\n\tOpt_nsdelegate = 0,\n\tOpt_memory_localevents = 1,\n\tOpt_memory_recursiveprot = 2,\n\tnr__cgroup2_params = 3,\n};\n\nstruct cgroupstats {\n\t__u64 nr_sleeping;\n\t__u64 nr_running;\n\t__u64 nr_stopped;\n\t__u64 nr_uninterruptible;\n\t__u64 nr_io_wait;\n};\n\nenum cgroup_filetype {\n\tCGROUP_FILE_PROCS = 0,\n\tCGROUP_FILE_TASKS = 1,\n};\n\nstruct cgroup_pidlist {\n\tstruct {\n\t\tenum cgroup_filetype type;\n\t\tstruct pid_namespace *ns;\n\t} key;\n\tpid_t *list;\n\tint length;\n\tstruct list_head links;\n\tstruct cgroup *owner;\n\tstruct delayed_work destroy_dwork;\n};\n\nenum cgroup1_param {\n\tOpt_all = 0,\n\tOpt_clone_children = 1,\n\tOpt_cpuset_v2_mode = 2,\n\tOpt_name = 3,\n\tOpt_none = 4,\n\tOpt_noprefix = 5,\n\tOpt_release_agent = 6,\n\tOpt_xattr = 7,\n};\n\nenum freezer_state_flags {\n\tCGROUP_FREEZER_ONLINE = 1,\n\tCGROUP_FREEZING_SELF = 2,\n\tCGROUP_FREEZING_PARENT = 4,\n\tCGROUP_FROZEN = 8,\n\tCGROUP_FREEZING = 6,\n};\n\nstruct freezer {\n\tstruct cgroup_subsys_state css;\n\tunsigned int state;\n};\n\nstruct fmeter {\n\tint cnt;\n\tint val;\n\ttime64_t time;\n\tspinlock_t lock;\n};\n\nstruct cpuset {\n\tstruct cgroup_subsys_state css;\n\tlong unsigned int flags;\n\tcpumask_var_t cpus_allowed;\n\tnodemask_t mems_allowed;\n\tcpumask_var_t effective_cpus;\n\tnodemask_t effective_mems;\n\tcpumask_var_t subparts_cpus;\n\tnodemask_t old_mems_allowed;\n\tstruct fmeter fmeter;\n\tint attach_in_progress;\n\tint pn;\n\tint relax_domain_level;\n\tint nr_subparts_cpus;\n\tint partition_root_state;\n\tint use_parent_ecpus;\n\tint child_ecpus_count;\n};\n\nstruct tmpmasks {\n\tcpumask_var_t addmask;\n\tcpumask_var_t delmask;\n\tcpumask_var_t new_cpus;\n};\n\ntypedef enum {\n\tCS_ONLINE = 0,\n\tCS_CPU_EXCLUSIVE = 1,\n\tCS_MEM_EXCLUSIVE = 2,\n\tCS_MEM_HARDWALL = 3,\n\tCS_MEMORY_MIGRATE = 4,\n\tCS_SCHED_LOAD_BALANCE = 5,\n\tCS_SPREAD_PAGE = 6,\n\tCS_SPREAD_SLAB = 7,\n} cpuset_flagbits_t;\n\nenum subparts_cmd {\n\tpartcmd_enable = 0,\n\tpartcmd_disable = 1,\n\tpartcmd_update = 2,\n};\n\nstruct cpuset_migrate_mm_work {\n\tstruct work_struct work;\n\tstruct mm_struct *mm;\n\tnodemask_t from;\n\tnodemask_t to;\n};\n\ntypedef enum {\n\tFILE_MEMORY_MIGRATE = 0,\n\tFILE_CPULIST = 1,\n\tFILE_MEMLIST = 2,\n\tFILE_EFFECTIVE_CPULIST = 3,\n\tFILE_EFFECTIVE_MEMLIST = 4,\n\tFILE_SUBPARTS_CPULIST = 5,\n\tFILE_CPU_EXCLUSIVE = 6,\n\tFILE_MEM_EXCLUSIVE = 7,\n\tFILE_MEM_HARDWALL = 8,\n\tFILE_SCHED_LOAD_BALANCE = 9,\n\tFILE_PARTITION_ROOT = 10,\n\tFILE_SCHED_RELAX_DOMAIN_LEVEL = 11,\n\tFILE_MEMORY_PRESSURE_ENABLED = 12,\n\tFILE_MEMORY_PRESSURE = 13,\n\tFILE_SPREAD_PAGE = 14,\n\tFILE_SPREAD_SLAB = 15,\n} cpuset_filetype_t;\n\nstruct cpu_stop_done {\n\tatomic_t nr_todo;\n\tint ret;\n\tstruct completion completion;\n};\n\nstruct cpu_stopper {\n\tstruct task_struct *thread;\n\traw_spinlock_t lock;\n\tbool enabled;\n\tstruct list_head works;\n\tstruct cpu_stop_work stop_work;\n};\n\nenum multi_stop_state {\n\tMULTI_STOP_NONE = 0,\n\tMULTI_STOP_PREPARE = 1,\n\tMULTI_STOP_DISABLE_IRQ = 2,\n\tMULTI_STOP_RUN = 3,\n\tMULTI_STOP_EXIT = 4,\n};\n\nstruct multi_stop_data {\n\tcpu_stop_fn_t fn;\n\tvoid *data;\n\tunsigned int num_threads;\n\tconst struct cpumask *active_cpus;\n\tenum multi_stop_state state;\n\tatomic_t thread_ack;\n};\n\ntypedef int __kernel_mqd_t;\n\ntypedef __kernel_mqd_t mqd_t;\n\nenum audit_state {\n\tAUDIT_DISABLED = 0,\n\tAUDIT_BUILD_CONTEXT = 1,\n\tAUDIT_RECORD_CONTEXT = 2,\n};\n\nstruct audit_cap_data {\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n\tunion {\n\t\tunsigned int fE;\n\t\tkernel_cap_t effective;\n\t};\n\tkernel_cap_t ambient;\n\tkuid_t rootid;\n};\n\nstruct audit_names {\n\tstruct list_head list;\n\tstruct filename *name;\n\tint name_len;\n\tbool hidden;\n\tlong unsigned int ino;\n\tdev_t dev;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tdev_t rdev;\n\tu32 osid;\n\tstruct audit_cap_data fcap;\n\tunsigned int fcap_ver;\n\tunsigned char type;\n\tbool should_free;\n};\n\nstruct mq_attr {\n\t__kernel_long_t mq_flags;\n\t__kernel_long_t mq_maxmsg;\n\t__kernel_long_t mq_msgsize;\n\t__kernel_long_t mq_curmsgs;\n\t__kernel_long_t __reserved[4];\n};\n\nstruct audit_proctitle {\n\tint len;\n\tchar *value;\n};\n\nstruct audit_aux_data;\n\nstruct audit_tree_refs;\n\nstruct audit_context {\n\tint dummy;\n\tint in_syscall;\n\tenum audit_state state;\n\tenum audit_state current_state;\n\tunsigned int serial;\n\tint major;\n\tstruct timespec64 ctime;\n\tlong unsigned int argv[4];\n\tlong int return_code;\n\tu64 prio;\n\tint return_valid;\n\tstruct audit_names preallocated_names[5];\n\tint name_count;\n\tstruct list_head names_list;\n\tchar *filterkey;\n\tstruct path pwd;\n\tstruct audit_aux_data *aux;\n\tstruct audit_aux_data *aux_pids;\n\tstruct __kernel_sockaddr_storage *sockaddr;\n\tsize_t sockaddr_len;\n\tpid_t pid;\n\tpid_t ppid;\n\tkuid_t uid;\n\tkuid_t euid;\n\tkuid_t suid;\n\tkuid_t fsuid;\n\tkgid_t gid;\n\tkgid_t egid;\n\tkgid_t sgid;\n\tkgid_t fsgid;\n\tlong unsigned int personality;\n\tint arch;\n\tpid_t target_pid;\n\tkuid_t target_auid;\n\tkuid_t target_uid;\n\tunsigned int target_sessionid;\n\tu32 target_sid;\n\tchar target_comm[16];\n\tstruct audit_tree_refs *trees;\n\tstruct audit_tree_refs *first_trees;\n\tstruct list_head killed_trees;\n\tint tree_count;\n\tint type;\n\tunion {\n\t\tstruct {\n\t\t\tint nargs;\n\t\t\tlong int args[6];\n\t\t} socketcall;\n\t\tstruct {\n\t\t\tkuid_t uid;\n\t\t\tkgid_t gid;\n\t\t\tumode_t mode;\n\t\t\tu32 osid;\n\t\t\tint has_perm;\n\t\t\tuid_t perm_uid;\n\t\t\tgid_t perm_gid;\n\t\t\tumode_t perm_mode;\n\t\t\tlong unsigned int qbytes;\n\t\t} ipc;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tstruct mq_attr mqstat;\n\t\t} mq_getsetattr;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tint sigev_signo;\n\t\t} mq_notify;\n\t\tstruct {\n\t\t\tmqd_t mqdes;\n\t\t\tsize_t msg_len;\n\t\t\tunsigned int msg_prio;\n\t\t\tstruct timespec64 abs_timeout;\n\t\t} mq_sendrecv;\n\t\tstruct {\n\t\t\tint oflag;\n\t\t\tumode_t mode;\n\t\t\tstruct mq_attr attr;\n\t\t} mq_open;\n\t\tstruct {\n\t\t\tpid_t pid;\n\t\t\tstruct audit_cap_data cap;\n\t\t} capset;\n\t\tstruct {\n\t\t\tint fd;\n\t\t\tint flags;\n\t\t} mmap;\n\t\tstruct {\n\t\t\tint argc;\n\t\t} execve;\n\t\tstruct {\n\t\t\tchar *name;\n\t\t} module;\n\t};\n\tint fds[2];\n\tstruct audit_proctitle proctitle;\n};\n\nenum audit_nlgrps {\n\tAUDIT_NLGRP_NONE = 0,\n\tAUDIT_NLGRP_READLOG = 1,\n\t__AUDIT_NLGRP_MAX = 2,\n};\n\nstruct audit_status {\n\t__u32 mask;\n\t__u32 enabled;\n\t__u32 failure;\n\t__u32 pid;\n\t__u32 rate_limit;\n\t__u32 backlog_limit;\n\t__u32 lost;\n\t__u32 backlog;\n\tunion {\n\t\t__u32 version;\n\t\t__u32 feature_bitmap;\n\t};\n\t__u32 backlog_wait_time;\n};\n\nstruct audit_features {\n\t__u32 vers;\n\t__u32 mask;\n\t__u32 features;\n\t__u32 lock;\n};\n\nstruct audit_tty_status {\n\t__u32 enabled;\n\t__u32 log_passwd;\n};\n\nstruct audit_sig_info {\n\tuid_t uid;\n\tpid_t pid;\n\tchar ctx[0];\n};\n\nstruct net_generic {\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int len;\n\t\t\tstruct callback_head rcu;\n\t\t} s;\n\t\tvoid *ptr[0];\n\t};\n};\n\nstruct scm_creds {\n\tu32 pid;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct netlink_skb_parms {\n\tstruct scm_creds creds;\n\t__u32 portid;\n\t__u32 dst_group;\n\t__u32 flags;\n\tstruct sock *sk;\n\tbool nsid_is_set;\n\tint nsid;\n};\n\nstruct netlink_kernel_cfg {\n\tunsigned int groups;\n\tunsigned int flags;\n\tvoid (*input)(struct sk_buff *);\n\tstruct mutex *cb_mutex;\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tbool (*compare)(struct net *, struct sock *);\n};\n\nstruct audit_netlink_list {\n\t__u32 portid;\n\tstruct net *net;\n\tstruct sk_buff_head q;\n};\n\nstruct audit_net {\n\tstruct sock *sk;\n};\n\nstruct auditd_connection {\n\tstruct pid *pid;\n\tu32 portid;\n\tstruct net *net;\n\tstruct callback_head rcu;\n};\n\nstruct audit_ctl_mutex {\n\tstruct mutex lock;\n\tvoid *owner;\n};\n\nstruct audit_buffer {\n\tstruct sk_buff *skb;\n\tstruct audit_context *ctx;\n\tgfp_t gfp_mask;\n};\n\nstruct audit_reply {\n\t__u32 portid;\n\tstruct net *net;\n\tstruct sk_buff *skb;\n};\n\nenum {\n\tAudit_equal = 0,\n\tAudit_not_equal = 1,\n\tAudit_bitmask = 2,\n\tAudit_bittest = 3,\n\tAudit_lt = 4,\n\tAudit_gt = 5,\n\tAudit_le = 6,\n\tAudit_ge = 7,\n\tAudit_bad = 8,\n};\n\nstruct audit_rule_data {\n\t__u32 flags;\n\t__u32 action;\n\t__u32 field_count;\n\t__u32 mask[64];\n\t__u32 fields[64];\n\t__u32 values[64];\n\t__u32 fieldflags[64];\n\t__u32 buflen;\n\tchar buf[0];\n};\n\nstruct audit_field;\n\nstruct audit_watch;\n\nstruct audit_tree;\n\nstruct audit_fsnotify_mark;\n\nstruct audit_krule {\n\tu32 pflags;\n\tu32 flags;\n\tu32 listnr;\n\tu32 action;\n\tu32 mask[64];\n\tu32 buflen;\n\tu32 field_count;\n\tchar *filterkey;\n\tstruct audit_field *fields;\n\tstruct audit_field *arch_f;\n\tstruct audit_field *inode_f;\n\tstruct audit_watch *watch;\n\tstruct audit_tree *tree;\n\tstruct audit_fsnotify_mark *exe;\n\tstruct list_head rlist;\n\tstruct list_head list;\n\tu64 prio;\n};\n\nstruct audit_field {\n\tu32 type;\n\tunion {\n\t\tu32 val;\n\t\tkuid_t uid;\n\t\tkgid_t gid;\n\t\tstruct {\n\t\t\tchar *lsm_str;\n\t\t\tvoid *lsm_rule;\n\t\t};\n\t};\n\tu32 op;\n};\n\nstruct audit_entry {\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tstruct audit_krule rule;\n};\n\nstruct audit_buffer___2;\n\ntypedef int __kernel_key_t;\n\ntypedef __kernel_key_t key_t;\n\nstruct cpu_vfs_cap_data {\n\t__u32 magic_etc;\n\tkernel_cap_t permitted;\n\tkernel_cap_t inheritable;\n\tkuid_t rootid;\n};\n\nstruct kern_ipc_perm {\n\tspinlock_t lock;\n\tbool deleted;\n\tint id;\n\tkey_t key;\n\tkuid_t uid;\n\tkgid_t gid;\n\tkuid_t cuid;\n\tkgid_t cgid;\n\tumode_t mode;\n\tlong unsigned int seq;\n\tvoid *security;\n\tstruct rhash_head khtnode;\n\tstruct callback_head rcu;\n\trefcount_t refcount;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef struct fsnotify_mark_connector *fsnotify_connp_t;\n\nstruct fsnotify_mark_connector {\n\tspinlock_t lock;\n\tshort unsigned int type;\n\tshort unsigned int flags;\n\t__kernel_fsid_t fsid;\n\tunion {\n\t\tfsnotify_connp_t *obj;\n\t\tstruct fsnotify_mark_connector *destroy_next;\n\t};\n\tstruct hlist_head list;\n};\n\nenum audit_nfcfgop {\n\tAUDIT_XT_OP_REGISTER = 0,\n\tAUDIT_XT_OP_REPLACE = 1,\n\tAUDIT_XT_OP_UNREGISTER = 2,\n};\n\nenum fsnotify_obj_type {\n\tFSNOTIFY_OBJ_TYPE_INODE = 0,\n\tFSNOTIFY_OBJ_TYPE_VFSMOUNT = 1,\n\tFSNOTIFY_OBJ_TYPE_SB = 2,\n\tFSNOTIFY_OBJ_TYPE_COUNT = 3,\n\tFSNOTIFY_OBJ_TYPE_DETACHED = 3,\n};\n\nstruct audit_aux_data {\n\tstruct audit_aux_data *next;\n\tint type;\n};\n\nstruct audit_chunk;\n\nstruct audit_tree_refs {\n\tstruct audit_tree_refs *next;\n\tstruct audit_chunk *c[31];\n};\n\nstruct audit_aux_data_pids {\n\tstruct audit_aux_data d;\n\tpid_t target_pid[16];\n\tkuid_t target_auid[16];\n\tkuid_t target_uid[16];\n\tunsigned int target_sessionid[16];\n\tu32 target_sid[16];\n\tchar target_comm[256];\n\tint pid_count;\n};\n\nstruct audit_aux_data_bprm_fcaps {\n\tstruct audit_aux_data d;\n\tstruct audit_cap_data fcap;\n\tunsigned int fcap_ver;\n\tstruct audit_cap_data old_pcap;\n\tstruct audit_cap_data new_pcap;\n};\n\nstruct audit_nfcfgop_tab {\n\tenum audit_nfcfgop op;\n\tconst char *s;\n};\n\nstruct audit_parent;\n\nstruct audit_watch {\n\trefcount_t count;\n\tdev_t dev;\n\tchar *path;\n\tlong unsigned int ino;\n\tstruct audit_parent *parent;\n\tstruct list_head wlist;\n\tstruct list_head rules;\n};\n\nstruct fsnotify_group;\n\nstruct fsnotify_iter_info;\n\nstruct fsnotify_mark;\n\nstruct fsnotify_event;\n\nstruct fsnotify_ops {\n\tint (*handle_event)(struct fsnotify_group *, struct inode *, u32, const void *, int, const struct qstr *, u32, struct fsnotify_iter_info *);\n\tvoid (*free_group_priv)(struct fsnotify_group *);\n\tvoid (*freeing_mark)(struct fsnotify_mark *, struct fsnotify_group *);\n\tvoid (*free_event)(struct fsnotify_event *);\n\tvoid (*free_mark)(struct fsnotify_mark *);\n};\n\nstruct inotify_group_private_data {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n\tstruct ucounts *ucounts;\n};\n\nstruct fsnotify_group {\n\tconst struct fsnotify_ops *ops;\n\trefcount_t refcnt;\n\tspinlock_t notification_lock;\n\tstruct list_head notification_list;\n\twait_queue_head_t notification_waitq;\n\tunsigned int q_len;\n\tunsigned int max_events;\n\tunsigned int priority;\n\tbool shutdown;\n\tstruct mutex mark_mutex;\n\tatomic_t num_marks;\n\tatomic_t user_waits;\n\tstruct list_head marks_list;\n\tstruct fasync_struct *fsn_fa;\n\tstruct fsnotify_event *overflow_event;\n\tstruct mem_cgroup *memcg;\n\tunion {\n\t\tvoid *private;\n\t\tstruct inotify_group_private_data inotify_data;\n\t};\n};\n\nstruct fsnotify_iter_info {\n\tstruct fsnotify_mark *marks[3];\n\tunsigned int report_mask;\n\tint srcu_idx;\n};\n\nstruct fsnotify_mark {\n\t__u32 mask;\n\trefcount_t refcnt;\n\tstruct fsnotify_group *group;\n\tstruct list_head g_list;\n\tspinlock_t lock;\n\tstruct hlist_node obj_list;\n\tstruct fsnotify_mark_connector *connector;\n\t__u32 ignored_mask;\n\tunsigned int flags;\n};\n\nstruct fsnotify_event {\n\tstruct list_head list;\n\tlong unsigned int objectid;\n};\n\nenum fsnotify_data_type {\n\tFSNOTIFY_EVENT_NONE = 0,\n\tFSNOTIFY_EVENT_PATH = 1,\n\tFSNOTIFY_EVENT_INODE = 2,\n};\n\nstruct audit_parent {\n\tstruct list_head watches;\n\tstruct fsnotify_mark mark;\n};\n\nstruct audit_fsnotify_mark {\n\tdev_t dev;\n\tlong unsigned int ino;\n\tchar *path;\n\tstruct fsnotify_mark mark;\n\tstruct audit_krule *rule;\n};\n\nstruct audit_chunk___2;\n\nstruct audit_tree {\n\trefcount_t count;\n\tint goner;\n\tstruct audit_chunk___2 *root;\n\tstruct list_head chunks;\n\tstruct list_head rules;\n\tstruct list_head list;\n\tstruct list_head same_root;\n\tstruct callback_head head;\n\tchar pathname[0];\n};\n\nstruct node___2 {\n\tstruct list_head list;\n\tstruct audit_tree *owner;\n\tunsigned int index;\n};\n\nstruct audit_chunk___2 {\n\tstruct list_head hash;\n\tlong unsigned int key;\n\tstruct fsnotify_mark *mark;\n\tstruct list_head trees;\n\tint count;\n\tatomic_long_t refs;\n\tstruct callback_head head;\n\tstruct node___2 owners[0];\n};\n\nstruct audit_tree_mark {\n\tstruct fsnotify_mark mark;\n\tstruct audit_chunk___2 *chunk;\n};\n\nenum {\n\tHASH_SIZE = 128,\n};\n\nstruct kprobe_blacklist_entry {\n\tstruct list_head list;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n};\n\nstruct kprobe_insn_page {\n\tstruct list_head list;\n\tkprobe_opcode_t *insns;\n\tstruct kprobe_insn_cache *cache;\n\tint nused;\n\tint ngarbage;\n\tchar slot_used[0];\n};\n\nenum kprobe_slot_state {\n\tSLOT_CLEAN = 0,\n\tSLOT_DIRTY = 1,\n\tSLOT_USED = 2,\n};\n\nstruct seccomp_notif_sizes {\n\t__u16 seccomp_notif;\n\t__u16 seccomp_notif_resp;\n\t__u16 seccomp_data;\n};\n\nstruct seccomp_notif {\n\t__u64 id;\n\t__u32 pid;\n\t__u32 flags;\n\tstruct seccomp_data data;\n};\n\nstruct seccomp_notif_resp {\n\t__u64 id;\n\t__s64 val;\n\t__s32 error;\n\t__u32 flags;\n};\n\nstruct notification;\n\nstruct seccomp_filter {\n\trefcount_t usage;\n\tbool log;\n\tstruct seccomp_filter *prev;\n\tstruct bpf_prog *prog;\n\tstruct notification *notif;\n\tstruct mutex notify_lock;\n};\n\nstruct ctl_path {\n\tconst char *procname;\n};\n\nstruct sock_fprog {\n\tshort unsigned int len;\n\tstruct sock_filter *filter;\n};\n\nstruct compat_sock_fprog {\n\tu16 len;\n\tcompat_uptr_t filter;\n};\n\nenum notify_state {\n\tSECCOMP_NOTIFY_INIT = 0,\n\tSECCOMP_NOTIFY_SENT = 1,\n\tSECCOMP_NOTIFY_REPLIED = 2,\n};\n\nstruct seccomp_knotif {\n\tstruct task_struct *task;\n\tu64 id;\n\tconst struct seccomp_data *data;\n\tenum notify_state state;\n\tint error;\n\tlong int val;\n\tu32 flags;\n\tstruct completion ready;\n\tstruct list_head list;\n};\n\nstruct notification {\n\tstruct semaphore request;\n\tu64 next_id;\n\tstruct list_head notifications;\n\twait_queue_head_t wqh;\n};\n\nstruct seccomp_log_name {\n\tu32 log;\n\tconst char *name;\n};\n\nstruct rchan;\n\nstruct rchan_buf {\n\tvoid *start;\n\tvoid *data;\n\tsize_t offset;\n\tsize_t subbufs_produced;\n\tsize_t subbufs_consumed;\n\tstruct rchan *chan;\n\twait_queue_head_t read_wait;\n\tstruct irq_work wakeup_work;\n\tstruct dentry *dentry;\n\tstruct kref kref;\n\tstruct page **page_array;\n\tunsigned int page_count;\n\tunsigned int finalized;\n\tsize_t *padding;\n\tsize_t prev_padding;\n\tsize_t bytes_consumed;\n\tsize_t early_bytes;\n\tunsigned int cpu;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rchan_callbacks;\n\nstruct rchan {\n\tu32 version;\n\tsize_t subbuf_size;\n\tsize_t n_subbufs;\n\tsize_t alloc_size;\n\tstruct rchan_callbacks *cb;\n\tstruct kref kref;\n\tvoid *private_data;\n\tsize_t last_toobig;\n\tstruct rchan_buf **buf;\n\tint is_global;\n\tstruct list_head list;\n\tstruct dentry *parent;\n\tint has_base_filename;\n\tchar base_filename[255];\n};\n\nstruct rchan_callbacks {\n\tint (*subbuf_start)(struct rchan_buf *, void *, void *, size_t);\n\tvoid (*buf_mapped)(struct rchan_buf *, struct file *);\n\tvoid (*buf_unmapped)(struct rchan_buf *, struct file *);\n\tstruct dentry * (*create_buf_file)(const char *, struct dentry *, umode_t, struct rchan_buf *, int *);\n\tint (*remove_buf_file)(struct dentry *);\n};\n\nstruct partial_page {\n\tunsigned int offset;\n\tunsigned int len;\n\tlong unsigned int private;\n};\n\nstruct splice_pipe_desc {\n\tstruct page **pages;\n\tstruct partial_page *partial;\n\tint nr_pages;\n\tunsigned int nr_pages_max;\n\tconst struct pipe_buf_operations *ops;\n\tvoid (*spd_release)(struct splice_pipe_desc *, unsigned int);\n};\n\nstruct rchan_percpu_buf_dispatcher {\n\tstruct rchan_buf *buf;\n\tstruct dentry *dentry;\n};\n\nenum {\n\tTASKSTATS_TYPE_UNSPEC = 0,\n\tTASKSTATS_TYPE_PID = 1,\n\tTASKSTATS_TYPE_TGID = 2,\n\tTASKSTATS_TYPE_STATS = 3,\n\tTASKSTATS_TYPE_AGGR_PID = 4,\n\tTASKSTATS_TYPE_AGGR_TGID = 5,\n\tTASKSTATS_TYPE_NULL = 6,\n\t__TASKSTATS_TYPE_MAX = 7,\n};\n\nenum {\n\tTASKSTATS_CMD_ATTR_UNSPEC = 0,\n\tTASKSTATS_CMD_ATTR_PID = 1,\n\tTASKSTATS_CMD_ATTR_TGID = 2,\n\tTASKSTATS_CMD_ATTR_REGISTER_CPUMASK = 3,\n\tTASKSTATS_CMD_ATTR_DEREGISTER_CPUMASK = 4,\n\t__TASKSTATS_CMD_ATTR_MAX = 5,\n};\n\nenum {\n\tCGROUPSTATS_CMD_UNSPEC = 3,\n\tCGROUPSTATS_CMD_GET = 4,\n\tCGROUPSTATS_CMD_NEW = 5,\n\t__CGROUPSTATS_CMD_MAX = 6,\n};\n\nenum {\n\tCGROUPSTATS_TYPE_UNSPEC = 0,\n\tCGROUPSTATS_TYPE_CGROUP_STATS = 1,\n\t__CGROUPSTATS_TYPE_MAX = 2,\n};\n\nenum {\n\tCGROUPSTATS_CMD_ATTR_UNSPEC = 0,\n\tCGROUPSTATS_CMD_ATTR_FD = 1,\n\t__CGROUPSTATS_CMD_ATTR_MAX = 2,\n};\n\nstruct genlmsghdr {\n\t__u8 cmd;\n\t__u8 version;\n\t__u16 reserved;\n};\n\nenum {\n\tNLA_UNSPEC = 0,\n\tNLA_U8 = 1,\n\tNLA_U16 = 2,\n\tNLA_U32 = 3,\n\tNLA_U64 = 4,\n\tNLA_STRING = 5,\n\tNLA_FLAG = 6,\n\tNLA_MSECS = 7,\n\tNLA_NESTED = 8,\n\tNLA_NESTED_ARRAY = 9,\n\tNLA_NUL_STRING = 10,\n\tNLA_BINARY = 11,\n\tNLA_S8 = 12,\n\tNLA_S16 = 13,\n\tNLA_S32 = 14,\n\tNLA_S64 = 15,\n\tNLA_BITFIELD32 = 16,\n\tNLA_REJECT = 17,\n\tNLA_EXACT_LEN = 18,\n\tNLA_MIN_LEN = 19,\n\t__NLA_TYPE_MAX = 20,\n};\n\nenum netlink_validation {\n\tNL_VALIDATE_LIBERAL = 0,\n\tNL_VALIDATE_TRAILING = 1,\n\tNL_VALIDATE_MAXTYPE = 2,\n\tNL_VALIDATE_UNSPEC = 4,\n\tNL_VALIDATE_STRICT_ATTRS = 8,\n\tNL_VALIDATE_NESTED = 16,\n};\n\nstruct genl_multicast_group {\n\tchar name[16];\n};\n\nstruct genl_ops;\n\nstruct genl_info;\n\nstruct genl_family {\n\tint id;\n\tunsigned int hdrsize;\n\tchar name[16];\n\tunsigned int version;\n\tunsigned int maxattr;\n\tbool netnsok;\n\tbool parallel_ops;\n\tconst struct nla_policy *policy;\n\tint (*pre_doit)(const struct genl_ops *, struct sk_buff *, struct genl_info *);\n\tvoid (*post_doit)(const struct genl_ops *, struct sk_buff *, struct genl_info *);\n\tconst struct genl_ops *ops;\n\tconst struct genl_multicast_group *mcgrps;\n\tunsigned int n_ops;\n\tunsigned int n_mcgrps;\n\tunsigned int mcgrp_offset;\n\tstruct module *module;\n};\n\nstruct genl_ops {\n\tint (*doit)(struct sk_buff *, struct genl_info *);\n\tint (*start)(struct netlink_callback *);\n\tint (*dumpit)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tu8 cmd;\n\tu8 internal_flags;\n\tu8 flags;\n\tu8 validate;\n};\n\nstruct genl_info {\n\tu32 snd_seq;\n\tu32 snd_portid;\n\tstruct nlmsghdr *nlhdr;\n\tstruct genlmsghdr *genlhdr;\n\tvoid *userhdr;\n\tstruct nlattr **attrs;\n\tpossible_net_t _net;\n\tvoid *user_ptr[2];\n\tstruct netlink_ext_ack *extack;\n};\n\nenum genl_validate_flags {\n\tGENL_DONT_VALIDATE_STRICT = 1,\n\tGENL_DONT_VALIDATE_DUMP = 2,\n\tGENL_DONT_VALIDATE_DUMP_STRICT = 4,\n};\n\nstruct listener {\n\tstruct list_head list;\n\tpid_t pid;\n\tchar valid;\n};\n\nstruct listener_list {\n\tstruct rw_semaphore sem;\n\tstruct list_head list;\n};\n\nenum actions {\n\tREGISTER = 0,\n\tDEREGISTER = 1,\n\tCPU_DONT_CARE = 2,\n};\n\nstruct tp_module {\n\tstruct list_head list;\n\tstruct module *mod;\n};\n\nstruct tp_probes {\n\tstruct callback_head rcu;\n\tstruct tracepoint_func probes[0];\n};\n\nenum ring_buffer_type {\n\tRINGBUF_TYPE_DATA_TYPE_LEN_MAX = 28,\n\tRINGBUF_TYPE_PADDING = 29,\n\tRINGBUF_TYPE_TIME_EXTEND = 30,\n\tRINGBUF_TYPE_TIME_STAMP = 31,\n};\n\nenum ring_buffer_flags {\n\tRB_FL_OVERWRITE = 1,\n};\n\nstruct ring_buffer_per_cpu;\n\nstruct buffer_page;\n\nstruct ring_buffer_iter {\n\tstruct ring_buffer_per_cpu *cpu_buffer;\n\tlong unsigned int head;\n\tlong unsigned int next_event;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *cache_reader_page;\n\tlong unsigned int cache_read;\n\tu64 read_stamp;\n\tu64 page_stamp;\n\tstruct ring_buffer_event *event;\n\tint missed_events;\n};\n\nstruct rb_irq_work {\n\tstruct irq_work work;\n\twait_queue_head_t waiters;\n\twait_queue_head_t full_waiters;\n\tbool waiters_pending;\n\tbool full_waiters_pending;\n\tbool wakeup_full;\n};\n\nstruct trace_buffer___2 {\n\tunsigned int flags;\n\tint cpus;\n\tatomic_t record_disabled;\n\tcpumask_var_t cpumask;\n\tstruct lock_class_key *reader_lock_key;\n\tstruct mutex mutex;\n\tstruct ring_buffer_per_cpu **buffers;\n\tstruct hlist_node node;\n\tu64 (*clock)();\n\tstruct rb_irq_work irq_work;\n\tbool time_stamp_abs;\n};\n\nenum {\n\tRB_LEN_TIME_EXTEND = 8,\n\tRB_LEN_TIME_STAMP = 8,\n};\n\nstruct buffer_data_page {\n\tu64 time_stamp;\n\tlocal_t commit;\n\tunsigned char data[0];\n};\n\nstruct buffer_page {\n\tstruct list_head list;\n\tlocal_t write;\n\tunsigned int read;\n\tlocal_t entries;\n\tlong unsigned int real_end;\n\tstruct buffer_data_page *page;\n};\n\nstruct rb_event_info {\n\tu64 ts;\n\tu64 delta;\n\tlong unsigned int length;\n\tstruct buffer_page *tail_page;\n\tint add_timestamp;\n};\n\nenum {\n\tRB_CTX_NMI = 0,\n\tRB_CTX_IRQ = 1,\n\tRB_CTX_SOFTIRQ = 2,\n\tRB_CTX_NORMAL = 3,\n\tRB_CTX_MAX = 4,\n};\n\nstruct ring_buffer_per_cpu {\n\tint cpu;\n\tatomic_t record_disabled;\n\tatomic_t resize_disabled;\n\tstruct trace_buffer___2 *buffer;\n\traw_spinlock_t reader_lock;\n\tarch_spinlock_t lock;\n\tstruct lock_class_key lock_key;\n\tstruct buffer_data_page *free_page;\n\tlong unsigned int nr_pages;\n\tunsigned int current_context;\n\tstruct list_head *pages;\n\tstruct buffer_page *head_page;\n\tstruct buffer_page *tail_page;\n\tstruct buffer_page *commit_page;\n\tstruct buffer_page *reader_page;\n\tlong unsigned int lost_events;\n\tlong unsigned int last_overrun;\n\tlong unsigned int nest;\n\tlocal_t entries_bytes;\n\tlocal_t entries;\n\tlocal_t overrun;\n\tlocal_t commit_overrun;\n\tlocal_t dropped_events;\n\tlocal_t committing;\n\tlocal_t commits;\n\tlocal_t pages_touched;\n\tlocal_t pages_read;\n\tlong int last_pages_touch;\n\tsize_t shortest_full;\n\tlong unsigned int read;\n\tlong unsigned int read_bytes;\n\tu64 write_stamp;\n\tu64 read_stamp;\n\tlong int nr_pages_to_update;\n\tstruct list_head new_pages;\n\tstruct work_struct update_pages_work;\n\tstruct completion update_done;\n\tstruct rb_irq_work irq_work;\n};\n\nstruct trace_export {\n\tstruct trace_export *next;\n\tvoid (*write)(struct trace_export *, const void *, unsigned int);\n};\n\nstruct prog_entry;\n\nstruct event_filter {\n\tstruct prog_entry *prog;\n\tchar *filter_string;\n};\n\nstruct trace_array_cpu;\n\nstruct array_buffer {\n\tstruct trace_array *tr;\n\tstruct trace_buffer *buffer;\n\tstruct trace_array_cpu *data;\n\tu64 time_start;\n\tint cpu;\n};\n\nstruct trace_pid_list;\n\nstruct trace_options;\n\nstruct trace_array {\n\tstruct list_head list;\n\tchar *name;\n\tstruct array_buffer array_buffer;\n\tstruct trace_pid_list *filtered_pids;\n\tstruct trace_pid_list *filtered_no_pids;\n\tarch_spinlock_t max_lock;\n\tint buffer_disabled;\n\tint stop_count;\n\tint clock_id;\n\tint nr_topts;\n\tbool clear_trace;\n\tint buffer_percent;\n\tunsigned int n_err_log_entries;\n\tstruct tracer *current_trace;\n\tunsigned int trace_flags;\n\tunsigned char trace_flags_index[32];\n\tunsigned int flags;\n\traw_spinlock_t start_lock;\n\tstruct list_head err_log;\n\tstruct dentry *dir;\n\tstruct dentry *options;\n\tstruct dentry *percpu_dir;\n\tstruct dentry *event_dir;\n\tstruct trace_options *topts;\n\tstruct list_head systems;\n\tstruct list_head events;\n\tstruct trace_event_file *trace_marker_file;\n\tcpumask_var_t tracing_cpumask;\n\tint ref;\n\tint time_stamp_abs_ref;\n\tstruct list_head hist_vars;\n};\n\nstruct tracer_flags;\n\nstruct tracer {\n\tconst char *name;\n\tint (*init)(struct trace_array *);\n\tvoid (*reset)(struct trace_array *);\n\tvoid (*start)(struct trace_array *);\n\tvoid (*stop)(struct trace_array *);\n\tint (*update_thresh)(struct trace_array *);\n\tvoid (*open)(struct trace_iterator *);\n\tvoid (*pipe_open)(struct trace_iterator *);\n\tvoid (*close)(struct trace_iterator *);\n\tvoid (*pipe_close)(struct trace_iterator *);\n\tssize_t (*read)(struct trace_iterator *, struct file *, char *, size_t, loff_t *);\n\tssize_t (*splice_read)(struct trace_iterator *, struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int);\n\tvoid (*print_header)(struct seq_file *);\n\tenum print_line_t (*print_line)(struct trace_iterator *);\n\tint (*set_flag)(struct trace_array *, u32, u32, int);\n\tint (*flag_changed)(struct trace_array *, u32, int);\n\tstruct tracer *next;\n\tstruct tracer_flags *flags;\n\tint enabled;\n\tint ref;\n\tbool print_max;\n\tbool allow_instances;\n\tbool noboot;\n};\n\nenum trace_iter_flags {\n\tTRACE_FILE_LAT_FMT = 1,\n\tTRACE_FILE_ANNOTATE = 2,\n\tTRACE_FILE_TIME_IN_NS = 4,\n};\n\nstruct event_subsystem;\n\nstruct trace_subsystem_dir {\n\tstruct list_head list;\n\tstruct event_subsystem *subsystem;\n\tstruct trace_array *tr;\n\tstruct dentry *entry;\n\tint ref_count;\n\tint nr_events;\n};\n\nenum event_trigger_type {\n\tETT_NONE = 0,\n\tETT_TRACE_ONOFF = 1,\n\tETT_SNAPSHOT = 2,\n\tETT_STACKTRACE = 4,\n\tETT_EVENT_ENABLE = 8,\n\tETT_EVENT_HIST = 16,\n\tETT_HIST_ENABLE = 32,\n};\n\nenum trace_type {\n\t__TRACE_FIRST_TYPE = 0,\n\tTRACE_FN = 1,\n\tTRACE_CTX = 2,\n\tTRACE_WAKE = 3,\n\tTRACE_STACK = 4,\n\tTRACE_PRINT = 5,\n\tTRACE_BPRINT = 6,\n\tTRACE_MMIO_RW = 7,\n\tTRACE_MMIO_MAP = 8,\n\tTRACE_BRANCH = 9,\n\tTRACE_GRAPH_RET = 10,\n\tTRACE_GRAPH_ENT = 11,\n\tTRACE_USER_STACK = 12,\n\tTRACE_BLK = 13,\n\tTRACE_BPUTS = 14,\n\tTRACE_HWLAT = 15,\n\tTRACE_RAW_DATA = 16,\n\t__TRACE_LAST_TYPE = 17,\n};\n\nstruct ftrace_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tlong unsigned int parent_ip;\n};\n\nstruct stack_entry {\n\tstruct trace_entry ent;\n\tint size;\n\tlong unsigned int caller[8];\n};\n\nstruct userstack_entry {\n\tstruct trace_entry ent;\n\tunsigned int tgid;\n\tlong unsigned int caller[8];\n};\n\nstruct bprint_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *fmt;\n\tu32 buf[0];\n};\n\nstruct print_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tchar buf[0];\n};\n\nstruct raw_data_entry {\n\tstruct trace_entry ent;\n\tunsigned int id;\n\tchar buf[0];\n};\n\nstruct bputs_entry {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n\tconst char *str;\n};\n\nenum trace_flag_type {\n\tTRACE_FLAG_IRQS_OFF = 1,\n\tTRACE_FLAG_IRQS_NOSUPPORT = 2,\n\tTRACE_FLAG_NEED_RESCHED = 4,\n\tTRACE_FLAG_HARDIRQ = 8,\n\tTRACE_FLAG_SOFTIRQ = 16,\n\tTRACE_FLAG_PREEMPT_RESCHED = 32,\n\tTRACE_FLAG_NMI = 64,\n};\n\nstruct trace_array_cpu {\n\tatomic_t disabled;\n\tvoid *buffer_page;\n\tlong unsigned int entries;\n\tlong unsigned int saved_latency;\n\tlong unsigned int critical_start;\n\tlong unsigned int critical_end;\n\tlong unsigned int critical_sequence;\n\tlong unsigned int nice;\n\tlong unsigned int policy;\n\tlong unsigned int rt_priority;\n\tlong unsigned int skipped_entries;\n\tu64 preempt_timestamp;\n\tpid_t pid;\n\tkuid_t uid;\n\tchar comm[16];\n\tbool ignore_pid;\n};\n\nstruct trace_option_dentry;\n\nstruct trace_options {\n\tstruct tracer *tracer;\n\tstruct trace_option_dentry *topts;\n};\n\nstruct tracer_opt;\n\nstruct trace_option_dentry {\n\tstruct tracer_opt *opt;\n\tstruct tracer_flags *flags;\n\tstruct trace_array *tr;\n\tstruct dentry *entry;\n};\n\nstruct trace_pid_list {\n\tint pid_max;\n\tlong unsigned int *pids;\n};\n\ntypedef bool (*cond_update_fn_t)(struct trace_array *, void *);\n\nenum {\n\tTRACE_ARRAY_FL_GLOBAL = 1,\n};\n\nstruct tracer_opt {\n\tconst char *name;\n\tu32 bit;\n};\n\nstruct tracer_flags {\n\tu32 val;\n\tstruct tracer_opt *opts;\n\tstruct tracer *trace;\n};\n\nstruct trace_parser {\n\tbool cont;\n\tchar *buffer;\n\tunsigned int idx;\n\tunsigned int size;\n};\n\nenum trace_iterator_bits {\n\tTRACE_ITER_PRINT_PARENT_BIT = 0,\n\tTRACE_ITER_SYM_OFFSET_BIT = 1,\n\tTRACE_ITER_SYM_ADDR_BIT = 2,\n\tTRACE_ITER_VERBOSE_BIT = 3,\n\tTRACE_ITER_RAW_BIT = 4,\n\tTRACE_ITER_HEX_BIT = 5,\n\tTRACE_ITER_BIN_BIT = 6,\n\tTRACE_ITER_BLOCK_BIT = 7,\n\tTRACE_ITER_PRINTK_BIT = 8,\n\tTRACE_ITER_ANNOTATE_BIT = 9,\n\tTRACE_ITER_USERSTACKTRACE_BIT = 10,\n\tTRACE_ITER_SYM_USEROBJ_BIT = 11,\n\tTRACE_ITER_PRINTK_MSGONLY_BIT = 12,\n\tTRACE_ITER_CONTEXT_INFO_BIT = 13,\n\tTRACE_ITER_LATENCY_FMT_BIT = 14,\n\tTRACE_ITER_RECORD_CMD_BIT = 15,\n\tTRACE_ITER_RECORD_TGID_BIT = 16,\n\tTRACE_ITER_OVERWRITE_BIT = 17,\n\tTRACE_ITER_STOP_ON_FREE_BIT = 18,\n\tTRACE_ITER_IRQ_INFO_BIT = 19,\n\tTRACE_ITER_MARKERS_BIT = 20,\n\tTRACE_ITER_EVENT_FORK_BIT = 21,\n\tTRACE_ITER_PAUSE_ON_TRACE_BIT = 22,\n\tTRACE_ITER_STACKTRACE_BIT = 23,\n\tTRACE_ITER_LAST_BIT = 24,\n};\n\nenum trace_iterator_flags {\n\tTRACE_ITER_PRINT_PARENT = 1,\n\tTRACE_ITER_SYM_OFFSET = 2,\n\tTRACE_ITER_SYM_ADDR = 4,\n\tTRACE_ITER_VERBOSE = 8,\n\tTRACE_ITER_RAW = 16,\n\tTRACE_ITER_HEX = 32,\n\tTRACE_ITER_BIN = 64,\n\tTRACE_ITER_BLOCK = 128,\n\tTRACE_ITER_PRINTK = 256,\n\tTRACE_ITER_ANNOTATE = 512,\n\tTRACE_ITER_USERSTACKTRACE = 1024,\n\tTRACE_ITER_SYM_USEROBJ = 2048,\n\tTRACE_ITER_PRINTK_MSGONLY = 4096,\n\tTRACE_ITER_CONTEXT_INFO = 8192,\n\tTRACE_ITER_LATENCY_FMT = 16384,\n\tTRACE_ITER_RECORD_CMD = 32768,\n\tTRACE_ITER_RECORD_TGID = 65536,\n\tTRACE_ITER_OVERWRITE = 131072,\n\tTRACE_ITER_STOP_ON_FREE = 262144,\n\tTRACE_ITER_IRQ_INFO = 524288,\n\tTRACE_ITER_MARKERS = 1048576,\n\tTRACE_ITER_EVENT_FORK = 2097152,\n\tTRACE_ITER_PAUSE_ON_TRACE = 4194304,\n\tTRACE_ITER_STACKTRACE = 8388608,\n};\n\nstruct event_subsystem {\n\tstruct list_head list;\n\tconst char *name;\n\tstruct event_filter *filter;\n\tint ref_count;\n};\n\nstruct saved_cmdlines_buffer {\n\tunsigned int map_pid_to_cmdline[32769];\n\tunsigned int *map_cmdline_to_pid;\n\tunsigned int cmdline_num;\n\tint cmdline_idx;\n\tchar *saved_cmdlines;\n};\n\nstruct ftrace_stack {\n\tlong unsigned int calls[1024];\n};\n\nstruct ftrace_stacks {\n\tstruct ftrace_stack stacks[4];\n};\n\nstruct trace_buffer_struct {\n\tint nesting;\n\tchar buffer[4096];\n};\n\nstruct ftrace_buffer_info {\n\tstruct trace_iterator iter;\n\tvoid *spare;\n\tunsigned int spare_cpu;\n\tunsigned int read;\n};\n\nstruct err_info {\n\tconst char **errs;\n\tu8 type;\n\tu8 pos;\n\tu64 ts;\n};\n\nstruct tracing_log_err {\n\tstruct list_head list;\n\tstruct err_info info;\n\tchar loc[128];\n\tchar cmd[256];\n};\n\nstruct buffer_ref {\n\tstruct trace_buffer *buffer;\n\tvoid *page;\n\tint cpu;\n\trefcount_t refcount;\n};\n\nstruct ctx_switch_entry {\n\tstruct trace_entry ent;\n\tunsigned int prev_pid;\n\tunsigned int next_pid;\n\tunsigned int next_cpu;\n\tunsigned char prev_prio;\n\tunsigned char prev_state;\n\tunsigned char next_prio;\n\tunsigned char next_state;\n};\n\nstruct hwlat_entry {\n\tstruct trace_entry ent;\n\tu64 duration;\n\tu64 outer_duration;\n\tu64 nmi_total_ts;\n\tstruct timespec64 timestamp;\n\tunsigned int nmi_count;\n\tunsigned int seqnum;\n\tunsigned int count;\n};\n\nstruct trace_mark {\n\tlong long unsigned int val;\n\tchar sym;\n};\n\nstruct tracer_stat {\n\tconst char *name;\n\tvoid * (*stat_start)(struct tracer_stat *);\n\tvoid * (*stat_next)(void *, int);\n\tcmp_func_t stat_cmp;\n\tint (*stat_show)(struct seq_file *, void *);\n\tvoid (*stat_release)(void *);\n\tint (*stat_headers)(struct seq_file *);\n};\n\nstruct stat_node {\n\tstruct rb_node node;\n\tvoid *stat;\n};\n\nstruct stat_session {\n\tstruct list_head session_list;\n\tstruct tracer_stat *ts;\n\tstruct rb_root stat_root;\n\tstruct mutex stat_mutex;\n\tstruct dentry *file;\n};\n\nstruct trace_bprintk_fmt {\n\tstruct list_head list;\n\tconst char *fmt;\n};\n\nenum {\n\tTRACE_NOP_OPT_ACCEPT = 1,\n\tTRACE_NOP_OPT_REFUSE = 2,\n};\n\ntypedef __u32 blk_mq_req_flags_t;\n\nstruct disk_stats {\n\tu64 nsecs[4];\n\tlong unsigned int sectors[4];\n\tlong unsigned int ios[4];\n\tlong unsigned int merges[4];\n\tlong unsigned int io_ticks;\n\tlocal_t in_flight[2];\n};\n\nstruct blk_mq_ctxs;\n\nstruct blk_mq_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head rq_lists[3];\n\t\tlong: 64;\n\t};\n\tunsigned int cpu;\n\tshort unsigned int index_hw[3];\n\tstruct blk_mq_hw_ctx *hctxs[3];\n\tlong unsigned int rq_dispatched[2];\n\tlong unsigned int rq_merged;\n\tlong unsigned int rq_completed[2];\n\tstruct request_queue *queue;\n\tstruct blk_mq_ctxs *ctxs;\n\tstruct kobject kobj;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbitmap_word;\n\nstruct sbitmap {\n\tunsigned int depth;\n\tunsigned int shift;\n\tunsigned int map_nr;\n\tstruct sbitmap_word *map;\n};\n\nstruct blk_mq_tags;\n\nstruct blk_mq_hw_ctx {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head dispatch;\n\t\tlong unsigned int state;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct delayed_work run_work;\n\tcpumask_var_t cpumask;\n\tint next_cpu;\n\tint next_cpu_batch;\n\tlong unsigned int flags;\n\tvoid *sched_data;\n\tstruct request_queue *queue;\n\tstruct blk_flush_queue *fq;\n\tvoid *driver_data;\n\tstruct sbitmap ctx_map;\n\tstruct blk_mq_ctx *dispatch_from;\n\tunsigned int dispatch_busy;\n\tshort unsigned int type;\n\tshort unsigned int nr_ctx;\n\tstruct blk_mq_ctx **ctxs;\n\tspinlock_t dispatch_wait_lock;\n\twait_queue_entry_t dispatch_wait;\n\tatomic_t wait_index;\n\tstruct blk_mq_tags *tags;\n\tstruct blk_mq_tags *sched_tags;\n\tlong unsigned int queued;\n\tlong unsigned int run;\n\tlong unsigned int dispatched[7];\n\tunsigned int numa_node;\n\tunsigned int queue_num;\n\tatomic_t nr_active;\n\tstruct hlist_node cpuhp_online;\n\tstruct hlist_node cpuhp_dead;\n\tstruct kobject kobj;\n\tlong unsigned int poll_considered;\n\tlong unsigned int poll_invoked;\n\tlong unsigned int poll_success;\n\tstruct dentry *debugfs_dir;\n\tstruct dentry *sched_debugfs_dir;\n\tstruct list_head hctx_list;\n\tstruct srcu_struct srcu[0];\n\tlong: 64;\n};\n\nstruct blk_mq_alloc_data {\n\tstruct request_queue *q;\n\tblk_mq_req_flags_t flags;\n\tunsigned int shallow_depth;\n\tunsigned int cmd_flags;\n\tstruct blk_mq_ctx *ctx;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\nstruct blk_stat_callback {\n\tstruct list_head list;\n\tstruct timer_list timer;\n\tstruct blk_rq_stat *cpu_stat;\n\tint (*bucket_fn)(const struct request *);\n\tunsigned int buckets;\n\tstruct blk_rq_stat *stat;\n\tvoid (*timer_fn)(struct blk_stat_callback *);\n\tvoid *data;\n\tstruct callback_head rcu;\n};\n\nstruct blk_trace {\n\tint trace_state;\n\tstruct rchan *rchan;\n\tlong unsigned int *sequence;\n\tunsigned char *msg_data;\n\tu16 act_mask;\n\tu64 start_lba;\n\tu64 end_lba;\n\tu32 pid;\n\tu32 dev;\n\tstruct dentry *dir;\n\tstruct dentry *dropped_file;\n\tstruct dentry *msg_file;\n\tstruct list_head running_list;\n\tatomic_t dropped;\n};\n\nstruct blk_flush_queue {\n\tunsigned int flush_pending_idx: 1;\n\tunsigned int flush_running_idx: 1;\n\tblk_status_t rq_status;\n\tlong unsigned int flush_pending_since;\n\tstruct list_head flush_queue[2];\n\tstruct list_head flush_data_in_flight;\n\tstruct request *flush_rq;\n\tstruct request *orig_rq;\n\tstruct lock_class_key key;\n\tspinlock_t mq_flush_lock;\n};\n\nstruct blk_mq_queue_map {\n\tunsigned int *mq_map;\n\tunsigned int nr_queues;\n\tunsigned int queue_offset;\n};\n\nstruct blk_mq_tag_set {\n\tstruct blk_mq_queue_map map[3];\n\tunsigned int nr_maps;\n\tconst struct blk_mq_ops *ops;\n\tunsigned int nr_hw_queues;\n\tunsigned int queue_depth;\n\tunsigned int reserved_tags;\n\tunsigned int cmd_size;\n\tint numa_node;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tvoid *driver_data;\n\tstruct blk_mq_tags **tags;\n\tstruct mutex tag_list_lock;\n\tstruct list_head tag_list;\n};\n\ntypedef u64 compat_u64;\n\nenum blktrace_cat {\n\tBLK_TC_READ = 1,\n\tBLK_TC_WRITE = 2,\n\tBLK_TC_FLUSH = 4,\n\tBLK_TC_SYNC = 8,\n\tBLK_TC_SYNCIO = 8,\n\tBLK_TC_QUEUE = 16,\n\tBLK_TC_REQUEUE = 32,\n\tBLK_TC_ISSUE = 64,\n\tBLK_TC_COMPLETE = 128,\n\tBLK_TC_FS = 256,\n\tBLK_TC_PC = 512,\n\tBLK_TC_NOTIFY = 1024,\n\tBLK_TC_AHEAD = 2048,\n\tBLK_TC_META = 4096,\n\tBLK_TC_DISCARD = 8192,\n\tBLK_TC_DRV_DATA = 16384,\n\tBLK_TC_FUA = 32768,\n\tBLK_TC_END = 32768,\n};\n\nenum blktrace_act {\n\t__BLK_TA_QUEUE = 1,\n\t__BLK_TA_BACKMERGE = 2,\n\t__BLK_TA_FRONTMERGE = 3,\n\t__BLK_TA_GETRQ = 4,\n\t__BLK_TA_SLEEPRQ = 5,\n\t__BLK_TA_REQUEUE = 6,\n\t__BLK_TA_ISSUE = 7,\n\t__BLK_TA_COMPLETE = 8,\n\t__BLK_TA_PLUG = 9,\n\t__BLK_TA_UNPLUG_IO = 10,\n\t__BLK_TA_UNPLUG_TIMER = 11,\n\t__BLK_TA_INSERT = 12,\n\t__BLK_TA_SPLIT = 13,\n\t__BLK_TA_BOUNCE = 14,\n\t__BLK_TA_REMAP = 15,\n\t__BLK_TA_ABORT = 16,\n\t__BLK_TA_DRV_DATA = 17,\n\t__BLK_TA_CGROUP = 256,\n};\n\nenum blktrace_notify {\n\t__BLK_TN_PROCESS = 0,\n\t__BLK_TN_TIMESTAMP = 1,\n\t__BLK_TN_MESSAGE = 2,\n\t__BLK_TN_CGROUP = 256,\n};\n\nstruct blk_io_trace {\n\t__u32 magic;\n\t__u32 sequence;\n\t__u64 time;\n\t__u64 sector;\n\t__u32 bytes;\n\t__u32 action;\n\t__u32 pid;\n\t__u32 device;\n\t__u32 cpu;\n\t__u16 error;\n\t__u16 pdu_len;\n};\n\nstruct blk_io_trace_remap {\n\t__be32 device_from;\n\t__be32 device_to;\n\t__be64 sector_from;\n};\n\nenum {\n\tBlktrace_setup = 1,\n\tBlktrace_running = 2,\n\tBlktrace_stopped = 3,\n};\n\nstruct blk_user_trace_setup {\n\tchar name[32];\n\t__u16 act_mask;\n\t__u32 buf_size;\n\t__u32 buf_nr;\n\t__u64 start_lba;\n\t__u64 end_lba;\n\t__u32 pid;\n};\n\nstruct compat_blk_user_trace_setup {\n\tchar name[32];\n\tu16 act_mask;\n\tshort: 16;\n\tu32 buf_size;\n\tu32 buf_nr;\n\tcompat_u64 start_lba;\n\tcompat_u64 end_lba;\n\tu32 pid;\n} __attribute__((packed));\n\nstruct blkcg {};\n\nstruct sbitmap_word {\n\tlong unsigned int depth;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int word;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int cleared;\n\tspinlock_t swap_lock;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbq_wait_state {\n\tatomic_t wait_cnt;\n\twait_queue_head_t wait;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sbitmap_queue {\n\tstruct sbitmap sb;\n\tunsigned int *alloc_hint;\n\tunsigned int wake_batch;\n\tatomic_t wake_index;\n\tstruct sbq_wait_state *ws;\n\tatomic_t ws_active;\n\tbool round_robin;\n\tunsigned int min_shallow_depth;\n};\n\nstruct blk_mq_tags {\n\tunsigned int nr_tags;\n\tunsigned int nr_reserved_tags;\n\tatomic_t active_queues;\n\tstruct sbitmap_queue bitmap_tags;\n\tstruct sbitmap_queue breserved_tags;\n\tstruct request **rqs;\n\tstruct request **static_rqs;\n\tstruct list_head page_list;\n};\n\nstruct blk_mq_queue_data {\n\tstruct request *rq;\n\tbool last;\n};\n\nstruct blk_crypto_mode {\n\tconst char *cipher_str;\n\tunsigned int keysize;\n\tunsigned int ivsize;\n};\n\nstruct blk_mq_ctxs {\n\tstruct kobject kobj;\n\tstruct blk_mq_ctx *queue_ctx;\n};\n\ntypedef void blk_log_action_t(struct trace_iterator *, const char *, bool);\n\nenum {\n\tTRACE_PIDS = 1,\n\tTRACE_NO_PIDS = 2,\n};\n\nstruct ftrace_event_field {\n\tstruct list_head link;\n\tconst char *name;\n\tconst char *type;\n\tint filter_type;\n\tint offset;\n\tint size;\n\tint is_signed;\n};\n\nenum {\n\tFORMAT_HEADER = 1,\n\tFORMAT_FIELD_SEPERATOR = 2,\n\tFORMAT_PRINTFMT = 3,\n};\n\ntypedef long unsigned int perf_trace_t[256];\n\nstruct filter_pred;\n\nstruct prog_entry {\n\tint target;\n\tint when_to_branch;\n\tstruct filter_pred *pred;\n};\n\ntypedef int (*filter_pred_fn_t)(struct filter_pred *, void *);\n\nstruct regex;\n\ntypedef int (*regex_match_func)(char *, struct regex *, int);\n\nstruct regex {\n\tchar pattern[256];\n\tint len;\n\tint field_len;\n\tregex_match_func match;\n};\n\nstruct filter_pred {\n\tfilter_pred_fn_t fn;\n\tu64 val;\n\tstruct regex regex;\n\tshort unsigned int *ops;\n\tstruct ftrace_event_field *field;\n\tint offset;\n\tint not;\n\tint op;\n};\n\nenum regex_type {\n\tMATCH_FULL = 0,\n\tMATCH_FRONT_ONLY = 1,\n\tMATCH_MIDDLE_ONLY = 2,\n\tMATCH_END_ONLY = 3,\n\tMATCH_GLOB = 4,\n\tMATCH_INDEX = 5,\n};\n\nenum filter_op_ids {\n\tOP_GLOB = 0,\n\tOP_NE = 1,\n\tOP_EQ = 2,\n\tOP_LE = 3,\n\tOP_LT = 4,\n\tOP_GE = 5,\n\tOP_GT = 6,\n\tOP_BAND = 7,\n\tOP_MAX = 8,\n};\n\nenum {\n\tFILT_ERR_NONE = 0,\n\tFILT_ERR_INVALID_OP = 1,\n\tFILT_ERR_TOO_MANY_OPEN = 2,\n\tFILT_ERR_TOO_MANY_CLOSE = 3,\n\tFILT_ERR_MISSING_QUOTE = 4,\n\tFILT_ERR_OPERAND_TOO_LONG = 5,\n\tFILT_ERR_EXPECT_STRING = 6,\n\tFILT_ERR_EXPECT_DIGIT = 7,\n\tFILT_ERR_ILLEGAL_FIELD_OP = 8,\n\tFILT_ERR_FIELD_NOT_FOUND = 9,\n\tFILT_ERR_ILLEGAL_INTVAL = 10,\n\tFILT_ERR_BAD_SUBSYS_FILTER = 11,\n\tFILT_ERR_TOO_MANY_PREDS = 12,\n\tFILT_ERR_INVALID_FILTER = 13,\n\tFILT_ERR_IP_FIELD_ONLY = 14,\n\tFILT_ERR_INVALID_VALUE = 15,\n\tFILT_ERR_ERRNO = 16,\n\tFILT_ERR_NO_FILTER = 17,\n};\n\nstruct filter_parse_error {\n\tint lasterr;\n\tint lasterr_pos;\n};\n\ntypedef int (*parse_pred_fn)(const char *, void *, int, struct filter_parse_error *, struct filter_pred **);\n\nenum {\n\tINVERT = 1,\n\tPROCESS_AND = 2,\n\tPROCESS_OR = 4,\n};\n\nenum {\n\tTOO_MANY_CLOSE = 4294967295,\n\tTOO_MANY_OPEN = 4294967294,\n\tMISSING_QUOTE = 4294967293,\n};\n\nstruct filter_list {\n\tstruct list_head list;\n\tstruct event_filter *filter;\n};\n\nstruct event_trigger_ops;\n\nstruct event_command;\n\nstruct event_trigger_data {\n\tlong unsigned int count;\n\tint ref;\n\tstruct event_trigger_ops *ops;\n\tstruct event_command *cmd_ops;\n\tstruct event_filter *filter;\n\tchar *filter_str;\n\tvoid *private_data;\n\tbool paused;\n\tbool paused_tmp;\n\tstruct list_head list;\n\tchar *name;\n\tstruct list_head named_list;\n\tstruct event_trigger_data *named_data;\n};\n\nstruct event_trigger_ops {\n\tvoid (*func)(struct event_trigger_data *, void *, struct ring_buffer_event *);\n\tint (*init)(struct event_trigger_ops *, struct event_trigger_data *);\n\tvoid (*free)(struct event_trigger_ops *, struct event_trigger_data *);\n\tint (*print)(struct seq_file *, struct event_trigger_ops *, struct event_trigger_data *);\n};\n\nstruct event_command {\n\tstruct list_head list;\n\tchar *name;\n\tenum event_trigger_type trigger_type;\n\tint flags;\n\tint (*func)(struct event_command *, struct trace_event_file *, char *, char *, char *);\n\tint (*reg)(char *, struct event_trigger_ops *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg)(char *, struct event_trigger_ops *, struct event_trigger_data *, struct trace_event_file *);\n\tvoid (*unreg_all)(struct trace_event_file *);\n\tint (*set_filter)(char *, struct event_trigger_data *, struct trace_event_file *);\n\tstruct event_trigger_ops * (*get_trigger_ops)(char *, char *);\n};\n\nstruct enable_trigger_data {\n\tstruct trace_event_file *file;\n\tbool enable;\n\tbool hist;\n};\n\nenum event_command_flags {\n\tEVENT_CMD_FL_POST_TRIGGER = 1,\n\tEVENT_CMD_FL_NEEDS_REC = 2,\n};\n\nenum {\n\tBPF_F_INDEX_MASK = 4294967295,\n\tBPF_F_CURRENT_CPU = 4294967295,\n\tBPF_F_CTXLEN_MASK = 0,\n};\n\nenum {\n\tBPF_F_GET_BRANCH_RECORDS_SIZE = 1,\n};\n\nstruct bpf_perf_event_value {\n\t__u64 counter;\n\t__u64 enabled;\n\t__u64 running;\n};\n\nstruct bpf_raw_tracepoint_args {\n\t__u64 args[0];\n};\n\nenum bpf_task_fd_type {\n\tBPF_FD_TYPE_RAW_TRACEPOINT = 0,\n\tBPF_FD_TYPE_TRACEPOINT = 1,\n\tBPF_FD_TYPE_KPROBE = 2,\n\tBPF_FD_TYPE_KRETPROBE = 3,\n\tBPF_FD_TYPE_UPROBE = 4,\n\tBPF_FD_TYPE_URETPROBE = 5,\n};\n\nstruct bpf_event_entry {\n\tstruct perf_event *event;\n\tstruct file *perf_file;\n\tstruct file *map_file;\n\tstruct callback_head rcu;\n};\n\ntypedef long unsigned int (*bpf_ctx_copy_t)(void *, const void *, long unsigned int, long unsigned int);\n\ntypedef struct pt_regs bpf_user_pt_regs_t;\n\nstruct bpf_perf_event_data {\n\tbpf_user_pt_regs_t regs;\n\t__u64 sample_period;\n\t__u64 addr;\n};\n\nstruct perf_event_query_bpf {\n\t__u32 ids_len;\n\t__u32 prog_cnt;\n\t__u32 ids[0];\n};\n\nstruct bpf_perf_event_data_kern {\n\tbpf_user_pt_regs_t *regs;\n\tstruct perf_sample_data *data;\n\tstruct perf_event *event;\n};\n\nstruct bpf_trace_module {\n\tstruct module *module;\n\tstruct list_head list;\n};\n\ntypedef u64 (*btf_bpf_override_return)(struct pt_regs *, long unsigned int);\n\ntypedef u64 (*btf_bpf_probe_read_user)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_user_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_kernel_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_compat)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_read_compat_str)(void *, u32, const void *);\n\ntypedef u64 (*btf_bpf_probe_write_user)(void *, const void *, u32);\n\ntypedef u64 (*btf_bpf_trace_printk)(char *, u32, u64, u64, u64);\n\nstruct bpf_seq_printf_buf {\n\tchar buf[768];\n};\n\ntypedef u64 (*btf_bpf_seq_printf)(struct seq_file *, char *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_seq_write)(struct seq_file *, const void *, u32);\n\ntypedef u64 (*btf_bpf_perf_event_read)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_perf_event_read_value)(struct bpf_map *, u64, struct bpf_perf_event_value *, u32);\n\nstruct bpf_trace_sample_data {\n\tstruct perf_sample_data sds[3];\n};\n\ntypedef u64 (*btf_bpf_perf_event_output)(struct pt_regs *, struct bpf_map *, u64, void *, u64);\n\nstruct bpf_nested_pt_regs {\n\tstruct pt_regs regs[3];\n};\n\ntypedef u64 (*btf_bpf_get_current_task)();\n\ntypedef u64 (*btf_bpf_current_task_under_cgroup)(struct bpf_map *, u32);\n\nstruct send_signal_irq_work {\n\tstruct irq_work irq_work;\n\tstruct task_struct *task;\n\tu32 sig;\n\tenum pid_type type;\n};\n\ntypedef u64 (*btf_bpf_send_signal)(u32);\n\ntypedef u64 (*btf_bpf_send_signal_thread)(u32);\n\ntypedef u64 (*btf_bpf_perf_event_output_tp)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_tp)(void *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stack_tp)(void *, void *, u32, u64);\n\ntypedef u64 (*btf_bpf_perf_prog_read_value)(struct bpf_perf_event_data_kern *, struct bpf_perf_event_value *, u32);\n\ntypedef u64 (*btf_bpf_read_branch_records)(struct bpf_perf_event_data_kern *, void *, u32, u64);\n\nstruct bpf_raw_tp_regs {\n\tstruct pt_regs regs[3];\n};\n\ntypedef u64 (*btf_bpf_perf_event_output_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_get_stackid_raw_tp)(struct bpf_raw_tracepoint_args *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stack_raw_tp)(struct bpf_raw_tracepoint_args *, void *, u32, u64);\n\ntypedef struct bpf_cgroup_storage *pto_T_____20;\n\nenum dynevent_type {\n\tDYNEVENT_TYPE_SYNTH = 1,\n\tDYNEVENT_TYPE_KPROBE = 2,\n\tDYNEVENT_TYPE_NONE = 3,\n};\n\nstruct dynevent_cmd;\n\ntypedef int (*dynevent_create_fn_t)(struct dynevent_cmd *);\n\nstruct dynevent_cmd {\n\tstruct seq_buf seq;\n\tconst char *event_name;\n\tunsigned int n_fields;\n\tenum dynevent_type type;\n\tdynevent_create_fn_t run_command;\n\tvoid *private_data;\n};\n\nstruct kprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int ip;\n};\n\nstruct kretprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int func;\n\tlong unsigned int ret_ip;\n};\n\nstruct dyn_event;\n\nstruct dyn_event_operations {\n\tstruct list_head list;\n\tint (*create)(int, const char **);\n\tint (*show)(struct seq_file *, struct dyn_event *);\n\tbool (*is_busy)(struct dyn_event *);\n\tint (*free)(struct dyn_event *);\n\tbool (*match)(const char *, const char *, int, const char **, struct dyn_event *);\n};\n\nstruct dyn_event {\n\tstruct list_head list;\n\tstruct dyn_event_operations *ops;\n};\n\nstruct dynevent_arg {\n\tconst char *str;\n\tchar separator;\n};\n\ntypedef int (*print_type_func_t)(struct trace_seq *, void *, void *);\n\nenum fetch_op {\n\tFETCH_OP_NOP = 0,\n\tFETCH_OP_REG = 1,\n\tFETCH_OP_STACK = 2,\n\tFETCH_OP_STACKP = 3,\n\tFETCH_OP_RETVAL = 4,\n\tFETCH_OP_IMM = 5,\n\tFETCH_OP_COMM = 6,\n\tFETCH_OP_ARG = 7,\n\tFETCH_OP_FOFFS = 8,\n\tFETCH_OP_DATA = 9,\n\tFETCH_OP_DEREF = 10,\n\tFETCH_OP_UDEREF = 11,\n\tFETCH_OP_ST_RAW = 12,\n\tFETCH_OP_ST_MEM = 13,\n\tFETCH_OP_ST_UMEM = 14,\n\tFETCH_OP_ST_STRING = 15,\n\tFETCH_OP_ST_USTRING = 16,\n\tFETCH_OP_MOD_BF = 17,\n\tFETCH_OP_LP_ARRAY = 18,\n\tFETCH_OP_END = 19,\n\tFETCH_NOP_SYMBOL = 20,\n};\n\nstruct fetch_insn {\n\tenum fetch_op op;\n\tunion {\n\t\tunsigned int param;\n\t\tstruct {\n\t\t\tunsigned int size;\n\t\t\tint offset;\n\t\t};\n\t\tstruct {\n\t\t\tunsigned char basesize;\n\t\t\tunsigned char lshift;\n\t\t\tunsigned char rshift;\n\t\t};\n\t\tlong unsigned int immediate;\n\t\tvoid *data;\n\t};\n};\n\nstruct fetch_type {\n\tconst char *name;\n\tsize_t size;\n\tint is_signed;\n\tprint_type_func_t print;\n\tconst char *fmt;\n\tconst char *fmttype;\n};\n\nstruct probe_arg {\n\tstruct fetch_insn *code;\n\tbool dynamic;\n\tunsigned int offset;\n\tunsigned int count;\n\tconst char *name;\n\tconst char *comm;\n\tchar *fmt;\n\tconst struct fetch_type *type;\n};\n\nstruct trace_uprobe_filter {\n\trwlock_t rwlock;\n\tint nr_systemwide;\n\tstruct list_head perf_events;\n};\n\nstruct trace_probe_event {\n\tunsigned int flags;\n\tstruct trace_event_class class;\n\tstruct trace_event_call call;\n\tstruct list_head files;\n\tstruct list_head probes;\n\tstruct trace_uprobe_filter filter[0];\n};\n\nstruct trace_probe {\n\tstruct list_head list;\n\tstruct trace_probe_event *event;\n\tssize_t size;\n\tunsigned int nr_args;\n\tstruct probe_arg args[0];\n};\n\nstruct event_file_link {\n\tstruct trace_event_file *file;\n\tstruct list_head list;\n};\n\nenum {\n\tTP_ERR_FILE_NOT_FOUND = 0,\n\tTP_ERR_NO_REGULAR_FILE = 1,\n\tTP_ERR_BAD_REFCNT = 2,\n\tTP_ERR_REFCNT_OPEN_BRACE = 3,\n\tTP_ERR_BAD_REFCNT_SUFFIX = 4,\n\tTP_ERR_BAD_UPROBE_OFFS = 5,\n\tTP_ERR_MAXACT_NO_KPROBE = 6,\n\tTP_ERR_BAD_MAXACT = 7,\n\tTP_ERR_MAXACT_TOO_BIG = 8,\n\tTP_ERR_BAD_PROBE_ADDR = 9,\n\tTP_ERR_BAD_RETPROBE = 10,\n\tTP_ERR_NO_GROUP_NAME = 11,\n\tTP_ERR_GROUP_TOO_LONG = 12,\n\tTP_ERR_BAD_GROUP_NAME = 13,\n\tTP_ERR_NO_EVENT_NAME = 14,\n\tTP_ERR_EVENT_TOO_LONG = 15,\n\tTP_ERR_BAD_EVENT_NAME = 16,\n\tTP_ERR_RETVAL_ON_PROBE = 17,\n\tTP_ERR_BAD_STACK_NUM = 18,\n\tTP_ERR_BAD_ARG_NUM = 19,\n\tTP_ERR_BAD_VAR = 20,\n\tTP_ERR_BAD_REG_NAME = 21,\n\tTP_ERR_BAD_MEM_ADDR = 22,\n\tTP_ERR_BAD_IMM = 23,\n\tTP_ERR_IMMSTR_NO_CLOSE = 24,\n\tTP_ERR_FILE_ON_KPROBE = 25,\n\tTP_ERR_BAD_FILE_OFFS = 26,\n\tTP_ERR_SYM_ON_UPROBE = 27,\n\tTP_ERR_TOO_MANY_OPS = 28,\n\tTP_ERR_DEREF_NEED_BRACE = 29,\n\tTP_ERR_BAD_DEREF_OFFS = 30,\n\tTP_ERR_DEREF_OPEN_BRACE = 31,\n\tTP_ERR_COMM_CANT_DEREF = 32,\n\tTP_ERR_BAD_FETCH_ARG = 33,\n\tTP_ERR_ARRAY_NO_CLOSE = 34,\n\tTP_ERR_BAD_ARRAY_SUFFIX = 35,\n\tTP_ERR_BAD_ARRAY_NUM = 36,\n\tTP_ERR_ARRAY_TOO_BIG = 37,\n\tTP_ERR_BAD_TYPE = 38,\n\tTP_ERR_BAD_STRING = 39,\n\tTP_ERR_BAD_BITFIELD = 40,\n\tTP_ERR_ARG_NAME_TOO_LONG = 41,\n\tTP_ERR_NO_ARG_NAME = 42,\n\tTP_ERR_BAD_ARG_NAME = 43,\n\tTP_ERR_USED_ARG_NAME = 44,\n\tTP_ERR_ARG_TOO_LONG = 45,\n\tTP_ERR_NO_ARG_BODY = 46,\n\tTP_ERR_BAD_INSN_BNDRY = 47,\n\tTP_ERR_FAIL_REG_PROBE = 48,\n\tTP_ERR_DIFF_PROBE_TYPE = 49,\n\tTP_ERR_DIFF_ARG_TYPE = 50,\n\tTP_ERR_SAME_PROBE = 51,\n};\n\nstruct trace_kprobe {\n\tstruct dyn_event devent;\n\tstruct kretprobe rp;\n\tlong unsigned int *nhit;\n\tconst char *symbol;\n\tstruct trace_probe tp;\n};\n\nstruct trace_event_raw_cpu {\n\tstruct trace_entry ent;\n\tu32 state;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_powernv_throttle {\n\tstruct trace_entry ent;\n\tint chip_id;\n\tu32 __data_loc_reason;\n\tint pmax;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pstate_sample {\n\tstruct trace_entry ent;\n\tu32 core_busy;\n\tu32 scaled_busy;\n\tu32 from;\n\tu32 to;\n\tu64 mperf;\n\tu64 aperf;\n\tu64 tsc;\n\tu32 freq;\n\tu32 io_boost;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_frequency_limits {\n\tstruct trace_entry ent;\n\tu32 min_freq;\n\tu32 max_freq;\n\tu32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_device_pm_callback_start {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_parent;\n\tu32 __data_loc_pm_ops;\n\tint event;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_device_pm_callback_end {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_suspend_resume {\n\tstruct trace_entry ent;\n\tconst char *action;\n\tint val;\n\tbool start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wakeup_source {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu64 state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clock {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu64 state;\n\tu64 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_power_domain {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu64 state;\n\tu64 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cpu_latency_qos_request {\n\tstruct trace_entry ent;\n\ts32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_pm_qos_update {\n\tstruct trace_entry ent;\n\tenum pm_qos_req_action action;\n\tint prev_value;\n\tint curr_value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dev_pm_qos_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tenum dev_pm_qos_req_type type;\n\ts32 new_value;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_cpu {};\n\nstruct trace_event_data_offsets_powernv_throttle {\n\tu32 reason;\n};\n\nstruct trace_event_data_offsets_pstate_sample {};\n\nstruct trace_event_data_offsets_cpu_frequency_limits {};\n\nstruct trace_event_data_offsets_device_pm_callback_start {\n\tu32 device;\n\tu32 driver;\n\tu32 parent;\n\tu32 pm_ops;\n};\n\nstruct trace_event_data_offsets_device_pm_callback_end {\n\tu32 device;\n\tu32 driver;\n};\n\nstruct trace_event_data_offsets_suspend_resume {};\n\nstruct trace_event_data_offsets_wakeup_source {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_clock {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_power_domain {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_cpu_latency_qos_request {};\n\nstruct trace_event_data_offsets_pm_qos_update {};\n\nstruct trace_event_data_offsets_dev_pm_qos_request {\n\tu32 name;\n};\n\ntypedef void (*btf_trace_cpu_idle)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_powernv_throttle)(void *, int, const char *, int);\n\ntypedef void (*btf_trace_pstate_sample)(void *, u32, u32, u32, u32, u64, u64, u64, u32, u32);\n\ntypedef void (*btf_trace_cpu_frequency)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_cpu_frequency_limits)(void *, struct cpufreq_policy *);\n\ntypedef void (*btf_trace_device_pm_callback_start)(void *, struct device *, const char *, int);\n\ntypedef void (*btf_trace_device_pm_callback_end)(void *, struct device *, int);\n\ntypedef void (*btf_trace_suspend_resume)(void *, const char *, int, bool);\n\ntypedef void (*btf_trace_wakeup_source_activate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_wakeup_source_deactivate)(void *, const char *, unsigned int);\n\ntypedef void (*btf_trace_clock_enable)(void *, const char *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_clock_disable)(void *, const char *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_clock_set_rate)(void *, const char *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_power_domain_target)(void *, const char *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_pm_qos_add_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_remove_request)(void *, s32);\n\ntypedef void (*btf_trace_pm_qos_update_target)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_pm_qos_update_flags)(void *, enum pm_qos_req_action, int, int);\n\ntypedef void (*btf_trace_dev_pm_qos_add_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_update_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\ntypedef void (*btf_trace_dev_pm_qos_remove_request)(void *, const char *, enum dev_pm_qos_req_type, s32);\n\nstruct trace_event_raw_rpm_internal {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint flags;\n\tint usage_count;\n\tint disable_depth;\n\tint runtime_auto;\n\tint request_pending;\n\tint irq_safe;\n\tint child_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpm_return_int {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int ip;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_rpm_internal {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_rpm_return_int {\n\tu32 name;\n};\n\ntypedef void (*btf_trace_rpm_suspend)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_resume)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_idle)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_usage)(void *, struct device *, int);\n\ntypedef void (*btf_trace_rpm_return_int)(void *, struct device *, long unsigned int, int);\n\ntypedef int (*dynevent_check_arg_fn_t)(void *);\n\nstruct dynevent_arg_pair {\n\tconst char *lhs;\n\tconst char *rhs;\n\tchar operator;\n\tchar separator;\n};\n\nstruct trace_probe_log {\n\tconst char *subsystem;\n\tconst char **argv;\n\tint argc;\n\tint index;\n};\n\nenum uprobe_filter_ctx {\n\tUPROBE_FILTER_REGISTER = 0,\n\tUPROBE_FILTER_UNREGISTER = 1,\n\tUPROBE_FILTER_MMAP = 2,\n};\n\nstruct uprobe_consumer {\n\tint (*handler)(struct uprobe_consumer *, struct pt_regs *);\n\tint (*ret_handler)(struct uprobe_consumer *, long unsigned int, struct pt_regs *);\n\tbool (*filter)(struct uprobe_consumer *, enum uprobe_filter_ctx, struct mm_struct *);\n\tstruct uprobe_consumer *next;\n};\n\nstruct uprobe_trace_entry_head {\n\tstruct trace_entry ent;\n\tlong unsigned int vaddr[0];\n};\n\nstruct trace_uprobe {\n\tstruct dyn_event devent;\n\tstruct uprobe_consumer consumer;\n\tstruct path path;\n\tstruct inode *inode;\n\tchar *filename;\n\tlong unsigned int offset;\n\tlong unsigned int ref_ctr_offset;\n\tlong unsigned int nhit;\n\tstruct trace_probe tp;\n};\n\nstruct uprobe_dispatch_data {\n\tstruct trace_uprobe *tu;\n\tlong unsigned int bp_addr;\n};\n\nstruct uprobe_cpu_buffer {\n\tstruct mutex mutex;\n\tvoid *buf;\n};\n\ntypedef bool (*filter_func_t)(struct uprobe_consumer *, enum uprobe_filter_ctx, struct mm_struct *);\n\ntypedef __u32 __le32;\n\ntypedef __u64 __le64;\n\nstruct rhash_lock_head;\n\nstruct bucket_table {\n\tunsigned int size;\n\tunsigned int nest;\n\tu32 hash_rnd;\n\tstruct list_head walkers;\n\tstruct callback_head rcu;\n\tstruct bucket_table *future_tbl;\n\tstruct lockdep_map dep_map;\n\tlong: 64;\n\tstruct rhash_lock_head *buckets[0];\n};\n\nenum xdp_action {\n\tXDP_ABORTED = 0,\n\tXDP_DROP = 1,\n\tXDP_PASS = 2,\n\tXDP_TX = 3,\n\tXDP_REDIRECT = 4,\n};\n\nenum xdp_mem_type {\n\tMEM_TYPE_PAGE_SHARED = 0,\n\tMEM_TYPE_PAGE_ORDER0 = 1,\n\tMEM_TYPE_PAGE_POOL = 2,\n\tMEM_TYPE_XSK_BUFF_POOL = 3,\n\tMEM_TYPE_MAX = 4,\n};\n\ntypedef void (*bpf_jit_fill_hole_t)(void *, unsigned int);\n\nstruct bpf_prog_dummy {\n\tstruct bpf_prog prog;\n};\n\ntypedef u64 (*btf_bpf_user_rnd_u32)();\n\ntypedef u64 (*btf_bpf_get_raw_cpu_id)();\n\nstruct _bpf_dtab_netdev {\n\tstruct net_device *dev;\n};\n\nstruct rhash_lock_head {};\n\nstruct zero_copy_allocator;\n\nstruct page_pool;\n\nstruct xdp_mem_allocator {\n\tstruct xdp_mem_info mem;\n\tunion {\n\t\tvoid *allocator;\n\t\tstruct page_pool *page_pool;\n\t\tstruct zero_copy_allocator *zc_alloc;\n\t};\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n};\n\nstruct trace_event_raw_xdp_exception {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_bulk_tx {\n\tstruct trace_entry ent;\n\tint ifindex;\n\tu32 act;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_redirect_template {\n\tstruct trace_entry ent;\n\tint prog_id;\n\tu32 act;\n\tint ifindex;\n\tint err;\n\tint to_ifindex;\n\tu32 map_id;\n\tint map_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_kthread {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint sched;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_cpumap_enqueue {\n\tstruct trace_entry ent;\n\tint map_id;\n\tu32 act;\n\tint cpu;\n\tunsigned int drops;\n\tunsigned int processed;\n\tint to_cpu;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xdp_devmap_xmit {\n\tstruct trace_entry ent;\n\tint from_ifindex;\n\tu32 act;\n\tint to_ifindex;\n\tint drops;\n\tint sent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mem_disconnect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mem_connect {\n\tstruct trace_entry ent;\n\tconst struct xdp_mem_allocator *xa;\n\tu32 mem_id;\n\tu32 mem_type;\n\tconst void *allocator;\n\tconst struct xdp_rxq_info *rxq;\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mem_return_failed {\n\tstruct trace_entry ent;\n\tconst struct page *page;\n\tu32 mem_id;\n\tu32 mem_type;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_xdp_exception {};\n\nstruct trace_event_data_offsets_xdp_bulk_tx {};\n\nstruct trace_event_data_offsets_xdp_redirect_template {};\n\nstruct trace_event_data_offsets_xdp_cpumap_kthread {};\n\nstruct trace_event_data_offsets_xdp_cpumap_enqueue {};\n\nstruct trace_event_data_offsets_xdp_devmap_xmit {};\n\nstruct trace_event_data_offsets_mem_disconnect {};\n\nstruct trace_event_data_offsets_mem_connect {};\n\nstruct trace_event_data_offsets_mem_return_failed {};\n\ntypedef void (*btf_trace_xdp_exception)(void *, const struct net_device *, const struct bpf_prog *, u32);\n\ntypedef void (*btf_trace_xdp_bulk_tx)(void *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_xdp_redirect)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, const struct bpf_map *, u32);\n\ntypedef void (*btf_trace_xdp_redirect_err)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, const struct bpf_map *, u32);\n\ntypedef void (*btf_trace_xdp_redirect_map)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, const struct bpf_map *, u32);\n\ntypedef void (*btf_trace_xdp_redirect_map_err)(void *, const struct net_device *, const struct bpf_prog *, const void *, int, const struct bpf_map *, u32);\n\ntypedef void (*btf_trace_xdp_cpumap_kthread)(void *, int, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_xdp_cpumap_enqueue)(void *, int, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_xdp_devmap_xmit)(void *, const struct net_device *, const struct net_device *, int, int, int);\n\ntypedef void (*btf_trace_mem_disconnect)(void *, const struct xdp_mem_allocator *);\n\ntypedef void (*btf_trace_mem_connect)(void *, const struct xdp_mem_allocator *, const struct xdp_rxq_info *);\n\ntypedef void (*btf_trace_mem_return_failed)(void *, const struct xdp_mem_info *, const struct page *);\n\nenum bpf_cmd {\n\tBPF_MAP_CREATE = 0,\n\tBPF_MAP_LOOKUP_ELEM = 1,\n\tBPF_MAP_UPDATE_ELEM = 2,\n\tBPF_MAP_DELETE_ELEM = 3,\n\tBPF_MAP_GET_NEXT_KEY = 4,\n\tBPF_PROG_LOAD = 5,\n\tBPF_OBJ_PIN = 6,\n\tBPF_OBJ_GET = 7,\n\tBPF_PROG_ATTACH = 8,\n\tBPF_PROG_DETACH = 9,\n\tBPF_PROG_TEST_RUN = 10,\n\tBPF_PROG_GET_NEXT_ID = 11,\n\tBPF_MAP_GET_NEXT_ID = 12,\n\tBPF_PROG_GET_FD_BY_ID = 13,\n\tBPF_MAP_GET_FD_BY_ID = 14,\n\tBPF_OBJ_GET_INFO_BY_FD = 15,\n\tBPF_PROG_QUERY = 16,\n\tBPF_RAW_TRACEPOINT_OPEN = 17,\n\tBPF_BTF_LOAD = 18,\n\tBPF_BTF_GET_FD_BY_ID = 19,\n\tBPF_TASK_FD_QUERY = 20,\n\tBPF_MAP_LOOKUP_AND_DELETE_ELEM = 21,\n\tBPF_MAP_FREEZE = 22,\n\tBPF_BTF_GET_NEXT_ID = 23,\n\tBPF_MAP_LOOKUP_BATCH = 24,\n\tBPF_MAP_LOOKUP_AND_DELETE_BATCH = 25,\n\tBPF_MAP_UPDATE_BATCH = 26,\n\tBPF_MAP_DELETE_BATCH = 27,\n\tBPF_LINK_CREATE = 28,\n\tBPF_LINK_UPDATE = 29,\n\tBPF_LINK_GET_FD_BY_ID = 30,\n\tBPF_LINK_GET_NEXT_ID = 31,\n\tBPF_ENABLE_STATS = 32,\n\tBPF_ITER_CREATE = 33,\n};\n\nenum {\n\tBPF_ANY = 0,\n\tBPF_NOEXIST = 1,\n\tBPF_EXIST = 2,\n\tBPF_F_LOCK = 4,\n};\n\nenum {\n\tBPF_F_NO_PREALLOC = 1,\n\tBPF_F_NO_COMMON_LRU = 2,\n\tBPF_F_NUMA_NODE = 4,\n\tBPF_F_RDONLY = 8,\n\tBPF_F_WRONLY = 16,\n\tBPF_F_STACK_BUILD_ID = 32,\n\tBPF_F_ZERO_SEED = 64,\n\tBPF_F_RDONLY_PROG = 128,\n\tBPF_F_WRONLY_PROG = 256,\n\tBPF_F_CLONE = 512,\n\tBPF_F_MMAPABLE = 1024,\n};\n\nenum bpf_stats_type {\n\tBPF_STATS_RUN_TIME = 0,\n};\n\nstruct bpf_prog_info {\n\t__u32 type;\n\t__u32 id;\n\t__u8 tag[8];\n\t__u32 jited_prog_len;\n\t__u32 xlated_prog_len;\n\t__u64 jited_prog_insns;\n\t__u64 xlated_prog_insns;\n\t__u64 load_time;\n\t__u32 created_by_uid;\n\t__u32 nr_map_ids;\n\t__u64 map_ids;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 gpl_compatible: 1;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 nr_jited_ksyms;\n\t__u32 nr_jited_func_lens;\n\t__u64 jited_ksyms;\n\t__u64 jited_func_lens;\n\t__u32 btf_id;\n\t__u32 func_info_rec_size;\n\t__u64 func_info;\n\t__u32 nr_func_info;\n\t__u32 nr_line_info;\n\t__u64 line_info;\n\t__u64 jited_line_info;\n\t__u32 nr_jited_line_info;\n\t__u32 line_info_rec_size;\n\t__u32 jited_line_info_rec_size;\n\t__u32 nr_prog_tags;\n\t__u64 prog_tags;\n\t__u64 run_time_ns;\n\t__u64 run_cnt;\n};\n\nstruct bpf_map_info {\n\t__u32 type;\n\t__u32 id;\n\t__u32 key_size;\n\t__u32 value_size;\n\t__u32 max_entries;\n\t__u32 map_flags;\n\tchar name[16];\n\t__u32 ifindex;\n\t__u32 btf_vmlinux_value_type_id;\n\t__u64 netns_dev;\n\t__u64 netns_ino;\n\t__u32 btf_id;\n\t__u32 btf_key_type_id;\n\t__u32 btf_value_type_id;\n};\n\nstruct bpf_btf_info {\n\t__u64 btf;\n\t__u32 btf_size;\n\t__u32 id;\n};\n\nstruct bpf_spin_lock {\n\t__u32 val;\n};\n\nstruct bpf_link_primer {\n\tstruct bpf_link *link;\n\tstruct file *file;\n\tint fd;\n\tu32 id;\n};\n\nenum perf_bpf_event_type {\n\tPERF_BPF_EVENT_UNKNOWN = 0,\n\tPERF_BPF_EVENT_PROG_LOAD = 1,\n\tPERF_BPF_EVENT_PROG_UNLOAD = 2,\n\tPERF_BPF_EVENT_MAX = 3,\n};\n\nstruct security_hook_heads {\n\tstruct hlist_head binder_set_context_mgr;\n\tstruct hlist_head binder_transaction;\n\tstruct hlist_head binder_transfer_binder;\n\tstruct hlist_head binder_transfer_file;\n\tstruct hlist_head ptrace_access_check;\n\tstruct hlist_head ptrace_traceme;\n\tstruct hlist_head capget;\n\tstruct hlist_head capset;\n\tstruct hlist_head capable;\n\tstruct hlist_head quotactl;\n\tstruct hlist_head quota_on;\n\tstruct hlist_head syslog;\n\tstruct hlist_head settime;\n\tstruct hlist_head vm_enough_memory;\n\tstruct hlist_head bprm_creds_for_exec;\n\tstruct hlist_head bprm_creds_from_file;\n\tstruct hlist_head bprm_check_security;\n\tstruct hlist_head bprm_committing_creds;\n\tstruct hlist_head bprm_committed_creds;\n\tstruct hlist_head fs_context_dup;\n\tstruct hlist_head fs_context_parse_param;\n\tstruct hlist_head sb_alloc_security;\n\tstruct hlist_head sb_free_security;\n\tstruct hlist_head sb_free_mnt_opts;\n\tstruct hlist_head sb_eat_lsm_opts;\n\tstruct hlist_head sb_remount;\n\tstruct hlist_head sb_kern_mount;\n\tstruct hlist_head sb_show_options;\n\tstruct hlist_head sb_statfs;\n\tstruct hlist_head sb_mount;\n\tstruct hlist_head sb_umount;\n\tstruct hlist_head sb_pivotroot;\n\tstruct hlist_head sb_set_mnt_opts;\n\tstruct hlist_head sb_clone_mnt_opts;\n\tstruct hlist_head sb_add_mnt_opt;\n\tstruct hlist_head move_mount;\n\tstruct hlist_head dentry_init_security;\n\tstruct hlist_head dentry_create_files_as;\n\tstruct hlist_head path_notify;\n\tstruct hlist_head inode_alloc_security;\n\tstruct hlist_head inode_free_security;\n\tstruct hlist_head inode_init_security;\n\tstruct hlist_head inode_create;\n\tstruct hlist_head inode_link;\n\tstruct hlist_head inode_unlink;\n\tstruct hlist_head inode_symlink;\n\tstruct hlist_head inode_mkdir;\n\tstruct hlist_head inode_rmdir;\n\tstruct hlist_head inode_mknod;\n\tstruct hlist_head inode_rename;\n\tstruct hlist_head inode_readlink;\n\tstruct hlist_head inode_follow_link;\n\tstruct hlist_head inode_permission;\n\tstruct hlist_head inode_setattr;\n\tstruct hlist_head inode_getattr;\n\tstruct hlist_head inode_setxattr;\n\tstruct hlist_head inode_post_setxattr;\n\tstruct hlist_head inode_getxattr;\n\tstruct hlist_head inode_listxattr;\n\tstruct hlist_head inode_removexattr;\n\tstruct hlist_head inode_need_killpriv;\n\tstruct hlist_head inode_killpriv;\n\tstruct hlist_head inode_getsecurity;\n\tstruct hlist_head inode_setsecurity;\n\tstruct hlist_head inode_listsecurity;\n\tstruct hlist_head inode_getsecid;\n\tstruct hlist_head inode_copy_up;\n\tstruct hlist_head inode_copy_up_xattr;\n\tstruct hlist_head kernfs_init_security;\n\tstruct hlist_head file_permission;\n\tstruct hlist_head file_alloc_security;\n\tstruct hlist_head file_free_security;\n\tstruct hlist_head file_ioctl;\n\tstruct hlist_head mmap_addr;\n\tstruct hlist_head mmap_file;\n\tstruct hlist_head file_mprotect;\n\tstruct hlist_head file_lock;\n\tstruct hlist_head file_fcntl;\n\tstruct hlist_head file_set_fowner;\n\tstruct hlist_head file_send_sigiotask;\n\tstruct hlist_head file_receive;\n\tstruct hlist_head file_open;\n\tstruct hlist_head task_alloc;\n\tstruct hlist_head task_free;\n\tstruct hlist_head cred_alloc_blank;\n\tstruct hlist_head cred_free;\n\tstruct hlist_head cred_prepare;\n\tstruct hlist_head cred_transfer;\n\tstruct hlist_head cred_getsecid;\n\tstruct hlist_head kernel_act_as;\n\tstruct hlist_head kernel_create_files_as;\n\tstruct hlist_head kernel_module_request;\n\tstruct hlist_head kernel_load_data;\n\tstruct hlist_head kernel_read_file;\n\tstruct hlist_head kernel_post_read_file;\n\tstruct hlist_head task_fix_setuid;\n\tstruct hlist_head task_fix_setgid;\n\tstruct hlist_head task_setpgid;\n\tstruct hlist_head task_getpgid;\n\tstruct hlist_head task_getsid;\n\tstruct hlist_head task_getsecid;\n\tstruct hlist_head task_setnice;\n\tstruct hlist_head task_setioprio;\n\tstruct hlist_head task_getioprio;\n\tstruct hlist_head task_prlimit;\n\tstruct hlist_head task_setrlimit;\n\tstruct hlist_head task_setscheduler;\n\tstruct hlist_head task_getscheduler;\n\tstruct hlist_head task_movememory;\n\tstruct hlist_head task_kill;\n\tstruct hlist_head task_prctl;\n\tstruct hlist_head task_to_inode;\n\tstruct hlist_head ipc_permission;\n\tstruct hlist_head ipc_getsecid;\n\tstruct hlist_head msg_msg_alloc_security;\n\tstruct hlist_head msg_msg_free_security;\n\tstruct hlist_head msg_queue_alloc_security;\n\tstruct hlist_head msg_queue_free_security;\n\tstruct hlist_head msg_queue_associate;\n\tstruct hlist_head msg_queue_msgctl;\n\tstruct hlist_head msg_queue_msgsnd;\n\tstruct hlist_head msg_queue_msgrcv;\n\tstruct hlist_head shm_alloc_security;\n\tstruct hlist_head shm_free_security;\n\tstruct hlist_head shm_associate;\n\tstruct hlist_head shm_shmctl;\n\tstruct hlist_head shm_shmat;\n\tstruct hlist_head sem_alloc_security;\n\tstruct hlist_head sem_free_security;\n\tstruct hlist_head sem_associate;\n\tstruct hlist_head sem_semctl;\n\tstruct hlist_head sem_semop;\n\tstruct hlist_head netlink_send;\n\tstruct hlist_head d_instantiate;\n\tstruct hlist_head getprocattr;\n\tstruct hlist_head setprocattr;\n\tstruct hlist_head ismaclabel;\n\tstruct hlist_head secid_to_secctx;\n\tstruct hlist_head secctx_to_secid;\n\tstruct hlist_head release_secctx;\n\tstruct hlist_head inode_invalidate_secctx;\n\tstruct hlist_head inode_notifysecctx;\n\tstruct hlist_head inode_setsecctx;\n\tstruct hlist_head inode_getsecctx;\n\tstruct hlist_head unix_stream_connect;\n\tstruct hlist_head unix_may_send;\n\tstruct hlist_head socket_create;\n\tstruct hlist_head socket_post_create;\n\tstruct hlist_head socket_socketpair;\n\tstruct hlist_head socket_bind;\n\tstruct hlist_head socket_connect;\n\tstruct hlist_head socket_listen;\n\tstruct hlist_head socket_accept;\n\tstruct hlist_head socket_sendmsg;\n\tstruct hlist_head socket_recvmsg;\n\tstruct hlist_head socket_getsockname;\n\tstruct hlist_head socket_getpeername;\n\tstruct hlist_head socket_getsockopt;\n\tstruct hlist_head socket_setsockopt;\n\tstruct hlist_head socket_shutdown;\n\tstruct hlist_head socket_sock_rcv_skb;\n\tstruct hlist_head socket_getpeersec_stream;\n\tstruct hlist_head socket_getpeersec_dgram;\n\tstruct hlist_head sk_alloc_security;\n\tstruct hlist_head sk_free_security;\n\tstruct hlist_head sk_clone_security;\n\tstruct hlist_head sk_getsecid;\n\tstruct hlist_head sock_graft;\n\tstruct hlist_head inet_conn_request;\n\tstruct hlist_head inet_csk_clone;\n\tstruct hlist_head inet_conn_established;\n\tstruct hlist_head secmark_relabel_packet;\n\tstruct hlist_head secmark_refcount_inc;\n\tstruct hlist_head secmark_refcount_dec;\n\tstruct hlist_head req_classify_flow;\n\tstruct hlist_head tun_dev_alloc_security;\n\tstruct hlist_head tun_dev_free_security;\n\tstruct hlist_head tun_dev_create;\n\tstruct hlist_head tun_dev_attach_queue;\n\tstruct hlist_head tun_dev_attach;\n\tstruct hlist_head tun_dev_open;\n\tstruct hlist_head sctp_assoc_request;\n\tstruct hlist_head sctp_bind_connect;\n\tstruct hlist_head sctp_sk_clone;\n\tstruct hlist_head key_alloc;\n\tstruct hlist_head key_free;\n\tstruct hlist_head key_permission;\n\tstruct hlist_head key_getsecurity;\n\tstruct hlist_head audit_rule_init;\n\tstruct hlist_head audit_rule_known;\n\tstruct hlist_head audit_rule_match;\n\tstruct hlist_head audit_rule_free;\n\tstruct hlist_head bpf;\n\tstruct hlist_head bpf_map;\n\tstruct hlist_head bpf_prog;\n\tstruct hlist_head bpf_map_alloc_security;\n\tstruct hlist_head bpf_map_free_security;\n\tstruct hlist_head bpf_prog_alloc_security;\n\tstruct hlist_head bpf_prog_free_security;\n\tstruct hlist_head locked_down;\n\tstruct hlist_head perf_event_open;\n\tstruct hlist_head perf_event_alloc;\n\tstruct hlist_head perf_event_free;\n\tstruct hlist_head perf_event_read;\n\tstruct hlist_head perf_event_write;\n};\n\nstruct lsm_blob_sizes {\n\tint lbs_cred;\n\tint lbs_file;\n\tint lbs_inode;\n\tint lbs_ipc;\n\tint lbs_msg_msg;\n\tint lbs_task;\n};\n\nenum lsm_order {\n\tLSM_ORDER_FIRST = 4294967295,\n\tLSM_ORDER_MUTABLE = 0,\n};\n\nstruct lsm_info {\n\tconst char *name;\n\tenum lsm_order order;\n\tlong unsigned int flags;\n\tint *enabled;\n\tint (*init)();\n\tstruct lsm_blob_sizes *blobs;\n};\n\nenum bpf_audit {\n\tBPF_AUDIT_LOAD = 0,\n\tBPF_AUDIT_UNLOAD = 1,\n\tBPF_AUDIT_MAX = 2,\n};\n\nstruct bpf_tracing_link {\n\tstruct bpf_link link;\n\tenum bpf_attach_type attach_type;\n};\n\nstruct bpf_raw_tp_link {\n\tstruct bpf_link link;\n\tstruct bpf_raw_event_map *btp;\n};\n\nstruct btf_member {\n\t__u32 name_off;\n\t__u32 type;\n\t__u32 offset;\n};\n\nenum btf_func_linkage {\n\tBTF_FUNC_STATIC = 0,\n\tBTF_FUNC_GLOBAL = 1,\n\tBTF_FUNC_EXTERN = 2,\n};\n\nstruct bpf_verifier_log {\n\tu32 level;\n\tchar kbuf[1024];\n\tchar *ubuf;\n\tu32 len_used;\n\tu32 len_total;\n};\n\nstruct bpf_subprog_info {\n\tu32 start;\n\tu32 linfo_idx;\n\tu16 stack_depth;\n};\n\nstruct bpf_verifier_stack_elem;\n\nstruct bpf_verifier_state;\n\nstruct bpf_verifier_state_list;\n\nstruct bpf_insn_aux_data;\n\nstruct bpf_verifier_env {\n\tu32 insn_idx;\n\tu32 prev_insn_idx;\n\tstruct bpf_prog *prog;\n\tconst struct bpf_verifier_ops *ops;\n\tstruct bpf_verifier_stack_elem *head;\n\tint stack_size;\n\tbool strict_alignment;\n\tbool test_state_freq;\n\tstruct bpf_verifier_state *cur_state;\n\tstruct bpf_verifier_state_list **explored_states;\n\tstruct bpf_verifier_state_list *free_list;\n\tstruct bpf_map *used_maps[64];\n\tu32 used_map_cnt;\n\tu32 id_gen;\n\tbool allow_ptr_leaks;\n\tbool bpf_capable;\n\tbool bypass_spec_v1;\n\tbool bypass_spec_v4;\n\tbool seen_direct_write;\n\tstruct bpf_insn_aux_data *insn_aux_data;\n\tconst struct bpf_line_info *prev_linfo;\n\tstruct bpf_verifier_log log;\n\tstruct bpf_subprog_info subprog_info[257];\n\tstruct {\n\t\tint *insn_state;\n\t\tint *insn_stack;\n\t\tint cur_stack;\n\t} cfg;\n\tu32 pass_cnt;\n\tu32 subprog_cnt;\n\tu32 prev_insn_processed;\n\tu32 insn_processed;\n\tu32 prev_jmps_processed;\n\tu32 jmps_processed;\n\tu64 verification_time;\n\tu32 max_states_per_insn;\n\tu32 total_states;\n\tu32 peak_states;\n\tu32 longest_mark_read_walk;\n};\n\nstruct bpf_struct_ops {\n\tconst struct bpf_verifier_ops *verifier_ops;\n\tint (*init)(struct btf *);\n\tint (*check_member)(const struct btf_type *, const struct btf_member *);\n\tint (*init_member)(const struct btf_type *, const struct btf_member *, void *, const void *);\n\tint (*reg)(void *);\n\tvoid (*unreg)(void *);\n\tconst struct btf_type *type;\n\tconst struct btf_type *value_type;\n\tconst char *name;\n\tstruct btf_func_model func_models[64];\n\tu32 type_id;\n\tu32 value_id;\n};\n\ntypedef u32 (*bpf_convert_ctx_access_t)(enum bpf_access_type, const struct bpf_insn *, struct bpf_insn *, struct bpf_prog *, u32 *);\n\nstruct tnum {\n\tu64 value;\n\tu64 mask;\n};\n\nenum bpf_reg_liveness {\n\tREG_LIVE_NONE = 0,\n\tREG_LIVE_READ32 = 1,\n\tREG_LIVE_READ64 = 2,\n\tREG_LIVE_READ = 3,\n\tREG_LIVE_WRITTEN = 4,\n\tREG_LIVE_DONE = 8,\n};\n\nstruct bpf_reg_state {\n\tenum bpf_reg_type type;\n\tunion {\n\t\tu16 range;\n\t\tstruct bpf_map *map_ptr;\n\t\tu32 btf_id;\n\t\tu32 mem_size;\n\t\tlong unsigned int raw;\n\t};\n\ts32 off;\n\tu32 id;\n\tu32 ref_obj_id;\n\tstruct tnum var_off;\n\ts64 smin_value;\n\ts64 smax_value;\n\tu64 umin_value;\n\tu64 umax_value;\n\ts32 s32_min_value;\n\ts32 s32_max_value;\n\tu32 u32_min_value;\n\tu32 u32_max_value;\n\tstruct bpf_reg_state *parent;\n\tu32 frameno;\n\ts32 subreg_def;\n\tenum bpf_reg_liveness live;\n\tbool precise;\n};\n\nenum bpf_stack_slot_type {\n\tSTACK_INVALID = 0,\n\tSTACK_SPILL = 1,\n\tSTACK_MISC = 2,\n\tSTACK_ZERO = 3,\n};\n\nstruct bpf_stack_state {\n\tstruct bpf_reg_state spilled_ptr;\n\tu8 slot_type[8];\n};\n\nstruct bpf_reference_state {\n\tint id;\n\tint insn_idx;\n};\n\nstruct bpf_func_state {\n\tstruct bpf_reg_state regs[11];\n\tint callsite;\n\tu32 frameno;\n\tu32 subprogno;\n\tint acquired_refs;\n\tstruct bpf_reference_state *refs;\n\tint allocated_stack;\n\tstruct bpf_stack_state *stack;\n};\n\nstruct bpf_idx_pair {\n\tu32 prev_idx;\n\tu32 idx;\n};\n\nstruct bpf_verifier_state {\n\tstruct bpf_func_state *frame[8];\n\tstruct bpf_verifier_state *parent;\n\tu32 branches;\n\tu32 insn_idx;\n\tu32 curframe;\n\tu32 active_spin_lock;\n\tbool speculative;\n\tu32 first_insn_idx;\n\tu32 last_insn_idx;\n\tstruct bpf_idx_pair *jmp_history;\n\tu32 jmp_history_cnt;\n};\n\nstruct bpf_verifier_state_list {\n\tstruct bpf_verifier_state state;\n\tstruct bpf_verifier_state_list *next;\n\tint miss_cnt;\n\tint hit_cnt;\n};\n\nstruct bpf_insn_aux_data {\n\tunion {\n\t\tenum bpf_reg_type ptr_type;\n\t\tlong unsigned int map_ptr_state;\n\t\ts32 call_imm;\n\t\tu32 alu_limit;\n\t\tstruct {\n\t\t\tu32 map_index;\n\t\t\tu32 map_off;\n\t\t};\n\t};\n\tu64 map_key_state;\n\tint ctx_field_size;\n\tint sanitize_stack_off;\n\tu32 seen;\n\tbool zext_dst;\n\tu8 alu_state;\n\tunsigned int orig_idx;\n\tbool prune_point;\n};\n\nstruct bpf_verifier_stack_elem {\n\tstruct bpf_verifier_state st;\n\tint insn_idx;\n\tint prev_insn_idx;\n\tstruct bpf_verifier_stack_elem *next;\n\tu32 log_pos;\n};\n\ntypedef void (*bpf_insn_print_t)(void *, const char *, ...);\n\ntypedef const char * (*bpf_insn_revmap_call_t)(void *, const struct bpf_insn *);\n\ntypedef const char * (*bpf_insn_print_imm_t)(void *, const struct bpf_insn *, __u64);\n\nstruct bpf_insn_cbs {\n\tbpf_insn_print_t cb_print;\n\tbpf_insn_revmap_call_t cb_call;\n\tbpf_insn_print_imm_t cb_imm;\n\tvoid *private_data;\n};\n\nstruct bpf_call_arg_meta {\n\tstruct bpf_map *map_ptr;\n\tbool raw_mode;\n\tbool pkt_access;\n\tint regno;\n\tint access_size;\n\tint mem_size;\n\tu64 msize_max_value;\n\tint ref_obj_id;\n\tint func_id;\n\tu32 btf_id;\n};\n\nenum reg_arg_type {\n\tSRC_OP = 0,\n\tDST_OP = 1,\n\tDST_OP_NO_MARK = 2,\n};\n\nenum {\n\tDISCOVERED = 16,\n\tEXPLORED = 32,\n\tFALLTHROUGH = 1,\n\tBRANCH = 2,\n};\n\nstruct idpair {\n\tu32 old;\n\tu32 cur;\n};\n\nstruct tree_descr {\n\tconst char *name;\n\tconst struct file_operations *ops;\n\tint mode;\n};\n\nenum bpf_type {\n\tBPF_TYPE_UNSPEC = 0,\n\tBPF_TYPE_PROG = 1,\n\tBPF_TYPE_MAP = 2,\n\tBPF_TYPE_LINK = 3,\n};\n\nstruct map_iter {\n\tvoid *key;\n\tbool done;\n};\n\nenum {\n\tOPT_MODE = 0,\n};\n\nstruct bpf_mount_opts {\n\tumode_t mode;\n};\n\nstruct bpf_pidns_info {\n\t__u32 pid;\n\t__u32 tgid;\n};\n\ntypedef u64 (*btf_bpf_map_lookup_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_update_elem)(struct bpf_map *, void *, void *, u64);\n\ntypedef u64 (*btf_bpf_map_delete_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_push_elem)(struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_map_pop_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_map_peek_elem)(struct bpf_map *, void *);\n\ntypedef u64 (*btf_bpf_get_smp_processor_id)();\n\ntypedef u64 (*btf_bpf_get_numa_node_id)();\n\ntypedef u64 (*btf_bpf_ktime_get_ns)();\n\ntypedef u64 (*btf_bpf_ktime_get_boot_ns)();\n\ntypedef u64 (*btf_bpf_get_current_pid_tgid)();\n\ntypedef u64 (*btf_bpf_get_current_uid_gid)();\n\ntypedef u64 (*btf_bpf_get_current_comm)(char *, u32);\n\ntypedef u64 (*btf_bpf_spin_lock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_spin_unlock)(struct bpf_spin_lock *);\n\ntypedef u64 (*btf_bpf_jiffies64)();\n\ntypedef u64 (*btf_bpf_get_current_cgroup_id)();\n\ntypedef u64 (*btf_bpf_get_current_ancestor_cgroup_id)(int);\n\ntypedef u64 (*btf_bpf_get_local_storage)(struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_strtol)(const char *, size_t, u64, long int *);\n\ntypedef u64 (*btf_bpf_strtoul)(const char *, size_t, u64, long unsigned int *);\n\ntypedef u64 (*btf_bpf_get_ns_current_pid_tgid)(u64, u64, struct bpf_pidns_info *, u32);\n\ntypedef u64 (*btf_bpf_event_output_data)(void *, struct bpf_map *, u64, void *, u64);\n\ntypedef int (*bpf_iter_init_seq_priv_t)(void *);\n\ntypedef void (*bpf_iter_fini_seq_priv_t)(void *);\n\nstruct bpf_iter_reg {\n\tconst char *target;\n\tconst struct seq_operations *seq_ops;\n\tbpf_iter_init_seq_priv_t init_seq_private;\n\tbpf_iter_fini_seq_priv_t fini_seq_private;\n\tu32 seq_priv_size;\n\tu32 ctx_arg_info_size;\n\tstruct bpf_ctx_arg_aux ctx_arg_info[2];\n};\n\nstruct bpf_iter_meta {\n\tunion {\n\t\tstruct seq_file *seq;\n\t};\n\tu64 session_id;\n\tu64 seq_num;\n};\n\nstruct bpf_iter_target_info {\n\tstruct list_head list;\n\tconst struct bpf_iter_reg *reg_info;\n\tu32 btf_id;\n};\n\nstruct bpf_iter_link {\n\tstruct bpf_link link;\n\tstruct bpf_iter_target_info *tinfo;\n};\n\nstruct bpf_iter_priv_data {\n\tstruct bpf_iter_target_info *tinfo;\n\tstruct bpf_prog *prog;\n\tu64 session_id;\n\tu64 seq_num;\n\tbool done_stop;\n\tlong: 56;\n\tu8 target_private[0];\n};\n\nstruct bpf_iter_seq_map_info {\n\tu32 mid;\n};\n\nstruct bpf_iter__bpf_map {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct bpf_map *map;\n\t};\n};\n\nstruct bpf_iter_seq_task_common {\n\tstruct pid_namespace *ns;\n};\n\nstruct bpf_iter_seq_task_info {\n\tstruct bpf_iter_seq_task_common common;\n\tu32 tid;\n};\n\nstruct bpf_iter__task {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n};\n\nstruct bpf_iter_seq_task_file_info {\n\tstruct bpf_iter_seq_task_common common;\n\tstruct task_struct *task;\n\tstruct files_struct *files;\n\tu32 tid;\n\tu32 fd;\n};\n\nstruct bpf_iter__task_file {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct task_struct *task;\n\t};\n\tu32 fd;\n\tunion {\n\t\tstruct file *file;\n\t};\n};\n\nstruct pcpu_freelist_node;\n\nstruct pcpu_freelist_head {\n\tstruct pcpu_freelist_node *first;\n\traw_spinlock_t lock;\n};\n\nstruct pcpu_freelist_node {\n\tstruct pcpu_freelist_node *next;\n};\n\nstruct pcpu_freelist {\n\tstruct pcpu_freelist_head *freelist;\n};\n\nstruct bpf_lru_node {\n\tstruct list_head list;\n\tu16 cpu;\n\tu8 type;\n\tu8 ref;\n};\n\nstruct bpf_lru_list {\n\tstruct list_head lists[3];\n\tunsigned int counts[2];\n\tstruct list_head *next_inactive_rotation;\n\traw_spinlock_t lock;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_lru_locallist {\n\tstruct list_head lists[2];\n\tu16 next_steal;\n\traw_spinlock_t lock;\n};\n\nstruct bpf_common_lru {\n\tstruct bpf_lru_list lru_list;\n\tstruct bpf_lru_locallist *local_list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef bool (*del_from_htab_func)(void *, struct bpf_lru_node *);\n\nstruct bpf_lru {\n\tunion {\n\t\tstruct bpf_common_lru common_lru;\n\t\tstruct bpf_lru_list *percpu_lru;\n\t};\n\tdel_from_htab_func del_from_htab;\n\tvoid *del_arg;\n\tunsigned int hash_offset;\n\tunsigned int nr_scans;\n\tbool percpu;\n\tlong: 56;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bucket {\n\tstruct hlist_nulls_head head;\n\tunion {\n\t\traw_spinlock_t raw_lock;\n\t\tspinlock_t lock;\n\t};\n};\n\nstruct htab_elem;\n\nstruct bpf_htab {\n\tstruct bpf_map map;\n\tstruct bucket *buckets;\n\tvoid *elems;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tstruct pcpu_freelist freelist;\n\t\tstruct bpf_lru lru;\n\t};\n\tstruct htab_elem **extra_elems;\n\tatomic_t count;\n\tu32 n_buckets;\n\tu32 elem_size;\n\tu32 hashrnd;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct htab_elem {\n\tunion {\n\t\tstruct hlist_nulls_node hash_node;\n\t\tstruct {\n\t\t\tvoid *padding;\n\t\t\tunion {\n\t\t\t\tstruct bpf_htab *htab;\n\t\t\t\tstruct pcpu_freelist_node fnode;\n\t\t\t\tstruct htab_elem *batch_flink;\n\t\t\t};\n\t\t};\n\t};\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct bpf_lru_node lru_node;\n\t};\n\tu32 hash;\n\tint: 32;\n\tchar key[0];\n};\n\nstruct prog_poke_elem {\n\tstruct list_head list;\n\tstruct bpf_prog_aux *aux;\n};\n\nenum bpf_lru_list_type {\n\tBPF_LRU_LIST_T_ACTIVE = 0,\n\tBPF_LRU_LIST_T_INACTIVE = 1,\n\tBPF_LRU_LIST_T_FREE = 2,\n\tBPF_LRU_LOCAL_LIST_T_FREE = 3,\n\tBPF_LRU_LOCAL_LIST_T_PENDING = 4,\n};\n\nstruct bpf_lpm_trie_key {\n\t__u32 prefixlen;\n\t__u8 data[0];\n};\n\nstruct lpm_trie_node {\n\tstruct callback_head rcu;\n\tstruct lpm_trie_node *child[2];\n\tu32 prefixlen;\n\tu32 flags;\n\tu8 data[0];\n};\n\nstruct lpm_trie {\n\tstruct bpf_map map;\n\tstruct lpm_trie_node *root;\n\tsize_t n_entries;\n\tsize_t max_prefixlen;\n\tsize_t data_size;\n\tspinlock_t lock;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_cgroup_storage_map {\n\tstruct bpf_map map;\n\tspinlock_t lock;\n\tstruct bpf_prog_aux *aux;\n\tstruct rb_root root;\n\tstruct list_head list;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_queue_stack {\n\tstruct bpf_map map;\n\traw_spinlock_t lock;\n\tu32 head;\n\tu32 tail;\n\tu32 size;\n\tchar elements[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nenum {\n\tBPF_RB_NO_WAKEUP = 1,\n\tBPF_RB_FORCE_WAKEUP = 2,\n};\n\nenum {\n\tBPF_RB_AVAIL_DATA = 0,\n\tBPF_RB_RING_SIZE = 1,\n\tBPF_RB_CONS_POS = 2,\n\tBPF_RB_PROD_POS = 3,\n};\n\nenum {\n\tBPF_RINGBUF_BUSY_BIT = 2147483648,\n\tBPF_RINGBUF_DISCARD_BIT = 1073741824,\n\tBPF_RINGBUF_HDR_SZ = 8,\n};\n\nstruct bpf_ringbuf {\n\twait_queue_head_t waitq;\n\tstruct irq_work work;\n\tu64 mask;\n\tstruct page **pages;\n\tint nr_pages;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t spinlock;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int consumer_pos;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int producer_pos;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar data[0];\n};\n\nstruct bpf_ringbuf_map {\n\tstruct bpf_map map;\n\tstruct bpf_map_memory memory;\n\tstruct bpf_ringbuf *rb;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_ringbuf_hdr {\n\tu32 len;\n\tu32 pg_off;\n};\n\ntypedef u64 (*btf_bpf_ringbuf_reserve)(struct bpf_map *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_submit)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_discard)(void *, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_output)(struct bpf_map *, void *, u64, u64);\n\ntypedef u64 (*btf_bpf_ringbuf_query)(struct bpf_map *, u64);\n\nenum perf_record_ksymbol_type {\n\tPERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0,\n\tPERF_RECORD_KSYMBOL_TYPE_BPF = 1,\n\tPERF_RECORD_KSYMBOL_TYPE_MAX = 2,\n};\n\nstruct btf_enum {\n\t__u32 name_off;\n\t__s32 val;\n};\n\nstruct btf_array {\n\t__u32 type;\n\t__u32 index_type;\n\t__u32 nelems;\n};\n\nstruct btf_param {\n\t__u32 name_off;\n\t__u32 type;\n};\n\nenum {\n\tBTF_VAR_STATIC = 0,\n\tBTF_VAR_GLOBAL_ALLOCATED = 1,\n\tBTF_VAR_GLOBAL_EXTERN = 2,\n};\n\nstruct btf_var {\n\t__u32 linkage;\n};\n\nstruct btf_var_secinfo {\n\t__u32 type;\n\t__u32 offset;\n\t__u32 size;\n};\n\nstruct bpf_flow_keys {\n\t__u16 nhoff;\n\t__u16 thoff;\n\t__u16 addr_proto;\n\t__u8 is_frag;\n\t__u8 is_first_frag;\n\t__u8 is_encap;\n\t__u8 ip_proto;\n\t__be16 n_proto;\n\t__be16 sport;\n\t__be16 dport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 ipv4_src;\n\t\t\t__be32 ipv4_dst;\n\t\t};\n\t\tstruct {\n\t\t\t__u32 ipv6_src[4];\n\t\t\t__u32 ipv6_dst[4];\n\t\t};\n\t};\n\t__u32 flags;\n\t__be32 flow_label;\n};\n\nstruct bpf_sock {\n\t__u32 bound_dev_if;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 mark;\n\t__u32 priority;\n\t__u32 src_ip4;\n\t__u32 src_ip6[4];\n\t__u32 src_port;\n\t__u32 dst_port;\n\t__u32 dst_ip4;\n\t__u32 dst_ip6[4];\n\t__u32 state;\n\t__s32 rx_queue_mapping;\n};\n\nstruct __sk_buff {\n\t__u32 len;\n\t__u32 pkt_type;\n\t__u32 mark;\n\t__u32 queue_mapping;\n\t__u32 protocol;\n\t__u32 vlan_present;\n\t__u32 vlan_tci;\n\t__u32 vlan_proto;\n\t__u32 priority;\n\t__u32 ingress_ifindex;\n\t__u32 ifindex;\n\t__u32 tc_index;\n\t__u32 cb[5];\n\t__u32 hash;\n\t__u32 tc_classid;\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 napi_id;\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 data_meta;\n\tunion {\n\t\tstruct bpf_flow_keys *flow_keys;\n\t};\n\t__u64 tstamp;\n\t__u32 wire_len;\n\t__u32 gso_segs;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\t__u32 gso_size;\n};\n\nstruct xdp_md {\n\t__u32 data;\n\t__u32 data_end;\n\t__u32 data_meta;\n\t__u32 ingress_ifindex;\n\t__u32 rx_queue_index;\n\t__u32 egress_ifindex;\n};\n\nstruct sk_msg_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 size;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct sk_reuseport_md {\n\tunion {\n\t\tvoid *data;\n\t};\n\tunion {\n\t\tvoid *data_end;\n\t};\n\t__u32 len;\n\t__u32 eth_protocol;\n\t__u32 ip_protocol;\n\t__u32 bind_inany;\n\t__u32 hash;\n};\n\nstruct bpf_sock_addr {\n\t__u32 user_family;\n\t__u32 user_ip4;\n\t__u32 user_ip6[4];\n\t__u32 user_port;\n\t__u32 family;\n\t__u32 type;\n\t__u32 protocol;\n\t__u32 msg_src_ip4;\n\t__u32 msg_src_ip6[4];\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct bpf_sock_ops {\n\t__u32 op;\n\tunion {\n\t\t__u32 args[4];\n\t\t__u32 reply;\n\t\t__u32 replylong[4];\n\t};\n\t__u32 family;\n\t__u32 remote_ip4;\n\t__u32 local_ip4;\n\t__u32 remote_ip6[4];\n\t__u32 local_ip6[4];\n\t__u32 remote_port;\n\t__u32 local_port;\n\t__u32 is_fullsock;\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 bpf_sock_ops_cb_flags;\n\t__u32 state;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u32 sk_txhash;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n};\n\nstruct bpf_cgroup_dev_ctx {\n\t__u32 access_type;\n\t__u32 major;\n\t__u32 minor;\n};\n\nstruct bpf_sysctl {\n\t__u32 write;\n\t__u32 file_pos;\n};\n\nstruct bpf_sockopt {\n\tunion {\n\t\tstruct bpf_sock *sk;\n\t};\n\tunion {\n\t\tvoid *optval;\n\t};\n\tunion {\n\t\tvoid *optval_end;\n\t};\n\t__s32 level;\n\t__s32 optname;\n\t__s32 optlen;\n\t__s32 retval;\n};\n\nstruct sk_reuseport_kern {\n\tstruct sk_buff *skb;\n\tstruct sock *sk;\n\tstruct sock *selected_sk;\n\tvoid *data_end;\n\tu32 hash;\n\tu32 reuseport_id;\n\tbool bind_inany;\n};\n\nstruct bpf_flow_dissector {\n\tstruct bpf_flow_keys *flow_keys;\n\tconst struct sk_buff *skb;\n\tvoid *data;\n\tvoid *data_end;\n};\n\nstruct inet_listen_hashbucket {\n\tspinlock_t lock;\n\tunsigned int count;\n\tunion {\n\t\tstruct hlist_head head;\n\t\tstruct hlist_nulls_head nulls_head;\n\t};\n};\n\nstruct inet_ehash_bucket;\n\nstruct inet_bind_hashbucket;\n\nstruct inet_hashinfo {\n\tstruct inet_ehash_bucket *ehash;\n\tspinlock_t *ehash_locks;\n\tunsigned int ehash_mask;\n\tunsigned int ehash_locks_mask;\n\tstruct kmem_cache *bind_bucket_cachep;\n\tstruct inet_bind_hashbucket *bhash;\n\tunsigned int bhash_size;\n\tunsigned int lhash2_mask;\n\tstruct inet_listen_hashbucket *lhash2;\n\tlong: 64;\n\tstruct inet_listen_hashbucket listening_hash[32];\n};\n\nstruct ip_ra_chain {\n\tstruct ip_ra_chain *next;\n\tstruct sock *sk;\n\tunion {\n\t\tvoid (*destructor)(struct sock *);\n\t\tstruct sock *saved_sk;\n\t};\n\tstruct callback_head rcu;\n};\n\nstruct fib_table {\n\tstruct hlist_node tb_hlist;\n\tu32 tb_id;\n\tint tb_num_default;\n\tstruct callback_head rcu;\n\tlong unsigned int *tb_data;\n\tlong unsigned int __data[0];\n};\n\nstruct inet_peer_base {\n\tstruct rb_root rb_root;\n\tseqlock_t lock;\n\tint total;\n};\n\nstruct tcp_fastopen_context {\n\tsiphash_key_t key[2];\n\tint num;\n\tstruct callback_head rcu;\n};\n\nstruct in_addr {\n\t__be32 s_addr;\n};\n\nstruct xdp_txq_info {\n\tstruct net_device *dev;\n};\n\nstruct xdp_buff {\n\tvoid *data;\n\tvoid *data_end;\n\tvoid *data_meta;\n\tvoid *data_hard_start;\n\tstruct xdp_rxq_info *rxq;\n\tstruct xdp_txq_info *txq;\n\tu32 frame_sz;\n};\n\nstruct bpf_sock_addr_kern {\n\tstruct sock *sk;\n\tstruct sockaddr *uaddr;\n\tu64 tmp_reg;\n\tvoid *t_ctx;\n};\n\nstruct bpf_sock_ops_kern {\n\tstruct sock *sk;\n\tu32 op;\n\tunion {\n\t\tu32 args[4];\n\t\tu32 reply;\n\t\tu32 replylong[4];\n\t};\n\tu32 is_fullsock;\n\tu64 temp;\n};\n\nstruct bpf_sysctl_kern {\n\tstruct ctl_table_header *head;\n\tstruct ctl_table *table;\n\tvoid *cur_val;\n\tsize_t cur_len;\n\tvoid *new_val;\n\tsize_t new_len;\n\tint new_updated;\n\tint write;\n\tloff_t *ppos;\n\tu64 tmp_reg;\n};\n\nstruct bpf_sockopt_kern {\n\tstruct sock *sk;\n\tu8 *optval;\n\tu8 *optval_end;\n\ts32 level;\n\ts32 optname;\n\ts32 optlen;\n\ts32 retval;\n};\n\nstruct sock_reuseport {\n\tstruct callback_head rcu;\n\tu16 max_socks;\n\tu16 num_socks;\n\tunsigned int synq_overflow_ts;\n\tunsigned int reuseport_id;\n\tunsigned int bind_inany: 1;\n\tunsigned int has_conns: 1;\n\tstruct bpf_prog *prog;\n\tstruct sock *socks[0];\n};\n\nstruct tcp_fastopen_cookie {\n\t__le64 val[2];\n\ts8 len;\n\tbool exp;\n};\n\nenum tcp_synack_type {\n\tTCP_SYNACK_NORMAL = 0,\n\tTCP_SYNACK_FASTOPEN = 1,\n\tTCP_SYNACK_COOKIE = 2,\n};\n\nstruct tcp_md5sig_key;\n\nstruct tcp_request_sock_ops {\n\tu16 mss_clamp;\n\tstruct tcp_md5sig_key * (*req_md5_lookup)(const struct sock *, const struct sock *);\n\tint (*calc_md5_hash)(char *, const struct tcp_md5sig_key *, const struct sock *, const struct sk_buff *);\n\tvoid (*init_req)(struct request_sock *, const struct sock *, struct sk_buff *);\n\t__u32 (*cookie_init_seq)(const struct sk_buff *, __u16 *);\n\tstruct dst_entry * (*route_req)(const struct sock *, struct flowi *, const struct request_sock *);\n\tu32 (*init_seq)(const struct sk_buff *);\n\tu32 (*init_ts_off)(const struct net *, const struct sk_buff *);\n\tint (*send_synack)(const struct sock *, struct dst_entry *, struct flowi *, struct request_sock *, struct tcp_fastopen_cookie *, enum tcp_synack_type);\n};\n\nunion tcp_md5_addr {\n\tstruct in_addr a4;\n\tstruct in6_addr a6;\n};\n\nstruct tcp_md5sig_key {\n\tstruct hlist_node node;\n\tu8 keylen;\n\tu8 family;\n\tu8 prefixlen;\n\tunion tcp_md5_addr addr;\n\tint l3index;\n\tu8 key[80];\n\tstruct callback_head rcu;\n};\n\nstruct ip_rt_acct {\n\t__u32 o_bytes;\n\t__u32 o_packets;\n\t__u32 i_bytes;\n\t__u32 i_packets;\n};\n\nstruct inet_ehash_bucket {\n\tstruct hlist_nulls_head chain;\n};\n\nstruct inet_bind_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_head chain;\n};\n\nstruct ack_sample {\n\tu32 pkts_acked;\n\ts32 rtt_us;\n\tu32 in_flight;\n};\n\nstruct rate_sample {\n\tu64 prior_mstamp;\n\tu32 prior_delivered;\n\ts32 delivered;\n\tlong int interval_us;\n\tu32 snd_interval_us;\n\tu32 rcv_interval_us;\n\tlong int rtt_us;\n\tint losses;\n\tu32 acked_sacked;\n\tu32 prior_in_flight;\n\tbool is_app_limited;\n\tbool is_retrans;\n\tbool is_ack_delayed;\n};\n\nstruct sk_msg_sg {\n\tu32 start;\n\tu32 curr;\n\tu32 end;\n\tu32 size;\n\tu32 copybreak;\n\tlong unsigned int copy;\n\tstruct scatterlist data[19];\n};\n\nstruct sk_msg {\n\tstruct sk_msg_sg sg;\n\tvoid *data;\n\tvoid *data_end;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 flags;\n\tstruct sk_buff *skb;\n\tstruct sock *sk_redir;\n\tstruct sock *sk;\n\tstruct list_head list;\n};\n\nenum verifier_phase {\n\tCHECK_META = 0,\n\tCHECK_TYPE = 1,\n};\n\nstruct resolve_vertex {\n\tconst struct btf_type *t;\n\tu32 type_id;\n\tu16 next_member;\n};\n\nenum visit_state {\n\tNOT_VISITED = 0,\n\tVISITED = 1,\n\tRESOLVED = 2,\n};\n\nenum resolve_mode {\n\tRESOLVE_TBD = 0,\n\tRESOLVE_PTR = 1,\n\tRESOLVE_STRUCT_OR_ARRAY = 2,\n};\n\nstruct btf_sec_info {\n\tu32 off;\n\tu32 len;\n};\n\nstruct btf_verifier_env {\n\tstruct btf *btf;\n\tu8 *visit_states;\n\tstruct resolve_vertex stack[32];\n\tstruct bpf_verifier_log log;\n\tu32 log_type_id;\n\tu32 top_stack;\n\tenum verifier_phase phase;\n\tenum resolve_mode resolve_mode;\n};\n\nstruct btf_kind_operations {\n\ts32 (*check_meta)(struct btf_verifier_env *, const struct btf_type *, u32);\n\tint (*resolve)(struct btf_verifier_env *, const struct resolve_vertex *);\n\tint (*check_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tint (*check_kflag_member)(struct btf_verifier_env *, const struct btf_type *, const struct btf_member *, const struct btf_type *);\n\tvoid (*log_details)(struct btf_verifier_env *, const struct btf_type *);\n\tvoid (*seq_show)(const struct btf *, const struct btf_type *, u32, void *, u8, struct seq_file *);\n};\n\nstruct bpf_ctx_convert {\n\tstruct __sk_buff BPF_PROG_TYPE_SOCKET_FILTER_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SOCKET_FILTER_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_CLS_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_CLS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SCHED_ACT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SCHED_ACT_kern;\n\tstruct xdp_md BPF_PROG_TYPE_XDP_prog;\n\tstruct xdp_buff BPF_PROG_TYPE_XDP_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_CGROUP_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_CGROUP_SKB_kern;\n\tstruct bpf_sock BPF_PROG_TYPE_CGROUP_SOCK_prog;\n\tstruct sock BPF_PROG_TYPE_CGROUP_SOCK_kern;\n\tstruct bpf_sock_addr BPF_PROG_TYPE_CGROUP_SOCK_ADDR_prog;\n\tstruct bpf_sock_addr_kern BPF_PROG_TYPE_CGROUP_SOCK_ADDR_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_IN_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_IN_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_OUT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_OUT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_XMIT_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_XMIT_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_prog;\n\tstruct sk_buff BPF_PROG_TYPE_LWT_SEG6LOCAL_kern;\n\tstruct bpf_sock_ops BPF_PROG_TYPE_SOCK_OPS_prog;\n\tstruct bpf_sock_ops_kern BPF_PROG_TYPE_SOCK_OPS_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_SK_SKB_prog;\n\tstruct sk_buff BPF_PROG_TYPE_SK_SKB_kern;\n\tstruct sk_msg_md BPF_PROG_TYPE_SK_MSG_prog;\n\tstruct sk_msg BPF_PROG_TYPE_SK_MSG_kern;\n\tstruct __sk_buff BPF_PROG_TYPE_FLOW_DISSECTOR_prog;\n\tstruct bpf_flow_dissector BPF_PROG_TYPE_FLOW_DISSECTOR_kern;\n\tbpf_user_pt_regs_t BPF_PROG_TYPE_KPROBE_prog;\n\tstruct pt_regs BPF_PROG_TYPE_KPROBE_kern;\n\t__u64 BPF_PROG_TYPE_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_TRACEPOINT_kern;\n\tstruct bpf_perf_event_data BPF_PROG_TYPE_PERF_EVENT_prog;\n\tstruct bpf_perf_event_data_kern BPF_PROG_TYPE_PERF_EVENT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_kern;\n\tstruct bpf_raw_tracepoint_args BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_prog;\n\tu64 BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE_kern;\n\tvoid *BPF_PROG_TYPE_TRACING_prog;\n\tvoid *BPF_PROG_TYPE_TRACING_kern;\n\tstruct bpf_cgroup_dev_ctx BPF_PROG_TYPE_CGROUP_DEVICE_prog;\n\tstruct bpf_cgroup_dev_ctx BPF_PROG_TYPE_CGROUP_DEVICE_kern;\n\tstruct bpf_sysctl BPF_PROG_TYPE_CGROUP_SYSCTL_prog;\n\tstruct bpf_sysctl_kern BPF_PROG_TYPE_CGROUP_SYSCTL_kern;\n\tstruct bpf_sockopt BPF_PROG_TYPE_CGROUP_SOCKOPT_prog;\n\tstruct bpf_sockopt_kern BPF_PROG_TYPE_CGROUP_SOCKOPT_kern;\n\tstruct sk_reuseport_md BPF_PROG_TYPE_SK_REUSEPORT_prog;\n\tstruct sk_reuseport_kern BPF_PROG_TYPE_SK_REUSEPORT_kern;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_prog;\n\tvoid *BPF_PROG_TYPE_STRUCT_OPS_kern;\n\tvoid *BPF_PROG_TYPE_EXT_prog;\n\tvoid *BPF_PROG_TYPE_EXT_kern;\n};\n\nenum {\n\t__ctx_convertBPF_PROG_TYPE_SOCKET_FILTER = 0,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_CLS = 1,\n\t__ctx_convertBPF_PROG_TYPE_SCHED_ACT = 2,\n\t__ctx_convertBPF_PROG_TYPE_XDP = 3,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SKB = 4,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCK = 5,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCK_ADDR = 6,\n\t__ctx_convertBPF_PROG_TYPE_LWT_IN = 7,\n\t__ctx_convertBPF_PROG_TYPE_LWT_OUT = 8,\n\t__ctx_convertBPF_PROG_TYPE_LWT_XMIT = 9,\n\t__ctx_convertBPF_PROG_TYPE_LWT_SEG6LOCAL = 10,\n\t__ctx_convertBPF_PROG_TYPE_SOCK_OPS = 11,\n\t__ctx_convertBPF_PROG_TYPE_SK_SKB = 12,\n\t__ctx_convertBPF_PROG_TYPE_SK_MSG = 13,\n\t__ctx_convertBPF_PROG_TYPE_FLOW_DISSECTOR = 14,\n\t__ctx_convertBPF_PROG_TYPE_KPROBE = 15,\n\t__ctx_convertBPF_PROG_TYPE_TRACEPOINT = 16,\n\t__ctx_convertBPF_PROG_TYPE_PERF_EVENT = 17,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT = 18,\n\t__ctx_convertBPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE = 19,\n\t__ctx_convertBPF_PROG_TYPE_TRACING = 20,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_DEVICE = 21,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SYSCTL = 22,\n\t__ctx_convertBPF_PROG_TYPE_CGROUP_SOCKOPT = 23,\n\t__ctx_convertBPF_PROG_TYPE_SK_REUSEPORT = 24,\n\t__ctx_convertBPF_PROG_TYPE_STRUCT_OPS = 25,\n\t__ctx_convertBPF_PROG_TYPE_EXT = 26,\n\t__ctx_convert_unused = 27,\n};\n\nstruct bpf_devmap_val {\n\t__u32 ifindex;\n\tunion {\n\t\tint fd;\n\t\t__u32 id;\n\t} bpf_prog;\n};\n\nenum net_device_flags {\n\tIFF_UP = 1,\n\tIFF_BROADCAST = 2,\n\tIFF_DEBUG = 4,\n\tIFF_LOOPBACK = 8,\n\tIFF_POINTOPOINT = 16,\n\tIFF_NOTRAILERS = 32,\n\tIFF_RUNNING = 64,\n\tIFF_NOARP = 128,\n\tIFF_PROMISC = 256,\n\tIFF_ALLMULTI = 512,\n\tIFF_MASTER = 1024,\n\tIFF_SLAVE = 2048,\n\tIFF_MULTICAST = 4096,\n\tIFF_PORTSEL = 8192,\n\tIFF_AUTOMEDIA = 16384,\n\tIFF_DYNAMIC = 32768,\n\tIFF_LOWER_UP = 65536,\n\tIFF_DORMANT = 131072,\n\tIFF_ECHO = 262144,\n};\n\nstruct xdp_dev_bulk_queue {\n\tstruct xdp_frame *q[16];\n\tstruct list_head flush_node;\n\tstruct net_device *dev;\n\tstruct net_device *dev_rx;\n\tunsigned int count;\n};\n\nenum netdev_cmd {\n\tNETDEV_UP = 1,\n\tNETDEV_DOWN = 2,\n\tNETDEV_REBOOT = 3,\n\tNETDEV_CHANGE = 4,\n\tNETDEV_REGISTER = 5,\n\tNETDEV_UNREGISTER = 6,\n\tNETDEV_CHANGEMTU = 7,\n\tNETDEV_CHANGEADDR = 8,\n\tNETDEV_PRE_CHANGEADDR = 9,\n\tNETDEV_GOING_DOWN = 10,\n\tNETDEV_CHANGENAME = 11,\n\tNETDEV_FEAT_CHANGE = 12,\n\tNETDEV_BONDING_FAILOVER = 13,\n\tNETDEV_PRE_UP = 14,\n\tNETDEV_PRE_TYPE_CHANGE = 15,\n\tNETDEV_POST_TYPE_CHANGE = 16,\n\tNETDEV_POST_INIT = 17,\n\tNETDEV_RELEASE = 18,\n\tNETDEV_NOTIFY_PEERS = 19,\n\tNETDEV_JOIN = 20,\n\tNETDEV_CHANGEUPPER = 21,\n\tNETDEV_RESEND_IGMP = 22,\n\tNETDEV_PRECHANGEMTU = 23,\n\tNETDEV_CHANGEINFODATA = 24,\n\tNETDEV_BONDING_INFO = 25,\n\tNETDEV_PRECHANGEUPPER = 26,\n\tNETDEV_CHANGELOWERSTATE = 27,\n\tNETDEV_UDP_TUNNEL_PUSH_INFO = 28,\n\tNETDEV_UDP_TUNNEL_DROP_INFO = 29,\n\tNETDEV_CHANGE_TX_QUEUE_LEN = 30,\n\tNETDEV_CVLAN_FILTER_PUSH_INFO = 31,\n\tNETDEV_CVLAN_FILTER_DROP_INFO = 32,\n\tNETDEV_SVLAN_FILTER_PUSH_INFO = 33,\n\tNETDEV_SVLAN_FILTER_DROP_INFO = 34,\n};\n\nstruct netdev_notifier_info {\n\tstruct net_device *dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct bpf_dtab;\n\nstruct bpf_dtab_netdev {\n\tstruct net_device *dev;\n\tstruct hlist_node index_hlist;\n\tstruct bpf_dtab *dtab;\n\tstruct bpf_prog *xdp_prog;\n\tstruct callback_head rcu;\n\tunsigned int idx;\n\tstruct bpf_devmap_val val;\n};\n\nstruct bpf_dtab {\n\tstruct bpf_map map;\n\tstruct bpf_dtab_netdev **netdev_map;\n\tstruct list_head list;\n\tstruct hlist_head *dev_index_head;\n\tspinlock_t index_lock;\n\tunsigned int items;\n\tu32 n_buckets;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef struct bio_vec skb_frag_t;\n\nstruct skb_shared_hwtstamps {\n\tktime_t hwtstamp;\n};\n\nstruct skb_shared_info {\n\t__u8 __unused;\n\t__u8 meta_len;\n\t__u8 nr_frags;\n\t__u8 tx_flags;\n\tshort unsigned int gso_size;\n\tshort unsigned int gso_segs;\n\tstruct sk_buff *frag_list;\n\tstruct skb_shared_hwtstamps hwtstamps;\n\tunsigned int gso_type;\n\tu32 tskey;\n\tatomic_t dataref;\n\tvoid *destructor_arg;\n\tskb_frag_t frags[17];\n};\n\nstruct ptr_ring {\n\tint producer;\n\tspinlock_t producer_lock;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tint consumer_head;\n\tint consumer_tail;\n\tspinlock_t consumer_lock;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tint size;\n\tint batch;\n\tvoid **queue;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_cpu_map_entry;\n\nstruct xdp_bulk_queue {\n\tvoid *q[8];\n\tstruct list_head flush_node;\n\tstruct bpf_cpu_map_entry *obj;\n\tunsigned int count;\n};\n\nstruct bpf_cpu_map;\n\nstruct bpf_cpu_map_entry {\n\tu32 cpu;\n\tint map_id;\n\tu32 qsize;\n\tstruct xdp_bulk_queue *bulkq;\n\tstruct bpf_cpu_map *cmap;\n\tstruct ptr_ring *queue;\n\tstruct task_struct *kthread;\n\tstruct work_struct kthread_stop_wq;\n\tatomic_t refcnt;\n\tstruct callback_head rcu;\n};\n\nstruct bpf_cpu_map {\n\tstruct bpf_map map;\n\tstruct bpf_cpu_map_entry **cpu_map;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rhlist_head {\n\tstruct rhash_head rhead;\n\tstruct rhlist_head *next;\n};\n\nstruct bpf_prog_offload_ops {\n\tint (*insn_hook)(struct bpf_verifier_env *, int, int);\n\tint (*finalize)(struct bpf_verifier_env *);\n\tint (*replace_insn)(struct bpf_verifier_env *, u32, struct bpf_insn *);\n\tint (*remove_insns)(struct bpf_verifier_env *, u32, u32);\n\tint (*prepare)(struct bpf_prog *);\n\tint (*translate)(struct bpf_prog *);\n\tvoid (*destroy)(struct bpf_prog *);\n};\n\nstruct bpf_offload_dev {\n\tconst struct bpf_prog_offload_ops *ops;\n\tstruct list_head netdevs;\n\tvoid *priv;\n};\n\nstruct bpf_offload_netdev {\n\tstruct rhash_head l;\n\tstruct net_device *netdev;\n\tstruct bpf_offload_dev *offdev;\n\tstruct list_head progs;\n\tstruct list_head maps;\n\tstruct list_head offdev_netdevs;\n};\n\nstruct ns_get_path_bpf_prog_args {\n\tstruct bpf_prog *prog;\n\tstruct bpf_prog_info *info;\n};\n\nstruct ns_get_path_bpf_map_args {\n\tstruct bpf_offloaded_map *offmap;\n\tstruct bpf_map_info *info;\n};\n\nstruct bpf_netns_link {\n\tstruct bpf_link link;\n\tenum bpf_attach_type type;\n\tenum netns_bpf_attach_type netns_type;\n\tstruct net *net;\n\tstruct list_head node;\n};\n\nenum bpf_stack_build_id_status {\n\tBPF_STACK_BUILD_ID_EMPTY = 0,\n\tBPF_STACK_BUILD_ID_VALID = 1,\n\tBPF_STACK_BUILD_ID_IP = 2,\n};\n\nstruct bpf_stack_build_id {\n\t__s32 status;\n\tunsigned char build_id[20];\n\tunion {\n\t\t__u64 offset;\n\t\t__u64 ip;\n\t};\n};\n\nenum {\n\tBPF_F_SKIP_FIELD_MASK = 255,\n\tBPF_F_USER_STACK = 256,\n\tBPF_F_FAST_STACK_CMP = 512,\n\tBPF_F_REUSE_STACKID = 1024,\n\tBPF_F_USER_BUILD_ID = 2048,\n};\n\ntypedef __u32 Elf32_Addr;\n\ntypedef __u16 Elf32_Half;\n\ntypedef __u32 Elf32_Off;\n\nstruct elf32_hdr {\n\tunsigned char e_ident[16];\n\tElf32_Half e_type;\n\tElf32_Half e_machine;\n\tElf32_Word e_version;\n\tElf32_Addr e_entry;\n\tElf32_Off e_phoff;\n\tElf32_Off e_shoff;\n\tElf32_Word e_flags;\n\tElf32_Half e_ehsize;\n\tElf32_Half e_phentsize;\n\tElf32_Half e_phnum;\n\tElf32_Half e_shentsize;\n\tElf32_Half e_shnum;\n\tElf32_Half e_shstrndx;\n};\n\ntypedef struct elf32_hdr Elf32_Ehdr;\n\nstruct elf32_phdr {\n\tElf32_Word p_type;\n\tElf32_Off p_offset;\n\tElf32_Addr p_vaddr;\n\tElf32_Addr p_paddr;\n\tElf32_Word p_filesz;\n\tElf32_Word p_memsz;\n\tElf32_Word p_flags;\n\tElf32_Word p_align;\n};\n\ntypedef struct elf32_phdr Elf32_Phdr;\n\nstruct elf64_phdr {\n\tElf64_Word p_type;\n\tElf64_Word p_flags;\n\tElf64_Off p_offset;\n\tElf64_Addr p_vaddr;\n\tElf64_Addr p_paddr;\n\tElf64_Xword p_filesz;\n\tElf64_Xword p_memsz;\n\tElf64_Xword p_align;\n};\n\ntypedef struct elf64_phdr Elf64_Phdr;\n\ntypedef struct elf32_note Elf32_Nhdr;\n\nstruct stack_map_bucket {\n\tstruct pcpu_freelist_node fnode;\n\tu32 hash;\n\tu32 nr;\n\tu64 data[0];\n};\n\nstruct bpf_stack_map {\n\tstruct bpf_map map;\n\tvoid *elems;\n\tstruct pcpu_freelist freelist;\n\tu32 n_buckets;\n\tstruct stack_map_bucket *buckets[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct stack_map_irq_work {\n\tstruct irq_work irq_work;\n\tstruct mm_struct *mm;\n};\n\ntypedef u64 (*btf_bpf_get_stackid)(struct pt_regs *, struct bpf_map *, u64);\n\ntypedef u64 (*btf_bpf_get_stack)(struct pt_regs *, void *, u32, u64);\n\nenum {\n\tBPF_F_SYSCTL_BASE_NAME = 1,\n};\n\nstruct bpf_prog_list {\n\tstruct list_head node;\n\tstruct bpf_prog *prog;\n\tstruct bpf_cgroup_link *link;\n\tstruct bpf_cgroup_storage *storage[2];\n};\n\nstruct qdisc_skb_cb {\n\tstruct {\n\t\tunsigned int pkt_len;\n\t\tu16 slave_dev_queue_mapping;\n\t\tu16 tc_classid;\n\t};\n\tunsigned char data[20];\n};\n\nstruct bpf_skb_data_end {\n\tstruct qdisc_skb_cb qdisc_cb;\n\tvoid *data_meta;\n\tvoid *data_end;\n};\n\nenum {\n\tTCPF_ESTABLISHED = 2,\n\tTCPF_SYN_SENT = 4,\n\tTCPF_SYN_RECV = 8,\n\tTCPF_FIN_WAIT1 = 16,\n\tTCPF_FIN_WAIT2 = 32,\n\tTCPF_TIME_WAIT = 64,\n\tTCPF_CLOSE = 128,\n\tTCPF_CLOSE_WAIT = 256,\n\tTCPF_LAST_ACK = 512,\n\tTCPF_LISTEN = 1024,\n\tTCPF_CLOSING = 2048,\n\tTCPF_NEW_SYN_RECV = 4096,\n};\n\ntypedef u64 (*btf_bpf_sysctl_get_name)(struct bpf_sysctl_kern *, char *, size_t, u64);\n\ntypedef u64 (*btf_bpf_sysctl_get_current_value)(struct bpf_sysctl_kern *, char *, size_t);\n\ntypedef u64 (*btf_bpf_sysctl_get_new_value)(struct bpf_sysctl_kern *, char *, size_t);\n\ntypedef u64 (*btf_bpf_sysctl_set_new_value)(struct bpf_sysctl_kern *, const char *, size_t);\n\nenum sock_type {\n\tSOCK_STREAM = 1,\n\tSOCK_DGRAM = 2,\n\tSOCK_RAW = 3,\n\tSOCK_RDM = 4,\n\tSOCK_SEQPACKET = 5,\n\tSOCK_DCCP = 6,\n\tSOCK_PACKET = 10,\n};\n\nenum {\n\tIPPROTO_IP = 0,\n\tIPPROTO_ICMP = 1,\n\tIPPROTO_IGMP = 2,\n\tIPPROTO_IPIP = 4,\n\tIPPROTO_TCP = 6,\n\tIPPROTO_EGP = 8,\n\tIPPROTO_PUP = 12,\n\tIPPROTO_UDP = 17,\n\tIPPROTO_IDP = 22,\n\tIPPROTO_TP = 29,\n\tIPPROTO_DCCP = 33,\n\tIPPROTO_IPV6 = 41,\n\tIPPROTO_RSVP = 46,\n\tIPPROTO_GRE = 47,\n\tIPPROTO_ESP = 50,\n\tIPPROTO_AH = 51,\n\tIPPROTO_MTP = 92,\n\tIPPROTO_BEETPH = 94,\n\tIPPROTO_ENCAP = 98,\n\tIPPROTO_PIM = 103,\n\tIPPROTO_COMP = 108,\n\tIPPROTO_SCTP = 132,\n\tIPPROTO_UDPLITE = 136,\n\tIPPROTO_MPLS = 137,\n\tIPPROTO_ETHERNET = 143,\n\tIPPROTO_RAW = 255,\n\tIPPROTO_MPTCP = 262,\n\tIPPROTO_MAX = 263,\n};\n\nenum sock_flags {\n\tSOCK_DEAD = 0,\n\tSOCK_DONE = 1,\n\tSOCK_URGINLINE = 2,\n\tSOCK_KEEPOPEN = 3,\n\tSOCK_LINGER = 4,\n\tSOCK_DESTROY = 5,\n\tSOCK_BROADCAST = 6,\n\tSOCK_TIMESTAMP = 7,\n\tSOCK_ZAPPED = 8,\n\tSOCK_USE_WRITE_QUEUE = 9,\n\tSOCK_DBG = 10,\n\tSOCK_RCVTSTAMP = 11,\n\tSOCK_RCVTSTAMPNS = 12,\n\tSOCK_LOCALROUTE = 13,\n\tSOCK_QUEUE_SHRUNK = 14,\n\tSOCK_MEMALLOC = 15,\n\tSOCK_TIMESTAMPING_RX_SOFTWARE = 16,\n\tSOCK_FASYNC = 17,\n\tSOCK_RXQ_OVFL = 18,\n\tSOCK_ZEROCOPY = 19,\n\tSOCK_WIFI_STATUS = 20,\n\tSOCK_NOFCS = 21,\n\tSOCK_FILTER_LOCKED = 22,\n\tSOCK_SELECT_ERR_QUEUE = 23,\n\tSOCK_RCU_FREE = 24,\n\tSOCK_TXTIME = 25,\n\tSOCK_XDP = 26,\n\tSOCK_TSTAMP_NEW = 27,\n};\n\nstruct reuseport_array {\n\tstruct bpf_map map;\n\tstruct sock *ptrs[0];\n};\n\nenum bpf_struct_ops_state {\n\tBPF_STRUCT_OPS_STATE_INIT = 0,\n\tBPF_STRUCT_OPS_STATE_INUSE = 1,\n\tBPF_STRUCT_OPS_STATE_TOBEFREE = 2,\n};\n\nstruct bpf_struct_ops_value {\n\trefcount_t refcnt;\n\tenum bpf_struct_ops_state state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar data[0];\n};\n\nstruct bpf_struct_ops_map {\n\tstruct bpf_map map;\n\tconst struct bpf_struct_ops *st_ops;\n\tstruct mutex lock;\n\tstruct bpf_prog **progs;\n\tvoid *image;\n\tstruct bpf_struct_ops_value *uvalue;\n\tstruct bpf_struct_ops_value kvalue;\n};\n\nstruct bpf_struct_ops_tcp_congestion_ops {\n\trefcount_t refcnt;\n\tenum bpf_struct_ops_state state;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct tcp_congestion_ops data;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nenum perf_event_read_format {\n\tPERF_FORMAT_TOTAL_TIME_ENABLED = 1,\n\tPERF_FORMAT_TOTAL_TIME_RUNNING = 2,\n\tPERF_FORMAT_ID = 4,\n\tPERF_FORMAT_GROUP = 8,\n\tPERF_FORMAT_MAX = 16,\n};\n\nenum perf_event_ioc_flags {\n\tPERF_IOC_FLAG_GROUP = 1,\n};\n\nstruct perf_ns_link_info {\n\t__u64 dev;\n\t__u64 ino;\n};\n\nenum {\n\tNET_NS_INDEX = 0,\n\tUTS_NS_INDEX = 1,\n\tIPC_NS_INDEX = 2,\n\tPID_NS_INDEX = 3,\n\tUSER_NS_INDEX = 4,\n\tMNT_NS_INDEX = 5,\n\tCGROUP_NS_INDEX = 6,\n\tNR_NAMESPACES = 7,\n};\n\nenum perf_event_type {\n\tPERF_RECORD_MMAP = 1,\n\tPERF_RECORD_LOST = 2,\n\tPERF_RECORD_COMM = 3,\n\tPERF_RECORD_EXIT = 4,\n\tPERF_RECORD_THROTTLE = 5,\n\tPERF_RECORD_UNTHROTTLE = 6,\n\tPERF_RECORD_FORK = 7,\n\tPERF_RECORD_READ = 8,\n\tPERF_RECORD_SAMPLE = 9,\n\tPERF_RECORD_MMAP2 = 10,\n\tPERF_RECORD_AUX = 11,\n\tPERF_RECORD_ITRACE_START = 12,\n\tPERF_RECORD_LOST_SAMPLES = 13,\n\tPERF_RECORD_SWITCH = 14,\n\tPERF_RECORD_SWITCH_CPU_WIDE = 15,\n\tPERF_RECORD_NAMESPACES = 16,\n\tPERF_RECORD_KSYMBOL = 17,\n\tPERF_RECORD_BPF_EVENT = 18,\n\tPERF_RECORD_CGROUP = 19,\n\tPERF_RECORD_MAX = 20,\n};\n\nstruct swevent_hlist {\n\tstruct hlist_head heads[256];\n\tstruct callback_head callback_head;\n};\n\nstruct pmu_event_list {\n\traw_spinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct perf_buffer {\n\trefcount_t refcount;\n\tstruct callback_head callback_head;\n\tint nr_pages;\n\tint overwrite;\n\tint paused;\n\tatomic_t poll;\n\tlocal_t head;\n\tunsigned int nest;\n\tlocal_t events;\n\tlocal_t wakeup;\n\tlocal_t lost;\n\tlong int watermark;\n\tlong int aux_watermark;\n\tspinlock_t event_lock;\n\tstruct list_head event_list;\n\tatomic_t mmap_count;\n\tlong unsigned int mmap_locked;\n\tstruct user_struct *mmap_user;\n\tlong int aux_head;\n\tunsigned int aux_nest;\n\tlong int aux_wakeup;\n\tlong unsigned int aux_pgoff;\n\tint aux_nr_pages;\n\tint aux_overwrite;\n\tatomic_t aux_mmap_count;\n\tlong unsigned int aux_mmap_locked;\n\tvoid (*free_aux)(void *);\n\trefcount_t aux_refcount;\n\tint aux_in_sampling;\n\tvoid **aux_pages;\n\tvoid *aux_priv;\n\tstruct perf_event_mmap_page *user_page;\n\tvoid *data_pages[0];\n};\n\nstruct match_token {\n\tint token;\n\tconst char *pattern;\n};\n\nenum {\n\tMAX_OPT_ARGS = 3,\n};\n\ntypedef struct {\n\tchar *from;\n\tchar *to;\n} substring_t;\n\nstruct min_heap {\n\tvoid *data;\n\tint nr;\n\tint size;\n};\n\nstruct min_heap_callbacks {\n\tint elem_size;\n\tbool (*less)(const void *, const void *);\n\tvoid (*swp)(void *, void *);\n};\n\ntypedef int (*remote_function_f)(void *);\n\nstruct remote_function_call {\n\tstruct task_struct *p;\n\tremote_function_f func;\n\tvoid *info;\n\tint ret;\n};\n\ntypedef void (*event_f)(struct perf_event *, struct perf_cpu_context *, struct perf_event_context *, void *);\n\nstruct event_function_struct {\n\tstruct perf_event *event;\n\tevent_f func;\n\tvoid *data;\n};\n\nenum event_type_t {\n\tEVENT_FLEXIBLE = 1,\n\tEVENT_PINNED = 2,\n\tEVENT_TIME = 4,\n\tEVENT_CPU = 8,\n\tEVENT_ALL = 3,\n};\n\nstruct stop_event_data {\n\tstruct perf_event *event;\n\tunsigned int restart;\n};\n\nstruct perf_read_data {\n\tstruct perf_event *event;\n\tbool group;\n\tint ret;\n};\n\nstruct perf_read_event {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\ntypedef void perf_iterate_f(struct perf_event *, void *);\n\nstruct remote_output {\n\tstruct perf_buffer *rb;\n\tint err;\n};\n\nstruct perf_task_event {\n\tstruct task_struct *task;\n\tstruct perf_event_context *task_ctx;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 ppid;\n\t\tu32 tid;\n\t\tu32 ptid;\n\t\tu64 time;\n\t} event_id;\n};\n\nstruct perf_comm_event {\n\tstruct task_struct *task;\n\tchar *comm;\n\tint comm_size;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t} event_id;\n};\n\nstruct perf_namespaces_event {\n\tstruct task_struct *task;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 nr_namespaces;\n\t\tstruct perf_ns_link_info link_info[7];\n\t} event_id;\n};\n\nstruct perf_mmap_event {\n\tstruct vm_area_struct *vma;\n\tconst char *file_name;\n\tint file_size;\n\tint maj;\n\tint min;\n\tu64 ino;\n\tu64 ino_generation;\n\tu32 prot;\n\tu32 flags;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 pid;\n\t\tu32 tid;\n\t\tu64 start;\n\t\tu64 len;\n\t\tu64 pgoff;\n\t} event_id;\n};\n\nstruct perf_switch_event {\n\tstruct task_struct *task;\n\tstruct task_struct *next_prev;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu32 next_prev_pid;\n\t\tu32 next_prev_tid;\n\t} event_id;\n};\n\nstruct perf_ksymbol_event {\n\tconst char *name;\n\tint name_len;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu64 addr;\n\t\tu32 len;\n\t\tu16 ksym_type;\n\t\tu16 flags;\n\t} event_id;\n};\n\nstruct perf_bpf_event {\n\tstruct bpf_prog *prog;\n\tstruct {\n\t\tstruct perf_event_header header;\n\t\tu16 type;\n\t\tu16 flags;\n\t\tu32 id;\n\t\tu8 tag[8];\n\t} event_id;\n};\n\nstruct swevent_htable {\n\tstruct swevent_hlist *swevent_hlist;\n\tstruct mutex hlist_mutex;\n\tint hlist_refcount;\n\tint recursion[4];\n};\n\nenum perf_probe_config {\n\tPERF_PROBE_CONFIG_IS_RETPROBE = 1,\n\tPERF_UPROBE_REF_CTR_OFFSET_BITS = 32,\n\tPERF_UPROBE_REF_CTR_OFFSET_SHIFT = 32,\n};\n\nenum {\n\tIF_ACT_NONE = 4294967295,\n\tIF_ACT_FILTER = 0,\n\tIF_ACT_START = 1,\n\tIF_ACT_STOP = 2,\n\tIF_SRC_FILE = 3,\n\tIF_SRC_KERNEL = 4,\n\tIF_SRC_FILEADDR = 5,\n\tIF_SRC_KERNELADDR = 6,\n};\n\nenum {\n\tIF_STATE_ACTION = 0,\n\tIF_STATE_SOURCE = 1,\n\tIF_STATE_END = 2,\n};\n\nstruct perf_aux_event {\n\tstruct perf_event_header header;\n\tu32 pid;\n\tu32 tid;\n};\n\nstruct perf_aux_event___2 {\n\tstruct perf_event_header header;\n\tu64 offset;\n\tu64 size;\n\tu64 flags;\n};\n\nenum perf_callchain_context {\n\tPERF_CONTEXT_HV = 4294967264,\n\tPERF_CONTEXT_KERNEL = 4294967168,\n\tPERF_CONTEXT_USER = 4294966784,\n\tPERF_CONTEXT_GUEST = 4294965248,\n\tPERF_CONTEXT_GUEST_KERNEL = 4294965120,\n\tPERF_CONTEXT_GUEST_USER = 4294964736,\n\tPERF_CONTEXT_MAX = 4294963201,\n};\n\nstruct callchain_cpus_entries {\n\tstruct callback_head callback_head;\n\tstruct perf_callchain_entry *cpu_entries[0];\n};\n\nenum bp_type_idx {\n\tTYPE_INST = 0,\n\tTYPE_DATA = 0,\n\tTYPE_MAX = 1,\n};\n\nstruct bp_cpuinfo {\n\tunsigned int cpu_pinned;\n\tunsigned int *tsk_pinned;\n\tunsigned int flexible;\n};\n\nstruct bp_busy_slots {\n\tunsigned int pinned;\n\tunsigned int flexible;\n};\n\ntypedef u8 uprobe_opcode_t;\n\nstruct uprobe {\n\tstruct rb_node rb_node;\n\trefcount_t ref;\n\tstruct rw_semaphore register_rwsem;\n\tstruct rw_semaphore consumer_rwsem;\n\tstruct list_head pending_list;\n\tstruct uprobe_consumer *consumers;\n\tstruct inode *inode;\n\tloff_t offset;\n\tloff_t ref_ctr_offset;\n\tlong unsigned int flags;\n\tstruct arch_uprobe arch;\n};\n\nstruct xol_area {\n\twait_queue_head_t wq;\n\tatomic_t slot_count;\n\tlong unsigned int *bitmap;\n\tstruct vm_special_mapping xol_mapping;\n\tstruct page *pages[2];\n\tlong unsigned int vaddr;\n};\n\ntypedef long unsigned int vm_flags_t;\n\nstruct compact_control;\n\nstruct capture_control {\n\tstruct compact_control *cc;\n\tstruct page *page;\n};\n\nstruct page_vma_mapped_walk {\n\tstruct page *page;\n\tstruct vm_area_struct *vma;\n\tlong unsigned int address;\n\tpmd_t *pmd;\n\tpte_t *pte;\n\tspinlock_t *ptl;\n\tunsigned int flags;\n};\n\nenum mmu_notifier_event {\n\tMMU_NOTIFY_UNMAP = 0,\n\tMMU_NOTIFY_CLEAR = 1,\n\tMMU_NOTIFY_PROTECTION_VMA = 2,\n\tMMU_NOTIFY_PROTECTION_PAGE = 3,\n\tMMU_NOTIFY_SOFT_DIRTY = 4,\n\tMMU_NOTIFY_RELEASE = 5,\n};\n\nstruct mmu_notifier_range {\n\tstruct vm_area_struct *vma;\n\tstruct mm_struct *mm;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tunsigned int flags;\n\tenum mmu_notifier_event event;\n};\n\nstruct compact_control {\n\tstruct list_head freepages;\n\tstruct list_head migratepages;\n\tunsigned int nr_freepages;\n\tunsigned int nr_migratepages;\n\tlong unsigned int free_pfn;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int fast_start_pfn;\n\tstruct zone *zone;\n\tlong unsigned int total_migrate_scanned;\n\tlong unsigned int total_free_scanned;\n\tshort unsigned int fast_search_fail;\n\tshort int search_order;\n\tconst gfp_t gfp_mask;\n\tint order;\n\tint migratetype;\n\tconst unsigned int alloc_flags;\n\tconst int highest_zoneidx;\n\tenum migrate_mode mode;\n\tbool ignore_skip_hint;\n\tbool no_set_skip_hint;\n\tbool ignore_block_suitable;\n\tbool direct_compaction;\n\tbool whole_zone;\n\tbool contended;\n\tbool rescan;\n\tbool alloc_contig;\n};\n\nstruct delayed_uprobe {\n\tstruct list_head list;\n\tstruct uprobe *uprobe;\n\tstruct mm_struct *mm;\n};\n\nstruct map_info {\n\tstruct map_info *next;\n\tstruct mm_struct *mm;\n\tlong unsigned int vaddr;\n};\n\nstruct static_key_mod {\n\tstruct static_key_mod *next;\n\tstruct jump_entry *entries;\n\tstruct module *mod;\n};\n\nstruct static_key_deferred {\n\tstruct static_key key;\n\tlong unsigned int timeout;\n\tstruct delayed_work work;\n};\n\nenum rseq_cpu_id_state {\n\tRSEQ_CPU_ID_UNINITIALIZED = 4294967295,\n\tRSEQ_CPU_ID_REGISTRATION_FAILED = 4294967294,\n};\n\nenum rseq_flags {\n\tRSEQ_FLAG_UNREGISTER = 1,\n};\n\nenum rseq_cs_flags {\n\tRSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT = 1,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL = 2,\n\tRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE = 4,\n};\n\nstruct rseq_cs {\n\t__u32 version;\n\t__u32 flags;\n\t__u64 start_ip;\n\t__u64 post_commit_offset;\n\t__u64 abort_ip;\n};\n\nstruct trace_event_raw_rseq_update {\n\tstruct trace_entry ent;\n\ts32 cpu_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rseq_ip_fixup {\n\tstruct trace_entry ent;\n\tlong unsigned int regs_ip;\n\tlong unsigned int start_ip;\n\tlong unsigned int post_commit_offset;\n\tlong unsigned int abort_ip;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_rseq_update {};\n\nstruct trace_event_data_offsets_rseq_ip_fixup {};\n\ntypedef void (*btf_trace_rseq_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_rseq_ip_fixup)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\nstruct __key_reference_with_attributes;\n\ntypedef struct __key_reference_with_attributes *key_ref_t;\n\nenum key_being_used_for {\n\tVERIFYING_MODULE_SIGNATURE = 0,\n\tVERIFYING_FIRMWARE_SIGNATURE = 1,\n\tVERIFYING_KEXEC_PE_SIGNATURE = 2,\n\tVERIFYING_KEY_SIGNATURE = 3,\n\tVERIFYING_KEY_SELF_SIGNATURE = 4,\n\tVERIFYING_UNSPECIFIED_SIGNATURE = 5,\n\tNR__KEY_BEING_USED_FOR = 6,\n};\n\nstruct key_preparsed_payload {\n\tchar *description;\n\tunion key_payload payload;\n\tconst void *data;\n\tsize_t datalen;\n\tsize_t quotalen;\n\ttime64_t expiry;\n};\n\nstruct key_match_data {\n\tbool (*cmp)(const struct key *, const struct key_match_data *);\n\tconst void *raw_data;\n\tvoid *preparsed;\n\tunsigned int lookup_type;\n};\n\nenum kernel_pkey_operation {\n\tkernel_pkey_encrypt = 0,\n\tkernel_pkey_decrypt = 1,\n\tkernel_pkey_sign = 2,\n\tkernel_pkey_verify = 3,\n};\n\nstruct kernel_pkey_params {\n\tstruct key *key;\n\tconst char *encoding;\n\tconst char *hash_algo;\n\tchar *info;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\tenum kernel_pkey_operation op: 8;\n};\n\nstruct kernel_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n};\n\nstruct asymmetric_key_subtype;\n\nstruct pkcs7_message;\n\ntypedef struct pglist_data pg_data_t;\n\ntypedef void (*xa_update_node_t)(struct xa_node *);\n\nstruct xa_state {\n\tstruct xarray *xa;\n\tlong unsigned int xa_index;\n\tunsigned char xa_shift;\n\tunsigned char xa_sibs;\n\tunsigned char xa_offset;\n\tunsigned char xa_pad;\n\tstruct xa_node *xa_node;\n\tstruct xa_node *xa_alloc;\n\txa_update_node_t xa_update;\n};\n\nenum positive_aop_returns {\n\tAOP_WRITEPAGE_ACTIVATE = 524288,\n\tAOP_TRUNCATED_PAGE = 524289,\n};\n\nenum mapping_flags {\n\tAS_EIO = 0,\n\tAS_ENOSPC = 1,\n\tAS_MM_ALL_LOCKS = 2,\n\tAS_UNEVICTABLE = 3,\n\tAS_EXITING = 4,\n\tAS_NO_WRITEBACK_TAGS = 5,\n};\n\nenum iter_type {\n\tITER_IOVEC = 4,\n\tITER_KVEC = 8,\n\tITER_BVEC = 16,\n\tITER_PIPE = 32,\n\tITER_DISCARD = 64,\n};\n\nstruct pagevec {\n\tunsigned char nr;\n\tbool percpu_pvec_drained;\n\tstruct page *pages[15];\n};\n\nstruct fid {\n\tunion {\n\t\tstruct {\n\t\t\tu32 ino;\n\t\t\tu32 gen;\n\t\t\tu32 parent_ino;\n\t\t\tu32 parent_gen;\n\t\t} i32;\n\t\tstruct {\n\t\t\tu32 block;\n\t\t\tu16 partref;\n\t\t\tu16 parent_partref;\n\t\t\tu32 generation;\n\t\t\tu32 parent_block;\n\t\t\tu32 parent_generation;\n\t\t} udf;\n\t\t__u32 raw[0];\n\t};\n};\n\nstruct trace_event_raw_mm_filemap_op_page_cache {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tlong unsigned int i_ino;\n\tlong unsigned int index;\n\tdev_t s_dev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filemap_set_wb_err {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t errseq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_file_check_and_advance_wb_err {\n\tstruct trace_entry ent;\n\tstruct file *file;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\terrseq_t old;\n\terrseq_t new;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_mm_filemap_op_page_cache {};\n\nstruct trace_event_data_offsets_filemap_set_wb_err {};\n\nstruct trace_event_data_offsets_file_check_and_advance_wb_err {};\n\ntypedef void (*btf_trace_mm_filemap_delete_from_page_cache)(void *, struct page *);\n\ntypedef void (*btf_trace_mm_filemap_add_to_page_cache)(void *, struct page *);\n\ntypedef void (*btf_trace_filemap_set_wb_err)(void *, struct address_space *, errseq_t);\n\ntypedef void (*btf_trace_file_check_and_advance_wb_err)(void *, struct file *, errseq_t);\n\nstruct wait_page_key {\n\tstruct page *page;\n\tint bit_nr;\n\tint page_match;\n};\n\nstruct wait_page_queue {\n\tstruct page *page;\n\tint bit_nr;\n\twait_queue_entry_t wait;\n};\n\nenum behavior {\n\tEXCLUSIVE = 0,\n\tSHARED = 1,\n\tDROP = 2,\n};\n\nstruct kmem_cache_order_objects {\n\tunsigned int x;\n};\n\nstruct kmem_cache_cpu;\n\nstruct kmem_cache_node;\n\nstruct kmem_cache {\n\tstruct kmem_cache_cpu *cpu_slab;\n\tslab_flags_t flags;\n\tlong unsigned int min_partial;\n\tunsigned int size;\n\tunsigned int object_size;\n\tunsigned int offset;\n\tunsigned int cpu_partial;\n\tstruct kmem_cache_order_objects oo;\n\tstruct kmem_cache_order_objects max;\n\tstruct kmem_cache_order_objects min;\n\tgfp_t allocflags;\n\tint refcount;\n\tvoid (*ctor)(void *);\n\tunsigned int inuse;\n\tunsigned int align;\n\tunsigned int red_left_pad;\n\tconst char *name;\n\tstruct list_head list;\n\tstruct kobject kobj;\n\tstruct work_struct kobj_remove_work;\n\tunsigned int remote_node_defrag_ratio;\n\tunsigned int useroffset;\n\tunsigned int usersize;\n\tstruct kmem_cache_node *node[64];\n};\n\nstruct kmem_cache_cpu {\n\tvoid **freelist;\n\tlong unsigned int tid;\n\tstruct page *page;\n\tstruct page *partial;\n};\n\nstruct kmem_cache_node {\n\tspinlock_t list_lock;\n\tlong unsigned int nr_partial;\n\tstruct list_head partial;\n\tatomic_long_t nr_slabs;\n\tatomic_long_t total_objects;\n\tstruct list_head full;\n};\n\nenum slab_state {\n\tDOWN = 0,\n\tPARTIAL = 1,\n\tPARTIAL_NODE = 2,\n\tUP = 3,\n\tFULL = 4,\n};\n\nstruct kmalloc_info_struct {\n\tconst char *name[3];\n\tunsigned int size;\n};\n\nenum oom_constraint {\n\tCONSTRAINT_NONE = 0,\n\tCONSTRAINT_CPUSET = 1,\n\tCONSTRAINT_MEMORY_POLICY = 2,\n\tCONSTRAINT_MEMCG = 3,\n};\n\nstruct oom_control {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *memcg;\n\tconst gfp_t gfp_mask;\n\tconst int order;\n\tlong unsigned int totalpages;\n\tstruct task_struct *chosen;\n\tlong unsigned int chosen_points;\n\tenum oom_constraint constraint;\n};\n\nenum memcg_memory_event {\n\tMEMCG_LOW = 0,\n\tMEMCG_HIGH = 1,\n\tMEMCG_MAX = 2,\n\tMEMCG_OOM = 3,\n\tMEMCG_OOM_KILL = 4,\n\tMEMCG_SWAP_HIGH = 5,\n\tMEMCG_SWAP_MAX = 6,\n\tMEMCG_SWAP_FAIL = 7,\n\tMEMCG_NR_MEMORY_EVENTS = 8,\n};\n\nenum compact_priority {\n\tCOMPACT_PRIO_SYNC_FULL = 0,\n\tMIN_COMPACT_PRIORITY = 0,\n\tCOMPACT_PRIO_SYNC_LIGHT = 1,\n\tMIN_COMPACT_COSTLY_PRIORITY = 1,\n\tDEF_COMPACT_PRIORITY = 1,\n\tCOMPACT_PRIO_ASYNC = 2,\n\tINIT_COMPACT_PRIORITY = 2,\n};\n\nenum compact_result {\n\tCOMPACT_NOT_SUITABLE_ZONE = 0,\n\tCOMPACT_SKIPPED = 1,\n\tCOMPACT_DEFERRED = 2,\n\tCOMPACT_INACTIVE = 2,\n\tCOMPACT_NO_SUITABLE_PAGE = 3,\n\tCOMPACT_CONTINUE = 4,\n\tCOMPACT_COMPLETE = 5,\n\tCOMPACT_PARTIAL_SKIPPED = 6,\n\tCOMPACT_CONTENDED = 7,\n\tCOMPACT_SUCCESS = 8,\n};\n\nstruct trace_event_raw_oom_score_adj_update {\n\tstruct trace_entry ent;\n\tpid_t pid;\n\tchar comm[16];\n\tshort int oom_score_adj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_reclaim_retry_zone {\n\tstruct trace_entry ent;\n\tint node;\n\tint zone_idx;\n\tint order;\n\tlong unsigned int reclaimable;\n\tlong unsigned int available;\n\tlong unsigned int min_wmark;\n\tint no_progress_loops;\n\tbool wmark_check;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mark_victim {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wake_reaper {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_start_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_finish_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skip_task_reaping {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_compact_retry {\n\tstruct trace_entry ent;\n\tint order;\n\tint priority;\n\tint result;\n\tint retries;\n\tint max_retries;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_oom_score_adj_update {};\n\nstruct trace_event_data_offsets_reclaim_retry_zone {};\n\nstruct trace_event_data_offsets_mark_victim {};\n\nstruct trace_event_data_offsets_wake_reaper {};\n\nstruct trace_event_data_offsets_start_task_reaping {};\n\nstruct trace_event_data_offsets_finish_task_reaping {};\n\nstruct trace_event_data_offsets_skip_task_reaping {};\n\nstruct trace_event_data_offsets_compact_retry {};\n\ntypedef void (*btf_trace_oom_score_adj_update)(void *, struct task_struct *);\n\ntypedef void (*btf_trace_reclaim_retry_zone)(void *, struct zoneref *, int, long unsigned int, long unsigned int, long unsigned int, int, bool);\n\ntypedef void (*btf_trace_mark_victim)(void *, int);\n\ntypedef void (*btf_trace_wake_reaper)(void *, int);\n\ntypedef void (*btf_trace_start_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_finish_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_skip_task_reaping)(void *, int);\n\ntypedef void (*btf_trace_compact_retry)(void *, int, enum compact_priority, enum compact_result, int, int, bool);\n\nenum wb_congested_state {\n\tWB_async_congested = 0,\n\tWB_sync_congested = 1,\n};\n\nenum {\n\tXA_CHECK_SCHED = 4096,\n};\n\nenum wb_state {\n\tWB_registered = 0,\n\tWB_writeback_running = 1,\n\tWB_has_dirty_io = 2,\n\tWB_start_all = 3,\n};\n\nenum {\n\tBLK_RW_ASYNC = 0,\n\tBLK_RW_SYNC = 1,\n};\n\nstruct wb_lock_cookie {\n\tbool locked;\n\tlong unsigned int flags;\n};\n\ntypedef int (*writepage_t)(struct page *, struct writeback_control *, void *);\n\nstruct dirty_throttle_control {\n\tstruct bdi_writeback *wb;\n\tstruct fprop_local_percpu *wb_completions;\n\tlong unsigned int avail;\n\tlong unsigned int dirty;\n\tlong unsigned int thresh;\n\tlong unsigned int bg_thresh;\n\tlong unsigned int wb_dirty;\n\tlong unsigned int wb_thresh;\n\tlong unsigned int wb_bg_thresh;\n\tlong unsigned int pos_ratio;\n};\n\nstruct trace_event_raw_mm_lru_insertion {\n\tstruct trace_entry ent;\n\tstruct page *page;\n\tlong unsigned int pfn;\n\tint lru;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_lru_activate {\n\tstruct trace_entry ent;\n\tstruct page *page;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_mm_lru_insertion {};\n\nstruct trace_event_data_offsets_mm_lru_activate {};\n\ntypedef void (*btf_trace_mm_lru_insertion)(void *, struct page *, int);\n\ntypedef void (*btf_trace_mm_lru_activate)(void *, struct page *);\n\nstruct lru_rotate {\n\tlocal_lock_t lock;\n\tstruct pagevec pvec;\n};\n\nstruct lru_pvecs {\n\tlocal_lock_t lock;\n\tstruct pagevec lru_add;\n\tstruct pagevec lru_deactivate_file;\n\tstruct pagevec lru_deactivate;\n\tstruct pagevec lru_lazyfree;\n\tstruct pagevec activate_page;\n};\n\nenum lruvec_flags {\n\tLRUVEC_CONGESTED = 0,\n};\n\nenum pgdat_flags {\n\tPGDAT_DIRTY = 0,\n\tPGDAT_WRITEBACK = 1,\n\tPGDAT_RECLAIM_LOCKED = 2,\n};\n\nstruct reclaim_stat {\n\tunsigned int nr_dirty;\n\tunsigned int nr_unqueued_dirty;\n\tunsigned int nr_congested;\n\tunsigned int nr_writeback;\n\tunsigned int nr_immediate;\n\tunsigned int nr_pageout;\n\tunsigned int nr_activate[2];\n\tunsigned int nr_ref_keep;\n\tunsigned int nr_unmap_fail;\n\tunsigned int nr_lazyfree_fail;\n};\n\nenum mem_cgroup_protection {\n\tMEMCG_PROT_NONE = 0,\n\tMEMCG_PROT_LOW = 1,\n\tMEMCG_PROT_MIN = 2,\n};\n\nstruct mem_cgroup_reclaim_cookie {\n\tpg_data_t *pgdat;\n\tunsigned int generation;\n};\n\nenum ttu_flags {\n\tTTU_MIGRATION = 1,\n\tTTU_MUNLOCK = 2,\n\tTTU_SPLIT_HUGE_PMD = 4,\n\tTTU_IGNORE_MLOCK = 8,\n\tTTU_IGNORE_ACCESS = 16,\n\tTTU_IGNORE_HWPOISON = 32,\n\tTTU_BATCH_FLUSH = 64,\n\tTTU_RMAP_LOCKED = 128,\n\tTTU_SPLIT_FREEZE = 256,\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_kswapd_wake {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_wakeup_kswapd {\n\tstruct trace_entry ent;\n\tint nid;\n\tint zid;\n\tint order;\n\tgfp_t gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_begin_template {\n\tstruct trace_entry ent;\n\tint order;\n\tgfp_t gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_direct_reclaim_end_template {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_reclaimed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_start {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tvoid *shrink;\n\tint nid;\n\tlong int nr_objects_to_shrink;\n\tgfp_t gfp_flags;\n\tlong unsigned int cache_items;\n\tlong long unsigned int delta;\n\tlong unsigned int total_scan;\n\tint priority;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_shrink_slab_end {\n\tstruct trace_entry ent;\n\tstruct shrinker *shr;\n\tint nid;\n\tvoid *shrink;\n\tlong int unused_scan;\n\tlong int new_scan;\n\tint retval;\n\tlong int total_scan;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_isolate {\n\tstruct trace_entry ent;\n\tint highest_zoneidx;\n\tint order;\n\tlong unsigned int nr_requested;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_skipped;\n\tlong unsigned int nr_taken;\n\tisolate_mode_t isolate_mode;\n\tint lru;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_writepage {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_inactive {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int nr_congested;\n\tlong unsigned int nr_immediate;\n\tunsigned int nr_activate0;\n\tunsigned int nr_activate1;\n\tlong unsigned int nr_ref_keep;\n\tlong unsigned int nr_unmap_fail;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_lru_shrink_active {\n\tstruct trace_entry ent;\n\tint nid;\n\tlong unsigned int nr_taken;\n\tlong unsigned int nr_active;\n\tlong unsigned int nr_deactivated;\n\tlong unsigned int nr_referenced;\n\tint priority;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_inactive_list_is_low {\n\tstruct trace_entry ent;\n\tint nid;\n\tint reclaim_idx;\n\tlong unsigned int total_inactive;\n\tlong unsigned int inactive;\n\tlong unsigned int total_active;\n\tlong unsigned int active;\n\tlong unsigned int ratio;\n\tint reclaim_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_vmscan_node_reclaim_begin {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tgfp_t gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_sleep {};\n\nstruct trace_event_data_offsets_mm_vmscan_kswapd_wake {};\n\nstruct trace_event_data_offsets_mm_vmscan_wakeup_kswapd {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_begin_template {};\n\nstruct trace_event_data_offsets_mm_vmscan_direct_reclaim_end_template {};\n\nstruct trace_event_data_offsets_mm_shrink_slab_start {};\n\nstruct trace_event_data_offsets_mm_shrink_slab_end {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_isolate {};\n\nstruct trace_event_data_offsets_mm_vmscan_writepage {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_inactive {};\n\nstruct trace_event_data_offsets_mm_vmscan_lru_shrink_active {};\n\nstruct trace_event_data_offsets_mm_vmscan_inactive_list_is_low {};\n\nstruct trace_event_data_offsets_mm_vmscan_node_reclaim_begin {};\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_vmscan_kswapd_wake)(void *, int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_wakeup_kswapd)(void *, int, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_begin)(void *, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_direct_reclaim_end)(void *, long unsigned int);\n\ntypedef void (*btf_trace_mm_shrink_slab_start)(void *, struct shrinker *, struct shrink_control *, long int, long unsigned int, long long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_shrink_slab_end)(void *, struct shrinker *, int, int, long int, long int, long int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_isolate)(void *, int, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, isolate_mode_t, int);\n\ntypedef void (*btf_trace_mm_vmscan_writepage)(void *, struct page *);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_inactive)(void *, int, long unsigned int, long unsigned int, struct reclaim_stat *, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_lru_shrink_active)(void *, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int, int);\n\ntypedef void (*btf_trace_mm_vmscan_inactive_list_is_low)(void *, int, int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, int);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_begin)(void *, int, int, gfp_t);\n\ntypedef void (*btf_trace_mm_vmscan_node_reclaim_end)(void *, long unsigned int);\n\nstruct scan_control {\n\tlong unsigned int nr_to_reclaim;\n\tnodemask_t *nodemask;\n\tstruct mem_cgroup *target_mem_cgroup;\n\tlong unsigned int anon_cost;\n\tlong unsigned int file_cost;\n\tunsigned int may_deactivate: 2;\n\tunsigned int force_deactivate: 1;\n\tunsigned int skipped_deactivate: 1;\n\tunsigned int may_writepage: 1;\n\tunsigned int may_unmap: 1;\n\tunsigned int may_swap: 1;\n\tunsigned int memcg_low_reclaim: 1;\n\tunsigned int memcg_low_skipped: 1;\n\tunsigned int hibernation_mode: 1;\n\tunsigned int compaction_ready: 1;\n\tunsigned int cache_trim_mode: 1;\n\tunsigned int file_is_tiny: 1;\n\ts8 order;\n\ts8 priority;\n\ts8 reclaim_idx;\n\tgfp_t gfp_mask;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_reclaimed;\n\tstruct {\n\t\tunsigned int dirty;\n\t\tunsigned int unqueued_dirty;\n\t\tunsigned int congested;\n\t\tunsigned int writeback;\n\t\tunsigned int immediate;\n\t\tunsigned int file_taken;\n\t\tunsigned int taken;\n\t} nr;\n\tstruct reclaim_state reclaim_state;\n};\n\ntypedef enum {\n\tPAGE_KEEP = 0,\n\tPAGE_ACTIVATE = 1,\n\tPAGE_SUCCESS = 2,\n\tPAGE_CLEAN = 3,\n} pageout_t;\n\nenum page_references {\n\tPAGEREF_RECLAIM = 0,\n\tPAGEREF_RECLAIM_CLEAN = 1,\n\tPAGEREF_KEEP = 2,\n\tPAGEREF_ACTIVATE = 3,\n};\n\nenum scan_balance {\n\tSCAN_EQUAL = 0,\n\tSCAN_FRACT = 1,\n\tSCAN_ANON = 2,\n\tSCAN_FILE = 3,\n};\n\nstruct xattr {\n\tconst char *name;\n\tvoid *value;\n\tsize_t value_len;\n};\n\nstruct constant_table {\n\tconst char *name;\n\tint value;\n};\n\nenum {\n\tMPOL_DEFAULT = 0,\n\tMPOL_PREFERRED = 1,\n\tMPOL_BIND = 2,\n\tMPOL_INTERLEAVE = 3,\n\tMPOL_LOCAL = 4,\n\tMPOL_MAX = 5,\n};\n\nstruct shared_policy {\n\tstruct rb_root root;\n\trwlock_t lock;\n};\n\nstruct simple_xattrs {\n\tstruct list_head head;\n\tspinlock_t lock;\n};\n\nstruct simple_xattr {\n\tstruct list_head list;\n\tchar *name;\n\tsize_t size;\n\tchar value[0];\n};\n\nenum fid_type {\n\tFILEID_ROOT = 0,\n\tFILEID_INO32_GEN = 1,\n\tFILEID_INO32_GEN_PARENT = 2,\n\tFILEID_BTRFS_WITHOUT_PARENT = 77,\n\tFILEID_BTRFS_WITH_PARENT = 78,\n\tFILEID_BTRFS_WITH_PARENT_ROOT = 79,\n\tFILEID_UDF_WITHOUT_PARENT = 81,\n\tFILEID_UDF_WITH_PARENT = 82,\n\tFILEID_NILFS_WITHOUT_PARENT = 97,\n\tFILEID_NILFS_WITH_PARENT = 98,\n\tFILEID_FAT_WITHOUT_PARENT = 113,\n\tFILEID_FAT_WITH_PARENT = 114,\n\tFILEID_LUSTRE = 151,\n\tFILEID_KERNFS = 254,\n\tFILEID_INVALID = 255,\n};\n\nstruct shmem_inode_info {\n\tspinlock_t lock;\n\tunsigned int seals;\n\tlong unsigned int flags;\n\tlong unsigned int alloced;\n\tlong unsigned int swapped;\n\tstruct list_head shrinklist;\n\tstruct list_head swaplist;\n\tstruct shared_policy policy;\n\tstruct simple_xattrs xattrs;\n\tatomic_t stop_eviction;\n\tstruct inode vfs_inode;\n};\n\nstruct shmem_sb_info {\n\tlong unsigned int max_blocks;\n\tstruct percpu_counter used_blocks;\n\tlong unsigned int max_inodes;\n\tlong unsigned int free_inodes;\n\tspinlock_t stat_lock;\n\tumode_t mode;\n\tunsigned char huge;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct mempolicy *mpol;\n\tspinlock_t shrinklist_lock;\n\tstruct list_head shrinklist;\n\tlong unsigned int shrinklist_len;\n};\n\nenum sgp_type {\n\tSGP_READ = 0,\n\tSGP_CACHE = 1,\n\tSGP_NOHUGE = 2,\n\tSGP_HUGE = 3,\n\tSGP_WRITE = 4,\n\tSGP_FALLOC = 5,\n};\n\nstruct shmem_falloc {\n\twait_queue_head_t *waitq;\n\tlong unsigned int start;\n\tlong unsigned int next;\n\tlong unsigned int nr_falloced;\n\tlong unsigned int nr_unswapped;\n};\n\nstruct shmem_options {\n\tlong long unsigned int blocks;\n\tlong long unsigned int inodes;\n\tstruct mempolicy *mpol;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tint huge;\n\tint seen;\n};\n\nenum shmem_param {\n\tOpt_gid = 0,\n\tOpt_huge = 1,\n\tOpt_mode = 2,\n\tOpt_mpol = 3,\n\tOpt_nr_blocks = 4,\n\tOpt_nr_inodes = 5,\n\tOpt_size = 6,\n\tOpt_uid = 7,\n};\n\nenum pageblock_bits {\n\tPB_migrate = 0,\n\tPB_migrate_end = 2,\n\tPB_migrate_skip = 3,\n\tNR_PAGEBLOCK_BITS = 4,\n};\n\nenum writeback_stat_item {\n\tNR_DIRTY_THRESHOLD = 0,\n\tNR_DIRTY_BG_THRESHOLD = 1,\n\tNR_VM_WRITEBACK_STAT_ITEMS = 2,\n};\n\nstruct contig_page_info {\n\tlong unsigned int free_pages;\n\tlong unsigned int free_blocks_total;\n\tlong unsigned int free_blocks_suitable;\n};\n\ntypedef s8 pto_T_____21;\n\nenum mminit_level {\n\tMMINIT_WARNING = 0,\n\tMMINIT_VERIFY = 1,\n\tMMINIT_TRACE = 2,\n};\n\nstruct pcpu_group_info {\n\tint nr_units;\n\tlong unsigned int base_offset;\n\tunsigned int *cpu_map;\n};\n\nstruct pcpu_alloc_info {\n\tsize_t static_size;\n\tsize_t reserved_size;\n\tsize_t dyn_size;\n\tsize_t unit_size;\n\tsize_t atom_size;\n\tsize_t alloc_size;\n\tsize_t __ai_size;\n\tint nr_groups;\n\tstruct pcpu_group_info groups[0];\n};\n\ntypedef void * (*pcpu_fc_alloc_fn_t)(unsigned int, size_t, size_t);\n\ntypedef void (*pcpu_fc_free_fn_t)(void *, size_t);\n\ntypedef void (*pcpu_fc_populate_pte_fn_t)(long unsigned int);\n\ntypedef int pcpu_fc_cpu_distance_fn_t(unsigned int, unsigned int);\n\nstruct trace_event_raw_percpu_alloc_percpu {\n\tstruct trace_entry ent;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_free_percpu {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tint off;\n\tvoid *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_alloc_percpu_fail {\n\tstruct trace_entry ent;\n\tbool reserved;\n\tbool is_atomic;\n\tsize_t size;\n\tsize_t align;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_create_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_percpu_destroy_chunk {\n\tstruct trace_entry ent;\n\tvoid *base_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu {};\n\nstruct trace_event_data_offsets_percpu_free_percpu {};\n\nstruct trace_event_data_offsets_percpu_alloc_percpu_fail {};\n\nstruct trace_event_data_offsets_percpu_create_chunk {};\n\nstruct trace_event_data_offsets_percpu_destroy_chunk {};\n\ntypedef void (*btf_trace_percpu_alloc_percpu)(void *, bool, bool, size_t, size_t, void *, int, void *);\n\ntypedef void (*btf_trace_percpu_free_percpu)(void *, void *, int, void *);\n\ntypedef void (*btf_trace_percpu_alloc_percpu_fail)(void *, bool, bool, size_t, size_t);\n\ntypedef void (*btf_trace_percpu_create_chunk)(void *, void *);\n\ntypedef void (*btf_trace_percpu_destroy_chunk)(void *, void *);\n\nstruct pcpu_block_md {\n\tint scan_hint;\n\tint scan_hint_start;\n\tint contig_hint;\n\tint contig_hint_start;\n\tint left_free;\n\tint right_free;\n\tint first_free;\n\tint nr_bits;\n};\n\nstruct pcpu_chunk {\n\tstruct list_head list;\n\tint free_bytes;\n\tstruct pcpu_block_md chunk_md;\n\tvoid *base_addr;\n\tlong unsigned int *alloc_map;\n\tlong unsigned int *bound_map;\n\tstruct pcpu_block_md *md_blocks;\n\tvoid *data;\n\tbool immutable;\n\tint start_offset;\n\tint end_offset;\n\tint nr_pages;\n\tint nr_populated;\n\tint nr_empty_pop_pages;\n\tlong unsigned int populated[0];\n};\n\nstruct trace_event_raw_kmem_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tgfp_t gfp_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_alloc_node {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tsize_t bytes_req;\n\tsize_t bytes_alloc;\n\tgfp_t gfp_flags;\n\tint node;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kmem_free {\n\tstruct trace_entry ent;\n\tlong unsigned int call_site;\n\tconst void *ptr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_free_batched {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tgfp_t gfp_flags;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_pcpu_drain {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tunsigned int order;\n\tint migratetype;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_page_alloc_extfrag {\n\tstruct trace_entry ent;\n\tlong unsigned int pfn;\n\tint alloc_order;\n\tint fallback_order;\n\tint alloc_migratetype;\n\tint fallback_migratetype;\n\tint change_ownership;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rss_stat {\n\tstruct trace_entry ent;\n\tunsigned int mm_id;\n\tunsigned int curr;\n\tint member;\n\tlong int size;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_kmem_alloc {};\n\nstruct trace_event_data_offsets_kmem_alloc_node {};\n\nstruct trace_event_data_offsets_kmem_free {};\n\nstruct trace_event_data_offsets_mm_page_free {};\n\nstruct trace_event_data_offsets_mm_page_free_batched {};\n\nstruct trace_event_data_offsets_mm_page_alloc {};\n\nstruct trace_event_data_offsets_mm_page {};\n\nstruct trace_event_data_offsets_mm_page_pcpu_drain {};\n\nstruct trace_event_data_offsets_mm_page_alloc_extfrag {};\n\nstruct trace_event_data_offsets_rss_stat {};\n\ntypedef void (*btf_trace_kmalloc)(void *, long unsigned int, const void *, size_t, size_t, gfp_t);\n\ntypedef void (*btf_trace_kmem_cache_alloc)(void *, long unsigned int, const void *, size_t, size_t, gfp_t);\n\ntypedef void (*btf_trace_kmalloc_node)(void *, long unsigned int, const void *, size_t, size_t, gfp_t, int);\n\ntypedef void (*btf_trace_kmem_cache_alloc_node)(void *, long unsigned int, const void *, size_t, size_t, gfp_t, int);\n\ntypedef void (*btf_trace_kfree)(void *, long unsigned int, const void *);\n\ntypedef void (*btf_trace_kmem_cache_free)(void *, long unsigned int, const void *);\n\ntypedef void (*btf_trace_mm_page_free)(void *, struct page *, unsigned int);\n\ntypedef void (*btf_trace_mm_page_free_batched)(void *, struct page *);\n\ntypedef void (*btf_trace_mm_page_alloc)(void *, struct page *, unsigned int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_page_alloc_zone_locked)(void *, struct page *, unsigned int, int);\n\ntypedef void (*btf_trace_mm_page_pcpu_drain)(void *, struct page *, unsigned int, int);\n\ntypedef void (*btf_trace_mm_page_alloc_extfrag)(void *, struct page *, int, int, int, int);\n\ntypedef void (*btf_trace_rss_stat)(void *, struct mm_struct *, int, long int);\n\nstruct slabinfo {\n\tlong unsigned int active_objs;\n\tlong unsigned int num_objs;\n\tlong unsigned int active_slabs;\n\tlong unsigned int num_slabs;\n\tlong unsigned int shared_avail;\n\tunsigned int limit;\n\tunsigned int batchcount;\n\tunsigned int shared;\n\tunsigned int objects_per_slab;\n\tunsigned int cache_order;\n};\n\nstruct alloc_context {\n\tstruct zonelist *zonelist;\n\tnodemask_t *nodemask;\n\tstruct zoneref *preferred_zoneref;\n\tint migratetype;\n\tenum zone_type highest_zoneidx;\n\tbool spread_dirty_pages;\n};\n\nstruct trace_event_raw_mm_compaction_isolate_template {\n\tstruct trace_entry ent;\n\tlong unsigned int start_pfn;\n\tlong unsigned int end_pfn;\n\tlong unsigned int nr_scanned;\n\tlong unsigned int nr_taken;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_migratepages {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_migrated;\n\tlong unsigned int nr_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_begin {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_end {\n\tstruct trace_entry ent;\n\tlong unsigned int zone_start;\n\tlong unsigned int migrate_pfn;\n\tlong unsigned int free_pfn;\n\tlong unsigned int zone_end;\n\tbool sync;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_try_to_compact_pages {\n\tstruct trace_entry ent;\n\tint order;\n\tgfp_t gfp_mask;\n\tint prio;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_suitable_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_defer_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tenum zone_type idx;\n\tint order;\n\tunsigned int considered;\n\tunsigned int defer_shift;\n\tint order_failed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mm_compaction_kcompactd_sleep {\n\tstruct trace_entry ent;\n\tint nid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kcompactd_wake_template {\n\tstruct trace_entry ent;\n\tint nid;\n\tint order;\n\tenum zone_type highest_zoneidx;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_mm_compaction_isolate_template {};\n\nstruct trace_event_data_offsets_mm_compaction_migratepages {};\n\nstruct trace_event_data_offsets_mm_compaction_begin {};\n\nstruct trace_event_data_offsets_mm_compaction_end {};\n\nstruct trace_event_data_offsets_mm_compaction_try_to_compact_pages {};\n\nstruct trace_event_data_offsets_mm_compaction_suitable_template {};\n\nstruct trace_event_data_offsets_mm_compaction_defer_template {};\n\nstruct trace_event_data_offsets_mm_compaction_kcompactd_sleep {};\n\nstruct trace_event_data_offsets_kcompactd_wake_template {};\n\ntypedef void (*btf_trace_mm_compaction_isolate_migratepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_isolate_freepages)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_mm_compaction_migratepages)(void *, long unsigned int, int, struct list_head *);\n\ntypedef void (*btf_trace_mm_compaction_begin)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, bool);\n\ntypedef void (*btf_trace_mm_compaction_end)(void *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, bool, int);\n\ntypedef void (*btf_trace_mm_compaction_try_to_compact_pages)(void *, int, gfp_t, int);\n\ntypedef void (*btf_trace_mm_compaction_finished)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_suitable)(void *, struct zone *, int, int);\n\ntypedef void (*btf_trace_mm_compaction_deferred)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_defer_compaction)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_defer_reset)(void *, struct zone *, int);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_sleep)(void *, int);\n\ntypedef void (*btf_trace_mm_compaction_wakeup_kcompactd)(void *, int, int, enum zone_type);\n\ntypedef void (*btf_trace_mm_compaction_kcompactd_wake)(void *, int, int, enum zone_type);\n\ntypedef enum {\n\tISOLATE_ABORT = 0,\n\tISOLATE_NONE = 1,\n\tISOLATE_SUCCESS = 2,\n} isolate_migrate_t;\n\nstruct anon_vma_chain {\n\tstruct vm_area_struct *vma;\n\tstruct anon_vma *anon_vma;\n\tstruct list_head same_vma;\n\tstruct rb_node rb;\n\tlong unsigned int rb_subtree_last;\n};\n\nenum lru_status {\n\tLRU_REMOVED = 0,\n\tLRU_REMOVED_RETRY = 1,\n\tLRU_ROTATE = 2,\n\tLRU_SKIP = 3,\n\tLRU_RETRY = 4,\n};\n\ntypedef enum lru_status (*list_lru_walk_cb)(struct list_head *, struct list_lru_one *, spinlock_t *, void *);\n\ntypedef struct {\n\tlong unsigned int pd;\n} hugepd_t;\n\nstruct follow_page_context {\n\tstruct dev_pagemap *pgmap;\n\tunsigned int page_mask;\n};\n\nstruct zap_details {\n\tstruct address_space *check_mapping;\n\tlong unsigned int first_index;\n\tlong unsigned int last_index;\n};\n\ntypedef int (*pte_fn_t)(pte_t *, long unsigned int, void *);\n\nenum {\n\tSWP_USED = 1,\n\tSWP_WRITEOK = 2,\n\tSWP_DISCARDABLE = 4,\n\tSWP_DISCARDING = 8,\n\tSWP_SOLIDSTATE = 16,\n\tSWP_CONTINUED = 32,\n\tSWP_BLKDEV = 64,\n\tSWP_ACTIVATED = 128,\n\tSWP_FS = 256,\n\tSWP_AREA_DISCARD = 512,\n\tSWP_PAGE_DISCARD = 1024,\n\tSWP_STABLE_WRITES = 2048,\n\tSWP_SYNCHRONOUS_IO = 4096,\n\tSWP_VALID = 8192,\n\tSWP_SCANNING = 16384,\n};\n\nstruct copy_subpage_arg {\n\tstruct page *dst;\n\tstruct page *src;\n\tstruct vm_area_struct *vma;\n};\n\nstruct mm_walk;\n\nstruct mm_walk_ops {\n\tint (*pgd_entry)(pgd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*p4d_entry)(p4d_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pud_entry)(pud_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pmd_entry)(pmd_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_entry)(pte_t *, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pte_hole)(long unsigned int, long unsigned int, int, struct mm_walk *);\n\tint (*hugetlb_entry)(pte_t *, long unsigned int, long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*test_walk)(long unsigned int, long unsigned int, struct mm_walk *);\n\tint (*pre_vma)(long unsigned int, long unsigned int, struct mm_walk *);\n\tvoid (*post_vma)(struct mm_walk *);\n};\n\nenum page_walk_action {\n\tACTION_SUBTREE = 0,\n\tACTION_CONTINUE = 1,\n\tACTION_AGAIN = 2,\n};\n\nstruct mm_walk {\n\tconst struct mm_walk_ops *ops;\n\tstruct mm_struct *mm;\n\tpgd_t *pgd;\n\tstruct vm_area_struct *vma;\n\tenum page_walk_action action;\n\tbool no_vma;\n\tvoid *private;\n};\n\nenum {\n\tHUGETLB_SHMFS_INODE = 1,\n\tHUGETLB_ANONHUGE_INODE = 2,\n};\n\nstruct trace_event_raw_vm_unmapped_area {\n\tstruct trace_entry ent;\n\tlong unsigned int addr;\n\tlong unsigned int total_vm;\n\tlong unsigned int flags;\n\tlong unsigned int length;\n\tlong unsigned int low_limit;\n\tlong unsigned int high_limit;\n\tlong unsigned int align_mask;\n\tlong unsigned int align_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_vm_unmapped_area {};\n\ntypedef void (*btf_trace_vm_unmapped_area)(void *, long unsigned int, struct vm_unmapped_area_info *);\n\nstruct rmap_walk_control {\n\tvoid *arg;\n\tbool (*rmap_one)(struct page *, struct vm_area_struct *, long unsigned int, void *);\n\tint (*done)(struct page *);\n\tstruct anon_vma * (*anon_lock)(struct page *);\n\tbool (*invalid_vma)(struct vm_area_struct *, void *);\n};\n\nstruct page_referenced_arg {\n\tint mapcount;\n\tint referenced;\n\tlong unsigned int vm_flags;\n\tstruct mem_cgroup *memcg;\n};\n\nstruct vmap_area {\n\tlong unsigned int va_start;\n\tlong unsigned int va_end;\n\tstruct rb_node rb_node;\n\tstruct list_head list;\n\tunion {\n\t\tlong unsigned int subtree_max_size;\n\t\tstruct vm_struct *vm;\n\t\tstruct llist_node purge_list;\n\t};\n};\n\ntypedef unsigned int pgtbl_mod_mask;\n\nstruct vfree_deferred {\n\tstruct llist_head list;\n\tstruct work_struct wq;\n};\n\nenum fit_type {\n\tNOTHING_FIT = 0,\n\tFL_FIT_TYPE = 1,\n\tLE_FIT_TYPE = 2,\n\tRE_FIT_TYPE = 3,\n\tNE_FIT_TYPE = 4,\n};\n\nstruct vmap_block_queue {\n\tspinlock_t lock;\n\tstruct list_head free;\n};\n\nstruct vmap_block {\n\tspinlock_t lock;\n\tstruct vmap_area *va;\n\tlong unsigned int free;\n\tlong unsigned int dirty;\n\tlong unsigned int dirty_min;\n\tlong unsigned int dirty_max;\n\tstruct list_head free_list;\n\tstruct callback_head callback_head;\n\tstruct list_head purge;\n};\n\ntypedef struct vmap_area *pto_T_____22;\n\nstruct page_frag_cache {\n\tvoid *va;\n\t__u16 offset;\n\t__u16 size;\n\tunsigned int pagecnt_bias;\n\tbool pfmemalloc;\n};\n\nenum zone_flags {\n\tZONE_BOOSTED_WATERMARK = 0,\n};\n\nenum memmap_context {\n\tMEMMAP_EARLY = 0,\n\tMEMMAP_HOTPLUG = 1,\n};\n\nstruct mminit_pfnnid_cache {\n\tlong unsigned int last_start;\n\tlong unsigned int last_end;\n\tint last_nid;\n};\n\nstruct pcpu_drain {\n\tstruct zone *zone;\n\tstruct work_struct work;\n};\n\nstruct madvise_walk_private {\n\tstruct mmu_gather *tlb;\n\tbool pageout;\n};\n\nstruct vma_swap_readahead {\n\tshort unsigned int win;\n\tshort unsigned int offset;\n\tshort unsigned int nr_pte;\n\tpte_t *ptes;\n};\n\nunion swap_header {\n\tstruct {\n\t\tchar reserved[4086];\n\t\tchar magic[10];\n\t} magic;\n\tstruct {\n\t\tchar bootbits[1024];\n\t\t__u32 version;\n\t\t__u32 last_page;\n\t\t__u32 nr_badpages;\n\t\tunsigned char sws_uuid[16];\n\t\tunsigned char sws_volume[16];\n\t\t__u32 padding[117];\n\t\t__u32 badpages[1];\n\t} info;\n};\n\nstruct swap_extent {\n\tstruct rb_node rb_node;\n\tlong unsigned int start_page;\n\tlong unsigned int nr_pages;\n\tsector_t start_block;\n};\n\nstruct swap_slots_cache {\n\tbool lock_initialized;\n\tstruct mutex alloc_lock;\n\tswp_entry_t *slots;\n\tint nr;\n\tint cur;\n\tspinlock_t free_lock;\n\tswp_entry_t *slots_ret;\n\tint n_ret;\n};\n\nstruct dma_pool {\n\tstruct list_head page_list;\n\tspinlock_t lock;\n\tsize_t size;\n\tstruct device *dev;\n\tsize_t allocation;\n\tsize_t boundary;\n\tchar name[32];\n\tstruct list_head pools;\n};\n\nstruct dma_page {\n\tstruct list_head page_list;\n\tvoid *vaddr;\n\tdma_addr_t dma;\n\tunsigned int in_use;\n\tunsigned int offset;\n};\n\nenum string_size_units {\n\tSTRING_UNITS_10 = 0,\n\tSTRING_UNITS_2 = 1,\n};\n\nstruct resv_map {\n\tstruct kref refs;\n\tspinlock_t lock;\n\tstruct list_head regions;\n\tlong int adds_in_progress;\n\tstruct list_head region_cache;\n\tlong int region_cache_count;\n};\n\nstruct file_region {\n\tstruct list_head link;\n\tlong int from;\n\tlong int to;\n};\n\nstruct huge_bootmem_page {\n\tstruct list_head list;\n\tstruct hstate *hstate;\n};\n\nenum vma_resv_mode {\n\tVMA_NEEDS_RESV = 0,\n\tVMA_COMMIT_RESV = 1,\n\tVMA_END_RESV = 2,\n\tVMA_ADD_RESV = 3,\n};\n\nstruct node_hstate {\n\tstruct kobject *hugepages_kobj;\n\tstruct kobject *hstate_kobjs[2];\n};\n\nstruct hugetlb_cgroup;\n\nstruct nodemask_scratch {\n\tnodemask_t mask1;\n\tnodemask_t mask2;\n};\n\nstruct sp_node {\n\tstruct rb_node nd;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct mempolicy *policy;\n};\n\nstruct mempolicy_operations {\n\tint (*create)(struct mempolicy *, const nodemask_t *);\n\tvoid (*rebind)(struct mempolicy *, const nodemask_t *);\n};\n\nstruct queue_pages {\n\tstruct list_head *pagelist;\n\tlong unsigned int flags;\n\tnodemask_t *nmask;\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tstruct vm_area_struct *first;\n};\n\nstruct mmu_notifier_subscriptions {\n\tstruct hlist_head list;\n\tbool has_itree;\n\tspinlock_t lock;\n\tlong unsigned int invalidate_seq;\n\tlong unsigned int active_invalidate_ranges;\n\tstruct rb_root_cached itree;\n\twait_queue_head_t wq;\n\tstruct hlist_head deferred_list;\n};\n\nstruct interval_tree_node {\n\tstruct rb_node rb;\n\tlong unsigned int start;\n\tlong unsigned int last;\n\tlong unsigned int __subtree_last;\n};\n\nstruct mmu_notifier;\n\nstruct mmu_notifier_ops {\n\tvoid (*release)(struct mmu_notifier *, struct mm_struct *);\n\tint (*clear_flush_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tint (*clear_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tint (*test_young)(struct mmu_notifier *, struct mm_struct *, long unsigned int);\n\tvoid (*change_pte)(struct mmu_notifier *, struct mm_struct *, long unsigned int, pte_t);\n\tint (*invalidate_range_start)(struct mmu_notifier *, const struct mmu_notifier_range *);\n\tvoid (*invalidate_range_end)(struct mmu_notifier *, const struct mmu_notifier_range *);\n\tvoid (*invalidate_range)(struct mmu_notifier *, struct mm_struct *, long unsigned int, long unsigned int);\n\tstruct mmu_notifier * (*alloc_notifier)(struct mm_struct *);\n\tvoid (*free_notifier)(struct mmu_notifier *);\n};\n\nstruct mmu_notifier {\n\tstruct hlist_node hlist;\n\tconst struct mmu_notifier_ops *ops;\n\tstruct mm_struct *mm;\n\tstruct callback_head rcu;\n\tunsigned int users;\n};\n\nstruct mmu_interval_notifier;\n\nstruct mmu_interval_notifier_ops {\n\tbool (*invalidate)(struct mmu_interval_notifier *, const struct mmu_notifier_range *, long unsigned int);\n};\n\nstruct mmu_interval_notifier {\n\tstruct interval_tree_node interval_tree;\n\tconst struct mmu_interval_notifier_ops *ops;\n\tstruct mm_struct *mm;\n\tstruct hlist_node deferred_item;\n\tlong unsigned int invalidate_seq;\n};\n\nenum stat_item {\n\tALLOC_FASTPATH = 0,\n\tALLOC_SLOWPATH = 1,\n\tFREE_FASTPATH = 2,\n\tFREE_SLOWPATH = 3,\n\tFREE_FROZEN = 4,\n\tFREE_ADD_PARTIAL = 5,\n\tFREE_REMOVE_PARTIAL = 6,\n\tALLOC_FROM_PARTIAL = 7,\n\tALLOC_SLAB = 8,\n\tALLOC_REFILL = 9,\n\tALLOC_NODE_MISMATCH = 10,\n\tFREE_SLAB = 11,\n\tCPUSLAB_FLUSH = 12,\n\tDEACTIVATE_FULL = 13,\n\tDEACTIVATE_EMPTY = 14,\n\tDEACTIVATE_TO_HEAD = 15,\n\tDEACTIVATE_TO_TAIL = 16,\n\tDEACTIVATE_REMOTE_FREES = 17,\n\tDEACTIVATE_BYPASS = 18,\n\tORDER_FALLBACK = 19,\n\tCMPXCHG_DOUBLE_CPU_FAIL = 20,\n\tCMPXCHG_DOUBLE_FAIL = 21,\n\tCPU_PARTIAL_ALLOC = 22,\n\tCPU_PARTIAL_FREE = 23,\n\tCPU_PARTIAL_NODE = 24,\n\tCPU_PARTIAL_DRAIN = 25,\n\tNR_SLUB_STAT_ITEMS = 26,\n};\n\nstruct track {\n\tlong unsigned int addr;\n\tlong unsigned int addrs[16];\n\tint cpu;\n\tint pid;\n\tlong unsigned int when;\n};\n\nenum track_item {\n\tTRACK_ALLOC = 0,\n\tTRACK_FREE = 1,\n};\n\nstruct detached_freelist {\n\tstruct page *page;\n\tvoid *tail;\n\tvoid *freelist;\n\tint cnt;\n\tstruct kmem_cache *s;\n};\n\nstruct location {\n\tlong unsigned int count;\n\tlong unsigned int addr;\n\tlong long int sum_time;\n\tlong int min_time;\n\tlong int max_time;\n\tlong int min_pid;\n\tlong int max_pid;\n\tlong unsigned int cpus[1];\n\tnodemask_t nodes;\n};\n\nstruct loc_track {\n\tlong unsigned int max;\n\tlong unsigned int count;\n\tstruct location *loc;\n};\n\nenum slab_stat_type {\n\tSL_ALL = 0,\n\tSL_PARTIAL = 1,\n\tSL_CPU = 2,\n\tSL_OBJECTS = 3,\n\tSL_TOTAL = 4,\n};\n\nstruct slab_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kmem_cache *, char *);\n\tssize_t (*store)(struct kmem_cache *, const char *, size_t);\n};\n\nstruct saved_alias {\n\tstruct kmem_cache *s;\n\tconst char *name;\n\tstruct saved_alias *next;\n};\n\nenum slab_modes {\n\tM_NONE = 0,\n\tM_PARTIAL = 1,\n\tM_FULL = 2,\n\tM_FREE = 3,\n};\n\nstruct buffer_head;\n\ntypedef void bh_end_io_t(struct buffer_head *, int);\n\nstruct buffer_head {\n\tlong unsigned int b_state;\n\tstruct buffer_head *b_this_page;\n\tstruct page *b_page;\n\tsector_t b_blocknr;\n\tsize_t b_size;\n\tchar *b_data;\n\tstruct block_device *b_bdev;\n\tbh_end_io_t *b_end_io;\n\tvoid *b_private;\n\tstruct list_head b_assoc_buffers;\n\tstruct address_space *b_assoc_map;\n\tatomic_t b_count;\n\tspinlock_t b_uptodate_lock;\n};\n\ntypedef struct page *new_page_t(struct page *, long unsigned int);\n\ntypedef void free_page_t(struct page *, long unsigned int);\n\nenum bh_state_bits {\n\tBH_Uptodate = 0,\n\tBH_Dirty = 1,\n\tBH_Lock = 2,\n\tBH_Req = 3,\n\tBH_Mapped = 4,\n\tBH_New = 5,\n\tBH_Async_Read = 6,\n\tBH_Async_Write = 7,\n\tBH_Delay = 8,\n\tBH_Boundary = 9,\n\tBH_Write_EIO = 10,\n\tBH_Unwritten = 11,\n\tBH_Quiet = 12,\n\tBH_Meta = 13,\n\tBH_Prio = 14,\n\tBH_Defer_Completion = 15,\n\tBH_PrivateStart = 16,\n};\n\nstruct trace_event_raw_mm_migrate_pages {\n\tstruct trace_entry ent;\n\tlong unsigned int succeeded;\n\tlong unsigned int failed;\n\tenum migrate_mode mode;\n\tint reason;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_mm_migrate_pages {};\n\ntypedef void (*btf_trace_mm_migrate_pages)(void *, long unsigned int, long unsigned int, enum migrate_mode, int);\n\nstruct hugetlbfs_inode_info {\n\tstruct shared_policy policy;\n\tstruct inode vfs_inode;\n\tunsigned int seals;\n};\n\nstruct open_how {\n\t__u64 flags;\n\t__u64 mode;\n\t__u64 resolve;\n};\n\ntypedef s32 compat_off_t;\n\nstruct fs_context_operations___2;\n\nstruct open_flags {\n\tint open_flag;\n\tumode_t mode;\n\tint acc_mode;\n\tint intent;\n\tint lookup_flags;\n};\n\ntypedef __kernel_long_t __kernel_off_t;\n\ntypedef __kernel_off_t off_t;\n\nstruct file_dedupe_range_info {\n\t__s64 dest_fd;\n\t__u64 dest_offset;\n\t__u64 bytes_deduped;\n\t__s32 status;\n\t__u32 reserved;\n};\n\nstruct file_dedupe_range {\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u16 dest_count;\n\t__u16 reserved1;\n\t__u32 reserved2;\n\tstruct file_dedupe_range_info info[0];\n};\n\ntypedef int __kernel_rwf_t;\n\ntypedef __kernel_rwf_t rwf_t;\n\ntypedef s32 compat_ssize_t;\n\nenum vfs_get_super_keying {\n\tvfs_get_single_super = 0,\n\tvfs_get_single_reconf_super = 1,\n\tvfs_get_keyed_super = 2,\n\tvfs_get_independent_super = 3,\n};\n\nstruct kobj_map;\n\nstruct char_device_struct {\n\tstruct char_device_struct *next;\n\tunsigned int major;\n\tunsigned int baseminor;\n\tint minorct;\n\tchar name[64];\n\tstruct cdev *cdev;\n};\n\nstruct stat {\n\t__kernel_ulong_t st_dev;\n\t__kernel_ulong_t st_ino;\n\t__kernel_ulong_t st_nlink;\n\tunsigned int st_mode;\n\tunsigned int st_uid;\n\tunsigned int st_gid;\n\tunsigned int __pad0;\n\t__kernel_ulong_t st_rdev;\n\t__kernel_long_t st_size;\n\t__kernel_long_t st_blksize;\n\t__kernel_long_t st_blocks;\n\t__kernel_ulong_t st_atime;\n\t__kernel_ulong_t st_atime_nsec;\n\t__kernel_ulong_t st_mtime;\n\t__kernel_ulong_t st_mtime_nsec;\n\t__kernel_ulong_t st_ctime;\n\t__kernel_ulong_t st_ctime_nsec;\n\t__kernel_long_t __unused[3];\n};\n\nstruct __old_kernel_stat {\n\tshort unsigned int st_dev;\n\tshort unsigned int st_ino;\n\tshort unsigned int st_mode;\n\tshort unsigned int st_nlink;\n\tshort unsigned int st_uid;\n\tshort unsigned int st_gid;\n\tshort unsigned int st_rdev;\n\tunsigned int st_size;\n\tunsigned int st_atime;\n\tunsigned int st_mtime;\n\tunsigned int st_ctime;\n};\n\nstruct statx_timestamp {\n\t__s64 tv_sec;\n\t__u32 tv_nsec;\n\t__s32 __reserved;\n};\n\nstruct statx {\n\t__u32 stx_mask;\n\t__u32 stx_blksize;\n\t__u64 stx_attributes;\n\t__u32 stx_nlink;\n\t__u32 stx_uid;\n\t__u32 stx_gid;\n\t__u16 stx_mode;\n\t__u16 __spare0[1];\n\t__u64 stx_ino;\n\t__u64 stx_size;\n\t__u64 stx_blocks;\n\t__u64 stx_attributes_mask;\n\tstruct statx_timestamp stx_atime;\n\tstruct statx_timestamp stx_btime;\n\tstruct statx_timestamp stx_ctime;\n\tstruct statx_timestamp stx_mtime;\n\t__u32 stx_rdev_major;\n\t__u32 stx_rdev_minor;\n\t__u32 stx_dev_major;\n\t__u32 stx_dev_minor;\n\t__u64 stx_mnt_id;\n\t__u64 __spare2;\n\t__u64 __spare3[12];\n};\n\nstruct mount;\n\nstruct mnt_namespace {\n\tatomic_t count;\n\tstruct ns_common ns;\n\tstruct mount *root;\n\tstruct list_head list;\n\tspinlock_t ns_lock;\n\tstruct user_namespace *user_ns;\n\tstruct ucounts *ucounts;\n\tu64 seq;\n\twait_queue_head_t poll;\n\tu64 event;\n\tunsigned int mounts;\n\tunsigned int pending_mounts;\n};\n\ntypedef u32 compat_ino_t;\n\ntypedef u16 __compat_uid_t;\n\ntypedef u16 __compat_gid_t;\n\ntypedef u16 compat_mode_t;\n\ntypedef u16 compat_dev_t;\n\ntypedef u16 compat_nlink_t;\n\nstruct compat_stat {\n\tcompat_dev_t st_dev;\n\tu16 __pad1;\n\tcompat_ino_t st_ino;\n\tcompat_mode_t st_mode;\n\tcompat_nlink_t st_nlink;\n\t__compat_uid_t st_uid;\n\t__compat_gid_t st_gid;\n\tcompat_dev_t st_rdev;\n\tu16 __pad2;\n\tu32 st_size;\n\tu32 st_blksize;\n\tu32 st_blocks;\n\tu32 st_atime;\n\tu32 st_atime_nsec;\n\tu32 st_mtime;\n\tu32 st_mtime_nsec;\n\tu32 st_ctime;\n\tu32 st_ctime_nsec;\n\tu32 __unused4;\n\tu32 __unused5;\n};\n\nstruct mnt_pcp;\n\nstruct mountpoint;\n\nstruct mount {\n\tstruct hlist_node mnt_hash;\n\tstruct mount *mnt_parent;\n\tstruct dentry *mnt_mountpoint;\n\tstruct vfsmount mnt;\n\tunion {\n\t\tstruct callback_head mnt_rcu;\n\t\tstruct llist_node mnt_llist;\n\t};\n\tstruct mnt_pcp *mnt_pcp;\n\tstruct list_head mnt_mounts;\n\tstruct list_head mnt_child;\n\tstruct list_head mnt_instance;\n\tconst char *mnt_devname;\n\tstruct list_head mnt_list;\n\tstruct list_head mnt_expire;\n\tstruct list_head mnt_share;\n\tstruct list_head mnt_slave_list;\n\tstruct list_head mnt_slave;\n\tstruct mount *mnt_master;\n\tstruct mnt_namespace *mnt_ns;\n\tstruct mountpoint *mnt_mp;\n\tunion {\n\t\tstruct hlist_node mnt_mp_list;\n\t\tstruct hlist_node mnt_umount;\n\t};\n\tstruct list_head mnt_umounting;\n\tstruct fsnotify_mark_connector *mnt_fsnotify_marks;\n\t__u32 mnt_fsnotify_mask;\n\tint mnt_id;\n\tint mnt_group_id;\n\tint mnt_expiry_mark;\n\tstruct hlist_head mnt_pins;\n\tstruct hlist_head mnt_stuck_children;\n};\n\nstruct mnt_pcp {\n\tint mnt_count;\n\tint mnt_writers;\n};\n\nstruct mountpoint {\n\tstruct hlist_node m_hash;\n\tstruct dentry *m_dentry;\n\tstruct hlist_head m_list;\n\tint m_count;\n};\n\ntypedef short unsigned int ushort;\n\nstruct user_arg_ptr {\n\tbool is_compat;\n\tunion {\n\t\tconst char * const *native;\n\t\tconst compat_uptr_t *compat;\n\t} ptr;\n};\n\nenum inode_i_mutex_lock_class {\n\tI_MUTEX_NORMAL = 0,\n\tI_MUTEX_PARENT = 1,\n\tI_MUTEX_CHILD = 2,\n\tI_MUTEX_XATTR = 3,\n\tI_MUTEX_NONDIR2 = 4,\n\tI_MUTEX_PARENT2 = 5,\n};\n\nstruct pseudo_fs_context {\n\tconst struct super_operations *ops;\n\tconst struct xattr_handler **xattr;\n\tconst struct dentry_operations *dops;\n\tlong unsigned int magic;\n};\n\nstruct name_snapshot {\n\tstruct qstr name;\n\tunsigned char inline_name[32];\n};\n\nstruct saved {\n\tstruct path link;\n\tstruct delayed_call done;\n\tconst char *name;\n\tunsigned int seq;\n};\n\nstruct nameidata {\n\tstruct path path;\n\tstruct qstr last;\n\tstruct path root;\n\tstruct inode *inode;\n\tunsigned int flags;\n\tunsigned int seq;\n\tunsigned int m_seq;\n\tunsigned int r_seq;\n\tint last_type;\n\tunsigned int depth;\n\tint total_link_count;\n\tstruct saved *stack;\n\tstruct saved internal[2];\n\tstruct filename *name;\n\tstruct nameidata *saved;\n\tunsigned int root_seq;\n\tint dfd;\n\tkuid_t dir_uid;\n\tumode_t dir_mode;\n};\n\nenum {\n\tLAST_NORM = 0,\n\tLAST_ROOT = 1,\n\tLAST_DOT = 2,\n\tLAST_DOTDOT = 3,\n};\n\nenum {\n\tWALK_TRAILING = 1,\n\tWALK_MORE = 2,\n\tWALK_NOFOLLOW = 4,\n};\n\nstruct word_at_a_time {\n\tconst long unsigned int one_bits;\n\tconst long unsigned int high_bits;\n};\n\nstruct f_owner_ex {\n\tint type;\n\t__kernel_pid_t pid;\n};\n\nstruct flock {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_off_t l_start;\n\t__kernel_off_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\nstruct compat_flock {\n\tshort int l_type;\n\tshort int l_whence;\n\tcompat_off_t l_start;\n\tcompat_off_t l_len;\n\tcompat_pid_t l_pid;\n};\n\nstruct compat_flock64 {\n\tshort int l_type;\n\tshort int l_whence;\n\tcompat_loff_t l_start;\n\tcompat_loff_t l_len;\n\tcompat_pid_t l_pid;\n} __attribute__((packed));\n\nstruct file_clone_range {\n\t__s64 src_fd;\n\t__u64 src_offset;\n\t__u64 src_length;\n\t__u64 dest_offset;\n};\n\ntypedef int get_block_t(struct inode *, sector_t, struct buffer_head *, int);\n\nstruct fiemap_extent;\n\nstruct fiemap_extent_info {\n\tunsigned int fi_flags;\n\tunsigned int fi_extents_mapped;\n\tunsigned int fi_extents_max;\n\tstruct fiemap_extent *fi_extents_start;\n};\n\nstruct space_resv {\n\t__s16 l_type;\n\t__s16 l_whence;\n\t__s64 l_start;\n\t__s64 l_len;\n\t__s32 l_sysid;\n\t__u32 l_pid;\n\t__s32 l_pad[4];\n};\n\nstruct space_resv_32 {\n\t__s16 l_type;\n\t__s16 l_whence;\n\t__s64 l_start;\n\t__s64 l_len;\n\t__s32 l_sysid;\n\t__u32 l_pid;\n\t__s32 l_pad[4];\n} __attribute__((packed));\n\nstruct fiemap_extent {\n\t__u64 fe_logical;\n\t__u64 fe_physical;\n\t__u64 fe_length;\n\t__u64 fe_reserved64[2];\n\t__u32 fe_flags;\n\t__u32 fe_reserved[3];\n};\n\nstruct fiemap {\n\t__u64 fm_start;\n\t__u64 fm_length;\n\t__u32 fm_flags;\n\t__u32 fm_mapped_extents;\n\t__u32 fm_extent_count;\n\t__u32 fm_reserved;\n\tstruct fiemap_extent fm_extents[0];\n};\n\nstruct linux_dirent64 {\n\tu64 d_ino;\n\ts64 d_off;\n\tshort unsigned int d_reclen;\n\tunsigned char d_type;\n\tchar d_name[0];\n};\n\nstruct old_linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_offset;\n\tshort unsigned int d_namlen;\n\tchar d_name[1];\n};\n\nstruct readdir_callback {\n\tstruct dir_context ctx;\n\tstruct old_linux_dirent *dirent;\n\tint result;\n};\n\nstruct linux_dirent {\n\tlong unsigned int d_ino;\n\tlong unsigned int d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[1];\n};\n\nstruct getdents_callback {\n\tstruct dir_context ctx;\n\tstruct linux_dirent *current_dir;\n\tint prev_reclen;\n\tint count;\n\tint error;\n};\n\nstruct getdents_callback64 {\n\tstruct dir_context ctx;\n\tstruct linux_dirent64 *current_dir;\n\tint prev_reclen;\n\tint count;\n\tint error;\n};\n\nstruct compat_old_linux_dirent {\n\tcompat_ulong_t d_ino;\n\tcompat_ulong_t d_offset;\n\tshort unsigned int d_namlen;\n\tchar d_name[1];\n};\n\nstruct compat_readdir_callback {\n\tstruct dir_context ctx;\n\tstruct compat_old_linux_dirent *dirent;\n\tint result;\n};\n\nstruct compat_linux_dirent {\n\tcompat_ulong_t d_ino;\n\tcompat_ulong_t d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[1];\n};\n\nstruct compat_getdents_callback {\n\tstruct dir_context ctx;\n\tstruct compat_linux_dirent *current_dir;\n\tint prev_reclen;\n\tint count;\n\tint error;\n};\n\ntypedef struct {\n\tlong unsigned int fds_bits[16];\n} __kernel_fd_set;\n\ntypedef __kernel_fd_set fd_set;\n\nstruct poll_table_entry {\n\tstruct file *filp;\n\t__poll_t key;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *wait_address;\n};\n\nstruct poll_table_page;\n\nstruct poll_wqueues {\n\tpoll_table pt;\n\tstruct poll_table_page *table;\n\tstruct task_struct *polling_task;\n\tint triggered;\n\tint error;\n\tint inline_index;\n\tstruct poll_table_entry inline_entries[9];\n};\n\nstruct poll_table_page {\n\tstruct poll_table_page *next;\n\tstruct poll_table_entry *entry;\n\tstruct poll_table_entry entries[0];\n};\n\nenum poll_time_type {\n\tPT_TIMEVAL = 0,\n\tPT_OLD_TIMEVAL = 1,\n\tPT_TIMESPEC = 2,\n\tPT_OLD_TIMESPEC = 3,\n};\n\ntypedef struct {\n\tlong unsigned int *in;\n\tlong unsigned int *out;\n\tlong unsigned int *ex;\n\tlong unsigned int *res_in;\n\tlong unsigned int *res_out;\n\tlong unsigned int *res_ex;\n} fd_set_bits;\n\nstruct sigset_argpack {\n\tsigset_t *p;\n\tsize_t size;\n};\n\nstruct poll_list {\n\tstruct poll_list *next;\n\tint len;\n\tstruct pollfd entries[0];\n};\n\nstruct compat_sel_arg_struct {\n\tcompat_ulong_t n;\n\tcompat_uptr_t inp;\n\tcompat_uptr_t outp;\n\tcompat_uptr_t exp;\n\tcompat_uptr_t tvp;\n};\n\nstruct compat_sigset_argpack {\n\tcompat_uptr_t p;\n\tcompat_size_t size;\n};\n\nenum dentry_d_lock_class {\n\tDENTRY_D_LOCK_NORMAL = 0,\n\tDENTRY_D_LOCK_NESTED = 1,\n};\n\nstruct external_name {\n\tunion {\n\t\tatomic_t count;\n\t\tstruct callback_head head;\n\t} u;\n\tunsigned char name[0];\n};\n\nenum d_walk_ret {\n\tD_WALK_CONTINUE = 0,\n\tD_WALK_QUIT = 1,\n\tD_WALK_NORETRY = 2,\n\tD_WALK_SKIP = 3,\n};\n\nstruct check_mount {\n\tstruct vfsmount *mnt;\n\tunsigned int mounted;\n};\n\nstruct select_data {\n\tstruct dentry *start;\n\tunion {\n\t\tlong int found;\n\t\tstruct dentry *victim;\n\t};\n\tstruct list_head dispose;\n};\n\ntypedef long int pao_T_____6;\n\nstruct fsxattr {\n\t__u32 fsx_xflags;\n\t__u32 fsx_extsize;\n\t__u32 fsx_nextents;\n\t__u32 fsx_projid;\n\t__u32 fsx_cowextsize;\n\tunsigned char fsx_pad[8];\n};\n\nenum file_time_flags {\n\tS_ATIME = 1,\n\tS_MTIME = 2,\n\tS_CTIME = 4,\n\tS_VERSION = 8,\n};\n\nstruct proc_mounts {\n\tstruct mnt_namespace *ns;\n\tstruct path root;\n\tint (*show)(struct seq_file *, struct vfsmount *);\n\tstruct mount cursor;\n};\n\nenum umount_tree_flags {\n\tUMOUNT_SYNC = 1,\n\tUMOUNT_PROPAGATE = 2,\n\tUMOUNT_CONNECTED = 4,\n};\n\nstruct simple_transaction_argresp {\n\tssize_t size;\n\tchar data[0];\n};\n\nstruct simple_attr {\n\tint (*get)(void *, u64 *);\n\tint (*set)(void *, u64);\n\tchar get_buf[24];\n\tchar set_buf[24];\n\tvoid *data;\n\tconst char *fmt;\n\tstruct mutex mutex;\n};\n\nstruct wb_completion {\n\tatomic_t cnt;\n\twait_queue_head_t *waitq;\n};\n\nstruct wb_writeback_work {\n\tlong int nr_pages;\n\tstruct super_block *sb;\n\tlong unsigned int *older_than_this;\n\tenum writeback_sync_modes sync_mode;\n\tunsigned int tagged_writepages: 1;\n\tunsigned int for_kupdate: 1;\n\tunsigned int range_cyclic: 1;\n\tunsigned int for_background: 1;\n\tunsigned int for_sync: 1;\n\tunsigned int auto_free: 1;\n\tenum wb_reason reason;\n\tstruct list_head list;\n\tstruct wb_completion *done;\n};\n\nstruct trace_event_raw_writeback_page_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_dirty_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_write_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tint sync_mode;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_work_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_pages;\n\tdev_t sb_dev;\n\tint sync_mode;\n\tint for_kupdate;\n\tint range_cyclic;\n\tint for_background;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_pages_written {\n\tstruct trace_entry ent;\n\tlong int pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_bdi_register {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wbc_class {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tint sync_mode;\n\tint for_kupdate;\n\tint for_background;\n\tint for_reclaim;\n\tint range_cyclic;\n\tlong int range_start;\n\tlong int range_end;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_queue_io {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong unsigned int older;\n\tlong int age;\n\tint moved;\n\tint reason;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_global_dirty_state {\n\tstruct trace_entry ent;\n\tlong unsigned int nr_dirty;\n\tlong unsigned int nr_writeback;\n\tlong unsigned int background_thresh;\n\tlong unsigned int dirty_thresh;\n\tlong unsigned int dirty_limit;\n\tlong unsigned int nr_dirtied;\n\tlong unsigned int nr_written;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_bdi_dirty_ratelimit {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int write_bw;\n\tlong unsigned int avg_write_bw;\n\tlong unsigned int dirty_rate;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tlong unsigned int balanced_dirty_ratelimit;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_balance_dirty_pages {\n\tstruct trace_entry ent;\n\tchar bdi[32];\n\tlong unsigned int limit;\n\tlong unsigned int setpoint;\n\tlong unsigned int dirty;\n\tlong unsigned int bdi_setpoint;\n\tlong unsigned int bdi_dirty;\n\tlong unsigned int dirty_ratelimit;\n\tlong unsigned int task_ratelimit;\n\tunsigned int dirtied;\n\tunsigned int dirtied_pause;\n\tlong unsigned int paused;\n\tlong int pause;\n\tlong unsigned int period;\n\tlong int think;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_sb_inodes_requeue {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_congest_waited_template {\n\tstruct trace_entry ent;\n\tunsigned int usec_timeout;\n\tunsigned int usec_delayed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_single_inode_template {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tino_t ino;\n\tlong unsigned int state;\n\tlong unsigned int dirtied_when;\n\tlong unsigned int writeback_index;\n\tlong int nr_to_write;\n\tlong unsigned int wrote;\n\tino_t cgroup_ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_writeback_inode_template {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int state;\n\t__u16 mode;\n\tlong unsigned int dirtied_when;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_writeback_page_template {};\n\nstruct trace_event_data_offsets_writeback_dirty_inode_template {};\n\nstruct trace_event_data_offsets_writeback_write_inode_template {};\n\nstruct trace_event_data_offsets_writeback_work_class {};\n\nstruct trace_event_data_offsets_writeback_pages_written {};\n\nstruct trace_event_data_offsets_writeback_class {};\n\nstruct trace_event_data_offsets_writeback_bdi_register {};\n\nstruct trace_event_data_offsets_wbc_class {};\n\nstruct trace_event_data_offsets_writeback_queue_io {};\n\nstruct trace_event_data_offsets_global_dirty_state {};\n\nstruct trace_event_data_offsets_bdi_dirty_ratelimit {};\n\nstruct trace_event_data_offsets_balance_dirty_pages {};\n\nstruct trace_event_data_offsets_writeback_sb_inodes_requeue {};\n\nstruct trace_event_data_offsets_writeback_congest_waited_template {};\n\nstruct trace_event_data_offsets_writeback_single_inode_template {};\n\nstruct trace_event_data_offsets_writeback_inode_template {};\n\ntypedef void (*btf_trace_writeback_dirty_page)(void *, struct page *, struct address_space *);\n\ntypedef void (*btf_trace_wait_on_page_writeback)(void *, struct page *, struct address_space *);\n\ntypedef void (*btf_trace_writeback_mark_inode_dirty)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_dirty_inode_start)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_dirty_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_writeback_write_inode_start)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_write_inode)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_writeback_queue)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_exec)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_start)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_written)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_wait)(void *, struct bdi_writeback *, struct wb_writeback_work *);\n\ntypedef void (*btf_trace_writeback_pages_written)(void *, long int);\n\ntypedef void (*btf_trace_writeback_wake_background)(void *, struct bdi_writeback *);\n\ntypedef void (*btf_trace_writeback_bdi_register)(void *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_wbc_writepage)(void *, struct writeback_control *, struct backing_dev_info *);\n\ntypedef void (*btf_trace_writeback_queue_io)(void *, struct bdi_writeback *, struct wb_writeback_work *, int);\n\ntypedef void (*btf_trace_global_dirty_state)(void *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_bdi_dirty_ratelimit)(void *, struct bdi_writeback *, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_balance_dirty_pages)(void *, struct bdi_writeback *, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long unsigned int, long int, long unsigned int);\n\ntypedef void (*btf_trace_writeback_sb_inodes_requeue)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_congestion_wait)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_writeback_wait_iff_congested)(void *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_writeback_single_inode_start)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_single_inode)(void *, struct inode *, struct writeback_control *, long unsigned int);\n\ntypedef void (*btf_trace_writeback_lazytime)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_lazytime_iput)(void *, struct inode *);\n\ntypedef void (*btf_trace_writeback_dirty_inode_enqueue)(void *, struct inode *);\n\ntypedef void (*btf_trace_sb_mark_inode_writeback)(void *, struct inode *);\n\ntypedef void (*btf_trace_sb_clear_inode_writeback)(void *, struct inode *);\n\nstruct splice_desc {\n\tsize_t total_len;\n\tunsigned int len;\n\tunsigned int flags;\n\tunion {\n\t\tvoid *userptr;\n\t\tstruct file *file;\n\t\tvoid *data;\n\t} u;\n\tloff_t pos;\n\tloff_t *opos;\n\tsize_t num_spliced;\n\tbool need_wakeup;\n};\n\ntypedef int splice_actor(struct pipe_inode_info *, struct pipe_buffer *, struct splice_desc *);\n\ntypedef int splice_direct_actor(struct pipe_inode_info *, struct splice_desc *);\n\nstruct old_utimbuf32 {\n\told_time32_t actime;\n\told_time32_t modtime;\n};\n\nstruct utimbuf {\n\t__kernel_old_time_t actime;\n\t__kernel_old_time_t modtime;\n};\n\ntypedef int __kernel_daddr_t;\n\nstruct ustat {\n\t__kernel_daddr_t f_tfree;\n\t__kernel_ino_t f_tinode;\n\tchar f_fname[6];\n\tchar f_fpack[6];\n};\n\nstruct statfs {\n\t__kernel_long_t f_type;\n\t__kernel_long_t f_bsize;\n\t__kernel_long_t f_blocks;\n\t__kernel_long_t f_bfree;\n\t__kernel_long_t f_bavail;\n\t__kernel_long_t f_files;\n\t__kernel_long_t f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__kernel_long_t f_namelen;\n\t__kernel_long_t f_frsize;\n\t__kernel_long_t f_flags;\n\t__kernel_long_t f_spare[4];\n};\n\nstruct statfs64 {\n\t__kernel_long_t f_type;\n\t__kernel_long_t f_bsize;\n\t__u64 f_blocks;\n\t__u64 f_bfree;\n\t__u64 f_bavail;\n\t__u64 f_files;\n\t__u64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__kernel_long_t f_namelen;\n\t__kernel_long_t f_frsize;\n\t__kernel_long_t f_flags;\n\t__kernel_long_t f_spare[4];\n};\n\nstruct compat_statfs64 {\n\t__u32 f_type;\n\t__u32 f_bsize;\n\t__u64 f_blocks;\n\t__u64 f_bfree;\n\t__u64 f_bavail;\n\t__u64 f_files;\n\t__u64 f_ffree;\n\t__kernel_fsid_t f_fsid;\n\t__u32 f_namelen;\n\t__u32 f_frsize;\n\t__u32 f_flags;\n\t__u32 f_spare[4];\n} __attribute__((packed));\n\ntypedef s32 compat_daddr_t;\n\ntypedef __kernel_fsid_t compat_fsid_t;\n\nstruct compat_statfs {\n\tint f_type;\n\tint f_bsize;\n\tint f_blocks;\n\tint f_bfree;\n\tint f_bavail;\n\tint f_files;\n\tint f_ffree;\n\tcompat_fsid_t f_fsid;\n\tint f_namelen;\n\tint f_frsize;\n\tint f_flags;\n\tint f_spare[4];\n};\n\nstruct compat_ustat {\n\tcompat_daddr_t f_tfree;\n\tcompat_ino_t f_tinode;\n\tchar f_fname[6];\n\tchar f_fpack[6];\n};\n\ntypedef struct ns_common *ns_get_path_helper_t(void *);\n\nstruct ns_get_path_task_args {\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct task_struct *task;\n};\n\nenum legacy_fs_param {\n\tLEGACY_FS_UNSET_PARAMS = 0,\n\tLEGACY_FS_MONOLITHIC_PARAMS = 1,\n\tLEGACY_FS_INDIVIDUAL_PARAMS = 2,\n};\n\nstruct legacy_fs_context {\n\tchar *legacy_data;\n\tsize_t data_size;\n\tenum legacy_fs_param param_type;\n};\n\nenum fsconfig_command {\n\tFSCONFIG_SET_FLAG = 0,\n\tFSCONFIG_SET_STRING = 1,\n\tFSCONFIG_SET_BINARY = 2,\n\tFSCONFIG_SET_PATH = 3,\n\tFSCONFIG_SET_PATH_EMPTY = 4,\n\tFSCONFIG_SET_FD = 5,\n\tFSCONFIG_CMD_CREATE = 6,\n\tFSCONFIG_CMD_RECONFIGURE = 7,\n};\n\nstruct dax_device;\n\nstruct iomap_page_ops;\n\nstruct iomap___2 {\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tstruct block_device *bdev;\n\tstruct dax_device *dax_dev;\n\tvoid *inline_data;\n\tvoid *private;\n\tconst struct iomap_page_ops *page_ops;\n};\n\nstruct iomap_page_ops {\n\tint (*page_prepare)(struct inode *, loff_t, unsigned int, struct iomap___2 *);\n\tvoid (*page_done)(struct inode *, loff_t, unsigned int, struct page *, struct iomap___2 *);\n};\n\nstruct decrypt_bh_ctx {\n\tstruct work_struct work;\n\tstruct buffer_head *bh;\n};\n\nstruct bh_lru {\n\tstruct buffer_head *bhs[16];\n};\n\nstruct bh_accounting {\n\tint nr;\n\tint ratelimit;\n};\n\ntypedef struct buffer_head *pto_T_____23;\n\nenum {\n\tDISK_EVENT_MEDIA_CHANGE = 1,\n\tDISK_EVENT_EJECT_REQUEST = 2,\n};\n\nstruct blk_integrity_profile;\n\nstruct blk_integrity {\n\tconst struct blk_integrity_profile *profile;\n\tunsigned char flags;\n\tunsigned char tuple_size;\n\tunsigned char interval_exp;\n\tunsigned char tag_size;\n};\n\nenum {\n\tBIOSET_NEED_BVECS = 1,\n\tBIOSET_NEED_RESCUER = 2,\n};\n\nstruct bdev_inode {\n\tstruct block_device bdev;\n\tstruct inode vfs_inode;\n};\n\nstruct blkdev_dio {\n\tunion {\n\t\tstruct kiocb *iocb;\n\t\tstruct task_struct *waiter;\n\t};\n\tsize_t size;\n\tatomic_t ref;\n\tbool multi_bio: 1;\n\tbool should_dirty: 1;\n\tbool is_sync: 1;\n\tstruct bio bio;\n};\n\nstruct bd_holder_disk {\n\tstruct list_head list;\n\tstruct gendisk *disk;\n\tint refcnt;\n};\n\ntypedef int dio_iodone_t(struct kiocb *, loff_t, ssize_t, void *);\n\ntypedef void dio_submit_t(struct bio *, struct inode *, loff_t);\n\nenum {\n\tDIO_LOCKING = 1,\n\tDIO_SKIP_HOLES = 2,\n};\n\nstruct dio_submit {\n\tstruct bio *bio;\n\tunsigned int blkbits;\n\tunsigned int blkfactor;\n\tunsigned int start_zero_done;\n\tint pages_in_io;\n\tsector_t block_in_file;\n\tunsigned int blocks_available;\n\tint reap_counter;\n\tsector_t final_block_in_request;\n\tint boundary;\n\tget_block_t *get_block;\n\tdio_submit_t *submit_io;\n\tloff_t logical_offset_in_bio;\n\tsector_t final_block_in_bio;\n\tsector_t next_block_for_io;\n\tstruct page *cur_page;\n\tunsigned int cur_page_offset;\n\tunsigned int cur_page_len;\n\tsector_t cur_page_block;\n\tloff_t cur_page_fs_offset;\n\tstruct iov_iter *iter;\n\tunsigned int head;\n\tunsigned int tail;\n\tsize_t from;\n\tsize_t to;\n};\n\nstruct dio {\n\tint flags;\n\tint op;\n\tint op_flags;\n\tblk_qc_t bio_cookie;\n\tstruct gendisk *bio_disk;\n\tstruct inode *inode;\n\tloff_t i_size;\n\tdio_iodone_t *end_io;\n\tvoid *private;\n\tspinlock_t bio_lock;\n\tint page_errors;\n\tint is_async;\n\tbool defer_completion;\n\tbool should_dirty;\n\tint io_error;\n\tlong unsigned int refcount;\n\tstruct bio *bio_list;\n\tstruct task_struct *waiter;\n\tstruct kiocb *iocb;\n\tssize_t result;\n\tunion {\n\t\tstruct page *pages[64];\n\t\tstruct work_struct complete_work;\n\t};\n\tlong: 64;\n};\n\nstruct bvec_iter_all {\n\tstruct bio_vec bv;\n\tint idx;\n\tunsigned int done;\n};\n\nstruct mpage_readpage_args {\n\tstruct bio *bio;\n\tstruct page *page;\n\tunsigned int nr_pages;\n\tbool is_readahead;\n\tsector_t last_block_in_bio;\n\tstruct buffer_head map_bh;\n\tlong unsigned int first_logical_block;\n\tget_block_t *get_block;\n};\n\nstruct mpage_data {\n\tstruct bio *bio;\n\tsector_t last_block_in_bio;\n\tget_block_t *get_block;\n\tunsigned int use_writepage;\n};\n\ntypedef u32 nlink_t;\n\ntypedef int (*proc_write_t)(struct file *, char *, size_t);\n\nstruct proc_dir_entry {\n\tatomic_t in_use;\n\trefcount_t refcnt;\n\tstruct list_head pde_openers;\n\tspinlock_t pde_unload_lock;\n\tstruct completion *pde_unload_completion;\n\tconst struct inode_operations *proc_iops;\n\tunion {\n\t\tconst struct proc_ops *proc_ops;\n\t\tconst struct file_operations *proc_dir_ops;\n\t};\n\tconst struct dentry_operations *proc_dops;\n\tunion {\n\t\tconst struct seq_operations *seq_ops;\n\t\tint (*single_show)(struct seq_file *, void *);\n\t};\n\tproc_write_t write;\n\tvoid *data;\n\tunsigned int state_size;\n\tunsigned int low_ino;\n\tnlink_t nlink;\n\tkuid_t uid;\n\tkgid_t gid;\n\tloff_t size;\n\tstruct proc_dir_entry *parent;\n\tstruct rb_root subdir;\n\tstruct rb_node subdir_node;\n\tchar *name;\n\tumode_t mode;\n\tu8 flags;\n\tu8 namelen;\n\tchar inline_name[0];\n};\n\nunion proc_op {\n\tint (*proc_get_link)(struct dentry *, struct path *);\n\tint (*proc_show)(struct seq_file *, struct pid_namespace *, struct pid *, struct task_struct *);\n\tconst char *lsm;\n};\n\nstruct proc_inode {\n\tstruct pid *pid;\n\tunsigned int fd;\n\tunion proc_op op;\n\tstruct proc_dir_entry *pde;\n\tstruct ctl_table_header *sysctl;\n\tstruct ctl_table *sysctl_entry;\n\tstruct hlist_node sibling_inodes;\n\tconst struct proc_ns_operations *ns_ops;\n\tstruct inode vfs_inode;\n};\n\nstruct proc_fs_opts {\n\tint flag;\n\tconst char *str;\n};\n\nstruct file_handle {\n\t__u32 handle_bytes;\n\tint handle_type;\n\tunsigned char f_handle[0];\n};\n\nstruct inotify_inode_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tint wd;\n};\n\nstruct dnotify_struct {\n\tstruct dnotify_struct *dn_next;\n\t__u32 dn_mask;\n\tint dn_fd;\n\tstruct file *dn_filp;\n\tfl_owner_t dn_owner;\n};\n\nstruct dnotify_mark {\n\tstruct fsnotify_mark fsn_mark;\n\tstruct dnotify_struct *dn;\n};\n\nstruct inotify_event_info {\n\tstruct fsnotify_event fse;\n\tu32 mask;\n\tint wd;\n\tu32 sync_cookie;\n\tint name_len;\n\tchar name[0];\n};\n\nstruct inotify_event {\n\t__s32 wd;\n\t__u32 mask;\n\t__u32 cookie;\n\t__u32 len;\n\tchar name[0];\n};\n\nstruct epoll_event {\n\t__poll_t events;\n\t__u64 data;\n} __attribute__((packed));\n\nstruct epoll_filefd {\n\tstruct file *file;\n\tint fd;\n} __attribute__((packed));\n\nstruct nested_call_node {\n\tstruct list_head llink;\n\tvoid *cookie;\n\tvoid *ctx;\n};\n\nstruct nested_calls {\n\tstruct list_head tasks_call_list;\n\tspinlock_t lock;\n};\n\nstruct eventpoll;\n\nstruct epitem {\n\tunion {\n\t\tstruct rb_node rbn;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct list_head rdllink;\n\tstruct epitem *next;\n\tstruct epoll_filefd ffd;\n\tint nwait;\n\tstruct list_head pwqlist;\n\tstruct eventpoll *ep;\n\tstruct list_head fllink;\n\tstruct wakeup_source *ws;\n\tstruct epoll_event event;\n};\n\nstruct eventpoll {\n\tstruct mutex mtx;\n\twait_queue_head_t wq;\n\twait_queue_head_t poll_wait;\n\tstruct list_head rdllist;\n\trwlock_t lock;\n\tstruct rb_root_cached rbr;\n\tstruct epitem *ovflist;\n\tstruct wakeup_source *ws;\n\tstruct user_struct *user;\n\tstruct file *file;\n\tstruct list_head visited_list_link;\n\tint visited;\n\tunsigned int napi_id;\n};\n\nstruct eppoll_entry {\n\tstruct list_head llink;\n\tstruct epitem *base;\n\twait_queue_entry_t wait;\n\twait_queue_head_t *whead;\n};\n\nstruct ep_pqueue {\n\tpoll_table pt;\n\tstruct epitem *epi;\n};\n\nstruct ep_send_events_data {\n\tint maxevents;\n\tstruct epoll_event *events;\n\tint res;\n};\n\nstruct signalfd_siginfo {\n\t__u32 ssi_signo;\n\t__s32 ssi_errno;\n\t__s32 ssi_code;\n\t__u32 ssi_pid;\n\t__u32 ssi_uid;\n\t__s32 ssi_fd;\n\t__u32 ssi_tid;\n\t__u32 ssi_band;\n\t__u32 ssi_overrun;\n\t__u32 ssi_trapno;\n\t__s32 ssi_status;\n\t__s32 ssi_int;\n\t__u64 ssi_ptr;\n\t__u64 ssi_utime;\n\t__u64 ssi_stime;\n\t__u64 ssi_addr;\n\t__u16 ssi_addr_lsb;\n\t__u16 __pad2;\n\t__s32 ssi_syscall;\n\t__u64 ssi_call_addr;\n\t__u32 ssi_arch;\n\t__u8 __pad[28];\n};\n\nstruct signalfd_ctx {\n\tsigset_t sigmask;\n};\n\nstruct timerfd_ctx {\n\tunion {\n\t\tstruct hrtimer tmr;\n\t\tstruct alarm alarm;\n\t} t;\n\tktime_t tintv;\n\tktime_t moffs;\n\twait_queue_head_t wqh;\n\tu64 ticks;\n\tint clockid;\n\tshort unsigned int expired;\n\tshort unsigned int settime_flags;\n\tstruct callback_head rcu;\n\tstruct list_head clist;\n\tspinlock_t cancel_lock;\n\tbool might_cancel;\n};\n\nstruct eventfd_ctx {\n\tstruct kref kref;\n\twait_queue_head_t wqh;\n\t__u64 count;\n\tunsigned int flags;\n\tint id;\n};\n\nstruct kioctx;\n\nstruct kioctx_table {\n\tstruct callback_head rcu;\n\tunsigned int nr;\n\tstruct kioctx *table[0];\n};\n\ntypedef __kernel_ulong_t aio_context_t;\n\nenum {\n\tIOCB_CMD_PREAD = 0,\n\tIOCB_CMD_PWRITE = 1,\n\tIOCB_CMD_FSYNC = 2,\n\tIOCB_CMD_FDSYNC = 3,\n\tIOCB_CMD_POLL = 5,\n\tIOCB_CMD_NOOP = 6,\n\tIOCB_CMD_PREADV = 7,\n\tIOCB_CMD_PWRITEV = 8,\n};\n\nstruct io_event {\n\t__u64 data;\n\t__u64 obj;\n\t__s64 res;\n\t__s64 res2;\n};\n\nstruct iocb {\n\t__u64 aio_data;\n\t__u32 aio_key;\n\t__kernel_rwf_t aio_rw_flags;\n\t__u16 aio_lio_opcode;\n\t__s16 aio_reqprio;\n\t__u32 aio_fildes;\n\t__u64 aio_buf;\n\t__u64 aio_nbytes;\n\t__s64 aio_offset;\n\t__u64 aio_reserved2;\n\t__u32 aio_flags;\n\t__u32 aio_resfd;\n};\n\ntypedef int kiocb_cancel_fn(struct kiocb *);\n\ntypedef u32 compat_aio_context_t;\n\nstruct aio_ring {\n\tunsigned int id;\n\tunsigned int nr;\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int magic;\n\tunsigned int compat_features;\n\tunsigned int incompat_features;\n\tunsigned int header_length;\n\tstruct io_event io_events[0];\n};\n\nstruct kioctx_cpu;\n\nstruct ctx_rq_wait;\n\nstruct kioctx {\n\tstruct percpu_ref users;\n\tatomic_t dead;\n\tstruct percpu_ref reqs;\n\tlong unsigned int user_id;\n\tstruct kioctx_cpu *cpu;\n\tunsigned int req_batch;\n\tunsigned int max_reqs;\n\tunsigned int nr_events;\n\tlong unsigned int mmap_base;\n\tlong unsigned int mmap_size;\n\tstruct page **ring_pages;\n\tlong int nr_pages;\n\tstruct rcu_work free_rwork;\n\tstruct ctx_rq_wait *rq_wait;\n\tlong: 64;\n\tstruct {\n\t\tatomic_t reqs_available;\n\t\tlong: 32;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tspinlock_t ctx_lock;\n\t\tstruct list_head active_reqs;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tstruct mutex ring_lock;\n\t\twait_queue_head_t wait;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tunsigned int tail;\n\t\tunsigned int completed_events;\n\t\tspinlock_t completion_lock;\n\t\tlong: 32;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tstruct page *internal_pages[8];\n\tstruct file *aio_ring_file;\n\tunsigned int id;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kioctx_cpu {\n\tunsigned int reqs_available;\n};\n\nstruct ctx_rq_wait {\n\tstruct completion comp;\n\tatomic_t count;\n};\n\nstruct fsync_iocb {\n\tstruct file *file;\n\tstruct work_struct work;\n\tbool datasync;\n\tstruct cred *creds;\n};\n\nstruct poll_iocb {\n\tstruct file *file;\n\tstruct wait_queue_head *head;\n\t__poll_t events;\n\tbool done;\n\tbool cancelled;\n\tstruct wait_queue_entry wait;\n\tstruct work_struct work;\n};\n\nstruct eventfd_ctx___2;\n\nstruct aio_kiocb {\n\tunion {\n\t\tstruct file *ki_filp;\n\t\tstruct kiocb rw;\n\t\tstruct fsync_iocb fsync;\n\t\tstruct poll_iocb poll;\n\t};\n\tstruct kioctx *ki_ctx;\n\tkiocb_cancel_fn *ki_cancel;\n\tstruct io_event ki_res;\n\tstruct list_head ki_list;\n\trefcount_t ki_refcnt;\n\tstruct eventfd_ctx___2 *ki_eventfd;\n};\n\nstruct aio_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct aio_kiocb *iocb;\n\tint error;\n};\n\nstruct __aio_sigset {\n\tconst sigset_t *sigmask;\n\tsize_t sigsetsize;\n};\n\nstruct __compat_aio_sigset {\n\tcompat_uptr_t sigmask;\n\tcompat_size_t sigsetsize;\n};\n\nenum {\n\tPERCPU_REF_INIT_ATOMIC = 1,\n\tPERCPU_REF_INIT_DEAD = 2,\n\tPERCPU_REF_ALLOW_REINIT = 4,\n};\n\nstruct user_msghdr {\n\tvoid *msg_name;\n\tint msg_namelen;\n\tstruct iovec *msg_iov;\n\t__kernel_size_t msg_iovlen;\n\tvoid *msg_control;\n\t__kernel_size_t msg_controllen;\n\tunsigned int msg_flags;\n};\n\nstruct compat_msghdr {\n\tcompat_uptr_t msg_name;\n\tcompat_int_t msg_namelen;\n\tcompat_uptr_t msg_iov;\n\tcompat_size_t msg_iovlen;\n\tcompat_uptr_t msg_control;\n\tcompat_size_t msg_controllen;\n\tcompat_uint_t msg_flags;\n};\n\nstruct scm_fp_list {\n\tshort int count;\n\tshort int max;\n\tstruct user_struct *user;\n\tstruct file *fp[253];\n};\n\nstruct unix_skb_parms {\n\tstruct pid *pid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct scm_fp_list *fp;\n\tu32 secid;\n\tu32 consumed;\n};\n\nstruct trace_event_raw_io_uring_create {\n\tstruct trace_entry ent;\n\tint fd;\n\tvoid *ctx;\n\tu32 sq_entries;\n\tu32 cq_entries;\n\tu32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_register {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tunsigned int opcode;\n\tunsigned int nr_files;\n\tunsigned int nr_bufs;\n\tbool eventfd;\n\tlong int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_file_get {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint fd;\n\tchar __data[0];\n};\n\nstruct io_wq_work;\n\nstruct trace_event_raw_io_uring_queue_async_work {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint rw;\n\tvoid *req;\n\tstruct io_wq_work *work;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct io_wq_work_node {\n\tstruct io_wq_work_node *next;\n};\n\nstruct io_wq_work {\n\tstruct io_wq_work_node list;\n\tstruct files_struct *files;\n\tstruct mm_struct *mm;\n\tconst struct cred *creds;\n\tstruct fs_struct *fs;\n\tunsigned int flags;\n};\n\nstruct trace_event_raw_io_uring_defer {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tlong long unsigned int data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_link {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tvoid *req;\n\tvoid *target_req;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_cqring_wait {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tint min_events;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_fail_link {\n\tstruct trace_entry ent;\n\tvoid *req;\n\tvoid *link;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_complete {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tu64 user_data;\n\tlong int res;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_submit_sqe {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tu8 opcode;\n\tu64 user_data;\n\tbool force_nonblock;\n\tbool sq_thread;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_poll_arm {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tu8 opcode;\n\tu64 user_data;\n\tint mask;\n\tint events;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_poll_wake {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tu8 opcode;\n\tu64 user_data;\n\tint mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_add {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tu8 opcode;\n\tu64 user_data;\n\tint mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_io_uring_task_run {\n\tstruct trace_entry ent;\n\tvoid *ctx;\n\tu8 opcode;\n\tu64 user_data;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_io_uring_create {};\n\nstruct trace_event_data_offsets_io_uring_register {};\n\nstruct trace_event_data_offsets_io_uring_file_get {};\n\nstruct trace_event_data_offsets_io_uring_queue_async_work {};\n\nstruct trace_event_data_offsets_io_uring_defer {};\n\nstruct trace_event_data_offsets_io_uring_link {};\n\nstruct trace_event_data_offsets_io_uring_cqring_wait {};\n\nstruct trace_event_data_offsets_io_uring_fail_link {};\n\nstruct trace_event_data_offsets_io_uring_complete {};\n\nstruct trace_event_data_offsets_io_uring_submit_sqe {};\n\nstruct trace_event_data_offsets_io_uring_poll_arm {};\n\nstruct trace_event_data_offsets_io_uring_poll_wake {};\n\nstruct trace_event_data_offsets_io_uring_task_add {};\n\nstruct trace_event_data_offsets_io_uring_task_run {};\n\ntypedef void (*btf_trace_io_uring_create)(void *, int, void *, u32, u32, u32);\n\ntypedef void (*btf_trace_io_uring_register)(void *, void *, unsigned int, unsigned int, unsigned int, bool, long int);\n\ntypedef void (*btf_trace_io_uring_file_get)(void *, void *, int);\n\ntypedef void (*btf_trace_io_uring_queue_async_work)(void *, void *, int, void *, struct io_wq_work *, unsigned int);\n\ntypedef void (*btf_trace_io_uring_defer)(void *, void *, void *, long long unsigned int);\n\ntypedef void (*btf_trace_io_uring_link)(void *, void *, void *, void *);\n\ntypedef void (*btf_trace_io_uring_cqring_wait)(void *, void *, int);\n\ntypedef void (*btf_trace_io_uring_fail_link)(void *, void *, void *);\n\ntypedef void (*btf_trace_io_uring_complete)(void *, void *, u64, long int);\n\ntypedef void (*btf_trace_io_uring_submit_sqe)(void *, void *, u8, u64, bool, bool);\n\ntypedef void (*btf_trace_io_uring_poll_arm)(void *, void *, u8, u64, int, int);\n\ntypedef void (*btf_trace_io_uring_poll_wake)(void *, void *, u8, u64, int);\n\ntypedef void (*btf_trace_io_uring_task_add)(void *, void *, u8, u64, int);\n\ntypedef void (*btf_trace_io_uring_task_run)(void *, void *, u8, u64);\n\nstruct io_uring_sqe {\n\t__u8 opcode;\n\t__u8 flags;\n\t__u16 ioprio;\n\t__s32 fd;\n\tunion {\n\t\t__u64 off;\n\t\t__u64 addr2;\n\t};\n\tunion {\n\t\t__u64 addr;\n\t\t__u64 splice_off_in;\n\t};\n\t__u32 len;\n\tunion {\n\t\t__kernel_rwf_t rw_flags;\n\t\t__u32 fsync_flags;\n\t\t__u16 poll_events;\n\t\t__u32 sync_range_flags;\n\t\t__u32 msg_flags;\n\t\t__u32 timeout_flags;\n\t\t__u32 accept_flags;\n\t\t__u32 cancel_flags;\n\t\t__u32 open_flags;\n\t\t__u32 statx_flags;\n\t\t__u32 fadvise_advice;\n\t\t__u32 splice_flags;\n\t};\n\t__u64 user_data;\n\tunion {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\t__u16 buf_index;\n\t\t\t\t__u16 buf_group;\n\t\t\t};\n\t\t\t__u16 personality;\n\t\t\t__s32 splice_fd_in;\n\t\t};\n\t\t__u64 __pad2[3];\n\t};\n};\n\nenum {\n\tIOSQE_FIXED_FILE_BIT = 0,\n\tIOSQE_IO_DRAIN_BIT = 1,\n\tIOSQE_IO_LINK_BIT = 2,\n\tIOSQE_IO_HARDLINK_BIT = 3,\n\tIOSQE_ASYNC_BIT = 4,\n\tIOSQE_BUFFER_SELECT_BIT = 5,\n};\n\nenum {\n\tIORING_OP_NOP = 0,\n\tIORING_OP_READV = 1,\n\tIORING_OP_WRITEV = 2,\n\tIORING_OP_FSYNC = 3,\n\tIORING_OP_READ_FIXED = 4,\n\tIORING_OP_WRITE_FIXED = 5,\n\tIORING_OP_POLL_ADD = 6,\n\tIORING_OP_POLL_REMOVE = 7,\n\tIORING_OP_SYNC_FILE_RANGE = 8,\n\tIORING_OP_SENDMSG = 9,\n\tIORING_OP_RECVMSG = 10,\n\tIORING_OP_TIMEOUT = 11,\n\tIORING_OP_TIMEOUT_REMOVE = 12,\n\tIORING_OP_ACCEPT = 13,\n\tIORING_OP_ASYNC_CANCEL = 14,\n\tIORING_OP_LINK_TIMEOUT = 15,\n\tIORING_OP_CONNECT = 16,\n\tIORING_OP_FALLOCATE = 17,\n\tIORING_OP_OPENAT = 18,\n\tIORING_OP_CLOSE = 19,\n\tIORING_OP_FILES_UPDATE = 20,\n\tIORING_OP_STATX = 21,\n\tIORING_OP_READ = 22,\n\tIORING_OP_WRITE = 23,\n\tIORING_OP_FADVISE = 24,\n\tIORING_OP_MADVISE = 25,\n\tIORING_OP_SEND = 26,\n\tIORING_OP_RECV = 27,\n\tIORING_OP_OPENAT2 = 28,\n\tIORING_OP_EPOLL_CTL = 29,\n\tIORING_OP_SPLICE = 30,\n\tIORING_OP_PROVIDE_BUFFERS = 31,\n\tIORING_OP_REMOVE_BUFFERS = 32,\n\tIORING_OP_TEE = 33,\n\tIORING_OP_LAST = 34,\n};\n\nstruct io_uring_cqe {\n\t__u64 user_data;\n\t__s32 res;\n\t__u32 flags;\n};\n\nenum {\n\tIORING_CQE_BUFFER_SHIFT = 16,\n};\n\nstruct io_sqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 flags;\n\t__u32 dropped;\n\t__u32 array;\n\t__u32 resv1;\n\t__u64 resv2;\n};\n\nstruct io_cqring_offsets {\n\t__u32 head;\n\t__u32 tail;\n\t__u32 ring_mask;\n\t__u32 ring_entries;\n\t__u32 overflow;\n\t__u32 cqes;\n\t__u32 flags;\n\t__u32 resv1;\n\t__u64 resv2;\n};\n\nstruct io_uring_params {\n\t__u32 sq_entries;\n\t__u32 cq_entries;\n\t__u32 flags;\n\t__u32 sq_thread_cpu;\n\t__u32 sq_thread_idle;\n\t__u32 features;\n\t__u32 wq_fd;\n\t__u32 resv[3];\n\tstruct io_sqring_offsets sq_off;\n\tstruct io_cqring_offsets cq_off;\n};\n\nstruct io_uring_files_update {\n\t__u32 offset;\n\t__u32 resv;\n\t__u64 fds;\n};\n\nstruct io_uring_probe_op {\n\t__u8 op;\n\t__u8 resv;\n\t__u16 flags;\n\t__u32 resv2;\n};\n\nstruct io_uring_probe {\n\t__u8 last_op;\n\t__u8 ops_len;\n\t__u16 resv;\n\t__u32 resv2[3];\n\tstruct io_uring_probe_op ops[0];\n};\n\nenum {\n\tIO_WQ_WORK_CANCEL = 1,\n\tIO_WQ_WORK_HASHED = 4,\n\tIO_WQ_WORK_UNBOUND = 32,\n\tIO_WQ_WORK_NO_CANCEL = 256,\n\tIO_WQ_WORK_CONCURRENT = 512,\n\tIO_WQ_HASH_SHIFT = 24,\n};\n\nenum io_wq_cancel {\n\tIO_WQ_CANCEL_OK = 0,\n\tIO_WQ_CANCEL_RUNNING = 1,\n\tIO_WQ_CANCEL_NOTFOUND = 2,\n};\n\ntypedef void free_work_fn(struct io_wq_work *);\n\ntypedef void io_wq_work_fn(struct io_wq_work **);\n\nstruct io_wq_data {\n\tstruct user_struct *user;\n\tio_wq_work_fn *do_work;\n\tfree_work_fn *free_work;\n};\n\nstruct io_uring {\n\tu32 head;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 tail;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct io_rings {\n\tstruct io_uring sq;\n\tstruct io_uring cq;\n\tu32 sq_ring_mask;\n\tu32 cq_ring_mask;\n\tu32 sq_ring_entries;\n\tu32 cq_ring_entries;\n\tu32 sq_dropped;\n\tu32 sq_flags;\n\tu32 cq_flags;\n\tu32 cq_overflow;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct io_uring_cqe cqes[0];\n};\n\nstruct io_mapped_ubuf {\n\tu64 ubuf;\n\tsize_t len;\n\tstruct bio_vec *bvec;\n\tunsigned int nr_bvecs;\n};\n\nstruct fixed_file_table {\n\tstruct file **files;\n};\n\nstruct fixed_file_data;\n\nstruct fixed_file_ref_node {\n\tstruct percpu_ref refs;\n\tstruct list_head node;\n\tstruct list_head file_list;\n\tstruct fixed_file_data *file_data;\n\tstruct llist_node llist;\n};\n\nstruct io_ring_ctx;\n\nstruct fixed_file_data {\n\tstruct fixed_file_table *table;\n\tstruct io_ring_ctx *ctx;\n\tstruct percpu_ref *cur_refs;\n\tstruct percpu_ref refs;\n\tstruct completion done;\n\tstruct list_head ref_list;\n\tspinlock_t lock;\n};\n\nstruct io_wq;\n\nstruct io_kiocb;\n\nstruct io_ring_ctx {\n\tstruct {\n\t\tstruct percpu_ref refs;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tunsigned int flags;\n\t\tunsigned int compat: 1;\n\t\tunsigned int account_mem: 1;\n\t\tunsigned int cq_overflow_flushed: 1;\n\t\tunsigned int drain_next: 1;\n\t\tunsigned int eventfd_async: 1;\n\t\tu32 *sq_array;\n\t\tunsigned int cached_sq_head;\n\t\tunsigned int sq_entries;\n\t\tunsigned int sq_mask;\n\t\tunsigned int sq_thread_idle;\n\t\tunsigned int cached_sq_dropped;\n\t\tatomic_t cached_cq_overflow;\n\t\tlong unsigned int sq_check_overflow;\n\t\tstruct list_head defer_list;\n\t\tstruct list_head timeout_list;\n\t\tstruct list_head cq_overflow_list;\n\t\twait_queue_head_t inflight_wait;\n\t\tstruct io_uring_sqe *sq_sqes;\n\t};\n\tstruct io_rings *rings;\n\tstruct io_wq *io_wq;\n\tstruct task_struct *sqo_thread;\n\tstruct mm_struct *sqo_mm;\n\twait_queue_head_t sqo_wait;\n\tstruct fixed_file_data *file_data;\n\tunsigned int nr_user_files;\n\tint ring_fd;\n\tstruct file *ring_file;\n\tunsigned int nr_user_bufs;\n\tstruct io_mapped_ubuf *user_bufs;\n\tstruct user_struct *user;\n\tconst struct cred *creds;\n\tstruct completion ref_comp;\n\tstruct completion sq_thread_comp;\n\tstruct io_kiocb *fallback_req;\n\tstruct socket *ring_sock;\n\tstruct idr io_buffer_idr;\n\tstruct idr personality_idr;\n\tlong: 64;\n\tlong: 64;\n\tstruct {\n\t\tunsigned int cached_cq_tail;\n\t\tunsigned int cq_entries;\n\t\tunsigned int cq_mask;\n\t\tatomic_t cq_timeouts;\n\t\tlong unsigned int cq_check_overflow;\n\t\tstruct wait_queue_head cq_wait;\n\t\tstruct fasync_struct *cq_fasync;\n\t\tstruct eventfd_ctx___2 *cq_ev_fd;\n\t};\n\tstruct {\n\t\tstruct mutex uring_lock;\n\t\twait_queue_head_t wait;\n\t\tlong: 64;\n\t};\n\tstruct {\n\t\tspinlock_t completion_lock;\n\t\tstruct list_head poll_list;\n\t\tstruct hlist_head *cancel_hash;\n\t\tunsigned int cancel_hash_bits;\n\t\tbool poll_multi_file;\n\t\tspinlock_t inflight_lock;\n\t\tstruct list_head inflight_list;\n\t};\n\tstruct delayed_work file_put_work;\n\tstruct llist_head file_put_llist;\n\tstruct work_struct exit_work;\n};\n\nstruct io_buffer {\n\tstruct list_head list;\n\t__u64 addr;\n\t__s32 len;\n\t__u16 bid;\n};\n\nstruct io_rw {\n\tstruct kiocb kiocb;\n\tu64 addr;\n\tu64 len;\n};\n\nstruct io_poll_iocb {\n\tstruct file *file;\n\tunion {\n\t\tstruct wait_queue_head *head;\n\t\tu64 addr;\n\t};\n\t__poll_t events;\n\tbool done;\n\tbool canceled;\n\tstruct wait_queue_entry wait;\n};\n\nstruct io_accept {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint *addr_len;\n\tint flags;\n\tlong unsigned int nofile;\n};\n\nstruct io_sync {\n\tstruct file *file;\n\tloff_t len;\n\tloff_t off;\n\tint flags;\n\tint mode;\n};\n\nstruct io_cancel {\n\tstruct file *file;\n\tu64 addr;\n};\n\nstruct io_timeout {\n\tstruct file *file;\n\tu64 addr;\n\tint flags;\n\tu32 off;\n\tu32 target_seq;\n};\n\nstruct io_connect {\n\tstruct file *file;\n\tstruct sockaddr *addr;\n\tint addr_len;\n};\n\nstruct io_sr_msg {\n\tstruct file *file;\n\tunion {\n\t\tstruct user_msghdr *msg;\n\t\tvoid *buf;\n\t};\n\tint msg_flags;\n\tint bgid;\n\tsize_t len;\n\tstruct io_buffer *kbuf;\n};\n\nstruct io_open {\n\tstruct file *file;\n\tint dfd;\n\tstruct filename *filename;\n\tstruct open_how how;\n\tlong unsigned int nofile;\n};\n\nstruct io_close {\n\tstruct file *file;\n\tstruct file *put_file;\n\tint fd;\n};\n\nstruct io_files_update {\n\tstruct file *file;\n\tu64 arg;\n\tu32 nr_args;\n\tu32 offset;\n};\n\nstruct io_fadvise {\n\tstruct file *file;\n\tu64 offset;\n\tu32 len;\n\tu32 advice;\n};\n\nstruct io_madvise {\n\tstruct file *file;\n\tu64 addr;\n\tu32 len;\n\tu32 advice;\n};\n\nstruct io_epoll {\n\tstruct file *file;\n\tint epfd;\n\tint op;\n\tint fd;\n\tstruct epoll_event event;\n} __attribute__((packed));\n\nstruct io_splice {\n\tstruct file *file_out;\n\tstruct file *file_in;\n\tloff_t off_out;\n\tloff_t off_in;\n\tu64 len;\n\tunsigned int flags;\n};\n\nstruct io_provide_buf {\n\tstruct file *file;\n\t__u64 addr;\n\t__s32 len;\n\t__u32 bgid;\n\t__u16 nbufs;\n\t__u16 bid;\n};\n\nstruct io_statx {\n\tstruct file *file;\n\tint dfd;\n\tunsigned int mask;\n\tunsigned int flags;\n\tconst char *filename;\n\tstruct statx *buffer;\n};\n\nstruct io_async_ctx;\n\nstruct async_poll;\n\nstruct io_kiocb {\n\tunion {\n\t\tstruct file *file;\n\t\tstruct io_rw rw;\n\t\tstruct io_poll_iocb poll;\n\t\tstruct io_accept accept;\n\t\tstruct io_sync sync;\n\t\tstruct io_cancel cancel;\n\t\tstruct io_timeout timeout;\n\t\tstruct io_connect connect;\n\t\tstruct io_sr_msg sr_msg;\n\t\tstruct io_open open;\n\t\tstruct io_close close;\n\t\tstruct io_files_update files_update;\n\t\tstruct io_fadvise fadvise;\n\t\tstruct io_madvise madvise;\n\t\tstruct io_epoll epoll;\n\t\tstruct io_splice splice;\n\t\tstruct io_provide_buf pbuf;\n\t\tstruct io_statx statx;\n\t};\n\tstruct io_async_ctx *io;\n\tint cflags;\n\tu8 opcode;\n\tu8 iopoll_completed;\n\tu16 buf_index;\n\tstruct io_ring_ctx *ctx;\n\tstruct list_head list;\n\tunsigned int flags;\n\trefcount_t refs;\n\tstruct task_struct *task;\n\tlong unsigned int fsize;\n\tu64 user_data;\n\tu32 result;\n\tu32 sequence;\n\tstruct list_head link_list;\n\tstruct list_head inflight_entry;\n\tstruct percpu_ref *fixed_file_refs;\n\tunion {\n\t\tstruct {\n\t\t\tstruct callback_head task_work;\n\t\t\tstruct hlist_node hash_node;\n\t\t\tstruct async_poll *apoll;\n\t\t};\n\t\tstruct io_wq_work work;\n\t};\n};\n\nstruct io_timeout_data {\n\tstruct io_kiocb *req;\n\tstruct hrtimer timer;\n\tstruct timespec64 ts;\n\tenum hrtimer_mode mode;\n};\n\nstruct io_async_connect {\n\tstruct __kernel_sockaddr_storage address;\n};\n\nstruct io_async_msghdr {\n\tstruct iovec fast_iov[8];\n\tstruct iovec *iov;\n\tstruct sockaddr *uaddr;\n\tstruct msghdr msg;\n\tstruct __kernel_sockaddr_storage addr;\n};\n\nstruct io_async_rw {\n\tstruct iovec fast_iov[8];\n\tstruct iovec *iov;\n\tssize_t nr_segs;\n\tssize_t size;\n};\n\nstruct io_async_ctx {\n\tunion {\n\t\tstruct io_async_rw rw;\n\t\tstruct io_async_msghdr msg;\n\t\tstruct io_async_connect connect;\n\t\tstruct io_timeout_data timeout;\n\t};\n};\n\nenum {\n\tREQ_F_FIXED_FILE_BIT = 0,\n\tREQ_F_IO_DRAIN_BIT = 1,\n\tREQ_F_LINK_BIT = 2,\n\tREQ_F_HARDLINK_BIT = 3,\n\tREQ_F_FORCE_ASYNC_BIT = 4,\n\tREQ_F_BUFFER_SELECT_BIT = 5,\n\tREQ_F_LINK_HEAD_BIT = 6,\n\tREQ_F_LINK_NEXT_BIT = 7,\n\tREQ_F_FAIL_LINK_BIT = 8,\n\tREQ_F_INFLIGHT_BIT = 9,\n\tREQ_F_CUR_POS_BIT = 10,\n\tREQ_F_NOWAIT_BIT = 11,\n\tREQ_F_LINK_TIMEOUT_BIT = 12,\n\tREQ_F_TIMEOUT_BIT = 13,\n\tREQ_F_ISREG_BIT = 14,\n\tREQ_F_MUST_PUNT_BIT = 15,\n\tREQ_F_TIMEOUT_NOSEQ_BIT = 16,\n\tREQ_F_COMP_LOCKED_BIT = 17,\n\tREQ_F_NEED_CLEANUP_BIT = 18,\n\tREQ_F_OVERFLOW_BIT = 19,\n\tREQ_F_POLLED_BIT = 20,\n\tREQ_F_BUFFER_SELECTED_BIT = 21,\n\tREQ_F_NO_FILE_TABLE_BIT = 22,\n\tREQ_F_QUEUE_TIMEOUT_BIT = 23,\n\tREQ_F_WORK_INITIALIZED_BIT = 24,\n\tREQ_F_TASK_PINNED_BIT = 25,\n\t__REQ_F_LAST_BIT = 26,\n};\n\nenum {\n\tREQ_F_FIXED_FILE = 1,\n\tREQ_F_IO_DRAIN = 2,\n\tREQ_F_LINK = 4,\n\tREQ_F_HARDLINK = 8,\n\tREQ_F_FORCE_ASYNC = 16,\n\tREQ_F_BUFFER_SELECT = 32,\n\tREQ_F_LINK_HEAD = 64,\n\tREQ_F_LINK_NEXT = 128,\n\tREQ_F_FAIL_LINK = 256,\n\tREQ_F_INFLIGHT = 512,\n\tREQ_F_CUR_POS = 1024,\n\tREQ_F_NOWAIT = 2048,\n\tREQ_F_LINK_TIMEOUT = 4096,\n\tREQ_F_TIMEOUT = 8192,\n\tREQ_F_ISREG = 16384,\n\tREQ_F_MUST_PUNT = 32768,\n\tREQ_F_TIMEOUT_NOSEQ = 65536,\n\tREQ_F_COMP_LOCKED = 131072,\n\tREQ_F_NEED_CLEANUP = 262144,\n\tREQ_F_OVERFLOW = 524288,\n\tREQ_F_POLLED = 1048576,\n\tREQ_F_BUFFER_SELECTED = 2097152,\n\tREQ_F_NO_FILE_TABLE = 4194304,\n\tREQ_F_QUEUE_TIMEOUT = 8388608,\n\tREQ_F_WORK_INITIALIZED = 16777216,\n\tREQ_F_TASK_PINNED = 33554432,\n};\n\nstruct async_poll {\n\tstruct io_poll_iocb poll;\n\tstruct io_poll_iocb *double_poll;\n\tstruct io_wq_work work;\n};\n\nstruct io_submit_state {\n\tstruct blk_plug plug;\n\tvoid *reqs[8];\n\tunsigned int free_reqs;\n\tstruct file *file;\n\tunsigned int fd;\n\tunsigned int has_refs;\n\tunsigned int used_refs;\n\tunsigned int ios_left;\n};\n\nstruct io_op_def {\n\tunsigned int async_ctx: 1;\n\tunsigned int needs_mm: 1;\n\tunsigned int needs_file: 1;\n\tunsigned int needs_file_no_error: 1;\n\tunsigned int hash_reg_file: 1;\n\tunsigned int unbound_nonreg_file: 1;\n\tunsigned int not_supported: 1;\n\tunsigned int file_table: 1;\n\tunsigned int needs_fs: 1;\n\tunsigned int pollin: 1;\n\tunsigned int pollout: 1;\n\tunsigned int buffer_select: 1;\n};\n\nstruct req_batch {\n\tvoid *reqs[8];\n\tint to_free;\n\tint need_iter;\n};\n\nstruct io_poll_table {\n\tstruct poll_table_struct pt;\n\tstruct io_kiocb *req;\n\tint error;\n};\n\nstruct io_wait_queue {\n\tstruct wait_queue_entry wq;\n\tstruct io_ring_ctx *ctx;\n\tunsigned int to_wait;\n\tunsigned int nr_timeouts;\n};\n\nstruct io_file_put {\n\tstruct list_head list;\n\tstruct file *file;\n};\n\nstruct io_wq_work_list {\n\tstruct io_wq_work_node *first;\n\tstruct io_wq_work_node *last;\n};\n\ntypedef bool work_cancel_fn(struct io_wq_work *, void *);\n\nenum {\n\tIO_WORKER_F_UP = 1,\n\tIO_WORKER_F_RUNNING = 2,\n\tIO_WORKER_F_FREE = 4,\n\tIO_WORKER_F_EXITING = 8,\n\tIO_WORKER_F_FIXED = 16,\n\tIO_WORKER_F_BOUND = 32,\n};\n\nenum {\n\tIO_WQ_BIT_EXIT = 0,\n\tIO_WQ_BIT_CANCEL = 1,\n\tIO_WQ_BIT_ERROR = 2,\n};\n\nenum {\n\tIO_WQE_FLAG_STALLED = 1,\n};\n\nstruct io_wqe;\n\nstruct io_worker {\n\trefcount_t ref;\n\tunsigned int flags;\n\tstruct hlist_nulls_node nulls_node;\n\tstruct list_head all_list;\n\tstruct task_struct *task;\n\tstruct io_wqe *wqe;\n\tstruct io_wq_work *cur_work;\n\tspinlock_t lock;\n\tstruct callback_head rcu;\n\tstruct mm_struct *mm;\n\tconst struct cred *cur_creds;\n\tconst struct cred *saved_creds;\n\tstruct files_struct *restore_files;\n\tstruct fs_struct *restore_fs;\n};\n\nstruct io_wqe_acct {\n\tunsigned int nr_workers;\n\tunsigned int max_workers;\n\tatomic_t nr_running;\n};\n\nstruct io_wq___2;\n\nstruct io_wqe {\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct io_wq_work_list work_list;\n\t\tlong unsigned int hash_map;\n\t\tunsigned int flags;\n\t\tlong: 32;\n\t\tlong: 64;\n\t\tlong: 64;\n\t\tlong: 64;\n\t};\n\tint node;\n\tstruct io_wqe_acct acct[2];\n\tstruct hlist_nulls_head free_list;\n\tstruct list_head all_list;\n\tstruct io_wq___2 *wq;\n\tstruct io_wq_work *hash_tail[64];\n};\n\nenum {\n\tIO_WQ_ACCT_BOUND = 0,\n\tIO_WQ_ACCT_UNBOUND = 1,\n};\n\nstruct io_wq___2 {\n\tstruct io_wqe **wqes;\n\tlong unsigned int state;\n\tfree_work_fn *free_work;\n\tio_wq_work_fn *do_work;\n\tstruct task_struct *manager;\n\tstruct user_struct *user;\n\trefcount_t refs;\n\tstruct completion done;\n\trefcount_t use_refs;\n};\n\nstruct io_cb_cancel_data {\n\twork_cancel_fn *fn;\n\tvoid *data;\n\tint nr_running;\n\tint nr_pending;\n\tbool cancel_all;\n};\n\nstruct flock64 {\n\tshort int l_type;\n\tshort int l_whence;\n\t__kernel_loff_t l_start;\n\t__kernel_loff_t l_len;\n\t__kernel_pid_t l_pid;\n};\n\nstruct trace_event_raw_locks_get_lock_context {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tunsigned char type;\n\tstruct file_lock_context *ctx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lock {\n\tstruct trace_entry ent;\n\tstruct file_lock *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock *fl_blocker;\n\tfl_owner_t fl_owner;\n\tunsigned int fl_pid;\n\tunsigned int fl_flags;\n\tunsigned char fl_type;\n\tloff_t fl_start;\n\tloff_t fl_end;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_filelock_lease {\n\tstruct trace_entry ent;\n\tstruct file_lock *fl;\n\tlong unsigned int i_ino;\n\tdev_t s_dev;\n\tstruct file_lock *fl_blocker;\n\tfl_owner_t fl_owner;\n\tunsigned int fl_flags;\n\tunsigned char fl_type;\n\tlong unsigned int fl_break_time;\n\tlong unsigned int fl_downgrade_time;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_generic_add_lease {\n\tstruct trace_entry ent;\n\tlong unsigned int i_ino;\n\tint wcount;\n\tint rcount;\n\tint icount;\n\tdev_t s_dev;\n\tfl_owner_t fl_owner;\n\tunsigned int fl_flags;\n\tunsigned char fl_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_leases_conflict {\n\tstruct trace_entry ent;\n\tvoid *lease;\n\tvoid *breaker;\n\tunsigned int l_fl_flags;\n\tunsigned int b_fl_flags;\n\tunsigned char l_fl_type;\n\tunsigned char b_fl_type;\n\tbool conflict;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_locks_get_lock_context {};\n\nstruct trace_event_data_offsets_filelock_lock {};\n\nstruct trace_event_data_offsets_filelock_lease {};\n\nstruct trace_event_data_offsets_generic_add_lease {};\n\nstruct trace_event_data_offsets_leases_conflict {};\n\ntypedef void (*btf_trace_locks_get_lock_context)(void *, struct inode *, int, struct file_lock_context *);\n\ntypedef void (*btf_trace_posix_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_fcntl_setlk)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_locks_remove_posix)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_flock_lock_inode)(void *, struct inode *, struct file_lock *, int);\n\ntypedef void (*btf_trace_break_lease_noblock)(void *, struct inode *, struct file_lock *);\n\ntypedef void (*btf_trace_break_lease_block)(void *, struct inode *, struct file_lock *);\n\ntypedef void (*btf_trace_break_lease_unblock)(void *, struct inode *, struct file_lock *);\n\ntypedef void (*btf_trace_generic_delete_lease)(void *, struct inode *, struct file_lock *);\n\ntypedef void (*btf_trace_time_out_leases)(void *, struct inode *, struct file_lock *);\n\ntypedef void (*btf_trace_generic_add_lease)(void *, struct inode *, struct file_lock *);\n\ntypedef void (*btf_trace_leases_conflict)(void *, bool, struct file_lock *, struct file_lock *);\n\nstruct file_lock_list_struct {\n\tspinlock_t lock;\n\tstruct hlist_head hlist;\n};\n\nstruct locks_iterator {\n\tint li_cpu;\n\tloff_t li_pos;\n};\n\nstruct nfs_string {\n\tunsigned int len;\n\tconst char *data;\n};\n\nstruct nfs4_mount_data {\n\tint version;\n\tint flags;\n\tint rsize;\n\tint wsize;\n\tint timeo;\n\tint retrans;\n\tint acregmin;\n\tint acregmax;\n\tint acdirmin;\n\tint acdirmax;\n\tstruct nfs_string client_addr;\n\tstruct nfs_string mnt_path;\n\tstruct nfs_string hostname;\n\tunsigned int host_addrlen;\n\tstruct sockaddr *host_addr;\n\tint proto;\n\tint auth_flavourlen;\n\tint *auth_flavours;\n};\n\nstruct compat_nfs_string {\n\tcompat_uint_t len;\n\tcompat_uptr_t data;\n};\n\nstruct compat_nfs4_mount_data_v1 {\n\tcompat_int_t version;\n\tcompat_int_t flags;\n\tcompat_int_t rsize;\n\tcompat_int_t wsize;\n\tcompat_int_t timeo;\n\tcompat_int_t retrans;\n\tcompat_int_t acregmin;\n\tcompat_int_t acregmax;\n\tcompat_int_t acdirmin;\n\tcompat_int_t acdirmax;\n\tstruct compat_nfs_string client_addr;\n\tstruct compat_nfs_string mnt_path;\n\tstruct compat_nfs_string hostname;\n\tcompat_uint_t host_addrlen;\n\tcompat_uptr_t host_addr;\n\tcompat_int_t proto;\n\tcompat_int_t auth_flavourlen;\n\tcompat_uptr_t auth_flavours;\n};\n\nenum {\n\tVERBOSE_STATUS = 1,\n};\n\nenum {\n\tEnabled = 0,\n\tMagic = 1,\n};\n\ntypedef struct {\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tint offset;\n\tint size;\n\tchar *magic;\n\tchar *mask;\n\tconst char *interpreter;\n\tchar *name;\n\tstruct dentry *dentry;\n\tstruct file *interp_file;\n} Node;\n\ntypedef unsigned int __kernel_uid_t;\n\ntypedef unsigned int __kernel_gid_t;\n\nstruct elf_prpsinfo {\n\tchar pr_state;\n\tchar pr_sname;\n\tchar pr_zomb;\n\tchar pr_nice;\n\tlong unsigned int pr_flag;\n\t__kernel_uid_t pr_uid;\n\t__kernel_gid_t pr_gid;\n\tpid_t pr_pid;\n\tpid_t pr_ppid;\n\tpid_t pr_pgrp;\n\tpid_t pr_sid;\n\tchar pr_fname[16];\n\tchar pr_psargs[80];\n};\n\nstruct arch_elf_state {};\n\nstruct memelfnote {\n\tconst char *name;\n\tint type;\n\tunsigned int datasz;\n\tvoid *data;\n};\n\nstruct elf_thread_core_info {\n\tstruct elf_thread_core_info *next;\n\tstruct task_struct *task;\n\tstruct elf_prstatus prstatus;\n\tstruct memelfnote notes[0];\n};\n\nstruct elf_note_info {\n\tstruct elf_thread_core_info *thread;\n\tstruct memelfnote psinfo;\n\tstruct memelfnote signote;\n\tstruct memelfnote auxv;\n\tstruct memelfnote files;\n\tsiginfo_t csigdata;\n\tsize_t size;\n\tint thread_notes;\n};\n\nstruct elf32_shdr {\n\tElf32_Word sh_name;\n\tElf32_Word sh_type;\n\tElf32_Word sh_flags;\n\tElf32_Addr sh_addr;\n\tElf32_Off sh_offset;\n\tElf32_Word sh_size;\n\tElf32_Word sh_link;\n\tElf32_Word sh_info;\n\tElf32_Word sh_addralign;\n\tElf32_Word sh_entsize;\n};\n\ntypedef struct user_regs_struct compat_elf_gregset_t;\n\nstruct compat_elf_siginfo {\n\tcompat_int_t si_signo;\n\tcompat_int_t si_code;\n\tcompat_int_t si_errno;\n};\n\nstruct compat_elf_prstatus {\n\tstruct compat_elf_siginfo pr_info;\n\tshort int pr_cursig;\n\tcompat_ulong_t pr_sigpend;\n\tcompat_ulong_t pr_sighold;\n\tcompat_pid_t pr_pid;\n\tcompat_pid_t pr_ppid;\n\tcompat_pid_t pr_pgrp;\n\tcompat_pid_t pr_sid;\n\tstruct old_timeval32 pr_utime;\n\tstruct old_timeval32 pr_stime;\n\tstruct old_timeval32 pr_cutime;\n\tstruct old_timeval32 pr_cstime;\n\tcompat_elf_gregset_t pr_reg;\n\tcompat_int_t pr_fpvalid;\n};\n\nstruct compat_elf_prpsinfo {\n\tchar pr_state;\n\tchar pr_sname;\n\tchar pr_zomb;\n\tchar pr_nice;\n\tcompat_ulong_t pr_flag;\n\t__compat_uid_t pr_uid;\n\t__compat_gid_t pr_gid;\n\tcompat_pid_t pr_pid;\n\tcompat_pid_t pr_ppid;\n\tcompat_pid_t pr_pgrp;\n\tcompat_pid_t pr_sid;\n\tchar pr_fname[16];\n\tchar pr_psargs[80];\n};\n\nstruct elf_thread_core_info___2 {\n\tstruct elf_thread_core_info___2 *next;\n\tstruct task_struct *task;\n\tstruct compat_elf_prstatus prstatus;\n\tstruct memelfnote notes[0];\n};\n\nstruct elf_note_info___2 {\n\tstruct elf_thread_core_info___2 *thread;\n\tstruct memelfnote psinfo;\n\tstruct memelfnote signote;\n\tstruct memelfnote auxv;\n\tstruct memelfnote files;\n\tcompat_siginfo_t csigdata;\n\tsize_t size;\n\tint thread_notes;\n};\n\nstruct mb_cache_entry {\n\tstruct list_head e_list;\n\tstruct hlist_bl_node e_hash_list;\n\tatomic_t e_refcnt;\n\tu32 e_key;\n\tu32 e_referenced: 1;\n\tu32 e_reusable: 1;\n\tu64 e_value;\n};\n\nstruct mb_cache {\n\tstruct hlist_bl_head *c_hash;\n\tint c_bucket_bits;\n\tlong unsigned int c_max_entries;\n\tspinlock_t c_list_lock;\n\tstruct list_head c_list;\n\tlong unsigned int c_entry_count;\n\tstruct shrinker c_shrink;\n\tstruct work_struct c_shrink_work;\n};\n\nstruct posix_acl_xattr_entry {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n};\n\nstruct posix_acl_xattr_header {\n\t__le32 a_version;\n};\n\nstruct xdr_array2_desc;\n\ntypedef int (*xdr_xcode_elem_t)(struct xdr_array2_desc *, void *);\n\nstruct xdr_array2_desc {\n\tunsigned int elem_size;\n\tunsigned int array_len;\n\tunsigned int array_maxlen;\n\txdr_xcode_elem_t xcode;\n};\n\nstruct nfsacl_encode_desc {\n\tstruct xdr_array2_desc desc;\n\tunsigned int count;\n\tstruct posix_acl *acl;\n\tint typeflag;\n\tkuid_t uid;\n\tkgid_t gid;\n};\n\nstruct nfsacl_simple_acl {\n\tstruct posix_acl acl;\n\tstruct posix_acl_entry ace[4];\n};\n\nstruct nfsacl_decode_desc {\n\tstruct xdr_array2_desc desc;\n\tunsigned int count;\n\tstruct posix_acl *acl;\n};\n\nstruct lock_manager {\n\tstruct list_head list;\n\tbool block_opens;\n};\n\nstruct core_name {\n\tchar *corename;\n\tint used;\n\tint size;\n};\n\nstruct trace_event_raw_iomap_readpage_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tint nr_pages;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_range_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tloff_t size;\n\tlong unsigned int offset;\n\tunsigned int length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tu64 addr;\n\tloff_t offset;\n\tu64 length;\n\tu16 type;\n\tu16 flags;\n\tdev_t bdev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iomap_apply {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tloff_t pos;\n\tloff_t length;\n\tunsigned int flags;\n\tconst void *ops;\n\tvoid *actor;\n\tlong unsigned int caller;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_iomap_readpage_class {};\n\nstruct trace_event_data_offsets_iomap_range_class {};\n\nstruct trace_event_data_offsets_iomap_class {};\n\nstruct trace_event_data_offsets_iomap_apply {};\n\ntypedef void (*btf_trace_iomap_readpage)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_readahead)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_iomap_writepage)(void *, struct inode *, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_iomap_releasepage)(void *, struct inode *, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_iomap_invalidatepage)(void *, struct inode *, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_iomap_apply_dstmap)(void *, struct inode *, struct iomap___2 *);\n\ntypedef void (*btf_trace_iomap_apply_srcmap)(void *, struct inode *, struct iomap___2 *);\n\ntypedef void (*btf_trace_iomap_apply)(void *, struct inode *, loff_t, loff_t, unsigned int, const void *, void *, long unsigned int);\n\nstruct iomap_ops {\n\tint (*iomap_begin)(struct inode *, loff_t, loff_t, unsigned int, struct iomap___2 *, struct iomap___2 *);\n\tint (*iomap_end)(struct inode *, loff_t, loff_t, ssize_t, unsigned int, struct iomap___2 *);\n};\n\ntypedef loff_t (*iomap_actor_t)(struct inode *, loff_t, loff_t, void *, struct iomap___2 *, struct iomap___2 *);\n\nstruct iomap_ioend {\n\tstruct list_head io_list;\n\tu16 io_type;\n\tu16 io_flags;\n\tstruct inode *io_inode;\n\tsize_t io_size;\n\tloff_t io_offset;\n\tvoid *io_private;\n\tstruct bio *io_bio;\n\tstruct bio io_inline_bio;\n};\n\nstruct iomap_writepage_ctx;\n\nstruct iomap_writeback_ops {\n\tint (*map_blocks)(struct iomap_writepage_ctx *, struct inode *, loff_t);\n\tint (*prepare_ioend)(struct iomap_ioend *, int);\n\tvoid (*discard_page)(struct page *);\n};\n\nstruct iomap_writepage_ctx {\n\tstruct iomap___2 iomap;\n\tstruct iomap_ioend *ioend;\n\tconst struct iomap_writeback_ops *ops;\n};\n\nstruct iomap_page {\n\tatomic_t read_count;\n\tatomic_t write_count;\n\tspinlock_t uptodate_lock;\n\tlong unsigned int uptodate[1];\n};\n\nstruct iomap_readpage_ctx {\n\tstruct page *cur_page;\n\tbool cur_page_in_bio;\n\tstruct bio *bio;\n\tstruct readahead_control *rac;\n};\n\nenum {\n\tIOMAP_WRITE_F_UNSHARE = 1,\n};\n\nstruct iomap_dio_ops {\n\tint (*end_io)(struct kiocb *, ssize_t, int, unsigned int);\n\tblk_qc_t (*submit_io)(struct inode *, struct iomap___2 *, struct bio *, loff_t);\n};\n\nstruct iomap_dio {\n\tstruct kiocb *iocb;\n\tconst struct iomap_dio_ops *dops;\n\tloff_t i_size;\n\tloff_t size;\n\tatomic_t ref;\n\tunsigned int flags;\n\tint error;\n\tbool wait_for_completion;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iov_iter *iter;\n\t\t\tstruct task_struct *waiter;\n\t\t\tstruct request_queue *last_queue;\n\t\t\tblk_qc_t cookie;\n\t\t} submit;\n\t\tstruct {\n\t\t\tstruct work_struct work;\n\t\t} aio;\n\t};\n};\n\nstruct fiemap_ctx {\n\tstruct fiemap_extent_info *fi;\n\tstruct iomap___2 prev;\n};\n\nstruct iomap_swapfile_info {\n\tstruct iomap___2 iomap;\n\tstruct swap_info_struct *sis;\n\tuint64_t lowest_ppage;\n\tuint64_t highest_ppage;\n\tlong unsigned int nr_pages;\n\tint nr_extents;\n};\n\nenum {\n\tQIF_BLIMITS_B = 0,\n\tQIF_SPACE_B = 1,\n\tQIF_ILIMITS_B = 2,\n\tQIF_INODES_B = 3,\n\tQIF_BTIME_B = 4,\n\tQIF_ITIME_B = 5,\n};\n\nenum {\n\tDQF_ROOT_SQUASH_B = 0,\n\tDQF_SYS_FILE_B = 16,\n\tDQF_PRIVATE = 17,\n};\n\ntypedef __kernel_uid32_t qid_t;\n\nenum {\n\tDQF_INFO_DIRTY_B = 17,\n};\n\nenum {\n\tDQST_LOOKUPS = 0,\n\tDQST_DROPS = 1,\n\tDQST_READS = 2,\n\tDQST_WRITES = 3,\n\tDQST_CACHE_HITS = 4,\n\tDQST_ALLOC_DQUOTS = 5,\n\tDQST_FREE_DQUOTS = 6,\n\tDQST_SYNCS = 7,\n\t_DQST_DQSTAT_LAST = 8,\n};\n\nenum {\n\t_DQUOT_USAGE_ENABLED = 0,\n\t_DQUOT_LIMITS_ENABLED = 1,\n\t_DQUOT_SUSPENDED = 2,\n\t_DQUOT_STATE_FLAGS = 3,\n};\n\nstruct quota_module_name {\n\tint qm_fmt_id;\n\tchar *qm_mod_name;\n};\n\nstruct dquot_warn {\n\tstruct super_block *w_sb;\n\tstruct kqid w_dq_id;\n\tshort int w_type;\n};\n\nstruct qtree_fmt_operations {\n\tvoid (*mem2disk_dqblk)(void *, struct dquot *);\n\tvoid (*disk2mem_dqblk)(struct dquot *, void *);\n\tint (*is_id)(void *, struct dquot *);\n};\n\nstruct qtree_mem_dqinfo {\n\tstruct super_block *dqi_sb;\n\tint dqi_type;\n\tunsigned int dqi_blocks;\n\tunsigned int dqi_free_blk;\n\tunsigned int dqi_free_entry;\n\tunsigned int dqi_blocksize_bits;\n\tunsigned int dqi_entry_size;\n\tunsigned int dqi_usable_bs;\n\tunsigned int dqi_qtree_depth;\n\tconst struct qtree_fmt_operations *dqi_ops;\n};\n\nstruct v2_disk_dqheader {\n\t__le32 dqh_magic;\n\t__le32 dqh_version;\n};\n\nstruct v2r0_disk_dqblk {\n\t__le32 dqb_id;\n\t__le32 dqb_ihardlimit;\n\t__le32 dqb_isoftlimit;\n\t__le32 dqb_curinodes;\n\t__le32 dqb_bhardlimit;\n\t__le32 dqb_bsoftlimit;\n\t__le64 dqb_curspace;\n\t__le64 dqb_btime;\n\t__le64 dqb_itime;\n};\n\nstruct v2r1_disk_dqblk {\n\t__le32 dqb_id;\n\t__le32 dqb_pad;\n\t__le64 dqb_ihardlimit;\n\t__le64 dqb_isoftlimit;\n\t__le64 dqb_curinodes;\n\t__le64 dqb_bhardlimit;\n\t__le64 dqb_bsoftlimit;\n\t__le64 dqb_curspace;\n\t__le64 dqb_btime;\n\t__le64 dqb_itime;\n};\n\nstruct v2_disk_dqinfo {\n\t__le32 dqi_bgrace;\n\t__le32 dqi_igrace;\n\t__le32 dqi_flags;\n\t__le32 dqi_blocks;\n\t__le32 dqi_free_blk;\n\t__le32 dqi_free_entry;\n};\n\nstruct qt_disk_dqdbheader {\n\t__le32 dqdh_next_free;\n\t__le32 dqdh_prev_free;\n\t__le16 dqdh_entries;\n\t__le16 dqdh_pad1;\n\t__le32 dqdh_pad2;\n};\n\nstruct fs_disk_quota {\n\t__s8 d_version;\n\t__s8 d_flags;\n\t__u16 d_fieldmask;\n\t__u32 d_id;\n\t__u64 d_blk_hardlimit;\n\t__u64 d_blk_softlimit;\n\t__u64 d_ino_hardlimit;\n\t__u64 d_ino_softlimit;\n\t__u64 d_bcount;\n\t__u64 d_icount;\n\t__s32 d_itimer;\n\t__s32 d_btimer;\n\t__u16 d_iwarns;\n\t__u16 d_bwarns;\n\t__s32 d_padding2;\n\t__u64 d_rtb_hardlimit;\n\t__u64 d_rtb_softlimit;\n\t__u64 d_rtbcount;\n\t__s32 d_rtbtimer;\n\t__u16 d_rtbwarns;\n\t__s16 d_padding3;\n\tchar d_padding4[8];\n};\n\nstruct fs_qfilestat {\n\t__u64 qfs_ino;\n\t__u64 qfs_nblks;\n\t__u32 qfs_nextents;\n};\n\ntypedef struct fs_qfilestat fs_qfilestat_t;\n\nstruct fs_quota_stat {\n\t__s8 qs_version;\n\t__u16 qs_flags;\n\t__s8 qs_pad;\n\tfs_qfilestat_t qs_uquota;\n\tfs_qfilestat_t qs_gquota;\n\t__u32 qs_incoredqs;\n\t__s32 qs_btimelimit;\n\t__s32 qs_itimelimit;\n\t__s32 qs_rtbtimelimit;\n\t__u16 qs_bwarnlimit;\n\t__u16 qs_iwarnlimit;\n};\n\nstruct fs_qfilestatv {\n\t__u64 qfs_ino;\n\t__u64 qfs_nblks;\n\t__u32 qfs_nextents;\n\t__u32 qfs_pad;\n};\n\nstruct fs_quota_statv {\n\t__s8 qs_version;\n\t__u8 qs_pad1;\n\t__u16 qs_flags;\n\t__u32 qs_incoredqs;\n\tstruct fs_qfilestatv qs_uquota;\n\tstruct fs_qfilestatv qs_gquota;\n\tstruct fs_qfilestatv qs_pquota;\n\t__s32 qs_btimelimit;\n\t__s32 qs_itimelimit;\n\t__s32 qs_rtbtimelimit;\n\t__u16 qs_bwarnlimit;\n\t__u16 qs_iwarnlimit;\n\t__u64 qs_pad2[8];\n};\n\nstruct if_dqblk {\n\t__u64 dqb_bhardlimit;\n\t__u64 dqb_bsoftlimit;\n\t__u64 dqb_curspace;\n\t__u64 dqb_ihardlimit;\n\t__u64 dqb_isoftlimit;\n\t__u64 dqb_curinodes;\n\t__u64 dqb_btime;\n\t__u64 dqb_itime;\n\t__u32 dqb_valid;\n};\n\nstruct if_nextdqblk {\n\t__u64 dqb_bhardlimit;\n\t__u64 dqb_bsoftlimit;\n\t__u64 dqb_curspace;\n\t__u64 dqb_ihardlimit;\n\t__u64 dqb_isoftlimit;\n\t__u64 dqb_curinodes;\n\t__u64 dqb_btime;\n\t__u64 dqb_itime;\n\t__u32 dqb_valid;\n\t__u32 dqb_id;\n};\n\nstruct if_dqinfo {\n\t__u64 dqi_bgrace;\n\t__u64 dqi_igrace;\n\t__u32 dqi_flags;\n\t__u32 dqi_valid;\n};\n\nstruct compat_if_dqblk {\n\tcompat_u64 dqb_bhardlimit;\n\tcompat_u64 dqb_bsoftlimit;\n\tcompat_u64 dqb_curspace;\n\tcompat_u64 dqb_ihardlimit;\n\tcompat_u64 dqb_isoftlimit;\n\tcompat_u64 dqb_curinodes;\n\tcompat_u64 dqb_btime;\n\tcompat_u64 dqb_itime;\n\tcompat_uint_t dqb_valid;\n} __attribute__((packed));\n\nstruct compat_fs_qfilestat {\n\tcompat_u64 dqb_bhardlimit;\n\tcompat_u64 qfs_nblks;\n\tcompat_uint_t qfs_nextents;\n} __attribute__((packed));\n\nstruct compat_fs_quota_stat {\n\t__s8 qs_version;\n\tchar: 8;\n\t__u16 qs_flags;\n\t__s8 qs_pad;\n\tint: 24;\n\tstruct compat_fs_qfilestat qs_uquota;\n\tstruct compat_fs_qfilestat qs_gquota;\n\tcompat_uint_t qs_incoredqs;\n\tcompat_int_t qs_btimelimit;\n\tcompat_int_t qs_itimelimit;\n\tcompat_int_t qs_rtbtimelimit;\n\t__u16 qs_bwarnlimit;\n\t__u16 qs_iwarnlimit;\n} __attribute__((packed));\n\nenum {\n\tQUOTA_NL_C_UNSPEC = 0,\n\tQUOTA_NL_C_WARNING = 1,\n\t__QUOTA_NL_C_MAX = 2,\n};\n\nenum {\n\tQUOTA_NL_A_UNSPEC = 0,\n\tQUOTA_NL_A_QTYPE = 1,\n\tQUOTA_NL_A_EXCESS_ID = 2,\n\tQUOTA_NL_A_WARNING = 3,\n\tQUOTA_NL_A_DEV_MAJOR = 4,\n\tQUOTA_NL_A_DEV_MINOR = 5,\n\tQUOTA_NL_A_CAUSED_ID = 6,\n\tQUOTA_NL_A_PAD = 7,\n\t__QUOTA_NL_A_MAX = 8,\n};\n\nstruct proc_maps_private {\n\tstruct inode *inode;\n\tstruct task_struct *task;\n\tstruct mm_struct *mm;\n\tstruct vm_area_struct *tail_vma;\n\tstruct mempolicy *task_mempolicy;\n};\n\nstruct mem_size_stats {\n\tlong unsigned int resident;\n\tlong unsigned int shared_clean;\n\tlong unsigned int shared_dirty;\n\tlong unsigned int private_clean;\n\tlong unsigned int private_dirty;\n\tlong unsigned int referenced;\n\tlong unsigned int anonymous;\n\tlong unsigned int lazyfree;\n\tlong unsigned int anonymous_thp;\n\tlong unsigned int shmem_thp;\n\tlong unsigned int file_thp;\n\tlong unsigned int swap;\n\tlong unsigned int shared_hugetlb;\n\tlong unsigned int private_hugetlb;\n\tu64 pss;\n\tu64 pss_anon;\n\tu64 pss_file;\n\tu64 pss_shmem;\n\tu64 pss_locked;\n\tu64 swap_pss;\n\tbool check_shmem_swap;\n};\n\nenum clear_refs_types {\n\tCLEAR_REFS_ALL = 1,\n\tCLEAR_REFS_ANON = 2,\n\tCLEAR_REFS_MAPPED = 3,\n\tCLEAR_REFS_SOFT_DIRTY = 4,\n\tCLEAR_REFS_MM_HIWATER_RSS = 5,\n\tCLEAR_REFS_LAST = 6,\n};\n\nstruct clear_refs_private {\n\tenum clear_refs_types type;\n};\n\ntypedef struct {\n\tu64 pme;\n} pagemap_entry_t;\n\nstruct pagemapread {\n\tint pos;\n\tint len;\n\tpagemap_entry_t *buffer;\n\tbool show_pfn;\n};\n\nstruct numa_maps {\n\tlong unsigned int pages;\n\tlong unsigned int anon;\n\tlong unsigned int active;\n\tlong unsigned int writeback;\n\tlong unsigned int mapcount_max;\n\tlong unsigned int dirty;\n\tlong unsigned int swapcache;\n\tlong unsigned int node[64];\n};\n\nstruct numa_maps_private {\n\tstruct proc_maps_private proc_maps;\n\tstruct numa_maps md;\n};\n\nstruct pde_opener {\n\tstruct list_head lh;\n\tstruct file *file;\n\tbool closing;\n\tstruct completion *c;\n};\n\nenum {\n\tBIAS = 2147483648,\n};\n\nstruct proc_fs_context {\n\tstruct pid_namespace *pid_ns;\n\tunsigned int mask;\n\tenum proc_hidepid hidepid;\n\tint gid;\n\tenum proc_pidonly pidonly;\n};\n\nenum proc_param {\n\tOpt_gid___2 = 0,\n\tOpt_hidepid = 1,\n\tOpt_subset = 2,\n};\n\nstruct genradix_root;\n\nstruct __genradix {\n\tstruct genradix_root *root;\n};\n\nstruct syscall_info {\n\t__u64 sp;\n\tstruct seccomp_data data;\n};\n\ntypedef struct dentry *instantiate_t(struct dentry *, struct task_struct *, const void *);\n\nstruct pid_entry {\n\tconst char *name;\n\tunsigned int len;\n\tumode_t mode;\n\tconst struct inode_operations *iop;\n\tconst struct file_operations *fop;\n\tunion proc_op op;\n};\n\nstruct limit_names {\n\tconst char *name;\n\tconst char *unit;\n};\n\nstruct map_files_info {\n\tlong unsigned int start;\n\tlong unsigned int end;\n\tfmode_t mode;\n};\n\nstruct tgid_iter {\n\tunsigned int tgid;\n\tstruct task_struct *task;\n};\n\nstruct fd_data {\n\tfmode_t mode;\n\tunsigned int fd;\n};\n\nstruct sysctl_alias {\n\tconst char *kernel_param;\n\tconst char *sysctl_param;\n};\n\nstruct seq_net_private {\n\tstruct net *net;\n};\n\nstruct vmcore {\n\tstruct list_head list;\n\tlong long unsigned int paddr;\n\tlong long unsigned int size;\n\tloff_t offset;\n};\n\ntypedef struct elf64_note Elf64_Nhdr;\n\nstruct kernfs_iattrs {\n\tkuid_t ia_uid;\n\tkgid_t ia_gid;\n\tstruct timespec64 ia_atime;\n\tstruct timespec64 ia_mtime;\n\tstruct timespec64 ia_ctime;\n\tstruct simple_xattrs xattrs;\n\tatomic_t nr_user_xattrs;\n\tatomic_t user_xattr_size;\n};\n\nstruct kernfs_super_info {\n\tstruct super_block *sb;\n\tstruct kernfs_root *root;\n\tconst void *ns;\n\tstruct list_head node;\n};\n\nenum kernfs_node_flag {\n\tKERNFS_ACTIVATED = 16,\n\tKERNFS_NS = 32,\n\tKERNFS_HAS_SEQ_SHOW = 64,\n\tKERNFS_HAS_MMAP = 128,\n\tKERNFS_LOCKDEP = 256,\n\tKERNFS_SUICIDAL = 1024,\n\tKERNFS_SUICIDED = 2048,\n\tKERNFS_EMPTY_DIR = 4096,\n\tKERNFS_HAS_RELEASE = 8192,\n};\n\nstruct kernfs_open_node {\n\tatomic_t refcnt;\n\tatomic_t event;\n\twait_queue_head_t poll;\n\tstruct list_head files;\n};\n\nstruct pts_mount_opts {\n\tint setuid;\n\tint setgid;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n\tumode_t ptmxmode;\n\tint reserve;\n\tint max;\n};\n\nenum {\n\tOpt_uid___2 = 0,\n\tOpt_gid___3 = 1,\n\tOpt_mode___2 = 2,\n\tOpt_ptmxmode = 3,\n\tOpt_newinstance = 4,\n\tOpt_max = 5,\n\tOpt_err = 6,\n};\n\nstruct pts_fs_info {\n\tstruct ida allocated_ptys;\n\tstruct pts_mount_opts mount_opts;\n\tstruct super_block *sb;\n\tstruct dentry *ptmx_dentry;\n};\n\nstruct dcookie_struct {\n\tstruct path path;\n\tstruct list_head hash_list;\n};\n\nstruct dcookie_user {\n\tstruct list_head next;\n};\n\ntypedef unsigned int tid_t;\n\nstruct transaction_chp_stats_s {\n\tlong unsigned int cs_chp_time;\n\t__u32 cs_forced_to_close;\n\t__u32 cs_written;\n\t__u32 cs_dropped;\n};\n\nstruct journal_s;\n\ntypedef struct journal_s journal_t;\n\nstruct journal_head;\n\nstruct transaction_s;\n\ntypedef struct transaction_s transaction_t;\n\nstruct transaction_s {\n\tjournal_t *t_journal;\n\ttid_t t_tid;\n\tenum {\n\t\tT_RUNNING = 0,\n\t\tT_LOCKED = 1,\n\t\tT_SWITCH = 2,\n\t\tT_FLUSH = 3,\n\t\tT_COMMIT = 4,\n\t\tT_COMMIT_DFLUSH = 5,\n\t\tT_COMMIT_JFLUSH = 6,\n\t\tT_COMMIT_CALLBACK = 7,\n\t\tT_FINISHED = 8,\n\t} t_state;\n\tlong unsigned int t_log_start;\n\tint t_nr_buffers;\n\tstruct journal_head *t_reserved_list;\n\tstruct journal_head *t_buffers;\n\tstruct journal_head *t_forget;\n\tstruct journal_head *t_checkpoint_list;\n\tstruct journal_head *t_checkpoint_io_list;\n\tstruct journal_head *t_shadow_list;\n\tstruct list_head t_inode_list;\n\tspinlock_t t_handle_lock;\n\tlong unsigned int t_max_wait;\n\tlong unsigned int t_start;\n\tlong unsigned int t_requested;\n\tstruct transaction_chp_stats_s t_chp_stats;\n\tatomic_t t_updates;\n\tatomic_t t_outstanding_credits;\n\tatomic_t t_outstanding_revokes;\n\tatomic_t t_handle_count;\n\ttransaction_t *t_cpnext;\n\ttransaction_t *t_cpprev;\n\tlong unsigned int t_expires;\n\tktime_t t_start_time;\n\tunsigned int t_synchronous_commit: 1;\n\tint t_need_data_flush;\n\tstruct list_head t_private_list;\n};\n\nstruct jbd2_buffer_trigger_type;\n\nstruct journal_head {\n\tstruct buffer_head *b_bh;\n\tspinlock_t b_state_lock;\n\tint b_jcount;\n\tunsigned int b_jlist;\n\tunsigned int b_modified;\n\tchar *b_frozen_data;\n\tchar *b_committed_data;\n\ttransaction_t *b_transaction;\n\ttransaction_t *b_next_transaction;\n\tstruct journal_head *b_tnext;\n\tstruct journal_head *b_tprev;\n\ttransaction_t *b_cp_transaction;\n\tstruct journal_head *b_cpnext;\n\tstruct journal_head *b_cpprev;\n\tstruct jbd2_buffer_trigger_type *b_triggers;\n\tstruct jbd2_buffer_trigger_type *b_frozen_triggers;\n};\n\nstruct jbd2_buffer_trigger_type {\n\tvoid (*t_frozen)(struct jbd2_buffer_trigger_type *, struct buffer_head *, void *, size_t);\n\tvoid (*t_abort)(struct jbd2_buffer_trigger_type *, struct buffer_head *);\n};\n\nstruct crypto_alg;\n\nstruct crypto_tfm {\n\tu32 crt_flags;\n\tvoid (*exit)(struct crypto_tfm *);\n\tstruct crypto_alg *__crt_alg;\n\tvoid *__crt_ctx[0];\n};\n\nstruct cipher_alg {\n\tunsigned int cia_min_keysize;\n\tunsigned int cia_max_keysize;\n\tint (*cia_setkey)(struct crypto_tfm *, const u8 *, unsigned int);\n\tvoid (*cia_encrypt)(struct crypto_tfm *, u8 *, const u8 *);\n\tvoid (*cia_decrypt)(struct crypto_tfm *, u8 *, const u8 *);\n};\n\nstruct compress_alg {\n\tint (*coa_compress)(struct crypto_tfm *, const u8 *, unsigned int, u8 *, unsigned int *);\n\tint (*coa_decompress)(struct crypto_tfm *, const u8 *, unsigned int, u8 *, unsigned int *);\n};\n\nstruct crypto_type;\n\nstruct crypto_alg {\n\tstruct list_head cra_list;\n\tstruct list_head cra_users;\n\tu32 cra_flags;\n\tunsigned int cra_blocksize;\n\tunsigned int cra_ctxsize;\n\tunsigned int cra_alignmask;\n\tint cra_priority;\n\trefcount_t cra_refcnt;\n\tchar cra_name[128];\n\tchar cra_driver_name[128];\n\tconst struct crypto_type *cra_type;\n\tunion {\n\t\tstruct cipher_alg cipher;\n\t\tstruct compress_alg compress;\n\t} cra_u;\n\tint (*cra_init)(struct crypto_tfm *);\n\tvoid (*cra_exit)(struct crypto_tfm *);\n\tvoid (*cra_destroy)(struct crypto_alg *);\n\tstruct module *cra_module;\n};\n\nstruct crypto_instance;\n\nstruct crypto_type {\n\tunsigned int (*ctxsize)(struct crypto_alg *, u32, u32);\n\tunsigned int (*extsize)(struct crypto_alg *);\n\tint (*init)(struct crypto_tfm *, u32, u32);\n\tint (*init_tfm)(struct crypto_tfm *);\n\tvoid (*show)(struct seq_file *, struct crypto_alg *);\n\tint (*report)(struct sk_buff *, struct crypto_alg *);\n\tvoid (*free)(struct crypto_instance *);\n\tunsigned int type;\n\tunsigned int maskclear;\n\tunsigned int maskset;\n\tunsigned int tfmsize;\n};\n\nstruct crypto_shash {\n\tunsigned int descsize;\n\tstruct crypto_tfm base;\n};\n\nstruct jbd2_journal_handle;\n\ntypedef struct jbd2_journal_handle handle_t;\n\nstruct jbd2_journal_handle {\n\tunion {\n\t\ttransaction_t *h_transaction;\n\t\tjournal_t *h_journal;\n\t};\n\thandle_t *h_rsv_handle;\n\tint h_total_credits;\n\tint h_revoke_credits;\n\tint h_revoke_credits_requested;\n\tint h_ref;\n\tint h_err;\n\tunsigned int h_sync: 1;\n\tunsigned int h_jdata: 1;\n\tunsigned int h_reserved: 1;\n\tunsigned int h_aborted: 1;\n\tunsigned int h_type: 8;\n\tunsigned int h_line_no: 16;\n\tlong unsigned int h_start_jiffies;\n\tunsigned int h_requested_credits;\n\tunsigned int saved_alloc_context;\n};\n\nstruct transaction_run_stats_s {\n\tlong unsigned int rs_wait;\n\tlong unsigned int rs_request_delay;\n\tlong unsigned int rs_running;\n\tlong unsigned int rs_locked;\n\tlong unsigned int rs_flushing;\n\tlong unsigned int rs_logging;\n\t__u32 rs_handle_count;\n\t__u32 rs_blocks;\n\t__u32 rs_blocks_logged;\n};\n\nstruct transaction_stats_s {\n\tlong unsigned int ts_tid;\n\tlong unsigned int ts_requested;\n\tstruct transaction_run_stats_s run;\n};\n\nstruct journal_superblock_s;\n\ntypedef struct journal_superblock_s journal_superblock_t;\n\nstruct jbd2_revoke_table_s;\n\nstruct journal_s {\n\tlong unsigned int j_flags;\n\tint j_errno;\n\tstruct mutex j_abort_mutex;\n\tstruct buffer_head *j_sb_buffer;\n\tjournal_superblock_t *j_superblock;\n\tint j_format_version;\n\trwlock_t j_state_lock;\n\tint j_barrier_count;\n\tstruct mutex j_barrier;\n\ttransaction_t *j_running_transaction;\n\ttransaction_t *j_committing_transaction;\n\ttransaction_t *j_checkpoint_transactions;\n\twait_queue_head_t j_wait_transaction_locked;\n\twait_queue_head_t j_wait_done_commit;\n\twait_queue_head_t j_wait_commit;\n\twait_queue_head_t j_wait_updates;\n\twait_queue_head_t j_wait_reserved;\n\tstruct mutex j_checkpoint_mutex;\n\tstruct buffer_head *j_chkpt_bhs[64];\n\tlong unsigned int j_head;\n\tlong unsigned int j_tail;\n\tlong unsigned int j_free;\n\tlong unsigned int j_first;\n\tlong unsigned int j_last;\n\tstruct block_device *j_dev;\n\tint j_blocksize;\n\tlong long unsigned int j_blk_offset;\n\tchar j_devname[56];\n\tstruct block_device *j_fs_dev;\n\tunsigned int j_maxlen;\n\tatomic_t j_reserved_credits;\n\tspinlock_t j_list_lock;\n\tstruct inode *j_inode;\n\ttid_t j_tail_sequence;\n\ttid_t j_transaction_sequence;\n\ttid_t j_commit_sequence;\n\ttid_t j_commit_request;\n\t__u8 j_uuid[16];\n\tstruct task_struct *j_task;\n\tint j_max_transaction_buffers;\n\tint j_revoke_records_per_block;\n\tlong unsigned int j_commit_interval;\n\tstruct timer_list j_commit_timer;\n\tspinlock_t j_revoke_lock;\n\tstruct jbd2_revoke_table_s *j_revoke;\n\tstruct jbd2_revoke_table_s *j_revoke_table[2];\n\tstruct buffer_head **j_wbuf;\n\tint j_wbufsize;\n\tpid_t j_last_sync_writer;\n\tu64 j_average_commit_time;\n\tu32 j_min_batch_time;\n\tu32 j_max_batch_time;\n\tvoid (*j_commit_callback)(journal_t *, transaction_t *);\n\tspinlock_t j_history_lock;\n\tstruct proc_dir_entry *j_proc_entry;\n\tstruct transaction_stats_s j_stats;\n\tunsigned int j_failed_commit;\n\tvoid *j_private;\n\tstruct crypto_shash *j_chksum_driver;\n\t__u32 j_csum_seed;\n};\n\nstruct journal_header_s {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n};\n\ntypedef struct journal_header_s journal_header_t;\n\nstruct journal_superblock_s {\n\tjournal_header_t s_header;\n\t__be32 s_blocksize;\n\t__be32 s_maxlen;\n\t__be32 s_first;\n\t__be32 s_sequence;\n\t__be32 s_start;\n\t__be32 s_errno;\n\t__be32 s_feature_compat;\n\t__be32 s_feature_incompat;\n\t__be32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\t__be32 s_nr_users;\n\t__be32 s_dynsuper;\n\t__be32 s_max_transaction;\n\t__be32 s_max_trans_data;\n\t__u8 s_checksum_type;\n\t__u8 s_padding2[3];\n\t__u32 s_padding[42];\n\t__be32 s_checksum;\n\t__u8 s_users[768];\n};\n\nenum jbd_state_bits {\n\tBH_JBD = 16,\n\tBH_JWrite = 17,\n\tBH_Freed = 18,\n\tBH_Revoked = 19,\n\tBH_RevokeValid = 20,\n\tBH_JBDDirty = 21,\n\tBH_JournalHead = 22,\n\tBH_Shadow = 23,\n\tBH_Verified = 24,\n\tBH_JBDPrivateStart = 25,\n};\n\nstruct jbd2_inode {\n\ttransaction_t *i_transaction;\n\ttransaction_t *i_next_transaction;\n\tstruct list_head i_list;\n\tstruct inode *i_vfs_inode;\n\tlong unsigned int i_flags;\n\tloff_t i_dirty_start;\n\tloff_t i_dirty_end;\n};\n\nstruct bgl_lock {\n\tspinlock_t lock;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct blockgroup_lock {\n\tstruct bgl_lock locks[128];\n};\n\nstruct fscrypt_dummy_context {};\n\nstruct fsverity_operations {\n\tint (*begin_enable_verity)(struct file *);\n\tint (*end_enable_verity)(struct file *, const void *, size_t, u64);\n\tint (*get_verity_descriptor)(struct inode *, void *, size_t);\n\tstruct page * (*read_merkle_tree_page)(struct inode *, long unsigned int, long unsigned int);\n\tint (*write_merkle_tree_block)(struct inode *, const void *, u64, int);\n};\n\ntypedef int ext4_grpblk_t;\n\ntypedef long long unsigned int ext4_fsblk_t;\n\ntypedef __u32 ext4_lblk_t;\n\ntypedef unsigned int ext4_group_t;\n\nstruct ext4_allocation_request {\n\tstruct inode *inode;\n\tunsigned int len;\n\text4_lblk_t logical;\n\text4_lblk_t lleft;\n\text4_lblk_t lright;\n\text4_fsblk_t goal;\n\text4_fsblk_t pleft;\n\text4_fsblk_t pright;\n\tunsigned int flags;\n};\n\nstruct ext4_system_blocks {\n\tstruct rb_root root;\n\tstruct callback_head rcu;\n};\n\nstruct ext4_group_desc {\n\t__le32 bg_block_bitmap_lo;\n\t__le32 bg_inode_bitmap_lo;\n\t__le32 bg_inode_table_lo;\n\t__le16 bg_free_blocks_count_lo;\n\t__le16 bg_free_inodes_count_lo;\n\t__le16 bg_used_dirs_count_lo;\n\t__le16 bg_flags;\n\t__le32 bg_exclude_bitmap_lo;\n\t__le16 bg_block_bitmap_csum_lo;\n\t__le16 bg_inode_bitmap_csum_lo;\n\t__le16 bg_itable_unused_lo;\n\t__le16 bg_checksum;\n\t__le32 bg_block_bitmap_hi;\n\t__le32 bg_inode_bitmap_hi;\n\t__le32 bg_inode_table_hi;\n\t__le16 bg_free_blocks_count_hi;\n\t__le16 bg_free_inodes_count_hi;\n\t__le16 bg_used_dirs_count_hi;\n\t__le16 bg_itable_unused_hi;\n\t__le32 bg_exclude_bitmap_hi;\n\t__le16 bg_block_bitmap_csum_hi;\n\t__le16 bg_inode_bitmap_csum_hi;\n\t__u32 bg_reserved;\n};\n\nstruct flex_groups {\n\tatomic64_t free_clusters;\n\tatomic_t free_inodes;\n\tatomic_t used_dirs;\n};\n\nstruct extent_status {\n\tstruct rb_node rb_node;\n\text4_lblk_t es_lblk;\n\text4_lblk_t es_len;\n\text4_fsblk_t es_pblk;\n};\n\nstruct ext4_es_tree {\n\tstruct rb_root root;\n\tstruct extent_status *cache_es;\n};\n\nstruct ext4_es_stats {\n\tlong unsigned int es_stats_shrunk;\n\tstruct percpu_counter es_stats_cache_hits;\n\tstruct percpu_counter es_stats_cache_misses;\n\tu64 es_stats_scan_time;\n\tu64 es_stats_max_scan_time;\n\tstruct percpu_counter es_stats_all_cnt;\n\tstruct percpu_counter es_stats_shk_cnt;\n};\n\nstruct ext4_pending_tree {\n\tstruct rb_root root;\n};\n\nstruct ext4_inode_info {\n\t__le32 i_data[15];\n\t__u32 i_dtime;\n\text4_fsblk_t i_file_acl;\n\text4_group_t i_block_group;\n\text4_lblk_t i_dir_start_lookup;\n\tlong unsigned int i_flags;\n\tstruct rw_semaphore xattr_sem;\n\tstruct list_head i_orphan;\n\tloff_t i_disksize;\n\tstruct rw_semaphore i_data_sem;\n\tstruct rw_semaphore i_mmap_sem;\n\tstruct inode vfs_inode;\n\tstruct jbd2_inode *jinode;\n\tspinlock_t i_raw_lock;\n\tstruct timespec64 i_crtime;\n\tstruct list_head i_prealloc_list;\n\tspinlock_t i_prealloc_lock;\n\tstruct ext4_es_tree i_es_tree;\n\trwlock_t i_es_lock;\n\tstruct list_head i_es_list;\n\tunsigned int i_es_all_nr;\n\tunsigned int i_es_shk_nr;\n\text4_lblk_t i_es_shrink_lblk;\n\text4_group_t i_last_alloc_group;\n\tunsigned int i_reserved_data_blocks;\n\tstruct ext4_pending_tree i_pending_tree;\n\t__u16 i_extra_isize;\n\tu16 i_inline_off;\n\tu16 i_inline_size;\n\tqsize_t i_reserved_quota;\n\tspinlock_t i_completed_io_lock;\n\tstruct list_head i_rsv_conversion_list;\n\tstruct work_struct i_rsv_conversion_work;\n\tatomic_t i_unwritten;\n\tspinlock_t i_block_reservation_lock;\n\ttid_t i_sync_tid;\n\ttid_t i_datasync_tid;\n\tstruct dquot *i_dquot[3];\n\t__u32 i_csum_seed;\n\tkprojid_t i_projid;\n};\n\nstruct ext4_super_block {\n\t__le32 s_inodes_count;\n\t__le32 s_blocks_count_lo;\n\t__le32 s_r_blocks_count_lo;\n\t__le32 s_free_blocks_count_lo;\n\t__le32 s_free_inodes_count;\n\t__le32 s_first_data_block;\n\t__le32 s_log_block_size;\n\t__le32 s_log_cluster_size;\n\t__le32 s_blocks_per_group;\n\t__le32 s_clusters_per_group;\n\t__le32 s_inodes_per_group;\n\t__le32 s_mtime;\n\t__le32 s_wtime;\n\t__le16 s_mnt_count;\n\t__le16 s_max_mnt_count;\n\t__le16 s_magic;\n\t__le16 s_state;\n\t__le16 s_errors;\n\t__le16 s_minor_rev_level;\n\t__le32 s_lastcheck;\n\t__le32 s_checkinterval;\n\t__le32 s_creator_os;\n\t__le32 s_rev_level;\n\t__le16 s_def_resuid;\n\t__le16 s_def_resgid;\n\t__le32 s_first_ino;\n\t__le16 s_inode_size;\n\t__le16 s_block_group_nr;\n\t__le32 s_feature_compat;\n\t__le32 s_feature_incompat;\n\t__le32 s_feature_ro_compat;\n\t__u8 s_uuid[16];\n\tchar s_volume_name[16];\n\tchar s_last_mounted[64];\n\t__le32 s_algorithm_usage_bitmap;\n\t__u8 s_prealloc_blocks;\n\t__u8 s_prealloc_dir_blocks;\n\t__le16 s_reserved_gdt_blocks;\n\t__u8 s_journal_uuid[16];\n\t__le32 s_journal_inum;\n\t__le32 s_journal_dev;\n\t__le32 s_last_orphan;\n\t__le32 s_hash_seed[4];\n\t__u8 s_def_hash_version;\n\t__u8 s_jnl_backup_type;\n\t__le16 s_desc_size;\n\t__le32 s_default_mount_opts;\n\t__le32 s_first_meta_bg;\n\t__le32 s_mkfs_time;\n\t__le32 s_jnl_blocks[17];\n\t__le32 s_blocks_count_hi;\n\t__le32 s_r_blocks_count_hi;\n\t__le32 s_free_blocks_count_hi;\n\t__le16 s_min_extra_isize;\n\t__le16 s_want_extra_isize;\n\t__le32 s_flags;\n\t__le16 s_raid_stride;\n\t__le16 s_mmp_update_interval;\n\t__le64 s_mmp_block;\n\t__le32 s_raid_stripe_width;\n\t__u8 s_log_groups_per_flex;\n\t__u8 s_checksum_type;\n\t__u8 s_encryption_level;\n\t__u8 s_reserved_pad;\n\t__le64 s_kbytes_written;\n\t__le32 s_snapshot_inum;\n\t__le32 s_snapshot_id;\n\t__le64 s_snapshot_r_blocks_count;\n\t__le32 s_snapshot_list;\n\t__le32 s_error_count;\n\t__le32 s_first_error_time;\n\t__le32 s_first_error_ino;\n\t__le64 s_first_error_block;\n\t__u8 s_first_error_func[32];\n\t__le32 s_first_error_line;\n\t__le32 s_last_error_time;\n\t__le32 s_last_error_ino;\n\t__le32 s_last_error_line;\n\t__le64 s_last_error_block;\n\t__u8 s_last_error_func[32];\n\t__u8 s_mount_opts[64];\n\t__le32 s_usr_quota_inum;\n\t__le32 s_grp_quota_inum;\n\t__le32 s_overhead_clusters;\n\t__le32 s_backup_bgs[2];\n\t__u8 s_encrypt_algos[4];\n\t__u8 s_encrypt_pw_salt[16];\n\t__le32 s_lpf_ino;\n\t__le32 s_prj_quota_inum;\n\t__le32 s_checksum_seed;\n\t__u8 s_wtime_hi;\n\t__u8 s_mtime_hi;\n\t__u8 s_mkfs_time_hi;\n\t__u8 s_lastcheck_hi;\n\t__u8 s_first_error_time_hi;\n\t__u8 s_last_error_time_hi;\n\t__u8 s_first_error_errcode;\n\t__u8 s_last_error_errcode;\n\t__le16 s_encoding;\n\t__le16 s_encoding_flags;\n\t__le32 s_reserved[95];\n\t__le32 s_checksum;\n};\n\nstruct mb_cache___2;\n\nstruct ext4_group_info;\n\nstruct ext4_locality_group;\n\nstruct ext4_li_request;\n\nstruct ext4_sb_info {\n\tlong unsigned int s_desc_size;\n\tlong unsigned int s_inodes_per_block;\n\tlong unsigned int s_blocks_per_group;\n\tlong unsigned int s_clusters_per_group;\n\tlong unsigned int s_inodes_per_group;\n\tlong unsigned int s_itb_per_group;\n\tlong unsigned int s_gdb_count;\n\tlong unsigned int s_desc_per_block;\n\text4_group_t s_groups_count;\n\text4_group_t s_blockfile_groups;\n\tlong unsigned int s_overhead;\n\tunsigned int s_cluster_ratio;\n\tunsigned int s_cluster_bits;\n\tloff_t s_bitmap_maxbytes;\n\tstruct buffer_head *s_sbh;\n\tstruct ext4_super_block *s_es;\n\tstruct buffer_head **s_group_desc;\n\tunsigned int s_mount_opt;\n\tunsigned int s_mount_opt2;\n\tunsigned int s_mount_flags;\n\tunsigned int s_def_mount_opt;\n\text4_fsblk_t s_sb_block;\n\tatomic64_t s_resv_clusters;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tshort unsigned int s_mount_state;\n\tshort unsigned int s_pad;\n\tint s_addr_per_block_bits;\n\tint s_desc_per_block_bits;\n\tint s_inode_size;\n\tint s_first_ino;\n\tunsigned int s_inode_readahead_blks;\n\tunsigned int s_inode_goal;\n\tu32 s_hash_seed[4];\n\tint s_def_hash_version;\n\tint s_hash_unsigned;\n\tstruct percpu_counter s_freeclusters_counter;\n\tstruct percpu_counter s_freeinodes_counter;\n\tstruct percpu_counter s_dirs_counter;\n\tstruct percpu_counter s_dirtyclusters_counter;\n\tstruct blockgroup_lock *s_blockgroup_lock;\n\tstruct proc_dir_entry *s_proc;\n\tstruct kobject s_kobj;\n\tstruct completion s_kobj_unregister;\n\tstruct super_block *s_sb;\n\tstruct journal_s *s_journal;\n\tstruct list_head s_orphan;\n\tstruct mutex s_orphan_lock;\n\tlong unsigned int s_ext4_flags;\n\tlong unsigned int s_commit_interval;\n\tu32 s_max_batch_time;\n\tu32 s_min_batch_time;\n\tstruct block_device *journal_bdev;\n\tchar *s_qf_names[3];\n\tint s_jquota_fmt;\n\tunsigned int s_want_extra_isize;\n\tstruct ext4_system_blocks *system_blks;\n\tstruct ext4_group_info ***s_group_info;\n\tstruct inode *s_buddy_cache;\n\tspinlock_t s_md_lock;\n\tshort unsigned int *s_mb_offsets;\n\tunsigned int *s_mb_maxs;\n\tunsigned int s_group_info_size;\n\tunsigned int s_mb_free_pending;\n\tstruct list_head s_freed_data_list;\n\tlong unsigned int s_stripe;\n\tunsigned int s_mb_stream_request;\n\tunsigned int s_mb_max_to_scan;\n\tunsigned int s_mb_min_to_scan;\n\tunsigned int s_mb_stats;\n\tunsigned int s_mb_order2_reqs;\n\tunsigned int s_mb_group_prealloc;\n\tunsigned int s_max_dir_size_kb;\n\tlong unsigned int s_mb_last_group;\n\tlong unsigned int s_mb_last_start;\n\tatomic_t s_bal_reqs;\n\tatomic_t s_bal_success;\n\tatomic_t s_bal_allocated;\n\tatomic_t s_bal_ex_scanned;\n\tatomic_t s_bal_goals;\n\tatomic_t s_bal_breaks;\n\tatomic_t s_bal_2orders;\n\tspinlock_t s_bal_lock;\n\tlong unsigned int s_mb_buddies_generated;\n\tlong long unsigned int s_mb_generation_time;\n\tatomic_t s_mb_lost_chunks;\n\tatomic_t s_mb_preallocated;\n\tatomic_t s_mb_discarded;\n\tatomic_t s_lock_busy;\n\tstruct ext4_locality_group *s_locality_groups;\n\tlong unsigned int s_sectors_written_start;\n\tu64 s_kbytes_written;\n\tunsigned int s_extent_max_zeroout_kb;\n\tunsigned int s_log_groups_per_flex;\n\tstruct flex_groups **s_flex_groups;\n\text4_group_t s_flex_groups_allocated;\n\tstruct workqueue_struct *rsv_conversion_wq;\n\tstruct timer_list s_err_report;\n\tstruct ext4_li_request *s_li_request;\n\tunsigned int s_li_wait_mult;\n\tstruct task_struct *s_mmp_tsk;\n\tatomic_t s_last_trim_minblks;\n\tstruct crypto_shash *s_chksum_driver;\n\t__u32 s_csum_seed;\n\tstruct shrinker s_es_shrinker;\n\tstruct list_head s_es_list;\n\tlong int s_es_nr_inode;\n\tstruct ext4_es_stats s_es_stats;\n\tstruct mb_cache___2 *s_ea_block_cache;\n\tstruct mb_cache___2 *s_ea_inode_cache;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t s_es_lock;\n\tstruct ratelimit_state s_err_ratelimit_state;\n\tstruct ratelimit_state s_warning_ratelimit_state;\n\tstruct ratelimit_state s_msg_ratelimit_state;\n\tstruct fscrypt_dummy_context s_dummy_enc_ctx;\n\tstruct percpu_rw_semaphore s_writepages_rwsem;\n\tstruct dax_device *s_daxdev;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ext4_group_info {\n\tlong unsigned int bb_state;\n\tstruct rb_root bb_free_root;\n\text4_grpblk_t bb_first_free;\n\text4_grpblk_t bb_free;\n\text4_grpblk_t bb_fragments;\n\text4_grpblk_t bb_largest_free_order;\n\tstruct list_head bb_prealloc_list;\n\tstruct rw_semaphore alloc_sem;\n\text4_grpblk_t bb_counters[0];\n};\n\nstruct ext4_locality_group {\n\tstruct mutex lg_mutex;\n\tstruct list_head lg_prealloc_list[10];\n\tspinlock_t lg_prealloc_lock;\n};\n\nstruct ext4_li_request {\n\tstruct super_block *lr_super;\n\tstruct ext4_sb_info *lr_sbi;\n\text4_group_t lr_next_group;\n\tstruct list_head lr_request;\n\tlong unsigned int lr_next_sched;\n\tlong unsigned int lr_timeout;\n};\n\nstruct iomap_ops___2;\n\nstruct shash_desc {\n\tstruct crypto_shash *tfm;\n\tvoid *__ctx[0];\n};\n\nstruct ext4_map_blocks {\n\text4_fsblk_t m_pblk;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\tunsigned int m_flags;\n};\n\nstruct ext4_system_zone {\n\tstruct rb_node node;\n\text4_fsblk_t start_blk;\n\tunsigned int count;\n};\n\nstruct fscrypt_str {\n\tunsigned char *name;\n\tu32 len;\n};\n\nenum {\n\tEXT4_INODE_SECRM = 0,\n\tEXT4_INODE_UNRM = 1,\n\tEXT4_INODE_COMPR = 2,\n\tEXT4_INODE_SYNC = 3,\n\tEXT4_INODE_IMMUTABLE = 4,\n\tEXT4_INODE_APPEND = 5,\n\tEXT4_INODE_NODUMP = 6,\n\tEXT4_INODE_NOATIME = 7,\n\tEXT4_INODE_DIRTY = 8,\n\tEXT4_INODE_COMPRBLK = 9,\n\tEXT4_INODE_NOCOMPR = 10,\n\tEXT4_INODE_ENCRYPT = 11,\n\tEXT4_INODE_INDEX = 12,\n\tEXT4_INODE_IMAGIC = 13,\n\tEXT4_INODE_JOURNAL_DATA = 14,\n\tEXT4_INODE_NOTAIL = 15,\n\tEXT4_INODE_DIRSYNC = 16,\n\tEXT4_INODE_TOPDIR = 17,\n\tEXT4_INODE_HUGE_FILE = 18,\n\tEXT4_INODE_EXTENTS = 19,\n\tEXT4_INODE_VERITY = 20,\n\tEXT4_INODE_EA_INODE = 21,\n\tEXT4_INODE_DAX = 25,\n\tEXT4_INODE_INLINE_DATA = 28,\n\tEXT4_INODE_PROJINHERIT = 29,\n\tEXT4_INODE_CASEFOLD = 30,\n\tEXT4_INODE_RESERVED = 31,\n};\n\nstruct ext4_dir_entry_2 {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[255];\n};\n\nstruct fname;\n\nstruct dir_private_info {\n\tstruct rb_root root;\n\tstruct rb_node *curr_node;\n\tstruct fname *extra_fname;\n\tloff_t last_pos;\n\t__u32 curr_hash;\n\t__u32 curr_minor_hash;\n\t__u32 next_hash;\n};\n\nstruct fname {\n\t__u32 hash;\n\t__u32 minor_hash;\n\tstruct rb_node rb_hash;\n\tstruct fname *next;\n\t__u32 inode;\n\t__u8 name_len;\n\t__u8 file_type;\n\tchar name[0];\n};\n\nenum SHIFT_DIRECTION {\n\tSHIFT_LEFT = 0,\n\tSHIFT_RIGHT = 1,\n};\n\nstruct ext4_io_end_vec {\n\tstruct list_head list;\n\tloff_t offset;\n\tssize_t size;\n};\n\nstruct ext4_io_end {\n\tstruct list_head list;\n\thandle_t *handle;\n\tstruct inode *inode;\n\tstruct bio *bio;\n\tunsigned int flag;\n\tatomic_t count;\n\tstruct list_head list_vec;\n};\n\ntypedef struct ext4_io_end ext4_io_end_t;\n\nenum {\n\tES_WRITTEN_B = 0,\n\tES_UNWRITTEN_B = 1,\n\tES_DELAYED_B = 2,\n\tES_HOLE_B = 3,\n\tES_REFERENCED_B = 4,\n\tES_FLAGS = 5,\n};\n\nenum {\n\tEXT4_STATE_JDATA = 0,\n\tEXT4_STATE_NEW = 1,\n\tEXT4_STATE_XATTR = 2,\n\tEXT4_STATE_NO_EXPAND = 3,\n\tEXT4_STATE_DA_ALLOC_CLOSE = 4,\n\tEXT4_STATE_EXT_MIGRATE = 5,\n\tEXT4_STATE_NEWENTRY = 6,\n\tEXT4_STATE_MAY_INLINE_DATA = 7,\n\tEXT4_STATE_EXT_PRECACHED = 8,\n\tEXT4_STATE_LUSTRE_EA_INODE = 9,\n\tEXT4_STATE_VERITY_IN_PROGRESS = 10,\n};\n\nstruct ext4_iloc {\n\tstruct buffer_head *bh;\n\tlong unsigned int offset;\n\text4_group_t block_group;\n};\n\nstruct ext4_extent_tail {\n\t__le32 et_checksum;\n};\n\nstruct ext4_extent {\n\t__le32 ee_block;\n\t__le16 ee_len;\n\t__le16 ee_start_hi;\n\t__le32 ee_start_lo;\n};\n\nstruct ext4_extent_idx {\n\t__le32 ei_block;\n\t__le32 ei_leaf_lo;\n\t__le16 ei_leaf_hi;\n\t__u16 ei_unused;\n};\n\nstruct ext4_extent_header {\n\t__le16 eh_magic;\n\t__le16 eh_entries;\n\t__le16 eh_max;\n\t__le16 eh_depth;\n\t__le32 eh_generation;\n};\n\nstruct ext4_ext_path {\n\text4_fsblk_t p_block;\n\t__u16 p_depth;\n\t__u16 p_maxdepth;\n\tstruct ext4_extent *p_ext;\n\tstruct ext4_extent_idx *p_idx;\n\tstruct ext4_extent_header *p_hdr;\n\tstruct buffer_head *p_bh;\n};\n\nstruct partial_cluster {\n\text4_fsblk_t pclu;\n\text4_lblk_t lblk;\n\tenum {\n\t\tinitial = 0,\n\t\ttofree = 1,\n\t\tnofree = 2,\n\t} state;\n};\n\nstruct pending_reservation {\n\tstruct rb_node rb_node;\n\text4_lblk_t lclu;\n};\n\nstruct rsvd_count {\n\tint ndelonly;\n\tbool first_do_lblk_found;\n\text4_lblk_t first_do_lblk;\n\text4_lblk_t last_do_lblk;\n\tstruct extent_status *left_es;\n\tbool partial;\n\text4_lblk_t lclu;\n};\n\nstruct fsverity_info;\n\nstruct fsmap {\n\t__u32 fmr_device;\n\t__u32 fmr_flags;\n\t__u64 fmr_physical;\n\t__u64 fmr_owner;\n\t__u64 fmr_offset;\n\t__u64 fmr_length;\n\t__u64 fmr_reserved[3];\n};\n\nstruct ext4_fsmap {\n\tstruct list_head fmr_list;\n\tdev_t fmr_device;\n\tuint32_t fmr_flags;\n\tuint64_t fmr_physical;\n\tuint64_t fmr_owner;\n\tuint64_t fmr_length;\n};\n\nstruct ext4_fsmap_head {\n\tuint32_t fmh_iflags;\n\tuint32_t fmh_oflags;\n\tunsigned int fmh_count;\n\tunsigned int fmh_entries;\n\tstruct ext4_fsmap fmh_keys[2];\n};\n\ntypedef int (*ext4_fsmap_format_t)(struct ext4_fsmap *, void *);\n\nstruct ext4_getfsmap_info {\n\tstruct ext4_fsmap_head *gfi_head;\n\text4_fsmap_format_t gfi_formatter;\n\tvoid *gfi_format_arg;\n\text4_fsblk_t gfi_next_fsblk;\n\tu32 gfi_dev;\n\text4_group_t gfi_agno;\n\tstruct ext4_fsmap gfi_low;\n\tstruct ext4_fsmap gfi_high;\n\tstruct ext4_fsmap gfi_lastfree;\n\tstruct list_head gfi_meta_list;\n\tbool gfi_last;\n};\n\nstruct ext4_getfsmap_dev {\n\tint (*gfd_fn)(struct super_block *, struct ext4_fsmap *, struct ext4_getfsmap_info *);\n\tu32 gfd_dev;\n};\n\nstruct dx_hash_info {\n\tu32 hash;\n\tu32 minor_hash;\n\tint hash_version;\n\tu32 *seed;\n};\n\nstruct ext4_inode {\n\t__le16 i_mode;\n\t__le16 i_uid;\n\t__le32 i_size_lo;\n\t__le32 i_atime;\n\t__le32 i_ctime;\n\t__le32 i_mtime;\n\t__le32 i_dtime;\n\t__le16 i_gid;\n\t__le16 i_links_count;\n\t__le32 i_blocks_lo;\n\t__le32 i_flags;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 l_i_version;\n\t\t} linux1;\n\t\tstruct {\n\t\t\t__u32 h_i_translator;\n\t\t} hurd1;\n\t\tstruct {\n\t\t\t__u32 m_i_reserved1;\n\t\t} masix1;\n\t} osd1;\n\t__le32 i_block[15];\n\t__le32 i_generation;\n\t__le32 i_file_acl_lo;\n\t__le32 i_size_high;\n\t__le32 i_obso_faddr;\n\tunion {\n\t\tstruct {\n\t\t\t__le16 l_i_blocks_high;\n\t\t\t__le16 l_i_file_acl_high;\n\t\t\t__le16 l_i_uid_high;\n\t\t\t__le16 l_i_gid_high;\n\t\t\t__le16 l_i_checksum_lo;\n\t\t\t__le16 l_i_reserved;\n\t\t} linux2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__u16 h_i_mode_high;\n\t\t\t__u16 h_i_uid_high;\n\t\t\t__u16 h_i_gid_high;\n\t\t\t__u32 h_i_author;\n\t\t} hurd2;\n\t\tstruct {\n\t\t\t__le16 h_i_reserved1;\n\t\t\t__le16 m_i_file_acl_high;\n\t\t\t__u32 m_i_reserved2[2];\n\t\t} masix2;\n\t} osd2;\n\t__le16 i_extra_isize;\n\t__le16 i_checksum_hi;\n\t__le32 i_ctime_extra;\n\t__le32 i_mtime_extra;\n\t__le32 i_atime_extra;\n\t__le32 i_crtime;\n\t__le32 i_crtime_extra;\n\t__le32 i_version_hi;\n\t__le32 i_projid;\n};\n\nstruct orlov_stats {\n\t__u64 free_clusters;\n\t__u32 free_inodes;\n\t__u32 used_dirs;\n};\n\ntypedef struct {\n\t__le32 *p;\n\t__le32 key;\n\tstruct buffer_head *bh;\n} Indirect;\n\nstruct ext4_filename {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tstruct dx_hash_info hinfo;\n};\n\nstruct ext4_xattr_ibody_header {\n\t__le32 h_magic;\n};\n\nstruct ext4_xattr_entry {\n\t__u8 e_name_len;\n\t__u8 e_name_index;\n\t__le16 e_value_offs;\n\t__le32 e_value_inum;\n\t__le32 e_value_size;\n\t__le32 e_hash;\n\tchar e_name[0];\n};\n\nstruct ext4_xattr_info {\n\tconst char *name;\n\tconst void *value;\n\tsize_t value_len;\n\tint name_index;\n\tint in_inode;\n};\n\nstruct ext4_xattr_search {\n\tstruct ext4_xattr_entry *first;\n\tvoid *base;\n\tvoid *end;\n\tstruct ext4_xattr_entry *here;\n\tint not_found;\n};\n\nstruct ext4_xattr_ibody_find {\n\tstruct ext4_xattr_search s;\n\tstruct ext4_iloc iloc;\n};\n\ntypedef short unsigned int __kernel_uid16_t;\n\ntypedef short unsigned int __kernel_gid16_t;\n\ntypedef __kernel_uid16_t uid16_t;\n\ntypedef __kernel_gid16_t gid16_t;\n\nstruct ext4_io_submit {\n\tstruct writeback_control *io_wbc;\n\tstruct bio *io_bio;\n\text4_io_end_t *io_end;\n\tsector_t io_next_block;\n};\n\ntypedef enum {\n\tEXT4_IGET_NORMAL = 0,\n\tEXT4_IGET_SPECIAL = 1,\n\tEXT4_IGET_HANDLE = 2,\n} ext4_iget_flags;\n\nstruct ext4_xattr_inode_array {\n\tunsigned int count;\n\tstruct inode *inodes[0];\n};\n\nstruct mpage_da_data {\n\tstruct inode *inode;\n\tstruct writeback_control *wbc;\n\tlong unsigned int first_page;\n\tlong unsigned int next_page;\n\tlong unsigned int last_page;\n\tstruct ext4_map_blocks map;\n\tstruct ext4_io_submit io_submit;\n\tunsigned int do_map: 1;\n\tunsigned int scanned_until_end: 1;\n};\n\nstruct fstrim_range {\n\t__u64 start;\n\t__u64 len;\n\t__u64 minlen;\n};\n\nstruct ext4_new_group_input {\n\t__u32 group;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 unused;\n};\n\nstruct compat_ext4_new_group_input {\n\tu32 group;\n\tcompat_u64 block_bitmap;\n\tcompat_u64 inode_bitmap;\n\tcompat_u64 inode_table;\n\tu32 blocks_count;\n\tu16 reserved_blocks;\n\tu16 unused;\n} __attribute__((packed));\n\nstruct ext4_new_group_data {\n\t__u32 group;\n\t__u64 block_bitmap;\n\t__u64 inode_bitmap;\n\t__u64 inode_table;\n\t__u32 blocks_count;\n\t__u16 reserved_blocks;\n\t__u16 mdata_blocks;\n\t__u32 free_clusters_count;\n};\n\nstruct move_extent {\n\t__u32 reserved;\n\t__u32 donor_fd;\n\t__u64 orig_start;\n\t__u64 donor_start;\n\t__u64 len;\n\t__u64 moved_len;\n};\n\nstruct fsmap_head {\n\t__u32 fmh_iflags;\n\t__u32 fmh_oflags;\n\t__u32 fmh_count;\n\t__u32 fmh_entries;\n\t__u64 fmh_reserved[6];\n\tstruct fsmap fmh_keys[2];\n\tstruct fsmap fmh_recs[0];\n};\n\nstruct getfsmap_info {\n\tstruct super_block *gi_sb;\n\tstruct fsmap_head *gi_data;\n\tunsigned int gi_idx;\n\t__u32 gi_last_flags;\n};\n\nstruct ext4_free_data {\n\tstruct list_head efd_list;\n\tstruct rb_node efd_node;\n\text4_group_t efd_group;\n\text4_grpblk_t efd_start_cluster;\n\text4_grpblk_t efd_count;\n\ttid_t efd_tid;\n};\n\nstruct ext4_prealloc_space {\n\tstruct list_head pa_inode_list;\n\tstruct list_head pa_group_list;\n\tunion {\n\t\tstruct list_head pa_tmp_list;\n\t\tstruct callback_head pa_rcu;\n\t} u;\n\tspinlock_t pa_lock;\n\tatomic_t pa_count;\n\tunsigned int pa_deleted;\n\text4_fsblk_t pa_pstart;\n\text4_lblk_t pa_lstart;\n\text4_grpblk_t pa_len;\n\text4_grpblk_t pa_free;\n\tshort unsigned int pa_type;\n\tspinlock_t *pa_obj_lock;\n\tstruct inode *pa_inode;\n};\n\nenum {\n\tMB_INODE_PA = 0,\n\tMB_GROUP_PA = 1,\n};\n\nstruct ext4_free_extent {\n\text4_lblk_t fe_logical;\n\text4_grpblk_t fe_start;\n\text4_group_t fe_group;\n\text4_grpblk_t fe_len;\n};\n\nstruct ext4_allocation_context {\n\tstruct inode *ac_inode;\n\tstruct super_block *ac_sb;\n\tstruct ext4_free_extent ac_o_ex;\n\tstruct ext4_free_extent ac_g_ex;\n\tstruct ext4_free_extent ac_b_ex;\n\tstruct ext4_free_extent ac_f_ex;\n\t__u16 ac_groups_scanned;\n\t__u16 ac_found;\n\t__u16 ac_tail;\n\t__u16 ac_buddy;\n\t__u16 ac_flags;\n\t__u8 ac_status;\n\t__u8 ac_criteria;\n\t__u8 ac_2order;\n\t__u8 ac_op;\n\tstruct page *ac_bitmap_page;\n\tstruct page *ac_buddy_page;\n\tstruct ext4_prealloc_space *ac_pa;\n\tstruct ext4_locality_group *ac_lg;\n};\n\nstruct ext4_buddy {\n\tstruct page *bd_buddy_page;\n\tvoid *bd_buddy;\n\tstruct page *bd_bitmap_page;\n\tvoid *bd_bitmap;\n\tstruct ext4_group_info *bd_info;\n\tstruct super_block *bd_sb;\n\t__u16 bd_blkbits;\n\text4_group_t bd_group;\n};\n\ntypedef int (*ext4_mballoc_query_range_fn)(struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t, void *);\n\nstruct sg {\n\tstruct ext4_group_info info;\n\text4_grpblk_t counters[18];\n};\n\nstruct migrate_struct {\n\text4_lblk_t first_block;\n\text4_lblk_t last_block;\n\text4_lblk_t curr_block;\n\text4_fsblk_t first_pblock;\n\text4_fsblk_t last_pblock;\n};\n\nstruct mmp_struct {\n\t__le32 mmp_magic;\n\t__le32 mmp_seq;\n\t__le64 mmp_time;\n\tchar mmp_nodename[64];\n\tchar mmp_bdevname[32];\n\t__le16 mmp_check_interval;\n\t__le16 mmp_pad1;\n\t__le32 mmp_pad2[226];\n\t__le32 mmp_checksum;\n};\n\nstruct mmpd_data {\n\tstruct buffer_head *bh;\n\tstruct super_block *sb;\n};\n\nstruct fscrypt_name {\n\tconst struct qstr *usr_fname;\n\tstruct fscrypt_str disk_name;\n\tu32 hash;\n\tu32 minor_hash;\n\tstruct fscrypt_str crypto_buf;\n\tbool is_ciphertext_name;\n};\n\nstruct ext4_dir_entry {\n\t__le32 inode;\n\t__le16 rec_len;\n\t__le16 name_len;\n\tchar name[255];\n};\n\nstruct ext4_dir_entry_tail {\n\t__le32 det_reserved_zero1;\n\t__le16 det_rec_len;\n\t__u8 det_reserved_zero2;\n\t__u8 det_reserved_ft;\n\t__le32 det_checksum;\n};\n\ntypedef enum {\n\tEITHER = 0,\n\tINDEX = 1,\n\tDIRENT = 2,\n\tDIRENT_HTREE = 3,\n} dirblock_type_t;\n\nstruct fake_dirent {\n\t__le32 inode;\n\t__le16 rec_len;\n\tu8 name_len;\n\tu8 file_type;\n};\n\nstruct dx_countlimit {\n\t__le16 limit;\n\t__le16 count;\n};\n\nstruct dx_entry {\n\t__le32 hash;\n\t__le32 block;\n};\n\nstruct dx_root_info {\n\t__le32 reserved_zero;\n\tu8 hash_version;\n\tu8 info_length;\n\tu8 indirect_levels;\n\tu8 unused_flags;\n};\n\nstruct dx_root {\n\tstruct fake_dirent dot;\n\tchar dot_name[4];\n\tstruct fake_dirent dotdot;\n\tchar dotdot_name[4];\n\tstruct dx_root_info info;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_node {\n\tstruct fake_dirent fake;\n\tstruct dx_entry entries[0];\n};\n\nstruct dx_frame {\n\tstruct buffer_head *bh;\n\tstruct dx_entry *entries;\n\tstruct dx_entry *at;\n};\n\nstruct dx_map_entry {\n\tu32 hash;\n\tu16 offs;\n\tu16 size;\n};\n\nstruct dx_tail {\n\tu32 dt_reserved;\n\t__le32 dt_checksum;\n};\n\nstruct ext4_renament {\n\tstruct inode *dir;\n\tstruct dentry *dentry;\n\tstruct inode *inode;\n\tbool is_dir;\n\tint dir_nlink_delta;\n\tstruct buffer_head *bh;\n\tstruct ext4_dir_entry_2 *de;\n\tint inlined;\n\tstruct buffer_head *dir_bh;\n\tstruct ext4_dir_entry_2 *parent_de;\n\tint dir_inlined;\n};\n\nunion fscrypt_context;\n\nenum bio_post_read_step {\n\tSTEP_INITIAL = 0,\n\tSTEP_DECRYPT = 1,\n\tSTEP_VERITY = 2,\n\tSTEP_MAX = 3,\n};\n\nstruct bio_post_read_ctx {\n\tstruct bio *bio;\n\tstruct work_struct work;\n\tunsigned int cur_step;\n\tunsigned int enabled_steps;\n};\n\nenum {\n\tBLOCK_BITMAP = 0,\n\tINODE_BITMAP = 1,\n\tINODE_TABLE = 2,\n\tGROUP_TABLE_COUNT = 3,\n};\n\nstruct ext4_rcu_ptr {\n\tstruct callback_head rcu;\n\tvoid *ptr;\n};\n\nstruct ext4_new_flex_group_data {\n\tstruct ext4_new_group_data *groups;\n\t__u16 *bg_flags;\n\text4_group_t count;\n};\n\nenum stat_group {\n\tSTAT_READ = 0,\n\tSTAT_WRITE = 1,\n\tSTAT_DISCARD = 2,\n\tSTAT_FLUSH = 3,\n\tNR_STAT_GROUPS = 4,\n};\n\nenum {\n\tI_DATA_SEM_NORMAL = 0,\n\tI_DATA_SEM_OTHER = 1,\n\tI_DATA_SEM_QUOTA = 2,\n};\n\nstruct ext4_lazy_init {\n\tlong unsigned int li_state;\n\tstruct list_head li_request_list;\n\tstruct mutex li_list_mtx;\n};\n\nstruct ext4_journal_cb_entry {\n\tstruct list_head jce_list;\n\tvoid (*jce_func)(struct super_block *, struct ext4_journal_cb_entry *, int);\n};\n\nstruct trace_event_raw_ext4_other_inode_update_time {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t orig_ino;\n\tuid_t uid;\n\tgid_t gid;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_free_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tuid_t uid;\n\tgid_t gid;\n\t__u64 blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_request_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_allocate_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t dir;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_evict_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint nlink;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_drop_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint drop;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_nfs_commit_metadata {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mark_inode_dirty {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int ip;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_begin_ordered_truncate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t new_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__write_begin {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int len;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__write_end {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int len;\n\tunsigned int copied;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_writepages {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong int nr_to_write;\n\tlong int pages_skipped;\n\tloff_t range_start;\n\tloff_t range_end;\n\tlong unsigned int writeback_index;\n\tint sync_mode;\n\tchar for_kupdate;\n\tchar range_cyclic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_pages {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int first_page;\n\tlong int nr_to_write;\n\tint sync_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_write_pages_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 lblk;\n\t__u32 len;\n\t__u32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_writepages_result {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tint pages_written;\n\tlong int pages_skipped;\n\tlong unsigned int writeback_index;\n\tint sync_mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__page_op {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_invalidatepage_op {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tlong unsigned int index;\n\tunsigned int offset;\n\tunsigned int length;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_discard_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u64 blk;\n\t__u64 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__mb_new_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 pa_pstart;\n\t__u64 pa_lstart;\n\t__u32 pa_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_release_inode_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\t__u32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_release_group_pa {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u64 pa_pstart;\n\t__u32 pa_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_discard_preallocations {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mb_discard_preallocations {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint needed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_request_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int len;\n\t__u32 logical;\n\t__u32 lleft;\n\t__u32 lright;\n\t__u64 goal;\n\t__u64 pleft;\n\t__u64 pright;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_allocate_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tunsigned int len;\n\t__u32 logical;\n\t__u32 lleft;\n\t__u32 lright;\n\t__u64 goal;\n\t__u64 pleft;\n\t__u64 pright;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_free_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tlong unsigned int count;\n\tint flags;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_file_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t parent;\n\tint datasync;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_file_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_sync_fs {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_alloc_da_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int data_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mballoc_alloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u32 orig_logical;\n\tint orig_start;\n\t__u32 orig_group;\n\tint orig_len;\n\t__u32 goal_logical;\n\tint goal_start;\n\t__u32 goal_group;\n\tint goal_len;\n\t__u32 result_logical;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\t__u16 found;\n\t__u16 groups;\n\t__u16 buddy;\n\t__u16 flags;\n\t__u16 tail;\n\t__u8 cr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_mballoc_prealloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u32 orig_logical;\n\tint orig_start;\n\t__u32 orig_group;\n\tint orig_len;\n\t__u32 result_logical;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__mballoc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint result_start;\n\t__u32 result_group;\n\tint result_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_forget {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 block;\n\tint is_metadata;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_update_reserve_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint used_blocks;\n\tint reserved_data_blocks;\n\tint quota_claim;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_reserve_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint reserved_data_blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_da_release_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 i_blocks;\n\tint freed_blocks;\n\tint reserved_data_blocks;\n\t__u16 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__bitmap_load {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\t__u32 group;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_direct_IO_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tlong unsigned int len;\n\tint rw;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_direct_IO_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tlong unsigned int len;\n\tint rw;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__fallocate_mode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tint mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fallocate_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t pos;\n\tunsigned int blocks;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_unlink_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tino_t parent;\n\tloff_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_unlink_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__truncate {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\t__u64 blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_convert_to_initialized_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\text4_lblk_t u_lblk;\n\tunsigned int u_len;\n\text4_fsblk_t u_pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_convert_to_initialized_fastpath {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t m_lblk;\n\tunsigned int m_len;\n\text4_lblk_t u_lblk;\n\tunsigned int u_len;\n\text4_fsblk_t u_pblk;\n\text4_lblk_t i_lblk;\n\tunsigned int i_len;\n\text4_fsblk_t i_pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__map_blocks_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__map_blocks_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tunsigned int flags;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tunsigned int mflags;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_load_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_load_inode {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tint rsv_blocks;\n\tint revoke_creds;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_journal_start_reserved {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int ip;\n\tint blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__trim {\n\tstruct trace_entry ent;\n\tint dev_major;\n\tint dev_minor;\n\t__u32 group;\n\tint start;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_handle_unwritten_extents {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tint flags;\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tunsigned int len;\n\tunsigned int allocated;\n\text4_fsblk_t newblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_get_implied_cluster_alloc_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\text4_lblk_t lblk;\n\text4_fsblk_t pblk;\n\tunsigned int len;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_put_in_cache {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\text4_fsblk_t start;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_in_cache {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_find_delalloc_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t from;\n\text4_lblk_t to;\n\tint reverse;\n\tint found;\n\text4_lblk_t found_blk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_get_reserved_cluster_alloc {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tunsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_show_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\text4_lblk_t lblk;\n\tshort unsigned int len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_remove_blocks {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t from;\n\text4_lblk_t to;\n\text4_fsblk_t ee_pblk;\n\text4_lblk_t ee_lblk;\n\tshort unsigned int ee_len;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_rm_leaf {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t ee_lblk;\n\text4_fsblk_t ee_pblk;\n\tshort int ee_len;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_rm_idx {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_fsblk_t pblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_remove_space {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t end;\n\tint depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_ext_remove_space_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t start;\n\text4_lblk_t end;\n\tint depth;\n\text4_fsblk_t pc_pclu;\n\text4_lblk_t pc_lblk;\n\tint pc_state;\n\tshort unsigned int eh_entries;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__es_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_remove_extent {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t lblk;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_find_extent_range_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_find_extent_range_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_lookup_extent_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_lookup_extent_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tint found;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4__es_shrink_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_to_scan;\n\tint cache_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_shrink_scan_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_shrunk;\n\tint cache_cnt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_collapse_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_insert_range {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tloff_t offset;\n\tloff_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_shrink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint nr_shrunk;\n\tlong long unsigned int scan_time;\n\tint nr_skipped;\n\tint retried;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_es_insert_delayed_block {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\text4_lblk_t lblk;\n\text4_lblk_t len;\n\text4_fsblk_t pblk;\n\tchar status;\n\tbool allocated;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_fsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\tu32 agno;\n\tu64 bno;\n\tu64 len;\n\tu64 owner;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_getfsmap_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tdev_t keydev;\n\tu64 block;\n\tu64 len;\n\tu64 owner;\n\tu64 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_shutdown {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ext4_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tconst char *function;\n\tunsigned int line;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_ext4_other_inode_update_time {};\n\nstruct trace_event_data_offsets_ext4_free_inode {};\n\nstruct trace_event_data_offsets_ext4_request_inode {};\n\nstruct trace_event_data_offsets_ext4_allocate_inode {};\n\nstruct trace_event_data_offsets_ext4_evict_inode {};\n\nstruct trace_event_data_offsets_ext4_drop_inode {};\n\nstruct trace_event_data_offsets_ext4_nfs_commit_metadata {};\n\nstruct trace_event_data_offsets_ext4_mark_inode_dirty {};\n\nstruct trace_event_data_offsets_ext4_begin_ordered_truncate {};\n\nstruct trace_event_data_offsets_ext4__write_begin {};\n\nstruct trace_event_data_offsets_ext4__write_end {};\n\nstruct trace_event_data_offsets_ext4_writepages {};\n\nstruct trace_event_data_offsets_ext4_da_write_pages {};\n\nstruct trace_event_data_offsets_ext4_da_write_pages_extent {};\n\nstruct trace_event_data_offsets_ext4_writepages_result {};\n\nstruct trace_event_data_offsets_ext4__page_op {};\n\nstruct trace_event_data_offsets_ext4_invalidatepage_op {};\n\nstruct trace_event_data_offsets_ext4_discard_blocks {};\n\nstruct trace_event_data_offsets_ext4__mb_new_pa {};\n\nstruct trace_event_data_offsets_ext4_mb_release_inode_pa {};\n\nstruct trace_event_data_offsets_ext4_mb_release_group_pa {};\n\nstruct trace_event_data_offsets_ext4_discard_preallocations {};\n\nstruct trace_event_data_offsets_ext4_mb_discard_preallocations {};\n\nstruct trace_event_data_offsets_ext4_request_blocks {};\n\nstruct trace_event_data_offsets_ext4_allocate_blocks {};\n\nstruct trace_event_data_offsets_ext4_free_blocks {};\n\nstruct trace_event_data_offsets_ext4_sync_file_enter {};\n\nstruct trace_event_data_offsets_ext4_sync_file_exit {};\n\nstruct trace_event_data_offsets_ext4_sync_fs {};\n\nstruct trace_event_data_offsets_ext4_alloc_da_blocks {};\n\nstruct trace_event_data_offsets_ext4_mballoc_alloc {};\n\nstruct trace_event_data_offsets_ext4_mballoc_prealloc {};\n\nstruct trace_event_data_offsets_ext4__mballoc {};\n\nstruct trace_event_data_offsets_ext4_forget {};\n\nstruct trace_event_data_offsets_ext4_da_update_reserve_space {};\n\nstruct trace_event_data_offsets_ext4_da_reserve_space {};\n\nstruct trace_event_data_offsets_ext4_da_release_space {};\n\nstruct trace_event_data_offsets_ext4__bitmap_load {};\n\nstruct trace_event_data_offsets_ext4_direct_IO_enter {};\n\nstruct trace_event_data_offsets_ext4_direct_IO_exit {};\n\nstruct trace_event_data_offsets_ext4__fallocate_mode {};\n\nstruct trace_event_data_offsets_ext4_fallocate_exit {};\n\nstruct trace_event_data_offsets_ext4_unlink_enter {};\n\nstruct trace_event_data_offsets_ext4_unlink_exit {};\n\nstruct trace_event_data_offsets_ext4__truncate {};\n\nstruct trace_event_data_offsets_ext4_ext_convert_to_initialized_enter {};\n\nstruct trace_event_data_offsets_ext4_ext_convert_to_initialized_fastpath {};\n\nstruct trace_event_data_offsets_ext4__map_blocks_enter {};\n\nstruct trace_event_data_offsets_ext4__map_blocks_exit {};\n\nstruct trace_event_data_offsets_ext4_ext_load_extent {};\n\nstruct trace_event_data_offsets_ext4_load_inode {};\n\nstruct trace_event_data_offsets_ext4_journal_start {};\n\nstruct trace_event_data_offsets_ext4_journal_start_reserved {};\n\nstruct trace_event_data_offsets_ext4__trim {};\n\nstruct trace_event_data_offsets_ext4_ext_handle_unwritten_extents {};\n\nstruct trace_event_data_offsets_ext4_get_implied_cluster_alloc_exit {};\n\nstruct trace_event_data_offsets_ext4_ext_put_in_cache {};\n\nstruct trace_event_data_offsets_ext4_ext_in_cache {};\n\nstruct trace_event_data_offsets_ext4_find_delalloc_range {};\n\nstruct trace_event_data_offsets_ext4_get_reserved_cluster_alloc {};\n\nstruct trace_event_data_offsets_ext4_ext_show_extent {};\n\nstruct trace_event_data_offsets_ext4_remove_blocks {};\n\nstruct trace_event_data_offsets_ext4_ext_rm_leaf {};\n\nstruct trace_event_data_offsets_ext4_ext_rm_idx {};\n\nstruct trace_event_data_offsets_ext4_ext_remove_space {};\n\nstruct trace_event_data_offsets_ext4_ext_remove_space_done {};\n\nstruct trace_event_data_offsets_ext4__es_extent {};\n\nstruct trace_event_data_offsets_ext4_es_remove_extent {};\n\nstruct trace_event_data_offsets_ext4_es_find_extent_range_enter {};\n\nstruct trace_event_data_offsets_ext4_es_find_extent_range_exit {};\n\nstruct trace_event_data_offsets_ext4_es_lookup_extent_enter {};\n\nstruct trace_event_data_offsets_ext4_es_lookup_extent_exit {};\n\nstruct trace_event_data_offsets_ext4__es_shrink_enter {};\n\nstruct trace_event_data_offsets_ext4_es_shrink_scan_exit {};\n\nstruct trace_event_data_offsets_ext4_collapse_range {};\n\nstruct trace_event_data_offsets_ext4_insert_range {};\n\nstruct trace_event_data_offsets_ext4_es_shrink {};\n\nstruct trace_event_data_offsets_ext4_es_insert_delayed_block {};\n\nstruct trace_event_data_offsets_ext4_fsmap_class {};\n\nstruct trace_event_data_offsets_ext4_getfsmap_class {};\n\nstruct trace_event_data_offsets_ext4_shutdown {};\n\nstruct trace_event_data_offsets_ext4_error {};\n\ntypedef void (*btf_trace_ext4_other_inode_update_time)(void *, struct inode *, ino_t);\n\ntypedef void (*btf_trace_ext4_free_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_request_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_allocate_inode)(void *, struct inode *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_evict_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_drop_inode)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_nfs_commit_metadata)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_mark_inode_dirty)(void *, struct inode *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_begin_ordered_truncate)(void *, struct inode *, loff_t);\n\ntypedef void (*btf_trace_ext4_write_begin)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_da_write_begin)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_journalled_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_da_write_end)(void *, struct inode *, loff_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_writepages)(void *, struct inode *, struct writeback_control *);\n\ntypedef void (*btf_trace_ext4_da_write_pages)(void *, struct inode *, long unsigned int, struct writeback_control *);\n\ntypedef void (*btf_trace_ext4_da_write_pages_extent)(void *, struct inode *, struct ext4_map_blocks *);\n\ntypedef void (*btf_trace_ext4_writepages_result)(void *, struct inode *, struct writeback_control *, int, int);\n\ntypedef void (*btf_trace_ext4_writepage)(void *, struct page *);\n\ntypedef void (*btf_trace_ext4_readpage)(void *, struct page *);\n\ntypedef void (*btf_trace_ext4_releasepage)(void *, struct page *);\n\ntypedef void (*btf_trace_ext4_invalidatepage)(void *, struct page *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_journalled_invalidatepage)(void *, struct page *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_discard_blocks)(void *, struct super_block *, long long unsigned int, long long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_new_inode_pa)(void *, struct ext4_allocation_context *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_new_group_pa)(void *, struct ext4_allocation_context *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_mb_release_inode_pa)(void *, struct ext4_prealloc_space *, long long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_release_group_pa)(void *, struct super_block *, struct ext4_prealloc_space *);\n\ntypedef void (*btf_trace_ext4_discard_preallocations)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_mb_discard_preallocations)(void *, struct super_block *, int);\n\ntypedef void (*btf_trace_ext4_request_blocks)(void *, struct ext4_allocation_request *);\n\ntypedef void (*btf_trace_ext4_allocate_blocks)(void *, struct ext4_allocation_request *, long long unsigned int);\n\ntypedef void (*btf_trace_ext4_free_blocks)(void *, struct inode *, __u64, long unsigned int, int);\n\ntypedef void (*btf_trace_ext4_sync_file_enter)(void *, struct file *, int);\n\ntypedef void (*btf_trace_ext4_sync_file_exit)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_sync_fs)(void *, struct super_block *, int);\n\ntypedef void (*btf_trace_ext4_alloc_da_blocks)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_mballoc_alloc)(void *, struct ext4_allocation_context *);\n\ntypedef void (*btf_trace_ext4_mballoc_prealloc)(void *, struct ext4_allocation_context *);\n\ntypedef void (*btf_trace_ext4_mballoc_discard)(void *, struct super_block *, struct inode *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_mballoc_free)(void *, struct super_block *, struct inode *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_forget)(void *, struct inode *, int, __u64);\n\ntypedef void (*btf_trace_ext4_da_update_reserve_space)(void *, struct inode *, int, int);\n\ntypedef void (*btf_trace_ext4_da_reserve_space)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_da_release_space)(void *, struct inode *, int);\n\ntypedef void (*btf_trace_ext4_mb_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_mb_buddy_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_read_block_bitmap_load)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_load_inode_bitmap)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_direct_IO_enter)(void *, struct inode *, loff_t, long unsigned int, int);\n\ntypedef void (*btf_trace_ext4_direct_IO_exit)(void *, struct inode *, loff_t, long unsigned int, int, int);\n\ntypedef void (*btf_trace_ext4_fallocate_enter)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_punch_hole)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_zero_range)(void *, struct inode *, loff_t, loff_t, int);\n\ntypedef void (*btf_trace_ext4_fallocate_exit)(void *, struct inode *, loff_t, unsigned int, int);\n\ntypedef void (*btf_trace_ext4_unlink_enter)(void *, struct inode *, struct dentry *);\n\ntypedef void (*btf_trace_ext4_unlink_exit)(void *, struct dentry *, int);\n\ntypedef void (*btf_trace_ext4_truncate_enter)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_truncate_exit)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_ext_convert_to_initialized_enter)(void *, struct inode *, struct ext4_map_blocks *, struct ext4_extent *);\n\ntypedef void (*btf_trace_ext4_ext_convert_to_initialized_fastpath)(void *, struct inode *, struct ext4_map_blocks *, struct ext4_extent *, struct ext4_extent *);\n\ntypedef void (*btf_trace_ext4_ext_map_blocks_enter)(void *, struct inode *, ext4_lblk_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_ind_map_blocks_enter)(void *, struct inode *, ext4_lblk_t, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ext4_ext_map_blocks_exit)(void *, struct inode *, unsigned int, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_ind_map_blocks_exit)(void *, struct inode *, unsigned int, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_ext_load_extent)(void *, struct inode *, ext4_lblk_t, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_load_inode)(void *, struct inode *);\n\ntypedef void (*btf_trace_ext4_journal_start)(void *, struct super_block *, int, int, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_journal_start_reserved)(void *, struct super_block *, int, long unsigned int);\n\ntypedef void (*btf_trace_ext4_trim_extent)(void *, struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_trim_all_free)(void *, struct super_block *, ext4_group_t, ext4_grpblk_t, ext4_grpblk_t);\n\ntypedef void (*btf_trace_ext4_ext_handle_unwritten_extents)(void *, struct inode *, struct ext4_map_blocks *, int, unsigned int, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_get_implied_cluster_alloc_exit)(void *, struct super_block *, struct ext4_map_blocks *, int);\n\ntypedef void (*btf_trace_ext4_ext_put_in_cache)(void *, struct inode *, ext4_lblk_t, unsigned int, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_in_cache)(void *, struct inode *, ext4_lblk_t, int);\n\ntypedef void (*btf_trace_ext4_find_delalloc_range)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int, int, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_get_reserved_cluster_alloc)(void *, struct inode *, ext4_lblk_t, unsigned int);\n\ntypedef void (*btf_trace_ext4_ext_show_extent)(void *, struct inode *, ext4_lblk_t, ext4_fsblk_t, short unsigned int);\n\ntypedef void (*btf_trace_ext4_remove_blocks)(void *, struct inode *, struct ext4_extent *, ext4_lblk_t, ext4_fsblk_t, struct partial_cluster *);\n\ntypedef void (*btf_trace_ext4_ext_rm_leaf)(void *, struct inode *, ext4_lblk_t, struct ext4_extent *, struct partial_cluster *);\n\ntypedef void (*btf_trace_ext4_ext_rm_idx)(void *, struct inode *, ext4_fsblk_t);\n\ntypedef void (*btf_trace_ext4_ext_remove_space)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int);\n\ntypedef void (*btf_trace_ext4_ext_remove_space_done)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t, int, struct partial_cluster *, __le16);\n\ntypedef void (*btf_trace_ext4_es_insert_extent)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_cache_extent)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_remove_extent)(void *, struct inode *, ext4_lblk_t, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_find_extent_range_enter)(void *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_find_extent_range_exit)(void *, struct inode *, struct extent_status *);\n\ntypedef void (*btf_trace_ext4_es_lookup_extent_enter)(void *, struct inode *, ext4_lblk_t);\n\ntypedef void (*btf_trace_ext4_es_lookup_extent_exit)(void *, struct inode *, struct extent_status *, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_count)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_scan_enter)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_es_shrink_scan_exit)(void *, struct super_block *, int, int);\n\ntypedef void (*btf_trace_ext4_collapse_range)(void *, struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_ext4_insert_range)(void *, struct inode *, loff_t, loff_t);\n\ntypedef void (*btf_trace_ext4_es_shrink)(void *, struct super_block *, int, u64, int, int);\n\ntypedef void (*btf_trace_ext4_es_insert_delayed_block)(void *, struct inode *, struct extent_status *, bool);\n\ntypedef void (*btf_trace_ext4_fsmap_low_key)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_fsmap_high_key)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_fsmap_mapping)(void *, struct super_block *, u32, u32, u64, u64, u64);\n\ntypedef void (*btf_trace_ext4_getfsmap_low_key)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_getfsmap_high_key)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_getfsmap_mapping)(void *, struct super_block *, struct ext4_fsmap *);\n\ntypedef void (*btf_trace_ext4_shutdown)(void *, struct super_block *, long unsigned int);\n\ntypedef void (*btf_trace_ext4_error)(void *, struct super_block *, const char *, unsigned int);\n\nenum {\n\tOpt_bsd_df = 0,\n\tOpt_minix_df = 1,\n\tOpt_grpid = 2,\n\tOpt_nogrpid = 3,\n\tOpt_resgid = 4,\n\tOpt_resuid = 5,\n\tOpt_sb = 6,\n\tOpt_err_cont = 7,\n\tOpt_err_panic = 8,\n\tOpt_err_ro = 9,\n\tOpt_nouid32 = 10,\n\tOpt_debug = 11,\n\tOpt_removed = 12,\n\tOpt_user_xattr = 13,\n\tOpt_nouser_xattr = 14,\n\tOpt_acl = 15,\n\tOpt_noacl = 16,\n\tOpt_auto_da_alloc = 17,\n\tOpt_noauto_da_alloc = 18,\n\tOpt_noload = 19,\n\tOpt_commit = 20,\n\tOpt_min_batch_time = 21,\n\tOpt_max_batch_time = 22,\n\tOpt_journal_dev = 23,\n\tOpt_journal_path = 24,\n\tOpt_journal_checksum = 25,\n\tOpt_journal_async_commit = 26,\n\tOpt_abort = 27,\n\tOpt_data_journal = 28,\n\tOpt_data_ordered = 29,\n\tOpt_data_writeback = 30,\n\tOpt_data_err_abort = 31,\n\tOpt_data_err_ignore = 32,\n\tOpt_test_dummy_encryption = 33,\n\tOpt_usrjquota = 34,\n\tOpt_grpjquota = 35,\n\tOpt_offusrjquota = 36,\n\tOpt_offgrpjquota = 37,\n\tOpt_jqfmt_vfsold = 38,\n\tOpt_jqfmt_vfsv0 = 39,\n\tOpt_jqfmt_vfsv1 = 40,\n\tOpt_quota = 41,\n\tOpt_noquota = 42,\n\tOpt_barrier = 43,\n\tOpt_nobarrier = 44,\n\tOpt_err___2 = 45,\n\tOpt_usrquota = 46,\n\tOpt_grpquota = 47,\n\tOpt_prjquota = 48,\n\tOpt_i_version = 49,\n\tOpt_dax = 50,\n\tOpt_dax_always = 51,\n\tOpt_dax_inode = 52,\n\tOpt_dax_never = 53,\n\tOpt_stripe = 54,\n\tOpt_delalloc = 55,\n\tOpt_nodelalloc = 56,\n\tOpt_warn_on_error = 57,\n\tOpt_nowarn_on_error = 58,\n\tOpt_mblk_io_submit = 59,\n\tOpt_lazytime = 60,\n\tOpt_nolazytime = 61,\n\tOpt_debug_want_extra_isize = 62,\n\tOpt_nomblk_io_submit = 63,\n\tOpt_block_validity = 64,\n\tOpt_noblock_validity = 65,\n\tOpt_inode_readahead_blks = 66,\n\tOpt_journal_ioprio = 67,\n\tOpt_dioread_nolock = 68,\n\tOpt_dioread_lock = 69,\n\tOpt_discard = 70,\n\tOpt_nodiscard = 71,\n\tOpt_init_itable = 72,\n\tOpt_noinit_itable = 73,\n\tOpt_max_dir_size_kb = 74,\n\tOpt_nojournal_checksum = 75,\n\tOpt_nombcache = 76,\n};\n\nstruct mount_opts {\n\tint token;\n\tint mount_opt;\n\tint flags;\n};\n\nstruct ext4_mount_options {\n\tlong unsigned int s_mount_opt;\n\tlong unsigned int s_mount_opt2;\n\tkuid_t s_resuid;\n\tkgid_t s_resgid;\n\tlong unsigned int s_commit_interval;\n\tu32 s_min_batch_time;\n\tu32 s_max_batch_time;\n\tint s_jquota_fmt;\n\tchar *s_qf_names[3];\n};\n\nenum {\n\tattr_noop = 0,\n\tattr_delayed_allocation_blocks = 1,\n\tattr_session_write_kbytes = 2,\n\tattr_lifetime_write_kbytes = 3,\n\tattr_reserved_clusters = 4,\n\tattr_inode_readahead = 5,\n\tattr_trigger_test_error = 6,\n\tattr_first_error_time = 7,\n\tattr_last_error_time = 8,\n\tattr_feature = 9,\n\tattr_pointer_ui = 10,\n\tattr_pointer_ul = 11,\n\tattr_pointer_u64 = 12,\n\tattr_pointer_u8 = 13,\n\tattr_pointer_string = 14,\n\tattr_pointer_atomic = 15,\n\tattr_journal_task = 16,\n};\n\nenum {\n\tptr_explicit = 0,\n\tptr_ext4_sb_info_offset = 1,\n\tptr_ext4_super_block_offset = 2,\n};\n\nstruct ext4_attr {\n\tstruct attribute attr;\n\tshort int attr_id;\n\tshort int attr_ptr;\n\tshort unsigned int attr_size;\n\tunion {\n\t\tint offset;\n\t\tvoid *explicit_ptr;\n\t} u;\n};\n\nstruct ext4_xattr_header {\n\t__le32 h_magic;\n\t__le32 h_refcount;\n\t__le32 h_blocks;\n\t__le32 h_hash;\n\t__le32 h_checksum;\n\t__u32 h_reserved[3];\n};\n\nstruct ext4_xattr_block_find {\n\tstruct ext4_xattr_search s;\n\tstruct buffer_head *bh;\n};\n\ntypedef struct {\n\t__le16 e_tag;\n\t__le16 e_perm;\n\t__le32 e_id;\n} ext4_acl_entry;\n\ntypedef struct {\n\t__le32 a_version;\n} ext4_acl_header;\n\nstruct commit_header {\n\t__be32 h_magic;\n\t__be32 h_blocktype;\n\t__be32 h_sequence;\n\tunsigned char h_chksum_type;\n\tunsigned char h_chksum_size;\n\tunsigned char h_padding[2];\n\t__be32 h_chksum[8];\n\t__be64 h_commit_sec;\n\t__be32 h_commit_nsec;\n};\n\nstruct journal_block_tag3_s {\n\t__be32 t_blocknr;\n\t__be32 t_flags;\n\t__be32 t_blocknr_high;\n\t__be32 t_checksum;\n};\n\ntypedef struct journal_block_tag3_s journal_block_tag3_t;\n\nstruct journal_block_tag_s {\n\t__be32 t_blocknr;\n\t__be16 t_checksum;\n\t__be16 t_flags;\n\t__be32 t_blocknr_high;\n};\n\ntypedef struct journal_block_tag_s journal_block_tag_t;\n\nstruct jbd2_journal_block_tail {\n\t__be32 t_checksum;\n};\n\nstruct jbd2_journal_revoke_header_s {\n\tjournal_header_t r_header;\n\t__be32 r_count;\n};\n\ntypedef struct jbd2_journal_revoke_header_s jbd2_journal_revoke_header_t;\n\nstruct recovery_info {\n\ttid_t start_transaction;\n\ttid_t end_transaction;\n\tint nr_replays;\n\tint nr_revokes;\n\tint nr_revoke_hits;\n};\n\nenum passtype {\n\tPASS_SCAN = 0,\n\tPASS_REVOKE = 1,\n\tPASS_REPLAY = 2,\n};\n\nstruct jbd2_revoke_table_s {\n\tint hash_size;\n\tint hash_shift;\n\tstruct list_head *hash_table;\n};\n\nstruct jbd2_revoke_record_s {\n\tstruct list_head hash;\n\ttid_t sequence;\n\tlong long unsigned int blocknr;\n};\n\nstruct trace_event_raw_jbd2_checkpoint {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar sync_commit;\n\tint transaction;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_end_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar sync_commit;\n\tint transaction;\n\tint head;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_submit_inode_data {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tino_t ino;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_start_class {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint requested_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_extend {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint buffer_credits;\n\tint requested_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_handle_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int tid;\n\tunsigned int type;\n\tunsigned int line_no;\n\tint interval;\n\tint sync;\n\tint requested_blocks;\n\tint dirtied_blocks;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_run_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int tid;\n\tlong unsigned int wait;\n\tlong unsigned int request_delay;\n\tlong unsigned int running;\n\tlong unsigned int locked;\n\tlong unsigned int flushing;\n\tlong unsigned int logging;\n\t__u32 handle_count;\n\t__u32 blocks;\n\t__u32 blocks_logged;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_checkpoint_stats {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int tid;\n\tlong unsigned int chp_time;\n\t__u32 forced_to_close;\n\t__u32 written;\n\t__u32 dropped;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_update_log_tail {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\ttid_t tail_sequence;\n\ttid_t first_tid;\n\tlong unsigned int block_nr;\n\tlong unsigned int freed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_write_superblock {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint write_op;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_jbd2_lock_buffer_stall {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int stall_ms;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_jbd2_checkpoint {};\n\nstruct trace_event_data_offsets_jbd2_commit {};\n\nstruct trace_event_data_offsets_jbd2_end_commit {};\n\nstruct trace_event_data_offsets_jbd2_submit_inode_data {};\n\nstruct trace_event_data_offsets_jbd2_handle_start_class {};\n\nstruct trace_event_data_offsets_jbd2_handle_extend {};\n\nstruct trace_event_data_offsets_jbd2_handle_stats {};\n\nstruct trace_event_data_offsets_jbd2_run_stats {};\n\nstruct trace_event_data_offsets_jbd2_checkpoint_stats {};\n\nstruct trace_event_data_offsets_jbd2_update_log_tail {};\n\nstruct trace_event_data_offsets_jbd2_write_superblock {};\n\nstruct trace_event_data_offsets_jbd2_lock_buffer_stall {};\n\ntypedef void (*btf_trace_jbd2_checkpoint)(void *, journal_t *, int);\n\ntypedef void (*btf_trace_jbd2_start_commit)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_locking)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_flushing)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_commit_logging)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_drop_transaction)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_end_commit)(void *, journal_t *, transaction_t *);\n\ntypedef void (*btf_trace_jbd2_submit_inode_data)(void *, struct inode *);\n\ntypedef void (*btf_trace_jbd2_handle_start)(void *, dev_t, long unsigned int, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_jbd2_handle_restart)(void *, dev_t, long unsigned int, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_jbd2_handle_extend)(void *, dev_t, long unsigned int, unsigned int, unsigned int, int, int);\n\ntypedef void (*btf_trace_jbd2_handle_stats)(void *, dev_t, long unsigned int, unsigned int, unsigned int, int, int, int, int);\n\ntypedef void (*btf_trace_jbd2_run_stats)(void *, dev_t, long unsigned int, struct transaction_run_stats_s *);\n\ntypedef void (*btf_trace_jbd2_checkpoint_stats)(void *, dev_t, long unsigned int, struct transaction_chp_stats_s *);\n\ntypedef void (*btf_trace_jbd2_update_log_tail)(void *, journal_t *, tid_t, long unsigned int, long unsigned int);\n\ntypedef void (*btf_trace_jbd2_write_superblock)(void *, journal_t *, int);\n\ntypedef void (*btf_trace_jbd2_lock_buffer_stall)(void *, dev_t, long unsigned int);\n\nstruct jbd2_stats_proc_session {\n\tjournal_t *journal;\n\tstruct transaction_stats_s *stats;\n\tint start;\n\tint max;\n};\n\nstruct ramfs_mount_opts {\n\tumode_t mode;\n};\n\nstruct ramfs_fs_info {\n\tstruct ramfs_mount_opts mount_opts;\n};\n\nenum ramfs_param {\n\tOpt_mode___3 = 0,\n};\n\nenum hugetlbfs_size_type {\n\tNO_SIZE = 0,\n\tSIZE_STD = 1,\n\tSIZE_PERCENT = 2,\n};\n\nstruct hugetlbfs_fs_context {\n\tstruct hstate *hstate;\n\tlong long unsigned int max_size_opt;\n\tlong long unsigned int min_size_opt;\n\tlong int max_hpages;\n\tlong int nr_inodes;\n\tlong int min_hpages;\n\tenum hugetlbfs_size_type max_val_type;\n\tenum hugetlbfs_size_type min_val_type;\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nenum hugetlb_param {\n\tOpt_gid___4 = 0,\n\tOpt_min_size = 1,\n\tOpt_mode___4 = 2,\n\tOpt_nr_inodes___2 = 3,\n\tOpt_pagesize = 4,\n\tOpt_size___2 = 5,\n\tOpt_uid___3 = 6,\n};\n\ntypedef u16 wchar_t;\n\nstruct nls_table {\n\tconst char *charset;\n\tconst char *alias;\n\tint (*uni2char)(wchar_t, unsigned char *, int);\n\tint (*char2uni)(const unsigned char *, int, wchar_t *);\n\tconst unsigned char *charset2lower;\n\tconst unsigned char *charset2upper;\n\tstruct module *owner;\n\tstruct nls_table *next;\n};\n\nstruct fat_mount_options {\n\tkuid_t fs_uid;\n\tkgid_t fs_gid;\n\tshort unsigned int fs_fmask;\n\tshort unsigned int fs_dmask;\n\tshort unsigned int codepage;\n\tint time_offset;\n\tchar *iocharset;\n\tshort unsigned int shortname;\n\tunsigned char name_check;\n\tunsigned char errors;\n\tunsigned char nfs;\n\tshort unsigned int allow_utime;\n\tunsigned int quiet: 1;\n\tunsigned int showexec: 1;\n\tunsigned int sys_immutable: 1;\n\tunsigned int dotsOK: 1;\n\tunsigned int isvfat: 1;\n\tunsigned int utf8: 1;\n\tunsigned int unicode_xlate: 1;\n\tunsigned int numtail: 1;\n\tunsigned int flush: 1;\n\tunsigned int nocase: 1;\n\tunsigned int usefree: 1;\n\tunsigned int tz_set: 1;\n\tunsigned int rodir: 1;\n\tunsigned int discard: 1;\n\tunsigned int dos1xfloppy: 1;\n};\n\nstruct fatent_operations;\n\nstruct msdos_sb_info {\n\tshort unsigned int sec_per_clus;\n\tshort unsigned int cluster_bits;\n\tunsigned int cluster_size;\n\tunsigned char fats;\n\tunsigned char fat_bits;\n\tshort unsigned int fat_start;\n\tlong unsigned int fat_length;\n\tlong unsigned int dir_start;\n\tshort unsigned int dir_entries;\n\tlong unsigned int data_start;\n\tlong unsigned int max_cluster;\n\tlong unsigned int root_cluster;\n\tlong unsigned int fsinfo_sector;\n\tstruct mutex fat_lock;\n\tstruct mutex nfs_build_inode_lock;\n\tstruct mutex s_lock;\n\tunsigned int prev_free;\n\tunsigned int free_clusters;\n\tunsigned int free_clus_valid;\n\tstruct fat_mount_options options;\n\tstruct nls_table *nls_disk;\n\tstruct nls_table *nls_io;\n\tconst void *dir_ops;\n\tint dir_per_block;\n\tint dir_per_block_bits;\n\tunsigned int vol_id;\n\tint fatent_shift;\n\tconst struct fatent_operations *fatent_ops;\n\tstruct inode *fat_inode;\n\tstruct inode *fsinfo_inode;\n\tstruct ratelimit_state ratelimit;\n\tspinlock_t inode_hash_lock;\n\tstruct hlist_head inode_hashtable[256];\n\tspinlock_t dir_hash_lock;\n\tstruct hlist_head dir_hashtable[256];\n\tunsigned int dirty;\n\tstruct callback_head rcu;\n};\n\nstruct fat_entry;\n\nstruct fatent_operations {\n\tvoid (*ent_blocknr)(struct super_block *, int, int *, sector_t *);\n\tvoid (*ent_set_ptr)(struct fat_entry *, int);\n\tint (*ent_bread)(struct super_block *, struct fat_entry *, int, sector_t);\n\tint (*ent_get)(struct fat_entry *);\n\tvoid (*ent_put)(struct fat_entry *, int);\n\tint (*ent_next)(struct fat_entry *);\n};\n\nstruct msdos_inode_info {\n\tspinlock_t cache_lru_lock;\n\tstruct list_head cache_lru;\n\tint nr_caches;\n\tunsigned int cache_valid_id;\n\tloff_t mmu_private;\n\tint i_start;\n\tint i_logstart;\n\tint i_attrs;\n\tloff_t i_pos;\n\tstruct hlist_node i_fat_hash;\n\tstruct hlist_node i_dir_hash;\n\tstruct rw_semaphore truncate_lock;\n\tstruct inode vfs_inode;\n};\n\nstruct fat_entry {\n\tint entry;\n\tunion {\n\t\tu8 *ent12_p[2];\n\t\t__le16 *ent16_p;\n\t\t__le32 *ent32_p;\n\t} u;\n\tint nr_bhs;\n\tstruct buffer_head *bhs[2];\n\tstruct inode *fat_inode;\n};\n\nstruct fat_cache {\n\tstruct list_head cache_list;\n\tint nr_contig;\n\tint fcluster;\n\tint dcluster;\n};\n\nstruct fat_cache_id {\n\tunsigned int id;\n\tint nr_contig;\n\tint fcluster;\n\tint dcluster;\n};\n\nstruct compat_dirent {\n\tu32 d_ino;\n\tcompat_off_t d_off;\n\tu16 d_reclen;\n\tchar d_name[256];\n};\n\nenum utf16_endian {\n\tUTF16_HOST_ENDIAN = 0,\n\tUTF16_LITTLE_ENDIAN = 1,\n\tUTF16_BIG_ENDIAN = 2,\n};\n\nstruct __fat_dirent {\n\tlong int d_ino;\n\t__kernel_off_t d_off;\n\tshort unsigned int d_reclen;\n\tchar d_name[256];\n};\n\nstruct msdos_dir_entry {\n\t__u8 name[11];\n\t__u8 attr;\n\t__u8 lcase;\n\t__u8 ctime_cs;\n\t__le16 ctime;\n\t__le16 cdate;\n\t__le16 adate;\n\t__le16 starthi;\n\t__le16 time;\n\t__le16 date;\n\t__le16 start;\n\t__le32 size;\n};\n\nstruct msdos_dir_slot {\n\t__u8 id;\n\t__u8 name0_4[10];\n\t__u8 attr;\n\t__u8 reserved;\n\t__u8 alias_checksum;\n\t__u8 name5_10[12];\n\t__le16 start;\n\t__u8 name11_12[4];\n};\n\nstruct fat_slot_info {\n\tloff_t i_pos;\n\tloff_t slot_off;\n\tint nr_slots;\n\tstruct msdos_dir_entry *de;\n\tstruct buffer_head *bh;\n};\n\ntypedef long long unsigned int llu;\n\nenum {\n\tPARSE_INVALID = 1,\n\tPARSE_NOT_LONGNAME = 2,\n\tPARSE_EOF = 3,\n};\n\nstruct fat_ioctl_filldir_callback {\n\tstruct dir_context ctx;\n\tvoid *dirent;\n\tint result;\n\tconst char *longname;\n\tint long_len;\n\tconst char *shortname;\n\tint short_len;\n};\n\nstruct fatent_ra {\n\tsector_t cur;\n\tsector_t limit;\n\tunsigned int ra_blocks;\n\tsector_t ra_advance;\n\tsector_t ra_next;\n\tsector_t ra_limit;\n};\n\nstruct fat_boot_sector {\n\t__u8 ignored[3];\n\t__u8 system_id[8];\n\t__u8 sector_size[2];\n\t__u8 sec_per_clus;\n\t__le16 reserved;\n\t__u8 fats;\n\t__u8 dir_entries[2];\n\t__u8 sectors[2];\n\t__u8 media;\n\t__le16 fat_length;\n\t__le16 secs_track;\n\t__le16 heads;\n\t__le32 hidden;\n\t__le32 total_sect;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat16;\n\t\tstruct {\n\t\t\t__le32 length;\n\t\t\t__le16 flags;\n\t\t\t__u8 version[2];\n\t\t\t__le32 root_cluster;\n\t\t\t__le16 info_sector;\n\t\t\t__le16 backup_boot;\n\t\t\t__le16 reserved2[6];\n\t\t\t__u8 drive_number;\n\t\t\t__u8 state;\n\t\t\t__u8 signature;\n\t\t\t__u8 vol_id[4];\n\t\t\t__u8 vol_label[11];\n\t\t\t__u8 fs_type[8];\n\t\t} fat32;\n\t};\n};\n\nstruct fat_boot_fsinfo {\n\t__le32 signature1;\n\t__le32 reserved1[120];\n\t__le32 signature2;\n\t__le32 free_clusters;\n\t__le32 next_cluster;\n\t__le32 reserved2[4];\n};\n\nstruct fat_bios_param_block {\n\tu16 fat_sector_size;\n\tu8 fat_sec_per_clus;\n\tu16 fat_reserved;\n\tu8 fat_fats;\n\tu16 fat_dir_entries;\n\tu16 fat_sectors;\n\tu16 fat_fat_length;\n\tu32 fat_total_sect;\n\tu8 fat16_state;\n\tu32 fat16_vol_id;\n\tu32 fat32_length;\n\tu32 fat32_root_cluster;\n\tu16 fat32_info_sector;\n\tu8 fat32_state;\n\tu32 fat32_vol_id;\n};\n\nstruct fat_floppy_defaults {\n\tunsigned int nr_sectors;\n\tunsigned int sec_per_clus;\n\tunsigned int dir_entries;\n\tunsigned int media;\n\tunsigned int fat_length;\n};\n\nenum {\n\tOpt_check_n = 0,\n\tOpt_check_r = 1,\n\tOpt_check_s = 2,\n\tOpt_uid___4 = 3,\n\tOpt_gid___5 = 4,\n\tOpt_umask = 5,\n\tOpt_dmask = 6,\n\tOpt_fmask = 7,\n\tOpt_allow_utime = 8,\n\tOpt_codepage = 9,\n\tOpt_usefree = 10,\n\tOpt_nocase = 11,\n\tOpt_quiet = 12,\n\tOpt_showexec = 13,\n\tOpt_debug___2 = 14,\n\tOpt_immutable = 15,\n\tOpt_dots = 16,\n\tOpt_nodots = 17,\n\tOpt_charset = 18,\n\tOpt_shortname_lower = 19,\n\tOpt_shortname_win95 = 20,\n\tOpt_shortname_winnt = 21,\n\tOpt_shortname_mixed = 22,\n\tOpt_utf8_no = 23,\n\tOpt_utf8_yes = 24,\n\tOpt_uni_xl_no = 25,\n\tOpt_uni_xl_yes = 26,\n\tOpt_nonumtail_no = 27,\n\tOpt_nonumtail_yes = 28,\n\tOpt_obsolete = 29,\n\tOpt_flush = 30,\n\tOpt_tz_utc = 31,\n\tOpt_rodir = 32,\n\tOpt_err_cont___2 = 33,\n\tOpt_err_panic___2 = 34,\n\tOpt_err_ro___2 = 35,\n\tOpt_discard___2 = 36,\n\tOpt_nfs = 37,\n\tOpt_time_offset = 38,\n\tOpt_nfs_stale_rw = 39,\n\tOpt_nfs_nostale_ro = 40,\n\tOpt_err___3 = 41,\n\tOpt_dos1xfloppy = 42,\n};\n\nstruct fat_fid {\n\tu32 i_gen;\n\tu32 i_pos_low;\n\tu16 i_pos_hi;\n\tu16 parent_i_pos_hi;\n\tu32 parent_i_pos_low;\n\tu32 parent_i_gen;\n};\n\nstruct shortname_info {\n\tunsigned char lower: 1;\n\tunsigned char upper: 1;\n\tunsigned char valid: 1;\n};\n\nstruct iso_directory_record {\n\t__u8 length[1];\n\t__u8 ext_attr_length[1];\n\t__u8 extent[8];\n\t__u8 size[8];\n\t__u8 date[7];\n\t__u8 flags[1];\n\t__u8 file_unit_size[1];\n\t__u8 interleave[1];\n\t__u8 volume_sequence_number[4];\n\t__u8 name_len[1];\n\tchar name[0];\n};\n\nstruct iso_inode_info {\n\tlong unsigned int i_iget5_block;\n\tlong unsigned int i_iget5_offset;\n\tunsigned int i_first_extent;\n\tunsigned char i_file_format;\n\tunsigned char i_format_parm[3];\n\tlong unsigned int i_next_section_block;\n\tlong unsigned int i_next_section_offset;\n\toff_t i_section_size;\n\tstruct inode vfs_inode;\n};\n\nstruct isofs_sb_info {\n\tlong unsigned int s_ninodes;\n\tlong unsigned int s_nzones;\n\tlong unsigned int s_firstdatazone;\n\tlong unsigned int s_log_zone_size;\n\tlong unsigned int s_max_size;\n\tint s_rock_offset;\n\ts32 s_sbsector;\n\tunsigned char s_joliet_level;\n\tunsigned char s_mapping;\n\tunsigned char s_check;\n\tunsigned char s_session;\n\tunsigned int s_high_sierra: 1;\n\tunsigned int s_rock: 2;\n\tunsigned int s_utf8: 1;\n\tunsigned int s_cruft: 1;\n\tunsigned int s_nocompress: 1;\n\tunsigned int s_hide: 1;\n\tunsigned int s_showassoc: 1;\n\tunsigned int s_overriderockperm: 1;\n\tunsigned int s_uid_set: 1;\n\tunsigned int s_gid_set: 1;\n\tumode_t s_fmode;\n\tumode_t s_dmode;\n\tkgid_t s_gid;\n\tkuid_t s_uid;\n\tstruct nls_table *s_nls_iocharset;\n};\n\nstruct scsi_sense_hdr {\n\tu8 response_code;\n\tu8 sense_key;\n\tu8 asc;\n\tu8 ascq;\n\tu8 byte4;\n\tu8 byte5;\n\tu8 byte6;\n\tu8 additional_length;\n};\n\nstruct cdrom_msf0 {\n\t__u8 minute;\n\t__u8 second;\n\t__u8 frame;\n};\n\nunion cdrom_addr {\n\tstruct cdrom_msf0 msf;\n\tint lba;\n};\n\nstruct cdrom_tocentry {\n\t__u8 cdte_track;\n\t__u8 cdte_adr: 4;\n\t__u8 cdte_ctrl: 4;\n\t__u8 cdte_format;\n\tunion cdrom_addr cdte_addr;\n\t__u8 cdte_datamode;\n};\n\nstruct cdrom_multisession {\n\tunion cdrom_addr addr;\n\t__u8 xa_flag;\n\t__u8 addr_format;\n};\n\nstruct cdrom_mcn {\n\t__u8 medium_catalog_number[14];\n};\n\nstruct packet_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct scsi_sense_hdr *sshdr;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tvoid *reserved[1];\n};\n\nstruct cdrom_device_ops;\n\nstruct cdrom_device_info {\n\tconst struct cdrom_device_ops *ops;\n\tstruct list_head list;\n\tstruct gendisk *disk;\n\tvoid *handle;\n\tint mask;\n\tint speed;\n\tint capacity;\n\tunsigned int options: 30;\n\tunsigned int mc_flags: 2;\n\tunsigned int vfs_events;\n\tunsigned int ioctl_events;\n\tint use_count;\n\tchar name[20];\n\t__u8 sanyo_slot: 2;\n\t__u8 keeplocked: 1;\n\t__u8 reserved: 5;\n\tint cdda_method;\n\t__u8 last_sense;\n\t__u8 media_written;\n\tshort unsigned int mmc3_profile;\n\tint for_data;\n\tint (*exit)(struct cdrom_device_info *);\n\tint mrw_mode_page;\n};\n\nstruct cdrom_device_ops {\n\tint (*open)(struct cdrom_device_info *, int);\n\tvoid (*release)(struct cdrom_device_info *);\n\tint (*drive_status)(struct cdrom_device_info *, int);\n\tunsigned int (*check_events)(struct cdrom_device_info *, unsigned int, int);\n\tint (*media_changed)(struct cdrom_device_info *, int);\n\tint (*tray_move)(struct cdrom_device_info *, int);\n\tint (*lock_door)(struct cdrom_device_info *, int);\n\tint (*select_speed)(struct cdrom_device_info *, int);\n\tint (*select_disc)(struct cdrom_device_info *, int);\n\tint (*get_last_session)(struct cdrom_device_info *, struct cdrom_multisession *);\n\tint (*get_mcn)(struct cdrom_device_info *, struct cdrom_mcn *);\n\tint (*reset)(struct cdrom_device_info *);\n\tint (*audio_ioctl)(struct cdrom_device_info *, unsigned int, void *);\n\tconst int capability;\n\tint (*generic_packet)(struct cdrom_device_info *, struct packet_command *);\n};\n\nstruct iso_volume_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 data[2041];\n};\n\nstruct iso_primary_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 unused1[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 unused3[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 opt_type_l_path_table[4];\n\t__u8 type_m_path_table[4];\n\t__u8 opt_type_m_path_table[4];\n\t__u8 root_directory_record[34];\n\tchar volume_set_id[128];\n\tchar publisher_id[128];\n\tchar preparer_id[128];\n\tchar application_id[128];\n\tchar copyright_file_id[37];\n\tchar abstract_file_id[37];\n\tchar bibliographic_file_id[37];\n\t__u8 creation_date[17];\n\t__u8 modification_date[17];\n\t__u8 expiration_date[17];\n\t__u8 effective_date[17];\n\t__u8 file_structure_version[1];\n\t__u8 unused4[1];\n\t__u8 application_data[512];\n\t__u8 unused5[653];\n};\n\nstruct iso_supplementary_descriptor {\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 flags[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 escape[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 opt_type_l_path_table[4];\n\t__u8 type_m_path_table[4];\n\t__u8 opt_type_m_path_table[4];\n\t__u8 root_directory_record[34];\n\tchar volume_set_id[128];\n\tchar publisher_id[128];\n\tchar preparer_id[128];\n\tchar application_id[128];\n\tchar copyright_file_id[37];\n\tchar abstract_file_id[37];\n\tchar bibliographic_file_id[37];\n\t__u8 creation_date[17];\n\t__u8 modification_date[17];\n\t__u8 expiration_date[17];\n\t__u8 effective_date[17];\n\t__u8 file_structure_version[1];\n\t__u8 unused4[1];\n\t__u8 application_data[512];\n\t__u8 unused5[653];\n};\n\nstruct hs_volume_descriptor {\n\t__u8 foo[8];\n\t__u8 type[1];\n\tchar id[5];\n\t__u8 version[1];\n\t__u8 data[2033];\n};\n\nstruct hs_primary_descriptor {\n\t__u8 foo[8];\n\t__u8 type[1];\n\t__u8 id[5];\n\t__u8 version[1];\n\t__u8 unused1[1];\n\tchar system_id[32];\n\tchar volume_id[32];\n\t__u8 unused2[8];\n\t__u8 volume_space_size[8];\n\t__u8 unused3[32];\n\t__u8 volume_set_size[4];\n\t__u8 volume_sequence_number[4];\n\t__u8 logical_block_size[4];\n\t__u8 path_table_size[8];\n\t__u8 type_l_path_table[4];\n\t__u8 unused4[28];\n\t__u8 root_directory_record[34];\n};\n\nenum isofs_file_format {\n\tisofs_file_normal = 0,\n\tisofs_file_sparse = 1,\n\tisofs_file_compressed = 2,\n};\n\nstruct iso9660_options {\n\tunsigned int rock: 1;\n\tunsigned int joliet: 1;\n\tunsigned int cruft: 1;\n\tunsigned int hide: 1;\n\tunsigned int showassoc: 1;\n\tunsigned int nocompress: 1;\n\tunsigned int overriderockperm: 1;\n\tunsigned int uid_set: 1;\n\tunsigned int gid_set: 1;\n\tunsigned int utf8: 1;\n\tunsigned char map;\n\tunsigned char check;\n\tunsigned int blocksize;\n\tumode_t fmode;\n\tumode_t dmode;\n\tkgid_t gid;\n\tkuid_t uid;\n\tchar *iocharset;\n\ts32 session;\n\ts32 sbsector;\n};\n\nenum {\n\tOpt_block = 0,\n\tOpt_check_r___2 = 1,\n\tOpt_check_s___2 = 2,\n\tOpt_cruft = 3,\n\tOpt_gid___6 = 4,\n\tOpt_ignore = 5,\n\tOpt_iocharset = 6,\n\tOpt_map_a = 7,\n\tOpt_map_n = 8,\n\tOpt_map_o = 9,\n\tOpt_mode___5 = 10,\n\tOpt_nojoliet = 11,\n\tOpt_norock = 12,\n\tOpt_sb___2 = 13,\n\tOpt_session = 14,\n\tOpt_uid___5 = 15,\n\tOpt_unhide = 16,\n\tOpt_utf8 = 17,\n\tOpt_err___4 = 18,\n\tOpt_nocompress = 19,\n\tOpt_hide = 20,\n\tOpt_showassoc = 21,\n\tOpt_dmode = 22,\n\tOpt_overriderockperm = 23,\n};\n\nstruct isofs_iget5_callback_data {\n\tlong unsigned int block;\n\tlong unsigned int offset;\n};\n\nstruct SU_SP_s {\n\t__u8 magic[2];\n\t__u8 skip;\n};\n\nstruct SU_CE_s {\n\t__u8 extent[8];\n\t__u8 offset[8];\n\t__u8 size[8];\n};\n\nstruct SU_ER_s {\n\t__u8 len_id;\n\t__u8 len_des;\n\t__u8 len_src;\n\t__u8 ext_ver;\n\t__u8 data[0];\n};\n\nstruct RR_RR_s {\n\t__u8 flags[1];\n};\n\nstruct RR_PX_s {\n\t__u8 mode[8];\n\t__u8 n_links[8];\n\t__u8 uid[8];\n\t__u8 gid[8];\n};\n\nstruct RR_PN_s {\n\t__u8 dev_high[8];\n\t__u8 dev_low[8];\n};\n\nstruct SL_component {\n\t__u8 flags;\n\t__u8 len;\n\t__u8 text[0];\n};\n\nstruct RR_SL_s {\n\t__u8 flags;\n\tstruct SL_component link;\n};\n\nstruct RR_NM_s {\n\t__u8 flags;\n\tchar name[0];\n};\n\nstruct RR_CL_s {\n\t__u8 location[8];\n};\n\nstruct RR_PL_s {\n\t__u8 location[8];\n};\n\nstruct stamp {\n\t__u8 time[7];\n};\n\nstruct RR_TF_s {\n\t__u8 flags;\n\tstruct stamp times[0];\n};\n\nstruct RR_ZF_s {\n\t__u8 algorithm[2];\n\t__u8 parms[2];\n\t__u8 real_size[8];\n};\n\nstruct rock_ridge {\n\t__u8 signature[2];\n\t__u8 len;\n\t__u8 version;\n\tunion {\n\t\tstruct SU_SP_s SP;\n\t\tstruct SU_CE_s CE;\n\t\tstruct SU_ER_s ER;\n\t\tstruct RR_RR_s RR;\n\t\tstruct RR_PX_s PX;\n\t\tstruct RR_PN_s PN;\n\t\tstruct RR_SL_s SL;\n\t\tstruct RR_NM_s NM;\n\t\tstruct RR_CL_s CL;\n\t\tstruct RR_PL_s PL;\n\t\tstruct RR_TF_s TF;\n\t\tstruct RR_ZF_s ZF;\n\t} u;\n};\n\nstruct rock_state {\n\tvoid *buffer;\n\tunsigned char *chr;\n\tint len;\n\tint cont_size;\n\tint cont_extent;\n\tint cont_offset;\n\tint cont_loops;\n\tstruct inode *inode;\n};\n\nstruct isofs_fid {\n\tu32 block;\n\tu16 offset;\n\tu16 parent_offset;\n\tu32 generation;\n\tu32 parent_block;\n\tu32 parent_generation;\n};\n\ntypedef unsigned char Byte;\n\ntypedef long unsigned int uLong;\n\nstruct internal_state;\n\nstruct z_stream_s {\n\tconst Byte *next_in;\n\tuLong avail_in;\n\tuLong total_in;\n\tByte *next_out;\n\tuLong avail_out;\n\tuLong total_out;\n\tchar *msg;\n\tstruct internal_state *state;\n\tvoid *workspace;\n\tint data_type;\n\tuLong adler;\n\tuLong reserved;\n};\n\nstruct internal_state {\n\tint dummy;\n};\n\ntypedef struct z_stream_s z_stream;\n\nstruct nfs_seqid_counter {\n\tktime_t create_time;\n\tint owner_id;\n\tint flags;\n\tu32 counter;\n\tspinlock_t lock;\n\tstruct list_head list;\n\tstruct rpc_wait_queue wait;\n};\n\nstruct nfs4_lock_state {\n\tstruct list_head ls_locks;\n\tstruct nfs4_state *ls_state;\n\tlong unsigned int ls_flags;\n\tstruct nfs_seqid_counter ls_seqid;\n\tnfs4_stateid ls_stateid;\n\trefcount_t ls_count;\n\tfl_owner_t ls_owner;\n};\n\nstruct sockaddr_in {\n\t__kernel_sa_family_t sin_family;\n\t__be16 sin_port;\n\tstruct in_addr sin_addr;\n\tunsigned char __pad[8];\n};\n\nstruct sockaddr_in6 {\n\tshort unsigned int sin6_family;\n\t__be16 sin6_port;\n\t__be32 sin6_flowinfo;\n\tstruct in6_addr sin6_addr;\n\t__u32 sin6_scope_id;\n};\n\nenum rpc_auth_flavors {\n\tRPC_AUTH_NULL = 0,\n\tRPC_AUTH_UNIX = 1,\n\tRPC_AUTH_SHORT = 2,\n\tRPC_AUTH_DES = 3,\n\tRPC_AUTH_KRB = 4,\n\tRPC_AUTH_GSS = 6,\n\tRPC_AUTH_MAXFLAVOR = 8,\n\tRPC_AUTH_GSS_KRB5 = 390003,\n\tRPC_AUTH_GSS_KRB5I = 390004,\n\tRPC_AUTH_GSS_KRB5P = 390005,\n\tRPC_AUTH_GSS_LKEY = 390006,\n\tRPC_AUTH_GSS_LKEYI = 390007,\n\tRPC_AUTH_GSS_LKEYP = 390008,\n\tRPC_AUTH_GSS_SPKM = 390009,\n\tRPC_AUTH_GSS_SPKMI = 390010,\n\tRPC_AUTH_GSS_SPKMP = 390011,\n};\n\nstruct xdr_netobj {\n\tunsigned int len;\n\tu8 *data;\n};\n\nstruct rpc_task_setup {\n\tstruct rpc_task *task;\n\tstruct rpc_clnt *rpc_client;\n\tstruct rpc_xprt *rpc_xprt;\n\tstruct rpc_cred *rpc_op_cred;\n\tconst struct rpc_message *rpc_message;\n\tconst struct rpc_call_ops *callback_ops;\n\tvoid *callback_data;\n\tstruct workqueue_struct *workqueue;\n\tshort unsigned int flags;\n\tsigned char priority;\n};\n\nenum rpc_display_format_t {\n\tRPC_DISPLAY_ADDR = 0,\n\tRPC_DISPLAY_PORT = 1,\n\tRPC_DISPLAY_PROTO = 2,\n\tRPC_DISPLAY_HEX_ADDR = 3,\n\tRPC_DISPLAY_HEX_PORT = 4,\n\tRPC_DISPLAY_NETID = 5,\n\tRPC_DISPLAY_MAX = 6,\n};\n\nenum xprt_transports {\n\tXPRT_TRANSPORT_UDP = 17,\n\tXPRT_TRANSPORT_TCP = 6,\n\tXPRT_TRANSPORT_BC_TCP = 2147483654,\n\tXPRT_TRANSPORT_RDMA = 256,\n\tXPRT_TRANSPORT_BC_RDMA = 2147483904,\n\tXPRT_TRANSPORT_LOCAL = 257,\n};\n\nstruct svc_xprt_class;\n\nstruct svc_xprt_ops;\n\nstruct svc_serv;\n\nstruct svc_xprt {\n\tstruct svc_xprt_class *xpt_class;\n\tconst struct svc_xprt_ops *xpt_ops;\n\tstruct kref xpt_ref;\n\tstruct list_head xpt_list;\n\tstruct list_head xpt_ready;\n\tlong unsigned int xpt_flags;\n\tstruct svc_serv *xpt_server;\n\tatomic_t xpt_reserved;\n\tatomic_t xpt_nr_rqsts;\n\tstruct mutex xpt_mutex;\n\tspinlock_t xpt_lock;\n\tvoid *xpt_auth_cache;\n\tstruct list_head xpt_deferred;\n\tstruct __kernel_sockaddr_storage xpt_local;\n\tsize_t xpt_locallen;\n\tstruct __kernel_sockaddr_storage xpt_remote;\n\tsize_t xpt_remotelen;\n\tchar xpt_remotebuf[58];\n\tstruct list_head xpt_users;\n\tstruct net *xpt_net;\n\tconst struct cred *xpt_cred;\n\tstruct rpc_xprt *xpt_bc_xprt;\n\tstruct rpc_xprt_switch *xpt_bc_xps;\n};\n\nstruct svc_program;\n\nstruct svc_stat {\n\tstruct svc_program *program;\n\tunsigned int netcnt;\n\tunsigned int netudpcnt;\n\tunsigned int nettcpcnt;\n\tunsigned int nettcpconn;\n\tunsigned int rpccnt;\n\tunsigned int rpcbadfmt;\n\tunsigned int rpcbadauth;\n\tunsigned int rpcbadclnt;\n};\n\nstruct svc_version;\n\nstruct svc_rqst;\n\nstruct svc_process_info;\n\nstruct svc_program {\n\tstruct svc_program *pg_next;\n\tu32 pg_prog;\n\tunsigned int pg_lovers;\n\tunsigned int pg_hivers;\n\tunsigned int pg_nvers;\n\tconst struct svc_version **pg_vers;\n\tchar *pg_name;\n\tchar *pg_class;\n\tstruct svc_stat *pg_stats;\n\tint (*pg_authenticate)(struct svc_rqst *);\n\t__be32 (*pg_init_request)(struct svc_rqst *, const struct svc_program *, struct svc_process_info *);\n\tint (*pg_rpcbind_set)(struct net *, const struct svc_program *, u32, int, short unsigned int, short unsigned int);\n};\n\nstruct rpc_pipe_msg {\n\tstruct list_head list;\n\tvoid *data;\n\tsize_t len;\n\tsize_t copied;\n\tint errno;\n};\n\nstruct rpc_pipe_ops {\n\tssize_t (*upcall)(struct file *, struct rpc_pipe_msg *, char *, size_t);\n\tssize_t (*downcall)(struct file *, const char *, size_t);\n\tvoid (*release_pipe)(struct inode *);\n\tint (*open_pipe)(struct inode *);\n\tvoid (*destroy_msg)(struct rpc_pipe_msg *);\n};\n\nstruct rpc_pipe {\n\tstruct list_head pipe;\n\tstruct list_head in_upcall;\n\tstruct list_head in_downcall;\n\tint pipelen;\n\tint nreaders;\n\tint nwriters;\n\tint flags;\n\tstruct delayed_work queue_timeout;\n\tconst struct rpc_pipe_ops *ops;\n\tspinlock_t lock;\n\tstruct dentry *dentry;\n};\n\nstruct rpc_iostats {\n\tspinlock_t om_lock;\n\tlong unsigned int om_ops;\n\tlong unsigned int om_ntrans;\n\tlong unsigned int om_timeouts;\n\tlong long unsigned int om_bytes_sent;\n\tlong long unsigned int om_bytes_recv;\n\tktime_t om_queue;\n\tktime_t om_rtt;\n\tktime_t om_execute;\n\tlong unsigned int om_error_status;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct rpc_create_args {\n\tstruct net *net;\n\tint protocol;\n\tstruct sockaddr *address;\n\tsize_t addrsize;\n\tstruct sockaddr *saddress;\n\tconst struct rpc_timeout *timeout;\n\tconst char *servername;\n\tconst char *nodename;\n\tconst struct rpc_program *program;\n\tu32 prognumber;\n\tu32 version;\n\trpc_authflavor_t authflavor;\n\tu32 nconnect;\n\tlong unsigned int flags;\n\tchar *client_name;\n\tstruct svc_xprt *bc_xprt;\n\tconst struct cred *cred;\n};\n\nstruct gss_api_mech;\n\nstruct gss_ctx {\n\tstruct gss_api_mech *mech_type;\n\tvoid *internal_ctx_id;\n\tunsigned int slack;\n\tunsigned int align;\n};\n\nstruct gss_api_ops;\n\nstruct pf_desc;\n\nstruct gss_api_mech {\n\tstruct list_head gm_list;\n\tstruct module *gm_owner;\n\tstruct rpcsec_gss_oid gm_oid;\n\tchar *gm_name;\n\tconst struct gss_api_ops *gm_ops;\n\tint gm_pf_num;\n\tstruct pf_desc *gm_pfs;\n\tconst char *gm_upcall_enctypes;\n};\n\nstruct auth_domain;\n\nstruct pf_desc {\n\tu32 pseudoflavor;\n\tu32 qop;\n\tu32 service;\n\tchar *name;\n\tchar *auth_domain_name;\n\tstruct auth_domain *domain;\n\tbool datatouch;\n};\n\nstruct auth_ops;\n\nstruct auth_domain {\n\tstruct kref ref;\n\tstruct hlist_node hash;\n\tchar *name;\n\tstruct auth_ops *flavour;\n\tstruct callback_head callback_head;\n};\n\nstruct gss_api_ops {\n\tint (*gss_import_sec_context)(const void *, size_t, struct gss_ctx *, time64_t *, gfp_t);\n\tu32 (*gss_get_mic)(struct gss_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*gss_verify_mic)(struct gss_ctx *, struct xdr_buf *, struct xdr_netobj *);\n\tu32 (*gss_wrap)(struct gss_ctx *, int, struct xdr_buf *, struct page **);\n\tu32 (*gss_unwrap)(struct gss_ctx *, int, int, struct xdr_buf *);\n\tvoid (*gss_delete_sec_context)(void *);\n};\n\nstruct pnfs_layout_range {\n\tu32 iomode;\n\tu64 offset;\n\tu64 length;\n};\n\nstruct pnfs_layout_hdr;\n\nstruct pnfs_layout_segment {\n\tstruct list_head pls_list;\n\tstruct list_head pls_lc_list;\n\tstruct list_head pls_commits;\n\tstruct pnfs_layout_range pls_range;\n\trefcount_t pls_refcount;\n\tu32 pls_seq;\n\tlong unsigned int pls_flags;\n\tstruct pnfs_layout_hdr *pls_layout;\n};\n\nstruct nfs_seqid {\n\tstruct nfs_seqid_counter *sequence;\n\tstruct list_head list;\n\tstruct rpc_task *task;\n};\n\nstruct nfs4_pathname {\n\tunsigned int ncomponents;\n\tstruct nfs4_string components[512];\n};\n\nstruct nfs4_fs_location {\n\tunsigned int nservers;\n\tstruct nfs4_string servers[10];\n\tstruct nfs4_pathname rootpath;\n};\n\nstruct nfs4_fs_locations {\n\tstruct nfs_fattr fattr;\n\tconst struct nfs_server *server;\n\tstruct nfs4_pathname fs_path;\n\tint nlocations;\n\tstruct nfs4_fs_location locations[10];\n};\n\nstruct nfs_page {\n\tstruct list_head wb_list;\n\tstruct page *wb_page;\n\tstruct nfs_lock_context *wb_lock_context;\n\tlong unsigned int wb_index;\n\tunsigned int wb_offset;\n\tunsigned int wb_pgbase;\n\tunsigned int wb_bytes;\n\tstruct kref wb_kref;\n\tlong unsigned int wb_flags;\n\tstruct nfs_write_verifier wb_verf;\n\tstruct nfs_page *wb_this_page;\n\tstruct nfs_page *wb_head;\n\tshort unsigned int wb_nio;\n};\n\nstruct nfs_subversion {\n\tstruct module *owner;\n\tstruct file_system_type *nfs_fs;\n\tconst struct rpc_version *rpc_vers;\n\tconst struct nfs_rpc_ops *rpc_ops;\n\tconst struct super_operations *sops;\n\tconst struct xattr_handler **xattr;\n\tstruct list_head list;\n};\n\nstruct nfs_iostats {\n\tlong long unsigned int bytes[8];\n\tlong unsigned int events[27];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct nfs4_state_owner;\n\nstruct nfs4_state {\n\tstruct list_head open_states;\n\tstruct list_head inode_states;\n\tstruct list_head lock_states;\n\tstruct nfs4_state_owner *owner;\n\tstruct inode *inode;\n\tlong unsigned int flags;\n\tspinlock_t state_lock;\n\tseqlock_t seqlock;\n\tnfs4_stateid stateid;\n\tnfs4_stateid open_stateid;\n\tunsigned int n_rdonly;\n\tunsigned int n_wronly;\n\tunsigned int n_rdwr;\n\tfmode_t state;\n\trefcount_t count;\n\twait_queue_head_t waitq;\n\tstruct callback_head callback_head;\n};\n\nstruct nlmsvc_binding {\n\t__be32 (*fopen)(struct svc_rqst *, struct nfs_fh *, struct file **);\n\tvoid (*fclose)(struct file *);\n};\n\nstruct svc_cred {\n\tkuid_t cr_uid;\n\tkgid_t cr_gid;\n\tstruct group_info *cr_group_info;\n\tu32 cr_flavor;\n\tchar *cr_raw_principal;\n\tchar *cr_principal;\n\tchar *cr_targ_princ;\n\tstruct gss_api_mech *cr_gss_mech;\n};\n\nstruct cache_deferred_req;\n\nstruct cache_req {\n\tstruct cache_deferred_req * (*defer)(struct cache_req *);\n\tint thread_wait;\n};\n\nstruct svc_cacherep;\n\nstruct svc_pool;\n\nstruct svc_procedure;\n\nstruct svc_deferred_req;\n\nstruct svc_rqst {\n\tstruct list_head rq_all;\n\tstruct callback_head rq_rcu_head;\n\tstruct svc_xprt *rq_xprt;\n\tstruct __kernel_sockaddr_storage rq_addr;\n\tsize_t rq_addrlen;\n\tstruct __kernel_sockaddr_storage rq_daddr;\n\tsize_t rq_daddrlen;\n\tstruct svc_serv *rq_server;\n\tstruct svc_pool *rq_pool;\n\tconst struct svc_procedure *rq_procinfo;\n\tstruct auth_ops *rq_authop;\n\tstruct svc_cred rq_cred;\n\tvoid *rq_xprt_ctxt;\n\tstruct svc_deferred_req *rq_deferred;\n\tsize_t rq_xprt_hlen;\n\tstruct xdr_buf rq_arg;\n\tstruct xdr_buf rq_res;\n\tstruct page *rq_pages[260];\n\tstruct page **rq_respages;\n\tstruct page **rq_next_page;\n\tstruct page **rq_page_end;\n\tstruct kvec rq_vec[259];\n\tstruct bio_vec rq_bvec[259];\n\t__be32 rq_xid;\n\tu32 rq_prog;\n\tu32 rq_vers;\n\tu32 rq_proc;\n\tu32 rq_prot;\n\tint rq_cachetype;\n\tlong unsigned int rq_flags;\n\tktime_t rq_qtime;\n\tvoid *rq_argp;\n\tvoid *rq_resp;\n\tvoid *rq_auth_data;\n\tint rq_auth_slack;\n\tint rq_reserved;\n\tktime_t rq_stime;\n\tstruct cache_req rq_chandle;\n\tstruct auth_domain *rq_client;\n\tstruct auth_domain *rq_gssclient;\n\tstruct svc_cacherep *rq_cacherep;\n\tstruct task_struct *rq_task;\n\tspinlock_t rq_lock;\n\tstruct net *rq_bc_net;\n\tvoid **rq_lease_breaker;\n};\n\nstruct nlmclnt_initdata {\n\tconst char *hostname;\n\tconst struct sockaddr *address;\n\tsize_t addrlen;\n\tshort unsigned int protocol;\n\tu32 nfs_version;\n\tint noresvport;\n\tstruct net *net;\n\tconst struct nlmclnt_operations *nlmclnt_ops;\n\tconst struct cred *cred;\n};\n\nstruct cache_head {\n\tstruct hlist_node cache_list;\n\ttime64_t expiry_time;\n\ttime64_t last_refresh;\n\tstruct kref ref;\n\tlong unsigned int flags;\n};\n\nstruct cache_detail {\n\tstruct module *owner;\n\tint hash_size;\n\tstruct hlist_head *hash_table;\n\tspinlock_t hash_lock;\n\tchar *name;\n\tvoid (*cache_put)(struct kref *);\n\tint (*cache_upcall)(struct cache_detail *, struct cache_head *);\n\tvoid (*cache_request)(struct cache_detail *, struct cache_head *, char **, int *);\n\tint (*cache_parse)(struct cache_detail *, char *, int);\n\tint (*cache_show)(struct seq_file *, struct cache_detail *, struct cache_head *);\n\tvoid (*warn_no_listener)(struct cache_detail *, int);\n\tstruct cache_head * (*alloc)();\n\tvoid (*flush)();\n\tint (*match)(struct cache_head *, struct cache_head *);\n\tvoid (*init)(struct cache_head *, struct cache_head *);\n\tvoid (*update)(struct cache_head *, struct cache_head *);\n\ttime64_t flush_time;\n\tstruct list_head others;\n\ttime64_t nextcheck;\n\tint entries;\n\tstruct list_head queue;\n\tatomic_t writers;\n\ttime64_t last_close;\n\ttime64_t last_warn;\n\tunion {\n\t\tstruct proc_dir_entry *procfs;\n\t\tstruct dentry *pipefs;\n\t};\n\tstruct net *net;\n};\n\nstruct cache_deferred_req {\n\tstruct hlist_node hash;\n\tstruct list_head recent;\n\tstruct cache_head *item;\n\tvoid *owner;\n\tvoid (*revisit)(struct cache_deferred_req *, int);\n};\n\nstruct auth_ops {\n\tchar *name;\n\tstruct module *owner;\n\tint flavour;\n\tint (*accept)(struct svc_rqst *, __be32 *);\n\tint (*release)(struct svc_rqst *);\n\tvoid (*domain_release)(struct auth_domain *);\n\tint (*set_client)(struct svc_rqst *);\n};\n\nstruct svc_pool_stats {\n\tatomic_long_t packets;\n\tlong unsigned int sockets_queued;\n\tatomic_long_t threads_woken;\n\tatomic_long_t threads_timedout;\n};\n\nstruct svc_pool {\n\tunsigned int sp_id;\n\tspinlock_t sp_lock;\n\tstruct list_head sp_sockets;\n\tunsigned int sp_nrthreads;\n\tstruct list_head sp_all_threads;\n\tstruct svc_pool_stats sp_stats;\n\tlong unsigned int sp_flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct svc_serv_ops {\n\tvoid (*svo_shutdown)(struct svc_serv *, struct net *);\n\tint (*svo_function)(void *);\n\tvoid (*svo_enqueue_xprt)(struct svc_xprt *);\n\tint (*svo_setup)(struct svc_serv *, struct svc_pool *, int);\n\tstruct module *svo_module;\n};\n\nstruct svc_serv {\n\tstruct svc_program *sv_program;\n\tstruct svc_stat *sv_stats;\n\tspinlock_t sv_lock;\n\tunsigned int sv_nrthreads;\n\tunsigned int sv_maxconn;\n\tunsigned int sv_max_payload;\n\tunsigned int sv_max_mesg;\n\tunsigned int sv_xdrsize;\n\tstruct list_head sv_permsocks;\n\tstruct list_head sv_tempsocks;\n\tint sv_tmpcnt;\n\tstruct timer_list sv_temptimer;\n\tchar *sv_name;\n\tunsigned int sv_nrpools;\n\tstruct svc_pool *sv_pools;\n\tconst struct svc_serv_ops *sv_ops;\n};\n\nstruct svc_procedure {\n\t__be32 (*pc_func)(struct svc_rqst *);\n\tint (*pc_decode)(struct svc_rqst *, __be32 *);\n\tint (*pc_encode)(struct svc_rqst *, __be32 *);\n\tvoid (*pc_release)(struct svc_rqst *);\n\tunsigned int pc_argsize;\n\tunsigned int pc_ressize;\n\tunsigned int pc_cachetype;\n\tunsigned int pc_xdrressize;\n};\n\nstruct svc_deferred_req {\n\tu32 prot;\n\tstruct svc_xprt *xprt;\n\tstruct __kernel_sockaddr_storage addr;\n\tsize_t addrlen;\n\tstruct __kernel_sockaddr_storage daddr;\n\tsize_t daddrlen;\n\tstruct cache_deferred_req handle;\n\tsize_t xprt_hlen;\n\tint argslen;\n\t__be32 args[0];\n};\n\nstruct svc_process_info {\n\tunion {\n\t\tint (*dispatch)(struct svc_rqst *, __be32 *);\n\t\tstruct {\n\t\t\tunsigned int lovers;\n\t\t\tunsigned int hivers;\n\t\t} mismatch;\n\t};\n};\n\nstruct svc_version {\n\tu32 vs_vers;\n\tu32 vs_nproc;\n\tconst struct svc_procedure *vs_proc;\n\tunsigned int *vs_count;\n\tu32 vs_xdrsize;\n\tbool vs_hidden;\n\tbool vs_rpcb_optnl;\n\tbool vs_need_cong_ctrl;\n\tint (*vs_dispatch)(struct svc_rqst *, __be32 *);\n};\n\nstruct svc_pool_map {\n\tint count;\n\tint mode;\n\tunsigned int npools;\n\tunsigned int *pool_to;\n\tunsigned int *to_pool;\n};\n\nstruct svc_xprt_ops {\n\tstruct svc_xprt * (*xpo_create)(struct svc_serv *, struct net *, struct sockaddr *, int, int);\n\tstruct svc_xprt * (*xpo_accept)(struct svc_xprt *);\n\tint (*xpo_has_wspace)(struct svc_xprt *);\n\tint (*xpo_recvfrom)(struct svc_rqst *);\n\tint (*xpo_sendto)(struct svc_rqst *);\n\tint (*xpo_read_payload)(struct svc_rqst *, unsigned int, unsigned int);\n\tvoid (*xpo_release_rqst)(struct svc_rqst *);\n\tvoid (*xpo_detach)(struct svc_xprt *);\n\tvoid (*xpo_free)(struct svc_xprt *);\n\tvoid (*xpo_secure_port)(struct svc_rqst *);\n\tvoid (*xpo_kill_temp_xprt)(struct svc_xprt *);\n};\n\nstruct svc_xprt_class {\n\tconst char *xcl_name;\n\tstruct module *xcl_owner;\n\tconst struct svc_xprt_ops *xcl_ops;\n\tstruct list_head xcl_list;\n\tu32 xcl_max_payload;\n\tint xcl_ident;\n};\n\nstruct nfs4_state_recovery_ops {\n\tint owner_flag_bit;\n\tint state_flag_bit;\n\tint (*recover_open)(struct nfs4_state_owner *, struct nfs4_state *);\n\tint (*recover_lock)(struct nfs4_state *, struct file_lock *);\n\tint (*establish_clid)(struct nfs_client *, const struct cred *);\n\tint (*reclaim_complete)(struct nfs_client *, const struct cred *);\n\tint (*detect_trunking)(struct nfs_client *, struct nfs_client **, const struct cred *);\n};\n\nstruct nfs4_state_maintenance_ops {\n\tint (*sched_state_renewal)(struct nfs_client *, const struct cred *, unsigned int);\n\tconst struct cred * (*get_state_renewal_cred)(struct nfs_client *);\n\tint (*renew_lease)(struct nfs_client *, const struct cred *);\n};\n\nstruct nfs4_mig_recovery_ops {\n\tint (*get_locations)(struct inode *, struct nfs4_fs_locations *, struct page *, const struct cred *);\n\tint (*fsid_present)(struct inode *, const struct cred *);\n};\n\nstruct nfs4_state_owner {\n\tstruct nfs_server *so_server;\n\tstruct list_head so_lru;\n\tlong unsigned int so_expires;\n\tstruct rb_node so_server_node;\n\tconst struct cred *so_cred;\n\tspinlock_t so_lock;\n\tatomic_t so_count;\n\tlong unsigned int so_flags;\n\tstruct list_head so_states;\n\tstruct nfs_seqid_counter so_seqid;\n\tseqcount_t so_reclaim_seqcount;\n\tstruct mutex so_delegreturn_mutex;\n};\n\nenum nfs_stat_bytecounters {\n\tNFSIOS_NORMALREADBYTES = 0,\n\tNFSIOS_NORMALWRITTENBYTES = 1,\n\tNFSIOS_DIRECTREADBYTES = 2,\n\tNFSIOS_DIRECTWRITTENBYTES = 3,\n\tNFSIOS_SERVERREADBYTES = 4,\n\tNFSIOS_SERVERWRITTENBYTES = 5,\n\tNFSIOS_READPAGES = 6,\n\tNFSIOS_WRITEPAGES = 7,\n\t__NFSIOS_BYTESMAX = 8,\n};\n\nenum nfs_stat_eventcounters {\n\tNFSIOS_INODEREVALIDATE = 0,\n\tNFSIOS_DENTRYREVALIDATE = 1,\n\tNFSIOS_DATAINVALIDATE = 2,\n\tNFSIOS_ATTRINVALIDATE = 3,\n\tNFSIOS_VFSOPEN = 4,\n\tNFSIOS_VFSLOOKUP = 5,\n\tNFSIOS_VFSACCESS = 6,\n\tNFSIOS_VFSUPDATEPAGE = 7,\n\tNFSIOS_VFSREADPAGE = 8,\n\tNFSIOS_VFSREADPAGES = 9,\n\tNFSIOS_VFSWRITEPAGE = 10,\n\tNFSIOS_VFSWRITEPAGES = 11,\n\tNFSIOS_VFSGETDENTS = 12,\n\tNFSIOS_VFSSETATTR = 13,\n\tNFSIOS_VFSFLUSH = 14,\n\tNFSIOS_VFSFSYNC = 15,\n\tNFSIOS_VFSLOCK = 16,\n\tNFSIOS_VFSRELEASE = 17,\n\tNFSIOS_CONGESTIONWAIT = 18,\n\tNFSIOS_SETATTRTRUNC = 19,\n\tNFSIOS_EXTENDWRITE = 20,\n\tNFSIOS_SILLYRENAME = 21,\n\tNFSIOS_SHORTREAD = 22,\n\tNFSIOS_SHORTWRITE = 23,\n\tNFSIOS_DELAY = 24,\n\tNFSIOS_PNFS_READ = 25,\n\tNFSIOS_PNFS_WRITE = 26,\n\t__NFSIOS_COUNTSMAX = 27,\n};\n\nstruct nfs_pageio_descriptor;\n\nstruct nfs_pageio_ops {\n\tvoid (*pg_init)(struct nfs_pageio_descriptor *, struct nfs_page *);\n\tsize_t (*pg_test)(struct nfs_pageio_descriptor *, struct nfs_page *, struct nfs_page *);\n\tint (*pg_doio)(struct nfs_pageio_descriptor *);\n\tunsigned int (*pg_get_mirror_count)(struct nfs_pageio_descriptor *, struct nfs_page *);\n\tvoid (*pg_cleanup)(struct nfs_pageio_descriptor *);\n};\n\nstruct nfs_pgio_mirror {\n\tstruct list_head pg_list;\n\tlong unsigned int pg_bytes_written;\n\tsize_t pg_count;\n\tsize_t pg_bsize;\n\tunsigned int pg_base;\n\tunsigned char pg_recoalesce: 1;\n};\n\nstruct nfs_pageio_descriptor {\n\tstruct inode *pg_inode;\n\tconst struct nfs_pageio_ops *pg_ops;\n\tconst struct nfs_rw_ops *pg_rw_ops;\n\tint pg_ioflags;\n\tint pg_error;\n\tconst struct rpc_call_ops *pg_rpc_callops;\n\tconst struct nfs_pgio_completion_ops *pg_completion_ops;\n\tstruct pnfs_layout_segment *pg_lseg;\n\tstruct nfs_io_completion *pg_io_completion;\n\tstruct nfs_direct_req *pg_dreq;\n\tunsigned int pg_bsize;\n\tu32 pg_mirror_count;\n\tstruct nfs_pgio_mirror *pg_mirrors;\n\tstruct nfs_pgio_mirror pg_mirrors_static[1];\n\tstruct nfs_pgio_mirror *pg_mirrors_dynamic;\n\tu32 pg_mirror_idx;\n\tshort unsigned int pg_maxretrans;\n\tunsigned char pg_moreio: 1;\n};\n\nstruct nfs_clone_mount {\n\tstruct super_block *sb;\n\tstruct dentry *dentry;\n\tstruct nfs_fattr *fattr;\n\tunsigned int inherited_bsize;\n};\n\nstruct nfs_fs_context {\n\tbool internal;\n\tbool skip_reconfig_option_check;\n\tbool need_mount;\n\tbool sloppy;\n\tunsigned int flags;\n\tunsigned int rsize;\n\tunsigned int wsize;\n\tunsigned int timeo;\n\tunsigned int retrans;\n\tunsigned int acregmin;\n\tunsigned int acregmax;\n\tunsigned int acdirmin;\n\tunsigned int acdirmax;\n\tunsigned int namlen;\n\tunsigned int options;\n\tunsigned int bsize;\n\tstruct nfs_auth_info auth_info;\n\trpc_authflavor_t selected_flavor;\n\tchar *client_address;\n\tunsigned int version;\n\tunsigned int minorversion;\n\tchar *fscache_uniq;\n\tshort unsigned int protofamily;\n\tshort unsigned int mountfamily;\n\tstruct {\n\t\tunion {\n\t\t\tstruct sockaddr address;\n\t\t\tstruct __kernel_sockaddr_storage _address;\n\t\t};\n\t\tsize_t addrlen;\n\t\tchar *hostname;\n\t\tu32 version;\n\t\tint port;\n\t\tshort unsigned int protocol;\n\t} mount_server;\n\tstruct {\n\t\tunion {\n\t\t\tstruct sockaddr address;\n\t\t\tstruct __kernel_sockaddr_storage _address;\n\t\t};\n\t\tsize_t addrlen;\n\t\tchar *hostname;\n\t\tchar *export_path;\n\t\tint port;\n\t\tshort unsigned int protocol;\n\t\tshort unsigned int nconnect;\n\t\tshort unsigned int export_path_len;\n\t} nfs_server;\n\tstruct nfs_fh *mntfh;\n\tstruct nfs_server *server;\n\tstruct nfs_subversion *nfs_mod;\n\tstruct nfs_clone_mount clone_data;\n};\n\nstruct bl_dev_msg {\n\tint32_t status;\n\tuint32_t major;\n\tuint32_t minor;\n};\n\nstruct nfs_netns_client;\n\nstruct nfs_net {\n\tstruct cache_detail *nfs_dns_resolve;\n\tstruct rpc_pipe *bl_device_pipe;\n\tstruct bl_dev_msg bl_mount_reply;\n\twait_queue_head_t bl_wq;\n\tstruct mutex bl_mutex;\n\tstruct list_head nfs_client_list;\n\tstruct list_head nfs_volume_list;\n\tstruct idr cb_ident_idr;\n\tshort unsigned int nfs_callback_tcpport;\n\tshort unsigned int nfs_callback_tcpport6;\n\tint cb_users[1];\n\tstruct nfs_netns_client *nfs_client;\n\tspinlock_t nfs_client_lock;\n\tktime_t boot_time;\n\tstruct proc_dir_entry *proc_nfsfs;\n};\n\nstruct nfs_netns_client {\n\tstruct kobject kobject;\n\tstruct net *net;\n\tconst char *identifier;\n};\n\nstruct nfs_open_dir_context {\n\tstruct list_head list;\n\tconst struct cred *cred;\n\tlong unsigned int attr_gencount;\n\t__u64 dir_cookie;\n\t__u64 dup_cookie;\n\tsigned char duped;\n};\n\nstruct nfs4_cached_acl;\n\nstruct nfs_delegation;\n\nstruct nfs_inode {\n\t__u64 fileid;\n\tstruct nfs_fh fh;\n\tlong unsigned int flags;\n\tlong unsigned int cache_validity;\n\tlong unsigned int read_cache_jiffies;\n\tlong unsigned int attrtimeo;\n\tlong unsigned int attrtimeo_timestamp;\n\tlong unsigned int attr_gencount;\n\tlong unsigned int cache_change_attribute;\n\tstruct rb_root access_cache;\n\tstruct list_head access_cache_entry_lru;\n\tstruct list_head access_cache_inode_lru;\n\t__be32 cookieverf[2];\n\tatomic_long_t nrequests;\n\tstruct nfs_mds_commit_info commit_info;\n\tstruct list_head open_files;\n\tstruct rw_semaphore rmdir_sem;\n\tstruct mutex commit_mutex;\n\tlong unsigned int page_index;\n\tstruct nfs4_cached_acl *nfs4_acl;\n\tstruct list_head open_states;\n\tstruct nfs_delegation *delegation;\n\tstruct rw_semaphore rwsem;\n\tstruct pnfs_layout_hdr *layout;\n\t__u64 write_io;\n\t__u64 read_io;\n\tstruct inode vfs_inode;\n};\n\nstruct nfs_delegation {\n\tstruct list_head super_list;\n\tconst struct cred *cred;\n\tstruct inode *inode;\n\tnfs4_stateid stateid;\n\tfmode_t type;\n\tlong unsigned int pagemod_limit;\n\t__u64 change_attr;\n\tlong unsigned int flags;\n\trefcount_t refcount;\n\tspinlock_t lock;\n\tstruct callback_head rcu;\n};\n\nstruct svc_version___2;\n\nstruct nfs_cache_array_entry {\n\tu64 cookie;\n\tu64 ino;\n\tstruct qstr string;\n\tunsigned char d_type;\n};\n\nstruct nfs_cache_array {\n\tint size;\n\tint eof_index;\n\tu64 last_cookie;\n\tstruct nfs_cache_array_entry array[0];\n};\n\ntypedef struct {\n\tstruct file *file;\n\tstruct page *page;\n\tstruct dir_context *ctx;\n\tlong unsigned int page_index;\n\tu64 *dir_cookie;\n\tu64 last_cookie;\n\tloff_t current_index;\n\tloff_t prev_index;\n\tlong unsigned int dir_verifier;\n\tlong unsigned int timestamp;\n\tlong unsigned int gencount;\n\tunsigned int cache_entry_index;\n\tbool plus;\n\tbool eof;\n} nfs_readdir_descriptor_t;\n\ntypedef long long unsigned int pao_T_____7;\n\nstruct nfs_find_desc {\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs4_sessionid {\n\tunsigned char data[16];\n};\n\nstruct nfs4_channel_attrs {\n\tu32 max_rqst_sz;\n\tu32 max_resp_sz;\n\tu32 max_resp_sz_cached;\n\tu32 max_ops;\n\tu32 max_reqs;\n};\n\nstruct nfs4_slot {\n\tstruct nfs4_slot_table *table;\n\tstruct nfs4_slot *next;\n\tlong unsigned int generation;\n\tu32 slot_nr;\n\tu32 seq_nr;\n\tu32 seq_nr_last_acked;\n\tu32 seq_nr_highest_sent;\n\tunsigned int privileged: 1;\n\tunsigned int seq_done: 1;\n};\n\nstruct nfs4_slot_table {\n\tstruct nfs4_session *session;\n\tstruct nfs4_slot *slots;\n\tlong unsigned int used_slots[16];\n\tspinlock_t slot_tbl_lock;\n\tstruct rpc_wait_queue slot_tbl_waitq;\n\twait_queue_head_t slot_waitq;\n\tu32 max_slots;\n\tu32 max_slotid;\n\tu32 highest_used_slotid;\n\tu32 target_highest_slotid;\n\tu32 server_highest_slotid;\n\ts32 d_target_highest_slotid;\n\ts32 d2_target_highest_slotid;\n\tlong unsigned int generation;\n\tstruct completion complete;\n\tlong unsigned int slot_tbl_state;\n};\n\nstruct nfs4_session {\n\tstruct nfs4_sessionid sess_id;\n\tu32 flags;\n\tlong unsigned int session_state;\n\tu32 hash_alg;\n\tu32 ssv_len;\n\tstruct nfs4_channel_attrs fc_attrs;\n\tstruct nfs4_slot_table fc_slot_table;\n\tstruct nfs4_channel_attrs bc_attrs;\n\tstruct nfs4_slot_table bc_slot_table;\n\tstruct nfs_client *clp;\n};\n\nstruct nfs_mount_request {\n\tstruct sockaddr *sap;\n\tsize_t salen;\n\tchar *hostname;\n\tchar *dirpath;\n\tu32 version;\n\tshort unsigned int protocol;\n\tstruct nfs_fh *fh;\n\tint noresvport;\n\tunsigned int *auth_flav_len;\n\trpc_authflavor_t *auth_flavs;\n\tstruct net *net;\n};\n\nstruct proc_nfs_info {\n\tint flag;\n\tconst char *str;\n\tconst char *nostr;\n};\n\nenum {\n\tNFS_IOHDR_ERROR = 0,\n\tNFS_IOHDR_EOF = 1,\n\tNFS_IOHDR_REDO = 2,\n\tNFS_IOHDR_STAT = 3,\n\tNFS_IOHDR_RESEND_PNFS = 4,\n\tNFS_IOHDR_RESEND_MDS = 5,\n};\n\nstruct nfs_direct_req {\n\tstruct kref kref;\n\tstruct nfs_open_context *ctx;\n\tstruct nfs_lock_context *l_ctx;\n\tstruct kiocb *iocb;\n\tstruct inode *inode;\n\tatomic_t io_count;\n\tspinlock_t lock;\n\tloff_t io_start;\n\tssize_t count;\n\tssize_t max_count;\n\tssize_t bytes_left;\n\tssize_t error;\n\tstruct completion completion;\n\tstruct nfs_mds_commit_info mds_cinfo;\n\tstruct pnfs_ds_commit_info ds_cinfo;\n\tstruct work_struct work;\n\tint flags;\n};\n\nenum {\n\tPG_BUSY = 0,\n\tPG_MAPPED = 1,\n\tPG_CLEAN = 2,\n\tPG_COMMIT_TO_DS = 3,\n\tPG_INODE_REF = 4,\n\tPG_HEADLOCK = 5,\n\tPG_TEARDOWN = 6,\n\tPG_UNLOCKPAGE = 7,\n\tPG_UPTODATE = 8,\n\tPG_WB_END = 9,\n\tPG_REMOVE = 10,\n\tPG_CONTENDED1 = 11,\n\tPG_CONTENDED2 = 12,\n};\n\nstruct nfs_readdesc {\n\tstruct nfs_pageio_descriptor *pgio;\n\tstruct nfs_open_context *ctx;\n};\n\nstruct nfs_io_completion {\n\tvoid (*complete)(void *);\n\tvoid *data;\n\tstruct kref refcount;\n};\n\nenum pnfs_try_status {\n\tPNFS_ATTEMPTED = 0,\n\tPNFS_NOT_ATTEMPTED = 1,\n\tPNFS_TRY_AGAIN = 2,\n};\n\nenum {\n\tMOUNTPROC_NULL = 0,\n\tMOUNTPROC_MNT = 1,\n\tMOUNTPROC_DUMP = 2,\n\tMOUNTPROC_UMNT = 3,\n\tMOUNTPROC_UMNTALL = 4,\n\tMOUNTPROC_EXPORT = 5,\n};\n\nenum {\n\tMOUNTPROC3_NULL = 0,\n\tMOUNTPROC3_MNT = 1,\n\tMOUNTPROC3_DUMP = 2,\n\tMOUNTPROC3_UMNT = 3,\n\tMOUNTPROC3_UMNTALL = 4,\n\tMOUNTPROC3_EXPORT = 5,\n};\n\nenum mountstat {\n\tMNT_OK = 0,\n\tMNT_EPERM = 1,\n\tMNT_ENOENT = 2,\n\tMNT_EACCES = 13,\n\tMNT_EINVAL = 22,\n};\n\nenum mountstat3 {\n\tMNT3_OK = 0,\n\tMNT3ERR_PERM = 1,\n\tMNT3ERR_NOENT = 2,\n\tMNT3ERR_IO = 5,\n\tMNT3ERR_ACCES = 13,\n\tMNT3ERR_NOTDIR = 20,\n\tMNT3ERR_INVAL = 22,\n\tMNT3ERR_NAMETOOLONG = 63,\n\tMNT3ERR_NOTSUPP = 10004,\n\tMNT3ERR_SERVERFAULT = 10006,\n};\n\nstruct mountres {\n\tint errno;\n\tstruct nfs_fh *fh;\n\tunsigned int *auth_count;\n\trpc_authflavor_t *auth_flavors;\n};\n\nenum nfs_stat {\n\tNFS_OK = 0,\n\tNFSERR_PERM = 1,\n\tNFSERR_NOENT = 2,\n\tNFSERR_IO = 5,\n\tNFSERR_NXIO = 6,\n\tNFSERR_EAGAIN = 11,\n\tNFSERR_ACCES = 13,\n\tNFSERR_EXIST = 17,\n\tNFSERR_XDEV = 18,\n\tNFSERR_NODEV = 19,\n\tNFSERR_NOTDIR = 20,\n\tNFSERR_ISDIR = 21,\n\tNFSERR_INVAL = 22,\n\tNFSERR_FBIG = 27,\n\tNFSERR_NOSPC = 28,\n\tNFSERR_ROFS = 30,\n\tNFSERR_MLINK = 31,\n\tNFSERR_OPNOTSUPP = 45,\n\tNFSERR_NAMETOOLONG = 63,\n\tNFSERR_NOTEMPTY = 66,\n\tNFSERR_DQUOT = 69,\n\tNFSERR_STALE = 70,\n\tNFSERR_REMOTE = 71,\n\tNFSERR_WFLUSH = 99,\n\tNFSERR_BADHANDLE = 10001,\n\tNFSERR_NOT_SYNC = 10002,\n\tNFSERR_BAD_COOKIE = 10003,\n\tNFSERR_NOTSUPP = 10004,\n\tNFSERR_TOOSMALL = 10005,\n\tNFSERR_SERVERFAULT = 10006,\n\tNFSERR_BADTYPE = 10007,\n\tNFSERR_JUKEBOX = 10008,\n\tNFSERR_SAME = 10009,\n\tNFSERR_DENIED = 10010,\n\tNFSERR_EXPIRED = 10011,\n\tNFSERR_LOCKED = 10012,\n\tNFSERR_GRACE = 10013,\n\tNFSERR_FHEXPIRED = 10014,\n\tNFSERR_SHARE_DENIED = 10015,\n\tNFSERR_WRONGSEC = 10016,\n\tNFSERR_CLID_INUSE = 10017,\n\tNFSERR_RESOURCE = 10018,\n\tNFSERR_MOVED = 10019,\n\tNFSERR_NOFILEHANDLE = 10020,\n\tNFSERR_MINOR_VERS_MISMATCH = 10021,\n\tNFSERR_STALE_CLIENTID = 10022,\n\tNFSERR_STALE_STATEID = 10023,\n\tNFSERR_OLD_STATEID = 10024,\n\tNFSERR_BAD_STATEID = 10025,\n\tNFSERR_BAD_SEQID = 10026,\n\tNFSERR_NOT_SAME = 10027,\n\tNFSERR_LOCK_RANGE = 10028,\n\tNFSERR_SYMLINK = 10029,\n\tNFSERR_RESTOREFH = 10030,\n\tNFSERR_LEASE_MOVED = 10031,\n\tNFSERR_ATTRNOTSUPP = 10032,\n\tNFSERR_NO_GRACE = 10033,\n\tNFSERR_RECLAIM_BAD = 10034,\n\tNFSERR_RECLAIM_CONFLICT = 10035,\n\tNFSERR_BAD_XDR = 10036,\n\tNFSERR_LOCKS_HELD = 10037,\n\tNFSERR_OPENMODE = 10038,\n\tNFSERR_BADOWNER = 10039,\n\tNFSERR_BADCHAR = 10040,\n\tNFSERR_BADNAME = 10041,\n\tNFSERR_BAD_RANGE = 10042,\n\tNFSERR_LOCK_NOTSUPP = 10043,\n\tNFSERR_OP_ILLEGAL = 10044,\n\tNFSERR_DEADLOCK = 10045,\n\tNFSERR_FILE_OPEN = 10046,\n\tNFSERR_ADMIN_REVOKED = 10047,\n\tNFSERR_CB_PATH_DOWN = 10048,\n};\n\nstruct trace_event_raw_nfs_inode_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 version;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_inode_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tunsigned char type;\n\tu64 fileid;\n\tu64 version;\n\tloff_t size;\n\tlong unsigned int nfsi_flags;\n\tlong unsigned int cache_validity;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_access_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tunsigned char type;\n\tu64 fileid;\n\tu64 version;\n\tloff_t size;\n\tlong unsigned int nfsi_flags;\n\tlong unsigned int cache_validity;\n\tunsigned int mask;\n\tunsigned int permitted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_lookup_event {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_lookup_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_atomic_open_enter {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tunsigned int fmode;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_atomic_open_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tunsigned int fmode;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_create_enter {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_create_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int flags;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_directory_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_directory_event_done {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_link_enter {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_link_exit {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_rename_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 old_dir;\n\tu64 new_dir;\n\tu32 __data_loc_old_name;\n\tu32 __data_loc_new_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_rename_event_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 old_dir;\n\tu32 __data_loc_old_name;\n\tu64 new_dir;\n\tu32 __data_loc_new_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_sillyrename_unlink {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_read {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readpage_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tbool eof;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_readpage_short {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tbool eof;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_pgio_error {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tloff_t pos;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_write {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tenum nfs3_stable_how stable;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_writeback_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tint status;\n\tenum nfs3_stable_how stable;\n\tchar verifier[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_page_error_class {\n\tstruct trace_entry ent;\n\tconst void *req;\n\tlong unsigned int index;\n\tunsigned int offset;\n\tunsigned int pgbase;\n\tunsigned int bytes;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_initiate_commit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_commit_done {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tint status;\n\tenum nfs3_stable_how stable;\n\tchar verifier[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_fh_to_dentry {\n\tstruct trace_entry ent;\n\tint error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs_xdr_status {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint version;\n\tlong unsigned int error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_nfs_inode_event {};\n\nstruct trace_event_data_offsets_nfs_inode_event_done {};\n\nstruct trace_event_data_offsets_nfs_access_exit {};\n\nstruct trace_event_data_offsets_nfs_lookup_event {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_nfs_lookup_event_done {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_nfs_atomic_open_enter {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_nfs_atomic_open_exit {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_nfs_create_enter {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_nfs_create_exit {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_nfs_directory_event {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_nfs_directory_event_done {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_nfs_link_enter {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_nfs_link_exit {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_nfs_rename_event {\n\tu32 old_name;\n\tu32 new_name;\n};\n\nstruct trace_event_data_offsets_nfs_rename_event_done {\n\tu32 old_name;\n\tu32 new_name;\n};\n\nstruct trace_event_data_offsets_nfs_sillyrename_unlink {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_nfs_initiate_read {};\n\nstruct trace_event_data_offsets_nfs_readpage_done {};\n\nstruct trace_event_data_offsets_nfs_readpage_short {};\n\nstruct trace_event_data_offsets_nfs_pgio_error {};\n\nstruct trace_event_data_offsets_nfs_initiate_write {};\n\nstruct trace_event_data_offsets_nfs_writeback_done {};\n\nstruct trace_event_data_offsets_nfs_page_error_class {};\n\nstruct trace_event_data_offsets_nfs_initiate_commit {};\n\nstruct trace_event_data_offsets_nfs_commit_done {};\n\nstruct trace_event_data_offsets_nfs_fh_to_dentry {};\n\nstruct trace_event_data_offsets_nfs_xdr_status {\n\tu32 program;\n\tu32 procedure;\n};\n\ntypedef void (*btf_trace_nfs_set_inode_stale)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_refresh_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_refresh_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_revalidate_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_revalidate_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_invalidate_mapping_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_invalidate_mapping_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_getattr_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_getattr_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_setattr_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_setattr_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_writeback_page_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_writeback_page_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_writeback_inode_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_writeback_inode_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_fsync_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_fsync_exit)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs_access_enter)(void *, const struct inode *);\n\ntypedef void (*btf_trace_nfs_access_exit)(void *, const struct inode *, unsigned int, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_lookup_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_lookup_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_lookup_revalidate_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_lookup_revalidate_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_atomic_open_enter)(void *, const struct inode *, const struct nfs_open_context *, unsigned int);\n\ntypedef void (*btf_trace_nfs_atomic_open_exit)(void *, const struct inode *, const struct nfs_open_context *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_create_enter)(void *, const struct inode *, const struct dentry *, unsigned int);\n\ntypedef void (*btf_trace_nfs_create_exit)(void *, const struct inode *, const struct dentry *, unsigned int, int);\n\ntypedef void (*btf_trace_nfs_mknod_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_mknod_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_mkdir_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_mkdir_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_rmdir_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_rmdir_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_remove_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_remove_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_unlink_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_unlink_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_symlink_enter)(void *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_symlink_exit)(void *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_link_enter)(void *, const struct inode *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_link_exit)(void *, const struct inode *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_rename_enter)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *);\n\ntypedef void (*btf_trace_nfs_rename_exit)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_sillyrename_rename)(void *, const struct inode *, const struct dentry *, const struct inode *, const struct dentry *, int);\n\ntypedef void (*btf_trace_nfs_sillyrename_unlink)(void *, const struct nfs_unlinkdata *, int);\n\ntypedef void (*btf_trace_nfs_initiate_read)(void *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_readpage_done)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_readpage_short)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_pgio_error)(void *, const struct nfs_pgio_header *, int, loff_t);\n\ntypedef void (*btf_trace_nfs_initiate_write)(void *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_writeback_done)(void *, const struct rpc_task *, const struct nfs_pgio_header *);\n\ntypedef void (*btf_trace_nfs_write_error)(void *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_comp_error)(void *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_commit_error)(void *, const struct nfs_page *, int);\n\ntypedef void (*btf_trace_nfs_initiate_commit)(void *, const struct nfs_commit_data *);\n\ntypedef void (*btf_trace_nfs_commit_done)(void *, const struct rpc_task *, const struct nfs_commit_data *);\n\ntypedef void (*btf_trace_nfs_fh_to_dentry)(void *, const struct super_block *, const struct nfs_fh *, u64, int);\n\ntypedef void (*btf_trace_nfs_xdr_status)(void *, const struct xdr_stream *, int);\n\nenum {\n\tFILEID_HIGH_OFF = 0,\n\tFILEID_LOW_OFF = 1,\n\tFILE_I_TYPE_OFF = 2,\n\tEMBED_FH_OFF = 3,\n};\n\nstruct nfs2_fh {\n\tchar data[32];\n};\n\nstruct nfs3_fh {\n\tshort unsigned int size;\n\tunsigned char data[64];\n};\n\nstruct nfs_mount_data {\n\tint version;\n\tint fd;\n\tstruct nfs2_fh old_root;\n\tint flags;\n\tint rsize;\n\tint wsize;\n\tint timeo;\n\tint retrans;\n\tint acregmin;\n\tint acregmax;\n\tint acdirmin;\n\tint acdirmax;\n\tstruct sockaddr_in addr;\n\tchar hostname[256];\n\tint namlen;\n\tunsigned int bsize;\n\tstruct nfs3_fh root;\n\tint pseudoflavor;\n\tchar context[257];\n};\n\nenum nfs_param {\n\tOpt_ac = 0,\n\tOpt_acdirmax = 1,\n\tOpt_acdirmin = 2,\n\tOpt_acl___2 = 3,\n\tOpt_acregmax = 4,\n\tOpt_acregmin = 5,\n\tOpt_actimeo = 6,\n\tOpt_addr = 7,\n\tOpt_bg = 8,\n\tOpt_bsize = 9,\n\tOpt_clientaddr = 10,\n\tOpt_cto = 11,\n\tOpt_fg = 12,\n\tOpt_fscache = 13,\n\tOpt_fscache_flag = 14,\n\tOpt_hard = 15,\n\tOpt_intr = 16,\n\tOpt_local_lock = 17,\n\tOpt_lock = 18,\n\tOpt_lookupcache = 19,\n\tOpt_migration = 20,\n\tOpt_minorversion = 21,\n\tOpt_mountaddr = 22,\n\tOpt_mounthost = 23,\n\tOpt_mountport = 24,\n\tOpt_mountproto = 25,\n\tOpt_mountvers = 26,\n\tOpt_namelen = 27,\n\tOpt_nconnect = 28,\n\tOpt_port = 29,\n\tOpt_posix = 30,\n\tOpt_proto = 31,\n\tOpt_rdirplus = 32,\n\tOpt_rdma = 33,\n\tOpt_resvport = 34,\n\tOpt_retrans = 35,\n\tOpt_retry = 36,\n\tOpt_rsize = 37,\n\tOpt_sec = 38,\n\tOpt_sharecache = 39,\n\tOpt_sloppy = 40,\n\tOpt_soft = 41,\n\tOpt_softerr = 42,\n\tOpt_softreval = 43,\n\tOpt_source = 44,\n\tOpt_tcp = 45,\n\tOpt_timeo = 46,\n\tOpt_udp = 47,\n\tOpt_v = 48,\n\tOpt_vers = 49,\n\tOpt_wsize = 50,\n};\n\nenum {\n\tOpt_local_lock_all = 0,\n\tOpt_local_lock_flock = 1,\n\tOpt_local_lock_none = 2,\n\tOpt_local_lock_posix = 3,\n};\n\nenum {\n\tOpt_lookupcache_all = 0,\n\tOpt_lookupcache_none = 1,\n\tOpt_lookupcache_positive = 2,\n};\n\nenum {\n\tOpt_vers_2 = 0,\n\tOpt_vers_3 = 1,\n\tOpt_vers_4 = 2,\n\tOpt_vers_4_0 = 3,\n\tOpt_vers_4_1 = 4,\n\tOpt_vers_4_2 = 5,\n};\n\nenum {\n\tOpt_xprt_rdma = 0,\n\tOpt_xprt_rdma6 = 1,\n\tOpt_xprt_tcp = 2,\n\tOpt_xprt_tcp6 = 3,\n\tOpt_xprt_udp = 4,\n\tOpt_xprt_udp6 = 5,\n\tnr__Opt_xprt = 6,\n};\n\nenum {\n\tOpt_sec_krb5 = 0,\n\tOpt_sec_krb5i = 1,\n\tOpt_sec_krb5p = 2,\n\tOpt_sec_lkey = 3,\n\tOpt_sec_lkeyi = 4,\n\tOpt_sec_lkeyp = 5,\n\tOpt_sec_none = 6,\n\tOpt_sec_spkm = 7,\n\tOpt_sec_spkmi = 8,\n\tOpt_sec_spkmp = 9,\n\tOpt_sec_sys = 10,\n\tnr__Opt_sec = 11,\n};\n\nstruct nfs2_fsstat {\n\t__u32 tsize;\n\t__u32 bsize;\n\t__u32 blocks;\n\t__u32 bfree;\n\t__u32 bavail;\n};\n\nstruct nfs_sattrargs {\n\tstruct nfs_fh *fh;\n\tstruct iattr *sattr;\n};\n\nstruct nfs_diropargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n};\n\nstruct nfs_createargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n};\n\nstruct nfs_linkargs {\n\tstruct nfs_fh *fromfh;\n\tstruct nfs_fh *tofh;\n\tconst char *toname;\n\tunsigned int tolen;\n};\n\nstruct nfs_symlinkargs {\n\tstruct nfs_fh *fromfh;\n\tconst char *fromname;\n\tunsigned int fromlen;\n\tstruct page **pages;\n\tunsigned int pathlen;\n\tstruct iattr *sattr;\n};\n\nstruct nfs_readdirargs {\n\tstruct nfs_fh *fh;\n\t__u32 cookie;\n\tunsigned int count;\n\tstruct page **pages;\n};\n\nstruct nfs_diropok {\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs_readlinkargs {\n\tstruct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs_createdata {\n\tstruct nfs_createargs arg;\n\tstruct nfs_diropok res;\n\tstruct nfs_fh fhandle;\n\tstruct nfs_fattr fattr;\n};\n\nenum nfs_ftype {\n\tNFNON = 0,\n\tNFREG = 1,\n\tNFDIR = 2,\n\tNFBLK = 3,\n\tNFCHR = 4,\n\tNFLNK = 5,\n\tNFSOCK = 6,\n\tNFBAD = 7,\n\tNFFIFO = 8,\n};\n\nenum nfs2_ftype {\n\tNF2NON = 0,\n\tNF2REG = 1,\n\tNF2DIR = 2,\n\tNF2BLK = 3,\n\tNF2CHR = 4,\n\tNF2LNK = 5,\n\tNF2SOCK = 6,\n\tNF2BAD = 7,\n\tNF2FIFO = 8,\n};\n\nenum nfs3_createmode {\n\tNFS3_CREATE_UNCHECKED = 0,\n\tNFS3_CREATE_GUARDED = 1,\n\tNFS3_CREATE_EXCLUSIVE = 2,\n};\n\nenum nfs3_ftype {\n\tNF3NON = 0,\n\tNF3REG = 1,\n\tNF3DIR = 2,\n\tNF3BLK = 3,\n\tNF3CHR = 4,\n\tNF3LNK = 5,\n\tNF3SOCK = 6,\n\tNF3FIFO = 7,\n\tNF3BAD = 8,\n};\n\nstruct nfs3_sattrargs {\n\tstruct nfs_fh *fh;\n\tstruct iattr *sattr;\n\tunsigned int guard;\n\tstruct timespec64 guardtime;\n};\n\nstruct nfs3_diropargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n};\n\nstruct nfs3_accessargs {\n\tstruct nfs_fh *fh;\n\t__u32 access;\n};\n\nstruct nfs3_createargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n\tenum nfs3_createmode createmode;\n\t__be32 verifier[2];\n};\n\nstruct nfs3_mkdirargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tstruct iattr *sattr;\n};\n\nstruct nfs3_symlinkargs {\n\tstruct nfs_fh *fromfh;\n\tconst char *fromname;\n\tunsigned int fromlen;\n\tstruct page **pages;\n\tunsigned int pathlen;\n\tstruct iattr *sattr;\n};\n\nstruct nfs3_mknodargs {\n\tstruct nfs_fh *fh;\n\tconst char *name;\n\tunsigned int len;\n\tenum nfs3_ftype type;\n\tstruct iattr *sattr;\n\tdev_t rdev;\n};\n\nstruct nfs3_linkargs {\n\tstruct nfs_fh *fromfh;\n\tstruct nfs_fh *tofh;\n\tconst char *toname;\n\tunsigned int tolen;\n};\n\nstruct nfs3_readdirargs {\n\tstruct nfs_fh *fh;\n\t__u64 cookie;\n\t__be32 verf[2];\n\tbool plus;\n\tunsigned int count;\n\tstruct page **pages;\n};\n\nstruct nfs3_diropres {\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs3_accessres {\n\tstruct nfs_fattr *fattr;\n\t__u32 access;\n};\n\nstruct nfs3_readlinkargs {\n\tstruct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs3_linkres {\n\tstruct nfs_fattr *dir_attr;\n\tstruct nfs_fattr *fattr;\n};\n\nstruct nfs3_readdirres {\n\tstruct nfs_fattr *dir_attr;\n\t__be32 *verf;\n\tbool plus;\n};\n\nstruct nfs3_createdata {\n\tstruct rpc_message msg;\n\tunion {\n\t\tstruct nfs3_createargs create;\n\t\tstruct nfs3_mkdirargs mkdir;\n\t\tstruct nfs3_symlinkargs symlink;\n\t\tstruct nfs3_mknodargs mknod;\n\t} arg;\n\tstruct nfs3_diropres res;\n\tstruct nfs_fh fh;\n\tstruct nfs_fattr fattr;\n\tstruct nfs_fattr dir_attr;\n};\n\nstruct nfs3_getaclargs {\n\tstruct nfs_fh *fh;\n\tint mask;\n\tstruct page **pages;\n};\n\nstruct nfs3_setaclargs {\n\tstruct inode *inode;\n\tint mask;\n\tstruct posix_acl *acl_access;\n\tstruct posix_acl *acl_default;\n\tsize_t len;\n\tunsigned int npages;\n\tstruct page **pages;\n};\n\nstruct nfs3_getaclres {\n\tstruct nfs_fattr *fattr;\n\tint mask;\n\tunsigned int acl_access_count;\n\tunsigned int acl_default_count;\n\tstruct posix_acl *acl_access;\n\tstruct posix_acl *acl_default;\n};\n\nenum nfsstat4 {\n\tNFS4_OK = 0,\n\tNFS4ERR_PERM = 1,\n\tNFS4ERR_NOENT = 2,\n\tNFS4ERR_IO = 5,\n\tNFS4ERR_NXIO = 6,\n\tNFS4ERR_ACCESS = 13,\n\tNFS4ERR_EXIST = 17,\n\tNFS4ERR_XDEV = 18,\n\tNFS4ERR_NOTDIR = 20,\n\tNFS4ERR_ISDIR = 21,\n\tNFS4ERR_INVAL = 22,\n\tNFS4ERR_FBIG = 27,\n\tNFS4ERR_NOSPC = 28,\n\tNFS4ERR_ROFS = 30,\n\tNFS4ERR_MLINK = 31,\n\tNFS4ERR_NAMETOOLONG = 63,\n\tNFS4ERR_NOTEMPTY = 66,\n\tNFS4ERR_DQUOT = 69,\n\tNFS4ERR_STALE = 70,\n\tNFS4ERR_BADHANDLE = 10001,\n\tNFS4ERR_BAD_COOKIE = 10003,\n\tNFS4ERR_NOTSUPP = 10004,\n\tNFS4ERR_TOOSMALL = 10005,\n\tNFS4ERR_SERVERFAULT = 10006,\n\tNFS4ERR_BADTYPE = 10007,\n\tNFS4ERR_DELAY = 10008,\n\tNFS4ERR_SAME = 10009,\n\tNFS4ERR_DENIED = 10010,\n\tNFS4ERR_EXPIRED = 10011,\n\tNFS4ERR_LOCKED = 10012,\n\tNFS4ERR_GRACE = 10013,\n\tNFS4ERR_FHEXPIRED = 10014,\n\tNFS4ERR_SHARE_DENIED = 10015,\n\tNFS4ERR_WRONGSEC = 10016,\n\tNFS4ERR_CLID_INUSE = 10017,\n\tNFS4ERR_RESOURCE = 10018,\n\tNFS4ERR_MOVED = 10019,\n\tNFS4ERR_NOFILEHANDLE = 10020,\n\tNFS4ERR_MINOR_VERS_MISMATCH = 10021,\n\tNFS4ERR_STALE_CLIENTID = 10022,\n\tNFS4ERR_STALE_STATEID = 10023,\n\tNFS4ERR_OLD_STATEID = 10024,\n\tNFS4ERR_BAD_STATEID = 10025,\n\tNFS4ERR_BAD_SEQID = 10026,\n\tNFS4ERR_NOT_SAME = 10027,\n\tNFS4ERR_LOCK_RANGE = 10028,\n\tNFS4ERR_SYMLINK = 10029,\n\tNFS4ERR_RESTOREFH = 10030,\n\tNFS4ERR_LEASE_MOVED = 10031,\n\tNFS4ERR_ATTRNOTSUPP = 10032,\n\tNFS4ERR_NO_GRACE = 10033,\n\tNFS4ERR_RECLAIM_BAD = 10034,\n\tNFS4ERR_RECLAIM_CONFLICT = 10035,\n\tNFS4ERR_BADXDR = 10036,\n\tNFS4ERR_LOCKS_HELD = 10037,\n\tNFS4ERR_OPENMODE = 10038,\n\tNFS4ERR_BADOWNER = 10039,\n\tNFS4ERR_BADCHAR = 10040,\n\tNFS4ERR_BADNAME = 10041,\n\tNFS4ERR_BAD_RANGE = 10042,\n\tNFS4ERR_LOCK_NOTSUPP = 10043,\n\tNFS4ERR_OP_ILLEGAL = 10044,\n\tNFS4ERR_DEADLOCK = 10045,\n\tNFS4ERR_FILE_OPEN = 10046,\n\tNFS4ERR_ADMIN_REVOKED = 10047,\n\tNFS4ERR_CB_PATH_DOWN = 10048,\n\tNFS4ERR_BADIOMODE = 10049,\n\tNFS4ERR_BADLAYOUT = 10050,\n\tNFS4ERR_BAD_SESSION_DIGEST = 10051,\n\tNFS4ERR_BADSESSION = 10052,\n\tNFS4ERR_BADSLOT = 10053,\n\tNFS4ERR_COMPLETE_ALREADY = 10054,\n\tNFS4ERR_CONN_NOT_BOUND_TO_SESSION = 10055,\n\tNFS4ERR_DELEG_ALREADY_WANTED = 10056,\n\tNFS4ERR_BACK_CHAN_BUSY = 10057,\n\tNFS4ERR_LAYOUTTRYLATER = 10058,\n\tNFS4ERR_LAYOUTUNAVAILABLE = 10059,\n\tNFS4ERR_NOMATCHING_LAYOUT = 10060,\n\tNFS4ERR_RECALLCONFLICT = 10061,\n\tNFS4ERR_UNKNOWN_LAYOUTTYPE = 10062,\n\tNFS4ERR_SEQ_MISORDERED = 10063,\n\tNFS4ERR_SEQUENCE_POS = 10064,\n\tNFS4ERR_REQ_TOO_BIG = 10065,\n\tNFS4ERR_REP_TOO_BIG = 10066,\n\tNFS4ERR_REP_TOO_BIG_TO_CACHE = 10067,\n\tNFS4ERR_RETRY_UNCACHED_REP = 10068,\n\tNFS4ERR_UNSAFE_COMPOUND = 10069,\n\tNFS4ERR_TOO_MANY_OPS = 10070,\n\tNFS4ERR_OP_NOT_IN_SESSION = 10071,\n\tNFS4ERR_HASH_ALG_UNSUPP = 10072,\n\tNFS4ERR_CLIENTID_BUSY = 10074,\n\tNFS4ERR_PNFS_IO_HOLE = 10075,\n\tNFS4ERR_SEQ_FALSE_RETRY = 10076,\n\tNFS4ERR_BAD_HIGH_SLOT = 10077,\n\tNFS4ERR_DEADSESSION = 10078,\n\tNFS4ERR_ENCR_ALG_UNSUPP = 10079,\n\tNFS4ERR_PNFS_NO_LAYOUT = 10080,\n\tNFS4ERR_NOT_ONLY_OP = 10081,\n\tNFS4ERR_WRONG_CRED = 10082,\n\tNFS4ERR_WRONG_TYPE = 10083,\n\tNFS4ERR_DIRDELEG_UNAVAIL = 10084,\n\tNFS4ERR_REJECT_DELEG = 10085,\n\tNFS4ERR_RETURNCONFLICT = 10086,\n\tNFS4ERR_DELEG_REVOKED = 10087,\n\tNFS4ERR_PARTNER_NOTSUPP = 10088,\n\tNFS4ERR_PARTNER_NO_AUTH = 10089,\n\tNFS4ERR_UNION_NOTSUPP = 10090,\n\tNFS4ERR_OFFLOAD_DENIED = 10091,\n\tNFS4ERR_WRONG_LFS = 10092,\n\tNFS4ERR_BADLABEL = 10093,\n\tNFS4ERR_OFFLOAD_NO_REQS = 10094,\n};\n\nenum nfs_ftype4 {\n\tNF4BAD = 0,\n\tNF4REG = 1,\n\tNF4DIR = 2,\n\tNF4BLK = 3,\n\tNF4CHR = 4,\n\tNF4LNK = 5,\n\tNF4SOCK = 6,\n\tNF4FIFO = 7,\n\tNF4ATTRDIR = 8,\n\tNF4NAMEDATTR = 9,\n};\n\nenum open_claim_type4 {\n\tNFS4_OPEN_CLAIM_NULL = 0,\n\tNFS4_OPEN_CLAIM_PREVIOUS = 1,\n\tNFS4_OPEN_CLAIM_DELEGATE_CUR = 2,\n\tNFS4_OPEN_CLAIM_DELEGATE_PREV = 3,\n\tNFS4_OPEN_CLAIM_FH = 4,\n\tNFS4_OPEN_CLAIM_DELEG_CUR_FH = 5,\n\tNFS4_OPEN_CLAIM_DELEG_PREV_FH = 6,\n};\n\nenum createmode4 {\n\tNFS4_CREATE_UNCHECKED = 0,\n\tNFS4_CREATE_GUARDED = 1,\n\tNFS4_CREATE_EXCLUSIVE = 2,\n\tNFS4_CREATE_EXCLUSIVE4_1 = 3,\n};\n\nenum {\n\tNFSPROC4_CLNT_NULL = 0,\n\tNFSPROC4_CLNT_READ = 1,\n\tNFSPROC4_CLNT_WRITE = 2,\n\tNFSPROC4_CLNT_COMMIT = 3,\n\tNFSPROC4_CLNT_OPEN = 4,\n\tNFSPROC4_CLNT_OPEN_CONFIRM = 5,\n\tNFSPROC4_CLNT_OPEN_NOATTR = 6,\n\tNFSPROC4_CLNT_OPEN_DOWNGRADE = 7,\n\tNFSPROC4_CLNT_CLOSE = 8,\n\tNFSPROC4_CLNT_SETATTR = 9,\n\tNFSPROC4_CLNT_FSINFO = 10,\n\tNFSPROC4_CLNT_RENEW = 11,\n\tNFSPROC4_CLNT_SETCLIENTID = 12,\n\tNFSPROC4_CLNT_SETCLIENTID_CONFIRM = 13,\n\tNFSPROC4_CLNT_LOCK = 14,\n\tNFSPROC4_CLNT_LOCKT = 15,\n\tNFSPROC4_CLNT_LOCKU = 16,\n\tNFSPROC4_CLNT_ACCESS = 17,\n\tNFSPROC4_CLNT_GETATTR = 18,\n\tNFSPROC4_CLNT_LOOKUP = 19,\n\tNFSPROC4_CLNT_LOOKUP_ROOT = 20,\n\tNFSPROC4_CLNT_REMOVE = 21,\n\tNFSPROC4_CLNT_RENAME = 22,\n\tNFSPROC4_CLNT_LINK = 23,\n\tNFSPROC4_CLNT_SYMLINK = 24,\n\tNFSPROC4_CLNT_CREATE = 25,\n\tNFSPROC4_CLNT_PATHCONF = 26,\n\tNFSPROC4_CLNT_STATFS = 27,\n\tNFSPROC4_CLNT_READLINK = 28,\n\tNFSPROC4_CLNT_READDIR = 29,\n\tNFSPROC4_CLNT_SERVER_CAPS = 30,\n\tNFSPROC4_CLNT_DELEGRETURN = 31,\n\tNFSPROC4_CLNT_GETACL = 32,\n\tNFSPROC4_CLNT_SETACL = 33,\n\tNFSPROC4_CLNT_FS_LOCATIONS = 34,\n\tNFSPROC4_CLNT_RELEASE_LOCKOWNER = 35,\n\tNFSPROC4_CLNT_SECINFO = 36,\n\tNFSPROC4_CLNT_FSID_PRESENT = 37,\n\tNFSPROC4_CLNT_EXCHANGE_ID = 38,\n\tNFSPROC4_CLNT_CREATE_SESSION = 39,\n\tNFSPROC4_CLNT_DESTROY_SESSION = 40,\n\tNFSPROC4_CLNT_SEQUENCE = 41,\n\tNFSPROC4_CLNT_GET_LEASE_TIME = 42,\n\tNFSPROC4_CLNT_RECLAIM_COMPLETE = 43,\n\tNFSPROC4_CLNT_LAYOUTGET = 44,\n\tNFSPROC4_CLNT_GETDEVICEINFO = 45,\n\tNFSPROC4_CLNT_LAYOUTCOMMIT = 46,\n\tNFSPROC4_CLNT_LAYOUTRETURN = 47,\n\tNFSPROC4_CLNT_SECINFO_NO_NAME = 48,\n\tNFSPROC4_CLNT_TEST_STATEID = 49,\n\tNFSPROC4_CLNT_FREE_STATEID = 50,\n\tNFSPROC4_CLNT_GETDEVICELIST = 51,\n\tNFSPROC4_CLNT_BIND_CONN_TO_SESSION = 52,\n\tNFSPROC4_CLNT_DESTROY_CLIENTID = 53,\n\tNFSPROC4_CLNT_SEEK = 54,\n\tNFSPROC4_CLNT_ALLOCATE = 55,\n\tNFSPROC4_CLNT_DEALLOCATE = 56,\n\tNFSPROC4_CLNT_LAYOUTSTATS = 57,\n\tNFSPROC4_CLNT_CLONE = 58,\n\tNFSPROC4_CLNT_COPY = 59,\n\tNFSPROC4_CLNT_OFFLOAD_CANCEL = 60,\n\tNFSPROC4_CLNT_LOOKUPP = 61,\n\tNFSPROC4_CLNT_LAYOUTERROR = 62,\n\tNFSPROC4_CLNT_COPY_NOTIFY = 63,\n};\n\nstruct nfs4_get_lease_time_args {\n\tstruct nfs4_sequence_args la_seq_args;\n};\n\nstruct nfs4_get_lease_time_res {\n\tstruct nfs4_sequence_res lr_seq_res;\n\tstruct nfs_fsinfo *lr_fsinfo;\n};\n\nstruct nfs4_xdr_opaque_data;\n\nstruct nfs4_xdr_opaque_ops {\n\tvoid (*encode)(struct xdr_stream *, const void *, const struct nfs4_xdr_opaque_data *);\n\tvoid (*free)(struct nfs4_xdr_opaque_data *);\n};\n\nstruct nfs4_xdr_opaque_data {\n\tconst struct nfs4_xdr_opaque_ops *ops;\n\tvoid *data;\n};\n\nstruct nfs4_layoutdriver_data {\n\tstruct page **pages;\n\t__u32 pglen;\n\t__u32 len;\n};\n\nstruct nfs4_layoutget_args {\n\tstruct nfs4_sequence_args seq_args;\n\t__u32 type;\n\tstruct pnfs_layout_range range;\n\t__u64 minlength;\n\t__u32 maxcount;\n\tstruct inode *inode;\n\tstruct nfs_open_context *ctx;\n\tnfs4_stateid stateid;\n\tstruct nfs4_layoutdriver_data layout;\n};\n\nstruct nfs4_layoutget_res {\n\tstruct nfs4_sequence_res seq_res;\n\tint status;\n\t__u32 return_on_close;\n\tstruct pnfs_layout_range range;\n\t__u32 type;\n\tnfs4_stateid stateid;\n\tstruct nfs4_layoutdriver_data *layoutp;\n};\n\nstruct nfs4_layoutget {\n\tstruct nfs4_layoutget_args args;\n\tstruct nfs4_layoutget_res res;\n\tconst struct cred *cred;\n\tgfp_t gfp_flags;\n};\n\nstruct nfs4_layoutreturn_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct pnfs_layout_hdr *layout;\n\tstruct inode *inode;\n\tstruct pnfs_layout_range range;\n\tnfs4_stateid stateid;\n\t__u32 layout_type;\n\tstruct nfs4_xdr_opaque_data *ld_private;\n};\n\nstruct nfs4_layoutreturn_res {\n\tstruct nfs4_sequence_res seq_res;\n\tu32 lrs_present;\n\tnfs4_stateid stateid;\n};\n\nstruct stateowner_id {\n\t__u64 create_time;\n\t__u32 uniquifier;\n};\n\nstruct nfs_openargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tstruct nfs_seqid *seqid;\n\tint open_flags;\n\tfmode_t fmode;\n\tu32 share_access;\n\tu32 access;\n\t__u64 clientid;\n\tstruct stateowner_id id;\n\tunion {\n\t\tstruct {\n\t\t\tstruct iattr *attrs;\n\t\t\tnfs4_verifier verifier;\n\t\t};\n\t\tnfs4_stateid delegation;\n\t\tfmode_t delegation_type;\n\t} u;\n\tconst struct qstr *name;\n\tconst struct nfs_server *server;\n\tconst u32 *bitmask;\n\tconst u32 *open_bitmap;\n\tenum open_claim_type4 claim;\n\tenum createmode4 createmode;\n\tconst struct nfs4_label *label;\n\tumode_t umask;\n\tstruct nfs4_layoutget_args *lg_args;\n};\n\nstruct nfs_openres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_fh fh;\n\tstruct nfs4_change_info cinfo;\n\t__u32 rflags;\n\tstruct nfs_fattr *f_attr;\n\tstruct nfs4_label *f_label;\n\tstruct nfs_seqid *seqid;\n\tconst struct nfs_server *server;\n\tfmode_t delegation_type;\n\tnfs4_stateid delegation;\n\tlong unsigned int pagemod_limit;\n\t__u32 do_recall;\n\t__u32 attrset[3];\n\tstruct nfs4_string *owner;\n\tstruct nfs4_string *group_owner;\n\t__u32 access_request;\n\t__u32 access_supported;\n\t__u32 access_result;\n\tstruct nfs4_layoutget_res *lg_res;\n};\n\nstruct nfs_open_confirmargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tnfs4_stateid *stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_open_confirmres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_closeargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n\tfmode_t fmode;\n\tu32 share_access;\n\tconst u32 *bitmask;\n\tstruct nfs4_layoutreturn_args *lr_args;\n};\n\nstruct nfs_closeres {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_seqid *seqid;\n\tconst struct nfs_server *server;\n\tstruct nfs4_layoutreturn_res *lr_res;\n\tint lr_ret;\n};\n\nstruct nfs_lowner {\n\t__u64 clientid;\n\t__u64 id;\n\tdev_t s_dev;\n};\n\nstruct nfs_lock_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_seqid *lock_seqid;\n\tnfs4_stateid lock_stateid;\n\tstruct nfs_seqid *open_seqid;\n\tnfs4_stateid open_stateid;\n\tstruct nfs_lowner lock_owner;\n\tunsigned char block: 1;\n\tunsigned char reclaim: 1;\n\tunsigned char new_lock: 1;\n\tunsigned char new_lock_owner: 1;\n};\n\nstruct nfs_lock_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *lock_seqid;\n\tstruct nfs_seqid *open_seqid;\n};\n\nstruct nfs_locku_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_seqid *seqid;\n\tnfs4_stateid stateid;\n};\n\nstruct nfs_locku_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_stateid stateid;\n\tstruct nfs_seqid *seqid;\n};\n\nstruct nfs_lockt_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tstruct file_lock *fl;\n\tstruct nfs_lowner lock_owner;\n};\n\nstruct nfs_lockt_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct file_lock *denied;\n};\n\nstruct nfs_release_lockowner_args {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_lowner lock_owner;\n};\n\nstruct nfs_release_lockowner_res {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs4_delegreturnargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fhandle;\n\tconst nfs4_stateid *stateid;\n\tconst u32 *bitmask;\n\tstruct nfs4_layoutreturn_args *lr_args;\n};\n\nstruct nfs4_delegreturnres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_server *server;\n\tstruct nfs4_layoutreturn_res *lr_res;\n\tint lr_ret;\n};\n\nstruct nfs_setattrargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tnfs4_stateid stateid;\n\tstruct iattr *iap;\n\tconst struct nfs_server *server;\n\tconst u32 *bitmask;\n\tconst struct nfs4_label *label;\n};\n\nstruct nfs_setaclargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tsize_t acl_len;\n\tstruct page **acl_pages;\n};\n\nstruct nfs_setaclres {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs_getaclargs {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fh;\n\tsize_t acl_len;\n\tstruct page **acl_pages;\n};\n\nstruct nfs_getaclres {\n\tstruct nfs4_sequence_res seq_res;\n\tsize_t acl_len;\n\tsize_t acl_data_offset;\n\tint acl_flags;\n\tstruct page *acl_scratch;\n};\n\nstruct nfs_setattrres {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_label *label;\n\tconst struct nfs_server *server;\n};\n\ntypedef u64 clientid4;\n\nstruct nfs4_accessargs {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n\tu32 access;\n};\n\nstruct nfs4_accessres {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tu32 supported;\n\tu32 access;\n};\n\nstruct nfs4_create_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tu32 ftype;\n\tunion {\n\t\tstruct {\n\t\t\tstruct page **pages;\n\t\t\tunsigned int len;\n\t\t} symlink;\n\t\tstruct {\n\t\t\tu32 specdata1;\n\t\t\tu32 specdata2;\n\t\t} device;\n\t} u;\n\tconst struct qstr *name;\n\tconst struct nfs_server *server;\n\tconst struct iattr *attrs;\n\tconst struct nfs_fh *dir_fh;\n\tconst u32 *bitmask;\n\tconst struct nfs4_label *label;\n\tumode_t umask;\n};\n\nstruct nfs4_create_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fh *fh;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_label *label;\n\tstruct nfs4_change_info dir_cinfo;\n};\n\nstruct nfs4_fsinfo_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_fsinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fsinfo *fsinfo;\n};\n\nstruct nfs4_getattr_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_getattr_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_label *label;\n};\n\nstruct nfs4_link_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_link_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs4_label *label;\n\tstruct nfs4_change_info cinfo;\n\tstruct nfs_fattr *dir_attr;\n};\n\nstruct nfs4_lookup_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookup_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_fh *fh;\n\tstruct nfs4_label *label;\n};\n\nstruct nfs4_lookupp_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_lookupp_res {\n\tstruct nfs4_sequence_res seq_res;\n\tconst struct nfs_server *server;\n\tstruct nfs_fattr *fattr;\n\tstruct nfs_fh *fh;\n\tstruct nfs4_label *label;\n};\n\nstruct nfs4_lookup_root_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_pathconf_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_pathconf_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_pathconf *pathconf;\n};\n\nstruct nfs4_readdir_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tu64 cookie;\n\tnfs4_verifier verifier;\n\tu32 count;\n\tstruct page **pages;\n\tunsigned int pgbase;\n\tconst u32 *bitmask;\n\tbool plus;\n};\n\nstruct nfs4_readdir_res {\n\tstruct nfs4_sequence_res seq_res;\n\tnfs4_verifier verifier;\n\tunsigned int pgbase;\n};\n\nstruct nfs4_readlink {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tunsigned int pgbase;\n\tunsigned int pglen;\n\tstruct page **pages;\n};\n\nstruct nfs4_readlink_res {\n\tstruct nfs4_sequence_res seq_res;\n};\n\nstruct nfs4_setclientid {\n\tconst nfs4_verifier *sc_verifier;\n\tu32 sc_prog;\n\tunsigned int sc_netid_len;\n\tchar sc_netid[6];\n\tunsigned int sc_uaddr_len;\n\tchar sc_uaddr[58];\n\tstruct nfs_client *sc_clnt;\n\tstruct rpc_cred *sc_cred;\n};\n\nstruct nfs4_setclientid_res {\n\tu64 clientid;\n\tnfs4_verifier confirm;\n};\n\nstruct nfs4_statfs_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_statfs_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fsstat *fsstat;\n};\n\nstruct nfs4_server_caps_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tstruct nfs_fh *fhandle;\n\tconst u32 *bitmask;\n};\n\nstruct nfs4_server_caps_res {\n\tstruct nfs4_sequence_res seq_res;\n\tu32 attr_bitmask[3];\n\tu32 exclcreat_bitmask[3];\n\tu32 acl_bitmask;\n\tu32 has_links;\n\tu32 has_symlinks;\n\tu32 fh_expire_type;\n};\n\nstruct nfs4_fs_locations_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct nfs_fh *fh;\n\tconst struct qstr *name;\n\tstruct page *page;\n\tconst u32 *bitmask;\n\tclientid4 clientid;\n\tunsigned char migration: 1;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fs_locations_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_fs_locations *fs_locations;\n\tunsigned char migration: 1;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_secinfo4 {\n\tu32 flavor;\n\tstruct rpcsec_gss_info flavor_info;\n};\n\nstruct nfs4_secinfo_flavors {\n\tunsigned int num_flavors;\n\tstruct nfs4_secinfo4 flavors[0];\n};\n\nstruct nfs4_secinfo_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *dir_fh;\n\tconst struct qstr *name;\n};\n\nstruct nfs4_secinfo_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs4_secinfo_flavors *flavors;\n};\n\nstruct nfs4_fsid_present_arg {\n\tstruct nfs4_sequence_args seq_args;\n\tconst struct nfs_fh *fh;\n\tclientid4 clientid;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_fsid_present_res {\n\tstruct nfs4_sequence_res seq_res;\n\tstruct nfs_fh *fh;\n\tunsigned char renew: 1;\n};\n\nstruct nfs4_cached_acl {\n\tint cached;\n\tsize_t len;\n\tchar data[0];\n};\n\nenum nfs4_client_state {\n\tNFS4CLNT_MANAGER_RUNNING = 0,\n\tNFS4CLNT_CHECK_LEASE = 1,\n\tNFS4CLNT_LEASE_EXPIRED = 2,\n\tNFS4CLNT_RECLAIM_REBOOT = 3,\n\tNFS4CLNT_RECLAIM_NOGRACE = 4,\n\tNFS4CLNT_DELEGRETURN = 5,\n\tNFS4CLNT_SESSION_RESET = 6,\n\tNFS4CLNT_LEASE_CONFIRM = 7,\n\tNFS4CLNT_SERVER_SCOPE_MISMATCH = 8,\n\tNFS4CLNT_PURGE_STATE = 9,\n\tNFS4CLNT_BIND_CONN_TO_SESSION = 10,\n\tNFS4CLNT_MOVED = 11,\n\tNFS4CLNT_LEASE_MOVED = 12,\n\tNFS4CLNT_DELEGATION_EXPIRED = 13,\n\tNFS4CLNT_RUN_MANAGER = 14,\n\tNFS4CLNT_RECALL_RUNNING = 15,\n\tNFS4CLNT_RECALL_ANY_LAYOUT_READ = 16,\n\tNFS4CLNT_RECALL_ANY_LAYOUT_RW = 17,\n};\n\nenum {\n\tNFS_OWNER_RECLAIM_REBOOT = 0,\n\tNFS_OWNER_RECLAIM_NOGRACE = 1,\n};\n\nenum {\n\tLK_STATE_IN_USE = 0,\n\tNFS_DELEGATED_STATE = 1,\n\tNFS_OPEN_STATE = 2,\n\tNFS_O_RDONLY_STATE = 3,\n\tNFS_O_WRONLY_STATE = 4,\n\tNFS_O_RDWR_STATE = 5,\n\tNFS_STATE_RECLAIM_REBOOT = 6,\n\tNFS_STATE_RECLAIM_NOGRACE = 7,\n\tNFS_STATE_POSIX_LOCKS = 8,\n\tNFS_STATE_RECOVERY_FAILED = 9,\n\tNFS_STATE_MAY_NOTIFY_LOCK = 10,\n\tNFS_STATE_CHANGE_WAIT = 11,\n\tNFS_CLNT_DST_SSC_COPY_STATE = 12,\n\tNFS_CLNT_SRC_SSC_COPY_STATE = 13,\n\tNFS_SRV_SSC_COPY_STATE = 14,\n};\n\nstruct nfs4_exception {\n\tstruct nfs4_state *state;\n\tstruct inode *inode;\n\tnfs4_stateid *stateid;\n\tlong int timeout;\n\tunsigned char delay: 1;\n\tunsigned char recovering: 1;\n\tunsigned char retry: 1;\n\tbool interruptible;\n};\n\nstruct nfs4_opendata {\n\tstruct kref kref;\n\tstruct nfs_openargs o_arg;\n\tstruct nfs_openres o_res;\n\tstruct nfs_open_confirmargs c_arg;\n\tstruct nfs_open_confirmres c_res;\n\tstruct nfs4_string owner_name;\n\tstruct nfs4_string group_name;\n\tstruct nfs4_label *a_label;\n\tstruct nfs_fattr f_attr;\n\tstruct nfs4_label *f_label;\n\tstruct dentry *dir;\n\tstruct dentry *dentry;\n\tstruct nfs4_state_owner *owner;\n\tstruct nfs4_state *state;\n\tstruct iattr attrs;\n\tstruct nfs4_layoutget *lgp;\n\tlong unsigned int timestamp;\n\tbool rpc_done;\n\tbool file_created;\n\tbool is_recover;\n\tbool cancelled;\n\tint rpc_status;\n};\n\nenum {\n\tNFS_DELEGATION_NEED_RECLAIM = 0,\n\tNFS_DELEGATION_RETURN = 1,\n\tNFS_DELEGATION_RETURN_IF_CLOSED = 2,\n\tNFS_DELEGATION_REFERENCED = 3,\n\tNFS_DELEGATION_RETURNING = 4,\n\tNFS_DELEGATION_REVOKED = 5,\n\tNFS_DELEGATION_TEST_EXPIRED = 6,\n\tNFS_DELEGATION_INODE_FREEING = 7,\n};\n\nenum nfs4_slot_tbl_state {\n\tNFS4_SLOT_TBL_DRAINING = 0,\n};\n\nstruct nfs4_call_sync_data {\n\tconst struct nfs_server *seq_server;\n\tstruct nfs4_sequence_args *seq_args;\n\tstruct nfs4_sequence_res *seq_res;\n};\n\nstruct nfs4_open_createattrs {\n\tstruct nfs4_label *label;\n\tstruct iattr *sattr;\n\tconst __u32 verf[2];\n};\n\nstruct nfs4_closedata {\n\tstruct inode *inode;\n\tstruct nfs4_state *state;\n\tstruct nfs_closeargs arg;\n\tstruct nfs_closeres res;\n\tstruct {\n\t\tstruct nfs4_layoutreturn_args arg;\n\t\tstruct nfs4_layoutreturn_res res;\n\t\tstruct nfs4_xdr_opaque_data ld_private;\n\t\tu32 roc_barrier;\n\t\tbool roc;\n\t} lr;\n\tstruct nfs_fattr fattr;\n\tlong unsigned int timestamp;\n};\n\nstruct nfs4_createdata {\n\tstruct rpc_message msg;\n\tstruct nfs4_create_arg arg;\n\tstruct nfs4_create_res res;\n\tstruct nfs_fh fh;\n\tstruct nfs_fattr fattr;\n\tstruct nfs4_label *label;\n};\n\nstruct nfs4_renewdata {\n\tstruct nfs_client *client;\n\tlong unsigned int timestamp;\n};\n\nstruct nfs4_delegreturndata {\n\tstruct nfs4_delegreturnargs args;\n\tstruct nfs4_delegreturnres res;\n\tstruct nfs_fh fh;\n\tnfs4_stateid stateid;\n\tlong unsigned int timestamp;\n\tstruct {\n\t\tstruct nfs4_layoutreturn_args arg;\n\t\tstruct nfs4_layoutreturn_res res;\n\t\tstruct nfs4_xdr_opaque_data ld_private;\n\t\tu32 roc_barrier;\n\t\tbool roc;\n\t} lr;\n\tstruct nfs_fattr fattr;\n\tint rpc_status;\n\tstruct inode *inode;\n};\n\nstruct nfs4_unlockdata {\n\tstruct nfs_locku_args arg;\n\tstruct nfs_locku_res res;\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_open_context *ctx;\n\tstruct nfs_lock_context *l_ctx;\n\tstruct file_lock fl;\n\tstruct nfs_server *server;\n\tlong unsigned int timestamp;\n};\n\nstruct nfs4_lockdata {\n\tstruct nfs_lock_args arg;\n\tstruct nfs_lock_res res;\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_open_context *ctx;\n\tstruct file_lock fl;\n\tlong unsigned int timestamp;\n\tint rpc_status;\n\tint cancelled;\n\tstruct nfs_server *server;\n};\n\nstruct nfs_release_lockowner_data {\n\tstruct nfs4_lock_state *lsp;\n\tstruct nfs_server *server;\n\tstruct nfs_release_lockowner_args args;\n\tstruct nfs_release_lockowner_res res;\n\tlong unsigned int timestamp;\n};\n\nstruct nfs4_get_lease_time_data {\n\tstruct nfs4_get_lease_time_args *args;\n\tstruct nfs4_get_lease_time_res *res;\n\tstruct nfs_client *clp;\n};\n\nenum opentype4 {\n\tNFS4_OPEN_NOCREATE = 0,\n\tNFS4_OPEN_CREATE = 1,\n};\n\nenum limit_by4 {\n\tNFS4_LIMIT_SIZE = 1,\n\tNFS4_LIMIT_BLOCKS = 2,\n};\n\nenum open_delegation_type4 {\n\tNFS4_OPEN_DELEGATE_NONE = 0,\n\tNFS4_OPEN_DELEGATE_READ = 1,\n\tNFS4_OPEN_DELEGATE_WRITE = 2,\n\tNFS4_OPEN_DELEGATE_NONE_EXT = 3,\n};\n\nenum why_no_delegation4 {\n\tWND4_NOT_WANTED = 0,\n\tWND4_CONTENTION = 1,\n\tWND4_RESOURCE = 2,\n\tWND4_NOT_SUPP_FTYPE = 3,\n\tWND4_WRITE_DELEG_NOT_SUPP_FTYPE = 4,\n\tWND4_NOT_SUPP_UPGRADE = 5,\n\tWND4_NOT_SUPP_DOWNGRADE = 6,\n\tWND4_CANCELLED = 7,\n\tWND4_IS_DIR = 8,\n};\n\nenum lock_type4 {\n\tNFS4_UNLOCK_LT = 0,\n\tNFS4_READ_LT = 1,\n\tNFS4_WRITE_LT = 2,\n\tNFS4_READW_LT = 3,\n\tNFS4_WRITEW_LT = 4,\n};\n\nstruct compound_hdr {\n\tint32_t status;\n\tuint32_t nops;\n\t__be32 *nops_p;\n\tuint32_t taglen;\n\tchar *tag;\n\tuint32_t replen;\n\tu32 minorversion;\n};\n\nstruct nfs_referral_count {\n\tstruct list_head list;\n\tconst struct task_struct *task;\n\tunsigned int referral_count;\n};\n\nstruct rpc_pipe_dir_object_ops;\n\nstruct rpc_pipe_dir_object {\n\tstruct list_head pdo_head;\n\tconst struct rpc_pipe_dir_object_ops *pdo_ops;\n\tvoid *pdo_data;\n};\n\nstruct rpc_pipe_dir_object_ops {\n\tint (*create)(struct dentry *, struct rpc_pipe_dir_object *);\n\tvoid (*destroy)(struct dentry *, struct rpc_pipe_dir_object *);\n};\n\nstruct rpc_inode {\n\tstruct inode vfs_inode;\n\tvoid *private;\n\tstruct rpc_pipe *pipe;\n\twait_queue_head_t waitq;\n};\n\nstruct idmap_legacy_upcalldata;\n\nstruct idmap {\n\tstruct rpc_pipe_dir_object idmap_pdo;\n\tstruct rpc_pipe *idmap_pipe;\n\tstruct idmap_legacy_upcalldata *idmap_upcall_data;\n\tstruct mutex idmap_mutex;\n\tconst struct cred *cred;\n};\n\nstruct user_key_payload {\n\tstruct callback_head rcu;\n\tshort unsigned int datalen;\n\tlong: 48;\n\tchar data[0];\n};\n\nstruct request_key_auth {\n\tstruct callback_head rcu;\n\tstruct key *target_key;\n\tstruct key *dest_keyring;\n\tconst struct cred *cred;\n\tvoid *callout_info;\n\tsize_t callout_len;\n\tpid_t pid;\n\tchar op[8];\n};\n\nstruct idmap_msg {\n\t__u8 im_type;\n\t__u8 im_conv;\n\tchar im_name[128];\n\t__u32 im_id;\n\t__u8 im_status;\n};\n\nstruct idmap_legacy_upcalldata {\n\tstruct rpc_pipe_msg pipe_msg;\n\tstruct idmap_msg idmap_msg;\n\tstruct key *authkey;\n\tstruct idmap *idmap;\n};\n\nenum {\n\tOpt_find_uid = 0,\n\tOpt_find_gid = 1,\n\tOpt_find_user = 2,\n\tOpt_find_group = 3,\n\tOpt_find_err = 4,\n};\n\nenum nfs4_callback_procnum {\n\tCB_NULL = 0,\n\tCB_COMPOUND = 1,\n};\n\nstruct nfs_callback_data {\n\tunsigned int users;\n\tstruct svc_serv *serv;\n};\n\nenum rpc_accept_stat {\n\tRPC_SUCCESS = 0,\n\tRPC_PROG_UNAVAIL = 1,\n\tRPC_PROG_MISMATCH = 2,\n\tRPC_PROC_UNAVAIL = 3,\n\tRPC_GARBAGE_ARGS = 4,\n\tRPC_SYSTEM_ERR = 5,\n\tRPC_DROP_REPLY = 60000,\n};\n\nenum rpc_auth_stat {\n\tRPC_AUTH_OK = 0,\n\tRPC_AUTH_BADCRED = 1,\n\tRPC_AUTH_REJECTEDCRED = 2,\n\tRPC_AUTH_BADVERF = 3,\n\tRPC_AUTH_REJECTEDVERF = 4,\n\tRPC_AUTH_TOOWEAK = 5,\n\tRPCSEC_GSS_CREDPROBLEM = 13,\n\tRPCSEC_GSS_CTXPROBLEM = 14,\n};\n\nenum nfs4_callback_opnum {\n\tOP_CB_GETATTR = 3,\n\tOP_CB_RECALL = 4,\n\tOP_CB_LAYOUTRECALL = 5,\n\tOP_CB_NOTIFY = 6,\n\tOP_CB_PUSH_DELEG = 7,\n\tOP_CB_RECALL_ANY = 8,\n\tOP_CB_RECALLABLE_OBJ_AVAIL = 9,\n\tOP_CB_RECALL_SLOT = 10,\n\tOP_CB_SEQUENCE = 11,\n\tOP_CB_WANTS_CANCELLED = 12,\n\tOP_CB_NOTIFY_LOCK = 13,\n\tOP_CB_NOTIFY_DEVICEID = 14,\n\tOP_CB_OFFLOAD = 15,\n\tOP_CB_ILLEGAL = 10044,\n};\n\nstruct cb_process_state {\n\t__be32 drc_status;\n\tstruct nfs_client *clp;\n\tstruct nfs4_slot *slot;\n\tu32 minorversion;\n\tstruct net *net;\n};\n\nstruct cb_compound_hdr_arg {\n\tunsigned int taglen;\n\tconst char *tag;\n\tunsigned int minorversion;\n\tunsigned int cb_ident;\n\tunsigned int nops;\n};\n\nstruct cb_compound_hdr_res {\n\t__be32 *status;\n\tunsigned int taglen;\n\tconst char *tag;\n\t__be32 *nops;\n};\n\nstruct cb_getattrargs {\n\tstruct nfs_fh fh;\n\tuint32_t bitmap[2];\n};\n\nstruct cb_getattrres {\n\t__be32 status;\n\tuint32_t bitmap[2];\n\tuint64_t size;\n\tuint64_t change_attr;\n\tstruct timespec64 ctime;\n\tstruct timespec64 mtime;\n};\n\nstruct cb_recallargs {\n\tstruct nfs_fh fh;\n\tnfs4_stateid stateid;\n\tuint32_t truncate;\n};\n\nstruct callback_op {\n\t__be32 (*process_op)(void *, void *, struct cb_process_state *);\n\t__be32 (*decode_args)(struct svc_rqst *, struct xdr_stream *, void *);\n\t__be32 (*encode_res)(struct svc_rqst *, struct xdr_stream *, const void *);\n\tlong int res_maxsize;\n};\n\nstruct xprt_create {\n\tint ident;\n\tstruct net *net;\n\tstruct sockaddr *srcaddr;\n\tstruct sockaddr *dstaddr;\n\tsize_t addrlen;\n\tconst char *servername;\n\tstruct svc_xprt *bc_xprt;\n\tstruct rpc_xprt_switch *bc_xps;\n\tunsigned int flags;\n};\n\nstruct trace_event_raw_nfs4_clientid_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dstaddr;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_setup_sequence {\n\tstruct trace_entry ent;\n\tunsigned int session;\n\tunsigned int slot_nr;\n\tunsigned int seq_nr;\n\tunsigned int highest_used_slotid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_mgr {\n\tstruct trace_entry ent;\n\tlong unsigned int state;\n\tu32 __data_loc_hostname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_mgr_failed {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tlong unsigned int state;\n\tu32 __data_loc_hostname;\n\tu32 __data_loc_section;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_xdr_status {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 op;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cb_error_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 cbident;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_open_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tunsigned int flags;\n\tunsigned int fmode;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint openstateid_seq;\n\tu32 openstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_cached_open {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_close {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lock_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tint cmd;\n\tchar type;\n\tloff_t start;\n\tloff_t end;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_set_lock {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tint cmd;\n\tchar type;\n\tloff_t start;\n\tloff_t end;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tint lockstateid_seq;\n\tu32 lockstateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_state_lock_reclaim {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int state_flags;\n\tlong unsigned int lock_flags;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_set_delegation_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int fmode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_delegreturn_exit {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lookup_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 dir;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_lookupp {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu64 ino;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_rename {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tlong unsigned int error;\n\tu64 olddir;\n\tu32 __data_loc_oldname;\n\tu64 newdir;\n\tu32 __data_loc_newname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_stateid_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_getattr_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tunsigned int valid;\n\tlong unsigned int error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_callback_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 __data_loc_dstaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_inode_stateid_callback_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tu32 __data_loc_dstaddr;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_idmap_event {\n\tstruct trace_entry ent;\n\tlong unsigned int error;\n\tu32 id;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_read_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_write_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tloff_t offset;\n\tu32 arg_count;\n\tu32 res_count;\n\tlong unsigned int error;\n\tint stateid_seq;\n\tu32 stateid_hash;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_nfs4_commit_event {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tu32 fhandle;\n\tu64 fileid;\n\tlong unsigned int error;\n\tloff_t offset;\n\tu32 count;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_nfs4_clientid_event {\n\tu32 dstaddr;\n};\n\nstruct trace_event_data_offsets_nfs4_setup_sequence {};\n\nstruct trace_event_data_offsets_nfs4_state_mgr {\n\tu32 hostname;\n};\n\nstruct trace_event_data_offsets_nfs4_state_mgr_failed {\n\tu32 hostname;\n\tu32 section;\n};\n\nstruct trace_event_data_offsets_nfs4_xdr_status {};\n\nstruct trace_event_data_offsets_nfs4_cb_error_class {};\n\nstruct trace_event_data_offsets_nfs4_open_event {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_nfs4_cached_open {};\n\nstruct trace_event_data_offsets_nfs4_close {};\n\nstruct trace_event_data_offsets_nfs4_lock_event {};\n\nstruct trace_event_data_offsets_nfs4_set_lock {};\n\nstruct trace_event_data_offsets_nfs4_state_lock_reclaim {};\n\nstruct trace_event_data_offsets_nfs4_set_delegation_event {};\n\nstruct trace_event_data_offsets_nfs4_delegreturn_exit {};\n\nstruct trace_event_data_offsets_nfs4_lookup_event {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_nfs4_lookupp {};\n\nstruct trace_event_data_offsets_nfs4_rename {\n\tu32 oldname;\n\tu32 newname;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_event {};\n\nstruct trace_event_data_offsets_nfs4_inode_stateid_event {};\n\nstruct trace_event_data_offsets_nfs4_getattr_event {};\n\nstruct trace_event_data_offsets_nfs4_inode_callback_event {\n\tu32 dstaddr;\n};\n\nstruct trace_event_data_offsets_nfs4_inode_stateid_callback_event {\n\tu32 dstaddr;\n};\n\nstruct trace_event_data_offsets_nfs4_idmap_event {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_nfs4_read_event {};\n\nstruct trace_event_data_offsets_nfs4_write_event {};\n\nstruct trace_event_data_offsets_nfs4_commit_event {};\n\ntypedef void (*btf_trace_nfs4_setclientid)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_setclientid_confirm)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_renew)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_renew_async)(void *, const struct nfs_client *, int);\n\ntypedef void (*btf_trace_nfs4_setup_sequence)(void *, const struct nfs4_session *, const struct nfs4_sequence_args *);\n\ntypedef void (*btf_trace_nfs4_state_mgr)(void *, const struct nfs_client *);\n\ntypedef void (*btf_trace_nfs4_state_mgr_failed)(void *, const struct nfs_client *, const char *, int);\n\ntypedef void (*btf_trace_nfs4_xdr_status)(void *, const struct xdr_stream *, u32, u32);\n\ntypedef void (*btf_trace_nfs_cb_no_clp)(void *, __be32, u32);\n\ntypedef void (*btf_trace_nfs_cb_badprinc)(void *, __be32, u32);\n\ntypedef void (*btf_trace_nfs4_open_reclaim)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_expired)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_open_file)(void *, const struct nfs_open_context *, int, int);\n\ntypedef void (*btf_trace_nfs4_cached_open)(void *, const struct nfs4_state *);\n\ntypedef void (*btf_trace_nfs4_close)(void *, const struct nfs4_state *, const struct nfs_closeargs *, const struct nfs_closeres *, int);\n\ntypedef void (*btf_trace_nfs4_get_lock)(void *, const struct file_lock *, const struct nfs4_state *, int, int);\n\ntypedef void (*btf_trace_nfs4_unlock)(void *, const struct file_lock *, const struct nfs4_state *, int, int);\n\ntypedef void (*btf_trace_nfs4_set_lock)(void *, const struct file_lock *, const struct nfs4_state *, const nfs4_stateid *, int, int);\n\ntypedef void (*btf_trace_nfs4_state_lock_reclaim)(void *, const struct nfs4_state *, const struct nfs4_lock_state *);\n\ntypedef void (*btf_trace_nfs4_set_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_reclaim_delegation)(void *, const struct inode *, fmode_t);\n\ntypedef void (*btf_trace_nfs4_delegreturn_exit)(void *, const struct nfs4_delegreturnargs *, const struct nfs4_delegreturnres *, int);\n\ntypedef void (*btf_trace_nfs4_lookup)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_symlink)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_mkdir)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_mknod)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_remove)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_get_fs_locations)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_secinfo)(void *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_lookupp)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_rename)(void *, const struct inode *, const struct qstr *, const struct inode *, const struct qstr *, int);\n\ntypedef void (*btf_trace_nfs4_access)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_readlink)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_readdir)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_get_acl)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_set_acl)(void *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_setattr)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_delegreturn)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_open_stateid_update_wait)(void *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_getattr)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_lookup_root)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_fsinfo)(void *, const struct nfs_server *, const struct nfs_fh *, const struct nfs_fattr *, int);\n\ntypedef void (*btf_trace_nfs4_cb_getattr)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, int);\n\ntypedef void (*btf_trace_nfs4_cb_recall)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_cb_layoutrecall_file)(void *, const struct nfs_client *, const struct nfs_fh *, const struct inode *, const nfs4_stateid *, int);\n\ntypedef void (*btf_trace_nfs4_map_name_to_uid)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_group_to_gid)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_uid_to_name)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_map_gid_to_group)(void *, const char *, int, u32, int);\n\ntypedef void (*btf_trace_nfs4_read)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_write)(void *, const struct nfs_pgio_header *, int);\n\ntypedef void (*btf_trace_nfs4_commit)(void *, const struct nfs_commit_data *, int);\n\nstruct getdents_callback___2 {\n\tstruct dir_context ctx;\n\tchar *name;\n\tu64 ino;\n\tint found;\n\tint sequence;\n};\n\nstruct nlm_lockowner {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct nlm_host *host;\n\tfl_owner_t owner;\n\tuint32_t pid;\n};\n\nstruct nsm_handle;\n\nstruct nlm_host {\n\tstruct hlist_node h_hash;\n\tstruct __kernel_sockaddr_storage h_addr;\n\tsize_t h_addrlen;\n\tstruct __kernel_sockaddr_storage h_srcaddr;\n\tsize_t h_srcaddrlen;\n\tstruct rpc_clnt *h_rpcclnt;\n\tchar *h_name;\n\tu32 h_version;\n\tshort unsigned int h_proto;\n\tshort unsigned int h_reclaiming: 1;\n\tshort unsigned int h_server: 1;\n\tshort unsigned int h_noresvport: 1;\n\tshort unsigned int h_inuse: 1;\n\twait_queue_head_t h_gracewait;\n\tstruct rw_semaphore h_rwsem;\n\tu32 h_state;\n\tu32 h_nsmstate;\n\tu32 h_pidcount;\n\trefcount_t h_count;\n\tstruct mutex h_mutex;\n\tlong unsigned int h_nextrebind;\n\tlong unsigned int h_expires;\n\tstruct list_head h_lockowners;\n\tspinlock_t h_lock;\n\tstruct list_head h_granted;\n\tstruct list_head h_reclaim;\n\tstruct nsm_handle *h_nsmhandle;\n\tchar *h_addrbuf;\n\tstruct net *net;\n\tconst struct cred *h_cred;\n\tchar nodename[65];\n\tconst struct nlmclnt_operations *h_nlmclnt_ops;\n};\n\nenum {\n\tNLM_LCK_GRANTED = 0,\n\tNLM_LCK_DENIED = 1,\n\tNLM_LCK_DENIED_NOLOCKS = 2,\n\tNLM_LCK_BLOCKED = 3,\n\tNLM_LCK_DENIED_GRACE_PERIOD = 4,\n\tNLM_DEADLCK = 5,\n\tNLM_ROFS = 6,\n\tNLM_STALE_FH = 7,\n\tNLM_FBIG = 8,\n\tNLM_FAILED = 9,\n};\n\nstruct nsm_private {\n\tunsigned char data[16];\n};\n\nstruct nlm_lock {\n\tchar *caller;\n\tunsigned int len;\n\tstruct nfs_fh fh;\n\tstruct xdr_netobj oh;\n\tu32 svid;\n\tstruct file_lock fl;\n};\n\nstruct nlm_cookie {\n\tunsigned char data[32];\n\tunsigned int len;\n};\n\nstruct nlm_args {\n\tstruct nlm_cookie cookie;\n\tstruct nlm_lock lock;\n\tu32 block;\n\tu32 reclaim;\n\tu32 state;\n\tu32 monitor;\n\tu32 fsm_access;\n\tu32 fsm_mode;\n};\n\nstruct nlm_res {\n\tstruct nlm_cookie cookie;\n\t__be32 status;\n\tstruct nlm_lock lock;\n};\n\nstruct nsm_handle {\n\tstruct list_head sm_link;\n\trefcount_t sm_count;\n\tchar *sm_mon_name;\n\tchar *sm_name;\n\tstruct __kernel_sockaddr_storage sm_addr;\n\tsize_t sm_addrlen;\n\tunsigned int sm_monitored: 1;\n\tunsigned int sm_sticky: 1;\n\tstruct nsm_private sm_priv;\n\tchar sm_addrbuf[51];\n};\n\nstruct nlm_block;\n\nstruct nlm_rqst {\n\trefcount_t a_count;\n\tunsigned int a_flags;\n\tstruct nlm_host *a_host;\n\tstruct nlm_args a_args;\n\tstruct nlm_res a_res;\n\tstruct nlm_block *a_block;\n\tunsigned int a_retries;\n\tu8 a_owner[74];\n\tvoid *a_callback_data;\n};\n\nstruct nlm_file;\n\nstruct nlm_block {\n\tstruct kref b_count;\n\tstruct list_head b_list;\n\tstruct list_head b_flist;\n\tstruct nlm_rqst *b_call;\n\tstruct svc_serv *b_daemon;\n\tstruct nlm_host *b_host;\n\tlong unsigned int b_when;\n\tunsigned int b_id;\n\tunsigned char b_granted;\n\tstruct nlm_file *b_file;\n\tstruct cache_req *b_cache_req;\n\tstruct cache_deferred_req *b_deferred_req;\n\tunsigned int b_flags;\n};\n\nstruct nlm_share;\n\nstruct nlm_file {\n\tstruct hlist_node f_list;\n\tstruct nfs_fh f_handle;\n\tstruct file *f_file;\n\tstruct nlm_share *f_shares;\n\tstruct list_head f_blocks;\n\tunsigned int f_locks;\n\tunsigned int f_count;\n\tstruct mutex f_mutex;\n};\n\nstruct nlm_wait {\n\tstruct list_head b_list;\n\twait_queue_head_t b_wait;\n\tstruct nlm_host *b_host;\n\tstruct file_lock *b_lock;\n\tshort unsigned int b_reclaim;\n\t__be32 b_status;\n};\n\nstruct nlm_wait___2;\n\nstruct nlm_reboot {\n\tchar *mon;\n\tunsigned int len;\n\tu32 state;\n\tstruct nsm_private priv;\n};\n\nstruct lockd_net {\n\tunsigned int nlmsvc_users;\n\tlong unsigned int next_gc;\n\tlong unsigned int nrhosts;\n\tstruct delayed_work grace_period_end;\n\tstruct lock_manager lockd_manager;\n\tstruct list_head nsm_handles;\n};\n\nstruct nlm_lookup_host_info {\n\tconst int server;\n\tconst struct sockaddr *sap;\n\tconst size_t salen;\n\tconst short unsigned int protocol;\n\tconst u32 version;\n\tconst char *hostname;\n\tconst size_t hostname_len;\n\tconst int noresvport;\n\tstruct net *net;\n\tconst struct cred *cred;\n};\n\nstruct ipv4_devconf {\n\tvoid *sysctl;\n\tint data[32];\n\tlong unsigned int state[1];\n};\n\nstruct in_ifaddr;\n\nstruct ip_mc_list;\n\nstruct in_device {\n\tstruct net_device *dev;\n\trefcount_t refcnt;\n\tint dead;\n\tstruct in_ifaddr *ifa_list;\n\tstruct ip_mc_list *mc_list;\n\tstruct ip_mc_list **mc_hash;\n\tint mc_count;\n\tspinlock_t mc_tomb_lock;\n\tstruct ip_mc_list *mc_tomb;\n\tlong unsigned int mr_v1_seen;\n\tlong unsigned int mr_v2_seen;\n\tlong unsigned int mr_maxdelay;\n\tlong unsigned int mr_qi;\n\tlong unsigned int mr_qri;\n\tunsigned char mr_qrv;\n\tunsigned char mr_gq_running;\n\tunsigned char mr_ifc_count;\n\tstruct timer_list mr_gq_timer;\n\tstruct timer_list mr_ifc_timer;\n\tstruct neigh_parms *arp_parms;\n\tstruct ipv4_devconf cnf;\n\tstruct callback_head callback_head;\n};\n\nstruct in_ifaddr {\n\tstruct hlist_node hash;\n\tstruct in_ifaddr *ifa_next;\n\tstruct in_device *ifa_dev;\n\tstruct callback_head callback_head;\n\t__be32 ifa_local;\n\t__be32 ifa_address;\n\t__be32 ifa_mask;\n\t__u32 ifa_rt_priority;\n\t__be32 ifa_broadcast;\n\tunsigned char ifa_scope;\n\tunsigned char ifa_prefixlen;\n\t__u32 ifa_flags;\n\tchar ifa_label[16];\n\t__u32 ifa_valid_lft;\n\t__u32 ifa_preferred_lft;\n\tlong unsigned int ifa_cstamp;\n\tlong unsigned int ifa_tstamp;\n};\n\nstruct inet6_ifaddr {\n\tstruct in6_addr addr;\n\t__u32 prefix_len;\n\t__u32 rt_priority;\n\t__u32 valid_lft;\n\t__u32 prefered_lft;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tint state;\n\t__u32 flags;\n\t__u8 dad_probes;\n\t__u8 stable_privacy_retry;\n\t__u16 scope;\n\t__u64 dad_nonce;\n\tlong unsigned int cstamp;\n\tlong unsigned int tstamp;\n\tstruct delayed_work dad_work;\n\tstruct inet6_dev *idev;\n\tstruct fib6_info *rt;\n\tstruct hlist_node addr_lst;\n\tstruct list_head if_list;\n\tstruct list_head tmp_list;\n\tstruct inet6_ifaddr *ifpub;\n\tint regen_count;\n\tbool tokenized;\n\tstruct callback_head rcu;\n\tstruct in6_addr peer_addr;\n};\n\ntypedef int (*nlm_host_match_fn_t)(void *, struct nlm_host *);\n\nstruct nlm_share {\n\tstruct nlm_share *s_next;\n\tstruct nlm_host *s_host;\n\tstruct nlm_file *s_file;\n\tstruct xdr_netobj s_owner;\n\tu32 s_access;\n\tu32 s_mode;\n};\n\nstruct rpc_version___2;\n\nstruct rpc_program___2;\n\nenum {\n\tNSMPROC_NULL = 0,\n\tNSMPROC_STAT = 1,\n\tNSMPROC_MON = 2,\n\tNSMPROC_UNMON = 3,\n\tNSMPROC_UNMON_ALL = 4,\n\tNSMPROC_SIMU_CRASH = 5,\n\tNSMPROC_NOTIFY = 6,\n};\n\nstruct nsm_args {\n\tstruct nsm_private *priv;\n\tu32 prog;\n\tu32 vers;\n\tu32 proc;\n\tchar *mon_name;\n\tconst char *nodename;\n};\n\nstruct nsm_res {\n\tu32 status;\n\tu32 state;\n};\n\ntypedef u32 unicode_t;\n\nstruct utf8_table {\n\tint cmask;\n\tint cval;\n\tint shift;\n\tlong int lmask;\n\tlong int lval;\n};\n\ntypedef unsigned int autofs_wqt_t;\n\nstruct autofs_sb_info;\n\nstruct autofs_info {\n\tstruct dentry *dentry;\n\tstruct inode *inode;\n\tint flags;\n\tstruct completion expire_complete;\n\tstruct list_head active;\n\tstruct list_head expiring;\n\tstruct autofs_sb_info *sbi;\n\tlong unsigned int last_used;\n\tint count;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct callback_head rcu;\n};\n\nstruct autofs_wait_queue;\n\nstruct autofs_sb_info {\n\tu32 magic;\n\tint pipefd;\n\tstruct file *pipe;\n\tstruct pid *oz_pgrp;\n\tint version;\n\tint sub_version;\n\tint min_proto;\n\tint max_proto;\n\tunsigned int flags;\n\tlong unsigned int exp_timeout;\n\tunsigned int type;\n\tstruct super_block *sb;\n\tstruct mutex wq_mutex;\n\tstruct mutex pipe_mutex;\n\tspinlock_t fs_lock;\n\tstruct autofs_wait_queue *queues;\n\tspinlock_t lookup_lock;\n\tstruct list_head active_list;\n\tstruct list_head expiring_list;\n\tstruct callback_head rcu;\n};\n\nstruct autofs_wait_queue {\n\twait_queue_head_t queue;\n\tstruct autofs_wait_queue *next;\n\tautofs_wqt_t wait_queue_token;\n\tstruct qstr name;\n\tu32 dev;\n\tu64 ino;\n\tkuid_t uid;\n\tkgid_t gid;\n\tpid_t pid;\n\tpid_t tgid;\n\tint status;\n\tunsigned int wait_ctr;\n};\n\nenum {\n\tOpt_err___5 = 0,\n\tOpt_fd = 1,\n\tOpt_uid___6 = 2,\n\tOpt_gid___7 = 3,\n\tOpt_pgrp = 4,\n\tOpt_minproto = 5,\n\tOpt_maxproto = 6,\n\tOpt_indirect = 7,\n\tOpt_direct = 8,\n\tOpt_offset = 9,\n\tOpt_strictexpire = 10,\n\tOpt_ignore___2 = 11,\n};\n\nenum {\n\tAUTOFS_IOC_READY_CMD = 96,\n\tAUTOFS_IOC_FAIL_CMD = 97,\n\tAUTOFS_IOC_CATATONIC_CMD = 98,\n\tAUTOFS_IOC_PROTOVER_CMD = 99,\n\tAUTOFS_IOC_SETTIMEOUT_CMD = 100,\n\tAUTOFS_IOC_EXPIRE_CMD = 101,\n};\n\nenum autofs_notify {\n\tNFY_NONE = 0,\n\tNFY_MOUNT = 1,\n\tNFY_EXPIRE = 2,\n};\n\nenum {\n\tAUTOFS_IOC_EXPIRE_MULTI_CMD = 102,\n\tAUTOFS_IOC_PROTOSUBVER_CMD = 103,\n\tAUTOFS_IOC_ASKUMOUNT_CMD = 112,\n};\n\nstruct autofs_packet_hdr {\n\tint proto_version;\n\tint type;\n};\n\nstruct autofs_packet_missing {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\tint len;\n\tchar name[256];\n};\n\nstruct autofs_packet_expire {\n\tstruct autofs_packet_hdr hdr;\n\tint len;\n\tchar name[256];\n};\n\nstruct autofs_packet_expire_multi {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\tint len;\n\tchar name[256];\n};\n\nunion autofs_packet_union {\n\tstruct autofs_packet_hdr hdr;\n\tstruct autofs_packet_missing missing;\n\tstruct autofs_packet_expire expire;\n\tstruct autofs_packet_expire_multi expire_multi;\n};\n\nstruct autofs_v5_packet {\n\tstruct autofs_packet_hdr hdr;\n\tautofs_wqt_t wait_queue_token;\n\t__u32 dev;\n\t__u64 ino;\n\t__u32 uid;\n\t__u32 gid;\n\t__u32 pid;\n\t__u32 tgid;\n\t__u32 len;\n\tchar name[256];\n};\n\ntypedef struct autofs_v5_packet autofs_packet_missing_indirect_t;\n\ntypedef struct autofs_v5_packet autofs_packet_expire_indirect_t;\n\ntypedef struct autofs_v5_packet autofs_packet_missing_direct_t;\n\ntypedef struct autofs_v5_packet autofs_packet_expire_direct_t;\n\nunion autofs_v5_packet_union {\n\tstruct autofs_packet_hdr hdr;\n\tstruct autofs_v5_packet v5_packet;\n\tautofs_packet_missing_indirect_t missing_indirect;\n\tautofs_packet_expire_indirect_t expire_indirect;\n\tautofs_packet_missing_direct_t missing_direct;\n\tautofs_packet_expire_direct_t expire_direct;\n};\n\nstruct args_protover {\n\t__u32 version;\n};\n\nstruct args_protosubver {\n\t__u32 sub_version;\n};\n\nstruct args_openmount {\n\t__u32 devid;\n};\n\nstruct args_ready {\n\t__u32 token;\n};\n\nstruct args_fail {\n\t__u32 token;\n\t__s32 status;\n};\n\nstruct args_setpipefd {\n\t__s32 pipefd;\n};\n\nstruct args_timeout {\n\t__u64 timeout;\n};\n\nstruct args_requester {\n\t__u32 uid;\n\t__u32 gid;\n};\n\nstruct args_expire {\n\t__u32 how;\n};\n\nstruct args_askumount {\n\t__u32 may_umount;\n};\n\nstruct args_in {\n\t__u32 type;\n};\n\nstruct args_out {\n\t__u32 devid;\n\t__u32 magic;\n};\n\nstruct args_ismountpoint {\n\tunion {\n\t\tstruct args_in in;\n\t\tstruct args_out out;\n\t};\n};\n\nstruct autofs_dev_ioctl {\n\t__u32 ver_major;\n\t__u32 ver_minor;\n\t__u32 size;\n\t__s32 ioctlfd;\n\tunion {\n\t\tstruct args_protover protover;\n\t\tstruct args_protosubver protosubver;\n\t\tstruct args_openmount openmount;\n\t\tstruct args_ready ready;\n\t\tstruct args_fail fail;\n\t\tstruct args_setpipefd setpipefd;\n\t\tstruct args_timeout timeout;\n\t\tstruct args_requester requester;\n\t\tstruct args_expire expire;\n\t\tstruct args_askumount askumount;\n\t\tstruct args_ismountpoint ismountpoint;\n\t};\n\tchar path[0];\n};\n\nenum {\n\tAUTOFS_DEV_IOCTL_VERSION_CMD = 113,\n\tAUTOFS_DEV_IOCTL_PROTOVER_CMD = 114,\n\tAUTOFS_DEV_IOCTL_PROTOSUBVER_CMD = 115,\n\tAUTOFS_DEV_IOCTL_OPENMOUNT_CMD = 116,\n\tAUTOFS_DEV_IOCTL_CLOSEMOUNT_CMD = 117,\n\tAUTOFS_DEV_IOCTL_READY_CMD = 118,\n\tAUTOFS_DEV_IOCTL_FAIL_CMD = 119,\n\tAUTOFS_DEV_IOCTL_SETPIPEFD_CMD = 120,\n\tAUTOFS_DEV_IOCTL_CATATONIC_CMD = 121,\n\tAUTOFS_DEV_IOCTL_TIMEOUT_CMD = 122,\n\tAUTOFS_DEV_IOCTL_REQUESTER_CMD = 123,\n\tAUTOFS_DEV_IOCTL_EXPIRE_CMD = 124,\n\tAUTOFS_DEV_IOCTL_ASKUMOUNT_CMD = 125,\n\tAUTOFS_DEV_IOCTL_ISMOUNTPOINT_CMD = 126,\n};\n\ntypedef int (*ioctl_fn)(struct file *, struct autofs_sb_info *, struct autofs_dev_ioctl *);\n\ntypedef struct vfsmount * (*debugfs_automount_t)(struct dentry *, void *);\n\nstruct debugfs_fsdata {\n\tconst struct file_operations *real_fops;\n\trefcount_t active_users;\n\tstruct completion active_users_drained;\n};\n\nstruct debugfs_mount_opts {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nenum {\n\tOpt_uid___7 = 0,\n\tOpt_gid___8 = 1,\n\tOpt_mode___6 = 2,\n\tOpt_err___6 = 3,\n};\n\nstruct debugfs_fs_info {\n\tstruct debugfs_mount_opts mount_opts;\n};\n\nstruct debugfs_reg32 {\n\tchar *name;\n\tlong unsigned int offset;\n};\n\nstruct debugfs_regset32 {\n\tconst struct debugfs_reg32 *regs;\n\tint nregs;\n\tvoid *base;\n\tstruct device *dev;\n};\n\nstruct array_data {\n\tvoid *array;\n\tu32 elements;\n};\n\nstruct debugfs_devm_entry {\n\tint (*read)(struct seq_file *, void *);\n\tstruct device *dev;\n};\n\nstruct tracefs_dir_ops {\n\tint (*mkdir)(const char *);\n\tint (*rmdir)(const char *);\n};\n\nstruct tracefs_mount_opts {\n\tkuid_t uid;\n\tkgid_t gid;\n\tumode_t mode;\n};\n\nstruct tracefs_fs_info {\n\tstruct tracefs_mount_opts mount_opts;\n};\n\ntypedef unsigned int __kernel_mode_t;\n\nstruct ipc64_perm {\n\t__kernel_key_t key;\n\t__kernel_uid32_t uid;\n\t__kernel_gid32_t gid;\n\t__kernel_uid32_t cuid;\n\t__kernel_gid32_t cgid;\n\t__kernel_mode_t mode;\n\tunsigned char __pad1[0];\n\tshort unsigned int seq;\n\tshort unsigned int __pad2;\n\t__kernel_ulong_t __unused1;\n\t__kernel_ulong_t __unused2;\n};\n\ntypedef s32 compat_key_t;\n\ntypedef u32 __compat_gid32_t;\n\nstruct compat_ipc64_perm {\n\tcompat_key_t key;\n\t__compat_uid32_t uid;\n\t__compat_gid32_t gid;\n\t__compat_uid32_t cuid;\n\t__compat_gid32_t cgid;\n\tshort unsigned int mode;\n\tshort unsigned int __pad1;\n\tshort unsigned int seq;\n\tshort unsigned int __pad2;\n\tcompat_ulong_t unused1;\n\tcompat_ulong_t unused2;\n};\n\nstruct compat_ipc_perm {\n\tkey_t key;\n\t__compat_uid_t uid;\n\t__compat_gid_t gid;\n\t__compat_uid_t cuid;\n\t__compat_gid_t cgid;\n\tcompat_mode_t mode;\n\tshort unsigned int seq;\n};\n\nstruct ipc_perm {\n\t__kernel_key_t key;\n\t__kernel_uid_t uid;\n\t__kernel_gid_t gid;\n\t__kernel_uid_t cuid;\n\t__kernel_gid_t cgid;\n\t__kernel_mode_t mode;\n\tshort unsigned int seq;\n};\n\nstruct ipc_params {\n\tkey_t key;\n\tint flg;\n\tunion {\n\t\tsize_t size;\n\t\tint nsems;\n\t} u;\n};\n\nstruct ipc_ops {\n\tint (*getnew)(struct ipc_namespace *, struct ipc_params *);\n\tint (*associate)(struct kern_ipc_perm *, int);\n\tint (*more_checks)(struct kern_ipc_perm *, struct ipc_params *);\n};\n\nstruct ipc_proc_iface {\n\tconst char *path;\n\tconst char *header;\n\tint ids;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct ipc_proc_iter {\n\tstruct ipc_namespace *ns;\n\tstruct pid_namespace *pid_ns;\n\tstruct ipc_proc_iface *iface;\n};\n\nstruct msg_msgseg;\n\nstruct msg_msg {\n\tstruct list_head m_list;\n\tlong int m_type;\n\tsize_t m_ts;\n\tstruct msg_msgseg *next;\n\tvoid *security;\n};\n\nstruct msg_msgseg {\n\tstruct msg_msgseg *next;\n};\n\ntypedef int __kernel_ipc_pid_t;\n\nstruct msgbuf {\n\t__kernel_long_t mtype;\n\tchar mtext[1];\n};\n\nstruct msg;\n\nstruct msqid_ds {\n\tstruct ipc_perm msg_perm;\n\tstruct msg *msg_first;\n\tstruct msg *msg_last;\n\t__kernel_old_time_t msg_stime;\n\t__kernel_old_time_t msg_rtime;\n\t__kernel_old_time_t msg_ctime;\n\tlong unsigned int msg_lcbytes;\n\tlong unsigned int msg_lqbytes;\n\tshort unsigned int msg_cbytes;\n\tshort unsigned int msg_qnum;\n\tshort unsigned int msg_qbytes;\n\t__kernel_ipc_pid_t msg_lspid;\n\t__kernel_ipc_pid_t msg_lrpid;\n};\n\nstruct msqid64_ds {\n\tstruct ipc64_perm msg_perm;\n\tlong int msg_stime;\n\tlong int msg_rtime;\n\tlong int msg_ctime;\n\tlong unsigned int msg_cbytes;\n\tlong unsigned int msg_qnum;\n\tlong unsigned int msg_qbytes;\n\t__kernel_pid_t msg_lspid;\n\t__kernel_pid_t msg_lrpid;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct msginfo {\n\tint msgpool;\n\tint msgmap;\n\tint msgmax;\n\tint msgmnb;\n\tint msgmni;\n\tint msgssz;\n\tint msgtql;\n\tshort unsigned int msgseg;\n};\n\ntypedef u16 compat_ipc_pid_t;\n\nstruct compat_msqid64_ds {\n\tstruct compat_ipc64_perm msg_perm;\n\tcompat_ulong_t msg_stime;\n\tcompat_ulong_t msg_stime_high;\n\tcompat_ulong_t msg_rtime;\n\tcompat_ulong_t msg_rtime_high;\n\tcompat_ulong_t msg_ctime;\n\tcompat_ulong_t msg_ctime_high;\n\tcompat_ulong_t msg_cbytes;\n\tcompat_ulong_t msg_qnum;\n\tcompat_ulong_t msg_qbytes;\n\tcompat_pid_t msg_lspid;\n\tcompat_pid_t msg_lrpid;\n\tcompat_ulong_t __unused4;\n\tcompat_ulong_t __unused5;\n};\n\nstruct msg_queue {\n\tstruct kern_ipc_perm q_perm;\n\ttime64_t q_stime;\n\ttime64_t q_rtime;\n\ttime64_t q_ctime;\n\tlong unsigned int q_cbytes;\n\tlong unsigned int q_qnum;\n\tlong unsigned int q_qbytes;\n\tstruct pid *q_lspid;\n\tstruct pid *q_lrpid;\n\tstruct list_head q_messages;\n\tstruct list_head q_receivers;\n\tstruct list_head q_senders;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct msg_receiver {\n\tstruct list_head r_list;\n\tstruct task_struct *r_tsk;\n\tint r_mode;\n\tlong int r_msgtype;\n\tlong int r_maxsize;\n\tstruct msg_msg *r_msg;\n};\n\nstruct msg_sender {\n\tstruct list_head list;\n\tstruct task_struct *tsk;\n\tsize_t msgsz;\n};\n\nstruct compat_msqid_ds {\n\tstruct compat_ipc_perm msg_perm;\n\tcompat_uptr_t msg_first;\n\tcompat_uptr_t msg_last;\n\told_time32_t msg_stime;\n\told_time32_t msg_rtime;\n\told_time32_t msg_ctime;\n\tcompat_ulong_t msg_lcbytes;\n\tcompat_ulong_t msg_lqbytes;\n\tshort unsigned int msg_cbytes;\n\tshort unsigned int msg_qnum;\n\tshort unsigned int msg_qbytes;\n\tcompat_ipc_pid_t msg_lspid;\n\tcompat_ipc_pid_t msg_lrpid;\n};\n\nstruct compat_msgbuf {\n\tcompat_long_t mtype;\n\tchar mtext[1];\n};\n\nstruct sem;\n\nstruct sem_queue;\n\nstruct sem_undo;\n\nstruct semid_ds {\n\tstruct ipc_perm sem_perm;\n\t__kernel_old_time_t sem_otime;\n\t__kernel_old_time_t sem_ctime;\n\tstruct sem *sem_base;\n\tstruct sem_queue *sem_pending;\n\tstruct sem_queue **sem_pending_last;\n\tstruct sem_undo *undo;\n\tshort unsigned int sem_nsems;\n};\n\nstruct sem {\n\tint semval;\n\tstruct pid *sempid;\n\tspinlock_t lock;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\ttime64_t sem_otime;\n};\n\nstruct sembuf;\n\nstruct sem_queue {\n\tstruct list_head list;\n\tstruct task_struct *sleeper;\n\tstruct sem_undo *undo;\n\tstruct pid *pid;\n\tint status;\n\tstruct sembuf *sops;\n\tstruct sembuf *blocking;\n\tint nsops;\n\tbool alter;\n\tbool dupsop;\n};\n\nstruct sem_undo {\n\tstruct list_head list_proc;\n\tstruct callback_head rcu;\n\tstruct sem_undo_list *ulp;\n\tstruct list_head list_id;\n\tint semid;\n\tshort int *semadj;\n};\n\nstruct semid64_ds {\n\tstruct ipc64_perm sem_perm;\n\t__kernel_long_t sem_otime;\n\t__kernel_ulong_t __unused1;\n\t__kernel_long_t sem_ctime;\n\t__kernel_ulong_t __unused2;\n\t__kernel_ulong_t sem_nsems;\n\t__kernel_ulong_t __unused3;\n\t__kernel_ulong_t __unused4;\n};\n\nstruct sembuf {\n\tshort unsigned int sem_num;\n\tshort int sem_op;\n\tshort int sem_flg;\n};\n\nstruct seminfo {\n\tint semmap;\n\tint semmni;\n\tint semmns;\n\tint semmnu;\n\tint semmsl;\n\tint semopm;\n\tint semume;\n\tint semusz;\n\tint semvmx;\n\tint semaem;\n};\n\nstruct sem_undo_list {\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tstruct list_head list_proc;\n};\n\nstruct compat_semid64_ds {\n\tstruct compat_ipc64_perm sem_perm;\n\tcompat_ulong_t sem_otime;\n\tcompat_ulong_t sem_otime_high;\n\tcompat_ulong_t sem_ctime;\n\tcompat_ulong_t sem_ctime_high;\n\tcompat_ulong_t sem_nsems;\n\tcompat_ulong_t __unused3;\n\tcompat_ulong_t __unused4;\n};\n\nstruct sem_array {\n\tstruct kern_ipc_perm sem_perm;\n\ttime64_t sem_ctime;\n\tstruct list_head pending_alter;\n\tstruct list_head pending_const;\n\tstruct list_head list_id;\n\tint sem_nsems;\n\tint complex_count;\n\tunsigned int use_global_lock;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct sem sems[0];\n};\n\nstruct compat_semid_ds {\n\tstruct compat_ipc_perm sem_perm;\n\told_time32_t sem_otime;\n\told_time32_t sem_ctime;\n\tcompat_uptr_t sem_base;\n\tcompat_uptr_t sem_pending;\n\tcompat_uptr_t sem_pending_last;\n\tcompat_uptr_t undo;\n\tshort unsigned int sem_nsems;\n};\n\nstruct shmid_ds {\n\tstruct ipc_perm shm_perm;\n\tint shm_segsz;\n\t__kernel_old_time_t shm_atime;\n\t__kernel_old_time_t shm_dtime;\n\t__kernel_old_time_t shm_ctime;\n\t__kernel_ipc_pid_t shm_cpid;\n\t__kernel_ipc_pid_t shm_lpid;\n\tshort unsigned int shm_nattch;\n\tshort unsigned int shm_unused;\n\tvoid *shm_unused2;\n\tvoid *shm_unused3;\n};\n\nstruct shmid64_ds {\n\tstruct ipc64_perm shm_perm;\n\tsize_t shm_segsz;\n\tlong int shm_atime;\n\tlong int shm_dtime;\n\tlong int shm_ctime;\n\t__kernel_pid_t shm_cpid;\n\t__kernel_pid_t shm_lpid;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int __unused4;\n\tlong unsigned int __unused5;\n};\n\nstruct shminfo64 {\n\tlong unsigned int shmmax;\n\tlong unsigned int shmmin;\n\tlong unsigned int shmmni;\n\tlong unsigned int shmseg;\n\tlong unsigned int shmall;\n\tlong unsigned int __unused1;\n\tlong unsigned int __unused2;\n\tlong unsigned int __unused3;\n\tlong unsigned int __unused4;\n};\n\nstruct shminfo {\n\tint shmmax;\n\tint shmmin;\n\tint shmmni;\n\tint shmseg;\n\tint shmall;\n};\n\nstruct shm_info {\n\tint used_ids;\n\t__kernel_ulong_t shm_tot;\n\t__kernel_ulong_t shm_rss;\n\t__kernel_ulong_t shm_swp;\n\t__kernel_ulong_t swap_attempts;\n\t__kernel_ulong_t swap_successes;\n};\n\nstruct compat_shmid64_ds {\n\tstruct compat_ipc64_perm shm_perm;\n\tcompat_size_t shm_segsz;\n\tcompat_ulong_t shm_atime;\n\tcompat_ulong_t shm_atime_high;\n\tcompat_ulong_t shm_dtime;\n\tcompat_ulong_t shm_dtime_high;\n\tcompat_ulong_t shm_ctime;\n\tcompat_ulong_t shm_ctime_high;\n\tcompat_pid_t shm_cpid;\n\tcompat_pid_t shm_lpid;\n\tcompat_ulong_t shm_nattch;\n\tcompat_ulong_t __unused4;\n\tcompat_ulong_t __unused5;\n};\n\nstruct shmid_kernel {\n\tstruct kern_ipc_perm shm_perm;\n\tstruct file *shm_file;\n\tlong unsigned int shm_nattch;\n\tlong unsigned int shm_segsz;\n\ttime64_t shm_atim;\n\ttime64_t shm_dtim;\n\ttime64_t shm_ctim;\n\tstruct pid *shm_cprid;\n\tstruct pid *shm_lprid;\n\tstruct user_struct *mlock_user;\n\tstruct task_struct *shm_creator;\n\tstruct list_head shm_clist;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct shm_file_data {\n\tint id;\n\tstruct ipc_namespace *ns;\n\tstruct file *file;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct compat_shmid_ds {\n\tstruct compat_ipc_perm shm_perm;\n\tint shm_segsz;\n\told_time32_t shm_atime;\n\told_time32_t shm_dtime;\n\told_time32_t shm_ctime;\n\tcompat_ipc_pid_t shm_cpid;\n\tcompat_ipc_pid_t shm_lpid;\n\tshort unsigned int shm_nattch;\n\tshort unsigned int shm_unused;\n\tcompat_uptr_t shm_unused2;\n\tcompat_uptr_t shm_unused3;\n};\n\nstruct compat_shminfo64 {\n\tcompat_ulong_t shmmax;\n\tcompat_ulong_t shmmin;\n\tcompat_ulong_t shmmni;\n\tcompat_ulong_t shmseg;\n\tcompat_ulong_t shmall;\n\tcompat_ulong_t __unused1;\n\tcompat_ulong_t __unused2;\n\tcompat_ulong_t __unused3;\n\tcompat_ulong_t __unused4;\n};\n\nstruct compat_shm_info {\n\tcompat_int_t used_ids;\n\tcompat_ulong_t shm_tot;\n\tcompat_ulong_t shm_rss;\n\tcompat_ulong_t shm_swp;\n\tcompat_ulong_t swap_attempts;\n\tcompat_ulong_t swap_successes;\n};\n\nstruct compat_ipc_kludge {\n\tcompat_uptr_t msgp;\n\tcompat_long_t msgtyp;\n};\n\nstruct mqueue_fs_context {\n\tstruct ipc_namespace *ipc_ns;\n};\n\nstruct posix_msg_tree_node {\n\tstruct rb_node rb_node;\n\tstruct list_head msg_list;\n\tint priority;\n};\n\nstruct ext_wait_queue {\n\tstruct task_struct *task;\n\tstruct list_head list;\n\tstruct msg_msg *msg;\n\tint state;\n};\n\nstruct mqueue_inode_info {\n\tspinlock_t lock;\n\tstruct inode vfs_inode;\n\twait_queue_head_t wait_q;\n\tstruct rb_root msg_tree;\n\tstruct rb_node *msg_tree_rightmost;\n\tstruct posix_msg_tree_node *node_cache;\n\tstruct mq_attr attr;\n\tstruct sigevent notify;\n\tstruct pid *notify_owner;\n\tu32 notify_self_exec_id;\n\tstruct user_namespace *notify_user_ns;\n\tstruct user_struct *user;\n\tstruct sock *notify_sock;\n\tstruct sk_buff *notify_cookie;\n\tstruct ext_wait_queue e_wait_q[2];\n\tlong unsigned int qsize;\n};\n\nstruct compat_mq_attr {\n\tcompat_long_t mq_flags;\n\tcompat_long_t mq_maxmsg;\n\tcompat_long_t mq_msgsize;\n\tcompat_long_t mq_curmsgs;\n\tcompat_long_t __reserved[4];\n};\n\nenum key_state {\n\tKEY_IS_UNINSTANTIATED = 0,\n\tKEY_IS_POSITIVE = 1,\n};\n\nstruct key_user {\n\tstruct rb_node node;\n\tstruct mutex cons_lock;\n\tspinlock_t lock;\n\trefcount_t usage;\n\tatomic_t nkeys;\n\tatomic_t nikeys;\n\tkuid_t uid;\n\tint qnkeys;\n\tint qnbytes;\n};\n\nenum key_need_perm {\n\tKEY_NEED_UNSPECIFIED = 0,\n\tKEY_NEED_VIEW = 1,\n\tKEY_NEED_READ = 2,\n\tKEY_NEED_WRITE = 3,\n\tKEY_NEED_SEARCH = 4,\n\tKEY_NEED_LINK = 5,\n\tKEY_NEED_SETATTR = 6,\n\tKEY_NEED_UNLINK = 7,\n\tKEY_SYSADMIN_OVERRIDE = 8,\n\tKEY_AUTHTOKEN_OVERRIDE = 9,\n\tKEY_DEFER_PERM_CHECK = 10,\n};\n\nenum key_notification_subtype {\n\tNOTIFY_KEY_INSTANTIATED = 0,\n\tNOTIFY_KEY_UPDATED = 1,\n\tNOTIFY_KEY_LINKED = 2,\n\tNOTIFY_KEY_UNLINKED = 3,\n\tNOTIFY_KEY_CLEARED = 4,\n\tNOTIFY_KEY_REVOKED = 5,\n\tNOTIFY_KEY_INVALIDATED = 6,\n\tNOTIFY_KEY_SETATTR = 7,\n};\n\nstruct assoc_array_edit;\n\nstruct assoc_array_ops {\n\tlong unsigned int (*get_key_chunk)(const void *, int);\n\tlong unsigned int (*get_object_key_chunk)(const void *, int);\n\tbool (*compare_object)(const void *, const void *);\n\tint (*diff_objects)(const void *, const void *);\n\tvoid (*free_object)(void *);\n};\n\nstruct assoc_array_node {\n\tstruct assoc_array_ptr *back_pointer;\n\tu8 parent_slot;\n\tstruct assoc_array_ptr *slots[16];\n\tlong unsigned int nr_leaves_on_branch;\n};\n\nstruct assoc_array_shortcut {\n\tstruct assoc_array_ptr *back_pointer;\n\tint parent_slot;\n\tint skip_to_level;\n\tstruct assoc_array_ptr *next_node;\n\tlong unsigned int index_key[0];\n};\n\nstruct assoc_array_edit___2 {\n\tstruct callback_head rcu;\n\tstruct assoc_array *array;\n\tconst struct assoc_array_ops *ops;\n\tconst struct assoc_array_ops *ops_for_excised_subtree;\n\tstruct assoc_array_ptr *leaf;\n\tstruct assoc_array_ptr **leaf_p;\n\tstruct assoc_array_ptr *dead_leaf;\n\tstruct assoc_array_ptr *new_meta[3];\n\tstruct assoc_array_ptr *excised_meta[1];\n\tstruct assoc_array_ptr *excised_subtree;\n\tstruct assoc_array_ptr **set_backpointers[16];\n\tstruct assoc_array_ptr *set_backpointers_to;\n\tstruct assoc_array_node *adjust_count_on;\n\tlong int adjust_count_by;\n\tstruct {\n\t\tstruct assoc_array_ptr **ptr;\n\t\tstruct assoc_array_ptr *to;\n\t} set[2];\n\tstruct {\n\t\tu8 *p;\n\t\tu8 to;\n\t} set_parent_slot[1];\n\tu8 segment_cache[17];\n};\n\nstruct keyring_search_context {\n\tstruct keyring_index_key index_key;\n\tconst struct cred *cred;\n\tstruct key_match_data match_data;\n\tunsigned int flags;\n\tint (*iterator)(const void *, void *);\n\tint skipped_ret;\n\tbool possessed;\n\tkey_ref_t result;\n\ttime64_t now;\n};\n\nstruct keyring_read_iterator_context {\n\tsize_t buflen;\n\tsize_t count;\n\tkey_serial_t *buffer;\n};\n\nstruct keyctl_dh_params {\n\tunion {\n\t\t__s32 private;\n\t\t__s32 priv;\n\t};\n\t__s32 prime;\n\t__s32 base;\n};\n\nstruct keyctl_kdf_params {\n\tchar *hashname;\n\tchar *otherinfo;\n\t__u32 otherinfolen;\n\t__u32 __spare[8];\n};\n\nstruct keyctl_pkey_query {\n\t__u32 supported_ops;\n\t__u32 key_size;\n\t__u16 max_data_size;\n\t__u16 max_sig_size;\n\t__u16 max_enc_size;\n\t__u16 max_dec_size;\n\t__u32 __spare[10];\n};\n\nstruct keyctl_pkey_params {\n\t__s32 key_id;\n\t__u32 in_len;\n\tunion {\n\t\t__u32 out_len;\n\t\t__u32 in2_len;\n\t};\n\t__u32 __spare[7];\n};\n\nenum {\n\tOpt_err___7 = 0,\n\tOpt_enc = 1,\n\tOpt_hash = 2,\n};\n\nstruct vfs_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n};\n\nstruct vfs_ns_cap_data {\n\t__le32 magic_etc;\n\tstruct {\n\t\t__le32 permitted;\n\t\t__le32 inheritable;\n\t} data[2];\n\t__le32 rootid;\n};\n\nstruct sctp_endpoint;\n\nunion security_list_options {\n\tint (*binder_set_context_mgr)(struct task_struct *);\n\tint (*binder_transaction)(struct task_struct *, struct task_struct *);\n\tint (*binder_transfer_binder)(struct task_struct *, struct task_struct *);\n\tint (*binder_transfer_file)(struct task_struct *, struct task_struct *, struct file *);\n\tint (*ptrace_access_check)(struct task_struct *, unsigned int);\n\tint (*ptrace_traceme)(struct task_struct *);\n\tint (*capget)(struct task_struct *, kernel_cap_t *, kernel_cap_t *, kernel_cap_t *);\n\tint (*capset)(struct cred *, const struct cred *, const kernel_cap_t *, const kernel_cap_t *, const kernel_cap_t *);\n\tint (*capable)(const struct cred *, struct user_namespace *, int, unsigned int);\n\tint (*quotactl)(int, int, int, struct super_block *);\n\tint (*quota_on)(struct dentry *);\n\tint (*syslog)(int);\n\tint (*settime)(const struct timespec64 *, const struct timezone *);\n\tint (*vm_enough_memory)(struct mm_struct *, long int);\n\tint (*bprm_creds_for_exec)(struct linux_binprm *);\n\tint (*bprm_creds_from_file)(struct linux_binprm *, struct file *);\n\tint (*bprm_check_security)(struct linux_binprm *);\n\tvoid (*bprm_committing_creds)(struct linux_binprm *);\n\tvoid (*bprm_committed_creds)(struct linux_binprm *);\n\tint (*fs_context_dup)(struct fs_context *, struct fs_context *);\n\tint (*fs_context_parse_param)(struct fs_context *, struct fs_parameter *);\n\tint (*sb_alloc_security)(struct super_block *);\n\tvoid (*sb_free_security)(struct super_block *);\n\tvoid (*sb_free_mnt_opts)(void *);\n\tint (*sb_eat_lsm_opts)(char *, void **);\n\tint (*sb_remount)(struct super_block *, void *);\n\tint (*sb_kern_mount)(struct super_block *);\n\tint (*sb_show_options)(struct seq_file *, struct super_block *);\n\tint (*sb_statfs)(struct dentry *);\n\tint (*sb_mount)(const char *, const struct path *, const char *, long unsigned int, void *);\n\tint (*sb_umount)(struct vfsmount *, int);\n\tint (*sb_pivotroot)(const struct path *, const struct path *);\n\tint (*sb_set_mnt_opts)(struct super_block *, void *, long unsigned int, long unsigned int *);\n\tint (*sb_clone_mnt_opts)(const struct super_block *, struct super_block *, long unsigned int, long unsigned int *);\n\tint (*sb_add_mnt_opt)(const char *, const char *, int, void **);\n\tint (*move_mount)(const struct path *, const struct path *);\n\tint (*dentry_init_security)(struct dentry *, int, const struct qstr *, void **, u32 *);\n\tint (*dentry_create_files_as)(struct dentry *, int, struct qstr *, const struct cred *, struct cred *);\n\tint (*path_notify)(const struct path *, u64, unsigned int);\n\tint (*inode_alloc_security)(struct inode *);\n\tvoid (*inode_free_security)(struct inode *);\n\tint (*inode_init_security)(struct inode *, struct inode *, const struct qstr *, const char **, void **, size_t *);\n\tint (*inode_create)(struct inode *, struct dentry *, umode_t);\n\tint (*inode_link)(struct dentry *, struct inode *, struct dentry *);\n\tint (*inode_unlink)(struct inode *, struct dentry *);\n\tint (*inode_symlink)(struct inode *, struct dentry *, const char *);\n\tint (*inode_mkdir)(struct inode *, struct dentry *, umode_t);\n\tint (*inode_rmdir)(struct inode *, struct dentry *);\n\tint (*inode_mknod)(struct inode *, struct dentry *, umode_t, dev_t);\n\tint (*inode_rename)(struct inode *, struct dentry *, struct inode *, struct dentry *);\n\tint (*inode_readlink)(struct dentry *);\n\tint (*inode_follow_link)(struct dentry *, struct inode *, bool);\n\tint (*inode_permission)(struct inode *, int);\n\tint (*inode_setattr)(struct dentry *, struct iattr *);\n\tint (*inode_getattr)(const struct path *);\n\tint (*inode_setxattr)(struct dentry *, const char *, const void *, size_t, int);\n\tvoid (*inode_post_setxattr)(struct dentry *, const char *, const void *, size_t, int);\n\tint (*inode_getxattr)(struct dentry *, const char *);\n\tint (*inode_listxattr)(struct dentry *);\n\tint (*inode_removexattr)(struct dentry *, const char *);\n\tint (*inode_need_killpriv)(struct dentry *);\n\tint (*inode_killpriv)(struct dentry *);\n\tint (*inode_getsecurity)(struct inode *, const char *, void **, bool);\n\tint (*inode_setsecurity)(struct inode *, const char *, const void *, size_t, int);\n\tint (*inode_listsecurity)(struct inode *, char *, size_t);\n\tvoid (*inode_getsecid)(struct inode *, u32 *);\n\tint (*inode_copy_up)(struct dentry *, struct cred **);\n\tint (*inode_copy_up_xattr)(const char *);\n\tint (*kernfs_init_security)(struct kernfs_node *, struct kernfs_node *);\n\tint (*file_permission)(struct file *, int);\n\tint (*file_alloc_security)(struct file *);\n\tvoid (*file_free_security)(struct file *);\n\tint (*file_ioctl)(struct file *, unsigned int, long unsigned int);\n\tint (*mmap_addr)(long unsigned int);\n\tint (*mmap_file)(struct file *, long unsigned int, long unsigned int, long unsigned int);\n\tint (*file_mprotect)(struct vm_area_struct *, long unsigned int, long unsigned int);\n\tint (*file_lock)(struct file *, unsigned int);\n\tint (*file_fcntl)(struct file *, unsigned int, long unsigned int);\n\tvoid (*file_set_fowner)(struct file *);\n\tint (*file_send_sigiotask)(struct task_struct *, struct fown_struct *, int);\n\tint (*file_receive)(struct file *);\n\tint (*file_open)(struct file *);\n\tint (*task_alloc)(struct task_struct *, long unsigned int);\n\tvoid (*task_free)(struct task_struct *);\n\tint (*cred_alloc_blank)(struct cred *, gfp_t);\n\tvoid (*cred_free)(struct cred *);\n\tint (*cred_prepare)(struct cred *, const struct cred *, gfp_t);\n\tvoid (*cred_transfer)(struct cred *, const struct cred *);\n\tvoid (*cred_getsecid)(const struct cred *, u32 *);\n\tint (*kernel_act_as)(struct cred *, u32);\n\tint (*kernel_create_files_as)(struct cred *, struct inode *);\n\tint (*kernel_module_request)(char *);\n\tint (*kernel_load_data)(enum kernel_load_data_id);\n\tint (*kernel_read_file)(struct file *, enum kernel_read_file_id);\n\tint (*kernel_post_read_file)(struct file *, char *, loff_t, enum kernel_read_file_id);\n\tint (*task_fix_setuid)(struct cred *, const struct cred *, int);\n\tint (*task_fix_setgid)(struct cred *, const struct cred *, int);\n\tint (*task_setpgid)(struct task_struct *, pid_t);\n\tint (*task_getpgid)(struct task_struct *);\n\tint (*task_getsid)(struct task_struct *);\n\tvoid (*task_getsecid)(struct task_struct *, u32 *);\n\tint (*task_setnice)(struct task_struct *, int);\n\tint (*task_setioprio)(struct task_struct *, int);\n\tint (*task_getioprio)(struct task_struct *);\n\tint (*task_prlimit)(const struct cred *, const struct cred *, unsigned int);\n\tint (*task_setrlimit)(struct task_struct *, unsigned int, struct rlimit *);\n\tint (*task_setscheduler)(struct task_struct *);\n\tint (*task_getscheduler)(struct task_struct *);\n\tint (*task_movememory)(struct task_struct *);\n\tint (*task_kill)(struct task_struct *, struct kernel_siginfo *, int, const struct cred *);\n\tint (*task_prctl)(int, long unsigned int, long unsigned int, long unsigned int, long unsigned int);\n\tvoid (*task_to_inode)(struct task_struct *, struct inode *);\n\tint (*ipc_permission)(struct kern_ipc_perm *, short int);\n\tvoid (*ipc_getsecid)(struct kern_ipc_perm *, u32 *);\n\tint (*msg_msg_alloc_security)(struct msg_msg *);\n\tvoid (*msg_msg_free_security)(struct msg_msg *);\n\tint (*msg_queue_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*msg_queue_free_security)(struct kern_ipc_perm *);\n\tint (*msg_queue_associate)(struct kern_ipc_perm *, int);\n\tint (*msg_queue_msgctl)(struct kern_ipc_perm *, int);\n\tint (*msg_queue_msgsnd)(struct kern_ipc_perm *, struct msg_msg *, int);\n\tint (*msg_queue_msgrcv)(struct kern_ipc_perm *, struct msg_msg *, struct task_struct *, long int, int);\n\tint (*shm_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*shm_free_security)(struct kern_ipc_perm *);\n\tint (*shm_associate)(struct kern_ipc_perm *, int);\n\tint (*shm_shmctl)(struct kern_ipc_perm *, int);\n\tint (*shm_shmat)(struct kern_ipc_perm *, char *, int);\n\tint (*sem_alloc_security)(struct kern_ipc_perm *);\n\tvoid (*sem_free_security)(struct kern_ipc_perm *);\n\tint (*sem_associate)(struct kern_ipc_perm *, int);\n\tint (*sem_semctl)(struct kern_ipc_perm *, int);\n\tint (*sem_semop)(struct kern_ipc_perm *, struct sembuf *, unsigned int, int);\n\tint (*netlink_send)(struct sock *, struct sk_buff *);\n\tvoid (*d_instantiate)(struct dentry *, struct inode *);\n\tint (*getprocattr)(struct task_struct *, char *, char **);\n\tint (*setprocattr)(const char *, void *, size_t);\n\tint (*ismaclabel)(const char *);\n\tint (*secid_to_secctx)(u32, char **, u32 *);\n\tint (*secctx_to_secid)(const char *, u32, u32 *);\n\tvoid (*release_secctx)(char *, u32);\n\tvoid (*inode_invalidate_secctx)(struct inode *);\n\tint (*inode_notifysecctx)(struct inode *, void *, u32);\n\tint (*inode_setsecctx)(struct dentry *, void *, u32);\n\tint (*inode_getsecctx)(struct inode *, void **, u32 *);\n\tint (*unix_stream_connect)(struct sock *, struct sock *, struct sock *);\n\tint (*unix_may_send)(struct socket *, struct socket *);\n\tint (*socket_create)(int, int, int, int);\n\tint (*socket_post_create)(struct socket *, int, int, int, int);\n\tint (*socket_socketpair)(struct socket *, struct socket *);\n\tint (*socket_bind)(struct socket *, struct sockaddr *, int);\n\tint (*socket_connect)(struct socket *, struct sockaddr *, int);\n\tint (*socket_listen)(struct socket *, int);\n\tint (*socket_accept)(struct socket *, struct socket *);\n\tint (*socket_sendmsg)(struct socket *, struct msghdr *, int);\n\tint (*socket_recvmsg)(struct socket *, struct msghdr *, int, int);\n\tint (*socket_getsockname)(struct socket *);\n\tint (*socket_getpeername)(struct socket *);\n\tint (*socket_getsockopt)(struct socket *, int, int);\n\tint (*socket_setsockopt)(struct socket *, int, int);\n\tint (*socket_shutdown)(struct socket *, int);\n\tint (*socket_sock_rcv_skb)(struct sock *, struct sk_buff *);\n\tint (*socket_getpeersec_stream)(struct socket *, char *, int *, unsigned int);\n\tint (*socket_getpeersec_dgram)(struct socket *, struct sk_buff *, u32 *);\n\tint (*sk_alloc_security)(struct sock *, int, gfp_t);\n\tvoid (*sk_free_security)(struct sock *);\n\tvoid (*sk_clone_security)(const struct sock *, struct sock *);\n\tvoid (*sk_getsecid)(struct sock *, u32 *);\n\tvoid (*sock_graft)(struct sock *, struct socket *);\n\tint (*inet_conn_request)(struct sock *, struct sk_buff *, struct request_sock *);\n\tvoid (*inet_csk_clone)(struct sock *, const struct request_sock *);\n\tvoid (*inet_conn_established)(struct sock *, struct sk_buff *);\n\tint (*secmark_relabel_packet)(u32);\n\tvoid (*secmark_refcount_inc)();\n\tvoid (*secmark_refcount_dec)();\n\tvoid (*req_classify_flow)(const struct request_sock *, struct flowi *);\n\tint (*tun_dev_alloc_security)(void **);\n\tvoid (*tun_dev_free_security)(void *);\n\tint (*tun_dev_create)();\n\tint (*tun_dev_attach_queue)(void *);\n\tint (*tun_dev_attach)(struct sock *, void *);\n\tint (*tun_dev_open)(void *);\n\tint (*sctp_assoc_request)(struct sctp_endpoint *, struct sk_buff *);\n\tint (*sctp_bind_connect)(struct sock *, int, struct sockaddr *, int);\n\tvoid (*sctp_sk_clone)(struct sctp_endpoint *, struct sock *, struct sock *);\n\tint (*key_alloc)(struct key *, const struct cred *, long unsigned int);\n\tvoid (*key_free)(struct key *);\n\tint (*key_permission)(key_ref_t, const struct cred *, enum key_need_perm);\n\tint (*key_getsecurity)(struct key *, char **);\n\tint (*audit_rule_init)(u32, u32, char *, void **);\n\tint (*audit_rule_known)(struct audit_krule *);\n\tint (*audit_rule_match)(u32, u32, u32, void *);\n\tvoid (*audit_rule_free)(void *);\n\tint (*bpf)(int, union bpf_attr *, unsigned int);\n\tint (*bpf_map)(struct bpf_map *, fmode_t);\n\tint (*bpf_prog)(struct bpf_prog *);\n\tint (*bpf_map_alloc_security)(struct bpf_map *);\n\tvoid (*bpf_map_free_security)(struct bpf_map *);\n\tint (*bpf_prog_alloc_security)(struct bpf_prog_aux *);\n\tvoid (*bpf_prog_free_security)(struct bpf_prog_aux *);\n\tint (*locked_down)(enum lockdown_reason);\n\tint (*perf_event_open)(struct perf_event_attr *, int);\n\tint (*perf_event_alloc)(struct perf_event *);\n\tvoid (*perf_event_free)(struct perf_event *);\n\tint (*perf_event_read)(struct perf_event *);\n\tint (*perf_event_write)(struct perf_event *);\n};\n\nstruct security_hook_list {\n\tstruct hlist_node list;\n\tstruct hlist_head *head;\n\tunion security_list_options hook;\n\tchar *lsm;\n};\n\nenum lsm_event {\n\tLSM_POLICY_CHANGE = 0,\n};\n\ntypedef int (*initxattrs)(struct inode *, const struct xattr *, void *);\n\nenum ib_uverbs_write_cmds {\n\tIB_USER_VERBS_CMD_GET_CONTEXT = 0,\n\tIB_USER_VERBS_CMD_QUERY_DEVICE = 1,\n\tIB_USER_VERBS_CMD_QUERY_PORT = 2,\n\tIB_USER_VERBS_CMD_ALLOC_PD = 3,\n\tIB_USER_VERBS_CMD_DEALLOC_PD = 4,\n\tIB_USER_VERBS_CMD_CREATE_AH = 5,\n\tIB_USER_VERBS_CMD_MODIFY_AH = 6,\n\tIB_USER_VERBS_CMD_QUERY_AH = 7,\n\tIB_USER_VERBS_CMD_DESTROY_AH = 8,\n\tIB_USER_VERBS_CMD_REG_MR = 9,\n\tIB_USER_VERBS_CMD_REG_SMR = 10,\n\tIB_USER_VERBS_CMD_REREG_MR = 11,\n\tIB_USER_VERBS_CMD_QUERY_MR = 12,\n\tIB_USER_VERBS_CMD_DEREG_MR = 13,\n\tIB_USER_VERBS_CMD_ALLOC_MW = 14,\n\tIB_USER_VERBS_CMD_BIND_MW = 15,\n\tIB_USER_VERBS_CMD_DEALLOC_MW = 16,\n\tIB_USER_VERBS_CMD_CREATE_COMP_CHANNEL = 17,\n\tIB_USER_VERBS_CMD_CREATE_CQ = 18,\n\tIB_USER_VERBS_CMD_RESIZE_CQ = 19,\n\tIB_USER_VERBS_CMD_DESTROY_CQ = 20,\n\tIB_USER_VERBS_CMD_POLL_CQ = 21,\n\tIB_USER_VERBS_CMD_PEEK_CQ = 22,\n\tIB_USER_VERBS_CMD_REQ_NOTIFY_CQ = 23,\n\tIB_USER_VERBS_CMD_CREATE_QP = 24,\n\tIB_USER_VERBS_CMD_QUERY_QP = 25,\n\tIB_USER_VERBS_CMD_MODIFY_QP = 26,\n\tIB_USER_VERBS_CMD_DESTROY_QP = 27,\n\tIB_USER_VERBS_CMD_POST_SEND = 28,\n\tIB_USER_VERBS_CMD_POST_RECV = 29,\n\tIB_USER_VERBS_CMD_ATTACH_MCAST = 30,\n\tIB_USER_VERBS_CMD_DETACH_MCAST = 31,\n\tIB_USER_VERBS_CMD_CREATE_SRQ = 32,\n\tIB_USER_VERBS_CMD_MODIFY_SRQ = 33,\n\tIB_USER_VERBS_CMD_QUERY_SRQ = 34,\n\tIB_USER_VERBS_CMD_DESTROY_SRQ = 35,\n\tIB_USER_VERBS_CMD_POST_SRQ_RECV = 36,\n\tIB_USER_VERBS_CMD_OPEN_XRCD = 37,\n\tIB_USER_VERBS_CMD_CLOSE_XRCD = 38,\n\tIB_USER_VERBS_CMD_CREATE_XSRQ = 39,\n\tIB_USER_VERBS_CMD_OPEN_QP = 40,\n};\n\nenum ib_uverbs_create_qp_mask {\n\tIB_UVERBS_CREATE_QP_MASK_IND_TABLE = 1,\n};\n\nenum ib_uverbs_wr_opcode {\n\tIB_UVERBS_WR_RDMA_WRITE = 0,\n\tIB_UVERBS_WR_RDMA_WRITE_WITH_IMM = 1,\n\tIB_UVERBS_WR_SEND = 2,\n\tIB_UVERBS_WR_SEND_WITH_IMM = 3,\n\tIB_UVERBS_WR_RDMA_READ = 4,\n\tIB_UVERBS_WR_ATOMIC_CMP_AND_SWP = 5,\n\tIB_UVERBS_WR_ATOMIC_FETCH_AND_ADD = 6,\n\tIB_UVERBS_WR_LOCAL_INV = 7,\n\tIB_UVERBS_WR_BIND_MW = 8,\n\tIB_UVERBS_WR_SEND_WITH_INV = 9,\n\tIB_UVERBS_WR_TSO = 10,\n\tIB_UVERBS_WR_RDMA_READ_WITH_INV = 11,\n\tIB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = 12,\n\tIB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13,\n};\n\nenum ib_uverbs_access_flags {\n\tIB_UVERBS_ACCESS_LOCAL_WRITE = 1,\n\tIB_UVERBS_ACCESS_REMOTE_WRITE = 2,\n\tIB_UVERBS_ACCESS_REMOTE_READ = 4,\n\tIB_UVERBS_ACCESS_REMOTE_ATOMIC = 8,\n\tIB_UVERBS_ACCESS_MW_BIND = 16,\n\tIB_UVERBS_ACCESS_ZERO_BASED = 32,\n\tIB_UVERBS_ACCESS_ON_DEMAND = 64,\n\tIB_UVERBS_ACCESS_HUGETLB = 128,\n\tIB_UVERBS_ACCESS_RELAXED_ORDERING = 1048576,\n\tIB_UVERBS_ACCESS_OPTIONAL_RANGE = 1072693248,\n};\n\nenum ib_uverbs_srq_type {\n\tIB_UVERBS_SRQT_BASIC = 0,\n\tIB_UVERBS_SRQT_XRC = 1,\n\tIB_UVERBS_SRQT_TM = 2,\n};\n\nenum ib_uverbs_wq_type {\n\tIB_UVERBS_WQT_RQ = 0,\n};\n\nenum ib_uverbs_wq_flags {\n\tIB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING = 1,\n\tIB_UVERBS_WQ_FLAGS_SCATTER_FCS = 2,\n\tIB_UVERBS_WQ_FLAGS_DELAY_DROP = 4,\n\tIB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING = 8,\n};\n\nenum ib_uverbs_qp_type {\n\tIB_UVERBS_QPT_RC = 2,\n\tIB_UVERBS_QPT_UC = 3,\n\tIB_UVERBS_QPT_UD = 4,\n\tIB_UVERBS_QPT_RAW_PACKET = 8,\n\tIB_UVERBS_QPT_XRC_INI = 9,\n\tIB_UVERBS_QPT_XRC_TGT = 10,\n\tIB_UVERBS_QPT_DRIVER = 255,\n};\n\nenum ib_uverbs_qp_create_flags {\n\tIB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 2,\n\tIB_UVERBS_QP_CREATE_SCATTER_FCS = 256,\n\tIB_UVERBS_QP_CREATE_CVLAN_STRIPPING = 512,\n\tIB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING = 2048,\n\tIB_UVERBS_QP_CREATE_SQ_SIG_ALL = 4096,\n};\n\nunion ib_gid {\n\tu8 raw[16];\n\tstruct {\n\t\t__be64 subnet_prefix;\n\t\t__be64 interface_id;\n\t} global;\n};\n\nenum ib_poll_context {\n\tIB_POLL_SOFTIRQ = 0,\n\tIB_POLL_WORKQUEUE = 1,\n\tIB_POLL_UNBOUND_WORKQUEUE = 2,\n\tIB_POLL_LAST_POOL_TYPE = 2,\n\tIB_POLL_DIRECT = 3,\n};\n\nstruct lsm_network_audit {\n\tint netif;\n\tstruct sock *sk;\n\tu16 family;\n\t__be16 dport;\n\t__be16 sport;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 daddr;\n\t\t\t__be32 saddr;\n\t\t} v4;\n\t\tstruct {\n\t\t\tstruct in6_addr daddr;\n\t\t\tstruct in6_addr saddr;\n\t\t} v6;\n\t} fam;\n};\n\nstruct lsm_ioctlop_audit {\n\tstruct path path;\n\tu16 cmd;\n};\n\nstruct lsm_ibpkey_audit {\n\tu64 subnet_prefix;\n\tu16 pkey;\n};\n\nstruct lsm_ibendport_audit {\n\tchar dev_name[64];\n\tu8 port;\n};\n\nstruct selinux_state;\n\nstruct selinux_audit_data {\n\tu32 ssid;\n\tu32 tsid;\n\tu16 tclass;\n\tu32 requested;\n\tu32 audited;\n\tu32 denied;\n\tint result;\n\tstruct selinux_state *state;\n};\n\nstruct common_audit_data {\n\tchar type;\n\tunion {\n\t\tstruct path path;\n\t\tstruct dentry *dentry;\n\t\tstruct inode *inode;\n\t\tstruct lsm_network_audit *net;\n\t\tint cap;\n\t\tint ipc_id;\n\t\tstruct task_struct *tsk;\n\t\tstruct {\n\t\t\tkey_serial_t key;\n\t\t\tchar *key_desc;\n\t\t} key_struct;\n\t\tchar *kmod_name;\n\t\tstruct lsm_ioctlop_audit *op;\n\t\tstruct file *file;\n\t\tstruct lsm_ibpkey_audit *ibpkey;\n\t\tstruct lsm_ibendport_audit *ibendport;\n\t\tint reason;\n\t} u;\n\tunion {\n\t\tstruct selinux_audit_data *selinux_audit_data;\n\t};\n};\n\nenum {\n\tPOLICYDB_CAPABILITY_NETPEER = 0,\n\tPOLICYDB_CAPABILITY_OPENPERM = 1,\n\tPOLICYDB_CAPABILITY_EXTSOCKCLASS = 2,\n\tPOLICYDB_CAPABILITY_ALWAYSNETWORK = 3,\n\tPOLICYDB_CAPABILITY_CGROUPSECLABEL = 4,\n\tPOLICYDB_CAPABILITY_NNP_NOSUID_TRANSITION = 5,\n\tPOLICYDB_CAPABILITY_GENFS_SECLABEL_SYMLINKS = 6,\n\t__POLICYDB_CAPABILITY_MAX = 7,\n};\n\nstruct selinux_avc;\n\nstruct selinux_ss;\n\nstruct selinux_state {\n\tbool disabled;\n\tbool enforcing;\n\tbool checkreqprot;\n\tbool initialized;\n\tbool policycap[7];\n\tstruct page *status_page;\n\tstruct mutex status_lock;\n\tstruct selinux_avc *avc;\n\tstruct selinux_ss *ss;\n};\n\nstruct avc_cache {\n\tstruct hlist_head slots[512];\n\tspinlock_t slots_lock[512];\n\tatomic_t lru_hint;\n\tatomic_t active_nodes;\n\tu32 latest_notif;\n};\n\nstruct selinux_avc {\n\tunsigned int avc_cache_threshold;\n\tstruct avc_cache avc_cache;\n};\n\nstruct av_decision {\n\tu32 allowed;\n\tu32 auditallow;\n\tu32 auditdeny;\n\tu32 seqno;\n\tu32 flags;\n};\n\nstruct extended_perms_data {\n\tu32 p[8];\n};\n\nstruct extended_perms_decision {\n\tu8 used;\n\tu8 driver;\n\tstruct extended_perms_data *allowed;\n\tstruct extended_perms_data *auditallow;\n\tstruct extended_perms_data *dontaudit;\n};\n\nstruct extended_perms {\n\tu16 len;\n\tstruct extended_perms_data drivers;\n};\n\nstruct avc_cache_stats {\n\tunsigned int lookups;\n\tunsigned int misses;\n\tunsigned int allocations;\n\tunsigned int reclaims;\n\tunsigned int frees;\n};\n\nstruct security_class_mapping {\n\tconst char *name;\n\tconst char *perms[33];\n};\n\nstruct avc_xperms_node;\n\nstruct avc_entry {\n\tu32 ssid;\n\tu32 tsid;\n\tu16 tclass;\n\tstruct av_decision avd;\n\tstruct avc_xperms_node *xp_node;\n};\n\nstruct avc_xperms_node {\n\tstruct extended_perms xp;\n\tstruct list_head xpd_head;\n};\n\nstruct avc_node {\n\tstruct avc_entry ae;\n\tstruct hlist_node list;\n\tstruct callback_head rhead;\n};\n\nstruct avc_xperms_decision_node {\n\tstruct extended_perms_decision xpd;\n\tstruct list_head xpd_list;\n};\n\nstruct avc_callback_node {\n\tint (*callback)(u32);\n\tu32 events;\n\tstruct avc_callback_node *next;\n};\n\ntypedef __u16 __sum16;\n\ntypedef u16 u_int16_t;\n\nstruct rhltable {\n\tstruct rhashtable ht;\n};\n\nenum sctp_endpoint_type {\n\tSCTP_EP_TYPE_SOCKET = 0,\n\tSCTP_EP_TYPE_ASSOCIATION = 1,\n};\n\nstruct sctp_chunk;\n\nstruct sctp_inq {\n\tstruct list_head in_chunk_list;\n\tstruct sctp_chunk *in_progress;\n\tstruct work_struct immediate;\n};\n\nstruct sctp_bind_addr {\n\t__u16 port;\n\tstruct list_head address_list;\n};\n\nstruct sctp_ep_common {\n\tstruct hlist_node node;\n\tint hashent;\n\tenum sctp_endpoint_type type;\n\trefcount_t refcnt;\n\tbool dead;\n\tstruct sock *sk;\n\tstruct net *net;\n\tstruct sctp_inq inqueue;\n\tstruct sctp_bind_addr bind_addr;\n};\n\nstruct sctp_hmac_algo_param;\n\nstruct sctp_chunks_param;\n\nstruct sctp_endpoint {\n\tstruct sctp_ep_common base;\n\tstruct list_head asocs;\n\t__u8 secret_key[32];\n\t__u8 *digest;\n\t__u32 sndbuf_policy;\n\t__u32 rcvbuf_policy;\n\tstruct crypto_shash **auth_hmacs;\n\tstruct sctp_hmac_algo_param *auth_hmacs_list;\n\tstruct sctp_chunks_param *auth_chunk_list;\n\tstruct list_head endpoint_shared_keys;\n\t__u16 active_key_id;\n\t__u8 ecn_enable: 1;\n\t__u8 auth_enable: 1;\n\t__u8 intl_enable: 1;\n\t__u8 prsctp_enable: 1;\n\t__u8 asconf_enable: 1;\n\t__u8 reconf_enable: 1;\n\t__u8 strreset_enable;\n\tu32 secid;\n\tu32 peer_secid;\n};\n\nenum ip_conntrack_info {\n\tIP_CT_ESTABLISHED = 0,\n\tIP_CT_RELATED = 1,\n\tIP_CT_NEW = 2,\n\tIP_CT_IS_REPLY = 3,\n\tIP_CT_ESTABLISHED_REPLY = 3,\n\tIP_CT_RELATED_REPLY = 4,\n\tIP_CT_NUMBER = 5,\n\tIP_CT_UNTRACKED = 7,\n};\n\nstruct nf_conntrack {\n\tatomic_t use;\n};\n\nstruct nf_hook_state;\n\ntypedef unsigned int nf_hookfn(void *, struct sk_buff *, const struct nf_hook_state *);\n\nstruct nf_hook_entry {\n\tnf_hookfn *hook;\n\tvoid *priv;\n};\n\nstruct nf_hook_entries {\n\tu16 num_hook_entries;\n\tstruct nf_hook_entry hooks[0];\n};\n\nstruct nf_hook_state {\n\tunsigned int hook;\n\tu_int8_t pf;\n\tstruct net_device *in;\n\tstruct net_device *out;\n\tstruct sock *sk;\n\tstruct net *net;\n\tint (*okfn)(struct net *, struct sock *, struct sk_buff *);\n};\n\nstruct nf_hook_ops {\n\tnf_hookfn *hook;\n\tstruct net_device *dev;\n\tvoid *priv;\n\tu_int8_t pf;\n\tunsigned int hooknum;\n\tint priority;\n};\n\nenum nf_nat_manip_type {\n\tNF_NAT_MANIP_SRC = 0,\n\tNF_NAT_MANIP_DST = 1,\n};\n\nstruct nf_conn;\n\nstruct nf_nat_hook {\n\tint (*parse_nat_setup)(struct nf_conn *, enum nf_nat_manip_type, const struct nlattr *);\n\tvoid (*decode_session)(struct sk_buff *, struct flowi *);\n\tunsigned int (*manip_pkt)(struct sk_buff *, struct nf_conn *, enum nf_nat_manip_type, enum ip_conntrack_dir);\n};\n\nunion nf_inet_addr {\n\t__u32 all[4];\n\t__be32 ip;\n\t__be32 ip6[4];\n\tstruct in_addr in;\n\tstruct in6_addr in6;\n};\n\nunion nf_conntrack_man_proto {\n\t__be16 all;\n\tstruct {\n\t\t__be16 port;\n\t} tcp;\n\tstruct {\n\t\t__be16 port;\n\t} udp;\n\tstruct {\n\t\t__be16 id;\n\t} icmp;\n\tstruct {\n\t\t__be16 port;\n\t} dccp;\n\tstruct {\n\t\t__be16 port;\n\t} sctp;\n\tstruct {\n\t\t__be16 key;\n\t} gre;\n};\n\nstruct nf_conntrack_man {\n\tunion nf_inet_addr u3;\n\tunion nf_conntrack_man_proto u;\n\tu_int16_t l3num;\n};\n\nstruct nf_conntrack_tuple {\n\tstruct nf_conntrack_man src;\n\tstruct {\n\t\tunion nf_inet_addr u3;\n\t\tunion {\n\t\t\t__be16 all;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} tcp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} udp;\n\t\t\tstruct {\n\t\t\t\tu_int8_t type;\n\t\t\t\tu_int8_t code;\n\t\t\t} icmp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} dccp;\n\t\t\tstruct {\n\t\t\t\t__be16 port;\n\t\t\t} sctp;\n\t\t\tstruct {\n\t\t\t\t__be16 key;\n\t\t\t} gre;\n\t\t} u;\n\t\tu_int8_t protonum;\n\t\tu_int8_t dir;\n\t} dst;\n};\n\nstruct nf_conntrack_tuple_hash {\n\tstruct hlist_nulls_node hnnode;\n\tstruct nf_conntrack_tuple tuple;\n};\n\ntypedef u32 u_int32_t;\n\ntypedef u64 u_int64_t;\n\nstruct nf_ct_dccp {\n\tu_int8_t role[2];\n\tu_int8_t state;\n\tu_int8_t last_pkt;\n\tu_int8_t last_dir;\n\tu_int64_t handshake_seq;\n};\n\nstruct ip_ct_sctp {\n\tenum sctp_conntrack state;\n\t__be32 vtag[2];\n};\n\nstruct ip_ct_tcp_state {\n\tu_int32_t td_end;\n\tu_int32_t td_maxend;\n\tu_int32_t td_maxwin;\n\tu_int32_t td_maxack;\n\tu_int8_t td_scale;\n\tu_int8_t flags;\n};\n\nstruct ip_ct_tcp {\n\tstruct ip_ct_tcp_state seen[2];\n\tu_int8_t state;\n\tu_int8_t last_dir;\n\tu_int8_t retrans;\n\tu_int8_t last_index;\n\tu_int32_t last_seq;\n\tu_int32_t last_ack;\n\tu_int32_t last_end;\n\tu_int16_t last_win;\n\tu_int8_t last_wscale;\n\tu_int8_t last_flags;\n};\n\nstruct nf_ct_udp {\n\tlong unsigned int stream_ts;\n};\n\nstruct nf_ct_gre {\n\tunsigned int stream_timeout;\n\tunsigned int timeout;\n};\n\nunion nf_conntrack_proto {\n\tstruct nf_ct_dccp dccp;\n\tstruct ip_ct_sctp sctp;\n\tstruct ip_ct_tcp tcp;\n\tstruct nf_ct_udp udp;\n\tstruct nf_ct_gre gre;\n\tunsigned int tmpl_padto;\n};\n\nstruct nf_ct_ext;\n\nstruct nf_conn {\n\tstruct nf_conntrack ct_general;\n\tspinlock_t lock;\n\tu32 timeout;\n\tstruct nf_conntrack_tuple_hash tuplehash[2];\n\tlong unsigned int status;\n\tu16 cpu;\n\tpossible_net_t ct_net;\n\tstruct hlist_node nat_bysource;\n\tstruct {\t} __nfct_init_offset;\n\tstruct nf_conn *master;\n\tu_int32_t secmark;\n\tstruct nf_ct_ext *ext;\n\tunion nf_conntrack_proto proto;\n};\n\nstruct nf_conntrack_zone {\n\tu16 id;\n\tu8 flags;\n\tu8 dir;\n};\n\nstruct nf_ct_hook {\n\tint (*update)(struct net *, struct sk_buff *);\n\tvoid (*destroy)(struct nf_conntrack *);\n\tbool (*get_tuple_skb)(struct nf_conntrack_tuple *, const struct sk_buff *);\n};\n\nstruct nfnl_ct_hook {\n\tstruct nf_conn * (*get_ct)(const struct sk_buff *, enum ip_conntrack_info *);\n\tsize_t (*build_size)(const struct nf_conn *);\n\tint (*build)(struct sk_buff *, struct nf_conn *, enum ip_conntrack_info, u_int16_t, u_int16_t);\n\tint (*parse)(const struct nlattr *, struct nf_conn *);\n\tint (*attach_expect)(const struct nlattr *, struct nf_conn *, u32, u32);\n\tvoid (*seq_adjust)(struct sk_buff *, struct nf_conn *, enum ip_conntrack_info, s32);\n};\n\nenum nf_ip_hook_priorities {\n\tNF_IP_PRI_FIRST = 2147483648,\n\tNF_IP_PRI_RAW_BEFORE_DEFRAG = 4294966846,\n\tNF_IP_PRI_CONNTRACK_DEFRAG = 4294966896,\n\tNF_IP_PRI_RAW = 4294966996,\n\tNF_IP_PRI_SELINUX_FIRST = 4294967071,\n\tNF_IP_PRI_CONNTRACK = 4294967096,\n\tNF_IP_PRI_MANGLE = 4294967146,\n\tNF_IP_PRI_NAT_DST = 4294967196,\n\tNF_IP_PRI_FILTER = 0,\n\tNF_IP_PRI_SECURITY = 50,\n\tNF_IP_PRI_NAT_SRC = 100,\n\tNF_IP_PRI_SELINUX_LAST = 225,\n\tNF_IP_PRI_CONNTRACK_HELPER = 300,\n\tNF_IP_PRI_CONNTRACK_CONFIRM = 2147483647,\n\tNF_IP_PRI_LAST = 2147483647,\n};\n\nenum nf_ip6_hook_priorities {\n\tNF_IP6_PRI_FIRST = 2147483648,\n\tNF_IP6_PRI_RAW_BEFORE_DEFRAG = 4294966846,\n\tNF_IP6_PRI_CONNTRACK_DEFRAG = 4294966896,\n\tNF_IP6_PRI_RAW = 4294966996,\n\tNF_IP6_PRI_SELINUX_FIRST = 4294967071,\n\tNF_IP6_PRI_CONNTRACK = 4294967096,\n\tNF_IP6_PRI_MANGLE = 4294967146,\n\tNF_IP6_PRI_NAT_DST = 4294967196,\n\tNF_IP6_PRI_FILTER = 0,\n\tNF_IP6_PRI_SECURITY = 50,\n\tNF_IP6_PRI_NAT_SRC = 100,\n\tNF_IP6_PRI_SELINUX_LAST = 225,\n\tNF_IP6_PRI_CONNTRACK_HELPER = 300,\n\tNF_IP6_PRI_LAST = 2147483647,\n};\n\nstruct socket_alloc {\n\tstruct socket socket;\n\tstruct inode vfs_inode;\n\tlong: 64;\n};\n\nstruct ip_options {\n\t__be32 faddr;\n\t__be32 nexthop;\n\tunsigned char optlen;\n\tunsigned char srr;\n\tunsigned char rr;\n\tunsigned char ts;\n\tunsigned char is_strictroute: 1;\n\tunsigned char srr_is_hit: 1;\n\tunsigned char is_changed: 1;\n\tunsigned char rr_needaddr: 1;\n\tunsigned char ts_needtime: 1;\n\tunsigned char ts_needaddr: 1;\n\tunsigned char router_alert;\n\tunsigned char cipso;\n\tunsigned char __pad2;\n\tunsigned char __data[0];\n};\n\nstruct ip_options_rcu {\n\tstruct callback_head rcu;\n\tstruct ip_options opt;\n};\n\nstruct ipv6_opt_hdr;\n\nstruct ipv6_rt_hdr;\n\nstruct ipv6_txoptions {\n\trefcount_t refcnt;\n\tint tot_len;\n\t__u16 opt_flen;\n\t__u16 opt_nflen;\n\tstruct ipv6_opt_hdr *hopopt;\n\tstruct ipv6_opt_hdr *dst0opt;\n\tstruct ipv6_rt_hdr *srcrt;\n\tstruct ipv6_opt_hdr *dst1opt;\n\tstruct callback_head rcu;\n};\n\nstruct inet_cork {\n\tunsigned int flags;\n\t__be32 addr;\n\tstruct ip_options *opt;\n\tunsigned int fragsize;\n\tint length;\n\tstruct dst_entry *dst;\n\tu8 tx_flags;\n\t__u8 ttl;\n\t__s16 tos;\n\tchar priority;\n\t__u16 gso_size;\n\tu64 transmit_time;\n\tu32 mark;\n};\n\nstruct inet_cork_full {\n\tstruct inet_cork base;\n\tstruct flowi fl;\n};\n\nstruct ipv6_pinfo;\n\nstruct ip_mc_socklist;\n\nstruct inet_sock {\n\tstruct sock sk;\n\tstruct ipv6_pinfo *pinet6;\n\t__be32 inet_saddr;\n\t__s16 uc_ttl;\n\t__u16 cmsg_flags;\n\t__be16 inet_sport;\n\t__u16 inet_id;\n\tstruct ip_options_rcu *inet_opt;\n\tint rx_dst_ifindex;\n\t__u8 tos;\n\t__u8 min_ttl;\n\t__u8 mc_ttl;\n\t__u8 pmtudisc;\n\t__u8 recverr: 1;\n\t__u8 is_icsk: 1;\n\t__u8 freebind: 1;\n\t__u8 hdrincl: 1;\n\t__u8 mc_loop: 1;\n\t__u8 transparent: 1;\n\t__u8 mc_all: 1;\n\t__u8 nodefrag: 1;\n\t__u8 bind_address_no_port: 1;\n\t__u8 defer_connect: 1;\n\t__u8 rcv_tos;\n\t__u8 convert_csum;\n\tint uc_index;\n\tint mc_index;\n\t__be32 mc_addr;\n\tstruct ip_mc_socklist *mc_list;\n\tstruct inet_cork_full cork;\n};\n\nstruct in6_pktinfo {\n\tstruct in6_addr ipi6_addr;\n\tint ipi6_ifindex;\n};\n\nstruct inet6_cork {\n\tstruct ipv6_txoptions *opt;\n\tu8 hop_limit;\n\tu8 tclass;\n};\n\nstruct ipv6_mc_socklist;\n\nstruct ipv6_ac_socklist;\n\nstruct ipv6_fl_socklist;\n\nstruct ipv6_pinfo {\n\tstruct in6_addr saddr;\n\tstruct in6_pktinfo sticky_pktinfo;\n\tconst struct in6_addr *daddr_cache;\n\t__be32 flow_label;\n\t__u32 frag_size;\n\t__u16 __unused_1: 7;\n\t__s16 hop_limit: 9;\n\t__u16 mc_loop: 1;\n\t__u16 __unused_2: 6;\n\t__s16 mcast_hops: 9;\n\tint ucast_oif;\n\tint mcast_oif;\n\tunion {\n\t\tstruct {\n\t\t\t__u16 srcrt: 1;\n\t\t\t__u16 osrcrt: 1;\n\t\t\t__u16 rxinfo: 1;\n\t\t\t__u16 rxoinfo: 1;\n\t\t\t__u16 rxhlim: 1;\n\t\t\t__u16 rxohlim: 1;\n\t\t\t__u16 hopopts: 1;\n\t\t\t__u16 ohopopts: 1;\n\t\t\t__u16 dstopts: 1;\n\t\t\t__u16 odstopts: 1;\n\t\t\t__u16 rxflow: 1;\n\t\t\t__u16 rxtclass: 1;\n\t\t\t__u16 rxpmtu: 1;\n\t\t\t__u16 rxorigdstaddr: 1;\n\t\t\t__u16 recvfragsize: 1;\n\t\t} bits;\n\t\t__u16 all;\n\t} rxopt;\n\t__u16 recverr: 1;\n\t__u16 sndflow: 1;\n\t__u16 repflow: 1;\n\t__u16 pmtudisc: 3;\n\t__u16 padding: 1;\n\t__u16 srcprefs: 3;\n\t__u16 dontfrag: 1;\n\t__u16 autoflowlabel: 1;\n\t__u16 autoflowlabel_set: 1;\n\t__u16 mc_all: 1;\n\t__u16 rtalert_isolate: 1;\n\t__u8 min_hopcount;\n\t__u8 tclass;\n\t__be32 rcv_flowinfo;\n\t__u32 dst_cookie;\n\t__u32 rx_dst_cookie;\n\tstruct ipv6_mc_socklist *ipv6_mc_list;\n\tstruct ipv6_ac_socklist *ipv6_ac_list;\n\tstruct ipv6_fl_socklist *ipv6_fl_list;\n\tstruct ipv6_txoptions *opt;\n\tstruct sk_buff *pktoptions;\n\tstruct sk_buff *rxpmtu;\n\tstruct inet6_cork cork;\n};\n\nstruct tcphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 seq;\n\t__be32 ack_seq;\n\t__u16 res1: 4;\n\t__u16 doff: 4;\n\t__u16 fin: 1;\n\t__u16 syn: 1;\n\t__u16 rst: 1;\n\t__u16 psh: 1;\n\t__u16 ack: 1;\n\t__u16 urg: 1;\n\t__u16 ece: 1;\n\t__u16 cwr: 1;\n\t__be16 window;\n\t__sum16 check;\n\t__be16 urg_ptr;\n};\n\nstruct iphdr {\n\t__u8 ihl: 4;\n\t__u8 version: 4;\n\t__u8 tos;\n\t__be16 tot_len;\n\t__be16 id;\n\t__be16 frag_off;\n\t__u8 ttl;\n\t__u8 protocol;\n\t__sum16 check;\n\t__be32 saddr;\n\t__be32 daddr;\n};\n\nstruct ipv6_rt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n};\n\nstruct ipv6_opt_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n};\n\nstruct ipv6hdr {\n\t__u8 priority: 4;\n\t__u8 version: 4;\n\t__u8 flow_lbl[3];\n\t__be16 payload_len;\n\t__u8 nexthdr;\n\t__u8 hop_limit;\n\tstruct in6_addr saddr;\n\tstruct in6_addr daddr;\n};\n\nstruct udphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be16 len;\n\t__sum16 check;\n};\n\nstruct inet6_skb_parm {\n\tint iif;\n\t__be16 ra;\n\t__u16 dst0;\n\t__u16 srcrt;\n\t__u16 dst1;\n\t__u16 lastopt;\n\t__u16 nhoff;\n\t__u16 flags;\n\t__u16 frag_max_size;\n};\n\nstruct ip6_sf_socklist;\n\nstruct ipv6_mc_socklist {\n\tstruct in6_addr addr;\n\tint ifindex;\n\tunsigned int sfmode;\n\tstruct ipv6_mc_socklist *next;\n\trwlock_t sflock;\n\tstruct ip6_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ipv6_ac_socklist {\n\tstruct in6_addr acl_addr;\n\tint acl_ifindex;\n\tstruct ipv6_ac_socklist *acl_next;\n};\n\nstruct ip6_flowlabel;\n\nstruct ipv6_fl_socklist {\n\tstruct ipv6_fl_socklist *next;\n\tstruct ip6_flowlabel *fl;\n\tstruct callback_head rcu;\n};\n\nstruct ip6_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct in6_addr sl_addr[0];\n};\n\nstruct ip6_flowlabel {\n\tstruct ip6_flowlabel *next;\n\t__be32 label;\n\tatomic_t users;\n\tstruct in6_addr dst;\n\tstruct ipv6_txoptions *opt;\n\tlong unsigned int linger;\n\tstruct callback_head rcu;\n\tu8 share;\n\tunion {\n\t\tstruct pid *pid;\n\t\tkuid_t uid;\n\t} owner;\n\tlong unsigned int lastuse;\n\tlong unsigned int expires;\n\tstruct net *fl_net;\n};\n\nstruct inet_skb_parm {\n\tint iif;\n\tstruct ip_options opt;\n\tu16 flags;\n\tu16 frag_max_size;\n};\n\nstruct nf_ipv6_ops {\n\tvoid (*route_input)(struct sk_buff *);\n\tint (*fragment)(struct net *, struct sock *, struct sk_buff *, int (*)(struct net *, struct sock *, struct sk_buff *));\n\tint (*reroute)(struct sk_buff *, const struct nf_queue_entry *);\n};\n\nstruct nf_queue_entry {\n\tstruct list_head list;\n\tstruct sk_buff *skb;\n\tunsigned int id;\n\tunsigned int hook_index;\n\tstruct nf_hook_state state;\n\tu16 size;\n};\n\nstruct tty_file_private {\n\tstruct tty_struct *tty;\n\tstruct file *file;\n\tstruct list_head list;\n};\n\nstruct icmp_err {\n\tint errno;\n\tunsigned int fatal: 1;\n};\n\nstruct netlbl_lsm_cache {\n\trefcount_t refcount;\n\tvoid (*free)(const void *);\n\tvoid *data;\n};\n\nstruct netlbl_lsm_catmap {\n\tu32 startbit;\n\tu64 bitmap[4];\n\tstruct netlbl_lsm_catmap *next;\n};\n\nstruct netlbl_lsm_secattr {\n\tu32 flags;\n\tu32 type;\n\tchar *domain;\n\tstruct netlbl_lsm_cache *cache;\n\tstruct {\n\t\tstruct {\n\t\t\tstruct netlbl_lsm_catmap *cat;\n\t\t\tu32 lvl;\n\t\t} mls;\n\t\tu32 secid;\n\t} attr;\n};\n\nstruct dccp_hdr {\n\t__be16 dccph_sport;\n\t__be16 dccph_dport;\n\t__u8 dccph_doff;\n\t__u8 dccph_cscov: 4;\n\t__u8 dccph_ccval: 4;\n\t__sum16 dccph_checksum;\n\t__u8 dccph_x: 1;\n\t__u8 dccph_type: 4;\n\t__u8 dccph_reserved: 3;\n\t__u8 dccph_seq2;\n\t__be16 dccph_seq;\n};\n\nenum dccp_state {\n\tDCCP_OPEN = 1,\n\tDCCP_REQUESTING = 2,\n\tDCCP_LISTEN = 10,\n\tDCCP_RESPOND = 3,\n\tDCCP_ACTIVE_CLOSEREQ = 4,\n\tDCCP_PASSIVE_CLOSE = 8,\n\tDCCP_CLOSING = 11,\n\tDCCP_TIME_WAIT = 6,\n\tDCCP_CLOSED = 7,\n\tDCCP_NEW_SYN_RECV = 12,\n\tDCCP_PARTOPEN = 13,\n\tDCCP_PASSIVE_CLOSEREQ = 14,\n\tDCCP_MAX_STATES = 15,\n};\n\ntypedef __s32 sctp_assoc_t;\n\nenum sctp_msg_flags {\n\tMSG_NOTIFICATION = 32768,\n};\n\nstruct sctp_initmsg {\n\t__u16 sinit_num_ostreams;\n\t__u16 sinit_max_instreams;\n\t__u16 sinit_max_attempts;\n\t__u16 sinit_max_init_timeo;\n};\n\nstruct sctp_sndrcvinfo {\n\t__u16 sinfo_stream;\n\t__u16 sinfo_ssn;\n\t__u16 sinfo_flags;\n\t__u32 sinfo_ppid;\n\t__u32 sinfo_context;\n\t__u32 sinfo_timetolive;\n\t__u32 sinfo_tsn;\n\t__u32 sinfo_cumtsn;\n\tsctp_assoc_t sinfo_assoc_id;\n};\n\nstruct sctp_rtoinfo {\n\tsctp_assoc_t srto_assoc_id;\n\t__u32 srto_initial;\n\t__u32 srto_max;\n\t__u32 srto_min;\n};\n\nstruct sctp_assocparams {\n\tsctp_assoc_t sasoc_assoc_id;\n\t__u16 sasoc_asocmaxrxt;\n\t__u16 sasoc_number_peer_destinations;\n\t__u32 sasoc_peer_rwnd;\n\t__u32 sasoc_local_rwnd;\n\t__u32 sasoc_cookie_life;\n};\n\nstruct sctp_paddrparams {\n\tsctp_assoc_t spp_assoc_id;\n\tstruct __kernel_sockaddr_storage spp_address;\n\t__u32 spp_hbinterval;\n\t__u16 spp_pathmaxrxt;\n\t__u32 spp_pathmtu;\n\t__u32 spp_sackdelay;\n\t__u32 spp_flags;\n\t__u32 spp_ipv6_flowlabel;\n\t__u8 spp_dscp;\n\tchar: 8;\n} __attribute__((packed));\n\nstruct sctphdr {\n\t__be16 source;\n\t__be16 dest;\n\t__be32 vtag;\n\t__le32 checksum;\n};\n\nstruct sctp_chunkhdr {\n\t__u8 type;\n\t__u8 flags;\n\t__be16 length;\n};\n\nenum sctp_cid {\n\tSCTP_CID_DATA = 0,\n\tSCTP_CID_INIT = 1,\n\tSCTP_CID_INIT_ACK = 2,\n\tSCTP_CID_SACK = 3,\n\tSCTP_CID_HEARTBEAT = 4,\n\tSCTP_CID_HEARTBEAT_ACK = 5,\n\tSCTP_CID_ABORT = 6,\n\tSCTP_CID_SHUTDOWN = 7,\n\tSCTP_CID_SHUTDOWN_ACK = 8,\n\tSCTP_CID_ERROR = 9,\n\tSCTP_CID_COOKIE_ECHO = 10,\n\tSCTP_CID_COOKIE_ACK = 11,\n\tSCTP_CID_ECN_ECNE = 12,\n\tSCTP_CID_ECN_CWR = 13,\n\tSCTP_CID_SHUTDOWN_COMPLETE = 14,\n\tSCTP_CID_AUTH = 15,\n\tSCTP_CID_I_DATA = 64,\n\tSCTP_CID_FWD_TSN = 192,\n\tSCTP_CID_ASCONF = 193,\n\tSCTP_CID_I_FWD_TSN = 194,\n\tSCTP_CID_ASCONF_ACK = 128,\n\tSCTP_CID_RECONF = 130,\n};\n\nstruct sctp_paramhdr {\n\t__be16 type;\n\t__be16 length;\n};\n\nenum sctp_param {\n\tSCTP_PARAM_HEARTBEAT_INFO = 256,\n\tSCTP_PARAM_IPV4_ADDRESS = 1280,\n\tSCTP_PARAM_IPV6_ADDRESS = 1536,\n\tSCTP_PARAM_STATE_COOKIE = 1792,\n\tSCTP_PARAM_UNRECOGNIZED_PARAMETERS = 2048,\n\tSCTP_PARAM_COOKIE_PRESERVATIVE = 2304,\n\tSCTP_PARAM_HOST_NAME_ADDRESS = 2816,\n\tSCTP_PARAM_SUPPORTED_ADDRESS_TYPES = 3072,\n\tSCTP_PARAM_ECN_CAPABLE = 128,\n\tSCTP_PARAM_RANDOM = 640,\n\tSCTP_PARAM_CHUNKS = 896,\n\tSCTP_PARAM_HMAC_ALGO = 1152,\n\tSCTP_PARAM_SUPPORTED_EXT = 2176,\n\tSCTP_PARAM_FWD_TSN_SUPPORT = 192,\n\tSCTP_PARAM_ADD_IP = 448,\n\tSCTP_PARAM_DEL_IP = 704,\n\tSCTP_PARAM_ERR_CAUSE = 960,\n\tSCTP_PARAM_SET_PRIMARY = 1216,\n\tSCTP_PARAM_SUCCESS_REPORT = 1472,\n\tSCTP_PARAM_ADAPTATION_LAYER_IND = 1728,\n\tSCTP_PARAM_RESET_OUT_REQUEST = 3328,\n\tSCTP_PARAM_RESET_IN_REQUEST = 3584,\n\tSCTP_PARAM_RESET_TSN_REQUEST = 3840,\n\tSCTP_PARAM_RESET_RESPONSE = 4096,\n\tSCTP_PARAM_RESET_ADD_OUT_STREAMS = 4352,\n\tSCTP_PARAM_RESET_ADD_IN_STREAMS = 4608,\n};\n\nstruct sctp_datahdr {\n\t__be32 tsn;\n\t__be16 stream;\n\t__be16 ssn;\n\t__u32 ppid;\n\t__u8 payload[0];\n};\n\nstruct sctp_idatahdr {\n\t__be32 tsn;\n\t__be16 stream;\n\t__be16 reserved;\n\t__be32 mid;\n\tunion {\n\t\t__u32 ppid;\n\t\t__be32 fsn;\n\t};\n\t__u8 payload[0];\n};\n\nstruct sctp_inithdr {\n\t__be32 init_tag;\n\t__be32 a_rwnd;\n\t__be16 num_outbound_streams;\n\t__be16 num_inbound_streams;\n\t__be32 initial_tsn;\n\t__u8 params[0];\n};\n\nstruct sctp_init_chunk {\n\tstruct sctp_chunkhdr chunk_hdr;\n\tstruct sctp_inithdr init_hdr;\n};\n\nstruct sctp_ipv4addr_param {\n\tstruct sctp_paramhdr param_hdr;\n\tstruct in_addr addr;\n};\n\nstruct sctp_ipv6addr_param {\n\tstruct sctp_paramhdr param_hdr;\n\tstruct in6_addr addr;\n};\n\nstruct sctp_cookie_preserve_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 lifespan_increment;\n};\n\nstruct sctp_hostname_param {\n\tstruct sctp_paramhdr param_hdr;\n\tuint8_t hostname[0];\n};\n\nstruct sctp_supported_addrs_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be16 types[0];\n};\n\nstruct sctp_adaptation_ind_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 adaptation_ind;\n};\n\nstruct sctp_supported_ext_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 chunks[0];\n};\n\nstruct sctp_random_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 random_val[0];\n};\n\nstruct sctp_chunks_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__u8 chunks[0];\n};\n\nstruct sctp_hmac_algo_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be16 hmac_ids[0];\n};\n\nstruct sctp_cookie_param {\n\tstruct sctp_paramhdr p;\n\t__u8 body[0];\n};\n\nstruct sctp_gap_ack_block {\n\t__be16 start;\n\t__be16 end;\n};\n\nunion sctp_sack_variable {\n\tstruct sctp_gap_ack_block gab;\n\t__be32 dup;\n};\n\nstruct sctp_sackhdr {\n\t__be32 cum_tsn_ack;\n\t__be32 a_rwnd;\n\t__be16 num_gap_ack_blocks;\n\t__be16 num_dup_tsns;\n\tunion sctp_sack_variable variable[0];\n};\n\nstruct sctp_heartbeathdr {\n\tstruct sctp_paramhdr info;\n};\n\nstruct sctp_shutdownhdr {\n\t__be32 cum_tsn_ack;\n};\n\nstruct sctp_errhdr {\n\t__be16 cause;\n\t__be16 length;\n\t__u8 variable[0];\n};\n\nstruct sctp_ecnehdr {\n\t__be32 lowest_tsn;\n};\n\nstruct sctp_cwrhdr {\n\t__be32 lowest_tsn;\n};\n\nstruct sctp_fwdtsn_skip {\n\t__be16 stream;\n\t__be16 ssn;\n};\n\nstruct sctp_fwdtsn_hdr {\n\t__be32 new_cum_tsn;\n\tstruct sctp_fwdtsn_skip skip[0];\n};\n\nstruct sctp_ifwdtsn_skip {\n\t__be16 stream;\n\t__u8 reserved;\n\t__u8 flags;\n\t__be32 mid;\n};\n\nstruct sctp_ifwdtsn_hdr {\n\t__be32 new_cum_tsn;\n\tstruct sctp_ifwdtsn_skip skip[0];\n};\n\nstruct sctp_addip_param {\n\tstruct sctp_paramhdr param_hdr;\n\t__be32 crr_id;\n};\n\nstruct sctp_addiphdr {\n\t__be32 serial;\n\t__u8 params[0];\n};\n\nstruct sctp_authhdr {\n\t__be16 shkey_id;\n\t__be16 hmac_id;\n\t__u8 hmac[0];\n};\n\nunion sctp_addr {\n\tstruct sockaddr_in v4;\n\tstruct sockaddr_in6 v6;\n\tstruct sockaddr sa;\n};\n\nstruct sctp_cookie {\n\t__u32 my_vtag;\n\t__u32 peer_vtag;\n\t__u32 my_ttag;\n\t__u32 peer_ttag;\n\tktime_t expiration;\n\t__u16 sinit_num_ostreams;\n\t__u16 sinit_max_instreams;\n\t__u32 initial_tsn;\n\tunion sctp_addr peer_addr;\n\t__u16 my_port;\n\t__u8 prsctp_capable;\n\t__u8 padding;\n\t__u32 adaptation_ind;\n\t__u8 auth_random[36];\n\t__u8 auth_hmacs[10];\n\t__u8 auth_chunks[20];\n\t__u32 raw_addr_list_len;\n\tstruct sctp_init_chunk peer_init[0];\n};\n\nstruct sctp_tsnmap {\n\tlong unsigned int *tsn_map;\n\t__u32 base_tsn;\n\t__u32 cumulative_tsn_ack_point;\n\t__u32 max_tsn_seen;\n\t__u16 len;\n\t__u16 pending_data;\n\t__u16 num_dup_tsns;\n\t__be32 dup_tsns[16];\n};\n\nstruct sctp_inithdr_host {\n\t__u32 init_tag;\n\t__u32 a_rwnd;\n\t__u16 num_outbound_streams;\n\t__u16 num_inbound_streams;\n\t__u32 initial_tsn;\n};\n\nenum sctp_state {\n\tSCTP_STATE_CLOSED = 0,\n\tSCTP_STATE_COOKIE_WAIT = 1,\n\tSCTP_STATE_COOKIE_ECHOED = 2,\n\tSCTP_STATE_ESTABLISHED = 3,\n\tSCTP_STATE_SHUTDOWN_PENDING = 4,\n\tSCTP_STATE_SHUTDOWN_SENT = 5,\n\tSCTP_STATE_SHUTDOWN_RECEIVED = 6,\n\tSCTP_STATE_SHUTDOWN_ACK_SENT = 7,\n};\n\nstruct sctp_stream_out_ext;\n\nstruct sctp_stream_out {\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\t__u32 mid_uo;\n\tstruct sctp_stream_out_ext *ext;\n\t__u8 state;\n};\n\nstruct sctp_stream_in {\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\t__u32 mid_uo;\n\t__u32 fsn;\n\t__u32 fsn_uo;\n\tchar pd_mode;\n\tchar pd_mode_uo;\n};\n\nstruct sctp_stream_interleave;\n\nstruct sctp_stream {\n\tstruct {\n\t\tstruct __genradix tree;\n\t\tstruct sctp_stream_out type[0];\n\t} out;\n\tstruct {\n\t\tstruct __genradix tree;\n\t\tstruct sctp_stream_in type[0];\n\t} in;\n\t__u16 outcnt;\n\t__u16 incnt;\n\tstruct sctp_stream_out *out_curr;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head prio_list;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head rr_list;\n\t\t\tstruct sctp_stream_out_ext *rr_next;\n\t\t};\n\t};\n\tstruct sctp_stream_interleave *si;\n};\n\nstruct sctp_sched_ops;\n\nstruct sctp_association;\n\nstruct sctp_outq {\n\tstruct sctp_association *asoc;\n\tstruct list_head out_chunk_list;\n\tstruct sctp_sched_ops *sched;\n\tunsigned int out_qlen;\n\tunsigned int error;\n\tstruct list_head control_chunk_list;\n\tstruct list_head sacked;\n\tstruct list_head retransmit;\n\tstruct list_head abandoned;\n\t__u32 outstanding_bytes;\n\tchar fast_rtx;\n\tchar cork;\n};\n\nstruct sctp_ulpq {\n\tchar pd_mode;\n\tstruct sctp_association *asoc;\n\tstruct sk_buff_head reasm;\n\tstruct sk_buff_head reasm_uo;\n\tstruct sk_buff_head lobby;\n};\n\nstruct sctp_priv_assoc_stats {\n\tstruct __kernel_sockaddr_storage obs_rto_ipaddr;\n\t__u64 max_obs_rto;\n\t__u64 isacks;\n\t__u64 osacks;\n\t__u64 opackets;\n\t__u64 ipackets;\n\t__u64 rtxchunks;\n\t__u64 outofseqtsns;\n\t__u64 idupchunks;\n\t__u64 gapcnt;\n\t__u64 ouodchunks;\n\t__u64 iuodchunks;\n\t__u64 oodchunks;\n\t__u64 iodchunks;\n\t__u64 octrlchunks;\n\t__u64 ictrlchunks;\n};\n\nstruct sctp_transport;\n\nstruct sctp_auth_bytes;\n\nstruct sctp_shared_key;\n\nstruct sctp_association {\n\tstruct sctp_ep_common base;\n\tstruct list_head asocs;\n\tsctp_assoc_t assoc_id;\n\tstruct sctp_endpoint *ep;\n\tstruct sctp_cookie c;\n\tstruct {\n\t\tstruct list_head transport_addr_list;\n\t\t__u32 rwnd;\n\t\t__u16 transport_count;\n\t\t__u16 port;\n\t\tstruct sctp_transport *primary_path;\n\t\tunion sctp_addr primary_addr;\n\t\tstruct sctp_transport *active_path;\n\t\tstruct sctp_transport *retran_path;\n\t\tstruct sctp_transport *last_sent_to;\n\t\tstruct sctp_transport *last_data_from;\n\t\tstruct sctp_tsnmap tsn_map;\n\t\t__be16 addip_disabled_mask;\n\t\t__u16 ecn_capable: 1;\n\t\t__u16 ipv4_address: 1;\n\t\t__u16 ipv6_address: 1;\n\t\t__u16 hostname_address: 1;\n\t\t__u16 asconf_capable: 1;\n\t\t__u16 prsctp_capable: 1;\n\t\t__u16 reconf_capable: 1;\n\t\t__u16 intl_capable: 1;\n\t\t__u16 auth_capable: 1;\n\t\t__u16 sack_needed: 1;\n\t\t__u16 sack_generation: 1;\n\t\t__u16 zero_window_announced: 1;\n\t\t__u32 sack_cnt;\n\t\t__u32 adaptation_ind;\n\t\tstruct sctp_inithdr_host i;\n\t\tvoid *cookie;\n\t\tint cookie_len;\n\t\t__u32 addip_serial;\n\t\tstruct sctp_random_param *peer_random;\n\t\tstruct sctp_chunks_param *peer_chunks;\n\t\tstruct sctp_hmac_algo_param *peer_hmacs;\n\t} peer;\n\tenum sctp_state state;\n\tint overall_error_count;\n\tktime_t cookie_life;\n\tlong unsigned int rto_initial;\n\tlong unsigned int rto_max;\n\tlong unsigned int rto_min;\n\tint max_burst;\n\tint max_retrans;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\t__u16 max_init_attempts;\n\t__u16 init_retries;\n\tlong unsigned int max_init_timeo;\n\tlong unsigned int hbinterval;\n\t__u16 pathmaxrxt;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\t__u8 pmtu_pending;\n\t__u32 pathmtu;\n\t__u32 param_flags;\n\t__u32 sackfreq;\n\tlong unsigned int sackdelay;\n\tlong unsigned int timeouts[11];\n\tstruct timer_list timers[11];\n\tstruct sctp_transport *shutdown_last_sent_to;\n\tstruct sctp_transport *init_last_sent_to;\n\tint shutdown_retries;\n\t__u32 next_tsn;\n\t__u32 ctsn_ack_point;\n\t__u32 adv_peer_ack_point;\n\t__u32 highest_sacked;\n\t__u32 fast_recovery_exit;\n\t__u8 fast_recovery;\n\t__u16 unack_data;\n\t__u32 rtx_data_chunks;\n\t__u32 rwnd;\n\t__u32 a_rwnd;\n\t__u32 rwnd_over;\n\t__u32 rwnd_press;\n\tint sndbuf_used;\n\tatomic_t rmem_alloc;\n\twait_queue_head_t wait;\n\t__u32 frag_point;\n\t__u32 user_frag;\n\tint init_err_counter;\n\tint init_cycle;\n\t__u16 default_stream;\n\t__u16 default_flags;\n\t__u32 default_ppid;\n\t__u32 default_context;\n\t__u32 default_timetolive;\n\t__u32 default_rcv_context;\n\tstruct sctp_stream stream;\n\tstruct sctp_outq outqueue;\n\tstruct sctp_ulpq ulpq;\n\t__u32 last_ecne_tsn;\n\t__u32 last_cwr_tsn;\n\tint numduptsns;\n\tstruct sctp_chunk *addip_last_asconf;\n\tstruct list_head asconf_ack_list;\n\tstruct list_head addip_chunk_list;\n\t__u32 addip_serial;\n\tint src_out_of_asoc_ok;\n\tunion sctp_addr *asconf_addr_del_pending;\n\tstruct sctp_transport *new_transport;\n\tstruct list_head endpoint_shared_keys;\n\tstruct sctp_auth_bytes *asoc_shared_key;\n\tstruct sctp_shared_key *shkey;\n\t__u16 default_hmac_id;\n\t__u16 active_key_id;\n\t__u8 need_ecne: 1;\n\t__u8 temp: 1;\n\t__u8 pf_expose: 2;\n\t__u8 force_delay: 1;\n\t__u8 strreset_enable;\n\t__u8 strreset_outstanding;\n\t__u32 strreset_outseq;\n\t__u32 strreset_inseq;\n\t__u32 strreset_result[2];\n\tstruct sctp_chunk *strreset_chunk;\n\tstruct sctp_priv_assoc_stats stats;\n\tint sent_cnt_removable;\n\t__u16 subscribe;\n\t__u64 abandoned_unsent[3];\n\t__u64 abandoned_sent[3];\n\tstruct callback_head rcu;\n};\n\nstruct sctp_auth_bytes {\n\trefcount_t refcnt;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct sctp_shared_key {\n\tstruct list_head key_list;\n\tstruct sctp_auth_bytes *key;\n\trefcount_t refcnt;\n\t__u16 key_id;\n\t__u8 deactivated;\n};\n\nenum {\n\tSCTP_MAX_STREAM = 65535,\n};\n\nenum sctp_event_timeout {\n\tSCTP_EVENT_TIMEOUT_NONE = 0,\n\tSCTP_EVENT_TIMEOUT_T1_COOKIE = 1,\n\tSCTP_EVENT_TIMEOUT_T1_INIT = 2,\n\tSCTP_EVENT_TIMEOUT_T2_SHUTDOWN = 3,\n\tSCTP_EVENT_TIMEOUT_T3_RTX = 4,\n\tSCTP_EVENT_TIMEOUT_T4_RTO = 5,\n\tSCTP_EVENT_TIMEOUT_T5_SHUTDOWN_GUARD = 6,\n\tSCTP_EVENT_TIMEOUT_HEARTBEAT = 7,\n\tSCTP_EVENT_TIMEOUT_RECONF = 8,\n\tSCTP_EVENT_TIMEOUT_SACK = 9,\n\tSCTP_EVENT_TIMEOUT_AUTOCLOSE = 10,\n};\n\nenum {\n\tSCTP_MAX_DUP_TSNS = 16,\n};\n\nenum sctp_scope {\n\tSCTP_SCOPE_GLOBAL = 0,\n\tSCTP_SCOPE_PRIVATE = 1,\n\tSCTP_SCOPE_LINK = 2,\n\tSCTP_SCOPE_LOOPBACK = 3,\n\tSCTP_SCOPE_UNUSABLE = 4,\n};\n\nenum {\n\tSCTP_AUTH_HMAC_ID_RESERVED_0 = 0,\n\tSCTP_AUTH_HMAC_ID_SHA1 = 1,\n\tSCTP_AUTH_HMAC_ID_RESERVED_2 = 2,\n\tSCTP_AUTH_HMAC_ID_SHA256 = 3,\n\t__SCTP_AUTH_HMAC_MAX = 4,\n};\n\nstruct sctp_ulpevent {\n\tstruct sctp_association *asoc;\n\tstruct sctp_chunk *chunk;\n\tunsigned int rmem_len;\n\tunion {\n\t\t__u32 mid;\n\t\t__u16 ssn;\n\t};\n\tunion {\n\t\t__u32 ppid;\n\t\t__u32 fsn;\n\t};\n\t__u32 tsn;\n\t__u32 cumtsn;\n\t__u16 stream;\n\t__u16 flags;\n\t__u16 msg_flags;\n} __attribute__((packed));\n\nunion sctp_addr_param;\n\nunion sctp_params {\n\tvoid *v;\n\tstruct sctp_paramhdr *p;\n\tstruct sctp_cookie_preserve_param *life;\n\tstruct sctp_hostname_param *dns;\n\tstruct sctp_cookie_param *cookie;\n\tstruct sctp_supported_addrs_param *sat;\n\tstruct sctp_ipv4addr_param *v4;\n\tstruct sctp_ipv6addr_param *v6;\n\tunion sctp_addr_param *addr;\n\tstruct sctp_adaptation_ind_param *aind;\n\tstruct sctp_supported_ext_param *ext;\n\tstruct sctp_random_param *random;\n\tstruct sctp_chunks_param *chunks;\n\tstruct sctp_hmac_algo_param *hmac_algo;\n\tstruct sctp_addip_param *addip;\n};\n\nstruct sctp_sender_hb_info;\n\nstruct sctp_signed_cookie;\n\nstruct sctp_datamsg;\n\nstruct sctp_chunk {\n\tstruct list_head list;\n\trefcount_t refcnt;\n\tint sent_count;\n\tunion {\n\t\tstruct list_head transmitted_list;\n\t\tstruct list_head stream_list;\n\t};\n\tstruct list_head frag_list;\n\tstruct sk_buff *skb;\n\tunion {\n\t\tstruct sk_buff *head_skb;\n\t\tstruct sctp_shared_key *shkey;\n\t};\n\tunion sctp_params param_hdr;\n\tunion {\n\t\t__u8 *v;\n\t\tstruct sctp_datahdr *data_hdr;\n\t\tstruct sctp_inithdr *init_hdr;\n\t\tstruct sctp_sackhdr *sack_hdr;\n\t\tstruct sctp_heartbeathdr *hb_hdr;\n\t\tstruct sctp_sender_hb_info *hbs_hdr;\n\t\tstruct sctp_shutdownhdr *shutdown_hdr;\n\t\tstruct sctp_signed_cookie *cookie_hdr;\n\t\tstruct sctp_ecnehdr *ecne_hdr;\n\t\tstruct sctp_cwrhdr *ecn_cwr_hdr;\n\t\tstruct sctp_errhdr *err_hdr;\n\t\tstruct sctp_addiphdr *addip_hdr;\n\t\tstruct sctp_fwdtsn_hdr *fwdtsn_hdr;\n\t\tstruct sctp_authhdr *auth_hdr;\n\t\tstruct sctp_idatahdr *idata_hdr;\n\t\tstruct sctp_ifwdtsn_hdr *ifwdtsn_hdr;\n\t} subh;\n\t__u8 *chunk_end;\n\tstruct sctp_chunkhdr *chunk_hdr;\n\tstruct sctphdr *sctp_hdr;\n\tstruct sctp_sndrcvinfo sinfo;\n\tstruct sctp_association *asoc;\n\tstruct sctp_ep_common *rcvr;\n\tlong unsigned int sent_at;\n\tunion sctp_addr source;\n\tunion sctp_addr dest;\n\tstruct sctp_datamsg *msg;\n\tstruct sctp_transport *transport;\n\tstruct sk_buff *auth_chunk;\n\t__u16 rtt_in_progress: 1;\n\t__u16 has_tsn: 1;\n\t__u16 has_ssn: 1;\n\t__u16 singleton: 1;\n\t__u16 end_of_packet: 1;\n\t__u16 ecn_ce_done: 1;\n\t__u16 pdiscard: 1;\n\t__u16 tsn_gap_acked: 1;\n\t__u16 data_accepted: 1;\n\t__u16 auth: 1;\n\t__u16 has_asconf: 1;\n\t__u16 tsn_missing_report: 2;\n\t__u16 fast_retransmit: 2;\n};\n\nstruct sctp_stream_interleave {\n\t__u16 data_chunk_len;\n\t__u16 ftsn_chunk_len;\n\tstruct sctp_chunk * (*make_datafrag)(const struct sctp_association *, const struct sctp_sndrcvinfo *, int, __u8, gfp_t);\n\tvoid (*assign_number)(struct sctp_chunk *);\n\tbool (*validate_data)(struct sctp_chunk *);\n\tint (*ulpevent_data)(struct sctp_ulpq *, struct sctp_chunk *, gfp_t);\n\tint (*enqueue_event)(struct sctp_ulpq *, struct sctp_ulpevent *);\n\tvoid (*renege_events)(struct sctp_ulpq *, struct sctp_chunk *, gfp_t);\n\tvoid (*start_pd)(struct sctp_ulpq *, gfp_t);\n\tvoid (*abort_pd)(struct sctp_ulpq *, gfp_t);\n\tvoid (*generate_ftsn)(struct sctp_outq *, __u32);\n\tbool (*validate_ftsn)(struct sctp_chunk *);\n\tvoid (*report_ftsn)(struct sctp_ulpq *, __u32);\n\tvoid (*handle_ftsn)(struct sctp_ulpq *, struct sctp_chunk *);\n};\n\nstruct sctp_bind_bucket {\n\tshort unsigned int port;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n\tkuid_t fastuid;\n\tstruct hlist_node node;\n\tstruct hlist_head owner;\n\tstruct net *net;\n};\n\nstruct sctp_bind_hashbucket {\n\tspinlock_t lock;\n\tstruct hlist_head chain;\n};\n\nstruct sctp_hashbucket {\n\trwlock_t lock;\n\tstruct hlist_head chain;\n};\n\nstruct sctp_globals {\n\tstruct list_head address_families;\n\tstruct sctp_hashbucket *ep_hashtable;\n\tstruct sctp_bind_hashbucket *port_hashtable;\n\tstruct rhltable transport_hashtable;\n\tint ep_hashsize;\n\tint port_hashsize;\n\t__u16 max_instreams;\n\t__u16 max_outstreams;\n\tbool checksum_disable;\n};\n\nenum sctp_socket_type {\n\tSCTP_SOCKET_UDP = 0,\n\tSCTP_SOCKET_UDP_HIGH_BANDWIDTH = 1,\n\tSCTP_SOCKET_TCP = 2,\n};\n\nstruct sctp_pf;\n\nstruct sctp_sock {\n\tstruct inet_sock inet;\n\tenum sctp_socket_type type;\n\tint: 32;\n\tstruct sctp_pf *pf;\n\tstruct crypto_shash *hmac;\n\tchar *sctp_hmac_alg;\n\tstruct sctp_endpoint *ep;\n\tstruct sctp_bind_bucket *bind_hash;\n\t__u16 default_stream;\n\tshort: 16;\n\t__u32 default_ppid;\n\t__u16 default_flags;\n\tshort: 16;\n\t__u32 default_context;\n\t__u32 default_timetolive;\n\t__u32 default_rcv_context;\n\tint max_burst;\n\t__u32 hbinterval;\n\t__u16 pathmaxrxt;\n\tshort: 16;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\tchar: 8;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\tshort: 16;\n\t__u32 pathmtu;\n\t__u32 sackdelay;\n\t__u32 sackfreq;\n\t__u32 param_flags;\n\t__u32 default_ss;\n\tstruct sctp_rtoinfo rtoinfo;\n\tstruct sctp_paddrparams paddrparam;\n\tstruct sctp_assocparams assocparams;\n\t__u16 subscribe;\n\tstruct sctp_initmsg initmsg;\n\tshort: 16;\n\tint user_frag;\n\t__u32 autoclose;\n\t__u32 adaptation_ind;\n\t__u32 pd_point;\n\t__u16 nodelay: 1;\n\t__u16 pf_expose: 2;\n\t__u16 reuse: 1;\n\t__u16 disable_fragments: 1;\n\t__u16 v4mapped: 1;\n\t__u16 frag_interleave: 1;\n\t__u16 recvrcvinfo: 1;\n\t__u16 recvnxtinfo: 1;\n\t__u16 data_ready_signalled: 1;\n\tint: 22;\n\tatomic_t pd_mode;\n\tstruct sk_buff_head pd_lobby;\n\tstruct list_head auto_asconf_list;\n\tint do_auto_asconf;\n\tint: 32;\n} __attribute__((packed));\n\nstruct sctp_af;\n\nstruct sctp_pf {\n\tvoid (*event_msgname)(struct sctp_ulpevent *, char *, int *);\n\tvoid (*skb_msgname)(struct sk_buff *, char *, int *);\n\tint (*af_supported)(sa_family_t, struct sctp_sock *);\n\tint (*cmp_addr)(const union sctp_addr *, const union sctp_addr *, struct sctp_sock *);\n\tint (*bind_verify)(struct sctp_sock *, union sctp_addr *);\n\tint (*send_verify)(struct sctp_sock *, union sctp_addr *);\n\tint (*supported_addrs)(const struct sctp_sock *, __be16 *);\n\tstruct sock * (*create_accept_sk)(struct sock *, struct sctp_association *, bool);\n\tint (*addr_to_user)(struct sctp_sock *, union sctp_addr *);\n\tvoid (*to_sk_saddr)(union sctp_addr *, struct sock *);\n\tvoid (*to_sk_daddr)(union sctp_addr *, struct sock *);\n\tvoid (*copy_ip_options)(struct sock *, struct sock *);\n\tstruct sctp_af *af;\n};\n\nstruct sctp_signed_cookie {\n\t__u8 signature[32];\n\t__u32 __pad;\n\tstruct sctp_cookie c;\n} __attribute__((packed));\n\nunion sctp_addr_param {\n\tstruct sctp_paramhdr p;\n\tstruct sctp_ipv4addr_param v4;\n\tstruct sctp_ipv6addr_param v6;\n};\n\nstruct sctp_sender_hb_info {\n\tstruct sctp_paramhdr param_hdr;\n\tunion sctp_addr daddr;\n\tlong unsigned int sent_at;\n\t__u64 hb_nonce;\n};\n\nstruct sctp_af {\n\tint (*sctp_xmit)(struct sk_buff *, struct sctp_transport *);\n\tint (*setsockopt)(struct sock *, int, int, char *, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tint (*compat_setsockopt)(struct sock *, int, int, char *, unsigned int);\n\tint (*compat_getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*get_dst)(struct sctp_transport *, union sctp_addr *, struct flowi *, struct sock *);\n\tvoid (*get_saddr)(struct sctp_sock *, struct sctp_transport *, struct flowi *);\n\tvoid (*copy_addrlist)(struct list_head *, struct net_device *);\n\tint (*cmp_addr)(const union sctp_addr *, const union sctp_addr *);\n\tvoid (*addr_copy)(union sctp_addr *, union sctp_addr *);\n\tvoid (*from_skb)(union sctp_addr *, struct sk_buff *, int);\n\tvoid (*from_sk)(union sctp_addr *, struct sock *);\n\tvoid (*from_addr_param)(union sctp_addr *, union sctp_addr_param *, __be16, int);\n\tint (*to_addr_param)(const union sctp_addr *, union sctp_addr_param *);\n\tint (*addr_valid)(union sctp_addr *, struct sctp_sock *, const struct sk_buff *);\n\tenum sctp_scope (*scope)(union sctp_addr *);\n\tvoid (*inaddr_any)(union sctp_addr *, __be16);\n\tint (*is_any)(const union sctp_addr *);\n\tint (*available)(union sctp_addr *, struct sctp_sock *);\n\tint (*skb_iif)(const struct sk_buff *);\n\tint (*is_ce)(const struct sk_buff *);\n\tvoid (*seq_dump_addr)(struct seq_file *, union sctp_addr *);\n\tvoid (*ecn_capable)(struct sock *);\n\t__u16 net_header_len;\n\tint sockaddr_len;\n\tint (*ip_options_len)(struct sock *);\n\tsa_family_t sa_family;\n\tstruct list_head list;\n};\n\nstruct sctp_packet {\n\t__u16 source_port;\n\t__u16 destination_port;\n\t__u32 vtag;\n\tstruct list_head chunk_list;\n\tsize_t overhead;\n\tsize_t size;\n\tsize_t max_size;\n\tstruct sctp_transport *transport;\n\tstruct sctp_chunk *auth;\n\tu8 has_cookie_echo: 1;\n\tu8 has_sack: 1;\n\tu8 has_auth: 1;\n\tu8 has_data: 1;\n\tu8 ipfragok: 1;\n};\n\nstruct sctp_transport {\n\tstruct list_head transports;\n\tstruct rhlist_head node;\n\trefcount_t refcnt;\n\t__u32 rto_pending: 1;\n\t__u32 hb_sent: 1;\n\t__u32 pmtu_pending: 1;\n\t__u32 dst_pending_confirm: 1;\n\t__u32 sack_generation: 1;\n\tu32 dst_cookie;\n\tstruct flowi fl;\n\tunion sctp_addr ipaddr;\n\tstruct sctp_af *af_specific;\n\tstruct sctp_association *asoc;\n\tlong unsigned int rto;\n\t__u32 rtt;\n\t__u32 rttvar;\n\t__u32 srtt;\n\t__u32 cwnd;\n\t__u32 ssthresh;\n\t__u32 partial_bytes_acked;\n\t__u32 flight_size;\n\t__u32 burst_limited;\n\tstruct dst_entry *dst;\n\tunion sctp_addr saddr;\n\tlong unsigned int hbinterval;\n\tlong unsigned int sackdelay;\n\t__u32 sackfreq;\n\tatomic_t mtu_info;\n\tktime_t last_time_heard;\n\tlong unsigned int last_time_sent;\n\tlong unsigned int last_time_ecne_reduced;\n\t__u16 pathmaxrxt;\n\t__u32 flowlabel;\n\t__u8 dscp;\n\t__u16 pf_retrans;\n\t__u16 ps_retrans;\n\t__u32 pathmtu;\n\t__u32 param_flags;\n\tint init_sent_count;\n\tint state;\n\tshort unsigned int error_count;\n\tstruct timer_list T3_rtx_timer;\n\tstruct timer_list hb_timer;\n\tstruct timer_list proto_unreach_timer;\n\tstruct timer_list reconf_timer;\n\tstruct list_head transmitted;\n\tstruct sctp_packet packet;\n\tstruct list_head send_ready;\n\tstruct {\n\t\t__u32 next_tsn_at_change;\n\t\tchar changeover_active;\n\t\tchar cycling_changeover;\n\t\tchar cacc_saw_newack;\n\t} cacc;\n\t__u64 hb_nonce;\n\tstruct callback_head rcu;\n};\n\nstruct sctp_datamsg {\n\tstruct list_head chunks;\n\trefcount_t refcnt;\n\tlong unsigned int expires_at;\n\tint send_error;\n\tu8 send_failed: 1;\n\tu8 can_delay: 1;\n\tu8 abandoned: 1;\n};\n\nstruct sctp_stream_priorities {\n\tstruct list_head prio_sched;\n\tstruct list_head active;\n\tstruct sctp_stream_out_ext *next;\n\t__u16 prio;\n};\n\nstruct sctp_stream_out_ext {\n\t__u64 abandoned_unsent[3];\n\t__u64 abandoned_sent[3];\n\tstruct list_head outq;\n\tunion {\n\t\tstruct {\n\t\t\tstruct list_head prio_list;\n\t\t\tstruct sctp_stream_priorities *prio_head;\n\t\t};\n\t\tstruct {\n\t\t\tstruct list_head rr_list;\n\t\t};\n\t};\n};\n\nstruct task_security_struct {\n\tu32 osid;\n\tu32 sid;\n\tu32 exec_sid;\n\tu32 create_sid;\n\tu32 keycreate_sid;\n\tu32 sockcreate_sid;\n};\n\nenum label_initialized {\n\tLABEL_INVALID = 0,\n\tLABEL_INITIALIZED = 1,\n\tLABEL_PENDING = 2,\n};\n\nstruct inode_security_struct {\n\tstruct inode *inode;\n\tstruct list_head list;\n\tu32 task_sid;\n\tu32 sid;\n\tu16 sclass;\n\tunsigned char initialized;\n\tspinlock_t lock;\n};\n\nstruct file_security_struct {\n\tu32 sid;\n\tu32 fown_sid;\n\tu32 isid;\n\tu32 pseqno;\n};\n\nstruct superblock_security_struct {\n\tstruct super_block *sb;\n\tu32 sid;\n\tu32 def_sid;\n\tu32 mntpoint_sid;\n\tshort unsigned int behavior;\n\tshort unsigned int flags;\n\tstruct mutex lock;\n\tstruct list_head isec_head;\n\tspinlock_t isec_lock;\n};\n\nstruct msg_security_struct {\n\tu32 sid;\n};\n\nstruct ipc_security_struct {\n\tu16 sclass;\n\tu32 sid;\n};\n\nstruct sk_security_struct {\n\tenum {\n\t\tNLBL_UNSET = 0,\n\t\tNLBL_REQUIRE = 1,\n\t\tNLBL_LABELED = 2,\n\t\tNLBL_REQSKB = 3,\n\t\tNLBL_CONNLABELED = 4,\n\t} nlbl_state;\n\tstruct netlbl_lsm_secattr *nlbl_secattr;\n\tu32 sid;\n\tu32 peer_sid;\n\tu16 sclass;\n\tenum {\n\t\tSCTP_ASSOC_UNSET = 0,\n\t\tSCTP_ASSOC_SET = 1,\n\t} sctp_assoc_state;\n};\n\nstruct tun_security_struct {\n\tu32 sid;\n};\n\nstruct key_security_struct {\n\tu32 sid;\n};\n\nstruct bpf_security_struct {\n\tu32 sid;\n};\n\nstruct perf_event_security_struct {\n\tu32 sid;\n};\n\nstruct selinux_mnt_opts {\n\tconst char *fscontext;\n\tconst char *context;\n\tconst char *rootcontext;\n\tconst char *defcontext;\n};\n\nenum {\n\tOpt_error = 4294967295,\n\tOpt_context = 0,\n\tOpt_defcontext = 1,\n\tOpt_fscontext = 2,\n\tOpt_rootcontext = 3,\n\tOpt_seclabel = 4,\n};\n\nenum sel_inos {\n\tSEL_ROOT_INO = 2,\n\tSEL_LOAD = 3,\n\tSEL_ENFORCE = 4,\n\tSEL_CONTEXT = 5,\n\tSEL_ACCESS = 6,\n\tSEL_CREATE = 7,\n\tSEL_RELABEL = 8,\n\tSEL_USER = 9,\n\tSEL_POLICYVERS = 10,\n\tSEL_COMMIT_BOOLS = 11,\n\tSEL_MLS = 12,\n\tSEL_DISABLE = 13,\n\tSEL_MEMBER = 14,\n\tSEL_CHECKREQPROT = 15,\n\tSEL_COMPAT_NET = 16,\n\tSEL_REJECT_UNKNOWN = 17,\n\tSEL_DENY_UNKNOWN = 18,\n\tSEL_STATUS = 19,\n\tSEL_POLICY = 20,\n\tSEL_VALIDATE_TRANS = 21,\n\tSEL_INO_NEXT = 22,\n};\n\nstruct selinux_fs_info {\n\tstruct dentry *bool_dir;\n\tunsigned int bool_num;\n\tchar **bool_pending_names;\n\tunsigned int *bool_pending_values;\n\tstruct dentry *class_dir;\n\tlong unsigned int last_class_ino;\n\tbool policy_opened;\n\tstruct dentry *policycap_dir;\n\tstruct mutex mutex;\n\tlong unsigned int last_ino;\n\tstruct selinux_state *state;\n\tstruct super_block *sb;\n};\n\nstruct policy_load_memory {\n\tsize_t len;\n\tvoid *data;\n};\n\nenum {\n\tSELNL_MSG_SETENFORCE = 16,\n\tSELNL_MSG_POLICYLOAD = 17,\n\tSELNL_MSG_MAX = 18,\n};\n\nenum selinux_nlgroups {\n\tSELNLGRP_NONE = 0,\n\tSELNLGRP_AVC = 1,\n\t__SELNLGRP_MAX = 2,\n};\n\nstruct selnl_msg_setenforce {\n\t__s32 val;\n};\n\nstruct selnl_msg_policyload {\n\t__u32 seqno;\n};\n\nenum {\n\tXFRM_MSG_BASE = 16,\n\tXFRM_MSG_NEWSA = 16,\n\tXFRM_MSG_DELSA = 17,\n\tXFRM_MSG_GETSA = 18,\n\tXFRM_MSG_NEWPOLICY = 19,\n\tXFRM_MSG_DELPOLICY = 20,\n\tXFRM_MSG_GETPOLICY = 21,\n\tXFRM_MSG_ALLOCSPI = 22,\n\tXFRM_MSG_ACQUIRE = 23,\n\tXFRM_MSG_EXPIRE = 24,\n\tXFRM_MSG_UPDPOLICY = 25,\n\tXFRM_MSG_UPDSA = 26,\n\tXFRM_MSG_POLEXPIRE = 27,\n\tXFRM_MSG_FLUSHSA = 28,\n\tXFRM_MSG_FLUSHPOLICY = 29,\n\tXFRM_MSG_NEWAE = 30,\n\tXFRM_MSG_GETAE = 31,\n\tXFRM_MSG_REPORT = 32,\n\tXFRM_MSG_MIGRATE = 33,\n\tXFRM_MSG_NEWSADINFO = 34,\n\tXFRM_MSG_GETSADINFO = 35,\n\tXFRM_MSG_NEWSPDINFO = 36,\n\tXFRM_MSG_GETSPDINFO = 37,\n\tXFRM_MSG_MAPPING = 38,\n\t__XFRM_MSG_MAX = 39,\n};\n\nenum {\n\tRTM_BASE = 16,\n\tRTM_NEWLINK = 16,\n\tRTM_DELLINK = 17,\n\tRTM_GETLINK = 18,\n\tRTM_SETLINK = 19,\n\tRTM_NEWADDR = 20,\n\tRTM_DELADDR = 21,\n\tRTM_GETADDR = 22,\n\tRTM_NEWROUTE = 24,\n\tRTM_DELROUTE = 25,\n\tRTM_GETROUTE = 26,\n\tRTM_NEWNEIGH = 28,\n\tRTM_DELNEIGH = 29,\n\tRTM_GETNEIGH = 30,\n\tRTM_NEWRULE = 32,\n\tRTM_DELRULE = 33,\n\tRTM_GETRULE = 34,\n\tRTM_NEWQDISC = 36,\n\tRTM_DELQDISC = 37,\n\tRTM_GETQDISC = 38,\n\tRTM_NEWTCLASS = 40,\n\tRTM_DELTCLASS = 41,\n\tRTM_GETTCLASS = 42,\n\tRTM_NEWTFILTER = 44,\n\tRTM_DELTFILTER = 45,\n\tRTM_GETTFILTER = 46,\n\tRTM_NEWACTION = 48,\n\tRTM_DELACTION = 49,\n\tRTM_GETACTION = 50,\n\tRTM_NEWPREFIX = 52,\n\tRTM_GETMULTICAST = 58,\n\tRTM_GETANYCAST = 62,\n\tRTM_NEWNEIGHTBL = 64,\n\tRTM_GETNEIGHTBL = 66,\n\tRTM_SETNEIGHTBL = 67,\n\tRTM_NEWNDUSEROPT = 68,\n\tRTM_NEWADDRLABEL = 72,\n\tRTM_DELADDRLABEL = 73,\n\tRTM_GETADDRLABEL = 74,\n\tRTM_GETDCB = 78,\n\tRTM_SETDCB = 79,\n\tRTM_NEWNETCONF = 80,\n\tRTM_DELNETCONF = 81,\n\tRTM_GETNETCONF = 82,\n\tRTM_NEWMDB = 84,\n\tRTM_DELMDB = 85,\n\tRTM_GETMDB = 86,\n\tRTM_NEWNSID = 88,\n\tRTM_DELNSID = 89,\n\tRTM_GETNSID = 90,\n\tRTM_NEWSTATS = 92,\n\tRTM_GETSTATS = 94,\n\tRTM_NEWCACHEREPORT = 96,\n\tRTM_NEWCHAIN = 100,\n\tRTM_DELCHAIN = 101,\n\tRTM_GETCHAIN = 102,\n\tRTM_NEWNEXTHOP = 104,\n\tRTM_DELNEXTHOP = 105,\n\tRTM_GETNEXTHOP = 106,\n\tRTM_NEWLINKPROP = 108,\n\tRTM_DELLINKPROP = 109,\n\tRTM_GETLINKPROP = 110,\n\tRTM_NEWVLAN = 112,\n\tRTM_DELVLAN = 113,\n\tRTM_GETVLAN = 114,\n\t__RTM_MAX = 115,\n};\n\nstruct nlmsg_perm {\n\tu16 nlmsg_type;\n\tu32 perm;\n};\n\nstruct netif_security_struct {\n\tstruct net *ns;\n\tint ifindex;\n\tu32 sid;\n};\n\nstruct sel_netif {\n\tstruct list_head list;\n\tstruct netif_security_struct nsec;\n\tstruct callback_head callback_head;\n};\n\nstruct netnode_security_struct {\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} addr;\n\tu32 sid;\n\tu16 family;\n};\n\nstruct sel_netnode_bkt {\n\tunsigned int size;\n\tstruct list_head list;\n};\n\nstruct sel_netnode {\n\tstruct netnode_security_struct nsec;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct netport_security_struct {\n\tu32 sid;\n\tu16 port;\n\tu8 protocol;\n};\n\nstruct sel_netport_bkt {\n\tint size;\n\tstruct list_head list;\n};\n\nstruct sel_netport {\n\tstruct netport_security_struct psec;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct selinux_kernel_status {\n\tu32 version;\n\tu32 sequence;\n\tu32 enforcing;\n\tu32 policyload;\n\tu32 deny_unknown;\n};\n\nstruct ebitmap_node {\n\tstruct ebitmap_node *next;\n\tlong unsigned int maps[6];\n\tu32 startbit;\n};\n\nstruct ebitmap {\n\tstruct ebitmap_node *node;\n\tu32 highbit;\n};\n\nstruct policy_file {\n\tchar *data;\n\tsize_t len;\n};\n\nstruct hashtab_node {\n\tvoid *key;\n\tvoid *datum;\n\tstruct hashtab_node *next;\n};\n\nstruct hashtab {\n\tstruct hashtab_node **htable;\n\tu32 size;\n\tu32 nel;\n\tu32 (*hash_value)(struct hashtab *, const void *);\n\tint (*keycmp)(struct hashtab *, const void *, const void *);\n};\n\nstruct hashtab_info {\n\tu32 slots_used;\n\tu32 max_chain_len;\n};\n\nstruct symtab {\n\tstruct hashtab table;\n\tu32 nprim;\n};\n\nstruct mls_level {\n\tu32 sens;\n\tstruct ebitmap cat;\n};\n\nstruct mls_range {\n\tstruct mls_level level[2];\n};\n\nstruct context___2 {\n\tu32 user;\n\tu32 role;\n\tu32 type;\n\tu32 len;\n\tstruct mls_range range;\n\tchar *str;\n};\n\nstruct sidtab_str_cache;\n\nstruct sidtab_entry {\n\tu32 sid;\n\tu32 hash;\n\tstruct context___2 context;\n\tstruct sidtab_str_cache *cache;\n\tstruct hlist_node list;\n};\n\nstruct sidtab_str_cache {\n\tstruct callback_head rcu_member;\n\tstruct list_head lru_member;\n\tstruct sidtab_entry *parent;\n\tu32 len;\n\tchar str[0];\n};\n\nstruct sidtab_node_inner;\n\nstruct sidtab_node_leaf;\n\nunion sidtab_entry_inner {\n\tstruct sidtab_node_inner *ptr_inner;\n\tstruct sidtab_node_leaf *ptr_leaf;\n};\n\nstruct sidtab_node_inner {\n\tunion sidtab_entry_inner entries[512];\n};\n\nstruct sidtab_node_leaf {\n\tstruct sidtab_entry entries[39];\n};\n\nstruct sidtab_isid_entry {\n\tint set;\n\tstruct sidtab_entry entry;\n};\n\nstruct sidtab;\n\nstruct sidtab_convert_params {\n\tint (*func)(struct context___2 *, struct context___2 *, void *);\n\tvoid *args;\n\tstruct sidtab *target;\n};\n\nstruct sidtab {\n\tunion sidtab_entry_inner roots[4];\n\tu32 count;\n\tstruct sidtab_convert_params *convert;\n\tspinlock_t lock;\n\tu32 cache_free_slots;\n\tstruct list_head cache_lru_list;\n\tspinlock_t cache_lock;\n\tstruct sidtab_isid_entry isids[27];\n\tstruct hlist_head context_to_sid[512];\n};\n\nstruct avtab_key {\n\tu16 source_type;\n\tu16 target_type;\n\tu16 target_class;\n\tu16 specified;\n};\n\nstruct avtab_extended_perms {\n\tu8 specified;\n\tu8 driver;\n\tstruct extended_perms_data perms;\n};\n\nstruct avtab_datum {\n\tunion {\n\t\tu32 data;\n\t\tstruct avtab_extended_perms *xperms;\n\t} u;\n};\n\nstruct avtab_node {\n\tstruct avtab_key key;\n\tstruct avtab_datum datum;\n\tstruct avtab_node *next;\n};\n\nstruct avtab {\n\tstruct avtab_node **htable;\n\tu32 nel;\n\tu32 nslot;\n\tu32 mask;\n};\n\nstruct type_set;\n\nstruct constraint_expr {\n\tu32 expr_type;\n\tu32 attr;\n\tu32 op;\n\tstruct ebitmap names;\n\tstruct type_set *type_names;\n\tstruct constraint_expr *next;\n};\n\nstruct type_set {\n\tstruct ebitmap types;\n\tstruct ebitmap negset;\n\tu32 flags;\n};\n\nstruct constraint_node {\n\tu32 permissions;\n\tstruct constraint_expr *expr;\n\tstruct constraint_node *next;\n};\n\nstruct common_datum {\n\tu32 value;\n\tstruct symtab permissions;\n};\n\nstruct class_datum {\n\tu32 value;\n\tchar *comkey;\n\tstruct common_datum *comdatum;\n\tstruct symtab permissions;\n\tstruct constraint_node *constraints;\n\tstruct constraint_node *validatetrans;\n\tchar default_user;\n\tchar default_role;\n\tchar default_type;\n\tchar default_range;\n};\n\nstruct role_datum {\n\tu32 value;\n\tu32 bounds;\n\tstruct ebitmap dominates;\n\tstruct ebitmap types;\n};\n\nstruct role_allow {\n\tu32 role;\n\tu32 new_role;\n\tstruct role_allow *next;\n};\n\nstruct type_datum {\n\tu32 value;\n\tu32 bounds;\n\tunsigned char primary;\n\tunsigned char attribute;\n};\n\nstruct user_datum {\n\tu32 value;\n\tu32 bounds;\n\tstruct ebitmap roles;\n\tstruct mls_range range;\n\tstruct mls_level dfltlevel;\n};\n\nstruct cond_bool_datum {\n\t__u32 value;\n\tint state;\n};\n\nstruct ocontext {\n\tunion {\n\t\tchar *name;\n\t\tstruct {\n\t\t\tu8 protocol;\n\t\t\tu16 low_port;\n\t\t\tu16 high_port;\n\t\t} port;\n\t\tstruct {\n\t\t\tu32 addr;\n\t\t\tu32 mask;\n\t\t} node;\n\t\tstruct {\n\t\t\tu32 addr[4];\n\t\t\tu32 mask[4];\n\t\t} node6;\n\t\tstruct {\n\t\t\tu64 subnet_prefix;\n\t\t\tu16 low_pkey;\n\t\t\tu16 high_pkey;\n\t\t} ibpkey;\n\t\tstruct {\n\t\t\tchar *dev_name;\n\t\t\tu8 port;\n\t\t} ibendport;\n\t} u;\n\tunion {\n\t\tu32 sclass;\n\t\tu32 behavior;\n\t} v;\n\tstruct context___2 context[2];\n\tu32 sid[2];\n\tstruct ocontext *next;\n};\n\nstruct genfs {\n\tchar *fstype;\n\tstruct ocontext *head;\n\tstruct genfs *next;\n};\n\nstruct cond_node;\n\nstruct policydb {\n\tint mls_enabled;\n\tstruct symtab symtab[8];\n\tchar **sym_val_to_name[8];\n\tstruct class_datum **class_val_to_struct;\n\tstruct role_datum **role_val_to_struct;\n\tstruct user_datum **user_val_to_struct;\n\tstruct type_datum **type_val_to_struct;\n\tstruct avtab te_avtab;\n\tstruct hashtab role_tr;\n\tstruct ebitmap filename_trans_ttypes;\n\tstruct hashtab filename_trans;\n\tu32 compat_filename_trans_count;\n\tstruct cond_bool_datum **bool_val_to_struct;\n\tstruct avtab te_cond_avtab;\n\tstruct cond_node *cond_list;\n\tu32 cond_list_len;\n\tstruct role_allow *role_allow;\n\tstruct ocontext *ocontexts[9];\n\tstruct genfs *genfs;\n\tstruct hashtab range_tr;\n\tstruct ebitmap *type_attr_map_array;\n\tstruct ebitmap policycaps;\n\tstruct ebitmap permissive_map;\n\tsize_t len;\n\tunsigned int policyvers;\n\tunsigned int reject_unknown: 1;\n\tunsigned int allow_unknown: 1;\n\tu16 process_class;\n\tu32 process_trans_perms;\n};\n\nstruct selinux_mapping;\n\nstruct selinux_map {\n\tstruct selinux_mapping *mapping;\n\tu16 size;\n};\n\nstruct selinux_ss {\n\tstruct sidtab *sidtab;\n\tstruct policydb policydb;\n\trwlock_t policy_rwlock;\n\tu32 latest_granting;\n\tstruct selinux_map map;\n};\n\nstruct perm_datum {\n\tu32 value;\n};\n\nstruct role_trans_key {\n\tu32 role;\n\tu32 type;\n\tu32 tclass;\n};\n\nstruct role_trans_datum {\n\tu32 new_role;\n};\n\nstruct filename_trans_key {\n\tu32 ttype;\n\tu16 tclass;\n\tconst char *name;\n};\n\nstruct filename_trans_datum {\n\tstruct ebitmap stypes;\n\tu32 otype;\n\tstruct filename_trans_datum *next;\n};\n\nstruct level_datum {\n\tstruct mls_level *level;\n\tunsigned char isalias;\n};\n\nstruct cat_datum {\n\tu32 value;\n\tunsigned char isalias;\n};\n\nstruct range_trans {\n\tu32 source_type;\n\tu32 target_type;\n\tu32 target_class;\n};\n\nstruct cond_expr_node;\n\nstruct cond_expr {\n\tstruct cond_expr_node *nodes;\n\tu32 len;\n};\n\nstruct cond_av_list {\n\tstruct avtab_node **nodes;\n\tu32 len;\n};\n\nstruct cond_node {\n\tint cur_state;\n\tstruct cond_expr expr;\n\tstruct cond_av_list true_list;\n\tstruct cond_av_list false_list;\n};\n\nstruct policy_data {\n\tstruct policydb *p;\n\tvoid *fp;\n};\n\nstruct cond_expr_node {\n\tu32 expr_type;\n\tu32 bool;\n};\n\nstruct selinux_mapping {\n\tu16 value;\n\tunsigned int num_perms;\n\tu32 perms[32];\n};\n\nstruct policydb_compat_info {\n\tint version;\n\tint sym_num;\n\tint ocon_num;\n};\n\nstruct convert_context_args {\n\tstruct selinux_state *state;\n\tstruct policydb *oldp;\n\tstruct policydb *newp;\n};\n\nstruct selinux_audit_rule {\n\tu32 au_seqno;\n\tstruct context___2 au_ctxt;\n};\n\nstruct cond_insertf_data {\n\tstruct policydb *p;\n\tstruct avtab_node **dst;\n\tstruct cond_av_list *other;\n};\n\nstruct sockaddr_un {\n\t__kernel_sa_family_t sun_family;\n\tchar sun_path[108];\n};\n\nstruct unix_address {\n\trefcount_t refcnt;\n\tint len;\n\tunsigned int hash;\n\tstruct sockaddr_un name[0];\n};\n\nstruct scm_stat {\n\tatomic_t nr_fds;\n};\n\nstruct unix_sock {\n\tstruct sock sk;\n\tstruct unix_address *addr;\n\tstruct path path;\n\tstruct mutex iolock;\n\tstruct mutex bindlock;\n\tstruct sock *peer;\n\tstruct list_head link;\n\tatomic_long_t inflight;\n\tspinlock_t lock;\n\tlong unsigned int gc_flags;\n\tlong: 64;\n\tstruct socket_wq peer_wq;\n\twait_queue_entry_t peer_wake;\n\tstruct scm_stat scm_stat;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n};\n\nenum integrity_status {\n\tINTEGRITY_PASS = 0,\n\tINTEGRITY_PASS_IMMUTABLE = 1,\n\tINTEGRITY_FAIL = 2,\n\tINTEGRITY_NOLABEL = 3,\n\tINTEGRITY_NOXATTRS = 4,\n\tINTEGRITY_UNKNOWN = 5,\n};\n\nstruct ima_digest_data {\n\tu8 algo;\n\tu8 length;\n\tunion {\n\t\tstruct {\n\t\t\tu8 unused;\n\t\t\tu8 type;\n\t\t} sha1;\n\t\tstruct {\n\t\t\tu8 type;\n\t\t\tu8 algo;\n\t\t} ng;\n\t\tu8 data[2];\n\t} xattr;\n\tu8 digest[0];\n};\n\nstruct integrity_iint_cache {\n\tstruct rb_node rb_node;\n\tstruct mutex mutex;\n\tstruct inode *inode;\n\tu64 version;\n\tlong unsigned int flags;\n\tlong unsigned int measured_pcrs;\n\tlong unsigned int atomic_flags;\n\tenum integrity_status ima_file_status: 4;\n\tenum integrity_status ima_mmap_status: 4;\n\tenum integrity_status ima_bprm_status: 4;\n\tenum integrity_status ima_read_status: 4;\n\tenum integrity_status ima_creds_status: 4;\n\tenum integrity_status evm_status: 4;\n\tstruct ima_digest_data *ima_hash;\n};\n\nstruct crypto_async_request;\n\ntypedef void (*crypto_completion_t)(struct crypto_async_request *, int);\n\nstruct crypto_async_request {\n\tstruct list_head list;\n\tcrypto_completion_t complete;\n\tvoid *data;\n\tstruct crypto_tfm *tfm;\n\tu32 flags;\n};\n\nstruct crypto_wait {\n\tstruct completion completion;\n\tint err;\n};\n\nstruct crypto_template;\n\nstruct crypto_spawn;\n\nstruct crypto_instance {\n\tstruct crypto_alg alg;\n\tstruct crypto_template *tmpl;\n\tunion {\n\t\tstruct hlist_node list;\n\t\tstruct crypto_spawn *spawns;\n\t};\n\tvoid *__ctx[0];\n};\n\nstruct crypto_spawn {\n\tstruct list_head list;\n\tstruct crypto_alg *alg;\n\tunion {\n\t\tstruct crypto_instance *inst;\n\t\tstruct crypto_spawn *next;\n\t};\n\tconst struct crypto_type *frontend;\n\tu32 mask;\n\tbool dead;\n\tbool registered;\n};\n\nstruct rtattr;\n\nstruct crypto_template {\n\tstruct list_head list;\n\tstruct hlist_head instances;\n\tstruct module *module;\n\tint (*create)(struct crypto_template *, struct rtattr **);\n\tchar name[128];\n};\n\nenum {\n\tCRYPTO_MSG_ALG_REQUEST = 0,\n\tCRYPTO_MSG_ALG_REGISTER = 1,\n\tCRYPTO_MSG_ALG_LOADED = 2,\n};\n\nstruct crypto_larval {\n\tstruct crypto_alg alg;\n\tstruct crypto_alg *adult;\n\tstruct completion completion;\n\tu32 mask;\n};\n\nstruct crypto_cipher {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_comp {\n\tstruct crypto_tfm base;\n};\n\nenum {\n\tCRYPTOA_UNSPEC = 0,\n\tCRYPTOA_ALG = 1,\n\tCRYPTOA_TYPE = 2,\n\tCRYPTOA_U32 = 3,\n\t__CRYPTOA_MAX = 4,\n};\n\nstruct crypto_attr_alg {\n\tchar name[128];\n};\n\nstruct crypto_attr_type {\n\tu32 type;\n\tu32 mask;\n};\n\nstruct crypto_attr_u32 {\n\tu32 num;\n};\n\nstruct rtattr {\n\tshort unsigned int rta_len;\n\tshort unsigned int rta_type;\n};\n\nstruct crypto_queue {\n\tstruct list_head list;\n\tstruct list_head *backlog;\n\tunsigned int qlen;\n\tunsigned int max_qlen;\n};\n\nstruct scatter_walk {\n\tstruct scatterlist *sg;\n\tunsigned int offset;\n};\n\nstruct aead_request {\n\tstruct crypto_async_request base;\n\tunsigned int assoclen;\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tvoid *__ctx[0];\n};\n\nstruct crypto_aead;\n\nstruct aead_alg {\n\tint (*setkey)(struct crypto_aead *, const u8 *, unsigned int);\n\tint (*setauthsize)(struct crypto_aead *, unsigned int);\n\tint (*encrypt)(struct aead_request *);\n\tint (*decrypt)(struct aead_request *);\n\tint (*init)(struct crypto_aead *);\n\tvoid (*exit)(struct crypto_aead *);\n\tunsigned int ivsize;\n\tunsigned int maxauthsize;\n\tunsigned int chunksize;\n\tstruct crypto_alg base;\n};\n\nstruct crypto_aead {\n\tunsigned int authsize;\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct aead_instance {\n\tvoid (*free)(struct aead_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct aead_alg alg;\n\t};\n};\n\nstruct crypto_aead_spawn {\n\tstruct crypto_spawn base;\n};\n\nenum crypto_attr_type_t {\n\tCRYPTOCFGA_UNSPEC = 0,\n\tCRYPTOCFGA_PRIORITY_VAL = 1,\n\tCRYPTOCFGA_REPORT_LARVAL = 2,\n\tCRYPTOCFGA_REPORT_HASH = 3,\n\tCRYPTOCFGA_REPORT_BLKCIPHER = 4,\n\tCRYPTOCFGA_REPORT_AEAD = 5,\n\tCRYPTOCFGA_REPORT_COMPRESS = 6,\n\tCRYPTOCFGA_REPORT_RNG = 7,\n\tCRYPTOCFGA_REPORT_CIPHER = 8,\n\tCRYPTOCFGA_REPORT_AKCIPHER = 9,\n\tCRYPTOCFGA_REPORT_KPP = 10,\n\tCRYPTOCFGA_REPORT_ACOMP = 11,\n\tCRYPTOCFGA_STAT_LARVAL = 12,\n\tCRYPTOCFGA_STAT_HASH = 13,\n\tCRYPTOCFGA_STAT_BLKCIPHER = 14,\n\tCRYPTOCFGA_STAT_AEAD = 15,\n\tCRYPTOCFGA_STAT_COMPRESS = 16,\n\tCRYPTOCFGA_STAT_RNG = 17,\n\tCRYPTOCFGA_STAT_CIPHER = 18,\n\tCRYPTOCFGA_STAT_AKCIPHER = 19,\n\tCRYPTOCFGA_STAT_KPP = 20,\n\tCRYPTOCFGA_STAT_ACOMP = 21,\n\t__CRYPTOCFGA_MAX = 22,\n};\n\nstruct crypto_report_aead {\n\tchar type[64];\n\tchar geniv[64];\n\tunsigned int blocksize;\n\tunsigned int maxauthsize;\n\tunsigned int ivsize;\n};\n\nstruct crypto_sync_skcipher;\n\nstruct aead_geniv_ctx {\n\tspinlock_t lock;\n\tstruct crypto_aead *child;\n\tstruct crypto_sync_skcipher *sknull;\n\tu8 salt[0];\n};\n\nstruct crypto_rng;\n\nstruct rng_alg {\n\tint (*generate)(struct crypto_rng *, const u8 *, unsigned int, u8 *, unsigned int);\n\tint (*seed)(struct crypto_rng *, const u8 *, unsigned int);\n\tvoid (*set_ent)(struct crypto_rng *, const u8 *, unsigned int);\n\tunsigned int seedsize;\n\tstruct crypto_alg base;\n};\n\nstruct crypto_rng {\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_cipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct skcipher_request {\n\tunsigned int cryptlen;\n\tu8 *iv;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tstruct crypto_async_request base;\n\tvoid *__ctx[0];\n};\n\nstruct crypto_skcipher {\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct crypto_sync_skcipher {\n\tstruct crypto_skcipher base;\n};\n\nstruct skcipher_alg {\n\tint (*setkey)(struct crypto_skcipher *, const u8 *, unsigned int);\n\tint (*encrypt)(struct skcipher_request *);\n\tint (*decrypt)(struct skcipher_request *);\n\tint (*init)(struct crypto_skcipher *);\n\tvoid (*exit)(struct crypto_skcipher *);\n\tunsigned int min_keysize;\n\tunsigned int max_keysize;\n\tunsigned int ivsize;\n\tunsigned int chunksize;\n\tunsigned int walksize;\n\tstruct crypto_alg base;\n};\n\nstruct skcipher_instance {\n\tvoid (*free)(struct skcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[64];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct skcipher_alg alg;\n\t};\n};\n\nstruct crypto_skcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct skcipher_walk {\n\tunion {\n\t\tstruct {\n\t\t\tstruct page *page;\n\t\t\tlong unsigned int offset;\n\t\t} phys;\n\t\tstruct {\n\t\t\tu8 *page;\n\t\t\tvoid *addr;\n\t\t} virt;\n\t} src;\n\tunion {\n\t\tstruct {\n\t\t\tstruct page *page;\n\t\t\tlong unsigned int offset;\n\t\t} phys;\n\t\tstruct {\n\t\t\tu8 *page;\n\t\t\tvoid *addr;\n\t\t} virt;\n\t} dst;\n\tstruct scatter_walk in;\n\tunsigned int nbytes;\n\tstruct scatter_walk out;\n\tunsigned int total;\n\tstruct list_head buffers;\n\tu8 *page;\n\tu8 *buffer;\n\tu8 *oiv;\n\tvoid *iv;\n\tunsigned int ivsize;\n\tint flags;\n\tunsigned int blocksize;\n\tunsigned int stride;\n\tunsigned int alignmask;\n};\n\nstruct skcipher_ctx_simple {\n\tstruct crypto_cipher *cipher;\n};\n\nstruct crypto_report_blkcipher {\n\tchar type[64];\n\tchar geniv[64];\n\tunsigned int blocksize;\n\tunsigned int min_keysize;\n\tunsigned int max_keysize;\n\tunsigned int ivsize;\n};\n\nenum {\n\tSKCIPHER_WALK_PHYS = 1,\n\tSKCIPHER_WALK_SLOW = 2,\n\tSKCIPHER_WALK_COPY = 4,\n\tSKCIPHER_WALK_DIFF = 8,\n\tSKCIPHER_WALK_SLEEP = 16,\n};\n\nstruct skcipher_walk_buffer {\n\tstruct list_head entry;\n\tstruct scatter_walk dst;\n\tunsigned int len;\n\tu8 *data;\n\tu8 buffer[0];\n};\n\nstruct hash_alg_common {\n\tunsigned int digestsize;\n\tunsigned int statesize;\n\tstruct crypto_alg base;\n};\n\nstruct ahash_request {\n\tstruct crypto_async_request base;\n\tunsigned int nbytes;\n\tstruct scatterlist *src;\n\tu8 *result;\n\tvoid *priv;\n\tvoid *__ctx[0];\n};\n\nstruct crypto_ahash;\n\nstruct ahash_alg {\n\tint (*init)(struct ahash_request *);\n\tint (*update)(struct ahash_request *);\n\tint (*final)(struct ahash_request *);\n\tint (*finup)(struct ahash_request *);\n\tint (*digest)(struct ahash_request *);\n\tint (*export)(struct ahash_request *, void *);\n\tint (*import)(struct ahash_request *, const void *);\n\tint (*setkey)(struct crypto_ahash *, const u8 *, unsigned int);\n\tstruct hash_alg_common halg;\n};\n\nstruct crypto_ahash {\n\tint (*init)(struct ahash_request *);\n\tint (*update)(struct ahash_request *);\n\tint (*final)(struct ahash_request *);\n\tint (*finup)(struct ahash_request *);\n\tint (*digest)(struct ahash_request *);\n\tint (*export)(struct ahash_request *, void *);\n\tint (*import)(struct ahash_request *, const void *);\n\tint (*setkey)(struct crypto_ahash *, const u8 *, unsigned int);\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct shash_alg {\n\tint (*init)(struct shash_desc *);\n\tint (*update)(struct shash_desc *, const u8 *, unsigned int);\n\tint (*final)(struct shash_desc *, u8 *);\n\tint (*finup)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*digest)(struct shash_desc *, const u8 *, unsigned int, u8 *);\n\tint (*export)(struct shash_desc *, void *);\n\tint (*import)(struct shash_desc *, const void *);\n\tint (*setkey)(struct crypto_shash *, const u8 *, unsigned int);\n\tint (*init_tfm)(struct crypto_shash *);\n\tvoid (*exit_tfm)(struct crypto_shash *);\n\tunsigned int descsize;\n\tint: 32;\n\tunsigned int digestsize;\n\tunsigned int statesize;\n\tstruct crypto_alg base;\n};\n\nstruct crypto_hash_walk {\n\tchar *data;\n\tunsigned int offset;\n\tunsigned int alignmask;\n\tstruct page *pg;\n\tunsigned int entrylen;\n\tunsigned int total;\n\tstruct scatterlist *sg;\n\tunsigned int flags;\n};\n\nstruct ahash_instance {\n\tvoid (*free)(struct ahash_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[72];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct ahash_alg alg;\n\t};\n};\n\nstruct crypto_ahash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_report_hash {\n\tchar type[64];\n\tunsigned int blocksize;\n\tunsigned int digestsize;\n};\n\nstruct ahash_request_priv {\n\tcrypto_completion_t complete;\n\tvoid *data;\n\tu8 *result;\n\tu32 flags;\n\tvoid *ubuf[0];\n};\n\nstruct shash_instance {\n\tvoid (*free)(struct shash_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[96];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct shash_alg alg;\n\t};\n};\n\nstruct crypto_shash_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_report_akcipher {\n\tchar type[64];\n};\n\nstruct akcipher_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tvoid *__ctx[0];\n};\n\nstruct crypto_akcipher {\n\tstruct crypto_tfm base;\n};\n\nstruct akcipher_alg {\n\tint (*sign)(struct akcipher_request *);\n\tint (*verify)(struct akcipher_request *);\n\tint (*encrypt)(struct akcipher_request *);\n\tint (*decrypt)(struct akcipher_request *);\n\tint (*set_pub_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tint (*set_priv_key)(struct crypto_akcipher *, const void *, unsigned int);\n\tunsigned int (*max_size)(struct crypto_akcipher *);\n\tint (*init)(struct crypto_akcipher *);\n\tvoid (*exit)(struct crypto_akcipher *);\n\tunsigned int reqsize;\n\tstruct crypto_alg base;\n};\n\nstruct akcipher_instance {\n\tvoid (*free)(struct akcipher_instance *);\n\tunion {\n\t\tstruct {\n\t\t\tchar head[80];\n\t\t\tstruct crypto_instance base;\n\t\t} s;\n\t\tstruct akcipher_alg alg;\n\t};\n};\n\nstruct crypto_akcipher_spawn {\n\tstruct crypto_spawn base;\n};\n\nstruct crypto_report_kpp {\n\tchar type[64];\n};\n\nstruct kpp_request {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int src_len;\n\tunsigned int dst_len;\n\tvoid *__ctx[0];\n};\n\nstruct crypto_kpp {\n\tstruct crypto_tfm base;\n};\n\nstruct kpp_alg {\n\tint (*set_secret)(struct crypto_kpp *, const void *, unsigned int);\n\tint (*generate_public_key)(struct kpp_request *);\n\tint (*compute_shared_secret)(struct kpp_request *);\n\tunsigned int (*max_size)(struct crypto_kpp *);\n\tint (*init)(struct crypto_kpp *);\n\tvoid (*exit)(struct crypto_kpp *);\n\tunsigned int reqsize;\n\tstruct crypto_alg base;\n};\n\nenum asn1_class {\n\tASN1_UNIV = 0,\n\tASN1_APPL = 1,\n\tASN1_CONT = 2,\n\tASN1_PRIV = 3,\n};\n\nenum asn1_method {\n\tASN1_PRIM = 0,\n\tASN1_CONS = 1,\n};\n\nenum asn1_tag {\n\tASN1_EOC = 0,\n\tASN1_BOOL = 1,\n\tASN1_INT = 2,\n\tASN1_BTS = 3,\n\tASN1_OTS = 4,\n\tASN1_NULL = 5,\n\tASN1_OID = 6,\n\tASN1_ODE = 7,\n\tASN1_EXT = 8,\n\tASN1_REAL = 9,\n\tASN1_ENUM = 10,\n\tASN1_EPDV = 11,\n\tASN1_UTF8STR = 12,\n\tASN1_RELOID = 13,\n\tASN1_SEQ = 16,\n\tASN1_SET = 17,\n\tASN1_NUMSTR = 18,\n\tASN1_PRNSTR = 19,\n\tASN1_TEXSTR = 20,\n\tASN1_VIDSTR = 21,\n\tASN1_IA5STR = 22,\n\tASN1_UNITIM = 23,\n\tASN1_GENTIM = 24,\n\tASN1_GRASTR = 25,\n\tASN1_VISSTR = 26,\n\tASN1_GENSTR = 27,\n\tASN1_UNISTR = 28,\n\tASN1_CHRSTR = 29,\n\tASN1_BMPSTR = 30,\n\tASN1_LONG_TAG = 31,\n};\n\ntypedef int (*asn1_action_t)(void *, size_t, unsigned char, const void *, size_t);\n\nstruct asn1_decoder {\n\tconst unsigned char *machine;\n\tsize_t machlen;\n\tconst asn1_action_t *actions;\n};\n\nenum asn1_opcode {\n\tASN1_OP_MATCH = 0,\n\tASN1_OP_MATCH_OR_SKIP = 1,\n\tASN1_OP_MATCH_ACT = 2,\n\tASN1_OP_MATCH_ACT_OR_SKIP = 3,\n\tASN1_OP_MATCH_JUMP = 4,\n\tASN1_OP_MATCH_JUMP_OR_SKIP = 5,\n\tASN1_OP_MATCH_ANY = 8,\n\tASN1_OP_MATCH_ANY_OR_SKIP = 9,\n\tASN1_OP_MATCH_ANY_ACT = 10,\n\tASN1_OP_MATCH_ANY_ACT_OR_SKIP = 11,\n\tASN1_OP_COND_MATCH_OR_SKIP = 17,\n\tASN1_OP_COND_MATCH_ACT_OR_SKIP = 19,\n\tASN1_OP_COND_MATCH_JUMP_OR_SKIP = 21,\n\tASN1_OP_COND_MATCH_ANY = 24,\n\tASN1_OP_COND_MATCH_ANY_OR_SKIP = 25,\n\tASN1_OP_COND_MATCH_ANY_ACT = 26,\n\tASN1_OP_COND_MATCH_ANY_ACT_OR_SKIP = 27,\n\tASN1_OP_COND_FAIL = 28,\n\tASN1_OP_COMPLETE = 29,\n\tASN1_OP_ACT = 30,\n\tASN1_OP_MAYBE_ACT = 31,\n\tASN1_OP_END_SEQ = 32,\n\tASN1_OP_END_SET = 33,\n\tASN1_OP_END_SEQ_OF = 34,\n\tASN1_OP_END_SET_OF = 35,\n\tASN1_OP_END_SEQ_ACT = 36,\n\tASN1_OP_END_SET_ACT = 37,\n\tASN1_OP_END_SEQ_OF_ACT = 38,\n\tASN1_OP_END_SET_OF_ACT = 39,\n\tASN1_OP_RETURN = 40,\n\tASN1_OP__NR = 41,\n};\n\nenum rsapubkey_actions {\n\tACT_rsa_get_e = 0,\n\tACT_rsa_get_n = 1,\n\tNR__rsapubkey_actions = 2,\n};\n\nenum rsaprivkey_actions {\n\tACT_rsa_get_d = 0,\n\tACT_rsa_get_dp = 1,\n\tACT_rsa_get_dq = 2,\n\tACT_rsa_get_e___2 = 3,\n\tACT_rsa_get_n___2 = 4,\n\tACT_rsa_get_p = 5,\n\tACT_rsa_get_q = 6,\n\tACT_rsa_get_qinv = 7,\n\tNR__rsaprivkey_actions = 8,\n};\n\ntypedef long unsigned int mpi_limb_t;\n\nstruct gcry_mpi {\n\tint alloced;\n\tint nlimbs;\n\tint nbits;\n\tint sign;\n\tunsigned int flags;\n\tmpi_limb_t *d;\n};\n\ntypedef struct gcry_mpi *MPI;\n\nstruct rsa_key {\n\tconst u8 *n;\n\tconst u8 *e;\n\tconst u8 *d;\n\tconst u8 *p;\n\tconst u8 *q;\n\tconst u8 *dp;\n\tconst u8 *dq;\n\tconst u8 *qinv;\n\tsize_t n_sz;\n\tsize_t e_sz;\n\tsize_t d_sz;\n\tsize_t p_sz;\n\tsize_t q_sz;\n\tsize_t dp_sz;\n\tsize_t dq_sz;\n\tsize_t qinv_sz;\n};\n\nstruct rsa_mpi_key {\n\tMPI n;\n\tMPI e;\n\tMPI d;\n};\n\nstruct crypto_template___2;\n\nstruct asn1_decoder___2;\n\nstruct rsa_asn1_template {\n\tconst char *name;\n\tconst u8 *data;\n\tsize_t size;\n};\n\nstruct pkcs1pad_ctx {\n\tstruct crypto_akcipher *child;\n\tunsigned int key_size;\n};\n\nstruct pkcs1pad_inst_ctx {\n\tstruct crypto_akcipher_spawn spawn;\n\tconst struct rsa_asn1_template *digest_info;\n};\n\nstruct pkcs1pad_request {\n\tstruct scatterlist in_sg[2];\n\tstruct scatterlist out_sg[1];\n\tuint8_t *in_buf;\n\tuint8_t *out_buf;\n\tstruct akcipher_request child_req;\n};\n\nstruct crypto_report_acomp {\n\tchar type[64];\n};\n\nstruct acomp_req {\n\tstruct crypto_async_request base;\n\tstruct scatterlist *src;\n\tstruct scatterlist *dst;\n\tunsigned int slen;\n\tunsigned int dlen;\n\tu32 flags;\n\tvoid *__ctx[0];\n};\n\nstruct crypto_acomp {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tvoid (*dst_free)(struct scatterlist *);\n\tunsigned int reqsize;\n\tstruct crypto_tfm base;\n};\n\nstruct acomp_alg {\n\tint (*compress)(struct acomp_req *);\n\tint (*decompress)(struct acomp_req *);\n\tvoid (*dst_free)(struct scatterlist *);\n\tint (*init)(struct crypto_acomp *);\n\tvoid (*exit)(struct crypto_acomp *);\n\tunsigned int reqsize;\n\tstruct crypto_alg base;\n};\n\nstruct crypto_report_comp {\n\tchar type[64];\n};\n\nstruct crypto_scomp {\n\tstruct crypto_tfm base;\n};\n\nstruct scomp_alg {\n\tvoid * (*alloc_ctx)(struct crypto_scomp *);\n\tvoid (*free_ctx)(struct crypto_scomp *, void *);\n\tint (*compress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tint (*decompress)(struct crypto_scomp *, const u8 *, unsigned int, u8 *, unsigned int *, void *);\n\tstruct crypto_alg base;\n};\n\nstruct scomp_scratch {\n\tspinlock_t lock;\n\tvoid *src;\n\tvoid *dst;\n};\n\nstruct cryptomgr_param {\n\tstruct rtattr *tb[34];\n\tstruct {\n\t\tstruct rtattr attr;\n\t\tstruct crypto_attr_type data;\n\t} type;\n\tunion {\n\t\tstruct rtattr attr;\n\t\tstruct {\n\t\t\tstruct rtattr attr;\n\t\t\tstruct crypto_attr_alg data;\n\t\t} alg;\n\t\tstruct {\n\t\t\tstruct rtattr attr;\n\t\t\tstruct crypto_attr_u32 data;\n\t\t} nu32;\n\t} attrs[32];\n\tchar template[128];\n\tstruct crypto_larval *larval;\n\tu32 otype;\n\tu32 omask;\n};\n\nstruct crypto_test_param {\n\tchar driver[128];\n\tchar alg[128];\n\tu32 type;\n};\n\nstruct cmac_tfm_ctx {\n\tstruct crypto_cipher *child;\n\tu8 ctx[0];\n};\n\nstruct cmac_desc_ctx {\n\tunsigned int len;\n\tu8 ctx[0];\n};\n\nstruct hmac_ctx {\n\tstruct crypto_shash *hash;\n};\n\nstruct md5_state {\n\tu32 hash[4];\n\tu32 block[16];\n\tu64 byte_count;\n};\n\nstruct sha1_state {\n\tu32 state[5];\n\tu64 count;\n\tu8 buffer[64];\n};\n\ntypedef void sha1_block_fn(struct sha1_state *, const u8 *, int);\n\nstruct sha256_state {\n\tu32 state[8];\n\tu64 count;\n\tu8 buf[64];\n};\n\ntypedef struct {\n\tu64 a;\n\tu64 b;\n} u128;\n\ntypedef struct {\n\t__be64 a;\n\t__be64 b;\n} be128;\n\ntypedef struct {\n\t__le64 b;\n\t__le64 a;\n} le128;\n\nstruct gf128mul_4k {\n\tbe128 t[256];\n};\n\nstruct gf128mul_64k {\n\tstruct gf128mul_4k *t[16];\n};\n\nstruct crypto_rfc3686_ctx {\n\tstruct crypto_skcipher *child;\n\tu8 nonce[4];\n};\n\nstruct crypto_rfc3686_req_ctx {\n\tu8 iv[16];\n\tstruct skcipher_request subreq;\n};\n\nstruct gcm_instance_ctx {\n\tstruct crypto_skcipher_spawn ctr;\n\tstruct crypto_ahash_spawn ghash;\n};\n\nstruct crypto_gcm_ctx {\n\tstruct crypto_skcipher *ctr;\n\tstruct crypto_ahash *ghash;\n};\n\nstruct crypto_rfc4106_ctx {\n\tstruct crypto_aead *child;\n\tu8 nonce[4];\n};\n\nstruct crypto_rfc4106_req_ctx {\n\tstruct scatterlist src[3];\n\tstruct scatterlist dst[3];\n\tstruct aead_request subreq;\n};\n\nstruct crypto_rfc4543_instance_ctx {\n\tstruct crypto_aead_spawn aead;\n};\n\nstruct crypto_rfc4543_ctx {\n\tstruct crypto_aead *child;\n\tstruct crypto_sync_skcipher *null;\n\tu8 nonce[4];\n};\n\nstruct crypto_rfc4543_req_ctx {\n\tstruct aead_request subreq;\n};\n\nstruct crypto_gcm_ghash_ctx {\n\tunsigned int cryptlen;\n\tstruct scatterlist *src;\n\tint (*complete)(struct aead_request *, u32);\n};\n\nstruct crypto_gcm_req_priv_ctx {\n\tu8 iv[16];\n\tu8 auth_tag[16];\n\tu8 iauth_tag[16];\n\tstruct scatterlist src[3];\n\tstruct scatterlist dst[3];\n\tstruct scatterlist sg;\n\tstruct crypto_gcm_ghash_ctx ghash_ctx;\n\tunion {\n\t\tstruct ahash_request ahreq;\n\t\tstruct skcipher_request skreq;\n\t} u;\n};\n\nstruct ccm_instance_ctx {\n\tstruct crypto_skcipher_spawn ctr;\n\tstruct crypto_ahash_spawn mac;\n};\n\nstruct crypto_ccm_ctx {\n\tstruct crypto_ahash *mac;\n\tstruct crypto_skcipher *ctr;\n};\n\nstruct crypto_rfc4309_ctx {\n\tstruct crypto_aead *child;\n\tu8 nonce[3];\n};\n\nstruct crypto_rfc4309_req_ctx {\n\tstruct scatterlist src[3];\n\tstruct scatterlist dst[3];\n\tstruct aead_request subreq;\n};\n\nstruct crypto_ccm_req_priv_ctx {\n\tu8 odata[16];\n\tu8 idata[16];\n\tu8 auth_tag[16];\n\tu32 flags;\n\tstruct scatterlist src[3];\n\tstruct scatterlist dst[3];\n\tunion {\n\t\tstruct ahash_request ahreq;\n\t\tstruct skcipher_request skreq;\n\t};\n};\n\nstruct cbcmac_tfm_ctx {\n\tstruct crypto_cipher *child;\n};\n\nstruct cbcmac_desc_ctx {\n\tunsigned int len;\n};\n\nstruct des_ctx {\n\tu32 expkey[32];\n};\n\nstruct des3_ede_ctx {\n\tu32 expkey[96];\n};\n\nstruct crypto_aes_ctx {\n\tu32 key_enc[60];\n\tu32 key_dec[60];\n\tu32 key_length;\n};\n\nstruct chksum_ctx {\n\tu32 key;\n};\n\nstruct chksum_desc_ctx {\n\tu32 crc;\n};\n\nenum {\n\tCRYPTO_AUTHENC_KEYA_UNSPEC = 0,\n\tCRYPTO_AUTHENC_KEYA_PARAM = 1,\n};\n\nstruct crypto_authenc_key_param {\n\t__be32 enckeylen;\n};\n\nstruct crypto_authenc_keys {\n\tconst u8 *authkey;\n\tconst u8 *enckey;\n\tunsigned int authkeylen;\n\tunsigned int enckeylen;\n};\n\nstruct authenc_instance_ctx {\n\tstruct crypto_ahash_spawn auth;\n\tstruct crypto_skcipher_spawn enc;\n\tunsigned int reqoff;\n};\n\nstruct crypto_authenc_ctx {\n\tstruct crypto_ahash *auth;\n\tstruct crypto_skcipher *enc;\n\tstruct crypto_sync_skcipher *null;\n};\n\nstruct authenc_request_ctx {\n\tstruct scatterlist src[2];\n\tstruct scatterlist dst[2];\n\tchar tail[0];\n};\n\nstruct authenc_esn_instance_ctx {\n\tstruct crypto_ahash_spawn auth;\n\tstruct crypto_skcipher_spawn enc;\n};\n\nstruct crypto_authenc_esn_ctx {\n\tunsigned int reqoff;\n\tstruct crypto_ahash *auth;\n\tstruct crypto_skcipher *enc;\n\tstruct crypto_sync_skcipher *null;\n};\n\nstruct authenc_esn_request_ctx {\n\tstruct scatterlist src[2];\n\tstruct scatterlist dst[2];\n\tchar tail[0];\n};\n\nstruct crypto_report_rng {\n\tchar type[64];\n\tunsigned int seedsize;\n};\n\nstruct random_ready_callback {\n\tstruct list_head list;\n\tvoid (*func)(struct random_ready_callback *);\n\tstruct module *owner;\n};\n\nstruct drbg_string {\n\tconst unsigned char *buf;\n\tsize_t len;\n\tstruct list_head list;\n};\n\ntypedef uint32_t drbg_flag_t;\n\nstruct drbg_core {\n\tdrbg_flag_t flags;\n\t__u8 statelen;\n\t__u8 blocklen_bytes;\n\tchar cra_name[128];\n\tchar backend_cra_name[128];\n};\n\nstruct drbg_state;\n\nstruct drbg_state_ops {\n\tint (*update)(struct drbg_state *, struct list_head *, int);\n\tint (*generate)(struct drbg_state *, unsigned char *, unsigned int, struct list_head *);\n\tint (*crypto_init)(struct drbg_state *);\n\tint (*crypto_fini)(struct drbg_state *);\n};\n\nstruct drbg_state {\n\tstruct mutex drbg_mutex;\n\tunsigned char *V;\n\tunsigned char *Vbuf;\n\tunsigned char *C;\n\tunsigned char *Cbuf;\n\tsize_t reseed_ctr;\n\tsize_t reseed_threshold;\n\tunsigned char *scratchpad;\n\tunsigned char *scratchpadbuf;\n\tvoid *priv_data;\n\tstruct crypto_skcipher *ctr_handle;\n\tstruct skcipher_request *ctr_req;\n\t__u8 *outscratchpadbuf;\n\t__u8 *outscratchpad;\n\tstruct crypto_wait ctr_wait;\n\tstruct scatterlist sg_in;\n\tstruct scatterlist sg_out;\n\tbool seeded;\n\tbool pr;\n\tbool fips_primed;\n\tunsigned char *prev;\n\tstruct work_struct seed_work;\n\tstruct crypto_rng *jent;\n\tconst struct drbg_state_ops *d_ops;\n\tconst struct drbg_core *core;\n\tstruct drbg_string test_data;\n\tstruct random_ready_callback random_ready;\n};\n\nenum drbg_prefixes {\n\tDRBG_PREFIX0 = 0,\n\tDRBG_PREFIX1 = 1,\n\tDRBG_PREFIX2 = 2,\n\tDRBG_PREFIX3 = 3,\n};\n\nstruct sdesc {\n\tstruct shash_desc shash;\n\tchar ctx[0];\n};\n\nstruct rand_data {\n\t__u64 data;\n\t__u64 old_data;\n\t__u64 prev_time;\n\t__u64 last_delta;\n\t__s64 last_delta2;\n\tunsigned int osr;\n\tunsigned char *mem;\n\tunsigned int memlocation;\n\tunsigned int memblocks;\n\tunsigned int memblocksize;\n\tunsigned int memaccessloops;\n\tint rct_count;\n\tunsigned int apt_observations;\n\tunsigned int apt_count;\n\tunsigned int apt_base;\n\tunsigned int apt_base_set: 1;\n\tunsigned int health_failure: 1;\n};\n\nstruct rand_data___2;\n\nstruct jitterentropy {\n\tspinlock_t jent_lock;\n\tstruct rand_data___2 *entropy_collector;\n\tunsigned int reset_cnt;\n};\n\nstruct ghash_ctx {\n\tstruct gf128mul_4k *gf128;\n};\n\nstruct ghash_desc_ctx {\n\tu8 buffer[16];\n\tu32 bytes;\n};\n\nenum asymmetric_payload_bits {\n\tasym_crypto = 0,\n\tasym_subtype = 1,\n\tasym_key_ids = 2,\n\tasym_auth = 3,\n};\n\nstruct asymmetric_key_id {\n\tshort unsigned int len;\n\tunsigned char data[0];\n};\n\nstruct asymmetric_key_ids {\n\tvoid *id[2];\n};\n\nstruct public_key_signature;\n\nstruct asymmetric_key_subtype___2 {\n\tstruct module *owner;\n\tconst char *name;\n\tshort unsigned int name_len;\n\tvoid (*describe)(const struct key *, struct seq_file *);\n\tvoid (*destroy)(void *, void *);\n\tint (*query)(const struct kernel_pkey_params *, struct kernel_pkey_query *);\n\tint (*eds_op)(struct kernel_pkey_params *, const void *, void *);\n\tint (*verify_signature)(const struct key *, const struct public_key_signature *);\n};\n\nstruct public_key_signature {\n\tstruct asymmetric_key_id *auth_ids[2];\n\tu8 *s;\n\tu32 s_size;\n\tu8 *digest;\n\tu8 digest_size;\n\tconst char *pkey_algo;\n\tconst char *hash_algo;\n\tconst char *encoding;\n};\n\nstruct asymmetric_key_parser {\n\tstruct list_head link;\n\tstruct module *owner;\n\tconst char *name;\n\tint (*parse)(struct key_preparsed_payload *);\n};\n\nenum OID {\n\tOID_id_dsa_with_sha1 = 0,\n\tOID_id_dsa = 1,\n\tOID_id_ecdsa_with_sha1 = 2,\n\tOID_id_ecPublicKey = 3,\n\tOID_rsaEncryption = 4,\n\tOID_md2WithRSAEncryption = 5,\n\tOID_md3WithRSAEncryption = 6,\n\tOID_md4WithRSAEncryption = 7,\n\tOID_sha1WithRSAEncryption = 8,\n\tOID_sha256WithRSAEncryption = 9,\n\tOID_sha384WithRSAEncryption = 10,\n\tOID_sha512WithRSAEncryption = 11,\n\tOID_sha224WithRSAEncryption = 12,\n\tOID_data = 13,\n\tOID_signed_data = 14,\n\tOID_email_address = 15,\n\tOID_contentType = 16,\n\tOID_messageDigest = 17,\n\tOID_signingTime = 18,\n\tOID_smimeCapabilites = 19,\n\tOID_smimeAuthenticatedAttrs = 20,\n\tOID_md2 = 21,\n\tOID_md4 = 22,\n\tOID_md5 = 23,\n\tOID_msIndirectData = 24,\n\tOID_msStatementType = 25,\n\tOID_msSpOpusInfo = 26,\n\tOID_msPeImageDataObjId = 27,\n\tOID_msIndividualSPKeyPurpose = 28,\n\tOID_msOutlookExpress = 29,\n\tOID_certAuthInfoAccess = 30,\n\tOID_sha1 = 31,\n\tOID_sha256 = 32,\n\tOID_sha384 = 33,\n\tOID_sha512 = 34,\n\tOID_sha224 = 35,\n\tOID_commonName = 36,\n\tOID_surname = 37,\n\tOID_countryName = 38,\n\tOID_locality = 39,\n\tOID_stateOrProvinceName = 40,\n\tOID_organizationName = 41,\n\tOID_organizationUnitName = 42,\n\tOID_title = 43,\n\tOID_description = 44,\n\tOID_name = 45,\n\tOID_givenName = 46,\n\tOID_initials = 47,\n\tOID_generationalQualifier = 48,\n\tOID_subjectKeyIdentifier = 49,\n\tOID_keyUsage = 50,\n\tOID_subjectAltName = 51,\n\tOID_issuerAltName = 52,\n\tOID_basicConstraints = 53,\n\tOID_crlDistributionPoints = 54,\n\tOID_certPolicies = 55,\n\tOID_authorityKeyIdentifier = 56,\n\tOID_extKeyUsage = 57,\n\tOID_gostCPSignA = 58,\n\tOID_gostCPSignB = 59,\n\tOID_gostCPSignC = 60,\n\tOID_gost2012PKey256 = 61,\n\tOID_gost2012PKey512 = 62,\n\tOID_gost2012Digest256 = 63,\n\tOID_gost2012Digest512 = 64,\n\tOID_gost2012Signature256 = 65,\n\tOID_gost2012Signature512 = 66,\n\tOID_gostTC26Sign256A = 67,\n\tOID_gostTC26Sign256B = 68,\n\tOID_gostTC26Sign256C = 69,\n\tOID_gostTC26Sign256D = 70,\n\tOID_gostTC26Sign512A = 71,\n\tOID_gostTC26Sign512B = 72,\n\tOID_gostTC26Sign512C = 73,\n\tOID__NR = 74,\n};\n\nstruct public_key {\n\tvoid *key;\n\tu32 keylen;\n\tenum OID algo;\n\tvoid *params;\n\tu32 paramlen;\n\tbool key_is_private;\n\tconst char *id_type;\n\tconst char *pkey_algo;\n};\n\nenum x509_actions {\n\tACT_x509_extract_key_data = 0,\n\tACT_x509_extract_name_segment = 1,\n\tACT_x509_note_OID = 2,\n\tACT_x509_note_issuer = 3,\n\tACT_x509_note_not_after = 4,\n\tACT_x509_note_not_before = 5,\n\tACT_x509_note_params = 6,\n\tACT_x509_note_pkey_algo = 7,\n\tACT_x509_note_serial = 8,\n\tACT_x509_note_signature = 9,\n\tACT_x509_note_subject = 10,\n\tACT_x509_note_tbs_certificate = 11,\n\tACT_x509_process_extension = 12,\n\tNR__x509_actions = 13,\n};\n\nenum x509_akid_actions {\n\tACT_x509_akid_note_kid = 0,\n\tACT_x509_akid_note_name = 1,\n\tACT_x509_akid_note_serial = 2,\n\tACT_x509_extract_name_segment___2 = 3,\n\tACT_x509_note_OID___2 = 4,\n\tNR__x509_akid_actions = 5,\n};\n\nstruct x509_certificate {\n\tstruct x509_certificate *next;\n\tstruct x509_certificate *signer;\n\tstruct public_key *pub;\n\tstruct public_key_signature *sig;\n\tchar *issuer;\n\tchar *subject;\n\tstruct asymmetric_key_id *id;\n\tstruct asymmetric_key_id *skid;\n\ttime64_t valid_from;\n\ttime64_t valid_to;\n\tconst void *tbs;\n\tunsigned int tbs_size;\n\tunsigned int raw_sig_size;\n\tconst void *raw_sig;\n\tconst void *raw_serial;\n\tunsigned int raw_serial_size;\n\tunsigned int raw_issuer_size;\n\tconst void *raw_issuer;\n\tconst void *raw_subject;\n\tunsigned int raw_subject_size;\n\tunsigned int raw_skid_size;\n\tconst void *raw_skid;\n\tunsigned int index;\n\tbool seen;\n\tbool verified;\n\tbool self_signed;\n\tbool unsupported_key;\n\tbool unsupported_sig;\n\tbool blacklisted;\n};\n\nstruct x509_parse_context {\n\tstruct x509_certificate *cert;\n\tlong unsigned int data;\n\tconst void *cert_start;\n\tconst void *key;\n\tsize_t key_size;\n\tconst void *params;\n\tsize_t params_size;\n\tenum OID key_algo;\n\tenum OID last_oid;\n\tenum OID algo_oid;\n\tunsigned char nr_mpi;\n\tu8 o_size;\n\tu8 cn_size;\n\tu8 email_size;\n\tu16 o_offset;\n\tu16 cn_offset;\n\tu16 email_offset;\n\tunsigned int raw_akid_size;\n\tconst void *raw_akid;\n\tconst void *akid_raw_issuer;\n\tunsigned int akid_raw_issuer_size;\n};\n\nenum pkcs7_actions {\n\tACT_pkcs7_check_content_type = 0,\n\tACT_pkcs7_extract_cert = 1,\n\tACT_pkcs7_note_OID = 2,\n\tACT_pkcs7_note_certificate_list = 3,\n\tACT_pkcs7_note_content = 4,\n\tACT_pkcs7_note_data = 5,\n\tACT_pkcs7_note_signed_info = 6,\n\tACT_pkcs7_note_signeddata_version = 7,\n\tACT_pkcs7_note_signerinfo_version = 8,\n\tACT_pkcs7_sig_note_authenticated_attr = 9,\n\tACT_pkcs7_sig_note_digest_algo = 10,\n\tACT_pkcs7_sig_note_issuer = 11,\n\tACT_pkcs7_sig_note_pkey_algo = 12,\n\tACT_pkcs7_sig_note_serial = 13,\n\tACT_pkcs7_sig_note_set_of_authattrs = 14,\n\tACT_pkcs7_sig_note_signature = 15,\n\tACT_pkcs7_sig_note_skid = 16,\n\tNR__pkcs7_actions = 17,\n};\n\nstruct pkcs7_signed_info {\n\tstruct pkcs7_signed_info *next;\n\tstruct x509_certificate *signer;\n\tunsigned int index;\n\tbool unsupported_crypto;\n\tbool blacklisted;\n\tconst void *msgdigest;\n\tunsigned int msgdigest_len;\n\tunsigned int authattrs_len;\n\tconst void *authattrs;\n\tlong unsigned int aa_set;\n\ttime64_t signing_time;\n\tstruct public_key_signature *sig;\n};\n\nstruct pkcs7_message___2 {\n\tstruct x509_certificate *certs;\n\tstruct x509_certificate *crl;\n\tstruct pkcs7_signed_info *signed_infos;\n\tu8 version;\n\tbool have_authattrs;\n\tenum OID data_type;\n\tsize_t data_len;\n\tsize_t data_hdrlen;\n\tconst void *data;\n};\n\nstruct pkcs7_parse_context {\n\tstruct pkcs7_message___2 *msg;\n\tstruct pkcs7_signed_info *sinfo;\n\tstruct pkcs7_signed_info **ppsinfo;\n\tstruct x509_certificate *certs;\n\tstruct x509_certificate **ppcerts;\n\tlong unsigned int data;\n\tenum OID last_oid;\n\tunsigned int x509_index;\n\tunsigned int sinfo_index;\n\tconst void *raw_serial;\n\tunsigned int raw_serial_size;\n\tunsigned int raw_issuer_size;\n\tconst void *raw_issuer;\n\tconst void *raw_skid;\n\tunsigned int raw_skid_size;\n\tbool expect_skid;\n};\n\nenum hash_algo {\n\tHASH_ALGO_MD4 = 0,\n\tHASH_ALGO_MD5 = 1,\n\tHASH_ALGO_SHA1 = 2,\n\tHASH_ALGO_RIPE_MD_160 = 3,\n\tHASH_ALGO_SHA256 = 4,\n\tHASH_ALGO_SHA384 = 5,\n\tHASH_ALGO_SHA512 = 6,\n\tHASH_ALGO_SHA224 = 7,\n\tHASH_ALGO_RIPE_MD_128 = 8,\n\tHASH_ALGO_RIPE_MD_256 = 9,\n\tHASH_ALGO_RIPE_MD_320 = 10,\n\tHASH_ALGO_WP_256 = 11,\n\tHASH_ALGO_WP_384 = 12,\n\tHASH_ALGO_WP_512 = 13,\n\tHASH_ALGO_TGR_128 = 14,\n\tHASH_ALGO_TGR_160 = 15,\n\tHASH_ALGO_TGR_192 = 16,\n\tHASH_ALGO_SM3_256 = 17,\n\tHASH_ALGO_STREEBOG_256 = 18,\n\tHASH_ALGO_STREEBOG_512 = 19,\n\tHASH_ALGO__LAST = 20,\n};\n\nstruct biovec_slab {\n\tint nr_vecs;\n\tchar *name;\n\tstruct kmem_cache *slab;\n};\n\nenum rq_qos_id {\n\tRQ_QOS_WBT = 0,\n\tRQ_QOS_LATENCY = 1,\n\tRQ_QOS_COST = 2,\n};\n\nstruct rq_qos_ops;\n\nstruct rq_qos {\n\tstruct rq_qos_ops *ops;\n\tstruct request_queue *q;\n\tenum rq_qos_id id;\n\tstruct rq_qos *next;\n\tstruct dentry *debugfs_dir;\n};\n\nenum {\n\tsysctl_hung_task_timeout_secs = 0,\n};\n\nenum hctx_type {\n\tHCTX_TYPE_DEFAULT = 0,\n\tHCTX_TYPE_READ = 1,\n\tHCTX_TYPE_POLL = 2,\n\tHCTX_MAX_TYPES = 3,\n};\n\nstruct rq_qos_ops {\n\tvoid (*throttle)(struct rq_qos *, struct bio *);\n\tvoid (*track)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*merge)(struct rq_qos *, struct request *, struct bio *);\n\tvoid (*issue)(struct rq_qos *, struct request *);\n\tvoid (*requeue)(struct rq_qos *, struct request *);\n\tvoid (*done)(struct rq_qos *, struct request *);\n\tvoid (*done_bio)(struct rq_qos *, struct bio *);\n\tvoid (*cleanup)(struct rq_qos *, struct bio *);\n\tvoid (*queue_depth_changed)(struct rq_qos *);\n\tvoid (*exit)(struct rq_qos *);\n\tconst struct blk_mq_debugfs_attr *debugfs_attrs;\n};\n\nstruct bio_slab {\n\tstruct kmem_cache *slab;\n\tunsigned int slab_ref;\n\tunsigned int slab_size;\n\tchar name[8];\n};\n\nenum {\n\tBLK_MQ_F_SHOULD_MERGE = 1,\n\tBLK_MQ_F_TAG_SHARED = 2,\n\tBLK_MQ_F_STACKING = 4,\n\tBLK_MQ_F_BLOCKING = 32,\n\tBLK_MQ_F_NO_SCHED = 64,\n\tBLK_MQ_F_ALLOC_POLICY_START_BIT = 8,\n\tBLK_MQ_F_ALLOC_POLICY_BITS = 1,\n\tBLK_MQ_S_STOPPED = 0,\n\tBLK_MQ_S_TAG_ACTIVE = 1,\n\tBLK_MQ_S_SCHED_RESTART = 2,\n\tBLK_MQ_S_INACTIVE = 3,\n\tBLK_MQ_MAX_DEPTH = 10240,\n\tBLK_MQ_CPU_WORK_BATCH = 8,\n};\n\nenum {\n\tWBT_RWQ_BG = 0,\n\tWBT_RWQ_KSWAPD = 1,\n\tWBT_RWQ_DISCARD = 2,\n\tWBT_NUM_RWQ = 3,\n};\n\nstruct blk_plug_cb;\n\ntypedef void (*blk_plug_cb_fn)(struct blk_plug_cb *, bool);\n\nstruct blk_plug_cb {\n\tstruct list_head list;\n\tblk_plug_cb_fn callback;\n\tvoid *data;\n};\n\nenum {\n\tBLK_MQ_REQ_NOWAIT = 1,\n\tBLK_MQ_REQ_RESERVED = 2,\n\tBLK_MQ_REQ_INTERNAL = 4,\n\tBLK_MQ_REQ_PREEMPT = 8,\n};\n\nstruct trace_event_raw_block_buffer {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_requeue {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tchar rwbs[8];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tchar rwbs[8];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tunsigned int bytes;\n\tchar rwbs[8];\n\tchar comm[16];\n\tu32 __data_loc_cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_bounce {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tchar rwbs[8];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_complete {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tint error;\n\tchar rwbs[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_merge {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tchar rwbs[8];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_queue {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tchar rwbs[8];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_get_rq {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tchar rwbs[8];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_plug {\n\tstruct trace_entry ent;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_unplug {\n\tstruct trace_entry ent;\n\tint nr_rq;\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_split {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tsector_t new_sector;\n\tchar rwbs[8];\n\tchar comm[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_bio_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tchar rwbs[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_block_rq_remap {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tsector_t sector;\n\tunsigned int nr_sector;\n\tdev_t old_dev;\n\tsector_t old_sector;\n\tunsigned int nr_bios;\n\tchar rwbs[8];\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_block_buffer {};\n\nstruct trace_event_data_offsets_block_rq_requeue {\n\tu32 cmd;\n};\n\nstruct trace_event_data_offsets_block_rq_complete {\n\tu32 cmd;\n};\n\nstruct trace_event_data_offsets_block_rq {\n\tu32 cmd;\n};\n\nstruct trace_event_data_offsets_block_bio_bounce {};\n\nstruct trace_event_data_offsets_block_bio_complete {};\n\nstruct trace_event_data_offsets_block_bio_merge {};\n\nstruct trace_event_data_offsets_block_bio_queue {};\n\nstruct trace_event_data_offsets_block_get_rq {};\n\nstruct trace_event_data_offsets_block_plug {};\n\nstruct trace_event_data_offsets_block_unplug {};\n\nstruct trace_event_data_offsets_block_split {};\n\nstruct trace_event_data_offsets_block_bio_remap {};\n\nstruct trace_event_data_offsets_block_rq_remap {};\n\ntypedef void (*btf_trace_block_touch_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_dirty_buffer)(void *, struct buffer_head *);\n\ntypedef void (*btf_trace_block_rq_requeue)(void *, struct request_queue *, struct request *);\n\ntypedef void (*btf_trace_block_rq_complete)(void *, struct request *, int, unsigned int);\n\ntypedef void (*btf_trace_block_rq_insert)(void *, struct request_queue *, struct request *);\n\ntypedef void (*btf_trace_block_rq_issue)(void *, struct request_queue *, struct request *);\n\ntypedef void (*btf_trace_block_bio_bounce)(void *, struct request_queue *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_complete)(void *, struct request_queue *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_backmerge)(void *, struct request_queue *, struct request *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_frontmerge)(void *, struct request_queue *, struct request *, struct bio *);\n\ntypedef void (*btf_trace_block_bio_queue)(void *, struct request_queue *, struct bio *);\n\ntypedef void (*btf_trace_block_getrq)(void *, struct request_queue *, struct bio *, int);\n\ntypedef void (*btf_trace_block_sleeprq)(void *, struct request_queue *, struct bio *, int);\n\ntypedef void (*btf_trace_block_plug)(void *, struct request_queue *);\n\ntypedef void (*btf_trace_block_unplug)(void *, struct request_queue *, unsigned int, bool);\n\ntypedef void (*btf_trace_block_split)(void *, struct request_queue *, struct bio *, unsigned int);\n\ntypedef void (*btf_trace_block_bio_remap)(void *, struct request_queue *, struct bio *, dev_t, sector_t);\n\ntypedef void (*btf_trace_block_rq_remap)(void *, struct request_queue *, struct request *, dev_t, sector_t);\n\nstruct queue_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct request_queue *, char *);\n\tssize_t (*store)(struct request_queue *, const char *, size_t);\n};\n\nenum {\n\tBLK_MQ_NO_TAG = 4294967295,\n\tBLK_MQ_TAG_MIN = 1,\n\tBLK_MQ_TAG_MAX = 4294967294,\n};\n\nenum {\n\tREQ_FSEQ_PREFLUSH = 1,\n\tREQ_FSEQ_DATA = 2,\n\tREQ_FSEQ_POSTFLUSH = 4,\n\tREQ_FSEQ_DONE = 8,\n\tREQ_FSEQ_ACTIONS = 7,\n\tFLUSH_PENDING_TIMEOUT = 5000,\n};\n\nenum blk_default_limits {\n\tBLK_MAX_SEGMENTS = 128,\n\tBLK_SAFE_MAX_SECTORS = 255,\n\tBLK_DEF_MAX_SECTORS = 2560,\n\tBLK_MAX_SEGMENT_SIZE = 65536,\n\tBLK_SEG_BOUNDARY_MASK = 4294967295,\n};\n\nenum {\n\tICQ_EXITED = 4,\n\tICQ_DESTROYED = 8,\n};\n\nstruct rq_map_data {\n\tstruct page **pages;\n\tint page_order;\n\tint nr_entries;\n\tlong unsigned int offset;\n\tint null_mapped;\n\tint from_user;\n};\n\nstruct bio_map_data {\n\tint is_our_pages;\n\tstruct iov_iter iter;\n\tstruct iovec iov[0];\n};\n\nstruct req_iterator {\n\tstruct bvec_iter iter;\n\tstruct bio *bio;\n};\n\ntypedef bool (*sb_for_each_fn)(struct sbitmap *, unsigned int, void *);\n\nenum {\n\tBLK_MQ_UNIQUE_TAG_BITS = 16,\n\tBLK_MQ_UNIQUE_TAG_MASK = 65535,\n};\n\nstruct mq_inflight {\n\tstruct hd_struct *part;\n\tunsigned int inflight[2];\n};\n\nstruct flush_busy_ctx_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct list_head *list;\n};\n\nstruct dispatch_rq_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tstruct request *rq;\n};\n\nstruct rq_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tbool has_rq;\n};\n\nstruct blk_mq_qe_pair {\n\tstruct list_head node;\n\tstruct request_queue *q;\n\tstruct elevator_type *type;\n};\n\nstruct sbq_wait {\n\tstruct sbitmap_queue *sbq;\n\tstruct wait_queue_entry wait;\n};\n\ntypedef bool busy_iter_fn(struct blk_mq_hw_ctx *, struct request *, void *, bool);\n\ntypedef bool busy_tag_iter_fn(struct request *, void *, bool);\n\nstruct bt_iter_data {\n\tstruct blk_mq_hw_ctx *hctx;\n\tbusy_iter_fn *fn;\n\tvoid *data;\n\tbool reserved;\n};\n\nstruct bt_tags_iter_data {\n\tstruct blk_mq_tags *tags;\n\tbusy_tag_iter_fn *fn;\n\tvoid *data;\n\tunsigned int flags;\n};\n\nstruct blk_queue_stats {\n\tstruct list_head callbacks;\n\tspinlock_t lock;\n\tbool enable_accounting;\n};\n\nstruct blk_mq_ctx_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_mq_ctx *, char *);\n\tssize_t (*store)(struct blk_mq_ctx *, const char *, size_t);\n};\n\nstruct blk_mq_hw_ctx_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct blk_mq_hw_ctx *, char *);\n\tssize_t (*store)(struct blk_mq_hw_ctx *, const char *, size_t);\n};\n\ntypedef u32 compat_caddr_t;\n\nstruct hd_geometry {\n\tunsigned char heads;\n\tunsigned char sectors;\n\tshort unsigned int cylinders;\n\tlong unsigned int start;\n};\n\nstruct blkpg_ioctl_arg {\n\tint op;\n\tint flags;\n\tint datalen;\n\tvoid *data;\n};\n\nstruct blkpg_partition {\n\tlong long int start;\n\tlong long int length;\n\tint pno;\n\tchar devname[64];\n\tchar volname[64];\n};\n\nstruct pr_reservation {\n\t__u64 key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct pr_registration {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct pr_preempt {\n\t__u64 old_key;\n\t__u64 new_key;\n\t__u32 type;\n\t__u32 flags;\n};\n\nstruct pr_clear {\n\t__u64 key;\n\t__u32 flags;\n\t__u32 __pad;\n};\n\nstruct compat_blkpg_ioctl_arg {\n\tcompat_int_t op;\n\tcompat_int_t flags;\n\tcompat_int_t datalen;\n\tcompat_caddr_t data;\n};\n\nstruct compat_hd_geometry {\n\tunsigned char heads;\n\tunsigned char sectors;\n\tshort unsigned int cylinders;\n\tu32 start;\n};\n\nstruct klist_node;\n\nstruct klist {\n\tspinlock_t k_lock;\n\tstruct list_head k_list;\n\tvoid (*get)(struct klist_node *);\n\tvoid (*put)(struct klist_node *);\n};\n\nstruct klist_node {\n\tvoid *n_klist;\n\tstruct list_head n_node;\n\tstruct kref n_ref;\n};\n\nstruct klist_iter {\n\tstruct klist *i_klist;\n\tstruct klist_node *i_cur;\n};\n\nstruct class_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n};\n\nenum {\n\tDISK_EVENT_FLAG_POLL = 1,\n\tDISK_EVENT_FLAG_UEVENT = 2,\n};\n\nstruct disk_events {\n\tstruct list_head node;\n\tstruct gendisk *disk;\n\tspinlock_t lock;\n\tstruct mutex block_mutex;\n\tint block;\n\tunsigned int pending;\n\tunsigned int clearing;\n\tlong int poll_msecs;\n\tstruct delayed_work dwork;\n};\n\nstruct badblocks {\n\tstruct device *dev;\n\tint count;\n\tint unacked_exist;\n\tint shift;\n\tu64 *page;\n\tint changed;\n\tseqlock_t lock;\n\tsector_t sector;\n\tsector_t size;\n};\n\nstruct disk_part_iter {\n\tstruct gendisk *disk;\n\tstruct hd_struct *part;\n\tint idx;\n\tunsigned int flags;\n};\n\nstruct blk_major_name {\n\tstruct blk_major_name *next;\n\tint major;\n\tchar name[16];\n};\n\nenum {\n\tIOPRIO_WHO_PROCESS = 1,\n\tIOPRIO_WHO_PGRP = 2,\n\tIOPRIO_WHO_USER = 3,\n};\n\nstruct parsed_partitions {\n\tstruct block_device *bdev;\n\tchar name[32];\n\tstruct {\n\t\tsector_t from;\n\t\tsector_t size;\n\t\tint flags;\n\t\tbool has_info;\n\t\tstruct partition_meta_info info;\n\t} *parts;\n\tint next;\n\tint limit;\n\tbool access_beyond_eod;\n\tchar *pp_buf;\n};\n\ntypedef struct {\n\tstruct page *v;\n} Sector;\n\nstruct msdos_partition {\n\tu8 boot_ind;\n\tu8 head;\n\tu8 sector;\n\tu8 cyl;\n\tu8 sys_ind;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_cyl;\n\t__le32 start_sect;\n\t__le32 nr_sects;\n};\n\nenum msdos_sys_ind {\n\tDOS_EXTENDED_PARTITION = 5,\n\tLINUX_EXTENDED_PARTITION = 133,\n\tWIN98_EXTENDED_PARTITION = 15,\n\tLINUX_DATA_PARTITION = 131,\n\tLINUX_LVM_PARTITION = 142,\n\tLINUX_RAID_PARTITION = 253,\n\tSOLARIS_X86_PARTITION = 130,\n\tNEW_SOLARIS_X86_PARTITION = 191,\n\tDM6_AUX1PARTITION = 81,\n\tDM6_AUX3PARTITION = 83,\n\tDM6_PARTITION = 84,\n\tEZD_PARTITION = 85,\n\tFREEBSD_PARTITION = 165,\n\tOPENBSD_PARTITION = 166,\n\tNETBSD_PARTITION = 169,\n\tBSDI_PARTITION = 183,\n\tMINIX_PARTITION = 129,\n\tUNIXWARE_PARTITION = 99,\n};\n\nstruct _gpt_header {\n\t__le64 signature;\n\t__le32 revision;\n\t__le32 header_size;\n\t__le32 header_crc32;\n\t__le32 reserved1;\n\t__le64 my_lba;\n\t__le64 alternate_lba;\n\t__le64 first_usable_lba;\n\t__le64 last_usable_lba;\n\tefi_guid_t disk_guid;\n\t__le64 partition_entry_lba;\n\t__le32 num_partition_entries;\n\t__le32 sizeof_partition_entry;\n\t__le32 partition_entry_array_crc32;\n} __attribute__((packed));\n\ntypedef struct _gpt_header gpt_header;\n\nstruct _gpt_entry_attributes {\n\tu64 required_to_function: 1;\n\tu64 reserved: 47;\n\tu64 type_guid_specific: 16;\n};\n\ntypedef struct _gpt_entry_attributes gpt_entry_attributes;\n\nstruct _gpt_entry {\n\tefi_guid_t partition_type_guid;\n\tefi_guid_t unique_partition_guid;\n\t__le64 starting_lba;\n\t__le64 ending_lba;\n\tgpt_entry_attributes attributes;\n\t__le16 partition_name[36];\n};\n\ntypedef struct _gpt_entry gpt_entry;\n\nstruct _gpt_mbr_record {\n\tu8 boot_indicator;\n\tu8 start_head;\n\tu8 start_sector;\n\tu8 start_track;\n\tu8 os_type;\n\tu8 end_head;\n\tu8 end_sector;\n\tu8 end_track;\n\t__le32 starting_lba;\n\t__le32 size_in_lba;\n};\n\ntypedef struct _gpt_mbr_record gpt_mbr_record;\n\nstruct _legacy_mbr {\n\tu8 boot_code[440];\n\t__le32 unique_mbr_signature;\n\t__le16 unknown;\n\tgpt_mbr_record partition_record[4];\n\t__le16 signature;\n} __attribute__((packed));\n\ntypedef struct _legacy_mbr legacy_mbr;\n\nstruct rq_wait {\n\twait_queue_head_t wait;\n\tatomic_t inflight;\n};\n\nstruct rq_depth {\n\tunsigned int max_depth;\n\tint scale_step;\n\tbool scaled_max;\n\tunsigned int queue_depth;\n\tunsigned int default_depth;\n};\n\ntypedef bool acquire_inflight_cb_t(struct rq_wait *, void *);\n\ntypedef void cleanup_cb_t(struct rq_wait *, void *);\n\nstruct rq_qos_wait_data {\n\tstruct wait_queue_entry wq;\n\tstruct task_struct *task;\n\tstruct rq_wait *rqw;\n\tacquire_inflight_cb_t *cb;\n\tvoid *private_data;\n\tbool got_token;\n};\n\nstruct request_sense;\n\nstruct cdrom_generic_command {\n\tunsigned char cmd[12];\n\tunsigned char *buffer;\n\tunsigned int buflen;\n\tint stat;\n\tstruct request_sense *sense;\n\tunsigned char data_direction;\n\tint quiet;\n\tint timeout;\n\tvoid *reserved[1];\n};\n\nstruct request_sense {\n\t__u8 error_code: 7;\n\t__u8 valid: 1;\n\t__u8 segment_number;\n\t__u8 sense_key: 4;\n\t__u8 reserved2: 1;\n\t__u8 ili: 1;\n\t__u8 reserved1: 2;\n\t__u8 information[4];\n\t__u8 add_sense_len;\n\t__u8 command_info[4];\n\t__u8 asc;\n\t__u8 ascq;\n\t__u8 fruc;\n\t__u8 sks[3];\n\t__u8 asb[46];\n};\n\nstruct scsi_ioctl_command {\n\tunsigned int inlen;\n\tunsigned int outlen;\n\tunsigned char data[0];\n};\n\nenum scsi_device_event {\n\tSDEV_EVT_MEDIA_CHANGE = 1,\n\tSDEV_EVT_INQUIRY_CHANGE_REPORTED = 2,\n\tSDEV_EVT_CAPACITY_CHANGE_REPORTED = 3,\n\tSDEV_EVT_SOFT_THRESHOLD_REACHED_REPORTED = 4,\n\tSDEV_EVT_MODE_PARAMETER_CHANGE_REPORTED = 5,\n\tSDEV_EVT_LUN_CHANGE_REPORTED = 6,\n\tSDEV_EVT_ALUA_STATE_CHANGE_REPORTED = 7,\n\tSDEV_EVT_POWER_ON_RESET_OCCURRED = 8,\n\tSDEV_EVT_FIRST = 1,\n\tSDEV_EVT_LAST = 8,\n\tSDEV_EVT_MAXBITS = 9,\n};\n\nstruct scsi_request {\n\tunsigned char __cmd[16];\n\tunsigned char *cmd;\n\tshort unsigned int cmd_len;\n\tint result;\n\tunsigned int sense_len;\n\tunsigned int resid_len;\n\tint retries;\n\tvoid *sense;\n};\n\nstruct sg_io_hdr {\n\tint interface_id;\n\tint dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tunsigned int dxfer_len;\n\tvoid *dxferp;\n\tunsigned char *cmdp;\n\tvoid *sbp;\n\tunsigned int timeout;\n\tunsigned int flags;\n\tint pack_id;\n\tvoid *usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tint resid;\n\tunsigned int duration;\n\tunsigned int info;\n};\n\nstruct compat_sg_io_hdr {\n\tcompat_int_t interface_id;\n\tcompat_int_t dxfer_direction;\n\tunsigned char cmd_len;\n\tunsigned char mx_sb_len;\n\tshort unsigned int iovec_count;\n\tcompat_uint_t dxfer_len;\n\tcompat_uint_t dxferp;\n\tcompat_uptr_t cmdp;\n\tcompat_uptr_t sbp;\n\tcompat_uint_t timeout;\n\tcompat_uint_t flags;\n\tcompat_int_t pack_id;\n\tcompat_uptr_t usr_ptr;\n\tunsigned char status;\n\tunsigned char masked_status;\n\tunsigned char msg_status;\n\tunsigned char sb_len_wr;\n\tshort unsigned int host_status;\n\tshort unsigned int driver_status;\n\tcompat_int_t resid;\n\tcompat_uint_t duration;\n\tcompat_uint_t info;\n};\n\nstruct blk_cmd_filter {\n\tlong unsigned int read_ok[4];\n\tlong unsigned int write_ok[4];\n};\n\nstruct compat_cdrom_generic_command {\n\tunsigned char cmd[12];\n\tcompat_caddr_t buffer;\n\tcompat_uint_t buflen;\n\tcompat_int_t stat;\n\tcompat_caddr_t sense;\n\tunsigned char data_direction;\n\tcompat_int_t quiet;\n\tcompat_int_t timeout;\n\tcompat_caddr_t reserved[1];\n};\n\nenum {\n\tOMAX_SB_LEN = 16,\n};\n\nstruct bsg_device {\n\tstruct request_queue *queue;\n\tspinlock_t lock;\n\tstruct hlist_node dev_list;\n\trefcount_t ref_count;\n\tchar name[20];\n\tint max_queue;\n};\n\nstruct deadline_data {\n\tstruct rb_root sort_list[2];\n\tstruct list_head fifo_list[2];\n\tstruct request *next_rq[2];\n\tunsigned int batching;\n\tunsigned int starved;\n\tint fifo_expire[2];\n\tint fifo_batch;\n\tint writes_starved;\n\tint front_merges;\n\tspinlock_t lock;\n\tspinlock_t zone_lock;\n\tstruct list_head dispatch;\n};\n\nstruct trace_event_raw_kyber_latency {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar type[8];\n\tu8 percentile;\n\tu8 numerator;\n\tu8 denominator;\n\tunsigned int samples;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_adjust {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tunsigned int depth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_kyber_throttled {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tchar domain[16];\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_kyber_latency {};\n\nstruct trace_event_data_offsets_kyber_adjust {};\n\nstruct trace_event_data_offsets_kyber_throttled {};\n\ntypedef void (*btf_trace_kyber_latency)(void *, struct request_queue *, const char *, const char *, unsigned int, unsigned int, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_kyber_adjust)(void *, struct request_queue *, const char *, unsigned int);\n\ntypedef void (*btf_trace_kyber_throttled)(void *, struct request_queue *, const char *);\n\nenum {\n\tKYBER_READ = 0,\n\tKYBER_WRITE = 1,\n\tKYBER_DISCARD = 2,\n\tKYBER_OTHER = 3,\n\tKYBER_NUM_DOMAINS = 4,\n};\n\nenum {\n\tKYBER_ASYNC_PERCENT = 75,\n};\n\nenum {\n\tKYBER_LATENCY_SHIFT = 2,\n\tKYBER_GOOD_BUCKETS = 4,\n\tKYBER_LATENCY_BUCKETS = 8,\n};\n\nenum {\n\tKYBER_TOTAL_LATENCY = 0,\n\tKYBER_IO_LATENCY = 1,\n};\n\nstruct kyber_cpu_latency {\n\tatomic_t buckets[48];\n};\n\nstruct kyber_ctx_queue {\n\tspinlock_t lock;\n\tstruct list_head rq_list[4];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct kyber_queue_data {\n\tstruct request_queue *q;\n\tstruct sbitmap_queue domain_tokens[4];\n\tunsigned int async_depth;\n\tstruct kyber_cpu_latency *cpu_latency;\n\tstruct timer_list timer;\n\tunsigned int latency_buckets[48];\n\tlong unsigned int latency_timeout[3];\n\tint domain_p99[3];\n\tu64 latency_targets[3];\n};\n\nstruct kyber_hctx_data {\n\tspinlock_t lock;\n\tstruct list_head rqs[4];\n\tunsigned int cur_domain;\n\tunsigned int batching;\n\tstruct kyber_ctx_queue *kcqs;\n\tstruct sbitmap kcq_map[4];\n\tstruct sbq_wait domain_wait[4];\n\tstruct sbq_wait_state *domain_ws[4];\n\tatomic_t wait_index[4];\n};\n\nstruct flush_kcq_data {\n\tstruct kyber_hctx_data *khd;\n\tunsigned int sched_domain;\n\tstruct list_head *list;\n};\n\nstruct show_busy_params {\n\tstruct seq_file *m;\n\tstruct blk_mq_hw_ctx *hctx;\n};\n\ntypedef void (*swap_func_t)(void *, void *, int);\n\ntypedef int (*cmp_r_func_t)(const void *, const void *, const void *);\n\ntypedef __kernel_long_t __kernel_ptrdiff_t;\n\ntypedef __kernel_ptrdiff_t ptrdiff_t;\n\nstruct region {\n\tunsigned int start;\n\tunsigned int off;\n\tunsigned int group_len;\n\tunsigned int end;\n};\n\nenum {\n\tREG_OP_ISFREE = 0,\n\tREG_OP_ALLOC = 1,\n\tREG_OP_RELEASE = 2,\n};\n\ntypedef struct scatterlist *sg_alloc_fn(unsigned int, gfp_t);\n\ntypedef void sg_free_fn(struct scatterlist *, unsigned int);\n\nstruct sg_page_iter {\n\tstruct scatterlist *sg;\n\tunsigned int sg_pgoffset;\n\tunsigned int __nents;\n\tint __pg_advance;\n};\n\nstruct sg_dma_page_iter {\n\tstruct sg_page_iter base;\n};\n\nstruct sg_mapping_iter {\n\tstruct page *page;\n\tvoid *addr;\n\tsize_t length;\n\tsize_t consumed;\n\tstruct sg_page_iter piter;\n\tunsigned int __offset;\n\tunsigned int __remaining;\n\tunsigned int __flags;\n};\n\ntypedef int (*cmp_func)(void *, const struct list_head *, const struct list_head *);\n\nstruct __kfifo {\n\tunsigned int in;\n\tunsigned int out;\n\tunsigned int mask;\n\tunsigned int esize;\n\tvoid *data;\n};\n\nstruct rhashtable_walker {\n\tstruct list_head list;\n\tstruct bucket_table *tbl;\n};\n\nstruct rhashtable_iter {\n\tstruct rhashtable *ht;\n\tstruct rhash_head *p;\n\tstruct rhlist_head *list;\n\tstruct rhashtable_walker walker;\n\tunsigned int slot;\n\tunsigned int skip;\n\tbool end_of_table;\n};\n\nunion nested_table {\n\tunion nested_table *table;\n\tstruct rhash_lock_head *bucket;\n};\n\nstruct once_work {\n\tstruct work_struct work;\n\tstruct static_key_true *key;\n};\n\nstruct genradix_iter {\n\tsize_t offset;\n\tsize_t pos;\n};\n\nstruct genradix_node {\n\tunion {\n\t\tstruct genradix_node *children[512];\n\t\tu8 data[4096];\n\t};\n};\n\nstruct reciprocal_value {\n\tu32 m;\n\tu8 sh1;\n\tu8 sh2;\n};\n\nstruct reciprocal_value_adv {\n\tu32 m;\n\tu8 sh;\n\tu8 exp;\n\tbool is_wide_m;\n};\n\nstruct arc4_ctx {\n\tu32 S[256];\n\tu32 x;\n\tu32 y;\n};\n\nenum devm_ioremap_type {\n\tDEVM_IOREMAP = 0,\n\tDEVM_IOREMAP_UC = 1,\n\tDEVM_IOREMAP_WC = 2,\n};\n\nstruct pcim_iomap_devres {\n\tvoid *table[6];\n};\n\nenum assoc_array_walk_status {\n\tassoc_array_walk_tree_empty = 0,\n\tassoc_array_walk_found_terminal_node = 1,\n\tassoc_array_walk_found_wrong_shortcut = 2,\n};\n\nstruct assoc_array_walk_result {\n\tstruct {\n\t\tstruct assoc_array_node *node;\n\t\tint level;\n\t\tint slot;\n\t} terminal_node;\n\tstruct {\n\t\tstruct assoc_array_shortcut *shortcut;\n\t\tint level;\n\t\tint sc_level;\n\t\tlong unsigned int sc_segments;\n\t\tlong unsigned int dissimilarity;\n\t} wrong_shortcut;\n};\n\nstruct assoc_array_delete_collapse_context {\n\tstruct assoc_array_node *node;\n\tconst void *skip_leaf;\n\tint slot;\n};\n\nstruct gen_pool_chunk {\n\tstruct list_head next_chunk;\n\tatomic_long_t avail;\n\tphys_addr_t phys_addr;\n\tvoid *owner;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n\tlong unsigned int bits[0];\n};\n\nstruct genpool_data_align {\n\tint align;\n};\n\nstruct genpool_data_fixed {\n\tlong unsigned int offset;\n};\n\ntypedef z_stream *z_streamp;\n\ntypedef struct {\n\tunsigned char op;\n\tunsigned char bits;\n\tshort unsigned int val;\n} code;\n\ntypedef enum {\n\tHEAD = 0,\n\tFLAGS = 1,\n\tTIME = 2,\n\tOS = 3,\n\tEXLEN = 4,\n\tEXTRA = 5,\n\tNAME = 6,\n\tCOMMENT = 7,\n\tHCRC = 8,\n\tDICTID = 9,\n\tDICT = 10,\n\tTYPE = 11,\n\tTYPEDO = 12,\n\tSTORED = 13,\n\tCOPY = 14,\n\tTABLE = 15,\n\tLENLENS = 16,\n\tCODELENS = 17,\n\tLEN = 18,\n\tLENEXT = 19,\n\tDIST = 20,\n\tDISTEXT = 21,\n\tMATCH = 22,\n\tLIT = 23,\n\tCHECK = 24,\n\tLENGTH = 25,\n\tDONE = 26,\n\tBAD = 27,\n\tMEM = 28,\n\tSYNC = 29,\n} inflate_mode;\n\nstruct inflate_state {\n\tinflate_mode mode;\n\tint last;\n\tint wrap;\n\tint havedict;\n\tint flags;\n\tunsigned int dmax;\n\tlong unsigned int check;\n\tlong unsigned int total;\n\tunsigned int wbits;\n\tunsigned int wsize;\n\tunsigned int whave;\n\tunsigned int write;\n\tunsigned char *window;\n\tlong unsigned int hold;\n\tunsigned int bits;\n\tunsigned int length;\n\tunsigned int offset;\n\tunsigned int extra;\n\tconst code *lencode;\n\tconst code *distcode;\n\tunsigned int lenbits;\n\tunsigned int distbits;\n\tunsigned int ncode;\n\tunsigned int nlen;\n\tunsigned int ndist;\n\tunsigned int have;\n\tcode *next;\n\tshort unsigned int lens[320];\n\tshort unsigned int work[288];\n\tcode codes[2048];\n};\n\nunion uu {\n\tshort unsigned int us;\n\tunsigned char b[2];\n};\n\ntypedef unsigned int uInt;\n\nstruct inflate_workspace {\n\tstruct inflate_state inflate_state;\n\tunsigned char working_window[32768];\n};\n\ntypedef enum {\n\tCODES = 0,\n\tLENS = 1,\n\tDISTS = 2,\n} codetype;\n\ntypedef unsigned char uch;\n\ntypedef short unsigned int ush;\n\ntypedef long unsigned int ulg;\n\nstruct ct_data_s {\n\tunion {\n\t\tush freq;\n\t\tush code;\n\t} fc;\n\tunion {\n\t\tush dad;\n\t\tush len;\n\t} dl;\n};\n\ntypedef struct ct_data_s ct_data;\n\nstruct static_tree_desc_s {\n\tconst ct_data *static_tree;\n\tconst int *extra_bits;\n\tint extra_base;\n\tint elems;\n\tint max_length;\n};\n\ntypedef struct static_tree_desc_s static_tree_desc;\n\nstruct tree_desc_s {\n\tct_data *dyn_tree;\n\tint max_code;\n\tstatic_tree_desc *stat_desc;\n};\n\ntypedef ush Pos;\n\ntypedef unsigned int IPos;\n\nstruct deflate_state {\n\tz_streamp strm;\n\tint status;\n\tByte *pending_buf;\n\tulg pending_buf_size;\n\tByte *pending_out;\n\tint pending;\n\tint noheader;\n\tByte data_type;\n\tByte method;\n\tint last_flush;\n\tuInt w_size;\n\tuInt w_bits;\n\tuInt w_mask;\n\tByte *window;\n\tulg window_size;\n\tPos *prev;\n\tPos *head;\n\tuInt ins_h;\n\tuInt hash_size;\n\tuInt hash_bits;\n\tuInt hash_mask;\n\tuInt hash_shift;\n\tlong int block_start;\n\tuInt match_length;\n\tIPos prev_match;\n\tint match_available;\n\tuInt strstart;\n\tuInt match_start;\n\tuInt lookahead;\n\tuInt prev_length;\n\tuInt max_chain_length;\n\tuInt max_lazy_match;\n\tint level;\n\tint strategy;\n\tuInt good_match;\n\tint nice_match;\n\tstruct ct_data_s dyn_ltree[573];\n\tstruct ct_data_s dyn_dtree[61];\n\tstruct ct_data_s bl_tree[39];\n\tstruct tree_desc_s l_desc;\n\tstruct tree_desc_s d_desc;\n\tstruct tree_desc_s bl_desc;\n\tush bl_count[16];\n\tint heap[573];\n\tint heap_len;\n\tint heap_max;\n\tuch depth[573];\n\tuch *l_buf;\n\tuInt lit_bufsize;\n\tuInt last_lit;\n\tush *d_buf;\n\tulg opt_len;\n\tulg static_len;\n\tulg compressed_len;\n\tuInt matches;\n\tint last_eob_len;\n\tush bi_buf;\n\tint bi_valid;\n};\n\ntypedef struct deflate_state deflate_state;\n\ntypedef enum {\n\tneed_more = 0,\n\tblock_done = 1,\n\tfinish_started = 2,\n\tfinish_done = 3,\n} block_state;\n\ntypedef block_state (*compress_func)(deflate_state *, int);\n\nstruct deflate_workspace {\n\tdeflate_state deflate_memory;\n\tByte *window_memory;\n\tPos *prev_memory;\n\tPos *head_memory;\n\tchar *overlay_memory;\n};\n\ntypedef struct deflate_workspace deflate_workspace;\n\nstruct config_s {\n\tush good_length;\n\tush max_lazy;\n\tush nice_length;\n\tush max_chain;\n\tcompress_func func;\n};\n\ntypedef struct config_s config;\n\ntypedef struct tree_desc_s tree_desc;\n\ntypedef struct {\n\tconst uint8_t *externalDict;\n\tsize_t extDictSize;\n\tconst uint8_t *prefixEnd;\n\tsize_t prefixSize;\n} LZ4_streamDecode_t_internal;\n\ntypedef union {\n\tlong long unsigned int table[4];\n\tLZ4_streamDecode_t_internal internal_donotuse;\n} LZ4_streamDecode_t;\n\ntypedef uint8_t BYTE;\n\ntypedef uint16_t U16;\n\ntypedef uint32_t U32;\n\ntypedef uint64_t U64;\n\ntypedef uintptr_t uptrval;\n\ntypedef enum {\n\tnoDict = 0,\n\twithPrefix64k = 1,\n\tusingExtDict = 2,\n} dict_directive;\n\ntypedef enum {\n\tendOnOutputSize = 0,\n\tendOnInputSize = 1,\n} endCondition_directive;\n\ntypedef enum {\n\tdecode_full_block = 0,\n\tpartial_decode = 1,\n} earlyEnd_directive;\n\nenum xz_mode {\n\tXZ_SINGLE = 0,\n\tXZ_PREALLOC = 1,\n\tXZ_DYNALLOC = 2,\n};\n\nenum xz_ret {\n\tXZ_OK = 0,\n\tXZ_STREAM_END = 1,\n\tXZ_UNSUPPORTED_CHECK = 2,\n\tXZ_MEM_ERROR = 3,\n\tXZ_MEMLIMIT_ERROR = 4,\n\tXZ_FORMAT_ERROR = 5,\n\tXZ_OPTIONS_ERROR = 6,\n\tXZ_DATA_ERROR = 7,\n\tXZ_BUF_ERROR = 8,\n};\n\nstruct xz_buf {\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_size;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n};\n\ntypedef uint64_t vli_type;\n\nenum xz_check {\n\tXZ_CHECK_NONE = 0,\n\tXZ_CHECK_CRC32 = 1,\n\tXZ_CHECK_CRC64 = 4,\n\tXZ_CHECK_SHA256 = 10,\n};\n\nstruct xz_dec_hash {\n\tvli_type unpadded;\n\tvli_type uncompressed;\n\tuint32_t crc32;\n};\n\nstruct xz_dec_lzma2;\n\nstruct xz_dec_bcj;\n\nstruct xz_dec {\n\tenum {\n\t\tSEQ_STREAM_HEADER = 0,\n\t\tSEQ_BLOCK_START = 1,\n\t\tSEQ_BLOCK_HEADER = 2,\n\t\tSEQ_BLOCK_UNCOMPRESS = 3,\n\t\tSEQ_BLOCK_PADDING = 4,\n\t\tSEQ_BLOCK_CHECK = 5,\n\t\tSEQ_INDEX = 6,\n\t\tSEQ_INDEX_PADDING = 7,\n\t\tSEQ_INDEX_CRC32 = 8,\n\t\tSEQ_STREAM_FOOTER = 9,\n\t} sequence;\n\tuint32_t pos;\n\tvli_type vli;\n\tsize_t in_start;\n\tsize_t out_start;\n\tuint32_t crc32;\n\tenum xz_check check_type;\n\tenum xz_mode mode;\n\tbool allow_buf_error;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tuint32_t size;\n\t} block_header;\n\tstruct {\n\t\tvli_type compressed;\n\t\tvli_type uncompressed;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} block;\n\tstruct {\n\t\tenum {\n\t\t\tSEQ_INDEX_COUNT = 0,\n\t\t\tSEQ_INDEX_UNPADDED = 1,\n\t\t\tSEQ_INDEX_UNCOMPRESSED = 2,\n\t\t} sequence;\n\t\tvli_type size;\n\t\tvli_type count;\n\t\tstruct xz_dec_hash hash;\n\t} index;\n\tstruct {\n\t\tsize_t pos;\n\t\tsize_t size;\n\t\tuint8_t buf[1024];\n\t} temp;\n\tstruct xz_dec_lzma2 *lzma2;\n\tstruct xz_dec_bcj *bcj;\n\tbool bcj_active;\n};\n\nenum lzma_state {\n\tSTATE_LIT_LIT = 0,\n\tSTATE_MATCH_LIT_LIT = 1,\n\tSTATE_REP_LIT_LIT = 2,\n\tSTATE_SHORTREP_LIT_LIT = 3,\n\tSTATE_MATCH_LIT = 4,\n\tSTATE_REP_LIT = 5,\n\tSTATE_SHORTREP_LIT = 6,\n\tSTATE_LIT_MATCH = 7,\n\tSTATE_LIT_LONGREP = 8,\n\tSTATE_LIT_SHORTREP = 9,\n\tSTATE_NONLIT_MATCH = 10,\n\tSTATE_NONLIT_REP = 11,\n};\n\nstruct dictionary {\n\tuint8_t *buf;\n\tsize_t start;\n\tsize_t pos;\n\tsize_t full;\n\tsize_t limit;\n\tsize_t end;\n\tuint32_t size;\n\tuint32_t size_max;\n\tuint32_t allocated;\n\tenum xz_mode mode;\n};\n\nstruct rc_dec {\n\tuint32_t range;\n\tuint32_t code;\n\tuint32_t init_bytes_left;\n\tconst uint8_t *in;\n\tsize_t in_pos;\n\tsize_t in_limit;\n};\n\nstruct lzma_len_dec {\n\tuint16_t choice;\n\tuint16_t choice2;\n\tuint16_t low[128];\n\tuint16_t mid[128];\n\tuint16_t high[256];\n};\n\nstruct lzma_dec {\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n\tenum lzma_state state;\n\tuint32_t len;\n\tuint32_t lc;\n\tuint32_t literal_pos_mask;\n\tuint32_t pos_mask;\n\tuint16_t is_match[192];\n\tuint16_t is_rep[12];\n\tuint16_t is_rep0[12];\n\tuint16_t is_rep1[12];\n\tuint16_t is_rep2[12];\n\tuint16_t is_rep0_long[192];\n\tuint16_t dist_slot[256];\n\tuint16_t dist_special[114];\n\tuint16_t dist_align[16];\n\tstruct lzma_len_dec match_len_dec;\n\tstruct lzma_len_dec rep_len_dec;\n\tuint16_t literal[12288];\n};\n\nenum lzma2_seq {\n\tSEQ_CONTROL = 0,\n\tSEQ_UNCOMPRESSED_1 = 1,\n\tSEQ_UNCOMPRESSED_2 = 2,\n\tSEQ_COMPRESSED_0 = 3,\n\tSEQ_COMPRESSED_1 = 4,\n\tSEQ_PROPERTIES = 5,\n\tSEQ_LZMA_PREPARE = 6,\n\tSEQ_LZMA_RUN = 7,\n\tSEQ_COPY = 8,\n};\n\nstruct lzma2_dec {\n\tenum lzma2_seq sequence;\n\tenum lzma2_seq next_sequence;\n\tuint32_t uncompressed;\n\tuint32_t compressed;\n\tbool need_dict_reset;\n\tbool need_props;\n};\n\nstruct xz_dec_lzma2___2 {\n\tstruct rc_dec rc;\n\tstruct dictionary dict;\n\tstruct lzma2_dec lzma2;\n\tstruct lzma_dec lzma;\n\tstruct {\n\t\tuint32_t size;\n\t\tuint8_t buf[63];\n\t} temp;\n};\n\nstruct xz_dec_bcj___2 {\n\tenum {\n\t\tBCJ_X86 = 4,\n\t\tBCJ_POWERPC = 5,\n\t\tBCJ_IA64 = 6,\n\t\tBCJ_ARM = 7,\n\t\tBCJ_ARMTHUMB = 8,\n\t\tBCJ_SPARC = 9,\n\t} type;\n\tenum xz_ret ret;\n\tbool single_call;\n\tuint32_t pos;\n\tuint32_t x86_prev_mask;\n\tuint8_t *out;\n\tsize_t out_pos;\n\tsize_t out_size;\n\tstruct {\n\t\tsize_t filtered;\n\t\tsize_t size;\n\t\tuint8_t buf[16];\n\t} temp;\n};\n\ntypedef s32 pao_T_____8;\n\nstruct ei_entry {\n\tstruct list_head list;\n\tlong unsigned int start_addr;\n\tlong unsigned int end_addr;\n\tint etype;\n\tvoid *priv;\n};\n\nstruct nla_bitfield32 {\n\t__u32 value;\n\t__u32 selector;\n};\n\nenum nla_policy_validation {\n\tNLA_VALIDATE_NONE = 0,\n\tNLA_VALIDATE_RANGE = 1,\n\tNLA_VALIDATE_MIN = 2,\n\tNLA_VALIDATE_MAX = 3,\n\tNLA_VALIDATE_RANGE_PTR = 4,\n\tNLA_VALIDATE_FUNCTION = 5,\n\tNLA_VALIDATE_WARN_TOO_LONG = 6,\n};\n\nstruct cpu_rmap {\n\tstruct kref refcount;\n\tu16 size;\n\tu16 used;\n\tvoid **obj;\n\tstruct {\n\t\tu16 index;\n\t\tu16 dist;\n\t} near[0];\n};\n\nstruct irq_glue {\n\tstruct irq_affinity_notify notify;\n\tstruct cpu_rmap *rmap;\n\tu16 index;\n};\n\ntypedef mpi_limb_t *mpi_ptr_t;\n\ntypedef int mpi_size_t;\n\ntypedef mpi_limb_t UWtype;\n\ntypedef unsigned int UHWtype;\n\nstruct karatsuba_ctx {\n\tstruct karatsuba_ctx *next;\n\tmpi_ptr_t tspace;\n\tmpi_size_t tspace_size;\n\tmpi_ptr_t tp;\n\tmpi_size_t tp_size;\n};\n\ntypedef long int mpi_limb_signed_t;\n\nstruct sg_pool {\n\tsize_t size;\n\tchar *name;\n\tstruct kmem_cache *slab;\n\tmempool_t *pool;\n};\n\nstruct font_desc {\n\tint idx;\n\tconst char *name;\n\tint width;\n\tint height;\n\tconst void *data;\n\tint pref;\n};\n\ntypedef u16 ucs2_char_t;\n\nstruct msr {\n\tunion {\n\t\tstruct {\n\t\t\tu32 l;\n\t\t\tu32 h;\n\t\t};\n\t\tu64 q;\n\t};\n};\n\nstruct msr_info {\n\tu32 msr_no;\n\tstruct msr reg;\n\tstruct msr *msrs;\n\tint err;\n};\n\nstruct msr_regs_info {\n\tu32 *regs;\n\tint err;\n};\n\nstruct msr_info_completion {\n\tstruct msr_info msr;\n\tstruct completion done;\n};\n\nstruct trace_event_raw_msr_trace_class {\n\tstruct trace_entry ent;\n\tunsigned int msr;\n\tu64 val;\n\tint failed;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_msr_trace_class {};\n\ntypedef void (*btf_trace_read_msr)(void *, unsigned int, u64, int);\n\ntypedef void (*btf_trace_write_msr)(void *, unsigned int, u64, int);\n\ntypedef void (*btf_trace_rdpmc)(void *, unsigned int, u64, int);\n\nstruct compress_format {\n\tunsigned char magic[2];\n\tconst char *name;\n\tdecompress_fn decompressor;\n};\n\nstruct group_data {\n\tint limit[21];\n\tint base[20];\n\tint permute[258];\n\tint minLen;\n\tint maxLen;\n};\n\nstruct bunzip_data {\n\tint writeCopies;\n\tint writePos;\n\tint writeRunCountdown;\n\tint writeCount;\n\tint writeCurrent;\n\tlong int (*fill)(void *, long unsigned int);\n\tlong int inbufCount;\n\tlong int inbufPos;\n\tunsigned char *inbuf;\n\tunsigned int inbufBitCount;\n\tunsigned int inbufBits;\n\tunsigned int crc32Table[256];\n\tunsigned int headerCRC;\n\tunsigned int totalCRC;\n\tunsigned int writeCRC;\n\tunsigned int *dbuf;\n\tunsigned int dbufSize;\n\tunsigned char selectors[32768];\n\tstruct group_data groups[6];\n\tint io_error;\n\tint byteCount[256];\n\tunsigned char symToByte[256];\n\tunsigned char mtfSymbol[256];\n};\n\nstruct rc {\n\tlong int (*fill)(void *, long unsigned int);\n\tuint8_t *ptr;\n\tuint8_t *buffer;\n\tuint8_t *buffer_end;\n\tlong int buffer_size;\n\tuint32_t code;\n\tuint32_t range;\n\tuint32_t bound;\n\tvoid (*error)(char *);\n};\n\nstruct lzma_header {\n\tuint8_t pos;\n\tuint32_t dict_size;\n\tuint64_t dst_size;\n} __attribute__((packed));\n\nstruct writer {\n\tuint8_t *buffer;\n\tuint8_t previous_byte;\n\tsize_t buffer_pos;\n\tint bufsize;\n\tsize_t global_pos;\n\tlong int (*flush)(void *, long unsigned int);\n\tstruct lzma_header *header;\n};\n\nstruct cstate {\n\tint state;\n\tuint32_t rep0;\n\tuint32_t rep1;\n\tuint32_t rep2;\n\tuint32_t rep3;\n};\n\nstruct xz_dec___2;\n\nenum cpio_fields {\n\tC_MAGIC = 0,\n\tC_INO = 1,\n\tC_MODE = 2,\n\tC_UID = 3,\n\tC_GID = 4,\n\tC_NLINK = 5,\n\tC_MTIME = 6,\n\tC_FILESIZE = 7,\n\tC_MAJ = 8,\n\tC_MIN = 9,\n\tC_RMAJ = 10,\n\tC_RMIN = 11,\n\tC_NAMESIZE = 12,\n\tC_CHKSUM = 13,\n\tC_NFIELDS = 14,\n};\n\nstruct fprop_local_single {\n\tlong unsigned int events;\n\tunsigned int period;\n\traw_spinlock_t lock;\n};\n\nstruct radix_tree_iter {\n\tlong unsigned int index;\n\tlong unsigned int next_index;\n\tlong unsigned int tags;\n\tstruct xa_node *node;\n};\n\nenum {\n\tRADIX_TREE_ITER_TAG_MASK = 15,\n\tRADIX_TREE_ITER_TAGGED = 16,\n\tRADIX_TREE_ITER_CONTIG = 32,\n};\n\nstruct ida_bitmap {\n\tlong unsigned int bitmap[16];\n};\n\nstruct klist_waiter {\n\tstruct list_head list;\n\tstruct klist_node *node;\n\tstruct task_struct *process;\n\tint woken;\n};\n\nstruct uevent_sock {\n\tstruct list_head list;\n\tstruct sock *sk;\n};\n\nenum {\n\tLOGIC_PIO_INDIRECT = 0,\n\tLOGIC_PIO_CPU_MMIO = 1,\n};\n\nstruct logic_pio_host_ops;\n\nstruct logic_pio_hwaddr {\n\tstruct list_head list;\n\tstruct fwnode_handle *fwnode;\n\tresource_size_t hw_start;\n\tresource_size_t io_start;\n\tresource_size_t size;\n\tlong unsigned int flags;\n\tvoid *hostdata;\n\tconst struct logic_pio_host_ops *ops;\n};\n\nstruct logic_pio_host_ops {\n\tu32 (*in)(void *, long unsigned int, size_t);\n\tvoid (*out)(void *, long unsigned int, u32, size_t);\n\tu32 (*ins)(void *, long unsigned int, void *, size_t, unsigned int);\n\tvoid (*outs)(void *, long unsigned int, const void *, size_t, unsigned int);\n};\n\ntypedef struct {\n\tlong unsigned int key[2];\n} hsiphash_key_t;\n\nstruct clk_hw;\n\nstruct clk_rate_request {\n\tlong unsigned int rate;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int best_parent_rate;\n\tstruct clk_hw *best_parent_hw;\n};\n\nstruct clk_core;\n\nstruct clk_init_data;\n\nstruct clk_hw {\n\tstruct clk_core *core;\n\tstruct clk *clk;\n\tconst struct clk_init_data *init;\n};\n\nstruct clk_duty {\n\tunsigned int num;\n\tunsigned int den;\n};\n\nstruct clk_ops {\n\tint (*prepare)(struct clk_hw *);\n\tvoid (*unprepare)(struct clk_hw *);\n\tint (*is_prepared)(struct clk_hw *);\n\tvoid (*unprepare_unused)(struct clk_hw *);\n\tint (*enable)(struct clk_hw *);\n\tvoid (*disable)(struct clk_hw *);\n\tint (*is_enabled)(struct clk_hw *);\n\tvoid (*disable_unused)(struct clk_hw *);\n\tint (*save_context)(struct clk_hw *);\n\tvoid (*restore_context)(struct clk_hw *);\n\tlong unsigned int (*recalc_rate)(struct clk_hw *, long unsigned int);\n\tlong int (*round_rate)(struct clk_hw *, long unsigned int, long unsigned int *);\n\tint (*determine_rate)(struct clk_hw *, struct clk_rate_request *);\n\tint (*set_parent)(struct clk_hw *, u8);\n\tu8 (*get_parent)(struct clk_hw *);\n\tint (*set_rate)(struct clk_hw *, long unsigned int, long unsigned int);\n\tint (*set_rate_and_parent)(struct clk_hw *, long unsigned int, long unsigned int, u8);\n\tlong unsigned int (*recalc_accuracy)(struct clk_hw *, long unsigned int);\n\tint (*get_phase)(struct clk_hw *);\n\tint (*set_phase)(struct clk_hw *, int);\n\tint (*get_duty_cycle)(struct clk_hw *, struct clk_duty *);\n\tint (*set_duty_cycle)(struct clk_hw *, struct clk_duty *);\n\tint (*init)(struct clk_hw *);\n\tvoid (*terminate)(struct clk_hw *);\n\tvoid (*debug_init)(struct clk_hw *, struct dentry *);\n};\n\nstruct clk_parent_data {\n\tconst struct clk_hw *hw;\n\tconst char *fw_name;\n\tconst char *name;\n\tint index;\n};\n\nstruct clk_init_data {\n\tconst char *name;\n\tconst struct clk_ops *ops;\n\tconst char * const *parent_names;\n\tconst struct clk_parent_data *parent_data;\n\tconst struct clk_hw **parent_hws;\n\tu8 num_parents;\n\tlong unsigned int flags;\n};\n\nenum format_type {\n\tFORMAT_TYPE_NONE = 0,\n\tFORMAT_TYPE_WIDTH = 1,\n\tFORMAT_TYPE_PRECISION = 2,\n\tFORMAT_TYPE_CHAR = 3,\n\tFORMAT_TYPE_STR = 4,\n\tFORMAT_TYPE_PTR = 5,\n\tFORMAT_TYPE_PERCENT_CHAR = 6,\n\tFORMAT_TYPE_INVALID = 7,\n\tFORMAT_TYPE_LONG_LONG = 8,\n\tFORMAT_TYPE_ULONG = 9,\n\tFORMAT_TYPE_LONG = 10,\n\tFORMAT_TYPE_UBYTE = 11,\n\tFORMAT_TYPE_BYTE = 12,\n\tFORMAT_TYPE_USHORT = 13,\n\tFORMAT_TYPE_SHORT = 14,\n\tFORMAT_TYPE_UINT = 15,\n\tFORMAT_TYPE_INT = 16,\n\tFORMAT_TYPE_SIZE_T = 17,\n\tFORMAT_TYPE_PTRDIFF = 18,\n};\n\nstruct printf_spec {\n\tunsigned int type: 8;\n\tint field_width: 24;\n\tunsigned int flags: 8;\n\tunsigned int base: 8;\n\tint precision: 16;\n};\n\nstruct minmax_sample {\n\tu32 t;\n\tu32 v;\n};\n\nstruct minmax {\n\tstruct minmax_sample s[3];\n};\n\nstruct xa_limit {\n\tu32 max;\n\tu32 min;\n};\n\nenum {\n\tst_wordstart = 0,\n\tst_wordcmp = 1,\n\tst_wordskip = 2,\n\tst_bufcpy = 3,\n};\n\nenum {\n\tst_wordstart___2 = 0,\n\tst_wordcmp___2 = 1,\n\tst_wordskip___2 = 2,\n};\n\nstruct in6_addr___2;\n\nenum reg_type {\n\tREG_TYPE_RM = 0,\n\tREG_TYPE_INDEX = 1,\n\tREG_TYPE_BASE = 2,\n};\n\nstruct pci_sriov {\n\tint pos;\n\tint nres;\n\tu32 cap;\n\tu16 ctrl;\n\tu16 total_VFs;\n\tu16 initial_VFs;\n\tu16 num_VFs;\n\tu16 offset;\n\tu16 stride;\n\tu16 vf_device;\n\tu32 pgsz;\n\tu8 link;\n\tu8 max_VF_buses;\n\tu16 driver_max_VFs;\n\tstruct pci_dev *dev;\n\tstruct pci_dev *self;\n\tu32 class;\n\tu8 hdr_type;\n\tu16 subsystem_vendor;\n\tu16 subsystem_device;\n\tresource_size_t barsz[6];\n\tbool drivers_autoprobe;\n};\n\nstruct pci_bus_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n\tunsigned int flags;\n};\n\ntypedef u64 pci_bus_addr_t;\n\nstruct pci_bus_region {\n\tpci_bus_addr_t start;\n\tpci_bus_addr_t end;\n};\n\nenum pci_fixup_pass {\n\tpci_fixup_early = 0,\n\tpci_fixup_header = 1,\n\tpci_fixup_final = 2,\n\tpci_fixup_enable = 3,\n\tpci_fixup_resume = 4,\n\tpci_fixup_suspend = 5,\n\tpci_fixup_resume_early = 6,\n\tpci_fixup_suspend_late = 7,\n};\n\nstruct hotplug_slot_ops;\n\nstruct hotplug_slot {\n\tconst struct hotplug_slot_ops *ops;\n\tstruct list_head slot_list;\n\tstruct pci_slot *pci_slot;\n\tstruct module *owner;\n\tconst char *mod_name;\n};\n\nenum pci_dev_flags {\n\tPCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = 1,\n\tPCI_DEV_FLAGS_NO_D3 = 2,\n\tPCI_DEV_FLAGS_ASSIGNED = 4,\n\tPCI_DEV_FLAGS_ACS_ENABLED_QUIRK = 8,\n\tPCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = 32,\n\tPCI_DEV_FLAGS_NO_BUS_RESET = 64,\n\tPCI_DEV_FLAGS_NO_PM_RESET = 128,\n\tPCI_DEV_FLAGS_VPD_REF_F0 = 256,\n\tPCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = 512,\n\tPCI_DEV_FLAGS_NO_FLR_RESET = 1024,\n\tPCI_DEV_FLAGS_NO_RELAXED_ORDERING = 2048,\n};\n\nenum pci_bus_flags {\n\tPCI_BUS_FLAGS_NO_MSI = 1,\n\tPCI_BUS_FLAGS_NO_MMRBC = 2,\n\tPCI_BUS_FLAGS_NO_AERSID = 4,\n\tPCI_BUS_FLAGS_NO_EXTCFG = 8,\n};\n\nenum pci_bus_speed {\n\tPCI_SPEED_33MHz = 0,\n\tPCI_SPEED_66MHz = 1,\n\tPCI_SPEED_66MHz_PCIX = 2,\n\tPCI_SPEED_100MHz_PCIX = 3,\n\tPCI_SPEED_133MHz_PCIX = 4,\n\tPCI_SPEED_66MHz_PCIX_ECC = 5,\n\tPCI_SPEED_100MHz_PCIX_ECC = 6,\n\tPCI_SPEED_133MHz_PCIX_ECC = 7,\n\tPCI_SPEED_66MHz_PCIX_266 = 9,\n\tPCI_SPEED_100MHz_PCIX_266 = 10,\n\tPCI_SPEED_133MHz_PCIX_266 = 11,\n\tAGP_UNKNOWN = 12,\n\tAGP_1X = 13,\n\tAGP_2X = 14,\n\tAGP_4X = 15,\n\tAGP_8X = 16,\n\tPCI_SPEED_66MHz_PCIX_533 = 17,\n\tPCI_SPEED_100MHz_PCIX_533 = 18,\n\tPCI_SPEED_133MHz_PCIX_533 = 19,\n\tPCIE_SPEED_2_5GT = 20,\n\tPCIE_SPEED_5_0GT = 21,\n\tPCIE_SPEED_8_0GT = 22,\n\tPCIE_SPEED_16_0GT = 23,\n\tPCIE_SPEED_32_0GT = 24,\n\tPCI_SPEED_UNKNOWN = 255,\n};\n\nstruct pci_host_bridge {\n\tstruct device dev;\n\tstruct pci_bus *bus;\n\tstruct pci_ops *ops;\n\tvoid *sysdata;\n\tint busnr;\n\tstruct list_head windows;\n\tstruct list_head dma_ranges;\n\tu8 (*swizzle_irq)(struct pci_dev *, u8 *);\n\tint (*map_irq)(const struct pci_dev *, u8, u8);\n\tvoid (*release_fn)(struct pci_host_bridge *);\n\tvoid *release_data;\n\tstruct msi_controller *msi;\n\tunsigned int ignore_reset_delay: 1;\n\tunsigned int no_ext_tags: 1;\n\tunsigned int native_aer: 1;\n\tunsigned int native_pcie_hotplug: 1;\n\tunsigned int native_shpc_hotplug: 1;\n\tunsigned int native_pme: 1;\n\tunsigned int native_ltr: 1;\n\tunsigned int native_dpc: 1;\n\tunsigned int preserve_config: 1;\n\tunsigned int size_windows: 1;\n\tresource_size_t (*align_resource)(struct pci_dev *, const struct resource *, resource_size_t, resource_size_t, resource_size_t);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong unsigned int private[0];\n};\n\nenum {\n\tPCI_REASSIGN_ALL_RSRC = 1,\n\tPCI_REASSIGN_ALL_BUS = 2,\n\tPCI_PROBE_ONLY = 4,\n\tPCI_CAN_SKIP_ISA_ALIGN = 8,\n\tPCI_ENABLE_PROC_DOMAINS = 16,\n\tPCI_COMPAT_DOMAIN_0 = 32,\n\tPCI_SCAN_ALL_PCIE_DEVS = 64,\n};\n\nstruct acpi_device_status {\n\tu32 present: 1;\n\tu32 enabled: 1;\n\tu32 show_in_ui: 1;\n\tu32 functional: 1;\n\tu32 battery_present: 1;\n\tu32 reserved: 27;\n};\n\nstruct acpi_device_flags {\n\tu32 dynamic_status: 1;\n\tu32 removable: 1;\n\tu32 ejectable: 1;\n\tu32 power_manageable: 1;\n\tu32 match_driver: 1;\n\tu32 initialized: 1;\n\tu32 visited: 1;\n\tu32 hotplug_notify: 1;\n\tu32 is_dock_station: 1;\n\tu32 of_compatible_ok: 1;\n\tu32 coherent_dma: 1;\n\tu32 cca_seen: 1;\n\tu32 enumeration_by_parent: 1;\n\tu32 reserved: 19;\n};\n\ntypedef char acpi_bus_id[8];\n\nstruct acpi_pnp_type {\n\tu32 hardware_id: 1;\n\tu32 bus_address: 1;\n\tu32 platform_id: 1;\n\tu32 reserved: 29;\n};\n\ntypedef u64 acpi_bus_address;\n\ntypedef char acpi_device_name[40];\n\ntypedef char acpi_device_class[20];\n\nunion acpi_object;\n\nstruct acpi_device_pnp {\n\tacpi_bus_id bus_id;\n\tstruct acpi_pnp_type type;\n\tacpi_bus_address bus_address;\n\tchar *unique_id;\n\tstruct list_head ids;\n\tacpi_device_name device_name;\n\tacpi_device_class device_class;\n\tunion acpi_object *str_obj;\n};\n\nstruct acpi_device_power_flags {\n\tu32 explicit_get: 1;\n\tu32 power_resources: 1;\n\tu32 inrush_current: 1;\n\tu32 power_removed: 1;\n\tu32 ignore_parent: 1;\n\tu32 dsw_present: 1;\n\tu32 reserved: 26;\n};\n\nstruct acpi_device_power_state {\n\tstruct {\n\t\tu8 valid: 1;\n\t\tu8 explicit_set: 1;\n\t\tu8 reserved: 6;\n\t} flags;\n\tint power;\n\tint latency;\n\tstruct list_head resources;\n};\n\nstruct acpi_device_power {\n\tint state;\n\tstruct acpi_device_power_flags flags;\n\tstruct acpi_device_power_state states[5];\n};\n\nstruct acpi_device_wakeup_flags {\n\tu8 valid: 1;\n\tu8 notifier_present: 1;\n};\n\nstruct acpi_device_wakeup_context {\n\tvoid (*func)(struct acpi_device_wakeup_context *);\n\tstruct device *dev;\n};\n\nstruct acpi_device_wakeup {\n\tacpi_handle gpe_device;\n\tu64 gpe_number;\n\tu64 sleep_state;\n\tstruct list_head resources;\n\tstruct acpi_device_wakeup_flags flags;\n\tstruct acpi_device_wakeup_context context;\n\tstruct wakeup_source *ws;\n\tint prepare_count;\n\tint enable_count;\n};\n\nstruct acpi_device_perf_flags {\n\tu8 reserved: 8;\n};\n\nstruct acpi_device_perf_state;\n\nstruct acpi_device_perf {\n\tint state;\n\tstruct acpi_device_perf_flags flags;\n\tint state_count;\n\tstruct acpi_device_perf_state *states;\n};\n\nstruct acpi_device_dir {\n\tstruct proc_dir_entry *entry;\n};\n\nstruct acpi_device_data {\n\tconst union acpi_object *pointer;\n\tstruct list_head properties;\n\tconst union acpi_object *of_compatible;\n\tstruct list_head subnodes;\n};\n\nstruct acpi_scan_handler;\n\nstruct acpi_hotplug_context;\n\nstruct acpi_driver;\n\nstruct acpi_gpio_mapping;\n\nstruct acpi_device {\n\tint device_type;\n\tacpi_handle handle;\n\tstruct fwnode_handle fwnode;\n\tstruct acpi_device *parent;\n\tstruct list_head children;\n\tstruct list_head node;\n\tstruct list_head wakeup_list;\n\tstruct list_head del_list;\n\tstruct acpi_device_status status;\n\tstruct acpi_device_flags flags;\n\tstruct acpi_device_pnp pnp;\n\tstruct acpi_device_power power;\n\tstruct acpi_device_wakeup wakeup;\n\tstruct acpi_device_perf performance;\n\tstruct acpi_device_dir dir;\n\tstruct acpi_device_data data;\n\tstruct acpi_scan_handler *handler;\n\tstruct acpi_hotplug_context *hp;\n\tstruct acpi_driver *driver;\n\tconst struct acpi_gpio_mapping *driver_gpios;\n\tvoid *driver_data;\n\tstruct device dev;\n\tunsigned int physical_node_count;\n\tunsigned int dep_unmet;\n\tstruct list_head physical_node_list;\n\tstruct mutex physical_node_lock;\n\tvoid (*remove)(struct acpi_device *);\n};\n\nstruct hotplug_slot_ops {\n\tint (*enable_slot)(struct hotplug_slot *);\n\tint (*disable_slot)(struct hotplug_slot *);\n\tint (*set_attention_status)(struct hotplug_slot *, u8);\n\tint (*hardware_test)(struct hotplug_slot *, u32);\n\tint (*get_power_status)(struct hotplug_slot *, u8 *);\n\tint (*get_attention_status)(struct hotplug_slot *, u8 *);\n\tint (*get_latch_status)(struct hotplug_slot *, u8 *);\n\tint (*get_adapter_status)(struct hotplug_slot *, u8 *);\n\tint (*reset_slot)(struct hotplug_slot *, int);\n};\n\ntypedef u64 acpi_io_address;\n\ntypedef u32 acpi_object_type;\n\nunion acpi_object {\n\tacpi_object_type type;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu64 value;\n\t} integer;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 length;\n\t\tchar *pointer;\n\t} string;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 length;\n\t\tu8 *pointer;\n\t} buffer;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 count;\n\t\tunion acpi_object *elements;\n\t} package;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tacpi_object_type actual_type;\n\t\tacpi_handle handle;\n\t} reference;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 proc_id;\n\t\tacpi_io_address pblk_address;\n\t\tu32 pblk_length;\n\t} processor;\n\tstruct {\n\t\tacpi_object_type type;\n\t\tu32 system_level;\n\t\tu32 resource_order;\n\t} power_resource;\n};\n\nstruct acpi_hotplug_profile {\n\tstruct kobject kobj;\n\tint (*scan_dependent)(struct acpi_device *);\n\tvoid (*notify_online)(struct acpi_device *);\n\tbool enabled: 1;\n\tbool demand_offline: 1;\n};\n\nstruct acpi_scan_handler {\n\tconst struct acpi_device_id *ids;\n\tstruct list_head list_node;\n\tbool (*match)(const char *, const struct acpi_device_id **);\n\tint (*attach)(struct acpi_device *, const struct acpi_device_id *);\n\tvoid (*detach)(struct acpi_device *);\n\tvoid (*bind)(struct device *);\n\tvoid (*unbind)(struct device *);\n\tstruct acpi_hotplug_profile hotplug;\n};\n\nstruct acpi_hotplug_context {\n\tstruct acpi_device *self;\n\tint (*notify)(struct acpi_device *, u32);\n\tvoid (*uevent)(struct acpi_device *, u32);\n\tvoid (*fixup)(struct acpi_device *);\n};\n\ntypedef int (*acpi_op_add)(struct acpi_device *);\n\ntypedef int (*acpi_op_remove)(struct acpi_device *);\n\ntypedef void (*acpi_op_notify)(struct acpi_device *, u32);\n\nstruct acpi_device_ops {\n\tacpi_op_add add;\n\tacpi_op_remove remove;\n\tacpi_op_notify notify;\n};\n\nstruct acpi_driver {\n\tchar name[80];\n\tchar class[80];\n\tconst struct acpi_device_id *ids;\n\tunsigned int flags;\n\tstruct acpi_device_ops ops;\n\tstruct device_driver drv;\n\tstruct module *owner;\n};\n\nstruct acpi_device_perf_state {\n\tstruct {\n\t\tu8 valid: 1;\n\t\tu8 reserved: 7;\n\t} flags;\n\tu8 power;\n\tu8 performance;\n\tint latency;\n};\n\nstruct acpi_gpio_params;\n\nstruct acpi_gpio_mapping {\n\tconst char *name;\n\tconst struct acpi_gpio_params *data;\n\tunsigned int size;\n\tunsigned int quirks;\n};\n\nenum pci_bar_type {\n\tpci_bar_unknown = 0,\n\tpci_bar_io = 1,\n\tpci_bar_mem32 = 2,\n\tpci_bar_mem64 = 3,\n};\n\nstruct pci_domain_busn_res {\n\tstruct list_head list;\n\tstruct resource res;\n\tint domain_nr;\n};\n\nstruct bus_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct bus_type *, char *);\n\tssize_t (*store)(struct bus_type *, const char *, size_t);\n};\n\nenum pcie_reset_state {\n\tpcie_deassert_reset = 1,\n\tpcie_warm_reset = 2,\n\tpcie_hot_reset = 3,\n};\n\nenum pcie_link_width {\n\tPCIE_LNK_WIDTH_RESRV = 0,\n\tPCIE_LNK_X1 = 1,\n\tPCIE_LNK_X2 = 2,\n\tPCIE_LNK_X4 = 4,\n\tPCIE_LNK_X8 = 8,\n\tPCIE_LNK_X12 = 12,\n\tPCIE_LNK_X16 = 16,\n\tPCIE_LNK_X32 = 32,\n\tPCIE_LNK_WIDTH_UNKNOWN = 255,\n};\n\nstruct pci_cap_saved_data {\n\tu16 cap_nr;\n\tbool cap_extended;\n\tunsigned int size;\n\tu32 data[0];\n};\n\nstruct pci_cap_saved_state {\n\tstruct hlist_node next;\n\tstruct pci_cap_saved_data cap;\n};\n\ntypedef int (*arch_set_vga_state_t)(struct pci_dev *, bool, unsigned int, u32);\n\nstruct pci_platform_pm_ops {\n\tbool (*bridge_d3)(struct pci_dev *);\n\tbool (*is_manageable)(struct pci_dev *);\n\tint (*set_state)(struct pci_dev *, pci_power_t);\n\tpci_power_t (*get_state)(struct pci_dev *);\n\tvoid (*refresh_state)(struct pci_dev *);\n\tpci_power_t (*choose_state)(struct pci_dev *);\n\tint (*set_wakeup)(struct pci_dev *, bool);\n\tbool (*need_resume)(struct pci_dev *);\n};\n\nstruct pci_pme_device {\n\tstruct list_head list;\n\tstruct pci_dev *dev;\n};\n\nstruct pci_saved_state {\n\tu32 config_space[16];\n\tstruct pci_cap_saved_data cap[0];\n};\n\nstruct pci_devres {\n\tunsigned int enabled: 1;\n\tunsigned int pinned: 1;\n\tunsigned int orig_intx: 1;\n\tunsigned int restore_intx: 1;\n\tunsigned int mwi: 1;\n\tu32 region_mask;\n};\n\nstruct driver_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct device_driver *, char *);\n\tssize_t (*store)(struct device_driver *, const char *, size_t);\n};\n\nenum pci_ers_result {\n\tPCI_ERS_RESULT_NONE = 1,\n\tPCI_ERS_RESULT_CAN_RECOVER = 2,\n\tPCI_ERS_RESULT_NEED_RESET = 3,\n\tPCI_ERS_RESULT_DISCONNECT = 4,\n\tPCI_ERS_RESULT_RECOVERED = 5,\n\tPCI_ERS_RESULT_NO_AER_DRIVER = 6,\n};\n\nstruct pcie_device {\n\tint irq;\n\tstruct pci_dev *port;\n\tu32 service;\n\tvoid *priv_data;\n\tstruct device device;\n};\n\nstruct pcie_port_service_driver {\n\tconst char *name;\n\tint (*probe)(struct pcie_device *);\n\tvoid (*remove)(struct pcie_device *);\n\tint (*suspend)(struct pcie_device *);\n\tint (*resume_noirq)(struct pcie_device *);\n\tint (*resume)(struct pcie_device *);\n\tint (*runtime_suspend)(struct pcie_device *);\n\tint (*runtime_resume)(struct pcie_device *);\n\tvoid (*error_resume)(struct pci_dev *);\n\tint port_type;\n\tu32 service;\n\tstruct device_driver driver;\n};\n\nstruct pci_dynid {\n\tstruct list_head node;\n\tstruct pci_device_id id;\n};\n\nstruct drv_dev_and_id {\n\tstruct pci_driver *drv;\n\tstruct pci_dev *dev;\n\tconst struct pci_device_id *id;\n};\n\nenum pci_mmap_state {\n\tpci_mmap_io = 0,\n\tpci_mmap_mem = 1,\n};\n\nenum pci_mmap_api {\n\tPCI_MMAP_SYSFS = 0,\n\tPCI_MMAP_PROCFS = 1,\n};\n\nenum pci_lost_interrupt_reason {\n\tPCI_LOST_IRQ_NO_INFORMATION = 0,\n\tPCI_LOST_IRQ_DISABLE_MSI = 1,\n\tPCI_LOST_IRQ_DISABLE_MSIX = 2,\n\tPCI_LOST_IRQ_DISABLE_ACPI = 3,\n};\n\nstruct pci_vpd_ops;\n\nstruct pci_vpd {\n\tconst struct pci_vpd_ops *ops;\n\tstruct bin_attribute *attr;\n\tstruct mutex lock;\n\tunsigned int len;\n\tu16 flag;\n\tu8 cap;\n\tunsigned int busy: 1;\n\tunsigned int valid: 1;\n};\n\nstruct pci_vpd_ops {\n\tssize_t (*read)(struct pci_dev *, loff_t, size_t, void *);\n\tssize_t (*write)(struct pci_dev *, loff_t, size_t, const void *);\n\tint (*set_size)(struct pci_dev *, size_t);\n};\n\nstruct pci_dev_resource {\n\tstruct list_head list;\n\tstruct resource *res;\n\tstruct pci_dev *dev;\n\tresource_size_t start;\n\tresource_size_t end;\n\tresource_size_t add_size;\n\tresource_size_t min_align;\n\tlong unsigned int flags;\n};\n\nenum release_type {\n\tleaf_only = 0,\n\twhole_subtree = 1,\n};\n\nenum enable_type {\n\tundefined = 4294967295,\n\tuser_disabled = 0,\n\tauto_disabled = 1,\n\tuser_enabled = 2,\n\tauto_enabled = 3,\n};\n\nstruct portdrv_service_data {\n\tstruct pcie_port_service_driver *drv;\n\tstruct device *dev;\n\tu32 service;\n};\n\ntypedef int (*pcie_pm_callback_t)(struct pcie_device *);\n\nstruct aspm_latency {\n\tu32 l0s;\n\tu32 l1;\n};\n\nstruct pcie_link_state {\n\tstruct pci_dev *pdev;\n\tstruct pci_dev *downstream;\n\tstruct pcie_link_state *root;\n\tstruct pcie_link_state *parent;\n\tstruct list_head sibling;\n\tu32 aspm_support: 7;\n\tu32 aspm_enabled: 7;\n\tu32 aspm_capable: 7;\n\tu32 aspm_default: 7;\n\tchar: 4;\n\tu32 aspm_disable: 7;\n\tu32 clkpm_capable: 1;\n\tu32 clkpm_enabled: 1;\n\tu32 clkpm_default: 1;\n\tu32 clkpm_disable: 1;\n\tstruct aspm_latency latency_up;\n\tstruct aspm_latency latency_dw;\n\tstruct aspm_latency acceptable[8];\n\tstruct {\n\t\tu32 up_cap_ptr;\n\t\tu32 dw_cap_ptr;\n\t\tu32 ctl1;\n\t\tu32 ctl2;\n\t} l1ss;\n};\n\nstruct aspm_register_info {\n\tu32 support: 2;\n\tu32 enabled: 2;\n\tu32 latency_encoding_l0s;\n\tu32 latency_encoding_l1;\n\tu32 l1ss_cap_ptr;\n\tu32 l1ss_cap;\n\tu32 l1ss_ctl1;\n\tu32 l1ss_ctl2;\n};\n\nstruct aer_stats {\n\tu64 dev_cor_errs[16];\n\tu64 dev_fatal_errs[27];\n\tu64 dev_nonfatal_errs[27];\n\tu64 dev_total_cor_errs;\n\tu64 dev_total_fatal_errs;\n\tu64 dev_total_nonfatal_errs;\n\tu64 rootport_total_cor_errs;\n\tu64 rootport_total_fatal_errs;\n\tu64 rootport_total_nonfatal_errs;\n};\n\nstruct aer_header_log_regs {\n\tunsigned int dw0;\n\tunsigned int dw1;\n\tunsigned int dw2;\n\tunsigned int dw3;\n};\n\nstruct aer_err_info {\n\tstruct pci_dev *dev[5];\n\tint error_dev_num;\n\tunsigned int id: 16;\n\tunsigned int severity: 2;\n\tunsigned int __pad1: 5;\n\tunsigned int multi_error_valid: 1;\n\tunsigned int first_error: 5;\n\tunsigned int __pad2: 2;\n\tunsigned int tlp_header_valid: 1;\n\tunsigned int status;\n\tunsigned int mask;\n\tstruct aer_header_log_regs tlp;\n};\n\nstruct aer_err_source {\n\tunsigned int status;\n\tunsigned int id;\n};\n\nstruct aer_rpc {\n\tstruct pci_dev *rpd;\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tstruct aer_err_source *type;\n\t\t\tconst struct aer_err_source *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tstruct aer_err_source *ptr;\n\t\t\tconst struct aer_err_source *ptr_const;\n\t\t};\n\t\tstruct aer_err_source buf[128];\n\t} aer_fifo;\n};\n\nstruct pcie_pme_service_data {\n\tspinlock_t lock;\n\tstruct pcie_device *srv;\n\tstruct work_struct work;\n\tbool noirq;\n};\n\nstruct pci_filp_private {\n\tenum pci_mmap_state mmap_state;\n\tint write_combine;\n};\n\nstruct pci_slot_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct pci_slot *, char *);\n\tssize_t (*store)(struct pci_slot *, const char *, size_t);\n};\n\ntypedef u64 acpi_size;\n\nstruct acpi_buffer {\n\tacpi_size length;\n\tvoid *pointer;\n};\n\nstruct acpi_bus_type {\n\tstruct list_head list;\n\tconst char *name;\n\tbool (*match)(struct device *);\n\tstruct acpi_device * (*find_companion)(struct device *);\n\tvoid (*setup)(struct device *);\n\tvoid (*cleanup)(struct device *);\n};\n\nstruct acpi_pci_root {\n\tstruct acpi_device *device;\n\tstruct pci_bus *bus;\n\tu16 segment;\n\tstruct resource secondary;\n\tu32 osc_support_set;\n\tu32 osc_control_set;\n\tphys_addr_t mcfg_addr;\n};\n\nenum pm_qos_flags_status {\n\tPM_QOS_FLAGS_UNDEFINED = 4294967295,\n\tPM_QOS_FLAGS_NONE = 0,\n\tPM_QOS_FLAGS_SOME = 1,\n\tPM_QOS_FLAGS_ALL = 2,\n};\n\nstruct hpx_type0 {\n\tu32 revision;\n\tu8 cache_line_size;\n\tu8 latency_timer;\n\tu8 enable_serr;\n\tu8 enable_perr;\n};\n\nstruct hpx_type1 {\n\tu32 revision;\n\tu8 max_mem_read;\n\tu8 avg_max_split;\n\tu16 tot_max_split;\n};\n\nstruct hpx_type2 {\n\tu32 revision;\n\tu32 unc_err_mask_and;\n\tu32 unc_err_mask_or;\n\tu32 unc_err_sever_and;\n\tu32 unc_err_sever_or;\n\tu32 cor_err_mask_and;\n\tu32 cor_err_mask_or;\n\tu32 adv_err_cap_and;\n\tu32 adv_err_cap_or;\n\tu16 pci_exp_devctl_and;\n\tu16 pci_exp_devctl_or;\n\tu16 pci_exp_lnkctl_and;\n\tu16 pci_exp_lnkctl_or;\n\tu32 sec_unc_err_sever_and;\n\tu32 sec_unc_err_sever_or;\n\tu32 sec_unc_err_mask_and;\n\tu32 sec_unc_err_mask_or;\n};\n\nstruct hpx_type3 {\n\tu16 device_type;\n\tu16 function_type;\n\tu16 config_space_location;\n\tu16 pci_exp_cap_id;\n\tu16 pci_exp_cap_ver;\n\tu16 pci_exp_vendor_id;\n\tu16 dvsec_id;\n\tu16 dvsec_rev;\n\tu16 match_offset;\n\tu32 match_mask_and;\n\tu32 match_value;\n\tu16 reg_offset;\n\tu32 reg_mask_and;\n\tu32 reg_mask_or;\n};\n\nenum hpx_type3_dev_type {\n\tHPX_TYPE_ENDPOINT = 1,\n\tHPX_TYPE_LEG_END = 2,\n\tHPX_TYPE_RC_END = 4,\n\tHPX_TYPE_RC_EC = 8,\n\tHPX_TYPE_ROOT_PORT = 16,\n\tHPX_TYPE_UPSTREAM = 32,\n\tHPX_TYPE_DOWNSTREAM = 64,\n\tHPX_TYPE_PCI_BRIDGE = 128,\n\tHPX_TYPE_PCIE_BRIDGE = 256,\n};\n\nenum hpx_type3_fn_type {\n\tHPX_FN_NORMAL = 1,\n\tHPX_FN_SRIOV_PHYS = 2,\n\tHPX_FN_SRIOV_VIRT = 4,\n};\n\nenum hpx_type3_cfg_loc {\n\tHPX_CFG_PCICFG = 0,\n\tHPX_CFG_PCIE_CAP = 1,\n\tHPX_CFG_PCIE_CAP_EXT = 2,\n\tHPX_CFG_VEND_CAP = 3,\n\tHPX_CFG_DVSEC = 4,\n\tHPX_CFG_MAX = 5,\n};\n\nenum pci_irq_reroute_variant {\n\tINTEL_IRQ_REROUTE_VARIANT = 1,\n\tMAX_IRQ_REROUTE_VARIANTS = 3,\n};\n\nstruct pci_fixup {\n\tu16 vendor;\n\tu16 device;\n\tu32 class;\n\tunsigned int class_shift;\n\tint hook_offset;\n};\n\nenum {\n\tNVME_REG_CAP = 0,\n\tNVME_REG_VS = 8,\n\tNVME_REG_INTMS = 12,\n\tNVME_REG_INTMC = 16,\n\tNVME_REG_CC = 20,\n\tNVME_REG_CSTS = 28,\n\tNVME_REG_NSSR = 32,\n\tNVME_REG_AQA = 36,\n\tNVME_REG_ASQ = 40,\n\tNVME_REG_ACQ = 48,\n\tNVME_REG_CMBLOC = 56,\n\tNVME_REG_CMBSZ = 60,\n\tNVME_REG_BPINFO = 64,\n\tNVME_REG_BPRSEL = 68,\n\tNVME_REG_BPMBL = 72,\n\tNVME_REG_PMRCAP = 3584,\n\tNVME_REG_PMRCTL = 3588,\n\tNVME_REG_PMRSTS = 3592,\n\tNVME_REG_PMREBS = 3596,\n\tNVME_REG_PMRSWTP = 3600,\n\tNVME_REG_DBS = 4096,\n};\n\nenum {\n\tNVME_CC_ENABLE = 1,\n\tNVME_CC_CSS_NVM = 0,\n\tNVME_CC_EN_SHIFT = 0,\n\tNVME_CC_CSS_SHIFT = 4,\n\tNVME_CC_MPS_SHIFT = 7,\n\tNVME_CC_AMS_SHIFT = 11,\n\tNVME_CC_SHN_SHIFT = 14,\n\tNVME_CC_IOSQES_SHIFT = 16,\n\tNVME_CC_IOCQES_SHIFT = 20,\n\tNVME_CC_AMS_RR = 0,\n\tNVME_CC_AMS_WRRU = 2048,\n\tNVME_CC_AMS_VS = 14336,\n\tNVME_CC_SHN_NONE = 0,\n\tNVME_CC_SHN_NORMAL = 16384,\n\tNVME_CC_SHN_ABRUPT = 32768,\n\tNVME_CC_SHN_MASK = 49152,\n\tNVME_CC_IOSQES = 393216,\n\tNVME_CC_IOCQES = 4194304,\n\tNVME_CSTS_RDY = 1,\n\tNVME_CSTS_CFS = 2,\n\tNVME_CSTS_NSSRO = 16,\n\tNVME_CSTS_PP = 32,\n\tNVME_CSTS_SHST_NORMAL = 0,\n\tNVME_CSTS_SHST_OCCUR = 4,\n\tNVME_CSTS_SHST_CMPLT = 8,\n\tNVME_CSTS_SHST_MASK = 12,\n};\n\nenum {\n\tNVME_AEN_BIT_NS_ATTR = 8,\n\tNVME_AEN_BIT_FW_ACT = 9,\n\tNVME_AEN_BIT_ANA_CHANGE = 11,\n\tNVME_AEN_BIT_DISC_CHANGE = 31,\n};\n\nenum {\n\tSWITCHTEC_GAS_MRPC_OFFSET = 0,\n\tSWITCHTEC_GAS_TOP_CFG_OFFSET = 4096,\n\tSWITCHTEC_GAS_SW_EVENT_OFFSET = 6144,\n\tSWITCHTEC_GAS_SYS_INFO_OFFSET = 8192,\n\tSWITCHTEC_GAS_FLASH_INFO_OFFSET = 8704,\n\tSWITCHTEC_GAS_PART_CFG_OFFSET = 16384,\n\tSWITCHTEC_GAS_NTB_OFFSET = 65536,\n\tSWITCHTEC_GAS_PFF_CSR_OFFSET = 1261568,\n};\n\nenum {\n\tSWITCHTEC_NTB_REG_INFO_OFFSET = 0,\n\tSWITCHTEC_NTB_REG_CTRL_OFFSET = 16384,\n\tSWITCHTEC_NTB_REG_DBMSG_OFFSET = 409600,\n};\n\nstruct nt_partition_info {\n\tu32 xlink_enabled;\n\tu32 target_part_low;\n\tu32 target_part_high;\n\tu32 reserved;\n};\n\nstruct ntb_info_regs {\n\tu8 partition_count;\n\tu8 partition_id;\n\tu16 reserved1;\n\tu64 ep_map;\n\tu16 requester_id;\n\tu16 reserved2;\n\tu32 reserved3[4];\n\tstruct nt_partition_info ntp_info[48];\n} __attribute__((packed));\n\nstruct ntb_ctrl_regs {\n\tu32 partition_status;\n\tu32 partition_op;\n\tu32 partition_ctrl;\n\tu32 bar_setup;\n\tu32 bar_error;\n\tu16 lut_table_entries;\n\tu16 lut_table_offset;\n\tu32 lut_error;\n\tu16 req_id_table_size;\n\tu16 req_id_table_offset;\n\tu32 req_id_error;\n\tu32 reserved1[7];\n\tstruct {\n\t\tu32 ctl;\n\t\tu32 win_size;\n\t\tu64 xlate_addr;\n\t} bar_entry[6];\n\tstruct {\n\t\tu32 win_size;\n\t\tu32 reserved[3];\n\t} bar_ext_entry[6];\n\tu32 reserved2[192];\n\tu32 req_id_table[512];\n\tu32 reserved3[256];\n\tu64 lut_entry[512];\n};\n\nstruct pci_dev_reset_methods {\n\tu16 vendor;\n\tu16 device;\n\tint (*reset)(struct pci_dev *, int);\n};\n\nstruct pci_dev_acs_enabled {\n\tu16 vendor;\n\tu16 device;\n\tint (*acs_enabled)(struct pci_dev *, u16);\n};\n\nstruct pci_dev_acs_ops {\n\tu16 vendor;\n\tu16 device;\n\tint (*enable_acs)(struct pci_dev *);\n\tint (*disable_acs_redir)(struct pci_dev *);\n};\n\nstruct msix_entry {\n\tu32 vector;\n\tu16 entry;\n};\n\nenum dmi_device_type {\n\tDMI_DEV_TYPE_ANY = 0,\n\tDMI_DEV_TYPE_OTHER = 1,\n\tDMI_DEV_TYPE_UNKNOWN = 2,\n\tDMI_DEV_TYPE_VIDEO = 3,\n\tDMI_DEV_TYPE_SCSI = 4,\n\tDMI_DEV_TYPE_ETHERNET = 5,\n\tDMI_DEV_TYPE_TOKENRING = 6,\n\tDMI_DEV_TYPE_SOUND = 7,\n\tDMI_DEV_TYPE_PATA = 8,\n\tDMI_DEV_TYPE_SATA = 9,\n\tDMI_DEV_TYPE_SAS = 10,\n\tDMI_DEV_TYPE_IPMI = 4294967295,\n\tDMI_DEV_TYPE_OEM_STRING = 4294967294,\n\tDMI_DEV_TYPE_DEV_ONBOARD = 4294967293,\n\tDMI_DEV_TYPE_DEV_SLOT = 4294967292,\n};\n\nstruct dmi_device {\n\tstruct list_head list;\n\tint type;\n\tconst char *name;\n\tvoid *device_data;\n};\n\nstruct dmi_dev_onboard {\n\tstruct dmi_device dev;\n\tint instance;\n\tint segment;\n\tint bus;\n\tint devfn;\n};\n\nenum smbios_attr_enum {\n\tSMBIOS_ATTR_NONE = 0,\n\tSMBIOS_ATTR_LABEL_SHOW = 1,\n\tSMBIOS_ATTR_INSTANCE_SHOW = 2,\n};\n\nenum acpi_attr_enum {\n\tACPI_ATTR_LABEL_SHOW = 0,\n\tACPI_ATTR_INDEX_SHOW = 1,\n};\n\nenum hdmi_infoframe_type {\n\tHDMI_INFOFRAME_TYPE_VENDOR = 129,\n\tHDMI_INFOFRAME_TYPE_AVI = 130,\n\tHDMI_INFOFRAME_TYPE_SPD = 131,\n\tHDMI_INFOFRAME_TYPE_AUDIO = 132,\n\tHDMI_INFOFRAME_TYPE_DRM = 135,\n};\n\nstruct hdmi_any_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n};\n\nenum hdmi_colorspace {\n\tHDMI_COLORSPACE_RGB = 0,\n\tHDMI_COLORSPACE_YUV422 = 1,\n\tHDMI_COLORSPACE_YUV444 = 2,\n\tHDMI_COLORSPACE_YUV420 = 3,\n\tHDMI_COLORSPACE_RESERVED4 = 4,\n\tHDMI_COLORSPACE_RESERVED5 = 5,\n\tHDMI_COLORSPACE_RESERVED6 = 6,\n\tHDMI_COLORSPACE_IDO_DEFINED = 7,\n};\n\nenum hdmi_scan_mode {\n\tHDMI_SCAN_MODE_NONE = 0,\n\tHDMI_SCAN_MODE_OVERSCAN = 1,\n\tHDMI_SCAN_MODE_UNDERSCAN = 2,\n\tHDMI_SCAN_MODE_RESERVED = 3,\n};\n\nenum hdmi_colorimetry {\n\tHDMI_COLORIMETRY_NONE = 0,\n\tHDMI_COLORIMETRY_ITU_601 = 1,\n\tHDMI_COLORIMETRY_ITU_709 = 2,\n\tHDMI_COLORIMETRY_EXTENDED = 3,\n};\n\nenum hdmi_picture_aspect {\n\tHDMI_PICTURE_ASPECT_NONE = 0,\n\tHDMI_PICTURE_ASPECT_4_3 = 1,\n\tHDMI_PICTURE_ASPECT_16_9 = 2,\n\tHDMI_PICTURE_ASPECT_64_27 = 3,\n\tHDMI_PICTURE_ASPECT_256_135 = 4,\n\tHDMI_PICTURE_ASPECT_RESERVED = 5,\n};\n\nenum hdmi_active_aspect {\n\tHDMI_ACTIVE_ASPECT_16_9_TOP = 2,\n\tHDMI_ACTIVE_ASPECT_14_9_TOP = 3,\n\tHDMI_ACTIVE_ASPECT_16_9_CENTER = 4,\n\tHDMI_ACTIVE_ASPECT_PICTURE = 8,\n\tHDMI_ACTIVE_ASPECT_4_3 = 9,\n\tHDMI_ACTIVE_ASPECT_16_9 = 10,\n\tHDMI_ACTIVE_ASPECT_14_9 = 11,\n\tHDMI_ACTIVE_ASPECT_4_3_SP_14_9 = 13,\n\tHDMI_ACTIVE_ASPECT_16_9_SP_14_9 = 14,\n\tHDMI_ACTIVE_ASPECT_16_9_SP_4_3 = 15,\n};\n\nenum hdmi_extended_colorimetry {\n\tHDMI_EXTENDED_COLORIMETRY_XV_YCC_601 = 0,\n\tHDMI_EXTENDED_COLORIMETRY_XV_YCC_709 = 1,\n\tHDMI_EXTENDED_COLORIMETRY_S_YCC_601 = 2,\n\tHDMI_EXTENDED_COLORIMETRY_OPYCC_601 = 3,\n\tHDMI_EXTENDED_COLORIMETRY_OPRGB = 4,\n\tHDMI_EXTENDED_COLORIMETRY_BT2020_CONST_LUM = 5,\n\tHDMI_EXTENDED_COLORIMETRY_BT2020 = 6,\n\tHDMI_EXTENDED_COLORIMETRY_RESERVED = 7,\n};\n\nenum hdmi_quantization_range {\n\tHDMI_QUANTIZATION_RANGE_DEFAULT = 0,\n\tHDMI_QUANTIZATION_RANGE_LIMITED = 1,\n\tHDMI_QUANTIZATION_RANGE_FULL = 2,\n\tHDMI_QUANTIZATION_RANGE_RESERVED = 3,\n};\n\nenum hdmi_nups {\n\tHDMI_NUPS_UNKNOWN = 0,\n\tHDMI_NUPS_HORIZONTAL = 1,\n\tHDMI_NUPS_VERTICAL = 2,\n\tHDMI_NUPS_BOTH = 3,\n};\n\nenum hdmi_ycc_quantization_range {\n\tHDMI_YCC_QUANTIZATION_RANGE_LIMITED = 0,\n\tHDMI_YCC_QUANTIZATION_RANGE_FULL = 1,\n};\n\nenum hdmi_content_type {\n\tHDMI_CONTENT_TYPE_GRAPHICS = 0,\n\tHDMI_CONTENT_TYPE_PHOTO = 1,\n\tHDMI_CONTENT_TYPE_CINEMA = 2,\n\tHDMI_CONTENT_TYPE_GAME = 3,\n};\n\nenum hdmi_metadata_type {\n\tHDMI_STATIC_METADATA_TYPE1 = 1,\n};\n\nenum hdmi_eotf {\n\tHDMI_EOTF_TRADITIONAL_GAMMA_SDR = 0,\n\tHDMI_EOTF_TRADITIONAL_GAMMA_HDR = 1,\n\tHDMI_EOTF_SMPTE_ST2084 = 2,\n\tHDMI_EOTF_BT_2100_HLG = 3,\n};\n\nstruct hdmi_avi_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tenum hdmi_colorspace colorspace;\n\tenum hdmi_scan_mode scan_mode;\n\tenum hdmi_colorimetry colorimetry;\n\tenum hdmi_picture_aspect picture_aspect;\n\tenum hdmi_active_aspect active_aspect;\n\tbool itc;\n\tenum hdmi_extended_colorimetry extended_colorimetry;\n\tenum hdmi_quantization_range quantization_range;\n\tenum hdmi_nups nups;\n\tunsigned char video_code;\n\tenum hdmi_ycc_quantization_range ycc_quantization_range;\n\tenum hdmi_content_type content_type;\n\tunsigned char pixel_repeat;\n\tshort unsigned int top_bar;\n\tshort unsigned int bottom_bar;\n\tshort unsigned int left_bar;\n\tshort unsigned int right_bar;\n};\n\nstruct hdmi_drm_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tenum hdmi_eotf eotf;\n\tenum hdmi_metadata_type metadata_type;\n\tstruct {\n\t\tu16 x;\n\t\tu16 y;\n\t} display_primaries[3];\n\tstruct {\n\t\tu16 x;\n\t\tu16 y;\n\t} white_point;\n\tu16 max_display_mastering_luminance;\n\tu16 min_display_mastering_luminance;\n\tu16 max_cll;\n\tu16 max_fall;\n};\n\nenum hdmi_spd_sdi {\n\tHDMI_SPD_SDI_UNKNOWN = 0,\n\tHDMI_SPD_SDI_DSTB = 1,\n\tHDMI_SPD_SDI_DVDP = 2,\n\tHDMI_SPD_SDI_DVHS = 3,\n\tHDMI_SPD_SDI_HDDVR = 4,\n\tHDMI_SPD_SDI_DVC = 5,\n\tHDMI_SPD_SDI_DSC = 6,\n\tHDMI_SPD_SDI_VCD = 7,\n\tHDMI_SPD_SDI_GAME = 8,\n\tHDMI_SPD_SDI_PC = 9,\n\tHDMI_SPD_SDI_BD = 10,\n\tHDMI_SPD_SDI_SACD = 11,\n\tHDMI_SPD_SDI_HDDVD = 12,\n\tHDMI_SPD_SDI_PMP = 13,\n};\n\nstruct hdmi_spd_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tchar vendor[8];\n\tchar product[16];\n\tenum hdmi_spd_sdi sdi;\n};\n\nenum hdmi_audio_coding_type {\n\tHDMI_AUDIO_CODING_TYPE_STREAM = 0,\n\tHDMI_AUDIO_CODING_TYPE_PCM = 1,\n\tHDMI_AUDIO_CODING_TYPE_AC3 = 2,\n\tHDMI_AUDIO_CODING_TYPE_MPEG1 = 3,\n\tHDMI_AUDIO_CODING_TYPE_MP3 = 4,\n\tHDMI_AUDIO_CODING_TYPE_MPEG2 = 5,\n\tHDMI_AUDIO_CODING_TYPE_AAC_LC = 6,\n\tHDMI_AUDIO_CODING_TYPE_DTS = 7,\n\tHDMI_AUDIO_CODING_TYPE_ATRAC = 8,\n\tHDMI_AUDIO_CODING_TYPE_DSD = 9,\n\tHDMI_AUDIO_CODING_TYPE_EAC3 = 10,\n\tHDMI_AUDIO_CODING_TYPE_DTS_HD = 11,\n\tHDMI_AUDIO_CODING_TYPE_MLP = 12,\n\tHDMI_AUDIO_CODING_TYPE_DST = 13,\n\tHDMI_AUDIO_CODING_TYPE_WMA_PRO = 14,\n\tHDMI_AUDIO_CODING_TYPE_CXT = 15,\n};\n\nenum hdmi_audio_sample_size {\n\tHDMI_AUDIO_SAMPLE_SIZE_STREAM = 0,\n\tHDMI_AUDIO_SAMPLE_SIZE_16 = 1,\n\tHDMI_AUDIO_SAMPLE_SIZE_20 = 2,\n\tHDMI_AUDIO_SAMPLE_SIZE_24 = 3,\n};\n\nenum hdmi_audio_sample_frequency {\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_STREAM = 0,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_32000 = 1,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_44100 = 2,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_48000 = 3,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_88200 = 4,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_96000 = 5,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_176400 = 6,\n\tHDMI_AUDIO_SAMPLE_FREQUENCY_192000 = 7,\n};\n\nenum hdmi_audio_coding_type_ext {\n\tHDMI_AUDIO_CODING_TYPE_EXT_CT = 0,\n\tHDMI_AUDIO_CODING_TYPE_EXT_HE_AAC = 1,\n\tHDMI_AUDIO_CODING_TYPE_EXT_HE_AAC_V2 = 2,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG_SURROUND = 3,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC = 4,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_V2 = 5,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC = 6,\n\tHDMI_AUDIO_CODING_TYPE_EXT_DRA = 7,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_SURROUND = 8,\n\tHDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC_SURROUND = 10,\n};\n\nstruct hdmi_audio_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tunsigned char channels;\n\tenum hdmi_audio_coding_type coding_type;\n\tenum hdmi_audio_sample_size sample_size;\n\tenum hdmi_audio_sample_frequency sample_frequency;\n\tenum hdmi_audio_coding_type_ext coding_type_ext;\n\tunsigned char channel_allocation;\n\tunsigned char level_shift_value;\n\tbool downmix_inhibit;\n};\n\nenum hdmi_3d_structure {\n\tHDMI_3D_STRUCTURE_INVALID = 4294967295,\n\tHDMI_3D_STRUCTURE_FRAME_PACKING = 0,\n\tHDMI_3D_STRUCTURE_FIELD_ALTERNATIVE = 1,\n\tHDMI_3D_STRUCTURE_LINE_ALTERNATIVE = 2,\n\tHDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL = 3,\n\tHDMI_3D_STRUCTURE_L_DEPTH = 4,\n\tHDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH = 5,\n\tHDMI_3D_STRUCTURE_TOP_AND_BOTTOM = 6,\n\tHDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF = 8,\n};\n\nstruct hdmi_vendor_infoframe {\n\tenum hdmi_infoframe_type type;\n\tunsigned char version;\n\tunsigned char length;\n\tunsigned int oui;\n\tu8 vic;\n\tenum hdmi_3d_structure s3d_struct;\n\tunsigned int s3d_ext_data;\n};\n\nunion hdmi_vendor_any_infoframe {\n\tstruct {\n\t\tenum hdmi_infoframe_type type;\n\t\tunsigned char version;\n\t\tunsigned char length;\n\t\tunsigned int oui;\n\t} any;\n\tstruct hdmi_vendor_infoframe hdmi;\n};\n\nunion hdmi_infoframe {\n\tstruct hdmi_any_infoframe any;\n\tstruct hdmi_avi_infoframe avi;\n\tstruct hdmi_spd_infoframe spd;\n\tunion hdmi_vendor_any_infoframe vendor;\n\tstruct hdmi_audio_infoframe audio;\n\tstruct hdmi_drm_infoframe drm;\n};\n\nstruct vgastate {\n\tvoid *vgabase;\n\tlong unsigned int membase;\n\t__u32 memsize;\n\t__u32 flags;\n\t__u32 depth;\n\t__u32 num_attr;\n\t__u32 num_crtc;\n\t__u32 num_gfx;\n\t__u32 num_seq;\n\tvoid *vidstate;\n};\n\nstruct vgacon_scrollback_info {\n\tvoid *data;\n\tint tail;\n\tint size;\n\tint rows;\n\tint cnt;\n\tint cur;\n\tint save;\n\tint restore;\n};\n\nstruct linux_logo {\n\tint type;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int clutsize;\n\tconst unsigned char *clut;\n\tconst unsigned char *data;\n};\n\nenum {\n\tFB_BLANK_UNBLANK = 0,\n\tFB_BLANK_NORMAL = 1,\n\tFB_BLANK_VSYNC_SUSPEND = 2,\n\tFB_BLANK_HSYNC_SUSPEND = 3,\n\tFB_BLANK_POWERDOWN = 4,\n};\n\nstruct fb_event {\n\tstruct fb_info *info;\n\tvoid *data;\n};\n\nenum backlight_update_reason {\n\tBACKLIGHT_UPDATE_HOTKEY = 0,\n\tBACKLIGHT_UPDATE_SYSFS = 1,\n};\n\nenum backlight_type {\n\tBACKLIGHT_RAW = 1,\n\tBACKLIGHT_PLATFORM = 2,\n\tBACKLIGHT_FIRMWARE = 3,\n\tBACKLIGHT_TYPE_MAX = 4,\n};\n\nenum backlight_notification {\n\tBACKLIGHT_REGISTERED = 0,\n\tBACKLIGHT_UNREGISTERED = 1,\n};\n\nenum backlight_scale {\n\tBACKLIGHT_SCALE_UNKNOWN = 0,\n\tBACKLIGHT_SCALE_LINEAR = 1,\n\tBACKLIGHT_SCALE_NON_LINEAR = 2,\n};\n\nstruct backlight_device;\n\nstruct backlight_ops {\n\tunsigned int options;\n\tint (*update_status)(struct backlight_device *);\n\tint (*get_brightness)(struct backlight_device *);\n\tint (*check_fb)(struct backlight_device *, struct fb_info *);\n};\n\nstruct backlight_properties {\n\tint brightness;\n\tint max_brightness;\n\tint power;\n\tint fb_blank;\n\tenum backlight_type type;\n\tunsigned int state;\n\tenum backlight_scale scale;\n};\n\nstruct backlight_device {\n\tstruct backlight_properties props;\n\tstruct mutex update_lock;\n\tstruct mutex ops_lock;\n\tconst struct backlight_ops *ops;\n\tstruct notifier_block fb_notif;\n\tstruct list_head entry;\n\tstruct device dev;\n\tbool fb_bl_on[32];\n\tint use_count;\n};\n\nstruct generic_bl_info {\n\tconst char *name;\n\tint max_intensity;\n\tint default_intensity;\n\tint limit_mask;\n\tvoid (*set_bl_intensity)(int);\n\tvoid (*kick_battery)();\n};\n\nstruct fb_cmap_user {\n\t__u32 start;\n\t__u32 len;\n\t__u16 *red;\n\t__u16 *green;\n\t__u16 *blue;\n\t__u16 *transp;\n};\n\nstruct fb_modelist {\n\tstruct list_head list;\n\tstruct fb_videomode mode;\n};\n\nstruct logo_data {\n\tint depth;\n\tint needs_directpalette;\n\tint needs_truepalette;\n\tint needs_cmapreset;\n\tconst struct linux_logo *logo;\n};\n\nstruct fb_fix_screeninfo32 {\n\tchar id[16];\n\tcompat_caddr_t smem_start;\n\tu32 smem_len;\n\tu32 type;\n\tu32 type_aux;\n\tu32 visual;\n\tu16 xpanstep;\n\tu16 ypanstep;\n\tu16 ywrapstep;\n\tu32 line_length;\n\tcompat_caddr_t mmio_start;\n\tu32 mmio_len;\n\tu32 accel;\n\tu16 reserved[3];\n};\n\nstruct fb_cmap32 {\n\tu32 start;\n\tu32 len;\n\tcompat_caddr_t red;\n\tcompat_caddr_t green;\n\tcompat_caddr_t blue;\n\tcompat_caddr_t transp;\n};\n\nstruct broken_edid {\n\tu8 manufacturer[4];\n\tu32 model;\n\tu32 fix;\n};\n\nstruct __fb_timings {\n\tu32 dclk;\n\tu32 hfreq;\n\tu32 vfreq;\n\tu32 hactive;\n\tu32 vactive;\n\tu32 hblank;\n\tu32 vblank;\n\tu32 htotal;\n\tu32 vtotal;\n};\n\nstruct fb_cvt_data {\n\tu32 xres;\n\tu32 yres;\n\tu32 refresh;\n\tu32 f_refresh;\n\tu32 pixclock;\n\tu32 hperiod;\n\tu32 hblank;\n\tu32 hfreq;\n\tu32 htotal;\n\tu32 vtotal;\n\tu32 vsync;\n\tu32 hsync;\n\tu32 h_front_porch;\n\tu32 h_back_porch;\n\tu32 v_front_porch;\n\tu32 v_back_porch;\n\tu32 h_margin;\n\tu32 v_margin;\n\tu32 interlace;\n\tu32 aspect_ratio;\n\tu32 active_pixels;\n\tu32 flags;\n\tu32 status;\n};\n\ntypedef unsigned char u_char;\n\ntypedef short unsigned int u_short;\n\nstruct fb_con2fbmap {\n\t__u32 console;\n\t__u32 framebuffer;\n};\n\nstruct fbcon_display {\n\tconst u_char *fontdata;\n\tint userfont;\n\tu_short scrollmode;\n\tu_short inverse;\n\tshort int yscroll;\n\tint vrows;\n\tint cursor_shape;\n\tint con_rotate;\n\tu32 xres_virtual;\n\tu32 yres_virtual;\n\tu32 height;\n\tu32 width;\n\tu32 bits_per_pixel;\n\tu32 grayscale;\n\tu32 nonstd;\n\tu32 accel_flags;\n\tu32 rotate;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\tconst struct fb_videomode *mode;\n};\n\nstruct fbcon_ops {\n\tvoid (*bmove)(struct vc_data *, struct fb_info *, int, int, int, int, int, int);\n\tvoid (*clear)(struct vc_data *, struct fb_info *, int, int, int, int);\n\tvoid (*putcs)(struct vc_data *, struct fb_info *, const short unsigned int *, int, int, int, int, int);\n\tvoid (*clear_margins)(struct vc_data *, struct fb_info *, int, int);\n\tvoid (*cursor)(struct vc_data *, struct fb_info *, int, int, int, int);\n\tint (*update_start)(struct fb_info *);\n\tint (*rotate_font)(struct fb_info *, struct vc_data *);\n\tstruct fb_var_screeninfo var;\n\tstruct timer_list cursor_timer;\n\tstruct fb_cursor cursor_state;\n\tstruct fbcon_display *p;\n\tstruct fb_info *info;\n\tint currcon;\n\tint cur_blink_jiffies;\n\tint cursor_flash;\n\tint cursor_reset;\n\tint blank_state;\n\tint graphics;\n\tint save_graphics;\n\tint flags;\n\tint rotate;\n\tint cur_rotate;\n\tchar *cursor_data;\n\tu8 *fontbuffer;\n\tu8 *fontdata;\n\tu8 *cursor_src;\n\tu32 cursor_size;\n\tu32 fd_size;\n};\n\nenum {\n\tFBCON_LOGO_CANSHOW = 4294967295,\n\tFBCON_LOGO_DRAW = 4294967294,\n\tFBCON_LOGO_DONTSHOW = 4294967293,\n};\n\nenum drm_panel_orientation {\n\tDRM_MODE_PANEL_ORIENTATION_UNKNOWN = 4294967295,\n\tDRM_MODE_PANEL_ORIENTATION_NORMAL = 0,\n\tDRM_MODE_PANEL_ORIENTATION_BOTTOM_UP = 1,\n\tDRM_MODE_PANEL_ORIENTATION_LEFT_UP = 2,\n\tDRM_MODE_PANEL_ORIENTATION_RIGHT_UP = 3,\n};\n\ntypedef u16 acpi_owner_id;\n\nunion acpi_name_union {\n\tu32 integer;\n\tchar ascii[4];\n};\n\nstruct acpi_table_desc {\n\tacpi_physical_address address;\n\tstruct acpi_table_header *pointer;\n\tu32 length;\n\tunion acpi_name_union signature;\n\tacpi_owner_id owner_id;\n\tu8 flags;\n\tu16 validation_count;\n};\n\nstruct acpi_madt_io_sapic {\n\tstruct acpi_subtable_header header;\n\tu8 id;\n\tu8 reserved;\n\tu32 global_irq_base;\n\tu64 address;\n};\n\nstruct acpi_madt_interrupt_source {\n\tstruct acpi_subtable_header header;\n\tu16 inti_flags;\n\tu8 type;\n\tu8 id;\n\tu8 eid;\n\tu8 io_sapic_vector;\n\tu32 global_irq;\n\tu32 flags;\n};\n\nstruct acpi_madt_generic_interrupt {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 cpu_interface_number;\n\tu32 uid;\n\tu32 flags;\n\tu32 parking_version;\n\tu32 performance_interrupt;\n\tu64 parked_address;\n\tu64 base_address;\n\tu64 gicv_base_address;\n\tu64 gich_base_address;\n\tu32 vgic_interrupt;\n\tu64 gicr_base_address;\n\tu64 arm_mpidr;\n\tu8 efficiency_class;\n\tu8 reserved2[1];\n\tu16 spe_interrupt;\n} __attribute__((packed));\n\nstruct acpi_madt_generic_distributor {\n\tstruct acpi_subtable_header header;\n\tu16 reserved;\n\tu32 gic_id;\n\tu64 base_address;\n\tu32 global_irq_base;\n\tu8 version;\n\tu8 reserved2[3];\n};\n\ntypedef int (*acpi_tbl_table_handler)(struct acpi_table_header *);\n\nstruct transaction;\n\nstruct acpi_ec {\n\tacpi_handle handle;\n\tint gpe;\n\tint irq;\n\tlong unsigned int command_addr;\n\tlong unsigned int data_addr;\n\tbool global_lock;\n\tlong unsigned int flags;\n\tlong unsigned int reference_count;\n\tstruct mutex mutex;\n\twait_queue_head_t wait;\n\tstruct list_head list;\n\tstruct transaction *curr;\n\tspinlock_t lock;\n\tstruct work_struct work;\n\tlong unsigned int timestamp;\n\tlong unsigned int nr_pending_queries;\n\tbool busy_polling;\n\tunsigned int polling_guard;\n};\n\nenum acpi_subtable_type {\n\tACPI_SUBTABLE_COMMON = 0,\n\tACPI_SUBTABLE_HMAT = 1,\n};\n\nstruct acpi_subtable_entry {\n\tunion acpi_subtable_headers *hdr;\n\tenum acpi_subtable_type type;\n};\n\nenum acpi_predicate {\n\tall_versions = 0,\n\tless_than_or_equal = 1,\n\tequal = 2,\n\tgreater_than_or_equal = 3,\n};\n\nstruct acpi_platform_list {\n\tchar oem_id[7];\n\tchar oem_table_id[9];\n\tu32 oem_revision;\n\tchar *table;\n\tenum acpi_predicate pred;\n\tchar *reason;\n\tu32 data;\n};\n\ntypedef char *acpi_string;\n\nstruct acpi_osi_entry {\n\tchar string[64];\n\tbool enable;\n};\n\nstruct acpi_osi_config {\n\tu8 default_disabling;\n\tunsigned int linux_enable: 1;\n\tunsigned int linux_dmi: 1;\n\tunsigned int linux_cmdline: 1;\n\tunsigned int darwin_enable: 1;\n\tunsigned int darwin_dmi: 1;\n\tunsigned int darwin_cmdline: 1;\n};\n\ntypedef u32 acpi_name;\n\nstruct acpi_predefined_names {\n\tconst char *name;\n\tu8 type;\n\tchar *val;\n};\n\ntypedef u32 (*acpi_osd_handler)(void *);\n\ntypedef void (*acpi_osd_exec_callback)(void *);\n\ntypedef u32 (*acpi_sci_handler)(void *);\n\ntypedef void (*acpi_gbl_event_handler)(u32, acpi_handle, u32, void *);\n\ntypedef u32 (*acpi_event_handler)(void *);\n\ntypedef u32 (*acpi_gpe_handler)(acpi_handle, u32, void *);\n\ntypedef void (*acpi_notify_handler)(acpi_handle, u32, void *);\n\ntypedef void (*acpi_object_handler)(acpi_handle, void *);\n\ntypedef acpi_status (*acpi_init_handler)(acpi_handle, u32);\n\ntypedef acpi_status (*acpi_exception_handler)(acpi_status, acpi_name, u16, u32, void *);\n\ntypedef acpi_status (*acpi_table_handler)(u32, void *, void *);\n\ntypedef acpi_status (*acpi_adr_space_handler)(u32, acpi_physical_address, u32, u64 *, void *, void *);\n\ntypedef acpi_status (*acpi_adr_space_setup)(acpi_handle, u32, void *, void **);\n\ntypedef u32 (*acpi_interface_handler)(acpi_string, u32);\n\nstruct acpi_pci_id {\n\tu16 segment;\n\tu16 bus;\n\tu16 device;\n\tu16 function;\n};\n\nstruct acpi_mem_space_context {\n\tu32 length;\n\tacpi_physical_address address;\n\tacpi_physical_address mapped_physical_address;\n\tu8 *mapped_logical_address;\n\tacpi_size mapped_length;\n};\n\nstruct acpi_table_facs {\n\tchar signature[4];\n\tu32 length;\n\tu32 hardware_signature;\n\tu32 firmware_waking_vector;\n\tu32 global_lock;\n\tu32 flags;\n\tu64 xfirmware_waking_vector;\n\tu8 version;\n\tu8 reserved[3];\n\tu32 ospm_flags;\n\tu8 reserved1[24];\n};\n\ntypedef enum {\n\tOSL_GLOBAL_LOCK_HANDLER = 0,\n\tOSL_NOTIFY_HANDLER = 1,\n\tOSL_GPE_HANDLER = 2,\n\tOSL_DEBUGGER_MAIN_THREAD = 3,\n\tOSL_DEBUGGER_EXEC_THREAD = 4,\n\tOSL_EC_POLL_HANDLER = 5,\n\tOSL_EC_BURST_HANDLER = 6,\n} acpi_execute_type;\n\nstruct acpi_gpio_params {\n\tunsigned int crs_entry_index;\n\tunsigned int line_index;\n\tbool active_low;\n};\n\nstruct acpi_rw_lock {\n\tvoid *writer_mutex;\n\tvoid *reader_mutex;\n\tu32 num_readers;\n};\n\nstruct acpi_mutex_info {\n\tvoid *mutex;\n\tu32 use_count;\n\tu64 thread_id;\n};\n\nunion acpi_operand_object;\n\nstruct acpi_namespace_node {\n\tunion acpi_operand_object *object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 flags;\n\tunion acpi_name_union name;\n\tstruct acpi_namespace_node *parent;\n\tstruct acpi_namespace_node *child;\n\tstruct acpi_namespace_node *peer;\n\tacpi_owner_id owner_id;\n};\n\nstruct acpi_object_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n};\n\nstruct acpi_object_integer {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 fill[3];\n\tu64 value;\n};\n\nstruct acpi_object_string {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tchar *pointer;\n\tu32 length;\n};\n\nstruct acpi_object_buffer {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 *pointer;\n\tu32 length;\n\tu32 aml_length;\n\tu8 *aml_start;\n\tstruct acpi_namespace_node *node;\n};\n\nstruct acpi_object_package {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object **elements;\n\tu8 *aml_start;\n\tu32 aml_length;\n\tu32 count;\n};\n\nstruct acpi_object_event {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tvoid *os_semaphore;\n};\n\nstruct acpi_walk_state;\n\ntypedef acpi_status (*acpi_internal_method)(struct acpi_walk_state *);\n\nstruct acpi_object_method {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 info_flags;\n\tu8 param_count;\n\tu8 sync_level;\n\tunion acpi_operand_object *mutex;\n\tunion acpi_operand_object *node;\n\tu8 *aml_start;\n\tunion {\n\t\tacpi_internal_method implementation;\n\t\tunion acpi_operand_object *handler;\n\t} dispatch;\n\tu32 aml_length;\n\tacpi_owner_id owner_id;\n\tu8 thread_count;\n};\n\nstruct acpi_thread_state;\n\nstruct acpi_object_mutex {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 sync_level;\n\tu16 acquisition_depth;\n\tvoid *os_mutex;\n\tu64 thread_id;\n\tstruct acpi_thread_state *owner_thread;\n\tunion acpi_operand_object *prev;\n\tunion acpi_operand_object *next;\n\tstruct acpi_namespace_node *node;\n\tu8 original_sync_level;\n};\n\nstruct acpi_object_region {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 space_id;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *handler;\n\tunion acpi_operand_object *next;\n\tacpi_physical_address address;\n\tu32 length;\n};\n\nstruct acpi_object_notify_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n};\n\nstruct acpi_gpe_block_info;\n\nstruct acpi_object_device {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tstruct acpi_gpe_block_info *gpe_block;\n};\n\nstruct acpi_object_power_resource {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tu32 system_level;\n\tu32 resource_order;\n};\n\nstruct acpi_object_processor {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 proc_id;\n\tu8 length;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n\tacpi_io_address address;\n};\n\nstruct acpi_object_thermal_zone {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *notify_list[2];\n\tunion acpi_operand_object *handler;\n};\n\nstruct acpi_object_field_common {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *region_obj;\n};\n\nstruct acpi_object_region_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tu16 resource_length;\n\tunion acpi_operand_object *region_obj;\n\tu8 *resource_buffer;\n\tu16 pin_number_index;\n\tu8 *internal_pcc_buffer;\n};\n\nstruct acpi_object_buffer_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tu8 is_create_field;\n\tunion acpi_operand_object *buffer_obj;\n};\n\nstruct acpi_object_bank_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *region_obj;\n\tunion acpi_operand_object *bank_obj;\n};\n\nstruct acpi_object_index_field {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 access_byte_width;\n\tstruct acpi_namespace_node *node;\n\tu32 bit_length;\n\tu32 base_byte_offset;\n\tu32 value;\n\tu8 start_field_bit_offset;\n\tu8 access_length;\n\tunion acpi_operand_object *index_obj;\n\tunion acpi_operand_object *data_obj;\n};\n\nstruct acpi_object_notify_handler {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *node;\n\tu32 handler_type;\n\tacpi_notify_handler handler;\n\tvoid *context;\n\tunion acpi_operand_object *next[2];\n};\n\nstruct acpi_object_addr_handler {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 space_id;\n\tu8 handler_flags;\n\tacpi_adr_space_handler handler;\n\tstruct acpi_namespace_node *node;\n\tvoid *context;\n\tacpi_adr_space_setup setup;\n\tunion acpi_operand_object *region_list;\n\tunion acpi_operand_object *next;\n};\n\nstruct acpi_object_reference {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tu8 class;\n\tu8 target_type;\n\tu8 resolved;\n\tvoid *object;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object **where;\n\tu8 *index_pointer;\n\tu8 *aml;\n\tu32 value;\n};\n\nstruct acpi_object_extra {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tstruct acpi_namespace_node *method_REG;\n\tstruct acpi_namespace_node *scope_node;\n\tvoid *region_context;\n\tu8 *aml_start;\n\tu32 aml_length;\n};\n\nstruct acpi_object_data {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tacpi_object_handler handler;\n\tvoid *pointer;\n};\n\nstruct acpi_object_cache_list {\n\tunion acpi_operand_object *next_object;\n\tu8 descriptor_type;\n\tu8 type;\n\tu16 reference_count;\n\tu8 flags;\n\tunion acpi_operand_object *next;\n};\n\nunion acpi_operand_object {\n\tstruct acpi_object_common common;\n\tstruct acpi_object_integer integer;\n\tstruct acpi_object_string string;\n\tstruct acpi_object_buffer buffer;\n\tstruct acpi_object_package package;\n\tstruct acpi_object_event event;\n\tstruct acpi_object_method method;\n\tstruct acpi_object_mutex mutex;\n\tstruct acpi_object_region region;\n\tstruct acpi_object_notify_common common_notify;\n\tstruct acpi_object_device device;\n\tstruct acpi_object_power_resource power_resource;\n\tstruct acpi_object_processor processor;\n\tstruct acpi_object_thermal_zone thermal_zone;\n\tstruct acpi_object_field_common common_field;\n\tstruct acpi_object_region_field field;\n\tstruct acpi_object_buffer_field buffer_field;\n\tstruct acpi_object_bank_field bank_field;\n\tstruct acpi_object_index_field index_field;\n\tstruct acpi_object_notify_handler notify;\n\tstruct acpi_object_addr_handler address_space;\n\tstruct acpi_object_reference reference;\n\tstruct acpi_object_extra extra;\n\tstruct acpi_object_data data;\n\tstruct acpi_object_cache_list cache;\n\tstruct acpi_namespace_node node;\n};\n\nstruct acpi_table_list {\n\tstruct acpi_table_desc *tables;\n\tu32 current_table_count;\n\tu32 max_table_count;\n\tu8 flags;\n};\n\nunion acpi_parse_object;\n\nunion acpi_generic_state;\n\nstruct acpi_parse_state {\n\tu8 *aml_start;\n\tu8 *aml;\n\tu8 *aml_end;\n\tu8 *pkg_start;\n\tu8 *pkg_end;\n\tunion acpi_parse_object *start_op;\n\tstruct acpi_namespace_node *start_node;\n\tunion acpi_generic_state *scope;\n\tunion acpi_parse_object *start_scope;\n\tu32 aml_size;\n};\n\ntypedef acpi_status (*acpi_parse_downwards)(struct acpi_walk_state *, union acpi_parse_object **);\n\ntypedef acpi_status (*acpi_parse_upwards)(struct acpi_walk_state *);\n\nstruct acpi_opcode_info;\n\nstruct acpi_walk_state {\n\tstruct acpi_walk_state *next;\n\tu8 descriptor_type;\n\tu8 walk_type;\n\tu16 opcode;\n\tu8 next_op_info;\n\tu8 num_operands;\n\tu8 operand_index;\n\tacpi_owner_id owner_id;\n\tu8 last_predicate;\n\tu8 current_result;\n\tu8 return_used;\n\tu8 scope_depth;\n\tu8 pass_number;\n\tu8 namespace_override;\n\tu8 result_size;\n\tu8 result_count;\n\tu8 *aml;\n\tu32 arg_types;\n\tu32 method_breakpoint;\n\tu32 user_breakpoint;\n\tu32 parse_flags;\n\tstruct acpi_parse_state parser_state;\n\tu32 prev_arg_types;\n\tu32 arg_count;\n\tu16 method_nesting_depth;\n\tu8 method_is_nested;\n\tstruct acpi_namespace_node arguments[7];\n\tstruct acpi_namespace_node local_variables[8];\n\tunion acpi_operand_object *operands[9];\n\tunion acpi_operand_object **params;\n\tu8 *aml_last_while;\n\tunion acpi_operand_object **caller_return_desc;\n\tunion acpi_generic_state *control_state;\n\tstruct acpi_namespace_node *deferred_node;\n\tunion acpi_operand_object *implicit_return_obj;\n\tstruct acpi_namespace_node *method_call_node;\n\tunion acpi_parse_object *method_call_op;\n\tunion acpi_operand_object *method_desc;\n\tstruct acpi_namespace_node *method_node;\n\tchar *method_pathname;\n\tunion acpi_parse_object *op;\n\tconst struct acpi_opcode_info *op_info;\n\tunion acpi_parse_object *origin;\n\tunion acpi_operand_object *result_obj;\n\tunion acpi_generic_state *results;\n\tunion acpi_operand_object *return_desc;\n\tunion acpi_generic_state *scope_info;\n\tunion acpi_parse_object *prev_op;\n\tunion acpi_parse_object *next_op;\n\tstruct acpi_thread_state *thread;\n\tacpi_parse_downwards descending_callback;\n\tacpi_parse_upwards ascending_callback;\n};\n\nstruct acpi_sci_handler_info {\n\tstruct acpi_sci_handler_info *next;\n\tacpi_sci_handler address;\n\tvoid *context;\n};\n\nstruct acpi_gpe_handler_info {\n\tacpi_gpe_handler address;\n\tvoid *context;\n\tstruct acpi_namespace_node *method_node;\n\tu8 original_flags;\n\tu8 originally_enabled;\n};\n\nstruct acpi_gpe_notify_info {\n\tstruct acpi_namespace_node *device_node;\n\tstruct acpi_gpe_notify_info *next;\n};\n\nunion acpi_gpe_dispatch_info {\n\tstruct acpi_namespace_node *method_node;\n\tstruct acpi_gpe_handler_info *handler;\n\tstruct acpi_gpe_notify_info *notify_list;\n};\n\nstruct acpi_gpe_register_info;\n\nstruct acpi_gpe_event_info {\n\tunion acpi_gpe_dispatch_info dispatch;\n\tstruct acpi_gpe_register_info *register_info;\n\tu8 flags;\n\tu8 gpe_number;\n\tu8 runtime_count;\n\tu8 disable_for_dispatch;\n};\n\nstruct acpi_gpe_register_info {\n\tstruct acpi_generic_address status_address;\n\tstruct acpi_generic_address enable_address;\n\tu16 base_gpe_number;\n\tu8 enable_for_wake;\n\tu8 enable_for_run;\n\tu8 mask_for_run;\n\tu8 enable_mask;\n} __attribute__((packed));\n\nstruct acpi_gpe_xrupt_info;\n\nstruct acpi_gpe_block_info {\n\tstruct acpi_namespace_node *node;\n\tstruct acpi_gpe_block_info *previous;\n\tstruct acpi_gpe_block_info *next;\n\tstruct acpi_gpe_xrupt_info *xrupt_block;\n\tstruct acpi_gpe_register_info *register_info;\n\tstruct acpi_gpe_event_info *event_info;\n\tu64 address;\n\tu32 register_count;\n\tu16 gpe_count;\n\tu16 block_base_number;\n\tu8 space_id;\n\tu8 initialized;\n};\n\nstruct acpi_gpe_xrupt_info {\n\tstruct acpi_gpe_xrupt_info *previous;\n\tstruct acpi_gpe_xrupt_info *next;\n\tstruct acpi_gpe_block_info *gpe_block_list_head;\n\tu32 interrupt_number;\n};\n\nstruct acpi_fixed_event_handler {\n\tacpi_event_handler handler;\n\tvoid *context;\n};\n\nstruct acpi_fixed_event_info {\n\tu8 status_register_id;\n\tu8 enable_register_id;\n\tu16 status_bit_mask;\n\tu16 enable_bit_mask;\n};\n\nstruct acpi_common_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n};\n\nstruct acpi_update_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tunion acpi_operand_object *object;\n};\n\nstruct acpi_pkg_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu32 index;\n\tunion acpi_operand_object *source_object;\n\tunion acpi_operand_object *dest_object;\n\tstruct acpi_walk_state *walk_state;\n\tvoid *this_target_obj;\n\tu32 num_packages;\n};\n\nstruct acpi_control_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu16 opcode;\n\tunion acpi_parse_object *predicate_op;\n\tu8 *aml_predicate_start;\n\tu8 *package_end;\n\tu64 loop_timeout;\n};\n\nunion acpi_parse_value {\n\tu64 integer;\n\tu32 size;\n\tchar *string;\n\tu8 *buffer;\n\tchar *name;\n\tunion acpi_parse_object *arg;\n};\n\nstruct acpi_parse_obj_common {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n};\n\nstruct acpi_parse_obj_named {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n\tchar *path;\n\tu8 *data;\n\tu32 length;\n\tu32 name;\n};\n\nstruct acpi_parse_obj_asl {\n\tunion acpi_parse_object *parent;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 aml_opcode;\n\tu8 *aml;\n\tunion acpi_parse_object *next;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_parse_value value;\n\tu8 arg_list_length;\n\tunion acpi_parse_object *child;\n\tunion acpi_parse_object *parent_method;\n\tchar *filename;\n\tu8 file_changed;\n\tchar *parent_filename;\n\tchar *external_name;\n\tchar *namepath;\n\tchar name_seg[4];\n\tu32 extra_value;\n\tu32 column;\n\tu32 line_number;\n\tu32 logical_line_number;\n\tu32 logical_byte_offset;\n\tu32 end_line;\n\tu32 end_logical_line;\n\tu32 acpi_btype;\n\tu32 aml_length;\n\tu32 aml_subtree_length;\n\tu32 final_aml_length;\n\tu32 final_aml_offset;\n\tu32 compile_flags;\n\tu16 parse_opcode;\n\tu8 aml_opcode_length;\n\tu8 aml_pkg_len_bytes;\n\tu8 extra;\n\tchar parse_op_name[20];\n};\n\nunion acpi_parse_object {\n\tstruct acpi_parse_obj_common common;\n\tstruct acpi_parse_obj_named named;\n\tstruct acpi_parse_obj_asl asl;\n};\n\nstruct acpi_scope_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tstruct acpi_namespace_node *node;\n};\n\nstruct acpi_pscope_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu32 arg_count;\n\tunion acpi_parse_object *op;\n\tu8 *arg_end;\n\tu8 *pkg_end;\n\tu32 arg_list;\n};\n\nstruct acpi_thread_state {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu8 current_sync_level;\n\tstruct acpi_walk_state *walk_state_list;\n\tunion acpi_operand_object *acquired_mutex_list;\n\tu64 thread_id;\n};\n\nstruct acpi_result_values {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tunion acpi_operand_object *obj_desc[8];\n};\n\nstruct acpi_global_notify_handler {\n\tacpi_notify_handler handler;\n\tvoid *context;\n};\n\nstruct acpi_notify_info {\n\tvoid *next;\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 value;\n\tu16 state;\n\tu8 handler_list_id;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *handler_list_head;\n\tstruct acpi_global_notify_handler *global;\n};\n\nunion acpi_generic_state {\n\tstruct acpi_common_state common;\n\tstruct acpi_control_state control;\n\tstruct acpi_update_state update;\n\tstruct acpi_scope_state scope;\n\tstruct acpi_pscope_state parse_scope;\n\tstruct acpi_pkg_state pkg;\n\tstruct acpi_thread_state thread;\n\tstruct acpi_result_values results;\n\tstruct acpi_notify_info notify;\n};\n\nstruct acpi_address_range {\n\tstruct acpi_address_range *next;\n\tstruct acpi_namespace_node *region_node;\n\tacpi_physical_address start_address;\n\tacpi_physical_address end_address;\n};\n\nstruct acpi_opcode_info {\n\tu32 parse_args;\n\tu32 runtime_args;\n\tu16 flags;\n\tu8 object_type;\n\tu8 class;\n\tu8 type;\n};\n\nstruct acpi_comment_node {\n\tchar *comment;\n\tstruct acpi_comment_node *next;\n};\n\nstruct acpi_bit_register_info {\n\tu8 parent_register;\n\tu8 bit_position;\n\tu16 access_bit_mask;\n};\n\nstruct acpi_interface_info {\n\tchar *name;\n\tstruct acpi_interface_info *next;\n\tu8 flags;\n\tu8 value;\n};\n\nstruct acpi_os_dpc {\n\tacpi_osd_exec_callback function;\n\tvoid *context;\n\tstruct work_struct work;\n};\n\nstruct acpi_ioremap {\n\tstruct list_head list;\n\tvoid *virt;\n\tacpi_physical_address phys;\n\tacpi_size size;\n\tlong unsigned int refcount;\n};\n\nstruct acpi_hp_work {\n\tstruct work_struct work;\n\tstruct acpi_device *adev;\n\tu32 src;\n};\n\nstruct acpi_object_list {\n\tu32 count;\n\tunion acpi_object *pointer;\n};\n\nstruct acpi_pld_info {\n\tu8 revision;\n\tu8 ignore_color;\n\tu8 red;\n\tu8 green;\n\tu8 blue;\n\tu16 width;\n\tu16 height;\n\tu8 user_visible;\n\tu8 dock;\n\tu8 lid;\n\tu8 panel;\n\tu8 vertical_position;\n\tu8 horizontal_position;\n\tu8 shape;\n\tu8 group_orientation;\n\tu8 group_token;\n\tu8 group_position;\n\tu8 bay;\n\tu8 ejectable;\n\tu8 ospm_eject_required;\n\tu8 cabinet_number;\n\tu8 card_cage_number;\n\tu8 reference;\n\tu8 rotation;\n\tu8 order;\n\tu8 reserved;\n\tu16 vertical_offset;\n\tu16 horizontal_offset;\n};\n\nstruct acpi_handle_list {\n\tu32 count;\n\tacpi_handle handles[10];\n};\n\nstruct acpi_device_bus_id {\n\tchar bus_id[15];\n\tunsigned int instance_no;\n\tstruct list_head node;\n};\n\nstruct acpi_dev_match_info {\n\tstruct acpi_device_id hid[2];\n\tconst char *uid;\n\ts64 hrv;\n};\n\nstruct nvs_region {\n\t__u64 phys_start;\n\t__u64 size;\n\tstruct list_head node;\n};\n\nstruct nvs_page {\n\tlong unsigned int phys_start;\n\tunsigned int size;\n\tvoid *kaddr;\n\tvoid *data;\n\tbool unmap;\n\tstruct list_head node;\n};\n\nstruct acpi_wakeup_handler {\n\tstruct list_head list_node;\n\tbool (*wakeup)(void *);\n\tvoid *context;\n};\n\ntypedef u32 acpi_event_status;\n\nstruct lpi_device_info {\n\tchar *name;\n\tint enabled;\n\tunion acpi_object *package;\n};\n\nstruct lpi_device_constraint {\n\tint uid;\n\tint min_dstate;\n\tint function_states;\n};\n\nstruct lpi_constraints {\n\tacpi_handle handle;\n\tint min_dstate;\n};\n\nstruct acpi_hardware_id {\n\tstruct list_head list;\n\tconst char *id;\n};\n\nstruct acpi_data_node {\n\tconst char *name;\n\tacpi_handle handle;\n\tstruct fwnode_handle fwnode;\n\tstruct fwnode_handle *parent;\n\tstruct acpi_device_data data;\n\tstruct list_head sibling;\n\tstruct kobject kobj;\n\tstruct completion kobj_done;\n};\n\nstruct acpi_data_node_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct acpi_data_node *, char *);\n\tssize_t (*store)(struct acpi_data_node *, const char *, size_t);\n};\n\nstruct acpi_device_physical_node {\n\tunsigned int node_id;\n\tstruct list_head node;\n\tstruct device *dev;\n\tbool put_online: 1;\n};\n\nenum acpi_bus_device_type {\n\tACPI_BUS_TYPE_DEVICE = 0,\n\tACPI_BUS_TYPE_POWER = 1,\n\tACPI_BUS_TYPE_PROCESSOR = 2,\n\tACPI_BUS_TYPE_THERMAL = 3,\n\tACPI_BUS_TYPE_POWER_BUTTON = 4,\n\tACPI_BUS_TYPE_SLEEP_BUTTON = 5,\n\tACPI_BUS_TYPE_ECDT_EC = 6,\n\tACPI_BUS_DEVICE_TYPE_COUNT = 7,\n};\n\nstruct acpi_osc_context {\n\tchar *uuid_str;\n\tint rev;\n\tstruct acpi_buffer cap;\n\tstruct acpi_buffer ret;\n};\n\nenum dev_dma_attr {\n\tDEV_DMA_NOT_SUPPORTED = 0,\n\tDEV_DMA_NON_COHERENT = 1,\n\tDEV_DMA_COHERENT = 2,\n};\n\nstruct acpi_pnp_device_id {\n\tu32 length;\n\tchar *string;\n};\n\nstruct acpi_pnp_device_id_list {\n\tu32 count;\n\tu32 list_size;\n\tstruct acpi_pnp_device_id ids[1];\n};\n\nstruct acpi_device_info {\n\tu32 info_size;\n\tu32 name;\n\tacpi_object_type type;\n\tu8 param_count;\n\tu16 valid;\n\tu8 flags;\n\tu8 highest_dstates[4];\n\tu8 lowest_dstates[5];\n\tu64 address;\n\tstruct acpi_pnp_device_id hardware_id;\n\tstruct acpi_pnp_device_id unique_id;\n\tstruct acpi_pnp_device_id class_code;\n\tstruct acpi_pnp_device_id_list compatible_id_list;\n};\n\nstruct acpi_table_spcr {\n\tstruct acpi_table_header header;\n\tu8 interface_type;\n\tu8 reserved[3];\n\tstruct acpi_generic_address serial_port;\n\tu8 interrupt_type;\n\tu8 pc_interrupt;\n\tu32 interrupt;\n\tu8 baud_rate;\n\tu8 parity;\n\tu8 stop_bits;\n\tu8 flow_control;\n\tu8 terminal_type;\n\tu8 reserved1;\n\tu16 pci_device_id;\n\tu16 pci_vendor_id;\n\tu8 pci_bus;\n\tu8 pci_device;\n\tu8 pci_function;\n\tu32 pci_flags;\n\tu8 pci_segment;\n\tu32 reserved2;\n} __attribute__((packed));\n\nstruct acpi_table_stao {\n\tstruct acpi_table_header header;\n\tu8 ignore_uart;\n} __attribute__((packed));\n\nstruct acpi_resource_irq {\n\tu8 descriptor_length;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 interrupt_count;\n\tu8 interrupts[1];\n};\n\nstruct acpi_resource_dma {\n\tu8 type;\n\tu8 bus_master;\n\tu8 transfer;\n\tu8 channel_count;\n\tu8 channels[1];\n};\n\nstruct acpi_resource_start_dependent {\n\tu8 descriptor_length;\n\tu8 compatibility_priority;\n\tu8 performance_robustness;\n};\n\nstruct acpi_resource_io {\n\tu8 io_decode;\n\tu8 alignment;\n\tu8 address_length;\n\tu16 minimum;\n\tu16 maximum;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_io {\n\tu16 address;\n\tu8 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_dma {\n\tu16 request_lines;\n\tu16 channels;\n\tu8 width;\n} __attribute__((packed));\n\nstruct acpi_resource_vendor {\n\tu16 byte_length;\n\tu8 byte_data[1];\n} __attribute__((packed));\n\nstruct acpi_resource_vendor_typed {\n\tu16 byte_length;\n\tu8 uuid_subtype;\n\tu8 uuid[16];\n\tu8 byte_data[1];\n};\n\nstruct acpi_resource_end_tag {\n\tu8 checksum;\n};\n\nstruct acpi_resource_memory24 {\n\tu8 write_protect;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 alignment;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_memory32 {\n\tu8 write_protect;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 alignment;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct acpi_resource_fixed_memory32 {\n\tu8 write_protect;\n\tu32 address;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct acpi_memory_attribute {\n\tu8 write_protect;\n\tu8 caching;\n\tu8 range_type;\n\tu8 translation;\n};\n\nstruct acpi_io_attribute {\n\tu8 range_type;\n\tu8 translation;\n\tu8 translation_type;\n\tu8 reserved1;\n};\n\nunion acpi_resource_attribute {\n\tstruct acpi_memory_attribute mem;\n\tstruct acpi_io_attribute io;\n\tu8 type_specific;\n};\n\nstruct acpi_resource_label {\n\tu16 string_length;\n\tchar *string_ptr;\n} __attribute__((packed));\n\nstruct acpi_resource_source {\n\tu8 index;\n\tu16 string_length;\n\tchar *string_ptr;\n} __attribute__((packed));\n\nstruct acpi_address16_attribute {\n\tu16 granularity;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 translation_offset;\n\tu16 address_length;\n};\n\nstruct acpi_address32_attribute {\n\tu32 granularity;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 translation_offset;\n\tu32 address_length;\n};\n\nstruct acpi_address64_attribute {\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n};\n\nstruct acpi_resource_address {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n};\n\nstruct acpi_resource_address16 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address16_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_address32 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address32_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_address64 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tstruct acpi_address64_attribute address;\n\tstruct acpi_resource_source resource_source;\n} __attribute__((packed));\n\nstruct acpi_resource_extended_address64 {\n\tu8 resource_type;\n\tu8 producer_consumer;\n\tu8 decode;\n\tu8 min_address_fixed;\n\tu8 max_address_fixed;\n\tunion acpi_resource_attribute info;\n\tu8 revision_ID;\n\tstruct acpi_address64_attribute address;\n\tu64 type_specific;\n} __attribute__((packed));\n\nstruct acpi_resource_extended_irq {\n\tu8 producer_consumer;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 interrupt_count;\n\tstruct acpi_resource_source resource_source;\n\tu32 interrupts[1];\n} __attribute__((packed));\n\nstruct acpi_resource_generic_register {\n\tu8 space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct acpi_resource_gpio {\n\tu8 revision_id;\n\tu8 connection_type;\n\tu8 producer_consumer;\n\tu8 pin_config;\n\tu8 shareable;\n\tu8 wake_capable;\n\tu8 io_restriction;\n\tu8 triggering;\n\tu8 polarity;\n\tu16 drive_strength;\n\tu16 debounce_timeout;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_common_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_i2c_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 access_mode;\n\tu16 slave_address;\n\tu32 connection_speed;\n} __attribute__((packed));\n\nstruct acpi_resource_spi_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 wire_mode;\n\tu8 device_polarity;\n\tu8 data_bit_length;\n\tu8 clock_phase;\n\tu8 clock_polarity;\n\tu16 device_selection;\n\tu32 connection_speed;\n} __attribute__((packed));\n\nstruct acpi_resource_uart_serialbus {\n\tu8 revision_id;\n\tu8 type;\n\tu8 producer_consumer;\n\tu8 slave_mode;\n\tu8 connection_sharing;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu8 *vendor_data;\n\tu8 endian;\n\tu8 data_bits;\n\tu8 stop_bits;\n\tu8 flow_control;\n\tu8 parity;\n\tu8 lines_enabled;\n\tu16 rx_fifo_size;\n\tu16 tx_fifo_size;\n\tu32 default_baud_rate;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_function {\n\tu8 revision_id;\n\tu8 pin_config;\n\tu8 shareable;\n\tu16 function_number;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_config {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tu16 *pin_table;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu16 pin_table_length;\n\tu16 vendor_length;\n\tu16 *pin_table;\n\tstruct acpi_resource_label resource_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group_function {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu16 function_number;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tstruct acpi_resource_label resource_source_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nstruct acpi_resource_pin_group_config {\n\tu8 revision_id;\n\tu8 producer_consumer;\n\tu8 shareable;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 vendor_length;\n\tstruct acpi_resource_source resource_source;\n\tstruct acpi_resource_label resource_source_label;\n\tu8 *vendor_data;\n} __attribute__((packed));\n\nunion acpi_resource_data {\n\tstruct acpi_resource_irq irq;\n\tstruct acpi_resource_dma dma;\n\tstruct acpi_resource_start_dependent start_dpf;\n\tstruct acpi_resource_io io;\n\tstruct acpi_resource_fixed_io fixed_io;\n\tstruct acpi_resource_fixed_dma fixed_dma;\n\tstruct acpi_resource_vendor vendor;\n\tstruct acpi_resource_vendor_typed vendor_typed;\n\tstruct acpi_resource_end_tag end_tag;\n\tstruct acpi_resource_memory24 memory24;\n\tstruct acpi_resource_memory32 memory32;\n\tstruct acpi_resource_fixed_memory32 fixed_memory32;\n\tstruct acpi_resource_address16 address16;\n\tstruct acpi_resource_address32 address32;\n\tstruct acpi_resource_address64 address64;\n\tstruct acpi_resource_extended_address64 ext_address64;\n\tstruct acpi_resource_extended_irq extended_irq;\n\tstruct acpi_resource_generic_register generic_reg;\n\tstruct acpi_resource_gpio gpio;\n\tstruct acpi_resource_i2c_serialbus i2c_serial_bus;\n\tstruct acpi_resource_spi_serialbus spi_serial_bus;\n\tstruct acpi_resource_uart_serialbus uart_serial_bus;\n\tstruct acpi_resource_common_serialbus common_serial_bus;\n\tstruct acpi_resource_pin_function pin_function;\n\tstruct acpi_resource_pin_config pin_config;\n\tstruct acpi_resource_pin_group pin_group;\n\tstruct acpi_resource_pin_group_function pin_group_function;\n\tstruct acpi_resource_pin_group_config pin_group_config;\n\tstruct acpi_resource_address address;\n};\n\nstruct acpi_resource {\n\tu32 type;\n\tu32 length;\n\tunion acpi_resource_data data;\n} __attribute__((packed));\n\nenum acpi_reconfig_event {\n\tACPI_RECONFIG_DEVICE_ADD = 0,\n\tACPI_RECONFIG_DEVICE_REMOVE = 1,\n};\n\nstruct acpi_probe_entry;\n\ntypedef bool (*acpi_probe_entry_validate_subtbl)(struct acpi_subtable_header *, struct acpi_probe_entry *);\n\nstruct acpi_probe_entry {\n\t__u8 id[5];\n\t__u8 type;\n\tacpi_probe_entry_validate_subtbl subtable_valid;\n\tunion {\n\t\tacpi_tbl_table_handler probe_table;\n\t\tacpi_tbl_entry_handler probe_subtbl;\n\t};\n\tkernel_ulong_t driver_data;\n};\n\nstruct acpi_dep_data {\n\tstruct list_head node;\n\tacpi_handle master;\n\tacpi_handle slave;\n};\n\nstruct acpi_table_events_work {\n\tstruct work_struct work;\n\tvoid *table;\n\tu32 event;\n};\n\nstruct resource_win {\n\tstruct resource res;\n\tresource_size_t offset;\n};\n\nstruct res_proc_context {\n\tstruct list_head *list;\n\tint (*preproc)(struct acpi_resource *, void *);\n\tvoid *preproc_data;\n\tint count;\n\tint error;\n};\n\nstruct acpi_table_ecdt {\n\tstruct acpi_table_header header;\n\tstruct acpi_generic_address control;\n\tstruct acpi_generic_address data;\n\tu32 uid;\n\tu8 gpe;\n\tu8 id[1];\n} __attribute__((packed));\n\nstruct transaction {\n\tconst u8 *wdata;\n\tu8 *rdata;\n\tshort unsigned int irq_count;\n\tu8 command;\n\tu8 wi;\n\tu8 ri;\n\tu8 wlen;\n\tu8 rlen;\n\tu8 flags;\n};\n\ntypedef int (*acpi_ec_query_func)(void *);\n\nenum ec_command {\n\tACPI_EC_COMMAND_READ = 128,\n\tACPI_EC_COMMAND_WRITE = 129,\n\tACPI_EC_BURST_ENABLE = 130,\n\tACPI_EC_BURST_DISABLE = 131,\n\tACPI_EC_COMMAND_QUERY = 132,\n};\n\nenum {\n\tEC_FLAGS_QUERY_ENABLED = 0,\n\tEC_FLAGS_QUERY_PENDING = 1,\n\tEC_FLAGS_QUERY_GUARDING = 2,\n\tEC_FLAGS_EVENT_HANDLER_INSTALLED = 3,\n\tEC_FLAGS_EC_HANDLER_INSTALLED = 4,\n\tEC_FLAGS_QUERY_METHODS_INSTALLED = 5,\n\tEC_FLAGS_STARTED = 6,\n\tEC_FLAGS_STOPPED = 7,\n\tEC_FLAGS_EVENTS_MASKED = 8,\n};\n\nstruct acpi_ec_query_handler {\n\tstruct list_head node;\n\tacpi_ec_query_func func;\n\tacpi_handle handle;\n\tvoid *data;\n\tu8 query_bit;\n\tstruct kref kref;\n};\n\nstruct acpi_ec_query {\n\tstruct transaction transaction;\n\tstruct work_struct work;\n\tstruct acpi_ec_query_handler *handler;\n};\n\nstruct dock_station {\n\tacpi_handle handle;\n\tlong unsigned int last_dock_time;\n\tu32 flags;\n\tstruct list_head dependent_devices;\n\tstruct list_head sibling;\n\tstruct platform_device *dock_device;\n};\n\nstruct dock_dependent_device {\n\tstruct list_head list;\n\tstruct acpi_device *adev;\n};\n\nenum dock_callback_type {\n\tDOCK_CALL_HANDLER = 0,\n\tDOCK_CALL_FIXUP = 1,\n\tDOCK_CALL_UEVENT = 2,\n};\n\nstruct acpi_pci_root_ops;\n\nstruct acpi_pci_root_info {\n\tstruct acpi_pci_root *root;\n\tstruct acpi_device *bridge;\n\tstruct acpi_pci_root_ops *ops;\n\tstruct list_head resources;\n\tchar name[16];\n};\n\nstruct acpi_pci_root_ops {\n\tstruct pci_ops *pci_ops;\n\tint (*init_info)(struct acpi_pci_root_info *);\n\tvoid (*release_info)(struct acpi_pci_root_info *);\n\tint (*prepare_resources)(struct acpi_pci_root_info *);\n};\n\nstruct pci_osc_bit_struct {\n\tu32 bit;\n\tchar *desc;\n};\n\nstruct acpi_handle_node {\n\tstruct list_head node;\n\tacpi_handle handle;\n};\n\nstruct acpi_pci_link_irq {\n\tu32 active;\n\tu8 triggering;\n\tu8 polarity;\n\tu8 resource_type;\n\tu8 possible_count;\n\tu32 possible[16];\n\tu8 initialized: 1;\n\tu8 reserved: 7;\n};\n\nstruct acpi_pci_link {\n\tstruct list_head list;\n\tstruct acpi_device *device;\n\tstruct acpi_pci_link_irq irq;\n\tint refcnt;\n};\n\nstruct acpi_pci_routing_table {\n\tu32 length;\n\tu32 pin;\n\tu64 address;\n\tu32 source_index;\n\tchar source[4];\n};\n\nstruct acpi_prt_entry {\n\tstruct acpi_pci_id id;\n\tu8 pin;\n\tacpi_handle link;\n\tu32 index;\n};\n\nstruct prt_quirk {\n\tconst struct dmi_system_id *system;\n\tunsigned int segment;\n\tunsigned int bus;\n\tunsigned int device;\n\tunsigned char pin;\n\tconst char *source;\n\tconst char *actual_source;\n};\n\nstruct apd_private_data;\n\nstruct apd_device_desc {\n\tunsigned int flags;\n\tunsigned int fixed_clk_rate;\n\tstruct property_entry *properties;\n\tint (*setup)(struct apd_private_data *);\n};\n\nstruct apd_private_data {\n\tstruct clk *clk;\n\tstruct acpi_device *adev;\n\tconst struct apd_device_desc *dev_desc;\n};\n\nstruct acpi_power_dependent_device {\n\tstruct device *dev;\n\tstruct list_head node;\n};\n\nstruct acpi_power_resource {\n\tstruct acpi_device device;\n\tstruct list_head list_node;\n\tchar *name;\n\tu32 system_level;\n\tu32 order;\n\tunsigned int ref_count;\n\tbool wakeup_enabled;\n\tstruct mutex resource_lock;\n\tstruct list_head dependents;\n};\n\nstruct acpi_power_resource_entry {\n\tstruct list_head node;\n\tstruct acpi_power_resource *resource;\n};\n\nstruct acpi_bus_event {\n\tstruct list_head node;\n\tacpi_device_class device_class;\n\tacpi_bus_id bus_id;\n\tu32 type;\n\tu32 data;\n};\n\nstruct acpi_genl_event {\n\tacpi_device_class device_class;\n\tchar bus_id[15];\n\tu32 type;\n\tu32 data;\n};\n\nenum {\n\tACPI_GENL_ATTR_UNSPEC = 0,\n\tACPI_GENL_ATTR_EVENT = 1,\n\t__ACPI_GENL_ATTR_MAX = 2,\n};\n\nenum {\n\tACPI_GENL_CMD_UNSPEC = 0,\n\tACPI_GENL_CMD_EVENT = 1,\n\t__ACPI_GENL_CMD_MAX = 2,\n};\n\nstruct acpi_ged_device {\n\tstruct device *dev;\n\tstruct list_head event_list;\n};\n\nstruct acpi_ged_event {\n\tstruct list_head node;\n\tstruct device *dev;\n\tunsigned int gsi;\n\tunsigned int irq;\n\tacpi_handle handle;\n};\n\nstruct acpi_table_bert {\n\tstruct acpi_table_header header;\n\tu32 region_length;\n\tu64 address;\n};\n\nstruct acpi_table_attr {\n\tstruct bin_attribute attr;\n\tchar name[4];\n\tint instance;\n\tchar filename[8];\n\tstruct list_head node;\n};\n\nstruct acpi_data_attr {\n\tstruct bin_attribute attr;\n\tu64 addr;\n};\n\nstruct acpi_data_obj {\n\tchar *name;\n\tint (*fn)(void *, struct acpi_data_attr *);\n};\n\nstruct event_counter {\n\tu32 count;\n\tu32 flags;\n};\n\nstruct acpi_device_properties {\n\tconst guid_t *guid;\n\tconst union acpi_object *properties;\n\tstruct list_head list;\n};\n\nstruct always_present_id {\n\tstruct acpi_device_id hid[2];\n\tstruct x86_cpu_id cpu_ids[2];\n\tstruct dmi_system_id dmi_ids[2];\n\tconst char *uid;\n};\n\nstruct acpi_lpat {\n\tint temp;\n\tint raw;\n};\n\nstruct acpi_lpat_conversion_table {\n\tstruct acpi_lpat *lpat;\n\tint lpat_count;\n};\n\nstruct acpi_table_lpit {\n\tstruct acpi_table_header header;\n};\n\nstruct acpi_lpit_header {\n\tu32 type;\n\tu32 length;\n\tu16 unique_id;\n\tu16 reserved;\n\tu32 flags;\n};\n\nstruct acpi_lpit_native {\n\tstruct acpi_lpit_header header;\n\tstruct acpi_generic_address entry_trigger;\n\tu32 residency;\n\tu32 latency;\n\tstruct acpi_generic_address residency_counter;\n\tu64 counter_frequency;\n} __attribute__((packed));\n\nstruct lpit_residency_info {\n\tstruct acpi_generic_address gaddr;\n\tu64 frequency;\n\tvoid *iomem_addr;\n};\n\nenum {\n\tACPI_REFCLASS_LOCAL = 0,\n\tACPI_REFCLASS_ARG = 1,\n\tACPI_REFCLASS_REFOF = 2,\n\tACPI_REFCLASS_INDEX = 3,\n\tACPI_REFCLASS_TABLE = 4,\n\tACPI_REFCLASS_NAME = 5,\n\tACPI_REFCLASS_DEBUG = 6,\n\tACPI_REFCLASS_MAX = 6,\n};\n\nstruct acpi_common_descriptor {\n\tvoid *common_pointer;\n\tu8 descriptor_type;\n};\n\nunion acpi_descriptor {\n\tstruct acpi_common_descriptor common;\n\tunion acpi_operand_object object;\n\tstruct acpi_namespace_node node;\n\tunion acpi_parse_object op;\n};\n\nstruct acpi_create_field_info {\n\tstruct acpi_namespace_node *region_node;\n\tstruct acpi_namespace_node *field_node;\n\tstruct acpi_namespace_node *register_node;\n\tstruct acpi_namespace_node *data_register_node;\n\tstruct acpi_namespace_node *connection_node;\n\tu8 *resource_buffer;\n\tu32 bank_value;\n\tu32 field_bit_position;\n\tu32 field_bit_length;\n\tu16 resource_length;\n\tu16 pin_number_index;\n\tu8 field_flags;\n\tu8 attribute;\n\tu8 field_type;\n\tu8 access_length;\n};\n\nstruct acpi_init_walk_info {\n\tu32 table_index;\n\tu32 object_count;\n\tu32 method_count;\n\tu32 serial_method_count;\n\tu32 non_serial_method_count;\n\tu32 serialized_method_count;\n\tu32 device_count;\n\tu32 op_region_count;\n\tu32 field_count;\n\tu32 buffer_count;\n\tu32 package_count;\n\tu32 op_region_init;\n\tu32 field_init;\n\tu32 buffer_init;\n\tu32 package_init;\n\tacpi_owner_id owner_id;\n};\n\nstruct acpi_name_info {\n\tchar name[4];\n\tu16 argument_list;\n\tu8 expected_btypes;\n} __attribute__((packed));\n\nstruct acpi_package_info {\n\tu8 type;\n\tu8 object_type1;\n\tu8 count1;\n\tu8 object_type2;\n\tu8 count2;\n\tu16 reserved;\n} __attribute__((packed));\n\nstruct acpi_package_info2 {\n\tu8 type;\n\tu8 count;\n\tu8 object_type[4];\n\tu8 reserved;\n};\n\nstruct acpi_package_info3 {\n\tu8 type;\n\tu8 count;\n\tu8 object_type[2];\n\tu8 tail_object_type;\n\tu16 reserved;\n} __attribute__((packed));\n\nstruct acpi_package_info4 {\n\tu8 type;\n\tu8 object_type1;\n\tu8 count1;\n\tu8 sub_object_types;\n\tu8 pkg_count;\n\tu16 reserved;\n} __attribute__((packed));\n\nunion acpi_predefined_info {\n\tstruct acpi_name_info info;\n\tstruct acpi_package_info ret_info;\n\tstruct acpi_package_info2 ret_info2;\n\tstruct acpi_package_info3 ret_info3;\n\tstruct acpi_package_info4 ret_info4;\n};\n\nstruct acpi_evaluate_info {\n\tstruct acpi_namespace_node *prefix_node;\n\tconst char *relative_pathname;\n\tunion acpi_operand_object **parameters;\n\tstruct acpi_namespace_node *node;\n\tunion acpi_operand_object *obj_desc;\n\tchar *full_pathname;\n\tconst union acpi_predefined_info *predefined;\n\tunion acpi_operand_object *return_object;\n\tunion acpi_operand_object *parent_package;\n\tu32 return_flags;\n\tu32 return_btype;\n\tu16 param_count;\n\tu16 node_flags;\n\tu8 pass_number;\n\tu8 return_object_type;\n\tu8 flags;\n};\n\nenum {\n\tAML_FIELD_ACCESS_ANY = 0,\n\tAML_FIELD_ACCESS_BYTE = 1,\n\tAML_FIELD_ACCESS_WORD = 2,\n\tAML_FIELD_ACCESS_DWORD = 3,\n\tAML_FIELD_ACCESS_QWORD = 4,\n\tAML_FIELD_ACCESS_BUFFER = 5,\n};\n\ntypedef enum {\n\tACPI_IMODE_LOAD_PASS1 = 1,\n\tACPI_IMODE_LOAD_PASS2 = 2,\n\tACPI_IMODE_EXECUTE = 3,\n} acpi_interpreter_mode;\n\ntypedef acpi_status (*acpi_execute_op)(struct acpi_walk_state *);\n\nstruct acpi_gpe_walk_info {\n\tstruct acpi_namespace_node *gpe_device;\n\tstruct acpi_gpe_block_info *gpe_block;\n\tu16 count;\n\tacpi_owner_id owner_id;\n\tu8 execute_by_owner_id;\n};\n\nstruct acpi_gpe_device_info {\n\tu32 index;\n\tu32 next_block_base_index;\n\tacpi_status status;\n\tstruct acpi_namespace_node *gpe_device;\n};\n\ntypedef acpi_status (*acpi_gpe_callback)(struct acpi_gpe_xrupt_info *, struct acpi_gpe_block_info *, void *);\n\nstruct acpi_connection_info {\n\tu8 *connection;\n\tu16 length;\n\tu8 access_length;\n};\n\nstruct acpi_reg_walk_info {\n\tu32 function;\n\tu32 reg_run_count;\n\tacpi_adr_space_type space_id;\n};\n\nenum {\n\tAML_FIELD_UPDATE_PRESERVE = 0,\n\tAML_FIELD_UPDATE_WRITE_AS_ONES = 32,\n\tAML_FIELD_UPDATE_WRITE_AS_ZEROS = 64,\n};\n\nstruct acpi_signal_fatal_info {\n\tu32 type;\n\tu32 code;\n\tu32 argument;\n};\n\nenum {\n\tMATCH_MTR = 0,\n\tMATCH_MEQ = 1,\n\tMATCH_MLE = 2,\n\tMATCH_MLT = 3,\n\tMATCH_MGE = 4,\n\tMATCH_MGT = 5,\n};\n\nenum {\n\tAML_FIELD_ATTRIB_QUICK = 2,\n\tAML_FIELD_ATTRIB_SEND_RECEIVE = 4,\n\tAML_FIELD_ATTRIB_BYTE = 6,\n\tAML_FIELD_ATTRIB_WORD = 8,\n\tAML_FIELD_ATTRIB_BLOCK = 10,\n\tAML_FIELD_ATTRIB_BYTES = 11,\n\tAML_FIELD_ATTRIB_PROCESS_CALL = 12,\n\tAML_FIELD_ATTRIB_BLOCK_PROCESS_CALL = 13,\n\tAML_FIELD_ATTRIB_RAW_BYTES = 14,\n\tAML_FIELD_ATTRIB_RAW_PROCESS_BYTES = 15,\n};\n\ntypedef enum {\n\tACPI_TRACE_AML_METHOD = 0,\n\tACPI_TRACE_AML_OPCODE = 1,\n\tACPI_TRACE_AML_REGION = 2,\n} acpi_trace_event_type;\n\nstruct acpi_gpe_block_status_context {\n\tstruct acpi_gpe_register_info *gpe_skip_register_info;\n\tu8 gpe_skip_mask;\n\tu8 retval;\n};\n\nstruct acpi_port_info {\n\tchar *name;\n\tu16 start;\n\tu16 end;\n\tu8 osi_dependency;\n};\n\nstruct acpi_pci_device {\n\tacpi_handle device;\n\tstruct acpi_pci_device *next;\n};\n\nstruct acpi_device_walk_info {\n\tstruct acpi_table_desc *table_desc;\n\tstruct acpi_evaluate_info *evaluate_info;\n\tu32 device_count;\n\tu32 num_STA;\n\tu32 num_INI;\n};\n\nenum acpi_return_package_types {\n\tACPI_PTYPE1_FIXED = 1,\n\tACPI_PTYPE1_VAR = 2,\n\tACPI_PTYPE1_OPTION = 3,\n\tACPI_PTYPE2 = 4,\n\tACPI_PTYPE2_COUNT = 5,\n\tACPI_PTYPE2_PKG_COUNT = 6,\n\tACPI_PTYPE2_FIXED = 7,\n\tACPI_PTYPE2_MIN = 8,\n\tACPI_PTYPE2_REV_FIXED = 9,\n\tACPI_PTYPE2_FIX_VAR = 10,\n\tACPI_PTYPE2_VAR_VAR = 11,\n\tACPI_PTYPE2_UUID_PAIR = 12,\n\tACPI_PTYPE_CUSTOM = 13,\n};\n\ntypedef acpi_status (*acpi_object_converter)(struct acpi_namespace_node *, union acpi_operand_object *, union acpi_operand_object **);\n\nstruct acpi_simple_repair_info {\n\tchar name[4];\n\tu32 unexpected_btypes;\n\tu32 package_index;\n\tacpi_object_converter object_converter;\n};\n\ntypedef acpi_status (*acpi_repair_function)(struct acpi_evaluate_info *, union acpi_operand_object **);\n\nstruct acpi_repair_info {\n\tchar name[4];\n\tacpi_repair_function repair_function;\n};\n\nstruct acpi_namestring_info {\n\tconst char *external_name;\n\tconst char *next_external_char;\n\tchar *internal_name;\n\tu32 length;\n\tu32 num_segments;\n\tu32 num_carats;\n\tu8 fully_qualified;\n};\n\ntypedef acpi_status (*acpi_walk_callback)(acpi_handle, u32, void *, void **);\n\nstruct acpi_get_devices_info {\n\tacpi_walk_callback user_function;\n\tvoid *context;\n\tconst char *hid;\n};\n\nstruct aml_resource_small_header {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_irq {\n\tu8 descriptor_type;\n\tu16 irq_mask;\n\tu8 flags;\n} __attribute__((packed));\n\nstruct aml_resource_dma {\n\tu8 descriptor_type;\n\tu8 dma_channel_mask;\n\tu8 flags;\n};\n\nstruct aml_resource_start_dependent {\n\tu8 descriptor_type;\n\tu8 flags;\n};\n\nstruct aml_resource_end_dependent {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_io {\n\tu8 descriptor_type;\n\tu8 flags;\n\tu16 minimum;\n\tu16 maximum;\n\tu8 alignment;\n\tu8 address_length;\n};\n\nstruct aml_resource_fixed_io {\n\tu8 descriptor_type;\n\tu16 address;\n\tu8 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_vendor_small {\n\tu8 descriptor_type;\n};\n\nstruct aml_resource_end_tag {\n\tu8 descriptor_type;\n\tu8 checksum;\n};\n\nstruct aml_resource_fixed_dma {\n\tu8 descriptor_type;\n\tu16 request_lines;\n\tu16 channels;\n\tu8 width;\n} __attribute__((packed));\n\nstruct aml_resource_large_header {\n\tu8 descriptor_type;\n\tu16 resource_length;\n} __attribute__((packed));\n\nstruct aml_resource_memory24 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 alignment;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_vendor_large {\n\tu8 descriptor_type;\n\tu16 resource_length;\n} __attribute__((packed));\n\nstruct aml_resource_memory32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 alignment;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_fixed_memory32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu32 address;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n} __attribute__((packed));\n\nstruct aml_resource_extended_address64 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu8 revision_ID;\n\tu8 reserved;\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n\tu64 type_specific;\n} __attribute__((packed));\n\nstruct aml_resource_address64 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu64 granularity;\n\tu64 minimum;\n\tu64 maximum;\n\tu64 translation_offset;\n\tu64 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address32 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu32 granularity;\n\tu32 minimum;\n\tu32 maximum;\n\tu32 translation_offset;\n\tu32 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_address16 {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 resource_type;\n\tu8 flags;\n\tu8 specific_flags;\n\tu16 granularity;\n\tu16 minimum;\n\tu16 maximum;\n\tu16 translation_offset;\n\tu16 address_length;\n} __attribute__((packed));\n\nstruct aml_resource_extended_irq {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 flags;\n\tu8 interrupt_count;\n\tu32 interrupts[1];\n} __attribute__((packed));\n\nstruct aml_resource_generic_register {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 address_space_id;\n\tu8 bit_width;\n\tu8 bit_offset;\n\tu8 access_size;\n\tu64 address;\n} __attribute__((packed));\n\nstruct aml_resource_gpio {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 connection_type;\n\tu16 flags;\n\tu16 int_flags;\n\tu8 pin_config;\n\tu16 drive_strength;\n\tu16 debounce_timeout;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_common_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n} __attribute__((packed));\n\nstruct aml_resource_i2c_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 connection_speed;\n\tu16 slave_address;\n} __attribute__((packed));\n\nstruct aml_resource_spi_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 connection_speed;\n\tu8 data_bit_length;\n\tu8 clock_phase;\n\tu8 clock_polarity;\n\tu16 device_selection;\n} __attribute__((packed));\n\nstruct aml_resource_uart_serialbus {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu8 res_source_index;\n\tu8 type;\n\tu8 flags;\n\tu16 type_specific_flags;\n\tu8 type_revision_id;\n\tu16 type_data_length;\n\tu32 default_baud_rate;\n\tu16 rx_fifo_size;\n\tu16 tx_fifo_size;\n\tu8 parity;\n\tu8 lines_enabled;\n} __attribute__((packed));\n\nstruct aml_resource_pin_function {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config;\n\tu16 function_number;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_config {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu16 pin_table_offset;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu16 pin_table_offset;\n\tu16 label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group_function {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu16 function_number;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 res_source_label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nstruct aml_resource_pin_group_config {\n\tu8 descriptor_type;\n\tu16 resource_length;\n\tu8 revision_id;\n\tu16 flags;\n\tu8 pin_config_type;\n\tu32 pin_config_value;\n\tu8 res_source_index;\n\tu16 res_source_offset;\n\tu16 res_source_label_offset;\n\tu16 vendor_offset;\n\tu16 vendor_length;\n} __attribute__((packed));\n\nunion aml_resource {\n\tu8 descriptor_type;\n\tstruct aml_resource_small_header small_header;\n\tstruct aml_resource_large_header large_header;\n\tstruct aml_resource_irq irq;\n\tstruct aml_resource_dma dma;\n\tstruct aml_resource_start_dependent start_dpf;\n\tstruct aml_resource_end_dependent end_dpf;\n\tstruct aml_resource_io io;\n\tstruct aml_resource_fixed_io fixed_io;\n\tstruct aml_resource_fixed_dma fixed_dma;\n\tstruct aml_resource_vendor_small vendor_small;\n\tstruct aml_resource_end_tag end_tag;\n\tstruct aml_resource_memory24 memory24;\n\tstruct aml_resource_generic_register generic_reg;\n\tstruct aml_resource_vendor_large vendor_large;\n\tstruct aml_resource_memory32 memory32;\n\tstruct aml_resource_fixed_memory32 fixed_memory32;\n\tstruct aml_resource_address16 address16;\n\tstruct aml_resource_address32 address32;\n\tstruct aml_resource_address64 address64;\n\tstruct aml_resource_extended_address64 ext_address64;\n\tstruct aml_resource_extended_irq extended_irq;\n\tstruct aml_resource_gpio gpio;\n\tstruct aml_resource_i2c_serialbus i2c_serial_bus;\n\tstruct aml_resource_spi_serialbus spi_serial_bus;\n\tstruct aml_resource_uart_serialbus uart_serial_bus;\n\tstruct aml_resource_common_serialbus common_serial_bus;\n\tstruct aml_resource_pin_function pin_function;\n\tstruct aml_resource_pin_config pin_config;\n\tstruct aml_resource_pin_group pin_group;\n\tstruct aml_resource_pin_group_function pin_group_function;\n\tstruct aml_resource_pin_group_config pin_group_config;\n\tstruct aml_resource_address address;\n\tu32 dword_item;\n\tu16 word_item;\n\tu8 byte_item;\n};\n\nstruct acpi_rsconvert_info {\n\tu8 opcode;\n\tu8 resource_offset;\n\tu8 aml_offset;\n\tu8 value;\n};\n\nenum {\n\tACPI_RSC_INITGET = 0,\n\tACPI_RSC_INITSET = 1,\n\tACPI_RSC_FLAGINIT = 2,\n\tACPI_RSC_1BITFLAG = 3,\n\tACPI_RSC_2BITFLAG = 4,\n\tACPI_RSC_3BITFLAG = 5,\n\tACPI_RSC_ADDRESS = 6,\n\tACPI_RSC_BITMASK = 7,\n\tACPI_RSC_BITMASK16 = 8,\n\tACPI_RSC_COUNT = 9,\n\tACPI_RSC_COUNT16 = 10,\n\tACPI_RSC_COUNT_GPIO_PIN = 11,\n\tACPI_RSC_COUNT_GPIO_RES = 12,\n\tACPI_RSC_COUNT_GPIO_VEN = 13,\n\tACPI_RSC_COUNT_SERIAL_RES = 14,\n\tACPI_RSC_COUNT_SERIAL_VEN = 15,\n\tACPI_RSC_DATA8 = 16,\n\tACPI_RSC_EXIT_EQ = 17,\n\tACPI_RSC_EXIT_LE = 18,\n\tACPI_RSC_EXIT_NE = 19,\n\tACPI_RSC_LENGTH = 20,\n\tACPI_RSC_MOVE_GPIO_PIN = 21,\n\tACPI_RSC_MOVE_GPIO_RES = 22,\n\tACPI_RSC_MOVE_SERIAL_RES = 23,\n\tACPI_RSC_MOVE_SERIAL_VEN = 24,\n\tACPI_RSC_MOVE8 = 25,\n\tACPI_RSC_MOVE16 = 26,\n\tACPI_RSC_MOVE32 = 27,\n\tACPI_RSC_MOVE64 = 28,\n\tACPI_RSC_SET8 = 29,\n\tACPI_RSC_SOURCE = 30,\n\tACPI_RSC_SOURCEX = 31,\n};\n\ntypedef u16 acpi_rs_length;\n\ntypedef u32 acpi_rsdesc_size;\n\nstruct acpi_vendor_uuid {\n\tu8 subtype;\n\tu8 data[16];\n};\n\ntypedef acpi_status (*acpi_walk_resource_callback)(struct acpi_resource *, void *);\n\nstruct acpi_vendor_walk_info {\n\tstruct acpi_vendor_uuid *uuid;\n\tstruct acpi_buffer *buffer;\n\tacpi_status status;\n};\n\nstruct acpi_fadt_info {\n\tconst char *name;\n\tu16 address64;\n\tu16 address32;\n\tu16 length;\n\tu8 default_length;\n\tu8 flags;\n};\n\nstruct acpi_fadt_pm_info {\n\tstruct acpi_generic_address *target;\n\tu16 source;\n\tu8 register_num;\n};\n\nstruct acpi_table_rsdp {\n\tchar signature[8];\n\tu8 checksum;\n\tchar oem_id[6];\n\tu8 revision;\n\tu32 rsdt_physical_address;\n\tu32 length;\n\tu64 xsdt_physical_address;\n\tu8 extended_checksum;\n\tu8 reserved[3];\n} __attribute__((packed));\n\nstruct acpi_pkg_info {\n\tu8 *free_space;\n\tacpi_size length;\n\tu32 object_space;\n\tu32 num_packages;\n};\n\nstruct acpi_exception_info {\n\tchar *name;\n};\n\ntypedef acpi_status (*acpi_pkg_callback)(u8, union acpi_operand_object *, union acpi_generic_state *, void *);\n\ntypedef u32 acpi_mutex_handle;\n\ntypedef acpi_status (*acpi_walk_aml_callback)(u8 *, u32, u32, u8, void **);\n\nenum led_brightness {\n\tLED_OFF = 0,\n\tLED_ON = 1,\n\tLED_HALF = 127,\n\tLED_FULL = 255,\n};\n\nstruct led_pattern;\n\nstruct led_trigger;\n\nstruct led_classdev {\n\tconst char *name;\n\tenum led_brightness brightness;\n\tenum led_brightness max_brightness;\n\tint flags;\n\tlong unsigned int work_flags;\n\tvoid (*brightness_set)(struct led_classdev *, enum led_brightness);\n\tint (*brightness_set_blocking)(struct led_classdev *, enum led_brightness);\n\tenum led_brightness (*brightness_get)(struct led_classdev *);\n\tint (*blink_set)(struct led_classdev *, long unsigned int *, long unsigned int *);\n\tint (*pattern_set)(struct led_classdev *, struct led_pattern *, u32, int);\n\tint (*pattern_clear)(struct led_classdev *);\n\tstruct device *dev;\n\tconst struct attribute_group **groups;\n\tstruct list_head node;\n\tconst char *default_trigger;\n\tlong unsigned int blink_delay_on;\n\tlong unsigned int blink_delay_off;\n\tstruct timer_list blink_timer;\n\tint blink_brightness;\n\tint new_blink_brightness;\n\tvoid (*flash_resume)(struct led_classdev *);\n\tstruct work_struct set_brightness_work;\n\tint delayed_set_value;\n\tstruct rw_semaphore trigger_lock;\n\tstruct led_trigger *trigger;\n\tstruct list_head trig_list;\n\tvoid *trigger_data;\n\tbool activated;\n\tstruct mutex led_access;\n};\n\nstruct led_pattern {\n\tu32 delta_t;\n\tint brightness;\n};\n\nstruct led_trigger {\n\tconst char *name;\n\tint (*activate)(struct led_classdev *);\n\tvoid (*deactivate)(struct led_classdev *);\n\trwlock_t leddev_list_lock;\n\tstruct list_head led_cdevs;\n\tstruct list_head next_trig;\n\tconst struct attribute_group **groups;\n};\n\nenum power_supply_property {\n\tPOWER_SUPPLY_PROP_STATUS = 0,\n\tPOWER_SUPPLY_PROP_CHARGE_TYPE = 1,\n\tPOWER_SUPPLY_PROP_HEALTH = 2,\n\tPOWER_SUPPLY_PROP_PRESENT = 3,\n\tPOWER_SUPPLY_PROP_ONLINE = 4,\n\tPOWER_SUPPLY_PROP_AUTHENTIC = 5,\n\tPOWER_SUPPLY_PROP_TECHNOLOGY = 6,\n\tPOWER_SUPPLY_PROP_CYCLE_COUNT = 7,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MAX = 8,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MIN = 9,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN = 10,\n\tPOWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN = 11,\n\tPOWER_SUPPLY_PROP_VOLTAGE_NOW = 12,\n\tPOWER_SUPPLY_PROP_VOLTAGE_AVG = 13,\n\tPOWER_SUPPLY_PROP_VOLTAGE_OCV = 14,\n\tPOWER_SUPPLY_PROP_VOLTAGE_BOOT = 15,\n\tPOWER_SUPPLY_PROP_CURRENT_MAX = 16,\n\tPOWER_SUPPLY_PROP_CURRENT_NOW = 17,\n\tPOWER_SUPPLY_PROP_CURRENT_AVG = 18,\n\tPOWER_SUPPLY_PROP_CURRENT_BOOT = 19,\n\tPOWER_SUPPLY_PROP_POWER_NOW = 20,\n\tPOWER_SUPPLY_PROP_POWER_AVG = 21,\n\tPOWER_SUPPLY_PROP_CHARGE_FULL_DESIGN = 22,\n\tPOWER_SUPPLY_PROP_CHARGE_EMPTY_DESIGN = 23,\n\tPOWER_SUPPLY_PROP_CHARGE_FULL = 24,\n\tPOWER_SUPPLY_PROP_CHARGE_EMPTY = 25,\n\tPOWER_SUPPLY_PROP_CHARGE_NOW = 26,\n\tPOWER_SUPPLY_PROP_CHARGE_AVG = 27,\n\tPOWER_SUPPLY_PROP_CHARGE_COUNTER = 28,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT = 29,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX = 30,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE = 31,\n\tPOWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX = 32,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT = 33,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT_MAX = 34,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_START_THRESHOLD = 35,\n\tPOWER_SUPPLY_PROP_CHARGE_CONTROL_END_THRESHOLD = 36,\n\tPOWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT = 37,\n\tPOWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT = 38,\n\tPOWER_SUPPLY_PROP_INPUT_POWER_LIMIT = 39,\n\tPOWER_SUPPLY_PROP_ENERGY_FULL_DESIGN = 40,\n\tPOWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN = 41,\n\tPOWER_SUPPLY_PROP_ENERGY_FULL = 42,\n\tPOWER_SUPPLY_PROP_ENERGY_EMPTY = 43,\n\tPOWER_SUPPLY_PROP_ENERGY_NOW = 44,\n\tPOWER_SUPPLY_PROP_ENERGY_AVG = 45,\n\tPOWER_SUPPLY_PROP_CAPACITY = 46,\n\tPOWER_SUPPLY_PROP_CAPACITY_ALERT_MIN = 47,\n\tPOWER_SUPPLY_PROP_CAPACITY_ALERT_MAX = 48,\n\tPOWER_SUPPLY_PROP_CAPACITY_ERROR_MARGIN = 49,\n\tPOWER_SUPPLY_PROP_CAPACITY_LEVEL = 50,\n\tPOWER_SUPPLY_PROP_TEMP = 51,\n\tPOWER_SUPPLY_PROP_TEMP_MAX = 52,\n\tPOWER_SUPPLY_PROP_TEMP_MIN = 53,\n\tPOWER_SUPPLY_PROP_TEMP_ALERT_MIN = 54,\n\tPOWER_SUPPLY_PROP_TEMP_ALERT_MAX = 55,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT = 56,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MIN = 57,\n\tPOWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MAX = 58,\n\tPOWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW = 59,\n\tPOWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG = 60,\n\tPOWER_SUPPLY_PROP_TIME_TO_FULL_NOW = 61,\n\tPOWER_SUPPLY_PROP_TIME_TO_FULL_AVG = 62,\n\tPOWER_SUPPLY_PROP_TYPE = 63,\n\tPOWER_SUPPLY_PROP_USB_TYPE = 64,\n\tPOWER_SUPPLY_PROP_SCOPE = 65,\n\tPOWER_SUPPLY_PROP_PRECHARGE_CURRENT = 66,\n\tPOWER_SUPPLY_PROP_CHARGE_TERM_CURRENT = 67,\n\tPOWER_SUPPLY_PROP_CALIBRATE = 68,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_YEAR = 69,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_MONTH = 70,\n\tPOWER_SUPPLY_PROP_MANUFACTURE_DAY = 71,\n\tPOWER_SUPPLY_PROP_MODEL_NAME = 72,\n\tPOWER_SUPPLY_PROP_MANUFACTURER = 73,\n\tPOWER_SUPPLY_PROP_SERIAL_NUMBER = 74,\n};\n\nenum power_supply_type {\n\tPOWER_SUPPLY_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_TYPE_BATTERY = 1,\n\tPOWER_SUPPLY_TYPE_UPS = 2,\n\tPOWER_SUPPLY_TYPE_MAINS = 3,\n\tPOWER_SUPPLY_TYPE_USB = 4,\n\tPOWER_SUPPLY_TYPE_USB_DCP = 5,\n\tPOWER_SUPPLY_TYPE_USB_CDP = 6,\n\tPOWER_SUPPLY_TYPE_USB_ACA = 7,\n\tPOWER_SUPPLY_TYPE_USB_TYPE_C = 8,\n\tPOWER_SUPPLY_TYPE_USB_PD = 9,\n\tPOWER_SUPPLY_TYPE_USB_PD_DRP = 10,\n\tPOWER_SUPPLY_TYPE_APPLE_BRICK_ID = 11,\n};\n\nenum power_supply_usb_type {\n\tPOWER_SUPPLY_USB_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_USB_TYPE_SDP = 1,\n\tPOWER_SUPPLY_USB_TYPE_DCP = 2,\n\tPOWER_SUPPLY_USB_TYPE_CDP = 3,\n\tPOWER_SUPPLY_USB_TYPE_ACA = 4,\n\tPOWER_SUPPLY_USB_TYPE_C = 5,\n\tPOWER_SUPPLY_USB_TYPE_PD = 6,\n\tPOWER_SUPPLY_USB_TYPE_PD_DRP = 7,\n\tPOWER_SUPPLY_USB_TYPE_PD_PPS = 8,\n\tPOWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID = 9,\n};\n\nunion power_supply_propval {\n\tint intval;\n\tconst char *strval;\n};\n\nstruct power_supply_config {\n\tstruct device_node *of_node;\n\tstruct fwnode_handle *fwnode;\n\tvoid *drv_data;\n\tconst struct attribute_group **attr_grp;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n};\n\nstruct power_supply;\n\nstruct power_supply_desc {\n\tconst char *name;\n\tenum power_supply_type type;\n\tconst enum power_supply_usb_type *usb_types;\n\tsize_t num_usb_types;\n\tconst enum power_supply_property *properties;\n\tsize_t num_properties;\n\tint (*get_property)(struct power_supply *, enum power_supply_property, union power_supply_propval *);\n\tint (*set_property)(struct power_supply *, enum power_supply_property, const union power_supply_propval *);\n\tint (*property_is_writeable)(struct power_supply *, enum power_supply_property);\n\tvoid (*external_power_changed)(struct power_supply *);\n\tvoid (*set_charged)(struct power_supply *);\n\tbool no_thermal;\n\tint use_for_apm;\n};\n\nstruct power_supply {\n\tconst struct power_supply_desc *desc;\n\tchar **supplied_to;\n\tsize_t num_supplicants;\n\tchar **supplied_from;\n\tsize_t num_supplies;\n\tstruct device_node *of_node;\n\tvoid *drv_data;\n\tstruct device dev;\n\tstruct work_struct changed_work;\n\tstruct delayed_work deferred_register_work;\n\tspinlock_t changed_lock;\n\tbool changed;\n\tbool initialized;\n\tbool removing;\n\tatomic_t use_cnt;\n\tstruct thermal_zone_device *tzd;\n\tstruct thermal_cooling_device *tcd;\n\tstruct led_trigger *charging_full_trig;\n\tchar *charging_full_trig_name;\n\tstruct led_trigger *charging_trig;\n\tchar *charging_trig_name;\n\tstruct led_trigger *full_trig;\n\tchar *full_trig_name;\n\tstruct led_trigger *online_trig;\n\tchar *online_trig_name;\n\tstruct led_trigger *charging_blink_full_solid_trig;\n\tchar *charging_blink_full_solid_trig_name;\n};\n\nstruct acpi_ac_bl {\n\tconst char *hid;\n\tint hrv;\n};\n\nstruct acpi_ac {\n\tstruct power_supply *charger;\n\tstruct power_supply_desc charger_desc;\n\tstruct acpi_device *device;\n\tlong long unsigned int state;\n\tstruct notifier_block battery_nb;\n};\n\nstruct input_id {\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n};\n\nstruct input_absinfo {\n\t__s32 value;\n\t__s32 minimum;\n\t__s32 maximum;\n\t__s32 fuzz;\n\t__s32 flat;\n\t__s32 resolution;\n};\n\nstruct input_keymap_entry {\n\t__u8 flags;\n\t__u8 len;\n\t__u16 index;\n\t__u32 keycode;\n\t__u8 scancode[32];\n};\n\nstruct ff_replay {\n\t__u16 length;\n\t__u16 delay;\n};\n\nstruct ff_trigger {\n\t__u16 button;\n\t__u16 interval;\n};\n\nstruct ff_envelope {\n\t__u16 attack_length;\n\t__u16 attack_level;\n\t__u16 fade_length;\n\t__u16 fade_level;\n};\n\nstruct ff_constant_effect {\n\t__s16 level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_ramp_effect {\n\t__s16 start_level;\n\t__s16 end_level;\n\tstruct ff_envelope envelope;\n};\n\nstruct ff_condition_effect {\n\t__u16 right_saturation;\n\t__u16 left_saturation;\n\t__s16 right_coeff;\n\t__s16 left_coeff;\n\t__u16 deadband;\n\t__s16 center;\n};\n\nstruct ff_periodic_effect {\n\t__u16 waveform;\n\t__u16 period;\n\t__s16 magnitude;\n\t__s16 offset;\n\t__u16 phase;\n\tstruct ff_envelope envelope;\n\t__u32 custom_len;\n\t__s16 *custom_data;\n};\n\nstruct ff_rumble_effect {\n\t__u16 strong_magnitude;\n\t__u16 weak_magnitude;\n};\n\nstruct ff_effect {\n\t__u16 type;\n\t__s16 id;\n\t__u16 direction;\n\tstruct ff_trigger trigger;\n\tstruct ff_replay replay;\n\tunion {\n\t\tstruct ff_constant_effect constant;\n\t\tstruct ff_ramp_effect ramp;\n\t\tstruct ff_periodic_effect periodic;\n\t\tstruct ff_condition_effect condition[2];\n\t\tstruct ff_rumble_effect rumble;\n\t} u;\n};\n\nstruct input_device_id {\n\tkernel_ulong_t flags;\n\t__u16 bustype;\n\t__u16 vendor;\n\t__u16 product;\n\t__u16 version;\n\tkernel_ulong_t evbit[1];\n\tkernel_ulong_t keybit[12];\n\tkernel_ulong_t relbit[1];\n\tkernel_ulong_t absbit[1];\n\tkernel_ulong_t mscbit[1];\n\tkernel_ulong_t ledbit[1];\n\tkernel_ulong_t sndbit[1];\n\tkernel_ulong_t ffbit[2];\n\tkernel_ulong_t swbit[1];\n\tkernel_ulong_t propbit[1];\n\tkernel_ulong_t driver_info;\n};\n\nstruct input_value {\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nenum input_clock_type {\n\tINPUT_CLK_REAL = 0,\n\tINPUT_CLK_MONO = 1,\n\tINPUT_CLK_BOOT = 2,\n\tINPUT_CLK_MAX = 3,\n};\n\nstruct ff_device;\n\nstruct input_dev_poller;\n\nstruct input_mt;\n\nstruct input_handle;\n\nstruct input_dev {\n\tconst char *name;\n\tconst char *phys;\n\tconst char *uniq;\n\tstruct input_id id;\n\tlong unsigned int propbit[1];\n\tlong unsigned int evbit[1];\n\tlong unsigned int keybit[12];\n\tlong unsigned int relbit[1];\n\tlong unsigned int absbit[1];\n\tlong unsigned int mscbit[1];\n\tlong unsigned int ledbit[1];\n\tlong unsigned int sndbit[1];\n\tlong unsigned int ffbit[2];\n\tlong unsigned int swbit[1];\n\tunsigned int hint_events_per_packet;\n\tunsigned int keycodemax;\n\tunsigned int keycodesize;\n\tvoid *keycode;\n\tint (*setkeycode)(struct input_dev *, const struct input_keymap_entry *, unsigned int *);\n\tint (*getkeycode)(struct input_dev *, struct input_keymap_entry *);\n\tstruct ff_device *ff;\n\tstruct input_dev_poller *poller;\n\tunsigned int repeat_key;\n\tstruct timer_list timer;\n\tint rep[2];\n\tstruct input_mt *mt;\n\tstruct input_absinfo *absinfo;\n\tlong unsigned int key[12];\n\tlong unsigned int led[1];\n\tlong unsigned int snd[1];\n\tlong unsigned int sw[1];\n\tint (*open)(struct input_dev *);\n\tvoid (*close)(struct input_dev *);\n\tint (*flush)(struct input_dev *, struct file *);\n\tint (*event)(struct input_dev *, unsigned int, unsigned int, int);\n\tstruct input_handle *grab;\n\tspinlock_t event_lock;\n\tstruct mutex mutex;\n\tunsigned int users;\n\tbool going_away;\n\tstruct device dev;\n\tstruct list_head h_list;\n\tstruct list_head node;\n\tunsigned int num_vals;\n\tunsigned int max_vals;\n\tstruct input_value *vals;\n\tbool devres_managed;\n\tktime_t timestamp[3];\n};\n\nstruct ff_device {\n\tint (*upload)(struct input_dev *, struct ff_effect *, struct ff_effect *);\n\tint (*erase)(struct input_dev *, int);\n\tint (*playback)(struct input_dev *, int, int);\n\tvoid (*set_gain)(struct input_dev *, u16);\n\tvoid (*set_autocenter)(struct input_dev *, u16);\n\tvoid (*destroy)(struct ff_device *);\n\tvoid *private;\n\tlong unsigned int ffbit[2];\n\tstruct mutex mutex;\n\tint max_effects;\n\tstruct ff_effect *effects;\n\tstruct file *effect_owners[0];\n};\n\nstruct input_handler;\n\nstruct input_handle {\n\tvoid *private;\n\tint open;\n\tconst char *name;\n\tstruct input_dev *dev;\n\tstruct input_handler *handler;\n\tstruct list_head d_node;\n\tstruct list_head h_node;\n};\n\nstruct input_handler {\n\tvoid *private;\n\tvoid (*event)(struct input_handle *, unsigned int, unsigned int, int);\n\tvoid (*events)(struct input_handle *, const struct input_value *, unsigned int);\n\tbool (*filter)(struct input_handle *, unsigned int, unsigned int, int);\n\tbool (*match)(struct input_handler *, struct input_dev *);\n\tint (*connect)(struct input_handler *, struct input_dev *, const struct input_device_id *);\n\tvoid (*disconnect)(struct input_handle *);\n\tvoid (*start)(struct input_handle *);\n\tbool legacy_minors;\n\tint minor;\n\tconst char *name;\n\tconst struct input_device_id *id_table;\n\tstruct list_head h_list;\n\tstruct list_head node;\n};\n\nenum {\n\tACPI_BUTTON_LID_INIT_IGNORE = 0,\n\tACPI_BUTTON_LID_INIT_OPEN = 1,\n\tACPI_BUTTON_LID_INIT_METHOD = 2,\n\tACPI_BUTTON_LID_INIT_DISABLED = 3,\n};\n\nstruct acpi_button {\n\tunsigned int type;\n\tstruct input_dev *input;\n\tchar phys[32];\n\tlong unsigned int pushed;\n\tint last_state;\n\tktime_t last_time;\n\tbool suspended;\n};\n\nstruct acpi_fan_fps {\n\tu64 control;\n\tu64 trip_point;\n\tu64 speed;\n\tu64 noise_level;\n\tu64 power;\n\tchar name[20];\n\tstruct device_attribute dev_attr;\n};\n\nstruct acpi_fan_fif {\n\tu64 revision;\n\tu64 fine_grain_ctrl;\n\tu64 step_size;\n\tu64 low_speed_notification;\n};\n\nstruct acpi_fan {\n\tbool acpi4;\n\tstruct acpi_fan_fif fif;\n\tstruct acpi_fan_fps *fps;\n\tint fps_count;\n\tstruct thermal_cooling_device *cdev;\n};\n\nstruct acpi_video_brightness_flags {\n\tu8 _BCL_no_ac_battery_levels: 1;\n\tu8 _BCL_reversed: 1;\n\tu8 _BQC_use_index: 1;\n};\n\nstruct acpi_video_device_brightness {\n\tint curr;\n\tint count;\n\tint *levels;\n\tstruct acpi_video_brightness_flags flags;\n};\n\nenum acpi_backlight_type {\n\tacpi_backlight_undef = 4294967295,\n\tacpi_backlight_none = 0,\n\tacpi_backlight_video = 1,\n\tacpi_backlight_vendor = 2,\n\tacpi_backlight_native = 3,\n};\n\nenum acpi_video_level_idx {\n\tACPI_VIDEO_AC_LEVEL = 0,\n\tACPI_VIDEO_BATTERY_LEVEL = 1,\n\tACPI_VIDEO_FIRST_LEVEL = 2,\n};\n\nstruct acpi_video_bus_flags {\n\tu8 multihead: 1;\n\tu8 rom: 1;\n\tu8 post: 1;\n\tu8 reserved: 5;\n};\n\nstruct acpi_video_bus_cap {\n\tu8 _DOS: 1;\n\tu8 _DOD: 1;\n\tu8 _ROM: 1;\n\tu8 _GPD: 1;\n\tu8 _SPD: 1;\n\tu8 _VPO: 1;\n\tu8 reserved: 2;\n};\n\nstruct acpi_video_device_attrib {\n\tu32 display_index: 4;\n\tu32 display_port_attachment: 4;\n\tu32 display_type: 4;\n\tu32 vendor_specific: 4;\n\tu32 bios_can_detect: 1;\n\tu32 depend_on_vga: 1;\n\tu32 pipe_id: 3;\n\tu32 reserved: 10;\n\tu32 device_id_scheme: 1;\n};\n\nstruct acpi_video_device;\n\nstruct acpi_video_enumerated_device {\n\tunion {\n\t\tu32 int_val;\n\t\tstruct acpi_video_device_attrib attrib;\n\t} value;\n\tstruct acpi_video_device *bind_info;\n};\n\nstruct acpi_video_device_flags {\n\tu8 crt: 1;\n\tu8 lcd: 1;\n\tu8 tvout: 1;\n\tu8 dvi: 1;\n\tu8 bios: 1;\n\tu8 unknown: 1;\n\tu8 notify: 1;\n\tu8 reserved: 1;\n};\n\nstruct acpi_video_device_cap {\n\tu8 _ADR: 1;\n\tu8 _BCL: 1;\n\tu8 _BCM: 1;\n\tu8 _BQC: 1;\n\tu8 _BCQ: 1;\n\tu8 _DDC: 1;\n};\n\nstruct acpi_video_bus;\n\nstruct acpi_video_device {\n\tlong unsigned int device_id;\n\tstruct acpi_video_device_flags flags;\n\tstruct acpi_video_device_cap cap;\n\tstruct list_head entry;\n\tstruct delayed_work switch_brightness_work;\n\tint switch_brightness_event;\n\tstruct acpi_video_bus *video;\n\tstruct acpi_device *dev;\n\tstruct acpi_video_device_brightness *brightness;\n\tstruct backlight_device *backlight;\n\tstruct thermal_cooling_device *cooling_dev;\n};\n\nstruct acpi_video_bus {\n\tstruct acpi_device *device;\n\tbool backlight_registered;\n\tu8 dos_setting;\n\tstruct acpi_video_enumerated_device *attached_array;\n\tu8 attached_count;\n\tu8 child_count;\n\tstruct acpi_video_bus_cap cap;\n\tstruct acpi_video_bus_flags flags;\n\tstruct list_head video_device_list;\n\tstruct mutex device_list_lock;\n\tstruct list_head entry;\n\tstruct input_dev *input;\n\tchar phys[32];\n\tstruct notifier_block pm_nb;\n};\n\nstruct acpi_lpi_states_array {\n\tunsigned int size;\n\tunsigned int composite_states_size;\n\tstruct acpi_lpi_state *entries;\n\tstruct acpi_lpi_state *composite_states[8];\n};\n\nstruct throttling_tstate {\n\tunsigned int cpu;\n\tint target_state;\n};\n\nstruct acpi_processor_throttling_arg {\n\tstruct acpi_processor *pr;\n\tint target_state;\n\tbool force;\n};\n\nstruct container_dev {\n\tstruct device dev;\n\tint (*offline)(struct container_dev *);\n};\n\nstruct acpi_thermal_state {\n\tu8 critical: 1;\n\tu8 hot: 1;\n\tu8 passive: 1;\n\tu8 active: 1;\n\tu8 reserved: 4;\n\tint active_index;\n};\n\nstruct acpi_thermal_state_flags {\n\tu8 valid: 1;\n\tu8 enabled: 1;\n\tu8 reserved: 6;\n};\n\nstruct acpi_thermal_critical {\n\tstruct acpi_thermal_state_flags flags;\n\tlong unsigned int temperature;\n};\n\nstruct acpi_thermal_hot {\n\tstruct acpi_thermal_state_flags flags;\n\tlong unsigned int temperature;\n};\n\nstruct acpi_thermal_passive {\n\tstruct acpi_thermal_state_flags flags;\n\tlong unsigned int temperature;\n\tlong unsigned int tc1;\n\tlong unsigned int tc2;\n\tlong unsigned int tsp;\n\tstruct acpi_handle_list devices;\n};\n\nstruct acpi_thermal_active {\n\tstruct acpi_thermal_state_flags flags;\n\tlong unsigned int temperature;\n\tstruct acpi_handle_list devices;\n};\n\nstruct acpi_thermal_trips {\n\tstruct acpi_thermal_critical critical;\n\tstruct acpi_thermal_hot hot;\n\tstruct acpi_thermal_passive passive;\n\tstruct acpi_thermal_active active[10];\n};\n\nstruct acpi_thermal_flags {\n\tu8 cooling_mode: 1;\n\tu8 devices: 1;\n\tu8 reserved: 6;\n};\n\nstruct acpi_thermal {\n\tstruct acpi_device *device;\n\tacpi_bus_id name;\n\tlong unsigned int temperature;\n\tlong unsigned int last_temperature;\n\tlong unsigned int polling_frequency;\n\tvolatile u8 zombie;\n\tstruct acpi_thermal_flags flags;\n\tstruct acpi_thermal_state state;\n\tstruct acpi_thermal_trips trips;\n\tstruct acpi_handle_list devices;\n\tstruct thermal_zone_device *thermal_zone;\n\tint tz_enabled;\n\tint kelvin_offset;\n\tstruct work_struct thermal_check_work;\n};\n\nstruct acpi_table_slit {\n\tstruct acpi_table_header header;\n\tu64 locality_count;\n\tu8 entry[1];\n} __attribute__((packed));\n\nstruct acpi_table_srat {\n\tstruct acpi_table_header header;\n\tu32 table_revision;\n\tu64 reserved;\n};\n\nenum acpi_srat_type {\n\tACPI_SRAT_TYPE_CPU_AFFINITY = 0,\n\tACPI_SRAT_TYPE_MEMORY_AFFINITY = 1,\n\tACPI_SRAT_TYPE_X2APIC_CPU_AFFINITY = 2,\n\tACPI_SRAT_TYPE_GICC_AFFINITY = 3,\n\tACPI_SRAT_TYPE_GIC_ITS_AFFINITY = 4,\n\tACPI_SRAT_TYPE_GENERIC_AFFINITY = 5,\n\tACPI_SRAT_TYPE_RESERVED = 6,\n};\n\nstruct acpi_srat_mem_affinity {\n\tstruct acpi_subtable_header header;\n\tu32 proximity_domain;\n\tu16 reserved;\n\tu64 base_address;\n\tu64 length;\n\tu32 reserved1;\n\tu32 flags;\n\tu64 reserved2;\n} __attribute__((packed));\n\nstruct acpi_srat_gicc_affinity {\n\tstruct acpi_subtable_header header;\n\tu32 proximity_domain;\n\tu32 acpi_processor_uid;\n\tu32 flags;\n\tu32 clock_domain;\n} __attribute__((packed));\n\nstruct acpi_pci_ioapic {\n\tacpi_handle root_handle;\n\tacpi_handle handle;\n\tu32 gsi_base;\n\tstruct resource res;\n\tstruct pci_dev *pdev;\n\tstruct list_head list;\n};\n\nenum dmi_entry_type {\n\tDMI_ENTRY_BIOS = 0,\n\tDMI_ENTRY_SYSTEM = 1,\n\tDMI_ENTRY_BASEBOARD = 2,\n\tDMI_ENTRY_CHASSIS = 3,\n\tDMI_ENTRY_PROCESSOR = 4,\n\tDMI_ENTRY_MEM_CONTROLLER = 5,\n\tDMI_ENTRY_MEM_MODULE = 6,\n\tDMI_ENTRY_CACHE = 7,\n\tDMI_ENTRY_PORT_CONNECTOR = 8,\n\tDMI_ENTRY_SYSTEM_SLOT = 9,\n\tDMI_ENTRY_ONBOARD_DEVICE = 10,\n\tDMI_ENTRY_OEMSTRINGS = 11,\n\tDMI_ENTRY_SYSCONF = 12,\n\tDMI_ENTRY_BIOS_LANG = 13,\n\tDMI_ENTRY_GROUP_ASSOC = 14,\n\tDMI_ENTRY_SYSTEM_EVENT_LOG = 15,\n\tDMI_ENTRY_PHYS_MEM_ARRAY = 16,\n\tDMI_ENTRY_MEM_DEVICE = 17,\n\tDMI_ENTRY_32_MEM_ERROR = 18,\n\tDMI_ENTRY_MEM_ARRAY_MAPPED_ADDR = 19,\n\tDMI_ENTRY_MEM_DEV_MAPPED_ADDR = 20,\n\tDMI_ENTRY_BUILTIN_POINTING_DEV = 21,\n\tDMI_ENTRY_PORTABLE_BATTERY = 22,\n\tDMI_ENTRY_SYSTEM_RESET = 23,\n\tDMI_ENTRY_HW_SECURITY = 24,\n\tDMI_ENTRY_SYSTEM_POWER_CONTROLS = 25,\n\tDMI_ENTRY_VOLTAGE_PROBE = 26,\n\tDMI_ENTRY_COOLING_DEV = 27,\n\tDMI_ENTRY_TEMP_PROBE = 28,\n\tDMI_ENTRY_ELECTRICAL_CURRENT_PROBE = 29,\n\tDMI_ENTRY_OOB_REMOTE_ACCESS = 30,\n\tDMI_ENTRY_BIS_ENTRY = 31,\n\tDMI_ENTRY_SYSTEM_BOOT = 32,\n\tDMI_ENTRY_MGMT_DEV = 33,\n\tDMI_ENTRY_MGMT_DEV_COMPONENT = 34,\n\tDMI_ENTRY_MGMT_DEV_THRES = 35,\n\tDMI_ENTRY_MEM_CHANNEL = 36,\n\tDMI_ENTRY_IPMI_DEV = 37,\n\tDMI_ENTRY_SYS_POWER_SUPPLY = 38,\n\tDMI_ENTRY_ADDITIONAL = 39,\n\tDMI_ENTRY_ONBOARD_DEV_EXT = 40,\n\tDMI_ENTRY_MGMT_CONTROLLER_HOST = 41,\n\tDMI_ENTRY_INACTIVE = 126,\n\tDMI_ENTRY_END_OF_TABLE = 127,\n};\n\nstruct dmi_header {\n\tu8 type;\n\tu8 length;\n\tu16 handle;\n};\n\nenum {\n\tPOWER_SUPPLY_STATUS_UNKNOWN = 0,\n\tPOWER_SUPPLY_STATUS_CHARGING = 1,\n\tPOWER_SUPPLY_STATUS_DISCHARGING = 2,\n\tPOWER_SUPPLY_STATUS_NOT_CHARGING = 3,\n\tPOWER_SUPPLY_STATUS_FULL = 4,\n};\n\nenum {\n\tPOWER_SUPPLY_TECHNOLOGY_UNKNOWN = 0,\n\tPOWER_SUPPLY_TECHNOLOGY_NiMH = 1,\n\tPOWER_SUPPLY_TECHNOLOGY_LION = 2,\n\tPOWER_SUPPLY_TECHNOLOGY_LIPO = 3,\n\tPOWER_SUPPLY_TECHNOLOGY_LiFe = 4,\n\tPOWER_SUPPLY_TECHNOLOGY_NiCd = 5,\n\tPOWER_SUPPLY_TECHNOLOGY_LiMn = 6,\n};\n\nenum {\n\tPOWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN = 0,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_CRITICAL = 1,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_LOW = 2,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_NORMAL = 3,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_HIGH = 4,\n\tPOWER_SUPPLY_CAPACITY_LEVEL_FULL = 5,\n};\n\nstruct acpi_battery_hook {\n\tconst char *name;\n\tint (*add_battery)(struct power_supply *);\n\tint (*remove_battery)(struct power_supply *);\n\tstruct list_head list;\n};\n\nenum {\n\tACPI_BATTERY_ALARM_PRESENT = 0,\n\tACPI_BATTERY_XINFO_PRESENT = 1,\n\tACPI_BATTERY_QUIRK_PERCENTAGE_CAPACITY = 2,\n\tACPI_BATTERY_QUIRK_THINKPAD_MAH = 3,\n\tACPI_BATTERY_QUIRK_DEGRADED_FULL_CHARGE = 4,\n};\n\nstruct acpi_battery {\n\tstruct mutex lock;\n\tstruct mutex sysfs_lock;\n\tstruct power_supply *bat;\n\tstruct power_supply_desc bat_desc;\n\tstruct acpi_device *device;\n\tstruct notifier_block pm_nb;\n\tstruct list_head list;\n\tlong unsigned int update_time;\n\tint revision;\n\tint rate_now;\n\tint capacity_now;\n\tint voltage_now;\n\tint design_capacity;\n\tint full_charge_capacity;\n\tint technology;\n\tint design_voltage;\n\tint design_capacity_warning;\n\tint design_capacity_low;\n\tint cycle_count;\n\tint measurement_accuracy;\n\tint max_sampling_time;\n\tint min_sampling_time;\n\tint max_averaging_interval;\n\tint min_averaging_interval;\n\tint capacity_granularity_1;\n\tint capacity_granularity_2;\n\tint alarm;\n\tchar model_number[32];\n\tchar serial_number[32];\n\tchar type[32];\n\tchar oem_info[32];\n\tint state;\n\tint power_unit;\n\tlong unsigned int flags;\n};\n\nstruct acpi_offsets {\n\tsize_t offset;\n\tu8 mode;\n};\n\nstruct acpi_pcct_hw_reduced {\n\tstruct acpi_subtable_header header;\n\tu32 platform_interrupt;\n\tu8 flags;\n\tu8 reserved;\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n} __attribute__((packed));\n\nstruct acpi_pcct_shared_memory {\n\tu32 signature;\n\tu16 command;\n\tu16 status;\n};\n\nstruct mbox_chan;\n\nstruct mbox_chan_ops {\n\tint (*send_data)(struct mbox_chan *, void *);\n\tint (*flush)(struct mbox_chan *, long unsigned int);\n\tint (*startup)(struct mbox_chan *);\n\tvoid (*shutdown)(struct mbox_chan *);\n\tbool (*last_tx_done)(struct mbox_chan *);\n\tbool (*peek_data)(struct mbox_chan *);\n};\n\nstruct mbox_controller;\n\nstruct mbox_client;\n\nstruct mbox_chan {\n\tstruct mbox_controller *mbox;\n\tunsigned int txdone_method;\n\tstruct mbox_client *cl;\n\tstruct completion tx_complete;\n\tvoid *active_req;\n\tunsigned int msg_count;\n\tunsigned int msg_free;\n\tvoid *msg_data[20];\n\tspinlock_t lock;\n\tvoid *con_priv;\n};\n\nstruct mbox_controller {\n\tstruct device *dev;\n\tconst struct mbox_chan_ops *ops;\n\tstruct mbox_chan *chans;\n\tint num_chans;\n\tbool txdone_irq;\n\tbool txdone_poll;\n\tunsigned int txpoll_period;\n\tstruct mbox_chan * (*of_xlate)(struct mbox_controller *, const struct of_phandle_args *);\n\tstruct hrtimer poll_hrt;\n\tstruct list_head node;\n};\n\nstruct mbox_client {\n\tstruct device *dev;\n\tbool tx_block;\n\tlong unsigned int tx_tout;\n\tbool knows_txdone;\n\tvoid (*rx_callback)(struct mbox_client *, void *);\n\tvoid (*tx_prepare)(struct mbox_client *, void *);\n\tvoid (*tx_done)(struct mbox_client *, void *, int);\n};\n\nstruct cpc_register_resource {\n\tacpi_object_type type;\n\tu64 *sys_mem_vaddr;\n\tunion {\n\t\tstruct cpc_reg reg;\n\t\tu64 int_value;\n\t} cpc_entry;\n};\n\nstruct cpc_desc {\n\tint num_entries;\n\tint version;\n\tint cpu_id;\n\tint write_cmd_status;\n\tint write_cmd_id;\n\tstruct cpc_register_resource cpc_regs[21];\n\tstruct acpi_psd_package domain_info;\n\tstruct kobject kobj;\n};\n\nenum cppc_regs {\n\tHIGHEST_PERF = 0,\n\tNOMINAL_PERF = 1,\n\tLOW_NON_LINEAR_PERF = 2,\n\tLOWEST_PERF = 3,\n\tGUARANTEED_PERF = 4,\n\tDESIRED_PERF = 5,\n\tMIN_PERF = 6,\n\tMAX_PERF = 7,\n\tPERF_REDUC_TOLERANCE = 8,\n\tTIME_WINDOW = 9,\n\tCTR_WRAP_TIME = 10,\n\tREFERENCE_CTR = 11,\n\tDELIVERED_CTR = 12,\n\tPERF_LIMITED = 13,\n\tENABLE = 14,\n\tAUTO_SEL_ENABLE = 15,\n\tAUTO_ACT_WINDOW = 16,\n\tENERGY_PERF = 17,\n\tREFERENCE_PERF = 18,\n\tLOWEST_FREQ = 19,\n\tNOMINAL_FREQ = 20,\n};\n\nstruct cppc_perf_caps {\n\tu32 guaranteed_perf;\n\tu32 highest_perf;\n\tu32 nominal_perf;\n\tu32 lowest_perf;\n\tu32 lowest_nonlinear_perf;\n\tu32 lowest_freq;\n\tu32 nominal_freq;\n};\n\nstruct cppc_perf_ctrls {\n\tu32 max_perf;\n\tu32 min_perf;\n\tu32 desired_perf;\n};\n\nstruct cppc_perf_fb_ctrs {\n\tu64 reference;\n\tu64 delivered;\n\tu64 reference_perf;\n\tu64 wraparound_time;\n};\n\nstruct cppc_cpudata {\n\tint cpu;\n\tstruct cppc_perf_caps perf_caps;\n\tstruct cppc_perf_ctrls perf_ctrls;\n\tstruct cppc_perf_fb_ctrs perf_fb_ctrs;\n\tstruct cpufreq_policy *cur_policy;\n\tunsigned int shared_type;\n\tcpumask_var_t shared_cpu_map;\n};\n\nstruct cppc_pcc_data {\n\tstruct mbox_chan *pcc_channel;\n\tvoid *pcc_comm_addr;\n\tbool pcc_channel_acquired;\n\tunsigned int deadline_us;\n\tunsigned int pcc_mpar;\n\tunsigned int pcc_mrtt;\n\tunsigned int pcc_nominal;\n\tbool pending_pcc_write_cmd;\n\tbool platform_owns_pcc;\n\tunsigned int pcc_write_cnt;\n\tstruct rw_semaphore pcc_lock;\n\twait_queue_head_t pcc_write_wait_q;\n\tktime_t last_cmd_cmpl_time;\n\tktime_t last_mpar_reset;\n\tint mpar_count;\n\tint refcount;\n};\n\nstruct cppc_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, const char *, ssize_t);\n};\n\nstruct pnp_resource {\n\tstruct list_head list;\n\tstruct resource res;\n};\n\nstruct pnp_port {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_size_t size;\n\tunsigned char flags;\n};\n\ntypedef struct {\n\tlong unsigned int bits[4];\n} pnp_irq_mask_t;\n\nstruct pnp_irq {\n\tpnp_irq_mask_t map;\n\tunsigned char flags;\n};\n\nstruct pnp_dma {\n\tunsigned char map;\n\tunsigned char flags;\n};\n\nstruct pnp_mem {\n\tresource_size_t min;\n\tresource_size_t max;\n\tresource_size_t align;\n\tresource_size_t size;\n\tunsigned char flags;\n};\n\nstruct pnp_option {\n\tstruct list_head list;\n\tunsigned int flags;\n\tlong unsigned int type;\n\tunion {\n\t\tstruct pnp_port port;\n\t\tstruct pnp_irq irq;\n\t\tstruct pnp_dma dma;\n\t\tstruct pnp_mem mem;\n\t} u;\n};\n\nstruct pnp_info_buffer {\n\tchar *buffer;\n\tchar *curr;\n\tlong unsigned int size;\n\tlong unsigned int len;\n\tint stop;\n\tint error;\n};\n\ntypedef struct pnp_info_buffer pnp_info_buffer_t;\n\nstruct pnp_fixup {\n\tchar id[7];\n\tvoid (*quirk_function)(struct pnp_dev *);\n};\n\nstruct acpipnp_parse_option_s {\n\tstruct pnp_dev *dev;\n\tunsigned int option_flags;\n};\n\nstruct clk_bulk_data {\n\tconst char *id;\n\tstruct clk *clk;\n};\n\nstruct clk_bulk_devres {\n\tstruct clk_bulk_data *clks;\n\tint num_clks;\n};\n\nstruct clk_lookup {\n\tstruct list_head node;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct clk *clk;\n\tstruct clk_hw *clk_hw;\n};\n\nstruct clk_lookup_alloc {\n\tstruct clk_lookup cl;\n\tchar dev_id[20];\n\tchar con_id[16];\n};\n\nstruct clk_notifier {\n\tstruct clk *clk;\n\tstruct srcu_notifier_head notifier_head;\n\tstruct list_head node;\n};\n\nstruct clk {\n\tstruct clk_core *core;\n\tstruct device *dev;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tunsigned int exclusive_count;\n\tstruct hlist_node clks_node;\n};\n\nstruct clk_notifier_data {\n\tstruct clk *clk;\n\tlong unsigned int old_rate;\n\tlong unsigned int new_rate;\n};\n\nstruct clk_parent_map;\n\nstruct clk_core {\n\tconst char *name;\n\tconst struct clk_ops *ops;\n\tstruct clk_hw *hw;\n\tstruct module *owner;\n\tstruct device *dev;\n\tstruct device_node *of_node;\n\tstruct clk_core *parent;\n\tstruct clk_parent_map *parents;\n\tu8 num_parents;\n\tu8 new_parent_index;\n\tlong unsigned int rate;\n\tlong unsigned int req_rate;\n\tlong unsigned int new_rate;\n\tstruct clk_core *new_parent;\n\tstruct clk_core *new_child;\n\tlong unsigned int flags;\n\tbool orphan;\n\tbool rpm_enabled;\n\tunsigned int enable_count;\n\tunsigned int prepare_count;\n\tunsigned int protect_count;\n\tlong unsigned int min_rate;\n\tlong unsigned int max_rate;\n\tlong unsigned int accuracy;\n\tint phase;\n\tstruct clk_duty duty;\n\tstruct hlist_head children;\n\tstruct hlist_node child_node;\n\tstruct hlist_head clks;\n\tunsigned int notifier_count;\n\tstruct dentry *dentry;\n\tstruct hlist_node debug_node;\n\tstruct kref ref;\n};\n\nstruct clk_parent_map {\n\tconst struct clk_hw *hw;\n\tstruct clk_core *core;\n\tconst char *fw_name;\n\tconst char *name;\n\tint index;\n};\n\nstruct trace_event_raw_clk {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_rate {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tlong unsigned int rate;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_parent {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_pname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_phase {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint phase;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_clk_duty_cycle {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int num;\n\tunsigned int den;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_clk {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_clk_rate {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_clk_parent {\n\tu32 name;\n\tu32 pname;\n};\n\nstruct trace_event_data_offsets_clk_phase {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_clk_duty_cycle {\n\tu32 name;\n};\n\ntypedef void (*btf_trace_clk_enable)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_enable_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_disable)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_disable_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_prepare)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_prepare_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_unprepare)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_unprepare_complete)(void *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_set_rate)(void *, struct clk_core *, long unsigned int);\n\ntypedef void (*btf_trace_clk_set_rate_complete)(void *, struct clk_core *, long unsigned int);\n\ntypedef void (*btf_trace_clk_set_parent)(void *, struct clk_core *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_set_parent_complete)(void *, struct clk_core *, struct clk_core *);\n\ntypedef void (*btf_trace_clk_set_phase)(void *, struct clk_core *, int);\n\ntypedef void (*btf_trace_clk_set_phase_complete)(void *, struct clk_core *, int);\n\ntypedef void (*btf_trace_clk_set_duty_cycle)(void *, struct clk_core *, struct clk_duty *);\n\ntypedef void (*btf_trace_clk_set_duty_cycle_complete)(void *, struct clk_core *, struct clk_duty *);\n\nstruct clk_div_table {\n\tunsigned int val;\n\tunsigned int div;\n};\n\nstruct clk_divider {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n\tconst struct clk_div_table *table;\n\tspinlock_t *lock;\n};\n\nstruct clk_fixed_factor {\n\tstruct clk_hw hw;\n\tunsigned int mult;\n\tunsigned int div;\n};\n\nstruct clk_fixed_rate {\n\tstruct clk_hw hw;\n\tlong unsigned int fixed_rate;\n\tlong unsigned int fixed_accuracy;\n\tlong unsigned int flags;\n};\n\nstruct clk_gate {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 bit_idx;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct clk_multiplier {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 shift;\n\tu8 width;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct clk_mux {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu32 *table;\n\tu32 mask;\n\tu8 shift;\n\tu8 flags;\n\tspinlock_t *lock;\n};\n\nstruct clk_composite {\n\tstruct clk_hw hw;\n\tstruct clk_ops ops;\n\tstruct clk_hw *mux_hw;\n\tstruct clk_hw *rate_hw;\n\tstruct clk_hw *gate_hw;\n\tconst struct clk_ops *mux_ops;\n\tconst struct clk_ops *rate_ops;\n\tconst struct clk_ops *gate_ops;\n};\n\nstruct clk_fractional_divider {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tu8 mshift;\n\tu8 mwidth;\n\tu32 mmask;\n\tu8 nshift;\n\tu8 nwidth;\n\tu32 nmask;\n\tu8 flags;\n\tvoid (*approximation)(struct clk_hw *, long unsigned int, long unsigned int *, long unsigned int *, long unsigned int *);\n\tspinlock_t *lock;\n};\n\nenum gpiod_flags {\n\tGPIOD_ASIS = 0,\n\tGPIOD_IN = 1,\n\tGPIOD_OUT_LOW = 3,\n\tGPIOD_OUT_HIGH = 7,\n\tGPIOD_OUT_LOW_OPEN_DRAIN = 11,\n\tGPIOD_OUT_HIGH_OPEN_DRAIN = 15,\n};\n\nstruct clk_gpio {\n\tstruct clk_hw hw;\n\tstruct gpio_desc *gpiod;\n};\n\nstruct pmc_clk {\n\tconst char *name;\n\tlong unsigned int freq;\n\tconst char *parent_name;\n};\n\nstruct pmc_clk_data {\n\tvoid *base;\n\tconst struct pmc_clk *clks;\n\tbool critical;\n};\n\nstruct clk_plt_fixed {\n\tstruct clk_hw *clk;\n\tstruct clk_lookup *lookup;\n};\n\nstruct clk_plt {\n\tstruct clk_hw hw;\n\tvoid *reg;\n\tstruct clk_lookup *lookup;\n\tspinlock_t lock;\n};\n\nstruct clk_plt_data {\n\tstruct clk_plt_fixed **parents;\n\tu8 nparents;\n\tstruct clk_plt *clks[6];\n\tstruct clk_lookup *mclk_lookup;\n\tstruct clk_lookup *ether_clk_lookup;\n};\n\ntypedef s32 dma_cookie_t;\n\nenum dma_status {\n\tDMA_COMPLETE = 0,\n\tDMA_IN_PROGRESS = 1,\n\tDMA_PAUSED = 2,\n\tDMA_ERROR = 3,\n};\n\nenum dma_transaction_type {\n\tDMA_MEMCPY = 0,\n\tDMA_XOR = 1,\n\tDMA_PQ = 2,\n\tDMA_XOR_VAL = 3,\n\tDMA_PQ_VAL = 4,\n\tDMA_MEMSET = 5,\n\tDMA_MEMSET_SG = 6,\n\tDMA_INTERRUPT = 7,\n\tDMA_PRIVATE = 8,\n\tDMA_ASYNC_TX = 9,\n\tDMA_SLAVE = 10,\n\tDMA_CYCLIC = 11,\n\tDMA_INTERLEAVE = 12,\n\tDMA_TX_TYPE_END = 13,\n};\n\nenum dma_transfer_direction {\n\tDMA_MEM_TO_MEM = 0,\n\tDMA_MEM_TO_DEV = 1,\n\tDMA_DEV_TO_MEM = 2,\n\tDMA_DEV_TO_DEV = 3,\n\tDMA_TRANS_NONE = 4,\n};\n\nstruct data_chunk {\n\tsize_t size;\n\tsize_t icg;\n\tsize_t dst_icg;\n\tsize_t src_icg;\n};\n\nstruct dma_interleaved_template {\n\tdma_addr_t src_start;\n\tdma_addr_t dst_start;\n\tenum dma_transfer_direction dir;\n\tbool src_inc;\n\tbool dst_inc;\n\tbool src_sgl;\n\tbool dst_sgl;\n\tsize_t numf;\n\tsize_t frame_size;\n\tstruct data_chunk sgl[0];\n};\n\nenum dma_ctrl_flags {\n\tDMA_PREP_INTERRUPT = 1,\n\tDMA_CTRL_ACK = 2,\n\tDMA_PREP_PQ_DISABLE_P = 4,\n\tDMA_PREP_PQ_DISABLE_Q = 8,\n\tDMA_PREP_CONTINUE = 16,\n\tDMA_PREP_FENCE = 32,\n\tDMA_CTRL_REUSE = 64,\n\tDMA_PREP_CMD = 128,\n};\n\nenum sum_check_bits {\n\tSUM_CHECK_P = 0,\n\tSUM_CHECK_Q = 1,\n};\n\nenum sum_check_flags {\n\tSUM_CHECK_P_RESULT = 1,\n\tSUM_CHECK_Q_RESULT = 2,\n};\n\ntypedef struct {\n\tlong unsigned int bits[1];\n} dma_cap_mask_t;\n\nenum dma_desc_metadata_mode {\n\tDESC_METADATA_NONE = 0,\n\tDESC_METADATA_CLIENT = 1,\n\tDESC_METADATA_ENGINE = 2,\n};\n\nstruct dma_chan_percpu {\n\tlong unsigned int memcpy_count;\n\tlong unsigned int bytes_transferred;\n};\n\nstruct dma_router {\n\tstruct device *dev;\n\tvoid (*route_free)(struct device *, void *);\n};\n\nstruct dma_device;\n\nstruct dma_chan_dev;\n\nstruct dma_chan___2 {\n\tstruct dma_device *device;\n\tstruct device *slave;\n\tdma_cookie_t cookie;\n\tdma_cookie_t completed_cookie;\n\tint chan_id;\n\tstruct dma_chan_dev *dev;\n\tconst char *name;\n\tchar *dbg_client_name;\n\tstruct list_head device_node;\n\tstruct dma_chan_percpu *local;\n\tint client_count;\n\tint table_count;\n\tstruct dma_router *router;\n\tvoid *route_data;\n\tvoid *private;\n};\n\ntypedef bool (*dma_filter_fn)(struct dma_chan___2 *, void *);\n\nstruct dma_slave_map;\n\nstruct dma_filter {\n\tdma_filter_fn fn;\n\tint mapcnt;\n\tconst struct dma_slave_map *map;\n};\n\nenum dmaengine_alignment {\n\tDMAENGINE_ALIGN_1_BYTE = 0,\n\tDMAENGINE_ALIGN_2_BYTES = 1,\n\tDMAENGINE_ALIGN_4_BYTES = 2,\n\tDMAENGINE_ALIGN_8_BYTES = 3,\n\tDMAENGINE_ALIGN_16_BYTES = 4,\n\tDMAENGINE_ALIGN_32_BYTES = 5,\n\tDMAENGINE_ALIGN_64_BYTES = 6,\n};\n\nenum dma_residue_granularity {\n\tDMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,\n\tDMA_RESIDUE_GRANULARITY_SEGMENT = 1,\n\tDMA_RESIDUE_GRANULARITY_BURST = 2,\n};\n\nstruct dma_async_tx_descriptor;\n\nstruct dma_slave_config;\n\nstruct dma_tx_state;\n\nstruct dma_device {\n\tstruct kref ref;\n\tunsigned int chancnt;\n\tunsigned int privatecnt;\n\tstruct list_head channels;\n\tstruct list_head global_node;\n\tstruct dma_filter filter;\n\tdma_cap_mask_t cap_mask;\n\tenum dma_desc_metadata_mode desc_metadata_modes;\n\tshort unsigned int max_xor;\n\tshort unsigned int max_pq;\n\tenum dmaengine_alignment copy_align;\n\tenum dmaengine_alignment xor_align;\n\tenum dmaengine_alignment pq_align;\n\tenum dmaengine_alignment fill_align;\n\tint dev_id;\n\tstruct device *dev;\n\tstruct module *owner;\n\tstruct ida chan_ida;\n\tstruct mutex chan_mutex;\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 max_burst;\n\tbool descriptor_reuse;\n\tenum dma_residue_granularity residue_granularity;\n\tint (*device_alloc_chan_resources)(struct dma_chan___2 *);\n\tvoid (*device_free_chan_resources)(struct dma_chan___2 *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memcpy)(struct dma_chan___2 *, dma_addr_t, dma_addr_t, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor)(struct dma_chan___2 *, dma_addr_t, dma_addr_t *, unsigned int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_xor_val)(struct dma_chan___2 *, dma_addr_t *, unsigned int, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq)(struct dma_chan___2 *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_pq_val)(struct dma_chan___2 *, dma_addr_t *, dma_addr_t *, unsigned int, const unsigned char *, size_t, enum sum_check_flags *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset)(struct dma_chan___2 *, dma_addr_t, int, size_t, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_memset_sg)(struct dma_chan___2 *, struct scatterlist *, unsigned int, int, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_interrupt)(struct dma_chan___2 *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_slave_sg)(struct dma_chan___2 *, struct scatterlist *, unsigned int, enum dma_transfer_direction, long unsigned int, void *);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_cyclic)(struct dma_chan___2 *, dma_addr_t, size_t, size_t, enum dma_transfer_direction, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_interleaved_dma)(struct dma_chan___2 *, struct dma_interleaved_template *, long unsigned int);\n\tstruct dma_async_tx_descriptor * (*device_prep_dma_imm_data)(struct dma_chan___2 *, dma_addr_t, u64, long unsigned int);\n\tint (*device_config)(struct dma_chan___2 *, struct dma_slave_config *);\n\tint (*device_pause)(struct dma_chan___2 *);\n\tint (*device_resume)(struct dma_chan___2 *);\n\tint (*device_terminate_all)(struct dma_chan___2 *);\n\tvoid (*device_synchronize)(struct dma_chan___2 *);\n\tenum dma_status (*device_tx_status)(struct dma_chan___2 *, dma_cookie_t, struct dma_tx_state *);\n\tvoid (*device_issue_pending)(struct dma_chan___2 *);\n\tvoid (*device_release)(struct dma_device *);\n\tvoid (*dbg_summary_show)(struct seq_file *, struct dma_device *);\n\tstruct dentry *dbg_dev_root;\n};\n\nstruct dma_chan_dev {\n\tstruct dma_chan___2 *chan;\n\tstruct device device;\n\tint dev_id;\n};\n\nenum dma_slave_buswidth {\n\tDMA_SLAVE_BUSWIDTH_UNDEFINED = 0,\n\tDMA_SLAVE_BUSWIDTH_1_BYTE = 1,\n\tDMA_SLAVE_BUSWIDTH_2_BYTES = 2,\n\tDMA_SLAVE_BUSWIDTH_3_BYTES = 3,\n\tDMA_SLAVE_BUSWIDTH_4_BYTES = 4,\n\tDMA_SLAVE_BUSWIDTH_8_BYTES = 8,\n\tDMA_SLAVE_BUSWIDTH_16_BYTES = 16,\n\tDMA_SLAVE_BUSWIDTH_32_BYTES = 32,\n\tDMA_SLAVE_BUSWIDTH_64_BYTES = 64,\n};\n\nstruct dma_slave_config {\n\tenum dma_transfer_direction direction;\n\tphys_addr_t src_addr;\n\tphys_addr_t dst_addr;\n\tenum dma_slave_buswidth src_addr_width;\n\tenum dma_slave_buswidth dst_addr_width;\n\tu32 src_maxburst;\n\tu32 dst_maxburst;\n\tu32 src_port_window_size;\n\tu32 dst_port_window_size;\n\tbool device_fc;\n\tunsigned int slave_id;\n};\n\nstruct dma_slave_caps {\n\tu32 src_addr_widths;\n\tu32 dst_addr_widths;\n\tu32 directions;\n\tu32 max_burst;\n\tbool cmd_pause;\n\tbool cmd_resume;\n\tbool cmd_terminate;\n\tenum dma_residue_granularity residue_granularity;\n\tbool descriptor_reuse;\n};\n\ntypedef void (*dma_async_tx_callback)(void *);\n\nenum dmaengine_tx_result {\n\tDMA_TRANS_NOERROR = 0,\n\tDMA_TRANS_READ_FAILED = 1,\n\tDMA_TRANS_WRITE_FAILED = 2,\n\tDMA_TRANS_ABORTED = 3,\n};\n\nstruct dmaengine_result {\n\tenum dmaengine_tx_result result;\n\tu32 residue;\n};\n\ntypedef void (*dma_async_tx_callback_result)(void *, const struct dmaengine_result *);\n\nstruct dmaengine_unmap_data {\n\tu8 map_cnt;\n\tu8 to_cnt;\n\tu8 from_cnt;\n\tu8 bidi_cnt;\n\tstruct device *dev;\n\tstruct kref kref;\n\tsize_t len;\n\tdma_addr_t addr[0];\n};\n\nstruct dma_descriptor_metadata_ops {\n\tint (*attach)(struct dma_async_tx_descriptor *, void *, size_t);\n\tvoid * (*get_ptr)(struct dma_async_tx_descriptor *, size_t *, size_t *);\n\tint (*set_len)(struct dma_async_tx_descriptor *, size_t);\n};\n\nstruct dma_async_tx_descriptor {\n\tdma_cookie_t cookie;\n\tenum dma_ctrl_flags flags;\n\tdma_addr_t phys;\n\tstruct dma_chan___2 *chan;\n\tdma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *);\n\tint (*desc_free)(struct dma_async_tx_descriptor *);\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n\tstruct dmaengine_unmap_data *unmap;\n\tenum dma_desc_metadata_mode desc_metadata_mode;\n\tstruct dma_descriptor_metadata_ops *metadata_ops;\n};\n\nstruct dma_tx_state {\n\tdma_cookie_t last;\n\tdma_cookie_t used;\n\tu32 residue;\n\tu32 in_flight_bytes;\n};\n\nstruct dma_slave_map {\n\tconst char *devname;\n\tconst char *slave;\n\tvoid *param;\n};\n\nstruct dma_chan_tbl_ent {\n\tstruct dma_chan___2 *chan;\n};\n\nstruct dmaengine_unmap_pool {\n\tstruct kmem_cache *cache;\n\tconst char *name;\n\tmempool_t *pool;\n\tsize_t size;\n};\n\nstruct dmaengine_desc_callback {\n\tdma_async_tx_callback callback;\n\tdma_async_tx_callback_result callback_result;\n\tvoid *callback_param;\n};\n\nstruct virt_dma_desc {\n\tstruct dma_async_tx_descriptor tx;\n\tstruct dmaengine_result tx_result;\n\tstruct list_head node;\n};\n\nstruct virt_dma_chan {\n\tstruct dma_chan___2 chan;\n\tstruct tasklet_struct task;\n\tvoid (*desc_free)(struct virt_dma_desc *);\n\tspinlock_t lock;\n\tstruct list_head desc_allocated;\n\tstruct list_head desc_submitted;\n\tstruct list_head desc_issued;\n\tstruct list_head desc_completed;\n\tstruct list_head desc_terminated;\n\tstruct virt_dma_desc *cyclic;\n};\n\nstruct acpi_table_csrt {\n\tstruct acpi_table_header header;\n};\n\nstruct acpi_csrt_group {\n\tu32 length;\n\tu32 vendor_id;\n\tu32 subvendor_id;\n\tu16 device_id;\n\tu16 subdevice_id;\n\tu16 revision;\n\tu16 reserved;\n\tu32 shared_info_length;\n};\n\nstruct acpi_csrt_shared_info {\n\tu16 major_version;\n\tu16 minor_version;\n\tu32 mmio_base_low;\n\tu32 mmio_base_high;\n\tu32 gsi_interrupt;\n\tu8 interrupt_polarity;\n\tu8 interrupt_mode;\n\tu8 num_channels;\n\tu8 dma_address_width;\n\tu16 base_request_line;\n\tu16 num_handshake_signals;\n\tu32 max_block_size;\n};\n\nstruct acpi_dma_spec {\n\tint chan_id;\n\tint slave_id;\n\tstruct device *dev;\n};\n\nstruct acpi_dma {\n\tstruct list_head dma_controllers;\n\tstruct device *dev;\n\tstruct dma_chan___2 * (*acpi_dma_xlate)(struct acpi_dma_spec *, struct acpi_dma *);\n\tvoid *data;\n\tshort unsigned int base_request_line;\n\tshort unsigned int end_request_line;\n};\n\nstruct acpi_dma_filter_info {\n\tdma_cap_mask_t dma_cap;\n\tdma_filter_fn filter_fn;\n};\n\nstruct acpi_dma_parser_data {\n\tstruct acpi_dma_spec dma_spec;\n\tsize_t index;\n\tsize_t n;\n};\n\nstruct dw_dma_slave {\n\tstruct device *dma_dev;\n\tu8 src_id;\n\tu8 dst_id;\n\tu8 m_master;\n\tu8 p_master;\n\tbool hs_polarity;\n};\n\nstruct dw_dma_platform_data {\n\tunsigned int nr_channels;\n\tunsigned char chan_allocation_order;\n\tunsigned char chan_priority;\n\tunsigned int block_size;\n\tunsigned char nr_masters;\n\tunsigned char data_width[4];\n\tunsigned char multi_block[8];\n\tunsigned char protctl;\n};\n\nstruct dw_dma;\n\nstruct dw_dma_chip {\n\tstruct device *dev;\n\tint id;\n\tint irq;\n\tvoid *regs;\n\tstruct clk *clk;\n\tstruct dw_dma *dw;\n\tconst struct dw_dma_platform_data *pdata;\n};\n\nstruct dma_pool___2;\n\nstruct dw_dma_chan;\n\nstruct dw_dma {\n\tstruct dma_device dma;\n\tchar name[20];\n\tvoid *regs;\n\tstruct dma_pool___2 *desc_pool;\n\tstruct tasklet_struct tasklet;\n\tstruct dw_dma_chan *chan;\n\tu8 all_chan_mask;\n\tu8 in_use;\n\tvoid (*initialize_chan)(struct dw_dma_chan *);\n\tvoid (*suspend_chan)(struct dw_dma_chan *, bool);\n\tvoid (*resume_chan)(struct dw_dma_chan *, bool);\n\tu32 (*prepare_ctllo)(struct dw_dma_chan *);\n\tvoid (*encode_maxburst)(struct dw_dma_chan *, u32 *);\n\tu32 (*bytes2block)(struct dw_dma_chan *, size_t, unsigned int, size_t *);\n\tsize_t (*block2bytes)(struct dw_dma_chan *, u32, u32);\n\tvoid (*set_device_name)(struct dw_dma *, int);\n\tvoid (*disable)(struct dw_dma *);\n\tvoid (*enable)(struct dw_dma *);\n\tstruct dw_dma_platform_data *pdata;\n};\n\nenum dw_dma_fc {\n\tDW_DMA_FC_D_M2M = 0,\n\tDW_DMA_FC_D_M2P = 1,\n\tDW_DMA_FC_D_P2M = 2,\n\tDW_DMA_FC_D_P2P = 3,\n\tDW_DMA_FC_P_P2M = 4,\n\tDW_DMA_FC_SP_P2P = 5,\n\tDW_DMA_FC_P_M2P = 6,\n\tDW_DMA_FC_DP_P2P = 7,\n};\n\nstruct dw_dma_chan_regs {\n\tu32 SAR;\n\tu32 __pad_SAR;\n\tu32 DAR;\n\tu32 __pad_DAR;\n\tu32 LLP;\n\tu32 __pad_LLP;\n\tu32 CTL_LO;\n\tu32 CTL_HI;\n\tu32 SSTAT;\n\tu32 __pad_SSTAT;\n\tu32 DSTAT;\n\tu32 __pad_DSTAT;\n\tu32 SSTATAR;\n\tu32 __pad_SSTATAR;\n\tu32 DSTATAR;\n\tu32 __pad_DSTATAR;\n\tu32 CFG_LO;\n\tu32 CFG_HI;\n\tu32 SGR;\n\tu32 __pad_SGR;\n\tu32 DSR;\n\tu32 __pad_DSR;\n};\n\nstruct dw_dma_irq_regs {\n\tu32 XFER;\n\tu32 __pad_XFER;\n\tu32 BLOCK;\n\tu32 __pad_BLOCK;\n\tu32 SRC_TRAN;\n\tu32 __pad_SRC_TRAN;\n\tu32 DST_TRAN;\n\tu32 __pad_DST_TRAN;\n\tu32 ERROR;\n\tu32 __pad_ERROR;\n};\n\nstruct dw_dma_regs {\n\tstruct dw_dma_chan_regs CHAN[8];\n\tstruct dw_dma_irq_regs RAW;\n\tstruct dw_dma_irq_regs STATUS;\n\tstruct dw_dma_irq_regs MASK;\n\tstruct dw_dma_irq_regs CLEAR;\n\tu32 STATUS_INT;\n\tu32 __pad_STATUS_INT;\n\tu32 REQ_SRC;\n\tu32 __pad_REQ_SRC;\n\tu32 REQ_DST;\n\tu32 __pad_REQ_DST;\n\tu32 SGL_REQ_SRC;\n\tu32 __pad_SGL_REQ_SRC;\n\tu32 SGL_REQ_DST;\n\tu32 __pad_SGL_REQ_DST;\n\tu32 LAST_SRC;\n\tu32 __pad_LAST_SRC;\n\tu32 LAST_DST;\n\tu32 __pad_LAST_DST;\n\tu32 CFG;\n\tu32 __pad_CFG;\n\tu32 CH_EN;\n\tu32 __pad_CH_EN;\n\tu32 ID;\n\tu32 __pad_ID;\n\tu32 TEST;\n\tu32 __pad_TEST;\n\tu32 CLASS_PRIORITY0;\n\tu32 __pad_CLASS_PRIORITY0;\n\tu32 CLASS_PRIORITY1;\n\tu32 __pad_CLASS_PRIORITY1;\n\tu32 __reserved;\n\tu32 DWC_PARAMS[8];\n\tu32 MULTI_BLK_TYPE;\n\tu32 MAX_BLK_SIZE;\n\tu32 DW_PARAMS;\n\tu32 COMP_TYPE;\n\tu32 COMP_VERSION;\n\tu32 FIFO_PARTITION0;\n\tu32 __pad_FIFO_PARTITION0;\n\tu32 FIFO_PARTITION1;\n\tu32 __pad_FIFO_PARTITION1;\n\tu32 SAI_ERR;\n\tu32 __pad_SAI_ERR;\n\tu32 GLOBAL_CFG;\n\tu32 __pad_GLOBAL_CFG;\n};\n\nenum dw_dmac_flags {\n\tDW_DMA_IS_CYCLIC = 0,\n\tDW_DMA_IS_SOFT_LLP = 1,\n\tDW_DMA_IS_PAUSED = 2,\n\tDW_DMA_IS_INITIALIZED = 3,\n};\n\nstruct dw_dma_chan {\n\tstruct dma_chan___2 chan;\n\tvoid *ch_regs;\n\tu8 mask;\n\tu8 priority;\n\tenum dma_transfer_direction direction;\n\tstruct list_head *tx_node_active;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n\tstruct list_head active_list;\n\tstruct list_head queue;\n\tunsigned int descs_allocated;\n\tunsigned int block_size;\n\tbool nollp;\n\tstruct dw_dma_slave dws;\n\tstruct dma_slave_config dma_sconfig;\n};\n\nstruct dw_lli {\n\t__le32 sar;\n\t__le32 dar;\n\t__le32 llp;\n\t__le32 ctllo;\n\t__le32 ctlhi;\n\t__le32 sstat;\n\t__le32 dstat;\n};\n\nstruct dw_desc {\n\tstruct dw_lli lli;\n\tstruct list_head desc_node;\n\tstruct list_head tx_list;\n\tstruct dma_async_tx_descriptor txd;\n\tsize_t len;\n\tsize_t total_len;\n\tu32 residue;\n};\n\nstruct dw_dma_chip_pdata {\n\tconst struct dw_dma_platform_data *pdata;\n\tint (*probe)(struct dw_dma_chip *);\n\tint (*remove)(struct dw_dma_chip *);\n\tstruct dw_dma_chip *chip;\n};\n\nenum dw_dma_msize {\n\tDW_DMA_MSIZE_1 = 0,\n\tDW_DMA_MSIZE_4 = 1,\n\tDW_DMA_MSIZE_8 = 2,\n\tDW_DMA_MSIZE_16 = 3,\n\tDW_DMA_MSIZE_32 = 4,\n\tDW_DMA_MSIZE_64 = 5,\n\tDW_DMA_MSIZE_128 = 6,\n\tDW_DMA_MSIZE_256 = 7,\n};\n\nenum idma32_msize {\n\tIDMA32_MSIZE_1 = 0,\n\tIDMA32_MSIZE_2 = 1,\n\tIDMA32_MSIZE_4 = 2,\n\tIDMA32_MSIZE_8 = 3,\n\tIDMA32_MSIZE_16 = 4,\n\tIDMA32_MSIZE_32 = 5,\n};\n\nstruct hsu_dma;\n\nstruct hsu_dma_chip {\n\tstruct device *dev;\n\tint irq;\n\tvoid *regs;\n\tunsigned int length;\n\tunsigned int offset;\n\tstruct hsu_dma *hsu;\n};\n\nstruct hsu_dma_chan;\n\nstruct hsu_dma {\n\tstruct dma_device dma;\n\tstruct hsu_dma_chan *chan;\n\tshort unsigned int nr_channels;\n};\n\nstruct hsu_dma_sg {\n\tdma_addr_t addr;\n\tunsigned int len;\n};\n\nstruct hsu_dma_desc {\n\tstruct virt_dma_desc vdesc;\n\tenum dma_transfer_direction direction;\n\tstruct hsu_dma_sg *sg;\n\tunsigned int nents;\n\tsize_t length;\n\tunsigned int active;\n\tenum dma_status status;\n};\n\nstruct hsu_dma_chan {\n\tstruct virt_dma_chan vchan;\n\tvoid *reg;\n\tenum dma_transfer_direction direction;\n\tstruct dma_slave_config config;\n\tstruct hsu_dma_desc *desc;\n};\n\nstruct serial_struct32 {\n\tcompat_int_t type;\n\tcompat_int_t line;\n\tcompat_uint_t port;\n\tcompat_int_t irq;\n\tcompat_int_t flags;\n\tcompat_int_t xmit_fifo_size;\n\tcompat_int_t custom_divisor;\n\tcompat_int_t baud_base;\n\tshort unsigned int close_delay;\n\tchar io_type;\n\tchar reserved_char[1];\n\tcompat_int_t hub6;\n\tshort unsigned int closing_wait;\n\tshort unsigned int closing_wait2;\n\tcompat_uint_t iomem_base;\n\tshort unsigned int iomem_reg_shift;\n\tunsigned int port_high;\n\tcompat_int_t reserved[1];\n};\n\nstruct n_tty_data {\n\tsize_t read_head;\n\tsize_t commit_head;\n\tsize_t canon_head;\n\tsize_t echo_head;\n\tsize_t echo_commit;\n\tsize_t echo_mark;\n\tlong unsigned int char_map[4];\n\tlong unsigned int overrun_time;\n\tint num_overrun;\n\tbool no_room;\n\tunsigned char lnext: 1;\n\tunsigned char erasing: 1;\n\tunsigned char raw: 1;\n\tunsigned char real_raw: 1;\n\tunsigned char icanon: 1;\n\tunsigned char push: 1;\n\tchar read_buf[4096];\n\tlong unsigned int read_flags[64];\n\tunsigned char echo_buf[4096];\n\tsize_t read_tail;\n\tsize_t line_start;\n\tunsigned int column;\n\tunsigned int canon_column;\n\tsize_t echo_tail;\n\tstruct mutex atomic_read_lock;\n\tstruct mutex output_lock;\n};\n\nenum {\n\tERASE = 0,\n\tWERASE = 1,\n\tKILL = 2,\n};\n\nstruct termios {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n};\n\nstruct termios2 {\n\ttcflag_t c_iflag;\n\ttcflag_t c_oflag;\n\ttcflag_t c_cflag;\n\ttcflag_t c_lflag;\n\tcc_t c_line;\n\tcc_t c_cc[19];\n\tspeed_t c_ispeed;\n\tspeed_t c_ospeed;\n};\n\nstruct termio {\n\tshort unsigned int c_iflag;\n\tshort unsigned int c_oflag;\n\tshort unsigned int c_cflag;\n\tshort unsigned int c_lflag;\n\tunsigned char c_line;\n\tunsigned char c_cc[8];\n};\n\nstruct ldsem_waiter {\n\tstruct list_head list;\n\tstruct task_struct *task;\n};\n\nstruct pts_fs_info___2;\n\nstruct tty_audit_buf {\n\tstruct mutex mutex;\n\tdev_t dev;\n\tunsigned int icanon: 1;\n\tsize_t valid;\n\tunsigned char *data;\n};\n\nstruct sysrq_state {\n\tstruct input_handle handle;\n\tstruct work_struct reinject_work;\n\tlong unsigned int key_down[12];\n\tunsigned int alt;\n\tunsigned int alt_use;\n\tbool active;\n\tbool need_reinject;\n\tbool reinjecting;\n\tbool reset_canceled;\n\tbool reset_requested;\n\tlong unsigned int reset_keybit[12];\n\tint reset_seq_len;\n\tint reset_seq_cnt;\n\tint reset_seq_version;\n\tstruct timer_list keyreset_timer;\n};\n\nstruct consolefontdesc {\n\tshort unsigned int charcount;\n\tshort unsigned int charheight;\n\tchar *chardata;\n};\n\nstruct unipair {\n\tshort unsigned int unicode;\n\tshort unsigned int fontpos;\n};\n\nstruct unimapdesc {\n\tshort unsigned int entry_ct;\n\tstruct unipair *entries;\n};\n\nstruct kbdiacruc {\n\tunsigned int diacr;\n\tunsigned int base;\n\tunsigned int result;\n};\n\nstruct kbd_repeat {\n\tint delay;\n\tint period;\n};\n\nstruct console_font_op {\n\tunsigned int op;\n\tunsigned int flags;\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int charcount;\n\tunsigned char *data;\n};\n\nstruct vt_stat {\n\tshort unsigned int v_active;\n\tshort unsigned int v_signal;\n\tshort unsigned int v_state;\n};\n\nstruct vt_sizes {\n\tshort unsigned int v_rows;\n\tshort unsigned int v_cols;\n\tshort unsigned int v_scrollsize;\n};\n\nstruct vt_consize {\n\tshort unsigned int v_rows;\n\tshort unsigned int v_cols;\n\tshort unsigned int v_vlin;\n\tshort unsigned int v_clin;\n\tshort unsigned int v_vcol;\n\tshort unsigned int v_ccol;\n};\n\nstruct vt_event {\n\tunsigned int event;\n\tunsigned int oldev;\n\tunsigned int newev;\n\tunsigned int pad[4];\n};\n\nstruct vt_setactivate {\n\tunsigned int console;\n\tstruct vt_mode mode;\n};\n\nstruct vt_event_wait {\n\tstruct list_head list;\n\tstruct vt_event event;\n\tint done;\n};\n\nstruct compat_consolefontdesc {\n\tshort unsigned int charcount;\n\tshort unsigned int charheight;\n\tcompat_caddr_t chardata;\n};\n\nstruct compat_console_font_op {\n\tcompat_uint_t op;\n\tcompat_uint_t flags;\n\tcompat_uint_t width;\n\tcompat_uint_t height;\n\tcompat_uint_t charcount;\n\tcompat_caddr_t data;\n};\n\nstruct compat_unimapdesc {\n\tshort unsigned int entry_ct;\n\tcompat_caddr_t entries;\n};\n\nstruct vt_notifier_param {\n\tstruct vc_data *vc;\n\tunsigned int c;\n};\n\nstruct vcs_poll_data {\n\tstruct notifier_block notifier;\n\tunsigned int cons_num;\n\tint event;\n\twait_queue_head_t waitq;\n\tstruct fasync_struct *fasync;\n};\n\nstruct tiocl_selection {\n\tshort unsigned int xs;\n\tshort unsigned int ys;\n\tshort unsigned int xe;\n\tshort unsigned int ye;\n\tshort unsigned int sel_mode;\n};\n\nstruct vc_selection {\n\tstruct mutex lock;\n\tstruct vc_data *cons;\n\tchar *buffer;\n\tunsigned int buf_len;\n\tvolatile int start;\n\tint end;\n};\n\nstruct keyboard_notifier_param {\n\tstruct vc_data *vc;\n\tint down;\n\tint shift;\n\tint ledstate;\n\tunsigned int value;\n};\n\nstruct kbd_struct {\n\tunsigned char lockstate;\n\tunsigned char slockstate;\n\tunsigned char ledmode: 1;\n\tunsigned char ledflagstate: 4;\n\tchar: 3;\n\tunsigned char default_ledflagstate: 4;\n\tunsigned char kbdmode: 3;\n\tchar: 1;\n\tunsigned char modeflags: 5;\n};\n\nstruct kbentry {\n\tunsigned char kb_table;\n\tunsigned char kb_index;\n\tshort unsigned int kb_value;\n};\n\nstruct kbsentry {\n\tunsigned char kb_func;\n\tunsigned char kb_string[512];\n};\n\nstruct kbdiacr {\n\tunsigned char diacr;\n\tunsigned char base;\n\tunsigned char result;\n};\n\nstruct kbdiacrs {\n\tunsigned int kb_cnt;\n\tstruct kbdiacr kbdiacr[256];\n};\n\nstruct kbdiacrsuc {\n\tunsigned int kb_cnt;\n\tstruct kbdiacruc kbdiacruc[256];\n};\n\nstruct kbkeycode {\n\tunsigned int scancode;\n\tunsigned int keycode;\n};\n\ntypedef void k_handler_fn(struct vc_data *, unsigned char, char);\n\ntypedef void fn_handler_fn(struct vc_data *);\n\nstruct getset_keycode_data {\n\tstruct input_keymap_entry ke;\n\tint error;\n};\n\nstruct kbd_led_trigger {\n\tstruct led_trigger trigger;\n\tunsigned int mask;\n};\n\nstruct uni_pagedir {\n\tu16 **uni_pgdir[32];\n\tlong unsigned int refcount;\n\tlong unsigned int sum;\n\tunsigned char *inverse_translations[4];\n\tu16 *inverse_trans_unicode;\n};\n\ntypedef uint32_t char32_t;\n\nstruct uni_screen {\n\tchar32_t *lines[0];\n};\n\nstruct con_driver {\n\tconst struct consw *con;\n\tconst char *desc;\n\tstruct device *dev;\n\tint node;\n\tint first;\n\tint last;\n\tint flag;\n};\n\nenum {\n\tblank_off = 0,\n\tblank_normal_wait = 1,\n\tblank_vesa_wait = 2,\n};\n\nenum {\n\tEPecma = 0,\n\tEPdec = 1,\n\tEPeq = 2,\n\tEPgt = 3,\n\tEPlt = 4,\n};\n\nstruct rgb {\n\tu8 r;\n\tu8 g;\n\tu8 b;\n};\n\nenum {\n\tESnormal = 0,\n\tESesc = 1,\n\tESsquare = 2,\n\tESgetpars = 3,\n\tESfunckey = 4,\n\tEShash = 5,\n\tESsetG0 = 6,\n\tESsetG1 = 7,\n\tESpercent = 8,\n\tEScsiignore = 9,\n\tESnonstd = 10,\n\tESpalette = 11,\n\tESosc = 12,\n};\n\nstruct interval {\n\tuint32_t first;\n\tuint32_t last;\n};\n\nstruct uart_driver {\n\tstruct module *owner;\n\tconst char *driver_name;\n\tconst char *dev_name;\n\tint major;\n\tint minor;\n\tint nr;\n\tstruct console *cons;\n\tstruct uart_state *state;\n\tstruct tty_driver *tty_driver;\n};\n\nstruct uart_match {\n\tstruct uart_port *port;\n\tstruct uart_driver *driver;\n};\n\nenum hwparam_type {\n\thwparam_ioport = 0,\n\thwparam_iomem = 1,\n\thwparam_ioport_or_iomem = 2,\n\thwparam_irq = 3,\n\thwparam_dma = 4,\n\thwparam_dma_addr = 5,\n\thwparam_other = 6,\n};\n\nstruct plat_serial8250_port {\n\tlong unsigned int iobase;\n\tvoid *membase;\n\tresource_size_t mapbase;\n\tunsigned int irq;\n\tlong unsigned int irqflags;\n\tunsigned int uartclk;\n\tvoid *private_data;\n\tunsigned char regshift;\n\tunsigned char iotype;\n\tunsigned char hub6;\n\tunsigned char has_sysrq;\n\tupf_t flags;\n\tunsigned int type;\n\tunsigned int (*serial_in)(struct uart_port *, int);\n\tvoid (*serial_out)(struct uart_port *, int, int);\n\tvoid (*set_termios)(struct uart_port *, struct ktermios *, struct ktermios *);\n\tvoid (*set_ldisc)(struct uart_port *, struct ktermios *);\n\tunsigned int (*get_mctrl)(struct uart_port *);\n\tint (*handle_irq)(struct uart_port *);\n\tvoid (*pm)(struct uart_port *, unsigned int, unsigned int);\n\tvoid (*handle_break)(struct uart_port *);\n};\n\nenum {\n\tPLAT8250_DEV_LEGACY = 4294967295,\n\tPLAT8250_DEV_PLATFORM = 0,\n\tPLAT8250_DEV_PLATFORM1 = 1,\n\tPLAT8250_DEV_PLATFORM2 = 2,\n\tPLAT8250_DEV_FOURPORT = 3,\n\tPLAT8250_DEV_ACCENT = 4,\n\tPLAT8250_DEV_BOCA = 5,\n\tPLAT8250_DEV_EXAR_ST16C554 = 6,\n\tPLAT8250_DEV_HUB6 = 7,\n\tPLAT8250_DEV_AU1X00 = 8,\n\tPLAT8250_DEV_SM501 = 9,\n};\n\nstruct uart_8250_port;\n\nstruct uart_8250_ops {\n\tint (*setup_irq)(struct uart_8250_port *);\n\tvoid (*release_irq)(struct uart_8250_port *);\n};\n\nstruct mctrl_gpios;\n\nstruct uart_8250_dma;\n\nstruct uart_8250_em485;\n\nstruct uart_8250_port {\n\tstruct uart_port port;\n\tstruct timer_list timer;\n\tstruct list_head list;\n\tu32 capabilities;\n\tshort unsigned int bugs;\n\tbool fifo_bug;\n\tunsigned int tx_loadsz;\n\tunsigned char acr;\n\tunsigned char fcr;\n\tunsigned char ier;\n\tunsigned char lcr;\n\tunsigned char mcr;\n\tunsigned char mcr_mask;\n\tunsigned char mcr_force;\n\tunsigned char cur_iotype;\n\tunsigned int rpm_tx_active;\n\tunsigned char canary;\n\tunsigned char probe;\n\tstruct mctrl_gpios *gpios;\n\tunsigned char lsr_saved_flags;\n\tunsigned char msr_saved_flags;\n\tstruct uart_8250_dma *dma;\n\tconst struct uart_8250_ops *ops;\n\tint (*dl_read)(struct uart_8250_port *);\n\tvoid (*dl_write)(struct uart_8250_port *, int);\n\tstruct uart_8250_em485 *em485;\n\tvoid (*rs485_start_tx)(struct uart_8250_port *);\n\tvoid (*rs485_stop_tx)(struct uart_8250_port *);\n\tstruct delayed_work overrun_backoff;\n\tu32 overrun_backoff_time_ms;\n};\n\nstruct uart_8250_em485 {\n\tstruct hrtimer start_tx_timer;\n\tstruct hrtimer stop_tx_timer;\n\tstruct hrtimer *active_timer;\n\tstruct uart_8250_port *port;\n\tunsigned int tx_stopped: 1;\n};\n\nstruct uart_8250_dma {\n\tint (*tx_dma)(struct uart_8250_port *);\n\tint (*rx_dma)(struct uart_8250_port *);\n\tdma_filter_fn fn;\n\tvoid *rx_param;\n\tvoid *tx_param;\n\tstruct dma_slave_config rxconf;\n\tstruct dma_slave_config txconf;\n\tstruct dma_chan___2 *rxchan;\n\tstruct dma_chan___2 *txchan;\n\tphys_addr_t rx_dma_addr;\n\tphys_addr_t tx_dma_addr;\n\tdma_addr_t rx_addr;\n\tdma_addr_t tx_addr;\n\tdma_cookie_t rx_cookie;\n\tdma_cookie_t tx_cookie;\n\tvoid *rx_buf;\n\tsize_t rx_size;\n\tsize_t tx_size;\n\tunsigned char tx_running;\n\tunsigned char tx_err;\n\tunsigned char rx_running;\n};\n\nstruct old_serial_port {\n\tunsigned int uart;\n\tunsigned int baud_base;\n\tunsigned int port;\n\tunsigned int irq;\n\tupf_t flags;\n\tunsigned char io_type;\n\tunsigned char *iomem_base;\n\tshort unsigned int iomem_reg_shift;\n};\n\nstruct irq_info {\n\tstruct hlist_node node;\n\tint irq;\n\tspinlock_t lock;\n\tstruct list_head *head;\n};\n\nstruct serial8250_config {\n\tconst char *name;\n\tshort unsigned int fifo_size;\n\tshort unsigned int tx_loadsz;\n\tunsigned char fcr;\n\tunsigned char rxtrig_bytes[4];\n\tunsigned int flags;\n};\n\nstruct dw8250_port_data {\n\tint line;\n\tstruct uart_8250_dma dma;\n\tu8 dlf_size;\n};\n\nstruct pciserial_board {\n\tunsigned int flags;\n\tunsigned int num_ports;\n\tunsigned int base_baud;\n\tunsigned int uart_offset;\n\tunsigned int reg_shift;\n\tunsigned int first_offset;\n};\n\nstruct serial_private;\n\nstruct pci_serial_quirk {\n\tu32 vendor;\n\tu32 device;\n\tu32 subvendor;\n\tu32 subdevice;\n\tint (*probe)(struct pci_dev *);\n\tint (*init)(struct pci_dev *);\n\tint (*setup)(struct serial_private *, const struct pciserial_board *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct serial_private {\n\tstruct pci_dev *dev;\n\tunsigned int nr;\n\tstruct pci_serial_quirk *quirk;\n\tconst struct pciserial_board *board;\n\tint line[0];\n};\n\nstruct f815xxa_data {\n\tspinlock_t lock;\n\tint idx;\n};\n\nstruct timedia_struct {\n\tint num;\n\tconst short unsigned int *ids;\n};\n\nstruct quatech_feature {\n\tu16 devid;\n\tbool amcc;\n};\n\nenum pci_board_num_t {\n\tpbn_default = 0,\n\tpbn_b0_1_115200 = 1,\n\tpbn_b0_2_115200 = 2,\n\tpbn_b0_4_115200 = 3,\n\tpbn_b0_5_115200 = 4,\n\tpbn_b0_8_115200 = 5,\n\tpbn_b0_1_921600 = 6,\n\tpbn_b0_2_921600 = 7,\n\tpbn_b0_4_921600 = 8,\n\tpbn_b0_2_1130000 = 9,\n\tpbn_b0_4_1152000 = 10,\n\tpbn_b0_4_1250000 = 11,\n\tpbn_b0_2_1843200 = 12,\n\tpbn_b0_4_1843200 = 13,\n\tpbn_b0_1_4000000 = 14,\n\tpbn_b0_bt_1_115200 = 15,\n\tpbn_b0_bt_2_115200 = 16,\n\tpbn_b0_bt_4_115200 = 17,\n\tpbn_b0_bt_8_115200 = 18,\n\tpbn_b0_bt_1_460800 = 19,\n\tpbn_b0_bt_2_460800 = 20,\n\tpbn_b0_bt_4_460800 = 21,\n\tpbn_b0_bt_1_921600 = 22,\n\tpbn_b0_bt_2_921600 = 23,\n\tpbn_b0_bt_4_921600 = 24,\n\tpbn_b0_bt_8_921600 = 25,\n\tpbn_b1_1_115200 = 26,\n\tpbn_b1_2_115200 = 27,\n\tpbn_b1_4_115200 = 28,\n\tpbn_b1_8_115200 = 29,\n\tpbn_b1_16_115200 = 30,\n\tpbn_b1_1_921600 = 31,\n\tpbn_b1_2_921600 = 32,\n\tpbn_b1_4_921600 = 33,\n\tpbn_b1_8_921600 = 34,\n\tpbn_b1_2_1250000 = 35,\n\tpbn_b1_bt_1_115200 = 36,\n\tpbn_b1_bt_2_115200 = 37,\n\tpbn_b1_bt_4_115200 = 38,\n\tpbn_b1_bt_2_921600 = 39,\n\tpbn_b1_1_1382400 = 40,\n\tpbn_b1_2_1382400 = 41,\n\tpbn_b1_4_1382400 = 42,\n\tpbn_b1_8_1382400 = 43,\n\tpbn_b2_1_115200 = 44,\n\tpbn_b2_2_115200 = 45,\n\tpbn_b2_4_115200 = 46,\n\tpbn_b2_8_115200 = 47,\n\tpbn_b2_1_460800 = 48,\n\tpbn_b2_4_460800 = 49,\n\tpbn_b2_8_460800 = 50,\n\tpbn_b2_16_460800 = 51,\n\tpbn_b2_1_921600 = 52,\n\tpbn_b2_4_921600 = 53,\n\tpbn_b2_8_921600 = 54,\n\tpbn_b2_8_1152000 = 55,\n\tpbn_b2_bt_1_115200 = 56,\n\tpbn_b2_bt_2_115200 = 57,\n\tpbn_b2_bt_4_115200 = 58,\n\tpbn_b2_bt_2_921600 = 59,\n\tpbn_b2_bt_4_921600 = 60,\n\tpbn_b3_2_115200 = 61,\n\tpbn_b3_4_115200 = 62,\n\tpbn_b3_8_115200 = 63,\n\tpbn_b4_bt_2_921600 = 64,\n\tpbn_b4_bt_4_921600 = 65,\n\tpbn_b4_bt_8_921600 = 66,\n\tpbn_panacom = 67,\n\tpbn_panacom2 = 68,\n\tpbn_panacom4 = 69,\n\tpbn_plx_romulus = 70,\n\tpbn_endrun_2_4000000 = 71,\n\tpbn_oxsemi = 72,\n\tpbn_oxsemi_1_4000000 = 73,\n\tpbn_oxsemi_2_4000000 = 74,\n\tpbn_oxsemi_4_4000000 = 75,\n\tpbn_oxsemi_8_4000000 = 76,\n\tpbn_intel_i960 = 77,\n\tpbn_sgi_ioc3 = 78,\n\tpbn_computone_4 = 79,\n\tpbn_computone_6 = 80,\n\tpbn_computone_8 = 81,\n\tpbn_sbsxrsio = 82,\n\tpbn_pasemi_1682M = 83,\n\tpbn_ni8430_2 = 84,\n\tpbn_ni8430_4 = 85,\n\tpbn_ni8430_8 = 86,\n\tpbn_ni8430_16 = 87,\n\tpbn_ADDIDATA_PCIe_1_3906250 = 88,\n\tpbn_ADDIDATA_PCIe_2_3906250 = 89,\n\tpbn_ADDIDATA_PCIe_4_3906250 = 90,\n\tpbn_ADDIDATA_PCIe_8_3906250 = 91,\n\tpbn_ce4100_1_115200 = 92,\n\tpbn_omegapci = 93,\n\tpbn_NETMOS9900_2s_115200 = 94,\n\tpbn_brcm_trumanage = 95,\n\tpbn_fintek_4 = 96,\n\tpbn_fintek_8 = 97,\n\tpbn_fintek_12 = 98,\n\tpbn_fintek_F81504A = 99,\n\tpbn_fintek_F81508A = 100,\n\tpbn_fintek_F81512A = 101,\n\tpbn_wch382_2 = 102,\n\tpbn_wch384_4 = 103,\n\tpbn_pericom_PI7C9X7951 = 104,\n\tpbn_pericom_PI7C9X7952 = 105,\n\tpbn_pericom_PI7C9X7954 = 106,\n\tpbn_pericom_PI7C9X7958 = 107,\n\tpbn_sunix_pci_1s = 108,\n\tpbn_sunix_pci_2s = 109,\n\tpbn_sunix_pci_4s = 110,\n\tpbn_sunix_pci_8s = 111,\n\tpbn_sunix_pci_16s = 112,\n\tpbn_moxa8250_2p = 113,\n\tpbn_moxa8250_4p = 114,\n\tpbn_moxa8250_8p = 115,\n};\n\nstruct exar8250_platform {\n\tint (*rs485_config)(struct uart_port *, struct serial_rs485 *);\n\tint (*register_gpio)(struct pci_dev *, struct uart_8250_port *);\n};\n\nstruct exar8250;\n\nstruct exar8250_board {\n\tunsigned int num_ports;\n\tunsigned int reg_shift;\n\tint (*setup)(struct exar8250 *, struct pci_dev *, struct uart_8250_port *, int);\n\tvoid (*exit)(struct pci_dev *);\n};\n\nstruct exar8250 {\n\tunsigned int nr;\n\tstruct exar8250_board *board;\n\tvoid *virt;\n\tint line[0];\n};\n\nstruct lpss8250;\n\nstruct lpss8250_board {\n\tlong unsigned int freq;\n\tunsigned int base_baud;\n\tint (*setup)(struct lpss8250 *, struct uart_port *);\n\tvoid (*exit)(struct lpss8250 *);\n};\n\nstruct lpss8250 {\n\tstruct dw8250_port_data data;\n\tstruct lpss8250_board *board;\n\tstruct dw_dma_chip dma_chip;\n\tstruct dw_dma_slave dma_param;\n\tu8 dma_maxburst;\n};\n\nstruct hsu_dma_slave {\n\tstruct device *dma_dev;\n\tint chan_id;\n};\n\nstruct mid8250;\n\nstruct mid8250_board {\n\tunsigned int flags;\n\tlong unsigned int freq;\n\tunsigned int base_baud;\n\tint (*setup)(struct mid8250 *, struct uart_port *);\n\tvoid (*exit)(struct mid8250 *);\n};\n\nstruct mid8250 {\n\tint line;\n\tint dma_index;\n\tstruct pci_dev *dma_dev;\n\tstruct uart_8250_dma dma;\n\tstruct mid8250_board *board;\n\tstruct hsu_dma_chip dma_chip;\n};\n\nstruct memdev {\n\tconst char *name;\n\tumode_t mode;\n\tconst struct file_operations *fops;\n\tfmode_t fmode;\n};\n\nstruct timer_rand_state {\n\tcycles_t last_time;\n\tlong int last_delta;\n\tlong int last_delta2;\n};\n\nstruct trace_event_raw_add_device_randomness {\n\tstruct trace_entry ent;\n\tint bytes;\n\tlong unsigned int IP;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_random__mix_pool_bytes {\n\tstruct trace_entry ent;\n\tconst char *pool_name;\n\tint bytes;\n\tlong unsigned int IP;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_credit_entropy_bits {\n\tstruct trace_entry ent;\n\tconst char *pool_name;\n\tint bits;\n\tint entropy_count;\n\tlong unsigned int IP;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_push_to_pool {\n\tstruct trace_entry ent;\n\tconst char *pool_name;\n\tint pool_bits;\n\tint input_bits;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_debit_entropy {\n\tstruct trace_entry ent;\n\tconst char *pool_name;\n\tint debit_bits;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_add_input_randomness {\n\tstruct trace_entry ent;\n\tint input_bits;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_add_disk_randomness {\n\tstruct trace_entry ent;\n\tdev_t dev;\n\tint input_bits;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xfer_secondary_pool {\n\tstruct trace_entry ent;\n\tconst char *pool_name;\n\tint xfer_bits;\n\tint request_bits;\n\tint pool_entropy;\n\tint input_entropy;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_random__get_random_bytes {\n\tstruct trace_entry ent;\n\tint nbytes;\n\tlong unsigned int IP;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_random__extract_entropy {\n\tstruct trace_entry ent;\n\tconst char *pool_name;\n\tint nbytes;\n\tint entropy_count;\n\tlong unsigned int IP;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_random_read {\n\tstruct trace_entry ent;\n\tint got_bits;\n\tint need_bits;\n\tint pool_left;\n\tint input_left;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_urandom_read {\n\tstruct trace_entry ent;\n\tint got_bits;\n\tint pool_left;\n\tint input_left;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_add_device_randomness {};\n\nstruct trace_event_data_offsets_random__mix_pool_bytes {};\n\nstruct trace_event_data_offsets_credit_entropy_bits {};\n\nstruct trace_event_data_offsets_push_to_pool {};\n\nstruct trace_event_data_offsets_debit_entropy {};\n\nstruct trace_event_data_offsets_add_input_randomness {};\n\nstruct trace_event_data_offsets_add_disk_randomness {};\n\nstruct trace_event_data_offsets_xfer_secondary_pool {};\n\nstruct trace_event_data_offsets_random__get_random_bytes {};\n\nstruct trace_event_data_offsets_random__extract_entropy {};\n\nstruct trace_event_data_offsets_random_read {};\n\nstruct trace_event_data_offsets_urandom_read {};\n\ntypedef void (*btf_trace_add_device_randomness)(void *, int, long unsigned int);\n\ntypedef void (*btf_trace_mix_pool_bytes)(void *, const char *, int, long unsigned int);\n\ntypedef void (*btf_trace_mix_pool_bytes_nolock)(void *, const char *, int, long unsigned int);\n\ntypedef void (*btf_trace_credit_entropy_bits)(void *, const char *, int, int, long unsigned int);\n\ntypedef void (*btf_trace_push_to_pool)(void *, const char *, int, int);\n\ntypedef void (*btf_trace_debit_entropy)(void *, const char *, int);\n\ntypedef void (*btf_trace_add_input_randomness)(void *, int);\n\ntypedef void (*btf_trace_add_disk_randomness)(void *, dev_t, int);\n\ntypedef void (*btf_trace_xfer_secondary_pool)(void *, const char *, int, int, int, int);\n\ntypedef void (*btf_trace_get_random_bytes)(void *, int, long unsigned int);\n\ntypedef void (*btf_trace_get_random_bytes_arch)(void *, int, long unsigned int);\n\ntypedef void (*btf_trace_extract_entropy)(void *, const char *, int, int, long unsigned int);\n\ntypedef void (*btf_trace_extract_entropy_user)(void *, const char *, int, int, long unsigned int);\n\ntypedef void (*btf_trace_random_read)(void *, int, int, int, int);\n\ntypedef void (*btf_trace_urandom_read)(void *, int, int, int);\n\nstruct poolinfo {\n\tint poolbitshift;\n\tint poolwords;\n\tint poolbytes;\n\tint poolfracbits;\n\tint tap1;\n\tint tap2;\n\tint tap3;\n\tint tap4;\n\tint tap5;\n};\n\nstruct crng_state {\n\t__u32 state[16];\n\tlong unsigned int init_time;\n\tspinlock_t lock;\n};\n\nstruct entropy_store {\n\tconst struct poolinfo *poolinfo;\n\t__u32 *pool;\n\tconst char *name;\n\tspinlock_t lock;\n\tshort unsigned int add_ptr;\n\tshort unsigned int input_rotate;\n\tint entropy_count;\n\tunsigned int initialized: 1;\n\tunsigned int last_data_init: 1;\n\t__u8 last_data[10];\n};\n\nstruct fast_pool {\n\t__u32 pool[4];\n\tlong unsigned int last;\n\tshort unsigned int reg_idx;\n\tunsigned char count;\n};\n\nstruct batched_entropy {\n\tunion {\n\t\tu64 entropy_u64[8];\n\t\tu32 entropy_u32[16];\n\t};\n\tunsigned int position;\n\tspinlock_t batch_lock;\n};\n\nstruct hpet_info {\n\tlong unsigned int hi_ireqfreq;\n\tlong unsigned int hi_flags;\n\tshort unsigned int hi_hpet;\n\tshort unsigned int hi_timer;\n};\n\nstruct hpet_timer {\n\tu64 hpet_config;\n\tunion {\n\t\tu64 _hpet_hc64;\n\t\tu32 _hpet_hc32;\n\t\tlong unsigned int _hpet_compare;\n\t} _u1;\n\tu64 hpet_fsb[2];\n};\n\nstruct hpet {\n\tu64 hpet_cap;\n\tu64 res0;\n\tu64 hpet_config;\n\tu64 res1;\n\tu64 hpet_isr;\n\tu64 res2[25];\n\tunion {\n\t\tu64 _hpet_mc64;\n\t\tu32 _hpet_mc32;\n\t\tlong unsigned int _hpet_mc;\n\t} _u0;\n\tu64 res3;\n\tstruct hpet_timer hpet_timers[1];\n};\n\nstruct hpets;\n\nstruct hpet_dev {\n\tstruct hpets *hd_hpets;\n\tstruct hpet *hd_hpet;\n\tstruct hpet_timer *hd_timer;\n\tlong unsigned int hd_ireqfreq;\n\tlong unsigned int hd_irqdata;\n\twait_queue_head_t hd_waitqueue;\n\tstruct fasync_struct *hd_async_queue;\n\tunsigned int hd_flags;\n\tunsigned int hd_irq;\n\tunsigned int hd_hdwirq;\n\tchar hd_name[7];\n};\n\nstruct hpets {\n\tstruct hpets *hp_next;\n\tstruct hpet *hp_hpet;\n\tlong unsigned int hp_hpet_phys;\n\tstruct clocksource *hp_clocksource;\n\tlong long unsigned int hp_tick_freq;\n\tlong unsigned int hp_delta;\n\tunsigned int hp_ntimer;\n\tunsigned int hp_which;\n\tstruct hpet_dev hp_dev[0];\n};\n\nstruct compat_hpet_info {\n\tcompat_ulong_t hi_ireqfreq;\n\tcompat_ulong_t hi_flags;\n\tshort unsigned int hi_hpet;\n\tshort unsigned int hi_timer;\n};\n\nstruct nvram_ops {\n\tssize_t (*get_size)();\n\tunsigned char (*read_byte)(int);\n\tvoid (*write_byte)(unsigned char, int);\n\tssize_t (*read)(char *, size_t, loff_t *);\n\tssize_t (*write)(char *, size_t, loff_t *);\n\tlong int (*initialize)();\n\tlong int (*set_checksum)();\n};\n\nstruct hwrng {\n\tconst char *name;\n\tint (*init)(struct hwrng *);\n\tvoid (*cleanup)(struct hwrng *);\n\tint (*data_present)(struct hwrng *, int);\n\tint (*data_read)(struct hwrng *, u32 *);\n\tint (*read)(struct hwrng *, void *, size_t, bool);\n\tlong unsigned int priv;\n\tshort unsigned int quality;\n\tstruct list_head list;\n\tstruct kref ref;\n\tstruct completion cleanup_done;\n};\n\nenum {\n\tVIA_STRFILT_CNT_SHIFT = 16,\n\tVIA_STRFILT_FAIL = 32768,\n\tVIA_STRFILT_ENABLE = 16384,\n\tVIA_RAWBITS_ENABLE = 8192,\n\tVIA_RNG_ENABLE = 64,\n\tVIA_NOISESRC1 = 256,\n\tVIA_NOISESRC2 = 512,\n\tVIA_XSTORE_CNT_MASK = 15,\n\tVIA_RNG_CHUNK_8 = 0,\n\tVIA_RNG_CHUNK_4 = 1,\n\tVIA_RNG_CHUNK_4_MASK = 4294967295,\n\tVIA_RNG_CHUNK_2 = 2,\n\tVIA_RNG_CHUNK_2_MASK = 65535,\n\tVIA_RNG_CHUNK_1 = 3,\n\tVIA_RNG_CHUNK_1_MASK = 255,\n};\n\nenum chipset_type {\n\tNOT_SUPPORTED = 0,\n\tSUPPORTED = 1,\n};\n\nstruct agp_version {\n\tu16 major;\n\tu16 minor;\n};\n\nstruct agp_bridge_data;\n\nstruct agp_memory {\n\tstruct agp_memory *next;\n\tstruct agp_memory *prev;\n\tstruct agp_bridge_data *bridge;\n\tstruct page **pages;\n\tsize_t page_count;\n\tint key;\n\tint num_scratch_pages;\n\toff_t pg_start;\n\tu32 type;\n\tu32 physical;\n\tbool is_bound;\n\tbool is_flushed;\n\tstruct list_head mapped_list;\n\tstruct scatterlist *sg_list;\n\tint num_sg;\n};\n\nstruct agp_bridge_driver;\n\nstruct agp_bridge_data {\n\tconst struct agp_version *version;\n\tconst struct agp_bridge_driver *driver;\n\tconst struct vm_operations_struct *vm_ops;\n\tvoid *previous_size;\n\tvoid *current_size;\n\tvoid *dev_private_data;\n\tstruct pci_dev *dev;\n\tu32 *gatt_table;\n\tu32 *gatt_table_real;\n\tlong unsigned int scratch_page;\n\tstruct page *scratch_page_page;\n\tdma_addr_t scratch_page_dma;\n\tlong unsigned int gart_bus_addr;\n\tlong unsigned int gatt_bus_addr;\n\tu32 mode;\n\tenum chipset_type type;\n\tlong unsigned int *key_list;\n\tatomic_t current_memory_agp;\n\tatomic_t agp_in_use;\n\tint max_memory_agp;\n\tint aperture_size_idx;\n\tint capndx;\n\tint flags;\n\tchar major_version;\n\tchar minor_version;\n\tstruct list_head list;\n\tu32 apbase_config;\n\tstruct list_head mapped_list;\n\tspinlock_t mapped_lock;\n};\n\nenum aper_size_type {\n\tU8_APER_SIZE = 0,\n\tU16_APER_SIZE = 1,\n\tU32_APER_SIZE = 2,\n\tLVL2_APER_SIZE = 3,\n\tFIXED_APER_SIZE = 4,\n};\n\nstruct gatt_mask {\n\tlong unsigned int mask;\n\tu32 type;\n};\n\nstruct aper_size_info_16 {\n\tint size;\n\tint num_entries;\n\tint page_order;\n\tu16 size_value;\n};\n\nstruct agp_bridge_driver {\n\tstruct module *owner;\n\tconst void *aperture_sizes;\n\tint num_aperture_sizes;\n\tenum aper_size_type size_type;\n\tbool cant_use_aperture;\n\tbool needs_scratch_page;\n\tconst struct gatt_mask *masks;\n\tint (*fetch_size)();\n\tint (*configure)();\n\tvoid (*agp_enable)(struct agp_bridge_data *, u32);\n\tvoid (*cleanup)();\n\tvoid (*tlb_flush)(struct agp_memory *);\n\tlong unsigned int (*mask_memory)(struct agp_bridge_data *, dma_addr_t, int);\n\tvoid (*cache_flush)();\n\tint (*create_gatt_table)(struct agp_bridge_data *);\n\tint (*free_gatt_table)(struct agp_bridge_data *);\n\tint (*insert_memory)(struct agp_memory *, off_t, int);\n\tint (*remove_memory)(struct agp_memory *, off_t, int);\n\tstruct agp_memory * (*alloc_by_type)(size_t, int);\n\tvoid (*free_by_type)(struct agp_memory *);\n\tstruct page * (*agp_alloc_page)(struct agp_bridge_data *);\n\tint (*agp_alloc_pages)(struct agp_bridge_data *, struct agp_memory *, size_t);\n\tvoid (*agp_destroy_page)(struct page *, int);\n\tvoid (*agp_destroy_pages)(struct agp_memory *);\n\tint (*agp_type_to_mask_type)(struct agp_bridge_data *, int);\n};\n\nstruct agp_kern_info {\n\tstruct agp_version version;\n\tstruct pci_dev *device;\n\tenum chipset_type chipset;\n\tlong unsigned int mode;\n\tlong unsigned int aper_base;\n\tsize_t aper_size;\n\tint max_memory;\n\tint current_memory;\n\tbool cant_use_aperture;\n\tlong unsigned int page_mask;\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct agp_info {\n\tstruct agp_version version;\n\tu32 bridge_id;\n\tu32 agp_mode;\n\tlong unsigned int aper_base;\n\tsize_t aper_size;\n\tsize_t pg_total;\n\tsize_t pg_system;\n\tsize_t pg_used;\n};\n\nstruct agp_setup {\n\tu32 agp_mode;\n};\n\nstruct agp_segment {\n\toff_t pg_start;\n\tsize_t pg_count;\n\tint prot;\n};\n\nstruct agp_segment_priv {\n\toff_t pg_start;\n\tsize_t pg_count;\n\tpgprot_t prot;\n};\n\nstruct agp_region {\n\tpid_t pid;\n\tsize_t seg_count;\n\tstruct agp_segment *seg_list;\n};\n\nstruct agp_allocate {\n\tint key;\n\tsize_t pg_count;\n\tu32 type;\n\tu32 physical;\n};\n\nstruct agp_bind {\n\tint key;\n\toff_t pg_start;\n};\n\nstruct agp_unbind {\n\tint key;\n\tu32 priority;\n};\n\nstruct agp_client {\n\tstruct agp_client *next;\n\tstruct agp_client *prev;\n\tpid_t pid;\n\tint num_segments;\n\tstruct agp_segment_priv **segments;\n};\n\nstruct agp_controller {\n\tstruct agp_controller *next;\n\tstruct agp_controller *prev;\n\tpid_t pid;\n\tint num_clients;\n\tstruct agp_memory *pool;\n\tstruct agp_client *clients;\n};\n\nstruct agp_file_private {\n\tstruct agp_file_private *next;\n\tstruct agp_file_private *prev;\n\tpid_t my_pid;\n\tlong unsigned int access_flags;\n};\n\nstruct agp_front_data {\n\tstruct mutex agp_mutex;\n\tstruct agp_controller *current_controller;\n\tstruct agp_controller *controllers;\n\tstruct agp_file_private *file_priv_list;\n\tbool used_by_controller;\n\tbool backend_acquired;\n};\n\nstruct aper_size_info_8 {\n\tint size;\n\tint num_entries;\n\tint page_order;\n\tu8 size_value;\n};\n\nstruct aper_size_info_32 {\n\tint size;\n\tint num_entries;\n\tint page_order;\n\tu32 size_value;\n};\n\nstruct aper_size_info_lvl2 {\n\tint size;\n\tint num_entries;\n\tu32 size_value;\n};\n\nstruct aper_size_info_fixed {\n\tint size;\n\tint num_entries;\n\tint page_order;\n};\n\nstruct agp_3_5_dev {\n\tstruct list_head list;\n\tu8 capndx;\n\tu32 maxbw;\n\tstruct pci_dev *dev;\n};\n\nstruct isoch_data {\n\tu32 maxbw;\n\tu32 n;\n\tu32 y;\n\tu32 l;\n\tu32 rq;\n\tstruct agp_3_5_dev *dev;\n};\n\nstruct agp_info32 {\n\tstruct agp_version version;\n\tu32 bridge_id;\n\tu32 agp_mode;\n\tcompat_long_t aper_base;\n\tcompat_size_t aper_size;\n\tcompat_size_t pg_total;\n\tcompat_size_t pg_system;\n\tcompat_size_t pg_used;\n};\n\nstruct agp_segment32 {\n\tcompat_off_t pg_start;\n\tcompat_size_t pg_count;\n\tcompat_int_t prot;\n};\n\nstruct agp_region32 {\n\tcompat_pid_t pid;\n\tcompat_size_t seg_count;\n\tstruct agp_segment32 *seg_list;\n};\n\nstruct agp_allocate32 {\n\tcompat_int_t key;\n\tcompat_size_t pg_count;\n\tu32 type;\n\tu32 physical;\n};\n\nstruct agp_bind32 {\n\tcompat_int_t key;\n\tcompat_off_t pg_start;\n};\n\nstruct agp_unbind32 {\n\tcompat_int_t key;\n\tu32 priority;\n};\n\nstruct intel_agp_driver_description {\n\tunsigned int chip_id;\n\tchar *name;\n\tconst struct agp_bridge_driver *driver;\n};\n\nstruct intel_gtt_driver {\n\tunsigned int gen: 8;\n\tunsigned int is_g33: 1;\n\tunsigned int is_pineview: 1;\n\tunsigned int is_ironlake: 1;\n\tunsigned int has_pgtbl_enable: 1;\n\tunsigned int dma_mask_size: 8;\n\tint (*setup)();\n\tvoid (*cleanup)();\n\tvoid (*write_entry)(dma_addr_t, unsigned int, unsigned int);\n\tbool (*check_flags)(unsigned int);\n\tvoid (*chipset_flush)();\n};\n\nstruct _intel_private {\n\tconst struct intel_gtt_driver *driver;\n\tstruct pci_dev *pcidev;\n\tstruct pci_dev *bridge_dev;\n\tu8 *registers;\n\tphys_addr_t gtt_phys_addr;\n\tu32 PGETBL_save;\n\tu32 *gtt;\n\tbool clear_fake_agp;\n\tint num_dcache_entries;\n\tvoid *i9xx_flush_page;\n\tchar *i81x_gtt_table;\n\tstruct resource ifp_resource;\n\tint resource_valid;\n\tstruct page *scratch_page;\n\tphys_addr_t scratch_page_dma;\n\tint refcount;\n\tunsigned int needs_dmar: 1;\n\tphys_addr_t gma_bus_addr;\n\tresource_size_t stolen_size;\n\tunsigned int gtt_total_entries;\n\tunsigned int gtt_mappable_entries;\n};\n\nstruct intel_gtt_driver_description {\n\tunsigned int gmch_chip_id;\n\tchar *name;\n\tconst struct intel_gtt_driver *gtt_driver;\n};\n\nenum device_link_state {\n\tDL_STATE_NONE = 4294967295,\n\tDL_STATE_DORMANT = 0,\n\tDL_STATE_AVAILABLE = 1,\n\tDL_STATE_CONSUMER_PROBE = 2,\n\tDL_STATE_ACTIVE = 3,\n\tDL_STATE_SUPPLIER_UNBIND = 4,\n};\n\nstruct device_link {\n\tstruct device *supplier;\n\tstruct list_head s_node;\n\tstruct device *consumer;\n\tstruct list_head c_node;\n\tenum device_link_state status;\n\tu32 flags;\n\trefcount_t rpm_active;\n\tstruct kref kref;\n\tstruct callback_head callback_head;\n\tbool supplier_preactivated;\n};\n\nstruct iommu_group {\n\tstruct kobject kobj;\n\tstruct kobject *devices_kobj;\n\tstruct list_head devices;\n\tstruct mutex mutex;\n\tstruct blocking_notifier_head notifier;\n\tvoid *iommu_data;\n\tvoid (*iommu_data_release)(void *);\n\tchar *name;\n\tint id;\n\tstruct iommu_domain *default_domain;\n\tstruct iommu_domain *domain;\n\tstruct list_head entry;\n};\n\ntypedef unsigned int ioasid_t;\n\nenum iommu_fault_type {\n\tIOMMU_FAULT_DMA_UNRECOV = 1,\n\tIOMMU_FAULT_PAGE_REQ = 2,\n};\n\nstruct fsl_mc_obj_desc {\n\tchar type[16];\n\tint id;\n\tu16 vendor;\n\tu16 ver_major;\n\tu16 ver_minor;\n\tu8 irq_count;\n\tu8 region_count;\n\tu32 state;\n\tchar label[16];\n\tu16 flags;\n};\n\nstruct fsl_mc_io;\n\nstruct fsl_mc_device_irq;\n\nstruct fsl_mc_resource;\n\nstruct fsl_mc_device {\n\tstruct device dev;\n\tu64 dma_mask;\n\tu16 flags;\n\tu16 icid;\n\tu16 mc_handle;\n\tstruct fsl_mc_io *mc_io;\n\tstruct fsl_mc_obj_desc obj_desc;\n\tstruct resource *regions;\n\tstruct fsl_mc_device_irq **irqs;\n\tstruct fsl_mc_resource *resource;\n\tstruct device_link *consumer_link;\n};\n\nenum fsl_mc_pool_type {\n\tFSL_MC_POOL_DPMCP = 0,\n\tFSL_MC_POOL_DPBP = 1,\n\tFSL_MC_POOL_DPCON = 2,\n\tFSL_MC_POOL_IRQ = 3,\n\tFSL_MC_NUM_POOL_TYPES = 4,\n};\n\nstruct fsl_mc_resource_pool;\n\nstruct fsl_mc_resource {\n\tenum fsl_mc_pool_type type;\n\ts32 id;\n\tvoid *data;\n\tstruct fsl_mc_resource_pool *parent_pool;\n\tstruct list_head node;\n};\n\nstruct fsl_mc_device_irq {\n\tstruct msi_desc *msi_desc;\n\tstruct fsl_mc_device *mc_dev;\n\tu8 dev_irq_index;\n\tstruct fsl_mc_resource resource;\n};\n\nstruct fsl_mc_io {\n\tstruct device *dev;\n\tu16 flags;\n\tu32 portal_size;\n\tphys_addr_t portal_phys_addr;\n\tvoid *portal_virt_addr;\n\tstruct fsl_mc_device *dpmcp_dev;\n\tunion {\n\t\tstruct mutex mutex;\n\t\tspinlock_t spinlock;\n\t};\n};\n\nstruct group_device {\n\tstruct list_head list;\n\tstruct device *dev;\n\tchar *name;\n};\n\nstruct iommu_group_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct iommu_group *, char *);\n\tssize_t (*store)(struct iommu_group *, const char *, size_t);\n};\n\nstruct group_for_pci_data {\n\tstruct pci_dev *pdev;\n\tstruct iommu_group *group;\n};\n\nstruct __group_domain_type {\n\tstruct device *dev;\n\tunsigned int type;\n};\n\nstruct trace_event_raw_iommu_group_event {\n\tstruct trace_entry ent;\n\tint gid;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_device_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_map {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tu64 paddr;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_unmap {\n\tstruct trace_entry ent;\n\tu64 iova;\n\tsize_t size;\n\tsize_t unmapped_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_iommu_error {\n\tstruct trace_entry ent;\n\tu32 __data_loc_device;\n\tu32 __data_loc_driver;\n\tu64 iova;\n\tint flags;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_iommu_group_event {\n\tu32 device;\n};\n\nstruct trace_event_data_offsets_iommu_device_event {\n\tu32 device;\n};\n\nstruct trace_event_data_offsets_map {};\n\nstruct trace_event_data_offsets_unmap {};\n\nstruct trace_event_data_offsets_iommu_error {\n\tu32 device;\n\tu32 driver;\n};\n\ntypedef void (*btf_trace_add_device_to_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_remove_device_from_group)(void *, int, struct device *);\n\ntypedef void (*btf_trace_attach_device_to_domain)(void *, struct device *);\n\ntypedef void (*btf_trace_detach_device_from_domain)(void *, struct device *);\n\ntypedef void (*btf_trace_map)(void *, long unsigned int, phys_addr_t, size_t);\n\ntypedef void (*btf_trace_unmap)(void *, long unsigned int, size_t, size_t);\n\ntypedef void (*btf_trace_io_page_fault)(void *, struct device *, long unsigned int, int);\n\nstruct iova {\n\tstruct rb_node node;\n\tlong unsigned int pfn_hi;\n\tlong unsigned int pfn_lo;\n};\n\nstruct iova_magazine;\n\nstruct iova_cpu_rcache;\n\nstruct iova_rcache {\n\tspinlock_t lock;\n\tlong unsigned int depot_size;\n\tstruct iova_magazine *depot[32];\n\tstruct iova_cpu_rcache *cpu_rcaches;\n};\n\nstruct iova_domain;\n\ntypedef void (*iova_flush_cb)(struct iova_domain *);\n\ntypedef void (*iova_entry_dtor)(long unsigned int);\n\nstruct iova_fq;\n\nstruct iova_domain {\n\tspinlock_t iova_rbtree_lock;\n\tstruct rb_root rbroot;\n\tstruct rb_node *cached_node;\n\tstruct rb_node *cached32_node;\n\tlong unsigned int granule;\n\tlong unsigned int start_pfn;\n\tlong unsigned int dma_32bit_pfn;\n\tlong unsigned int max32_alloc_size;\n\tstruct iova_fq *fq;\n\tatomic64_t fq_flush_start_cnt;\n\tatomic64_t fq_flush_finish_cnt;\n\tstruct iova anchor;\n\tstruct iova_rcache rcaches[6];\n\tiova_flush_cb flush_cb;\n\tiova_entry_dtor entry_dtor;\n\tstruct timer_list fq_timer;\n\tatomic_t fq_timer_on;\n};\n\nstruct iova_fq_entry {\n\tlong unsigned int iova_pfn;\n\tlong unsigned int pages;\n\tlong unsigned int data;\n\tu64 counter;\n};\n\nstruct iova_fq {\n\tstruct iova_fq_entry entries[256];\n\tunsigned int head;\n\tunsigned int tail;\n\tspinlock_t lock;\n};\n\nstruct iommu_dma_msi_page {\n\tstruct list_head list;\n\tdma_addr_t iova;\n\tphys_addr_t phys;\n};\n\nenum iommu_dma_cookie_type {\n\tIOMMU_DMA_IOVA_COOKIE = 0,\n\tIOMMU_DMA_MSI_COOKIE = 1,\n};\n\nstruct iommu_dma_cookie {\n\tenum iommu_dma_cookie_type type;\n\tunion {\n\t\tstruct iova_domain iovad;\n\t\tdma_addr_t msi_iova;\n\t};\n\tstruct list_head msi_page_list;\n\tstruct iommu_domain *fq_domain;\n};\n\ntypedef ioasid_t (*ioasid_alloc_fn_t)(ioasid_t, ioasid_t, void *);\n\ntypedef void (*ioasid_free_fn_t)(ioasid_t, void *);\n\nstruct ioasid_set {\n\tint dummy;\n};\n\nstruct ioasid_allocator_ops {\n\tioasid_alloc_fn_t alloc;\n\tioasid_free_fn_t free;\n\tstruct list_head list;\n\tvoid *pdata;\n};\n\nstruct ioasid_data {\n\tioasid_t id;\n\tstruct ioasid_set *set;\n\tvoid *private;\n\tstruct callback_head rcu;\n};\n\nstruct ioasid_allocator_data {\n\tstruct ioasid_allocator_ops *ops;\n\tstruct list_head list;\n\tstruct list_head slist;\n\tlong unsigned int flags;\n\tstruct xarray xa;\n\tstruct callback_head rcu;\n};\n\nstruct iova_magazine {\n\tlong unsigned int size;\n\tlong unsigned int pfns[128];\n};\n\nstruct iova_cpu_rcache {\n\tspinlock_t lock;\n\tstruct iova_magazine *loaded;\n\tstruct iova_magazine *prev;\n};\n\nstruct amd_iommu_device_info {\n\tint max_pasids;\n\tu32 flags;\n};\n\nstruct irq_remap_table {\n\traw_spinlock_t lock;\n\tunsigned int min_index;\n\tu32 *table;\n};\n\nstruct amd_iommu_fault {\n\tu64 address;\n\tu32 pasid;\n\tu16 device_id;\n\tu16 tag;\n\tu16 flags;\n};\n\nstruct protection_domain {\n\tstruct list_head dev_list;\n\tstruct iommu_domain domain;\n\tspinlock_t lock;\n\tu16 id;\n\tatomic64_t pt_root;\n\tint glx;\n\tu64 *gcr3_tbl;\n\tlong unsigned int flags;\n\tunsigned int dev_cnt;\n\tunsigned int dev_iommu[32];\n};\n\nstruct domain_pgtable {\n\tint mode;\n\tu64 *root;\n};\n\nstruct amd_iommu___2 {\n\tstruct list_head list;\n\tint index;\n\traw_spinlock_t lock;\n\tstruct pci_dev *dev;\n\tstruct pci_dev *root_pdev;\n\tu64 mmio_phys;\n\tu64 mmio_phys_end;\n\tu8 *mmio_base;\n\tu32 cap;\n\tu8 acpi_flags;\n\tu64 features;\n\tbool is_iommu_v2;\n\tu16 devid;\n\tu16 cap_ptr;\n\tu16 pci_seg;\n\tu64 exclusion_start;\n\tu64 exclusion_length;\n\tu8 *cmd_buf;\n\tu32 cmd_buf_head;\n\tu32 cmd_buf_tail;\n\tu8 *evt_buf;\n\tu8 *ppr_log;\n\tu8 *ga_log;\n\tu8 *ga_log_tail;\n\tbool int_enabled;\n\tbool need_sync;\n\tstruct iommu_device iommu;\n\tu32 stored_addr_lo;\n\tu32 stored_addr_hi;\n\tu32 stored_l1[108];\n\tu32 stored_l2[131];\n\tu8 max_banks;\n\tu8 max_counters;\n\tu32 flags;\n\tvolatile u64 cmd_sem;\n\tstruct irq_affinity_notify intcapxt_notify;\n};\n\nstruct acpihid_map_entry {\n\tstruct list_head list;\n\tu8 uid[256];\n\tu8 hid[9];\n\tu16 devid;\n\tu16 root_devid;\n\tbool cmd_line;\n\tstruct iommu_group *group;\n};\n\nstruct iommu_dev_data {\n\tspinlock_t lock;\n\tstruct list_head list;\n\tstruct llist_node dev_data_list;\n\tstruct protection_domain *domain;\n\tstruct pci_dev *pdev;\n\tu16 devid;\n\tbool iommu_v2;\n\tstruct {\n\t\tbool enabled;\n\t\tint qdep;\n\t} ats;\n\tbool pri_tlp;\n\tu32 errata;\n\tbool use_vapic;\n\tbool defer_attach;\n\tstruct ratelimit_state rs;\n};\n\nstruct dev_table_entry {\n\tu64 data[4];\n};\n\nstruct unity_map_entry {\n\tstruct list_head list;\n\tu16 devid_start;\n\tu16 devid_end;\n\tu64 address_start;\n\tu64 address_end;\n\tint prot;\n};\n\nstruct iommu_cmd {\n\tu32 data[4];\n};\n\nenum {\n\tIRQ_REMAP_XAPIC_MODE = 0,\n\tIRQ_REMAP_X2APIC_MODE = 1,\n};\n\nstruct devid_map {\n\tstruct list_head list;\n\tu8 id;\n\tu16 devid;\n\tbool cmd_line;\n};\n\nenum amd_iommu_intr_mode_type {\n\tAMD_IOMMU_GUEST_IR_LEGACY = 0,\n\tAMD_IOMMU_GUEST_IR_LEGACY_GA = 1,\n\tAMD_IOMMU_GUEST_IR_VAPIC = 2,\n};\n\nstruct ivhd_header {\n\tu8 type;\n\tu8 flags;\n\tu16 length;\n\tu16 devid;\n\tu16 cap_ptr;\n\tu64 mmio_phys;\n\tu16 pci_seg;\n\tu16 info;\n\tu32 efr_attr;\n\tu64 efr_reg;\n\tu64 res;\n};\n\nstruct ivhd_entry {\n\tu8 type;\n\tu16 devid;\n\tu8 flags;\n\tu32 ext;\n\tu32 hidh;\n\tu64 cid;\n\tu8 uidf;\n\tu8 uidl;\n\tu8 uid;\n} __attribute__((packed));\n\nstruct ivmd_header {\n\tu8 type;\n\tu8 flags;\n\tu16 length;\n\tu16 devid;\n\tu16 aux;\n\tu64 resv;\n\tu64 range_start;\n\tu64 range_length;\n};\n\nenum iommu_init_state {\n\tIOMMU_START_STATE = 0,\n\tIOMMU_IVRS_DETECTED = 1,\n\tIOMMU_ACPI_FINISHED = 2,\n\tIOMMU_ENABLED = 3,\n\tIOMMU_PCI_INIT = 4,\n\tIOMMU_INTERRUPTS_EN = 5,\n\tIOMMU_DMA_OPS = 6,\n\tIOMMU_INITIALIZED = 7,\n\tIOMMU_NOT_FOUND = 8,\n\tIOMMU_INIT_ERROR = 9,\n\tIOMMU_CMDLINE_DISABLED = 10,\n};\n\nstruct ivrs_quirk_entry {\n\tu8 id;\n\tu16 devid;\n};\n\nenum {\n\tDELL_INSPIRON_7375 = 0,\n\tDELL_LATITUDE_5495 = 1,\n\tLENOVO_IDEAPAD_330S_15ARR = 2,\n};\n\nstruct acpi_table_dmar {\n\tstruct acpi_table_header header;\n\tu8 width;\n\tu8 flags;\n\tu8 reserved[10];\n};\n\nstruct acpi_dmar_header {\n\tu16 type;\n\tu16 length;\n};\n\nenum acpi_dmar_type {\n\tACPI_DMAR_TYPE_HARDWARE_UNIT = 0,\n\tACPI_DMAR_TYPE_RESERVED_MEMORY = 1,\n\tACPI_DMAR_TYPE_ROOT_ATS = 2,\n\tACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3,\n\tACPI_DMAR_TYPE_NAMESPACE = 4,\n\tACPI_DMAR_TYPE_RESERVED = 5,\n};\n\nstruct acpi_dmar_device_scope {\n\tu8 entry_type;\n\tu8 length;\n\tu16 reserved;\n\tu8 enumeration_id;\n\tu8 bus;\n};\n\nenum acpi_dmar_scope_type {\n\tACPI_DMAR_SCOPE_TYPE_NOT_USED = 0,\n\tACPI_DMAR_SCOPE_TYPE_ENDPOINT = 1,\n\tACPI_DMAR_SCOPE_TYPE_BRIDGE = 2,\n\tACPI_DMAR_SCOPE_TYPE_IOAPIC = 3,\n\tACPI_DMAR_SCOPE_TYPE_HPET = 4,\n\tACPI_DMAR_SCOPE_TYPE_NAMESPACE = 5,\n\tACPI_DMAR_SCOPE_TYPE_RESERVED = 6,\n};\n\nstruct acpi_dmar_pci_path {\n\tu8 device;\n\tu8 function;\n};\n\nstruct acpi_dmar_hardware_unit {\n\tstruct acpi_dmar_header header;\n\tu8 flags;\n\tu8 reserved;\n\tu16 segment;\n\tu64 address;\n};\n\nstruct acpi_dmar_reserved_memory {\n\tstruct acpi_dmar_header header;\n\tu16 reserved;\n\tu16 segment;\n\tu64 base_address;\n\tu64 end_address;\n};\n\nstruct acpi_dmar_atsr {\n\tstruct acpi_dmar_header header;\n\tu8 flags;\n\tu8 reserved;\n\tu16 segment;\n};\n\nstruct acpi_dmar_rhsa {\n\tstruct acpi_dmar_header header;\n\tu32 reserved;\n\tu64 base_address;\n\tu32 proximity_domain;\n} __attribute__((packed));\n\nstruct acpi_dmar_andd {\n\tstruct acpi_dmar_header header;\n\tu8 reserved[3];\n\tu8 device_number;\n\tchar device_name[1];\n} __attribute__((packed));\n\nstruct dmar_dev_scope {\n\tstruct device *dev;\n\tu8 bus;\n\tu8 devfn;\n};\n\nstruct intel_iommu;\n\nstruct dmar_drhd_unit {\n\tstruct list_head list;\n\tstruct acpi_dmar_header *hdr;\n\tu64 reg_base_addr;\n\tstruct dmar_dev_scope *devices;\n\tint devices_cnt;\n\tu16 segment;\n\tu8 ignored: 1;\n\tu8 include_all: 1;\n\tstruct intel_iommu *iommu;\n};\n\nstruct iommu_flush {\n\tvoid (*flush_context)(struct intel_iommu *, u16, u16, u8, u64);\n\tvoid (*flush_iotlb)(struct intel_iommu *, u16, u64, unsigned int, u64);\n};\n\nstruct dmar_domain;\n\nstruct root_entry;\n\nstruct q_inval;\n\nstruct intel_iommu {\n\tvoid *reg;\n\tu64 reg_phys;\n\tu64 reg_size;\n\tu64 cap;\n\tu64 ecap;\n\tu64 vccap;\n\tu32 gcmd;\n\traw_spinlock_t register_lock;\n\tint seq_id;\n\tint agaw;\n\tint msagaw;\n\tunsigned int irq;\n\tunsigned int pr_irq;\n\tu16 segment;\n\tunsigned char name[13];\n\tlong unsigned int *domain_ids;\n\tstruct dmar_domain ***domains;\n\tspinlock_t lock;\n\tstruct root_entry *root_entry;\n\tstruct iommu_flush flush;\n\tstruct q_inval *qi;\n\tu32 *iommu_state;\n\tstruct iommu_device iommu;\n\tint node;\n\tu32 flags;\n};\n\nstruct dmar_pci_path {\n\tu8 bus;\n\tu8 device;\n\tu8 function;\n};\n\nstruct dmar_pci_notify_info {\n\tstruct pci_dev *dev;\n\tlong unsigned int event;\n\tint bus;\n\tu16 seg;\n\tu16 level;\n\tstruct dmar_pci_path path[0];\n};\n\nenum {\n\tQI_FREE = 0,\n\tQI_IN_USE = 1,\n\tQI_DONE = 2,\n\tQI_ABORT = 3,\n};\n\nstruct qi_desc {\n\tu64 qw0;\n\tu64 qw1;\n\tu64 qw2;\n\tu64 qw3;\n};\n\nstruct q_inval {\n\traw_spinlock_t q_lock;\n\tvoid *desc;\n\tint *desc_status;\n\tint free_head;\n\tint free_tail;\n\tint free_cnt;\n};\n\nstruct root_entry {\n\tu64 lo;\n\tu64 hi;\n};\n\nstruct dma_pte;\n\nstruct dmar_domain {\n\tint nid;\n\tunsigned int iommu_refcnt[128];\n\tu16 iommu_did[128];\n\tunsigned int auxd_refcnt;\n\tbool has_iotlb_device;\n\tstruct list_head devices;\n\tstruct list_head auxd;\n\tstruct iova_domain iovad;\n\tstruct dma_pte *pgd;\n\tint gaw;\n\tint agaw;\n\tint flags;\n\tint iommu_coherency;\n\tint iommu_snooping;\n\tint iommu_count;\n\tint iommu_superpage;\n\tu64 max_addr;\n\tint default_pasid;\n\tstruct iommu_domain domain;\n};\n\nstruct dma_pte {\n\tu64 val;\n};\n\ntypedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *);\n\nstruct dmar_res_callback {\n\tdmar_res_handler_t cb[5];\n\tvoid *arg[5];\n\tbool ignore_unhandled;\n\tbool print_entry;\n};\n\nenum faulttype {\n\tDMA_REMAP = 0,\n\tINTR_REMAP = 1,\n\tUNKNOWN = 2,\n};\n\nstruct memory_notify {\n\tlong unsigned int start_pfn;\n\tlong unsigned int nr_pages;\n\tint status_change_nid_normal;\n\tint status_change_nid_high;\n\tint status_change_nid;\n};\n\nenum {\n\tSR_DMAR_FECTL_REG = 0,\n\tSR_DMAR_FEDATA_REG = 1,\n\tSR_DMAR_FEADDR_REG = 2,\n\tSR_DMAR_FEUADDR_REG = 3,\n\tMAX_SR_DMAR_REGS = 4,\n};\n\nstruct context_entry {\n\tu64 lo;\n\tu64 hi;\n};\n\nstruct pasid_table;\n\nstruct device_domain_info {\n\tstruct list_head link;\n\tstruct list_head global;\n\tstruct list_head table;\n\tstruct list_head auxiliary_domains;\n\tu32 segment;\n\tu8 bus;\n\tu8 devfn;\n\tu16 pfsid;\n\tu8 pasid_supported: 3;\n\tu8 pasid_enabled: 1;\n\tu8 pri_supported: 1;\n\tu8 pri_enabled: 1;\n\tu8 ats_supported: 1;\n\tu8 ats_enabled: 1;\n\tu8 auxd_enabled: 1;\n\tu8 ats_qdep;\n\tstruct device *dev;\n\tstruct intel_iommu *iommu;\n\tstruct dmar_domain *domain;\n\tstruct pasid_table *pasid_table;\n};\n\nstruct pasid_table {\n\tvoid *table;\n\tint order;\n\tint max_pasid;\n\tstruct list_head dev;\n};\n\nstruct dmar_rmrr_unit {\n\tstruct list_head list;\n\tstruct acpi_dmar_header *hdr;\n\tu64 base_address;\n\tu64 end_address;\n\tstruct dmar_dev_scope *devices;\n\tint devices_cnt;\n};\n\nstruct dmar_atsr_unit {\n\tstruct list_head list;\n\tstruct acpi_dmar_header *hdr;\n\tstruct dmar_dev_scope *devices;\n\tint devices_cnt;\n\tu8 include_all: 1;\n};\n\nstruct domain_context_mapping_data {\n\tstruct dmar_domain *domain;\n\tstruct intel_iommu *iommu;\n\tstruct pasid_table *table;\n};\n\nstruct pasid_dir_entry {\n\tu64 val;\n};\n\nstruct pasid_entry {\n\tu64 val[8];\n};\n\nstruct pasid_table_opaque {\n\tstruct pasid_table **pasid_table;\n\tint segment;\n\tint bus;\n\tint devfn;\n};\n\nstruct trace_event_raw_dma_map {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tdma_addr_t dev_addr;\n\tphys_addr_t phys_addr;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_unmap {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tdma_addr_t dev_addr;\n\tsize_t size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_dma_map_sg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tdma_addr_t dev_addr;\n\tphys_addr_t phys_addr;\n\tsize_t size;\n\tint index;\n\tint total;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_dma_map {\n\tu32 dev_name;\n};\n\nstruct trace_event_data_offsets_dma_unmap {\n\tu32 dev_name;\n};\n\nstruct trace_event_data_offsets_dma_map_sg {\n\tu32 dev_name;\n};\n\ntypedef void (*btf_trace_map_single)(void *, struct device *, dma_addr_t, phys_addr_t, size_t);\n\ntypedef void (*btf_trace_bounce_map_single)(void *, struct device *, dma_addr_t, phys_addr_t, size_t);\n\ntypedef void (*btf_trace_unmap_single)(void *, struct device *, dma_addr_t, size_t);\n\ntypedef void (*btf_trace_unmap_sg)(void *, struct device *, dma_addr_t, size_t);\n\ntypedef void (*btf_trace_bounce_unmap_single)(void *, struct device *, dma_addr_t, size_t);\n\ntypedef void (*btf_trace_map_sg)(void *, struct device *, int, int, struct scatterlist *);\n\ntypedef void (*btf_trace_bounce_map_sg)(void *, struct device *, int, int, struct scatterlist *);\n\nstruct i2c_msg {\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\t__u8 *buf;\n};\n\nunion i2c_smbus_data {\n\t__u8 byte;\n\t__u16 word;\n\t__u8 block[34];\n};\n\nstruct i2c_algorithm;\n\nstruct i2c_lock_operations;\n\nstruct i2c_bus_recovery_info;\n\nstruct i2c_adapter_quirks;\n\nstruct i2c_adapter {\n\tstruct module *owner;\n\tunsigned int class;\n\tconst struct i2c_algorithm *algo;\n\tvoid *algo_data;\n\tconst struct i2c_lock_operations *lock_ops;\n\tstruct rt_mutex bus_lock;\n\tstruct rt_mutex mux_lock;\n\tint timeout;\n\tint retries;\n\tstruct device dev;\n\tlong unsigned int locked_flags;\n\tint nr;\n\tchar name[48];\n\tstruct completion dev_released;\n\tstruct mutex userspace_clients_lock;\n\tstruct list_head userspace_clients;\n\tstruct i2c_bus_recovery_info *bus_recovery_info;\n\tconst struct i2c_adapter_quirks *quirks;\n\tstruct irq_domain *host_notify_domain;\n};\n\nstruct i2c_algorithm {\n\tint (*master_xfer)(struct i2c_adapter *, struct i2c_msg *, int);\n\tint (*master_xfer_atomic)(struct i2c_adapter *, struct i2c_msg *, int);\n\tint (*smbus_xfer)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tint (*smbus_xfer_atomic)(struct i2c_adapter *, u16, short unsigned int, char, u8, int, union i2c_smbus_data *);\n\tu32 (*functionality)(struct i2c_adapter *);\n};\n\nstruct i2c_lock_operations {\n\tvoid (*lock_bus)(struct i2c_adapter *, unsigned int);\n\tint (*trylock_bus)(struct i2c_adapter *, unsigned int);\n\tvoid (*unlock_bus)(struct i2c_adapter *, unsigned int);\n};\n\nstruct i2c_bus_recovery_info {\n\tint (*recover_bus)(struct i2c_adapter *);\n\tint (*get_scl)(struct i2c_adapter *);\n\tvoid (*set_scl)(struct i2c_adapter *, int);\n\tint (*get_sda)(struct i2c_adapter *);\n\tvoid (*set_sda)(struct i2c_adapter *, int);\n\tint (*get_bus_free)(struct i2c_adapter *);\n\tvoid (*prepare_recovery)(struct i2c_adapter *);\n\tvoid (*unprepare_recovery)(struct i2c_adapter *);\n\tstruct gpio_desc *scl_gpiod;\n\tstruct gpio_desc *sda_gpiod;\n};\n\nstruct i2c_adapter_quirks {\n\tu64 flags;\n\tint max_num_msgs;\n\tu16 max_write_len;\n\tu16 max_read_len;\n\tu16 max_comb_1st_msg_len;\n\tu16 max_comb_2nd_msg_len;\n};\n\nstruct hdr_static_metadata {\n\t__u8 eotf;\n\t__u8 metadata_type;\n\t__u16 max_cll;\n\t__u16 max_fall;\n\t__u16 min_cll;\n};\n\nstruct hdr_sink_metadata {\n\t__u32 metadata_type;\n\tunion {\n\t\tstruct hdr_static_metadata hdmi_type1;\n\t};\n};\n\nstruct drm_clip_rect {\n\tshort unsigned int x1;\n\tshort unsigned int y1;\n\tshort unsigned int x2;\n\tshort unsigned int y2;\n};\n\nenum drm_mode_subconnector {\n\tDRM_MODE_SUBCONNECTOR_Automatic = 0,\n\tDRM_MODE_SUBCONNECTOR_Unknown = 0,\n\tDRM_MODE_SUBCONNECTOR_DVID = 3,\n\tDRM_MODE_SUBCONNECTOR_DVIA = 4,\n\tDRM_MODE_SUBCONNECTOR_Composite = 5,\n\tDRM_MODE_SUBCONNECTOR_SVIDEO = 6,\n\tDRM_MODE_SUBCONNECTOR_Component = 8,\n\tDRM_MODE_SUBCONNECTOR_SCART = 9,\n};\n\nstruct drm_mode_fb_cmd2 {\n\t__u32 fb_id;\n\t__u32 width;\n\t__u32 height;\n\t__u32 pixel_format;\n\t__u32 flags;\n\t__u32 handles[4];\n\t__u32 pitches[4];\n\t__u32 offsets[4];\n\t__u64 modifier[4];\n};\n\nstruct drm_modeset_lock;\n\nstruct drm_modeset_acquire_ctx {\n\tstruct ww_acquire_ctx ww_ctx;\n\tstruct drm_modeset_lock *contended;\n\tstruct list_head locked;\n\tbool trylock_only;\n\tbool interruptible;\n};\n\nstruct drm_modeset_lock {\n\tstruct ww_mutex mutex;\n\tstruct list_head head;\n};\n\nstruct drm_rect {\n\tint x1;\n\tint y1;\n\tint x2;\n\tint y2;\n};\n\nstruct drm_object_properties;\n\nstruct drm_mode_object {\n\tuint32_t id;\n\tuint32_t type;\n\tstruct drm_object_properties *properties;\n\tstruct kref refcount;\n\tvoid (*free_cb)(struct kref *);\n};\n\nstruct drm_property;\n\nstruct drm_object_properties {\n\tint count;\n\tstruct drm_property *properties[24];\n\tuint64_t values[24];\n};\n\nstruct drm_device;\n\nstruct drm_property {\n\tstruct list_head head;\n\tstruct drm_mode_object base;\n\tuint32_t flags;\n\tchar name[32];\n\tuint32_t num_values;\n\tuint64_t *values;\n\tstruct drm_device *dev;\n\tstruct list_head enum_list;\n};\n\nstruct drm_framebuffer;\n\nstruct drm_file;\n\nstruct drm_framebuffer_funcs {\n\tvoid (*destroy)(struct drm_framebuffer *);\n\tint (*create_handle)(struct drm_framebuffer *, struct drm_file *, unsigned int *);\n\tint (*dirty)(struct drm_framebuffer *, struct drm_file *, unsigned int, unsigned int, struct drm_clip_rect *, unsigned int);\n};\n\nstruct drm_format_info;\n\nstruct drm_gem_object;\n\nstruct drm_framebuffer {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tstruct drm_mode_object base;\n\tchar comm[16];\n\tconst struct drm_format_info *format;\n\tconst struct drm_framebuffer_funcs *funcs;\n\tunsigned int pitches[4];\n\tunsigned int offsets[4];\n\tuint64_t modifier;\n\tunsigned int width;\n\tunsigned int height;\n\tint flags;\n\tint hot_x;\n\tint hot_y;\n\tstruct list_head filp_head;\n\tstruct drm_gem_object *obj[4];\n};\n\nstruct drm_mode_config_funcs;\n\nstruct drm_atomic_state;\n\nstruct drm_mode_config_helper_funcs;\n\nstruct drm_mode_config {\n\tstruct mutex mutex;\n\tstruct drm_modeset_lock connection_mutex;\n\tstruct drm_modeset_acquire_ctx *acquire_ctx;\n\tstruct mutex idr_mutex;\n\tstruct idr object_idr;\n\tstruct idr tile_idr;\n\tstruct mutex fb_lock;\n\tint num_fb;\n\tstruct list_head fb_list;\n\tspinlock_t connector_list_lock;\n\tint num_connector;\n\tstruct ida connector_ida;\n\tstruct list_head connector_list;\n\tstruct llist_head connector_free_list;\n\tstruct work_struct connector_free_work;\n\tint num_encoder;\n\tstruct list_head encoder_list;\n\tint num_total_plane;\n\tstruct list_head plane_list;\n\tint num_crtc;\n\tstruct list_head crtc_list;\n\tstruct list_head property_list;\n\tstruct list_head privobj_list;\n\tint min_width;\n\tint min_height;\n\tint max_width;\n\tint max_height;\n\tconst struct drm_mode_config_funcs *funcs;\n\tresource_size_t fb_base;\n\tbool poll_enabled;\n\tbool poll_running;\n\tbool delayed_event;\n\tstruct delayed_work output_poll_work;\n\tstruct mutex blob_lock;\n\tstruct list_head property_blob_list;\n\tstruct drm_property *edid_property;\n\tstruct drm_property *dpms_property;\n\tstruct drm_property *path_property;\n\tstruct drm_property *tile_property;\n\tstruct drm_property *link_status_property;\n\tstruct drm_property *plane_type_property;\n\tstruct drm_property *prop_src_x;\n\tstruct drm_property *prop_src_y;\n\tstruct drm_property *prop_src_w;\n\tstruct drm_property *prop_src_h;\n\tstruct drm_property *prop_crtc_x;\n\tstruct drm_property *prop_crtc_y;\n\tstruct drm_property *prop_crtc_w;\n\tstruct drm_property *prop_crtc_h;\n\tstruct drm_property *prop_fb_id;\n\tstruct drm_property *prop_in_fence_fd;\n\tstruct drm_property *prop_out_fence_ptr;\n\tstruct drm_property *prop_crtc_id;\n\tstruct drm_property *prop_fb_damage_clips;\n\tstruct drm_property *prop_active;\n\tstruct drm_property *prop_mode_id;\n\tstruct drm_property *prop_vrr_enabled;\n\tstruct drm_property *dvi_i_subconnector_property;\n\tstruct drm_property *dvi_i_select_subconnector_property;\n\tstruct drm_property *tv_subconnector_property;\n\tstruct drm_property *tv_select_subconnector_property;\n\tstruct drm_property *tv_mode_property;\n\tstruct drm_property *tv_left_margin_property;\n\tstruct drm_property *tv_right_margin_property;\n\tstruct drm_property *tv_top_margin_property;\n\tstruct drm_property *tv_bottom_margin_property;\n\tstruct drm_property *tv_brightness_property;\n\tstruct drm_property *tv_contrast_property;\n\tstruct drm_property *tv_flicker_reduction_property;\n\tstruct drm_property *tv_overscan_property;\n\tstruct drm_property *tv_saturation_property;\n\tstruct drm_property *tv_hue_property;\n\tstruct drm_property *scaling_mode_property;\n\tstruct drm_property *aspect_ratio_property;\n\tstruct drm_property *content_type_property;\n\tstruct drm_property *degamma_lut_property;\n\tstruct drm_property *degamma_lut_size_property;\n\tstruct drm_property *ctm_property;\n\tstruct drm_property *gamma_lut_property;\n\tstruct drm_property *gamma_lut_size_property;\n\tstruct drm_property *suggested_x_property;\n\tstruct drm_property *suggested_y_property;\n\tstruct drm_property *non_desktop_property;\n\tstruct drm_property *panel_orientation_property;\n\tstruct drm_property *writeback_fb_id_property;\n\tstruct drm_property *writeback_pixel_formats_property;\n\tstruct drm_property *writeback_out_fence_ptr_property;\n\tstruct drm_property *hdr_output_metadata_property;\n\tstruct drm_property *content_protection_property;\n\tstruct drm_property *hdcp_content_type_property;\n\tuint32_t preferred_depth;\n\tuint32_t prefer_shadow;\n\tbool prefer_shadow_fbdev;\n\tbool fbdev_use_iomem;\n\tbool quirk_addfb_prefer_xbgr_30bpp;\n\tbool quirk_addfb_prefer_host_byte_order;\n\tbool async_page_flip;\n\tbool allow_fb_modifiers;\n\tbool normalize_zpos;\n\tstruct drm_property *modifiers_property;\n\tuint32_t cursor_width;\n\tuint32_t cursor_height;\n\tstruct drm_atomic_state *suspend_state;\n\tconst struct drm_mode_config_helper_funcs *helper_private;\n};\n\nstruct drm_vram_mm;\n\nenum switch_power_state {\n\tDRM_SWITCH_POWER_ON = 0,\n\tDRM_SWITCH_POWER_OFF = 1,\n\tDRM_SWITCH_POWER_CHANGING = 2,\n\tDRM_SWITCH_POWER_DYNAMIC_OFF = 3,\n};\n\nstruct drm_driver;\n\nstruct drm_minor;\n\nstruct drm_master;\n\nstruct drm_vblank_crtc;\n\nstruct drm_agp_head;\n\nstruct drm_vma_offset_manager;\n\nstruct drm_fb_helper;\n\nstruct drm_device {\n\tstruct list_head legacy_dev_list;\n\tint if_version;\n\tstruct kref ref;\n\tstruct device *dev;\n\tstruct {\n\t\tstruct list_head resources;\n\t\tvoid *final_kfree;\n\t\tspinlock_t lock;\n\t} managed;\n\tstruct drm_driver *driver;\n\tvoid *dev_private;\n\tstruct drm_minor *primary;\n\tstruct drm_minor *render;\n\tbool registered;\n\tstruct drm_master *master;\n\tu32 driver_features;\n\tbool unplugged;\n\tstruct inode *anon_inode;\n\tchar *unique;\n\tstruct mutex struct_mutex;\n\tstruct mutex master_mutex;\n\tatomic_t open_count;\n\tstruct mutex filelist_mutex;\n\tstruct list_head filelist;\n\tstruct list_head filelist_internal;\n\tstruct mutex clientlist_mutex;\n\tstruct list_head clientlist;\n\tbool irq_enabled;\n\tint irq;\n\tbool vblank_disable_immediate;\n\tstruct drm_vblank_crtc *vblank;\n\tspinlock_t vblank_time_lock;\n\tspinlock_t vbl_lock;\n\tu32 max_vblank_count;\n\tstruct list_head vblank_event_list;\n\tspinlock_t event_lock;\n\tstruct drm_agp_head *agp;\n\tstruct pci_dev *pdev;\n\tunsigned int num_crtcs;\n\tstruct drm_mode_config mode_config;\n\tstruct mutex object_name_lock;\n\tstruct idr object_name_idr;\n\tstruct drm_vma_offset_manager *vma_offset_manager;\n\tstruct drm_vram_mm *vram_mm;\n\tenum switch_power_state switch_power_state;\n\tstruct drm_fb_helper *fb_helper;\n};\n\nstruct drm_format_info {\n\tu32 format;\n\tu8 depth;\n\tu8 num_planes;\n\tunion {\n\t\tu8 cpp[4];\n\t\tu8 char_per_block[4];\n\t};\n\tu8 block_w[4];\n\tu8 block_h[4];\n\tu8 hsub;\n\tu8 vsub;\n\tbool has_alpha;\n\tbool is_yuv;\n};\n\nenum drm_connector_force {\n\tDRM_FORCE_UNSPECIFIED = 0,\n\tDRM_FORCE_OFF = 1,\n\tDRM_FORCE_ON = 2,\n\tDRM_FORCE_ON_DIGITAL = 3,\n};\n\nenum drm_connector_status {\n\tconnector_status_connected = 1,\n\tconnector_status_disconnected = 2,\n\tconnector_status_unknown = 3,\n};\n\nenum drm_connector_registration_state {\n\tDRM_CONNECTOR_INITIALIZING = 0,\n\tDRM_CONNECTOR_REGISTERED = 1,\n\tDRM_CONNECTOR_UNREGISTERED = 2,\n};\n\nenum subpixel_order {\n\tSubPixelUnknown = 0,\n\tSubPixelHorizontalRGB = 1,\n\tSubPixelHorizontalBGR = 2,\n\tSubPixelVerticalRGB = 3,\n\tSubPixelVerticalBGR = 4,\n\tSubPixelNone = 5,\n};\n\nstruct drm_scrambling {\n\tbool supported;\n\tbool low_rates;\n};\n\nstruct drm_scdc {\n\tbool supported;\n\tbool read_request;\n\tstruct drm_scrambling scrambling;\n};\n\nstruct drm_hdmi_info {\n\tstruct drm_scdc scdc;\n\tlong unsigned int y420_vdb_modes[4];\n\tlong unsigned int y420_cmdb_modes[4];\n\tu64 y420_cmdb_map;\n\tu8 y420_dc_modes;\n};\n\nenum drm_link_status {\n\tDRM_LINK_STATUS_GOOD = 0,\n\tDRM_LINK_STATUS_BAD = 1,\n};\n\nstruct drm_monitor_range_info {\n\tu8 min_vfreq;\n\tu8 max_vfreq;\n};\n\nstruct drm_display_info {\n\tunsigned int width_mm;\n\tunsigned int height_mm;\n\tunsigned int bpc;\n\tenum subpixel_order subpixel_order;\n\tint panel_orientation;\n\tu32 color_formats;\n\tconst u32 *bus_formats;\n\tunsigned int num_bus_formats;\n\tu32 bus_flags;\n\tint max_tmds_clock;\n\tbool dvi_dual;\n\tbool is_hdmi;\n\tbool has_hdmi_infoframe;\n\tbool rgb_quant_range_selectable;\n\tu8 edid_hdmi_dc_modes;\n\tu8 cea_rev;\n\tstruct drm_hdmi_info hdmi;\n\tbool non_desktop;\n\tstruct drm_monitor_range_info monitor_range;\n};\n\nstruct drm_connector_tv_margins {\n\tunsigned int bottom;\n\tunsigned int left;\n\tunsigned int right;\n\tunsigned int top;\n};\n\nstruct drm_tv_connector_state {\n\tenum drm_mode_subconnector subconnector;\n\tstruct drm_connector_tv_margins margins;\n\tunsigned int mode;\n\tunsigned int brightness;\n\tunsigned int contrast;\n\tunsigned int flicker_reduction;\n\tunsigned int overscan;\n\tunsigned int saturation;\n\tunsigned int hue;\n};\n\nstruct drm_connector;\n\nstruct drm_crtc;\n\nstruct drm_encoder;\n\nstruct drm_crtc_commit;\n\nstruct drm_writeback_job;\n\nstruct drm_property_blob;\n\nstruct drm_connector_state {\n\tstruct drm_connector *connector;\n\tstruct drm_crtc *crtc;\n\tstruct drm_encoder *best_encoder;\n\tenum drm_link_status link_status;\n\tstruct drm_atomic_state *state;\n\tstruct drm_crtc_commit *commit;\n\tstruct drm_tv_connector_state tv;\n\tbool self_refresh_aware;\n\tenum hdmi_picture_aspect picture_aspect_ratio;\n\tunsigned int content_type;\n\tunsigned int hdcp_content_type;\n\tunsigned int scaling_mode;\n\tunsigned int content_protection;\n\tu32 colorspace;\n\tstruct drm_writeback_job *writeback_job;\n\tu8 max_requested_bpc;\n\tu8 max_bpc;\n\tstruct drm_property_blob *hdr_output_metadata;\n};\n\nstruct drm_cmdline_mode {\n\tchar name[32];\n\tbool specified;\n\tbool refresh_specified;\n\tbool bpp_specified;\n\tint xres;\n\tint yres;\n\tint bpp;\n\tint refresh;\n\tbool rb;\n\tbool interlace;\n\tbool cvt;\n\tbool margins;\n\tenum drm_connector_force force;\n\tunsigned int rotation_reflection;\n\tenum drm_panel_orientation panel_orientation;\n\tstruct drm_connector_tv_margins tv_margins;\n};\n\nstruct drm_connector_funcs;\n\nstruct drm_connector_helper_funcs;\n\nstruct drm_tile_group;\n\nstruct drm_connector {\n\tstruct drm_device *dev;\n\tstruct device *kdev;\n\tstruct device_attribute *attr;\n\tstruct list_head head;\n\tstruct drm_mode_object base;\n\tchar *name;\n\tstruct mutex mutex;\n\tunsigned int index;\n\tint connector_type;\n\tint connector_type_id;\n\tbool interlace_allowed;\n\tbool doublescan_allowed;\n\tbool stereo_allowed;\n\tbool ycbcr_420_allowed;\n\tenum drm_connector_registration_state registration_state;\n\tstruct list_head modes;\n\tenum drm_connector_status status;\n\tstruct list_head probed_modes;\n\tstruct drm_display_info display_info;\n\tconst struct drm_connector_funcs *funcs;\n\tstruct drm_property_blob *edid_blob_ptr;\n\tstruct drm_object_properties properties;\n\tstruct drm_property *scaling_mode_property;\n\tstruct drm_property *vrr_capable_property;\n\tstruct drm_property *colorspace_property;\n\tstruct drm_property_blob *path_blob_ptr;\n\tstruct drm_property *max_bpc_property;\n\tuint8_t polled;\n\tint dpms;\n\tconst struct drm_connector_helper_funcs *helper_private;\n\tstruct drm_cmdline_mode cmdline_mode;\n\tenum drm_connector_force force;\n\tbool override_edid;\n\tu32 possible_encoders;\n\tstruct drm_encoder *encoder;\n\tuint8_t eld[128];\n\tbool latency_present[2];\n\tint video_latency[2];\n\tint audio_latency[2];\n\tstruct i2c_adapter *ddc;\n\tint null_edid_counter;\n\tunsigned int bad_edid_counter;\n\tbool edid_corrupt;\n\tu8 real_edid_checksum;\n\tstruct dentry *debugfs_entry;\n\tstruct drm_connector_state *state;\n\tstruct drm_property_blob *tile_blob_ptr;\n\tbool has_tile;\n\tstruct drm_tile_group *tile_group;\n\tbool tile_is_single_monitor;\n\tuint8_t num_h_tile;\n\tuint8_t num_v_tile;\n\tuint8_t tile_h_loc;\n\tuint8_t tile_v_loc;\n\tuint16_t tile_h_size;\n\tuint16_t tile_v_size;\n\tstruct llist_node free_node;\n\tstruct hdr_sink_metadata hdr_sink_metadata;\n};\n\nenum drm_mode_status {\n\tMODE_OK = 0,\n\tMODE_HSYNC = 1,\n\tMODE_VSYNC = 2,\n\tMODE_H_ILLEGAL = 3,\n\tMODE_V_ILLEGAL = 4,\n\tMODE_BAD_WIDTH = 5,\n\tMODE_NOMODE = 6,\n\tMODE_NO_INTERLACE = 7,\n\tMODE_NO_DBLESCAN = 8,\n\tMODE_NO_VSCAN = 9,\n\tMODE_MEM = 10,\n\tMODE_VIRTUAL_X = 11,\n\tMODE_VIRTUAL_Y = 12,\n\tMODE_MEM_VIRT = 13,\n\tMODE_NOCLOCK = 14,\n\tMODE_CLOCK_HIGH = 15,\n\tMODE_CLOCK_LOW = 16,\n\tMODE_CLOCK_RANGE = 17,\n\tMODE_BAD_HVALUE = 18,\n\tMODE_BAD_VVALUE = 19,\n\tMODE_BAD_VSCAN = 20,\n\tMODE_HSYNC_NARROW = 21,\n\tMODE_HSYNC_WIDE = 22,\n\tMODE_HBLANK_NARROW = 23,\n\tMODE_HBLANK_WIDE = 24,\n\tMODE_VSYNC_NARROW = 25,\n\tMODE_VSYNC_WIDE = 26,\n\tMODE_VBLANK_NARROW = 27,\n\tMODE_VBLANK_WIDE = 28,\n\tMODE_PANEL = 29,\n\tMODE_INTERLACE_WIDTH = 30,\n\tMODE_ONE_WIDTH = 31,\n\tMODE_ONE_HEIGHT = 32,\n\tMODE_ONE_SIZE = 33,\n\tMODE_NO_REDUCED = 34,\n\tMODE_NO_STEREO = 35,\n\tMODE_NO_420 = 36,\n\tMODE_STALE = 4294967293,\n\tMODE_BAD = 4294967294,\n\tMODE_ERROR = 4294967295,\n};\n\nstruct drm_display_mode {\n\tstruct list_head head;\n\tchar name[32];\n\tenum drm_mode_status status;\n\tunsigned int type;\n\tint clock;\n\tint hdisplay;\n\tint hsync_start;\n\tint hsync_end;\n\tint htotal;\n\tint hskew;\n\tint vdisplay;\n\tint vsync_start;\n\tint vsync_end;\n\tint vtotal;\n\tint vscan;\n\tunsigned int flags;\n\tint width_mm;\n\tint height_mm;\n\tint crtc_clock;\n\tint crtc_hdisplay;\n\tint crtc_hblank_start;\n\tint crtc_hblank_end;\n\tint crtc_hsync_start;\n\tint crtc_hsync_end;\n\tint crtc_htotal;\n\tint crtc_hskew;\n\tint crtc_vdisplay;\n\tint crtc_vblank_start;\n\tint crtc_vblank_end;\n\tint crtc_vsync_start;\n\tint crtc_vsync_end;\n\tint crtc_vtotal;\n\tint private_flags;\n\tint vrefresh;\n\tenum hdmi_picture_aspect picture_aspect_ratio;\n\tstruct list_head export_head;\n};\n\nstruct drm_crtc_crc_entry;\n\nstruct drm_crtc_crc {\n\tspinlock_t lock;\n\tconst char *source;\n\tbool opened;\n\tbool overflow;\n\tstruct drm_crtc_crc_entry *entries;\n\tint head;\n\tint tail;\n\tsize_t values_cnt;\n\twait_queue_head_t wq;\n};\n\nstruct drm_plane;\n\nstruct drm_crtc_funcs;\n\nstruct drm_crtc_helper_funcs;\n\nstruct drm_crtc_state;\n\nstruct drm_self_refresh_data;\n\nstruct drm_crtc {\n\tstruct drm_device *dev;\n\tstruct device_node *port;\n\tstruct list_head head;\n\tchar *name;\n\tstruct drm_modeset_lock mutex;\n\tstruct drm_mode_object base;\n\tstruct drm_plane *primary;\n\tstruct drm_plane *cursor;\n\tunsigned int index;\n\tint cursor_x;\n\tint cursor_y;\n\tbool enabled;\n\tstruct drm_display_mode mode;\n\tstruct drm_display_mode hwmode;\n\tint x;\n\tint y;\n\tconst struct drm_crtc_funcs *funcs;\n\tuint32_t gamma_size;\n\tuint16_t *gamma_store;\n\tconst struct drm_crtc_helper_funcs *helper_private;\n\tstruct drm_object_properties properties;\n\tstruct drm_crtc_state *state;\n\tstruct list_head commit_list;\n\tspinlock_t commit_lock;\n\tstruct dentry *debugfs_entry;\n\tstruct drm_crtc_crc crc;\n\tunsigned int fence_context;\n\tspinlock_t fence_lock;\n\tlong unsigned int fence_seqno;\n\tchar timeline_name[32];\n\tstruct drm_self_refresh_data *self_refresh_data;\n};\n\nstruct drm_encoder_funcs;\n\nstruct drm_encoder_helper_funcs;\n\nstruct drm_encoder {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tstruct drm_mode_object base;\n\tchar *name;\n\tint encoder_type;\n\tunsigned int index;\n\tuint32_t possible_crtcs;\n\tuint32_t possible_clones;\n\tstruct drm_crtc *crtc;\n\tstruct list_head bridge_chain;\n\tconst struct drm_encoder_funcs *funcs;\n\tconst struct drm_encoder_helper_funcs *helper_private;\n};\n\nstruct __drm_planes_state;\n\nstruct __drm_crtcs_state;\n\nstruct __drm_connnectors_state;\n\nstruct __drm_private_objs_state;\n\nstruct drm_atomic_state {\n\tstruct kref ref;\n\tstruct drm_device *dev;\n\tbool allow_modeset: 1;\n\tbool legacy_cursor_update: 1;\n\tbool async_update: 1;\n\tbool duplicated: 1;\n\tstruct __drm_planes_state *planes;\n\tstruct __drm_crtcs_state *crtcs;\n\tint num_connector;\n\tstruct __drm_connnectors_state *connectors;\n\tint num_private_objs;\n\tstruct __drm_private_objs_state *private_objs;\n\tstruct drm_modeset_acquire_ctx *acquire_ctx;\n\tstruct drm_crtc_commit *fake_commit;\n\tstruct work_struct commit_work;\n};\n\nstruct drm_pending_vblank_event;\n\nstruct drm_crtc_commit {\n\tstruct drm_crtc *crtc;\n\tstruct kref ref;\n\tstruct completion flip_done;\n\tstruct completion hw_done;\n\tstruct completion cleanup_done;\n\tstruct list_head commit_entry;\n\tstruct drm_pending_vblank_event *event;\n\tbool abort_completion;\n};\n\nstruct drm_property_blob {\n\tstruct drm_mode_object base;\n\tstruct drm_device *dev;\n\tstruct list_head head_global;\n\tstruct list_head head_file;\n\tsize_t length;\n\tvoid *data;\n};\n\nstruct drm_printer;\n\nstruct drm_connector_funcs {\n\tint (*dpms)(struct drm_connector *, int);\n\tvoid (*reset)(struct drm_connector *);\n\tenum drm_connector_status (*detect)(struct drm_connector *, bool);\n\tvoid (*force)(struct drm_connector *);\n\tint (*fill_modes)(struct drm_connector *, uint32_t, uint32_t);\n\tint (*set_property)(struct drm_connector *, struct drm_property *, uint64_t);\n\tint (*late_register)(struct drm_connector *);\n\tvoid (*early_unregister)(struct drm_connector *);\n\tvoid (*destroy)(struct drm_connector *);\n\tstruct drm_connector_state * (*atomic_duplicate_state)(struct drm_connector *);\n\tvoid (*atomic_destroy_state)(struct drm_connector *, struct drm_connector_state *);\n\tint (*atomic_set_property)(struct drm_connector *, struct drm_connector_state *, struct drm_property *, uint64_t);\n\tint (*atomic_get_property)(struct drm_connector *, const struct drm_connector_state *, struct drm_property *, uint64_t *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_connector_state *);\n};\n\nstruct drm_writeback_connector;\n\nstruct drm_connector_helper_funcs {\n\tint (*get_modes)(struct drm_connector *);\n\tint (*detect_ctx)(struct drm_connector *, struct drm_modeset_acquire_ctx *, bool);\n\tenum drm_mode_status (*mode_valid)(struct drm_connector *, struct drm_display_mode *);\n\tstruct drm_encoder * (*best_encoder)(struct drm_connector *);\n\tstruct drm_encoder * (*atomic_best_encoder)(struct drm_connector *, struct drm_connector_state *);\n\tint (*atomic_check)(struct drm_connector *, struct drm_atomic_state *);\n\tvoid (*atomic_commit)(struct drm_connector *, struct drm_connector_state *);\n\tint (*prepare_writeback_job)(struct drm_writeback_connector *, struct drm_writeback_job *);\n\tvoid (*cleanup_writeback_job)(struct drm_writeback_connector *, struct drm_writeback_job *);\n};\n\nstruct drm_tile_group {\n\tstruct kref refcount;\n\tstruct drm_device *dev;\n\tint id;\n\tu8 group_data[8];\n};\n\nstruct drm_mode_config_funcs {\n\tstruct drm_framebuffer * (*fb_create)(struct drm_device *, struct drm_file *, const struct drm_mode_fb_cmd2 *);\n\tconst struct drm_format_info * (*get_format_info)(const struct drm_mode_fb_cmd2 *);\n\tvoid (*output_poll_changed)(struct drm_device *);\n\tenum drm_mode_status (*mode_valid)(struct drm_device *, const struct drm_display_mode *);\n\tint (*atomic_check)(struct drm_device *, struct drm_atomic_state *);\n\tint (*atomic_commit)(struct drm_device *, struct drm_atomic_state *, bool);\n\tstruct drm_atomic_state * (*atomic_state_alloc)(struct drm_device *);\n\tvoid (*atomic_state_clear)(struct drm_atomic_state *);\n\tvoid (*atomic_state_free)(struct drm_atomic_state *);\n};\n\nstruct drm_mode_config_helper_funcs {\n\tvoid (*atomic_commit_tail)(struct drm_atomic_state *);\n};\n\nstruct est_timings {\n\tu8 t1;\n\tu8 t2;\n\tu8 mfg_rsvd;\n};\n\nstruct std_timing {\n\tu8 hsize;\n\tu8 vfreq_aspect;\n};\n\nstruct detailed_pixel_timing {\n\tu8 hactive_lo;\n\tu8 hblank_lo;\n\tu8 hactive_hblank_hi;\n\tu8 vactive_lo;\n\tu8 vblank_lo;\n\tu8 vactive_vblank_hi;\n\tu8 hsync_offset_lo;\n\tu8 hsync_pulse_width_lo;\n\tu8 vsync_offset_pulse_width_lo;\n\tu8 hsync_vsync_offset_pulse_width_hi;\n\tu8 width_mm_lo;\n\tu8 height_mm_lo;\n\tu8 width_height_mm_hi;\n\tu8 hborder;\n\tu8 vborder;\n\tu8 misc;\n};\n\nstruct detailed_data_string {\n\tu8 str[13];\n};\n\nstruct detailed_data_monitor_range {\n\tu8 min_vfreq;\n\tu8 max_vfreq;\n\tu8 min_hfreq_khz;\n\tu8 max_hfreq_khz;\n\tu8 pixel_clock_mhz;\n\tu8 flags;\n\tunion {\n\t\tstruct {\n\t\t\tu8 reserved;\n\t\t\tu8 hfreq_start_khz;\n\t\t\tu8 c;\n\t\t\t__le16 m;\n\t\t\tu8 k;\n\t\t\tu8 j;\n\t\t} __attribute__((packed)) gtf2;\n\t\tstruct {\n\t\t\tu8 version;\n\t\t\tu8 data1;\n\t\t\tu8 data2;\n\t\t\tu8 supported_aspects;\n\t\t\tu8 flags;\n\t\t\tu8 supported_scalings;\n\t\t\tu8 preferred_refresh;\n\t\t} cvt;\n\t} formula;\n} __attribute__((packed));\n\nstruct detailed_data_wpindex {\n\tu8 white_yx_lo;\n\tu8 white_x_hi;\n\tu8 white_y_hi;\n\tu8 gamma;\n};\n\nstruct cvt_timing {\n\tu8 code[3];\n};\n\nstruct detailed_non_pixel {\n\tu8 pad1;\n\tu8 type;\n\tu8 pad2;\n\tunion {\n\t\tstruct detailed_data_string str;\n\t\tstruct detailed_data_monitor_range range;\n\t\tstruct detailed_data_wpindex color;\n\t\tstruct std_timing timings[6];\n\t\tstruct cvt_timing cvt[4];\n\t} data;\n} __attribute__((packed));\n\nstruct detailed_timing {\n\t__le16 pixel_clock;\n\tunion {\n\t\tstruct detailed_pixel_timing pixel_data;\n\t\tstruct detailed_non_pixel other_data;\n\t} data;\n};\n\nstruct edid {\n\tu8 header[8];\n\tu8 mfg_id[2];\n\tu8 prod_code[2];\n\tu32 serial;\n\tu8 mfg_week;\n\tu8 mfg_year;\n\tu8 version;\n\tu8 revision;\n\tu8 input;\n\tu8 width_cm;\n\tu8 height_cm;\n\tu8 gamma;\n\tu8 features;\n\tu8 red_green_lo;\n\tu8 black_white_lo;\n\tu8 red_x;\n\tu8 red_y;\n\tu8 green_x;\n\tu8 green_y;\n\tu8 blue_x;\n\tu8 blue_y;\n\tu8 white_x;\n\tu8 white_y;\n\tstruct est_timings established_timings;\n\tstruct std_timing standard_timings[8];\n\tstruct detailed_timing detailed_timings[4];\n\tu8 extensions;\n\tu8 checksum;\n};\n\nenum drm_color_encoding {\n\tDRM_COLOR_YCBCR_BT601 = 0,\n\tDRM_COLOR_YCBCR_BT709 = 1,\n\tDRM_COLOR_YCBCR_BT2020 = 2,\n\tDRM_COLOR_ENCODING_MAX = 3,\n};\n\nenum drm_color_range {\n\tDRM_COLOR_YCBCR_LIMITED_RANGE = 0,\n\tDRM_COLOR_YCBCR_FULL_RANGE = 1,\n\tDRM_COLOR_RANGE_MAX = 2,\n};\n\nstruct dma_fence;\n\nstruct drm_plane_state {\n\tstruct drm_plane *plane;\n\tstruct drm_crtc *crtc;\n\tstruct drm_framebuffer *fb;\n\tstruct dma_fence *fence;\n\tint32_t crtc_x;\n\tint32_t crtc_y;\n\tuint32_t crtc_w;\n\tuint32_t crtc_h;\n\tuint32_t src_x;\n\tuint32_t src_y;\n\tuint32_t src_h;\n\tuint32_t src_w;\n\tu16 alpha;\n\tuint16_t pixel_blend_mode;\n\tunsigned int rotation;\n\tunsigned int zpos;\n\tunsigned int normalized_zpos;\n\tenum drm_color_encoding color_encoding;\n\tenum drm_color_range color_range;\n\tstruct drm_property_blob *fb_damage_clips;\n\tstruct drm_rect src;\n\tstruct drm_rect dst;\n\tbool visible;\n\tstruct drm_crtc_commit *commit;\n\tstruct drm_atomic_state *state;\n};\n\nenum drm_plane_type {\n\tDRM_PLANE_TYPE_OVERLAY = 0,\n\tDRM_PLANE_TYPE_PRIMARY = 1,\n\tDRM_PLANE_TYPE_CURSOR = 2,\n};\n\nstruct drm_plane_funcs;\n\nstruct drm_plane_helper_funcs;\n\nstruct drm_plane {\n\tstruct drm_device *dev;\n\tstruct list_head head;\n\tchar *name;\n\tstruct drm_modeset_lock mutex;\n\tstruct drm_mode_object base;\n\tuint32_t possible_crtcs;\n\tuint32_t *format_types;\n\tunsigned int format_count;\n\tbool format_default;\n\tuint64_t *modifiers;\n\tunsigned int modifier_count;\n\tstruct drm_crtc *crtc;\n\tstruct drm_framebuffer *fb;\n\tstruct drm_framebuffer *old_fb;\n\tconst struct drm_plane_funcs *funcs;\n\tstruct drm_object_properties properties;\n\tenum drm_plane_type type;\n\tunsigned int index;\n\tconst struct drm_plane_helper_funcs *helper_private;\n\tstruct drm_plane_state *state;\n\tstruct drm_property *alpha_property;\n\tstruct drm_property *zpos_property;\n\tstruct drm_property *rotation_property;\n\tstruct drm_property *blend_mode_property;\n\tstruct drm_property *color_encoding_property;\n\tstruct drm_property *color_range_property;\n};\n\nstruct drm_plane_funcs {\n\tint (*update_plane)(struct drm_plane *, struct drm_crtc *, struct drm_framebuffer *, int, int, unsigned int, unsigned int, uint32_t, uint32_t, uint32_t, uint32_t, struct drm_modeset_acquire_ctx *);\n\tint (*disable_plane)(struct drm_plane *, struct drm_modeset_acquire_ctx *);\n\tvoid (*destroy)(struct drm_plane *);\n\tvoid (*reset)(struct drm_plane *);\n\tint (*set_property)(struct drm_plane *, struct drm_property *, uint64_t);\n\tstruct drm_plane_state * (*atomic_duplicate_state)(struct drm_plane *);\n\tvoid (*atomic_destroy_state)(struct drm_plane *, struct drm_plane_state *);\n\tint (*atomic_set_property)(struct drm_plane *, struct drm_plane_state *, struct drm_property *, uint64_t);\n\tint (*atomic_get_property)(struct drm_plane *, const struct drm_plane_state *, struct drm_property *, uint64_t *);\n\tint (*late_register)(struct drm_plane *);\n\tvoid (*early_unregister)(struct drm_plane *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_plane_state *);\n\tbool (*format_mod_supported)(struct drm_plane *, uint32_t, uint64_t);\n};\n\nstruct drm_plane_helper_funcs {\n\tint (*prepare_fb)(struct drm_plane *, struct drm_plane_state *);\n\tvoid (*cleanup_fb)(struct drm_plane *, struct drm_plane_state *);\n\tint (*atomic_check)(struct drm_plane *, struct drm_plane_state *);\n\tvoid (*atomic_update)(struct drm_plane *, struct drm_plane_state *);\n\tvoid (*atomic_disable)(struct drm_plane *, struct drm_plane_state *);\n\tint (*atomic_async_check)(struct drm_plane *, struct drm_plane_state *);\n\tvoid (*atomic_async_update)(struct drm_plane *, struct drm_plane_state *);\n};\n\nstruct drm_crtc_crc_entry {\n\tbool has_frame_counter;\n\tuint32_t frame;\n\tuint32_t crcs[10];\n};\n\nstruct drm_crtc_state {\n\tstruct drm_crtc *crtc;\n\tbool enable;\n\tbool active;\n\tbool planes_changed: 1;\n\tbool mode_changed: 1;\n\tbool active_changed: 1;\n\tbool connectors_changed: 1;\n\tbool zpos_changed: 1;\n\tbool color_mgmt_changed: 1;\n\tbool no_vblank: 1;\n\tu32 plane_mask;\n\tu32 connector_mask;\n\tu32 encoder_mask;\n\tstruct drm_display_mode adjusted_mode;\n\tstruct drm_display_mode mode;\n\tstruct drm_property_blob *mode_blob;\n\tstruct drm_property_blob *degamma_lut;\n\tstruct drm_property_blob *ctm;\n\tstruct drm_property_blob *gamma_lut;\n\tu32 target_vblank;\n\tbool async_flip;\n\tbool vrr_enabled;\n\tbool self_refresh_active;\n\tstruct drm_pending_vblank_event *event;\n\tstruct drm_crtc_commit *commit;\n\tstruct drm_atomic_state *state;\n};\n\nstruct drm_mode_set;\n\nstruct drm_crtc_funcs {\n\tvoid (*reset)(struct drm_crtc *);\n\tint (*cursor_set)(struct drm_crtc *, struct drm_file *, uint32_t, uint32_t, uint32_t);\n\tint (*cursor_set2)(struct drm_crtc *, struct drm_file *, uint32_t, uint32_t, uint32_t, int32_t, int32_t);\n\tint (*cursor_move)(struct drm_crtc *, int, int);\n\tint (*gamma_set)(struct drm_crtc *, u16 *, u16 *, u16 *, uint32_t, struct drm_modeset_acquire_ctx *);\n\tvoid (*destroy)(struct drm_crtc *);\n\tint (*set_config)(struct drm_mode_set *, struct drm_modeset_acquire_ctx *);\n\tint (*page_flip)(struct drm_crtc *, struct drm_framebuffer *, struct drm_pending_vblank_event *, uint32_t, struct drm_modeset_acquire_ctx *);\n\tint (*page_flip_target)(struct drm_crtc *, struct drm_framebuffer *, struct drm_pending_vblank_event *, uint32_t, uint32_t, struct drm_modeset_acquire_ctx *);\n\tint (*set_property)(struct drm_crtc *, struct drm_property *, uint64_t);\n\tstruct drm_crtc_state * (*atomic_duplicate_state)(struct drm_crtc *);\n\tvoid (*atomic_destroy_state)(struct drm_crtc *, struct drm_crtc_state *);\n\tint (*atomic_set_property)(struct drm_crtc *, struct drm_crtc_state *, struct drm_property *, uint64_t);\n\tint (*atomic_get_property)(struct drm_crtc *, const struct drm_crtc_state *, struct drm_property *, uint64_t *);\n\tint (*late_register)(struct drm_crtc *);\n\tvoid (*early_unregister)(struct drm_crtc *);\n\tint (*set_crc_source)(struct drm_crtc *, const char *);\n\tint (*verify_crc_source)(struct drm_crtc *, const char *, size_t *);\n\tconst char * const * (*get_crc_sources)(struct drm_crtc *, size_t *);\n\tvoid (*atomic_print_state)(struct drm_printer *, const struct drm_crtc_state *);\n\tu32 (*get_vblank_counter)(struct drm_crtc *);\n\tint (*enable_vblank)(struct drm_crtc *);\n\tvoid (*disable_vblank)(struct drm_crtc *);\n\tbool (*get_vblank_timestamp)(struct drm_crtc *, int *, ktime_t *, bool);\n};\n\nstruct drm_mode_set {\n\tstruct drm_framebuffer *fb;\n\tstruct drm_crtc *crtc;\n\tstruct drm_display_mode *mode;\n\tuint32_t x;\n\tuint32_t y;\n\tstruct drm_connector **connectors;\n\tsize_t num_connectors;\n};\n\nenum mode_set_atomic {\n\tLEAVE_ATOMIC_MODE_SET = 0,\n\tENTER_ATOMIC_MODE_SET = 1,\n};\n\nstruct drm_crtc_helper_funcs {\n\tvoid (*dpms)(struct drm_crtc *, int);\n\tvoid (*prepare)(struct drm_crtc *);\n\tvoid (*commit)(struct drm_crtc *);\n\tenum drm_mode_status (*mode_valid)(struct drm_crtc *, const struct drm_display_mode *);\n\tbool (*mode_fixup)(struct drm_crtc *, const struct drm_display_mode *, struct drm_display_mode *);\n\tint (*mode_set)(struct drm_crtc *, struct drm_display_mode *, struct drm_display_mode *, int, int, struct drm_framebuffer *);\n\tvoid (*mode_set_nofb)(struct drm_crtc *);\n\tint (*mode_set_base)(struct drm_crtc *, int, int, struct drm_framebuffer *);\n\tint (*mode_set_base_atomic)(struct drm_crtc *, struct drm_framebuffer *, int, int, enum mode_set_atomic);\n\tvoid (*disable)(struct drm_crtc *);\n\tint (*atomic_check)(struct drm_crtc *, struct drm_crtc_state *);\n\tvoid (*atomic_begin)(struct drm_crtc *, struct drm_crtc_state *);\n\tvoid (*atomic_flush)(struct drm_crtc *, struct drm_crtc_state *);\n\tvoid (*atomic_enable)(struct drm_crtc *, struct drm_crtc_state *);\n\tvoid (*atomic_disable)(struct drm_crtc *, struct drm_crtc_state *);\n\tbool (*get_scanout_position)(struct drm_crtc *, bool, int *, int *, ktime_t *, ktime_t *, const struct drm_display_mode *);\n};\n\nstruct __drm_planes_state {\n\tstruct drm_plane *ptr;\n\tstruct drm_plane_state *state;\n\tstruct drm_plane_state *old_state;\n\tstruct drm_plane_state *new_state;\n};\n\nstruct __drm_crtcs_state {\n\tstruct drm_crtc *ptr;\n\tstruct drm_crtc_state *state;\n\tstruct drm_crtc_state *old_state;\n\tstruct drm_crtc_state *new_state;\n\tstruct drm_crtc_commit *commit;\n\ts32 *out_fence_ptr;\n\tu64 last_vblank_count;\n};\n\nstruct __drm_connnectors_state {\n\tstruct drm_connector *ptr;\n\tstruct drm_connector_state *state;\n\tstruct drm_connector_state *old_state;\n\tstruct drm_connector_state *new_state;\n\ts32 *out_fence_ptr;\n};\n\nstruct drm_private_state;\n\nstruct drm_private_obj;\n\nstruct drm_private_state_funcs {\n\tstruct drm_private_state * (*atomic_duplicate_state)(struct drm_private_obj *);\n\tvoid (*atomic_destroy_state)(struct drm_private_obj *, struct drm_private_state *);\n};\n\nstruct drm_private_state {\n\tstruct drm_atomic_state *state;\n};\n\nstruct drm_private_obj {\n\tstruct list_head head;\n\tstruct drm_modeset_lock lock;\n\tstruct drm_private_state *state;\n\tconst struct drm_private_state_funcs *funcs;\n};\n\nstruct __drm_private_objs_state {\n\tstruct drm_private_obj *ptr;\n\tstruct drm_private_state *state;\n\tstruct drm_private_state *old_state;\n\tstruct drm_private_state *new_state;\n};\n\nstruct drm_bus_cfg {\n\tu32 format;\n\tu32 flags;\n};\n\nstruct drm_bridge;\n\nstruct drm_bridge_state {\n\tstruct drm_private_state base;\n\tstruct drm_bridge *bridge;\n\tstruct drm_bus_cfg input_bus_cfg;\n\tstruct drm_bus_cfg output_bus_cfg;\n};\n\nenum drm_bridge_ops {\n\tDRM_BRIDGE_OP_DETECT = 1,\n\tDRM_BRIDGE_OP_EDID = 2,\n\tDRM_BRIDGE_OP_HPD = 4,\n\tDRM_BRIDGE_OP_MODES = 8,\n};\n\nstruct drm_bridge_timings;\n\nstruct drm_bridge_funcs;\n\nstruct drm_bridge {\n\tstruct drm_private_obj base;\n\tstruct drm_device *dev;\n\tstruct drm_encoder *encoder;\n\tstruct list_head chain_node;\n\tstruct list_head list;\n\tconst struct drm_bridge_timings *timings;\n\tconst struct drm_bridge_funcs *funcs;\n\tvoid *driver_private;\n\tenum drm_bridge_ops ops;\n\tint type;\n\tbool interlace_allowed;\n\tstruct i2c_adapter *ddc;\n\tstruct mutex hpd_mutex;\n\tvoid (*hpd_cb)(void *, enum drm_connector_status);\n\tvoid *hpd_data;\n};\n\nstruct drm_encoder_funcs {\n\tvoid (*reset)(struct drm_encoder *);\n\tvoid (*destroy)(struct drm_encoder *);\n\tint (*late_register)(struct drm_encoder *);\n\tvoid (*early_unregister)(struct drm_encoder *);\n};\n\nstruct drm_encoder_helper_funcs {\n\tvoid (*dpms)(struct drm_encoder *, int);\n\tenum drm_mode_status (*mode_valid)(struct drm_encoder *, const struct drm_display_mode *);\n\tbool (*mode_fixup)(struct drm_encoder *, const struct drm_display_mode *, struct drm_display_mode *);\n\tvoid (*prepare)(struct drm_encoder *);\n\tvoid (*commit)(struct drm_encoder *);\n\tvoid (*mode_set)(struct drm_encoder *, struct drm_display_mode *, struct drm_display_mode *);\n\tvoid (*atomic_mode_set)(struct drm_encoder *, struct drm_crtc_state *, struct drm_connector_state *);\n\tenum drm_connector_status (*detect)(struct drm_encoder *, struct drm_connector *);\n\tvoid (*atomic_disable)(struct drm_encoder *, struct drm_atomic_state *);\n\tvoid (*atomic_enable)(struct drm_encoder *, struct drm_atomic_state *);\n\tvoid (*disable)(struct drm_encoder *);\n\tvoid (*enable)(struct drm_encoder *);\n\tint (*atomic_check)(struct drm_encoder *, struct drm_crtc_state *, struct drm_connector_state *);\n};\n\nenum drm_bridge_attach_flags {\n\tDRM_BRIDGE_ATTACH_NO_CONNECTOR = 1,\n};\n\nstruct drm_bridge_funcs {\n\tint (*attach)(struct drm_bridge *, enum drm_bridge_attach_flags);\n\tvoid (*detach)(struct drm_bridge *);\n\tenum drm_mode_status (*mode_valid)(struct drm_bridge *, const struct drm_display_mode *);\n\tbool (*mode_fixup)(struct drm_bridge *, const struct drm_display_mode *, struct drm_display_mode *);\n\tvoid (*disable)(struct drm_bridge *);\n\tvoid (*post_disable)(struct drm_bridge *);\n\tvoid (*mode_set)(struct drm_bridge *, const struct drm_display_mode *, const struct drm_display_mode *);\n\tvoid (*pre_enable)(struct drm_bridge *);\n\tvoid (*enable)(struct drm_bridge *);\n\tvoid (*atomic_pre_enable)(struct drm_bridge *, struct drm_bridge_state *);\n\tvoid (*atomic_enable)(struct drm_bridge *, struct drm_bridge_state *);\n\tvoid (*atomic_disable)(struct drm_bridge *, struct drm_bridge_state *);\n\tvoid (*atomic_post_disable)(struct drm_bridge *, struct drm_bridge_state *);\n\tstruct drm_bridge_state * (*atomic_duplicate_state)(struct drm_bridge *);\n\tvoid (*atomic_destroy_state)(struct drm_bridge *, struct drm_bridge_state *);\n\tu32 * (*atomic_get_output_bus_fmts)(struct drm_bridge *, struct drm_bridge_state *, struct drm_crtc_state *, struct drm_connector_state *, unsigned int *);\n\tu32 * (*atomic_get_input_bus_fmts)(struct drm_bridge *, struct drm_bridge_state *, struct drm_crtc_state *, struct drm_connector_state *, u32, unsigned int *);\n\tint (*atomic_check)(struct drm_bridge *, struct drm_bridge_state *, struct drm_crtc_state *, struct drm_connector_state *);\n\tstruct drm_bridge_state * (*atomic_reset)(struct drm_bridge *);\n\tenum drm_connector_status (*detect)(struct drm_bridge *);\n\tint (*get_modes)(struct drm_bridge *, struct drm_connector *);\n\tstruct edid * (*get_edid)(struct drm_bridge *, struct drm_connector *);\n\tvoid (*hpd_notify)(struct drm_bridge *, enum drm_connector_status);\n\tvoid (*hpd_enable)(struct drm_bridge *);\n\tvoid (*hpd_disable)(struct drm_bridge *);\n};\n\nstruct drm_bridge_timings {\n\tu32 input_bus_flags;\n\tu32 setup_time_ps;\n\tu32 hold_time_ps;\n\tbool dual_link;\n};\n\nstruct drm_bridge_connector {\n\tstruct drm_connector base;\n\tstruct drm_encoder *encoder;\n\tstruct drm_bridge *bridge_edid;\n\tstruct drm_bridge *bridge_hpd;\n\tstruct drm_bridge *bridge_detect;\n\tstruct drm_bridge *bridge_modes;\n};\n\ntypedef unsigned int drm_magic_t;\n\nstruct drm_event {\n\t__u32 type;\n\t__u32 length;\n};\n\nstruct drm_event_vblank {\n\tstruct drm_event base;\n\t__u64 user_data;\n\t__u32 tv_sec;\n\t__u32 tv_usec;\n\t__u32 sequence;\n\t__u32 crtc_id;\n};\n\nstruct drm_event_crtc_sequence {\n\tstruct drm_event base;\n\t__u64 user_data;\n\t__s64 time_ns;\n\t__u64 sequence;\n};\n\nstruct drm_mode_create_dumb {\n\t__u32 height;\n\t__u32 width;\n\t__u32 bpp;\n\t__u32 flags;\n\t__u32 handle;\n\t__u32 pitch;\n\t__u64 size;\n};\n\nstruct drm_prime_file_private {\n\tstruct mutex lock;\n\tstruct rb_root dmabufs;\n\tstruct rb_root handles;\n};\n\nstruct drm_file {\n\tbool authenticated;\n\tbool stereo_allowed;\n\tbool universal_planes;\n\tbool atomic;\n\tbool aspect_ratio_allowed;\n\tbool writeback_connectors;\n\tbool was_master;\n\tbool is_master;\n\tstruct drm_master *master;\n\tstruct pid *pid;\n\tdrm_magic_t magic;\n\tstruct list_head lhead;\n\tstruct drm_minor *minor;\n\tstruct idr object_idr;\n\tspinlock_t table_lock;\n\tstruct idr syncobj_idr;\n\tspinlock_t syncobj_table_lock;\n\tstruct file *filp;\n\tvoid *driver_priv;\n\tstruct list_head fbs;\n\tstruct mutex fbs_lock;\n\tstruct list_head blobs;\n\twait_queue_head_t event_wait;\n\tstruct list_head pending_event_list;\n\tstruct list_head event_list;\n\tint event_space;\n\tstruct mutex event_read_lock;\n\tstruct drm_prime_file_private prime;\n};\n\nstruct drm_mm;\n\nstruct drm_mm_node {\n\tlong unsigned int color;\n\tu64 start;\n\tu64 size;\n\tstruct drm_mm *mm;\n\tstruct list_head node_list;\n\tstruct list_head hole_stack;\n\tstruct rb_node rb;\n\tstruct rb_node rb_hole_size;\n\tstruct rb_node rb_hole_addr;\n\tu64 __subtree_last;\n\tu64 hole_size;\n\tu64 subtree_max_hole;\n\tlong unsigned int flags;\n};\n\nstruct drm_vma_offset_node {\n\trwlock_t vm_lock;\n\tstruct drm_mm_node vm_node;\n\tstruct rb_root vm_files;\n\tbool readonly: 1;\n};\n\nstruct dma_resv_list;\n\nstruct dma_resv {\n\tstruct ww_mutex lock;\n\tseqcount_t seq;\n\tstruct dma_fence *fence_excl;\n\tstruct dma_resv_list *fence;\n};\n\nstruct dma_buf;\n\nstruct dma_buf_attachment;\n\nstruct drm_gem_object_funcs;\n\nstruct drm_gem_object {\n\tstruct kref refcount;\n\tunsigned int handle_count;\n\tstruct drm_device *dev;\n\tstruct file *filp;\n\tstruct drm_vma_offset_node vma_node;\n\tsize_t size;\n\tint name;\n\tstruct dma_buf *dma_buf;\n\tstruct dma_buf_attachment *import_attach;\n\tstruct dma_resv *resv;\n\tstruct dma_resv _resv;\n\tconst struct drm_gem_object_funcs *funcs;\n};\n\nstruct drm_printer {\n\tvoid (*printfn)(struct drm_printer *, struct va_format *);\n\tvoid (*puts)(struct drm_printer *, const char *);\n\tvoid *arg;\n\tconst char *prefix;\n};\n\nstruct drm_connector_list_iter {\n\tstruct drm_device *dev;\n\tstruct drm_connector *conn;\n};\n\nstruct drm_ioctl_desc;\n\nstruct drm_driver {\n\tint (*load)(struct drm_device *, long unsigned int);\n\tint (*open)(struct drm_device *, struct drm_file *);\n\tvoid (*postclose)(struct drm_device *, struct drm_file *);\n\tvoid (*lastclose)(struct drm_device *);\n\tvoid (*unload)(struct drm_device *);\n\tvoid (*release)(struct drm_device *);\n\tirqreturn_t (*irq_handler)(int, void *);\n\tvoid (*irq_preinstall)(struct drm_device *);\n\tint (*irq_postinstall)(struct drm_device *);\n\tvoid (*irq_uninstall)(struct drm_device *);\n\tint (*master_set)(struct drm_device *, struct drm_file *, bool);\n\tvoid (*master_drop)(struct drm_device *, struct drm_file *);\n\tvoid (*debugfs_init)(struct drm_minor *);\n\tvoid (*gem_free_object)(struct drm_gem_object *);\n\tvoid (*gem_free_object_unlocked)(struct drm_gem_object *);\n\tint (*gem_open_object)(struct drm_gem_object *, struct drm_file *);\n\tvoid (*gem_close_object)(struct drm_gem_object *, struct drm_file *);\n\tvoid (*gem_print_info)(struct drm_printer *, unsigned int, const struct drm_gem_object *);\n\tstruct drm_gem_object * (*gem_create_object)(struct drm_device *, size_t);\n\tint (*prime_handle_to_fd)(struct drm_device *, struct drm_file *, uint32_t, uint32_t, int *);\n\tint (*prime_fd_to_handle)(struct drm_device *, struct drm_file *, int, uint32_t *);\n\tstruct dma_buf * (*gem_prime_export)(struct drm_gem_object *, int);\n\tstruct drm_gem_object * (*gem_prime_import)(struct drm_device *, struct dma_buf *);\n\tint (*gem_prime_pin)(struct drm_gem_object *);\n\tvoid (*gem_prime_unpin)(struct drm_gem_object *);\n\tstruct sg_table * (*gem_prime_get_sg_table)(struct drm_gem_object *);\n\tstruct drm_gem_object * (*gem_prime_import_sg_table)(struct drm_device *, struct dma_buf_attachment *, struct sg_table *);\n\tvoid * (*gem_prime_vmap)(struct drm_gem_object *);\n\tvoid (*gem_prime_vunmap)(struct drm_gem_object *, void *);\n\tint (*gem_prime_mmap)(struct drm_gem_object *, struct vm_area_struct *);\n\tint (*dumb_create)(struct drm_file *, struct drm_device *, struct drm_mode_create_dumb *);\n\tint (*dumb_map_offset)(struct drm_file *, struct drm_device *, uint32_t, uint64_t *);\n\tint (*dumb_destroy)(struct drm_file *, struct drm_device *, uint32_t);\n\tconst struct vm_operations_struct *gem_vm_ops;\n\tint major;\n\tint minor;\n\tint patchlevel;\n\tchar *name;\n\tchar *desc;\n\tchar *date;\n\tu32 driver_features;\n\tconst struct drm_ioctl_desc *ioctls;\n\tint num_ioctls;\n\tconst struct file_operations *fops;\n\tstruct list_head legacy_dev_list;\n\tint (*firstopen)(struct drm_device *);\n\tvoid (*preclose)(struct drm_device *, struct drm_file *);\n\tint (*dma_ioctl)(struct drm_device *, void *, struct drm_file *);\n\tint (*dma_quiescent)(struct drm_device *);\n\tint (*context_dtor)(struct drm_device *, int);\n\tu32 (*get_vblank_counter)(struct drm_device *, unsigned int);\n\tint (*enable_vblank)(struct drm_device *, unsigned int);\n\tvoid (*disable_vblank)(struct drm_device *, unsigned int);\n\tint dev_priv_size;\n};\n\nstruct drm_minor {\n\tint index;\n\tint type;\n\tstruct device *kdev;\n\tstruct drm_device *dev;\n\tstruct dentry *debugfs_root;\n\tstruct list_head debugfs_list;\n\tstruct mutex debugfs_lock;\n};\n\nstruct drm_vblank_crtc {\n\tstruct drm_device *dev;\n\twait_queue_head_t queue;\n\tstruct timer_list disable_timer;\n\tseqlock_t seqlock;\n\tatomic64_t count;\n\tktime_t time;\n\tatomic_t refcount;\n\tu32 last;\n\tu32 max_vblank_count;\n\tunsigned int inmodeset;\n\tunsigned int pipe;\n\tint framedur_ns;\n\tint linedur_ns;\n\tstruct drm_display_mode hwmode;\n\tbool enabled;\n};\n\nstruct drm_client_funcs;\n\nstruct drm_client_dev {\n\tstruct drm_device *dev;\n\tconst char *name;\n\tstruct list_head list;\n\tconst struct drm_client_funcs *funcs;\n\tstruct drm_file *file;\n\tstruct mutex modeset_mutex;\n\tstruct drm_mode_set *modesets;\n};\n\nstruct drm_client_buffer;\n\nstruct drm_fb_helper_funcs;\n\nstruct drm_fb_helper {\n\tstruct drm_client_dev client;\n\tstruct drm_client_buffer *buffer;\n\tstruct drm_framebuffer *fb;\n\tstruct drm_device *dev;\n\tconst struct drm_fb_helper_funcs *funcs;\n\tstruct fb_info *fbdev;\n\tu32 pseudo_palette[17];\n\tstruct drm_clip_rect dirty_clip;\n\tspinlock_t dirty_lock;\n\tstruct work_struct dirty_work;\n\tstruct work_struct resume_work;\n\tstruct mutex lock;\n\tstruct list_head kernel_fb_list;\n\tbool delayed_hotplug;\n\tbool deferred_setup;\n\tint preferred_bpp;\n};\n\nstruct drm_pending_event {\n\tstruct completion *completion;\n\tvoid (*completion_release)(struct completion *);\n\tstruct drm_event *event;\n\tstruct dma_fence *fence;\n\tstruct drm_file *file_priv;\n\tstruct list_head link;\n\tstruct list_head pending_link;\n};\n\nstruct drm_pending_vblank_event {\n\tstruct drm_pending_event base;\n\tunsigned int pipe;\n\tu64 sequence;\n\tunion {\n\t\tstruct drm_event base;\n\t\tstruct drm_event_vblank vbl;\n\t\tstruct drm_event_crtc_sequence seq;\n\t} event;\n};\n\nenum drm_driver_feature {\n\tDRIVER_GEM = 1,\n\tDRIVER_MODESET = 2,\n\tDRIVER_RENDER = 8,\n\tDRIVER_ATOMIC = 16,\n\tDRIVER_SYNCOBJ = 32,\n\tDRIVER_SYNCOBJ_TIMELINE = 64,\n\tDRIVER_USE_AGP = 33554432,\n\tDRIVER_LEGACY = 67108864,\n\tDRIVER_PCI_DMA = 134217728,\n\tDRIVER_SG = 268435456,\n\tDRIVER_HAVE_DMA = 536870912,\n\tDRIVER_HAVE_IRQ = 1073741824,\n\tDRIVER_KMS_LEGACY_CONTEXT = 2147483648,\n};\n\nenum drm_ioctl_flags {\n\tDRM_AUTH = 1,\n\tDRM_MASTER = 2,\n\tDRM_ROOT_ONLY = 4,\n\tDRM_UNLOCKED = 16,\n\tDRM_RENDER_ALLOW = 32,\n};\n\ntypedef int drm_ioctl_t(struct drm_device *, void *, struct drm_file *);\n\nstruct drm_ioctl_desc {\n\tunsigned int cmd;\n\tenum drm_ioctl_flags flags;\n\tdrm_ioctl_t *func;\n\tconst char *name;\n};\n\nstruct drm_client_funcs {\n\tstruct module *owner;\n\tvoid (*unregister)(struct drm_client_dev *);\n\tint (*restore)(struct drm_client_dev *);\n\tint (*hotplug)(struct drm_client_dev *);\n};\n\nstruct drm_client_buffer {\n\tstruct drm_client_dev *client;\n\tu32 handle;\n\tu32 pitch;\n\tstruct drm_gem_object *gem;\n\tvoid *vaddr;\n\tstruct drm_framebuffer *fb;\n};\n\nstruct drm_fb_helper_surface_size {\n\tu32 fb_width;\n\tu32 fb_height;\n\tu32 surface_width;\n\tu32 surface_height;\n\tu32 surface_bpp;\n\tu32 surface_depth;\n};\n\nstruct drm_fb_helper_funcs {\n\tint (*fb_probe)(struct drm_fb_helper *, struct drm_fb_helper_surface_size *);\n};\n\nenum drm_debug_category {\n\tDRM_UT_CORE = 1,\n\tDRM_UT_DRIVER = 2,\n\tDRM_UT_KMS = 4,\n\tDRM_UT_PRIME = 8,\n\tDRM_UT_ATOMIC = 16,\n\tDRM_UT_VBL = 32,\n\tDRM_UT_STATE = 64,\n\tDRM_UT_LEASE = 128,\n\tDRM_UT_DP = 256,\n\tDRM_UT_DRMRES = 512,\n};\n\nenum dp_pixelformat {\n\tDP_PIXELFORMAT_RGB = 0,\n\tDP_PIXELFORMAT_YUV444 = 1,\n\tDP_PIXELFORMAT_YUV422 = 2,\n\tDP_PIXELFORMAT_YUV420 = 3,\n\tDP_PIXELFORMAT_Y_ONLY = 4,\n\tDP_PIXELFORMAT_RAW = 5,\n\tDP_PIXELFORMAT_RESERVED = 6,\n};\n\nenum dp_colorimetry {\n\tDP_COLORIMETRY_DEFAULT = 0,\n\tDP_COLORIMETRY_RGB_WIDE_FIXED = 1,\n\tDP_COLORIMETRY_BT709_YCC = 1,\n\tDP_COLORIMETRY_RGB_WIDE_FLOAT = 2,\n\tDP_COLORIMETRY_XVYCC_601 = 2,\n\tDP_COLORIMETRY_OPRGB = 3,\n\tDP_COLORIMETRY_XVYCC_709 = 3,\n\tDP_COLORIMETRY_DCI_P3_RGB = 4,\n\tDP_COLORIMETRY_SYCC_601 = 4,\n\tDP_COLORIMETRY_RGB_CUSTOM = 5,\n\tDP_COLORIMETRY_OPYCC_601 = 5,\n\tDP_COLORIMETRY_BT2020_RGB = 6,\n\tDP_COLORIMETRY_BT2020_CYCC = 6,\n\tDP_COLORIMETRY_BT2020_YCC = 7,\n};\n\nenum dp_dynamic_range {\n\tDP_DYNAMIC_RANGE_VESA = 0,\n\tDP_DYNAMIC_RANGE_CTA = 1,\n};\n\nenum dp_content_type {\n\tDP_CONTENT_TYPE_NOT_DEFINED = 0,\n\tDP_CONTENT_TYPE_GRAPHICS = 1,\n\tDP_CONTENT_TYPE_PHOTO = 2,\n\tDP_CONTENT_TYPE_VIDEO = 3,\n\tDP_CONTENT_TYPE_GAME = 4,\n};\n\nstruct drm_dp_vsc_sdp {\n\tunsigned char sdp_type;\n\tunsigned char revision;\n\tunsigned char length;\n\tenum dp_pixelformat pixelformat;\n\tenum dp_colorimetry colorimetry;\n\tint bpc;\n\tenum dp_dynamic_range dynamic_range;\n\tenum dp_content_type content_type;\n};\n\nstruct drm_dp_aux_msg {\n\tunsigned int address;\n\tu8 request;\n\tu8 reply;\n\tvoid *buffer;\n\tsize_t size;\n};\n\nstruct cec_adapter;\n\nstruct drm_dp_aux_cec {\n\tstruct mutex lock;\n\tstruct cec_adapter *adap;\n\tstruct drm_connector *connector;\n\tstruct delayed_work unregister_work;\n};\n\nstruct drm_dp_aux {\n\tconst char *name;\n\tstruct i2c_adapter ddc;\n\tstruct device *dev;\n\tstruct drm_crtc *crtc;\n\tstruct mutex hw_mutex;\n\tstruct work_struct crc_work;\n\tu8 crc_count;\n\tssize_t (*transfer)(struct drm_dp_aux *, struct drm_dp_aux_msg *);\n\tunsigned int i2c_nack_count;\n\tunsigned int i2c_defer_count;\n\tstruct drm_dp_aux_cec cec;\n\tbool is_remote;\n};\n\nstruct drm_dp_dpcd_ident {\n\tu8 oui[3];\n\tu8 device_id[6];\n\tu8 hw_rev;\n\tu8 sw_major_rev;\n\tu8 sw_minor_rev;\n};\n\nstruct drm_dp_desc {\n\tstruct drm_dp_dpcd_ident ident;\n\tu32 quirks;\n};\n\nenum drm_dp_quirk {\n\tDP_DPCD_QUIRK_CONSTANT_N = 0,\n\tDP_DPCD_QUIRK_NO_PSR = 1,\n\tDP_DPCD_QUIRK_NO_SINK_COUNT = 2,\n\tDP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD = 3,\n\tDP_QUIRK_FORCE_DPCD_BACKLIGHT = 4,\n\tDP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS = 5,\n};\n\nstruct drm_dp_phy_test_params {\n\tint link_rate;\n\tu8 num_lanes;\n\tu8 phy_pattern;\n\tu8 hbr2_reset[2];\n\tu8 custom80[10];\n\tbool enhanced_frame_cap;\n};\n\nstruct dpcd_quirk {\n\tu8 oui[3];\n\tu8 device_id[6];\n\tbool is_branch;\n\tu32 quirks;\n};\n\nstruct edid_quirk {\n\tu8 mfg_id[2];\n\tu8 prod_id[2];\n\tu32 quirks;\n};\n\nstruct dp_sdp_header {\n\tu8 HB0;\n\tu8 HB1;\n\tu8 HB2;\n\tu8 HB3;\n};\n\nstruct drm_dsc_rc_range_parameters {\n\tu8 range_min_qp;\n\tu8 range_max_qp;\n\tu8 range_bpg_offset;\n};\n\nstruct drm_dsc_config {\n\tu8 line_buf_depth;\n\tu8 bits_per_component;\n\tbool convert_rgb;\n\tu8 slice_count;\n\tu16 slice_width;\n\tu16 slice_height;\n\tbool simple_422;\n\tu16 pic_width;\n\tu16 pic_height;\n\tu8 rc_tgt_offset_high;\n\tu8 rc_tgt_offset_low;\n\tu16 bits_per_pixel;\n\tu8 rc_edge_factor;\n\tu8 rc_quant_incr_limit1;\n\tu8 rc_quant_incr_limit0;\n\tu16 initial_xmit_delay;\n\tu16 initial_dec_delay;\n\tbool block_pred_enable;\n\tu8 first_line_bpg_offset;\n\tu16 initial_offset;\n\tu16 rc_buf_thresh[14];\n\tstruct drm_dsc_rc_range_parameters rc_range_params[15];\n\tu16 rc_model_size;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\tu8 initial_scale_value;\n\tu16 scale_decrement_interval;\n\tu16 scale_increment_interval;\n\tu16 nfl_bpg_offset;\n\tu16 slice_bpg_offset;\n\tu16 final_offset;\n\tbool vbr_enable;\n\tu8 mux_word_size;\n\tu16 slice_chunk_size;\n\tu16 rc_bits;\n\tu8 dsc_version_minor;\n\tu8 dsc_version_major;\n\tbool native_422;\n\tbool native_420;\n\tu8 second_line_bpg_offset;\n\tu16 nsl_bpg_offset;\n\tu16 second_line_offset_adj;\n};\n\nstruct drm_dsc_picture_parameter_set {\n\tu8 dsc_version;\n\tu8 pps_identifier;\n\tu8 pps_reserved;\n\tu8 pps_3;\n\tu8 pps_4;\n\tu8 bits_per_pixel_low;\n\t__be16 pic_height;\n\t__be16 pic_width;\n\t__be16 slice_height;\n\t__be16 slice_width;\n\t__be16 chunk_size;\n\tu8 initial_xmit_delay_high;\n\tu8 initial_xmit_delay_low;\n\t__be16 initial_dec_delay;\n\tu8 pps20_reserved;\n\tu8 initial_scale_value;\n\t__be16 scale_increment_interval;\n\tu8 scale_decrement_interval_high;\n\tu8 scale_decrement_interval_low;\n\tu8 pps26_reserved;\n\tu8 first_line_bpg_offset;\n\t__be16 nfl_bpg_offset;\n\t__be16 slice_bpg_offset;\n\t__be16 initial_offset;\n\t__be16 final_offset;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\t__be16 rc_model_size;\n\tu8 rc_edge_factor;\n\tu8 rc_quant_incr_limit0;\n\tu8 rc_quant_incr_limit1;\n\tu8 rc_tgt_offset;\n\tu8 rc_buf_thresh[14];\n\t__be16 rc_range_parameters[15];\n\tu8 native_422_420;\n\tu8 second_line_bpg_offset;\n\t__be16 nsl_bpg_offset;\n\t__be16 second_line_offset_adj;\n\tu32 pps_long_94_reserved;\n\tu32 pps_long_98_reserved;\n\tu32 pps_long_102_reserved;\n\tu32 pps_long_106_reserved;\n\tu32 pps_long_110_reserved;\n\tu32 pps_long_114_reserved;\n\tu32 pps_long_118_reserved;\n\tu32 pps_long_122_reserved;\n\t__be16 pps_short_126_reserved;\n} __attribute__((packed));\n\nstruct drm_dp_vcpi {\n\tint vcpi;\n\tint pbn;\n\tint aligned_pbn;\n\tint num_slots;\n};\n\nstruct drm_dp_mst_branch;\n\nstruct drm_dp_mst_topology_mgr;\n\nstruct drm_dp_mst_port {\n\tstruct kref topology_kref;\n\tstruct kref malloc_kref;\n\tu8 port_num;\n\tbool input;\n\tbool mcs;\n\tbool ddps;\n\tu8 pdt;\n\tbool ldps;\n\tu8 dpcd_rev;\n\tu8 num_sdp_streams;\n\tu8 num_sdp_stream_sinks;\n\tuint16_t full_pbn;\n\tstruct list_head next;\n\tstruct drm_dp_mst_branch *mstb;\n\tstruct drm_dp_aux aux;\n\tstruct drm_dp_mst_branch *parent;\n\tstruct drm_dp_vcpi vcpi;\n\tstruct drm_connector *connector;\n\tstruct drm_dp_mst_topology_mgr *mgr;\n\tstruct edid *cached_edid;\n\tbool has_audio;\n\tbool fec_capable;\n};\n\nstruct drm_dp_mst_branch {\n\tstruct kref topology_kref;\n\tstruct kref malloc_kref;\n\tstruct list_head destroy_next;\n\tu8 rad[8];\n\tu8 lct;\n\tint num_ports;\n\tstruct list_head ports;\n\tstruct drm_dp_mst_port *port_parent;\n\tstruct drm_dp_mst_topology_mgr *mgr;\n\tbool link_address_sent;\n\tu8 guid[16];\n};\n\nstruct drm_dp_sideband_msg_hdr {\n\tu8 lct;\n\tu8 lcr;\n\tu8 rad[8];\n\tbool broadcast;\n\tbool path_msg;\n\tu8 msg_len;\n\tbool somt;\n\tbool eomt;\n\tbool seqno;\n};\n\nstruct drm_dp_sideband_msg_rx {\n\tu8 chunk[48];\n\tu8 msg[256];\n\tu8 curchunk_len;\n\tu8 curchunk_idx;\n\tu8 curchunk_hdrlen;\n\tu8 curlen;\n\tbool have_somt;\n\tbool have_eomt;\n\tstruct drm_dp_sideband_msg_hdr initial_hdr;\n};\n\nstruct drm_dp_mst_topology_cbs;\n\nstruct drm_dp_payload;\n\nstruct drm_dp_mst_topology_mgr {\n\tstruct drm_private_obj base;\n\tstruct drm_device *dev;\n\tconst struct drm_dp_mst_topology_cbs *cbs;\n\tint max_dpcd_transaction_bytes;\n\tstruct drm_dp_aux *aux;\n\tint max_payloads;\n\tint conn_base_id;\n\tstruct drm_dp_sideband_msg_rx up_req_recv;\n\tstruct drm_dp_sideband_msg_rx down_rep_recv;\n\tstruct mutex lock;\n\tstruct mutex probe_lock;\n\tbool mst_state: 1;\n\tbool payload_id_table_cleared: 1;\n\tstruct drm_dp_mst_branch *mst_primary;\n\tu8 dpcd[15];\n\tu8 sink_count;\n\tint pbn_div;\n\tconst struct drm_private_state_funcs *funcs;\n\tstruct mutex qlock;\n\tstruct list_head tx_msg_downq;\n\tstruct mutex payload_lock;\n\tstruct drm_dp_vcpi **proposed_vcpis;\n\tstruct drm_dp_payload *payloads;\n\tlong unsigned int payload_mask;\n\tlong unsigned int vcpi_mask;\n\twait_queue_head_t tx_waitq;\n\tstruct work_struct work;\n\tstruct work_struct tx_work;\n\tstruct list_head destroy_port_list;\n\tstruct list_head destroy_branch_device_list;\n\tstruct mutex delayed_destroy_lock;\n\tstruct work_struct delayed_destroy_work;\n\tstruct list_head up_req_list;\n\tstruct mutex up_req_lock;\n\tstruct work_struct up_req_work;\n};\n\nstruct drm_dp_nak_reply {\n\tu8 guid[16];\n\tu8 reason;\n\tu8 nak_data;\n};\n\nstruct drm_dp_link_addr_reply_port {\n\tbool input_port;\n\tu8 peer_device_type;\n\tu8 port_number;\n\tbool mcs;\n\tbool ddps;\n\tbool legacy_device_plug_status;\n\tu8 dpcd_revision;\n\tu8 peer_guid[16];\n\tu8 num_sdp_streams;\n\tu8 num_sdp_stream_sinks;\n};\n\nstruct drm_dp_link_address_ack_reply {\n\tu8 guid[16];\n\tu8 nports;\n\tstruct drm_dp_link_addr_reply_port ports[16];\n};\n\nstruct drm_dp_remote_dpcd_read_ack_reply {\n\tu8 port_number;\n\tu8 num_bytes;\n\tu8 bytes[255];\n};\n\nstruct drm_dp_remote_dpcd_write_ack_reply {\n\tu8 port_number;\n};\n\nstruct drm_dp_remote_dpcd_write_nak_reply {\n\tu8 port_number;\n\tu8 reason;\n\tu8 bytes_written_before_failure;\n};\n\nstruct drm_dp_remote_i2c_read_ack_reply {\n\tu8 port_number;\n\tu8 num_bytes;\n\tu8 bytes[255];\n};\n\nstruct drm_dp_remote_i2c_read_nak_reply {\n\tu8 port_number;\n\tu8 nak_reason;\n\tu8 i2c_nak_transaction;\n};\n\nstruct drm_dp_remote_i2c_write_ack_reply {\n\tu8 port_number;\n};\n\nstruct drm_dp_allocate_payload {\n\tu8 port_number;\n\tu8 number_sdp_streams;\n\tu8 vcpi;\n\tu16 pbn;\n\tu8 sdp_stream_sink[16];\n};\n\nstruct drm_dp_allocate_payload_ack_reply {\n\tu8 port_number;\n\tu8 vcpi;\n\tu16 allocated_pbn;\n};\n\nstruct drm_dp_connection_status_notify {\n\tu8 guid[16];\n\tu8 port_number;\n\tbool legacy_device_plug_status;\n\tbool displayport_device_plug_status;\n\tbool message_capability_status;\n\tbool input_port;\n\tu8 peer_device_type;\n};\n\nstruct drm_dp_remote_dpcd_read {\n\tu8 port_number;\n\tu32 dpcd_address;\n\tu8 num_bytes;\n};\n\nstruct drm_dp_remote_dpcd_write {\n\tu8 port_number;\n\tu32 dpcd_address;\n\tu8 num_bytes;\n\tu8 *bytes;\n};\n\nstruct drm_dp_remote_i2c_read_tx {\n\tu8 i2c_dev_id;\n\tu8 num_bytes;\n\tu8 *bytes;\n\tu8 no_stop_bit;\n\tu8 i2c_transaction_delay;\n};\n\nstruct drm_dp_remote_i2c_read {\n\tu8 num_transactions;\n\tu8 port_number;\n\tstruct drm_dp_remote_i2c_read_tx transactions[4];\n\tu8 read_i2c_device_id;\n\tu8 num_bytes_read;\n};\n\nstruct drm_dp_remote_i2c_write {\n\tu8 port_number;\n\tu8 write_i2c_device_id;\n\tu8 num_bytes;\n\tu8 *bytes;\n};\n\nstruct drm_dp_port_number_req {\n\tu8 port_number;\n};\n\nstruct drm_dp_enum_path_resources_ack_reply {\n\tu8 port_number;\n\tbool fec_capable;\n\tu16 full_payload_bw_number;\n\tu16 avail_payload_bw_number;\n};\n\nstruct drm_dp_port_number_rep {\n\tu8 port_number;\n};\n\nstruct drm_dp_query_payload {\n\tu8 port_number;\n\tu8 vcpi;\n};\n\nstruct drm_dp_resource_status_notify {\n\tu8 port_number;\n\tu8 guid[16];\n\tu16 available_pbn;\n};\n\nstruct drm_dp_query_payload_ack_reply {\n\tu8 port_number;\n\tu16 allocated_pbn;\n};\n\nunion ack_req {\n\tstruct drm_dp_connection_status_notify conn_stat;\n\tstruct drm_dp_port_number_req port_num;\n\tstruct drm_dp_resource_status_notify resource_stat;\n\tstruct drm_dp_query_payload query_payload;\n\tstruct drm_dp_allocate_payload allocate_payload;\n\tstruct drm_dp_remote_dpcd_read dpcd_read;\n\tstruct drm_dp_remote_dpcd_write dpcd_write;\n\tstruct drm_dp_remote_i2c_read i2c_read;\n\tstruct drm_dp_remote_i2c_write i2c_write;\n};\n\nstruct drm_dp_sideband_msg_req_body {\n\tu8 req_type;\n\tunion ack_req u;\n};\n\nunion ack_replies {\n\tstruct drm_dp_nak_reply nak;\n\tstruct drm_dp_link_address_ack_reply link_addr;\n\tstruct drm_dp_port_number_rep port_number;\n\tstruct drm_dp_enum_path_resources_ack_reply path_resources;\n\tstruct drm_dp_allocate_payload_ack_reply allocate_payload;\n\tstruct drm_dp_query_payload_ack_reply query_payload;\n\tstruct drm_dp_remote_dpcd_read_ack_reply remote_dpcd_read_ack;\n\tstruct drm_dp_remote_dpcd_write_ack_reply remote_dpcd_write_ack;\n\tstruct drm_dp_remote_dpcd_write_nak_reply remote_dpcd_write_nack;\n\tstruct drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack;\n\tstruct drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack;\n\tstruct drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack;\n};\n\nstruct drm_dp_sideband_msg_reply_body {\n\tu8 reply_type;\n\tu8 req_type;\n\tunion ack_replies u;\n};\n\nstruct drm_dp_sideband_msg_tx {\n\tu8 msg[256];\n\tu8 chunk[48];\n\tu8 cur_offset;\n\tu8 cur_len;\n\tstruct drm_dp_mst_branch *dst;\n\tstruct list_head next;\n\tint seqno;\n\tint state;\n\tbool path_msg;\n\tstruct drm_dp_sideband_msg_reply_body reply;\n};\n\nstruct drm_dp_mst_topology_cbs {\n\tstruct drm_connector * (*add_connector)(struct drm_dp_mst_topology_mgr *, struct drm_dp_mst_port *, const char *);\n};\n\nstruct drm_dp_payload {\n\tint payload_state;\n\tint start_slot;\n\tint num_slots;\n\tint vcpi;\n};\n\nstruct drm_dp_vcpi_allocation {\n\tstruct drm_dp_mst_port *port;\n\tint vcpi;\n\tint pbn;\n\tbool dsc_enabled;\n\tstruct list_head next;\n};\n\nstruct drm_dp_mst_topology_state {\n\tstruct drm_private_state base;\n\tstruct list_head vcpis;\n\tstruct drm_dp_mst_topology_mgr *mgr;\n};\n\nstruct drm_dp_pending_up_req {\n\tstruct drm_dp_sideband_msg_hdr hdr;\n\tstruct drm_dp_sideband_msg_req_body msg;\n\tstruct list_head next;\n};\n\nstruct dma_fence_ops;\n\nstruct dma_fence {\n\tspinlock_t *lock;\n\tconst struct dma_fence_ops *ops;\n\tunion {\n\t\tstruct list_head cb_list;\n\t\tktime_t timestamp;\n\t\tstruct callback_head rcu;\n\t};\n\tu64 context;\n\tu64 seqno;\n\tlong unsigned int flags;\n\tstruct kref refcount;\n\tint error;\n};\n\nstruct dma_fence_ops {\n\tbool use_64bit_seqno;\n\tconst char * (*get_driver_name)(struct dma_fence *);\n\tconst char * (*get_timeline_name)(struct dma_fence *);\n\tbool (*enable_signaling)(struct dma_fence *);\n\tbool (*signaled)(struct dma_fence *);\n\tlong int (*wait)(struct dma_fence *, bool, long int);\n\tvoid (*release)(struct dma_fence *);\n\tvoid (*fence_value_str)(struct dma_fence *, char *, int);\n\tvoid (*timeline_value_str)(struct dma_fence *, char *, int);\n};\n\nstruct drm_color_lut {\n\t__u16 red;\n\t__u16 green;\n\t__u16 blue;\n\t__u16 reserved;\n};\n\nstruct drm_writeback_job {\n\tstruct drm_writeback_connector *connector;\n\tbool prepared;\n\tstruct work_struct cleanup_work;\n\tstruct list_head list_entry;\n\tstruct drm_framebuffer *fb;\n\tstruct dma_fence *out_fence;\n\tvoid *priv;\n};\n\nstruct drm_writeback_connector {\n\tstruct drm_connector base;\n\tstruct drm_encoder encoder;\n\tstruct drm_property_blob *pixel_formats_blob_ptr;\n\tspinlock_t job_lock;\n\tstruct list_head job_queue;\n\tunsigned int fence_context;\n\tspinlock_t fence_lock;\n\tlong unsigned int fence_seqno;\n\tchar timeline_name[32];\n};\n\nenum drm_lspcon_mode {\n\tDRM_LSPCON_MODE_INVALID = 0,\n\tDRM_LSPCON_MODE_LS = 1,\n\tDRM_LSPCON_MODE_PCON = 2,\n};\n\nenum drm_dp_dual_mode_type {\n\tDRM_DP_DUAL_MODE_NONE = 0,\n\tDRM_DP_DUAL_MODE_UNKNOWN = 1,\n\tDRM_DP_DUAL_MODE_TYPE1_DVI = 2,\n\tDRM_DP_DUAL_MODE_TYPE1_HDMI = 3,\n\tDRM_DP_DUAL_MODE_TYPE2_DVI = 4,\n\tDRM_DP_DUAL_MODE_TYPE2_HDMI = 5,\n\tDRM_DP_DUAL_MODE_LSPCON = 6,\n};\n\nstruct drm_simple_display_pipe;\n\nstruct drm_simple_display_pipe_funcs {\n\tenum drm_mode_status (*mode_valid)(struct drm_simple_display_pipe *, const struct drm_display_mode *);\n\tvoid (*enable)(struct drm_simple_display_pipe *, struct drm_crtc_state *, struct drm_plane_state *);\n\tvoid (*disable)(struct drm_simple_display_pipe *);\n\tint (*check)(struct drm_simple_display_pipe *, struct drm_plane_state *, struct drm_crtc_state *);\n\tvoid (*update)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tint (*prepare_fb)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tvoid (*cleanup_fb)(struct drm_simple_display_pipe *, struct drm_plane_state *);\n\tint (*enable_vblank)(struct drm_simple_display_pipe *);\n\tvoid (*disable_vblank)(struct drm_simple_display_pipe *);\n};\n\nstruct drm_simple_display_pipe {\n\tstruct drm_crtc crtc;\n\tstruct drm_plane plane;\n\tstruct drm_encoder encoder;\n\tstruct drm_connector *connector;\n\tconst struct drm_simple_display_pipe_funcs *funcs;\n};\n\nstruct dma_fence_cb;\n\ntypedef void (*dma_fence_func_t)(struct dma_fence *, struct dma_fence_cb *);\n\nstruct dma_fence_cb {\n\tstruct list_head node;\n\tdma_fence_func_t func;\n};\n\nstruct dma_buf_ops {\n\tbool cache_sgt_mapping;\n\tint (*attach)(struct dma_buf *, struct dma_buf_attachment *);\n\tvoid (*detach)(struct dma_buf *, struct dma_buf_attachment *);\n\tint (*pin)(struct dma_buf_attachment *);\n\tvoid (*unpin)(struct dma_buf_attachment *);\n\tstruct sg_table * (*map_dma_buf)(struct dma_buf_attachment *, enum dma_data_direction);\n\tvoid (*unmap_dma_buf)(struct dma_buf_attachment *, struct sg_table *, enum dma_data_direction);\n\tvoid (*release)(struct dma_buf *);\n\tint (*begin_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*end_cpu_access)(struct dma_buf *, enum dma_data_direction);\n\tint (*mmap)(struct dma_buf *, struct vm_area_struct *);\n\tvoid * (*vmap)(struct dma_buf *);\n\tvoid (*vunmap)(struct dma_buf *, void *);\n};\n\nstruct dma_buf_poll_cb_t {\n\tstruct dma_fence_cb cb;\n\twait_queue_head_t *poll;\n\t__poll_t active;\n};\n\nstruct dma_buf {\n\tsize_t size;\n\tstruct file *file;\n\tstruct list_head attachments;\n\tconst struct dma_buf_ops *ops;\n\tstruct mutex lock;\n\tunsigned int vmapping_counter;\n\tvoid *vmap_ptr;\n\tconst char *exp_name;\n\tconst char *name;\n\tspinlock_t name_lock;\n\tstruct module *owner;\n\tstruct list_head list_node;\n\tvoid *priv;\n\tstruct dma_resv *resv;\n\twait_queue_head_t poll;\n\tstruct dma_buf_poll_cb_t cb_excl;\n\tstruct dma_buf_poll_cb_t cb_shared;\n};\n\nstruct dma_buf_attach_ops;\n\nstruct dma_buf_attachment {\n\tstruct dma_buf *dmabuf;\n\tstruct device *dev;\n\tstruct list_head node;\n\tstruct sg_table *sgt;\n\tenum dma_data_direction dir;\n\tbool peer2peer;\n\tconst struct dma_buf_attach_ops *importer_ops;\n\tvoid *importer_priv;\n\tvoid *priv;\n};\n\nstruct dma_buf_attach_ops {\n\tbool allow_peer2peer;\n\tvoid (*move_notify)(struct dma_buf_attachment *);\n};\n\nstruct ww_class {\n\tatomic_long_t stamp;\n\tstruct lock_class_key acquire_key;\n\tstruct lock_class_key mutex_key;\n\tconst char *acquire_name;\n\tconst char *mutex_name;\n\tunsigned int is_wait_die;\n};\n\nstruct dma_resv_list {\n\tstruct callback_head rcu;\n\tu32 shared_count;\n\tu32 shared_max;\n\tstruct dma_fence *shared[0];\n};\n\nstruct drm_afbc_framebuffer {\n\tstruct drm_framebuffer base;\n\tu32 block_width;\n\tu32 block_height;\n\tu32 aligned_width;\n\tu32 aligned_height;\n\tu32 offset;\n\tu32 afbc_size;\n};\n\nstruct drm_mm {\n\tvoid (*color_adjust)(const struct drm_mm_node *, long unsigned int, u64 *, u64 *);\n\tstruct list_head hole_stack;\n\tstruct drm_mm_node head_node;\n\tstruct rb_root_cached interval_tree;\n\tstruct rb_root_cached holes_size;\n\tstruct rb_root holes_addr;\n\tlong unsigned int scan_active;\n};\n\nstruct drm_vma_offset_manager {\n\trwlock_t vm_lock;\n\tstruct drm_mm vm_addr_space_mm;\n};\n\nstruct drm_gem_object_funcs {\n\tvoid (*free)(struct drm_gem_object *);\n\tint (*open)(struct drm_gem_object *, struct drm_file *);\n\tvoid (*close)(struct drm_gem_object *, struct drm_file *);\n\tvoid (*print_info)(struct drm_printer *, unsigned int, const struct drm_gem_object *);\n\tstruct dma_buf * (*export)(struct drm_gem_object *, int);\n\tint (*pin)(struct drm_gem_object *);\n\tvoid (*unpin)(struct drm_gem_object *);\n\tstruct sg_table * (*get_sg_table)(struct drm_gem_object *);\n\tvoid * (*vmap)(struct drm_gem_object *);\n\tvoid (*vunmap)(struct drm_gem_object *, void *);\n\tint (*mmap)(struct drm_gem_object *, struct vm_area_struct *);\n\tconst struct vm_operations_struct *vm_ops;\n};\n\nstruct drm_mode_rect {\n\t__s32 x1;\n\t__s32 y1;\n\t__s32 x2;\n\t__s32 y2;\n};\n\nstruct drm_atomic_helper_damage_iter {\n\tstruct drm_rect plane_src;\n\tconst struct drm_rect *clips;\n\tuint32_t num_clips;\n\tuint32_t curr_clip;\n\tbool full_update;\n};\n\nstruct ewma_psr_time {\n\tlong unsigned int internal;\n};\n\nstruct drm_self_refresh_data {\n\tstruct drm_crtc *crtc;\n\tstruct delayed_work entry_work;\n\tstruct mutex avg_mutex;\n\tstruct ewma_psr_time entry_avg_ms;\n\tstruct ewma_psr_time exit_avg_ms;\n};\n\nstruct display_timing;\n\nstruct drm_panel;\n\nstruct drm_panel_funcs {\n\tint (*prepare)(struct drm_panel *);\n\tint (*enable)(struct drm_panel *);\n\tint (*disable)(struct drm_panel *);\n\tint (*unprepare)(struct drm_panel *);\n\tint (*get_modes)(struct drm_panel *, struct drm_connector *);\n\tint (*get_timings)(struct drm_panel *, unsigned int, struct display_timing *);\n};\n\nstruct drm_panel {\n\tstruct device *dev;\n\tstruct backlight_device *backlight;\n\tconst struct drm_panel_funcs *funcs;\n\tint connector_type;\n\tstruct list_head list;\n};\n\nstruct panel_bridge {\n\tstruct drm_bridge bridge;\n\tstruct drm_connector connector;\n\tstruct drm_panel *panel;\n\tu32 connector_type;\n};\n\nstruct drm_master {\n\tstruct kref refcount;\n\tstruct drm_device *dev;\n\tchar *unique;\n\tint unique_len;\n\tstruct idr magic_map;\n\tvoid *driver_priv;\n\tstruct drm_master *lessor;\n\tint lessee_id;\n\tstruct list_head lessee_list;\n\tstruct list_head lessees;\n\tstruct idr leases;\n\tstruct idr lessee_idr;\n};\n\nstruct drm_auth {\n\tdrm_magic_t magic;\n};\n\nenum drm_minor_type {\n\tDRM_MINOR_PRIMARY = 0,\n\tDRM_MINOR_CONTROL = 1,\n\tDRM_MINOR_RENDER = 2,\n};\n\nstruct drm_gem_close {\n\t__u32 handle;\n\t__u32 pad;\n};\n\nstruct drm_gem_flink {\n\t__u32 handle;\n\t__u32 name;\n};\n\nstruct drm_gem_open {\n\t__u32 name;\n\t__u32 handle;\n\t__u64 size;\n};\n\nstruct drm_version {\n\tint version_major;\n\tint version_minor;\n\tint version_patchlevel;\n\t__kernel_size_t name_len;\n\tchar *name;\n\t__kernel_size_t date_len;\n\tchar *date;\n\t__kernel_size_t desc_len;\n\tchar *desc;\n};\n\nstruct drm_unique {\n\t__kernel_size_t unique_len;\n\tchar *unique;\n};\n\nstruct drm_client {\n\tint idx;\n\tint auth;\n\tlong unsigned int pid;\n\tlong unsigned int uid;\n\tlong unsigned int magic;\n\tlong unsigned int iocs;\n};\n\nenum drm_stat_type {\n\t_DRM_STAT_LOCK = 0,\n\t_DRM_STAT_OPENS = 1,\n\t_DRM_STAT_CLOSES = 2,\n\t_DRM_STAT_IOCTLS = 3,\n\t_DRM_STAT_LOCKS = 4,\n\t_DRM_STAT_UNLOCKS = 5,\n\t_DRM_STAT_VALUE = 6,\n\t_DRM_STAT_BYTE = 7,\n\t_DRM_STAT_COUNT = 8,\n\t_DRM_STAT_IRQ = 9,\n\t_DRM_STAT_PRIMARY = 10,\n\t_DRM_STAT_SECONDARY = 11,\n\t_DRM_STAT_DMA = 12,\n\t_DRM_STAT_SPECIAL = 13,\n\t_DRM_STAT_MISSED = 14,\n};\n\nstruct drm_stats {\n\tlong unsigned int count;\n\tstruct {\n\t\tlong unsigned int value;\n\t\tenum drm_stat_type type;\n\t} data[15];\n};\n\nstruct drm_set_version {\n\tint drm_di_major;\n\tint drm_di_minor;\n\tint drm_dd_major;\n\tint drm_dd_minor;\n};\n\nstruct drm_get_cap {\n\t__u64 capability;\n\t__u64 value;\n};\n\nstruct drm_set_client_cap {\n\t__u64 capability;\n\t__u64 value;\n};\n\nstruct drm_agp_head {\n\tstruct agp_kern_info agp_info;\n\tstruct list_head memory;\n\tlong unsigned int mode;\n\tstruct agp_bridge_data *bridge;\n\tint enabled;\n\tint acquired;\n\tlong unsigned int base;\n\tint agp_mtrr;\n\tint cant_use_aperture;\n\tlong unsigned int page_mask;\n};\n\nenum drm_map_type {\n\t_DRM_FRAME_BUFFER = 0,\n\t_DRM_REGISTERS = 1,\n\t_DRM_SHM = 2,\n\t_DRM_AGP = 3,\n\t_DRM_SCATTER_GATHER = 4,\n\t_DRM_CONSISTENT = 5,\n};\n\nenum drm_map_flags {\n\t_DRM_RESTRICTED = 1,\n\t_DRM_READ_ONLY = 2,\n\t_DRM_LOCKED = 4,\n\t_DRM_KERNEL = 8,\n\t_DRM_WRITE_COMBINING = 16,\n\t_DRM_CONTAINS_LOCK = 32,\n\t_DRM_REMOVABLE = 64,\n\t_DRM_DRIVER = 128,\n};\n\nstruct drm_local_map {\n\tdma_addr_t offset;\n\tlong unsigned int size;\n\tenum drm_map_type type;\n\tenum drm_map_flags flags;\n\tvoid *handle;\n\tint mtrr;\n};\n\nstruct drm_agp_mem {\n\tlong unsigned int handle;\n\tstruct agp_memory *memory;\n\tlong unsigned int bound;\n\tint pages;\n\tstruct list_head head;\n};\n\nstruct class_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct class *, struct class_attribute *, char *);\n\tssize_t (*store)(struct class *, struct class_attribute *, const char *, size_t);\n};\n\nstruct class_attribute_string {\n\tstruct class_attribute attr;\n\tchar *str;\n};\n\nstruct drm_hash_item {\n\tstruct hlist_node head;\n\tlong unsigned int key;\n};\n\nstruct drm_open_hash {\n\tstruct hlist_head *table;\n\tu8 order;\n};\n\nenum drm_mm_insert_mode {\n\tDRM_MM_INSERT_BEST = 0,\n\tDRM_MM_INSERT_LOW = 1,\n\tDRM_MM_INSERT_HIGH = 2,\n\tDRM_MM_INSERT_EVICT = 3,\n\tDRM_MM_INSERT_ONCE = 2147483648,\n\tDRM_MM_INSERT_HIGHEST = 2147483650,\n\tDRM_MM_INSERT_LOWEST = 2147483649,\n};\n\nstruct drm_mm_scan {\n\tstruct drm_mm *mm;\n\tu64 size;\n\tu64 alignment;\n\tu64 remainder_mask;\n\tu64 range_start;\n\tu64 range_end;\n\tu64 hit_start;\n\tu64 hit_end;\n\tlong unsigned int color;\n\tenum drm_mm_insert_mode mode;\n};\n\nstruct drm_mode_modeinfo {\n\t__u32 clock;\n\t__u16 hdisplay;\n\t__u16 hsync_start;\n\t__u16 hsync_end;\n\t__u16 htotal;\n\t__u16 hskew;\n\t__u16 vdisplay;\n\t__u16 vsync_start;\n\t__u16 vsync_end;\n\t__u16 vtotal;\n\t__u16 vscan;\n\t__u32 vrefresh;\n\t__u32 flags;\n\t__u32 type;\n\tchar name[32];\n};\n\nstruct drm_mode_crtc {\n\t__u64 set_connectors_ptr;\n\t__u32 count_connectors;\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 x;\n\t__u32 y;\n\t__u32 gamma_size;\n\t__u32 mode_valid;\n\tstruct drm_mode_modeinfo mode;\n};\n\nstruct drm_format_name_buf {\n\tchar str[32];\n};\n\nstruct displayid_hdr {\n\tu8 rev;\n\tu8 bytes;\n\tu8 prod_id;\n\tu8 ext_count;\n};\n\nstruct displayid_block {\n\tu8 tag;\n\tu8 rev;\n\tu8 num_bytes;\n};\n\nstruct displayid_tiled_block {\n\tstruct displayid_block base;\n\tu8 tile_cap;\n\tu8 topo[3];\n\tu8 tile_size[4];\n\tu8 tile_pixel_bezel[5];\n\tu8 topology_id[8];\n};\n\nstruct displayid_detailed_timings_1 {\n\tu8 pixel_clock[3];\n\tu8 flags;\n\tu8 hactive[2];\n\tu8 hblank[2];\n\tu8 hsync[2];\n\tu8 hsw[2];\n\tu8 vactive[2];\n\tu8 vblank[2];\n\tu8 vsync[2];\n\tu8 vsw[2];\n};\n\nstruct displayid_detailed_timing_block {\n\tstruct displayid_block base;\n\tstruct displayid_detailed_timings_1 timings[0];\n};\n\nstruct hdr_metadata_infoframe {\n\t__u8 eotf;\n\t__u8 metadata_type;\n\tstruct {\n\t\t__u16 x;\n\t\t__u16 y;\n\t} display_primaries[3];\n\tstruct {\n\t\t__u16 x;\n\t\t__u16 y;\n\t} white_point;\n\t__u16 max_display_mastering_luminance;\n\t__u16 min_display_mastering_luminance;\n\t__u16 max_cll;\n\t__u16 max_fall;\n};\n\nstruct hdr_output_metadata {\n\t__u32 metadata_type;\n\tunion {\n\t\tstruct hdr_metadata_infoframe hdmi_metadata_type1;\n\t};\n};\n\nstruct cea_sad {\n\tu8 format;\n\tu8 channels;\n\tu8 freq;\n\tu8 byte2;\n};\n\nstruct detailed_mode_closure {\n\tstruct drm_connector *connector;\n\tstruct edid *edid;\n\tbool preferred;\n\tu32 quirks;\n\tint modes;\n};\n\nstruct edid_quirk___2 {\n\tchar vendor[4];\n\tint product_id;\n\tu32 quirks;\n};\n\nstruct minimode {\n\tshort int w;\n\tshort int h;\n\tshort int r;\n\tshort int rb;\n};\n\ntypedef void detailed_cb(struct detailed_timing *, void *);\n\nstruct stereo_mandatory_mode {\n\tint width;\n\tint height;\n\tint vrefresh;\n\tunsigned int flags;\n};\n\nstruct i2c_device_id {\n\tchar name[20];\n\tkernel_ulong_t driver_data;\n};\n\nstruct i2c_client {\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tchar name[20];\n\tstruct i2c_adapter *adapter;\n\tstruct device dev;\n\tint init_irq;\n\tint irq;\n\tstruct list_head detected;\n};\n\nenum i2c_alert_protocol {\n\tI2C_PROTOCOL_SMBUS_ALERT = 0,\n\tI2C_PROTOCOL_SMBUS_HOST_NOTIFY = 1,\n};\n\nstruct i2c_board_info;\n\nstruct i2c_driver {\n\tunsigned int class;\n\tint (*probe)(struct i2c_client *, const struct i2c_device_id *);\n\tint (*remove)(struct i2c_client *);\n\tint (*probe_new)(struct i2c_client *);\n\tvoid (*shutdown)(struct i2c_client *);\n\tvoid (*alert)(struct i2c_client *, enum i2c_alert_protocol, unsigned int);\n\tint (*command)(struct i2c_client *, unsigned int, void *);\n\tstruct device_driver driver;\n\tconst struct i2c_device_id *id_table;\n\tint (*detect)(struct i2c_client *, struct i2c_board_info *);\n\tconst short unsigned int *address_list;\n\tstruct list_head clients;\n\tbool disable_i2c_core_irq_mapping;\n};\n\nstruct i2c_board_info {\n\tchar type[20];\n\tshort unsigned int flags;\n\tshort unsigned int addr;\n\tconst char *dev_name;\n\tvoid *platform_data;\n\tstruct device_node *of_node;\n\tstruct fwnode_handle *fwnode;\n\tconst struct property_entry *properties;\n\tconst struct resource *resources;\n\tunsigned int num_resources;\n\tint irq;\n};\n\nstruct drm_encoder_slave_funcs {\n\tvoid (*set_config)(struct drm_encoder *, void *);\n\tvoid (*destroy)(struct drm_encoder *);\n\tvoid (*dpms)(struct drm_encoder *, int);\n\tvoid (*save)(struct drm_encoder *);\n\tvoid (*restore)(struct drm_encoder *);\n\tbool (*mode_fixup)(struct drm_encoder *, const struct drm_display_mode *, struct drm_display_mode *);\n\tint (*mode_valid)(struct drm_encoder *, struct drm_display_mode *);\n\tvoid (*mode_set)(struct drm_encoder *, struct drm_display_mode *, struct drm_display_mode *);\n\tenum drm_connector_status (*detect)(struct drm_encoder *, struct drm_connector *);\n\tint (*get_modes)(struct drm_encoder *, struct drm_connector *);\n\tint (*create_resources)(struct drm_encoder *, struct drm_connector *);\n\tint (*set_property)(struct drm_encoder *, struct drm_connector *, struct drm_property *, uint64_t);\n};\n\nstruct drm_encoder_slave {\n\tstruct drm_encoder base;\n\tconst struct drm_encoder_slave_funcs *slave_funcs;\n\tvoid *slave_priv;\n\tvoid *bus_priv;\n};\n\nstruct drm_i2c_encoder_driver {\n\tstruct i2c_driver i2c_driver;\n\tint (*encoder_init)(struct i2c_client *, struct drm_device *, struct drm_encoder_slave *);\n};\n\nstruct trace_event_raw_drm_vblank_event {\n\tstruct trace_entry ent;\n\tint crtc;\n\tunsigned int seq;\n\tktime_t time;\n\tbool high_prec;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drm_vblank_event_queued {\n\tstruct trace_entry ent;\n\tstruct drm_file *file;\n\tint crtc;\n\tunsigned int seq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drm_vblank_event_delivered {\n\tstruct trace_entry ent;\n\tstruct drm_file *file;\n\tint crtc;\n\tunsigned int seq;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_drm_vblank_event {};\n\nstruct trace_event_data_offsets_drm_vblank_event_queued {};\n\nstruct trace_event_data_offsets_drm_vblank_event_delivered {};\n\ntypedef void (*btf_trace_drm_vblank_event)(void *, int, unsigned int, ktime_t, bool);\n\ntypedef void (*btf_trace_drm_vblank_event_queued)(void *, struct drm_file *, int, unsigned int);\n\ntypedef void (*btf_trace_drm_vblank_event_delivered)(void *, struct drm_file *, int, unsigned int);\n\nstruct dma_buf_export_info {\n\tconst char *exp_name;\n\tstruct module *owner;\n\tconst struct dma_buf_ops *ops;\n\tsize_t size;\n\tint flags;\n\tstruct dma_resv *resv;\n\tvoid *priv;\n};\n\nstruct drm_prime_handle {\n\t__u32 handle;\n\t__u32 flags;\n\t__s32 fd;\n};\n\nstruct drm_prime_member {\n\tstruct dma_buf *dma_buf;\n\tuint32_t handle;\n\tstruct rb_node dmabuf_rb;\n\tstruct rb_node handle_rb;\n};\n\nstruct drm_vma_offset_file {\n\tstruct rb_node vm_rb;\n\tstruct drm_file *vm_tag;\n\tlong unsigned int vm_count;\n};\n\nstruct drm_flip_work;\n\ntypedef void (*drm_flip_func_t)(struct drm_flip_work *, void *);\n\nstruct drm_flip_work {\n\tconst char *name;\n\tdrm_flip_func_t func;\n\tstruct work_struct worker;\n\tstruct list_head queued;\n\tstruct list_head commited;\n\tspinlock_t lock;\n};\n\nstruct drm_flip_task {\n\tstruct list_head node;\n\tvoid *data;\n};\n\nstruct drm_info_list {\n\tconst char *name;\n\tint (*show)(struct seq_file *, void *);\n\tu32 driver_features;\n\tvoid *data;\n};\n\nstruct drm_info_node {\n\tstruct drm_minor *minor;\n\tconst struct drm_info_list *info_ent;\n\tstruct list_head list;\n\tstruct dentry *dent;\n};\n\nstruct drm_mode_fb_cmd {\n\t__u32 fb_id;\n\t__u32 width;\n\t__u32 height;\n\t__u32 pitch;\n\t__u32 bpp;\n\t__u32 depth;\n\t__u32 handle;\n};\n\nstruct drm_mode_fb_dirty_cmd {\n\t__u32 fb_id;\n\t__u32 flags;\n\t__u32 color;\n\t__u32 num_clips;\n\t__u64 clips_ptr;\n};\n\nstruct drm_mode_rmfb_work {\n\tstruct work_struct work;\n\tstruct list_head fbs;\n};\n\nstruct drm_mode_get_connector {\n\t__u64 encoders_ptr;\n\t__u64 modes_ptr;\n\t__u64 props_ptr;\n\t__u64 prop_values_ptr;\n\t__u32 count_modes;\n\t__u32 count_props;\n\t__u32 count_encoders;\n\t__u32 encoder_id;\n\t__u32 connector_id;\n\t__u32 connector_type;\n\t__u32 connector_type_id;\n\t__u32 connection;\n\t__u32 mm_width;\n\t__u32 mm_height;\n\t__u32 subpixel;\n\t__u32 pad;\n};\n\nstruct drm_mode_connector_set_property {\n\t__u64 value;\n\t__u32 prop_id;\n\t__u32 connector_id;\n};\n\nstruct drm_mode_obj_set_property {\n\t__u64 value;\n\t__u32 prop_id;\n\t__u32 obj_id;\n\t__u32 obj_type;\n};\n\nstruct drm_prop_enum_list {\n\tint type;\n\tconst char *name;\n};\n\nstruct drm_conn_prop_enum_list {\n\tint type;\n\tconst char *name;\n\tstruct ida ida;\n};\n\nstruct drm_mode_get_encoder {\n\t__u32 encoder_id;\n\t__u32 encoder_type;\n\t__u32 crtc_id;\n\t__u32 possible_crtcs;\n\t__u32 possible_clones;\n};\n\nstruct drm_mode_obj_get_properties {\n\t__u64 props_ptr;\n\t__u64 prop_values_ptr;\n\t__u32 count_props;\n\t__u32 obj_id;\n\t__u32 obj_type;\n};\n\nstruct drm_mode_property_enum {\n\t__u64 value;\n\tchar name[32];\n};\n\nstruct drm_mode_get_property {\n\t__u64 values_ptr;\n\t__u64 enum_blob_ptr;\n\t__u32 prop_id;\n\t__u32 flags;\n\tchar name[32];\n\t__u32 count_values;\n\t__u32 count_enum_blobs;\n};\n\nstruct drm_mode_get_blob {\n\t__u32 blob_id;\n\t__u32 length;\n\t__u64 data;\n};\n\nstruct drm_mode_create_blob {\n\t__u64 data;\n\t__u32 length;\n\t__u32 blob_id;\n};\n\nstruct drm_mode_destroy_blob {\n\t__u32 blob_id;\n};\n\nstruct drm_property_enum {\n\tuint64_t value;\n\tstruct list_head head;\n\tchar name[32];\n};\n\nstruct drm_mode_set_plane {\n\t__u32 plane_id;\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 flags;\n\t__s32 crtc_x;\n\t__s32 crtc_y;\n\t__u32 crtc_w;\n\t__u32 crtc_h;\n\t__u32 src_x;\n\t__u32 src_y;\n\t__u32 src_h;\n\t__u32 src_w;\n};\n\nstruct drm_mode_get_plane {\n\t__u32 plane_id;\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 possible_crtcs;\n\t__u32 gamma_size;\n\t__u32 count_format_types;\n\t__u64 format_type_ptr;\n};\n\nstruct drm_mode_get_plane_res {\n\t__u64 plane_id_ptr;\n\t__u32 count_planes;\n};\n\nstruct drm_mode_cursor {\n\t__u32 flags;\n\t__u32 crtc_id;\n\t__s32 x;\n\t__s32 y;\n\t__u32 width;\n\t__u32 height;\n\t__u32 handle;\n};\n\nstruct drm_mode_cursor2 {\n\t__u32 flags;\n\t__u32 crtc_id;\n\t__s32 x;\n\t__s32 y;\n\t__u32 width;\n\t__u32 height;\n\t__u32 handle;\n\t__s32 hot_x;\n\t__s32 hot_y;\n};\n\nstruct drm_mode_crtc_page_flip_target {\n\t__u32 crtc_id;\n\t__u32 fb_id;\n\t__u32 flags;\n\t__u32 sequence;\n\t__u64 user_data;\n};\n\nstruct drm_format_modifier_blob {\n\t__u32 version;\n\t__u32 flags;\n\t__u32 count_formats;\n\t__u32 formats_offset;\n\t__u32 count_modifiers;\n\t__u32 modifiers_offset;\n};\n\nstruct drm_format_modifier {\n\t__u64 formats;\n\t__u32 offset;\n\t__u32 pad;\n\t__u64 modifier;\n};\n\nstruct drm_mode_crtc_lut {\n\t__u32 crtc_id;\n\t__u32 gamma_size;\n\t__u64 red;\n\t__u64 green;\n\t__u64 blue;\n};\n\nenum drm_color_lut_tests {\n\tDRM_COLOR_LUT_EQUAL_CHANNELS = 1,\n\tDRM_COLOR_LUT_NON_DECREASING = 2,\n};\n\nstruct drm_print_iterator {\n\tvoid *data;\n\tssize_t start;\n\tssize_t remain;\n\tssize_t offset;\n};\n\nstruct drm_mode_map_dumb {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n};\n\nstruct drm_mode_destroy_dumb {\n\t__u32 handle;\n};\n\nstruct drm_mode_card_res {\n\t__u64 fb_id_ptr;\n\t__u64 crtc_id_ptr;\n\t__u64 connector_id_ptr;\n\t__u64 encoder_id_ptr;\n\t__u32 count_fbs;\n\t__u32 count_crtcs;\n\t__u32 count_connectors;\n\t__u32 count_encoders;\n\t__u32 min_width;\n\t__u32 max_width;\n\t__u32 min_height;\n\t__u32 max_height;\n};\n\nenum drm_vblank_seq_type {\n\t_DRM_VBLANK_ABSOLUTE = 0,\n\t_DRM_VBLANK_RELATIVE = 1,\n\t_DRM_VBLANK_HIGH_CRTC_MASK = 62,\n\t_DRM_VBLANK_EVENT = 67108864,\n\t_DRM_VBLANK_FLIP = 134217728,\n\t_DRM_VBLANK_NEXTONMISS = 268435456,\n\t_DRM_VBLANK_SECONDARY = 536870912,\n\t_DRM_VBLANK_SIGNAL = 1073741824,\n};\n\nstruct drm_wait_vblank_request {\n\tenum drm_vblank_seq_type type;\n\tunsigned int sequence;\n\tlong unsigned int signal;\n};\n\nstruct drm_wait_vblank_reply {\n\tenum drm_vblank_seq_type type;\n\tunsigned int sequence;\n\tlong int tval_sec;\n\tlong int tval_usec;\n};\n\nunion drm_wait_vblank {\n\tstruct drm_wait_vblank_request request;\n\tstruct drm_wait_vblank_reply reply;\n};\n\nstruct drm_modeset_ctl {\n\t__u32 crtc;\n\t__u32 cmd;\n};\n\nstruct drm_crtc_get_sequence {\n\t__u32 crtc_id;\n\t__u32 active;\n\t__u64 sequence;\n\t__s64 sequence_ns;\n};\n\nstruct drm_crtc_queue_sequence {\n\t__u32 crtc_id;\n\t__u32 flags;\n\t__u64 sequence;\n\t__u64 user_data;\n};\n\ntypedef bool (*drm_vblank_get_scanout_position_func)(struct drm_crtc *, bool, int *, int *, ktime_t *, ktime_t *, const struct drm_display_mode *);\n\nenum dma_fence_flag_bits {\n\tDMA_FENCE_FLAG_SIGNALED_BIT = 0,\n\tDMA_FENCE_FLAG_TIMESTAMP_BIT = 1,\n\tDMA_FENCE_FLAG_ENABLE_SIGNAL_BIT = 2,\n\tDMA_FENCE_FLAG_USER_BITS = 3,\n};\n\nstruct sync_file {\n\tstruct file *file;\n\tchar user_name[32];\n\tstruct list_head sync_file_list;\n\twait_queue_head_t wq;\n\tlong unsigned int flags;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb cb;\n};\n\nstruct drm_syncobj_create {\n\t__u32 handle;\n\t__u32 flags;\n};\n\nstruct drm_syncobj_destroy {\n\t__u32 handle;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_handle {\n\t__u32 handle;\n\t__u32 flags;\n\t__s32 fd;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_transfer {\n\t__u32 src_handle;\n\t__u32 dst_handle;\n\t__u64 src_point;\n\t__u64 dst_point;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_wait {\n\t__u64 handles;\n\t__s64 timeout_nsec;\n\t__u32 count_handles;\n\t__u32 flags;\n\t__u32 first_signaled;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_timeline_wait {\n\t__u64 handles;\n\t__u64 points;\n\t__s64 timeout_nsec;\n\t__u32 count_handles;\n\t__u32 flags;\n\t__u32 first_signaled;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_array {\n\t__u64 handles;\n\t__u32 count_handles;\n\t__u32 pad;\n};\n\nstruct drm_syncobj_timeline_array {\n\t__u64 handles;\n\t__u64 points;\n\t__u32 count_handles;\n\t__u32 flags;\n};\n\nstruct dma_fence_chain {\n\tstruct dma_fence base;\n\tspinlock_t lock;\n\tstruct dma_fence *prev;\n\tu64 prev_seqno;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb cb;\n\tstruct irq_work work;\n};\n\nstruct drm_syncobj {\n\tstruct kref refcount;\n\tstruct dma_fence *fence;\n\tstruct list_head cb_list;\n\tspinlock_t lock;\n\tstruct file *file;\n};\n\nstruct syncobj_wait_entry {\n\tstruct list_head node;\n\tstruct task_struct *task;\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb fence_cb;\n\tu64 point;\n};\n\nstruct drm_mode_create_lease {\n\t__u64 object_ids;\n\t__u32 object_count;\n\t__u32 flags;\n\t__u32 lessee_id;\n\t__u32 fd;\n};\n\nstruct drm_mode_list_lessees {\n\t__u32 count_lessees;\n\t__u32 pad;\n\t__u64 lessees_ptr;\n};\n\nstruct drm_mode_get_lease {\n\t__u32 count_objects;\n\t__u32 pad;\n\t__u64 objects_ptr;\n};\n\nstruct drm_mode_revoke_lease {\n\t__u32 lessee_id;\n};\n\nstruct drm_client_offset {\n\tint x;\n\tint y;\n};\n\nstruct drm_mode_atomic {\n\t__u32 flags;\n\t__u32 count_objs;\n\t__u64 objs_ptr;\n\t__u64 count_props_ptr;\n\t__u64 props_ptr;\n\t__u64 prop_values_ptr;\n\t__u64 reserved;\n\t__u64 user_data;\n};\n\nstruct drm_out_fence_state {\n\ts32 *out_fence_ptr;\n\tstruct sync_file *sync_file;\n\tint fd;\n};\n\nstruct hdcp_srm_header {\n\tu8 srm_id;\n\tu8 reserved;\n\t__be16 srm_version;\n\tu8 srm_gen_no;\n} __attribute__((packed));\n\ntypedef void (*drmres_release_t)(struct drm_device *, void *);\n\nstruct drmres_node {\n\tstruct list_head entry;\n\tdrmres_release_t release;\n\tconst char *name;\n\tsize_t size;\n};\n\nstruct drmres {\n\tstruct drmres_node node;\n\tu8 data[0];\n};\n\ntypedef unsigned int drm_drawable_t;\n\nstruct drm_agp_mode {\n\tlong unsigned int mode;\n};\n\nstruct drm_agp_buffer {\n\tlong unsigned int size;\n\tlong unsigned int handle;\n\tlong unsigned int type;\n\tlong unsigned int physical;\n};\n\nstruct drm_agp_binding {\n\tlong unsigned int handle;\n\tlong unsigned int offset;\n};\n\nstruct drm_agp_info {\n\tint agp_version_major;\n\tint agp_version_minor;\n\tlong unsigned int mode;\n\tlong unsigned int aperture_base;\n\tlong unsigned int aperture_size;\n\tlong unsigned int memory_allowed;\n\tlong unsigned int memory_used;\n\tshort unsigned int id_vendor;\n\tshort unsigned int id_device;\n};\n\ntypedef int drm_ioctl_compat_t(struct file *, unsigned int, long unsigned int);\n\nstruct drm_version_32 {\n\tint version_major;\n\tint version_minor;\n\tint version_patchlevel;\n\tu32 name_len;\n\tu32 name;\n\tu32 date_len;\n\tu32 date;\n\tu32 desc_len;\n\tu32 desc;\n};\n\ntypedef struct drm_version_32 drm_version32_t;\n\nstruct drm_unique32 {\n\tu32 unique_len;\n\tu32 unique;\n};\n\ntypedef struct drm_unique32 drm_unique32_t;\n\nstruct drm_client32 {\n\tint idx;\n\tint auth;\n\tu32 pid;\n\tu32 uid;\n\tu32 magic;\n\tu32 iocs;\n};\n\ntypedef struct drm_client32 drm_client32_t;\n\nstruct drm_stats32 {\n\tu32 count;\n\tstruct {\n\t\tu32 value;\n\t\tenum drm_stat_type type;\n\t} data[15];\n};\n\ntypedef struct drm_stats32 drm_stats32_t;\n\nstruct drm_agp_mode32 {\n\tu32 mode;\n};\n\ntypedef struct drm_agp_mode32 drm_agp_mode32_t;\n\nstruct drm_agp_info32 {\n\tint agp_version_major;\n\tint agp_version_minor;\n\tu32 mode;\n\tu32 aperture_base;\n\tu32 aperture_size;\n\tu32 memory_allowed;\n\tu32 memory_used;\n\tshort unsigned int id_vendor;\n\tshort unsigned int id_device;\n};\n\ntypedef struct drm_agp_info32 drm_agp_info32_t;\n\nstruct drm_agp_buffer32 {\n\tu32 size;\n\tu32 handle;\n\tu32 type;\n\tu32 physical;\n};\n\ntypedef struct drm_agp_buffer32 drm_agp_buffer32_t;\n\nstruct drm_agp_binding32 {\n\tu32 handle;\n\tu32 offset;\n};\n\ntypedef struct drm_agp_binding32 drm_agp_binding32_t;\n\nstruct drm_update_draw32 {\n\tdrm_drawable_t handle;\n\tunsigned int type;\n\tunsigned int num;\n\tu64 data;\n} __attribute__((packed));\n\ntypedef struct drm_update_draw32 drm_update_draw32_t;\n\nstruct drm_wait_vblank_request32 {\n\tenum drm_vblank_seq_type type;\n\tunsigned int sequence;\n\tu32 signal;\n};\n\nstruct drm_wait_vblank_reply32 {\n\tenum drm_vblank_seq_type type;\n\tunsigned int sequence;\n\ts32 tval_sec;\n\ts32 tval_usec;\n};\n\nunion drm_wait_vblank32 {\n\tstruct drm_wait_vblank_request32 request;\n\tstruct drm_wait_vblank_reply32 reply;\n};\n\ntypedef union drm_wait_vblank32 drm_wait_vblank32_t;\n\nstruct drm_mode_fb_cmd232 {\n\tu32 fb_id;\n\tu32 width;\n\tu32 height;\n\tu32 pixel_format;\n\tu32 flags;\n\tu32 handles[4];\n\tu32 pitches[4];\n\tu32 offsets[4];\n\tu64 modifier[4];\n} __attribute__((packed));\n\nstruct drm_irq_busid {\n\tint irq;\n\tint busnum;\n\tint devnum;\n\tint funcnum;\n};\n\nstruct mipi_dsi_msg {\n\tu8 channel;\n\tu8 type;\n\tu16 flags;\n\tsize_t tx_len;\n\tconst void *tx_buf;\n\tsize_t rx_len;\n\tvoid *rx_buf;\n};\n\nstruct mipi_dsi_packet {\n\tsize_t size;\n\tu8 header[4];\n\tsize_t payload_length;\n\tconst u8 *payload;\n};\n\nstruct mipi_dsi_host;\n\nstruct mipi_dsi_device;\n\nstruct mipi_dsi_host_ops {\n\tint (*attach)(struct mipi_dsi_host *, struct mipi_dsi_device *);\n\tint (*detach)(struct mipi_dsi_host *, struct mipi_dsi_device *);\n\tssize_t (*transfer)(struct mipi_dsi_host *, const struct mipi_dsi_msg *);\n};\n\nstruct mipi_dsi_host {\n\tstruct device *dev;\n\tconst struct mipi_dsi_host_ops *ops;\n\tstruct list_head list;\n};\n\nenum mipi_dsi_pixel_format {\n\tMIPI_DSI_FMT_RGB888 = 0,\n\tMIPI_DSI_FMT_RGB666 = 1,\n\tMIPI_DSI_FMT_RGB666_PACKED = 2,\n\tMIPI_DSI_FMT_RGB565 = 3,\n};\n\nstruct mipi_dsi_device {\n\tstruct mipi_dsi_host *host;\n\tstruct device dev;\n\tchar name[20];\n\tunsigned int channel;\n\tunsigned int lanes;\n\tenum mipi_dsi_pixel_format format;\n\tlong unsigned int mode_flags;\n\tlong unsigned int hs_rate;\n\tlong unsigned int lp_rate;\n};\n\nstruct mipi_dsi_device_info {\n\tchar type[20];\n\tu32 channel;\n\tstruct device_node *node;\n};\n\nenum mipi_dsi_dcs_tear_mode {\n\tMIPI_DSI_DCS_TEAR_MODE_VBLANK = 0,\n\tMIPI_DSI_DCS_TEAR_MODE_VHBLANK = 1,\n};\n\nstruct mipi_dsi_driver {\n\tstruct device_driver driver;\n\tint (*probe)(struct mipi_dsi_device *);\n\tint (*remove)(struct mipi_dsi_device *);\n\tvoid (*shutdown)(struct mipi_dsi_device *);\n};\n\nenum {\n\tMIPI_DSI_V_SYNC_START = 1,\n\tMIPI_DSI_V_SYNC_END = 17,\n\tMIPI_DSI_H_SYNC_START = 33,\n\tMIPI_DSI_H_SYNC_END = 49,\n\tMIPI_DSI_COMPRESSION_MODE = 7,\n\tMIPI_DSI_END_OF_TRANSMISSION = 8,\n\tMIPI_DSI_COLOR_MODE_OFF = 2,\n\tMIPI_DSI_COLOR_MODE_ON = 18,\n\tMIPI_DSI_SHUTDOWN_PERIPHERAL = 34,\n\tMIPI_DSI_TURN_ON_PERIPHERAL = 50,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 3,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 19,\n\tMIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 35,\n\tMIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 4,\n\tMIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 20,\n\tMIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 36,\n\tMIPI_DSI_DCS_SHORT_WRITE = 5,\n\tMIPI_DSI_DCS_SHORT_WRITE_PARAM = 21,\n\tMIPI_DSI_DCS_READ = 6,\n\tMIPI_DSI_EXECUTE_QUEUE = 22,\n\tMIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 55,\n\tMIPI_DSI_NULL_PACKET = 9,\n\tMIPI_DSI_BLANKING_PACKET = 25,\n\tMIPI_DSI_GENERIC_LONG_WRITE = 41,\n\tMIPI_DSI_DCS_LONG_WRITE = 57,\n\tMIPI_DSI_PICTURE_PARAMETER_SET = 10,\n\tMIPI_DSI_COMPRESSED_PIXEL_STREAM = 11,\n\tMIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 12,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 28,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 44,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_30 = 13,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_36 = 29,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 61,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_16 = 14,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_18 = 30,\n\tMIPI_DSI_PIXEL_STREAM_3BYTE_18 = 46,\n\tMIPI_DSI_PACKED_PIXEL_STREAM_24 = 62,\n};\n\nenum {\n\tMIPI_DCS_NOP = 0,\n\tMIPI_DCS_SOFT_RESET = 1,\n\tMIPI_DCS_GET_COMPRESSION_MODE = 3,\n\tMIPI_DCS_GET_DISPLAY_ID = 4,\n\tMIPI_DCS_GET_ERROR_COUNT_ON_DSI = 5,\n\tMIPI_DCS_GET_RED_CHANNEL = 6,\n\tMIPI_DCS_GET_GREEN_CHANNEL = 7,\n\tMIPI_DCS_GET_BLUE_CHANNEL = 8,\n\tMIPI_DCS_GET_DISPLAY_STATUS = 9,\n\tMIPI_DCS_GET_POWER_MODE = 10,\n\tMIPI_DCS_GET_ADDRESS_MODE = 11,\n\tMIPI_DCS_GET_PIXEL_FORMAT = 12,\n\tMIPI_DCS_GET_DISPLAY_MODE = 13,\n\tMIPI_DCS_GET_SIGNAL_MODE = 14,\n\tMIPI_DCS_GET_DIAGNOSTIC_RESULT = 15,\n\tMIPI_DCS_ENTER_SLEEP_MODE = 16,\n\tMIPI_DCS_EXIT_SLEEP_MODE = 17,\n\tMIPI_DCS_ENTER_PARTIAL_MODE = 18,\n\tMIPI_DCS_ENTER_NORMAL_MODE = 19,\n\tMIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 20,\n\tMIPI_DCS_GET_IMAGE_CHECKSUM_CT = 21,\n\tMIPI_DCS_EXIT_INVERT_MODE = 32,\n\tMIPI_DCS_ENTER_INVERT_MODE = 33,\n\tMIPI_DCS_SET_GAMMA_CURVE = 38,\n\tMIPI_DCS_SET_DISPLAY_OFF = 40,\n\tMIPI_DCS_SET_DISPLAY_ON = 41,\n\tMIPI_DCS_SET_COLUMN_ADDRESS = 42,\n\tMIPI_DCS_SET_PAGE_ADDRESS = 43,\n\tMIPI_DCS_WRITE_MEMORY_START = 44,\n\tMIPI_DCS_WRITE_LUT = 45,\n\tMIPI_DCS_READ_MEMORY_START = 46,\n\tMIPI_DCS_SET_PARTIAL_ROWS = 48,\n\tMIPI_DCS_SET_PARTIAL_COLUMNS = 49,\n\tMIPI_DCS_SET_SCROLL_AREA = 51,\n\tMIPI_DCS_SET_TEAR_OFF = 52,\n\tMIPI_DCS_SET_TEAR_ON = 53,\n\tMIPI_DCS_SET_ADDRESS_MODE = 54,\n\tMIPI_DCS_SET_SCROLL_START = 55,\n\tMIPI_DCS_EXIT_IDLE_MODE = 56,\n\tMIPI_DCS_ENTER_IDLE_MODE = 57,\n\tMIPI_DCS_SET_PIXEL_FORMAT = 58,\n\tMIPI_DCS_WRITE_MEMORY_CONTINUE = 60,\n\tMIPI_DCS_SET_3D_CONTROL = 61,\n\tMIPI_DCS_READ_MEMORY_CONTINUE = 62,\n\tMIPI_DCS_GET_3D_CONTROL = 63,\n\tMIPI_DCS_SET_VSYNC_TIMING = 64,\n\tMIPI_DCS_SET_TEAR_SCANLINE = 68,\n\tMIPI_DCS_GET_SCANLINE = 69,\n\tMIPI_DCS_SET_DISPLAY_BRIGHTNESS = 81,\n\tMIPI_DCS_GET_DISPLAY_BRIGHTNESS = 82,\n\tMIPI_DCS_WRITE_CONTROL_DISPLAY = 83,\n\tMIPI_DCS_GET_CONTROL_DISPLAY = 84,\n\tMIPI_DCS_WRITE_POWER_SAVE = 85,\n\tMIPI_DCS_GET_POWER_SAVE = 86,\n\tMIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 94,\n\tMIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 95,\n\tMIPI_DCS_READ_DDB_START = 161,\n\tMIPI_DCS_READ_PPS_START = 162,\n\tMIPI_DCS_READ_DDB_CONTINUE = 168,\n\tMIPI_DCS_READ_PPS_CONTINUE = 169,\n};\n\nstruct drm_dmi_panel_orientation_data {\n\tint width;\n\tint height;\n\tconst char * const *bios_dates;\n\tint orientation;\n};\n\ntypedef u32 depot_stack_handle_t;\n\nenum pipe {\n\tINVALID_PIPE = 4294967295,\n\tPIPE_A = 0,\n\tPIPE_B = 1,\n\tPIPE_C = 2,\n\tPIPE_D = 3,\n\t_PIPE_EDP = 4,\n\tI915_MAX_PIPES = 4,\n};\n\nenum transcoder {\n\tINVALID_TRANSCODER = 4294967295,\n\tTRANSCODER_A = 0,\n\tTRANSCODER_B = 1,\n\tTRANSCODER_C = 2,\n\tTRANSCODER_D = 3,\n\tTRANSCODER_EDP = 4,\n\tTRANSCODER_DSI_0 = 5,\n\tTRANSCODER_DSI_1 = 6,\n\tTRANSCODER_DSI_A = 5,\n\tTRANSCODER_DSI_C = 6,\n\tI915_MAX_TRANSCODERS = 7,\n};\n\nenum i9xx_plane_id {\n\tPLANE_A = 0,\n\tPLANE_B = 1,\n\tPLANE_C = 2,\n};\n\nenum plane_id {\n\tPLANE_PRIMARY = 0,\n\tPLANE_SPRITE0 = 1,\n\tPLANE_SPRITE1 = 2,\n\tPLANE_SPRITE2 = 3,\n\tPLANE_SPRITE3 = 4,\n\tPLANE_SPRITE4 = 5,\n\tPLANE_SPRITE5 = 6,\n\tPLANE_CURSOR = 7,\n\tI915_MAX_PLANES = 8,\n};\n\nenum port {\n\tPORT_NONE = 4294967295,\n\tPORT_A = 0,\n\tPORT_B = 1,\n\tPORT_C = 2,\n\tPORT_D = 3,\n\tPORT_E = 4,\n\tPORT_F = 5,\n\tPORT_G = 6,\n\tPORT_H = 7,\n\tPORT_I = 8,\n\tI915_MAX_PORTS = 9,\n};\n\nenum tc_port_mode {\n\tTC_PORT_TBT_ALT = 0,\n\tTC_PORT_DP_ALT = 1,\n\tTC_PORT_LEGACY = 2,\n};\n\nenum dpio_phy {\n\tDPIO_PHY0 = 0,\n\tDPIO_PHY1 = 1,\n\tDPIO_PHY2 = 2,\n};\n\nenum aux_ch {\n\tAUX_CH_A = 0,\n\tAUX_CH_B = 1,\n\tAUX_CH_C = 2,\n\tAUX_CH_D = 3,\n\tAUX_CH_E = 4,\n\tAUX_CH_F = 5,\n\tAUX_CH_G = 6,\n};\n\nstruct intel_link_m_n {\n\tu32 tu;\n\tu32 gmch_m;\n\tu32 gmch_n;\n\tu32 link_m;\n\tu32 link_n;\n};\n\nenum phy_fia {\n\tFIA1 = 0,\n\tFIA2 = 1,\n\tFIA3 = 2,\n};\n\nstruct intel_global_state;\n\nstruct intel_global_obj;\n\nstruct intel_global_state_funcs {\n\tstruct intel_global_state * (*atomic_duplicate_state)(struct intel_global_obj *);\n\tvoid (*atomic_destroy_state)(struct intel_global_obj *, struct intel_global_state *);\n};\n\nstruct intel_atomic_state;\n\nstruct intel_global_state {\n\tstruct intel_global_obj *obj;\n\tstruct intel_atomic_state *state;\n\tstruct kref ref;\n\tbool changed;\n};\n\nstruct intel_global_obj {\n\tstruct list_head head;\n\tstruct intel_global_state *state;\n\tconst struct intel_global_state_funcs *funcs;\n};\n\ntypedef depot_stack_handle_t intel_wakeref_t;\n\nstruct intel_dpll_hw_state {\n\tu32 dpll;\n\tu32 dpll_md;\n\tu32 fp0;\n\tu32 fp1;\n\tu32 wrpll;\n\tu32 spll;\n\tu32 ctrl1;\n\tu32 cfgcr1;\n\tu32 cfgcr2;\n\tu32 cfgcr0;\n\tu32 ebb0;\n\tu32 ebb4;\n\tu32 pll0;\n\tu32 pll1;\n\tu32 pll2;\n\tu32 pll3;\n\tu32 pll6;\n\tu32 pll8;\n\tu32 pll9;\n\tu32 pll10;\n\tu32 pcsdw12;\n\tu32 mg_refclkin_ctl;\n\tu32 mg_clktop2_coreclkctl1;\n\tu32 mg_clktop2_hsclkctl;\n\tu32 mg_pll_div0;\n\tu32 mg_pll_div1;\n\tu32 mg_pll_lf;\n\tu32 mg_pll_frac_lock;\n\tu32 mg_pll_ssc;\n\tu32 mg_pll_bias;\n\tu32 mg_pll_tdc_coldst_bias;\n\tu32 mg_pll_bias_mask;\n\tu32 mg_pll_tdc_coldst_bias_mask;\n};\n\nstruct intel_shared_dpll_state {\n\tunsigned int crtc_mask;\n\tstruct intel_dpll_hw_state hw_state;\n};\n\nstruct i915_sw_fence {\n\twait_queue_head_t wait;\n\tlong unsigned int flags;\n\tatomic_t pending;\n\tint error;\n};\n\nstruct __intel_global_objs_state;\n\nstruct intel_atomic_state {\n\tstruct drm_atomic_state base;\n\tintel_wakeref_t wakeref;\n\tstruct __intel_global_objs_state *global_objs;\n\tint num_global_objs;\n\tbool dpll_set;\n\tbool modeset;\n\tu8 active_pipe_changes;\n\tu8 active_pipes;\n\tstruct intel_shared_dpll_state shared_dpll[9];\n\tbool skip_intermediate_wm;\n\tbool rps_interactive;\n\tbool global_state_changed;\n\tu8 enabled_dbuf_slices_mask;\n\tstruct i915_sw_fence commit_ready;\n\tstruct llist_node freed;\n};\n\nstruct __intel_global_objs_state {\n\tstruct intel_global_obj *ptr;\n\tstruct intel_global_state *state;\n\tstruct intel_global_state *old_state;\n\tstruct intel_global_state *new_state;\n};\n\nenum drm_i915_pmu_engine_sample {\n\tI915_SAMPLE_BUSY = 0,\n\tI915_SAMPLE_WAIT = 1,\n\tI915_SAMPLE_SEMA = 2,\n};\n\nstruct drm_i915_gem_pwrite {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 size;\n\t__u64 data_ptr;\n};\n\nstruct io_mapping {\n\tresource_size_t base;\n\tlong unsigned int size;\n\tpgprot_t prot;\n\tvoid *iomem;\n};\n\nstruct i2c_algo_bit_data {\n\tvoid *data;\n\tvoid (*setsda)(void *, int);\n\tvoid (*setscl)(void *, int);\n\tint (*getsda)(void *);\n\tint (*getscl)(void *);\n\tint (*pre_xfer)(struct i2c_adapter *);\n\tvoid (*post_xfer)(struct i2c_adapter *);\n\tint udelay;\n\tint timeout;\n\tbool can_do_atomic;\n};\n\nstruct cec_devnode {\n\tstruct device dev;\n\tstruct cdev cdev;\n\tint minor;\n\tbool registered;\n\tbool unregistered;\n\tstruct list_head fhs;\n\tstruct mutex lock;\n};\n\nstruct cec_log_addrs {\n\t__u8 log_addr[4];\n\t__u16 log_addr_mask;\n\t__u8 cec_version;\n\t__u8 num_log_addrs;\n\t__u32 vendor_id;\n\t__u32 flags;\n\tchar osd_name[15];\n\t__u8 primary_device_type[4];\n\t__u8 log_addr_type[4];\n\t__u8 all_device_types[4];\n\t__u8 features[48];\n};\n\nstruct cec_drm_connector_info {\n\t__u32 card_no;\n\t__u32 connector_id;\n};\n\nstruct cec_connector_info {\n\t__u32 type;\n\tunion {\n\t\tstruct cec_drm_connector_info drm;\n\t\t__u32 raw[16];\n\t};\n};\n\nstruct rc_dev;\n\nstruct cec_data;\n\nstruct cec_adap_ops;\n\nstruct cec_fh;\n\nstruct cec_adapter {\n\tstruct module *owner;\n\tchar name[32];\n\tstruct cec_devnode devnode;\n\tstruct mutex lock;\n\tstruct rc_dev *rc;\n\tstruct list_head transmit_queue;\n\tunsigned int transmit_queue_sz;\n\tstruct list_head wait_queue;\n\tstruct cec_data *transmitting;\n\tbool transmit_in_progress;\n\tstruct task_struct *kthread_config;\n\tstruct completion config_completion;\n\tstruct task_struct *kthread;\n\twait_queue_head_t kthread_waitq;\n\twait_queue_head_t waitq;\n\tconst struct cec_adap_ops *ops;\n\tvoid *priv;\n\tu32 capabilities;\n\tu8 available_log_addrs;\n\tu16 phys_addr;\n\tbool needs_hpd;\n\tbool is_configuring;\n\tbool is_configured;\n\tbool cec_pin_is_high;\n\tu8 last_initiator;\n\tu32 monitor_all_cnt;\n\tu32 monitor_pin_cnt;\n\tu32 follower_cnt;\n\tstruct cec_fh *cec_follower;\n\tstruct cec_fh *cec_initiator;\n\tbool passthrough;\n\tstruct cec_log_addrs log_addrs;\n\tstruct cec_connector_info conn_info;\n\tu32 tx_timeouts;\n\tstruct dentry *cec_dir;\n\tstruct dentry *status_file;\n\tstruct dentry *error_inj_file;\n\tu16 phys_addrs[15];\n\tu32 sequence;\n\tchar input_phys[32];\n};\n\nstruct hdcp2_cert_rx {\n\tu8 receiver_id[5];\n\tu8 kpub_rx[131];\n\tu8 reserved[2];\n\tu8 dcp_signature[384];\n};\n\nstruct hdcp2_streamid_type {\n\tu8 stream_id;\n\tu8 stream_type;\n};\n\nstruct hdcp2_tx_caps {\n\tu8 version;\n\tu8 tx_cap_mask[2];\n};\n\nstruct hdcp2_ake_init {\n\tu8 msg_id;\n\tu8 r_tx[8];\n\tstruct hdcp2_tx_caps tx_caps;\n};\n\nstruct hdcp2_ake_send_cert {\n\tu8 msg_id;\n\tstruct hdcp2_cert_rx cert_rx;\n\tu8 r_rx[8];\n\tu8 rx_caps[3];\n};\n\nstruct hdcp2_ake_no_stored_km {\n\tu8 msg_id;\n\tu8 e_kpub_km[128];\n};\n\nstruct hdcp2_ake_send_hprime {\n\tu8 msg_id;\n\tu8 h_prime[32];\n};\n\nstruct hdcp2_ake_send_pairing_info {\n\tu8 msg_id;\n\tu8 e_kh_km[16];\n};\n\nstruct hdcp2_lc_init {\n\tu8 msg_id;\n\tu8 r_n[8];\n};\n\nstruct hdcp2_lc_send_lprime {\n\tu8 msg_id;\n\tu8 l_prime[32];\n};\n\nstruct hdcp2_ske_send_eks {\n\tu8 msg_id;\n\tu8 e_dkey_ks[16];\n\tu8 riv[8];\n};\n\nstruct hdcp2_rep_send_receiverid_list {\n\tu8 msg_id;\n\tu8 rx_info[2];\n\tu8 seq_num_v[3];\n\tu8 v_prime[16];\n\tu8 receiver_ids[155];\n};\n\nstruct hdcp2_rep_send_ack {\n\tu8 msg_id;\n\tu8 v[16];\n};\n\nstruct hdcp2_rep_stream_ready {\n\tu8 msg_id;\n\tu8 m_prime[32];\n};\n\nenum hdcp_wired_protocol {\n\tHDCP_PROTOCOL_INVALID = 0,\n\tHDCP_PROTOCOL_HDMI = 1,\n\tHDCP_PROTOCOL_DP = 2,\n};\n\nenum mei_fw_ddi {\n\tMEI_DDI_INVALID_PORT = 0,\n\tMEI_DDI_B = 1,\n\tMEI_DDI_C = 2,\n\tMEI_DDI_D = 3,\n\tMEI_DDI_E = 4,\n\tMEI_DDI_F = 5,\n\tMEI_DDI_A = 7,\n\tMEI_DDI_RANGE_END = 7,\n};\n\nenum mei_fw_tc {\n\tMEI_INVALID_TRANSCODER = 0,\n\tMEI_TRANSCODER_EDP = 1,\n\tMEI_TRANSCODER_DSI0 = 2,\n\tMEI_TRANSCODER_DSI1 = 3,\n\tMEI_TRANSCODER_A = 16,\n\tMEI_TRANSCODER_B = 17,\n\tMEI_TRANSCODER_C = 18,\n\tMEI_TRANSCODER_D = 19,\n};\n\nstruct hdcp_port_data {\n\tenum mei_fw_ddi fw_ddi;\n\tenum mei_fw_tc fw_tc;\n\tu8 port_type;\n\tu8 protocol;\n\tu16 k;\n\tu32 seq_num_m;\n\tstruct hdcp2_streamid_type *streams;\n};\n\nstruct i915_hdcp_component_ops {\n\tstruct module *owner;\n\tint (*initiate_hdcp2_session)(struct device *, struct hdcp_port_data *, struct hdcp2_ake_init *);\n\tint (*verify_receiver_cert_prepare_km)(struct device *, struct hdcp_port_data *, struct hdcp2_ake_send_cert *, bool *, struct hdcp2_ake_no_stored_km *, size_t *);\n\tint (*verify_hprime)(struct device *, struct hdcp_port_data *, struct hdcp2_ake_send_hprime *);\n\tint (*store_pairing_info)(struct device *, struct hdcp_port_data *, struct hdcp2_ake_send_pairing_info *);\n\tint (*initiate_locality_check)(struct device *, struct hdcp_port_data *, struct hdcp2_lc_init *);\n\tint (*verify_lprime)(struct device *, struct hdcp_port_data *, struct hdcp2_lc_send_lprime *);\n\tint (*get_session_key)(struct device *, struct hdcp_port_data *, struct hdcp2_ske_send_eks *);\n\tint (*repeater_check_flow_prepare_ack)(struct device *, struct hdcp_port_data *, struct hdcp2_rep_send_receiverid_list *, struct hdcp2_rep_send_ack *);\n\tint (*verify_mprime)(struct device *, struct hdcp_port_data *, struct hdcp2_rep_stream_ready *);\n\tint (*enable_hdcp_authentication)(struct device *, struct hdcp_port_data *);\n\tint (*close_hdcp_session)(struct device *, struct hdcp_port_data *);\n};\n\nstruct i915_hdcp_comp_master {\n\tstruct device *mei_dev;\n\tconst struct i915_hdcp_component_ops *ops;\n\tstruct mutex mutex;\n};\n\nstruct i915_params {\n\tchar *vbt_firmware;\n\tint modeset;\n\tint lvds_channel_mode;\n\tint panel_use_ssc;\n\tint vbt_sdvo_panel_type;\n\tint enable_dc;\n\tint enable_fbc;\n\tint enable_psr;\n\tint disable_power_well;\n\tint enable_ips;\n\tint invert_brightness;\n\tint enable_guc;\n\tint guc_log_level;\n\tchar *guc_firmware_path;\n\tchar *huc_firmware_path;\n\tchar *dmc_firmware_path;\n\tint mmio_debug;\n\tint edp_vswing;\n\tunsigned int reset;\n\tunsigned int inject_probe_failure;\n\tint fastboot;\n\tint enable_dpcd_backlight;\n\tchar *force_probe;\n\tlong unsigned int fake_lmem_start;\n\tbool enable_hangcheck;\n\tbool load_detect_test;\n\tbool force_reset_modeset_test;\n\tbool error_capture;\n\tbool disable_display;\n\tbool verbose_state_checks;\n\tbool nuclear_pageflip;\n\tbool enable_dp_mst;\n\tbool enable_gvt;\n};\n\ntypedef struct {\n\tu32 reg;\n} i915_reg_t;\n\nenum intel_backlight_type {\n\tINTEL_BACKLIGHT_PMIC = 0,\n\tINTEL_BACKLIGHT_LPSS = 1,\n\tINTEL_BACKLIGHT_DISPLAY_DDI = 2,\n\tINTEL_BACKLIGHT_DSI_DCS = 3,\n\tINTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE = 4,\n\tINTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE = 5,\n};\n\nstruct edp_power_seq {\n\tu16 t1_t3;\n\tu16 t8;\n\tu16 t9;\n\tu16 t10;\n\tu16 t11_t12;\n};\n\nenum mipi_seq {\n\tMIPI_SEQ_END = 0,\n\tMIPI_SEQ_DEASSERT_RESET = 1,\n\tMIPI_SEQ_INIT_OTP = 2,\n\tMIPI_SEQ_DISPLAY_ON = 3,\n\tMIPI_SEQ_DISPLAY_OFF = 4,\n\tMIPI_SEQ_ASSERT_RESET = 5,\n\tMIPI_SEQ_BACKLIGHT_ON = 6,\n\tMIPI_SEQ_BACKLIGHT_OFF = 7,\n\tMIPI_SEQ_TEAR_ON = 8,\n\tMIPI_SEQ_TEAR_OFF = 9,\n\tMIPI_SEQ_POWER_ON = 10,\n\tMIPI_SEQ_POWER_OFF = 11,\n\tMIPI_SEQ_MAX = 12,\n};\n\nstruct mipi_config {\n\tu16 panel_id;\n\tu32 enable_dithering: 1;\n\tu32 rsvd1: 1;\n\tu32 is_bridge: 1;\n\tu32 panel_arch_type: 2;\n\tu32 is_cmd_mode: 1;\n\tu32 video_transfer_mode: 2;\n\tu32 cabc_supported: 1;\n\tu32 pwm_blc: 1;\n\tu32 videomode_color_format: 4;\n\tu32 rotation: 2;\n\tu32 bta_enabled: 1;\n\tu32 rsvd2: 15;\n\tu16 dual_link: 2;\n\tu16 lane_cnt: 2;\n\tu16 pixel_overlap: 3;\n\tu16 rgb_flip: 1;\n\tu16 dl_dcs_cabc_ports: 2;\n\tu16 dl_dcs_backlight_ports: 2;\n\tu16 rsvd3: 4;\n\tu16 rsvd4;\n\tu8 rsvd5;\n\tu32 target_burst_mode_freq;\n\tu32 dsi_ddr_clk;\n\tu32 bridge_ref_clk;\n\tu8 byte_clk_sel: 2;\n\tu8 rsvd6: 6;\n\tu16 dphy_param_valid: 1;\n\tu16 eot_pkt_disabled: 1;\n\tu16 enable_clk_stop: 1;\n\tu16 rsvd7: 13;\n\tu32 hs_tx_timeout;\n\tu32 lp_rx_timeout;\n\tu32 turn_around_timeout;\n\tu32 device_reset_timer;\n\tu32 master_init_timer;\n\tu32 dbi_bw_timer;\n\tu32 lp_byte_clk_val;\n\tu32 prepare_cnt: 6;\n\tu32 rsvd8: 2;\n\tu32 clk_zero_cnt: 8;\n\tu32 trail_cnt: 5;\n\tu32 rsvd9: 3;\n\tu32 exit_zero_cnt: 6;\n\tu32 rsvd10: 2;\n\tu32 clk_lane_switch_cnt;\n\tu32 hl_switch_cnt;\n\tu32 rsvd11[6];\n\tu8 tclk_miss;\n\tu8 tclk_post;\n\tu8 rsvd12;\n\tu8 tclk_pre;\n\tu8 tclk_prepare;\n\tu8 tclk_settle;\n\tu8 tclk_term_enable;\n\tu8 tclk_trail;\n\tu16 tclk_prepare_clkzero;\n\tu8 rsvd13;\n\tu8 td_term_enable;\n\tu8 teot;\n\tu8 ths_exit;\n\tu8 ths_prepare;\n\tu16 ths_prepare_hszero;\n\tu8 rsvd14;\n\tu8 ths_settle;\n\tu8 ths_skip;\n\tu8 ths_trail;\n\tu8 tinit;\n\tu8 tlpx;\n\tu8 rsvd15[3];\n\tu8 panel_enable;\n\tu8 bl_enable;\n\tu8 pwm_enable;\n\tu8 reset_r_n;\n\tu8 pwr_down_r;\n\tu8 stdby_r_n;\n} __attribute__((packed));\n\nstruct mipi_pps_data {\n\tu16 panel_on_delay;\n\tu16 bl_enable_delay;\n\tu16 bl_disable_delay;\n\tu16 panel_off_delay;\n\tu16 panel_power_cycle_delay;\n};\n\nstruct intel_wakeref;\n\nstruct intel_wakeref_ops {\n\tint (*get)(struct intel_wakeref *);\n\tint (*put)(struct intel_wakeref *);\n};\n\nstruct intel_runtime_pm;\n\nstruct intel_wakeref {\n\tatomic_t count;\n\tstruct mutex mutex;\n\tintel_wakeref_t wakeref;\n\tstruct intel_runtime_pm *rpm;\n\tconst struct intel_wakeref_ops *ops;\n\tstruct delayed_work work;\n};\n\nstruct intel_runtime_pm {\n\tatomic_t wakeref_count;\n\tstruct device *kdev;\n\tbool available;\n\tbool suspended;\n\tbool irqs_enabled;\n};\n\nstruct intel_wakeref_auto {\n\tstruct intel_runtime_pm *rpm;\n\tstruct timer_list timer;\n\tintel_wakeref_t wakeref;\n\tspinlock_t lock;\n\trefcount_t count;\n};\n\nenum i915_drm_suspend_mode {\n\tI915_DRM_SUSPEND_IDLE = 0,\n\tI915_DRM_SUSPEND_MEM = 1,\n\tI915_DRM_SUSPEND_HIBERNATE = 2,\n};\n\nenum intel_display_power_domain {\n\tPOWER_DOMAIN_DISPLAY_CORE = 0,\n\tPOWER_DOMAIN_PIPE_A = 1,\n\tPOWER_DOMAIN_PIPE_B = 2,\n\tPOWER_DOMAIN_PIPE_C = 3,\n\tPOWER_DOMAIN_PIPE_D = 4,\n\tPOWER_DOMAIN_PIPE_A_PANEL_FITTER = 5,\n\tPOWER_DOMAIN_PIPE_B_PANEL_FITTER = 6,\n\tPOWER_DOMAIN_PIPE_C_PANEL_FITTER = 7,\n\tPOWER_DOMAIN_PIPE_D_PANEL_FITTER = 8,\n\tPOWER_DOMAIN_TRANSCODER_A = 9,\n\tPOWER_DOMAIN_TRANSCODER_B = 10,\n\tPOWER_DOMAIN_TRANSCODER_C = 11,\n\tPOWER_DOMAIN_TRANSCODER_D = 12,\n\tPOWER_DOMAIN_TRANSCODER_EDP = 13,\n\tPOWER_DOMAIN_TRANSCODER_VDSC_PW2 = 14,\n\tPOWER_DOMAIN_TRANSCODER_DSI_A = 15,\n\tPOWER_DOMAIN_TRANSCODER_DSI_C = 16,\n\tPOWER_DOMAIN_PORT_DDI_A_LANES = 17,\n\tPOWER_DOMAIN_PORT_DDI_B_LANES = 18,\n\tPOWER_DOMAIN_PORT_DDI_C_LANES = 19,\n\tPOWER_DOMAIN_PORT_DDI_D_LANES = 20,\n\tPOWER_DOMAIN_PORT_DDI_E_LANES = 21,\n\tPOWER_DOMAIN_PORT_DDI_F_LANES = 22,\n\tPOWER_DOMAIN_PORT_DDI_G_LANES = 23,\n\tPOWER_DOMAIN_PORT_DDI_H_LANES = 24,\n\tPOWER_DOMAIN_PORT_DDI_I_LANES = 25,\n\tPOWER_DOMAIN_PORT_DDI_A_IO = 26,\n\tPOWER_DOMAIN_PORT_DDI_B_IO = 27,\n\tPOWER_DOMAIN_PORT_DDI_C_IO = 28,\n\tPOWER_DOMAIN_PORT_DDI_D_IO = 29,\n\tPOWER_DOMAIN_PORT_DDI_E_IO = 30,\n\tPOWER_DOMAIN_PORT_DDI_F_IO = 31,\n\tPOWER_DOMAIN_PORT_DDI_G_IO = 32,\n\tPOWER_DOMAIN_PORT_DDI_H_IO = 33,\n\tPOWER_DOMAIN_PORT_DDI_I_IO = 34,\n\tPOWER_DOMAIN_PORT_DSI = 35,\n\tPOWER_DOMAIN_PORT_CRT = 36,\n\tPOWER_DOMAIN_PORT_OTHER = 37,\n\tPOWER_DOMAIN_VGA = 38,\n\tPOWER_DOMAIN_AUDIO = 39,\n\tPOWER_DOMAIN_AUX_A = 40,\n\tPOWER_DOMAIN_AUX_B = 41,\n\tPOWER_DOMAIN_AUX_C = 42,\n\tPOWER_DOMAIN_AUX_D = 43,\n\tPOWER_DOMAIN_AUX_E = 44,\n\tPOWER_DOMAIN_AUX_F = 45,\n\tPOWER_DOMAIN_AUX_G = 46,\n\tPOWER_DOMAIN_AUX_H = 47,\n\tPOWER_DOMAIN_AUX_I = 48,\n\tPOWER_DOMAIN_AUX_IO_A = 49,\n\tPOWER_DOMAIN_AUX_C_TBT = 50,\n\tPOWER_DOMAIN_AUX_D_TBT = 51,\n\tPOWER_DOMAIN_AUX_E_TBT = 52,\n\tPOWER_DOMAIN_AUX_F_TBT = 53,\n\tPOWER_DOMAIN_AUX_G_TBT = 54,\n\tPOWER_DOMAIN_AUX_H_TBT = 55,\n\tPOWER_DOMAIN_AUX_I_TBT = 56,\n\tPOWER_DOMAIN_GMBUS = 57,\n\tPOWER_DOMAIN_MODESET = 58,\n\tPOWER_DOMAIN_GT_IRQ = 59,\n\tPOWER_DOMAIN_DPLL_DC_OFF = 60,\n\tPOWER_DOMAIN_TC_COLD_OFF = 61,\n\tPOWER_DOMAIN_INIT = 62,\n\tPOWER_DOMAIN_NUM = 63,\n};\n\nenum i915_power_well_id {\n\tDISP_PW_ID_NONE = 0,\n\tVLV_DISP_PW_DISP2D = 1,\n\tBXT_DISP_PW_DPIO_CMN_A = 2,\n\tVLV_DISP_PW_DPIO_CMN_BC = 3,\n\tGLK_DISP_PW_DPIO_CMN_C = 4,\n\tCHV_DISP_PW_DPIO_CMN_D = 5,\n\tHSW_DISP_PW_GLOBAL = 6,\n\tSKL_DISP_PW_MISC_IO = 7,\n\tSKL_DISP_PW_1 = 8,\n\tSKL_DISP_PW_2 = 9,\n\tICL_DISP_PW_3 = 10,\n\tSKL_DISP_DC_OFF = 11,\n};\n\nstruct drm_i915_private;\n\nstruct i915_power_well;\n\nstruct i915_power_well_ops {\n\tvoid (*sync_hw)(struct drm_i915_private *, struct i915_power_well *);\n\tvoid (*enable)(struct drm_i915_private *, struct i915_power_well *);\n\tvoid (*disable)(struct drm_i915_private *, struct i915_power_well *);\n\tbool (*is_enabled)(struct drm_i915_private *, struct i915_power_well *);\n};\n\ntypedef u8 intel_engine_mask_t;\n\nenum intel_platform {\n\tINTEL_PLATFORM_UNINITIALIZED = 0,\n\tINTEL_I830 = 1,\n\tINTEL_I845G = 2,\n\tINTEL_I85X = 3,\n\tINTEL_I865G = 4,\n\tINTEL_I915G = 5,\n\tINTEL_I915GM = 6,\n\tINTEL_I945G = 7,\n\tINTEL_I945GM = 8,\n\tINTEL_G33 = 9,\n\tINTEL_PINEVIEW = 10,\n\tINTEL_I965G = 11,\n\tINTEL_I965GM = 12,\n\tINTEL_G45 = 13,\n\tINTEL_GM45 = 14,\n\tINTEL_IRONLAKE = 15,\n\tINTEL_SANDYBRIDGE = 16,\n\tINTEL_IVYBRIDGE = 17,\n\tINTEL_VALLEYVIEW = 18,\n\tINTEL_HASWELL = 19,\n\tINTEL_BROADWELL = 20,\n\tINTEL_CHERRYVIEW = 21,\n\tINTEL_SKYLAKE = 22,\n\tINTEL_BROXTON = 23,\n\tINTEL_KABYLAKE = 24,\n\tINTEL_GEMINILAKE = 25,\n\tINTEL_COFFEELAKE = 26,\n\tINTEL_CANNONLAKE = 27,\n\tINTEL_ICELAKE = 28,\n\tINTEL_ELKHARTLAKE = 29,\n\tINTEL_TIGERLAKE = 30,\n\tINTEL_MAX_PLATFORMS = 31,\n};\n\nenum intel_ppgtt_type {\n\tINTEL_PPGTT_NONE = 0,\n\tINTEL_PPGTT_ALIASING = 1,\n\tINTEL_PPGTT_FULL = 2,\n};\n\nstruct color_luts {\n\tu32 degamma_lut_size;\n\tu32 gamma_lut_size;\n\tu32 degamma_lut_tests;\n\tu32 gamma_lut_tests;\n};\n\nstruct intel_device_info {\n\tu16 gen_mask;\n\tu8 gen;\n\tu8 gt;\n\tintel_engine_mask_t engine_mask;\n\tenum intel_platform platform;\n\tunsigned int dma_mask_size;\n\tenum intel_ppgtt_type ppgtt_type;\n\tunsigned int ppgtt_size;\n\tunsigned int page_sizes;\n\tu32 memory_regions;\n\tu32 display_mmio_offset;\n\tu8 pipe_mask;\n\tu8 cpu_transcoder_mask;\n\tu8 is_mobile: 1;\n\tu8 is_lp: 1;\n\tu8 require_force_probe: 1;\n\tu8 is_dgfx: 1;\n\tu8 has_64bit_reloc: 1;\n\tu8 gpu_reset_clobbers_display: 1;\n\tu8 has_reset_engine: 1;\n\tu8 has_fpga_dbg: 1;\n\tu8 has_global_mocs: 1;\n\tu8 has_gt_uc: 1;\n\tu8 has_l3_dpf: 1;\n\tu8 has_llc: 1;\n\tu8 has_logical_ring_contexts: 1;\n\tu8 has_logical_ring_elsq: 1;\n\tu8 has_logical_ring_preemption: 1;\n\tu8 has_pooled_eu: 1;\n\tu8 has_rc6: 1;\n\tu8 has_rc6p: 1;\n\tu8 has_rps: 1;\n\tu8 has_runtime_pm: 1;\n\tu8 has_snoop: 1;\n\tu8 has_coherent_ggtt: 1;\n\tu8 unfenced_needs_alignment: 1;\n\tu8 hws_needs_physical: 1;\n\tstruct {\n\t\tu8 cursor_needs_physical: 1;\n\t\tu8 has_csr: 1;\n\t\tu8 has_ddi: 1;\n\t\tu8 has_dp_mst: 1;\n\t\tu8 has_dsb: 1;\n\t\tu8 has_dsc: 1;\n\t\tu8 has_fbc: 1;\n\t\tu8 has_gmch: 1;\n\t\tu8 has_hdcp: 1;\n\t\tu8 has_hotplug: 1;\n\t\tu8 has_ipc: 1;\n\t\tu8 has_modular_fia: 1;\n\t\tu8 has_overlay: 1;\n\t\tu8 has_psr: 1;\n\t\tu8 overlay_needs_physical: 1;\n\t\tu8 supports_tv: 1;\n\t} display;\n\tu16 ddb_size;\n\tu8 num_supported_dbuf_slices;\n\tint pipe_offsets[7];\n\tint trans_offsets[7];\n\tint cursor_offsets[4];\n\tstruct color_luts color;\n};\n\nstruct sseu_dev_info {\n\tu8 slice_mask;\n\tu8 subslice_mask[6];\n\tu8 eu_mask[96];\n\tu16 eu_total;\n\tu8 eu_per_subslice;\n\tu8 min_eu_in_pool;\n\tu8 subslice_7eu[3];\n\tu8 has_slice_pg: 1;\n\tu8 has_subslice_pg: 1;\n\tu8 has_eu_pg: 1;\n\tu8 max_slices;\n\tu8 max_subslices;\n\tu8 max_eus_per_subslice;\n\tu8 ss_stride;\n\tu8 eu_stride;\n};\n\nstruct intel_runtime_info {\n\tu32 platform_mask[2];\n\tu16 device_id;\n\tu8 num_sprites[4];\n\tu8 num_scalers[4];\n\tu8 num_engines;\n\tstruct sseu_dev_info sseu;\n\tu32 rawclk_freq;\n\tu32 cs_timestamp_frequency_hz;\n\tu32 cs_timestamp_period_ns;\n\tu8 vdbox_sfc_access;\n};\n\nstruct intel_driver_caps {\n\tunsigned int scheduler;\n\tbool has_logical_contexts: 1;\n};\n\nenum forcewake_domains {\n\tFORCEWAKE_RENDER = 1,\n\tFORCEWAKE_BLITTER = 2,\n\tFORCEWAKE_MEDIA = 4,\n\tFORCEWAKE_MEDIA_VDBOX0 = 8,\n\tFORCEWAKE_MEDIA_VDBOX1 = 16,\n\tFORCEWAKE_MEDIA_VDBOX2 = 32,\n\tFORCEWAKE_MEDIA_VDBOX3 = 64,\n\tFORCEWAKE_MEDIA_VEBOX0 = 128,\n\tFORCEWAKE_MEDIA_VEBOX1 = 256,\n\tFORCEWAKE_ALL = 511,\n};\n\nstruct intel_uncore;\n\nstruct intel_uncore_funcs {\n\tvoid (*force_wake_get)(struct intel_uncore *, enum forcewake_domains);\n\tvoid (*force_wake_put)(struct intel_uncore *, enum forcewake_domains);\n\tenum forcewake_domains (*read_fw_domains)(struct intel_uncore *, i915_reg_t);\n\tenum forcewake_domains (*write_fw_domains)(struct intel_uncore *, i915_reg_t);\n\tu8 (*mmio_readb)(struct intel_uncore *, i915_reg_t, bool);\n\tu16 (*mmio_readw)(struct intel_uncore *, i915_reg_t, bool);\n\tu32 (*mmio_readl)(struct intel_uncore *, i915_reg_t, bool);\n\tu64 (*mmio_readq)(struct intel_uncore *, i915_reg_t, bool);\n\tvoid (*mmio_writeb)(struct intel_uncore *, i915_reg_t, u8, bool);\n\tvoid (*mmio_writew)(struct intel_uncore *, i915_reg_t, u16, bool);\n\tvoid (*mmio_writel)(struct intel_uncore *, i915_reg_t, u32, bool);\n};\n\nstruct intel_forcewake_range;\n\nstruct intel_uncore_forcewake_domain;\n\nstruct intel_uncore_mmio_debug;\n\nstruct intel_uncore {\n\tvoid *regs;\n\tstruct drm_i915_private *i915;\n\tstruct intel_runtime_pm *rpm;\n\tspinlock_t lock;\n\tunsigned int flags;\n\tconst struct intel_forcewake_range *fw_domains_table;\n\tunsigned int fw_domains_table_entries;\n\tstruct notifier_block pmic_bus_access_nb;\n\tstruct intel_uncore_funcs funcs;\n\tunsigned int fifo_count;\n\tenum forcewake_domains fw_domains;\n\tenum forcewake_domains fw_domains_active;\n\tenum forcewake_domains fw_domains_timer;\n\tenum forcewake_domains fw_domains_saved;\n\tstruct intel_uncore_forcewake_domain *fw_domain[9];\n\tunsigned int user_forcewake_count;\n\tstruct intel_uncore_mmio_debug *debug;\n};\n\nstruct intel_uncore_mmio_debug {\n\tspinlock_t lock;\n\tint unclaimed_mmio_check;\n\tint saved_mmio_check;\n\tu32 suspend_count;\n};\n\nstruct i915_virtual_gpu {\n\tstruct mutex lock;\n\tbool active;\n\tu32 caps;\n};\n\nstruct intel_gvt;\n\nstruct intel_wopcm {\n\tu32 size;\n\tstruct {\n\t\tu32 base;\n\t\tu32 size;\n\t} guc;\n};\n\nstruct intel_csr {\n\tstruct work_struct work;\n\tconst char *fw_path;\n\tu32 required_version;\n\tu32 max_fw_size;\n\tu32 *dmc_payload;\n\tu32 dmc_fw_size;\n\tu32 version;\n\tu32 mmio_count;\n\ti915_reg_t mmioaddr[20];\n\tu32 mmiodata[20];\n\tu32 dc_state;\n\tu32 target_dc_state;\n\tu32 allowed_dc_mask;\n\tintel_wakeref_t wakeref;\n};\n\nstruct intel_gmbus {\n\tstruct i2c_adapter adapter;\n\tu32 force_bit;\n\tu32 reg0;\n\ti915_reg_t gpio_reg;\n\tstruct i2c_algo_bit_data bit_algo;\n\tstruct drm_i915_private *dev_priv;\n};\n\nstruct i915_hotplug {\n\tstruct delayed_work hotplug_work;\n\tconst u32 *hpd;\n\tconst u32 *pch_hpd;\n\tstruct {\n\t\tlong unsigned int last_jiffies;\n\t\tint count;\n\t\tenum {\n\t\t\tHPD_ENABLED = 0,\n\t\t\tHPD_DISABLED = 1,\n\t\t\tHPD_MARK_DISABLED = 2,\n\t\t} state;\n\t} stats[13];\n\tu32 event_bits;\n\tu32 retry_bits;\n\tstruct delayed_work reenable_work;\n\tu32 long_port_mask;\n\tu32 short_port_mask;\n\tstruct work_struct dig_port_work;\n\tstruct work_struct poll_init_work;\n\tbool poll_enabled;\n\tunsigned int hpd_storm_threshold;\n\tu8 hpd_short_storm_enabled;\n\tstruct workqueue_struct *dp_wq;\n};\n\nstruct intel_fbc_state_cache {\n\tstruct {\n\t\tunsigned int mode_flags;\n\t\tu32 hsw_bdw_pixel_rate;\n\t} crtc;\n\tstruct {\n\t\tunsigned int rotation;\n\t\tint src_w;\n\t\tint src_h;\n\t\tbool visible;\n\t\tint adjusted_x;\n\t\tint adjusted_y;\n\t\tu16 pixel_blend_mode;\n\t} plane;\n\tstruct {\n\t\tconst struct drm_format_info *format;\n\t\tunsigned int stride;\n\t\tu64 modifier;\n\t} fb;\n\tunsigned int fence_y_offset;\n\tu16 gen9_wa_cfb_stride;\n\ts8 fence_id;\n};\n\nstruct intel_fbc_reg_params {\n\tstruct {\n\t\tenum pipe pipe;\n\t\tenum i9xx_plane_id i9xx_plane;\n\t} crtc;\n\tstruct {\n\t\tconst struct drm_format_info *format;\n\t\tunsigned int stride;\n\t\tu64 modifier;\n\t} fb;\n\tint cfb_size;\n\tunsigned int fence_y_offset;\n\tu16 gen9_wa_cfb_stride;\n\ts8 fence_id;\n\tbool plane_visible;\n};\n\nstruct intel_crtc;\n\nstruct intel_fbc {\n\tstruct mutex lock;\n\tunsigned int threshold;\n\tunsigned int possible_framebuffer_bits;\n\tunsigned int busy_bits;\n\tstruct intel_crtc *crtc;\n\tstruct drm_mm_node compressed_fb;\n\tstruct drm_mm_node *compressed_llb;\n\tbool false_color;\n\tbool active;\n\tbool activated;\n\tbool flip_pending;\n\tbool underrun_detected;\n\tstruct work_struct underrun_work;\n\tstruct intel_fbc_state_cache state_cache;\n\tstruct intel_fbc_reg_params params;\n\tconst char *no_fbc_reason;\n};\n\nenum drrs_refresh_rate_type {\n\tDRRS_HIGH_RR = 0,\n\tDRRS_LOW_RR = 1,\n\tDRRS_MAX_RR = 2,\n};\n\nenum drrs_support_type {\n\tDRRS_NOT_SUPPORTED = 0,\n\tSTATIC_DRRS_SUPPORT = 1,\n\tSEAMLESS_DRRS_SUPPORT = 2,\n};\n\nstruct intel_dp;\n\nstruct i915_drrs {\n\tstruct mutex mutex;\n\tstruct delayed_work work;\n\tstruct intel_dp *dp;\n\tunsigned int busy_frontbuffer_bits;\n\tenum drrs_refresh_rate_type refresh_rate_type;\n\tenum drrs_support_type type;\n};\n\nstruct opregion_header;\n\nstruct opregion_acpi;\n\nstruct opregion_swsci;\n\nstruct opregion_asle;\n\nstruct intel_opregion {\n\tstruct opregion_header *header;\n\tstruct opregion_acpi *acpi;\n\tstruct opregion_swsci *swsci;\n\tu32 swsci_gbda_sub_functions;\n\tu32 swsci_sbcb_sub_functions;\n\tstruct opregion_asle *asle;\n\tvoid *rvda;\n\tvoid *vbt_firmware;\n\tconst void *vbt;\n\tu32 vbt_size;\n\tu32 *lid_state;\n\tstruct work_struct asle_work;\n\tstruct notifier_block acpi_notifier;\n};\n\nenum psr_lines_to_wait {\n\tPSR_0_LINES_TO_WAIT = 0,\n\tPSR_1_LINE_TO_WAIT = 1,\n\tPSR_4_LINES_TO_WAIT = 2,\n\tPSR_8_LINES_TO_WAIT = 3,\n};\n\nstruct child_device_config;\n\nstruct ddi_vbt_port_info {\n\tconst struct child_device_config *child;\n\tint max_tmds_clock;\n\tu8 hdmi_level_shift;\n\tu8 hdmi_level_shift_set: 1;\n\tu8 supports_dvi: 1;\n\tu8 supports_hdmi: 1;\n\tu8 supports_dp: 1;\n\tu8 supports_edp: 1;\n\tu8 supports_typec_usb: 1;\n\tu8 supports_tbt: 1;\n\tu8 alternate_aux_channel;\n\tu8 alternate_ddc_pin;\n\tu8 dp_boost_level;\n\tu8 hdmi_boost_level;\n\tint dp_max_link_rate;\n};\n\nstruct sdvo_device_mapping {\n\tu8 initialized;\n\tu8 dvo_port;\n\tu8 slave_addr;\n\tu8 dvo_wiring;\n\tu8 i2c_pin;\n\tu8 ddc_pin;\n};\n\nstruct intel_vbt_data {\n\tstruct drm_display_mode *lfp_lvds_vbt_mode;\n\tstruct drm_display_mode *sdvo_lvds_vbt_mode;\n\tunsigned int int_tv_support: 1;\n\tunsigned int lvds_dither: 1;\n\tunsigned int int_crt_support: 1;\n\tunsigned int lvds_use_ssc: 1;\n\tunsigned int int_lvds_support: 1;\n\tunsigned int display_clock_mode: 1;\n\tunsigned int fdi_rx_polarity_inverted: 1;\n\tunsigned int panel_type: 4;\n\tint lvds_ssc_freq;\n\tunsigned int bios_lvds_val;\n\tenum drm_panel_orientation orientation;\n\tenum drrs_support_type drrs_type;\n\tstruct {\n\t\tint rate;\n\t\tint lanes;\n\t\tint preemphasis;\n\t\tint vswing;\n\t\tbool low_vswing;\n\t\tbool initialized;\n\t\tint bpp;\n\t\tstruct edp_power_seq pps;\n\t} edp;\n\tstruct {\n\t\tbool enable;\n\t\tbool full_link;\n\t\tbool require_aux_wakeup;\n\t\tint idle_frames;\n\t\tenum psr_lines_to_wait lines_to_wait;\n\t\tint tp1_wakeup_time_us;\n\t\tint tp2_tp3_wakeup_time_us;\n\t\tint psr2_tp2_tp3_wakeup_time_us;\n\t} psr;\n\tstruct {\n\t\tu16 pwm_freq_hz;\n\t\tbool present;\n\t\tbool active_low_pwm;\n\t\tu8 min_brightness;\n\t\tu8 controller;\n\t\tenum intel_backlight_type type;\n\t} backlight;\n\tstruct {\n\t\tu16 panel_id;\n\t\tstruct mipi_config *config;\n\t\tstruct mipi_pps_data *pps;\n\t\tu16 bl_ports;\n\t\tu16 cabc_ports;\n\t\tu8 seq_version;\n\t\tu32 size;\n\t\tu8 *data;\n\t\tconst u8 *sequence[12];\n\t\tu8 *deassert_seq;\n\t\tenum drm_panel_orientation orientation;\n\t} dsi;\n\tint crt_ddc_pin;\n\tstruct list_head display_devices;\n\tstruct ddi_vbt_port_info ddi_port_info[9];\n\tstruct sdvo_device_mapping sdvo_mappings[2];\n};\n\nstruct intel_cdclk_config {\n\tunsigned int cdclk;\n\tunsigned int vco;\n\tunsigned int ref;\n\tunsigned int bypass;\n\tu8 voltage_level;\n};\n\nstruct intel_crtc_state;\n\nstruct intel_cdclk_state;\n\nstruct intel_initial_plane_config;\n\nstruct intel_encoder;\n\nstruct drm_i915_display_funcs {\n\tvoid (*get_cdclk)(struct drm_i915_private *, struct intel_cdclk_config *);\n\tvoid (*set_cdclk)(struct drm_i915_private *, const struct intel_cdclk_config *, enum pipe);\n\tint (*get_fifo_size)(struct drm_i915_private *, enum i9xx_plane_id);\n\tint (*compute_pipe_wm)(struct intel_crtc_state *);\n\tint (*compute_intermediate_wm)(struct intel_crtc_state *);\n\tvoid (*initial_watermarks)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*atomic_update_watermarks)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*optimize_watermarks)(struct intel_atomic_state *, struct intel_crtc *);\n\tint (*compute_global_watermarks)(struct intel_atomic_state *);\n\tvoid (*update_wm)(struct intel_crtc *);\n\tint (*modeset_calc_cdclk)(struct intel_cdclk_state *);\n\tu8 (*calc_voltage_level)(int);\n\tbool (*get_pipe_config)(struct intel_crtc *, struct intel_crtc_state *);\n\tvoid (*get_initial_plane_config)(struct intel_crtc *, struct intel_initial_plane_config *);\n\tint (*crtc_compute_clock)(struct intel_crtc *, struct intel_crtc_state *);\n\tvoid (*crtc_enable)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*crtc_disable)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*commit_modeset_enables)(struct intel_atomic_state *);\n\tvoid (*commit_modeset_disables)(struct intel_atomic_state *);\n\tvoid (*audio_codec_enable)(struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*audio_codec_disable)(struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*fdi_link_train)(struct intel_crtc *, const struct intel_crtc_state *);\n\tvoid (*init_clock_gating)(struct drm_i915_private *);\n\tvoid (*hpd_irq_setup)(struct drm_i915_private *);\n\tint (*color_check)(struct intel_crtc_state *);\n\tvoid (*color_commit)(const struct intel_crtc_state *);\n\tvoid (*load_luts)(const struct intel_crtc_state *);\n\tvoid (*read_luts)(struct intel_crtc_state *);\n};\n\nenum intel_pch {\n\tPCH_NOP = 4294967295,\n\tPCH_NONE = 0,\n\tPCH_IBX = 1,\n\tPCH_CPT = 2,\n\tPCH_LPT = 3,\n\tPCH_SPT = 4,\n\tPCH_CNP = 5,\n\tPCH_ICP = 6,\n\tPCH_JSP = 7,\n\tPCH_MCC = 8,\n\tPCH_TGP = 9,\n};\n\nstruct i915_page_dma {\n\tstruct page *page;\n\tunion {\n\t\tdma_addr_t daddr;\n\t\tu32 ggtt_offset;\n\t};\n};\n\nstruct i915_page_scratch {\n\tstruct i915_page_dma base;\n\tu64 encode;\n};\n\nstruct pagestash {\n\tspinlock_t lock;\n\tstruct pagevec pvec;\n};\n\nenum i915_cache_level {\n\tI915_CACHE_NONE = 0,\n\tI915_CACHE_LLC = 1,\n\tI915_CACHE_L3_LLC = 2,\n\tI915_CACHE_WT = 3,\n};\n\nstruct i915_vma;\n\nstruct i915_vma_ops {\n\tint (*bind_vma)(struct i915_vma *, enum i915_cache_level, u32);\n\tvoid (*unbind_vma)(struct i915_vma *);\n\tint (*set_pages)(struct i915_vma *);\n\tvoid (*clear_pages)(struct i915_vma *);\n};\n\nstruct intel_gt;\n\nstruct drm_i915_file_private;\n\nstruct i915_address_space {\n\tstruct kref ref;\n\tstruct rcu_work rcu;\n\tstruct drm_mm mm;\n\tstruct intel_gt *gt;\n\tstruct drm_i915_private *i915;\n\tstruct device *dma;\n\tstruct drm_i915_file_private *file;\n\tu64 total;\n\tu64 reserved;\n\tunsigned int bind_async_flags;\n\tatomic_t open;\n\tstruct mutex mutex;\n\tstruct i915_page_scratch scratch[4];\n\tunsigned int scratch_order;\n\tunsigned int top;\n\tstruct list_head bound_list;\n\tstruct pagestash free_pages;\n\tbool is_ggtt: 1;\n\tbool pt_kmap_wc: 1;\n\tbool has_read_only: 1;\n\tu64 (*pte_encode)(dma_addr_t, enum i915_cache_level, u32);\n\tint (*allocate_va_range)(struct i915_address_space *, u64, u64);\n\tvoid (*clear_range)(struct i915_address_space *, u64, u64);\n\tvoid (*insert_page)(struct i915_address_space *, dma_addr_t, u64, enum i915_cache_level, u32);\n\tvoid (*insert_entries)(struct i915_address_space *, struct i915_vma *, enum i915_cache_level, u32);\n\tvoid (*cleanup)(struct i915_address_space *);\n\tstruct i915_vma_ops vma_ops;\n};\n\nstruct i915_ppgtt;\n\nstruct i915_fence_reg;\n\nstruct i915_ggtt {\n\tstruct i915_address_space vm;\n\tstruct io_mapping iomap;\n\tstruct resource gmadr;\n\tresource_size_t mappable_end;\n\tvoid *gsm;\n\tvoid (*invalidate)(struct i915_ggtt *);\n\tstruct i915_ppgtt *alias;\n\tbool do_idle_maps;\n\tint mtrr;\n\tu32 bit_6_swizzle_x;\n\tu32 bit_6_swizzle_y;\n\tu32 pin_bias;\n\tunsigned int num_fences;\n\tstruct i915_fence_reg *fence_regs;\n\tstruct list_head fence_list;\n\tstruct list_head userfault_list;\n\tstruct intel_wakeref_auto userfault_wakeref;\n\tstruct mutex error_mutex;\n\tstruct drm_mm_node error_capture;\n\tstruct drm_mm_node uc_fw;\n};\n\nstruct intel_memory_region;\n\nstruct i915_gem_mm {\n\tstruct drm_mm stolen;\n\tstruct mutex stolen_lock;\n\tspinlock_t obj_lock;\n\tstruct list_head purge_list;\n\tstruct list_head shrink_list;\n\tstruct llist_head free_list;\n\tstruct work_struct free_work;\n\tatomic_t free_count;\n\tstruct pagestash wc_stash;\n\tstruct vfsmount *gemfs;\n\tstruct intel_memory_region *regions[3];\n\tstruct notifier_block oom_notifier;\n\tstruct notifier_block vmap_notifier;\n\tstruct shrinker shrinker;\n\tstruct workqueue_struct *userptr_wq;\n\tu64 shrink_memory;\n\tu32 shrink_count;\n};\n\nstruct dpll_info;\n\nstruct intel_shared_dpll {\n\tstruct intel_shared_dpll_state state;\n\tunsigned int active_mask;\n\tbool on;\n\tconst struct dpll_info *info;\n\tintel_wakeref_t wakeref;\n};\n\nstruct i915_wa;\n\nstruct i915_wa_list {\n\tconst char *name;\n\tconst char *engine_name;\n\tstruct i915_wa *list;\n\tunsigned int count;\n\tunsigned int wa_count;\n};\n\nstruct i915_frontbuffer_tracking {\n\tspinlock_t lock;\n\tunsigned int busy_bits;\n\tunsigned int flip_bits;\n};\n\nstruct intel_atomic_helper {\n\tstruct llist_head free_list;\n\tstruct work_struct free_work;\n};\n\nstruct intel_l3_parity {\n\tu32 *remap_info[2];\n\tstruct work_struct error_work;\n\tint which_slice;\n};\n\nstruct i915_power_domains {\n\tbool initializing;\n\tbool display_core_suspended;\n\tint power_well_count;\n\tintel_wakeref_t wakeref;\n\tstruct mutex lock;\n\tint domain_use_count[63];\n\tstruct delayed_work async_put_work;\n\tintel_wakeref_t async_put_wakeref;\n\tu64 async_put_domains[2];\n\tstruct i915_power_well *power_wells;\n};\n\nstruct i915_psr {\n\tstruct mutex lock;\n\tu32 debug;\n\tbool sink_support;\n\tbool enabled;\n\tstruct intel_dp *dp;\n\tenum pipe pipe;\n\tenum transcoder transcoder;\n\tbool active;\n\tstruct work_struct work;\n\tunsigned int busy_frontbuffer_bits;\n\tbool sink_psr2_support;\n\tbool link_standby;\n\tbool colorimetry_support;\n\tbool psr2_enabled;\n\tu8 sink_sync_latency;\n\tktime_t last_entry_attempt;\n\tktime_t last_exit;\n\tbool sink_not_reliable;\n\tbool irq_aux_error;\n\tu16 su_x_granularity;\n\tbool dc3co_enabled;\n\tu32 dc3co_exit_delay;\n\tstruct delayed_work dc3co_work;\n\tbool force_mode_changed;\n\tstruct drm_dp_vsc_sdp vsc;\n};\n\nstruct i915_gpu_coredump;\n\nstruct i915_gpu_error {\n\tspinlock_t lock;\n\tstruct i915_gpu_coredump *first_error;\n\tatomic_t pending_fb_pin;\n\tatomic_t reset_count;\n\tatomic_t reset_engine_count[8];\n};\n\nstruct i915_suspend_saved_registers {\n\tu32 saveDSPARB;\n\tu32 saveFBC_CONTROL;\n\tu32 saveCACHE_MODE_0;\n\tu32 saveMI_ARB_STATE;\n\tu32 saveSWF0[16];\n\tu32 saveSWF1[16];\n\tu32 saveSWF3[3];\n\tu32 savePCH_PORT_HOTPLUG;\n\tu16 saveGCDGMBUS;\n};\n\nenum intel_ddb_partitioning {\n\tINTEL_DDB_PART_1_2 = 0,\n\tINTEL_DDB_PART_5_6 = 1,\n};\n\nstruct ilk_wm_values {\n\tu32 wm_pipe[3];\n\tu32 wm_lp[3];\n\tu32 wm_lp_spr[3];\n\tbool enable_fbc_wm;\n\tenum intel_ddb_partitioning partitioning;\n};\n\nstruct g4x_pipe_wm {\n\tu16 plane[8];\n\tu16 fbc;\n};\n\nstruct g4x_sr_wm {\n\tu16 plane;\n\tu16 cursor;\n\tu16 fbc;\n};\n\nstruct vlv_wm_ddl_values {\n\tu8 plane[8];\n};\n\nstruct vlv_wm_values {\n\tstruct g4x_pipe_wm pipe[3];\n\tstruct g4x_sr_wm sr;\n\tstruct vlv_wm_ddl_values ddl[3];\n\tu8 level;\n\tbool cxsr;\n};\n\nstruct g4x_wm_values {\n\tstruct g4x_pipe_wm pipe[2];\n\tstruct g4x_sr_wm sr;\n\tstruct g4x_sr_wm hpll;\n\tbool cxsr;\n\tbool hpll_en;\n\tbool fbc_en;\n};\n\nenum intel_dram_type {\n\tINTEL_DRAM_UNKNOWN = 0,\n\tINTEL_DRAM_DDR3 = 1,\n\tINTEL_DRAM_DDR4 = 2,\n\tINTEL_DRAM_LPDDR3 = 3,\n\tINTEL_DRAM_LPDDR4 = 4,\n};\n\nstruct dram_info {\n\tbool valid;\n\tbool is_16gb_dimm;\n\tu8 num_channels;\n\tu8 ranks;\n\tu32 bandwidth_kbps;\n\tbool symmetric_memory;\n\tenum intel_dram_type type;\n};\n\nstruct intel_bw_info {\n\tunsigned int deratedbw[8];\n\tu8 num_qgv_points;\n\tu8 num_planes;\n};\n\nstruct intel_sseu {\n\tu8 slice_mask;\n\tu8 subslice_mask;\n\tu8 min_eus_per_subslice;\n\tu8 max_eus_per_subslice;\n};\n\nstruct i915_perf;\n\nstruct i915_perf_stream;\n\nstruct i915_active;\n\nstruct i915_oa_ops {\n\tbool (*is_valid_b_counter_reg)(struct i915_perf *, u32);\n\tbool (*is_valid_mux_reg)(struct i915_perf *, u32);\n\tbool (*is_valid_flex_reg)(struct i915_perf *, u32);\n\tint (*enable_metric_set)(struct i915_perf_stream *, struct i915_active *);\n\tvoid (*disable_metric_set)(struct i915_perf_stream *);\n\tvoid (*oa_enable)(struct i915_perf_stream *);\n\tvoid (*oa_disable)(struct i915_perf_stream *);\n\tint (*read)(struct i915_perf_stream *, char *, size_t, size_t *);\n\tu32 (*oa_hw_tail_read)(struct i915_perf_stream *);\n};\n\nstruct i915_oa_format;\n\nstruct i915_perf {\n\tstruct drm_i915_private *i915;\n\tstruct kobject *metrics_kobj;\n\tstruct mutex metrics_lock;\n\tstruct idr metrics_idr;\n\tstruct mutex lock;\n\tstruct i915_perf_stream *exclusive_stream;\n\tstruct intel_sseu sseu;\n\tstruct ratelimit_state spurious_report_rs;\n\tstruct ratelimit_state tail_pointer_race;\n\tu32 gen7_latched_oastatus1;\n\tu32 ctx_oactxctrl_offset;\n\tu32 ctx_flexeu0_offset;\n\tu32 gen8_valid_ctx_bit;\n\tstruct i915_oa_ops ops;\n\tconst struct i915_oa_format *oa_formats;\n\tatomic64_t noa_programming_delay;\n};\n\nenum intel_uc_fw_type {\n\tINTEL_UC_FW_TYPE_GUC = 0,\n\tINTEL_UC_FW_TYPE_HUC = 1,\n};\n\nenum intel_uc_fw_status {\n\tINTEL_UC_FIRMWARE_NOT_SUPPORTED = 4294967295,\n\tINTEL_UC_FIRMWARE_UNINITIALIZED = 0,\n\tINTEL_UC_FIRMWARE_DISABLED = 1,\n\tINTEL_UC_FIRMWARE_SELECTED = 2,\n\tINTEL_UC_FIRMWARE_MISSING = 3,\n\tINTEL_UC_FIRMWARE_ERROR = 4,\n\tINTEL_UC_FIRMWARE_AVAILABLE = 5,\n\tINTEL_UC_FIRMWARE_LOADABLE = 6,\n\tINTEL_UC_FIRMWARE_FAIL = 7,\n\tINTEL_UC_FIRMWARE_TRANSFERRED = 8,\n\tINTEL_UC_FIRMWARE_RUNNING = 9,\n};\n\nstruct drm_i915_gem_object;\n\nstruct intel_uc_fw {\n\tenum intel_uc_fw_type type;\n\tunion {\n\t\tconst enum intel_uc_fw_status status;\n\t\tenum intel_uc_fw_status __status;\n\t};\n\tconst char *path;\n\tbool user_overridden;\n\tsize_t size;\n\tstruct drm_i915_gem_object *obj;\n\tu16 major_ver_wanted;\n\tu16 minor_ver_wanted;\n\tu16 major_ver_found;\n\tu16 minor_ver_found;\n\tu32 rsa_size;\n\tu32 ucode_size;\n};\n\nstruct intel_guc_log {\n\tu32 level;\n\tstruct i915_vma *vma;\n\tstruct {\n\t\tvoid *buf_addr;\n\t\tbool started;\n\t\tstruct work_struct flush_work;\n\t\tstruct rchan *channel;\n\t\tstruct mutex lock;\n\t\tu32 full_count;\n\t} relay;\n\tstruct {\n\t\tu32 sampled_overflow;\n\t\tu32 overflow;\n\t\tu32 flush;\n\t} stats[3];\n};\n\nstruct guc_ct_buffer_desc;\n\nstruct intel_guc_ct_buffer {\n\tstruct guc_ct_buffer_desc *desc;\n\tu32 *cmds;\n};\n\nstruct intel_guc_ct {\n\tstruct i915_vma *vma;\n\tbool enabled;\n\tstruct intel_guc_ct_buffer ctbs[2];\n\tstruct {\n\t\tu32 last_fence;\n\t\tspinlock_t lock;\n\t\tstruct list_head pending;\n\t\tstruct list_head incoming;\n\t\tstruct work_struct worker;\n\t} requests;\n};\n\nstruct __guc_ads_blob;\n\nstruct intel_guc {\n\tstruct intel_uc_fw fw;\n\tstruct intel_guc_log log;\n\tstruct intel_guc_ct ct;\n\tspinlock_t irq_lock;\n\tunsigned int msg_enabled_mask;\n\tstruct {\n\t\tbool enabled;\n\t\tvoid (*reset)(struct intel_guc *);\n\t\tvoid (*enable)(struct intel_guc *);\n\t\tvoid (*disable)(struct intel_guc *);\n\t} interrupts;\n\tbool submission_selected;\n\tstruct i915_vma *ads_vma;\n\tstruct __guc_ads_blob *ads_blob;\n\tstruct i915_vma *stage_desc_pool;\n\tvoid *stage_desc_pool_vaddr;\n\tstruct i915_vma *workqueue;\n\tvoid *workqueue_vaddr;\n\tspinlock_t wq_lock;\n\tstruct i915_vma *proc_desc;\n\tvoid *proc_desc_vaddr;\n\tu32 params[14];\n\tstruct {\n\t\tu32 base;\n\t\tunsigned int count;\n\t\tenum forcewake_domains fw_domains;\n\t} send_regs;\n\ti915_reg_t notify_reg;\n\tu32 mmio_msg;\n\tstruct mutex send_mutex;\n};\n\nstruct intel_huc {\n\tstruct intel_uc_fw fw;\n\tstruct i915_vma *rsa_data;\n\tstruct {\n\t\ti915_reg_t reg;\n\t\tu32 mask;\n\t\tu32 value;\n\t} status;\n};\n\nstruct intel_uc_ops;\n\nstruct intel_uc {\n\tconst struct intel_uc_ops *ops;\n\tstruct intel_guc guc;\n\tstruct intel_huc huc;\n\tstruct drm_i915_gem_object *load_err_log;\n};\n\nstruct intel_gt_timelines {\n\tspinlock_t lock;\n\tstruct list_head active_list;\n\tspinlock_t hwsp_lock;\n\tstruct list_head hwsp_free_list;\n};\n\nstruct intel_gt_requests {\n\tstruct delayed_work retire_work;\n};\n\nstruct intel_reset {\n\tlong unsigned int flags;\n\tstruct mutex mutex;\n\twait_queue_head_t queue;\n\tstruct srcu_struct backoff_srcu;\n};\n\nstruct intel_llc {};\n\nstruct intel_rc6 {\n\tu64 prev_hw_residency[4];\n\tu64 cur_residency[4];\n\tu32 ctl_enable;\n\tstruct drm_i915_gem_object *pctx;\n\tbool supported: 1;\n\tbool enabled: 1;\n\tbool manual: 1;\n\tbool wakeref: 1;\n};\n\nstruct intel_rps_ei {\n\tktime_t ktime;\n\tu32 render_c0;\n\tu32 media_c0;\n};\n\nstruct intel_ips {\n\tu64 last_count1;\n\tlong unsigned int last_time1;\n\tlong unsigned int chipset_power;\n\tu64 last_count2;\n\tu64 last_time2;\n\tlong unsigned int gfx_power;\n\tu8 corr;\n\tint c;\n\tint m;\n};\n\nstruct intel_rps {\n\tstruct mutex lock;\n\tstruct timer_list timer;\n\tstruct work_struct work;\n\tlong unsigned int flags;\n\tktime_t pm_timestamp;\n\tu32 pm_interval;\n\tu32 pm_iir;\n\tu32 pm_intrmsk_mbz;\n\tu32 pm_events;\n\tu8 cur_freq;\n\tu8 last_freq;\n\tu8 min_freq_softlimit;\n\tu8 max_freq_softlimit;\n\tu8 max_freq;\n\tu8 min_freq;\n\tu8 boost_freq;\n\tu8 idle_freq;\n\tu8 efficient_freq;\n\tu8 rp1_freq;\n\tu8 rp0_freq;\n\tu16 gpll_ref_freq;\n\tint last_adj;\n\tstruct {\n\t\tstruct mutex mutex;\n\t\tenum {\n\t\t\tLOW_POWER = 0,\n\t\t\tBETWEEN = 1,\n\t\t\tHIGH_POWER = 2,\n\t\t} mode;\n\t\tunsigned int interactive;\n\t\tu8 up_threshold;\n\t\tu8 down_threshold;\n\t} power;\n\tatomic_t num_waiters;\n\tatomic_t boosts;\n\tstruct intel_rps_ei ei;\n\tstruct intel_ips ips;\n};\n\nstruct intel_gt_buffer_pool {\n\tspinlock_t lock;\n\tstruct list_head cache_list[4];\n\tstruct delayed_work work;\n};\n\nstruct intel_engine_cs;\n\nstruct intel_gt {\n\tstruct drm_i915_private *i915;\n\tstruct intel_uncore *uncore;\n\tstruct i915_ggtt *ggtt;\n\tstruct intel_uc uc;\n\tstruct intel_gt_timelines timelines;\n\tstruct intel_gt_requests requests;\n\tstruct intel_wakeref wakeref;\n\tatomic_t user_wakeref;\n\tstruct list_head closed_vma;\n\tspinlock_t closed_lock;\n\tktime_t last_init_time;\n\tstruct intel_reset reset;\n\tintel_wakeref_t awake;\n\tu32 clock_frequency;\n\tstruct intel_llc llc;\n\tstruct intel_rc6 rc6;\n\tstruct intel_rps rps;\n\tspinlock_t irq_lock;\n\tu32 gt_imr;\n\tu32 pm_ier;\n\tu32 pm_imr;\n\tu32 pm_guc_events;\n\tstruct intel_engine_cs *engine[8];\n\tstruct intel_engine_cs *engine_class[20];\n\tstruct i915_address_space *vm;\n\tstruct intel_gt_buffer_pool buffer_pool;\n\tstruct i915_vma *scratch;\n};\n\nstruct i915_gem_contexts {\n\tspinlock_t lock;\n\tstruct list_head list;\n\tstruct llist_head free_list;\n\tstruct work_struct free_work;\n};\n\nstruct i915_pmu_sample {\n\tu64 cur;\n};\n\nstruct i915_pmu {\n\tstruct {\n\t\tstruct hlist_node node;\n\t\tenum cpuhp_state slot;\n\t} cpuhp;\n\tstruct pmu base;\n\tconst char *name;\n\tspinlock_t lock;\n\tstruct hrtimer timer;\n\tu64 enable;\n\tktime_t timer_last;\n\tunsigned int enable_count[20];\n\tbool timer_enabled;\n\tstruct i915_pmu_sample sample[4];\n\tktime_t sleep_last;\n\tstruct attribute_group events_attr_group;\n\tvoid *i915_attr;\n\tvoid *pmu_attr;\n};\n\nstruct intel_overlay;\n\nstruct intel_cdclk_vals;\n\nstruct intel_dpll_mgr;\n\nstruct intel_fbdev;\n\nstruct i915_audio_component;\n\nstruct vlv_s0ix_state;\n\nstruct drm_i915_private {\n\tstruct drm_device drm;\n\tbool do_release;\n\tconst struct intel_device_info __info;\n\tstruct intel_runtime_info __runtime;\n\tstruct intel_driver_caps caps;\n\tstruct resource dsm;\n\tstruct resource dsm_reserved;\n\tresource_size_t stolen_usable_size;\n\tstruct intel_uncore uncore;\n\tstruct intel_uncore_mmio_debug mmio_debug;\n\tstruct i915_virtual_gpu vgpu;\n\tstruct intel_gvt *gvt;\n\tstruct intel_wopcm wopcm;\n\tstruct intel_csr csr;\n\tstruct intel_gmbus gmbus[15];\n\tstruct mutex gmbus_mutex;\n\tu32 gpio_mmio_base;\n\tu32 hsw_psr_mmio_adjust;\n\tu32 mipi_mmio_base;\n\tu32 pps_mmio_base;\n\twait_queue_head_t gmbus_wait_queue;\n\tstruct pci_dev *bridge_dev;\n\tstruct rb_root uabi_engines;\n\tstruct resource mch_res;\n\tspinlock_t irq_lock;\n\tbool display_irqs_enabled;\n\tstruct pm_qos_request pm_qos;\n\tstruct mutex sb_lock;\n\tstruct pm_qos_request sb_qos;\n\tunion {\n\t\tu32 irq_mask;\n\t\tu32 de_irq_mask[4];\n\t};\n\tu32 pipestat_irq_mask[4];\n\tstruct i915_hotplug hotplug;\n\tstruct intel_fbc fbc;\n\tstruct i915_drrs drrs;\n\tstruct intel_opregion opregion;\n\tstruct intel_vbt_data vbt;\n\tbool preserve_bios_swizzle;\n\tstruct intel_overlay *overlay;\n\tstruct mutex backlight_lock;\n\tstruct mutex pps_mutex;\n\tunsigned int fsb_freq;\n\tunsigned int mem_freq;\n\tunsigned int is_ddr3;\n\tunsigned int skl_preferred_vco_freq;\n\tunsigned int max_cdclk_freq;\n\tunsigned int max_dotclk_freq;\n\tunsigned int hpll_freq;\n\tunsigned int fdi_pll_freq;\n\tunsigned int czclk_freq;\n\tstruct {\n\t\tstruct intel_cdclk_config hw;\n\t\tconst struct intel_cdclk_vals *table;\n\t\tstruct intel_global_obj obj;\n\t} cdclk;\n\tstruct workqueue_struct *wq;\n\tstruct workqueue_struct *modeset_wq;\n\tstruct workqueue_struct *flip_wq;\n\tstruct drm_i915_display_funcs display;\n\tenum intel_pch pch_type;\n\tshort unsigned int pch_id;\n\tlong unsigned int quirks;\n\tstruct drm_atomic_state *modeset_restore_state;\n\tstruct drm_modeset_acquire_ctx reset_ctx;\n\tstruct i915_ggtt ggtt;\n\tstruct i915_gem_mm mm;\n\tstruct hlist_head mm_structs[128];\n\tstruct mutex mm_lock;\n\tstruct intel_crtc *plane_to_crtc_mapping[4];\n\tstruct intel_crtc *pipe_to_crtc_mapping[4];\n\tstruct {\n\t\tstruct mutex lock;\n\t\tint num_shared_dpll;\n\t\tstruct intel_shared_dpll shared_dplls[9];\n\t\tconst struct intel_dpll_mgr *mgr;\n\t\tstruct {\n\t\t\tint nssc;\n\t\t\tint ssc;\n\t\t} ref_clks;\n\t} dpll;\n\tstruct list_head global_obj_list;\n\tu8 active_pipes;\n\tint dpio_phy_iosf_port[2];\n\tstruct i915_wa_list gt_wa_list;\n\tstruct i915_frontbuffer_tracking fb_tracking;\n\tstruct intel_atomic_helper atomic_helper;\n\tbool mchbar_need_disable;\n\tstruct intel_l3_parity l3_parity;\n\tu32 edram_size_mb;\n\tstruct i915_power_domains power_domains;\n\tstruct i915_psr psr;\n\tstruct i915_gpu_error gpu_error;\n\tstruct drm_i915_gem_object *vlv_pctx;\n\tstruct intel_fbdev *fbdev;\n\tstruct work_struct fbdev_suspend_work;\n\tstruct drm_property *broadcast_rgb_property;\n\tstruct drm_property *force_audio_property;\n\tstruct i915_audio_component *audio_component;\n\tbool audio_component_registered;\n\tstruct mutex av_mutex;\n\tint audio_power_refcount;\n\tu32 audio_freq_cntrl;\n\tu32 fdi_rx_config;\n\tu32 chv_phy_control;\n\tu32 chv_dpll_md[4];\n\tu32 bxt_phy_grc;\n\tu32 suspend_count;\n\tbool power_domains_suspended;\n\tstruct i915_suspend_saved_registers regfile;\n\tstruct vlv_s0ix_state *vlv_s0ix_state;\n\tenum {\n\t\tI915_SAGV_UNKNOWN = 0,\n\t\tI915_SAGV_DISABLED = 1,\n\t\tI915_SAGV_ENABLED = 2,\n\t\tI915_SAGV_NOT_CONTROLLED = 3,\n\t} sagv_status;\n\tu32 sagv_block_time_us;\n\tstruct {\n\t\tu16 pri_latency[5];\n\t\tu16 spr_latency[5];\n\t\tu16 cur_latency[5];\n\t\tu16 skl_latency[8];\n\t\tunion {\n\t\t\tstruct ilk_wm_values hw;\n\t\t\tstruct vlv_wm_values vlv;\n\t\t\tstruct g4x_wm_values g4x;\n\t\t};\n\t\tu8 max_level;\n\t\tstruct mutex wm_mutex;\n\t\tbool distrust_bios_wm;\n\t} wm;\n\tu8 enabled_dbuf_slices_mask;\n\tstruct dram_info dram_info;\n\tstruct intel_bw_info max_bw[6];\n\tstruct intel_global_obj bw_obj;\n\tstruct intel_runtime_pm runtime_pm;\n\tstruct i915_perf perf;\n\tstruct intel_gt gt;\n\tstruct {\n\t\tstruct i915_gem_contexts contexts;\n\t\tstruct file *mmap_singleton;\n\t} gem;\n\tu8 pch_ssc_use;\n\tu8 vblank_enabled;\n\tbool chv_phy_assert[2];\n\tbool ipc_enabled;\n\tstruct intel_encoder *av_enc_map[4];\n\tstruct {\n\t\tstruct platform_device *platdev;\n\t\tint irq;\n\t} lpe_audio;\n\tstruct i915_pmu pmu;\n\tstruct i915_hdcp_comp_master *hdcp_master;\n\tbool hdcp_comp_added;\n\tstruct mutex hdcp_comp_mutex;\n};\n\nstruct i915_power_well_desc;\n\nstruct i915_power_well {\n\tconst struct i915_power_well_desc *desc;\n\tint count;\n\tbool hw_enabled;\n};\n\nstruct i915_power_well_regs {\n\ti915_reg_t bios;\n\ti915_reg_t driver;\n\ti915_reg_t kvmr;\n\ti915_reg_t debug;\n};\n\nstruct i915_power_well_desc {\n\tconst char *name;\n\tbool always_on;\n\tu64 domains;\n\tenum i915_power_well_id id;\n\tunion {\n\t\tstruct {\n\t\t\tu8 idx;\n\t\t} vlv;\n\t\tstruct {\n\t\t\tenum dpio_phy phy;\n\t\t} bxt;\n\t\tstruct {\n\t\t\tconst struct i915_power_well_regs *regs;\n\t\t\tu8 idx;\n\t\t\tu8 irq_pipe_mask;\n\t\t\tbool has_vga: 1;\n\t\t\tbool has_fuses: 1;\n\t\t\tbool is_tc_tbt: 1;\n\t\t} hsw;\n\t};\n\tconst struct i915_power_well_ops *ops;\n};\n\nenum intel_dpll_id {\n\tDPLL_ID_PRIVATE = 4294967295,\n\tDPLL_ID_PCH_PLL_A = 0,\n\tDPLL_ID_PCH_PLL_B = 1,\n\tDPLL_ID_WRPLL1 = 0,\n\tDPLL_ID_WRPLL2 = 1,\n\tDPLL_ID_SPLL = 2,\n\tDPLL_ID_LCPLL_810 = 3,\n\tDPLL_ID_LCPLL_1350 = 4,\n\tDPLL_ID_LCPLL_2700 = 5,\n\tDPLL_ID_SKL_DPLL0 = 0,\n\tDPLL_ID_SKL_DPLL1 = 1,\n\tDPLL_ID_SKL_DPLL2 = 2,\n\tDPLL_ID_SKL_DPLL3 = 3,\n\tDPLL_ID_ICL_DPLL0 = 0,\n\tDPLL_ID_ICL_DPLL1 = 1,\n\tDPLL_ID_EHL_DPLL4 = 2,\n\tDPLL_ID_ICL_TBTPLL = 2,\n\tDPLL_ID_ICL_MGPLL1 = 3,\n\tDPLL_ID_ICL_MGPLL2 = 4,\n\tDPLL_ID_ICL_MGPLL3 = 5,\n\tDPLL_ID_ICL_MGPLL4 = 6,\n\tDPLL_ID_TGL_MGPLL5 = 7,\n\tDPLL_ID_TGL_MGPLL6 = 8,\n};\n\nenum icl_port_dpll_id {\n\tICL_PORT_DPLL_DEFAULT = 0,\n\tICL_PORT_DPLL_MG_PHY = 1,\n\tICL_PORT_DPLL_COUNT = 2,\n};\n\nstruct intel_shared_dpll_funcs {\n\tvoid (*prepare)(struct drm_i915_private *, struct intel_shared_dpll *);\n\tvoid (*enable)(struct drm_i915_private *, struct intel_shared_dpll *);\n\tvoid (*disable)(struct drm_i915_private *, struct intel_shared_dpll *);\n\tbool (*get_hw_state)(struct drm_i915_private *, struct intel_shared_dpll *, struct intel_dpll_hw_state *);\n\tint (*get_freq)(struct drm_i915_private *, const struct intel_shared_dpll *);\n};\n\nstruct dpll_info {\n\tconst char *name;\n\tconst struct intel_shared_dpll_funcs *funcs;\n\tenum intel_dpll_id id;\n\tu32 flags;\n};\n\nenum dsb_id {\n\tINVALID_DSB = 4294967295,\n\tDSB1 = 0,\n\tDSB2 = 1,\n\tDSB3 = 2,\n\tMAX_DSB_PER_PIPE = 3,\n};\n\nstruct intel_dsb {\n\tlong int refcount;\n\tenum dsb_id id;\n\tu32 *cmd_buf;\n\tstruct i915_vma *vma;\n\tint free_pos;\n\tu32 ins_start_offset;\n};\n\nstruct i915_page_sizes {\n\tunsigned int phys;\n\tunsigned int sg;\n\tunsigned int gtt;\n};\n\nstruct i915_active_fence {\n\tstruct dma_fence *fence;\n\tstruct dma_fence_cb cb;\n};\n\nstruct active_node;\n\nstruct i915_active {\n\tatomic_t count;\n\tstruct mutex mutex;\n\tspinlock_t tree_lock;\n\tstruct active_node *cache;\n\tstruct rb_root tree;\n\tstruct i915_active_fence excl;\n\tlong unsigned int flags;\n\tint (*active)(struct i915_active *);\n\tvoid (*retire)(struct i915_active *);\n\tstruct work_struct work;\n\tstruct llist_head preallocated_barriers;\n};\n\nenum i915_ggtt_view_type {\n\tI915_GGTT_VIEW_NORMAL = 0,\n\tI915_GGTT_VIEW_ROTATED = 32,\n\tI915_GGTT_VIEW_PARTIAL = 12,\n\tI915_GGTT_VIEW_REMAPPED = 36,\n};\n\nstruct intel_partial_info {\n\tu64 offset;\n\tunsigned int size;\n} __attribute__((packed));\n\nstruct intel_remapped_plane_info {\n\tunsigned int width;\n\tunsigned int height;\n\tunsigned int stride;\n\tunsigned int offset;\n};\n\nstruct intel_rotation_info {\n\tstruct intel_remapped_plane_info plane[2];\n};\n\nstruct intel_remapped_info {\n\tstruct intel_remapped_plane_info plane[2];\n\tunsigned int unused_mbz;\n};\n\nstruct i915_ggtt_view {\n\tenum i915_ggtt_view_type type;\n\tunion {\n\t\tstruct intel_partial_info partial;\n\t\tstruct intel_rotation_info rotated;\n\t\tstruct intel_remapped_info remapped;\n\t};\n} __attribute__((packed));\n\nstruct i915_mmap_offset;\n\nstruct i915_vma {\n\tstruct drm_mm_node node;\n\tstruct i915_address_space *vm;\n\tconst struct i915_vma_ops *ops;\n\tstruct drm_i915_gem_object *obj;\n\tstruct dma_resv *resv;\n\tstruct sg_table *pages;\n\tvoid *iomap;\n\tvoid *private;\n\tstruct i915_fence_reg *fence;\n\tu64 size;\n\tu64 display_alignment;\n\tstruct i915_page_sizes page_sizes;\n\tstruct i915_mmap_offset *mmo;\n\tu32 fence_size;\n\tu32 fence_alignment;\n\tstruct kref ref;\n\tatomic_t open_count;\n\tatomic_t flags;\n\tstruct i915_active active;\n\tatomic_t pages_count;\n\tstruct mutex pages_mutex;\n\tstruct i915_ggtt_view ggtt_view;\n\tstruct list_head vm_link;\n\tstruct list_head obj_link;\n\tstruct rb_node obj_node;\n\tstruct hlist_node obj_hash;\n\tstruct list_head evict_link;\n\tstruct list_head closed_link;\n};\n\nenum {\n\t__I915_SAMPLE_FREQ_ACT = 0,\n\t__I915_SAMPLE_FREQ_REQ = 1,\n\t__I915_SAMPLE_RC6 = 2,\n\t__I915_SAMPLE_RC6_LAST_REPORTED = 3,\n\t__I915_NUM_PMU_SAMPLERS = 4,\n};\n\nstruct i915_priolist {\n\tstruct list_head requests[1];\n\tstruct rb_node node;\n\tlong unsigned int used;\n\tint priority;\n};\n\nstruct i915_syncmap;\n\nstruct intel_timeline_cacheline;\n\nstruct intel_timeline {\n\tu64 fence_context;\n\tu32 seqno;\n\tstruct mutex mutex;\n\tatomic_t pin_count;\n\tatomic_t active_count;\n\tconst u32 *hwsp_seqno;\n\tstruct i915_vma *hwsp_ggtt;\n\tu32 hwsp_offset;\n\tstruct intel_timeline_cacheline *hwsp_cacheline;\n\tbool has_initial_breadcrumb;\n\tstruct list_head requests;\n\tstruct i915_active_fence last_request;\n\tstruct intel_timeline *retire;\n\tstruct i915_syncmap *sync;\n\tstruct list_head link;\n\tstruct intel_gt *gt;\n\tstruct kref kref;\n\tstruct callback_head rcu;\n};\n\nstruct intel_timeline_hwsp;\n\nstruct intel_timeline_cacheline {\n\tstruct i915_active active;\n\tstruct intel_timeline_hwsp *hwsp;\n\tvoid *vaddr;\n\tstruct callback_head rcu;\n};\n\nstruct i915_wa {\n\ti915_reg_t reg;\n\tu32 clr;\n\tu32 set;\n\tu32 read;\n};\n\nstruct intel_hw_status_page {\n\tstruct i915_vma *vma;\n\tu32 *addr;\n};\n\nstruct intel_instdone {\n\tu32 instdone;\n\tu32 slice_common;\n\tu32 slice_common_extra[2];\n\tu32 sampler[24];\n\tu32 row[24];\n};\n\nstruct i915_wa_ctx_bb {\n\tu32 offset;\n\tu32 size;\n};\n\nstruct i915_ctx_workarounds {\n\tstruct i915_wa_ctx_bb indirect_ctx;\n\tstruct i915_wa_ctx_bb per_ctx;\n\tstruct i915_vma *vma;\n};\n\nenum intel_engine_id {\n\tRCS0 = 0,\n\tBCS0 = 1,\n\tVCS0 = 2,\n\tVCS1 = 3,\n\tVCS2 = 4,\n\tVCS3 = 5,\n\tVECS0 = 6,\n\tVECS1 = 7,\n\tI915_NUM_ENGINES = 8,\n};\n\nstruct ewma__engine_latency {\n\tlong unsigned int internal;\n};\n\nstruct i915_request;\n\nstruct intel_engine_execlists {\n\tstruct tasklet_struct tasklet;\n\tstruct timer_list timer;\n\tstruct timer_list preempt;\n\tstruct i915_priolist default_priolist;\n\tu32 ccid;\n\tu32 yield;\n\tu32 error_interrupt;\n\tu32 reset_ccid;\n\tbool no_priolist;\n\tu32 *submit_reg;\n\tu32 *ctrl_reg;\n\tstruct i915_request * const *active;\n\tstruct i915_request *inflight[3];\n\tstruct i915_request *pending[3];\n\tunsigned int port_mask;\n\tint switch_priority_hint;\n\tint queue_priority_hint;\n\tstruct rb_root_cached queue;\n\tstruct rb_root_cached virtual;\n\tu32 *csb_write;\n\tu32 *csb_status;\n\tu8 csb_size;\n\tu8 csb_head;\n};\n\nstruct i915_sw_dma_fence_cb {\n\tstruct dma_fence_cb base;\n\tstruct i915_sw_fence *fence;\n};\n\nstruct i915_request_duration_cb {\n\tstruct dma_fence_cb cb;\n\tktime_t emitted;\n};\n\nstruct i915_sched_attr {\n\tint priority;\n};\n\nstruct i915_sched_node {\n\tstruct list_head signalers_list;\n\tstruct list_head waiters_list;\n\tstruct list_head link;\n\tstruct i915_sched_attr attr;\n\tunsigned int flags;\n\tintel_engine_mask_t semaphores;\n};\n\nstruct i915_dependency {\n\tstruct i915_sched_node *signaler;\n\tstruct i915_sched_node *waiter;\n\tstruct list_head signal_link;\n\tstruct list_head wait_link;\n\tstruct list_head dfs_link;\n\tlong unsigned int flags;\n};\n\nstruct intel_context;\n\nstruct intel_ring;\n\nstruct i915_capture_list;\n\nstruct i915_request {\n\tstruct dma_fence fence;\n\tspinlock_t lock;\n\tstruct drm_i915_private *i915;\n\tstruct intel_engine_cs *engine;\n\tstruct intel_context *context;\n\tstruct intel_ring *ring;\n\tstruct intel_timeline *timeline;\n\tstruct list_head signal_link;\n\tlong unsigned int rcustate;\n\tstruct pin_cookie cookie;\n\tstruct i915_sw_fence submit;\n\tunion {\n\t\twait_queue_entry_t submitq;\n\t\tstruct i915_sw_dma_fence_cb dmaq;\n\t\tstruct i915_request_duration_cb duration;\n\t};\n\tstruct list_head execute_cb;\n\tstruct i915_sw_fence semaphore;\n\tstruct i915_sched_node sched;\n\tstruct i915_dependency dep;\n\tintel_engine_mask_t execution_mask;\n\tconst u32 *hwsp_seqno;\n\tstruct intel_timeline_cacheline *hwsp_cacheline;\n\tu32 head;\n\tu32 infix;\n\tu32 postfix;\n\tu32 tail;\n\tu32 wa_tail;\n\tu32 reserved_space;\n\tstruct i915_vma *batch;\n\tstruct i915_capture_list *capture_list;\n\tlong unsigned int emitted_jiffies;\n\tstruct list_head link;\n\tstruct drm_i915_file_private *file_priv;\n\tstruct list_head client_link;\n};\n\nstruct intel_ring {\n\tstruct kref ref;\n\tstruct i915_vma *vma;\n\tvoid *vaddr;\n\tatomic_t pin_count;\n\tu32 head;\n\tu32 tail;\n\tu32 emit;\n\tu32 space;\n\tu32 size;\n\tu32 wrap;\n\tu32 effective_size;\n};\n\nstruct intel_breadcrumbs {\n\tspinlock_t irq_lock;\n\tstruct list_head signalers;\n\tstruct list_head signaled_requests;\n\tstruct irq_work irq_work;\n\tunsigned int irq_enabled;\n\tbool irq_armed;\n};\n\nstruct intel_engine_pmu {\n\tu32 enable;\n\tunsigned int enable_count[3];\n\tstruct i915_pmu_sample sample[3];\n};\n\nstruct intel_context_ops;\n\nstruct drm_i915_reg_table;\n\nstruct intel_engine_cs {\n\tstruct drm_i915_private *i915;\n\tstruct intel_gt *gt;\n\tstruct intel_uncore *uncore;\n\tchar name[8];\n\tenum intel_engine_id id;\n\tenum intel_engine_id legacy_idx;\n\tunsigned int hw_id;\n\tunsigned int guc_id;\n\tintel_engine_mask_t mask;\n\tu8 class;\n\tu8 instance;\n\tu16 uabi_class;\n\tu16 uabi_instance;\n\tu32 uabi_capabilities;\n\tu32 context_size;\n\tu32 mmio_base;\n\tlong unsigned int context_tag;\n\tstruct rb_node uabi_node;\n\tstruct intel_sseu sseu;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head requests;\n\t\tstruct list_head hold;\n\t} active;\n\tstruct i915_request *request_pool;\n\tstruct llist_head barrier_tasks;\n\tstruct intel_context *kernel_context;\n\tintel_engine_mask_t saturated;\n\tstruct {\n\t\tstruct delayed_work work;\n\t\tstruct i915_request *systole;\n\t} heartbeat;\n\tlong unsigned int serial;\n\tlong unsigned int wakeref_serial;\n\tstruct intel_wakeref wakeref;\n\tstruct file *default_state;\n\tstruct {\n\t\tstruct intel_ring *ring;\n\t\tstruct intel_timeline *timeline;\n\t} legacy;\n\tstruct ewma__engine_latency latency;\n\tstruct intel_breadcrumbs breadcrumbs;\n\tstruct intel_engine_pmu pmu;\n\tstruct intel_hw_status_page status_page;\n\tstruct i915_ctx_workarounds wa_ctx;\n\tstruct i915_wa_list ctx_wa_list;\n\tstruct i915_wa_list wa_list;\n\tstruct i915_wa_list whitelist;\n\tu32 irq_keep_mask;\n\tu32 irq_enable_mask;\n\tvoid (*irq_enable)(struct intel_engine_cs *);\n\tvoid (*irq_disable)(struct intel_engine_cs *);\n\tvoid (*sanitize)(struct intel_engine_cs *);\n\tint (*resume)(struct intel_engine_cs *);\n\tstruct {\n\t\tvoid (*prepare)(struct intel_engine_cs *);\n\t\tvoid (*rewind)(struct intel_engine_cs *, bool);\n\t\tvoid (*cancel)(struct intel_engine_cs *);\n\t\tvoid (*finish)(struct intel_engine_cs *);\n\t} reset;\n\tvoid (*park)(struct intel_engine_cs *);\n\tvoid (*unpark)(struct intel_engine_cs *);\n\tvoid (*set_default_submission)(struct intel_engine_cs *);\n\tconst struct intel_context_ops *cops;\n\tint (*request_alloc)(struct i915_request *);\n\tint (*emit_flush)(struct i915_request *, u32);\n\tint (*emit_bb_start)(struct i915_request *, u64, u32, unsigned int);\n\tint (*emit_init_breadcrumb)(struct i915_request *);\n\tu32 * (*emit_fini_breadcrumb)(struct i915_request *, u32 *);\n\tunsigned int emit_fini_breadcrumb_dw;\n\tvoid (*submit_request)(struct i915_request *);\n\tvoid (*bond_execute)(struct i915_request *, struct dma_fence *);\n\tvoid (*schedule)(struct i915_request *, const struct i915_sched_attr *);\n\tvoid (*release)(struct intel_engine_cs *);\n\tstruct intel_engine_execlists execlists;\n\tstruct intel_timeline *retire;\n\tstruct work_struct retire_work;\n\tstruct atomic_notifier_head context_status_notifier;\n\tunsigned int flags;\n\tstruct hlist_head cmd_hash[512];\n\tconst struct drm_i915_reg_table *reg_tables;\n\tint reg_table_count;\n\tu32 (*get_cmd_length_mask)(u32);\n\tstruct {\n\t\tatomic_t active;\n\t\tseqlock_t lock;\n\t\tktime_t total;\n\t\tktime_t start;\n\t\tktime_t rps;\n\t} stats;\n\tstruct {\n\t\tlong unsigned int heartbeat_interval_ms;\n\t\tlong unsigned int max_busywait_duration_ns;\n\t\tlong unsigned int preempt_timeout_ms;\n\t\tlong unsigned int stop_timeout_ms;\n\t\tlong unsigned int timeslice_duration_ms;\n\t} props;\n\tstruct {\n\t\tlong unsigned int heartbeat_interval_ms;\n\t\tlong unsigned int max_busywait_duration_ns;\n\t\tlong unsigned int preempt_timeout_ms;\n\t\tlong unsigned int stop_timeout_ms;\n\t\tlong unsigned int timeslice_duration_ms;\n\t} defaults;\n};\n\nstruct ewma_runtime {\n\tlong unsigned int internal;\n};\n\nstruct i915_gem_context;\n\nstruct intel_context {\n\tstruct kref ref;\n\tstruct intel_engine_cs *engine;\n\tstruct intel_engine_cs *inflight;\n\tstruct i915_address_space *vm;\n\tstruct i915_gem_context *gem_context;\n\tstruct list_head signal_link;\n\tstruct list_head signals;\n\tstruct i915_vma *state;\n\tstruct intel_ring *ring;\n\tstruct intel_timeline *timeline;\n\tlong unsigned int flags;\n\tu32 *lrc_reg_state;\n\tunion {\n\t\tstruct {\n\t\t\tu32 lrca;\n\t\t\tu32 ccid;\n\t\t};\n\t\tu64 desc;\n\t} lrc;\n\tu32 tag;\n\tstruct {\n\t\tstruct ewma_runtime avg;\n\t\tu64 total;\n\t\tu32 last;\n\t} runtime;\n\tunsigned int active_count;\n\tatomic_t pin_count;\n\tstruct mutex pin_mutex;\n\tstruct i915_active active;\n\tconst struct intel_context_ops *ops;\n\tstruct intel_sseu sseu;\n\tu8 wa_bb_page;\n};\n\nstruct intel_context_ops {\n\tint (*alloc)(struct intel_context *);\n\tint (*pin)(struct intel_context *);\n\tvoid (*unpin)(struct intel_context *);\n\tvoid (*enter)(struct intel_context *);\n\tvoid (*exit)(struct intel_context *);\n\tvoid (*reset)(struct intel_context *);\n\tvoid (*destroy)(struct kref *);\n};\n\nstruct drm_i915_reg_descriptor;\n\nstruct drm_i915_reg_table {\n\tconst struct drm_i915_reg_descriptor *regs;\n\tint num_regs;\n};\n\nstruct i915_gem_engines;\n\nstruct i915_gem_context {\n\tstruct drm_i915_private *i915;\n\tstruct drm_i915_file_private *file_priv;\n\tstruct i915_gem_engines *engines;\n\tstruct mutex engines_mutex;\n\tstruct intel_timeline *timeline;\n\tstruct i915_address_space *vm;\n\tstruct pid *pid;\n\tstruct list_head link;\n\tstruct llist_node free_link;\n\tstruct kref ref;\n\tstruct callback_head rcu;\n\tlong unsigned int user_flags;\n\tlong unsigned int flags;\n\tstruct mutex mutex;\n\tstruct i915_sched_attr sched;\n\tatomic_t guilty_count;\n\tatomic_t active_count;\n\tlong unsigned int hang_timestamp[2];\n\tu8 remap_slice;\n\tstruct xarray handles_vma;\n\tchar name[24];\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head engines;\n\t} stale;\n};\n\nstruct i915_gem_engines {\n\tunion {\n\t\tstruct list_head link;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct i915_sw_fence fence;\n\tstruct i915_gem_context *ctx;\n\tunsigned int num_engines;\n\tstruct intel_context *engines[0];\n};\n\nstruct drm_i915_file_private {\n\tstruct drm_i915_private *dev_priv;\n\tunion {\n\t\tstruct drm_file *file;\n\t\tstruct callback_head rcu;\n\t};\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head request_list;\n\t} mm;\n\tstruct xarray context_xa;\n\tstruct xarray vm_xa;\n\tunsigned int bsd_engine;\n\tatomic_t ban_score;\n\tlong unsigned int hang_timestamp;\n};\n\nstruct i915_capture_list {\n\tstruct i915_capture_list *next;\n\tstruct i915_vma *vma;\n};\n\nstruct drm_i915_gem_object_ops {\n\tunsigned int flags;\n\tint (*get_pages)(struct drm_i915_gem_object *);\n\tvoid (*put_pages)(struct drm_i915_gem_object *, struct sg_table *);\n\tvoid (*truncate)(struct drm_i915_gem_object *);\n\tvoid (*writeback)(struct drm_i915_gem_object *);\n\tint (*pwrite)(struct drm_i915_gem_object *, const struct drm_i915_gem_pwrite *);\n\tint (*dmabuf_export)(struct drm_i915_gem_object *);\n\tvoid (*release)(struct drm_i915_gem_object *);\n};\n\nstruct i915_gem_object_page_iter {\n\tstruct scatterlist *sg_pos;\n\tunsigned int sg_idx;\n\tstruct xarray radix;\n\tstruct mutex lock;\n};\n\nstruct i915_mm_struct;\n\nstruct i915_mmu_object;\n\nstruct i915_gem_userptr {\n\tuintptr_t ptr;\n\tstruct i915_mm_struct *mm;\n\tstruct i915_mmu_object *mmu_object;\n\tstruct work_struct *work;\n};\n\nstruct intel_frontbuffer;\n\nstruct drm_i915_gem_object {\n\tstruct drm_gem_object base;\n\tconst struct drm_i915_gem_object_ops *ops;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct list_head list;\n\t\tstruct rb_root tree;\n\t} vma;\n\tstruct list_head lut_list;\n\tstruct drm_mm_node *stolen;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct llist_node freed;\n\t};\n\tunsigned int userfault_count;\n\tstruct list_head userfault_link;\n\tstruct {\n\t\tspinlock_t lock;\n\t\tstruct rb_root offsets;\n\t} mmo;\n\tlong unsigned int flags;\n\tunsigned int cache_level: 3;\n\tunsigned int cache_coherent: 2;\n\tunsigned int cache_dirty: 1;\n\tu16 read_domains;\n\tu16 write_domain;\n\tstruct intel_frontbuffer *frontbuffer;\n\tunsigned int tiling_and_stride;\n\tstruct {\n\t\tstruct mutex lock;\n\t\tatomic_t pages_pin_count;\n\t\tatomic_t shrink_pin;\n\t\tstruct intel_memory_region *region;\n\t\tstruct list_head blocks;\n\t\tstruct list_head region_link;\n\t\tstruct sg_table *pages;\n\t\tvoid *mapping;\n\t\tstruct i915_page_sizes page_sizes;\n\t\tstruct i915_gem_object_page_iter get_page;\n\t\tstruct list_head link;\n\t\tunsigned int madv: 2;\n\t\tbool dirty: 1;\n\t\tbool quirked: 1;\n\t} mm;\n\tlong unsigned int *bit_17;\n\tunion {\n\t\tstruct i915_gem_userptr userptr;\n\t\tlong unsigned int scratch;\n\t\tvoid *gvt_info;\n\t};\n};\n\nenum i915_mmap_type {\n\tI915_MMAP_TYPE_GTT = 0,\n\tI915_MMAP_TYPE_WC = 1,\n\tI915_MMAP_TYPE_WB = 2,\n\tI915_MMAP_TYPE_UC = 3,\n};\n\nstruct i915_mmap_offset {\n\tstruct drm_vma_offset_node vma_node;\n\tstruct drm_i915_gem_object *obj;\n\tenum i915_mmap_type mmap_type;\n\tstruct rb_node offset;\n};\n\nstruct i915_buddy_block;\n\nstruct i915_buddy_mm {\n\tstruct list_head *free_list;\n\tstruct i915_buddy_block **roots;\n\tunsigned int n_roots;\n\tunsigned int max_order;\n\tu64 chunk_size;\n\tu64 size;\n};\n\nstruct intel_memory_region_ops;\n\nstruct intel_memory_region {\n\tstruct drm_i915_private *i915;\n\tconst struct intel_memory_region_ops *ops;\n\tstruct io_mapping iomap;\n\tstruct resource region;\n\tstruct drm_mm_node fake_mappable;\n\tstruct i915_buddy_mm mm;\n\tstruct mutex mm_lock;\n\tstruct kref kref;\n\tresource_size_t io_start;\n\tresource_size_t min_page_size;\n\tresource_size_t total;\n\tresource_size_t avail;\n\tunsigned int type;\n\tunsigned int instance;\n\tunsigned int id;\n\tchar name[8];\n\tdma_addr_t remap_addr;\n\tstruct {\n\t\tstruct mutex lock;\n\t\tstruct list_head list;\n\t\tstruct list_head purgeable;\n\t} objects;\n};\n\nstruct intel_frontbuffer {\n\tstruct kref ref;\n\tatomic_t bits;\n\tstruct i915_active write;\n\tstruct drm_i915_gem_object *obj;\n\tstruct callback_head rcu;\n};\n\nenum forcewake_domain_id {\n\tFW_DOMAIN_ID_RENDER = 0,\n\tFW_DOMAIN_ID_BLITTER = 1,\n\tFW_DOMAIN_ID_MEDIA = 2,\n\tFW_DOMAIN_ID_MEDIA_VDBOX0 = 3,\n\tFW_DOMAIN_ID_MEDIA_VDBOX1 = 4,\n\tFW_DOMAIN_ID_MEDIA_VDBOX2 = 5,\n\tFW_DOMAIN_ID_MEDIA_VDBOX3 = 6,\n\tFW_DOMAIN_ID_MEDIA_VEBOX0 = 7,\n\tFW_DOMAIN_ID_MEDIA_VEBOX1 = 8,\n\tFW_DOMAIN_ID_COUNT = 9,\n};\n\nstruct intel_forcewake_range {\n\tu32 start;\n\tu32 end;\n\tenum forcewake_domains domains;\n};\n\nstruct intel_uncore_forcewake_domain {\n\tstruct intel_uncore *uncore;\n\tenum forcewake_domain_id id;\n\tenum forcewake_domains mask;\n\tunsigned int wake_count;\n\tbool active;\n\tstruct hrtimer timer;\n\tu32 *reg_set;\n\tu32 *reg_ack;\n};\n\nstruct guc_ct_buffer_desc {\n\tu32 addr;\n\tu64 host_private;\n\tu32 size;\n\tu32 head;\n\tu32 tail;\n\tu32 is_in_error;\n\tu32 fence;\n\tu32 status;\n\tu32 owner;\n\tu32 owner_sub_id;\n\tu32 reserved[5];\n} __attribute__((packed));\n\nenum guc_log_buffer_type {\n\tGUC_ISR_LOG_BUFFER = 0,\n\tGUC_DPC_LOG_BUFFER = 1,\n\tGUC_CRASH_DUMP_LOG_BUFFER = 2,\n\tGUC_MAX_LOG_BUFFER = 3,\n};\n\nstruct i915_fence_reg {\n\tstruct list_head link;\n\tstruct i915_ggtt *ggtt;\n\tstruct i915_vma *vma;\n\tatomic_t pin_count;\n\tstruct i915_active active;\n\tint id;\n\tbool dirty;\n\tu32 start;\n\tu32 size;\n\tu32 tiling;\n\tu32 stride;\n};\n\nstruct i915_page_table {\n\tstruct i915_page_dma base;\n\tatomic_t used;\n};\n\nstruct i915_page_directory {\n\tstruct i915_page_table pt;\n\tspinlock_t lock;\n\tvoid *entry[512];\n};\n\nstruct i915_ppgtt {\n\tstruct i915_address_space vm;\n\tstruct i915_page_directory *pd;\n};\n\nstruct intel_uc_ops {\n\tint (*sanitize)(struct intel_uc *);\n\tvoid (*init_fw)(struct intel_uc *);\n\tvoid (*fini_fw)(struct intel_uc *);\n\tint (*init)(struct intel_uc *);\n\tvoid (*fini)(struct intel_uc *);\n\tint (*init_hw)(struct intel_uc *);\n\tvoid (*fini_hw)(struct intel_uc *);\n};\n\nstruct i915_buddy_block {\n\tu64 header;\n\tstruct i915_buddy_block *left;\n\tstruct i915_buddy_block *right;\n\tstruct i915_buddy_block *parent;\n\tvoid *private;\n\tstruct list_head link;\n\tstruct list_head tmp_link;\n};\n\nenum intel_region_id {\n\tINTEL_REGION_SMEM = 0,\n\tINTEL_REGION_LMEM = 1,\n\tINTEL_REGION_STOLEN = 2,\n\tINTEL_REGION_UNKNOWN = 3,\n};\n\nstruct intel_memory_region_ops {\n\tunsigned int flags;\n\tint (*init)(struct intel_memory_region *);\n\tvoid (*release)(struct intel_memory_region *);\n\tstruct drm_i915_gem_object * (*create_object)(struct intel_memory_region *, resource_size_t, unsigned int);\n};\n\nstruct i915_vma_coredump {\n\tstruct i915_vma_coredump *next;\n\tchar name[20];\n\tu64 gtt_offset;\n\tu64 gtt_size;\n\tu32 gtt_page_sizes;\n\tint num_pages;\n\tint page_count;\n\tint unused;\n\tu32 *pages[0];\n};\n\nstruct i915_request_coredump {\n\tlong unsigned int flags;\n\tpid_t pid;\n\tu32 context;\n\tu32 seqno;\n\tu32 head;\n\tu32 tail;\n\tstruct i915_sched_attr sched_attr;\n};\n\nstruct i915_gem_context_coredump {\n\tchar comm[16];\n\tu64 total_runtime;\n\tu32 avg_runtime;\n\tpid_t pid;\n\tint active;\n\tint guilty;\n\tstruct i915_sched_attr sched_attr;\n};\n\nstruct intel_engine_coredump {\n\tconst struct intel_engine_cs *engine;\n\tbool simulated;\n\tu32 reset_count;\n\tu32 rq_head;\n\tu32 rq_post;\n\tu32 rq_tail;\n\tu32 ccid;\n\tu32 start;\n\tu32 tail;\n\tu32 head;\n\tu32 ctl;\n\tu32 mode;\n\tu32 hws;\n\tu32 ipeir;\n\tu32 ipehr;\n\tu32 esr;\n\tu32 bbstate;\n\tu32 instpm;\n\tu32 instps;\n\tu64 bbaddr;\n\tu64 acthd;\n\tu32 fault_reg;\n\tu64 faddr;\n\tu32 rc_psmi;\n\tstruct intel_instdone instdone;\n\tstruct i915_gem_context_coredump context;\n\tstruct i915_vma_coredump *vma;\n\tstruct i915_request_coredump execlist[2];\n\tunsigned int num_ports;\n\tstruct {\n\t\tu32 gfx_mode;\n\t\tunion {\n\t\t\tu64 pdp[4];\n\t\t\tu32 pp_dir_base;\n\t\t};\n\t} vm_info;\n\tstruct intel_engine_coredump *next;\n};\n\nstruct intel_uc_coredump {\n\tstruct intel_uc_fw guc_fw;\n\tstruct intel_uc_fw huc_fw;\n\tstruct i915_vma_coredump *guc_log;\n};\n\nstruct intel_gt_coredump {\n\tconst struct intel_gt *_gt;\n\tbool awake;\n\tbool simulated;\n\tu32 eir;\n\tu32 pgtbl_er;\n\tu32 ier;\n\tu32 gtier[6];\n\tu32 ngtier;\n\tu32 derrmr;\n\tu32 forcewake;\n\tu32 error;\n\tu32 err_int;\n\tu32 fault_data0;\n\tu32 fault_data1;\n\tu32 done_reg;\n\tu32 gac_eco;\n\tu32 gam_ecochk;\n\tu32 gab_ctl;\n\tu32 gfx_mode;\n\tu32 gtt_cache;\n\tu32 aux_err;\n\tu32 sfc_done[4];\n\tu32 gam_done;\n\tu32 nfence;\n\tu64 fence[32];\n\tstruct intel_engine_coredump *engine;\n\tstruct intel_uc_coredump *uc;\n\tstruct intel_gt_coredump *next;\n};\n\nstruct intel_overlay_error_state;\n\nstruct intel_display_error_state;\n\nstruct i915_gpu_coredump {\n\tstruct kref ref;\n\tktime_t time;\n\tktime_t boottime;\n\tktime_t uptime;\n\tlong unsigned int capture;\n\tstruct drm_i915_private *i915;\n\tstruct intel_gt_coredump *gt;\n\tchar error_msg[128];\n\tbool simulated;\n\tbool wakelock;\n\tbool suspended;\n\tint iommu;\n\tu32 reset_count;\n\tu32 suspend_count;\n\tstruct intel_device_info device_info;\n\tstruct intel_runtime_info runtime_info;\n\tstruct intel_driver_caps driver_caps;\n\tstruct i915_params params;\n\tstruct intel_overlay_error_state *overlay;\n\tstruct intel_display_error_state *display;\n\tstruct scatterlist *sgl;\n\tstruct scatterlist *fit;\n};\n\nstruct i915_oa_format {\n\tu32 format;\n\tint size;\n};\n\nstruct i915_oa_reg {\n\ti915_reg_t addr;\n\tu32 value;\n};\n\nstruct i915_oa_config {\n\tstruct i915_perf *perf;\n\tchar uuid[37];\n\tint id;\n\tconst struct i915_oa_reg *mux_regs;\n\tu32 mux_regs_len;\n\tconst struct i915_oa_reg *b_counter_regs;\n\tu32 b_counter_regs_len;\n\tconst struct i915_oa_reg *flex_regs;\n\tu32 flex_regs_len;\n\tstruct attribute_group sysfs_metric;\n\tstruct attribute *attrs[2];\n\tstruct device_attribute sysfs_metric_id;\n\tstruct kref ref;\n\tstruct callback_head rcu;\n};\n\nstruct i915_perf_stream_ops {\n\tvoid (*enable)(struct i915_perf_stream *);\n\tvoid (*disable)(struct i915_perf_stream *);\n\tvoid (*poll_wait)(struct i915_perf_stream *, struct file *, poll_table *);\n\tint (*wait_unlocked)(struct i915_perf_stream *);\n\tint (*read)(struct i915_perf_stream *, char *, size_t, size_t *);\n\tvoid (*destroy)(struct i915_perf_stream *);\n};\n\nstruct i915_perf_stream {\n\tstruct i915_perf *perf;\n\tstruct intel_uncore *uncore;\n\tstruct intel_engine_cs *engine;\n\tu32 sample_flags;\n\tint sample_size;\n\tstruct i915_gem_context *ctx;\n\tbool enabled;\n\tbool hold_preemption;\n\tconst struct i915_perf_stream_ops *ops;\n\tstruct i915_oa_config *oa_config;\n\tstruct llist_head oa_config_bos;\n\tstruct intel_context *pinned_ctx;\n\tu32 specific_ctx_id;\n\tu32 specific_ctx_id_mask;\n\tstruct hrtimer poll_check_timer;\n\twait_queue_head_t poll_wq;\n\tbool pollin;\n\tbool periodic;\n\tint period_exponent;\n\tstruct {\n\t\tstruct i915_vma *vma;\n\t\tu8 *vaddr;\n\t\tu32 last_ctx_id;\n\t\tint format;\n\t\tint format_size;\n\t\tint size_exponent;\n\t\tspinlock_t ptr_lock;\n\t\tu32 aging_tail;\n\t\tu64 aging_timestamp;\n\t\tu32 head;\n\t\tu32 tail;\n\t} oa_buffer;\n\tstruct i915_vma *noa_wait;\n\tu64 poll_oa_period;\n};\n\nenum hpd_pin {\n\tHPD_NONE = 0,\n\tHPD_TV = 0,\n\tHPD_CRT = 1,\n\tHPD_SDVO_B = 2,\n\tHPD_SDVO_C = 3,\n\tHPD_PORT_A = 4,\n\tHPD_PORT_B = 5,\n\tHPD_PORT_C = 6,\n\tHPD_PORT_D = 7,\n\tHPD_PORT_E = 8,\n\tHPD_PORT_F = 9,\n\tHPD_PORT_G = 10,\n\tHPD_PORT_H = 11,\n\tHPD_PORT_I = 12,\n\tHPD_NUM_PINS = 13,\n};\n\nstruct dpll {\n\tint n;\n\tint m1;\n\tint m2;\n\tint p1;\n\tint p2;\n\tint dot;\n\tint vco;\n\tint m;\n\tint p;\n};\n\nstruct icl_port_dpll {\n\tstruct intel_shared_dpll *pll;\n\tstruct intel_dpll_hw_state hw_state;\n};\n\nstruct intel_scaler {\n\tint in_use;\n\tu32 mode;\n};\n\nstruct intel_crtc_scaler_state {\n\tstruct intel_scaler scalers[2];\n\tunsigned int scaler_users;\n\tint scaler_id;\n};\n\nstruct intel_wm_level {\n\tbool enable;\n\tu32 pri_val;\n\tu32 spr_val;\n\tu32 cur_val;\n\tu32 fbc_val;\n};\n\nstruct intel_pipe_wm {\n\tstruct intel_wm_level wm[5];\n\tbool fbc_wm_enabled;\n\tbool pipe_enabled;\n\tbool sprites_enabled;\n\tbool sprites_scaled;\n};\n\nstruct skl_wm_level {\n\tu16 min_ddb_alloc;\n\tu16 plane_res_b;\n\tu8 plane_res_l;\n\tbool plane_en;\n\tbool ignore_lines;\n};\n\nstruct skl_plane_wm {\n\tstruct skl_wm_level wm[8];\n\tstruct skl_wm_level uv_wm[8];\n\tstruct skl_wm_level trans_wm;\n\tstruct skl_wm_level sagv_wm0;\n\tbool is_planar;\n};\n\nstruct skl_pipe_wm {\n\tstruct skl_plane_wm planes[8];\n\tbool use_sagv_wm;\n};\n\nstruct skl_ddb_entry {\n\tu16 start;\n\tu16 end;\n};\n\nstruct vlv_wm_state {\n\tstruct g4x_pipe_wm wm[3];\n\tstruct g4x_sr_wm sr[3];\n\tu8 num_levels;\n\tbool cxsr;\n};\n\nstruct vlv_fifo_state {\n\tu16 plane[8];\n};\n\nstruct g4x_wm_state {\n\tstruct g4x_pipe_wm wm;\n\tstruct g4x_sr_wm sr;\n\tstruct g4x_sr_wm hpll;\n\tbool cxsr;\n\tbool hpll_en;\n\tbool fbc_en;\n};\n\nstruct intel_crtc_wm_state {\n\tunion {\n\t\tstruct {\n\t\t\tstruct intel_pipe_wm intermediate;\n\t\t\tstruct intel_pipe_wm optimal;\n\t\t} ilk;\n\t\tstruct {\n\t\t\tstruct skl_pipe_wm optimal;\n\t\t\tstruct skl_ddb_entry ddb;\n\t\t\tstruct skl_ddb_entry plane_ddb_y[8];\n\t\t\tstruct skl_ddb_entry plane_ddb_uv[8];\n\t\t} skl;\n\t\tstruct {\n\t\t\tstruct g4x_pipe_wm raw[3];\n\t\t\tstruct vlv_wm_state intermediate;\n\t\t\tstruct vlv_wm_state optimal;\n\t\t\tstruct vlv_fifo_state fifo_state;\n\t\t} vlv;\n\t\tstruct {\n\t\t\tstruct g4x_pipe_wm raw[3];\n\t\t\tstruct g4x_wm_state intermediate;\n\t\t\tstruct g4x_wm_state optimal;\n\t\t} g4x;\n\t};\n\tbool need_postvbl_update;\n};\n\nenum intel_output_format {\n\tINTEL_OUTPUT_FORMAT_INVALID = 0,\n\tINTEL_OUTPUT_FORMAT_RGB = 1,\n\tINTEL_OUTPUT_FORMAT_YCBCR420 = 2,\n\tINTEL_OUTPUT_FORMAT_YCBCR444 = 3,\n};\n\nstruct intel_crtc_state {\n\tstruct drm_crtc_state uapi;\n\tstruct {\n\t\tbool active;\n\t\tbool enable;\n\t\tstruct drm_property_blob *degamma_lut;\n\t\tstruct drm_property_blob *gamma_lut;\n\t\tstruct drm_property_blob *ctm;\n\t\tstruct drm_display_mode mode;\n\t\tstruct drm_display_mode adjusted_mode;\n\t} hw;\n\tlong unsigned int quirks;\n\tunsigned int fb_bits;\n\tbool update_pipe;\n\tbool disable_cxsr;\n\tbool update_wm_pre;\n\tbool update_wm_post;\n\tbool fifo_changed;\n\tbool preload_luts;\n\tint pipe_src_w;\n\tint pipe_src_h;\n\tunsigned int pixel_rate;\n\tbool has_pch_encoder;\n\tbool has_infoframe;\n\tenum transcoder cpu_transcoder;\n\tbool limited_color_range;\n\tunsigned int output_types;\n\tbool has_hdmi_sink;\n\tbool has_audio;\n\tbool dither;\n\tbool dither_force_disable;\n\tbool clock_set;\n\tbool sdvo_tv_clock;\n\tbool bw_constrained;\n\tstruct dpll dpll;\n\tstruct intel_shared_dpll *shared_dpll;\n\tstruct intel_dpll_hw_state dpll_hw_state;\n\tstruct icl_port_dpll icl_port_dplls[2];\n\tstruct {\n\t\tu32 ctrl;\n\t\tu32 div;\n\t} dsi_pll;\n\tint pipe_bpp;\n\tstruct intel_link_m_n dp_m_n;\n\tstruct intel_link_m_n dp_m2_n2;\n\tbool has_drrs;\n\tbool has_psr;\n\tbool has_psr2;\n\tu32 dc3co_exitline;\n\tint port_clock;\n\tunsigned int pixel_multiplier;\n\tu8 lane_count;\n\tu8 lane_lat_optim_mask;\n\tu8 min_voltage_level;\n\tstruct {\n\t\tu32 control;\n\t\tu32 pgm_ratios;\n\t\tu32 lvds_border_bits;\n\t} gmch_pfit;\n\tstruct {\n\t\tstruct drm_rect dst;\n\t\tbool enabled;\n\t\tbool force_thru;\n\t} pch_pfit;\n\tint fdi_lanes;\n\tstruct intel_link_m_n fdi_m_n;\n\tbool ips_enabled;\n\tbool crc_enabled;\n\tbool enable_fbc;\n\tbool double_wide;\n\tint pbn;\n\tstruct intel_crtc_scaler_state scaler_state;\n\tenum pipe hsw_workaround_pipe;\n\tbool disable_lp_wm;\n\tstruct intel_crtc_wm_state wm;\n\tint min_cdclk[8];\n\tu32 data_rate[8];\n\tu32 gamma_mode;\n\tunion {\n\t\tu32 csc_mode;\n\t\tu32 cgm_mode;\n\t};\n\tu8 active_planes;\n\tu8 nv12_planes;\n\tu8 c8_planes;\n\tu8 update_planes;\n\tstruct {\n\t\tu32 enable;\n\t\tu32 gcp;\n\t\tunion hdmi_infoframe avi;\n\t\tunion hdmi_infoframe spd;\n\t\tunion hdmi_infoframe hdmi;\n\t\tunion hdmi_infoframe drm;\n\t\tstruct drm_dp_vsc_sdp vsc;\n\t} infoframes;\n\tbool hdmi_scrambling;\n\tbool hdmi_high_tmds_clock_ratio;\n\tenum intel_output_format output_format;\n\tbool lspcon_downsampling;\n\tbool gamma_enable;\n\tbool csc_enable;\n\tstruct {\n\t\tbool compression_enable;\n\t\tbool dsc_split;\n\t\tu16 compressed_bpp;\n\t\tu8 slice_count;\n\t\tstruct drm_dsc_config config;\n\t} dsc;\n\tu16 linetime;\n\tu16 ips_linetime;\n\tbool fec_enable;\n\tenum transcoder master_transcoder;\n\tu8 sync_mode_slaves_mask;\n\tenum transcoder mst_master_transcoder;\n};\n\nenum intel_pipe_crc_source {\n\tINTEL_PIPE_CRC_SOURCE_NONE = 0,\n\tINTEL_PIPE_CRC_SOURCE_PLANE1 = 1,\n\tINTEL_PIPE_CRC_SOURCE_PLANE2 = 2,\n\tINTEL_PIPE_CRC_SOURCE_PLANE3 = 3,\n\tINTEL_PIPE_CRC_SOURCE_PLANE4 = 4,\n\tINTEL_PIPE_CRC_SOURCE_PLANE5 = 5,\n\tINTEL_PIPE_CRC_SOURCE_PLANE6 = 6,\n\tINTEL_PIPE_CRC_SOURCE_PLANE7 = 7,\n\tINTEL_PIPE_CRC_SOURCE_PIPE = 8,\n\tINTEL_PIPE_CRC_SOURCE_TV = 9,\n\tINTEL_PIPE_CRC_SOURCE_DP_B = 10,\n\tINTEL_PIPE_CRC_SOURCE_DP_C = 11,\n\tINTEL_PIPE_CRC_SOURCE_DP_D = 12,\n\tINTEL_PIPE_CRC_SOURCE_AUTO = 13,\n\tINTEL_PIPE_CRC_SOURCE_MAX = 14,\n};\n\nstruct intel_pipe_crc {\n\tspinlock_t lock;\n\tint skipped;\n\tenum intel_pipe_crc_source source;\n};\n\nstruct intel_crtc {\n\tstruct drm_crtc base;\n\tenum pipe pipe;\n\tbool active;\n\tu8 plane_ids_mask;\n\tlong long unsigned int enabled_power_domains;\n\tstruct intel_overlay *overlay;\n\tstruct intel_crtc_state *config;\n\tbool cpu_fifo_underrun_disabled;\n\tbool pch_fifo_underrun_disabled;\n\tstruct {\n\t\tunion {\n\t\t\tstruct intel_pipe_wm ilk;\n\t\t\tstruct vlv_wm_state vlv;\n\t\t\tstruct g4x_wm_state g4x;\n\t\t} active;\n\t} wm;\n\tint scanline_offset;\n\tstruct {\n\t\tunsigned int start_vbl_count;\n\t\tktime_t start_vbl_time;\n\t\tint min_vbl;\n\t\tint max_vbl;\n\t\tint scanline_start;\n\t} debug;\n\tint num_scalers;\n\tstruct intel_dsb dsb;\n\tstruct intel_pipe_crc pipe_crc;\n};\n\nstruct intel_cdclk_state {\n\tstruct intel_global_state base;\n\tstruct intel_cdclk_config logical;\n\tstruct intel_cdclk_config actual;\n\tint min_cdclk[4];\n\tu8 min_voltage_level[4];\n\tenum pipe pipe;\n\tint force_min_cdclk;\n\tbool force_min_cdclk_changed;\n\tu8 active_pipes;\n};\n\nstruct intel_framebuffer;\n\nstruct intel_initial_plane_config {\n\tstruct intel_framebuffer *fb;\n\tstruct i915_vma *vma;\n\tunsigned int tiling;\n\tint size;\n\tu32 base;\n\tu8 rotation;\n};\n\nenum intel_output_type {\n\tINTEL_OUTPUT_UNUSED = 0,\n\tINTEL_OUTPUT_ANALOG = 1,\n\tINTEL_OUTPUT_DVO = 2,\n\tINTEL_OUTPUT_SDVO = 3,\n\tINTEL_OUTPUT_LVDS = 4,\n\tINTEL_OUTPUT_TVOUT = 5,\n\tINTEL_OUTPUT_HDMI = 6,\n\tINTEL_OUTPUT_DP = 7,\n\tINTEL_OUTPUT_EDP = 8,\n\tINTEL_OUTPUT_DSI = 9,\n\tINTEL_OUTPUT_DDI = 10,\n\tINTEL_OUTPUT_DP_MST = 11,\n};\n\nenum intel_hotplug_state {\n\tINTEL_HOTPLUG_UNCHANGED = 0,\n\tINTEL_HOTPLUG_CHANGED = 1,\n\tINTEL_HOTPLUG_RETRY = 2,\n};\n\nstruct intel_connector;\n\nstruct intel_encoder {\n\tstruct drm_encoder base;\n\tenum intel_output_type type;\n\tenum port port;\n\tu16 cloneable;\n\tu8 pipe_mask;\n\tenum intel_hotplug_state (*hotplug)(struct intel_encoder *, struct intel_connector *);\n\tenum intel_output_type (*compute_output_type)(struct intel_encoder *, struct intel_crtc_state *, struct drm_connector_state *);\n\tint (*compute_config)(struct intel_encoder *, struct intel_crtc_state *, struct drm_connector_state *);\n\tint (*compute_config_late)(struct intel_encoder *, struct intel_crtc_state *, struct drm_connector_state *);\n\tvoid (*update_prepare)(struct intel_atomic_state *, struct intel_encoder *, struct intel_crtc *);\n\tvoid (*pre_pll_enable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*pre_enable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*enable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*update_complete)(struct intel_atomic_state *, struct intel_encoder *, struct intel_crtc *);\n\tvoid (*disable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*post_disable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*post_pll_disable)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tvoid (*update_pipe)(struct intel_atomic_state *, struct intel_encoder *, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tbool (*get_hw_state)(struct intel_encoder *, enum pipe *);\n\tvoid (*get_config)(struct intel_encoder *, struct intel_crtc_state *);\n\tvoid (*get_power_domains)(struct intel_encoder *, struct intel_crtc_state *);\n\tvoid (*suspend)(struct intel_encoder *);\n\tenum hpd_pin hpd_pin;\n\tenum intel_display_power_domain power_domain;\n\tconst struct drm_connector *audio_connector;\n};\n\nstruct intel_dp_compliance_data {\n\tlong unsigned int edid;\n\tu8 video_pattern;\n\tu16 hdisplay;\n\tu16 vdisplay;\n\tu8 bpc;\n\tstruct drm_dp_phy_test_params phytest;\n};\n\nstruct intel_dp_compliance {\n\tlong unsigned int test_type;\n\tstruct intel_dp_compliance_data test_data;\n\tbool test_active;\n\tint test_link_rate;\n\tu8 test_lane_count;\n};\n\nstruct intel_dp_mst_encoder;\n\nstruct intel_dp {\n\ti915_reg_t output_reg;\n\tu32 DP;\n\tint link_rate;\n\tu8 lane_count;\n\tu8 sink_count;\n\tbool link_mst;\n\tbool link_trained;\n\tbool has_audio;\n\tbool reset_link_params;\n\tu8 dpcd[15];\n\tu8 psr_dpcd[2];\n\tu8 downstream_ports[16];\n\tu8 edp_dpcd[3];\n\tu8 dsc_dpcd[15];\n\tu8 fec_capable;\n\tshort: 16;\n\tint num_source_rates;\n\tint: 32;\n\tconst int *source_rates;\n\tint num_sink_rates;\n\tint sink_rates[8];\n\tbool use_rate_select;\n\tint: 24;\n\tint num_common_rates;\n\tint common_rates[8];\n\tint max_link_lane_count;\n\tint max_link_rate;\n\tstruct drm_dp_desc desc;\n\tu32 edid_quirks;\n\tstruct drm_dp_aux aux;\n\tu32 aux_busy_last_status;\n\tu8 train_set[4];\n\tint panel_power_up_delay;\n\tint panel_power_down_delay;\n\tint panel_power_cycle_delay;\n\tint backlight_on_delay;\n\tint backlight_off_delay;\n\tint: 32;\n\tstruct delayed_work panel_vdd_work;\n\tbool want_panel_vdd;\n\tlong: 56;\n\tlong unsigned int last_power_on;\n\tlong unsigned int last_backlight_off;\n\tktime_t panel_power_off_time;\n\tstruct notifier_block edp_notifier;\n\tenum pipe pps_pipe;\n\tenum pipe active_pipe;\n\tbool pps_reset;\n\tstruct edp_power_seq pps_delays;\n\tbool can_mst;\n\tbool is_mst;\n\tint: 24;\n\tint active_mst_links;\n\tstruct {\n\t\ti915_reg_t dp_tp_ctl;\n\t\ti915_reg_t dp_tp_status;\n\t} regs;\n\tint: 32;\n\tstruct intel_connector *attached_connector;\n\tstruct intel_dp_mst_encoder *mst_encoders[4];\n\tstruct drm_dp_mst_topology_mgr mst_mgr;\n\tu32 (*get_aux_clock_divider)(struct intel_dp *, int);\n\tu32 (*get_aux_send_ctl)(struct intel_dp *, int, u32);\n\ti915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *);\n\ti915_reg_t (*aux_ch_data_reg)(struct intel_dp *, int);\n\tvoid (*prepare_link_retrain)(struct intel_dp *);\n\tvoid (*set_link_train)(struct intel_dp *, u8);\n\tvoid (*set_idle_link_train)(struct intel_dp *);\n\tvoid (*set_signal_levels)(struct intel_dp *);\n\tstruct intel_dp_compliance compliance;\n\tbool force_dsc_en;\n\tlong: 56;\n} __attribute__((packed));\n\nstruct child_device_config {\n\tu16 handle;\n\tu16 device_type;\n\tunion {\n\t\tu8 device_id[10];\n\t\tstruct {\n\t\t\tu8 i2c_speed;\n\t\t\tu8 dp_onboard_redriver;\n\t\t\tu8 dp_ondock_redriver;\n\t\t\tu8 hdmi_level_shifter_value: 5;\n\t\t\tu8 hdmi_max_data_rate: 3;\n\t\t\tu16 dtd_buf_ptr;\n\t\t\tu8 edidless_efp: 1;\n\t\t\tu8 compression_enable: 1;\n\t\t\tu8 compression_method_cps: 1;\n\t\t\tu8 ganged_edp: 1;\n\t\t\tu8 reserved0: 4;\n\t\t\tu8 compression_structure_index: 4;\n\t\t\tu8 reserved1: 4;\n\t\t\tu8 slave_port;\n\t\t\tu8 reserved2;\n\t\t};\n\t};\n\tu16 addin_offset;\n\tu8 dvo_port;\n\tu8 i2c_pin;\n\tu8 slave_addr;\n\tu8 ddc_pin;\n\tu16 edid_ptr;\n\tu8 dvo_cfg;\n\tunion {\n\t\tstruct {\n\t\t\tu8 dvo2_port;\n\t\t\tu8 i2c2_pin;\n\t\t\tu8 slave2_addr;\n\t\t\tu8 ddc2_pin;\n\t\t};\n\t\tstruct {\n\t\t\tu8 efp_routed: 1;\n\t\t\tu8 lane_reversal: 1;\n\t\t\tu8 lspcon: 1;\n\t\t\tu8 iboost: 1;\n\t\t\tu8 hpd_invert: 1;\n\t\t\tu8 use_vbt_vswing: 1;\n\t\t\tu8 flag_reserved: 2;\n\t\t\tu8 hdmi_support: 1;\n\t\t\tu8 dp_support: 1;\n\t\t\tu8 tmds_support: 1;\n\t\t\tu8 support_reserved: 5;\n\t\t\tu8 aux_channel;\n\t\t\tu8 dongle_detect;\n\t\t};\n\t};\n\tu8 pipe_cap: 2;\n\tu8 sdvo_stall: 1;\n\tu8 hpd_status: 2;\n\tu8 integrated_encoder: 1;\n\tu8 capabilities_reserved: 2;\n\tu8 dvo_wiring;\n\tunion {\n\t\tu8 dvo2_wiring;\n\t\tu8 mipi_bridge_type;\n\t};\n\tu16 extended_type;\n\tu8 dvo_function;\n\tu8 dp_usb_type_c: 1;\n\tu8 tbt: 1;\n\tu8 flags2_reserved: 2;\n\tu8 dp_port_trace_length: 4;\n\tu8 dp_gpio_index;\n\tu16 dp_gpio_pin_num;\n\tu8 dp_iboost_level: 4;\n\tu8 hdmi_iboost_level: 4;\n\tu8 dp_max_link_rate: 2;\n\tu8 dp_max_link_rate_reserved: 6;\n} __attribute__((packed));\n\nstruct intel_cdclk_vals {\n\tu16 refclk;\n\tu32 cdclk;\n\tu8 divider;\n\tu8 ratio;\n};\n\nstruct intel_dpll_mgr {\n\tconst struct dpll_info *dpll_info;\n\tbool (*get_dplls)(struct intel_atomic_state *, struct intel_crtc *, struct intel_encoder *);\n\tvoid (*put_dplls)(struct intel_atomic_state *, struct intel_crtc *);\n\tvoid (*update_active_dpll)(struct intel_atomic_state *, struct intel_crtc *, struct intel_encoder *);\n\tvoid (*update_ref_clks)(struct drm_i915_private *);\n\tvoid (*dump_hw_state)(struct drm_i915_private *, const struct intel_dpll_hw_state *);\n};\n\nstruct intel_fbdev {\n\tstruct drm_fb_helper helper;\n\tstruct intel_framebuffer *fb;\n\tstruct i915_vma *vma;\n\tlong unsigned int vma_flags;\n\tasync_cookie_t cookie;\n\tint preferred_bpp;\n\tbool hpd_suspended: 1;\n\tbool hpd_waiting: 1;\n\tstruct mutex hpd_lock;\n};\n\nstruct cec_msg {\n\t__u64 tx_ts;\n\t__u64 rx_ts;\n\t__u32 len;\n\t__u32 timeout;\n\t__u32 sequence;\n\t__u32 flags;\n\t__u8 msg[16];\n\t__u8 reply;\n\t__u8 rx_status;\n\t__u8 tx_status;\n\t__u8 tx_arb_lost_cnt;\n\t__u8 tx_nack_cnt;\n\t__u8 tx_low_drive_cnt;\n\t__u8 tx_error_cnt;\n};\n\nstruct cec_event_state_change {\n\t__u16 phys_addr;\n\t__u16 log_addr_mask;\n\t__u16 have_conn_info;\n};\n\nstruct cec_event_lost_msgs {\n\t__u32 lost_msgs;\n};\n\nstruct cec_event {\n\t__u64 ts;\n\t__u32 event;\n\t__u32 flags;\n\tunion {\n\t\tstruct cec_event_state_change state_change;\n\t\tstruct cec_event_lost_msgs lost_msgs;\n\t\t__u32 raw[16];\n\t};\n};\n\nenum rc_proto {\n\tRC_PROTO_UNKNOWN = 0,\n\tRC_PROTO_OTHER = 1,\n\tRC_PROTO_RC5 = 2,\n\tRC_PROTO_RC5X_20 = 3,\n\tRC_PROTO_RC5_SZ = 4,\n\tRC_PROTO_JVC = 5,\n\tRC_PROTO_SONY12 = 6,\n\tRC_PROTO_SONY15 = 7,\n\tRC_PROTO_SONY20 = 8,\n\tRC_PROTO_NEC = 9,\n\tRC_PROTO_NECX = 10,\n\tRC_PROTO_NEC32 = 11,\n\tRC_PROTO_SANYO = 12,\n\tRC_PROTO_MCIR2_KBD = 13,\n\tRC_PROTO_MCIR2_MSE = 14,\n\tRC_PROTO_RC6_0 = 15,\n\tRC_PROTO_RC6_6A_20 = 16,\n\tRC_PROTO_RC6_6A_24 = 17,\n\tRC_PROTO_RC6_6A_32 = 18,\n\tRC_PROTO_RC6_MCE = 19,\n\tRC_PROTO_SHARP = 20,\n\tRC_PROTO_XMP = 21,\n\tRC_PROTO_CEC = 22,\n\tRC_PROTO_IMON = 23,\n\tRC_PROTO_RCMM12 = 24,\n\tRC_PROTO_RCMM24 = 25,\n\tRC_PROTO_RCMM32 = 26,\n\tRC_PROTO_XBOX_DVD = 27,\n};\n\nstruct rc_map_table {\n\tu64 scancode;\n\tu32 keycode;\n};\n\nstruct rc_map {\n\tstruct rc_map_table *scan;\n\tunsigned int size;\n\tunsigned int len;\n\tunsigned int alloc;\n\tenum rc_proto rc_proto;\n\tconst char *name;\n\tspinlock_t lock;\n};\n\nenum rc_driver_type {\n\tRC_DRIVER_SCANCODE = 0,\n\tRC_DRIVER_IR_RAW = 1,\n\tRC_DRIVER_IR_RAW_TX = 2,\n};\n\nstruct rc_scancode_filter {\n\tu32 data;\n\tu32 mask;\n};\n\nstruct ir_raw_event_ctrl;\n\nstruct rc_dev {\n\tstruct device dev;\n\tbool managed_alloc;\n\tconst struct attribute_group *sysfs_groups[5];\n\tconst char *device_name;\n\tconst char *input_phys;\n\tstruct input_id input_id;\n\tconst char *driver_name;\n\tconst char *map_name;\n\tstruct rc_map rc_map;\n\tstruct mutex lock;\n\tunsigned int minor;\n\tstruct ir_raw_event_ctrl *raw;\n\tstruct input_dev *input_dev;\n\tenum rc_driver_type driver_type;\n\tbool idle;\n\tbool encode_wakeup;\n\tu64 allowed_protocols;\n\tu64 enabled_protocols;\n\tu64 allowed_wakeup_protocols;\n\tenum rc_proto wakeup_protocol;\n\tstruct rc_scancode_filter scancode_filter;\n\tstruct rc_scancode_filter scancode_wakeup_filter;\n\tu32 scancode_mask;\n\tu32 users;\n\tvoid *priv;\n\tspinlock_t keylock;\n\tbool keypressed;\n\tlong unsigned int keyup_jiffies;\n\tstruct timer_list timer_keyup;\n\tstruct timer_list timer_repeat;\n\tu32 last_keycode;\n\tenum rc_proto last_protocol;\n\tu64 last_scancode;\n\tu8 last_toggle;\n\tu32 timeout;\n\tu32 min_timeout;\n\tu32 max_timeout;\n\tu32 rx_resolution;\n\tu32 tx_resolution;\n\tbool registered;\n\tint (*change_protocol)(struct rc_dev *, u64 *);\n\tint (*open)(struct rc_dev *);\n\tvoid (*close)(struct rc_dev *);\n\tint (*s_tx_mask)(struct rc_dev *, u32);\n\tint (*s_tx_carrier)(struct rc_dev *, u32);\n\tint (*s_tx_duty_cycle)(struct rc_dev *, u32);\n\tint (*s_rx_carrier_range)(struct rc_dev *, u32, u32);\n\tint (*tx_ir)(struct rc_dev *, unsigned int *, unsigned int);\n\tvoid (*s_idle)(struct rc_dev *, bool);\n\tint (*s_learning_mode)(struct rc_dev *, int);\n\tint (*s_carrier_report)(struct rc_dev *, int);\n\tint (*s_filter)(struct rc_dev *, struct rc_scancode_filter *);\n\tint (*s_wakeup_filter)(struct rc_dev *, struct rc_scancode_filter *);\n\tint (*s_timeout)(struct rc_dev *, unsigned int);\n};\n\nstruct cec_data {\n\tstruct list_head list;\n\tstruct list_head xfer_list;\n\tstruct cec_adapter *adap;\n\tstruct cec_msg msg;\n\tstruct cec_fh *fh;\n\tstruct delayed_work work;\n\tstruct completion c;\n\tu8 attempts;\n\tbool blocking;\n\tbool completed;\n};\n\nstruct cec_event_entry {\n\tstruct list_head list;\n\tstruct cec_event ev;\n};\n\nstruct cec_fh {\n\tstruct list_head list;\n\tstruct list_head xfer_list;\n\tstruct cec_adapter *adap;\n\tu8 mode_initiator;\n\tu8 mode_follower;\n\twait_queue_head_t wait;\n\tstruct mutex lock;\n\tstruct list_head events[8];\n\tu16 queued_events[8];\n\tunsigned int total_queued_events;\n\tstruct cec_event_entry core_events[2];\n\tstruct list_head msgs;\n\tunsigned int queued_msgs;\n};\n\nstruct cec_adap_ops {\n\tint (*adap_enable)(struct cec_adapter *, bool);\n\tint (*adap_monitor_all_enable)(struct cec_adapter *, bool);\n\tint (*adap_monitor_pin_enable)(struct cec_adapter *, bool);\n\tint (*adap_log_addr)(struct cec_adapter *, u8);\n\tint (*adap_transmit)(struct cec_adapter *, u8, u32, struct cec_msg *);\n\tvoid (*adap_status)(struct cec_adapter *, struct seq_file *);\n\tvoid (*adap_free)(struct cec_adapter *);\n\tint (*error_inj_show)(struct cec_adapter *, struct seq_file *);\n\tbool (*error_inj_parse_line)(struct cec_adapter *, char *);\n\tint (*received)(struct cec_adapter *, struct cec_msg *);\n};\n\nstruct intel_framebuffer {\n\tstruct drm_framebuffer base;\n\tstruct intel_frontbuffer *frontbuffer;\n\tstruct intel_rotation_info rot_info;\n\tstruct {\n\t\tunsigned int x;\n\t\tunsigned int y;\n\t} normal[4];\n\tstruct {\n\t\tunsigned int x;\n\t\tunsigned int y;\n\t\tunsigned int pitch;\n\t} rotated[2];\n};\n\nstruct pwm_device;\n\nstruct intel_panel {\n\tstruct drm_display_mode *fixed_mode;\n\tstruct drm_display_mode *downclock_mode;\n\tstruct {\n\t\tbool present;\n\t\tu32 level;\n\t\tu32 min;\n\t\tu32 max;\n\t\tbool enabled;\n\t\tbool combination_mode;\n\t\tbool active_low_pwm;\n\t\tbool alternate_pwm_increment;\n\t\tbool util_pin_active_low;\n\t\tu8 controller;\n\t\tstruct pwm_device *pwm;\n\t\tu8 pwmgen_bit_count;\n\t\tstruct backlight_device *device;\n\t\tint (*setup)(struct intel_connector *, enum pipe);\n\t\tu32 (*get)(struct intel_connector *);\n\t\tvoid (*set)(const struct drm_connector_state *, u32);\n\t\tvoid (*disable)(const struct drm_connector_state *);\n\t\tvoid (*enable)(const struct intel_crtc_state *, const struct drm_connector_state *);\n\t\tu32 (*hz_to_pwm)(struct intel_connector *, u32);\n\t\tvoid (*power)(struct intel_connector *, bool);\n\t} backlight;\n};\n\nstruct intel_hdcp_shim;\n\nstruct intel_hdcp {\n\tconst struct intel_hdcp_shim *shim;\n\tstruct mutex mutex;\n\tu64 value;\n\tstruct delayed_work check_work;\n\tstruct work_struct prop_work;\n\tbool hdcp_encrypted;\n\tbool hdcp2_supported;\n\tbool hdcp2_encrypted;\n\tu8 content_type;\n\tstruct hdcp_port_data port_data;\n\tbool is_paired;\n\tbool is_repeater;\n\tu32 seq_num_v;\n\tu32 seq_num_m;\n\twait_queue_head_t cp_irq_queue;\n\tatomic_t cp_irq_count;\n\tint cp_irq_count_cached;\n\tenum transcoder cpu_transcoder;\n};\n\nstruct intel_connector {\n\tstruct drm_connector base;\n\tstruct intel_encoder *encoder;\n\tu32 acpi_device_id;\n\tbool (*get_hw_state)(struct intel_connector *);\n\tstruct intel_panel panel;\n\tstruct edid *edid;\n\tstruct edid *detect_edid;\n\tint hotplug_retries;\n\tu8 polled;\n\tstruct drm_dp_mst_port *port;\n\tstruct intel_dp *mst_port;\n\tstruct work_struct modeset_retry_work;\n\tstruct intel_hdcp hdcp;\n};\n\nstruct intel_digital_port;\n\nstruct intel_hdcp_shim {\n\tint (*write_an_aksv)(struct intel_digital_port *, u8 *);\n\tint (*read_bksv)(struct intel_digital_port *, u8 *);\n\tint (*read_bstatus)(struct intel_digital_port *, u8 *);\n\tint (*repeater_present)(struct intel_digital_port *, bool *);\n\tint (*read_ri_prime)(struct intel_digital_port *, u8 *);\n\tint (*read_ksv_ready)(struct intel_digital_port *, bool *);\n\tint (*read_ksv_fifo)(struct intel_digital_port *, int, u8 *);\n\tint (*read_v_prime_part)(struct intel_digital_port *, int, u32 *);\n\tint (*toggle_signalling)(struct intel_digital_port *, bool);\n\tbool (*check_link)(struct intel_digital_port *);\n\tint (*hdcp_capable)(struct intel_digital_port *, bool *);\n\tenum hdcp_wired_protocol protocol;\n\tint (*hdcp_2_2_capable)(struct intel_digital_port *, bool *);\n\tint (*write_2_2_msg)(struct intel_digital_port *, void *, size_t);\n\tint (*read_2_2_msg)(struct intel_digital_port *, u8, void *, size_t);\n\tint (*config_stream_type)(struct intel_digital_port *, bool, u8);\n\tint (*check_2_2_link)(struct intel_digital_port *);\n};\n\nstruct cec_notifier;\n\nstruct intel_hdmi {\n\ti915_reg_t hdmi_reg;\n\tint ddc_bus;\n\tstruct {\n\t\tenum drm_dp_dual_mode_type type;\n\t\tint max_tmds_clock;\n\t} dp_dual_mode;\n\tbool has_hdmi_sink;\n\tbool has_audio;\n\tstruct intel_connector *attached_connector;\n\tstruct cec_notifier *cec_notifier;\n};\n\nenum lspcon_vendor {\n\tLSPCON_VENDOR_MCA = 0,\n\tLSPCON_VENDOR_PARADE = 1,\n};\n\nstruct intel_lspcon {\n\tbool active;\n\tenum drm_lspcon_mode mode;\n\tenum lspcon_vendor vendor;\n};\n\nstruct intel_digital_port {\n\tstruct intel_encoder base;\n\tu32 saved_port_bits;\n\tstruct intel_dp dp;\n\tstruct intel_hdmi hdmi;\n\tstruct intel_lspcon lspcon;\n\tenum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);\n\tbool release_cl2_override;\n\tu8 max_lanes;\n\tenum aux_ch aux_ch;\n\tenum intel_display_power_domain ddi_io_power_domain;\n\tstruct mutex tc_lock;\n\tintel_wakeref_t tc_lock_wakeref;\n\tint tc_link_refcount;\n\tbool tc_legacy_port: 1;\n\tchar tc_port_name[8];\n\tenum tc_port_mode tc_mode;\n\tenum phy_fia tc_phy_fia;\n\tu8 tc_phy_fia_idx;\n\tvoid (*write_infoframe)(struct intel_encoder *, const struct intel_crtc_state *, unsigned int, const void *, ssize_t);\n\tvoid (*read_infoframe)(struct intel_encoder *, const struct intel_crtc_state *, unsigned int, void *, ssize_t);\n\tvoid (*set_infoframes)(struct intel_encoder *, bool, const struct intel_crtc_state *, const struct drm_connector_state *);\n\tu32 (*infoframes_enabled)(struct intel_encoder *, const struct intel_crtc_state *);\n\tbool (*connected)(struct intel_encoder *);\n};\n\nenum vlv_wm_level {\n\tVLV_WM_LEVEL_PM2 = 0,\n\tVLV_WM_LEVEL_PM5 = 1,\n\tVLV_WM_LEVEL_DDR_DVFS = 2,\n\tNUM_VLV_WM_LEVELS = 3,\n};\n\nenum g4x_wm_level {\n\tG4X_WM_LEVEL_NORMAL = 0,\n\tG4X_WM_LEVEL_SR = 1,\n\tG4X_WM_LEVEL_HPLL = 2,\n\tNUM_G4X_WM_LEVELS = 3,\n};\n\nstruct intel_dp_mst_encoder {\n\tstruct intel_encoder base;\n\tenum pipe pipe;\n\tstruct intel_digital_port *primary;\n\tstruct intel_connector *connector;\n};\n\nenum tc_port {\n\tPORT_TC_NONE = 4294967295,\n\tPORT_TC1 = 0,\n\tPORT_TC2 = 1,\n\tPORT_TC3 = 2,\n\tPORT_TC4 = 3,\n\tPORT_TC5 = 4,\n\tPORT_TC6 = 5,\n\tI915_MAX_TC_PORTS = 6,\n};\n\ntypedef bool (*long_pulse_detect_func)(enum hpd_pin, u32);\n\nenum drm_i915_gem_engine_class {\n\tI915_ENGINE_CLASS_RENDER = 0,\n\tI915_ENGINE_CLASS_COPY = 1,\n\tI915_ENGINE_CLASS_VIDEO = 2,\n\tI915_ENGINE_CLASS_VIDEO_ENHANCE = 3,\n\tI915_ENGINE_CLASS_INVALID = 4294967295,\n};\n\nstruct drm_i915_getparam {\n\t__s32 param;\n\tint *value;\n};\n\ntypedef struct drm_i915_getparam drm_i915_getparam_t;\n\nenum vga_switcheroo_state {\n\tVGA_SWITCHEROO_OFF = 0,\n\tVGA_SWITCHEROO_ON = 1,\n\tVGA_SWITCHEROO_NOT_FOUND = 2,\n};\n\nenum vga_switcheroo_client_id {\n\tVGA_SWITCHEROO_UNKNOWN_ID = 4096,\n\tVGA_SWITCHEROO_IGD = 0,\n\tVGA_SWITCHEROO_DIS = 1,\n\tVGA_SWITCHEROO_MAX_CLIENTS = 2,\n};\n\nstruct vga_switcheroo_client_ops {\n\tvoid (*set_gpu_state)(struct pci_dev *, enum vga_switcheroo_state);\n\tvoid (*reprobe)(struct pci_dev *);\n\tbool (*can_switch)(struct pci_dev *);\n\tvoid (*gpu_bound)(struct pci_dev *, enum vga_switcheroo_client_id);\n};\n\nstruct dram_dimm_info {\n\tu8 size;\n\tu8 width;\n\tu8 ranks;\n};\n\nstruct dram_channel_info {\n\tstruct dram_dimm_info dimm_l;\n\tstruct dram_dimm_info dimm_s;\n\tu8 ranks;\n\tbool is_16gb_dimm;\n};\n\nenum intel_memory_type {\n\tINTEL_MEMORY_SYSTEM = 0,\n\tINTEL_MEMORY_LOCAL = 1,\n\tINTEL_MEMORY_STOLEN = 2,\n};\n\nstruct drm_intel_sprite_colorkey {\n\t__u32 plane_id;\n\t__u32 min_value;\n\t__u32 channel_mask;\n\t__u32 max_value;\n\t__u32 flags;\n};\n\nenum dbuf_slice {\n\tDBUF_S1 = 0,\n\tDBUF_S2 = 1,\n};\n\nstruct intel_plane;\n\nstruct intel_plane_state {\n\tstruct drm_plane_state uapi;\n\tstruct {\n\t\tstruct drm_crtc *crtc;\n\t\tstruct drm_framebuffer *fb;\n\t\tu16 alpha;\n\t\tuint16_t pixel_blend_mode;\n\t\tunsigned int rotation;\n\t\tenum drm_color_encoding color_encoding;\n\t\tenum drm_color_range color_range;\n\t} hw;\n\tstruct i915_ggtt_view view;\n\tstruct i915_vma *vma;\n\tlong unsigned int flags;\n\tstruct {\n\t\tu32 offset;\n\t\tu32 stride;\n\t\tint x;\n\t\tint y;\n\t} color_plane[4];\n\tu32 ctl;\n\tu32 color_ctl;\n\tu32 cus_ctl;\n\tint scaler_id;\n\tstruct intel_plane *planar_linked_plane;\n\tu32 planar_slave;\n\tstruct drm_intel_sprite_colorkey ckey;\n};\n\nstruct intel_plane {\n\tstruct drm_plane base;\n\tenum i9xx_plane_id i9xx_plane;\n\tenum plane_id id;\n\tenum pipe pipe;\n\tbool has_fbc;\n\tbool has_ccs;\n\tu32 frontbuffer_bit;\n\tstruct {\n\t\tu32 base;\n\t\tu32 cntl;\n\t\tu32 size;\n\t} cursor;\n\tunsigned int (*max_stride)(struct intel_plane *, u32, u64, unsigned int);\n\tvoid (*update_plane)(struct intel_plane *, const struct intel_crtc_state *, const struct intel_plane_state *);\n\tvoid (*disable_plane)(struct intel_plane *, const struct intel_crtc_state *);\n\tbool (*get_hw_state)(struct intel_plane *, enum pipe *);\n\tint (*check_plane)(struct intel_crtc_state *, struct intel_plane_state *);\n\tint (*min_cdclk)(const struct intel_crtc_state *, const struct intel_plane_state *);\n};\n\nstruct intel_watermark_params {\n\tu16 fifo_size;\n\tu16 max_wm;\n\tu8 default_wm;\n\tu8 guard_size;\n\tu8 cacheline_size;\n};\n\nstruct cxsr_latency {\n\tbool is_desktop: 1;\n\tbool is_ddr3: 1;\n\tu16 fsb_freq;\n\tu16 mem_freq;\n\tu16 display_sr;\n\tu16 display_hpll_disable;\n\tu16 cursor_sr;\n\tu16 cursor_hpll_disable;\n};\n\ntypedef struct {\n\tu32 val;\n} uint_fixed_16_16_t;\n\nstruct intel_bw_state {\n\tstruct intel_global_state base;\n\tu8 pipe_sagv_reject;\n\tu8 qgv_points_mask;\n\tunsigned int data_rate[4];\n\tu8 num_active_planes[4];\n\tu8 active_pipes;\n};\n\nenum {\n\tVLV_IOSF_SB_BUNIT = 0,\n\tVLV_IOSF_SB_CCK = 1,\n\tVLV_IOSF_SB_CCU = 2,\n\tVLV_IOSF_SB_DPIO = 3,\n\tVLV_IOSF_SB_FLISDSI = 4,\n\tVLV_IOSF_SB_GPIO = 5,\n\tVLV_IOSF_SB_NC = 6,\n\tVLV_IOSF_SB_PUNIT = 7,\n};\n\nstruct skl_wm_params {\n\tbool x_tiled;\n\tbool y_tiled;\n\tbool rc_surface;\n\tbool is_planar;\n\tu32 width;\n\tu8 cpp;\n\tu32 plane_pixel_rate;\n\tu32 y_min_scanlines;\n\tu32 plane_bytes_per_line;\n\tuint_fixed_16_16_t plane_blocks_per_line;\n\tuint_fixed_16_16_t y_tile_minimum;\n\tu32 linetime_us;\n\tu32 dbuf_block_size;\n};\n\nstruct intel_wm_config {\n\tunsigned int num_pipes_active;\n\tbool sprites_enabled;\n\tbool sprites_scaled;\n};\n\nstruct ilk_wm_maximums {\n\tu16 pri;\n\tu16 spr;\n\tu16 cur;\n\tu16 fbc;\n};\n\nstruct dbuf_slice_conf_entry {\n\tu8 active_pipes;\n\tu8 dbuf_mask[4];\n};\n\nenum intel_sbi_destination {\n\tSBI_ICLK = 0,\n\tSBI_MPHY = 1,\n};\n\nstruct drm_i915_reg_read {\n\t__u64 offset;\n\t__u64 val;\n};\n\nenum ack_type {\n\tACK_CLEAR = 0,\n\tACK_SET = 1,\n};\n\nstruct reg_whitelist {\n\ti915_reg_t offset_ldw;\n\ti915_reg_t offset_udw;\n\tu16 gen_mask;\n\tu8 size;\n};\n\nstruct intel_wakeref_lockclass {\n\tstruct lock_class_key mutex;\n\tstruct lock_class_key work;\n};\n\nenum {\n\tINTEL_WAKEREF_PUT_ASYNC_BIT = 0,\n\t__INTEL_WAKEREF_PUT_LAST_BIT__ = 1,\n};\n\nstruct vlv_s0ix_state {\n\tu32 wr_watermark;\n\tu32 gfx_prio_ctrl;\n\tu32 arb_mode;\n\tu32 gfx_pend_tlb0;\n\tu32 gfx_pend_tlb1;\n\tu32 lra_limits[13];\n\tu32 media_max_req_count;\n\tu32 gfx_max_req_count;\n\tu32 render_hwsp;\n\tu32 ecochk;\n\tu32 bsd_hwsp;\n\tu32 blt_hwsp;\n\tu32 tlb_rd_addr;\n\tu32 g3dctl;\n\tu32 gsckgctl;\n\tu32 mbctl;\n\tu32 ucgctl1;\n\tu32 ucgctl3;\n\tu32 rcgctl1;\n\tu32 rcgctl2;\n\tu32 rstctl;\n\tu32 misccpctl;\n\tu32 gfxpause;\n\tu32 rpdeuhwtc;\n\tu32 rpdeuc;\n\tu32 ecobus;\n\tu32 pwrdwnupctl;\n\tu32 rp_down_timeout;\n\tu32 rp_deucsw;\n\tu32 rcubmabdtmr;\n\tu32 rcedata;\n\tu32 spare2gh;\n\tu32 gt_imr;\n\tu32 gt_ier;\n\tu32 pm_imr;\n\tu32 pm_ier;\n\tu32 gt_scratch[8];\n\tu32 tilectl;\n\tu32 gt_fifoctl;\n\tu32 gtlc_wake_ctrl;\n\tu32 gtlc_survive;\n\tu32 pmwgicz;\n\tu32 gu_ctl0;\n\tu32 gu_ctl1;\n\tu32 pcbr;\n\tu32 clock_gate_dis2;\n};\n\nstruct sgt_iter {\n\tstruct scatterlist *sgp;\n\tunion {\n\t\tlong unsigned int pfn;\n\t\tdma_addr_t dma;\n\t};\n\tunsigned int curr;\n\tunsigned int max;\n};\n\nstruct remap_pfn {\n\tstruct mm_struct *mm;\n\tlong unsigned int pfn;\n\tpgprot_t prot;\n\tstruct sgt_iter sgt;\n\tresource_size_t iobase;\n};\n\nenum i915_sw_fence_notify {\n\tFENCE_COMPLETE = 0,\n\tFENCE_FREE = 1,\n};\n\ntypedef int (*i915_sw_fence_notify_t)(struct i915_sw_fence *, enum i915_sw_fence_notify);\n\nenum {\n\tDEBUG_FENCE_IDLE = 0,\n\tDEBUG_FENCE_NOTIFY = 1,\n};\n\nstruct i915_sw_dma_fence_cb_timer {\n\tstruct i915_sw_dma_fence_cb base;\n\tstruct dma_fence *dma;\n\tstruct timer_list timer;\n\tstruct irq_work work;\n\tstruct callback_head rcu;\n};\n\nstruct dma_fence_work;\n\nstruct dma_fence_work_ops {\n\tconst char *name;\n\tint (*work)(struct dma_fence_work *);\n\tvoid (*release)(struct dma_fence_work *);\n};\n\nstruct dma_fence_work {\n\tstruct dma_fence dma;\n\tspinlock_t lock;\n\tstruct i915_sw_fence chain;\n\tstruct i915_sw_dma_fence_cb cb;\n\tstruct work_struct work;\n\tconst struct dma_fence_work_ops *ops;\n};\n\nenum {\n\tDMA_FENCE_WORK_IMM = 3,\n};\n\nstruct i915_syncmap___2 {\n\tu64 prefix;\n\tunsigned int height;\n\tunsigned int bitmap;\n\tstruct i915_syncmap___2 *parent;\n};\n\nstruct i915_user_extension {\n\t__u64 next_extension;\n\t__u32 name;\n\t__u32 flags;\n\t__u32 rsvd[4];\n};\n\ntypedef int (*i915_user_extension_fn)(struct i915_user_extension *, void *);\n\nstruct drm_i915_getparam32 {\n\ts32 param;\n\tu32 value;\n};\n\nstruct i915_gem_engines_iter {\n\tunsigned int idx;\n\tconst struct i915_gem_engines *engines;\n};\n\nenum {\n\tINTEL_RPS_ENABLED = 0,\n\tINTEL_RPS_ACTIVE = 1,\n\tINTEL_RPS_INTERRUPTS = 2,\n\tINTEL_RPS_TIMER = 3,\n};\n\nstruct file_stats {\n\tstruct i915_address_space *vm;\n\tlong unsigned int count;\n\tu64 total;\n\tu64 active;\n\tu64 inactive;\n\tu64 closed;\n};\n\nstruct i915_debugfs_files {\n\tconst char *name;\n\tconst struct file_operations *fops;\n};\n\nstruct i915_str_attribute {\n\tstruct device_attribute attr;\n\tconst char *str;\n};\n\nstruct i915_ext_attribute {\n\tstruct device_attribute attr;\n\tlong unsigned int val;\n};\n\nstruct debugfs_gt_file {\n\tconst char *name;\n\tconst struct file_operations *fops;\n\tbool (*eval)(void *);\n};\n\ntypedef u32 gen6_pte_t;\n\nstruct sgt_dma {\n\tstruct scatterlist *sg;\n\tdma_addr_t dma;\n\tdma_addr_t max;\n};\n\nstruct gen6_ppgtt {\n\tstruct i915_ppgtt base;\n\tstruct mutex flush;\n\tstruct i915_vma *vma;\n\tgen6_pte_t *pd_addr;\n\tatomic_t pin_count;\n\tstruct mutex pin_mutex;\n\tbool scan_for_unused_pt;\n};\n\nenum i915_map_type {\n\tI915_MAP_WB = 0,\n\tI915_MAP_WC = 1,\n\tI915_MAP_FORCE_WB = 2147483648,\n\tI915_MAP_FORCE_WC = 2147483649,\n};\n\nstruct cb_kernel {\n\tconst void *data;\n\tu32 size;\n};\n\nstruct batch_chunk {\n\tstruct i915_vma *vma;\n\tu32 offset;\n\tu32 *start;\n\tu32 *end;\n\tu32 max_items;\n};\n\nstruct batch_vals {\n\tu32 max_primitives;\n\tu32 max_urb_entries;\n\tu32 cmd_size;\n\tu32 state_size;\n\tu32 state_start;\n\tu32 batch_size;\n\tu32 surface_height;\n\tu32 surface_width;\n\tu32 scratch_size;\n\tu32 max_size;\n};\n\ntypedef u64 gen8_pte_t;\n\nenum vgt_g2v_type {\n\tVGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,\n\tVGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY = 3,\n\tVGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE = 4,\n\tVGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY = 5,\n\tVGT_G2V_EXECLIST_CONTEXT_CREATE = 6,\n\tVGT_G2V_EXECLIST_CONTEXT_DESTROY = 7,\n\tVGT_G2V_MAX = 8,\n};\n\nenum {\n\tI915_FENCE_FLAG_ACTIVE = 3,\n\tI915_FENCE_FLAG_PQUEUE = 4,\n\tI915_FENCE_FLAG_HOLD = 5,\n\tI915_FENCE_FLAG_INITIAL_BREADCRUMB = 6,\n\tI915_FENCE_FLAG_SIGNAL = 7,\n\tI915_FENCE_FLAG_NOPREEMPT = 8,\n\tI915_FENCE_FLAG_SENTINEL = 9,\n\tI915_FENCE_FLAG_BOOST = 10,\n};\n\ntypedef void (*i915_global_func_t)();\n\nstruct i915_global {\n\tstruct list_head link;\n\ti915_global_func_t shrink;\n\ti915_global_func_t exit;\n};\n\nstruct i915_global_context {\n\tstruct i915_global base;\n\tstruct kmem_cache *slab_ce;\n};\n\nstruct engine_mmio_base {\n\tu32 gen: 8;\n\tu32 base: 24;\n};\n\nstruct engine_info {\n\tunsigned int hw_id;\n\tu8 class;\n\tu8 instance;\n\tstruct engine_mmio_base mmio_bases[3];\n};\n\nstruct measure_breadcrumb {\n\tstruct i915_request rq;\n\tstruct intel_ring ring;\n\tu32 cs[2048];\n};\n\nenum {\n\tI915_PRIORITY_MIN = 4294966272,\n\tI915_PRIORITY_NORMAL = 0,\n\tI915_PRIORITY_MAX = 1024,\n\tI915_PRIORITY_HEARTBEAT = 1025,\n\tI915_PRIORITY_DISPLAY = 1026,\n};\n\nstruct legacy_ring {\n\tstruct intel_gt *gt;\n\tu8 class;\n\tu8 instance;\n};\n\nstruct insert_page {\n\tstruct i915_address_space *vm;\n\tdma_addr_t addr;\n\tu64 offset;\n\tenum i915_cache_level level;\n};\n\nstruct insert_entries {\n\tstruct i915_address_space *vm;\n\tstruct i915_vma *vma;\n\tenum i915_cache_level level;\n\tu32 flags;\n};\n\nstruct intel_renderstate_rodata {\n\tconst u32 *reloc;\n\tconst u32 *batch;\n\tconst u32 batch_items;\n};\n\nstruct intel_renderstate {\n\tconst struct intel_renderstate_rodata *rodata;\n\tstruct i915_vma *vma;\n\tu32 batch_offset;\n\tu32 batch_size;\n\tu32 aux_offset;\n\tu32 aux_size;\n};\n\nstruct intel_gt_buffer_pool_node {\n\tstruct i915_active active;\n\tstruct drm_i915_gem_object *obj;\n\tstruct list_head link;\n\tstruct intel_gt_buffer_pool *pool;\n\tlong unsigned int age;\n};\n\nstruct ia_constants {\n\tunsigned int min_gpu_freq;\n\tunsigned int max_gpu_freq;\n\tunsigned int min_ring_freq;\n\tunsigned int max_ia_freq;\n};\n\nenum {\n\tINTEL_ADVANCED_CONTEXT = 0,\n\tINTEL_LEGACY_32B_CONTEXT = 1,\n\tINTEL_ADVANCED_AD_CONTEXT = 2,\n\tINTEL_LEGACY_64B_CONTEXT = 3,\n};\n\nenum {\n\tINTEL_CONTEXT_SCHEDULE_IN = 0,\n\tINTEL_CONTEXT_SCHEDULE_OUT = 1,\n\tINTEL_CONTEXT_SCHEDULE_PREEMPTED = 2,\n};\n\nenum intel_gt_scratch_field {\n\tINTEL_GT_SCRATCH_FIELD_DEFAULT = 0,\n\tINTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128,\n\tINTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,\n\tINTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,\n\tINTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,\n};\n\nstruct ve_node {\n\tstruct rb_node rb;\n\tint prio;\n};\n\nstruct ve_bond {\n\tconst struct intel_engine_cs *master;\n\tintel_engine_mask_t sibling_mask;\n};\n\nstruct virtual_engine {\n\tstruct intel_engine_cs base;\n\tstruct intel_context context;\n\tstruct i915_request *request;\n\tstruct ve_node nodes[8];\n\tstruct ve_bond *bonds;\n\tunsigned int num_bonds;\n\tunsigned int num_siblings;\n\tstruct intel_engine_cs *siblings[0];\n};\n\nstruct execlists_capture {\n\tstruct work_struct work;\n\tstruct i915_request *rq;\n\tstruct i915_gpu_coredump *error;\n};\n\nstruct lri {\n\ti915_reg_t reg;\n\tu32 value;\n};\n\ntypedef u32 * (*wa_bb_func_t)(struct intel_engine_cs *, u32 *);\n\nstruct intel_engine_capture_vma;\n\nstruct i915_vma_compress;\n\nenum i915_mocs_table_index {\n\tI915_MOCS_UNCACHED = 0,\n\tI915_MOCS_PTE = 1,\n\tI915_MOCS_CACHED = 2,\n};\n\nstruct drm_i915_mocs_entry {\n\tu32 control_value;\n\tu16 l3cc_value;\n\tu16 used;\n};\n\nstruct drm_i915_mocs_table {\n\tunsigned int size;\n\tunsigned int n_entries;\n\tconst struct drm_i915_mocs_entry *table;\n};\n\nenum {\n\tHAS_GLOBAL_MOCS = 1,\n\tHAS_ENGINE_MOCS = 2,\n\tHAS_RENDER_L3CC = 4,\n};\n\nstruct intel_wedge_me {\n\tstruct delayed_work work;\n\tstruct intel_gt *gt;\n\tconst char *name;\n};\n\ntypedef int (*reset_func)(struct intel_gt *, intel_engine_mask_t, unsigned int);\n\nstruct cparams {\n\tu16 i;\n\tu16 t;\n\tu16 m;\n\tu16 c;\n};\n\nstruct intel_timeline_hwsp {\n\tstruct intel_gt *gt;\n\tstruct intel_gt_timelines *gt_timelines;\n\tstruct list_head free_link;\n\tstruct i915_vma *vma;\n\tu64 free_bitmap;\n};\n\nstruct kobj_engine {\n\tstruct kobject base;\n\tstruct intel_engine_cs *engine;\n};\n\nstruct drm_i915_gem_busy {\n\t__u32 handle;\n\t__u32 busy;\n};\n\nenum fb_op_origin {\n\tORIGIN_GTT = 0,\n\tORIGIN_CPU = 1,\n\tORIGIN_CS = 2,\n\tORIGIN_FLIP = 3,\n\tORIGIN_DIRTYFB = 4,\n};\n\nstruct clflush {\n\tstruct dma_fence_work base;\n\tstruct drm_i915_gem_object *obj;\n};\n\nstruct i915_sleeve {\n\tstruct i915_vma *vma;\n\tstruct drm_i915_gem_object *obj;\n\tstruct sg_table *pages;\n\tstruct i915_page_sizes page_sizes;\n};\n\nstruct clear_pages_work {\n\tstruct dma_fence dma;\n\tstruct dma_fence_cb cb;\n\tstruct i915_sw_fence wait;\n\tstruct work_struct work;\n\tstruct irq_work irq_work;\n\tstruct i915_sleeve *sleeve;\n\tstruct intel_context *ce;\n\tu32 value;\n};\n\nstruct i915_engine_class_instance {\n\t__u16 engine_class;\n\t__u16 engine_instance;\n};\n\nstruct drm_i915_gem_context_create_ext {\n\t__u32 ctx_id;\n\t__u32 flags;\n\t__u64 extensions;\n};\n\nstruct drm_i915_gem_context_param {\n\t__u32 ctx_id;\n\t__u32 size;\n\t__u64 param;\n\t__u64 value;\n};\n\nstruct drm_i915_gem_context_param_sseu {\n\tstruct i915_engine_class_instance engine;\n\t__u32 flags;\n\t__u64 slice_mask;\n\t__u64 subslice_mask;\n\t__u16 min_eus_per_subslice;\n\t__u16 max_eus_per_subslice;\n\t__u32 rsvd;\n};\n\nstruct i915_context_engines_load_balance {\n\tstruct i915_user_extension base;\n\t__u16 engine_index;\n\t__u16 num_siblings;\n\t__u32 flags;\n\t__u64 mbz64;\n\tstruct i915_engine_class_instance engines[0];\n};\n\nstruct i915_context_engines_bond {\n\tstruct i915_user_extension base;\n\tstruct i915_engine_class_instance master;\n\t__u16 virtual_index;\n\t__u16 num_bonds;\n\t__u64 flags;\n\t__u64 mbz64[4];\n\tstruct i915_engine_class_instance engines[0];\n};\n\nstruct i915_context_param_engines {\n\t__u64 extensions;\n\tstruct i915_engine_class_instance engines[0];\n};\n\nstruct drm_i915_gem_context_create_ext_setparam {\n\tstruct i915_user_extension base;\n\tstruct drm_i915_gem_context_param param;\n};\n\nstruct drm_i915_gem_context_create_ext_clone {\n\tstruct i915_user_extension base;\n\t__u32 clone_id;\n\t__u32 flags;\n\t__u64 rsvd;\n};\n\nstruct drm_i915_gem_context_destroy {\n\t__u32 ctx_id;\n\t__u32 pad;\n};\n\nstruct drm_i915_gem_vm_control {\n\t__u64 extensions;\n\t__u32 flags;\n\t__u32 vm_id;\n};\n\nstruct drm_i915_reset_stats {\n\t__u32 ctx_id;\n\t__u32 flags;\n\t__u32 reset_count;\n\t__u32 batch_active;\n\t__u32 batch_pending;\n\t__u32 pad;\n};\n\nstruct i915_lut_handle {\n\tstruct list_head obj_link;\n\tstruct i915_gem_context *ctx;\n\tu32 handle;\n};\n\nstruct i915_global_gem_context {\n\tstruct i915_global base;\n\tstruct kmem_cache *slab_luts;\n};\n\nstruct context_barrier_task {\n\tstruct i915_active base;\n\tvoid (*task)(void *);\n\tvoid *data;\n};\n\nstruct set_engines {\n\tstruct i915_gem_context *ctx;\n\tstruct i915_gem_engines *engines;\n};\n\nstruct create_ext {\n\tstruct i915_gem_context *ctx;\n\tstruct drm_i915_file_private *fpriv;\n};\n\nstruct drm_i915_gem_set_domain {\n\t__u32 handle;\n\t__u32 read_domains;\n\t__u32 write_domain;\n};\n\nstruct drm_i915_gem_caching {\n\t__u32 handle;\n\t__u32 caching;\n};\n\nstruct drm_i915_gem_relocation_entry {\n\t__u32 target_handle;\n\t__u32 delta;\n\t__u64 offset;\n\t__u64 presumed_offset;\n\t__u32 read_domains;\n\t__u32 write_domain;\n};\n\nstruct drm_i915_gem_exec_object {\n\t__u32 handle;\n\t__u32 relocation_count;\n\t__u64 relocs_ptr;\n\t__u64 alignment;\n\t__u64 offset;\n};\n\nstruct drm_i915_gem_execbuffer {\n\t__u64 buffers_ptr;\n\t__u32 buffer_count;\n\t__u32 batch_start_offset;\n\t__u32 batch_len;\n\t__u32 DR1;\n\t__u32 DR4;\n\t__u32 num_cliprects;\n\t__u64 cliprects_ptr;\n};\n\nstruct drm_i915_gem_exec_object2 {\n\t__u32 handle;\n\t__u32 relocation_count;\n\t__u64 relocs_ptr;\n\t__u64 alignment;\n\t__u64 offset;\n\t__u64 flags;\n\tunion {\n\t\t__u64 rsvd1;\n\t\t__u64 pad_to_size;\n\t};\n\t__u64 rsvd2;\n};\n\nstruct drm_i915_gem_exec_fence {\n\t__u32 handle;\n\t__u32 flags;\n};\n\nstruct drm_i915_gem_execbuffer2 {\n\t__u64 buffers_ptr;\n\t__u32 buffer_count;\n\t__u32 batch_start_offset;\n\t__u32 batch_len;\n\t__u32 DR1;\n\t__u32 DR4;\n\t__u32 num_cliprects;\n\t__u64 cliprects_ptr;\n\t__u64 flags;\n\t__u64 rsvd1;\n\t__u64 rsvd2;\n};\n\nstruct eb_vma {\n\tstruct i915_vma *vma;\n\tunsigned int flags;\n\tstruct drm_i915_gem_exec_object2 *exec;\n\tstruct list_head bind_link;\n\tstruct list_head reloc_link;\n\tstruct hlist_node node;\n\tu32 handle;\n};\n\nstruct eb_vma_array {\n\tstruct kref kref;\n\tstruct eb_vma vma[0];\n};\n\nenum {\n\tFORCE_CPU_RELOC = 1,\n\tFORCE_GTT_RELOC = 2,\n\tFORCE_GPU_RELOC = 3,\n};\n\nstruct reloc_cache {\n\tstruct drm_mm_node node;\n\tlong unsigned int vaddr;\n\tlong unsigned int page;\n\tunsigned int gen;\n\tbool use_64bit_reloc: 1;\n\tbool has_llc: 1;\n\tbool has_fence: 1;\n\tbool needs_unfenced: 1;\n\tstruct i915_vma *target;\n\tstruct i915_request *rq;\n\tstruct i915_vma *rq_vma;\n\tu32 *rq_cmd;\n\tunsigned int rq_size;\n};\n\nstruct i915_execbuffer {\n\tstruct drm_i915_private *i915;\n\tstruct drm_file *file;\n\tstruct drm_i915_gem_execbuffer2 *args;\n\tstruct drm_i915_gem_exec_object2 *exec;\n\tstruct eb_vma *vma;\n\tstruct intel_engine_cs *engine;\n\tstruct intel_context *context;\n\tstruct i915_gem_context *gem_context;\n\tstruct i915_request *request;\n\tstruct eb_vma *batch;\n\tstruct i915_vma *trampoline;\n\tunsigned int buffer_count;\n\tstruct list_head unbound;\n\tstruct list_head relocs;\n\tstruct reloc_cache reloc_cache;\n\tu64 invalid_flags;\n\tu32 context_flags;\n\tu32 batch_start_offset;\n\tu32 batch_len;\n\tu32 batch_flags;\n\tint lut_size;\n\tstruct hlist_head *buckets;\n\tstruct eb_vma_array *array;\n};\n\nstruct eb_parse_work {\n\tstruct dma_fence_work base;\n\tstruct intel_engine_cs *engine;\n\tstruct i915_vma *batch;\n\tstruct i915_vma *shadow;\n\tstruct i915_vma *trampoline;\n\tunsigned int batch_offset;\n\tunsigned int batch_length;\n};\n\nstruct stub_fence {\n\tstruct dma_fence dma;\n\tstruct i915_sw_fence chain;\n};\n\nstruct i915_global_object {\n\tstruct i915_global base;\n\tstruct kmem_cache *slab_objects;\n};\n\nstruct drm_i915_gem_mmap {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 size;\n\t__u64 addr_ptr;\n\t__u64 flags;\n};\n\nstruct drm_i915_gem_mmap_offset {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 flags;\n\t__u64 extensions;\n};\n\nstruct drm_i915_gem_set_tiling {\n\t__u32 handle;\n\t__u32 tiling_mode;\n\t__u32 stride;\n\t__u32 swizzle_mode;\n};\n\nstruct drm_i915_gem_get_tiling {\n\t__u32 handle;\n\t__u32 tiling_mode;\n\t__u32 swizzle_mode;\n\t__u32 phys_swizzle_mode;\n};\n\nstruct drm_i915_gem_userptr {\n\t__u64 user_ptr;\n\t__u64 user_size;\n\t__u32 flags;\n\t__u32 handle;\n};\n\nstruct i915_mmu_notifier;\n\nstruct i915_mm_struct {\n\tstruct mm_struct *mm;\n\tstruct drm_i915_private *i915;\n\tstruct i915_mmu_notifier *mn;\n\tstruct hlist_node node;\n\tstruct kref kref;\n\tstruct work_struct work;\n};\n\nstruct i915_mmu_object {\n\tstruct i915_mmu_notifier *mn;\n\tstruct drm_i915_gem_object *obj;\n\tstruct interval_tree_node it;\n};\n\nstruct i915_mmu_notifier {\n\tspinlock_t lock;\n\tstruct hlist_node node;\n\tstruct mmu_notifier mn;\n\tstruct rb_root_cached objects;\n\tstruct i915_mm_struct *mm;\n};\n\nstruct get_pages_work {\n\tstruct work_struct work;\n\tstruct drm_i915_gem_object *obj;\n\tstruct task_struct *task;\n};\n\nstruct dma_fence_array {\n\tstruct dma_fence base;\n\tspinlock_t lock;\n\tunsigned int num_fences;\n\tatomic_t num_pending;\n\tstruct dma_fence **fences;\n\tstruct irq_work work;\n};\n\nstruct drm_i915_gem_wait {\n\t__u32 bo_handle;\n\t__u32 flags;\n\t__s64 timeout_ns;\n};\n\nstruct active_node {\n\tstruct i915_active_fence base;\n\tstruct i915_active *ref;\n\tstruct rb_node node;\n\tu64 timeline;\n};\n\nstruct i915_global_active {\n\tstruct i915_global base;\n\tstruct kmem_cache *slab_cache;\n};\n\nstruct wait_barrier {\n\tstruct wait_queue_entry base;\n\tstruct i915_active *ref;\n};\n\nstruct auto_active {\n\tstruct i915_active base;\n\tstruct kref ref;\n};\n\nstruct i915_global_block {\n\tstruct i915_global base;\n\tstruct kmem_cache *slab_blocks;\n};\n\nstruct drm_i915_cmd_descriptor {\n\tu32 flags;\n\tstruct {\n\t\tu32 value;\n\t\tu32 mask;\n\t} cmd;\n\tunion {\n\t\tu32 fixed;\n\t\tu32 mask;\n\t} length;\n\tstruct {\n\t\tu32 offset;\n\t\tu32 mask;\n\t\tu32 step;\n\t} reg;\n\tstruct {\n\t\tu32 offset;\n\t\tu32 mask;\n\t\tu32 expected;\n\t\tu32 condition_offset;\n\t\tu32 condition_mask;\n\t} bits[3];\n};\n\nstruct drm_i915_cmd_table {\n\tconst struct drm_i915_cmd_descriptor *table;\n\tint count;\n};\n\nstruct drm_i915_reg_descriptor {\n\ti915_reg_t addr;\n\tu32 mask;\n\tu32 value;\n};\n\nstruct cmd_node {\n\tconst struct drm_i915_cmd_descriptor *desc;\n\tstruct hlist_node node;\n};\n\nstruct drm_i915_gem_create {\n\t__u64 size;\n\t__u32 handle;\n\t__u32 pad;\n};\n\nstruct drm_i915_gem_pread {\n\t__u32 handle;\n\t__u32 pad;\n\t__u64 offset;\n\t__u64 size;\n\t__u64 data_ptr;\n};\n\nstruct drm_i915_gem_sw_finish {\n\t__u32 handle;\n};\n\nstruct drm_i915_gem_get_aperture {\n\t__u64 aper_size;\n\t__u64 aper_available_size;\n};\n\nstruct drm_i915_gem_madvise {\n\t__u32 handle;\n\t__u32 madv;\n\t__u32 retained;\n};\n\nstruct park_work {\n\tstruct delayed_work work;\n\tstruct callback_head rcu;\n\tlong unsigned int flags;\n\tint epoch;\n};\n\nstruct drm_i915_perf_oa_config {\n\tchar uuid[36];\n\t__u32 n_mux_regs;\n\t__u32 n_boolean_regs;\n\t__u32 n_flex_regs;\n\t__u64 mux_regs_ptr;\n\t__u64 boolean_regs_ptr;\n\t__u64 flex_regs_ptr;\n};\n\nstruct drm_i915_query_item {\n\t__u64 query_id;\n\t__s32 length;\n\t__u32 flags;\n\t__u64 data_ptr;\n};\n\nstruct drm_i915_query {\n\t__u32 num_items;\n\t__u32 flags;\n\t__u64 items_ptr;\n};\n\nstruct drm_i915_query_topology_info {\n\t__u16 flags;\n\t__u16 max_slices;\n\t__u16 max_subslices;\n\t__u16 max_eus_per_subslice;\n\t__u16 subslice_offset;\n\t__u16 subslice_stride;\n\t__u16 eu_offset;\n\t__u16 eu_stride;\n\t__u8 data[0];\n};\n\nstruct drm_i915_engine_info {\n\tstruct i915_engine_class_instance engine;\n\t__u32 rsvd0;\n\t__u64 flags;\n\t__u64 capabilities;\n\t__u64 rsvd1[4];\n};\n\nstruct drm_i915_query_engine_info {\n\t__u32 num_engines;\n\t__u32 rsvd[3];\n\tstruct drm_i915_engine_info engines[0];\n};\n\nstruct drm_i915_query_perf_config {\n\tunion {\n\t\t__u64 n_configs;\n\t\t__u64 config;\n\t\tchar uuid[36];\n\t};\n\t__u32 flags;\n\t__u8 data[0];\n};\n\nstruct execute_cb {\n\tstruct list_head link;\n\tstruct irq_work work;\n\tstruct i915_sw_fence *fence;\n\tvoid (*hook)(struct i915_request *, struct dma_fence *);\n\tstruct i915_request *signal;\n};\n\nstruct i915_global_request {\n\tstruct i915_global base;\n\tstruct kmem_cache *slab_requests;\n\tstruct kmem_cache *slab_execute_cbs;\n};\n\nstruct request_wait {\n\tstruct dma_fence_cb cb;\n\tstruct task_struct *tsk;\n};\n\nstruct i915_global_scheduler {\n\tstruct i915_global base;\n\tstruct kmem_cache *slab_dependencies;\n\tstruct kmem_cache *slab_priorities;\n};\n\nstruct sched_cache {\n\tstruct list_head *priolist;\n};\n\nstruct trace_event_raw_intel_pipe_enable {\n\tstruct trace_entry ent;\n\tu32 frame[3];\n\tu32 scanline[3];\n\tenum pipe pipe;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_disable {\n\tstruct trace_entry ent;\n\tu32 frame[3];\n\tu32 scanline[3];\n\tenum pipe pipe;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_crc {\n\tstruct trace_entry ent;\n\tenum pipe pipe;\n\tu32 frame;\n\tu32 scanline;\n\tu32 crcs[5];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_cpu_fifo_underrun {\n\tstruct trace_entry ent;\n\tenum pipe pipe;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pch_fifo_underrun {\n\tstruct trace_entry ent;\n\tenum pipe pipe;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_memory_cxsr {\n\tstruct trace_entry ent;\n\tu32 frame[3];\n\tu32 scanline[3];\n\tbool old;\n\tbool new;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_g4x_wm {\n\tstruct trace_entry ent;\n\tenum pipe pipe;\n\tu32 frame;\n\tu32 scanline;\n\tu16 primary;\n\tu16 sprite;\n\tu16 cursor;\n\tu16 sr_plane;\n\tu16 sr_cursor;\n\tu16 sr_fbc;\n\tu16 hpll_plane;\n\tu16 hpll_cursor;\n\tu16 hpll_fbc;\n\tbool cxsr;\n\tbool hpll;\n\tbool fbc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vlv_wm {\n\tstruct trace_entry ent;\n\tenum pipe pipe;\n\tu32 frame;\n\tu32 scanline;\n\tu32 level;\n\tu32 cxsr;\n\tu32 primary;\n\tu32 sprite0;\n\tu32 sprite1;\n\tu32 cursor;\n\tu32 sr_plane;\n\tu32 sr_cursor;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_vlv_fifo_size {\n\tstruct trace_entry ent;\n\tenum pipe pipe;\n\tu32 frame;\n\tu32 scanline;\n\tu32 sprite0_start;\n\tu32 sprite1_start;\n\tu32 fifo_size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_update_plane {\n\tstruct trace_entry ent;\n\tenum pipe pipe;\n\tu32 frame;\n\tu32 scanline;\n\tint src[4];\n\tint dst[4];\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_disable_plane {\n\tstruct trace_entry ent;\n\tenum pipe pipe;\n\tu32 frame;\n\tu32 scanline;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_fbc_activate {\n\tstruct trace_entry ent;\n\tenum pipe pipe;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_fbc_deactivate {\n\tstruct trace_entry ent;\n\tenum pipe pipe;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_fbc_nuke {\n\tstruct trace_entry ent;\n\tenum pipe pipe;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_update_start {\n\tstruct trace_entry ent;\n\tenum pipe pipe;\n\tu32 frame;\n\tu32 scanline;\n\tu32 min;\n\tu32 max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_update_vblank_evaded {\n\tstruct trace_entry ent;\n\tenum pipe pipe;\n\tu32 frame;\n\tu32 scanline;\n\tu32 min;\n\tu32 max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_pipe_update_end {\n\tstruct trace_entry ent;\n\tenum pipe pipe;\n\tu32 frame;\n\tu32 scanline;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object_create {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tu64 size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_shrink {\n\tstruct trace_entry ent;\n\tint dev;\n\tlong unsigned int target;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_vma_bind {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tstruct i915_address_space *vm;\n\tu64 offset;\n\tu64 size;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_vma_unbind {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tstruct i915_address_space *vm;\n\tu64 offset;\n\tu64 size;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object_pwrite {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tu64 offset;\n\tu64 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object_pread {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tu64 offset;\n\tu64 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object_fault {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tu64 index;\n\tbool gtt;\n\tbool write;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_object {\n\tstruct trace_entry ent;\n\tstruct drm_i915_gem_object *obj;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_evict {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tstruct i915_address_space *vm;\n\tu64 size;\n\tu64 align;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_evict_node {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tstruct i915_address_space *vm;\n\tu64 start;\n\tu64 size;\n\tlong unsigned int color;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_gem_evict_vm {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tstruct i915_address_space *vm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_request_queue {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tu64 ctx;\n\tu16 class;\n\tu16 instance;\n\tu32 seqno;\n\tu32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_request {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tu64 ctx;\n\tu16 class;\n\tu16 instance;\n\tu32 seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_request_wait_begin {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tu64 ctx;\n\tu16 class;\n\tu16 instance;\n\tu32 seqno;\n\tunsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_reg_rw {\n\tstruct trace_entry ent;\n\tu64 val;\n\tu32 reg;\n\tu16 write;\n\tu16 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_intel_gpu_freq_change {\n\tstruct trace_entry ent;\n\tu32 freq;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_ppgtt {\n\tstruct trace_entry ent;\n\tstruct i915_address_space *vm;\n\tu32 dev;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i915_context {\n\tstruct trace_entry ent;\n\tu32 dev;\n\tstruct i915_gem_context *ctx;\n\tstruct i915_address_space *vm;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_intel_pipe_enable {};\n\nstruct trace_event_data_offsets_intel_pipe_disable {};\n\nstruct trace_event_data_offsets_intel_pipe_crc {};\n\nstruct trace_event_data_offsets_intel_cpu_fifo_underrun {};\n\nstruct trace_event_data_offsets_intel_pch_fifo_underrun {};\n\nstruct trace_event_data_offsets_intel_memory_cxsr {};\n\nstruct trace_event_data_offsets_g4x_wm {};\n\nstruct trace_event_data_offsets_vlv_wm {};\n\nstruct trace_event_data_offsets_vlv_fifo_size {};\n\nstruct trace_event_data_offsets_intel_update_plane {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_intel_disable_plane {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_intel_fbc_activate {};\n\nstruct trace_event_data_offsets_intel_fbc_deactivate {};\n\nstruct trace_event_data_offsets_intel_fbc_nuke {};\n\nstruct trace_event_data_offsets_intel_pipe_update_start {};\n\nstruct trace_event_data_offsets_intel_pipe_update_vblank_evaded {};\n\nstruct trace_event_data_offsets_intel_pipe_update_end {};\n\nstruct trace_event_data_offsets_i915_gem_object_create {};\n\nstruct trace_event_data_offsets_i915_gem_shrink {};\n\nstruct trace_event_data_offsets_i915_vma_bind {};\n\nstruct trace_event_data_offsets_i915_vma_unbind {};\n\nstruct trace_event_data_offsets_i915_gem_object_pwrite {};\n\nstruct trace_event_data_offsets_i915_gem_object_pread {};\n\nstruct trace_event_data_offsets_i915_gem_object_fault {};\n\nstruct trace_event_data_offsets_i915_gem_object {};\n\nstruct trace_event_data_offsets_i915_gem_evict {};\n\nstruct trace_event_data_offsets_i915_gem_evict_node {};\n\nstruct trace_event_data_offsets_i915_gem_evict_vm {};\n\nstruct trace_event_data_offsets_i915_request_queue {};\n\nstruct trace_event_data_offsets_i915_request {};\n\nstruct trace_event_data_offsets_i915_request_wait_begin {};\n\nstruct trace_event_data_offsets_i915_reg_rw {};\n\nstruct trace_event_data_offsets_intel_gpu_freq_change {};\n\nstruct trace_event_data_offsets_i915_ppgtt {};\n\nstruct trace_event_data_offsets_i915_context {};\n\ntypedef void (*btf_trace_intel_pipe_enable)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_pipe_disable)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_pipe_crc)(void *, struct intel_crtc *, const u32 *);\n\ntypedef void (*btf_trace_intel_cpu_fifo_underrun)(void *, struct drm_i915_private *, enum pipe);\n\ntypedef void (*btf_trace_intel_pch_fifo_underrun)(void *, struct drm_i915_private *, enum pipe);\n\ntypedef void (*btf_trace_intel_memory_cxsr)(void *, struct drm_i915_private *, bool, bool);\n\ntypedef void (*btf_trace_g4x_wm)(void *, struct intel_crtc *, const struct g4x_wm_values *);\n\ntypedef void (*btf_trace_vlv_wm)(void *, struct intel_crtc *, const struct vlv_wm_values *);\n\ntypedef void (*btf_trace_vlv_fifo_size)(void *, struct intel_crtc *, u32, u32, u32);\n\ntypedef void (*btf_trace_intel_update_plane)(void *, struct drm_plane *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_disable_plane)(void *, struct drm_plane *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_fbc_activate)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_fbc_deactivate)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_fbc_nuke)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_pipe_update_start)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_pipe_update_vblank_evaded)(void *, struct intel_crtc *);\n\ntypedef void (*btf_trace_intel_pipe_update_end)(void *, struct intel_crtc *, u32, int);\n\ntypedef void (*btf_trace_i915_gem_object_create)(void *, struct drm_i915_gem_object *);\n\ntypedef void (*btf_trace_i915_gem_shrink)(void *, struct drm_i915_private *, long unsigned int, unsigned int);\n\ntypedef void (*btf_trace_i915_vma_bind)(void *, struct i915_vma *, unsigned int);\n\ntypedef void (*btf_trace_i915_vma_unbind)(void *, struct i915_vma *);\n\ntypedef void (*btf_trace_i915_gem_object_pwrite)(void *, struct drm_i915_gem_object *, u64, u64);\n\ntypedef void (*btf_trace_i915_gem_object_pread)(void *, struct drm_i915_gem_object *, u64, u64);\n\ntypedef void (*btf_trace_i915_gem_object_fault)(void *, struct drm_i915_gem_object *, u64, bool, bool);\n\ntypedef void (*btf_trace_i915_gem_object_clflush)(void *, struct drm_i915_gem_object *);\n\ntypedef void (*btf_trace_i915_gem_object_destroy)(void *, struct drm_i915_gem_object *);\n\ntypedef void (*btf_trace_i915_gem_evict)(void *, struct i915_address_space *, u64, u64, unsigned int);\n\ntypedef void (*btf_trace_i915_gem_evict_node)(void *, struct i915_address_space *, struct drm_mm_node *, unsigned int);\n\ntypedef void (*btf_trace_i915_gem_evict_vm)(void *, struct i915_address_space *);\n\ntypedef void (*btf_trace_i915_request_queue)(void *, struct i915_request *, u32);\n\ntypedef void (*btf_trace_i915_request_add)(void *, struct i915_request *);\n\ntypedef void (*btf_trace_i915_request_retire)(void *, struct i915_request *);\n\ntypedef void (*btf_trace_i915_request_wait_begin)(void *, struct i915_request *, unsigned int);\n\ntypedef void (*btf_trace_i915_request_wait_end)(void *, struct i915_request *);\n\ntypedef void (*btf_trace_i915_reg_rw)(void *, bool, i915_reg_t, u64, int, bool);\n\ntypedef void (*btf_trace_intel_gpu_freq_change)(void *, u32);\n\ntypedef void (*btf_trace_i915_ppgtt_create)(void *, struct i915_address_space *);\n\ntypedef void (*btf_trace_i915_ppgtt_release)(void *, struct i915_address_space *);\n\ntypedef void (*btf_trace_i915_context_create)(void *, struct i915_gem_context *);\n\ntypedef void (*btf_trace_i915_context_free)(void *, struct i915_gem_context *);\n\nstruct i915_global_vma {\n\tstruct i915_global base;\n\tstruct kmem_cache *slab_vmas;\n};\n\nstruct i915_vma_work {\n\tstruct dma_fence_work base;\n\tstruct i915_vma *vma;\n\tstruct drm_i915_gem_object *pinned;\n\tstruct i915_sw_dma_fence_cb cb;\n\tenum i915_cache_level cache_level;\n\tunsigned int flags;\n};\n\nstruct uc_css_header {\n\tu32 module_type;\n\tu32 header_size_dw;\n\tu32 header_version;\n\tu32 module_id;\n\tu32 module_vendor;\n\tu32 date;\n\tu32 size_dw;\n\tu32 key_size_dw;\n\tu32 modulus_size_dw;\n\tu32 exponent_size_dw;\n\tu32 time;\n\tchar username[8];\n\tchar buildnumber[12];\n\tu32 sw_version;\n\tu32 reserved[14];\n\tu32 header_info;\n};\n\nstruct uc_fw_blob {\n\tu8 major;\n\tu8 minor;\n\tconst char *path;\n} __attribute__((packed));\n\nstruct uc_fw_platform_requirement {\n\tenum intel_platform p;\n\tu8 rev;\n\tconst struct uc_fw_blob blobs[2];\n} __attribute__((packed));\n\nenum intel_guc_msg_type {\n\tINTEL_GUC_MSG_TYPE_REQUEST = 0,\n\tINTEL_GUC_MSG_TYPE_RESPONSE = 15,\n};\n\nenum intel_guc_action {\n\tINTEL_GUC_ACTION_DEFAULT = 0,\n\tINTEL_GUC_ACTION_REQUEST_PREEMPTION = 2,\n\tINTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 3,\n\tINTEL_GUC_ACTION_ALLOCATE_DOORBELL = 16,\n\tINTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 32,\n\tINTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 48,\n\tINTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 64,\n\tINTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 770,\n\tINTEL_GUC_ACTION_ENTER_S_STATE = 1281,\n\tINTEL_GUC_ACTION_EXIT_S_STATE = 1282,\n\tINTEL_GUC_ACTION_SLPC_REQUEST = 12291,\n\tINTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 12293,\n\tINTEL_GUC_ACTION_AUTHENTICATE_HUC = 16384,\n\tINTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 17669,\n\tINTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 17670,\n\tINTEL_GUC_ACTION_LIMIT = 17671,\n};\n\nenum intel_guc_sleep_state_status {\n\tINTEL_GUC_SLEEP_STATE_SUCCESS = 1,\n\tINTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 2,\n\tINTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 3,\n};\n\nenum intel_guc_response_status {\n\tINTEL_GUC_RESPONSE_STATUS_SUCCESS = 0,\n\tINTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 61440,\n};\n\nenum intel_guc_recv_message {\n\tINTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = 2,\n\tINTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = 8,\n};\n\nstruct guc_policy {\n\tu32 execution_quantum;\n\tu32 preemption_time;\n\tu32 fault_time;\n\tu32 policy_flags;\n\tu32 reserved[8];\n};\n\nstruct guc_policies {\n\tstruct guc_policy policy[20];\n\tu32 submission_queue_depth[5];\n\tu32 dpc_promote_time;\n\tu32 is_valid;\n\tu32 max_num_work_items;\n\tu32 reserved[4];\n};\n\nstruct guc_mmio_reg {\n\tu32 offset;\n\tu32 value;\n\tu32 flags;\n};\n\nstruct guc_mmio_regset {\n\tstruct guc_mmio_reg registers[64];\n\tu32 values_valid;\n\tu32 number_of_registers;\n};\n\nstruct guc_mmio_reg_state {\n\tstruct guc_mmio_regset engine_reg[80];\n\tu32 reserved[98];\n};\n\nstruct guc_gt_system_info {\n\tu32 slice_enabled;\n\tu32 rcs_enabled;\n\tu32 reserved0;\n\tu32 bcs_enabled;\n\tu32 vdbox_enable_mask;\n\tu32 vdbox_sfc_support_mask;\n\tu32 vebox_enable_mask;\n\tu32 reserved[9];\n};\n\nstruct guc_ct_pool_entry {\n\tstruct guc_ct_buffer_desc desc;\n\tu32 reserved[7];\n} __attribute__((packed));\n\nstruct guc_clients_info {\n\tu32 clients_num;\n\tu32 reserved0[13];\n\tu32 ct_pool_addr;\n\tu32 ct_pool_count;\n\tu32 reserved[4];\n};\n\nstruct guc_ads {\n\tu32 reg_state_addr;\n\tu32 reg_state_buffer;\n\tu32 scheduler_policies;\n\tu32 gt_system_info;\n\tu32 clients_info;\n\tu32 control_data;\n\tu32 golden_context_lrca[5];\n\tu32 eng_state_size[5];\n\tu32 reserved[16];\n};\n\nstruct __guc_ads_blob {\n\tstruct guc_ads ads;\n\tstruct guc_policies policies;\n\tstruct guc_mmio_reg_state reg_state;\n\tstruct guc_gt_system_info system_info;\n\tstruct guc_clients_info clients_info;\n\tstruct guc_ct_pool_entry ct_pool[2];\n\tu8 reg_state_buffer[40960];\n};\n\nstruct ct_request {\n\tstruct list_head link;\n\tu32 fence;\n\tu32 status;\n\tu32 response_len;\n\tu32 *response_buf;\n};\n\nstruct ct_incoming_request {\n\tstruct list_head link;\n\tu32 msg[0];\n};\n\nenum {\n\tCTB_SEND = 0,\n\tCTB_RECV = 1,\n};\n\nenum {\n\tCTB_OWNER_HOST = 0,\n};\n\nstruct guc_log_buffer_state {\n\tu32 marker[2];\n\tu32 read_ptr;\n\tu32 write_ptr;\n\tu32 size;\n\tu32 sampled_write_ptr;\n\tunion {\n\t\tstruct {\n\t\t\tu32 flush_to_file: 1;\n\t\t\tu32 buffer_full_cnt: 4;\n\t\t\tu32 reserved: 27;\n\t\t};\n\t\tu32 flags;\n\t};\n\tu32 version;\n};\n\nstruct guc_wq_item {\n\tu32 header;\n\tu32 context_desc;\n\tu32 submit_element_info;\n\tu32 fence_id;\n};\n\nstruct guc_process_desc {\n\tu32 stage_id;\n\tu64 db_base_addr;\n\tu32 head;\n\tu32 tail;\n\tu32 error_offset;\n\tu64 wq_base_addr;\n\tu32 wq_size_bytes;\n\tu32 wq_status;\n\tu32 engine_presence;\n\tu32 priority;\n\tu32 reserved[30];\n} __attribute__((packed));\n\nstruct guc_execlist_context {\n\tu32 context_desc;\n\tu32 context_id;\n\tu32 ring_status;\n\tu32 ring_lrca;\n\tu32 ring_begin;\n\tu32 ring_end;\n\tu32 ring_next_free_location;\n\tu32 ring_current_tail_pointer_value;\n\tu8 engine_state_submit_value;\n\tu8 engine_state_wait_value;\n\tu16 pagefault_count;\n\tu16 engine_submit_queue_count;\n} __attribute__((packed));\n\nstruct guc_stage_desc {\n\tu32 sched_common_area;\n\tu32 stage_id;\n\tu32 pas_id;\n\tu8 engines_used;\n\tu64 db_trigger_cpu;\n\tu32 db_trigger_uk;\n\tu64 db_trigger_phy;\n\tu16 db_id;\n\tstruct guc_execlist_context lrc[5];\n\tu8 attribute;\n\tu32 priority;\n\tu32 wq_sampled_tail_offset;\n\tu32 wq_total_submit_enqueues;\n\tu32 process_desc;\n\tu32 wq_addr;\n\tu32 wq_size;\n\tu32 engine_presence;\n\tu8 engine_suspended;\n\tu8 reserved0[3];\n\tu64 reserved1[1];\n\tu64 desc_private;\n} __attribute__((packed));\n\nenum hdmi_force_audio {\n\tHDMI_AUDIO_OFF_DVI = 4294967294,\n\tHDMI_AUDIO_OFF = 4294967295,\n\tHDMI_AUDIO_AUTO = 0,\n\tHDMI_AUDIO_ON = 1,\n};\n\nstruct intel_digital_connector_state {\n\tstruct drm_connector_state base;\n\tenum hdmi_force_audio force_audio;\n\tint broadcast_rgb;\n};\n\nstruct component_ops {\n\tint (*bind)(struct device *, struct device *, void *);\n\tvoid (*unbind)(struct device *, struct device *, void *);\n};\n\nstruct drm_audio_component_ops {\n\tstruct module *owner;\n\tlong unsigned int (*get_power)(struct device *);\n\tvoid (*put_power)(struct device *, long unsigned int);\n\tvoid (*codec_wake_override)(struct device *, bool);\n\tint (*get_cdclk_freq)(struct device *);\n\tint (*sync_audio_rate)(struct device *, int, int, int);\n\tint (*get_eld)(struct device *, int, int, bool *, unsigned char *, int);\n};\n\nstruct drm_audio_component;\n\nstruct drm_audio_component_audio_ops {\n\tvoid *audio_ptr;\n\tvoid (*pin_eld_notify)(void *, int, int);\n\tint (*pin2port)(void *, int);\n\tint (*master_bind)(struct device *, struct drm_audio_component *);\n\tvoid (*master_unbind)(struct device *, struct drm_audio_component *);\n};\n\nstruct drm_audio_component {\n\tstruct device *dev;\n\tconst struct drm_audio_component_ops *ops;\n\tconst struct drm_audio_component_audio_ops *audio_ops;\n};\n\nenum i915_component_type {\n\tI915_COMPONENT_AUDIO = 1,\n\tI915_COMPONENT_HDCP = 2,\n};\n\nstruct i915_audio_component {\n\tstruct drm_audio_component base;\n\tint aud_sample_rate[9];\n};\n\nstruct dp_aud_n_m {\n\tint sample_rate;\n\tint clock;\n\tu16 m;\n\tu16 n;\n};\n\nstruct hdmi_aud_ncts {\n\tint sample_rate;\n\tint clock;\n\tint n;\n\tint cts;\n};\n\nenum phy {\n\tPHY_NONE = 4294967295,\n\tPHY_A = 0,\n\tPHY_B = 1,\n\tPHY_C = 2,\n\tPHY_D = 3,\n\tPHY_E = 4,\n\tPHY_F = 5,\n\tPHY_G = 6,\n\tPHY_H = 7,\n\tPHY_I = 8,\n\tI915_MAX_PHYS = 9,\n};\n\nenum mipi_seq_element {\n\tMIPI_SEQ_ELEM_END = 0,\n\tMIPI_SEQ_ELEM_SEND_PKT = 1,\n\tMIPI_SEQ_ELEM_DELAY = 2,\n\tMIPI_SEQ_ELEM_GPIO = 3,\n\tMIPI_SEQ_ELEM_I2C = 4,\n\tMIPI_SEQ_ELEM_SPI = 5,\n\tMIPI_SEQ_ELEM_PMIC = 6,\n\tMIPI_SEQ_ELEM_MAX = 7,\n};\n\nstruct vbt_header {\n\tu8 signature[20];\n\tu16 version;\n\tu16 header_size;\n\tu16 vbt_size;\n\tu8 vbt_checksum;\n\tu8 reserved0;\n\tu32 bdb_offset;\n\tu32 aim_offset[4];\n};\n\nstruct bdb_header {\n\tu8 signature[16];\n\tu16 version;\n\tu16 header_size;\n\tu16 bdb_size;\n};\n\nenum bdb_block_id {\n\tBDB_GENERAL_FEATURES = 1,\n\tBDB_GENERAL_DEFINITIONS = 2,\n\tBDB_OLD_TOGGLE_LIST = 3,\n\tBDB_MODE_SUPPORT_LIST = 4,\n\tBDB_GENERIC_MODE_TABLE = 5,\n\tBDB_EXT_MMIO_REGS = 6,\n\tBDB_SWF_IO = 7,\n\tBDB_SWF_MMIO = 8,\n\tBDB_PSR = 9,\n\tBDB_MODE_REMOVAL_TABLE = 10,\n\tBDB_CHILD_DEVICE_TABLE = 11,\n\tBDB_DRIVER_FEATURES = 12,\n\tBDB_DRIVER_PERSISTENCE = 13,\n\tBDB_EXT_TABLE_PTRS = 14,\n\tBDB_DOT_CLOCK_OVERRIDE = 15,\n\tBDB_DISPLAY_SELECT = 16,\n\tBDB_DRIVER_ROTATION = 18,\n\tBDB_DISPLAY_REMOVE = 19,\n\tBDB_OEM_CUSTOM = 20,\n\tBDB_EFP_LIST = 21,\n\tBDB_SDVO_LVDS_OPTIONS = 22,\n\tBDB_SDVO_PANEL_DTDS = 23,\n\tBDB_SDVO_LVDS_PNP_IDS = 24,\n\tBDB_SDVO_LVDS_POWER_SEQ = 25,\n\tBDB_TV_OPTIONS = 26,\n\tBDB_EDP = 27,\n\tBDB_LVDS_OPTIONS = 40,\n\tBDB_LVDS_LFP_DATA_PTRS = 41,\n\tBDB_LVDS_LFP_DATA = 42,\n\tBDB_LVDS_BACKLIGHT = 43,\n\tBDB_LFP_POWER = 44,\n\tBDB_MIPI_CONFIG = 52,\n\tBDB_MIPI_SEQUENCE = 53,\n\tBDB_COMPRESSION_PARAMETERS = 56,\n\tBDB_GENERIC_DTD = 58,\n\tBDB_SKIP = 254,\n};\n\nstruct bdb_general_features {\n\tu8 panel_fitting: 2;\n\tu8 flexaim: 1;\n\tu8 msg_enable: 1;\n\tu8 clear_screen: 3;\n\tu8 color_flip: 1;\n\tu8 download_ext_vbt: 1;\n\tu8 enable_ssc: 1;\n\tu8 ssc_freq: 1;\n\tu8 enable_lfp_on_override: 1;\n\tu8 disable_ssc_ddt: 1;\n\tu8 underscan_vga_timings: 1;\n\tu8 display_clock_mode: 1;\n\tu8 vbios_hotplug_support: 1;\n\tu8 disable_smooth_vision: 1;\n\tu8 single_dvi: 1;\n\tu8 rotate_180: 1;\n\tu8 fdi_rx_polarity_inverted: 1;\n\tu8 vbios_extended_mode: 1;\n\tu8 copy_ilfp_dtd_to_sdvo_lvds_dtd: 1;\n\tu8 panel_best_fit_timing: 1;\n\tu8 ignore_strap_state: 1;\n\tu8 legacy_monitor_detect;\n\tu8 int_crt_support: 1;\n\tu8 int_tv_support: 1;\n\tu8 int_efp_support: 1;\n\tu8 dp_ssc_enable: 1;\n\tu8 dp_ssc_freq: 1;\n\tu8 dp_ssc_dongle_supported: 1;\n\tu8 rsvd11: 2;\n};\n\nenum vbt_gmbus_ddi {\n\tDDC_BUS_DDI_B = 1,\n\tDDC_BUS_DDI_C = 2,\n\tDDC_BUS_DDI_D = 3,\n\tDDC_BUS_DDI_F = 4,\n\tICL_DDC_BUS_DDI_A = 1,\n\tICL_DDC_BUS_DDI_B = 2,\n\tTGL_DDC_BUS_DDI_C = 3,\n\tICL_DDC_BUS_PORT_1 = 4,\n\tICL_DDC_BUS_PORT_2 = 5,\n\tICL_DDC_BUS_PORT_3 = 6,\n\tICL_DDC_BUS_PORT_4 = 7,\n\tTGL_DDC_BUS_PORT_5 = 8,\n\tTGL_DDC_BUS_PORT_6 = 9,\n};\n\nstruct bdb_general_definitions {\n\tu8 crt_ddc_gmbus_pin;\n\tu8 dpms_acpi: 1;\n\tu8 skip_boot_crt_detect: 1;\n\tu8 dpms_aim: 1;\n\tu8 rsvd1: 5;\n\tu8 boot_display[2];\n\tu8 child_dev_size;\n\tu8 devices[0];\n};\n\nstruct psr_table {\n\tu8 full_link: 1;\n\tu8 require_aux_to_wakeup: 1;\n\tu8 feature_bits_rsvd: 6;\n\tu8 idle_frames: 4;\n\tu8 lines_to_wait: 3;\n\tu8 wait_times_rsvd: 1;\n\tu16 tp1_wakeup_time;\n\tu16 tp2_tp3_wakeup_time;\n};\n\nstruct bdb_psr {\n\tstruct psr_table psr_table[16];\n\tu32 psr2_tp2_tp3_wakeup_time;\n};\n\nstruct bdb_driver_features {\n\tu8 boot_dev_algorithm: 1;\n\tu8 block_display_switch: 1;\n\tu8 allow_display_switch: 1;\n\tu8 hotplug_dvo: 1;\n\tu8 dual_view_zoom: 1;\n\tu8 int15h_hook: 1;\n\tu8 sprite_in_clone: 1;\n\tu8 primary_lfp_id: 1;\n\tu16 boot_mode_x;\n\tu16 boot_mode_y;\n\tu8 boot_mode_bpp;\n\tu8 boot_mode_refresh;\n\tu16 enable_lfp_primary: 1;\n\tu16 selective_mode_pruning: 1;\n\tu16 dual_frequency: 1;\n\tu16 render_clock_freq: 1;\n\tu16 nt_clone_support: 1;\n\tu16 power_scheme_ui: 1;\n\tu16 sprite_display_assign: 1;\n\tu16 cui_aspect_scaling: 1;\n\tu16 preserve_aspect_ratio: 1;\n\tu16 sdvo_device_power_down: 1;\n\tu16 crt_hotplug: 1;\n\tu16 lvds_config: 2;\n\tu16 tv_hotplug: 1;\n\tu16 hdmi_config: 2;\n\tu8 static_display: 1;\n\tu8 reserved2: 7;\n\tu16 legacy_crt_max_x;\n\tu16 legacy_crt_max_y;\n\tu8 legacy_crt_max_refresh;\n\tu8 hdmi_termination;\n\tu8 custom_vbt_version;\n\tu16 rmpm_enabled: 1;\n\tu16 s2ddt_enabled: 1;\n\tu16 dpst_enabled: 1;\n\tu16 bltclt_enabled: 1;\n\tu16 adb_enabled: 1;\n\tu16 drrs_enabled: 1;\n\tu16 grs_enabled: 1;\n\tu16 gpmt_enabled: 1;\n\tu16 tbt_enabled: 1;\n\tu16 psr_enabled: 1;\n\tu16 ips_enabled: 1;\n\tu16 reserved3: 4;\n\tu16 pc_feature_valid: 1;\n} __attribute__((packed));\n\nstruct bdb_sdvo_lvds_options {\n\tu8 panel_backlight;\n\tu8 h40_set_panel_type;\n\tu8 panel_type;\n\tu8 ssc_clk_freq;\n\tu16 als_low_trip;\n\tu16 als_high_trip;\n\tu8 sclalarcoeff_tab_row_num;\n\tu8 sclalarcoeff_tab_row_size;\n\tu8 coefficient[8];\n\tu8 panel_misc_bits_1;\n\tu8 panel_misc_bits_2;\n\tu8 panel_misc_bits_3;\n\tu8 panel_misc_bits_4;\n};\n\nstruct lvds_dvo_timing {\n\tu16 clock;\n\tu8 hactive_lo;\n\tu8 hblank_lo;\n\tu8 hblank_hi: 4;\n\tu8 hactive_hi: 4;\n\tu8 vactive_lo;\n\tu8 vblank_lo;\n\tu8 vblank_hi: 4;\n\tu8 vactive_hi: 4;\n\tu8 hsync_off_lo;\n\tu8 hsync_pulse_width_lo;\n\tu8 vsync_pulse_width_lo: 4;\n\tu8 vsync_off_lo: 4;\n\tu8 vsync_pulse_width_hi: 2;\n\tu8 vsync_off_hi: 2;\n\tu8 hsync_pulse_width_hi: 2;\n\tu8 hsync_off_hi: 2;\n\tu8 himage_lo;\n\tu8 vimage_lo;\n\tu8 vimage_hi: 4;\n\tu8 himage_hi: 4;\n\tu8 h_border;\n\tu8 v_border;\n\tu8 rsvd1: 3;\n\tu8 digital: 2;\n\tu8 vsync_positive: 1;\n\tu8 hsync_positive: 1;\n\tu8 non_interlaced: 1;\n};\n\nstruct bdb_sdvo_panel_dtds {\n\tstruct lvds_dvo_timing dtds[4];\n};\n\nstruct edp_fast_link_params {\n\tu8 rate: 4;\n\tu8 lanes: 4;\n\tu8 preemphasis: 4;\n\tu8 vswing: 4;\n};\n\nstruct edp_pwm_delays {\n\tu16 pwm_on_to_backlight_enable;\n\tu16 backlight_disable_to_pwm_off;\n};\n\nstruct edp_full_link_params {\n\tu8 preemphasis: 4;\n\tu8 vswing: 4;\n};\n\nstruct bdb_edp {\n\tstruct edp_power_seq power_seqs[16];\n\tu32 color_depth;\n\tstruct edp_fast_link_params fast_link_params[16];\n\tu32 sdrrs_msa_timing_delay;\n\tu16 edp_s3d_feature;\n\tu16 edp_t3_optimization;\n\tu64 edp_vswing_preemph;\n\tu16 fast_link_training;\n\tu16 dpcd_600h_write_required;\n\tstruct edp_pwm_delays pwm_delays[16];\n\tu16 full_link_params_provided;\n\tstruct edp_full_link_params full_link_params[16];\n} __attribute__((packed));\n\nstruct bdb_lvds_options {\n\tu8 panel_type;\n\tu8 panel_type2;\n\tu8 pfit_mode: 2;\n\tu8 pfit_text_mode_enhanced: 1;\n\tu8 pfit_gfx_mode_enhanced: 1;\n\tu8 pfit_ratio_auto: 1;\n\tu8 pixel_dither: 1;\n\tu8 lvds_edid: 1;\n\tu8 rsvd2: 1;\n\tu8 rsvd4;\n\tu32 lvds_panel_channel_bits;\n\tu16 ssc_bits;\n\tu16 ssc_freq;\n\tu16 ssc_ddt;\n\tu16 panel_color_depth;\n\tu32 dps_panel_type_bits;\n\tu32 blt_control_type_bits;\n\tu16 lcdvcc_s0_enable;\n\tu32 rotation;\n} __attribute__((packed));\n\nstruct lvds_lfp_data_ptr {\n\tu16 fp_timing_offset;\n\tu8 fp_table_size;\n\tu16 dvo_timing_offset;\n\tu8 dvo_table_size;\n\tu16 panel_pnp_id_offset;\n\tu8 pnp_table_size;\n} __attribute__((packed));\n\nstruct bdb_lvds_lfp_data_ptrs {\n\tu8 lvds_entries;\n\tstruct lvds_lfp_data_ptr ptr[16];\n} __attribute__((packed));\n\nstruct lvds_fp_timing {\n\tu16 x_res;\n\tu16 y_res;\n\tu32 lvds_reg;\n\tu32 lvds_reg_val;\n\tu32 pp_on_reg;\n\tu32 pp_on_reg_val;\n\tu32 pp_off_reg;\n\tu32 pp_off_reg_val;\n\tu32 pp_cycle_reg;\n\tu32 pp_cycle_reg_val;\n\tu32 pfit_reg;\n\tu32 pfit_reg_val;\n\tu16 terminator;\n} __attribute__((packed));\n\nstruct lvds_pnp_id {\n\tu16 mfg_name;\n\tu16 product_code;\n\tu32 serial;\n\tu8 mfg_week;\n\tu8 mfg_year;\n} __attribute__((packed));\n\nstruct lvds_lfp_data_entry {\n\tstruct lvds_fp_timing fp_timing;\n\tstruct lvds_dvo_timing dvo_timing;\n\tstruct lvds_pnp_id pnp_id;\n} __attribute__((packed));\n\nstruct bdb_lvds_lfp_data {\n\tstruct lvds_lfp_data_entry data[16];\n};\n\nstruct lfp_backlight_data_entry {\n\tu8 type: 2;\n\tu8 active_low_pwm: 1;\n\tu8 obsolete1: 5;\n\tu16 pwm_freq_hz;\n\tu8 min_brightness;\n\tu8 obsolete2;\n\tu8 obsolete3;\n} __attribute__((packed));\n\nstruct lfp_backlight_control_method {\n\tu8 type: 4;\n\tu8 controller: 4;\n};\n\nstruct bdb_lfp_backlight_data {\n\tu8 entry_size;\n\tstruct lfp_backlight_data_entry data[16];\n\tu8 level[16];\n\tstruct lfp_backlight_control_method backlight_control[16];\n} __attribute__((packed));\n\nstruct als_data_entry {\n\tu16 backlight_adjust;\n\tu16 lux;\n};\n\nstruct agressiveness_profile_entry {\n\tu8 dpst_agressiveness: 4;\n\tu8 lace_agressiveness: 4;\n};\n\nstruct bdb_lfp_power {\n\tu8 lfp_feature_bits;\n\tstruct als_data_entry als[5];\n\tu8 lace_aggressiveness_profile;\n\tu16 dpst;\n\tu16 psr;\n\tu16 drrs;\n\tu16 lace_support;\n\tu16 adt;\n\tu16 dmrrs;\n\tu16 adb;\n\tu16 lace_enabled_status;\n\tstruct agressiveness_profile_entry aggressivenes[16];\n} __attribute__((packed));\n\nstruct bdb_mipi_config {\n\tstruct mipi_config config[6];\n\tstruct mipi_pps_data pps[6];\n};\n\nstruct bdb_mipi_sequence {\n\tu8 version;\n\tu8 data[0];\n};\n\nstruct dsc_compression_parameters_entry {\n\tu8 version_major: 4;\n\tu8 version_minor: 4;\n\tu8 rc_buffer_block_size: 2;\n\tu8 reserved1: 6;\n\tu8 rc_buffer_size;\n\tu32 slices_per_line;\n\tu8 line_buffer_depth: 4;\n\tu8 reserved2: 4;\n\tu8 block_prediction_enable: 1;\n\tu8 reserved3: 7;\n\tu8 max_bpp;\n\tu8 reserved4: 1;\n\tu8 support_8bpc: 1;\n\tu8 support_10bpc: 1;\n\tu8 support_12bpc: 1;\n\tu8 reserved5: 4;\n\tu16 slice_height;\n} __attribute__((packed));\n\nstruct bdb_compression_parameters {\n\tu16 entry_size;\n\tstruct dsc_compression_parameters_entry data[16];\n} __attribute__((packed));\n\nstruct generic_dtd_entry {\n\tu32 pixel_clock;\n\tu16 hactive;\n\tu16 hblank;\n\tu16 hfront_porch;\n\tu16 hsync;\n\tu16 vactive;\n\tu16 vblank;\n\tu16 vfront_porch;\n\tu16 vsync;\n\tu16 width_mm;\n\tu16 height_mm;\n\tu8 rsvd_flags: 6;\n\tu8 vsync_positive_polarity: 1;\n\tu8 hsync_positive_polarity: 1;\n\tu8 rsvd[3];\n};\n\nstruct bdb_generic_dtd {\n\tu16 gdtd_size;\n\tstruct generic_dtd_entry dtd[0];\n} __attribute__((packed));\n\nstruct display_device_data {\n\tstruct child_device_config child;\n\tstruct dsc_compression_parameters_entry *dsc;\n\tstruct list_head node;\n};\n\nstruct intel_qgv_point {\n\tu16 dclk;\n\tu16 t_rp;\n\tu16 t_rdpre;\n\tu16 t_rc;\n\tu16 t_ras;\n\tu16 t_rcd;\n};\n\nstruct intel_qgv_info {\n\tstruct intel_qgv_point points[8];\n\tu8 num_points;\n\tu8 num_channels;\n\tu8 t_bl;\n\tenum intel_dram_type dram_type;\n};\n\nstruct intel_sa_info {\n\tu16 displayrtids;\n\tu8 deburst;\n\tu8 deprogbwlimit;\n};\n\nstruct drm_color_ctm {\n\t__u64 matrix[9];\n};\n\nenum {\n\tPROCMON_0_85V_DOT_0 = 0,\n\tPROCMON_0_95V_DOT_0 = 1,\n\tPROCMON_0_95V_DOT_1 = 2,\n\tPROCMON_1_05V_DOT_0 = 3,\n\tPROCMON_1_05V_DOT_1 = 4,\n};\n\nstruct cnl_procmon {\n\tu32 dw1;\n\tu32 dw9;\n\tu32 dw10;\n};\n\nenum intel_broadcast_rgb {\n\tINTEL_BROADCAST_RGB_AUTO = 0,\n\tINTEL_BROADCAST_RGB_FULL = 1,\n\tINTEL_BROADCAST_RGB_LIMITED = 2,\n};\n\nstruct intel_css_header {\n\tu32 module_type;\n\tu32 header_len;\n\tu32 header_ver;\n\tu32 module_id;\n\tu32 module_vendor;\n\tu32 date;\n\tu32 size;\n\tu32 key_size;\n\tu32 modulus_size;\n\tu32 exponent_size;\n\tu32 reserved1[12];\n\tu32 version;\n\tu32 reserved2[8];\n\tu32 kernel_header_info;\n};\n\nstruct intel_fw_info {\n\tu8 reserved1;\n\tu8 dmc_id;\n\tchar stepping;\n\tchar substepping;\n\tu32 offset;\n\tu32 reserved2;\n};\n\nstruct intel_package_header {\n\tu8 header_len;\n\tu8 header_ver;\n\tu8 reserved[10];\n\tu32 num_entries;\n};\n\nstruct intel_dmc_header_base {\n\tu32 signature;\n\tu8 header_len;\n\tu8 header_ver;\n\tu16 dmcc_ver;\n\tu32 project;\n\tu32 fw_size;\n\tu32 fw_version;\n};\n\nstruct intel_dmc_header_v1 {\n\tstruct intel_dmc_header_base base;\n\tu32 mmio_count;\n\tu32 mmioaddr[8];\n\tu32 mmiodata[8];\n\tchar dfile[32];\n\tu32 reserved1[2];\n};\n\nstruct intel_dmc_header_v3 {\n\tstruct intel_dmc_header_base base;\n\tu32 start_mmioaddr;\n\tu32 reserved[9];\n\tchar dfile[32];\n\tu32 mmio_count;\n\tu32 mmioaddr[20];\n\tu32 mmiodata[20];\n};\n\nstruct stepping_info {\n\tchar stepping;\n\tchar substepping;\n};\n\nenum hdmi_packet_type {\n\tHDMI_PACKET_TYPE_NULL = 0,\n\tHDMI_PACKET_TYPE_AUDIO_CLOCK_REGEN = 1,\n\tHDMI_PACKET_TYPE_AUDIO_SAMPLE = 2,\n\tHDMI_PACKET_TYPE_GENERAL_CONTROL = 3,\n\tHDMI_PACKET_TYPE_ACP = 4,\n\tHDMI_PACKET_TYPE_ISRC1 = 5,\n\tHDMI_PACKET_TYPE_ISRC2 = 6,\n\tHDMI_PACKET_TYPE_ONE_BIT_AUDIO_SAMPLE = 7,\n\tHDMI_PACKET_TYPE_DST_AUDIO = 8,\n\tHDMI_PACKET_TYPE_HBR_AUDIO_STREAM = 9,\n\tHDMI_PACKET_TYPE_GAMUT_METADATA = 10,\n};\n\nenum dpio_channel {\n\tDPIO_CH0 = 0,\n\tDPIO_CH1 = 1,\n};\n\nstruct drm_i915_get_pipe_from_crtc_id {\n\t__u32 crtc_id;\n\t__u32 pipe;\n};\n\nstruct intel_cursor_error_state {\n\tu32 control;\n\tu32 position;\n\tu32 base;\n\tu32 size;\n};\n\nstruct intel_pipe_error_state {\n\tbool power_domain_on;\n\tu32 source;\n\tu32 stat;\n};\n\nstruct intel_plane_error_state {\n\tu32 control;\n\tu32 stride;\n\tu32 size;\n\tu32 pos;\n\tu32 addr;\n\tu32 surface;\n\tu32 tile_offset;\n};\n\nstruct intel_transcoder_error_state {\n\tbool available;\n\tbool power_domain_on;\n\tenum transcoder cpu_transcoder;\n\tu32 conf;\n\tu32 htotal;\n\tu32 hblank;\n\tu32 hsync;\n\tu32 vtotal;\n\tu32 vblank;\n\tu32 vsync;\n};\n\nstruct intel_display_error_state {\n\tu32 power_well_driver;\n\tstruct intel_cursor_error_state cursor[4];\n\tstruct intel_pipe_error_state pipe[4];\n\tstruct intel_plane_error_state plane[4];\n\tstruct intel_transcoder_error_state transcoder[5];\n};\n\nstruct drm_i915_error_state_buf {\n\tstruct drm_i915_private *i915;\n\tstruct scatterlist *sgl;\n\tstruct scatterlist *cur;\n\tstruct scatterlist *end;\n\tchar *buf;\n\tsize_t bytes;\n\tsize_t size;\n\tloff_t iter;\n\tint err;\n};\n\nenum link_m_n_set {\n\tM1_N1 = 0,\n\tM2_N2 = 1,\n};\n\nstruct intel_load_detect_pipe {\n\tstruct drm_atomic_state *restore_state;\n};\n\nstruct intel_limit {\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} dot;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} vco;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} n;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} m;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} m1;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} m2;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} p;\n\tstruct {\n\t\tint min;\n\t\tint max;\n\t} p1;\n\tstruct {\n\t\tint dot_limit;\n\t\tint p2_slow;\n\t\tint p2_fast;\n\t} p2;\n};\n\nstruct wait_rps_boost {\n\tstruct wait_queue_entry wait;\n\tstruct drm_crtc *crtc;\n\tstruct i915_request *request;\n};\n\nstruct skl_hw_state {\n\tstruct skl_ddb_entry ddb_y[8];\n\tstruct skl_ddb_entry ddb_uv[8];\n\tstruct skl_pipe_wm wm;\n};\n\nenum skl_power_gate {\n\tSKL_PG0 = 0,\n\tSKL_PG1 = 1,\n\tSKL_PG2 = 2,\n\tICL_PG3 = 3,\n\tICL_PG4 = 4,\n};\n\nstruct buddy_page_mask {\n\tu32 page_mask;\n\tu8 type;\n\tu8 num_channels;\n};\n\nstruct bxt_ddi_phy_info {\n\tbool dual_channel;\n\tenum dpio_phy rcomp_phy;\n\tint reset_delay;\n\tu32 pwron_mask;\n\tstruct {\n\t\tenum port port;\n\t} channel[2];\n};\n\nstruct hsw_wrpll_rnp {\n\tunsigned int p;\n\tunsigned int n2;\n\tunsigned int r2;\n};\n\nstruct skl_dpll_regs {\n\ti915_reg_t ctl;\n\ti915_reg_t cfgcr1;\n\ti915_reg_t cfgcr2;\n};\n\nstruct skl_wrpll_context {\n\tu64 min_deviation;\n\tu64 central_freq;\n\tu64 dco_freq;\n\tunsigned int p;\n};\n\nstruct skl_wrpll_params {\n\tu32 dco_fraction;\n\tu32 dco_integer;\n\tu32 qdiv_ratio;\n\tu32 qdiv_mode;\n\tu32 kdiv;\n\tu32 pdiv;\n\tu32 central_freq;\n};\n\nstruct bxt_clk_div {\n\tint clock;\n\tu32 p1;\n\tu32 p2;\n\tu32 m2_int;\n\tu32 m2_frac;\n\tbool m2_frac_en;\n\tu32 n;\n\tint vco;\n};\n\nstruct icl_combo_pll_params {\n\tint clock;\n\tstruct skl_wrpll_params wrpll;\n};\n\nstruct hdcp2_rep_stream_manage {\n\tu8 msg_id;\n\tu8 seq_num_m[3];\n\t__be16 k;\n\tstruct hdcp2_streamid_type streams[1];\n};\n\nenum hdcp_port_type {\n\tHDCP_PORT_TYPE_INVALID = 0,\n\tHDCP_PORT_TYPE_INTEGRATED = 1,\n\tHDCP_PORT_TYPE_LSPCON = 2,\n\tHDCP_PORT_TYPE_CPDP = 3,\n};\n\nenum check_link_response {\n\tHDCP_LINK_PROTECTED = 0,\n\tHDCP_TOPOLOGY_CHANGE = 1,\n\tHDCP_LINK_INTEGRITY_FAILURE = 2,\n\tHDCP_REAUTH_REQUEST = 3,\n};\n\nstruct intel_hdmi_lpe_audio_port_pdata {\n\tu8 eld[128];\n\tint port;\n\tint pipe;\n\tint ls_clock;\n\tbool dp_output;\n};\n\nstruct intel_hdmi_lpe_audio_pdata {\n\tstruct intel_hdmi_lpe_audio_port_pdata port[3];\n\tint num_ports;\n\tint num_pipes;\n\tvoid (*notify_audio_lpe)(struct platform_device *, int);\n\tspinlock_t lpe_audio_slock;\n};\n\nstruct drm_intel_overlay_put_image {\n\t__u32 flags;\n\t__u32 bo_handle;\n\t__u16 stride_Y;\n\t__u16 stride_UV;\n\t__u32 offset_Y;\n\t__u32 offset_U;\n\t__u32 offset_V;\n\t__u16 src_width;\n\t__u16 src_height;\n\t__u16 src_scan_width;\n\t__u16 src_scan_height;\n\t__u32 crtc_id;\n\t__u16 dst_x;\n\t__u16 dst_y;\n\t__u16 dst_width;\n\t__u16 dst_height;\n};\n\nstruct drm_intel_overlay_attrs {\n\t__u32 flags;\n\t__u32 color_key;\n\t__s32 brightness;\n\t__u32 contrast;\n\t__u32 saturation;\n\t__u32 gamma0;\n\t__u32 gamma1;\n\t__u32 gamma2;\n\t__u32 gamma3;\n\t__u32 gamma4;\n\t__u32 gamma5;\n};\n\nstruct overlay_registers {\n\tu32 OBUF_0Y;\n\tu32 OBUF_1Y;\n\tu32 OBUF_0U;\n\tu32 OBUF_0V;\n\tu32 OBUF_1U;\n\tu32 OBUF_1V;\n\tu32 OSTRIDE;\n\tu32 YRGB_VPH;\n\tu32 UV_VPH;\n\tu32 HORZ_PH;\n\tu32 INIT_PHS;\n\tu32 DWINPOS;\n\tu32 DWINSZ;\n\tu32 SWIDTH;\n\tu32 SWIDTHSW;\n\tu32 SHEIGHT;\n\tu32 YRGBSCALE;\n\tu32 UVSCALE;\n\tu32 OCLRC0;\n\tu32 OCLRC1;\n\tu32 DCLRKV;\n\tu32 DCLRKM;\n\tu32 SCLRKVH;\n\tu32 SCLRKVL;\n\tu32 SCLRKEN;\n\tu32 OCONFIG;\n\tu32 OCMD;\n\tu32 RESERVED1;\n\tu32 OSTART_0Y;\n\tu32 OSTART_1Y;\n\tu32 OSTART_0U;\n\tu32 OSTART_0V;\n\tu32 OSTART_1U;\n\tu32 OSTART_1V;\n\tu32 OTILEOFF_0Y;\n\tu32 OTILEOFF_1Y;\n\tu32 OTILEOFF_0U;\n\tu32 OTILEOFF_0V;\n\tu32 OTILEOFF_1U;\n\tu32 OTILEOFF_1V;\n\tu32 FASTHSCALE;\n\tu32 UVSCALEV;\n\tu32 RESERVEDC[86];\n\tu16 Y_VCOEFS[51];\n\tu16 RESERVEDD[77];\n\tu16 Y_HCOEFS[85];\n\tu16 RESERVEDE[171];\n\tu16 UV_VCOEFS[51];\n\tu16 RESERVEDF[77];\n\tu16 UV_HCOEFS[51];\n\tu16 RESERVEDG[77];\n};\n\nstruct intel_overlay_error_state {\n\tstruct overlay_registers regs;\n\tlong unsigned int base;\n\tu32 dovsta;\n\tu32 isr;\n};\n\nstruct intel_overlay {\n\tstruct drm_i915_private *i915;\n\tstruct intel_context *context;\n\tstruct intel_crtc *crtc;\n\tstruct i915_vma *vma;\n\tstruct i915_vma *old_vma;\n\tbool active;\n\tbool pfit_active;\n\tu32 pfit_vscale_ratio;\n\tu32 color_key: 24;\n\tu32 color_key_enabled: 1;\n\tu32 brightness;\n\tu32 contrast;\n\tu32 saturation;\n\tu32 old_xscale;\n\tu32 old_yscale;\n\tstruct drm_i915_gem_object *reg_bo;\n\tstruct overlay_registers *regs;\n\tu32 flip_addr;\n\tstruct i915_active last_flip;\n\tvoid (*flip_complete)(struct intel_overlay *);\n};\n\nstruct intel_quirk {\n\tint device;\n\tint subsystem_vendor;\n\tint subsystem_device;\n\tvoid (*hook)(struct drm_i915_private *);\n};\n\nstruct intel_dmi_quirk {\n\tvoid (*hook)(struct drm_i915_private *);\n\tconst struct dmi_system_id (*dmi_id_list)[0];\n};\n\nstruct opregion_header {\n\tu8 signature[16];\n\tu32 size;\n\tstruct {\n\t\tu8 rsvd;\n\t\tu8 revision;\n\t\tu8 minor;\n\t\tu8 major;\n\t} over;\n\tu8 bios_ver[32];\n\tu8 vbios_ver[16];\n\tu8 driver_ver[16];\n\tu32 mboxes;\n\tu32 driver_model;\n\tu32 pcon;\n\tu8 dver[32];\n\tu8 rsvd[124];\n};\n\nstruct opregion_acpi {\n\tu32 drdy;\n\tu32 csts;\n\tu32 cevt;\n\tu8 rsvd1[20];\n\tu32 didl[8];\n\tu32 cpdl[8];\n\tu32 cadl[8];\n\tu32 nadl[8];\n\tu32 aslp;\n\tu32 tidx;\n\tu32 chpd;\n\tu32 clid;\n\tu32 cdck;\n\tu32 sxsw;\n\tu32 evts;\n\tu32 cnot;\n\tu32 nrdy;\n\tu32 did2[7];\n\tu32 cpd2[7];\n\tu8 rsvd2[4];\n};\n\nstruct opregion_swsci {\n\tu32 scic;\n\tu32 parm;\n\tu32 dslp;\n\tu8 rsvd[244];\n};\n\nstruct opregion_asle {\n\tu32 ardy;\n\tu32 aslc;\n\tu32 tche;\n\tu32 alsi;\n\tu32 bclp;\n\tu32 pfit;\n\tu32 cblv;\n\tu16 bclm[20];\n\tu32 cpfm;\n\tu32 epfm;\n\tu8 plut[74];\n\tu32 pfmb;\n\tu32 cddv;\n\tu32 pcft;\n\tu32 srot;\n\tu32 iuer;\n\tu64 fdss;\n\tu32 fdsp;\n\tu32 stat;\n\tu64 rvda;\n\tu32 rvds;\n\tu8 rsvd[58];\n} __attribute__((packed));\n\nstruct intel_dvo_dev_ops;\n\nstruct intel_dvo_device {\n\tconst char *name;\n\tint type;\n\ti915_reg_t dvo_reg;\n\ti915_reg_t dvo_srcdim_reg;\n\tu32 gpio;\n\tint slave_addr;\n\tconst struct intel_dvo_dev_ops *dev_ops;\n\tvoid *dev_priv;\n\tstruct i2c_adapter *i2c_bus;\n};\n\nstruct intel_dvo_dev_ops {\n\tbool (*init)(struct intel_dvo_device *, struct i2c_adapter *);\n\tvoid (*create_resources)(struct intel_dvo_device *);\n\tvoid (*dpms)(struct intel_dvo_device *, bool);\n\tint (*mode_valid)(struct intel_dvo_device *, struct drm_display_mode *);\n\tvoid (*prepare)(struct intel_dvo_device *);\n\tvoid (*commit)(struct intel_dvo_device *);\n\tvoid (*mode_set)(struct intel_dvo_device *, const struct drm_display_mode *, const struct drm_display_mode *);\n\tenum drm_connector_status (*detect)(struct intel_dvo_device *);\n\tbool (*get_hw_state)(struct intel_dvo_device *);\n\tstruct drm_display_mode * (*get_modes)(struct intel_dvo_device *);\n\tvoid (*destroy)(struct intel_dvo_device *);\n\tvoid (*dump_regs)(struct intel_dvo_device *);\n};\n\nstruct ch7017_priv {\n\tu8 dummy;\n};\n\nstruct ch7xxx_id_struct {\n\tu8 vid;\n\tchar *name;\n};\n\nstruct ch7xxx_did_struct {\n\tu8 did;\n\tchar *name;\n};\n\nstruct ch7xxx_priv {\n\tbool quiet;\n};\n\nstruct ivch_priv {\n\tbool quiet;\n\tu16 width;\n\tu16 height;\n\tu16 reg_backup[24];\n};\n\nenum {\n\tMODE_640x480 = 0,\n\tMODE_800x600 = 1,\n\tMODE_1024x768 = 2,\n};\n\nstruct ns2501_reg {\n\tu8 offset;\n\tu8 value;\n};\n\nstruct ns2501_configuration {\n\tu8 sync;\n\tu8 conf;\n\tu8 syncb;\n\tu8 dither;\n\tu8 pll_a;\n\tu16 pll_b;\n\tu16 hstart;\n\tu16 hstop;\n\tu16 vstart;\n\tu16 vstop;\n\tu16 vsync;\n\tu16 vtotal;\n\tu16 hpos;\n\tu16 vpos;\n\tu16 voffs;\n\tu16 hscale;\n\tu16 vscale;\n};\n\nstruct ns2501_priv {\n\tbool quiet;\n\tconst struct ns2501_configuration *conf;\n};\n\nstruct sil164_priv {\n\tbool quiet;\n};\n\nstruct tfp410_priv {\n\tbool quiet;\n};\n\nstruct intel_dsi_host;\n\nstruct intel_dsi {\n\tstruct intel_encoder base;\n\tstruct intel_dsi_host *dsi_hosts[9];\n\tintel_wakeref_t io_wakeref[9];\n\tstruct gpio_desc *gpio_panel;\n\tstruct gpio_desc *gpio_backlight;\n\tstruct intel_connector *attached_connector;\n\tunion {\n\t\tu16 ports;\n\t\tu16 phys;\n\t};\n\tbool hs;\n\tint channel;\n\tu16 operation_mode;\n\tunsigned int lane_count;\n\tint i2c_bus_num;\n\tenum mipi_dsi_pixel_format pixel_format;\n\tu32 video_mode_format;\n\tu8 eotp_pkt;\n\tu8 clock_stop;\n\tu8 escape_clk_div;\n\tu8 dual_link;\n\tu16 dcs_backlight_ports;\n\tu16 dcs_cabc_ports;\n\tbool bgr_enabled;\n\tu8 pixel_overlap;\n\tu32 port_bits;\n\tu32 bw_timer;\n\tu32 dphy_reg;\n\tu32 dphy_data_lane_reg;\n\tu32 video_frmt_cfg_bits;\n\tu16 lp_byte_clk;\n\tu16 hs_tx_timeout;\n\tu16 lp_rx_timeout;\n\tu16 turn_arnd_val;\n\tu16 rst_timer_val;\n\tu16 hs_to_lp_count;\n\tu16 clk_lp_to_hs_count;\n\tu16 clk_hs_to_lp_count;\n\tu16 init_count;\n\tu32 pclk;\n\tu16 burst_mode_ratio;\n\tu16 backlight_off_delay;\n\tu16 backlight_on_delay;\n\tu16 panel_on_delay;\n\tu16 panel_off_delay;\n\tu16 panel_pwr_cycle_delay;\n};\n\nstruct intel_dsi_host {\n\tstruct mipi_dsi_host base;\n\tstruct intel_dsi *intel_dsi;\n\tenum port port;\n\tstruct mipi_dsi_device *device;\n};\n\nstruct intel_crt {\n\tstruct intel_encoder base;\n\tstruct intel_connector *connector;\n\tbool force_hotplug_required;\n\ti915_reg_t adpa_reg;\n};\n\nstruct ddi_buf_trans {\n\tu32 trans1;\n\tu32 trans2;\n\tu8 i_boost;\n};\n\nstruct bxt_ddi_buf_trans {\n\tu8 margin;\n\tu8 scale;\n\tu8 enable;\n\tu8 deemphasis;\n};\n\nstruct cnl_ddi_buf_trans {\n\tu8 dw2_swing_sel;\n\tu8 dw7_n_scalar;\n\tu8 dw4_cursor_coeff;\n\tu8 dw4_post_cursor_2;\n\tu8 dw4_post_cursor_1;\n};\n\nstruct icl_mg_phy_ddi_buf_trans {\n\tu32 cri_txdeemph_override_11_6;\n\tu32 cri_txdeemph_override_5_0;\n\tu32 cri_txdeemph_override_17_12;\n};\n\nstruct tgl_dkl_phy_ddi_buf_trans {\n\tu32 dkl_vswing_control;\n\tu32 dkl_preshoot_control;\n\tu32 dkl_de_emphasis_control;\n};\n\nstruct dp_sdp {\n\tstruct dp_sdp_header sdp_header;\n\tu8 db[32];\n};\n\nstruct link_config_limits {\n\tint min_clock;\n\tint max_clock;\n\tint min_lane_count;\n\tint max_lane_count;\n\tint min_bpp;\n\tint max_bpp;\n};\n\nstruct dp_link_dpll {\n\tint clock;\n\tstruct dpll dpll;\n};\n\ntypedef bool (*vlv_pipe_check)(struct drm_i915_private *, enum pipe);\n\nstruct pps_registers {\n\ti915_reg_t pp_ctrl;\n\ti915_reg_t pp_stat;\n\ti915_reg_t pp_on;\n\ti915_reg_t pp_off;\n\ti915_reg_t pp_div;\n};\n\nstruct hdcp2_dp_errata_stream_type {\n\tu8 msg_id;\n\tu8 stream_type;\n};\n\nstruct hdcp2_dp_msg_data {\n\tu8 msg_id;\n\tu32 offset;\n\tbool msg_detectable;\n\tu32 timeout;\n\tu32 timeout2;\n};\n\nenum gpio_lookup_flags {\n\tGPIO_ACTIVE_HIGH = 0,\n\tGPIO_ACTIVE_LOW = 1,\n\tGPIO_OPEN_DRAIN = 2,\n\tGPIO_OPEN_SOURCE = 4,\n\tGPIO_PERSISTENT = 0,\n\tGPIO_TRANSITORY = 8,\n\tGPIO_PULL_UP = 16,\n\tGPIO_PULL_DOWN = 32,\n\tGPIO_LOOKUP_FLAGS_DEFAULT = 0,\n};\n\nstruct gpiod_lookup {\n\tconst char *key;\n\tu16 chip_hwnum;\n\tconst char *con_id;\n\tunsigned int idx;\n\tlong unsigned int flags;\n};\n\nstruct gpiod_lookup_table {\n\tstruct list_head list;\n\tconst char *dev_id;\n\tstruct gpiod_lookup table[0];\n};\n\nenum pinctrl_map_type {\n\tPIN_MAP_TYPE_INVALID = 0,\n\tPIN_MAP_TYPE_DUMMY_STATE = 1,\n\tPIN_MAP_TYPE_MUX_GROUP = 2,\n\tPIN_MAP_TYPE_CONFIGS_PIN = 3,\n\tPIN_MAP_TYPE_CONFIGS_GROUP = 4,\n};\n\nstruct pinctrl_map_mux {\n\tconst char *group;\n\tconst char *function;\n};\n\nstruct pinctrl_map_configs {\n\tconst char *group_or_pin;\n\tlong unsigned int *configs;\n\tunsigned int num_configs;\n};\n\nstruct pinctrl_map {\n\tconst char *dev_name;\n\tconst char *name;\n\tenum pinctrl_map_type type;\n\tconst char *ctrl_dev_name;\n\tunion {\n\t\tstruct pinctrl_map_mux mux;\n\t\tstruct pinctrl_map_configs configs;\n\t} data;\n};\n\nstruct gpio_map {\n\tu16 base_offset;\n\tbool init;\n};\n\nstruct i2c_adapter_lookup {\n\tu16 slave_addr;\n\tstruct intel_dsi *intel_dsi;\n\tacpi_handle dev_handle;\n};\n\ntypedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *, const u8 *);\n\nstruct pinctrl;\n\nstruct pinctrl_state;\n\nstruct intel_dvo {\n\tstruct intel_encoder base;\n\tstruct intel_dvo_device dev;\n\tstruct intel_connector *attached_connector;\n\tbool panel_wants_dither;\n};\n\nenum i915_gpio {\n\tGPIOA = 0,\n\tGPIOB = 1,\n\tGPIOC = 2,\n\tGPIOD = 3,\n\tGPIOE = 4,\n\tGPIOF = 5,\n\tGPIOG = 6,\n\tGPIOH = 7,\n\t__GPIOI_UNUSED = 8,\n\tGPIOJ = 9,\n\tGPIOK = 10,\n\tGPIOL = 11,\n\tGPIOM = 12,\n\tGPION = 13,\n\tGPIOO = 14,\n};\n\nstruct gmbus_pin {\n\tconst char *name;\n\tenum i915_gpio gpio;\n};\n\nstruct hdcp2_hdmi_msg_timeout {\n\tu8 msg_id;\n\tu16 timeout;\n};\n\nenum vga_switcheroo_handler_flags_t {\n\tVGA_SWITCHEROO_CAN_SWITCH_DDC = 1,\n\tVGA_SWITCHEROO_NEEDS_EDP_CONFIG = 2,\n};\n\nstruct intel_lvds_pps {\n\tint t1_t2;\n\tint t3;\n\tint t4;\n\tint t5;\n\tint tx;\n\tint divider;\n\tint port;\n\tbool powerdown_on_reset;\n};\n\nstruct intel_lvds_encoder {\n\tstruct intel_encoder base;\n\tbool is_dual_link;\n\ti915_reg_t reg;\n\tu32 a3_power;\n\tstruct intel_lvds_pps init_pps;\n\tu32 init_lvds_val;\n\tstruct intel_connector *attached_connector;\n};\n\nenum pwm_polarity {\n\tPWM_POLARITY_NORMAL = 0,\n\tPWM_POLARITY_INVERSED = 1,\n};\n\nstruct pwm_args {\n\tunsigned int period;\n\tenum pwm_polarity polarity;\n};\n\nstruct pwm_state {\n\tunsigned int period;\n\tunsigned int duty_cycle;\n\tenum pwm_polarity polarity;\n\tbool enabled;\n};\n\nstruct pwm_chip;\n\nstruct pwm_device {\n\tconst char *label;\n\tlong unsigned int flags;\n\tunsigned int hwpwm;\n\tunsigned int pwm;\n\tstruct pwm_chip *chip;\n\tvoid *chip_data;\n\tstruct pwm_args args;\n\tstruct pwm_state state;\n\tstruct pwm_state last;\n};\n\nstruct pwm_ops;\n\nstruct pwm_chip {\n\tstruct device *dev;\n\tconst struct pwm_ops *ops;\n\tint base;\n\tunsigned int npwm;\n\tstruct pwm_device * (*of_xlate)(struct pwm_chip *, const struct of_phandle_args *);\n\tunsigned int of_pwm_n_cells;\n\tstruct list_head list;\n\tstruct pwm_device *pwms;\n};\n\nstruct pwm_capture;\n\nstruct pwm_ops {\n\tint (*request)(struct pwm_chip *, struct pwm_device *);\n\tvoid (*free)(struct pwm_chip *, struct pwm_device *);\n\tint (*capture)(struct pwm_chip *, struct pwm_device *, struct pwm_capture *, long unsigned int);\n\tint (*apply)(struct pwm_chip *, struct pwm_device *, const struct pwm_state *);\n\tvoid (*get_state)(struct pwm_chip *, struct pwm_device *, struct pwm_state *);\n\tstruct module *owner;\n\tint (*config)(struct pwm_chip *, struct pwm_device *, int, int);\n\tint (*set_polarity)(struct pwm_chip *, struct pwm_device *, enum pwm_polarity);\n\tint (*enable)(struct pwm_chip *, struct pwm_device *);\n\tvoid (*disable)(struct pwm_chip *, struct pwm_device *);\n};\n\nstruct pwm_capture {\n\tunsigned int period;\n\tunsigned int duty_cycle;\n};\n\nstruct intel_sdvo_caps {\n\tu8 vendor_id;\n\tu8 device_id;\n\tu8 device_rev_id;\n\tu8 sdvo_version_major;\n\tu8 sdvo_version_minor;\n\tunsigned int sdvo_inputs_mask: 2;\n\tunsigned int smooth_scaling: 1;\n\tunsigned int sharp_scaling: 1;\n\tunsigned int up_scaling: 1;\n\tunsigned int down_scaling: 1;\n\tunsigned int stall_support: 1;\n\tunsigned int pad: 1;\n\tu16 output_flags;\n};\n\nstruct intel_sdvo_dtd {\n\tstruct {\n\t\tu16 clock;\n\t\tu8 h_active;\n\t\tu8 h_blank;\n\t\tu8 h_high;\n\t\tu8 v_active;\n\t\tu8 v_blank;\n\t\tu8 v_high;\n\t} part1;\n\tstruct {\n\t\tu8 h_sync_off;\n\t\tu8 h_sync_width;\n\t\tu8 v_sync_off_width;\n\t\tu8 sync_off_width_high;\n\t\tu8 dtd_flags;\n\t\tu8 sdvo_flags;\n\t\tu8 v_sync_off_high;\n\t\tu8 reserved;\n\t} part2;\n};\n\nstruct intel_sdvo_pixel_clock_range {\n\tu16 min;\n\tu16 max;\n};\n\nstruct intel_sdvo_preferred_input_timing_args {\n\tu16 clock;\n\tu16 width;\n\tu16 height;\n\tu8 interlace: 1;\n\tu8 scaled: 1;\n\tu8 pad: 6;\n} __attribute__((packed));\n\nstruct intel_sdvo_get_trained_inputs_response {\n\tunsigned int input0_trained: 1;\n\tunsigned int input1_trained: 1;\n\tunsigned int pad: 6;\n} __attribute__((packed));\n\nstruct intel_sdvo_in_out_map {\n\tu16 in0;\n\tu16 in1;\n};\n\nstruct intel_sdvo_set_target_input_args {\n\tunsigned int target_1: 1;\n\tunsigned int pad: 7;\n} __attribute__((packed));\n\nstruct intel_sdvo_tv_format {\n\tunsigned int ntsc_m: 1;\n\tunsigned int ntsc_j: 1;\n\tunsigned int ntsc_443: 1;\n\tunsigned int pal_b: 1;\n\tunsigned int pal_d: 1;\n\tunsigned int pal_g: 1;\n\tunsigned int pal_h: 1;\n\tunsigned int pal_i: 1;\n\tunsigned int pal_m: 1;\n\tunsigned int pal_n: 1;\n\tunsigned int pal_nc: 1;\n\tunsigned int pal_60: 1;\n\tunsigned int secam_b: 1;\n\tunsigned int secam_d: 1;\n\tunsigned int secam_g: 1;\n\tunsigned int secam_k: 1;\n\tunsigned int secam_k1: 1;\n\tunsigned int secam_l: 1;\n\tunsigned int secam_60: 1;\n\tunsigned int hdtv_std_smpte_240m_1080i_59: 1;\n\tunsigned int hdtv_std_smpte_240m_1080i_60: 1;\n\tunsigned int hdtv_std_smpte_260m_1080i_59: 1;\n\tunsigned int hdtv_std_smpte_260m_1080i_60: 1;\n\tunsigned int hdtv_std_smpte_274m_1080i_50: 1;\n\tunsigned int hdtv_std_smpte_274m_1080i_59: 1;\n\tunsigned int hdtv_std_smpte_274m_1080i_60: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_23: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_24: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_25: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_29: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_30: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_50: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_59: 1;\n\tunsigned int hdtv_std_smpte_274m_1080p_60: 1;\n\tunsigned int hdtv_std_smpte_295m_1080i_50: 1;\n\tunsigned int hdtv_std_smpte_295m_1080p_50: 1;\n\tunsigned int hdtv_std_smpte_296m_720p_59: 1;\n\tunsigned int hdtv_std_smpte_296m_720p_60: 1;\n\tunsigned int hdtv_std_smpte_296m_720p_50: 1;\n\tunsigned int hdtv_std_smpte_293m_480p_59: 1;\n\tunsigned int hdtv_std_smpte_170m_480i_59: 1;\n\tunsigned int hdtv_std_iturbt601_576i_50: 1;\n\tunsigned int hdtv_std_iturbt601_576p_50: 1;\n\tunsigned int hdtv_std_eia_7702a_480i_60: 1;\n\tunsigned int hdtv_std_eia_7702a_480p_60: 1;\n\tunsigned int pad: 3;\n} __attribute__((packed));\n\nstruct intel_sdvo_sdtv_resolution_request {\n\tunsigned int ntsc_m: 1;\n\tunsigned int ntsc_j: 1;\n\tunsigned int ntsc_443: 1;\n\tunsigned int pal_b: 1;\n\tunsigned int pal_d: 1;\n\tunsigned int pal_g: 1;\n\tunsigned int pal_h: 1;\n\tunsigned int pal_i: 1;\n\tunsigned int pal_m: 1;\n\tunsigned int pal_n: 1;\n\tunsigned int pal_nc: 1;\n\tunsigned int pal_60: 1;\n\tunsigned int secam_b: 1;\n\tunsigned int secam_d: 1;\n\tunsigned int secam_g: 1;\n\tunsigned int secam_k: 1;\n\tunsigned int secam_k1: 1;\n\tunsigned int secam_l: 1;\n\tunsigned int secam_60: 1;\n\tunsigned int pad: 5;\n} __attribute__((packed));\n\nstruct intel_sdvo_enhancements_reply {\n\tunsigned int flicker_filter: 1;\n\tunsigned int flicker_filter_adaptive: 1;\n\tunsigned int flicker_filter_2d: 1;\n\tunsigned int saturation: 1;\n\tunsigned int hue: 1;\n\tunsigned int brightness: 1;\n\tunsigned int contrast: 1;\n\tunsigned int overscan_h: 1;\n\tunsigned int overscan_v: 1;\n\tunsigned int hpos: 1;\n\tunsigned int vpos: 1;\n\tunsigned int sharpness: 1;\n\tunsigned int dot_crawl: 1;\n\tunsigned int dither: 1;\n\tunsigned int tv_chroma_filter: 1;\n\tunsigned int tv_luma_filter: 1;\n} __attribute__((packed));\n\nstruct intel_sdvo_encode {\n\tu8 dvi_rev;\n\tu8 hdmi_rev;\n};\n\nstruct intel_sdvo {\n\tstruct intel_encoder base;\n\tstruct i2c_adapter *i2c;\n\tu8 slave_addr;\n\tlong: 56;\n\tstruct i2c_adapter ddc;\n\ti915_reg_t sdvo_reg;\n\tu16 controlled_output;\n\tstruct intel_sdvo_caps caps;\n\tshort: 16;\n\tint pixel_clock_min;\n\tint pixel_clock_max;\n\tu16 attached_output;\n\tu16 hotplug_active;\n\tenum port port;\n\tbool has_hdmi_monitor;\n\tbool has_hdmi_audio;\n\tu8 ddc_bus;\n\tu8 dtd_sdvo_flags;\n\tint: 32;\n} __attribute__((packed));\n\nstruct intel_sdvo_connector {\n\tstruct intel_connector base;\n\tu16 output_flag;\n\tu8 tv_format_supported[19];\n\tint format_supported_num;\n\tstruct drm_property *tv_format;\n\tstruct drm_property *left;\n\tstruct drm_property *right;\n\tstruct drm_property *top;\n\tstruct drm_property *bottom;\n\tstruct drm_property *hpos;\n\tstruct drm_property *vpos;\n\tstruct drm_property *contrast;\n\tstruct drm_property *saturation;\n\tstruct drm_property *hue;\n\tstruct drm_property *sharpness;\n\tstruct drm_property *flicker_filter;\n\tstruct drm_property *flicker_filter_adaptive;\n\tstruct drm_property *flicker_filter_2d;\n\tstruct drm_property *tv_chroma_filter;\n\tstruct drm_property *tv_luma_filter;\n\tstruct drm_property *dot_crawl;\n\tstruct drm_property *brightness;\n\tu32 max_hscan;\n\tu32 max_vscan;\n\tbool is_hdmi;\n};\n\nstruct intel_sdvo_connector_state {\n\tstruct intel_digital_connector_state base;\n\tstruct {\n\t\tunsigned int overscan_h;\n\t\tunsigned int overscan_v;\n\t\tunsigned int hpos;\n\t\tunsigned int vpos;\n\t\tunsigned int sharpness;\n\t\tunsigned int flicker_filter;\n\t\tunsigned int flicker_filter_2d;\n\t\tunsigned int flicker_filter_adaptive;\n\t\tunsigned int chroma_filter;\n\t\tunsigned int luma_filter;\n\t\tunsigned int dot_crawl;\n\t} tv;\n};\n\nstruct intel_tv {\n\tstruct intel_encoder base;\n\tint type;\n};\n\nstruct video_levels {\n\tu16 blank;\n\tu16 black;\n\tu8 burst;\n};\n\nstruct color_conversion {\n\tu16 ry;\n\tu16 gy;\n\tu16 by;\n\tu16 ay;\n\tu16 ru;\n\tu16 gu;\n\tu16 bu;\n\tu16 au;\n\tu16 rv;\n\tu16 gv;\n\tu16 bv;\n\tu16 av;\n};\n\nstruct tv_mode {\n\tconst char *name;\n\tu32 clock;\n\tu16 refresh;\n\tu8 oversample;\n\tu8 hsync_end;\n\tu16 hblank_start;\n\tu16 hblank_end;\n\tu16 htotal;\n\tbool progressive: 1;\n\tbool trilevel_sync: 1;\n\tbool component_only: 1;\n\tu8 vsync_start_f1;\n\tu8 vsync_start_f2;\n\tu8 vsync_len;\n\tbool veq_ena: 1;\n\tu8 veq_start_f1;\n\tu8 veq_start_f2;\n\tu8 veq_len;\n\tu8 vi_end_f1;\n\tu8 vi_end_f2;\n\tu16 nbr_end;\n\tbool burst_ena: 1;\n\tu8 hburst_start;\n\tu8 hburst_len;\n\tu8 vburst_start_f1;\n\tu16 vburst_end_f1;\n\tu8 vburst_start_f2;\n\tu16 vburst_end_f2;\n\tu8 vburst_start_f3;\n\tu16 vburst_end_f3;\n\tu8 vburst_start_f4;\n\tu16 vburst_end_f4;\n\tu16 dda2_size;\n\tu16 dda3_size;\n\tu8 dda1_inc;\n\tu16 dda2_inc;\n\tu16 dda3_inc;\n\tu32 sc_reset;\n\tbool pal_burst: 1;\n\tconst struct video_levels *composite_levels;\n\tconst struct video_levels *svideo_levels;\n\tconst struct color_conversion *composite_color;\n\tconst struct color_conversion *svideo_color;\n\tconst u32 *filter_table;\n};\n\nstruct intel_tv_connector_state {\n\tstruct drm_connector_state base;\n\tstruct {\n\t\tu16 top;\n\t\tu16 bottom;\n\t} margins;\n\tbool bypass_vfilter;\n};\n\nstruct input_res {\n\tu16 w;\n\tu16 h;\n};\n\nstruct drm_dsc_pps_infoframe {\n\tstruct dp_sdp_header pps_header;\n\tstruct drm_dsc_picture_parameter_set pps_payload;\n};\n\nenum ROW_INDEX_BPP {\n\tROW_INDEX_6BPP = 0,\n\tROW_INDEX_8BPP = 1,\n\tROW_INDEX_10BPP = 2,\n\tROW_INDEX_12BPP = 3,\n\tROW_INDEX_15BPP = 4,\n\tMAX_ROW_INDEX = 5,\n};\n\nenum COLUMN_INDEX_BPC {\n\tCOLUMN_INDEX_8BPC = 0,\n\tCOLUMN_INDEX_10BPC = 1,\n\tCOLUMN_INDEX_12BPC = 2,\n\tCOLUMN_INDEX_14BPC = 3,\n\tCOLUMN_INDEX_16BPC = 4,\n\tMAX_COLUMN_INDEX = 5,\n};\n\nstruct rc_parameters {\n\tu16 initial_xmit_delay;\n\tu8 first_line_bpg_offset;\n\tu16 initial_offset;\n\tu8 flatness_min_qp;\n\tu8 flatness_max_qp;\n\tu8 rc_quant_incr_limit0;\n\tu8 rc_quant_incr_limit1;\n\tstruct drm_dsc_rc_range_parameters rc_range_params[15];\n};\n\nenum drm_i915_oa_format {\n\tI915_OA_FORMAT_A13 = 1,\n\tI915_OA_FORMAT_A29 = 2,\n\tI915_OA_FORMAT_A13_B8_C8 = 3,\n\tI915_OA_FORMAT_B4_C8 = 4,\n\tI915_OA_FORMAT_A45_B8_C8 = 5,\n\tI915_OA_FORMAT_B4_C8_A16 = 6,\n\tI915_OA_FORMAT_C4_B8 = 7,\n\tI915_OA_FORMAT_A12 = 8,\n\tI915_OA_FORMAT_A12_B8_C8 = 9,\n\tI915_OA_FORMAT_A32u40_A4u32_B8_C8 = 10,\n\tI915_OA_FORMAT_MAX = 11,\n};\n\nenum drm_i915_perf_property_id {\n\tDRM_I915_PERF_PROP_CTX_HANDLE = 1,\n\tDRM_I915_PERF_PROP_SAMPLE_OA = 2,\n\tDRM_I915_PERF_PROP_OA_METRICS_SET = 3,\n\tDRM_I915_PERF_PROP_OA_FORMAT = 4,\n\tDRM_I915_PERF_PROP_OA_EXPONENT = 5,\n\tDRM_I915_PERF_PROP_HOLD_PREEMPTION = 6,\n\tDRM_I915_PERF_PROP_GLOBAL_SSEU = 7,\n\tDRM_I915_PERF_PROP_POLL_OA_PERIOD = 8,\n\tDRM_I915_PERF_PROP_MAX = 9,\n};\n\nstruct drm_i915_perf_open_param {\n\t__u32 flags;\n\t__u32 num_properties;\n\t__u64 properties_ptr;\n};\n\nstruct drm_i915_perf_record_header {\n\t__u32 type;\n\t__u16 pad;\n\t__u16 size;\n};\n\nenum drm_i915_perf_record_type {\n\tDRM_I915_PERF_RECORD_SAMPLE = 1,\n\tDRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,\n\tDRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,\n\tDRM_I915_PERF_RECORD_MAX = 4,\n};\n\nstruct perf_open_properties {\n\tu32 sample_flags;\n\tu64 single_context: 1;\n\tu64 hold_preemption: 1;\n\tu64 ctx_handle;\n\tint metrics_set;\n\tint oa_format;\n\tbool oa_periodic;\n\tint oa_period_exponent;\n\tstruct intel_engine_cs *engine;\n\tbool has_sseu;\n\tstruct intel_sseu sseu;\n\tu64 poll_oa_period;\n};\n\nstruct i915_oa_config_bo {\n\tstruct llist_node node;\n\tstruct i915_oa_config *oa_config;\n\tstruct i915_vma *vma;\n};\n\nstruct flex {\n\ti915_reg_t reg;\n\tu32 offset;\n\tu32 value;\n};\n\nenum {\n\tSTART_TS = 0,\n\tNOW_TS = 1,\n\tDELTA_TS = 2,\n\tJUMP_PREDICATE = 3,\n\tDELTA_TARGET = 4,\n\tN_CS_GPR = 5,\n};\n\nstruct i915_vma_compress___2 {\n\tstruct pagevec pool;\n\tstruct z_stream_s zstream;\n\tvoid *tmp;\n};\n\nstruct intel_engine_capture_vma___2 {\n\tstruct intel_engine_capture_vma___2 *next;\n\tstruct i915_vma *vma;\n\tchar name[16];\n};\n\nstruct _balloon_info_ {\n\tstruct drm_mm_node space[4];\n};\n\nstruct vga_device {\n\tstruct list_head list;\n\tstruct pci_dev *pdev;\n\tunsigned int decodes;\n\tunsigned int owns;\n\tunsigned int locks;\n\tunsigned int io_lock_cnt;\n\tunsigned int mem_lock_cnt;\n\tunsigned int io_norm_cnt;\n\tunsigned int mem_norm_cnt;\n\tbool bridge_has_one_vga;\n\tvoid *cookie;\n\tvoid (*irq_set_state)(void *, bool);\n\tunsigned int (*set_vga_decode)(void *, bool);\n};\n\nstruct vga_arb_user_card {\n\tstruct pci_dev *pdev;\n\tunsigned int mem_cnt;\n\tunsigned int io_cnt;\n};\n\nstruct vga_arb_private {\n\tstruct list_head list;\n\tstruct pci_dev *target;\n\tstruct vga_arb_user_card cards[16];\n\tspinlock_t lock;\n};\n\nstruct cb_id {\n\t__u32 idx;\n\t__u32 val;\n};\n\nstruct cn_msg {\n\tstruct cb_id id;\n\t__u32 seq;\n\t__u32 ack;\n\t__u16 len;\n\t__u16 flags;\n\t__u8 data[0];\n};\n\nstruct cn_queue_dev {\n\tatomic_t refcnt;\n\tunsigned char name[32];\n\tstruct list_head queue_list;\n\tspinlock_t queue_lock;\n\tstruct sock *nls;\n};\n\nstruct cn_callback_id {\n\tunsigned char name[32];\n\tstruct cb_id id;\n};\n\nstruct cn_callback_entry {\n\tstruct list_head callback_entry;\n\trefcount_t refcnt;\n\tstruct cn_queue_dev *pdev;\n\tstruct cn_callback_id id;\n\tvoid (*callback)(struct cn_msg *, struct netlink_skb_parms *);\n\tu32 seq;\n\tu32 group;\n};\n\nstruct cn_dev {\n\tstruct cb_id id;\n\tu32 seq;\n\tu32 groups;\n\tstruct sock *nls;\n\tstruct cn_queue_dev *cbdev;\n};\n\nenum proc_cn_mcast_op {\n\tPROC_CN_MCAST_LISTEN = 1,\n\tPROC_CN_MCAST_IGNORE = 2,\n};\n\nstruct fork_proc_event {\n\t__kernel_pid_t parent_pid;\n\t__kernel_pid_t parent_tgid;\n\t__kernel_pid_t child_pid;\n\t__kernel_pid_t child_tgid;\n};\n\nstruct exec_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n};\n\nstruct id_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\tunion {\n\t\t__u32 ruid;\n\t\t__u32 rgid;\n\t} r;\n\tunion {\n\t\t__u32 euid;\n\t\t__u32 egid;\n\t} e;\n};\n\nstruct sid_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n};\n\nstruct ptrace_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\t__kernel_pid_t tracer_pid;\n\t__kernel_pid_t tracer_tgid;\n};\n\nstruct comm_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\tchar comm[16];\n};\n\nstruct coredump_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\t__kernel_pid_t parent_pid;\n\t__kernel_pid_t parent_tgid;\n};\n\nstruct exit_proc_event {\n\t__kernel_pid_t process_pid;\n\t__kernel_pid_t process_tgid;\n\t__u32 exit_code;\n\t__u32 exit_signal;\n\t__kernel_pid_t parent_pid;\n\t__kernel_pid_t parent_tgid;\n};\n\nstruct proc_event {\n\tenum what what;\n\t__u32 cpu;\n\t__u64 timestamp_ns;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 err;\n\t\t} ack;\n\t\tstruct fork_proc_event fork;\n\t\tstruct exec_proc_event exec;\n\t\tstruct id_proc_event id;\n\t\tstruct sid_proc_event sid;\n\t\tstruct ptrace_proc_event ptrace;\n\t\tstruct comm_proc_event comm;\n\t\tstruct coredump_proc_event coredump;\n\t\tstruct exit_proc_event exit;\n\t} event_data;\n};\n\nstruct local_event {\n\tlocal_lock_t lock;\n\t__u32 count;\n};\n\nstruct component_master_ops {\n\tint (*bind)(struct device *);\n\tvoid (*unbind)(struct device *);\n};\n\nstruct component;\n\nstruct component_match_array {\n\tvoid *data;\n\tint (*compare)(struct device *, void *);\n\tint (*compare_typed)(struct device *, int, void *);\n\tvoid (*release)(struct device *, void *);\n\tstruct component *component;\n\tbool duplicate;\n};\n\nstruct master;\n\nstruct component {\n\tstruct list_head node;\n\tstruct master *master;\n\tbool bound;\n\tconst struct component_ops *ops;\n\tint subcomponent;\n\tstruct device *dev;\n};\n\nstruct component_match {\n\tsize_t alloc;\n\tsize_t num;\n\tstruct component_match_array *compare;\n};\n\nstruct master {\n\tstruct list_head node;\n\tbool bound;\n\tconst struct component_master_ops *ops;\n\tstruct device *dev;\n\tstruct component_match *match;\n\tstruct dentry *dentry;\n};\n\nstruct wake_irq {\n\tstruct device *dev;\n\tunsigned int status;\n\tint irq;\n\tconst char *name;\n};\n\nenum dpm_order {\n\tDPM_ORDER_NONE = 0,\n\tDPM_ORDER_DEV_AFTER_PARENT = 1,\n\tDPM_ORDER_PARENT_BEFORE_DEV = 2,\n\tDPM_ORDER_DEV_LAST = 3,\n};\n\nstruct subsys_private {\n\tstruct kset subsys;\n\tstruct kset *devices_kset;\n\tstruct list_head interfaces;\n\tstruct mutex mutex;\n\tstruct kset *drivers_kset;\n\tstruct klist klist_devices;\n\tstruct klist klist_drivers;\n\tstruct blocking_notifier_head bus_notifier;\n\tunsigned int drivers_autoprobe: 1;\n\tstruct bus_type *bus;\n\tstruct kset glue_dirs;\n\tstruct class *class;\n};\n\nstruct driver_private {\n\tstruct kobject kobj;\n\tstruct klist klist_devices;\n\tstruct klist_node knode_bus;\n\tstruct module_kobject *mkobj;\n\tstruct device_driver *driver;\n};\n\nstruct device_private {\n\tstruct klist klist_children;\n\tstruct klist_node knode_parent;\n\tstruct klist_node knode_driver;\n\tstruct klist_node knode_bus;\n\tstruct klist_node knode_class;\n\tstruct list_head deferred_probe;\n\tstruct device_driver *async_driver;\n\tstruct device *device;\n\tu8 dead: 1;\n};\n\nunion device_attr_group_devres {\n\tconst struct attribute_group *group;\n\tconst struct attribute_group **groups;\n};\n\nstruct class_dir {\n\tstruct kobject kobj;\n\tstruct class *class;\n};\n\nstruct root_device {\n\tstruct device dev;\n\tstruct module *owner;\n};\n\nstruct subsys_dev_iter {\n\tstruct klist_iter ki;\n\tconst struct device_type *type;\n};\n\nstruct device_attach_data {\n\tstruct device *dev;\n\tbool check_async;\n\tbool want_async;\n\tbool have_async;\n};\n\nstruct class_compat {\n\tstruct kobject *kobj;\n};\n\nstruct platform_object {\n\tstruct platform_device pdev;\n\tchar name[0];\n};\n\nstruct cpu_attr {\n\tstruct device_attribute attr;\n\tconst struct cpumask * const map;\n};\n\ntypedef struct kobject *kobj_probe_t(dev_t, int *, void *);\n\nstruct probe {\n\tstruct probe *next;\n\tdev_t dev;\n\tlong unsigned int range;\n\tstruct module *owner;\n\tkobj_probe_t *get;\n\tint (*lock)(dev_t, void *);\n\tvoid *data;\n};\n\nstruct kobj_map___2 {\n\tstruct probe *probes[255];\n\tstruct mutex *lock;\n};\n\ntypedef void (*dr_release_t)(struct device *, void *);\n\ntypedef int (*dr_match_t)(struct device *, void *, void *);\n\nstruct devres_node {\n\tstruct list_head entry;\n\tdr_release_t release;\n\tconst char *name;\n\tsize_t size;\n};\n\nstruct devres {\n\tstruct devres_node node;\n\tu8 data[0];\n};\n\nstruct devres_group {\n\tstruct devres_node node[2];\n\tvoid *id;\n\tint color;\n};\n\nstruct action_devres {\n\tvoid *data;\n\tvoid (*action)(void *);\n};\n\nstruct pages_devres {\n\tlong unsigned int addr;\n\tunsigned int order;\n};\n\nstruct attribute_container {\n\tstruct list_head node;\n\tstruct klist containers;\n\tstruct class *class;\n\tconst struct attribute_group *grp;\n\tstruct device_attribute **attrs;\n\tint (*match)(struct attribute_container *, struct device *);\n\tlong unsigned int flags;\n};\n\nstruct internal_container {\n\tstruct klist_node node;\n\tstruct attribute_container *cont;\n\tstruct device classdev;\n};\n\nstruct transport_container;\n\nstruct transport_class {\n\tstruct class class;\n\tint (*setup)(struct transport_container *, struct device *, struct device *);\n\tint (*configure)(struct transport_container *, struct device *, struct device *);\n\tint (*remove)(struct transport_container *, struct device *, struct device *);\n};\n\nstruct transport_container {\n\tstruct attribute_container ac;\n\tconst struct attribute_group *statistics;\n};\n\nstruct anon_transport_class {\n\tstruct transport_class tclass;\n\tstruct attribute_container container;\n};\n\nstruct reset_control;\n\nstruct mii_bus;\n\nstruct mdio_device {\n\tstruct device dev;\n\tstruct mii_bus *bus;\n\tchar modalias[32];\n\tint (*bus_match)(struct device *, struct device_driver *);\n\tvoid (*device_free)(struct mdio_device *);\n\tvoid (*device_remove)(struct mdio_device *);\n\tint addr;\n\tint flags;\n\tstruct gpio_desc *reset_gpio;\n\tstruct reset_control *reset_ctrl;\n\tunsigned int reset_assert_delay;\n\tunsigned int reset_deassert_delay;\n};\n\nstruct phy_c45_device_ids {\n\tu32 devices_in_package;\n\tu32 device_ids[8];\n};\n\nenum phy_state {\n\tPHY_DOWN = 0,\n\tPHY_READY = 1,\n\tPHY_HALTED = 2,\n\tPHY_UP = 3,\n\tPHY_RUNNING = 4,\n\tPHY_NOLINK = 5,\n\tPHY_CABLETEST = 6,\n};\n\ntypedef enum {\n\tPHY_INTERFACE_MODE_NA = 0,\n\tPHY_INTERFACE_MODE_INTERNAL = 1,\n\tPHY_INTERFACE_MODE_MII = 2,\n\tPHY_INTERFACE_MODE_GMII = 3,\n\tPHY_INTERFACE_MODE_SGMII = 4,\n\tPHY_INTERFACE_MODE_TBI = 5,\n\tPHY_INTERFACE_MODE_REVMII = 6,\n\tPHY_INTERFACE_MODE_RMII = 7,\n\tPHY_INTERFACE_MODE_RGMII = 8,\n\tPHY_INTERFACE_MODE_RGMII_ID = 9,\n\tPHY_INTERFACE_MODE_RGMII_RXID = 10,\n\tPHY_INTERFACE_MODE_RGMII_TXID = 11,\n\tPHY_INTERFACE_MODE_RTBI = 12,\n\tPHY_INTERFACE_MODE_SMII = 13,\n\tPHY_INTERFACE_MODE_XGMII = 14,\n\tPHY_INTERFACE_MODE_XLGMII = 15,\n\tPHY_INTERFACE_MODE_MOCA = 16,\n\tPHY_INTERFACE_MODE_QSGMII = 17,\n\tPHY_INTERFACE_MODE_TRGMII = 18,\n\tPHY_INTERFACE_MODE_1000BASEX = 19,\n\tPHY_INTERFACE_MODE_2500BASEX = 20,\n\tPHY_INTERFACE_MODE_RXAUI = 21,\n\tPHY_INTERFACE_MODE_XAUI = 22,\n\tPHY_INTERFACE_MODE_10GBASER = 23,\n\tPHY_INTERFACE_MODE_USXGMII = 24,\n\tPHY_INTERFACE_MODE_10GKR = 25,\n\tPHY_INTERFACE_MODE_MAX = 26,\n} phy_interface_t;\n\nstruct phylink;\n\nstruct phy_driver;\n\nstruct phy_package_shared;\n\nstruct mii_timestamper;\n\nstruct phy_device {\n\tstruct mdio_device mdio;\n\tstruct phy_driver *drv;\n\tu32 phy_id;\n\tstruct phy_c45_device_ids c45_ids;\n\tunsigned int is_c45: 1;\n\tunsigned int is_internal: 1;\n\tunsigned int is_pseudo_fixed_link: 1;\n\tunsigned int is_gigabit_capable: 1;\n\tunsigned int has_fixups: 1;\n\tunsigned int suspended: 1;\n\tunsigned int suspended_by_mdio_bus: 1;\n\tunsigned int sysfs_links: 1;\n\tunsigned int loopback_enabled: 1;\n\tunsigned int downshifted_rate: 1;\n\tunsigned int autoneg: 1;\n\tunsigned int link: 1;\n\tunsigned int autoneg_complete: 1;\n\tunsigned int interrupts: 1;\n\tenum phy_state state;\n\tu32 dev_flags;\n\tphy_interface_t interface;\n\tint speed;\n\tint duplex;\n\tint pause;\n\tint asym_pause;\n\tu8 master_slave_get;\n\tu8 master_slave_set;\n\tu8 master_slave_state;\n\tlong unsigned int supported[2];\n\tlong unsigned int advertising[2];\n\tlong unsigned int lp_advertising[2];\n\tlong unsigned int adv_old[2];\n\tu32 eee_broken_modes;\n\tint irq;\n\tvoid *priv;\n\tstruct phy_package_shared *shared;\n\tstruct sk_buff *skb;\n\tvoid *ehdr;\n\tstruct nlattr *nest;\n\tstruct delayed_work state_queue;\n\tstruct mutex lock;\n\tbool sfp_bus_attached;\n\tstruct sfp_bus *sfp_bus;\n\tstruct phylink *phylink;\n\tstruct net_device *attached_dev;\n\tstruct mii_timestamper *mii_ts;\n\tu8 mdix;\n\tu8 mdix_ctrl;\n\tvoid (*phy_link_change)(struct phy_device *, bool);\n\tvoid (*adjust_link)(struct net_device *);\n};\n\nstruct mdio_bus_stats {\n\tu64_stats_t transfers;\n\tu64_stats_t errors;\n\tu64_stats_t writes;\n\tu64_stats_t reads;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct mii_bus {\n\tstruct module *owner;\n\tconst char *name;\n\tchar id[61];\n\tvoid *priv;\n\tint (*read)(struct mii_bus *, int, int);\n\tint (*write)(struct mii_bus *, int, int, u16);\n\tint (*reset)(struct mii_bus *);\n\tstruct mdio_bus_stats stats[32];\n\tunsigned int is_managed: 1;\n\tunsigned int is_managed_registered: 1;\n\tstruct mutex mdio_lock;\n\tstruct device *parent;\n\tenum {\n\t\tMDIOBUS_ALLOCATED = 1,\n\t\tMDIOBUS_REGISTERED = 2,\n\t\tMDIOBUS_UNREGISTERED = 3,\n\t\tMDIOBUS_RELEASED = 4,\n\t} state;\n\tstruct device dev;\n\tstruct mdio_device *mdio_map[32];\n\tu32 phy_mask;\n\tu32 phy_ignore_ta_mask;\n\tint irq[32];\n\tint reset_delay_us;\n\tstruct gpio_desc *reset_gpiod;\n\tstruct mutex shared_lock;\n\tstruct phy_package_shared *shared[32];\n};\n\nstruct mdio_driver_common {\n\tstruct device_driver driver;\n\tint flags;\n};\n\nstruct mii_timestamper {\n\tbool (*rxtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tvoid (*txtstamp)(struct mii_timestamper *, struct sk_buff *, int);\n\tint (*hwtstamp)(struct mii_timestamper *, struct ifreq *);\n\tvoid (*link_state)(struct mii_timestamper *, struct phy_device *);\n\tint (*ts_info)(struct mii_timestamper *, struct ethtool_ts_info *);\n\tstruct device *device;\n};\n\nstruct phy_package_shared {\n\tint addr;\n\trefcount_t refcnt;\n\tlong unsigned int flags;\n\tsize_t priv_size;\n\tvoid *priv;\n};\n\nstruct phy_tdr_config;\n\nstruct phy_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tu32 phy_id;\n\tchar *name;\n\tu32 phy_id_mask;\n\tconst long unsigned int * const features;\n\tu32 flags;\n\tconst void *driver_data;\n\tint (*soft_reset)(struct phy_device *);\n\tint (*config_init)(struct phy_device *);\n\tint (*probe)(struct phy_device *);\n\tint (*get_features)(struct phy_device *);\n\tint (*suspend)(struct phy_device *);\n\tint (*resume)(struct phy_device *);\n\tint (*config_aneg)(struct phy_device *);\n\tint (*aneg_done)(struct phy_device *);\n\tint (*read_status)(struct phy_device *);\n\tint (*ack_interrupt)(struct phy_device *);\n\tint (*config_intr)(struct phy_device *);\n\tint (*did_interrupt)(struct phy_device *);\n\tirqreturn_t (*handle_interrupt)(struct phy_device *);\n\tvoid (*remove)(struct phy_device *);\n\tint (*match_phy_device)(struct phy_device *);\n\tint (*set_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*get_wol)(struct phy_device *, struct ethtool_wolinfo *);\n\tvoid (*link_change_notify)(struct phy_device *);\n\tint (*read_mmd)(struct phy_device *, int, u16);\n\tint (*write_mmd)(struct phy_device *, int, u16, u16);\n\tint (*read_page)(struct phy_device *);\n\tint (*write_page)(struct phy_device *, int);\n\tint (*module_info)(struct phy_device *, struct ethtool_modinfo *);\n\tint (*module_eeprom)(struct phy_device *, struct ethtool_eeprom *, u8 *);\n\tint (*cable_test_start)(struct phy_device *);\n\tint (*cable_test_tdr_start)(struct phy_device *, const struct phy_tdr_config *);\n\tint (*cable_test_get_status)(struct phy_device *, bool *);\n\tint (*get_sset_count)(struct phy_device *);\n\tvoid (*get_strings)(struct phy_device *, u8 *);\n\tvoid (*get_stats)(struct phy_device *, struct ethtool_stats *, u64 *);\n\tint (*get_tunable)(struct phy_device *, struct ethtool_tunable *, void *);\n\tint (*set_tunable)(struct phy_device *, struct ethtool_tunable *, const void *);\n\tint (*set_loopback)(struct phy_device *, bool);\n\tint (*get_sqi)(struct phy_device *);\n\tint (*get_sqi_max)(struct phy_device *);\n};\n\nstruct phy_tdr_config {\n\tu32 first;\n\tu32 last;\n\tu32 step;\n\ts8 pair;\n};\n\nstruct device_connection {\n\tstruct fwnode_handle *fwnode;\n\tconst char *endpoint[2];\n\tconst char *id;\n\tstruct list_head list;\n};\n\ntypedef void * (*devcon_match_fn_t)(struct device_connection *, int, void *);\n\nstruct software_node;\n\nstruct software_node_ref_args {\n\tconst struct software_node *node;\n\tunsigned int nargs;\n\tu64 args[8];\n};\n\nstruct software_node {\n\tconst char *name;\n\tconst struct software_node *parent;\n\tconst struct property_entry *properties;\n};\n\nstruct swnode {\n\tint id;\n\tstruct kobject kobj;\n\tstruct fwnode_handle fwnode;\n\tconst struct software_node *node;\n\tstruct ida child_ids;\n\tstruct list_head entry;\n\tstruct list_head children;\n\tstruct swnode *parent;\n\tunsigned int allocated: 1;\n};\n\nstruct req {\n\tstruct req *next;\n\tstruct completion done;\n\tint err;\n\tconst char *name;\n\tumode_t mode;\n\tkuid_t uid;\n\tkgid_t gid;\n\tstruct device *dev;\n};\n\ntypedef int (*pm_callback_t)(struct device *);\n\nstruct pm_clk_notifier_block {\n\tstruct notifier_block nb;\n\tstruct dev_pm_domain *pm_domain;\n\tchar *con_ids[0];\n};\n\nenum pce_status {\n\tPCE_STATUS_NONE = 0,\n\tPCE_STATUS_ACQUIRED = 1,\n\tPCE_STATUS_ENABLED = 2,\n\tPCE_STATUS_ERROR = 3,\n};\n\nstruct pm_clock_entry {\n\tstruct list_head node;\n\tchar *con_id;\n\tstruct clk *clk;\n\tenum pce_status status;\n};\n\nenum fw_opt {\n\tFW_OPT_UEVENT = 1,\n\tFW_OPT_NOWAIT = 2,\n\tFW_OPT_USERHELPER = 4,\n\tFW_OPT_NO_WARN = 8,\n\tFW_OPT_NOCACHE = 16,\n\tFW_OPT_NOFALLBACK_SYSFS = 32,\n\tFW_OPT_FALLBACK_PLATFORM = 64,\n};\n\nenum fw_status {\n\tFW_STATUS_UNKNOWN = 0,\n\tFW_STATUS_LOADING = 1,\n\tFW_STATUS_DONE = 2,\n\tFW_STATUS_ABORTED = 3,\n};\n\nstruct fw_state {\n\tstruct completion completion;\n\tenum fw_status status;\n};\n\nstruct firmware_cache;\n\nstruct fw_priv {\n\tstruct kref ref;\n\tstruct list_head list;\n\tstruct firmware_cache *fwc;\n\tstruct fw_state fw_st;\n\tvoid *data;\n\tsize_t size;\n\tsize_t allocated_size;\n\tconst char *fw_name;\n};\n\nstruct firmware_cache {\n\tspinlock_t lock;\n\tstruct list_head head;\n\tint state;\n\tspinlock_t name_lock;\n\tstruct list_head fw_names;\n\tstruct delayed_work work;\n\tstruct notifier_block pm_notify;\n};\n\nstruct fw_cache_entry {\n\tstruct list_head list;\n\tconst char *name;\n};\n\nstruct fw_name_devm {\n\tlong unsigned int magic;\n\tconst char *name;\n};\n\nstruct firmware_work {\n\tstruct work_struct work;\n\tstruct module *module;\n\tconst char *name;\n\tstruct device *device;\n\tvoid *context;\n\tvoid (*cont)(const struct firmware *, void *);\n\tu32 opt_flags;\n};\n\ntypedef void (*node_registration_func_t)(struct node *);\n\nstruct node_access_nodes {\n\tstruct device dev;\n\tstruct list_head list_node;\n\tunsigned int access;\n};\n\nstruct node_attr {\n\tstruct device_attribute attr;\n\tenum node_states state;\n};\n\nenum regcache_type {\n\tREGCACHE_NONE = 0,\n\tREGCACHE_RBTREE = 1,\n\tREGCACHE_COMPRESSED = 2,\n\tREGCACHE_FLAT = 3,\n};\n\nstruct reg_default {\n\tunsigned int reg;\n\tunsigned int def;\n};\n\nstruct reg_sequence {\n\tunsigned int reg;\n\tunsigned int def;\n\tunsigned int delay_us;\n};\n\nenum regmap_endian {\n\tREGMAP_ENDIAN_DEFAULT = 0,\n\tREGMAP_ENDIAN_BIG = 1,\n\tREGMAP_ENDIAN_LITTLE = 2,\n\tREGMAP_ENDIAN_NATIVE = 3,\n};\n\nstruct regmap_range {\n\tunsigned int range_min;\n\tunsigned int range_max;\n};\n\nstruct regmap_access_table {\n\tconst struct regmap_range *yes_ranges;\n\tunsigned int n_yes_ranges;\n\tconst struct regmap_range *no_ranges;\n\tunsigned int n_no_ranges;\n};\n\ntypedef void (*regmap_lock)(void *);\n\ntypedef void (*regmap_unlock)(void *);\n\nstruct regmap_range_cfg;\n\nstruct regmap_config {\n\tconst char *name;\n\tint reg_bits;\n\tint reg_stride;\n\tint pad_bits;\n\tint val_bits;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tbool disable_locking;\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tbool fast_io;\n\tunsigned int max_register;\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tconst struct reg_default *reg_defaults;\n\tunsigned int num_reg_defaults;\n\tenum regcache_type cache_type;\n\tconst void *reg_defaults_raw;\n\tunsigned int num_reg_defaults_raw;\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tbool zero_flag_mask;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool can_multi_write;\n\tenum regmap_endian reg_format_endian;\n\tenum regmap_endian val_format_endian;\n\tconst struct regmap_range_cfg *ranges;\n\tunsigned int num_ranges;\n\tbool use_hwlock;\n\tunsigned int hwlock_id;\n\tunsigned int hwlock_mode;\n};\n\nstruct regmap_range_cfg {\n\tconst char *name;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\ntypedef int (*regmap_hw_write)(void *, const void *, size_t);\n\ntypedef int (*regmap_hw_gather_write)(void *, const void *, size_t, const void *, size_t);\n\nstruct regmap_async;\n\ntypedef int (*regmap_hw_async_write)(void *, const void *, size_t, const void *, size_t, struct regmap_async *);\n\nstruct regmap;\n\nstruct regmap_async {\n\tstruct list_head list;\n\tstruct regmap *map;\n\tvoid *work_buf;\n};\n\ntypedef int (*regmap_hw_read)(void *, const void *, size_t, void *, size_t);\n\ntypedef int (*regmap_hw_reg_read)(void *, unsigned int, unsigned int *);\n\ntypedef int (*regmap_hw_reg_write)(void *, unsigned int, unsigned int);\n\ntypedef int (*regmap_hw_reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\ntypedef struct regmap_async * (*regmap_hw_async_alloc)();\n\ntypedef void (*regmap_hw_free_context)(void *);\n\nstruct regmap_bus {\n\tbool fast_io;\n\tregmap_hw_write write;\n\tregmap_hw_gather_write gather_write;\n\tregmap_hw_async_write async_write;\n\tregmap_hw_reg_write reg_write;\n\tregmap_hw_reg_update_bits reg_update_bits;\n\tregmap_hw_read read;\n\tregmap_hw_reg_read reg_read;\n\tregmap_hw_free_context free_context;\n\tregmap_hw_async_alloc async_alloc;\n\tu8 read_flag_mask;\n\tenum regmap_endian reg_format_endian_default;\n\tenum regmap_endian val_format_endian_default;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n};\n\nstruct reg_field {\n\tunsigned int reg;\n\tunsigned int lsb;\n\tunsigned int msb;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct regmap_format {\n\tsize_t buf_size;\n\tsize_t reg_bytes;\n\tsize_t pad_bytes;\n\tsize_t val_bytes;\n\tvoid (*format_write)(struct regmap *, unsigned int, unsigned int);\n\tvoid (*format_reg)(void *, unsigned int, unsigned int);\n\tvoid (*format_val)(void *, unsigned int, unsigned int);\n\tunsigned int (*parse_val)(const void *);\n\tvoid (*parse_inplace)(void *);\n};\n\nstruct hwspinlock;\n\nstruct regcache_ops;\n\nstruct regmap {\n\tunion {\n\t\tstruct mutex mutex;\n\t\tstruct {\n\t\t\tspinlock_t spinlock;\n\t\t\tlong unsigned int spinlock_flags;\n\t\t};\n\t};\n\tregmap_lock lock;\n\tregmap_unlock unlock;\n\tvoid *lock_arg;\n\tgfp_t alloc_flags;\n\tstruct device *dev;\n\tvoid *work_buf;\n\tstruct regmap_format format;\n\tconst struct regmap_bus *bus;\n\tvoid *bus_context;\n\tconst char *name;\n\tbool async;\n\tspinlock_t async_lock;\n\twait_queue_head_t async_waitq;\n\tstruct list_head async_list;\n\tstruct list_head async_free;\n\tint async_ret;\n\tbool debugfs_disable;\n\tstruct dentry *debugfs;\n\tconst char *debugfs_name;\n\tunsigned int debugfs_reg_len;\n\tunsigned int debugfs_val_len;\n\tunsigned int debugfs_tot_len;\n\tstruct list_head debugfs_off_cache;\n\tstruct mutex cache_lock;\n\tunsigned int max_register;\n\tbool (*writeable_reg)(struct device *, unsigned int);\n\tbool (*readable_reg)(struct device *, unsigned int);\n\tbool (*volatile_reg)(struct device *, unsigned int);\n\tbool (*precious_reg)(struct device *, unsigned int);\n\tbool (*writeable_noinc_reg)(struct device *, unsigned int);\n\tbool (*readable_noinc_reg)(struct device *, unsigned int);\n\tconst struct regmap_access_table *wr_table;\n\tconst struct regmap_access_table *rd_table;\n\tconst struct regmap_access_table *volatile_table;\n\tconst struct regmap_access_table *precious_table;\n\tconst struct regmap_access_table *wr_noinc_table;\n\tconst struct regmap_access_table *rd_noinc_table;\n\tint (*reg_read)(void *, unsigned int, unsigned int *);\n\tint (*reg_write)(void *, unsigned int, unsigned int);\n\tint (*reg_update_bits)(void *, unsigned int, unsigned int, unsigned int);\n\tbool defer_caching;\n\tlong unsigned int read_flag_mask;\n\tlong unsigned int write_flag_mask;\n\tint reg_shift;\n\tint reg_stride;\n\tint reg_stride_order;\n\tconst struct regcache_ops *cache_ops;\n\tenum regcache_type cache_type;\n\tunsigned int cache_size_raw;\n\tunsigned int cache_word_size;\n\tunsigned int num_reg_defaults;\n\tunsigned int num_reg_defaults_raw;\n\tbool cache_only;\n\tbool cache_bypass;\n\tbool cache_free;\n\tstruct reg_default *reg_defaults;\n\tconst void *reg_defaults_raw;\n\tvoid *cache;\n\tbool cache_dirty;\n\tbool no_sync_defaults;\n\tstruct reg_sequence *patch;\n\tint patch_regs;\n\tbool use_single_read;\n\tbool use_single_write;\n\tbool can_multi_write;\n\tsize_t max_raw_read;\n\tsize_t max_raw_write;\n\tstruct rb_root range_tree;\n\tvoid *selector_work_buf;\n\tstruct hwspinlock *hwlock;\n};\n\nstruct regcache_ops {\n\tconst char *name;\n\tenum regcache_type type;\n\tint (*init)(struct regmap *);\n\tint (*exit)(struct regmap *);\n\tvoid (*debugfs_init)(struct regmap *);\n\tint (*read)(struct regmap *, unsigned int, unsigned int *);\n\tint (*write)(struct regmap *, unsigned int, unsigned int);\n\tint (*sync)(struct regmap *, unsigned int, unsigned int);\n\tint (*drop)(struct regmap *, unsigned int, unsigned int);\n};\n\nstruct regmap_range_node {\n\tstruct rb_node node;\n\tconst char *name;\n\tstruct regmap *map;\n\tunsigned int range_min;\n\tunsigned int range_max;\n\tunsigned int selector_reg;\n\tunsigned int selector_mask;\n\tint selector_shift;\n\tunsigned int window_start;\n\tunsigned int window_len;\n};\n\nstruct regmap_field {\n\tstruct regmap *regmap;\n\tunsigned int mask;\n\tunsigned int shift;\n\tunsigned int reg;\n\tunsigned int id_size;\n\tunsigned int id_offset;\n};\n\nstruct trace_event_raw_regmap_reg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tunsigned int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_block {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int reg;\n\tint count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regcache_sync {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_status;\n\tu32 __data_loc_type;\n\tint type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_bool {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tint flag;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regmap_async {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_regcache_drop_region {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int from;\n\tunsigned int to;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_regmap_reg {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_regmap_block {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_regcache_sync {\n\tu32 name;\n\tu32 status;\n\tu32 type;\n};\n\nstruct trace_event_data_offsets_regmap_bool {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_regmap_async {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_regcache_drop_region {\n\tu32 name;\n};\n\ntypedef void (*btf_trace_regmap_reg_write)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_reg_read)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_reg_read_cache)(void *, struct regmap *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_regmap_hw_read_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_read_done)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_write_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_hw_write_done)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regcache_sync)(void *, struct regmap *, const char *, const char *);\n\ntypedef void (*btf_trace_regmap_cache_only)(void *, struct regmap *, bool);\n\ntypedef void (*btf_trace_regmap_cache_bypass)(void *, struct regmap *, bool);\n\ntypedef void (*btf_trace_regmap_async_write_start)(void *, struct regmap *, unsigned int, int);\n\ntypedef void (*btf_trace_regmap_async_io_complete)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_complete_start)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regmap_async_complete_done)(void *, struct regmap *);\n\ntypedef void (*btf_trace_regcache_drop_region)(void *, struct regmap *, unsigned int, unsigned int);\n\nstruct regcache_rbtree_node {\n\tvoid *block;\n\tlong int *cache_present;\n\tunsigned int base_reg;\n\tunsigned int blklen;\n\tstruct rb_node node;\n};\n\nstruct regcache_rbtree_ctx {\n\tstruct rb_root root;\n\tstruct regcache_rbtree_node *cached_rbnode;\n};\n\nstruct regmap_debugfs_off_cache {\n\tstruct list_head list;\n\toff_t min;\n\toff_t max;\n\tunsigned int base_reg;\n\tunsigned int max_reg;\n};\n\nstruct regmap_debugfs_node {\n\tstruct regmap *map;\n\tconst char *name;\n\tstruct list_head link;\n};\n\ntypedef void (*irq_write_msi_msg_t)(struct msi_desc *, struct msi_msg *);\n\nstruct platform_msi_priv_data {\n\tstruct device *dev;\n\tvoid *host_data;\n\tmsi_alloc_info_t arg;\n\tirq_write_msi_msg_t write_msg;\n\tint devid;\n};\n\ntypedef long unsigned int __kernel_old_dev_t;\n\nenum {\n\tLO_FLAGS_READ_ONLY = 1,\n\tLO_FLAGS_AUTOCLEAR = 4,\n\tLO_FLAGS_PARTSCAN = 8,\n\tLO_FLAGS_DIRECT_IO = 16,\n};\n\nstruct loop_info {\n\tint lo_number;\n\t__kernel_old_dev_t lo_device;\n\tlong unsigned int lo_inode;\n\t__kernel_old_dev_t lo_rdevice;\n\tint lo_offset;\n\tint lo_encrypt_type;\n\tint lo_encrypt_key_size;\n\tint lo_flags;\n\tchar lo_name[64];\n\tunsigned char lo_encrypt_key[32];\n\tlong unsigned int lo_init[2];\n\tchar reserved[4];\n};\n\nstruct loop_info64 {\n\t__u64 lo_device;\n\t__u64 lo_inode;\n\t__u64 lo_rdevice;\n\t__u64 lo_offset;\n\t__u64 lo_sizelimit;\n\t__u32 lo_number;\n\t__u32 lo_encrypt_type;\n\t__u32 lo_encrypt_key_size;\n\t__u32 lo_flags;\n\t__u8 lo_file_name[64];\n\t__u8 lo_crypt_name[64];\n\t__u8 lo_encrypt_key[32];\n\t__u64 lo_init[2];\n};\n\nstruct loop_config {\n\t__u32 fd;\n\t__u32 block_size;\n\tstruct loop_info64 info;\n\t__u64 __reserved[8];\n};\n\nenum {\n\tLo_unbound = 0,\n\tLo_bound = 1,\n\tLo_rundown = 2,\n};\n\nstruct loop_func_table;\n\nstruct loop_device {\n\tint lo_number;\n\tatomic_t lo_refcnt;\n\tloff_t lo_offset;\n\tloff_t lo_sizelimit;\n\tint lo_flags;\n\tint (*transfer)(struct loop_device *, int, struct page *, unsigned int, struct page *, unsigned int, int, sector_t);\n\tchar lo_file_name[64];\n\tchar lo_crypt_name[64];\n\tchar lo_encrypt_key[32];\n\tint lo_encrypt_key_size;\n\tstruct loop_func_table *lo_encryption;\n\t__u32 lo_init[2];\n\tkuid_t lo_key_owner;\n\tint (*ioctl)(struct loop_device *, int, long unsigned int);\n\tstruct file *lo_backing_file;\n\tstruct block_device *lo_device;\n\tvoid *key_data;\n\tgfp_t old_gfp_mask;\n\tspinlock_t lo_lock;\n\tint lo_state;\n\tstruct kthread_worker worker;\n\tstruct task_struct *worker_task;\n\tbool use_dio;\n\tbool sysfs_inited;\n\tstruct request_queue *lo_queue;\n\tstruct blk_mq_tag_set tag_set;\n\tstruct gendisk *lo_disk;\n};\n\nstruct loop_func_table {\n\tint number;\n\tint (*transfer)(struct loop_device *, int, struct page *, unsigned int, struct page *, unsigned int, int, sector_t);\n\tint (*init)(struct loop_device *, const struct loop_info64 *);\n\tint (*release)(struct loop_device *);\n\tint (*ioctl)(struct loop_device *, int, long unsigned int);\n\tstruct module *owner;\n};\n\nstruct loop_cmd {\n\tstruct kthread_work work;\n\tbool use_aio;\n\tatomic_t ref;\n\tlong int ret;\n\tstruct kiocb iocb;\n\tstruct bio_vec *bvec;\n\tstruct cgroup_subsys_state *css;\n};\n\nstruct compat_loop_info {\n\tcompat_int_t lo_number;\n\tcompat_dev_t lo_device;\n\tcompat_ulong_t lo_inode;\n\tcompat_dev_t lo_rdevice;\n\tcompat_int_t lo_offset;\n\tcompat_int_t lo_encrypt_type;\n\tcompat_int_t lo_encrypt_key_size;\n\tcompat_int_t lo_flags;\n\tchar lo_name[64];\n\tunsigned char lo_encrypt_key[32];\n\tcompat_ulong_t lo_init[2];\n\tchar reserved[4];\n};\n\nstruct dma_buf_sync {\n\t__u64 flags;\n};\n\nstruct dma_buf_list {\n\tstruct list_head head;\n\tstruct mutex lock;\n};\n\nstruct trace_event_raw_dma_fence {\n\tstruct trace_entry ent;\n\tu32 __data_loc_driver;\n\tu32 __data_loc_timeline;\n\tunsigned int context;\n\tunsigned int seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_dma_fence {\n\tu32 driver;\n\tu32 timeline;\n};\n\ntypedef void (*btf_trace_dma_fence_emit)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_init)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_destroy)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_enable_signal)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_signaled)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_start)(void *, struct dma_fence *);\n\ntypedef void (*btf_trace_dma_fence_wait_end)(void *, struct dma_fence *);\n\nstruct default_wait_cb {\n\tstruct dma_fence_cb base;\n\tstruct task_struct *task;\n};\n\nstruct dma_fence_array_cb {\n\tstruct dma_fence_cb cb;\n\tstruct dma_fence_array *array;\n};\n\nenum seqno_fence_condition {\n\tSEQNO_FENCE_WAIT_GEQUAL = 0,\n\tSEQNO_FENCE_WAIT_NONZERO = 1,\n};\n\nstruct seqno_fence {\n\tstruct dma_fence base;\n\tconst struct dma_fence_ops *ops;\n\tstruct dma_buf *sync_buf;\n\tuint32_t seqno_ofs;\n\tenum seqno_fence_condition condition;\n};\n\nstruct sync_merge_data {\n\tchar name[32];\n\t__s32 fd2;\n\t__s32 fence;\n\t__u32 flags;\n\t__u32 pad;\n};\n\nstruct sync_fence_info {\n\tchar obj_name[32];\n\tchar driver_name[32];\n\t__s32 status;\n\t__u32 flags;\n\t__u64 timestamp_ns;\n};\n\nstruct sync_file_info {\n\tchar name[32];\n\t__s32 status;\n\t__u32 flags;\n\t__u32 num_fences;\n\t__u32 pad;\n\t__u64 sync_fence_info;\n};\n\ntypedef __u64 blist_flags_t;\n\nenum scsi_device_state {\n\tSDEV_CREATED = 1,\n\tSDEV_RUNNING = 2,\n\tSDEV_CANCEL = 3,\n\tSDEV_DEL = 4,\n\tSDEV_QUIESCE = 5,\n\tSDEV_OFFLINE = 6,\n\tSDEV_TRANSPORT_OFFLINE = 7,\n\tSDEV_BLOCK = 8,\n\tSDEV_CREATED_BLOCK = 9,\n};\n\nstruct scsi_vpd {\n\tstruct callback_head rcu;\n\tint len;\n\tunsigned char data[0];\n};\n\nstruct Scsi_Host;\n\nstruct scsi_target;\n\nstruct scsi_device_handler;\n\nstruct scsi_device {\n\tstruct Scsi_Host *host;\n\tstruct request_queue *request_queue;\n\tstruct list_head siblings;\n\tstruct list_head same_target_siblings;\n\tatomic_t device_busy;\n\tatomic_t device_blocked;\n\tspinlock_t list_lock;\n\tstruct list_head starved_entry;\n\tshort unsigned int queue_depth;\n\tshort unsigned int max_queue_depth;\n\tshort unsigned int last_queue_full_depth;\n\tshort unsigned int last_queue_full_count;\n\tlong unsigned int last_queue_full_time;\n\tlong unsigned int queue_ramp_up_period;\n\tlong unsigned int last_queue_ramp_up;\n\tunsigned int id;\n\tunsigned int channel;\n\tu64 lun;\n\tunsigned int manufacturer;\n\tunsigned int sector_size;\n\tvoid *hostdata;\n\tunsigned char type;\n\tchar scsi_level;\n\tchar inq_periph_qual;\n\tstruct mutex inquiry_mutex;\n\tunsigned char inquiry_len;\n\tunsigned char *inquiry;\n\tconst char *vendor;\n\tconst char *model;\n\tconst char *rev;\n\tstruct scsi_vpd *vpd_pg0;\n\tstruct scsi_vpd *vpd_pg83;\n\tstruct scsi_vpd *vpd_pg80;\n\tstruct scsi_vpd *vpd_pg89;\n\tunsigned char current_tag;\n\tstruct scsi_target *sdev_target;\n\tblist_flags_t sdev_bflags;\n\tunsigned int eh_timeout;\n\tunsigned int removable: 1;\n\tunsigned int changed: 1;\n\tunsigned int busy: 1;\n\tunsigned int lockable: 1;\n\tunsigned int locked: 1;\n\tunsigned int borken: 1;\n\tunsigned int disconnect: 1;\n\tunsigned int soft_reset: 1;\n\tunsigned int sdtr: 1;\n\tunsigned int wdtr: 1;\n\tunsigned int ppr: 1;\n\tunsigned int tagged_supported: 1;\n\tunsigned int simple_tags: 1;\n\tunsigned int was_reset: 1;\n\tunsigned int expecting_cc_ua: 1;\n\tunsigned int use_10_for_rw: 1;\n\tunsigned int use_10_for_ms: 1;\n\tunsigned int set_dbd_for_ms: 1;\n\tunsigned int no_report_opcodes: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int use_16_for_rw: 1;\n\tunsigned int skip_ms_page_8: 1;\n\tunsigned int skip_ms_page_3f: 1;\n\tunsigned int skip_vpd_pages: 1;\n\tunsigned int try_vpd_pages: 1;\n\tunsigned int use_192_bytes_for_3f: 1;\n\tunsigned int no_start_on_add: 1;\n\tunsigned int allow_restart: 1;\n\tunsigned int manage_start_stop: 1;\n\tunsigned int start_stop_pwr_cond: 1;\n\tunsigned int no_uld_attach: 1;\n\tunsigned int select_no_atn: 1;\n\tunsigned int fix_capacity: 1;\n\tunsigned int guess_capacity: 1;\n\tunsigned int retry_hwerror: 1;\n\tunsigned int last_sector_bug: 1;\n\tunsigned int no_read_disc_info: 1;\n\tunsigned int no_read_capacity_16: 1;\n\tunsigned int try_rc_10_first: 1;\n\tunsigned int security_supported: 1;\n\tunsigned int is_visible: 1;\n\tunsigned int wce_default_on: 1;\n\tunsigned int no_dif: 1;\n\tunsigned int broken_fua: 1;\n\tunsigned int lun_in_cdb: 1;\n\tunsigned int unmap_limit_for_ws: 1;\n\tunsigned int rpm_autosuspend: 1;\n\tbool offline_already;\n\tatomic_t disk_events_disable_depth;\n\tlong unsigned int supported_events[1];\n\tlong unsigned int pending_events[1];\n\tstruct list_head event_list;\n\tstruct work_struct event_work;\n\tunsigned int max_device_blocked;\n\tatomic_t iorequest_cnt;\n\tatomic_t iodone_cnt;\n\tatomic_t ioerr_cnt;\n\tstruct device sdev_gendev;\n\tstruct device sdev_dev;\n\tstruct execute_work ew;\n\tstruct work_struct requeue_work;\n\tstruct scsi_device_handler *handler;\n\tvoid *handler_data;\n\tsize_t dma_drain_len;\n\tvoid *dma_drain_buf;\n\tunsigned char access_state;\n\tstruct mutex state_mutex;\n\tenum scsi_device_state sdev_state;\n\tstruct task_struct *quiesced_by;\n\tlong unsigned int sdev_data[0];\n};\n\nenum scsi_host_state {\n\tSHOST_CREATED = 1,\n\tSHOST_RUNNING = 2,\n\tSHOST_CANCEL = 3,\n\tSHOST_DEL = 4,\n\tSHOST_RECOVERY = 5,\n\tSHOST_CANCEL_RECOVERY = 6,\n\tSHOST_DEL_RECOVERY = 7,\n};\n\nstruct scsi_host_template;\n\nstruct scsi_transport_template;\n\nstruct Scsi_Host {\n\tstruct list_head __devices;\n\tstruct list_head __targets;\n\tstruct list_head starved_list;\n\tspinlock_t default_lock;\n\tspinlock_t *host_lock;\n\tstruct mutex scan_mutex;\n\tstruct list_head eh_cmd_q;\n\tstruct task_struct *ehandler;\n\tstruct completion *eh_action;\n\twait_queue_head_t host_wait;\n\tstruct scsi_host_template *hostt;\n\tstruct scsi_transport_template *transportt;\n\tstruct blk_mq_tag_set tag_set;\n\tatomic_t host_blocked;\n\tunsigned int host_failed;\n\tunsigned int host_eh_scheduled;\n\tunsigned int host_no;\n\tint eh_deadline;\n\tlong unsigned int last_reset;\n\tunsigned int max_channel;\n\tunsigned int max_id;\n\tu64 max_lun;\n\tunsigned int unique_id;\n\tshort unsigned int max_cmd_len;\n\tint this_id;\n\tint can_queue;\n\tshort int cmd_per_lun;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int max_segment_size;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tunsigned int nr_hw_queues;\n\tunsigned int active_mode: 2;\n\tunsigned int unchecked_isa_dma: 1;\n\tunsigned int host_self_blocked: 1;\n\tunsigned int reverse_ordering: 1;\n\tunsigned int tmf_in_progress: 1;\n\tunsigned int async_scan: 1;\n\tunsigned int eh_noresume: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int short_inquiry: 1;\n\tunsigned int no_scsi2_lun_in_cdb: 1;\n\tchar work_q_name[20];\n\tstruct workqueue_struct *work_q;\n\tstruct workqueue_struct *tmf_work_q;\n\tunsigned int max_host_blocked;\n\tunsigned int prot_capabilities;\n\tunsigned char prot_guard_type;\n\tlong unsigned int base;\n\tlong unsigned int io_port;\n\tunsigned char n_io_port;\n\tunsigned char dma_channel;\n\tunsigned int irq;\n\tenum scsi_host_state shost_state;\n\tstruct device shost_gendev;\n\tstruct device shost_dev;\n\tvoid *shost_data;\n\tstruct device *dma_dev;\n\tlong unsigned int hostdata[0];\n};\n\nenum scsi_target_state {\n\tSTARGET_CREATED = 1,\n\tSTARGET_RUNNING = 2,\n\tSTARGET_REMOVE = 3,\n\tSTARGET_CREATED_REMOVE = 4,\n\tSTARGET_DEL = 5,\n};\n\nstruct scsi_target {\n\tstruct scsi_device *starget_sdev_user;\n\tstruct list_head siblings;\n\tstruct list_head devices;\n\tstruct device dev;\n\tstruct kref reap_ref;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int create: 1;\n\tunsigned int single_lun: 1;\n\tunsigned int pdt_1f_for_no_lun: 1;\n\tunsigned int no_report_luns: 1;\n\tunsigned int expecting_lun_change: 1;\n\tatomic_t target_busy;\n\tatomic_t target_blocked;\n\tunsigned int can_queue;\n\tunsigned int max_target_blocked;\n\tchar scsi_level;\n\tenum scsi_target_state state;\n\tvoid *hostdata;\n\tlong unsigned int starget_data[0];\n};\n\nstruct scsi_data_buffer {\n\tstruct sg_table table;\n\tunsigned int length;\n};\n\nstruct scsi_pointer {\n\tchar *ptr;\n\tint this_residual;\n\tstruct scatterlist *buffer;\n\tint buffers_residual;\n\tdma_addr_t dma_handle;\n\tvolatile int Status;\n\tvolatile int Message;\n\tvolatile int have_data_in;\n\tvolatile int sent_command;\n\tvolatile int phase;\n};\n\nstruct scsi_cmnd {\n\tstruct scsi_request req;\n\tstruct scsi_device *device;\n\tstruct list_head eh_entry;\n\tstruct delayed_work abort_work;\n\tstruct callback_head rcu;\n\tint eh_eflags;\n\tlong unsigned int jiffies_at_alloc;\n\tint retries;\n\tint allowed;\n\tunsigned char prot_op;\n\tunsigned char prot_type;\n\tunsigned char prot_flags;\n\tshort unsigned int cmd_len;\n\tenum dma_data_direction sc_data_direction;\n\tunsigned char *cmnd;\n\tstruct scsi_data_buffer sdb;\n\tstruct scsi_data_buffer *prot_sdb;\n\tunsigned int underflow;\n\tunsigned int transfersize;\n\tstruct request *request;\n\tunsigned char *sense_buffer;\n\tvoid (*scsi_done)(struct scsi_cmnd *);\n\tstruct scsi_pointer SCp;\n\tunsigned char *host_scribble;\n\tint result;\n\tint flags;\n\tlong unsigned int state;\n\tunsigned char tag;\n\tunsigned int extra_len;\n};\n\nenum scsi_prot_operations {\n\tSCSI_PROT_NORMAL = 0,\n\tSCSI_PROT_READ_INSERT = 1,\n\tSCSI_PROT_WRITE_STRIP = 2,\n\tSCSI_PROT_READ_STRIP = 3,\n\tSCSI_PROT_WRITE_INSERT = 4,\n\tSCSI_PROT_READ_PASS = 5,\n\tSCSI_PROT_WRITE_PASS = 6,\n};\n\nstruct scsi_driver {\n\tstruct device_driver gendrv;\n\tvoid (*rescan)(struct device *);\n\tblk_status_t (*init_command)(struct scsi_cmnd *);\n\tvoid (*uninit_command)(struct scsi_cmnd *);\n\tint (*done)(struct scsi_cmnd *);\n\tint (*eh_action)(struct scsi_cmnd *, int);\n\tvoid (*eh_reset)(struct scsi_cmnd *);\n};\n\nstruct scsi_host_cmd_pool;\n\nstruct scsi_host_template {\n\tstruct module *module;\n\tconst char *name;\n\tconst char * (*info)(struct Scsi_Host *);\n\tint (*ioctl)(struct scsi_device *, unsigned int, void *);\n\tint (*compat_ioctl)(struct scsi_device *, unsigned int, void *);\n\tint (*init_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*exit_cmd_priv)(struct Scsi_Host *, struct scsi_cmnd *);\n\tint (*queuecommand)(struct Scsi_Host *, struct scsi_cmnd *);\n\tvoid (*commit_rqs)(struct Scsi_Host *, u16);\n\tint (*eh_abort_handler)(struct scsi_cmnd *);\n\tint (*eh_device_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_target_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_bus_reset_handler)(struct scsi_cmnd *);\n\tint (*eh_host_reset_handler)(struct scsi_cmnd *);\n\tint (*slave_alloc)(struct scsi_device *);\n\tint (*slave_configure)(struct scsi_device *);\n\tvoid (*slave_destroy)(struct scsi_device *);\n\tint (*target_alloc)(struct scsi_target *);\n\tvoid (*target_destroy)(struct scsi_target *);\n\tint (*scan_finished)(struct Scsi_Host *, long unsigned int);\n\tvoid (*scan_start)(struct Scsi_Host *);\n\tint (*change_queue_depth)(struct scsi_device *, int);\n\tint (*map_queues)(struct Scsi_Host *);\n\tbool (*dma_need_drain)(struct request *);\n\tint (*bios_param)(struct scsi_device *, struct block_device *, sector_t, int *);\n\tvoid (*unlock_native_capacity)(struct scsi_device *);\n\tint (*show_info)(struct seq_file *, struct Scsi_Host *);\n\tint (*write_info)(struct Scsi_Host *, char *, int);\n\tenum blk_eh_timer_return (*eh_timed_out)(struct scsi_cmnd *);\n\tint (*host_reset)(struct Scsi_Host *, int);\n\tconst char *proc_name;\n\tstruct proc_dir_entry *proc_dir;\n\tint can_queue;\n\tint this_id;\n\tshort unsigned int sg_tablesize;\n\tshort unsigned int sg_prot_tablesize;\n\tunsigned int max_sectors;\n\tunsigned int max_segment_size;\n\tlong unsigned int dma_boundary;\n\tlong unsigned int virt_boundary_mask;\n\tshort int cmd_per_lun;\n\tunsigned char present;\n\tint tag_alloc_policy;\n\tunsigned int track_queue_depth: 1;\n\tunsigned int supported_mode: 2;\n\tunsigned int unchecked_isa_dma: 1;\n\tunsigned int emulated: 1;\n\tunsigned int skip_settle_delay: 1;\n\tunsigned int no_write_same: 1;\n\tunsigned int max_host_blocked;\n\tstruct device_attribute **shost_attrs;\n\tstruct device_attribute **sdev_attrs;\n\tconst struct attribute_group **sdev_groups;\n\tu64 vendor_id;\n\tunsigned int cmd_size;\n\tstruct scsi_host_cmd_pool *cmd_pool;\n\tint rpm_autosuspend_delay;\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_start {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_dispatch_cmd_error {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint rtn;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_cmd_done_timeout_template {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tunsigned int channel;\n\tunsigned int id;\n\tunsigned int lun;\n\tint result;\n\tunsigned int opcode;\n\tunsigned int cmd_len;\n\tunsigned int data_sglen;\n\tunsigned int prot_sglen;\n\tunsigned char prot_op;\n\tu32 __data_loc_cmnd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_scsi_eh_wakeup {\n\tstruct trace_entry ent;\n\tunsigned int host_no;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_start {\n\tu32 cmnd;\n};\n\nstruct trace_event_data_offsets_scsi_dispatch_cmd_error {\n\tu32 cmnd;\n};\n\nstruct trace_event_data_offsets_scsi_cmd_done_timeout_template {\n\tu32 cmnd;\n};\n\nstruct trace_event_data_offsets_scsi_eh_wakeup {};\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_start)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_error)(void *, struct scsi_cmnd *, int);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_done)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_dispatch_cmd_timeout)(void *, struct scsi_cmnd *);\n\ntypedef void (*btf_trace_scsi_eh_wakeup)(void *, struct Scsi_Host *);\n\nstruct scsi_transport_template {\n\tstruct transport_container host_attrs;\n\tstruct transport_container target_attrs;\n\tstruct transport_container device_attrs;\n\tint (*user_scan)(struct Scsi_Host *, uint, uint, u64);\n\tint device_size;\n\tint device_private_offset;\n\tint target_size;\n\tint target_private_offset;\n\tint host_size;\n\tunsigned int create_work_queue: 1;\n\tvoid (*eh_strategy_handler)(struct Scsi_Host *);\n};\n\nstruct scsi_host_busy_iter_data {\n\tbool (*fn)(struct scsi_cmnd *, void *, bool);\n\tvoid *priv;\n};\n\nstruct scsi_idlun {\n\t__u32 dev_id;\n\t__u32 host_unique_id;\n};\n\ntypedef void (*activate_complete)(void *, int);\n\nstruct scsi_device_handler {\n\tstruct list_head list;\n\tstruct module *module;\n\tconst char *name;\n\tint (*check_sense)(struct scsi_device *, struct scsi_sense_hdr *);\n\tint (*attach)(struct scsi_device *);\n\tvoid (*detach)(struct scsi_device *);\n\tint (*activate)(struct scsi_device *, activate_complete, void *);\n\tblk_status_t (*prep_fn)(struct scsi_device *, struct request *);\n\tint (*set_params)(struct scsi_device *, const char *);\n\tvoid (*rescan)(struct scsi_device *);\n};\n\nstruct scsi_eh_save {\n\tint result;\n\tunsigned int resid_len;\n\tint eh_eflags;\n\tenum dma_data_direction data_direction;\n\tunsigned int underflow;\n\tunsigned char cmd_len;\n\tunsigned char prot_op;\n\tunsigned char *cmnd;\n\tstruct scsi_data_buffer sdb;\n\tunsigned char eh_cmnd[16];\n\tstruct scatterlist sense_sgl;\n};\n\nstruct scsi_varlen_cdb_hdr {\n\t__u8 opcode;\n\t__u8 control;\n\t__u8 misc[5];\n\t__u8 additional_cdb_length;\n\t__be16 service_action;\n};\n\nstruct scsi_mode_data {\n\t__u32 length;\n\t__u16 block_descriptor_length;\n\t__u8 medium_type;\n\t__u8 device_specific;\n\t__u8 header_length;\n\t__u8 longlba: 1;\n};\n\nstruct scsi_event {\n\tenum scsi_device_event evt_type;\n\tstruct list_head node;\n};\n\nenum scsi_host_prot_capabilities {\n\tSHOST_DIF_TYPE1_PROTECTION = 1,\n\tSHOST_DIF_TYPE2_PROTECTION = 2,\n\tSHOST_DIF_TYPE3_PROTECTION = 4,\n\tSHOST_DIX_TYPE0_PROTECTION = 8,\n\tSHOST_DIX_TYPE1_PROTECTION = 16,\n\tSHOST_DIX_TYPE2_PROTECTION = 32,\n\tSHOST_DIX_TYPE3_PROTECTION = 64,\n};\n\nenum {\n\tACTION_FAIL = 0,\n\tACTION_REPREP = 1,\n\tACTION_RETRY = 2,\n\tACTION_DELAYED_RETRY = 3,\n};\n\nstruct value_name_pair;\n\nstruct sa_name_list {\n\tint opcode;\n\tconst struct value_name_pair *arr;\n\tint arr_sz;\n};\n\nstruct value_name_pair {\n\tint value;\n\tconst char *name;\n};\n\nstruct error_info {\n\tshort unsigned int code12;\n\tshort unsigned int size;\n};\n\nstruct error_info2 {\n\tunsigned char code1;\n\tunsigned char code2_min;\n\tunsigned char code2_max;\n\tconst char *str;\n\tconst char *fmt;\n};\n\nstruct scsi_lun {\n\t__u8 scsi_lun[8];\n};\n\nenum scsi_timeouts {\n\tSCSI_DEFAULT_EH_TIMEOUT = 10000,\n};\n\nenum scsi_scan_mode {\n\tSCSI_SCAN_INITIAL = 0,\n\tSCSI_SCAN_RESCAN = 1,\n\tSCSI_SCAN_MANUAL = 2,\n};\n\nstruct async_scan_data {\n\tstruct list_head list;\n\tstruct Scsi_Host *shost;\n\tstruct completion prev_finished;\n};\n\nenum scsi_devinfo_key {\n\tSCSI_DEVINFO_GLOBAL = 0,\n\tSCSI_DEVINFO_SPI = 1,\n};\n\nstruct scsi_dev_info_list {\n\tstruct list_head dev_info_list;\n\tchar vendor[8];\n\tchar model[16];\n\tblist_flags_t flags;\n\tunsigned int compatible;\n};\n\nstruct scsi_dev_info_list_table {\n\tstruct list_head node;\n\tstruct list_head scsi_dev_info_list;\n\tconst char *name;\n\tint key;\n};\n\nstruct double_list {\n\tstruct list_head *top;\n\tstruct list_head *bottom;\n};\n\nstruct spi_transport_attrs {\n\tint period;\n\tint min_period;\n\tint offset;\n\tint max_offset;\n\tunsigned int width: 1;\n\tunsigned int max_width: 1;\n\tunsigned int iu: 1;\n\tunsigned int max_iu: 1;\n\tunsigned int dt: 1;\n\tunsigned int qas: 1;\n\tunsigned int max_qas: 1;\n\tunsigned int wr_flow: 1;\n\tunsigned int rd_strm: 1;\n\tunsigned int rti: 1;\n\tunsigned int pcomp_en: 1;\n\tunsigned int hold_mcs: 1;\n\tunsigned int initial_dv: 1;\n\tlong unsigned int flags;\n\tunsigned int support_sync: 1;\n\tunsigned int support_wide: 1;\n\tunsigned int support_dt: 1;\n\tunsigned int support_dt_only;\n\tunsigned int support_ius;\n\tunsigned int support_qas;\n\tunsigned int dv_pending: 1;\n\tunsigned int dv_in_progress: 1;\n\tstruct mutex dv_mutex;\n};\n\nenum spi_signal_type {\n\tSPI_SIGNAL_UNKNOWN = 1,\n\tSPI_SIGNAL_SE = 2,\n\tSPI_SIGNAL_LVD = 3,\n\tSPI_SIGNAL_HVD = 4,\n};\n\nstruct spi_host_attrs {\n\tenum spi_signal_type signalling;\n};\n\nstruct spi_function_template {\n\tvoid (*get_period)(struct scsi_target *);\n\tvoid (*set_period)(struct scsi_target *, int);\n\tvoid (*get_offset)(struct scsi_target *);\n\tvoid (*set_offset)(struct scsi_target *, int);\n\tvoid (*get_width)(struct scsi_target *);\n\tvoid (*set_width)(struct scsi_target *, int);\n\tvoid (*get_iu)(struct scsi_target *);\n\tvoid (*set_iu)(struct scsi_target *, int);\n\tvoid (*get_dt)(struct scsi_target *);\n\tvoid (*set_dt)(struct scsi_target *, int);\n\tvoid (*get_qas)(struct scsi_target *);\n\tvoid (*set_qas)(struct scsi_target *, int);\n\tvoid (*get_wr_flow)(struct scsi_target *);\n\tvoid (*set_wr_flow)(struct scsi_target *, int);\n\tvoid (*get_rd_strm)(struct scsi_target *);\n\tvoid (*set_rd_strm)(struct scsi_target *, int);\n\tvoid (*get_rti)(struct scsi_target *);\n\tvoid (*set_rti)(struct scsi_target *, int);\n\tvoid (*get_pcomp_en)(struct scsi_target *);\n\tvoid (*set_pcomp_en)(struct scsi_target *, int);\n\tvoid (*get_hold_mcs)(struct scsi_target *);\n\tvoid (*set_hold_mcs)(struct scsi_target *, int);\n\tvoid (*get_signalling)(struct Scsi_Host *);\n\tvoid (*set_signalling)(struct Scsi_Host *, enum spi_signal_type);\n\tint (*deny_binding)(struct scsi_target *);\n\tlong unsigned int show_period: 1;\n\tlong unsigned int show_offset: 1;\n\tlong unsigned int show_width: 1;\n\tlong unsigned int show_iu: 1;\n\tlong unsigned int show_dt: 1;\n\tlong unsigned int show_qas: 1;\n\tlong unsigned int show_wr_flow: 1;\n\tlong unsigned int show_rd_strm: 1;\n\tlong unsigned int show_rti: 1;\n\tlong unsigned int show_pcomp_en: 1;\n\tlong unsigned int show_hold_mcs: 1;\n};\n\nenum {\n\tSPI_BLIST_NOIUS = 1,\n};\n\nstruct spi_internal {\n\tstruct scsi_transport_template t;\n\tstruct spi_function_template *f;\n};\n\nenum spi_compare_returns {\n\tSPI_COMPARE_SUCCESS = 0,\n\tSPI_COMPARE_FAILURE = 1,\n\tSPI_COMPARE_SKIP_TEST = 2,\n};\n\nstruct work_queue_wrapper {\n\tstruct work_struct work;\n\tstruct scsi_device *sdev;\n};\n\nenum bip_flags {\n\tBIP_BLOCK_INTEGRITY = 1,\n\tBIP_MAPPED_INTEGRITY = 2,\n\tBIP_CTRL_NOCHECK = 4,\n\tBIP_DISK_NOCHECK = 8,\n\tBIP_IP_CHECKSUM = 16,\n};\n\nenum t10_dif_type {\n\tT10_PI_TYPE0_PROTECTION = 0,\n\tT10_PI_TYPE1_PROTECTION = 1,\n\tT10_PI_TYPE2_PROTECTION = 2,\n\tT10_PI_TYPE3_PROTECTION = 3,\n};\n\nenum scsi_prot_flags {\n\tSCSI_PROT_TRANSFER_PI = 1,\n\tSCSI_PROT_GUARD_CHECK = 2,\n\tSCSI_PROT_REF_CHECK = 4,\n\tSCSI_PROT_REF_INCREMENT = 8,\n\tSCSI_PROT_IP_CHECKSUM = 16,\n};\n\nenum {\n\tSD_EXT_CDB_SIZE = 32,\n\tSD_MEMPOOL_SIZE = 2,\n};\n\nenum {\n\tSD_DEF_XFER_BLOCKS = 65535,\n\tSD_MAX_XFER_BLOCKS = 4294967295,\n\tSD_MAX_WS10_BLOCKS = 65535,\n\tSD_MAX_WS16_BLOCKS = 8388607,\n};\n\nenum {\n\tSD_LBP_FULL = 0,\n\tSD_LBP_UNMAP = 1,\n\tSD_LBP_WS16 = 2,\n\tSD_LBP_WS10 = 3,\n\tSD_LBP_ZERO = 4,\n\tSD_LBP_DISABLE = 5,\n};\n\nenum {\n\tSD_ZERO_WRITE = 0,\n\tSD_ZERO_WS = 1,\n\tSD_ZERO_WS16_UNMAP = 2,\n\tSD_ZERO_WS10_UNMAP = 3,\n};\n\nstruct opal_dev;\n\nstruct scsi_disk {\n\tstruct scsi_driver *driver;\n\tstruct scsi_device *device;\n\tstruct device dev;\n\tstruct gendisk *disk;\n\tstruct opal_dev *opal_dev;\n\tatomic_t openers;\n\tsector_t capacity;\n\tu32 max_xfer_blocks;\n\tu32 opt_xfer_blocks;\n\tu32 max_ws_blocks;\n\tu32 max_unmap_blocks;\n\tu32 unmap_granularity;\n\tu32 unmap_alignment;\n\tu32 index;\n\tunsigned int physical_block_size;\n\tunsigned int max_medium_access_timeouts;\n\tunsigned int medium_access_timed_out;\n\tu8 media_present;\n\tu8 write_prot;\n\tu8 protection_type;\n\tu8 provisioning_mode;\n\tu8 zeroing_mode;\n\tunsigned int ATO: 1;\n\tunsigned int cache_override: 1;\n\tunsigned int WCE: 1;\n\tunsigned int RCD: 1;\n\tunsigned int DPOFUA: 1;\n\tunsigned int first_scan: 1;\n\tunsigned int lbpme: 1;\n\tunsigned int lbprz: 1;\n\tunsigned int lbpu: 1;\n\tunsigned int lbpws: 1;\n\tunsigned int lbpws10: 1;\n\tunsigned int lbpvpd: 1;\n\tunsigned int ws10: 1;\n\tunsigned int ws16: 1;\n\tunsigned int rc_basis: 2;\n\tunsigned int zoned: 2;\n\tunsigned int urswrz: 1;\n\tunsigned int security: 1;\n\tunsigned int ignore_medium_access_errors: 1;\n};\n\nenum {\n\tmechtype_caddy = 0,\n\tmechtype_tray = 1,\n\tmechtype_popup = 2,\n\tmechtype_individual_changer = 4,\n\tmechtype_cartridge_changer = 5,\n};\n\nstruct event_header {\n\t__be16 data_len;\n\t__u8 notification_class: 3;\n\t__u8 reserved1: 4;\n\t__u8 nea: 1;\n\t__u8 supp_event_class;\n};\n\nstruct media_event_desc {\n\t__u8 media_event_code: 4;\n\t__u8 reserved1: 4;\n\t__u8 door_open: 1;\n\t__u8 media_present: 1;\n\t__u8 reserved2: 6;\n\t__u8 start_slot;\n\t__u8 end_slot;\n};\n\nstruct scsi_cd {\n\tstruct scsi_driver *driver;\n\tunsigned int capacity;\n\tstruct scsi_device *device;\n\tunsigned int vendor;\n\tlong unsigned int ms_offset;\n\tunsigned int writeable: 1;\n\tunsigned int use: 1;\n\tunsigned int xa_flag: 1;\n\tunsigned int readcd_known: 1;\n\tunsigned int readcd_cdda: 1;\n\tunsigned int media_present: 1;\n\tint tur_mismatch;\n\tbool tur_changed: 1;\n\tbool get_event_changed: 1;\n\tbool ignore_get_event: 1;\n\tstruct cdrom_device_info cdi;\n\tstruct mutex lock;\n\tstruct kref kref;\n\tstruct gendisk *disk;\n};\n\nstruct cdrom_ti {\n\t__u8 cdti_trk0;\n\t__u8 cdti_ind0;\n\t__u8 cdti_trk1;\n\t__u8 cdti_ind1;\n};\n\nstruct cdrom_tochdr {\n\t__u8 cdth_trk0;\n\t__u8 cdth_trk1;\n};\n\ntypedef struct scsi_cd Scsi_CD;\n\nstruct ccs_modesel_head {\n\t__u8 _r1;\n\t__u8 medium;\n\t__u8 _r2;\n\t__u8 block_desc_length;\n\t__u8 density;\n\t__u8 number_blocks_hi;\n\t__u8 number_blocks_med;\n\t__u8 number_blocks_lo;\n\t__u8 _r3;\n\t__u8 block_length_hi;\n\t__u8 block_length_med;\n\t__u8 block_length_lo;\n};\n\ntypedef struct sg_io_hdr sg_io_hdr_t;\n\nstruct sg_scsi_id {\n\tint host_no;\n\tint channel;\n\tint scsi_id;\n\tint lun;\n\tint scsi_type;\n\tshort int h_cmd_per_lun;\n\tshort int d_queue_depth;\n\tint unused[2];\n};\n\ntypedef struct sg_scsi_id sg_scsi_id_t;\n\nstruct sg_req_info {\n\tchar req_state;\n\tchar orphan;\n\tchar sg_io_owned;\n\tchar problem;\n\tint pack_id;\n\tvoid *usr_ptr;\n\tunsigned int duration;\n\tint unused;\n};\n\ntypedef struct sg_req_info sg_req_info_t;\n\nstruct sg_header {\n\tint pack_len;\n\tint reply_len;\n\tint pack_id;\n\tint result;\n\tunsigned int twelve_byte: 1;\n\tunsigned int target_status: 5;\n\tunsigned int host_status: 8;\n\tunsigned int driver_status: 8;\n\tunsigned int other_flags: 10;\n\tunsigned char sense_buffer[16];\n};\n\nstruct sg_scatter_hold {\n\tshort unsigned int k_use_sg;\n\tunsigned int sglist_len;\n\tunsigned int bufflen;\n\tstruct page **pages;\n\tint page_order;\n\tchar dio_in_use;\n\tunsigned char cmd_opcode;\n};\n\ntypedef struct sg_scatter_hold Sg_scatter_hold;\n\nstruct sg_fd;\n\nstruct sg_request {\n\tstruct list_head entry;\n\tstruct sg_fd *parentfp;\n\tSg_scatter_hold data;\n\tsg_io_hdr_t header;\n\tunsigned char sense_b[96];\n\tchar res_used;\n\tchar orphan;\n\tchar sg_io_owned;\n\tchar done;\n\tstruct request *rq;\n\tstruct bio *bio;\n\tstruct execute_work ew;\n};\n\ntypedef struct sg_request Sg_request;\n\nstruct sg_device;\n\nstruct sg_fd {\n\tstruct list_head sfd_siblings;\n\tstruct sg_device *parentdp;\n\twait_queue_head_t read_wait;\n\trwlock_t rq_list_lock;\n\tstruct mutex f_mutex;\n\tint timeout;\n\tint timeout_user;\n\tSg_scatter_hold reserve;\n\tstruct list_head rq_list;\n\tstruct fasync_struct *async_qp;\n\tSg_request req_arr[16];\n\tchar force_packid;\n\tchar cmd_q;\n\tunsigned char next_cmd_len;\n\tchar keep_orphan;\n\tchar mmap_called;\n\tchar res_in_use;\n\tstruct kref f_ref;\n\tstruct execute_work ew;\n};\n\nstruct sg_device {\n\tstruct scsi_device *device;\n\twait_queue_head_t open_wait;\n\tstruct mutex open_rel_lock;\n\tint sg_tablesize;\n\tu32 index;\n\tstruct list_head sfds;\n\trwlock_t sfd_lock;\n\tatomic_t detaching;\n\tbool exclude;\n\tint open_cnt;\n\tchar sgdebug;\n\tstruct gendisk *disk;\n\tstruct cdev *cdev;\n\tstruct kref d_ref;\n};\n\ntypedef struct sg_fd Sg_fd;\n\ntypedef struct sg_device Sg_device;\n\nstruct compat_sg_req_info {\n\tchar req_state;\n\tchar orphan;\n\tchar sg_io_owned;\n\tchar problem;\n\tint pack_id;\n\tcompat_uptr_t usr_ptr;\n\tunsigned int duration;\n\tint unused;\n};\n\nstruct sg_proc_deviter {\n\tloff_t index;\n\tsize_t max;\n};\n\nenum {\n\tATA_MAX_DEVICES = 2,\n\tATA_MAX_PRD = 256,\n\tATA_SECT_SIZE = 512,\n\tATA_MAX_SECTORS_128 = 128,\n\tATA_MAX_SECTORS = 256,\n\tATA_MAX_SECTORS_1024 = 1024,\n\tATA_MAX_SECTORS_LBA48 = 65535,\n\tATA_MAX_SECTORS_TAPE = 65535,\n\tATA_MAX_TRIM_RNUM = 64,\n\tATA_ID_WORDS = 256,\n\tATA_ID_CONFIG = 0,\n\tATA_ID_CYLS = 1,\n\tATA_ID_HEADS = 3,\n\tATA_ID_SECTORS = 6,\n\tATA_ID_SERNO = 10,\n\tATA_ID_BUF_SIZE = 21,\n\tATA_ID_FW_REV = 23,\n\tATA_ID_PROD = 27,\n\tATA_ID_MAX_MULTSECT = 47,\n\tATA_ID_DWORD_IO = 48,\n\tATA_ID_TRUSTED = 48,\n\tATA_ID_CAPABILITY = 49,\n\tATA_ID_OLD_PIO_MODES = 51,\n\tATA_ID_OLD_DMA_MODES = 52,\n\tATA_ID_FIELD_VALID = 53,\n\tATA_ID_CUR_CYLS = 54,\n\tATA_ID_CUR_HEADS = 55,\n\tATA_ID_CUR_SECTORS = 56,\n\tATA_ID_MULTSECT = 59,\n\tATA_ID_LBA_CAPACITY = 60,\n\tATA_ID_SWDMA_MODES = 62,\n\tATA_ID_MWDMA_MODES = 63,\n\tATA_ID_PIO_MODES = 64,\n\tATA_ID_EIDE_DMA_MIN = 65,\n\tATA_ID_EIDE_DMA_TIME = 66,\n\tATA_ID_EIDE_PIO = 67,\n\tATA_ID_EIDE_PIO_IORDY = 68,\n\tATA_ID_ADDITIONAL_SUPP = 69,\n\tATA_ID_QUEUE_DEPTH = 75,\n\tATA_ID_SATA_CAPABILITY = 76,\n\tATA_ID_SATA_CAPABILITY_2 = 77,\n\tATA_ID_FEATURE_SUPP = 78,\n\tATA_ID_MAJOR_VER = 80,\n\tATA_ID_COMMAND_SET_1 = 82,\n\tATA_ID_COMMAND_SET_2 = 83,\n\tATA_ID_CFSSE = 84,\n\tATA_ID_CFS_ENABLE_1 = 85,\n\tATA_ID_CFS_ENABLE_2 = 86,\n\tATA_ID_CSF_DEFAULT = 87,\n\tATA_ID_UDMA_MODES = 88,\n\tATA_ID_HW_CONFIG = 93,\n\tATA_ID_SPG = 98,\n\tATA_ID_LBA_CAPACITY_2 = 100,\n\tATA_ID_SECTOR_SIZE = 106,\n\tATA_ID_WWN = 108,\n\tATA_ID_LOGICAL_SECTOR_SIZE = 117,\n\tATA_ID_COMMAND_SET_3 = 119,\n\tATA_ID_COMMAND_SET_4 = 120,\n\tATA_ID_LAST_LUN = 126,\n\tATA_ID_DLF = 128,\n\tATA_ID_CSFO = 129,\n\tATA_ID_CFA_POWER = 160,\n\tATA_ID_CFA_KEY_MGMT = 162,\n\tATA_ID_CFA_MODES = 163,\n\tATA_ID_DATA_SET_MGMT = 169,\n\tATA_ID_SCT_CMD_XPORT = 206,\n\tATA_ID_ROT_SPEED = 217,\n\tATA_ID_PIO4 = 2,\n\tATA_ID_SERNO_LEN = 20,\n\tATA_ID_FW_REV_LEN = 8,\n\tATA_ID_PROD_LEN = 40,\n\tATA_ID_WWN_LEN = 8,\n\tATA_PCI_CTL_OFS = 2,\n\tATA_PIO0 = 1,\n\tATA_PIO1 = 3,\n\tATA_PIO2 = 7,\n\tATA_PIO3 = 15,\n\tATA_PIO4 = 31,\n\tATA_PIO5 = 63,\n\tATA_PIO6 = 127,\n\tATA_PIO4_ONLY = 16,\n\tATA_SWDMA0 = 1,\n\tATA_SWDMA1 = 3,\n\tATA_SWDMA2 = 7,\n\tATA_SWDMA2_ONLY = 4,\n\tATA_MWDMA0 = 1,\n\tATA_MWDMA1 = 3,\n\tATA_MWDMA2 = 7,\n\tATA_MWDMA3 = 15,\n\tATA_MWDMA4 = 31,\n\tATA_MWDMA12_ONLY = 6,\n\tATA_MWDMA2_ONLY = 4,\n\tATA_UDMA0 = 1,\n\tATA_UDMA1 = 3,\n\tATA_UDMA2 = 7,\n\tATA_UDMA3 = 15,\n\tATA_UDMA4 = 31,\n\tATA_UDMA5 = 63,\n\tATA_UDMA6 = 127,\n\tATA_UDMA7 = 255,\n\tATA_UDMA24_ONLY = 20,\n\tATA_UDMA_MASK_40C = 7,\n\tATA_PRD_SZ = 8,\n\tATA_PRD_TBL_SZ = 2048,\n\tATA_PRD_EOT = 2147483648,\n\tATA_DMA_TABLE_OFS = 4,\n\tATA_DMA_STATUS = 2,\n\tATA_DMA_CMD = 0,\n\tATA_DMA_WR = 8,\n\tATA_DMA_START = 1,\n\tATA_DMA_INTR = 4,\n\tATA_DMA_ERR = 2,\n\tATA_DMA_ACTIVE = 1,\n\tATA_HOB = 128,\n\tATA_NIEN = 2,\n\tATA_LBA = 64,\n\tATA_DEV1 = 16,\n\tATA_DEVICE_OBS = 160,\n\tATA_DEVCTL_OBS = 8,\n\tATA_BUSY = 128,\n\tATA_DRDY = 64,\n\tATA_DF = 32,\n\tATA_DSC = 16,\n\tATA_DRQ = 8,\n\tATA_CORR = 4,\n\tATA_SENSE = 2,\n\tATA_ERR = 1,\n\tATA_SRST = 4,\n\tATA_ICRC = 128,\n\tATA_BBK = 128,\n\tATA_UNC = 64,\n\tATA_MC = 32,\n\tATA_IDNF = 16,\n\tATA_MCR = 8,\n\tATA_ABORTED = 4,\n\tATA_TRK0NF = 2,\n\tATA_AMNF = 1,\n\tATAPI_LFS = 240,\n\tATAPI_EOM = 2,\n\tATAPI_ILI = 1,\n\tATAPI_IO = 2,\n\tATAPI_COD = 1,\n\tATA_REG_DATA = 0,\n\tATA_REG_ERR = 1,\n\tATA_REG_NSECT = 2,\n\tATA_REG_LBAL = 3,\n\tATA_REG_LBAM = 4,\n\tATA_REG_LBAH = 5,\n\tATA_REG_DEVICE = 6,\n\tATA_REG_STATUS = 7,\n\tATA_REG_FEATURE = 1,\n\tATA_REG_CMD = 7,\n\tATA_REG_BYTEL = 4,\n\tATA_REG_BYTEH = 5,\n\tATA_REG_DEVSEL = 6,\n\tATA_REG_IRQ = 2,\n\tATA_CMD_DEV_RESET = 8,\n\tATA_CMD_CHK_POWER = 229,\n\tATA_CMD_STANDBY = 226,\n\tATA_CMD_IDLE = 227,\n\tATA_CMD_EDD = 144,\n\tATA_CMD_DOWNLOAD_MICRO = 146,\n\tATA_CMD_DOWNLOAD_MICRO_DMA = 147,\n\tATA_CMD_NOP = 0,\n\tATA_CMD_FLUSH = 231,\n\tATA_CMD_FLUSH_EXT = 234,\n\tATA_CMD_ID_ATA = 236,\n\tATA_CMD_ID_ATAPI = 161,\n\tATA_CMD_SERVICE = 162,\n\tATA_CMD_READ = 200,\n\tATA_CMD_READ_EXT = 37,\n\tATA_CMD_READ_QUEUED = 38,\n\tATA_CMD_READ_STREAM_EXT = 43,\n\tATA_CMD_READ_STREAM_DMA_EXT = 42,\n\tATA_CMD_WRITE = 202,\n\tATA_CMD_WRITE_EXT = 53,\n\tATA_CMD_WRITE_QUEUED = 54,\n\tATA_CMD_WRITE_STREAM_EXT = 59,\n\tATA_CMD_WRITE_STREAM_DMA_EXT = 58,\n\tATA_CMD_WRITE_FUA_EXT = 61,\n\tATA_CMD_WRITE_QUEUED_FUA_EXT = 62,\n\tATA_CMD_FPDMA_READ = 96,\n\tATA_CMD_FPDMA_WRITE = 97,\n\tATA_CMD_NCQ_NON_DATA = 99,\n\tATA_CMD_FPDMA_SEND = 100,\n\tATA_CMD_FPDMA_RECV = 101,\n\tATA_CMD_PIO_READ = 32,\n\tATA_CMD_PIO_READ_EXT = 36,\n\tATA_CMD_PIO_WRITE = 48,\n\tATA_CMD_PIO_WRITE_EXT = 52,\n\tATA_CMD_READ_MULTI = 196,\n\tATA_CMD_READ_MULTI_EXT = 41,\n\tATA_CMD_WRITE_MULTI = 197,\n\tATA_CMD_WRITE_MULTI_EXT = 57,\n\tATA_CMD_WRITE_MULTI_FUA_EXT = 206,\n\tATA_CMD_SET_FEATURES = 239,\n\tATA_CMD_SET_MULTI = 198,\n\tATA_CMD_PACKET = 160,\n\tATA_CMD_VERIFY = 64,\n\tATA_CMD_VERIFY_EXT = 66,\n\tATA_CMD_WRITE_UNCORR_EXT = 69,\n\tATA_CMD_STANDBYNOW1 = 224,\n\tATA_CMD_IDLEIMMEDIATE = 225,\n\tATA_CMD_SLEEP = 230,\n\tATA_CMD_INIT_DEV_PARAMS = 145,\n\tATA_CMD_READ_NATIVE_MAX = 248,\n\tATA_CMD_READ_NATIVE_MAX_EXT = 39,\n\tATA_CMD_SET_MAX = 249,\n\tATA_CMD_SET_MAX_EXT = 55,\n\tATA_CMD_READ_LOG_EXT = 47,\n\tATA_CMD_WRITE_LOG_EXT = 63,\n\tATA_CMD_READ_LOG_DMA_EXT = 71,\n\tATA_CMD_WRITE_LOG_DMA_EXT = 87,\n\tATA_CMD_TRUSTED_NONDATA = 91,\n\tATA_CMD_TRUSTED_RCV = 92,\n\tATA_CMD_TRUSTED_RCV_DMA = 93,\n\tATA_CMD_TRUSTED_SND = 94,\n\tATA_CMD_TRUSTED_SND_DMA = 95,\n\tATA_CMD_PMP_READ = 228,\n\tATA_CMD_PMP_READ_DMA = 233,\n\tATA_CMD_PMP_WRITE = 232,\n\tATA_CMD_PMP_WRITE_DMA = 235,\n\tATA_CMD_CONF_OVERLAY = 177,\n\tATA_CMD_SEC_SET_PASS = 241,\n\tATA_CMD_SEC_UNLOCK = 242,\n\tATA_CMD_SEC_ERASE_PREP = 243,\n\tATA_CMD_SEC_ERASE_UNIT = 244,\n\tATA_CMD_SEC_FREEZE_LOCK = 245,\n\tATA_CMD_SEC_DISABLE_PASS = 246,\n\tATA_CMD_CONFIG_STREAM = 81,\n\tATA_CMD_SMART = 176,\n\tATA_CMD_MEDIA_LOCK = 222,\n\tATA_CMD_MEDIA_UNLOCK = 223,\n\tATA_CMD_DSM = 6,\n\tATA_CMD_CHK_MED_CRD_TYP = 209,\n\tATA_CMD_CFA_REQ_EXT_ERR = 3,\n\tATA_CMD_CFA_WRITE_NE = 56,\n\tATA_CMD_CFA_TRANS_SECT = 135,\n\tATA_CMD_CFA_ERASE = 192,\n\tATA_CMD_CFA_WRITE_MULT_NE = 205,\n\tATA_CMD_REQ_SENSE_DATA = 11,\n\tATA_CMD_SANITIZE_DEVICE = 180,\n\tATA_CMD_ZAC_MGMT_IN = 74,\n\tATA_CMD_ZAC_MGMT_OUT = 159,\n\tATA_CMD_RESTORE = 16,\n\tATA_SUBCMD_FPDMA_RECV_RD_LOG_DMA_EXT = 1,\n\tATA_SUBCMD_FPDMA_RECV_ZAC_MGMT_IN = 2,\n\tATA_SUBCMD_FPDMA_SEND_DSM = 0,\n\tATA_SUBCMD_FPDMA_SEND_WR_LOG_DMA_EXT = 2,\n\tATA_SUBCMD_NCQ_NON_DATA_ABORT_QUEUE = 0,\n\tATA_SUBCMD_NCQ_NON_DATA_SET_FEATURES = 5,\n\tATA_SUBCMD_NCQ_NON_DATA_ZERO_EXT = 6,\n\tATA_SUBCMD_NCQ_NON_DATA_ZAC_MGMT_OUT = 7,\n\tATA_SUBCMD_ZAC_MGMT_IN_REPORT_ZONES = 0,\n\tATA_SUBCMD_ZAC_MGMT_OUT_CLOSE_ZONE = 1,\n\tATA_SUBCMD_ZAC_MGMT_OUT_FINISH_ZONE = 2,\n\tATA_SUBCMD_ZAC_MGMT_OUT_OPEN_ZONE = 3,\n\tATA_SUBCMD_ZAC_MGMT_OUT_RESET_WRITE_POINTER = 4,\n\tATA_LOG_DIRECTORY = 0,\n\tATA_LOG_SATA_NCQ = 16,\n\tATA_LOG_NCQ_NON_DATA = 18,\n\tATA_LOG_NCQ_SEND_RECV = 19,\n\tATA_LOG_IDENTIFY_DEVICE = 48,\n\tATA_LOG_SECURITY = 6,\n\tATA_LOG_SATA_SETTINGS = 8,\n\tATA_LOG_ZONED_INFORMATION = 9,\n\tATA_LOG_DEVSLP_OFFSET = 48,\n\tATA_LOG_DEVSLP_SIZE = 8,\n\tATA_LOG_DEVSLP_MDAT = 0,\n\tATA_LOG_DEVSLP_MDAT_MASK = 31,\n\tATA_LOG_DEVSLP_DETO = 1,\n\tATA_LOG_DEVSLP_VALID = 7,\n\tATA_LOG_DEVSLP_VALID_MASK = 128,\n\tATA_LOG_NCQ_PRIO_OFFSET = 9,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_SEND_RECV_SUBCMDS_DSM = 1,\n\tATA_LOG_NCQ_SEND_RECV_DSM_OFFSET = 4,\n\tATA_LOG_NCQ_SEND_RECV_DSM_TRIM = 1,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_OFFSET = 8,\n\tATA_LOG_NCQ_SEND_RECV_RD_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_OFFSET = 12,\n\tATA_LOG_NCQ_SEND_RECV_WR_LOG_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OFFSET = 16,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OUT_SUPPORTED = 1,\n\tATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_IN_SUPPORTED = 2,\n\tATA_LOG_NCQ_SEND_RECV_SIZE = 20,\n\tATA_LOG_NCQ_NON_DATA_SUBCMDS_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_OFFSET = 0,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NCQ = 1,\n\tATA_LOG_NCQ_NON_DATA_ABORT_ALL = 2,\n\tATA_LOG_NCQ_NON_DATA_ABORT_STREAMING = 4,\n\tATA_LOG_NCQ_NON_DATA_ABORT_NON_STREAMING = 8,\n\tATA_LOG_NCQ_NON_DATA_ABORT_SELECTED = 16,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OFFSET = 28,\n\tATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OUT = 1,\n\tATA_LOG_NCQ_NON_DATA_SIZE = 64,\n\tATA_CMD_READ_LONG = 34,\n\tATA_CMD_READ_LONG_ONCE = 35,\n\tATA_CMD_WRITE_LONG = 50,\n\tATA_CMD_WRITE_LONG_ONCE = 51,\n\tSETFEATURES_XFER = 3,\n\tXFER_UDMA_7 = 71,\n\tXFER_UDMA_6 = 70,\n\tXFER_UDMA_5 = 69,\n\tXFER_UDMA_4 = 68,\n\tXFER_UDMA_3 = 67,\n\tXFER_UDMA_2 = 66,\n\tXFER_UDMA_1 = 65,\n\tXFER_UDMA_0 = 64,\n\tXFER_MW_DMA_4 = 36,\n\tXFER_MW_DMA_3 = 35,\n\tXFER_MW_DMA_2 = 34,\n\tXFER_MW_DMA_1 = 33,\n\tXFER_MW_DMA_0 = 32,\n\tXFER_SW_DMA_2 = 18,\n\tXFER_SW_DMA_1 = 17,\n\tXFER_SW_DMA_0 = 16,\n\tXFER_PIO_6 = 14,\n\tXFER_PIO_5 = 13,\n\tXFER_PIO_4 = 12,\n\tXFER_PIO_3 = 11,\n\tXFER_PIO_2 = 10,\n\tXFER_PIO_1 = 9,\n\tXFER_PIO_0 = 8,\n\tXFER_PIO_SLOW = 0,\n\tSETFEATURES_WC_ON = 2,\n\tSETFEATURES_WC_OFF = 130,\n\tSETFEATURES_RA_ON = 170,\n\tSETFEATURES_RA_OFF = 85,\n\tSETFEATURES_AAM_ON = 66,\n\tSETFEATURES_AAM_OFF = 194,\n\tSETFEATURES_SPINUP = 7,\n\tSETFEATURES_SPINUP_TIMEOUT = 30000,\n\tSETFEATURES_SATA_ENABLE = 16,\n\tSETFEATURES_SATA_DISABLE = 144,\n\tSATA_FPDMA_OFFSET = 1,\n\tSATA_FPDMA_AA = 2,\n\tSATA_DIPM = 3,\n\tSATA_FPDMA_IN_ORDER = 4,\n\tSATA_AN = 5,\n\tSATA_SSP = 6,\n\tSATA_DEVSLP = 9,\n\tSETFEATURE_SENSE_DATA = 195,\n\tATA_SET_MAX_ADDR = 0,\n\tATA_SET_MAX_PASSWD = 1,\n\tATA_SET_MAX_LOCK = 2,\n\tATA_SET_MAX_UNLOCK = 3,\n\tATA_SET_MAX_FREEZE_LOCK = 4,\n\tATA_SET_MAX_PASSWD_DMA = 5,\n\tATA_SET_MAX_UNLOCK_DMA = 6,\n\tATA_DCO_RESTORE = 192,\n\tATA_DCO_FREEZE_LOCK = 193,\n\tATA_DCO_IDENTIFY = 194,\n\tATA_DCO_SET = 195,\n\tATA_SMART_ENABLE = 216,\n\tATA_SMART_READ_VALUES = 208,\n\tATA_SMART_READ_THRESHOLDS = 209,\n\tATA_DSM_TRIM = 1,\n\tATA_SMART_LBAM_PASS = 79,\n\tATA_SMART_LBAH_PASS = 194,\n\tATAPI_PKT_DMA = 1,\n\tATAPI_DMADIR = 4,\n\tATAPI_CDB_LEN = 16,\n\tSATA_PMP_MAX_PORTS = 15,\n\tSATA_PMP_CTRL_PORT = 15,\n\tSATA_PMP_GSCR_DWORDS = 128,\n\tSATA_PMP_GSCR_PROD_ID = 0,\n\tSATA_PMP_GSCR_REV = 1,\n\tSATA_PMP_GSCR_PORT_INFO = 2,\n\tSATA_PMP_GSCR_ERROR = 32,\n\tSATA_PMP_GSCR_ERROR_EN = 33,\n\tSATA_PMP_GSCR_FEAT = 64,\n\tSATA_PMP_GSCR_FEAT_EN = 96,\n\tSATA_PMP_PSCR_STATUS = 0,\n\tSATA_PMP_PSCR_ERROR = 1,\n\tSATA_PMP_PSCR_CONTROL = 2,\n\tSATA_PMP_FEAT_BIST = 1,\n\tSATA_PMP_FEAT_PMREQ = 2,\n\tSATA_PMP_FEAT_DYNSSC = 4,\n\tSATA_PMP_FEAT_NOTIFY = 8,\n\tATA_CBL_NONE = 0,\n\tATA_CBL_PATA40 = 1,\n\tATA_CBL_PATA80 = 2,\n\tATA_CBL_PATA40_SHORT = 3,\n\tATA_CBL_PATA_UNK = 4,\n\tATA_CBL_PATA_IGN = 5,\n\tATA_CBL_SATA = 6,\n\tSCR_STATUS = 0,\n\tSCR_ERROR = 1,\n\tSCR_CONTROL = 2,\n\tSCR_ACTIVE = 3,\n\tSCR_NOTIFICATION = 4,\n\tSERR_DATA_RECOVERED = 1,\n\tSERR_COMM_RECOVERED = 2,\n\tSERR_DATA = 256,\n\tSERR_PERSISTENT = 512,\n\tSERR_PROTOCOL = 1024,\n\tSERR_INTERNAL = 2048,\n\tSERR_PHYRDY_CHG = 65536,\n\tSERR_PHY_INT_ERR = 131072,\n\tSERR_COMM_WAKE = 262144,\n\tSERR_10B_8B_ERR = 524288,\n\tSERR_DISPARITY = 1048576,\n\tSERR_CRC = 2097152,\n\tSERR_HANDSHAKE = 4194304,\n\tSERR_LINK_SEQ_ERR = 8388608,\n\tSERR_TRANS_ST_ERROR = 16777216,\n\tSERR_UNRECOG_FIS = 33554432,\n\tSERR_DEV_XCHG = 67108864,\n};\n\nenum ata_prot_flags {\n\tATA_PROT_FLAG_PIO = 1,\n\tATA_PROT_FLAG_DMA = 2,\n\tATA_PROT_FLAG_NCQ = 4,\n\tATA_PROT_FLAG_ATAPI = 8,\n\tATA_PROT_UNKNOWN = 255,\n\tATA_PROT_NODATA = 0,\n\tATA_PROT_PIO = 1,\n\tATA_PROT_DMA = 2,\n\tATA_PROT_NCQ_NODATA = 4,\n\tATA_PROT_NCQ = 6,\n\tATAPI_PROT_NODATA = 8,\n\tATAPI_PROT_PIO = 9,\n\tATAPI_PROT_DMA = 10,\n};\n\nstruct ata_bmdma_prd {\n\t__le32 addr;\n\t__le32 flags_len;\n};\n\nenum {\n\tATA_MSG_DRV = 1,\n\tATA_MSG_INFO = 2,\n\tATA_MSG_PROBE = 4,\n\tATA_MSG_WARN = 8,\n\tATA_MSG_MALLOC = 16,\n\tATA_MSG_CTL = 32,\n\tATA_MSG_INTR = 64,\n\tATA_MSG_ERR = 128,\n};\n\nenum {\n\tLIBATA_MAX_PRD = 128,\n\tLIBATA_DUMB_MAX_PRD = 64,\n\tATA_DEF_QUEUE = 1,\n\tATA_MAX_QUEUE = 32,\n\tATA_TAG_INTERNAL = 32,\n\tATA_SHORT_PAUSE = 16,\n\tATAPI_MAX_DRAIN = 16384,\n\tATA_ALL_DEVICES = 3,\n\tATA_SHT_EMULATED = 1,\n\tATA_SHT_THIS_ID = 4294967295,\n\tATA_TFLAG_LBA48 = 1,\n\tATA_TFLAG_ISADDR = 2,\n\tATA_TFLAG_DEVICE = 4,\n\tATA_TFLAG_WRITE = 8,\n\tATA_TFLAG_LBA = 16,\n\tATA_TFLAG_FUA = 32,\n\tATA_TFLAG_POLLING = 64,\n\tATA_DFLAG_LBA = 1,\n\tATA_DFLAG_LBA48 = 2,\n\tATA_DFLAG_CDB_INTR = 4,\n\tATA_DFLAG_NCQ = 8,\n\tATA_DFLAG_FLUSH_EXT = 16,\n\tATA_DFLAG_ACPI_PENDING = 32,\n\tATA_DFLAG_ACPI_FAILED = 64,\n\tATA_DFLAG_AN = 128,\n\tATA_DFLAG_TRUSTED = 256,\n\tATA_DFLAG_DMADIR = 1024,\n\tATA_DFLAG_CFG_MASK = 4095,\n\tATA_DFLAG_PIO = 4096,\n\tATA_DFLAG_NCQ_OFF = 8192,\n\tATA_DFLAG_SLEEPING = 32768,\n\tATA_DFLAG_DUBIOUS_XFER = 65536,\n\tATA_DFLAG_NO_UNLOAD = 131072,\n\tATA_DFLAG_UNLOCK_HPA = 262144,\n\tATA_DFLAG_NCQ_SEND_RECV = 524288,\n\tATA_DFLAG_NCQ_PRIO = 1048576,\n\tATA_DFLAG_NCQ_PRIO_ENABLE = 2097152,\n\tATA_DFLAG_INIT_MASK = 16777215,\n\tATA_DFLAG_DETACH = 16777216,\n\tATA_DFLAG_DETACHED = 33554432,\n\tATA_DFLAG_DA = 67108864,\n\tATA_DFLAG_DEVSLP = 134217728,\n\tATA_DFLAG_ACPI_DISABLED = 268435456,\n\tATA_DFLAG_D_SENSE = 536870912,\n\tATA_DFLAG_ZAC = 1073741824,\n\tATA_DEV_UNKNOWN = 0,\n\tATA_DEV_ATA = 1,\n\tATA_DEV_ATA_UNSUP = 2,\n\tATA_DEV_ATAPI = 3,\n\tATA_DEV_ATAPI_UNSUP = 4,\n\tATA_DEV_PMP = 5,\n\tATA_DEV_PMP_UNSUP = 6,\n\tATA_DEV_SEMB = 7,\n\tATA_DEV_SEMB_UNSUP = 8,\n\tATA_DEV_ZAC = 9,\n\tATA_DEV_ZAC_UNSUP = 10,\n\tATA_DEV_NONE = 11,\n\tATA_LFLAG_NO_HRST = 2,\n\tATA_LFLAG_NO_SRST = 4,\n\tATA_LFLAG_ASSUME_ATA = 8,\n\tATA_LFLAG_ASSUME_SEMB = 16,\n\tATA_LFLAG_ASSUME_CLASS = 24,\n\tATA_LFLAG_NO_RETRY = 32,\n\tATA_LFLAG_DISABLED = 64,\n\tATA_LFLAG_SW_ACTIVITY = 128,\n\tATA_LFLAG_NO_LPM = 256,\n\tATA_LFLAG_RST_ONCE = 512,\n\tATA_LFLAG_CHANGED = 1024,\n\tATA_LFLAG_NO_DB_DELAY = 2048,\n\tATA_FLAG_SLAVE_POSS = 1,\n\tATA_FLAG_SATA = 2,\n\tATA_FLAG_NO_LPM = 4,\n\tATA_FLAG_NO_LOG_PAGE = 32,\n\tATA_FLAG_NO_ATAPI = 64,\n\tATA_FLAG_PIO_DMA = 128,\n\tATA_FLAG_PIO_LBA48 = 256,\n\tATA_FLAG_PIO_POLLING = 512,\n\tATA_FLAG_NCQ = 1024,\n\tATA_FLAG_NO_POWEROFF_SPINDOWN = 2048,\n\tATA_FLAG_NO_HIBERNATE_SPINDOWN = 4096,\n\tATA_FLAG_DEBUGMSG = 8192,\n\tATA_FLAG_FPDMA_AA = 16384,\n\tATA_FLAG_IGN_SIMPLEX = 32768,\n\tATA_FLAG_NO_IORDY = 65536,\n\tATA_FLAG_ACPI_SATA = 131072,\n\tATA_FLAG_AN = 262144,\n\tATA_FLAG_PMP = 524288,\n\tATA_FLAG_FPDMA_AUX = 1048576,\n\tATA_FLAG_EM = 2097152,\n\tATA_FLAG_SW_ACTIVITY = 4194304,\n\tATA_FLAG_NO_DIPM = 8388608,\n\tATA_FLAG_SAS_HOST = 16777216,\n\tATA_PFLAG_EH_PENDING = 1,\n\tATA_PFLAG_EH_IN_PROGRESS = 2,\n\tATA_PFLAG_FROZEN = 4,\n\tATA_PFLAG_RECOVERED = 8,\n\tATA_PFLAG_LOADING = 16,\n\tATA_PFLAG_SCSI_HOTPLUG = 64,\n\tATA_PFLAG_INITIALIZING = 128,\n\tATA_PFLAG_RESETTING = 256,\n\tATA_PFLAG_UNLOADING = 512,\n\tATA_PFLAG_UNLOADED = 1024,\n\tATA_PFLAG_SUSPENDED = 131072,\n\tATA_PFLAG_PM_PENDING = 262144,\n\tATA_PFLAG_INIT_GTM_VALID = 524288,\n\tATA_PFLAG_PIO32 = 1048576,\n\tATA_PFLAG_PIO32CHANGE = 2097152,\n\tATA_PFLAG_EXTERNAL = 4194304,\n\tATA_QCFLAG_ACTIVE = 1,\n\tATA_QCFLAG_DMAMAP = 2,\n\tATA_QCFLAG_IO = 8,\n\tATA_QCFLAG_RESULT_TF = 16,\n\tATA_QCFLAG_CLEAR_EXCL = 32,\n\tATA_QCFLAG_QUIET = 64,\n\tATA_QCFLAG_RETRY = 128,\n\tATA_QCFLAG_FAILED = 65536,\n\tATA_QCFLAG_SENSE_VALID = 131072,\n\tATA_QCFLAG_EH_SCHEDULED = 262144,\n\tATA_HOST_SIMPLEX = 1,\n\tATA_HOST_STARTED = 2,\n\tATA_HOST_PARALLEL_SCAN = 4,\n\tATA_HOST_IGNORE_ATA = 8,\n\tATA_TMOUT_BOOT = 30000,\n\tATA_TMOUT_BOOT_QUICK = 7000,\n\tATA_TMOUT_INTERNAL_QUICK = 5000,\n\tATA_TMOUT_MAX_PARK = 30000,\n\tATA_TMOUT_FF_WAIT_LONG = 2000,\n\tATA_TMOUT_FF_WAIT = 800,\n\tATA_WAIT_AFTER_RESET = 150,\n\tATA_TMOUT_PMP_SRST_WAIT = 5000,\n\tATA_TMOUT_SPURIOUS_PHY = 10000,\n\tBUS_UNKNOWN = 0,\n\tBUS_DMA = 1,\n\tBUS_IDLE = 2,\n\tBUS_NOINTR = 3,\n\tBUS_NODATA = 4,\n\tBUS_TIMER = 5,\n\tBUS_PIO = 6,\n\tBUS_EDD = 7,\n\tBUS_IDENTIFY = 8,\n\tBUS_PACKET = 9,\n\tPORT_UNKNOWN = 0,\n\tPORT_ENABLED = 1,\n\tPORT_DISABLED = 2,\n\tATA_NR_PIO_MODES = 7,\n\tATA_NR_MWDMA_MODES = 5,\n\tATA_NR_UDMA_MODES = 8,\n\tATA_SHIFT_PIO = 0,\n\tATA_SHIFT_MWDMA = 7,\n\tATA_SHIFT_UDMA = 12,\n\tATA_SHIFT_PRIO = 6,\n\tATA_PRIO_HIGH = 2,\n\tATA_DMA_PAD_SZ = 4,\n\tATA_ERING_SIZE = 32,\n\tATA_DEFER_LINK = 1,\n\tATA_DEFER_PORT = 2,\n\tATA_EH_DESC_LEN = 80,\n\tATA_EH_REVALIDATE = 1,\n\tATA_EH_SOFTRESET = 2,\n\tATA_EH_HARDRESET = 4,\n\tATA_EH_RESET = 6,\n\tATA_EH_ENABLE_LINK = 8,\n\tATA_EH_PARK = 32,\n\tATA_EH_PERDEV_MASK = 33,\n\tATA_EH_ALL_ACTIONS = 15,\n\tATA_EHI_HOTPLUGGED = 1,\n\tATA_EHI_NO_AUTOPSY = 4,\n\tATA_EHI_QUIET = 8,\n\tATA_EHI_NO_RECOVERY = 16,\n\tATA_EHI_DID_SOFTRESET = 65536,\n\tATA_EHI_DID_HARDRESET = 131072,\n\tATA_EHI_PRINTINFO = 262144,\n\tATA_EHI_SETMODE = 524288,\n\tATA_EHI_POST_SETMODE = 1048576,\n\tATA_EHI_DID_RESET = 196608,\n\tATA_EHI_TO_SLAVE_MASK = 12,\n\tATA_EH_MAX_TRIES = 5,\n\tATA_LINK_RESUME_TRIES = 5,\n\tATA_PROBE_MAX_TRIES = 3,\n\tATA_EH_DEV_TRIES = 3,\n\tATA_EH_PMP_TRIES = 5,\n\tATA_EH_PMP_LINK_TRIES = 3,\n\tSATA_PMP_RW_TIMEOUT = 3000,\n\tATA_EH_CMD_TIMEOUT_TABLE_SIZE = 6,\n\tATA_HORKAGE_DIAGNOSTIC = 1,\n\tATA_HORKAGE_NODMA = 2,\n\tATA_HORKAGE_NONCQ = 4,\n\tATA_HORKAGE_MAX_SEC_128 = 8,\n\tATA_HORKAGE_BROKEN_HPA = 16,\n\tATA_HORKAGE_DISABLE = 32,\n\tATA_HORKAGE_HPA_SIZE = 64,\n\tATA_HORKAGE_IVB = 256,\n\tATA_HORKAGE_STUCK_ERR = 512,\n\tATA_HORKAGE_BRIDGE_OK = 1024,\n\tATA_HORKAGE_ATAPI_MOD16_DMA = 2048,\n\tATA_HORKAGE_FIRMWARE_WARN = 4096,\n\tATA_HORKAGE_1_5_GBPS = 8192,\n\tATA_HORKAGE_NOSETXFER = 16384,\n\tATA_HORKAGE_BROKEN_FPDMA_AA = 32768,\n\tATA_HORKAGE_DUMP_ID = 65536,\n\tATA_HORKAGE_MAX_SEC_LBA48 = 131072,\n\tATA_HORKAGE_ATAPI_DMADIR = 262144,\n\tATA_HORKAGE_NO_NCQ_TRIM = 524288,\n\tATA_HORKAGE_NOLPM = 1048576,\n\tATA_HORKAGE_WD_BROKEN_LPM = 2097152,\n\tATA_HORKAGE_ZERO_AFTER_TRIM = 4194304,\n\tATA_HORKAGE_NO_DMA_LOG = 8388608,\n\tATA_HORKAGE_NOTRIM = 16777216,\n\tATA_HORKAGE_MAX_SEC_1024 = 33554432,\n\tATA_DMA_MASK_ATA = 1,\n\tATA_DMA_MASK_ATAPI = 2,\n\tATA_DMA_MASK_CFA = 4,\n\tATAPI_READ = 0,\n\tATAPI_WRITE = 1,\n\tATAPI_READ_CD = 2,\n\tATAPI_PASS_THRU = 3,\n\tATAPI_MISC = 4,\n\tATA_TIMING_SETUP = 1,\n\tATA_TIMING_ACT8B = 2,\n\tATA_TIMING_REC8B = 4,\n\tATA_TIMING_CYC8B = 8,\n\tATA_TIMING_8BIT = 14,\n\tATA_TIMING_ACTIVE = 16,\n\tATA_TIMING_RECOVER = 32,\n\tATA_TIMING_DMACK_HOLD = 64,\n\tATA_TIMING_CYCLE = 128,\n\tATA_TIMING_UDMA = 256,\n\tATA_TIMING_ALL = 511,\n\tATA_ACPI_FILTER_SETXFER = 1,\n\tATA_ACPI_FILTER_LOCK = 2,\n\tATA_ACPI_FILTER_DIPM = 4,\n\tATA_ACPI_FILTER_FPDMA_OFFSET = 8,\n\tATA_ACPI_FILTER_FPDMA_AA = 16,\n\tATA_ACPI_FILTER_DEFAULT = 7,\n};\n\nenum ata_xfer_mask {\n\tATA_MASK_PIO = 127,\n\tATA_MASK_MWDMA = 3968,\n\tATA_MASK_UDMA = 1044480,\n};\n\nenum ata_completion_errors {\n\tAC_ERR_OK = 0,\n\tAC_ERR_DEV = 1,\n\tAC_ERR_HSM = 2,\n\tAC_ERR_TIMEOUT = 4,\n\tAC_ERR_MEDIA = 8,\n\tAC_ERR_ATA_BUS = 16,\n\tAC_ERR_HOST_BUS = 32,\n\tAC_ERR_SYSTEM = 64,\n\tAC_ERR_INVALID = 128,\n\tAC_ERR_OTHER = 256,\n\tAC_ERR_NODEV_HINT = 512,\n\tAC_ERR_NCQ = 1024,\n};\n\nenum ata_lpm_policy {\n\tATA_LPM_UNKNOWN = 0,\n\tATA_LPM_MAX_POWER = 1,\n\tATA_LPM_MED_POWER = 2,\n\tATA_LPM_MED_POWER_WITH_DIPM = 3,\n\tATA_LPM_MIN_POWER_WITH_PARTIAL = 4,\n\tATA_LPM_MIN_POWER = 5,\n};\n\nstruct ata_queued_cmd;\n\ntypedef void (*ata_qc_cb_t)(struct ata_queued_cmd *);\n\nstruct ata_taskfile {\n\tlong unsigned int flags;\n\tu8 protocol;\n\tu8 ctl;\n\tu8 hob_feature;\n\tu8 hob_nsect;\n\tu8 hob_lbal;\n\tu8 hob_lbam;\n\tu8 hob_lbah;\n\tu8 feature;\n\tu8 nsect;\n\tu8 lbal;\n\tu8 lbam;\n\tu8 lbah;\n\tu8 device;\n\tu8 command;\n\tu32 auxiliary;\n};\n\nstruct ata_port;\n\nstruct ata_device;\n\nstruct ata_queued_cmd {\n\tstruct ata_port *ap;\n\tstruct ata_device *dev;\n\tstruct scsi_cmnd *scsicmd;\n\tvoid (*scsidone)(struct scsi_cmnd *);\n\tstruct ata_taskfile tf;\n\tu8 cdb[16];\n\tlong unsigned int flags;\n\tunsigned int tag;\n\tunsigned int hw_tag;\n\tunsigned int n_elem;\n\tunsigned int orig_n_elem;\n\tint dma_dir;\n\tunsigned int sect_size;\n\tunsigned int nbytes;\n\tunsigned int extrabytes;\n\tunsigned int curbytes;\n\tstruct scatterlist sgent;\n\tstruct scatterlist *sg;\n\tstruct scatterlist *cursg;\n\tunsigned int cursg_ofs;\n\tunsigned int err_mask;\n\tstruct ata_taskfile result_tf;\n\tata_qc_cb_t complete_fn;\n\tvoid *private_data;\n\tvoid *lldd_task;\n};\n\nstruct ata_link;\n\ntypedef int (*ata_prereset_fn_t)(struct ata_link *, long unsigned int);\n\nstruct ata_eh_info {\n\tstruct ata_device *dev;\n\tu32 serror;\n\tunsigned int err_mask;\n\tunsigned int action;\n\tunsigned int dev_action[2];\n\tunsigned int flags;\n\tunsigned int probe_mask;\n\tchar desc[80];\n\tint desc_len;\n};\n\nstruct ata_eh_context {\n\tstruct ata_eh_info i;\n\tint tries[2];\n\tint cmd_timeout_idx[12];\n\tunsigned int classes[2];\n\tunsigned int did_probe_mask;\n\tunsigned int unloaded_mask;\n\tunsigned int saved_ncq_enabled;\n\tu8 saved_xfer_mode[2];\n\tlong unsigned int last_reset;\n};\n\nstruct ata_ering_entry {\n\tunsigned int eflags;\n\tunsigned int err_mask;\n\tu64 timestamp;\n};\n\nstruct ata_ering {\n\tint cursor;\n\tstruct ata_ering_entry ring[32];\n};\n\nstruct ata_device {\n\tstruct ata_link *link;\n\tunsigned int devno;\n\tunsigned int horkage;\n\tlong unsigned int flags;\n\tstruct scsi_device *sdev;\n\tvoid *private_data;\n\tunion acpi_object *gtf_cache;\n\tunsigned int gtf_filter;\n\tstruct device tdev;\n\tu64 n_sectors;\n\tu64 n_native_sectors;\n\tunsigned int class;\n\tlong unsigned int unpark_deadline;\n\tu8 pio_mode;\n\tu8 dma_mode;\n\tu8 xfer_mode;\n\tunsigned int xfer_shift;\n\tunsigned int multi_count;\n\tunsigned int max_sectors;\n\tunsigned int cdb_len;\n\tlong unsigned int pio_mask;\n\tlong unsigned int mwdma_mask;\n\tlong unsigned int udma_mask;\n\tu16 cylinders;\n\tu16 heads;\n\tu16 sectors;\n\tlong: 16;\n\tlong: 64;\n\tlong: 64;\n\tunion {\n\t\tu16 id[256];\n\t\tu32 gscr[128];\n\t};\n\tu8 devslp_timing[8];\n\tu8 ncq_send_recv_cmds[20];\n\tu8 ncq_non_data_cmds[64];\n\tu32 zac_zoned_cap;\n\tu32 zac_zones_optimal_open;\n\tu32 zac_zones_optimal_nonseq;\n\tu32 zac_zones_max_open;\n\tint spdn_cnt;\n\tstruct ata_ering ering;\n\tlong: 64;\n};\n\nstruct ata_link {\n\tstruct ata_port *ap;\n\tint pmp;\n\tstruct device tdev;\n\tunsigned int active_tag;\n\tu32 sactive;\n\tunsigned int flags;\n\tu32 saved_scontrol;\n\tunsigned int hw_sata_spd_limit;\n\tunsigned int sata_spd_limit;\n\tunsigned int sata_spd;\n\tenum ata_lpm_policy lpm_policy;\n\tstruct ata_eh_info eh_info;\n\tstruct ata_eh_context eh_context;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ata_device device[2];\n\tlong unsigned int last_lpm_change;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef int (*ata_reset_fn_t)(struct ata_link *, unsigned int *, long unsigned int);\n\ntypedef void (*ata_postreset_fn_t)(struct ata_link *, unsigned int *);\n\nenum sw_activity {\n\tOFF = 0,\n\tBLINK_ON = 1,\n\tBLINK_OFF = 2,\n};\n\nstruct ata_ioports {\n\tvoid *cmd_addr;\n\tvoid *data_addr;\n\tvoid *error_addr;\n\tvoid *feature_addr;\n\tvoid *nsect_addr;\n\tvoid *lbal_addr;\n\tvoid *lbam_addr;\n\tvoid *lbah_addr;\n\tvoid *device_addr;\n\tvoid *status_addr;\n\tvoid *command_addr;\n\tvoid *altstatus_addr;\n\tvoid *ctl_addr;\n\tvoid *bmdma_addr;\n\tvoid *scr_addr;\n};\n\nstruct ata_port_operations;\n\nstruct ata_host {\n\tspinlock_t lock;\n\tstruct device *dev;\n\tvoid * const *iomap;\n\tunsigned int n_ports;\n\tunsigned int n_tags;\n\tvoid *private_data;\n\tstruct ata_port_operations *ops;\n\tlong unsigned int flags;\n\tstruct kref kref;\n\tstruct mutex eh_mutex;\n\tstruct task_struct *eh_owner;\n\tstruct ata_port *simplex_claimed;\n\tstruct ata_port *ports[0];\n};\n\nstruct ata_port_operations {\n\tint (*qc_defer)(struct ata_queued_cmd *);\n\tint (*check_atapi_dma)(struct ata_queued_cmd *);\n\tenum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *);\n\tunsigned int (*qc_issue)(struct ata_queued_cmd *);\n\tbool (*qc_fill_rtf)(struct ata_queued_cmd *);\n\tint (*cable_detect)(struct ata_port *);\n\tlong unsigned int (*mode_filter)(struct ata_device *, long unsigned int);\n\tvoid (*set_piomode)(struct ata_port *, struct ata_device *);\n\tvoid (*set_dmamode)(struct ata_port *, struct ata_device *);\n\tint (*set_mode)(struct ata_link *, struct ata_device **);\n\tunsigned int (*read_id)(struct ata_device *, struct ata_taskfile *, u16 *);\n\tvoid (*dev_config)(struct ata_device *);\n\tvoid (*freeze)(struct ata_port *);\n\tvoid (*thaw)(struct ata_port *);\n\tata_prereset_fn_t prereset;\n\tata_reset_fn_t softreset;\n\tata_reset_fn_t hardreset;\n\tata_postreset_fn_t postreset;\n\tata_prereset_fn_t pmp_prereset;\n\tata_reset_fn_t pmp_softreset;\n\tata_reset_fn_t pmp_hardreset;\n\tata_postreset_fn_t pmp_postreset;\n\tvoid (*error_handler)(struct ata_port *);\n\tvoid (*lost_interrupt)(struct ata_port *);\n\tvoid (*post_internal_cmd)(struct ata_queued_cmd *);\n\tvoid (*sched_eh)(struct ata_port *);\n\tvoid (*end_eh)(struct ata_port *);\n\tint (*scr_read)(struct ata_link *, unsigned int, u32 *);\n\tint (*scr_write)(struct ata_link *, unsigned int, u32);\n\tvoid (*pmp_attach)(struct ata_port *);\n\tvoid (*pmp_detach)(struct ata_port *);\n\tint (*set_lpm)(struct ata_link *, enum ata_lpm_policy, unsigned int);\n\tint (*port_suspend)(struct ata_port *, pm_message_t);\n\tint (*port_resume)(struct ata_port *);\n\tint (*port_start)(struct ata_port *);\n\tvoid (*port_stop)(struct ata_port *);\n\tvoid (*host_stop)(struct ata_host *);\n\tvoid (*sff_dev_select)(struct ata_port *, unsigned int);\n\tvoid (*sff_set_devctl)(struct ata_port *, u8);\n\tu8 (*sff_check_status)(struct ata_port *);\n\tu8 (*sff_check_altstatus)(struct ata_port *);\n\tvoid (*sff_tf_load)(struct ata_port *, const struct ata_taskfile *);\n\tvoid (*sff_tf_read)(struct ata_port *, struct ata_taskfile *);\n\tvoid (*sff_exec_command)(struct ata_port *, const struct ata_taskfile *);\n\tunsigned int (*sff_data_xfer)(struct ata_queued_cmd *, unsigned char *, unsigned int, int);\n\tvoid (*sff_irq_on)(struct ata_port *);\n\tbool (*sff_irq_check)(struct ata_port *);\n\tvoid (*sff_irq_clear)(struct ata_port *);\n\tvoid (*sff_drain_fifo)(struct ata_queued_cmd *);\n\tvoid (*bmdma_setup)(struct ata_queued_cmd *);\n\tvoid (*bmdma_start)(struct ata_queued_cmd *);\n\tvoid (*bmdma_stop)(struct ata_queued_cmd *);\n\tu8 (*bmdma_status)(struct ata_port *);\n\tssize_t (*em_show)(struct ata_port *, char *);\n\tssize_t (*em_store)(struct ata_port *, const char *, size_t);\n\tssize_t (*sw_activity_show)(struct ata_device *, char *);\n\tssize_t (*sw_activity_store)(struct ata_device *, enum sw_activity);\n\tssize_t (*transmit_led_message)(struct ata_port *, u32, ssize_t);\n\tvoid (*phy_reset)(struct ata_port *);\n\tvoid (*eng_timeout)(struct ata_port *);\n\tconst struct ata_port_operations *inherits;\n};\n\nstruct ata_port_stats {\n\tlong unsigned int unhandled_irq;\n\tlong unsigned int idle_irq;\n\tlong unsigned int rw_reqbuf;\n};\n\nstruct ata_acpi_drive {\n\tu32 pio;\n\tu32 dma;\n};\n\nstruct ata_acpi_gtm {\n\tstruct ata_acpi_drive drive[2];\n\tu32 flags;\n};\n\nstruct ata_port {\n\tstruct Scsi_Host *scsi_host;\n\tstruct ata_port_operations *ops;\n\tspinlock_t *lock;\n\tlong unsigned int flags;\n\tunsigned int pflags;\n\tunsigned int print_id;\n\tunsigned int local_port_no;\n\tunsigned int port_no;\n\tstruct ata_ioports ioaddr;\n\tu8 ctl;\n\tu8 last_ctl;\n\tstruct ata_link *sff_pio_task_link;\n\tstruct delayed_work sff_pio_task;\n\tstruct ata_bmdma_prd *bmdma_prd;\n\tdma_addr_t bmdma_prd_dma;\n\tunsigned int pio_mask;\n\tunsigned int mwdma_mask;\n\tunsigned int udma_mask;\n\tunsigned int cbl;\n\tstruct ata_queued_cmd qcmd[33];\n\tlong unsigned int sas_tag_allocated;\n\tu64 qc_active;\n\tint nr_active_links;\n\tunsigned int sas_last_tag;\n\tlong: 64;\n\tstruct ata_link link;\n\tstruct ata_link *slave_link;\n\tint nr_pmp_links;\n\tstruct ata_link *pmp_link;\n\tstruct ata_link *excl_link;\n\tstruct ata_port_stats stats;\n\tstruct ata_host *host;\n\tstruct device *dev;\n\tstruct device tdev;\n\tstruct mutex scsi_scan_mutex;\n\tstruct delayed_work hotplug_task;\n\tstruct work_struct scsi_rescan_task;\n\tunsigned int hsm_task_state;\n\tu32 msg_enable;\n\tstruct list_head eh_done_q;\n\twait_queue_head_t eh_wait_q;\n\tint eh_tries;\n\tstruct completion park_req_pending;\n\tpm_message_t pm_mesg;\n\tenum ata_lpm_policy target_lpm_policy;\n\tstruct timer_list fastdrain_timer;\n\tlong unsigned int fastdrain_cnt;\n\tasync_cookie_t cookie;\n\tint em_message_type;\n\tvoid *private_data;\n\tstruct ata_acpi_gtm __acpi_init_gtm;\n\tint: 32;\n\tu8 sector_buf[512];\n};\n\nstruct ata_port_info {\n\tlong unsigned int flags;\n\tlong unsigned int link_flags;\n\tlong unsigned int pio_mask;\n\tlong unsigned int mwdma_mask;\n\tlong unsigned int udma_mask;\n\tstruct ata_port_operations *port_ops;\n\tvoid *private_data;\n};\n\nstruct ata_timing {\n\tshort unsigned int mode;\n\tshort unsigned int setup;\n\tshort unsigned int act8b;\n\tshort unsigned int rec8b;\n\tshort unsigned int cyc8b;\n\tshort unsigned int active;\n\tshort unsigned int recover;\n\tshort unsigned int dmack_hold;\n\tshort unsigned int cycle;\n\tshort unsigned int udma;\n};\n\nstruct pci_bits {\n\tunsigned int reg;\n\tunsigned int width;\n\tlong unsigned int mask;\n\tlong unsigned int val;\n};\n\nenum ata_link_iter_mode {\n\tATA_LITER_EDGE = 0,\n\tATA_LITER_HOST_FIRST = 1,\n\tATA_LITER_PMP_FIRST = 2,\n};\n\nenum ata_dev_iter_mode {\n\tATA_DITER_ENABLED = 0,\n\tATA_DITER_ENABLED_REVERSE = 1,\n\tATA_DITER_ALL = 2,\n\tATA_DITER_ALL_REVERSE = 3,\n};\n\nstruct trace_event_raw_ata_qc_issue {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned char cmd;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char feature;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char ctl;\n\tunsigned char proto;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_qc_complete_template {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned char status;\n\tunsigned char dev;\n\tunsigned char lbal;\n\tunsigned char lbam;\n\tunsigned char lbah;\n\tunsigned char nsect;\n\tunsigned char error;\n\tunsigned char hob_lbal;\n\tunsigned char hob_lbam;\n\tunsigned char hob_lbah;\n\tunsigned char hob_nsect;\n\tunsigned char hob_feature;\n\tunsigned char ctl;\n\tlong unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_link_autopsy {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int eh_action;\n\tunsigned int eh_err_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_ata_eh_link_autopsy_qc {\n\tstruct trace_entry ent;\n\tunsigned int ata_port;\n\tunsigned int ata_dev;\n\tunsigned int tag;\n\tunsigned int qc_flags;\n\tunsigned int eh_err_mask;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_ata_qc_issue {};\n\nstruct trace_event_data_offsets_ata_qc_complete_template {};\n\nstruct trace_event_data_offsets_ata_eh_link_autopsy {};\n\nstruct trace_event_data_offsets_ata_eh_link_autopsy_qc {};\n\ntypedef void (*btf_trace_ata_qc_issue)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_internal)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_failed)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_qc_complete_done)(void *, struct ata_queued_cmd *);\n\ntypedef void (*btf_trace_ata_eh_link_autopsy)(void *, struct ata_device *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_ata_eh_link_autopsy_qc)(void *, struct ata_queued_cmd *);\n\nenum {\n\tATA_READID_POSTRESET = 1,\n\tATA_DNXFER_PIO = 0,\n\tATA_DNXFER_DMA = 1,\n\tATA_DNXFER_40C = 2,\n\tATA_DNXFER_FORCE_PIO = 3,\n\tATA_DNXFER_FORCE_PIO0 = 4,\n\tATA_DNXFER_QUIET = 2147483648,\n};\n\nstruct ata_force_param {\n\tconst char *name;\n\tu8 cbl;\n\tu8 spd_limit;\n\tlong unsigned int xfer_mask;\n\tunsigned int horkage_on;\n\tunsigned int horkage_off;\n\tu16 lflags;\n};\n\nstruct ata_force_ent {\n\tint port;\n\tint device;\n\tstruct ata_force_param param;\n};\n\nstruct ata_xfer_ent {\n\tint shift;\n\tint bits;\n\tu8 base;\n};\n\nstruct ata_blacklist_entry {\n\tconst char *model_num;\n\tconst char *model_rev;\n\tlong unsigned int horkage;\n};\n\ntypedef unsigned int (*ata_xlat_func_t)(struct ata_queued_cmd *);\n\nstruct ata_scsi_args {\n\tstruct ata_device *dev;\n\tu16 *id;\n\tstruct scsi_cmnd *cmd;\n};\n\nenum ata_lpm_hints {\n\tATA_LPM_EMPTY = 1,\n\tATA_LPM_HIPM = 2,\n\tATA_LPM_WAKE_ONLY = 4,\n};\n\nenum {\n\tATA_EH_SPDN_NCQ_OFF = 1,\n\tATA_EH_SPDN_SPEED_DOWN = 2,\n\tATA_EH_SPDN_FALLBACK_TO_PIO = 4,\n\tATA_EH_SPDN_KEEP_ERRORS = 8,\n\tATA_EFLAG_IS_IO = 1,\n\tATA_EFLAG_DUBIOUS_XFER = 2,\n\tATA_EFLAG_OLD_ER = 2147483648,\n\tATA_ECAT_NONE = 0,\n\tATA_ECAT_ATA_BUS = 1,\n\tATA_ECAT_TOUT_HSM = 2,\n\tATA_ECAT_UNK_DEV = 3,\n\tATA_ECAT_DUBIOUS_NONE = 4,\n\tATA_ECAT_DUBIOUS_ATA_BUS = 5,\n\tATA_ECAT_DUBIOUS_TOUT_HSM = 6,\n\tATA_ECAT_DUBIOUS_UNK_DEV = 7,\n\tATA_ECAT_NR = 8,\n\tATA_EH_CMD_DFL_TIMEOUT = 5000,\n\tATA_EH_RESET_COOL_DOWN = 5000,\n\tATA_EH_PRERESET_TIMEOUT = 10000,\n\tATA_EH_FASTDRAIN_INTERVAL = 3000,\n\tATA_EH_UA_TRIES = 5,\n\tATA_EH_PROBE_TRIAL_INTERVAL = 60000,\n\tATA_EH_PROBE_TRIALS = 2,\n};\n\nstruct ata_eh_cmd_timeout_ent {\n\tconst u8 *commands;\n\tconst long unsigned int *timeouts;\n};\n\nstruct speed_down_verdict_arg {\n\tu64 since;\n\tint xfer_ok;\n\tint nr_errors[8];\n};\n\nstruct ata_internal {\n\tstruct scsi_transport_template t;\n\tstruct device_attribute private_port_attrs[3];\n\tstruct device_attribute private_link_attrs[3];\n\tstruct device_attribute private_dev_attrs[9];\n\tstruct transport_container link_attr_cont;\n\tstruct transport_container dev_attr_cont;\n\tstruct device_attribute *link_attrs[4];\n\tstruct device_attribute *port_attrs[4];\n\tstruct device_attribute *dev_attrs[10];\n};\n\nstruct ata_show_ering_arg {\n\tchar *buf;\n\tint written;\n};\n\nenum hsm_task_states {\n\tHSM_ST_IDLE = 0,\n\tHSM_ST_FIRST = 1,\n\tHSM_ST = 2,\n\tHSM_ST_LAST = 3,\n\tHSM_ST_ERR = 4,\n};\n\nstruct ata_acpi_gtf {\n\tu8 tf[7];\n};\n\nstruct ata_acpi_hotplug_context {\n\tstruct acpi_hotplug_context hp;\n\tunion {\n\t\tstruct ata_port *ap;\n\t\tstruct ata_device *dev;\n\t} data;\n};\n\nstruct regulator;\n\nstruct phy_configure_opts_dp {\n\tunsigned int link_rate;\n\tunsigned int lanes;\n\tunsigned int voltage[4];\n\tunsigned int pre[4];\n\tu8 ssc: 1;\n\tu8 set_rate: 1;\n\tu8 set_lanes: 1;\n\tu8 set_voltages: 1;\n};\n\nstruct phy_configure_opts_mipi_dphy {\n\tunsigned int clk_miss;\n\tunsigned int clk_post;\n\tunsigned int clk_pre;\n\tunsigned int clk_prepare;\n\tunsigned int clk_settle;\n\tunsigned int clk_term_en;\n\tunsigned int clk_trail;\n\tunsigned int clk_zero;\n\tunsigned int d_term_en;\n\tunsigned int eot;\n\tunsigned int hs_exit;\n\tunsigned int hs_prepare;\n\tunsigned int hs_settle;\n\tunsigned int hs_skip;\n\tunsigned int hs_trail;\n\tunsigned int hs_zero;\n\tunsigned int init;\n\tunsigned int lpx;\n\tunsigned int ta_get;\n\tunsigned int ta_go;\n\tunsigned int ta_sure;\n\tunsigned int wakeup;\n\tlong unsigned int hs_clk_rate;\n\tlong unsigned int lp_clk_rate;\n\tunsigned char lanes;\n};\n\nenum phy_mode {\n\tPHY_MODE_INVALID = 0,\n\tPHY_MODE_USB_HOST = 1,\n\tPHY_MODE_USB_HOST_LS = 2,\n\tPHY_MODE_USB_HOST_FS = 3,\n\tPHY_MODE_USB_HOST_HS = 4,\n\tPHY_MODE_USB_HOST_SS = 5,\n\tPHY_MODE_USB_DEVICE = 6,\n\tPHY_MODE_USB_DEVICE_LS = 7,\n\tPHY_MODE_USB_DEVICE_FS = 8,\n\tPHY_MODE_USB_DEVICE_HS = 9,\n\tPHY_MODE_USB_DEVICE_SS = 10,\n\tPHY_MODE_USB_OTG = 11,\n\tPHY_MODE_UFS_HS_A = 12,\n\tPHY_MODE_UFS_HS_B = 13,\n\tPHY_MODE_PCIE = 14,\n\tPHY_MODE_ETHERNET = 15,\n\tPHY_MODE_MIPI_DPHY = 16,\n\tPHY_MODE_SATA = 17,\n\tPHY_MODE_LVDS = 18,\n\tPHY_MODE_DP = 19,\n};\n\nunion phy_configure_opts {\n\tstruct phy_configure_opts_mipi_dphy mipi_dphy;\n\tstruct phy_configure_opts_dp dp;\n};\n\nstruct phy___2;\n\nstruct phy_ops {\n\tint (*init)(struct phy___2 *);\n\tint (*exit)(struct phy___2 *);\n\tint (*power_on)(struct phy___2 *);\n\tint (*power_off)(struct phy___2 *);\n\tint (*set_mode)(struct phy___2 *, enum phy_mode, int);\n\tint (*configure)(struct phy___2 *, union phy_configure_opts *);\n\tint (*validate)(struct phy___2 *, enum phy_mode, int, union phy_configure_opts *);\n\tint (*reset)(struct phy___2 *);\n\tint (*calibrate)(struct phy___2 *);\n\tvoid (*release)(struct phy___2 *);\n\tstruct module *owner;\n};\n\nstruct phy_attrs {\n\tu32 bus_width;\n\tenum phy_mode mode;\n};\n\nstruct phy___2 {\n\tstruct device dev;\n\tint id;\n\tconst struct phy_ops *ops;\n\tstruct mutex mutex;\n\tint init_count;\n\tint power_count;\n\tstruct phy_attrs attrs;\n\tstruct regulator *pwr;\n};\n\nenum {\n\tAHCI_MAX_PORTS = 32,\n\tAHCI_MAX_CLKS = 5,\n\tAHCI_MAX_SG = 168,\n\tAHCI_DMA_BOUNDARY = 4294967295,\n\tAHCI_MAX_CMDS = 32,\n\tAHCI_CMD_SZ = 32,\n\tAHCI_CMD_SLOT_SZ = 1024,\n\tAHCI_RX_FIS_SZ = 256,\n\tAHCI_CMD_TBL_CDB = 64,\n\tAHCI_CMD_TBL_HDR_SZ = 128,\n\tAHCI_CMD_TBL_SZ = 2816,\n\tAHCI_CMD_TBL_AR_SZ = 90112,\n\tAHCI_PORT_PRIV_DMA_SZ = 91392,\n\tAHCI_PORT_PRIV_FBS_DMA_SZ = 95232,\n\tAHCI_IRQ_ON_SG = 2147483648,\n\tAHCI_CMD_ATAPI = 32,\n\tAHCI_CMD_WRITE = 64,\n\tAHCI_CMD_PREFETCH = 128,\n\tAHCI_CMD_RESET = 256,\n\tAHCI_CMD_CLR_BUSY = 1024,\n\tRX_FIS_PIO_SETUP = 32,\n\tRX_FIS_D2H_REG = 64,\n\tRX_FIS_SDB = 88,\n\tRX_FIS_UNK = 96,\n\tHOST_CAP = 0,\n\tHOST_CTL = 4,\n\tHOST_IRQ_STAT = 8,\n\tHOST_PORTS_IMPL = 12,\n\tHOST_VERSION = 16,\n\tHOST_EM_LOC = 28,\n\tHOST_EM_CTL = 32,\n\tHOST_CAP2 = 36,\n\tHOST_RESET = 1,\n\tHOST_IRQ_EN = 2,\n\tHOST_MRSM = 4,\n\tHOST_AHCI_EN = 2147483648,\n\tHOST_CAP_SXS = 32,\n\tHOST_CAP_EMS = 64,\n\tHOST_CAP_CCC = 128,\n\tHOST_CAP_PART = 8192,\n\tHOST_CAP_SSC = 16384,\n\tHOST_CAP_PIO_MULTI = 32768,\n\tHOST_CAP_FBS = 65536,\n\tHOST_CAP_PMP = 131072,\n\tHOST_CAP_ONLY = 262144,\n\tHOST_CAP_CLO = 16777216,\n\tHOST_CAP_LED = 33554432,\n\tHOST_CAP_ALPM = 67108864,\n\tHOST_CAP_SSS = 134217728,\n\tHOST_CAP_MPS = 268435456,\n\tHOST_CAP_SNTF = 536870912,\n\tHOST_CAP_NCQ = 1073741824,\n\tHOST_CAP_64 = 2147483648,\n\tHOST_CAP2_BOH = 1,\n\tHOST_CAP2_NVMHCI = 2,\n\tHOST_CAP2_APST = 4,\n\tHOST_CAP2_SDS = 8,\n\tHOST_CAP2_SADM = 16,\n\tHOST_CAP2_DESO = 32,\n\tPORT_LST_ADDR = 0,\n\tPORT_LST_ADDR_HI = 4,\n\tPORT_FIS_ADDR = 8,\n\tPORT_FIS_ADDR_HI = 12,\n\tPORT_IRQ_STAT = 16,\n\tPORT_IRQ_MASK = 20,\n\tPORT_CMD = 24,\n\tPORT_TFDATA = 32,\n\tPORT_SIG = 36,\n\tPORT_CMD_ISSUE = 56,\n\tPORT_SCR_STAT = 40,\n\tPORT_SCR_CTL = 44,\n\tPORT_SCR_ERR = 48,\n\tPORT_SCR_ACT = 52,\n\tPORT_SCR_NTF = 60,\n\tPORT_FBS = 64,\n\tPORT_DEVSLP = 68,\n\tPORT_IRQ_COLD_PRES = 2147483648,\n\tPORT_IRQ_TF_ERR = 1073741824,\n\tPORT_IRQ_HBUS_ERR = 536870912,\n\tPORT_IRQ_HBUS_DATA_ERR = 268435456,\n\tPORT_IRQ_IF_ERR = 134217728,\n\tPORT_IRQ_IF_NONFATAL = 67108864,\n\tPORT_IRQ_OVERFLOW = 16777216,\n\tPORT_IRQ_BAD_PMP = 8388608,\n\tPORT_IRQ_PHYRDY = 4194304,\n\tPORT_IRQ_DEV_ILCK = 128,\n\tPORT_IRQ_CONNECT = 64,\n\tPORT_IRQ_SG_DONE = 32,\n\tPORT_IRQ_UNK_FIS = 16,\n\tPORT_IRQ_SDB_FIS = 8,\n\tPORT_IRQ_DMAS_FIS = 4,\n\tPORT_IRQ_PIOS_FIS = 2,\n\tPORT_IRQ_D2H_REG_FIS = 1,\n\tPORT_IRQ_FREEZE = 683671632,\n\tPORT_IRQ_ERROR = 2025848912,\n\tDEF_PORT_IRQ = 2025848959,\n\tPORT_CMD_ASP = 134217728,\n\tPORT_CMD_ALPE = 67108864,\n\tPORT_CMD_ATAPI = 16777216,\n\tPORT_CMD_FBSCP = 4194304,\n\tPORT_CMD_ESP = 2097152,\n\tPORT_CMD_HPCP = 262144,\n\tPORT_CMD_PMP = 131072,\n\tPORT_CMD_LIST_ON = 32768,\n\tPORT_CMD_FIS_ON = 16384,\n\tPORT_CMD_FIS_RX = 16,\n\tPORT_CMD_CLO = 8,\n\tPORT_CMD_POWER_ON = 4,\n\tPORT_CMD_SPIN_UP = 2,\n\tPORT_CMD_START = 1,\n\tPORT_CMD_ICC_MASK = 4026531840,\n\tPORT_CMD_ICC_ACTIVE = 268435456,\n\tPORT_CMD_ICC_PARTIAL = 536870912,\n\tPORT_CMD_ICC_SLUMBER = 1610612736,\n\tPORT_FBS_DWE_OFFSET = 16,\n\tPORT_FBS_ADO_OFFSET = 12,\n\tPORT_FBS_DEV_OFFSET = 8,\n\tPORT_FBS_DEV_MASK = 3840,\n\tPORT_FBS_SDE = 4,\n\tPORT_FBS_DEC = 2,\n\tPORT_FBS_EN = 1,\n\tPORT_DEVSLP_DM_OFFSET = 25,\n\tPORT_DEVSLP_DM_MASK = 503316480,\n\tPORT_DEVSLP_DITO_OFFSET = 15,\n\tPORT_DEVSLP_MDAT_OFFSET = 10,\n\tPORT_DEVSLP_DETO_OFFSET = 2,\n\tPORT_DEVSLP_DSP = 2,\n\tPORT_DEVSLP_ADSE = 1,\n\tAHCI_HFLAG_NO_NCQ = 1,\n\tAHCI_HFLAG_IGN_IRQ_IF_ERR = 2,\n\tAHCI_HFLAG_IGN_SERR_INTERNAL = 4,\n\tAHCI_HFLAG_32BIT_ONLY = 8,\n\tAHCI_HFLAG_MV_PATA = 16,\n\tAHCI_HFLAG_NO_MSI = 32,\n\tAHCI_HFLAG_NO_PMP = 64,\n\tAHCI_HFLAG_SECT255 = 256,\n\tAHCI_HFLAG_YES_NCQ = 512,\n\tAHCI_HFLAG_NO_SUSPEND = 1024,\n\tAHCI_HFLAG_SRST_TOUT_IS_OFFLINE = 2048,\n\tAHCI_HFLAG_NO_SNTF = 4096,\n\tAHCI_HFLAG_NO_FPDMA_AA = 8192,\n\tAHCI_HFLAG_YES_FBS = 16384,\n\tAHCI_HFLAG_DELAY_ENGINE = 32768,\n\tAHCI_HFLAG_NO_DEVSLP = 131072,\n\tAHCI_HFLAG_NO_FBS = 262144,\n\tAHCI_HFLAG_MULTI_MSI = 1048576,\n\tAHCI_HFLAG_WAKE_BEFORE_STOP = 4194304,\n\tAHCI_HFLAG_YES_ALPM = 8388608,\n\tAHCI_HFLAG_NO_WRITE_TO_RO = 16777216,\n\tAHCI_HFLAG_IS_MOBILE = 33554432,\n\tAHCI_HFLAG_SUSPEND_PHYS = 67108864,\n\tAHCI_FLAG_COMMON = 393346,\n\tICH_MAP = 144,\n\tPCS_6 = 146,\n\tPCS_7 = 148,\n\tEM_MAX_SLOTS = 8,\n\tEM_MAX_RETRY = 5,\n\tEM_CTL_RST = 512,\n\tEM_CTL_TM = 256,\n\tEM_CTL_MR = 1,\n\tEM_CTL_ALHD = 67108864,\n\tEM_CTL_XMT = 33554432,\n\tEM_CTL_SMB = 16777216,\n\tEM_CTL_SGPIO = 524288,\n\tEM_CTL_SES = 262144,\n\tEM_CTL_SAFTE = 131072,\n\tEM_CTL_LED = 65536,\n\tEM_MSG_TYPE_LED = 1,\n\tEM_MSG_TYPE_SAFTE = 2,\n\tEM_MSG_TYPE_SES2 = 4,\n\tEM_MSG_TYPE_SGPIO = 8,\n};\n\nstruct ahci_cmd_hdr {\n\t__le32 opts;\n\t__le32 status;\n\t__le32 tbl_addr;\n\t__le32 tbl_addr_hi;\n\t__le32 reserved[4];\n};\n\nstruct ahci_em_priv {\n\tenum sw_activity blink_policy;\n\tstruct timer_list timer;\n\tlong unsigned int saved_activity;\n\tlong unsigned int activity;\n\tlong unsigned int led_state;\n\tstruct ata_link *link;\n};\n\nstruct ahci_port_priv {\n\tstruct ata_link *active_link;\n\tstruct ahci_cmd_hdr *cmd_slot;\n\tdma_addr_t cmd_slot_dma;\n\tvoid *cmd_tbl;\n\tdma_addr_t cmd_tbl_dma;\n\tvoid *rx_fis;\n\tdma_addr_t rx_fis_dma;\n\tunsigned int ncq_saw_d2h: 1;\n\tunsigned int ncq_saw_dmas: 1;\n\tunsigned int ncq_saw_sdb: 1;\n\tspinlock_t lock;\n\tu32 intr_mask;\n\tbool fbs_supported;\n\tbool fbs_enabled;\n\tint fbs_last_dev;\n\tstruct ahci_em_priv em_priv[8];\n\tchar *irq_desc;\n};\n\nstruct ahci_host_priv {\n\tunsigned int flags;\n\tu32 force_port_map;\n\tu32 mask_port_map;\n\tvoid *mmio;\n\tu32 cap;\n\tu32 cap2;\n\tu32 version;\n\tu32 port_map;\n\tu32 saved_cap;\n\tu32 saved_cap2;\n\tu32 saved_port_map;\n\tu32 em_loc;\n\tu32 em_buf_sz;\n\tu32 em_msg_type;\n\tu32 remapped_nvme;\n\tbool got_runtime_pm;\n\tstruct clk *clks[5];\n\tstruct reset_control *rsts;\n\tstruct regulator **target_pwrs;\n\tstruct regulator *ahci_regulator;\n\tstruct regulator *phy_regulator;\n\tstruct phy___2 **phys;\n\tunsigned int nports;\n\tvoid *plat_data;\n\tunsigned int irq;\n\tvoid (*start_engine)(struct ata_port *);\n\tint (*stop_engine)(struct ata_port *);\n\tirqreturn_t (*irq_handler)(int, void *);\n\tint (*get_irq_vector)(struct ata_host *, int);\n};\n\nenum {\n\tAHCI_PCI_BAR_STA2X11 = 0,\n\tAHCI_PCI_BAR_CAVIUM = 0,\n\tAHCI_PCI_BAR_LOONGSON = 0,\n\tAHCI_PCI_BAR_ENMOTUS = 2,\n\tAHCI_PCI_BAR_CAVIUM_GEN5 = 4,\n\tAHCI_PCI_BAR_STANDARD = 5,\n};\n\nenum board_ids {\n\tboard_ahci = 0,\n\tboard_ahci_ign_iferr = 1,\n\tboard_ahci_mobile = 2,\n\tboard_ahci_nomsi = 3,\n\tboard_ahci_noncq = 4,\n\tboard_ahci_nosntf = 5,\n\tboard_ahci_yes_fbs = 6,\n\tboard_ahci_al = 7,\n\tboard_ahci_avn = 8,\n\tboard_ahci_mcp65 = 9,\n\tboard_ahci_mcp77 = 10,\n\tboard_ahci_mcp89 = 11,\n\tboard_ahci_mv = 12,\n\tboard_ahci_sb600 = 13,\n\tboard_ahci_sb700 = 14,\n\tboard_ahci_vt8251 = 15,\n\tboard_ahci_pcs7 = 16,\n\tboard_ahci_mcp_linux = 9,\n\tboard_ahci_mcp67 = 9,\n\tboard_ahci_mcp73 = 9,\n\tboard_ahci_mcp79 = 10,\n};\n\nstruct ahci_sg {\n\t__le32 addr;\n\t__le32 addr_hi;\n\t__le32 reserved;\n\t__le32 flags_size;\n};\n\nenum {\n\tPIIX_IOCFG = 84,\n\tICH5_PMR = 144,\n\tICH5_PCS = 146,\n\tPIIX_SIDPR_BAR = 5,\n\tPIIX_SIDPR_LEN = 16,\n\tPIIX_SIDPR_IDX = 0,\n\tPIIX_SIDPR_DATA = 4,\n\tPIIX_FLAG_CHECKINTR = 268435456,\n\tPIIX_FLAG_SIDPR = 536870912,\n\tPIIX_PATA_FLAGS = 1,\n\tPIIX_SATA_FLAGS = 268435458,\n\tPIIX_FLAG_PIO16 = 1073741824,\n\tPIIX_80C_PRI = 48,\n\tPIIX_80C_SEC = 192,\n\tP0 = 0,\n\tP1 = 1,\n\tP2 = 2,\n\tP3 = 3,\n\tIDE = 4294967295,\n\tNA = 4294967294,\n\tRV = 4294967293,\n\tPIIX_AHCI_DEVICE = 6,\n\tPIIX_HOST_BROKEN_SUSPEND = 16777216,\n};\n\nenum piix_controller_ids {\n\tpiix_pata_mwdma = 0,\n\tpiix_pata_33 = 1,\n\tich_pata_33 = 2,\n\tich_pata_66 = 3,\n\tich_pata_100 = 4,\n\tich_pata_100_nomwdma1 = 5,\n\tich5_sata = 6,\n\tich6_sata = 7,\n\tich6m_sata = 8,\n\tich8_sata = 9,\n\tich8_2port_sata = 10,\n\tich8m_apple_sata = 11,\n\ttolapai_sata = 12,\n\tpiix_pata_vmw = 13,\n\tich8_sata_snb = 14,\n\tich8_2port_sata_snb = 15,\n\tich8_2port_sata_byt = 16,\n};\n\nstruct piix_map_db {\n\tconst u32 mask;\n\tconst u16 port_enable;\n\tconst int map[0];\n};\n\nstruct piix_host_priv {\n\tconst int *map;\n\tu32 saved_iocfg;\n\tvoid *sidpr;\n};\n\nstruct ich_laptop {\n\tu16 device;\n\tu16 subvendor;\n\tu16 subdevice;\n};\n\nenum {\n\tD0TIM = 128,\n\tD1TIM = 132,\n\tPM = 7,\n\tMDM = 768,\n\tUDM = 458752,\n\tPPE = 1073741824,\n\tUSD = 2147483648,\n};\n\nstruct ethtool_cmd {\n\t__u32 cmd;\n\t__u32 supported;\n\t__u32 advertising;\n\t__u16 speed;\n\t__u8 duplex;\n\t__u8 port;\n\t__u8 phy_address;\n\t__u8 transceiver;\n\t__u8 autoneg;\n\t__u8 mdio_support;\n\t__u32 maxtxpkt;\n\t__u32 maxrxpkt;\n\t__u16 speed_hi;\n\t__u8 eth_tp_mdix;\n\t__u8 eth_tp_mdix_ctrl;\n\t__u32 lp_advertising;\n\t__u32 reserved[2];\n};\n\nenum netdev_state_t {\n\t__LINK_STATE_START = 0,\n\t__LINK_STATE_PRESENT = 1,\n\t__LINK_STATE_NOCARRIER = 2,\n\t__LINK_STATE_LINKWATCH_PENDING = 3,\n\t__LINK_STATE_DORMANT = 4,\n\t__LINK_STATE_TESTING = 5,\n};\n\nstruct mii_ioctl_data {\n\t__u16 phy_id;\n\t__u16 reg_num;\n\t__u16 val_in;\n\t__u16 val_out;\n};\n\nstruct mii_if_info {\n\tint phy_id;\n\tint advertising;\n\tint phy_id_mask;\n\tint reg_num_mask;\n\tunsigned int full_duplex: 1;\n\tunsigned int force_media: 1;\n\tunsigned int supports_gmii: 1;\n\tstruct net_device *dev;\n\tint (*mdio_read)(struct net_device *, int, int);\n\tvoid (*mdio_write)(struct net_device *, int, int, int);\n};\n\nstruct devprobe2 {\n\tstruct net_device * (*probe)(int);\n\tint status;\n};\n\nenum {\n\tNETIF_F_SG_BIT = 0,\n\tNETIF_F_IP_CSUM_BIT = 1,\n\t__UNUSED_NETIF_F_1 = 2,\n\tNETIF_F_HW_CSUM_BIT = 3,\n\tNETIF_F_IPV6_CSUM_BIT = 4,\n\tNETIF_F_HIGHDMA_BIT = 5,\n\tNETIF_F_FRAGLIST_BIT = 6,\n\tNETIF_F_HW_VLAN_CTAG_TX_BIT = 7,\n\tNETIF_F_HW_VLAN_CTAG_RX_BIT = 8,\n\tNETIF_F_HW_VLAN_CTAG_FILTER_BIT = 9,\n\tNETIF_F_VLAN_CHALLENGED_BIT = 10,\n\tNETIF_F_GSO_BIT = 11,\n\tNETIF_F_LLTX_BIT = 12,\n\tNETIF_F_NETNS_LOCAL_BIT = 13,\n\tNETIF_F_GRO_BIT = 14,\n\tNETIF_F_LRO_BIT = 15,\n\tNETIF_F_GSO_SHIFT = 16,\n\tNETIF_F_TSO_BIT = 16,\n\tNETIF_F_GSO_ROBUST_BIT = 17,\n\tNETIF_F_TSO_ECN_BIT = 18,\n\tNETIF_F_TSO_MANGLEID_BIT = 19,\n\tNETIF_F_TSO6_BIT = 20,\n\tNETIF_F_FSO_BIT = 21,\n\tNETIF_F_GSO_GRE_BIT = 22,\n\tNETIF_F_GSO_GRE_CSUM_BIT = 23,\n\tNETIF_F_GSO_IPXIP4_BIT = 24,\n\tNETIF_F_GSO_IPXIP6_BIT = 25,\n\tNETIF_F_GSO_UDP_TUNNEL_BIT = 26,\n\tNETIF_F_GSO_UDP_TUNNEL_CSUM_BIT = 27,\n\tNETIF_F_GSO_PARTIAL_BIT = 28,\n\tNETIF_F_GSO_TUNNEL_REMCSUM_BIT = 29,\n\tNETIF_F_GSO_SCTP_BIT = 30,\n\tNETIF_F_GSO_ESP_BIT = 31,\n\tNETIF_F_GSO_UDP_BIT = 32,\n\tNETIF_F_GSO_UDP_L4_BIT = 33,\n\tNETIF_F_GSO_FRAGLIST_BIT = 34,\n\tNETIF_F_GSO_LAST = 34,\n\tNETIF_F_FCOE_CRC_BIT = 35,\n\tNETIF_F_SCTP_CRC_BIT = 36,\n\tNETIF_F_FCOE_MTU_BIT = 37,\n\tNETIF_F_NTUPLE_BIT = 38,\n\tNETIF_F_RXHASH_BIT = 39,\n\tNETIF_F_RXCSUM_BIT = 40,\n\tNETIF_F_NOCACHE_COPY_BIT = 41,\n\tNETIF_F_LOOPBACK_BIT = 42,\n\tNETIF_F_RXFCS_BIT = 43,\n\tNETIF_F_RXALL_BIT = 44,\n\tNETIF_F_HW_VLAN_STAG_TX_BIT = 45,\n\tNETIF_F_HW_VLAN_STAG_RX_BIT = 46,\n\tNETIF_F_HW_VLAN_STAG_FILTER_BIT = 47,\n\tNETIF_F_HW_L2FW_DOFFLOAD_BIT = 48,\n\tNETIF_F_HW_TC_BIT = 49,\n\tNETIF_F_HW_ESP_BIT = 50,\n\tNETIF_F_HW_ESP_TX_CSUM_BIT = 51,\n\tNETIF_F_RX_UDP_TUNNEL_PORT_BIT = 52,\n\tNETIF_F_HW_TLS_TX_BIT = 53,\n\tNETIF_F_HW_TLS_RX_BIT = 54,\n\tNETIF_F_GRO_HW_BIT = 55,\n\tNETIF_F_HW_TLS_RECORD_BIT = 56,\n\tNETIF_F_GRO_FRAGLIST_BIT = 57,\n\tNETIF_F_HW_MACSEC_BIT = 58,\n\tNETDEV_FEATURE_COUNT = 59,\n};\n\nenum {\n\tSKBTX_HW_TSTAMP = 1,\n\tSKBTX_SW_TSTAMP = 2,\n\tSKBTX_IN_PROGRESS = 4,\n\tSKBTX_DEV_ZEROCOPY = 8,\n\tSKBTX_WIFI_STATUS = 16,\n\tSKBTX_SHARED_FRAG = 32,\n\tSKBTX_SCHED_TSTAMP = 64,\n};\n\nenum netdev_priv_flags {\n\tIFF_802_1Q_VLAN = 1,\n\tIFF_EBRIDGE = 2,\n\tIFF_BONDING = 4,\n\tIFF_ISATAP = 8,\n\tIFF_WAN_HDLC = 16,\n\tIFF_XMIT_DST_RELEASE = 32,\n\tIFF_DONT_BRIDGE = 64,\n\tIFF_DISABLE_NETPOLL = 128,\n\tIFF_MACVLAN_PORT = 256,\n\tIFF_BRIDGE_PORT = 512,\n\tIFF_OVS_DATAPATH = 1024,\n\tIFF_TX_SKB_SHARING = 2048,\n\tIFF_UNICAST_FLT = 4096,\n\tIFF_TEAM_PORT = 8192,\n\tIFF_SUPP_NOFCS = 16384,\n\tIFF_LIVE_ADDR_CHANGE = 32768,\n\tIFF_MACVLAN = 65536,\n\tIFF_XMIT_DST_RELEASE_PERM = 131072,\n\tIFF_L3MDEV_MASTER = 262144,\n\tIFF_NO_QUEUE = 524288,\n\tIFF_OPENVSWITCH = 1048576,\n\tIFF_L3MDEV_SLAVE = 2097152,\n\tIFF_TEAM = 4194304,\n\tIFF_RXFH_CONFIGURED = 8388608,\n\tIFF_PHONY_HEADROOM = 16777216,\n\tIFF_MACSEC = 33554432,\n\tIFF_NO_RX_HANDLER = 67108864,\n\tIFF_FAILOVER = 134217728,\n\tIFF_FAILOVER_SLAVE = 268435456,\n\tIFF_L3MDEV_RX_HANDLER = 536870912,\n\tIFF_LIVE_RENAME_OK = 1073741824,\n};\n\nstruct netpoll;\n\nstruct netpoll_info {\n\trefcount_t refcnt;\n\tstruct semaphore dev_lock;\n\tstruct sk_buff_head txq;\n\tstruct delayed_work tx_work;\n\tstruct netpoll *netpoll;\n\tstruct callback_head rcu;\n};\n\nunion inet_addr {\n\t__u32 all[4];\n\t__be32 ip;\n\t__be32 ip6[4];\n\tstruct in_addr in;\n\tstruct in6_addr in6;\n};\n\nstruct netpoll {\n\tstruct net_device *dev;\n\tchar dev_name[16];\n\tconst char *name;\n\tunion inet_addr local_ip;\n\tunion inet_addr remote_ip;\n\tbool ipv6;\n\tu16 local_port;\n\tu16 remote_port;\n\tu8 remote_mac[6];\n};\n\nstruct netconsole_target {\n\tstruct list_head list;\n\tbool enabled;\n\tbool extended;\n\tstruct netpoll np;\n};\n\nstruct mdio_board_info {\n\tconst char *bus_id;\n\tchar modalias[32];\n\tint mdio_addr;\n\tconst void *platform_data;\n};\n\nstruct mdio_board_entry {\n\tstruct list_head list;\n\tstruct mdio_board_info board_info;\n};\n\nenum {\n\tETHTOOL_MSG_KERNEL_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET_REPLY = 1,\n\tETHTOOL_MSG_LINKINFO_GET_REPLY = 2,\n\tETHTOOL_MSG_LINKINFO_NTF = 3,\n\tETHTOOL_MSG_LINKMODES_GET_REPLY = 4,\n\tETHTOOL_MSG_LINKMODES_NTF = 5,\n\tETHTOOL_MSG_LINKSTATE_GET_REPLY = 6,\n\tETHTOOL_MSG_DEBUG_GET_REPLY = 7,\n\tETHTOOL_MSG_DEBUG_NTF = 8,\n\tETHTOOL_MSG_WOL_GET_REPLY = 9,\n\tETHTOOL_MSG_WOL_NTF = 10,\n\tETHTOOL_MSG_FEATURES_GET_REPLY = 11,\n\tETHTOOL_MSG_FEATURES_SET_REPLY = 12,\n\tETHTOOL_MSG_FEATURES_NTF = 13,\n\tETHTOOL_MSG_PRIVFLAGS_GET_REPLY = 14,\n\tETHTOOL_MSG_PRIVFLAGS_NTF = 15,\n\tETHTOOL_MSG_RINGS_GET_REPLY = 16,\n\tETHTOOL_MSG_RINGS_NTF = 17,\n\tETHTOOL_MSG_CHANNELS_GET_REPLY = 18,\n\tETHTOOL_MSG_CHANNELS_NTF = 19,\n\tETHTOOL_MSG_COALESCE_GET_REPLY = 20,\n\tETHTOOL_MSG_COALESCE_NTF = 21,\n\tETHTOOL_MSG_PAUSE_GET_REPLY = 22,\n\tETHTOOL_MSG_PAUSE_NTF = 23,\n\tETHTOOL_MSG_EEE_GET_REPLY = 24,\n\tETHTOOL_MSG_EEE_NTF = 25,\n\tETHTOOL_MSG_TSINFO_GET_REPLY = 26,\n\tETHTOOL_MSG_CABLE_TEST_NTF = 27,\n\tETHTOOL_MSG_CABLE_TEST_TDR_NTF = 28,\n\t__ETHTOOL_MSG_KERNEL_CNT = 29,\n\tETHTOOL_MSG_KERNEL_MAX = 28,\n};\n\nstruct phy_setting {\n\tu32 speed;\n\tu8 duplex;\n\tu8 bit;\n};\n\nstruct phy_fixup {\n\tstruct list_head list;\n\tchar bus_id[64];\n\tu32 phy_uid;\n\tu32 phy_uid_mask;\n\tint (*run)(struct phy_device *);\n};\n\nstruct sfp_eeprom_base {\n\tu8 phys_id;\n\tu8 phys_ext_id;\n\tu8 connector;\n\tu8 if_1x_copper_passive: 1;\n\tu8 if_1x_copper_active: 1;\n\tu8 if_1x_lx: 1;\n\tu8 if_1x_sx: 1;\n\tu8 e10g_base_sr: 1;\n\tu8 e10g_base_lr: 1;\n\tu8 e10g_base_lrm: 1;\n\tu8 e10g_base_er: 1;\n\tu8 sonet_oc3_short_reach: 1;\n\tu8 sonet_oc3_smf_intermediate_reach: 1;\n\tu8 sonet_oc3_smf_long_reach: 1;\n\tu8 unallocated_5_3: 1;\n\tu8 sonet_oc12_short_reach: 1;\n\tu8 sonet_oc12_smf_intermediate_reach: 1;\n\tu8 sonet_oc12_smf_long_reach: 1;\n\tu8 unallocated_5_7: 1;\n\tu8 sonet_oc48_short_reach: 1;\n\tu8 sonet_oc48_intermediate_reach: 1;\n\tu8 sonet_oc48_long_reach: 1;\n\tu8 sonet_reach_bit2: 1;\n\tu8 sonet_reach_bit1: 1;\n\tu8 sonet_oc192_short_reach: 1;\n\tu8 escon_smf_1310_laser: 1;\n\tu8 escon_mmf_1310_led: 1;\n\tu8 e1000_base_sx: 1;\n\tu8 e1000_base_lx: 1;\n\tu8 e1000_base_cx: 1;\n\tu8 e1000_base_t: 1;\n\tu8 e100_base_lx: 1;\n\tu8 e100_base_fx: 1;\n\tu8 e_base_bx10: 1;\n\tu8 e_base_px: 1;\n\tu8 fc_tech_electrical_inter_enclosure: 1;\n\tu8 fc_tech_lc: 1;\n\tu8 fc_tech_sa: 1;\n\tu8 fc_ll_m: 1;\n\tu8 fc_ll_l: 1;\n\tu8 fc_ll_i: 1;\n\tu8 fc_ll_s: 1;\n\tu8 fc_ll_v: 1;\n\tu8 unallocated_8_0: 1;\n\tu8 unallocated_8_1: 1;\n\tu8 sfp_ct_passive: 1;\n\tu8 sfp_ct_active: 1;\n\tu8 fc_tech_ll: 1;\n\tu8 fc_tech_sl: 1;\n\tu8 fc_tech_sn: 1;\n\tu8 fc_tech_electrical_intra_enclosure: 1;\n\tu8 fc_media_sm: 1;\n\tu8 unallocated_9_1: 1;\n\tu8 fc_media_m5: 1;\n\tu8 fc_media_m6: 1;\n\tu8 fc_media_tv: 1;\n\tu8 fc_media_mi: 1;\n\tu8 fc_media_tp: 1;\n\tu8 fc_media_tw: 1;\n\tu8 fc_speed_100: 1;\n\tu8 unallocated_10_1: 1;\n\tu8 fc_speed_200: 1;\n\tu8 fc_speed_3200: 1;\n\tu8 fc_speed_400: 1;\n\tu8 fc_speed_1600: 1;\n\tu8 fc_speed_800: 1;\n\tu8 fc_speed_1200: 1;\n\tu8 encoding;\n\tu8 br_nominal;\n\tu8 rate_id;\n\tu8 link_len[6];\n\tchar vendor_name[16];\n\tu8 extended_cc;\n\tchar vendor_oui[3];\n\tchar vendor_pn[16];\n\tchar vendor_rev[4];\n\tunion {\n\t\t__be16 optical_wavelength;\n\t\t__be16 cable_compliance;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 reserved60_2: 6;\n\t\t\tu8 reserved61: 8;\n\t\t} passive;\n\t\tstruct {\n\t\t\tu8 sff8431_app_e: 1;\n\t\t\tu8 fc_pi_4_app_h: 1;\n\t\t\tu8 sff8431_lim: 1;\n\t\t\tu8 fc_pi_4_lim: 1;\n\t\t\tu8 reserved60_4: 4;\n\t\t\tu8 reserved61: 8;\n\t\t} active;\n\t};\n\tu8 reserved62;\n\tu8 cc_base;\n};\n\nstruct sfp_eeprom_ext {\n\t__be16 options;\n\tu8 br_max;\n\tu8 br_min;\n\tchar vendor_sn[16];\n\tchar datecode[8];\n\tu8 diagmon;\n\tu8 enhopts;\n\tu8 sff8472_compliance;\n\tu8 cc_ext;\n};\n\nstruct sfp_eeprom_id {\n\tstruct sfp_eeprom_base base;\n\tstruct sfp_eeprom_ext ext;\n};\n\nstruct sfp_upstream_ops {\n\tvoid (*attach)(void *, struct sfp_bus *);\n\tvoid (*detach)(void *, struct sfp_bus *);\n\tint (*module_insert)(void *, const struct sfp_eeprom_id *);\n\tvoid (*module_remove)(void *);\n\tint (*module_start)(void *);\n\tvoid (*module_stop)(void *);\n\tvoid (*link_down)(void *);\n\tvoid (*link_up)(void *);\n\tint (*connect_phy)(void *, struct phy_device *);\n\tvoid (*disconnect_phy)(void *);\n};\n\nstruct trace_event_raw_mdio_access {\n\tstruct trace_entry ent;\n\tchar busid[61];\n\tchar read;\n\tu8 addr;\n\tu16 val;\n\tunsigned int regnum;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_mdio_access {};\n\ntypedef void (*btf_trace_mdio_access)(void *, struct mii_bus *, char, u8, unsigned int, u16, int);\n\nstruct mdio_bus_stat_attr {\n\tint addr;\n\tunsigned int field_offset;\n};\n\nstruct mdio_driver {\n\tstruct mdio_driver_common mdiodrv;\n\tint (*probe)(struct mdio_device *);\n\tvoid (*remove)(struct mdio_device *);\n};\n\nstruct mdio_device_id {\n\t__u32 phy_id;\n\t__u32 phy_id_mask;\n};\n\nenum {\n\tSKB_GSO_TCPV4 = 1,\n\tSKB_GSO_DODGY = 2,\n\tSKB_GSO_TCP_ECN = 4,\n\tSKB_GSO_TCP_FIXEDID = 8,\n\tSKB_GSO_TCPV6 = 16,\n\tSKB_GSO_FCOE = 32,\n\tSKB_GSO_GRE = 64,\n\tSKB_GSO_GRE_CSUM = 128,\n\tSKB_GSO_IPXIP4 = 256,\n\tSKB_GSO_IPXIP6 = 512,\n\tSKB_GSO_UDP_TUNNEL = 1024,\n\tSKB_GSO_UDP_TUNNEL_CSUM = 2048,\n\tSKB_GSO_PARTIAL = 4096,\n\tSKB_GSO_TUNNEL_REMCSUM = 8192,\n\tSKB_GSO_SCTP = 16384,\n\tSKB_GSO_ESP = 32768,\n\tSKB_GSO_UDP = 65536,\n\tSKB_GSO_UDP_L4 = 131072,\n\tSKB_GSO_FRAGLIST = 262144,\n};\n\nenum ethtool_stringset {\n\tETH_SS_TEST = 0,\n\tETH_SS_STATS = 1,\n\tETH_SS_PRIV_FLAGS = 2,\n\tETH_SS_NTUPLE_FILTERS = 3,\n\tETH_SS_FEATURES = 4,\n\tETH_SS_RSS_HASH_FUNCS = 5,\n\tETH_SS_TUNABLES = 6,\n\tETH_SS_PHY_STATS = 7,\n\tETH_SS_PHY_TUNABLES = 8,\n\tETH_SS_LINK_MODES = 9,\n\tETH_SS_MSG_CLASSES = 10,\n\tETH_SS_WOL_MODES = 11,\n\tETH_SS_SOF_TIMESTAMPING = 12,\n\tETH_SS_TS_TX_TYPES = 13,\n\tETH_SS_TS_RX_FILTERS = 14,\n\tETH_SS_COUNT = 15,\n};\n\nenum ethtool_test_flags {\n\tETH_TEST_FL_OFFLINE = 1,\n\tETH_TEST_FL_FAILED = 2,\n\tETH_TEST_FL_EXTERNAL_LB = 4,\n\tETH_TEST_FL_EXTERNAL_LB_DONE = 8,\n};\n\nenum {\n\tETH_RSS_HASH_TOP_BIT = 0,\n\tETH_RSS_HASH_XOR_BIT = 1,\n\tETH_RSS_HASH_CRC32_BIT = 2,\n\tETH_RSS_HASH_FUNCS_COUNT = 3,\n};\n\nstruct netdev_hw_addr {\n\tstruct list_head list;\n\tunsigned char addr[32];\n\tunsigned char type;\n\tbool global_use;\n\tint sync_cnt;\n\tint refcount;\n\tint synced;\n\tstruct callback_head callback_head;\n};\n\nenum netdev_queue_state_t {\n\t__QUEUE_STATE_DRV_XOFF = 0,\n\t__QUEUE_STATE_STACK_XOFF = 1,\n\t__QUEUE_STATE_FROZEN = 2,\n};\n\nenum skb_free_reason {\n\tSKB_REASON_CONSUMED = 0,\n\tSKB_REASON_DROPPED = 1,\n};\n\nenum {\n\tSOF_TIMESTAMPING_TX_HARDWARE = 1,\n\tSOF_TIMESTAMPING_TX_SOFTWARE = 2,\n\tSOF_TIMESTAMPING_RX_HARDWARE = 4,\n\tSOF_TIMESTAMPING_RX_SOFTWARE = 8,\n\tSOF_TIMESTAMPING_SOFTWARE = 16,\n\tSOF_TIMESTAMPING_SYS_HARDWARE = 32,\n\tSOF_TIMESTAMPING_RAW_HARDWARE = 64,\n\tSOF_TIMESTAMPING_OPT_ID = 128,\n\tSOF_TIMESTAMPING_TX_SCHED = 256,\n\tSOF_TIMESTAMPING_TX_ACK = 512,\n\tSOF_TIMESTAMPING_OPT_CMSG = 1024,\n\tSOF_TIMESTAMPING_OPT_TSONLY = 2048,\n\tSOF_TIMESTAMPING_OPT_STATS = 4096,\n\tSOF_TIMESTAMPING_OPT_PKTINFO = 8192,\n\tSOF_TIMESTAMPING_OPT_TX_SWHW = 16384,\n\tSOF_TIMESTAMPING_LAST = 16384,\n\tSOF_TIMESTAMPING_MASK = 32767,\n};\n\nstruct hwtstamp_config {\n\tint flags;\n\tint tx_type;\n\tint rx_filter;\n};\n\nenum hwtstamp_tx_types {\n\tHWTSTAMP_TX_OFF = 0,\n\tHWTSTAMP_TX_ON = 1,\n\tHWTSTAMP_TX_ONESTEP_SYNC = 2,\n\tHWTSTAMP_TX_ONESTEP_P2P = 3,\n\t__HWTSTAMP_TX_CNT = 4,\n};\n\nenum hwtstamp_rx_filters {\n\tHWTSTAMP_FILTER_NONE = 0,\n\tHWTSTAMP_FILTER_ALL = 1,\n\tHWTSTAMP_FILTER_SOME = 2,\n\tHWTSTAMP_FILTER_PTP_V1_L4_EVENT = 3,\n\tHWTSTAMP_FILTER_PTP_V1_L4_SYNC = 4,\n\tHWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ = 5,\n\tHWTSTAMP_FILTER_PTP_V2_L4_EVENT = 6,\n\tHWTSTAMP_FILTER_PTP_V2_L4_SYNC = 7,\n\tHWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ = 8,\n\tHWTSTAMP_FILTER_PTP_V2_L2_EVENT = 9,\n\tHWTSTAMP_FILTER_PTP_V2_L2_SYNC = 10,\n\tHWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ = 11,\n\tHWTSTAMP_FILTER_PTP_V2_EVENT = 12,\n\tHWTSTAMP_FILTER_PTP_V2_SYNC = 13,\n\tHWTSTAMP_FILTER_PTP_V2_DELAY_REQ = 14,\n\tHWTSTAMP_FILTER_NTP_ALL = 15,\n\t__HWTSTAMP_FILTER_CNT = 16,\n};\n\nstruct sensor_device_attribute {\n\tstruct device_attribute dev_attr;\n\tint index;\n};\n\nstruct ptp_clock_time {\n\t__s64 sec;\n\t__u32 nsec;\n\t__u32 reserved;\n};\n\nstruct ptp_extts_request {\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nstruct ptp_perout_request {\n\tstruct ptp_clock_time start;\n\tstruct ptp_clock_time period;\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[4];\n};\n\nenum ptp_pin_function {\n\tPTP_PF_NONE = 0,\n\tPTP_PF_EXTTS = 1,\n\tPTP_PF_PEROUT = 2,\n\tPTP_PF_PHYSYNC = 3,\n};\n\nstruct ptp_pin_desc {\n\tchar name[64];\n\tunsigned int index;\n\tunsigned int func;\n\tunsigned int chan;\n\tunsigned int rsv[5];\n};\n\nstruct ptp_clock_request {\n\tenum {\n\t\tPTP_CLK_REQ_EXTTS = 0,\n\t\tPTP_CLK_REQ_PEROUT = 1,\n\t\tPTP_CLK_REQ_PPS = 2,\n\t} type;\n\tunion {\n\t\tstruct ptp_extts_request extts;\n\t\tstruct ptp_perout_request perout;\n\t};\n};\n\nstruct ptp_system_timestamp {\n\tstruct timespec64 pre_ts;\n\tstruct timespec64 post_ts;\n};\n\nstruct ptp_clock_info {\n\tstruct module *owner;\n\tchar name[16];\n\ts32 max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint n_pins;\n\tint pps;\n\tstruct ptp_pin_desc *pin_config;\n\tint (*adjfine)(struct ptp_clock_info *, long int);\n\tint (*adjfreq)(struct ptp_clock_info *, s32);\n\tint (*adjphase)(struct ptp_clock_info *, s32);\n\tint (*adjtime)(struct ptp_clock_info *, s64);\n\tint (*gettime64)(struct ptp_clock_info *, struct timespec64 *);\n\tint (*gettimex64)(struct ptp_clock_info *, struct timespec64 *, struct ptp_system_timestamp *);\n\tint (*getcrosststamp)(struct ptp_clock_info *, struct system_device_crosststamp *);\n\tint (*settime64)(struct ptp_clock_info *, const struct timespec64 *);\n\tint (*enable)(struct ptp_clock_info *, struct ptp_clock_request *, int);\n\tint (*verify)(struct ptp_clock_info *, unsigned int, enum ptp_pin_function, unsigned int);\n\tlong int (*do_aux_work)(struct ptp_clock_info *);\n};\n\nstruct tg3_tx_buffer_desc {\n\tu32 addr_hi;\n\tu32 addr_lo;\n\tu32 len_flags;\n\tu32 vlan_tag;\n};\n\nstruct tg3_rx_buffer_desc {\n\tu32 addr_hi;\n\tu32 addr_lo;\n\tu32 idx_len;\n\tu32 type_flags;\n\tu32 ip_tcp_csum;\n\tu32 err_vlan;\n\tu32 reserved;\n\tu32 opaque;\n};\n\nstruct tg3_ext_rx_buffer_desc {\n\tstruct {\n\t\tu32 addr_hi;\n\t\tu32 addr_lo;\n\t} addrlist[3];\n\tu32 len2_len1;\n\tu32 resv_len3;\n\tstruct tg3_rx_buffer_desc std;\n};\n\nstruct tg3_internal_buffer_desc {\n\tu32 addr_hi;\n\tu32 addr_lo;\n\tu32 nic_mbuf;\n\tu16 len;\n\tu16 cqid_sqid;\n\tu32 flags;\n\tu32 __cookie1;\n\tu32 __cookie2;\n\tu32 __cookie3;\n};\n\nstruct tg3_hw_status {\n\tu32 status;\n\tu32 status_tag;\n\tu16 rx_jumbo_consumer;\n\tu16 rx_consumer;\n\tu16 rx_mini_consumer;\n\tu16 reserved;\n\tstruct {\n\t\tu16 rx_producer;\n\t\tu16 tx_consumer;\n\t} idx[16];\n};\n\ntypedef struct {\n\tu32 high;\n\tu32 low;\n} tg3_stat64_t;\n\nstruct tg3_hw_stats {\n\tu8 __reserved0[256];\n\ttg3_stat64_t rx_octets;\n\tu64 __reserved1;\n\ttg3_stat64_t rx_fragments;\n\ttg3_stat64_t rx_ucast_packets;\n\ttg3_stat64_t rx_mcast_packets;\n\ttg3_stat64_t rx_bcast_packets;\n\ttg3_stat64_t rx_fcs_errors;\n\ttg3_stat64_t rx_align_errors;\n\ttg3_stat64_t rx_xon_pause_rcvd;\n\ttg3_stat64_t rx_xoff_pause_rcvd;\n\ttg3_stat64_t rx_mac_ctrl_rcvd;\n\ttg3_stat64_t rx_xoff_entered;\n\ttg3_stat64_t rx_frame_too_long_errors;\n\ttg3_stat64_t rx_jabbers;\n\ttg3_stat64_t rx_undersize_packets;\n\ttg3_stat64_t rx_in_length_errors;\n\ttg3_stat64_t rx_out_length_errors;\n\ttg3_stat64_t rx_64_or_less_octet_packets;\n\ttg3_stat64_t rx_65_to_127_octet_packets;\n\ttg3_stat64_t rx_128_to_255_octet_packets;\n\ttg3_stat64_t rx_256_to_511_octet_packets;\n\ttg3_stat64_t rx_512_to_1023_octet_packets;\n\ttg3_stat64_t rx_1024_to_1522_octet_packets;\n\ttg3_stat64_t rx_1523_to_2047_octet_packets;\n\ttg3_stat64_t rx_2048_to_4095_octet_packets;\n\ttg3_stat64_t rx_4096_to_8191_octet_packets;\n\ttg3_stat64_t rx_8192_to_9022_octet_packets;\n\tu64 __unused0[37];\n\ttg3_stat64_t tx_octets;\n\tu64 __reserved2;\n\ttg3_stat64_t tx_collisions;\n\ttg3_stat64_t tx_xon_sent;\n\ttg3_stat64_t tx_xoff_sent;\n\ttg3_stat64_t tx_flow_control;\n\ttg3_stat64_t tx_mac_errors;\n\ttg3_stat64_t tx_single_collisions;\n\ttg3_stat64_t tx_mult_collisions;\n\ttg3_stat64_t tx_deferred;\n\tu64 __reserved3;\n\ttg3_stat64_t tx_excessive_collisions;\n\ttg3_stat64_t tx_late_collisions;\n\ttg3_stat64_t tx_collide_2times;\n\ttg3_stat64_t tx_collide_3times;\n\ttg3_stat64_t tx_collide_4times;\n\ttg3_stat64_t tx_collide_5times;\n\ttg3_stat64_t tx_collide_6times;\n\ttg3_stat64_t tx_collide_7times;\n\ttg3_stat64_t tx_collide_8times;\n\ttg3_stat64_t tx_collide_9times;\n\ttg3_stat64_t tx_collide_10times;\n\ttg3_stat64_t tx_collide_11times;\n\ttg3_stat64_t tx_collide_12times;\n\ttg3_stat64_t tx_collide_13times;\n\ttg3_stat64_t tx_collide_14times;\n\ttg3_stat64_t tx_collide_15times;\n\ttg3_stat64_t tx_ucast_packets;\n\ttg3_stat64_t tx_mcast_packets;\n\ttg3_stat64_t tx_bcast_packets;\n\ttg3_stat64_t tx_carrier_sense_errors;\n\ttg3_stat64_t tx_discards;\n\ttg3_stat64_t tx_errors;\n\tu64 __unused1[31];\n\ttg3_stat64_t COS_rx_packets[16];\n\ttg3_stat64_t COS_rx_filter_dropped;\n\ttg3_stat64_t dma_writeq_full;\n\ttg3_stat64_t dma_write_prioq_full;\n\ttg3_stat64_t rxbds_empty;\n\ttg3_stat64_t rx_discards;\n\ttg3_stat64_t rx_errors;\n\ttg3_stat64_t rx_threshold_hit;\n\tu64 __unused2[9];\n\ttg3_stat64_t COS_out_packets[16];\n\ttg3_stat64_t dma_readq_full;\n\ttg3_stat64_t dma_read_prioq_full;\n\ttg3_stat64_t tx_comp_queue_full;\n\ttg3_stat64_t ring_set_send_prod_index;\n\ttg3_stat64_t ring_status_update;\n\ttg3_stat64_t nic_irqs;\n\ttg3_stat64_t nic_avoided_irqs;\n\ttg3_stat64_t nic_tx_threshold_hit;\n\ttg3_stat64_t mbuf_lwm_thresh_hit;\n\tu8 __reserved4[312];\n};\n\nstruct tg3_ocir {\n\tu32 signature;\n\tu16 version_flags;\n\tu16 refresh_int;\n\tu32 refresh_tmr;\n\tu32 update_tmr;\n\tu32 dst_base_addr;\n\tu16 src_hdr_offset;\n\tu16 src_hdr_length;\n\tu16 src_data_offset;\n\tu16 src_data_length;\n\tu16 dst_hdr_offset;\n\tu16 dst_data_offset;\n\tu16 dst_reg_upd_offset;\n\tu16 dst_sem_offset;\n\tu32 reserved1[2];\n\tu32 port0_flags;\n\tu32 port1_flags;\n\tu32 port2_flags;\n\tu32 port3_flags;\n\tu32 reserved2[1];\n};\n\nstruct ring_info {\n\tu8 *data;\n\tdma_addr_t mapping;\n};\n\nstruct tg3_tx_ring_info {\n\tstruct sk_buff *skb;\n\tdma_addr_t mapping;\n\tbool fragmented;\n};\n\nstruct tg3_link_config {\n\tu32 advertising;\n\tu32 speed;\n\tu8 duplex;\n\tu8 autoneg;\n\tu8 flowctrl;\n\tu8 active_flowctrl;\n\tu8 active_duplex;\n\tu32 active_speed;\n\tu32 rmt_adv;\n};\n\nstruct tg3_bufmgr_config {\n\tu32 mbuf_read_dma_low_water;\n\tu32 mbuf_mac_rx_low_water;\n\tu32 mbuf_high_water;\n\tu32 mbuf_read_dma_low_water_jumbo;\n\tu32 mbuf_mac_rx_low_water_jumbo;\n\tu32 mbuf_high_water_jumbo;\n\tu32 dma_low_water;\n\tu32 dma_high_water;\n};\n\nstruct tg3_ethtool_stats {\n\tu64 rx_octets;\n\tu64 rx_fragments;\n\tu64 rx_ucast_packets;\n\tu64 rx_mcast_packets;\n\tu64 rx_bcast_packets;\n\tu64 rx_fcs_errors;\n\tu64 rx_align_errors;\n\tu64 rx_xon_pause_rcvd;\n\tu64 rx_xoff_pause_rcvd;\n\tu64 rx_mac_ctrl_rcvd;\n\tu64 rx_xoff_entered;\n\tu64 rx_frame_too_long_errors;\n\tu64 rx_jabbers;\n\tu64 rx_undersize_packets;\n\tu64 rx_in_length_errors;\n\tu64 rx_out_length_errors;\n\tu64 rx_64_or_less_octet_packets;\n\tu64 rx_65_to_127_octet_packets;\n\tu64 rx_128_to_255_octet_packets;\n\tu64 rx_256_to_511_octet_packets;\n\tu64 rx_512_to_1023_octet_packets;\n\tu64 rx_1024_to_1522_octet_packets;\n\tu64 rx_1523_to_2047_octet_packets;\n\tu64 rx_2048_to_4095_octet_packets;\n\tu64 rx_4096_to_8191_octet_packets;\n\tu64 rx_8192_to_9022_octet_packets;\n\tu64 tx_octets;\n\tu64 tx_collisions;\n\tu64 tx_xon_sent;\n\tu64 tx_xoff_sent;\n\tu64 tx_flow_control;\n\tu64 tx_mac_errors;\n\tu64 tx_single_collisions;\n\tu64 tx_mult_collisions;\n\tu64 tx_deferred;\n\tu64 tx_excessive_collisions;\n\tu64 tx_late_collisions;\n\tu64 tx_collide_2times;\n\tu64 tx_collide_3times;\n\tu64 tx_collide_4times;\n\tu64 tx_collide_5times;\n\tu64 tx_collide_6times;\n\tu64 tx_collide_7times;\n\tu64 tx_collide_8times;\n\tu64 tx_collide_9times;\n\tu64 tx_collide_10times;\n\tu64 tx_collide_11times;\n\tu64 tx_collide_12times;\n\tu64 tx_collide_13times;\n\tu64 tx_collide_14times;\n\tu64 tx_collide_15times;\n\tu64 tx_ucast_packets;\n\tu64 tx_mcast_packets;\n\tu64 tx_bcast_packets;\n\tu64 tx_carrier_sense_errors;\n\tu64 tx_discards;\n\tu64 tx_errors;\n\tu64 dma_writeq_full;\n\tu64 dma_write_prioq_full;\n\tu64 rxbds_empty;\n\tu64 rx_discards;\n\tu64 rx_errors;\n\tu64 rx_threshold_hit;\n\tu64 dma_readq_full;\n\tu64 dma_read_prioq_full;\n\tu64 tx_comp_queue_full;\n\tu64 ring_set_send_prod_index;\n\tu64 ring_status_update;\n\tu64 nic_irqs;\n\tu64 nic_avoided_irqs;\n\tu64 nic_tx_threshold_hit;\n\tu64 mbuf_lwm_thresh_hit;\n};\n\nstruct tg3_rx_prodring_set {\n\tu32 rx_std_prod_idx;\n\tu32 rx_std_cons_idx;\n\tu32 rx_jmb_prod_idx;\n\tu32 rx_jmb_cons_idx;\n\tstruct tg3_rx_buffer_desc *rx_std;\n\tstruct tg3_ext_rx_buffer_desc *rx_jmb;\n\tstruct ring_info *rx_std_buffers;\n\tstruct ring_info *rx_jmb_buffers;\n\tdma_addr_t rx_std_mapping;\n\tdma_addr_t rx_jmb_mapping;\n};\n\nstruct tg3;\n\nstruct tg3_napi {\n\tstruct napi_struct napi;\n\tstruct tg3 *tp;\n\tstruct tg3_hw_status *hw_status;\n\tu32 chk_msi_cnt;\n\tu32 last_tag;\n\tu32 last_irq_tag;\n\tu32 int_mbox;\n\tu32 coal_now;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tu32 consmbox;\n\tu32 rx_rcb_ptr;\n\tu32 last_rx_cons;\n\tu16 *rx_rcb_prod_idx;\n\tstruct tg3_rx_prodring_set prodring;\n\tstruct tg3_rx_buffer_desc *rx_rcb;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 tx_prod;\n\tu32 tx_cons;\n\tu32 tx_pending;\n\tu32 last_tx_cons;\n\tu32 prodmbox;\n\tstruct tg3_tx_buffer_desc *tx_ring;\n\tstruct tg3_tx_ring_info *tx_buffers;\n\tdma_addr_t status_mapping;\n\tdma_addr_t rx_rcb_mapping;\n\tdma_addr_t tx_desc_mapping;\n\tchar irq_lbl[16];\n\tunsigned int irq_vec;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ptp_clock;\n\nstruct tg3 {\n\tunsigned int irq_sync;\n\tspinlock_t lock;\n\tspinlock_t indirect_lock;\n\tu32 (*read32)(struct tg3 *, u32);\n\tvoid (*write32)(struct tg3 *, u32, u32);\n\tu32 (*read32_mbox)(struct tg3 *, u32);\n\tvoid (*write32_mbox)(struct tg3 *, u32, u32);\n\tvoid *regs;\n\tvoid *aperegs;\n\tstruct net_device *dev;\n\tstruct pci_dev *pdev;\n\tu32 coal_now;\n\tu32 msg_enable;\n\tstruct ptp_clock_info ptp_info;\n\tstruct ptp_clock *ptp_clock;\n\ts64 ptp_adjust;\n\tvoid (*write32_tx_mbox)(struct tg3 *, u32, u32);\n\tu32 dma_limit;\n\tu32 txq_req;\n\tu32 txq_cnt;\n\tu32 txq_max;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct tg3_napi napi[5];\n\tvoid (*write32_rx_mbox)(struct tg3 *, u32, u32);\n\tu32 rx_copy_thresh;\n\tu32 rx_std_ring_mask;\n\tu32 rx_jmb_ring_mask;\n\tu32 rx_ret_ring_mask;\n\tu32 rx_pending;\n\tu32 rx_jumbo_pending;\n\tu32 rx_std_max_post;\n\tu32 rx_offset;\n\tu32 rx_pkt_map_sz;\n\tu32 rxq_req;\n\tu32 rxq_cnt;\n\tu32 rxq_max;\n\tbool rx_refill;\n\tlong unsigned int rx_dropped;\n\tlong unsigned int tx_dropped;\n\tstruct rtnl_link_stats64 net_stats_prev;\n\tstruct tg3_ethtool_stats estats_prev;\n\tlong unsigned int tg3_flags[2];\n\tunion {\n\t\tlong unsigned int phy_crc_errors;\n\t\tlong unsigned int last_event_jiffies;\n\t};\n\tstruct timer_list timer;\n\tu16 timer_counter;\n\tu16 timer_multiplier;\n\tu32 timer_offset;\n\tu16 asf_counter;\n\tu16 asf_multiplier;\n\tu32 serdes_counter;\n\tstruct tg3_link_config link_config;\n\tstruct tg3_bufmgr_config bufmgr_config;\n\tu32 rx_mode;\n\tu32 tx_mode;\n\tu32 mac_mode;\n\tu32 mi_mode;\n\tu32 misc_host_ctrl;\n\tu32 grc_mode;\n\tu32 grc_local_ctrl;\n\tu32 dma_rwctrl;\n\tu32 coalesce_mode;\n\tu32 pwrmgmt_thresh;\n\tu32 rxptpctl;\n\tu32 pci_chip_rev_id;\n\tu16 pci_cmd;\n\tu8 pci_cacheline_sz;\n\tu8 pci_lat_timer;\n\tint pci_fn;\n\tint msi_cap;\n\tint pcix_cap;\n\tint pcie_readrq;\n\tstruct mii_bus *mdio_bus;\n\tint old_link;\n\tu8 phy_addr;\n\tu8 phy_ape_lock;\n\tu32 phy_id;\n\tu32 phy_flags;\n\tu32 led_ctrl;\n\tu32 phy_otp;\n\tu32 setlpicnt;\n\tu8 rss_ind_tbl[128];\n\tchar board_part_number[24];\n\tchar fw_ver[32];\n\tu32 nic_sram_data_cfg;\n\tu32 pci_clock_ctrl;\n\tstruct pci_dev *pdev_peer;\n\tstruct tg3_hw_stats *hw_stats;\n\tdma_addr_t stats_mapping;\n\tstruct work_struct reset_task;\n\tint nvram_lock_cnt;\n\tu32 nvram_size;\n\tu32 nvram_pagesize;\n\tu32 nvram_jedecnum;\n\tunsigned int irq_max;\n\tunsigned int irq_cnt;\n\tstruct ethtool_coalesce coal;\n\tstruct ethtool_eee eee;\n\tconst char *fw_needed;\n\tconst struct firmware *fw;\n\tu32 fw_len;\n\tstruct device *hwmon_dev;\n\tbool link_up;\n\tbool pcierr_recovery;\n\tu32 ape_hb;\n\tlong unsigned int ape_hb_interval;\n\tlong unsigned int ape_hb_jiffies;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nenum TG3_FLAGS {\n\tTG3_FLAG_TAGGED_STATUS = 0,\n\tTG3_FLAG_TXD_MBOX_HWBUG = 1,\n\tTG3_FLAG_USE_LINKCHG_REG = 2,\n\tTG3_FLAG_ERROR_PROCESSED = 3,\n\tTG3_FLAG_ENABLE_ASF = 4,\n\tTG3_FLAG_ASPM_WORKAROUND = 5,\n\tTG3_FLAG_POLL_SERDES = 6,\n\tTG3_FLAG_POLL_CPMU_LINK = 7,\n\tTG3_FLAG_MBOX_WRITE_REORDER = 8,\n\tTG3_FLAG_PCIX_TARGET_HWBUG = 9,\n\tTG3_FLAG_WOL_SPEED_100MB = 10,\n\tTG3_FLAG_WOL_ENABLE = 11,\n\tTG3_FLAG_EEPROM_WRITE_PROT = 12,\n\tTG3_FLAG_NVRAM = 13,\n\tTG3_FLAG_NVRAM_BUFFERED = 14,\n\tTG3_FLAG_SUPPORT_MSI = 15,\n\tTG3_FLAG_SUPPORT_MSIX = 16,\n\tTG3_FLAG_USING_MSI = 17,\n\tTG3_FLAG_USING_MSIX = 18,\n\tTG3_FLAG_PCIX_MODE = 19,\n\tTG3_FLAG_PCI_HIGH_SPEED = 20,\n\tTG3_FLAG_PCI_32BIT = 21,\n\tTG3_FLAG_SRAM_USE_CONFIG = 22,\n\tTG3_FLAG_TX_RECOVERY_PENDING = 23,\n\tTG3_FLAG_WOL_CAP = 24,\n\tTG3_FLAG_JUMBO_RING_ENABLE = 25,\n\tTG3_FLAG_PAUSE_AUTONEG = 26,\n\tTG3_FLAG_CPMU_PRESENT = 27,\n\tTG3_FLAG_40BIT_DMA_BUG = 28,\n\tTG3_FLAG_BROKEN_CHECKSUMS = 29,\n\tTG3_FLAG_JUMBO_CAPABLE = 30,\n\tTG3_FLAG_CHIP_RESETTING = 31,\n\tTG3_FLAG_INIT_COMPLETE = 32,\n\tTG3_FLAG_MAX_RXPEND_64 = 33,\n\tTG3_FLAG_PCI_EXPRESS = 34,\n\tTG3_FLAG_ASF_NEW_HANDSHAKE = 35,\n\tTG3_FLAG_HW_AUTONEG = 36,\n\tTG3_FLAG_IS_NIC = 37,\n\tTG3_FLAG_FLASH = 38,\n\tTG3_FLAG_FW_TSO = 39,\n\tTG3_FLAG_HW_TSO_1 = 40,\n\tTG3_FLAG_HW_TSO_2 = 41,\n\tTG3_FLAG_HW_TSO_3 = 42,\n\tTG3_FLAG_TSO_CAPABLE = 43,\n\tTG3_FLAG_TSO_BUG = 44,\n\tTG3_FLAG_ICH_WORKAROUND = 45,\n\tTG3_FLAG_1SHOT_MSI = 46,\n\tTG3_FLAG_NO_FWARE_REPORTED = 47,\n\tTG3_FLAG_NO_NVRAM_ADDR_TRANS = 48,\n\tTG3_FLAG_ENABLE_APE = 49,\n\tTG3_FLAG_PROTECTED_NVRAM = 50,\n\tTG3_FLAG_5701_DMA_BUG = 51,\n\tTG3_FLAG_USE_PHYLIB = 52,\n\tTG3_FLAG_MDIOBUS_INITED = 53,\n\tTG3_FLAG_LRG_PROD_RING_CAP = 54,\n\tTG3_FLAG_RGMII_INBAND_DISABLE = 55,\n\tTG3_FLAG_RGMII_EXT_IBND_RX_EN = 56,\n\tTG3_FLAG_RGMII_EXT_IBND_TX_EN = 57,\n\tTG3_FLAG_CLKREQ_BUG = 58,\n\tTG3_FLAG_NO_NVRAM = 59,\n\tTG3_FLAG_ENABLE_RSS = 60,\n\tTG3_FLAG_ENABLE_TSS = 61,\n\tTG3_FLAG_SHORT_DMA_BUG = 62,\n\tTG3_FLAG_USE_JUMBO_BDFLAG = 63,\n\tTG3_FLAG_L1PLLPD_EN = 64,\n\tTG3_FLAG_APE_HAS_NCSI = 65,\n\tTG3_FLAG_TX_TSTAMP_EN = 66,\n\tTG3_FLAG_4K_FIFO_LIMIT = 67,\n\tTG3_FLAG_5719_5720_RDMA_BUG = 68,\n\tTG3_FLAG_RESET_TASK_PENDING = 69,\n\tTG3_FLAG_PTP_CAPABLE = 70,\n\tTG3_FLAG_5705_PLUS = 71,\n\tTG3_FLAG_IS_5788 = 72,\n\tTG3_FLAG_5750_PLUS = 73,\n\tTG3_FLAG_5780_CLASS = 74,\n\tTG3_FLAG_5755_PLUS = 75,\n\tTG3_FLAG_57765_PLUS = 76,\n\tTG3_FLAG_57765_CLASS = 77,\n\tTG3_FLAG_5717_PLUS = 78,\n\tTG3_FLAG_IS_SSB_CORE = 79,\n\tTG3_FLAG_FLUSH_POSTED_WRITES = 80,\n\tTG3_FLAG_ROBOSWITCH = 81,\n\tTG3_FLAG_ONE_DMA_AT_ONCE = 82,\n\tTG3_FLAG_RGMII_MODE = 83,\n\tTG3_FLAG_NUMBER_OF_FLAGS = 84,\n};\n\nstruct tg3_firmware_hdr {\n\t__be32 version;\n\t__be32 base_addr;\n\t__be32 len;\n};\n\nstruct tg3_fiber_aneginfo {\n\tint state;\n\tu32 flags;\n\tlong unsigned int link_time;\n\tlong unsigned int cur_time;\n\tu32 ability_match_cfg;\n\tint ability_match_count;\n\tchar ability_match;\n\tchar idle_match;\n\tchar ack_match;\n\tu32 txconfig;\n\tu32 rxconfig;\n};\n\nstruct subsys_tbl_ent {\n\tu16 subsys_vendor;\n\tu16 subsys_devid;\n\tu32 phy_id;\n};\n\nstruct tg3_dev_id {\n\tu32 vendor;\n\tu32 device;\n\tu32 rev;\n};\n\nstruct tg3_dev_id___2 {\n\tu32 vendor;\n\tu32 device;\n};\n\nstruct mem_entry {\n\tu32 offset;\n\tu32 len;\n};\n\nenum mac {\n\tmac_82557_D100_A = 0,\n\tmac_82557_D100_B = 1,\n\tmac_82557_D100_C = 2,\n\tmac_82558_D101_A4 = 4,\n\tmac_82558_D101_B0 = 5,\n\tmac_82559_D101M = 8,\n\tmac_82559_D101S = 9,\n\tmac_82550_D102 = 12,\n\tmac_82550_D102_C = 13,\n\tmac_82551_E = 14,\n\tmac_82551_F = 15,\n\tmac_82551_10 = 16,\n\tmac_unknown = 255,\n};\n\nenum phy___3 {\n\tphy_100a = 992,\n\tphy_100c = 55575208,\n\tphy_82555_tx = 22020776,\n\tphy_nsc_tx = 1543512064,\n\tphy_82562_et = 53478056,\n\tphy_82562_em = 52429480,\n\tphy_82562_ek = 51380904,\n\tphy_82562_eh = 24117928,\n\tphy_82552_v = 3496017997,\n\tphy_unknown = 4294967295,\n};\n\nstruct csr {\n\tstruct {\n\t\tu8 status;\n\t\tu8 stat_ack;\n\t\tu8 cmd_lo;\n\t\tu8 cmd_hi;\n\t\tu32 gen_ptr;\n\t} scb;\n\tu32 port;\n\tu16 flash_ctrl;\n\tu8 eeprom_ctrl_lo;\n\tu8 eeprom_ctrl_hi;\n\tu32 mdi_ctrl;\n\tu32 rx_dma_count;\n};\n\nenum scb_status {\n\trus_no_res = 8,\n\trus_ready = 16,\n\trus_mask = 60,\n};\n\nenum ru_state {\n\tRU_SUSPENDED = 0,\n\tRU_RUNNING = 1,\n\tRU_UNINITIALIZED = 4294967295,\n};\n\nenum scb_stat_ack {\n\tstat_ack_not_ours = 0,\n\tstat_ack_sw_gen = 4,\n\tstat_ack_rnr = 16,\n\tstat_ack_cu_idle = 32,\n\tstat_ack_frame_rx = 64,\n\tstat_ack_cu_cmd_done = 128,\n\tstat_ack_not_present = 255,\n\tstat_ack_rx = 84,\n\tstat_ack_tx = 160,\n};\n\nenum scb_cmd_hi {\n\tirq_mask_none = 0,\n\tirq_mask_all = 1,\n\tirq_sw_gen = 2,\n};\n\nenum scb_cmd_lo {\n\tcuc_nop = 0,\n\truc_start = 1,\n\truc_load_base = 6,\n\tcuc_start = 16,\n\tcuc_resume = 32,\n\tcuc_dump_addr = 64,\n\tcuc_dump_stats = 80,\n\tcuc_load_base = 96,\n\tcuc_dump_reset = 112,\n};\n\nenum cuc_dump {\n\tcuc_dump_complete = 40965,\n\tcuc_dump_reset_complete = 40967,\n};\n\nenum port___2 {\n\tsoftware_reset = 0,\n\tselftest = 1,\n\tselective_reset = 2,\n};\n\nenum eeprom_ctrl_lo {\n\teesk = 1,\n\teecs = 2,\n\teedi = 4,\n\teedo = 8,\n};\n\nenum mdi_ctrl {\n\tmdi_write = 67108864,\n\tmdi_read = 134217728,\n\tmdi_ready = 268435456,\n};\n\nenum eeprom_op {\n\top_write = 5,\n\top_read = 6,\n\top_ewds = 16,\n\top_ewen = 19,\n};\n\nenum eeprom_offsets {\n\teeprom_cnfg_mdix = 3,\n\teeprom_phy_iface = 6,\n\teeprom_id = 10,\n\teeprom_config_asf = 13,\n\teeprom_smbus_addr = 144,\n};\n\nenum eeprom_cnfg_mdix {\n\teeprom_mdix_enabled = 128,\n};\n\nenum eeprom_phy_iface {\n\tNoSuchPhy = 0,\n\tI82553AB = 1,\n\tI82553C = 2,\n\tI82503 = 3,\n\tDP83840 = 4,\n\tS80C240 = 5,\n\tS80C24 = 6,\n\tI82555 = 7,\n\tDP83840A = 10,\n};\n\nenum eeprom_id {\n\teeprom_id_wol = 32,\n};\n\nenum eeprom_config_asf {\n\teeprom_asf = 32768,\n\teeprom_gcl = 16384,\n};\n\nenum cb_status {\n\tcb_complete = 32768,\n\tcb_ok = 8192,\n};\n\nenum cb_command {\n\tcb_nop = 0,\n\tcb_iaaddr = 1,\n\tcb_config = 2,\n\tcb_multi = 3,\n\tcb_tx = 4,\n\tcb_ucode = 5,\n\tcb_dump = 6,\n\tcb_tx_sf = 8,\n\tcb_tx_nc = 16,\n\tcb_cid = 7936,\n\tcb_i = 8192,\n\tcb_s = 16384,\n\tcb_el = 32768,\n};\n\nstruct rfd {\n\t__le16 status;\n\t__le16 command;\n\t__le32 link;\n\t__le32 rbd;\n\t__le16 actual_size;\n\t__le16 size;\n};\n\nstruct rx {\n\tstruct rx *next;\n\tstruct rx *prev;\n\tstruct sk_buff *skb;\n\tdma_addr_t dma_addr;\n};\n\nstruct config {\n\tu8 byte_count: 6;\n\tu8 pad0: 2;\n\tu8 rx_fifo_limit: 4;\n\tu8 tx_fifo_limit: 3;\n\tu8 pad1: 1;\n\tu8 adaptive_ifs;\n\tu8 mwi_enable: 1;\n\tu8 type_enable: 1;\n\tu8 read_align_enable: 1;\n\tu8 term_write_cache_line: 1;\n\tu8 pad3: 4;\n\tu8 rx_dma_max_count: 7;\n\tu8 pad4: 1;\n\tu8 tx_dma_max_count: 7;\n\tu8 dma_max_count_enable: 1;\n\tu8 late_scb_update: 1;\n\tu8 direct_rx_dma: 1;\n\tu8 tno_intr: 1;\n\tu8 cna_intr: 1;\n\tu8 standard_tcb: 1;\n\tu8 standard_stat_counter: 1;\n\tu8 rx_save_overruns: 1;\n\tu8 rx_save_bad_frames: 1;\n\tu8 rx_discard_short_frames: 1;\n\tu8 tx_underrun_retry: 2;\n\tu8 pad7: 2;\n\tu8 rx_extended_rfd: 1;\n\tu8 tx_two_frames_in_fifo: 1;\n\tu8 tx_dynamic_tbd: 1;\n\tu8 mii_mode: 1;\n\tu8 pad8: 6;\n\tu8 csma_disabled: 1;\n\tu8 rx_tcpudp_checksum: 1;\n\tu8 pad9: 3;\n\tu8 vlan_arp_tco: 1;\n\tu8 link_status_wake: 1;\n\tu8 arp_wake: 1;\n\tu8 mcmatch_wake: 1;\n\tu8 pad10: 3;\n\tu8 no_source_addr_insertion: 1;\n\tu8 preamble_length: 2;\n\tu8 loopback: 2;\n\tu8 linear_priority: 3;\n\tu8 pad11: 5;\n\tu8 linear_priority_mode: 1;\n\tu8 pad12: 3;\n\tu8 ifs: 4;\n\tu8 ip_addr_lo;\n\tu8 ip_addr_hi;\n\tu8 promiscuous_mode: 1;\n\tu8 broadcast_disabled: 1;\n\tu8 wait_after_win: 1;\n\tu8 pad15_1: 1;\n\tu8 ignore_ul_bit: 1;\n\tu8 crc_16_bit: 1;\n\tu8 pad15_2: 1;\n\tu8 crs_or_cdt: 1;\n\tu8 fc_delay_lo;\n\tu8 fc_delay_hi;\n\tu8 rx_stripping: 1;\n\tu8 tx_padding: 1;\n\tu8 rx_crc_transfer: 1;\n\tu8 rx_long_ok: 1;\n\tu8 fc_priority_threshold: 3;\n\tu8 pad18: 1;\n\tu8 addr_wake: 1;\n\tu8 magic_packet_disable: 1;\n\tu8 fc_disable: 1;\n\tu8 fc_restop: 1;\n\tu8 fc_restart: 1;\n\tu8 fc_reject: 1;\n\tu8 full_duplex_force: 1;\n\tu8 full_duplex_pin: 1;\n\tu8 pad20_1: 5;\n\tu8 fc_priority_location: 1;\n\tu8 multi_ia: 1;\n\tu8 pad20_2: 1;\n\tu8 pad21_1: 3;\n\tu8 multicast_all: 1;\n\tu8 pad21_2: 4;\n\tu8 rx_d102_mode: 1;\n\tu8 rx_vlan_drop: 1;\n\tu8 pad22: 6;\n\tu8 pad_d102[9];\n};\n\nstruct multi {\n\t__le16 count;\n\tu8 addr[386];\n};\n\nstruct cb {\n\t__le16 status;\n\t__le16 command;\n\t__le32 link;\n\tunion {\n\t\tu8 iaaddr[6];\n\t\t__le32 ucode[134];\n\t\tstruct config config;\n\t\tstruct multi multi;\n\t\tstruct {\n\t\t\tu32 tbd_array;\n\t\t\tu16 tcb_byte_count;\n\t\t\tu8 threshold;\n\t\t\tu8 tbd_count;\n\t\t\tstruct {\n\t\t\t\t__le32 buf_addr;\n\t\t\t\t__le16 size;\n\t\t\t\tu16 eol;\n\t\t\t} tbd;\n\t\t} tcb;\n\t\t__le32 dump_buffer_addr;\n\t} u;\n\tstruct cb *next;\n\tstruct cb *prev;\n\tdma_addr_t dma_addr;\n\tstruct sk_buff *skb;\n};\n\nenum loopback {\n\tlb_none = 0,\n\tlb_mac = 1,\n\tlb_phy = 3,\n};\n\nstruct stats {\n\t__le32 tx_good_frames;\n\t__le32 tx_max_collisions;\n\t__le32 tx_late_collisions;\n\t__le32 tx_underruns;\n\t__le32 tx_lost_crs;\n\t__le32 tx_deferred;\n\t__le32 tx_single_collisions;\n\t__le32 tx_multiple_collisions;\n\t__le32 tx_total_collisions;\n\t__le32 rx_good_frames;\n\t__le32 rx_crc_errors;\n\t__le32 rx_alignment_errors;\n\t__le32 rx_resource_errors;\n\t__le32 rx_overrun_errors;\n\t__le32 rx_cdt_errors;\n\t__le32 rx_short_frame_errors;\n\t__le32 fc_xmt_pause;\n\t__le32 fc_rcv_pause;\n\t__le32 fc_rcv_unsupported;\n\t__le16 xmt_tco_frames;\n\t__le16 rcv_tco_frames;\n\t__le32 complete;\n};\n\nstruct mem {\n\tstruct {\n\t\tu32 signature;\n\t\tu32 result;\n\t} selftest;\n\tstruct stats stats;\n\tu8 dump_buf[596];\n};\n\nstruct param_range {\n\tu32 min;\n\tu32 max;\n\tu32 count;\n};\n\nstruct params {\n\tstruct param_range rfds;\n\tstruct param_range cbs;\n};\n\nstruct nic {\n\tu32 msg_enable;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tu16 (*mdio_ctrl)(struct nic *, u32, u32, u32, u16);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct rx *rxs;\n\tstruct rx *rx_to_use;\n\tstruct rx *rx_to_clean;\n\tstruct rfd blank_rfd;\n\tenum ru_state ru_running;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t cb_lock;\n\tspinlock_t cmd_lock;\n\tstruct csr *csr;\n\tenum scb_cmd_lo cuc_cmd;\n\tunsigned int cbs_avail;\n\tstruct napi_struct napi;\n\tstruct cb *cbs;\n\tstruct cb *cb_to_use;\n\tstruct cb *cb_to_send;\n\tstruct cb *cb_to_clean;\n\t__le16 tx_command;\n\tlong: 48;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tenum {\n\t\tich = 1,\n\t\tpromiscuous = 2,\n\t\tmulticast_all = 4,\n\t\twol_magic = 8,\n\t\tich_10h_workaround = 16,\n\t} flags;\n\tenum mac mac;\n\tenum phy___3 phy;\n\tstruct params params;\n\tstruct timer_list watchdog;\n\tstruct mii_if_info mii;\n\tstruct work_struct tx_timeout_task;\n\tenum loopback loopback;\n\tstruct mem *mem;\n\tdma_addr_t dma_addr;\n\tstruct dma_pool___2 *cbs_pool;\n\tdma_addr_t cbs_dma_addr;\n\tu8 adaptive_ifs;\n\tu8 tx_threshold;\n\tu32 tx_frames;\n\tu32 tx_collisions;\n\tu32 tx_deferred;\n\tu32 tx_single_collisions;\n\tu32 tx_multiple_collisions;\n\tu32 tx_fc_pause;\n\tu32 tx_tco_frames;\n\tu32 rx_fc_pause;\n\tu32 rx_fc_unsupported;\n\tu32 rx_tco_frames;\n\tu32 rx_short_frame_errors;\n\tu32 rx_over_length_errors;\n\tu16 eeprom_wc;\n\t__le16 eeprom[256];\n\tspinlock_t mdio_lock;\n\tconst struct firmware *fw;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nenum led_state {\n\tled_on = 1,\n\tled_off = 4,\n\tled_on_559 = 5,\n\tled_on_557 = 7,\n};\n\nstruct vlan_hdr {\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nstruct qdisc_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tint (*fn)(struct Qdisc *, long unsigned int, struct qdisc_walker *);\n};\n\ntypedef enum {\n\te1000_undefined = 0,\n\te1000_82542_rev2_0 = 1,\n\te1000_82542_rev2_1 = 2,\n\te1000_82543 = 3,\n\te1000_82544 = 4,\n\te1000_82540 = 5,\n\te1000_82545 = 6,\n\te1000_82545_rev_3 = 7,\n\te1000_82546 = 8,\n\te1000_ce4100 = 9,\n\te1000_82546_rev_3 = 10,\n\te1000_82541 = 11,\n\te1000_82541_rev_2 = 12,\n\te1000_82547 = 13,\n\te1000_82547_rev_2 = 14,\n\te1000_num_macs = 15,\n} e1000_mac_type;\n\ntypedef enum {\n\te1000_eeprom_uninitialized = 0,\n\te1000_eeprom_spi = 1,\n\te1000_eeprom_microwire = 2,\n\te1000_eeprom_flash = 3,\n\te1000_eeprom_none = 4,\n\te1000_num_eeprom_types = 5,\n} e1000_eeprom_type;\n\ntypedef enum {\n\te1000_media_type_copper = 0,\n\te1000_media_type_fiber = 1,\n\te1000_media_type_internal_serdes = 2,\n\te1000_num_media_types = 3,\n} e1000_media_type;\n\nenum {\n\te1000_10_half = 0,\n\te1000_10_full = 1,\n\te1000_100_half = 2,\n\te1000_100_full = 3,\n};\n\ntypedef enum {\n\tE1000_FC_NONE = 0,\n\tE1000_FC_RX_PAUSE = 1,\n\tE1000_FC_TX_PAUSE = 2,\n\tE1000_FC_FULL = 3,\n\tE1000_FC_DEFAULT = 255,\n} e1000_fc_type;\n\nstruct e1000_shadow_ram {\n\tu16 eeprom_word;\n\tbool modified;\n};\n\ntypedef enum {\n\te1000_bus_type_unknown = 0,\n\te1000_bus_type_pci = 1,\n\te1000_bus_type_pcix = 2,\n\te1000_bus_type_reserved = 3,\n} e1000_bus_type;\n\ntypedef enum {\n\te1000_bus_speed_unknown = 0,\n\te1000_bus_speed_33 = 1,\n\te1000_bus_speed_66 = 2,\n\te1000_bus_speed_100 = 3,\n\te1000_bus_speed_120 = 4,\n\te1000_bus_speed_133 = 5,\n\te1000_bus_speed_reserved = 6,\n} e1000_bus_speed;\n\ntypedef enum {\n\te1000_bus_width_unknown = 0,\n\te1000_bus_width_32 = 1,\n\te1000_bus_width_64 = 2,\n\te1000_bus_width_reserved = 3,\n} e1000_bus_width;\n\ntypedef enum {\n\te1000_cable_length_50 = 0,\n\te1000_cable_length_50_80 = 1,\n\te1000_cable_length_80_110 = 2,\n\te1000_cable_length_110_140 = 3,\n\te1000_cable_length_140 = 4,\n\te1000_cable_length_undefined = 255,\n} e1000_cable_length;\n\ntypedef enum {\n\te1000_10bt_ext_dist_enable_normal = 0,\n\te1000_10bt_ext_dist_enable_lower = 1,\n\te1000_10bt_ext_dist_enable_undefined = 255,\n} e1000_10bt_ext_dist_enable;\n\ntypedef enum {\n\te1000_rev_polarity_normal = 0,\n\te1000_rev_polarity_reversed = 1,\n\te1000_rev_polarity_undefined = 255,\n} e1000_rev_polarity;\n\ntypedef enum {\n\te1000_downshift_normal = 0,\n\te1000_downshift_activated = 1,\n\te1000_downshift_undefined = 255,\n} e1000_downshift;\n\ntypedef enum {\n\te1000_smart_speed_default = 0,\n\te1000_smart_speed_on = 1,\n\te1000_smart_speed_off = 2,\n} e1000_smart_speed;\n\ntypedef enum {\n\te1000_polarity_reversal_enabled = 0,\n\te1000_polarity_reversal_disabled = 1,\n\te1000_polarity_reversal_undefined = 255,\n} e1000_polarity_reversal;\n\ntypedef enum {\n\te1000_auto_x_mode_manual_mdi = 0,\n\te1000_auto_x_mode_manual_mdix = 1,\n\te1000_auto_x_mode_auto1 = 2,\n\te1000_auto_x_mode_auto2 = 3,\n\te1000_auto_x_mode_undefined = 255,\n} e1000_auto_x_mode;\n\ntypedef enum {\n\te1000_1000t_rx_status_not_ok = 0,\n\te1000_1000t_rx_status_ok = 1,\n\te1000_1000t_rx_status_undefined = 255,\n} e1000_1000t_rx_status;\n\ntypedef enum {\n\te1000_phy_m88 = 0,\n\te1000_phy_igp = 1,\n\te1000_phy_8211 = 2,\n\te1000_phy_8201 = 3,\n\te1000_phy_undefined = 255,\n} e1000_phy_type;\n\ntypedef enum {\n\te1000_ms_hw_default = 0,\n\te1000_ms_force_master = 1,\n\te1000_ms_force_slave = 2,\n\te1000_ms_auto = 3,\n} e1000_ms_type;\n\ntypedef enum {\n\te1000_ffe_config_enabled = 0,\n\te1000_ffe_config_active = 1,\n\te1000_ffe_config_blocked = 2,\n} e1000_ffe_config;\n\ntypedef enum {\n\te1000_dsp_config_disabled = 0,\n\te1000_dsp_config_enabled = 1,\n\te1000_dsp_config_activated = 2,\n\te1000_dsp_config_undefined = 255,\n} e1000_dsp_config;\n\nstruct e1000_phy_info {\n\te1000_cable_length cable_length;\n\te1000_10bt_ext_dist_enable extended_10bt_distance;\n\te1000_rev_polarity cable_polarity;\n\te1000_downshift downshift;\n\te1000_polarity_reversal polarity_correction;\n\te1000_auto_x_mode mdix_mode;\n\te1000_1000t_rx_status local_rx;\n\te1000_1000t_rx_status remote_rx;\n};\n\nstruct e1000_phy_stats {\n\tu32 idle_errors;\n\tu32 receive_errors;\n};\n\nstruct e1000_eeprom_info {\n\te1000_eeprom_type type;\n\tu16 word_size;\n\tu16 opcode_bits;\n\tu16 address_bits;\n\tu16 delay_usec;\n\tu16 page_size;\n};\n\nstruct e1000_host_mng_dhcp_cookie {\n\tu32 signature;\n\tu8 status;\n\tu8 reserved0;\n\tu16 vlan_id;\n\tu32 reserved1;\n\tu16 reserved2;\n\tu8 reserved3;\n\tu8 checksum;\n};\n\nstruct e1000_rx_desc {\n\t__le64 buffer_addr;\n\t__le16 length;\n\t__le16 csum;\n\tu8 status;\n\tu8 errors;\n\t__le16 special;\n};\n\nstruct e1000_tx_desc {\n\t__le64 buffer_addr;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\t__le16 length;\n\t\t\tu8 cso;\n\t\t\tu8 cmd;\n\t\t} flags;\n\t} lower;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status;\n\t\t\tu8 css;\n\t\t\t__le16 special;\n\t\t} fields;\n\t} upper;\n};\n\nstruct e1000_context_desc {\n\tunion {\n\t\t__le32 ip_config;\n\t\tstruct {\n\t\t\tu8 ipcss;\n\t\t\tu8 ipcso;\n\t\t\t__le16 ipcse;\n\t\t} ip_fields;\n\t} lower_setup;\n\tunion {\n\t\t__le32 tcp_config;\n\t\tstruct {\n\t\t\tu8 tucss;\n\t\t\tu8 tucso;\n\t\t\t__le16 tucse;\n\t\t} tcp_fields;\n\t} upper_setup;\n\t__le32 cmd_and_length;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status;\n\t\t\tu8 hdr_len;\n\t\t\t__le16 mss;\n\t\t} fields;\n\t} tcp_seg_setup;\n};\n\nstruct e1000_hw_stats {\n\tu64 crcerrs;\n\tu64 algnerrc;\n\tu64 symerrs;\n\tu64 rxerrc;\n\tu64 txerrc;\n\tu64 mpc;\n\tu64 scc;\n\tu64 ecol;\n\tu64 mcc;\n\tu64 latecol;\n\tu64 colc;\n\tu64 dc;\n\tu64 tncrs;\n\tu64 sec;\n\tu64 cexterr;\n\tu64 rlec;\n\tu64 xonrxc;\n\tu64 xontxc;\n\tu64 xoffrxc;\n\tu64 xofftxc;\n\tu64 fcruc;\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorcl;\n\tu64 gorch;\n\tu64 gotcl;\n\tu64 gotch;\n\tu64 rnbc;\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rlerrc;\n\tu64 rjc;\n\tu64 mgprc;\n\tu64 mgpdc;\n\tu64 mgptc;\n\tu64 torl;\n\tu64 torh;\n\tu64 totl;\n\tu64 toth;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 tsctc;\n\tu64 tsctfc;\n\tu64 iac;\n\tu64 icrxptc;\n\tu64 icrxatc;\n\tu64 ictxptc;\n\tu64 ictxatc;\n\tu64 ictxqec;\n\tu64 ictxqmtc;\n\tu64 icrxdmtc;\n\tu64 icrxoc;\n};\n\nstruct e1000_hw {\n\tu8 *hw_addr;\n\tu8 *flash_address;\n\tvoid *ce4100_gbe_mdio_base_virt;\n\te1000_mac_type mac_type;\n\te1000_phy_type phy_type;\n\tu32 phy_init_script;\n\te1000_media_type media_type;\n\tvoid *back;\n\tstruct e1000_shadow_ram *eeprom_shadow_ram;\n\tu32 flash_bank_size;\n\tu32 flash_base_addr;\n\te1000_fc_type fc;\n\te1000_bus_speed bus_speed;\n\te1000_bus_width bus_width;\n\te1000_bus_type bus_type;\n\tstruct e1000_eeprom_info eeprom;\n\te1000_ms_type master_slave;\n\te1000_ms_type original_master_slave;\n\te1000_ffe_config ffe_config_state;\n\tu32 asf_firmware_present;\n\tu32 eeprom_semaphore_present;\n\tlong unsigned int io_base;\n\tu32 phy_id;\n\tu32 phy_revision;\n\tu32 phy_addr;\n\tu32 original_fc;\n\tu32 txcw;\n\tu32 autoneg_failed;\n\tu32 max_frame_size;\n\tu32 min_frame_size;\n\tu32 mc_filter_type;\n\tu32 num_mc_addrs;\n\tu32 collision_delta;\n\tu32 tx_packet_delta;\n\tu32 ledctl_default;\n\tu32 ledctl_mode1;\n\tu32 ledctl_mode2;\n\tbool tx_pkt_filtering;\n\tstruct e1000_host_mng_dhcp_cookie mng_cookie;\n\tu16 phy_spd_default;\n\tu16 autoneg_advertised;\n\tu16 pci_cmd_word;\n\tu16 fc_high_water;\n\tu16 fc_low_water;\n\tu16 fc_pause_time;\n\tu16 current_ifs_val;\n\tu16 ifs_min_val;\n\tu16 ifs_max_val;\n\tu16 ifs_step_size;\n\tu16 ifs_ratio;\n\tu16 device_id;\n\tu16 vendor_id;\n\tu16 subsystem_id;\n\tu16 subsystem_vendor_id;\n\tu8 revision_id;\n\tu8 autoneg;\n\tu8 mdix;\n\tu8 forced_speed_duplex;\n\tu8 wait_autoneg_complete;\n\tu8 dma_fairness;\n\tu8 mac_addr[6];\n\tu8 perm_mac_addr[6];\n\tbool disable_polarity_correction;\n\tbool speed_downgraded;\n\te1000_smart_speed smart_speed;\n\te1000_dsp_config dsp_config_state;\n\tbool get_link_status;\n\tbool serdes_has_link;\n\tbool tbi_compatibility_en;\n\tbool tbi_compatibility_on;\n\tbool laa_is_present;\n\tbool phy_reset_disable;\n\tbool initialize_hw_bits_disable;\n\tbool fc_send_xon;\n\tbool fc_strict_ieee;\n\tbool report_tx_early;\n\tbool adaptive_ifs;\n\tbool ifs_params_forced;\n\tbool in_ifs_mode;\n\tbool mng_reg_access_disabled;\n\tbool leave_av_bit_off;\n\tbool bad_tx_carr_stats_fd;\n\tbool has_smbus;\n};\n\nstruct e1000_tx_buffer {\n\tstruct sk_buff *skb;\n\tdma_addr_t dma;\n\tlong unsigned int time_stamp;\n\tu16 length;\n\tu16 next_to_watch;\n\tbool mapped_as_page;\n\tshort unsigned int segs;\n\tunsigned int bytecount;\n};\n\nstruct e1000_rx_buffer {\n\tunion {\n\t\tstruct page *page;\n\t\tu8 *data;\n\t} rxbuf;\n\tdma_addr_t dma;\n};\n\nstruct e1000_tx_ring {\n\tvoid *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tunsigned int next_to_use;\n\tunsigned int next_to_clean;\n\tstruct e1000_tx_buffer *buffer_info;\n\tu16 tdh;\n\tu16 tdt;\n\tbool last_tx_tso;\n};\n\nstruct e1000_rx_ring {\n\tvoid *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tunsigned int next_to_use;\n\tunsigned int next_to_clean;\n\tstruct e1000_rx_buffer *buffer_info;\n\tstruct sk_buff *rx_skb_top;\n\tint cpu;\n\tu16 rdh;\n\tu16 rdt;\n};\n\nstruct e1000_adapter {\n\tlong unsigned int active_vlans[64];\n\tu16 mng_vlan_id;\n\tu32 bd_number;\n\tu32 rx_buffer_len;\n\tu32 wol;\n\tu32 smartspeed;\n\tu32 en_mng_pt;\n\tu16 link_speed;\n\tu16 link_duplex;\n\tspinlock_t stats_lock;\n\tunsigned int total_tx_bytes;\n\tunsigned int total_tx_packets;\n\tunsigned int total_rx_bytes;\n\tunsigned int total_rx_packets;\n\tu32 itr;\n\tu32 itr_setting;\n\tu16 tx_itr;\n\tu16 rx_itr;\n\tu8 fc_autoneg;\n\tstruct e1000_tx_ring *tx_ring;\n\tunsigned int restart_queue;\n\tu32 txd_cmd;\n\tu32 tx_int_delay;\n\tu32 tx_abs_int_delay;\n\tu32 gotcl;\n\tu64 gotcl_old;\n\tu64 tpt_old;\n\tu64 colc_old;\n\tu32 tx_timeout_count;\n\tu32 tx_fifo_head;\n\tu32 tx_head_addr;\n\tu32 tx_fifo_size;\n\tu8 tx_timeout_factor;\n\tatomic_t tx_fifo_stall;\n\tbool pcix_82544;\n\tbool detect_tx_hung;\n\tbool dump_buffers;\n\tbool (*clean_rx)(struct e1000_adapter *, struct e1000_rx_ring *, int *, int);\n\tvoid (*alloc_rx_buf)(struct e1000_adapter *, struct e1000_rx_ring *, int);\n\tstruct e1000_rx_ring *rx_ring;\n\tstruct napi_struct napi;\n\tint num_tx_queues;\n\tint num_rx_queues;\n\tu64 hw_csum_err;\n\tu64 hw_csum_good;\n\tu32 alloc_rx_buff_failed;\n\tu32 rx_int_delay;\n\tu32 rx_abs_int_delay;\n\tbool rx_csum;\n\tu32 gorcl;\n\tu64 gorcl_old;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tstruct e1000_hw hw;\n\tstruct e1000_hw_stats stats;\n\tstruct e1000_phy_info phy_info;\n\tstruct e1000_phy_stats phy_stats;\n\tu32 test_icr;\n\tstruct e1000_tx_ring test_tx_ring;\n\tstruct e1000_rx_ring test_rx_ring;\n\tint msg_enable;\n\tbool tso_force;\n\tbool smart_power_down;\n\tbool quad_port_a;\n\tlong unsigned int flags;\n\tu32 eeprom_wol;\n\tint bars;\n\tint need_ioport;\n\tbool discarding;\n\tstruct work_struct reset_task;\n\tstruct delayed_work watchdog_task;\n\tstruct delayed_work fifo_stall_task;\n\tstruct delayed_work phy_info_task;\n};\n\nenum e1000_state_t {\n\t__E1000_TESTING = 0,\n\t__E1000_RESETTING = 1,\n\t__E1000_DOWN = 2,\n\t__E1000_DISABLED = 3,\n};\n\nenum latency_range {\n\tlowest_latency = 0,\n\tlow_latency = 1,\n\tbulk_latency = 2,\n\tlatency_invalid = 255,\n};\n\nstruct my_u {\n\t__le64 a;\n\t__le64 b;\n};\n\nenum {\n\te1000_igp_cable_length_10 = 10,\n\te1000_igp_cable_length_20 = 20,\n\te1000_igp_cable_length_30 = 30,\n\te1000_igp_cable_length_40 = 40,\n\te1000_igp_cable_length_50 = 50,\n\te1000_igp_cable_length_60 = 60,\n\te1000_igp_cable_length_70 = 70,\n\te1000_igp_cable_length_80 = 80,\n\te1000_igp_cable_length_90 = 90,\n\te1000_igp_cable_length_100 = 100,\n\te1000_igp_cable_length_110 = 110,\n\te1000_igp_cable_length_115 = 115,\n\te1000_igp_cable_length_120 = 120,\n\te1000_igp_cable_length_130 = 130,\n\te1000_igp_cable_length_140 = 140,\n\te1000_igp_cable_length_150 = 150,\n\te1000_igp_cable_length_160 = 160,\n\te1000_igp_cable_length_170 = 170,\n\te1000_igp_cable_length_180 = 180,\n};\n\nenum {\n\tNETDEV_STATS = 0,\n\tE1000_STATS = 1,\n};\n\nstruct e1000_stats {\n\tchar stat_string[32];\n\tint type;\n\tint sizeof_stat;\n\tint stat_offset;\n};\n\nstruct e1000_opt_list {\n\tint i;\n\tchar *str;\n};\n\nstruct e1000_option {\n\tenum {\n\t\tenable_option = 0,\n\t\trange_option = 1,\n\t\tlist_option = 2,\n\t} type;\n\tconst char *name;\n\tconst char *err;\n\tint def;\n\tunion {\n\t\tstruct {\n\t\t\tint min;\n\t\t\tint max;\n\t\t} r;\n\t\tstruct {\n\t\t\tint nr;\n\t\t\tconst struct e1000_opt_list *p;\n\t\t} l;\n\t} arg;\n};\n\nenum e1000_mac_type {\n\te1000_82571 = 0,\n\te1000_82572 = 1,\n\te1000_82573 = 2,\n\te1000_82574 = 3,\n\te1000_82583 = 4,\n\te1000_80003es2lan = 5,\n\te1000_ich8lan = 6,\n\te1000_ich9lan = 7,\n\te1000_ich10lan = 8,\n\te1000_pchlan = 9,\n\te1000_pch2lan = 10,\n\te1000_pch_lpt = 11,\n\te1000_pch_spt = 12,\n\te1000_pch_cnp = 13,\n\te1000_pch_tgp = 14,\n\te1000_pch_adp = 15,\n};\n\nenum e1000_media_type {\n\te1000_media_type_unknown = 0,\n\te1000_media_type_copper___2 = 1,\n\te1000_media_type_fiber___2 = 2,\n\te1000_media_type_internal_serdes___2 = 3,\n\te1000_num_media_types___2 = 4,\n};\n\nenum e1000_nvm_type {\n\te1000_nvm_unknown = 0,\n\te1000_nvm_none = 1,\n\te1000_nvm_eeprom_spi = 2,\n\te1000_nvm_flash_hw = 3,\n\te1000_nvm_flash_sw = 4,\n};\n\nenum e1000_nvm_override {\n\te1000_nvm_override_none = 0,\n\te1000_nvm_override_spi_small = 1,\n\te1000_nvm_override_spi_large = 2,\n};\n\nenum e1000_phy_type {\n\te1000_phy_unknown = 0,\n\te1000_phy_none = 1,\n\te1000_phy_m88___2 = 2,\n\te1000_phy_igp___2 = 3,\n\te1000_phy_igp_2 = 4,\n\te1000_phy_gg82563 = 5,\n\te1000_phy_igp_3 = 6,\n\te1000_phy_ife = 7,\n\te1000_phy_bm = 8,\n\te1000_phy_82578 = 9,\n\te1000_phy_82577 = 10,\n\te1000_phy_82579 = 11,\n\te1000_phy_i217 = 12,\n};\n\nenum e1000_bus_width {\n\te1000_bus_width_unknown___2 = 0,\n\te1000_bus_width_pcie_x1 = 1,\n\te1000_bus_width_pcie_x2 = 2,\n\te1000_bus_width_pcie_x4 = 4,\n\te1000_bus_width_pcie_x8 = 8,\n\te1000_bus_width_32___2 = 9,\n\te1000_bus_width_64___2 = 10,\n\te1000_bus_width_reserved___2 = 11,\n};\n\nenum e1000_1000t_rx_status {\n\te1000_1000t_rx_status_not_ok___2 = 0,\n\te1000_1000t_rx_status_ok___2 = 1,\n\te1000_1000t_rx_status_undefined___2 = 255,\n};\n\nenum e1000_rev_polarity {\n\te1000_rev_polarity_normal___2 = 0,\n\te1000_rev_polarity_reversed___2 = 1,\n\te1000_rev_polarity_undefined___2 = 255,\n};\n\nenum e1000_fc_mode {\n\te1000_fc_none = 0,\n\te1000_fc_rx_pause = 1,\n\te1000_fc_tx_pause = 2,\n\te1000_fc_full = 3,\n\te1000_fc_default = 255,\n};\n\nenum e1000_ms_type {\n\te1000_ms_hw_default___2 = 0,\n\te1000_ms_force_master___2 = 1,\n\te1000_ms_force_slave___2 = 2,\n\te1000_ms_auto___2 = 3,\n};\n\nenum e1000_smart_speed {\n\te1000_smart_speed_default___2 = 0,\n\te1000_smart_speed_on___2 = 1,\n\te1000_smart_speed_off___2 = 2,\n};\n\nenum e1000_serdes_link_state {\n\te1000_serdes_link_down = 0,\n\te1000_serdes_link_autoneg_progress = 1,\n\te1000_serdes_link_autoneg_complete = 2,\n\te1000_serdes_link_forced_up = 3,\n};\n\nstruct e1000_hw_stats___2 {\n\tu64 crcerrs;\n\tu64 algnerrc;\n\tu64 symerrs;\n\tu64 rxerrc;\n\tu64 mpc;\n\tu64 scc;\n\tu64 ecol;\n\tu64 mcc;\n\tu64 latecol;\n\tu64 colc;\n\tu64 dc;\n\tu64 tncrs;\n\tu64 sec;\n\tu64 cexterr;\n\tu64 rlec;\n\tu64 xonrxc;\n\tu64 xontxc;\n\tu64 xoffrxc;\n\tu64 xofftxc;\n\tu64 fcruc;\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 rnbc;\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rjc;\n\tu64 mgprc;\n\tu64 mgpdc;\n\tu64 mgptc;\n\tu64 tor;\n\tu64 tot;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 tsctc;\n\tu64 tsctfc;\n\tu64 iac;\n\tu64 icrxptc;\n\tu64 icrxatc;\n\tu64 ictxptc;\n\tu64 ictxatc;\n\tu64 ictxqec;\n\tu64 ictxqmtc;\n\tu64 icrxdmtc;\n\tu64 icrxoc;\n};\n\nstruct e1000_hw___2;\n\nstruct e1000_mac_operations {\n\ts32 (*id_led_init)(struct e1000_hw___2 *);\n\ts32 (*blink_led)(struct e1000_hw___2 *);\n\tbool (*check_mng_mode)(struct e1000_hw___2 *);\n\ts32 (*check_for_link)(struct e1000_hw___2 *);\n\ts32 (*cleanup_led)(struct e1000_hw___2 *);\n\tvoid (*clear_hw_cntrs)(struct e1000_hw___2 *);\n\tvoid (*clear_vfta)(struct e1000_hw___2 *);\n\ts32 (*get_bus_info)(struct e1000_hw___2 *);\n\tvoid (*set_lan_id)(struct e1000_hw___2 *);\n\ts32 (*get_link_up_info)(struct e1000_hw___2 *, u16 *, u16 *);\n\ts32 (*led_on)(struct e1000_hw___2 *);\n\ts32 (*led_off)(struct e1000_hw___2 *);\n\tvoid (*update_mc_addr_list)(struct e1000_hw___2 *, u8 *, u32);\n\ts32 (*reset_hw)(struct e1000_hw___2 *);\n\ts32 (*init_hw)(struct e1000_hw___2 *);\n\ts32 (*setup_link)(struct e1000_hw___2 *);\n\ts32 (*setup_physical_interface)(struct e1000_hw___2 *);\n\ts32 (*setup_led)(struct e1000_hw___2 *);\n\tvoid (*write_vfta)(struct e1000_hw___2 *, u32, u32);\n\tvoid (*config_collision_dist)(struct e1000_hw___2 *);\n\tint (*rar_set)(struct e1000_hw___2 *, u8 *, u32);\n\ts32 (*read_mac_addr)(struct e1000_hw___2 *);\n\tu32 (*rar_get_count)(struct e1000_hw___2 *);\n};\n\nstruct e1000_mac_info {\n\tstruct e1000_mac_operations ops;\n\tu8 addr[6];\n\tu8 perm_addr[6];\n\tenum e1000_mac_type type;\n\tu32 collision_delta;\n\tu32 ledctl_default;\n\tu32 ledctl_mode1;\n\tu32 ledctl_mode2;\n\tu32 mc_filter_type;\n\tu32 tx_packet_delta;\n\tu32 txcw;\n\tu16 current_ifs_val;\n\tu16 ifs_max_val;\n\tu16 ifs_min_val;\n\tu16 ifs_ratio;\n\tu16 ifs_step_size;\n\tu16 mta_reg_count;\n\tu32 mta_shadow[128];\n\tu16 rar_entry_count;\n\tu8 forced_speed_duplex;\n\tbool adaptive_ifs;\n\tbool has_fwsm;\n\tbool arc_subsystem_valid;\n\tbool autoneg;\n\tbool autoneg_failed;\n\tbool get_link_status;\n\tbool in_ifs_mode;\n\tbool serdes_has_link;\n\tbool tx_pkt_filtering;\n\tenum e1000_serdes_link_state serdes_link_state;\n};\n\nstruct e1000_fc_info {\n\tu32 high_water;\n\tu32 low_water;\n\tu16 pause_time;\n\tu16 refresh_time;\n\tbool send_xon;\n\tbool strict_ieee;\n\tenum e1000_fc_mode current_mode;\n\tenum e1000_fc_mode requested_mode;\n};\n\nstruct e1000_phy_operations {\n\ts32 (*acquire)(struct e1000_hw___2 *);\n\ts32 (*cfg_on_link_up)(struct e1000_hw___2 *);\n\ts32 (*check_polarity)(struct e1000_hw___2 *);\n\ts32 (*check_reset_block)(struct e1000_hw___2 *);\n\ts32 (*commit)(struct e1000_hw___2 *);\n\ts32 (*force_speed_duplex)(struct e1000_hw___2 *);\n\ts32 (*get_cfg_done)(struct e1000_hw___2 *);\n\ts32 (*get_cable_length)(struct e1000_hw___2 *);\n\ts32 (*get_info)(struct e1000_hw___2 *);\n\ts32 (*set_page)(struct e1000_hw___2 *, u16);\n\ts32 (*read_reg)(struct e1000_hw___2 *, u32, u16 *);\n\ts32 (*read_reg_locked)(struct e1000_hw___2 *, u32, u16 *);\n\ts32 (*read_reg_page)(struct e1000_hw___2 *, u32, u16 *);\n\tvoid (*release)(struct e1000_hw___2 *);\n\ts32 (*reset)(struct e1000_hw___2 *);\n\ts32 (*set_d0_lplu_state)(struct e1000_hw___2 *, bool);\n\ts32 (*set_d3_lplu_state)(struct e1000_hw___2 *, bool);\n\ts32 (*write_reg)(struct e1000_hw___2 *, u32, u16);\n\ts32 (*write_reg_locked)(struct e1000_hw___2 *, u32, u16);\n\ts32 (*write_reg_page)(struct e1000_hw___2 *, u32, u16);\n\tvoid (*power_up)(struct e1000_hw___2 *);\n\tvoid (*power_down)(struct e1000_hw___2 *);\n};\n\nstruct e1000_phy_info___2 {\n\tstruct e1000_phy_operations ops;\n\tenum e1000_phy_type type;\n\tenum e1000_1000t_rx_status local_rx;\n\tenum e1000_1000t_rx_status remote_rx;\n\tenum e1000_ms_type ms_type;\n\tenum e1000_ms_type original_ms_type;\n\tenum e1000_rev_polarity cable_polarity;\n\tenum e1000_smart_speed smart_speed;\n\tu32 addr;\n\tu32 id;\n\tu32 reset_delay_us;\n\tu32 revision;\n\tenum e1000_media_type media_type;\n\tu16 autoneg_advertised;\n\tu16 autoneg_mask;\n\tu16 cable_length;\n\tu16 max_cable_length;\n\tu16 min_cable_length;\n\tu8 mdix;\n\tbool disable_polarity_correction;\n\tbool is_mdix;\n\tbool polarity_correction;\n\tbool speed_downgraded;\n\tbool autoneg_wait_to_complete;\n};\n\nstruct e1000_nvm_operations {\n\ts32 (*acquire)(struct e1000_hw___2 *);\n\ts32 (*read)(struct e1000_hw___2 *, u16, u16, u16 *);\n\tvoid (*release)(struct e1000_hw___2 *);\n\tvoid (*reload)(struct e1000_hw___2 *);\n\ts32 (*update)(struct e1000_hw___2 *);\n\ts32 (*valid_led_default)(struct e1000_hw___2 *, u16 *);\n\ts32 (*validate)(struct e1000_hw___2 *);\n\ts32 (*write)(struct e1000_hw___2 *, u16, u16, u16 *);\n};\n\nstruct e1000_nvm_info {\n\tstruct e1000_nvm_operations ops;\n\tenum e1000_nvm_type type;\n\tenum e1000_nvm_override override;\n\tu32 flash_bank_size;\n\tu32 flash_base_addr;\n\tu16 word_size;\n\tu16 delay_usec;\n\tu16 address_bits;\n\tu16 opcode_bits;\n\tu16 page_size;\n};\n\nstruct e1000_bus_info {\n\tenum e1000_bus_width width;\n\tu16 func;\n};\n\nstruct e1000_dev_spec_82571 {\n\tbool laa_is_present;\n\tu32 smb_counter;\n};\n\nstruct e1000_dev_spec_80003es2lan {\n\tbool mdic_wa_enable;\n};\n\nstruct e1000_shadow_ram___2 {\n\tu16 value;\n\tbool modified;\n};\n\nenum e1000_ulp_state {\n\te1000_ulp_state_unknown = 0,\n\te1000_ulp_state_off = 1,\n\te1000_ulp_state_on = 2,\n};\n\nstruct e1000_dev_spec_ich8lan {\n\tbool kmrn_lock_loss_workaround_enabled;\n\tstruct e1000_shadow_ram___2 shadow_ram[2048];\n\tbool nvm_k1_enabled;\n\tbool eee_disable;\n\tu16 eee_lp_ability;\n\tenum e1000_ulp_state ulp_state;\n};\n\nstruct e1000_adapter___2;\n\nstruct e1000_hw___2 {\n\tstruct e1000_adapter___2 *adapter;\n\tvoid *hw_addr;\n\tvoid *flash_address;\n\tstruct e1000_mac_info mac;\n\tstruct e1000_fc_info fc;\n\tstruct e1000_phy_info___2 phy;\n\tstruct e1000_nvm_info nvm;\n\tstruct e1000_bus_info bus;\n\tstruct e1000_host_mng_dhcp_cookie mng_cookie;\n\tunion {\n\t\tstruct e1000_dev_spec_82571 e82571;\n\t\tstruct e1000_dev_spec_80003es2lan e80003es2lan;\n\t\tstruct e1000_dev_spec_ich8lan ich8lan;\n\t} dev_spec;\n};\n\nstruct e1000_phy_regs {\n\tu16 bmcr;\n\tu16 bmsr;\n\tu16 advertise;\n\tu16 lpa;\n\tu16 expansion;\n\tu16 ctrl1000;\n\tu16 stat1000;\n\tu16 estatus;\n};\n\nstruct e1000_buffer;\n\nstruct e1000_ring {\n\tstruct e1000_adapter___2 *adapter;\n\tvoid *desc;\n\tdma_addr_t dma;\n\tunsigned int size;\n\tunsigned int count;\n\tu16 next_to_use;\n\tu16 next_to_clean;\n\tvoid *head;\n\tvoid *tail;\n\tstruct e1000_buffer *buffer_info;\n\tchar name[21];\n\tu32 ims_val;\n\tu32 itr_val;\n\tvoid *itr_register;\n\tint set_itr;\n\tstruct sk_buff *rx_skb_top;\n};\n\nstruct e1000_info;\n\nstruct e1000_adapter___2 {\n\tstruct timer_list watchdog_timer;\n\tstruct timer_list phy_info_timer;\n\tstruct timer_list blink_timer;\n\tstruct work_struct reset_task;\n\tstruct work_struct watchdog_task;\n\tconst struct e1000_info *ei;\n\tlong unsigned int active_vlans[64];\n\tu32 bd_number;\n\tu32 rx_buffer_len;\n\tu16 mng_vlan_id;\n\tu16 link_speed;\n\tu16 link_duplex;\n\tu16 eeprom_vers;\n\tlong unsigned int state;\n\tu32 itr;\n\tu32 itr_setting;\n\tu16 tx_itr;\n\tu16 rx_itr;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct e1000_ring *tx_ring;\n\tu32 tx_fifo_limit;\n\tstruct napi_struct napi;\n\tunsigned int uncorr_errors;\n\tunsigned int corr_errors;\n\tunsigned int restart_queue;\n\tu32 txd_cmd;\n\tbool detect_tx_hung;\n\tbool tx_hang_recheck;\n\tu8 tx_timeout_factor;\n\tu32 tx_int_delay;\n\tu32 tx_abs_int_delay;\n\tunsigned int total_tx_bytes;\n\tunsigned int total_tx_packets;\n\tunsigned int total_rx_bytes;\n\tunsigned int total_rx_packets;\n\tu64 tpt_old;\n\tu64 colc_old;\n\tu32 gotc;\n\tu64 gotc_old;\n\tu32 tx_timeout_count;\n\tu32 tx_fifo_head;\n\tu32 tx_head_addr;\n\tu32 tx_fifo_size;\n\tu32 tx_dma_failed;\n\tu32 tx_hwtstamp_timeouts;\n\tu32 tx_hwtstamp_skipped;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tbool (*clean_rx)(struct e1000_ring *, int *, int);\n\tvoid (*alloc_rx_buf)(struct e1000_ring *, int, gfp_t);\n\tstruct e1000_ring *rx_ring;\n\tu32 rx_int_delay;\n\tu32 rx_abs_int_delay;\n\tu64 hw_csum_err;\n\tu64 hw_csum_good;\n\tu64 rx_hdr_split;\n\tu32 gorc;\n\tu64 gorc_old;\n\tu32 alloc_rx_buff_failed;\n\tu32 rx_dma_failed;\n\tu32 rx_hwtstamp_cleared;\n\tunsigned int rx_ps_pages;\n\tu16 rx_ps_bsize0;\n\tu32 max_frame_size;\n\tu32 min_frame_size;\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\tstruct e1000_hw___2 hw;\n\tspinlock_t stats64_lock;\n\tstruct e1000_hw_stats___2 stats;\n\tstruct e1000_phy_info___2 phy_info;\n\tstruct e1000_phy_stats phy_stats;\n\tstruct e1000_phy_regs phy_regs;\n\tstruct e1000_ring test_tx_ring;\n\tstruct e1000_ring test_rx_ring;\n\tu32 test_icr;\n\tu32 msg_enable;\n\tunsigned int num_vectors;\n\tstruct msix_entry *msix_entries;\n\tint int_mode;\n\tu32 eiac_mask;\n\tu32 eeprom_wol;\n\tu32 wol;\n\tu32 pba;\n\tu32 max_hw_frame_size;\n\tbool fc_autoneg;\n\tunsigned int flags;\n\tunsigned int flags2;\n\tstruct work_struct downshift_task;\n\tstruct work_struct update_phy_task;\n\tstruct work_struct print_hang_task;\n\tint phy_hang_count;\n\tu16 tx_ring_count;\n\tu16 rx_ring_count;\n\tstruct hwtstamp_config hwtstamp_config;\n\tstruct delayed_work systim_overflow_work;\n\tstruct sk_buff *tx_hwtstamp_skb;\n\tlong unsigned int tx_hwtstamp_start;\n\tstruct work_struct tx_hwtstamp_work;\n\tspinlock_t systim_lock;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_clock_info;\n\tstruct pm_qos_request pm_qos_req;\n\ts32 ptp_delta;\n\tu16 eee_advert;\n\tlong: 16;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct e1000_ps_page {\n\tstruct page *page;\n\tu64 dma;\n};\n\nstruct e1000_buffer {\n\tdma_addr_t dma;\n\tstruct sk_buff *skb;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int time_stamp;\n\t\t\tu16 length;\n\t\t\tu16 next_to_watch;\n\t\t\tunsigned int segs;\n\t\t\tunsigned int bytecount;\n\t\t\tu16 mapped_as_page;\n\t\t};\n\t\tstruct {\n\t\t\tstruct e1000_ps_page *ps_pages;\n\t\t\tstruct page *page;\n\t\t};\n\t};\n};\n\nstruct e1000_info {\n\tenum e1000_mac_type mac;\n\tunsigned int flags;\n\tunsigned int flags2;\n\tu32 pba;\n\tu32 max_hw_frame_size;\n\ts32 (*get_variants)(struct e1000_adapter___2 *);\n\tconst struct e1000_mac_operations *mac_ops;\n\tconst struct e1000_phy_operations *phy_ops;\n\tconst struct e1000_nvm_operations *nvm_ops;\n};\n\nenum e1000_state_t___2 {\n\t__E1000_TESTING___2 = 0,\n\t__E1000_RESETTING___2 = 1,\n\t__E1000_ACCESS_SHARED_RESOURCE = 2,\n\t__E1000_DOWN___2 = 3,\n};\n\nstruct ich8_hsfsts {\n\tu16 flcdone: 1;\n\tu16 flcerr: 1;\n\tu16 dael: 1;\n\tu16 berasesz: 2;\n\tu16 flcinprog: 1;\n\tu16 reserved1: 2;\n\tu16 reserved2: 6;\n\tu16 fldesvalid: 1;\n\tu16 flockdn: 1;\n};\n\nunion ich8_hws_flash_status {\n\tstruct ich8_hsfsts hsf_status;\n\tu16 regval;\n};\n\nstruct ich8_hsflctl {\n\tu16 flcgo: 1;\n\tu16 flcycle: 2;\n\tu16 reserved: 5;\n\tu16 fldbcount: 2;\n\tu16 flockdn: 6;\n};\n\nunion ich8_hws_flash_ctrl {\n\tstruct ich8_hsflctl hsf_ctrl;\n\tu16 regval;\n};\n\nstruct ich8_pr {\n\tu32 base: 13;\n\tu32 reserved1: 2;\n\tu32 rpe: 1;\n\tu32 limit: 13;\n\tu32 reserved2: 2;\n\tu32 wpe: 1;\n};\n\nunion ich8_flash_protected_range {\n\tstruct ich8_pr range;\n\tu32 regval;\n};\n\nstruct e1000_host_mng_command_header {\n\tu8 command_id;\n\tu8 checksum;\n\tu16 reserved1;\n\tu16 reserved2;\n\tu16 command_length;\n};\n\nenum e1000_mng_mode {\n\te1000_mng_mode_none = 0,\n\te1000_mng_mode_asf = 1,\n\te1000_mng_mode_pt = 2,\n\te1000_mng_mode_ipmi = 3,\n\te1000_mng_mode_host_if_only = 4,\n};\n\nstruct e1000_option___2 {\n\tenum {\n\t\tenable_option___2 = 0,\n\t\trange_option___2 = 1,\n\t\tlist_option___2 = 2,\n\t} type;\n\tconst char *name;\n\tconst char *err;\n\tint def;\n\tunion {\n\t\tstruct {\n\t\t\tint min;\n\t\t\tint max;\n\t\t} r;\n\t\tstruct {\n\t\t\tint nr;\n\t\t\tstruct e1000_opt_list *p;\n\t\t} l;\n\t} arg;\n};\n\nunion e1000_rx_desc_extended {\n\tstruct {\n\t\t__le64 buffer_addr;\n\t\t__le64 reserved;\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length;\n\t\t\t__le16 vlan;\n\t\t} upper;\n\t} wb;\n};\n\nenum pkt_hash_types {\n\tPKT_HASH_TYPE_NONE = 0,\n\tPKT_HASH_TYPE_L2 = 1,\n\tPKT_HASH_TYPE_L3 = 2,\n\tPKT_HASH_TYPE_L4 = 3,\n};\n\nunion e1000_rx_desc_packet_split {\n\tstruct {\n\t\t__le64 buffer_addr[4];\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq;\n\t\t\tunion {\n\t\t\t\t__le32 rss;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id;\n\t\t\t\t\t__le16 csum;\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error;\n\t\t\t__le16 length0;\n\t\t\t__le16 vlan;\n\t\t} middle;\n\t\tstruct {\n\t\t\t__le16 header_status;\n\t\t\t__le16 length[3];\n\t\t} upper;\n\t\t__le64 reserved;\n\t} wb;\n};\n\nenum e1000_boards {\n\tboard_82571 = 0,\n\tboard_82572 = 1,\n\tboard_82573 = 2,\n\tboard_82574 = 3,\n\tboard_82583 = 4,\n\tboard_80003es2lan = 5,\n\tboard_ich8lan = 6,\n\tboard_ich9lan = 7,\n\tboard_ich10lan = 8,\n\tboard_pchlan = 9,\n\tboard_pch2lan = 10,\n\tboard_pch_lpt = 11,\n\tboard_pch_spt = 12,\n\tboard_pch_cnp = 13,\n};\n\nstruct e1000_reg_info {\n\tu32 ofs;\n\tchar *name;\n};\n\nstruct e1000e_me_supported {\n\tu16 device_id;\n};\n\nstruct my_u0 {\n\t__le64 a;\n\t__le64 b;\n};\n\nstruct my_u1 {\n\t__le64 a;\n\t__le64 b;\n\t__le64 c;\n\t__le64 d;\n};\n\nenum {\n\tPCI_DEV_REG1 = 64,\n\tPCI_DEV_REG2 = 68,\n\tPCI_DEV_STATUS = 124,\n\tPCI_DEV_REG3 = 128,\n\tPCI_DEV_REG4 = 132,\n\tPCI_DEV_REG5 = 136,\n\tPCI_CFG_REG_0 = 144,\n\tPCI_CFG_REG_1 = 148,\n\tPSM_CONFIG_REG0 = 152,\n\tPSM_CONFIG_REG1 = 156,\n\tPSM_CONFIG_REG2 = 352,\n\tPSM_CONFIG_REG3 = 356,\n\tPSM_CONFIG_REG4 = 360,\n\tPCI_LDO_CTRL = 188,\n};\n\nenum pci_dev_reg_1 {\n\tPCI_Y2_PIG_ENA = 2147483648,\n\tPCI_Y2_DLL_DIS = 1073741824,\n\tPCI_SW_PWR_ON_RST = 1073741824,\n\tPCI_Y2_PHY2_COMA = 536870912,\n\tPCI_Y2_PHY1_COMA = 268435456,\n\tPCI_Y2_PHY2_POWD = 134217728,\n\tPCI_Y2_PHY1_POWD = 67108864,\n\tPCI_Y2_PME_LEGACY = 32768,\n\tPCI_PHY_LNK_TIM_MSK = 768,\n\tPCI_ENA_L1_EVENT = 128,\n\tPCI_ENA_GPHY_LNK = 64,\n\tPCI_FORCE_PEX_L1 = 32,\n};\n\nenum pci_dev_reg_2 {\n\tPCI_VPD_WR_THR = 4278190080,\n\tPCI_DEV_SEL = 16646144,\n\tPCI_VPD_ROM_SZ = 114688,\n\tPCI_PATCH_DIR = 3840,\n\tPCI_EXT_PATCHS = 240,\n\tPCI_EN_DUMMY_RD = 8,\n\tPCI_REV_DESC = 4,\n\tPCI_USEDATA64 = 1,\n};\n\nenum pci_dev_reg_3 {\n\tP_CLK_ASF_REGS_DIS = 262144,\n\tP_CLK_COR_REGS_D0_DIS = 131072,\n\tP_CLK_MACSEC_DIS = 131072,\n\tP_CLK_PCI_REGS_D0_DIS = 65536,\n\tP_CLK_COR_YTB_ARB_DIS = 32768,\n\tP_CLK_MAC_LNK1_D3_DIS = 16384,\n\tP_CLK_COR_LNK1_D0_DIS = 8192,\n\tP_CLK_MAC_LNK1_D0_DIS = 4096,\n\tP_CLK_COR_LNK1_D3_DIS = 2048,\n\tP_CLK_PCI_MST_ARB_DIS = 1024,\n\tP_CLK_COR_REGS_D3_DIS = 512,\n\tP_CLK_PCI_REGS_D3_DIS = 256,\n\tP_CLK_REF_LNK1_GM_DIS = 128,\n\tP_CLK_COR_LNK1_GM_DIS = 64,\n\tP_CLK_PCI_COMMON_DIS = 32,\n\tP_CLK_COR_COMMON_DIS = 16,\n\tP_CLK_PCI_LNK1_BMU_DIS = 8,\n\tP_CLK_COR_LNK1_BMU_DIS = 4,\n\tP_CLK_PCI_LNK1_BIU_DIS = 2,\n\tP_CLK_COR_LNK1_BIU_DIS = 1,\n\tPCIE_OUR3_WOL_D3_COLD_SET = 406548,\n};\n\nenum pci_dev_reg_4 {\n\tP_PEX_LTSSM_STAT_MSK = 4261412864,\n\tP_PEX_LTSSM_L1_STAT = 52,\n\tP_PEX_LTSSM_DET_STAT = 1,\n\tP_TIMER_VALUE_MSK = 16711680,\n\tP_FORCE_ASPM_REQUEST = 32768,\n\tP_ASPM_GPHY_LINK_DOWN = 16384,\n\tP_ASPM_INT_FIFO_EMPTY = 8192,\n\tP_ASPM_CLKRUN_REQUEST = 4096,\n\tP_ASPM_FORCE_CLKREQ_ENA = 16,\n\tP_ASPM_CLKREQ_PAD_CTL = 8,\n\tP_ASPM_A1_MODE_SELECT = 4,\n\tP_CLK_GATE_PEX_UNIT_ENA = 2,\n\tP_CLK_GATE_ROOT_COR_ENA = 1,\n\tP_ASPM_CONTROL_MSK = 61440,\n};\n\nenum pci_dev_reg_5 {\n\tP_CTL_DIV_CORE_CLK_ENA = 2147483648,\n\tP_CTL_SRESET_VMAIN_AV = 1073741824,\n\tP_CTL_BYPASS_VMAIN_AV = 536870912,\n\tP_CTL_TIM_VMAIN_AV_MSK = 402653184,\n\tP_REL_PCIE_RST_DE_ASS = 67108864,\n\tP_REL_GPHY_REC_PACKET = 33554432,\n\tP_REL_INT_FIFO_N_EMPTY = 16777216,\n\tP_REL_MAIN_PWR_AVAIL = 8388608,\n\tP_REL_CLKRUN_REQ_REL = 4194304,\n\tP_REL_PCIE_RESET_ASS = 2097152,\n\tP_REL_PME_ASSERTED = 1048576,\n\tP_REL_PCIE_EXIT_L1_ST = 524288,\n\tP_REL_LOADER_NOT_FIN = 262144,\n\tP_REL_PCIE_RX_EX_IDLE = 131072,\n\tP_REL_GPHY_LINK_UP = 65536,\n\tP_GAT_PCIE_RST_ASSERTED = 1024,\n\tP_GAT_GPHY_N_REC_PACKET = 512,\n\tP_GAT_INT_FIFO_EMPTY = 256,\n\tP_GAT_MAIN_PWR_N_AVAIL = 128,\n\tP_GAT_CLKRUN_REQ_REL = 64,\n\tP_GAT_PCIE_RESET_ASS = 32,\n\tP_GAT_PME_DE_ASSERTED = 16,\n\tP_GAT_PCIE_ENTER_L1_ST = 8,\n\tP_GAT_LOADER_FINISHED = 4,\n\tP_GAT_PCIE_RX_EL_IDLE = 2,\n\tP_GAT_GPHY_LINK_DOWN = 1,\n\tPCIE_OUR5_EVENT_CLK_D3_SET = 50987786,\n};\n\nenum {\n\tPSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_MSK = 240,\n\tPSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE = 4,\n\tPSM_CONFIG_REG4_DEBUG_TIMER = 2,\n\tPSM_CONFIG_REG4_RST_PHY_LINK_DETECT = 1,\n};\n\nenum csr_regs {\n\tB0_RAP = 0,\n\tB0_CTST = 4,\n\tB0_POWER_CTRL = 7,\n\tB0_ISRC = 8,\n\tB0_IMSK = 12,\n\tB0_HWE_ISRC = 16,\n\tB0_HWE_IMSK = 20,\n\tB0_Y2_SP_ISRC2 = 28,\n\tB0_Y2_SP_ISRC3 = 32,\n\tB0_Y2_SP_EISR = 36,\n\tB0_Y2_SP_LISR = 40,\n\tB0_Y2_SP_ICR = 44,\n\tB2_MAC_1 = 256,\n\tB2_MAC_2 = 264,\n\tB2_MAC_3 = 272,\n\tB2_CONN_TYP = 280,\n\tB2_PMD_TYP = 281,\n\tB2_MAC_CFG = 282,\n\tB2_CHIP_ID = 283,\n\tB2_E_0 = 284,\n\tB2_Y2_CLK_GATE = 285,\n\tB2_Y2_HW_RES = 286,\n\tB2_E_3 = 287,\n\tB2_Y2_CLK_CTRL = 288,\n\tB2_TI_INI = 304,\n\tB2_TI_VAL = 308,\n\tB2_TI_CTRL = 312,\n\tB2_TI_TEST = 313,\n\tB2_TST_CTRL1 = 344,\n\tB2_TST_CTRL2 = 345,\n\tB2_GP_IO = 348,\n\tB2_I2C_CTRL = 352,\n\tB2_I2C_DATA = 356,\n\tB2_I2C_IRQ = 360,\n\tB2_I2C_SW = 364,\n\tY2_PEX_PHY_DATA = 368,\n\tY2_PEX_PHY_ADDR = 370,\n\tB3_RAM_ADDR = 384,\n\tB3_RAM_DATA_LO = 388,\n\tB3_RAM_DATA_HI = 392,\n\tB3_RI_WTO_R1 = 400,\n\tB3_RI_WTO_XA1 = 401,\n\tB3_RI_WTO_XS1 = 402,\n\tB3_RI_RTO_R1 = 403,\n\tB3_RI_RTO_XA1 = 404,\n\tB3_RI_RTO_XS1 = 405,\n\tB3_RI_WTO_R2 = 406,\n\tB3_RI_WTO_XA2 = 407,\n\tB3_RI_WTO_XS2 = 408,\n\tB3_RI_RTO_R2 = 409,\n\tB3_RI_RTO_XA2 = 410,\n\tB3_RI_RTO_XS2 = 411,\n\tB3_RI_TO_VAL = 412,\n\tB3_RI_CTRL = 416,\n\tB3_RI_TEST = 418,\n\tB3_MA_TOINI_RX1 = 432,\n\tB3_MA_TOINI_RX2 = 433,\n\tB3_MA_TOINI_TX1 = 434,\n\tB3_MA_TOINI_TX2 = 435,\n\tB3_MA_TOVAL_RX1 = 436,\n\tB3_MA_TOVAL_RX2 = 437,\n\tB3_MA_TOVAL_TX1 = 438,\n\tB3_MA_TOVAL_TX2 = 439,\n\tB3_MA_TO_CTRL = 440,\n\tB3_MA_TO_TEST = 442,\n\tB3_MA_RCINI_RX1 = 448,\n\tB3_MA_RCINI_RX2 = 449,\n\tB3_MA_RCINI_TX1 = 450,\n\tB3_MA_RCINI_TX2 = 451,\n\tB3_MA_RCVAL_RX1 = 452,\n\tB3_MA_RCVAL_RX2 = 453,\n\tB3_MA_RCVAL_TX1 = 454,\n\tB3_MA_RCVAL_TX2 = 455,\n\tB3_MA_RC_CTRL = 456,\n\tB3_MA_RC_TEST = 458,\n\tB3_PA_TOINI_RX1 = 464,\n\tB3_PA_TOINI_RX2 = 468,\n\tB3_PA_TOINI_TX1 = 472,\n\tB3_PA_TOINI_TX2 = 476,\n\tB3_PA_TOVAL_RX1 = 480,\n\tB3_PA_TOVAL_RX2 = 484,\n\tB3_PA_TOVAL_TX1 = 488,\n\tB3_PA_TOVAL_TX2 = 492,\n\tB3_PA_CTRL = 496,\n\tB3_PA_TEST = 498,\n\tY2_CFG_SPC = 7168,\n\tY2_CFG_AER = 7424,\n};\n\nenum {\n\tY2_VMAIN_AVAIL = 131072,\n\tY2_VAUX_AVAIL = 65536,\n\tY2_HW_WOL_ON = 32768,\n\tY2_HW_WOL_OFF = 16384,\n\tY2_ASF_ENABLE = 8192,\n\tY2_ASF_DISABLE = 4096,\n\tY2_CLK_RUN_ENA = 2048,\n\tY2_CLK_RUN_DIS = 1024,\n\tY2_LED_STAT_ON = 512,\n\tY2_LED_STAT_OFF = 256,\n\tCS_ST_SW_IRQ = 128,\n\tCS_CL_SW_IRQ = 64,\n\tCS_STOP_DONE = 32,\n\tCS_STOP_MAST = 16,\n\tCS_MRST_CLR = 8,\n\tCS_MRST_SET = 4,\n\tCS_RST_CLR = 2,\n\tCS_RST_SET = 1,\n};\n\nenum {\n\tPC_VAUX_ENA = 128,\n\tPC_VAUX_DIS = 64,\n\tPC_VCC_ENA = 32,\n\tPC_VCC_DIS = 16,\n\tPC_VAUX_ON = 8,\n\tPC_VAUX_OFF = 4,\n\tPC_VCC_ON = 2,\n\tPC_VCC_OFF = 1,\n};\n\nenum {\n\tY2_IS_HW_ERR = 2147483648,\n\tY2_IS_STAT_BMU = 1073741824,\n\tY2_IS_ASF = 536870912,\n\tY2_IS_CPU_TO = 268435456,\n\tY2_IS_POLL_CHK = 134217728,\n\tY2_IS_TWSI_RDY = 67108864,\n\tY2_IS_IRQ_SW = 33554432,\n\tY2_IS_TIMINT = 16777216,\n\tY2_IS_IRQ_PHY2 = 4096,\n\tY2_IS_IRQ_MAC2 = 2048,\n\tY2_IS_CHK_RX2 = 1024,\n\tY2_IS_CHK_TXS2 = 512,\n\tY2_IS_CHK_TXA2 = 256,\n\tY2_IS_PSM_ACK = 128,\n\tY2_IS_PTP_TIST = 64,\n\tY2_IS_PHY_QLNK = 32,\n\tY2_IS_IRQ_PHY1 = 16,\n\tY2_IS_IRQ_MAC1 = 8,\n\tY2_IS_CHK_RX1 = 4,\n\tY2_IS_CHK_TXS1 = 2,\n\tY2_IS_CHK_TXA1 = 1,\n\tY2_IS_BASE = 3221225472,\n\tY2_IS_PORT_1 = 29,\n\tY2_IS_PORT_2 = 7424,\n\tY2_IS_ERROR = 2147486989,\n};\n\nenum {\n\tY2_IS_TIST_OV = 536870912,\n\tY2_IS_SENSOR = 268435456,\n\tY2_IS_MST_ERR = 134217728,\n\tY2_IS_IRQ_STAT = 67108864,\n\tY2_IS_PCI_EXP = 33554432,\n\tY2_IS_PCI_NEXP = 16777216,\n\tY2_IS_PAR_RD2 = 8192,\n\tY2_IS_PAR_WR2 = 4096,\n\tY2_IS_PAR_MAC2 = 2048,\n\tY2_IS_PAR_RX2 = 1024,\n\tY2_IS_TCP_TXS2 = 512,\n\tY2_IS_TCP_TXA2 = 256,\n\tY2_IS_PAR_RD1 = 32,\n\tY2_IS_PAR_WR1 = 16,\n\tY2_IS_PAR_MAC1 = 8,\n\tY2_IS_PAR_RX1 = 4,\n\tY2_IS_TCP_TXS1 = 2,\n\tY2_IS_TCP_TXA1 = 1,\n\tY2_HWE_L1_MASK = 63,\n\tY2_HWE_L2_MASK = 16128,\n\tY2_HWE_ALL_MASK = 738213695,\n};\n\nenum {\n\tDPT_START = 2,\n\tDPT_STOP = 1,\n};\n\nenum {\n\tTST_FRC_DPERR_MR = 128,\n\tTST_FRC_DPERR_MW = 64,\n\tTST_FRC_DPERR_TR = 32,\n\tTST_FRC_DPERR_TW = 16,\n\tTST_FRC_APERR_M = 8,\n\tTST_FRC_APERR_T = 4,\n\tTST_CFG_WRITE_ON = 2,\n\tTST_CFG_WRITE_OFF = 1,\n};\n\nenum {\n\tGLB_GPIO_CLK_DEB_ENA = 2147483648,\n\tGLB_GPIO_CLK_DBG_MSK = 1006632960,\n\tGLB_GPIO_INT_RST_D3_DIS = 32768,\n\tGLB_GPIO_LED_PAD_SPEED_UP = 16384,\n\tGLB_GPIO_STAT_RACE_DIS = 8192,\n\tGLB_GPIO_TEST_SEL_MSK = 6144,\n\tGLB_GPIO_TEST_SEL_BASE = 2048,\n\tGLB_GPIO_RAND_ENA = 1024,\n\tGLB_GPIO_RAND_BIT_1 = 512,\n};\n\nenum {\n\tCFG_CHIP_R_MSK = 240,\n\tCFG_DIS_M2_CLK = 2,\n\tCFG_SNG_MAC = 1,\n};\n\nenum {\n\tCHIP_ID_YUKON_XL = 179,\n\tCHIP_ID_YUKON_EC_U = 180,\n\tCHIP_ID_YUKON_EX = 181,\n\tCHIP_ID_YUKON_EC = 182,\n\tCHIP_ID_YUKON_FE = 183,\n\tCHIP_ID_YUKON_FE_P = 184,\n\tCHIP_ID_YUKON_SUPR = 185,\n\tCHIP_ID_YUKON_UL_2 = 186,\n\tCHIP_ID_YUKON_OPT = 188,\n\tCHIP_ID_YUKON_PRM = 189,\n\tCHIP_ID_YUKON_OP_2 = 190,\n};\n\nenum yukon_xl_rev {\n\tCHIP_REV_YU_XL_A0 = 0,\n\tCHIP_REV_YU_XL_A1 = 1,\n\tCHIP_REV_YU_XL_A2 = 2,\n\tCHIP_REV_YU_XL_A3 = 3,\n};\n\nenum yukon_ec_rev {\n\tCHIP_REV_YU_EC_A1 = 0,\n\tCHIP_REV_YU_EC_A2 = 1,\n\tCHIP_REV_YU_EC_A3 = 2,\n};\n\nenum yukon_ec_u_rev {\n\tCHIP_REV_YU_EC_U_A0 = 1,\n\tCHIP_REV_YU_EC_U_A1 = 2,\n\tCHIP_REV_YU_EC_U_B0 = 3,\n\tCHIP_REV_YU_EC_U_B1 = 5,\n};\n\nenum yukon_fe_p_rev {\n\tCHIP_REV_YU_FE2_A0 = 0,\n};\n\nenum yukon_ex_rev {\n\tCHIP_REV_YU_EX_A0 = 1,\n\tCHIP_REV_YU_EX_B0 = 2,\n};\n\nenum yukon_supr_rev {\n\tCHIP_REV_YU_SU_A0 = 0,\n\tCHIP_REV_YU_SU_B0 = 1,\n\tCHIP_REV_YU_SU_B1 = 3,\n};\n\nenum yukon_prm_rev {\n\tCHIP_REV_YU_PRM_Z1 = 1,\n\tCHIP_REV_YU_PRM_A0 = 2,\n};\n\nenum {\n\tY2_STATUS_LNK2_INAC = 128,\n\tY2_CLK_GAT_LNK2_DIS = 64,\n\tY2_COR_CLK_LNK2_DIS = 32,\n\tY2_PCI_CLK_LNK2_DIS = 16,\n\tY2_STATUS_LNK1_INAC = 8,\n\tY2_CLK_GAT_LNK1_DIS = 4,\n\tY2_COR_CLK_LNK1_DIS = 2,\n\tY2_PCI_CLK_LNK1_DIS = 1,\n};\n\nenum {\n\tCFG_LED_MODE_MSK = 28,\n\tCFG_LINK_2_AVAIL = 2,\n\tCFG_LINK_1_AVAIL = 1,\n};\n\nenum {\n\tY2_CLK_DIV_VAL_MSK = 16711680,\n\tY2_CLK_DIV_VAL2_MSK = 14680064,\n\tY2_CLK_SELECT2_MSK = 2031616,\n\tY2_CLK_DIV_ENA = 2,\n\tY2_CLK_DIV_DIS = 1,\n};\n\nenum {\n\tTIM_START = 4,\n\tTIM_STOP = 2,\n\tTIM_CLR_IRQ = 1,\n};\n\nenum {\n\tPEX_RD_ACCESS = 2147483648,\n\tPEX_DB_ACCESS = 1073741824,\n};\n\nenum {\n\tRI_CLR_RD_PERR = 512,\n\tRI_CLR_WR_PERR = 256,\n\tRI_RST_CLR = 2,\n\tRI_RST_SET = 1,\n};\n\nenum {\n\tTXA_ENA_FSYNC = 128,\n\tTXA_DIS_FSYNC = 64,\n\tTXA_ENA_ALLOC = 32,\n\tTXA_DIS_ALLOC = 16,\n\tTXA_START_RC = 8,\n\tTXA_STOP_RC = 4,\n\tTXA_ENA_ARB = 2,\n\tTXA_DIS_ARB = 1,\n};\n\nenum {\n\tTXA_ITI_INI = 512,\n\tTXA_ITI_VAL = 516,\n\tTXA_LIM_INI = 520,\n\tTXA_LIM_VAL = 524,\n\tTXA_CTRL = 528,\n\tTXA_TEST = 529,\n\tTXA_STAT = 530,\n\tRSS_KEY = 544,\n\tRSS_CFG = 584,\n};\n\nenum {\n\tHASH_TCP_IPV6_EX_CTRL = 32,\n\tHASH_IPV6_EX_CTRL = 16,\n\tHASH_TCP_IPV6_CTRL = 8,\n\tHASH_IPV6_CTRL = 4,\n\tHASH_TCP_IPV4_CTRL = 2,\n\tHASH_IPV4_CTRL = 1,\n\tHASH_ALL = 63,\n};\n\nenum {\n\tB6_EXT_REG = 768,\n\tB7_CFG_SPC = 896,\n\tB8_RQ1_REGS = 1024,\n\tB8_RQ2_REGS = 1152,\n\tB8_TS1_REGS = 1536,\n\tB8_TA1_REGS = 1664,\n\tB8_TS2_REGS = 1792,\n\tB8_TA2_REGS = 1920,\n\tB16_RAM_REGS = 2048,\n};\n\nenum {\n\tB8_Q_REGS = 1024,\n\tQ_D = 0,\n\tQ_VLAN = 32,\n\tQ_DONE = 36,\n\tQ_AC_L = 40,\n\tQ_AC_H = 44,\n\tQ_BC = 48,\n\tQ_CSR = 52,\n\tQ_TEST = 56,\n\tQ_WM = 64,\n\tQ_AL = 66,\n\tQ_RSP = 68,\n\tQ_RSL = 70,\n\tQ_RP = 72,\n\tQ_RL = 74,\n\tQ_WP = 76,\n\tQ_WSP = 77,\n\tQ_WL = 78,\n\tQ_WSL = 79,\n};\n\nenum {\n\tF_TX_CHK_AUTO_OFF = 2147483648,\n\tF_TX_CHK_AUTO_ON = 1073741824,\n\tF_M_RX_RAM_DIS = 16777216,\n};\n\nenum {\n\tY2_B8_PREF_REGS = 1104,\n\tPREF_UNIT_CTRL = 0,\n\tPREF_UNIT_LAST_IDX = 4,\n\tPREF_UNIT_ADDR_LO = 8,\n\tPREF_UNIT_ADDR_HI = 12,\n\tPREF_UNIT_GET_IDX = 16,\n\tPREF_UNIT_PUT_IDX = 20,\n\tPREF_UNIT_FIFO_WP = 32,\n\tPREF_UNIT_FIFO_RP = 36,\n\tPREF_UNIT_FIFO_WM = 40,\n\tPREF_UNIT_FIFO_LEV = 44,\n\tPREF_UNIT_MASK_IDX = 4095,\n};\n\nenum {\n\tRB_START = 0,\n\tRB_END = 4,\n\tRB_WP = 8,\n\tRB_RP = 12,\n\tRB_RX_UTPP = 16,\n\tRB_RX_LTPP = 20,\n\tRB_RX_UTHP = 24,\n\tRB_RX_LTHP = 28,\n\tRB_PC = 32,\n\tRB_LEV = 36,\n\tRB_CTRL = 40,\n\tRB_TST1 = 41,\n\tRB_TST2 = 42,\n};\n\nenum {\n\tQ_R1 = 0,\n\tQ_R2 = 128,\n\tQ_XS1 = 512,\n\tQ_XA1 = 640,\n\tQ_XS2 = 768,\n\tQ_XA2 = 896,\n};\n\nenum {\n\tPHY_ADDR_MARV = 0,\n};\n\nenum {\n\tLNK_SYNC_INI = 3120,\n\tLNK_SYNC_VAL = 3124,\n\tLNK_SYNC_CTRL = 3128,\n\tLNK_SYNC_TST = 3129,\n\tLNK_LED_REG = 3132,\n\tRX_GMF_EA = 3136,\n\tRX_GMF_AF_THR = 3140,\n\tRX_GMF_CTRL_T = 3144,\n\tRX_GMF_FL_MSK = 3148,\n\tRX_GMF_FL_THR = 3152,\n\tRX_GMF_FL_CTRL = 3154,\n\tRX_GMF_TR_THR = 3156,\n\tRX_GMF_UP_THR = 3160,\n\tRX_GMF_LP_THR = 3162,\n\tRX_GMF_VLAN = 3164,\n\tRX_GMF_WP = 3168,\n\tRX_GMF_WLEV = 3176,\n\tRX_GMF_RP = 3184,\n\tRX_GMF_RLEV = 3192,\n};\n\nenum {\n\tBMU_IDLE = 2147483648,\n\tBMU_RX_TCP_PKT = 1073741824,\n\tBMU_RX_IP_PKT = 536870912,\n\tBMU_ENA_RX_RSS_HASH = 32768,\n\tBMU_DIS_RX_RSS_HASH = 16384,\n\tBMU_ENA_RX_CHKSUM = 8192,\n\tBMU_DIS_RX_CHKSUM = 4096,\n\tBMU_CLR_IRQ_PAR = 2048,\n\tBMU_CLR_IRQ_TCP = 2048,\n\tBMU_CLR_IRQ_CHK = 1024,\n\tBMU_STOP = 512,\n\tBMU_START = 256,\n\tBMU_FIFO_OP_ON = 128,\n\tBMU_FIFO_OP_OFF = 64,\n\tBMU_FIFO_ENA = 32,\n\tBMU_FIFO_RST = 16,\n\tBMU_OP_ON = 8,\n\tBMU_OP_OFF = 4,\n\tBMU_RST_CLR = 2,\n\tBMU_RST_SET = 1,\n\tBMU_CLR_RESET = 22,\n\tBMU_OPER_INIT = 3368,\n\tBMU_WM_DEFAULT = 1536,\n\tBMU_WM_PEX = 128,\n};\n\nenum {\n\tTBMU_TEST_BMU_TX_CHK_AUTO_OFF = 2147483648,\n\tTBMU_TEST_BMU_TX_CHK_AUTO_ON = 1073741824,\n\tTBMU_TEST_HOME_ADD_PAD_FIX1_EN = 536870912,\n\tTBMU_TEST_HOME_ADD_PAD_FIX1_DIS = 268435456,\n\tTBMU_TEST_ROUTING_ADD_FIX_EN = 134217728,\n\tTBMU_TEST_ROUTING_ADD_FIX_DIS = 67108864,\n\tTBMU_TEST_HOME_ADD_FIX_EN = 33554432,\n\tTBMU_TEST_HOME_ADD_FIX_DIS = 16777216,\n\tTBMU_TEST_TEST_RSPTR_ON = 4194304,\n\tTBMU_TEST_TEST_RSPTR_OFF = 2097152,\n\tTBMU_TEST_TESTSTEP_RSPTR = 1048576,\n\tTBMU_TEST_TEST_RPTR_ON = 262144,\n\tTBMU_TEST_TEST_RPTR_OFF = 131072,\n\tTBMU_TEST_TESTSTEP_RPTR = 65536,\n\tTBMU_TEST_TEST_WSPTR_ON = 16384,\n\tTBMU_TEST_TEST_WSPTR_OFF = 8192,\n\tTBMU_TEST_TESTSTEP_WSPTR = 4096,\n\tTBMU_TEST_TEST_WPTR_ON = 1024,\n\tTBMU_TEST_TEST_WPTR_OFF = 512,\n\tTBMU_TEST_TESTSTEP_WPTR = 256,\n\tTBMU_TEST_TEST_REQ_NB_ON = 64,\n\tTBMU_TEST_TEST_REQ_NB_OFF = 32,\n\tTBMU_TEST_TESTSTEP_REQ_NB = 16,\n\tTBMU_TEST_TEST_DONE_IDX_ON = 4,\n\tTBMU_TEST_TEST_DONE_IDX_OFF = 2,\n\tTBMU_TEST_TESTSTEP_DONE_IDX = 1,\n};\n\nenum {\n\tPREF_UNIT_OP_ON = 8,\n\tPREF_UNIT_OP_OFF = 4,\n\tPREF_UNIT_RST_CLR = 2,\n\tPREF_UNIT_RST_SET = 1,\n};\n\nenum {\n\tRB_ENA_STFWD = 32,\n\tRB_DIS_STFWD = 16,\n\tRB_ENA_OP_MD = 8,\n\tRB_DIS_OP_MD = 4,\n\tRB_RST_CLR = 2,\n\tRB_RST_SET = 1,\n};\n\nenum {\n\tTX_GMF_EA = 3392,\n\tTX_GMF_AE_THR = 3396,\n\tTX_GMF_CTRL_T = 3400,\n\tTX_GMF_WP = 3424,\n\tTX_GMF_WSP = 3428,\n\tTX_GMF_WLEV = 3432,\n\tTX_GMF_RP = 3440,\n\tTX_GMF_RSTP = 3444,\n\tTX_GMF_RLEV = 3448,\n\tECU_AE_THR = 112,\n\tECU_TXFF_LEV = 416,\n\tECU_JUMBO_WM = 128,\n};\n\nenum {\n\tB28_DPT_INI = 3584,\n\tB28_DPT_VAL = 3588,\n\tB28_DPT_CTRL = 3592,\n\tB28_DPT_TST = 3594,\n};\n\nenum {\n\tGMAC_TI_ST_VAL = 3604,\n\tGMAC_TI_ST_CTRL = 3608,\n\tGMAC_TI_ST_TST = 3610,\n};\n\nenum {\n\tCPU_WDOG = 3656,\n\tCPU_CNTR = 3660,\n\tCPU_TIM = 3664,\n\tCPU_AHB_ADDR = 3668,\n\tCPU_AHB_WDATA = 3672,\n\tCPU_AHB_RDATA = 3676,\n\tHCU_MAP_BASE = 3680,\n\tCPU_AHB_CTRL = 3684,\n\tHCU_CCSR = 3688,\n\tHCU_HCSR = 3692,\n};\n\nenum {\n\tB28_Y2_SMB_CONFIG = 3648,\n\tB28_Y2_SMB_CSD_REG = 3652,\n\tB28_Y2_ASF_IRQ_V_BASE = 3680,\n\tB28_Y2_ASF_STAT_CMD = 3688,\n\tB28_Y2_ASF_HOST_COM = 3692,\n\tB28_Y2_DATA_REG_1 = 3696,\n\tB28_Y2_DATA_REG_2 = 3700,\n\tB28_Y2_DATA_REG_3 = 3704,\n\tB28_Y2_DATA_REG_4 = 3708,\n};\n\nenum {\n\tSTAT_CTRL = 3712,\n\tSTAT_LAST_IDX = 3716,\n\tSTAT_LIST_ADDR_LO = 3720,\n\tSTAT_LIST_ADDR_HI = 3724,\n\tSTAT_TXA1_RIDX = 3728,\n\tSTAT_TXS1_RIDX = 3730,\n\tSTAT_TXA2_RIDX = 3732,\n\tSTAT_TXS2_RIDX = 3734,\n\tSTAT_TX_IDX_TH = 3736,\n\tSTAT_PUT_IDX = 3740,\n\tSTAT_FIFO_WP = 3744,\n\tSTAT_FIFO_RP = 3748,\n\tSTAT_FIFO_RSP = 3750,\n\tSTAT_FIFO_LEVEL = 3752,\n\tSTAT_FIFO_SHLVL = 3754,\n\tSTAT_FIFO_WM = 3756,\n\tSTAT_FIFO_ISR_WM = 3757,\n\tSTAT_LEV_TIMER_INI = 3760,\n\tSTAT_LEV_TIMER_CNT = 3764,\n\tSTAT_LEV_TIMER_CTRL = 3768,\n\tSTAT_LEV_TIMER_TEST = 3769,\n\tSTAT_TX_TIMER_INI = 3776,\n\tSTAT_TX_TIMER_CNT = 3780,\n\tSTAT_TX_TIMER_CTRL = 3784,\n\tSTAT_TX_TIMER_TEST = 3785,\n\tSTAT_ISR_TIMER_INI = 3792,\n\tSTAT_ISR_TIMER_CNT = 3796,\n\tSTAT_ISR_TIMER_CTRL = 3800,\n\tSTAT_ISR_TIMER_TEST = 3801,\n};\n\nenum {\n\tLINKLED_OFF = 1,\n\tLINKLED_ON = 2,\n\tLINKLED_LINKSYNC_OFF = 4,\n\tLINKLED_LINKSYNC_ON = 8,\n\tLINKLED_BLINK_OFF = 16,\n\tLINKLED_BLINK_ON = 32,\n};\n\nenum {\n\tGMAC_CTRL = 3840,\n\tGPHY_CTRL = 3844,\n\tGMAC_IRQ_SRC = 3848,\n\tGMAC_IRQ_MSK = 3852,\n\tGMAC_LINK_CTRL = 3856,\n\tWOL_CTRL_STAT = 3872,\n\tWOL_MATCH_CTL = 3874,\n\tWOL_MATCH_RES = 3875,\n\tWOL_MAC_ADDR = 3876,\n\tWOL_PATT_RPTR = 3884,\n\tWOL_PATT_LEN_LO = 3888,\n\tWOL_PATT_LEN_HI = 3892,\n\tWOL_PATT_CNT_0 = 3896,\n\tWOL_PATT_CNT_4 = 3900,\n};\n\nenum {\n\tBASE_GMAC_1 = 10240,\n\tBASE_GMAC_2 = 14336,\n};\n\nenum {\n\tPHY_MARV_CTRL = 0,\n\tPHY_MARV_STAT = 1,\n\tPHY_MARV_ID0 = 2,\n\tPHY_MARV_ID1 = 3,\n\tPHY_MARV_AUNE_ADV = 4,\n\tPHY_MARV_AUNE_LP = 5,\n\tPHY_MARV_AUNE_EXP = 6,\n\tPHY_MARV_NEPG = 7,\n\tPHY_MARV_NEPG_LP = 8,\n\tPHY_MARV_1000T_CTRL = 9,\n\tPHY_MARV_1000T_STAT = 10,\n\tPHY_MARV_EXT_STAT = 15,\n\tPHY_MARV_PHY_CTRL = 16,\n\tPHY_MARV_PHY_STAT = 17,\n\tPHY_MARV_INT_MASK = 18,\n\tPHY_MARV_INT_STAT = 19,\n\tPHY_MARV_EXT_CTRL = 20,\n\tPHY_MARV_RXE_CNT = 21,\n\tPHY_MARV_EXT_ADR = 22,\n\tPHY_MARV_PORT_IRQ = 23,\n\tPHY_MARV_LED_CTRL = 24,\n\tPHY_MARV_LED_OVER = 25,\n\tPHY_MARV_EXT_CTRL_2 = 26,\n\tPHY_MARV_EXT_P_STAT = 27,\n\tPHY_MARV_CABLE_DIAG = 28,\n\tPHY_MARV_PAGE_ADDR = 29,\n\tPHY_MARV_PAGE_DATA = 30,\n\tPHY_MARV_FE_LED_PAR = 22,\n\tPHY_MARV_FE_LED_SER = 23,\n\tPHY_MARV_FE_VCT_TX = 26,\n\tPHY_MARV_FE_VCT_RX = 27,\n\tPHY_MARV_FE_SPEC_2 = 28,\n};\n\nenum {\n\tPHY_CT_RESET = 32768,\n\tPHY_CT_LOOP = 16384,\n\tPHY_CT_SPS_LSB = 8192,\n\tPHY_CT_ANE = 4096,\n\tPHY_CT_PDOWN = 2048,\n\tPHY_CT_ISOL = 1024,\n\tPHY_CT_RE_CFG = 512,\n\tPHY_CT_DUP_MD = 256,\n\tPHY_CT_COL_TST = 128,\n\tPHY_CT_SPS_MSB = 64,\n};\n\nenum {\n\tPHY_CT_SP1000 = 64,\n\tPHY_CT_SP100 = 8192,\n\tPHY_CT_SP10 = 0,\n};\n\nenum {\n\tPHY_MARV_ID0_VAL = 321,\n\tPHY_BCOM_ID1_A1 = 24641,\n\tPHY_BCOM_ID1_B2 = 24643,\n\tPHY_BCOM_ID1_C0 = 24644,\n\tPHY_BCOM_ID1_C5 = 24647,\n\tPHY_MARV_ID1_B0 = 3107,\n\tPHY_MARV_ID1_B2 = 3109,\n\tPHY_MARV_ID1_C2 = 3266,\n\tPHY_MARV_ID1_Y2 = 3217,\n\tPHY_MARV_ID1_FE = 3203,\n\tPHY_MARV_ID1_ECU = 3248,\n};\n\nenum {\n\tPHY_AN_NXT_PG = 32768,\n\tPHY_AN_ACK = 16384,\n\tPHY_AN_RF = 8192,\n\tPHY_AN_PAUSE_ASYM = 2048,\n\tPHY_AN_PAUSE_CAP = 1024,\n\tPHY_AN_100BASE4 = 512,\n\tPHY_AN_100FULL = 256,\n\tPHY_AN_100HALF = 128,\n\tPHY_AN_10FULL = 64,\n\tPHY_AN_10HALF = 32,\n\tPHY_AN_CSMA = 1,\n\tPHY_AN_SEL = 31,\n\tPHY_AN_FULL = 321,\n\tPHY_AN_ALL = 480,\n};\n\nenum {\n\tPHY_M_AN_NXT_PG = 32768,\n\tPHY_M_AN_ACK = 16384,\n\tPHY_M_AN_RF = 8192,\n\tPHY_M_AN_ASP = 2048,\n\tPHY_M_AN_PC = 1024,\n\tPHY_M_AN_100_T4 = 512,\n\tPHY_M_AN_100_FD = 256,\n\tPHY_M_AN_100_HD = 128,\n\tPHY_M_AN_10_FD = 64,\n\tPHY_M_AN_10_HD = 32,\n\tPHY_M_AN_SEL_MSK = 496,\n};\n\nenum {\n\tPHY_M_AN_ASP_X = 256,\n\tPHY_M_AN_PC_X = 128,\n\tPHY_M_AN_1000X_AHD = 64,\n\tPHY_M_AN_1000X_AFD = 32,\n};\n\nenum {\n\tPHY_M_P_NO_PAUSE_X = 0,\n\tPHY_M_P_SYM_MD_X = 128,\n\tPHY_M_P_ASYM_MD_X = 256,\n\tPHY_M_P_BOTH_MD_X = 384,\n};\n\nenum {\n\tPHY_M_1000C_TEST = 57344,\n\tPHY_M_1000C_MSE = 4096,\n\tPHY_M_1000C_MSC = 2048,\n\tPHY_M_1000C_MPD = 1024,\n\tPHY_M_1000C_AFD = 512,\n\tPHY_M_1000C_AHD = 256,\n};\n\nenum {\n\tPHY_M_PC_TX_FFD_MSK = 49152,\n\tPHY_M_PC_RX_FFD_MSK = 12288,\n\tPHY_M_PC_ASS_CRS_TX = 2048,\n\tPHY_M_PC_FL_GOOD = 1024,\n\tPHY_M_PC_EN_DET_MSK = 768,\n\tPHY_M_PC_ENA_EXT_D = 128,\n\tPHY_M_PC_MDIX_MSK = 96,\n\tPHY_M_PC_DIS_125CLK = 16,\n\tPHY_M_PC_MAC_POW_UP = 8,\n\tPHY_M_PC_SQE_T_ENA = 4,\n\tPHY_M_PC_POL_R_DIS = 2,\n\tPHY_M_PC_DIS_JABBER = 1,\n};\n\nenum {\n\tPHY_M_PC_MAN_MDI = 0,\n\tPHY_M_PC_MAN_MDIX = 1,\n\tPHY_M_PC_ENA_AUTO = 3,\n};\n\nenum {\n\tPHY_M_PC_COP_TX_DIS = 8,\n\tPHY_M_PC_POW_D_ENA = 4,\n};\n\nenum {\n\tPHY_M_PC_ENA_DTE_DT = 32768,\n\tPHY_M_PC_ENA_ENE_DT = 16384,\n\tPHY_M_PC_DIS_NLP_CK = 8192,\n\tPHY_M_PC_ENA_LIP_NP = 4096,\n\tPHY_M_PC_DIS_NLP_GN = 2048,\n\tPHY_M_PC_DIS_SCRAMB = 512,\n\tPHY_M_PC_DIS_FEFI = 256,\n\tPHY_M_PC_SH_TP_SEL = 64,\n\tPHY_M_PC_RX_FD_MSK = 12,\n};\n\nenum {\n\tPHY_M_PS_SPEED_MSK = 49152,\n\tPHY_M_PS_SPEED_1000 = 32768,\n\tPHY_M_PS_SPEED_100 = 16384,\n\tPHY_M_PS_SPEED_10 = 0,\n\tPHY_M_PS_FULL_DUP = 8192,\n\tPHY_M_PS_PAGE_REC = 4096,\n\tPHY_M_PS_SPDUP_RES = 2048,\n\tPHY_M_PS_LINK_UP = 1024,\n\tPHY_M_PS_CABLE_MSK = 896,\n\tPHY_M_PS_MDI_X_STAT = 64,\n\tPHY_M_PS_DOWNS_STAT = 32,\n\tPHY_M_PS_ENDET_STAT = 16,\n\tPHY_M_PS_TX_P_EN = 8,\n\tPHY_M_PS_RX_P_EN = 4,\n\tPHY_M_PS_POL_REV = 2,\n\tPHY_M_PS_JABBER = 1,\n};\n\nenum {\n\tPHY_M_IS_AN_ERROR = 32768,\n\tPHY_M_IS_LSP_CHANGE = 16384,\n\tPHY_M_IS_DUP_CHANGE = 8192,\n\tPHY_M_IS_AN_PR = 4096,\n\tPHY_M_IS_AN_COMPL = 2048,\n\tPHY_M_IS_LST_CHANGE = 1024,\n\tPHY_M_IS_SYMB_ERROR = 512,\n\tPHY_M_IS_FALSE_CARR = 256,\n\tPHY_M_IS_FIFO_ERROR = 128,\n\tPHY_M_IS_MDI_CHANGE = 64,\n\tPHY_M_IS_DOWNSH_DET = 32,\n\tPHY_M_IS_END_CHANGE = 16,\n\tPHY_M_IS_DTE_CHANGE = 4,\n\tPHY_M_IS_POL_CHANGE = 2,\n\tPHY_M_IS_JABBER = 1,\n\tPHY_M_DEF_MSK = 25600,\n\tPHY_M_AN_MSK = 34816,\n};\n\nenum {\n\tPHY_M_EC_ENA_BC_EXT = 32768,\n\tPHY_M_EC_ENA_LIN_LB = 16384,\n\tPHY_M_EC_DIS_LINK_P = 4096,\n\tPHY_M_EC_M_DSC_MSK = 3072,\n\tPHY_M_EC_S_DSC_MSK = 768,\n\tPHY_M_EC_M_DSC_MSK2 = 3584,\n\tPHY_M_EC_DOWN_S_ENA = 256,\n\tPHY_M_EC_RX_TIM_CT = 128,\n\tPHY_M_EC_MAC_S_MSK = 112,\n\tPHY_M_EC_FIB_AN_ENA = 8,\n\tPHY_M_EC_DTE_D_ENA = 4,\n\tPHY_M_EC_TX_TIM_CT = 2,\n\tPHY_M_EC_TRANS_DIS = 1,\n\tPHY_M_10B_TE_ENABLE = 128,\n};\n\nenum {\n\tPHY_M_PC_DIS_LINK_Pa = 32768,\n\tPHY_M_PC_DSC_MSK = 28672,\n\tPHY_M_PC_DOWN_S_ENA = 2048,\n};\n\nenum {\n\tMAC_TX_CLK_0_MHZ = 2,\n\tMAC_TX_CLK_2_5_MHZ = 6,\n\tMAC_TX_CLK_25_MHZ = 7,\n};\n\nenum {\n\tPHY_M_LEDC_DIS_LED = 32768,\n\tPHY_M_LEDC_PULS_MSK = 28672,\n\tPHY_M_LEDC_F_INT = 2048,\n\tPHY_M_LEDC_BL_R_MSK = 1792,\n\tPHY_M_LEDC_DP_C_LSB = 128,\n\tPHY_M_LEDC_TX_C_LSB = 64,\n\tPHY_M_LEDC_LK_C_MSK = 56,\n};\n\nenum {\n\tPHY_M_LEDC_LINK_MSK = 24,\n\tPHY_M_LEDC_DP_CTRL = 4,\n\tPHY_M_LEDC_DP_C_MSB = 4,\n\tPHY_M_LEDC_RX_CTRL = 2,\n\tPHY_M_LEDC_TX_CTRL = 1,\n\tPHY_M_LEDC_TX_C_MSB = 1,\n};\n\nenum {\n\tPHY_M_POLC_LS1M_MSK = 61440,\n\tPHY_M_POLC_IS0M_MSK = 3840,\n\tPHY_M_POLC_LOS_MSK = 192,\n\tPHY_M_POLC_INIT_MSK = 48,\n\tPHY_M_POLC_STA1_MSK = 12,\n\tPHY_M_POLC_STA0_MSK = 3,\n};\n\nenum {\n\tPULS_NO_STR = 0,\n\tPULS_21MS = 1,\n\tPULS_42MS = 2,\n\tPULS_84MS = 3,\n\tPULS_170MS = 4,\n\tPULS_340MS = 5,\n\tPULS_670MS = 6,\n\tPULS_1300MS = 7,\n};\n\nenum {\n\tBLINK_42MS = 0,\n\tBLINK_84MS = 1,\n\tBLINK_170MS = 2,\n\tBLINK_340MS = 3,\n\tBLINK_670MS = 4,\n};\n\nenum led_mode {\n\tMO_LED_NORM = 0,\n\tMO_LED_BLINK = 1,\n\tMO_LED_OFF = 2,\n\tMO_LED_ON = 3,\n};\n\nenum {\n\tPHY_M_FC_AUTO_SEL = 32768,\n\tPHY_M_FC_AN_REG_ACC = 16384,\n\tPHY_M_FC_RESOLUTION = 8192,\n\tPHY_M_SER_IF_AN_BP = 4096,\n\tPHY_M_SER_IF_BP_ST = 2048,\n\tPHY_M_IRQ_POLARITY = 1024,\n\tPHY_M_DIS_AUT_MED = 512,\n\tPHY_M_UNDOC1 = 128,\n\tPHY_M_DTE_POW_STAT = 16,\n\tPHY_M_MODE_MASK = 15,\n};\n\nenum {\n\tPHY_M_FELP_LED2_MSK = 3840,\n\tPHY_M_FELP_LED1_MSK = 240,\n\tPHY_M_FELP_LED0_MSK = 15,\n};\n\nenum {\n\tLED_PAR_CTRL_COLX = 0,\n\tLED_PAR_CTRL_ERROR = 1,\n\tLED_PAR_CTRL_DUPLEX = 2,\n\tLED_PAR_CTRL_DP_COL = 3,\n\tLED_PAR_CTRL_SPEED = 4,\n\tLED_PAR_CTRL_LINK = 5,\n\tLED_PAR_CTRL_TX = 6,\n\tLED_PAR_CTRL_RX = 7,\n\tLED_PAR_CTRL_ACT = 8,\n\tLED_PAR_CTRL_LNK_RX = 9,\n\tLED_PAR_CTRL_LNK_AC = 10,\n\tLED_PAR_CTRL_ACT_BL = 11,\n\tLED_PAR_CTRL_TX_BL = 12,\n\tLED_PAR_CTRL_RX_BL = 13,\n\tLED_PAR_CTRL_COL_BL = 14,\n\tLED_PAR_CTRL_INACT = 15,\n};\n\nenum {\n\tPHY_M_FESC_DIS_WAIT = 4,\n\tPHY_M_FESC_ENA_MCLK = 2,\n\tPHY_M_FESC_SEL_CL_A = 1,\n};\n\nenum {\n\tPHY_M_FIB_FORCE_LNK = 1024,\n\tPHY_M_FIB_SIGD_POL = 512,\n\tPHY_M_FIB_TX_DIS = 8,\n};\n\nenum {\n\tPHY_M_MAC_MD_MSK = 896,\n\tPHY_M_MAC_GMIF_PUP = 8,\n\tPHY_M_MAC_MD_AUTO = 3,\n\tPHY_M_MAC_MD_COPPER = 5,\n\tPHY_M_MAC_MD_1000BX = 7,\n};\n\nenum {\n\tPHY_M_LEDC_LOS_MSK = 61440,\n\tPHY_M_LEDC_INIT_MSK = 3840,\n\tPHY_M_LEDC_STA1_MSK = 240,\n\tPHY_M_LEDC_STA0_MSK = 15,\n};\n\nenum {\n\tGM_GP_STAT = 0,\n\tGM_GP_CTRL = 4,\n\tGM_TX_CTRL = 8,\n\tGM_RX_CTRL = 12,\n\tGM_TX_FLOW_CTRL = 16,\n\tGM_TX_PARAM = 20,\n\tGM_SERIAL_MODE = 24,\n\tGM_SRC_ADDR_1L = 28,\n\tGM_SRC_ADDR_1M = 32,\n\tGM_SRC_ADDR_1H = 36,\n\tGM_SRC_ADDR_2L = 40,\n\tGM_SRC_ADDR_2M = 44,\n\tGM_SRC_ADDR_2H = 48,\n\tGM_MC_ADDR_H1 = 52,\n\tGM_MC_ADDR_H2 = 56,\n\tGM_MC_ADDR_H3 = 60,\n\tGM_MC_ADDR_H4 = 64,\n\tGM_TX_IRQ_SRC = 68,\n\tGM_RX_IRQ_SRC = 72,\n\tGM_TR_IRQ_SRC = 76,\n\tGM_TX_IRQ_MSK = 80,\n\tGM_RX_IRQ_MSK = 84,\n\tGM_TR_IRQ_MSK = 88,\n\tGM_SMI_CTRL = 128,\n\tGM_SMI_DATA = 132,\n\tGM_PHY_ADDR = 136,\n\tGM_MIB_CNT_BASE = 256,\n\tGM_MIB_CNT_END = 604,\n};\n\nenum {\n\tGM_RXF_UC_OK = 256,\n\tGM_RXF_BC_OK = 264,\n\tGM_RXF_MPAUSE = 272,\n\tGM_RXF_MC_OK = 280,\n\tGM_RXF_FCS_ERR = 288,\n\tGM_RXO_OK_LO = 304,\n\tGM_RXO_OK_HI = 312,\n\tGM_RXO_ERR_LO = 320,\n\tGM_RXO_ERR_HI = 328,\n\tGM_RXF_SHT = 336,\n\tGM_RXE_FRAG = 344,\n\tGM_RXF_64B = 352,\n\tGM_RXF_127B = 360,\n\tGM_RXF_255B = 368,\n\tGM_RXF_511B = 376,\n\tGM_RXF_1023B = 384,\n\tGM_RXF_1518B = 392,\n\tGM_RXF_MAX_SZ = 400,\n\tGM_RXF_LNG_ERR = 408,\n\tGM_RXF_JAB_PKT = 416,\n\tGM_RXE_FIFO_OV = 432,\n\tGM_TXF_UC_OK = 448,\n\tGM_TXF_BC_OK = 456,\n\tGM_TXF_MPAUSE = 464,\n\tGM_TXF_MC_OK = 472,\n\tGM_TXO_OK_LO = 480,\n\tGM_TXO_OK_HI = 488,\n\tGM_TXF_64B = 496,\n\tGM_TXF_127B = 504,\n\tGM_TXF_255B = 512,\n\tGM_TXF_511B = 520,\n\tGM_TXF_1023B = 528,\n\tGM_TXF_1518B = 536,\n\tGM_TXF_MAX_SZ = 544,\n\tGM_TXF_COL = 560,\n\tGM_TXF_LAT_COL = 568,\n\tGM_TXF_ABO_COL = 576,\n\tGM_TXF_MUL_COL = 584,\n\tGM_TXF_SNG_COL = 592,\n\tGM_TXE_FIFO_UR = 600,\n};\n\nenum {\n\tGM_GPCR_PROM_ENA = 16384,\n\tGM_GPCR_FC_TX_DIS = 8192,\n\tGM_GPCR_TX_ENA = 4096,\n\tGM_GPCR_RX_ENA = 2048,\n\tGM_GPCR_BURST_ENA = 1024,\n\tGM_GPCR_LOOP_ENA = 512,\n\tGM_GPCR_PART_ENA = 256,\n\tGM_GPCR_GIGS_ENA = 128,\n\tGM_GPCR_FL_PASS = 64,\n\tGM_GPCR_DUP_FULL = 32,\n\tGM_GPCR_FC_RX_DIS = 16,\n\tGM_GPCR_SPEED_100 = 8,\n\tGM_GPCR_AU_DUP_DIS = 4,\n\tGM_GPCR_AU_FCT_DIS = 2,\n\tGM_GPCR_AU_SPD_DIS = 1,\n};\n\nenum {\n\tGM_TXCR_FORCE_JAM = 32768,\n\tGM_TXCR_CRC_DIS = 16384,\n\tGM_TXCR_PAD_DIS = 8192,\n\tGM_TXCR_COL_THR_MSK = 7168,\n};\n\nenum {\n\tGM_RXCR_UCF_ENA = 32768,\n\tGM_RXCR_MCF_ENA = 16384,\n\tGM_RXCR_CRC_DIS = 8192,\n\tGM_RXCR_PASS_FC = 4096,\n};\n\nenum {\n\tGM_TXPA_JAMLEN_MSK = 49152,\n\tGM_TXPA_JAMIPG_MSK = 15872,\n\tGM_TXPA_JAMDAT_MSK = 496,\n\tGM_TXPA_BO_LIM_MSK = 15,\n\tTX_JAM_LEN_DEF = 3,\n\tTX_JAM_IPG_DEF = 11,\n\tTX_IPG_JAM_DEF = 28,\n\tTX_BOF_LIM_DEF = 4,\n};\n\nenum {\n\tGM_SMOD_DATABL_MSK = 63488,\n\tGM_SMOD_LIMIT_4 = 1024,\n\tGM_SMOD_VLAN_ENA = 512,\n\tGM_SMOD_JUMBO_ENA = 256,\n\tGM_NEW_FLOW_CTRL = 64,\n\tGM_SMOD_IPG_MSK = 31,\n};\n\nenum {\n\tGM_SMI_CT_PHY_A_MSK = 63488,\n\tGM_SMI_CT_REG_A_MSK = 1984,\n\tGM_SMI_CT_OP_RD = 32,\n\tGM_SMI_CT_RD_VAL = 16,\n\tGM_SMI_CT_BUSY = 8,\n};\n\nenum {\n\tGM_PAR_MIB_CLR = 32,\n\tGM_PAR_MIB_TST = 16,\n};\n\nenum {\n\tGMR_FS_LEN = 2147418112,\n\tGMR_FS_VLAN = 8192,\n\tGMR_FS_JABBER = 4096,\n\tGMR_FS_UN_SIZE = 2048,\n\tGMR_FS_MC = 1024,\n\tGMR_FS_BC = 512,\n\tGMR_FS_RX_OK = 256,\n\tGMR_FS_GOOD_FC = 128,\n\tGMR_FS_BAD_FC = 64,\n\tGMR_FS_MII_ERR = 32,\n\tGMR_FS_LONG_ERR = 16,\n\tGMR_FS_FRAGMENT = 8,\n\tGMR_FS_CRC_ERR = 2,\n\tGMR_FS_RX_FF_OV = 1,\n\tGMR_FS_ANY_ERR = 6267,\n};\n\nenum {\n\tRX_GCLKMAC_ENA = 2147483648,\n\tRX_GCLKMAC_OFF = 1073741824,\n\tRX_STFW_DIS = 536870912,\n\tRX_STFW_ENA = 268435456,\n\tRX_TRUNC_ON = 134217728,\n\tRX_TRUNC_OFF = 67108864,\n\tRX_VLAN_STRIP_ON = 33554432,\n\tRX_VLAN_STRIP_OFF = 16777216,\n\tRX_MACSEC_FLUSH_ON = 8388608,\n\tRX_MACSEC_FLUSH_OFF = 4194304,\n\tRX_MACSEC_ASF_FLUSH_ON = 2097152,\n\tRX_MACSEC_ASF_FLUSH_OFF = 1048576,\n\tGMF_RX_OVER_ON = 524288,\n\tGMF_RX_OVER_OFF = 262144,\n\tGMF_ASF_RX_OVER_ON = 131072,\n\tGMF_ASF_RX_OVER_OFF = 65536,\n\tGMF_WP_TST_ON = 16384,\n\tGMF_WP_TST_OFF = 8192,\n\tGMF_WP_STEP = 4096,\n\tGMF_RP_TST_ON = 1024,\n\tGMF_RP_TST_OFF = 512,\n\tGMF_RP_STEP = 256,\n\tGMF_RX_F_FL_ON = 128,\n\tGMF_RX_F_FL_OFF = 64,\n\tGMF_CLI_RX_FO = 32,\n\tGMF_CLI_RX_C = 16,\n\tGMF_OPER_ON = 8,\n\tGMF_OPER_OFF = 4,\n\tGMF_RST_CLR = 2,\n\tGMF_RST_SET = 1,\n\tRX_GMF_FL_THR_DEF = 10,\n\tGMF_RX_CTRL_DEF = 136,\n};\n\nenum {\n\tRX_IPV6_SA_MOB_ENA = 512,\n\tRX_IPV6_SA_MOB_DIS = 256,\n\tRX_IPV6_DA_MOB_ENA = 128,\n\tRX_IPV6_DA_MOB_DIS = 64,\n\tRX_PTR_SYNCDLY_ENA = 32,\n\tRX_PTR_SYNCDLY_DIS = 16,\n\tRX_ASF_NEWFLAG_ENA = 8,\n\tRX_ASF_NEWFLAG_DIS = 4,\n\tRX_FLSH_MISSPKT_ENA = 2,\n\tRX_FLSH_MISSPKT_DIS = 1,\n};\n\nenum {\n\tTX_DYN_WM_ENA = 3,\n};\n\nenum {\n\tTX_STFW_DIS = 2147483648,\n\tTX_STFW_ENA = 1073741824,\n\tTX_VLAN_TAG_ON = 33554432,\n\tTX_VLAN_TAG_OFF = 16777216,\n\tTX_PCI_JUM_ENA = 8388608,\n\tTX_PCI_JUM_DIS = 4194304,\n\tGMF_WSP_TST_ON = 262144,\n\tGMF_WSP_TST_OFF = 131072,\n\tGMF_WSP_STEP = 65536,\n\tGMF_CLI_TX_FU = 64,\n\tGMF_CLI_TX_FC = 32,\n\tGMF_CLI_TX_PE = 16,\n};\n\nenum {\n\tGMT_ST_START = 4,\n\tGMT_ST_STOP = 2,\n\tGMT_ST_CLR_IRQ = 1,\n};\n\nenum {\n\tY2_ASF_OS_PRES = 16,\n\tY2_ASF_RESET = 8,\n\tY2_ASF_RUNNING = 4,\n\tY2_ASF_CLR_HSTI = 2,\n\tY2_ASF_IRQ = 1,\n\tY2_ASF_UC_STATE = 12,\n\tY2_ASF_CLK_HALT = 0,\n};\n\nenum {\n\tHCU_CCSR_SMBALERT_MONITOR = 134217728,\n\tHCU_CCSR_CPU_SLEEP = 67108864,\n\tHCU_CCSR_CS_TO = 33554432,\n\tHCU_CCSR_WDOG = 16777216,\n\tHCU_CCSR_CLR_IRQ_HOST = 131072,\n\tHCU_CCSR_SET_IRQ_HCU = 65536,\n\tHCU_CCSR_AHB_RST = 512,\n\tHCU_CCSR_CPU_RST_MODE = 256,\n\tHCU_CCSR_SET_SYNC_CPU = 32,\n\tHCU_CCSR_CPU_CLK_DIVIDE_MSK = 24,\n\tHCU_CCSR_CPU_CLK_DIVIDE_BASE = 8,\n\tHCU_CCSR_OS_PRSNT = 4,\n\tHCU_CCSR_UC_STATE_MSK = 3,\n\tHCU_CCSR_UC_STATE_BASE = 1,\n\tHCU_CCSR_ASF_RESET = 0,\n\tHCU_CCSR_ASF_HALTED = 2,\n\tHCU_CCSR_ASF_RUNNING = 1,\n};\n\nenum {\n\tSC_STAT_CLR_IRQ = 16,\n\tSC_STAT_OP_ON = 8,\n\tSC_STAT_OP_OFF = 4,\n\tSC_STAT_RST_CLR = 2,\n\tSC_STAT_RST_SET = 1,\n};\n\nenum {\n\tGMC_SET_RST = 32768,\n\tGMC_SEC_RST_OFF = 16384,\n\tGMC_BYP_MACSECRX_ON = 8192,\n\tGMC_BYP_MACSECRX_OFF = 4096,\n\tGMC_BYP_MACSECTX_ON = 2048,\n\tGMC_BYP_MACSECTX_OFF = 1024,\n\tGMC_BYP_RETR_ON = 512,\n\tGMC_BYP_RETR_OFF = 256,\n\tGMC_H_BURST_ON = 128,\n\tGMC_H_BURST_OFF = 64,\n\tGMC_F_LOOPB_ON = 32,\n\tGMC_F_LOOPB_OFF = 16,\n\tGMC_PAUSE_ON = 8,\n\tGMC_PAUSE_OFF = 4,\n\tGMC_RST_CLR = 2,\n\tGMC_RST_SET = 1,\n};\n\nenum {\n\tGPC_TX_PAUSE = 1073741824,\n\tGPC_RX_PAUSE = 536870912,\n\tGPC_SPEED = 402653184,\n\tGPC_LINK = 67108864,\n\tGPC_DUPLEX = 33554432,\n\tGPC_CLOCK = 16777216,\n\tGPC_PDOWN = 8388608,\n\tGPC_TSTMODE = 4194304,\n\tGPC_REG18 = 2097152,\n\tGPC_REG12SEL = 1572864,\n\tGPC_REG18SEL = 393216,\n\tGPC_SPILOCK = 65536,\n\tGPC_LEDMUX = 49152,\n\tGPC_INTPOL = 8192,\n\tGPC_DETECT = 4096,\n\tGPC_1000HD = 2048,\n\tGPC_SLAVE = 1024,\n\tGPC_PAUSE = 512,\n\tGPC_LEDCTL = 192,\n\tGPC_RST_CLR = 2,\n\tGPC_RST_SET = 1,\n};\n\nenum {\n\tGM_IS_TX_CO_OV = 32,\n\tGM_IS_RX_CO_OV = 16,\n\tGM_IS_TX_FF_UR = 8,\n\tGM_IS_TX_COMPL = 4,\n\tGM_IS_RX_FF_OR = 2,\n\tGM_IS_RX_COMPL = 1,\n};\n\nenum {\n\tGMLC_RST_CLR = 2,\n\tGMLC_RST_SET = 1,\n};\n\nenum {\n\tWOL_CTL_LINK_CHG_OCC = 32768,\n\tWOL_CTL_MAGIC_PKT_OCC = 16384,\n\tWOL_CTL_PATTERN_OCC = 8192,\n\tWOL_CTL_CLEAR_RESULT = 4096,\n\tWOL_CTL_ENA_PME_ON_LINK_CHG = 2048,\n\tWOL_CTL_DIS_PME_ON_LINK_CHG = 1024,\n\tWOL_CTL_ENA_PME_ON_MAGIC_PKT = 512,\n\tWOL_CTL_DIS_PME_ON_MAGIC_PKT = 256,\n\tWOL_CTL_ENA_PME_ON_PATTERN = 128,\n\tWOL_CTL_DIS_PME_ON_PATTERN = 64,\n\tWOL_CTL_ENA_LINK_CHG_UNIT = 32,\n\tWOL_CTL_DIS_LINK_CHG_UNIT = 16,\n\tWOL_CTL_ENA_MAGIC_PKT_UNIT = 8,\n\tWOL_CTL_DIS_MAGIC_PKT_UNIT = 4,\n\tWOL_CTL_ENA_PATTERN_UNIT = 2,\n\tWOL_CTL_DIS_PATTERN_UNIT = 1,\n};\n\nenum {\n\tUDPTCP = 1,\n\tCALSUM = 2,\n\tWR_SUM = 4,\n\tINIT_SUM = 8,\n\tLOCK_SUM = 16,\n\tINS_VLAN = 32,\n\tEOP = 128,\n};\n\nenum {\n\tHW_OWNER = 128,\n\tOP_TCPWRITE = 17,\n\tOP_TCPSTART = 18,\n\tOP_TCPINIT = 20,\n\tOP_TCPLCK = 24,\n\tOP_TCPCHKSUM = 18,\n\tOP_TCPIS = 22,\n\tOP_TCPLW = 25,\n\tOP_TCPLSW = 27,\n\tOP_TCPLISW = 31,\n\tOP_ADDR64 = 33,\n\tOP_VLAN = 34,\n\tOP_ADDR64VLAN = 35,\n\tOP_LRGLEN = 36,\n\tOP_LRGLENVLAN = 38,\n\tOP_MSS = 40,\n\tOP_MSSVLAN = 42,\n\tOP_BUFFER = 64,\n\tOP_PACKET = 65,\n\tOP_LARGESEND = 67,\n\tOP_LSOV2 = 69,\n\tOP_RXSTAT = 96,\n\tOP_RXTIMESTAMP = 97,\n\tOP_RXVLAN = 98,\n\tOP_RXCHKS = 100,\n\tOP_RXCHKSVLAN = 102,\n\tOP_RXTIMEVLAN = 99,\n\tOP_RSS_HASH = 101,\n\tOP_TXINDEXLE = 104,\n\tOP_MACSEC = 108,\n\tOP_PUTIDX = 112,\n};\n\nenum status_css {\n\tCSS_TCPUDPCSOK = 128,\n\tCSS_ISUDP = 64,\n\tCSS_ISTCP = 32,\n\tCSS_ISIPFRAG = 16,\n\tCSS_ISIPV6 = 8,\n\tCSS_IPV4CSUMOK = 4,\n\tCSS_ISIPV4 = 2,\n\tCSS_LINK_BIT = 1,\n};\n\nstruct sky2_tx_le {\n\t__le32 addr;\n\t__le16 length;\n\tu8 ctrl;\n\tu8 opcode;\n};\n\nstruct sky2_rx_le {\n\t__le32 addr;\n\t__le16 length;\n\tu8 ctrl;\n\tu8 opcode;\n};\n\nstruct sky2_status_le {\n\t__le32 status;\n\t__le16 length;\n\tu8 css;\n\tu8 opcode;\n};\n\nstruct tx_ring_info {\n\tstruct sk_buff *skb;\n\tlong unsigned int flags;\n\tdma_addr_t mapaddr;\n\t__u32 maplen;\n};\n\nstruct rx_ring_info {\n\tstruct sk_buff *skb;\n\tdma_addr_t data_addr;\n\t__u32 data_size;\n\tdma_addr_t frag_addr[2];\n};\n\nenum flow_control {\n\tFC_NONE = 0,\n\tFC_TX = 1,\n\tFC_RX = 2,\n\tFC_BOTH = 3,\n};\n\nstruct sky2_stats {\n\tstruct u64_stats_sync syncp;\n\tu64 packets;\n\tu64 bytes;\n};\n\nstruct sky2_hw;\n\nstruct sky2_port {\n\tstruct sky2_hw *hw;\n\tstruct net_device *netdev;\n\tunsigned int port;\n\tu32 msg_enable;\n\tspinlock_t phy_lock;\n\tstruct tx_ring_info *tx_ring;\n\tstruct sky2_tx_le *tx_le;\n\tstruct sky2_stats tx_stats;\n\tu16 tx_ring_size;\n\tu16 tx_cons;\n\tu16 tx_prod;\n\tu16 tx_next;\n\tu16 tx_pending;\n\tu16 tx_last_mss;\n\tu32 tx_last_upper;\n\tu32 tx_tcpsum;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct rx_ring_info *rx_ring;\n\tstruct sky2_rx_le *rx_le;\n\tstruct sky2_stats rx_stats;\n\tu16 rx_next;\n\tu16 rx_put;\n\tu16 rx_pending;\n\tu16 rx_data_size;\n\tu16 rx_nfrags;\n\tlong unsigned int last_rx;\n\tstruct {\n\t\tlong unsigned int last;\n\t\tu32 mac_rp;\n\t\tu8 mac_lev;\n\t\tu8 fifo_rp;\n\t\tu8 fifo_lev;\n\t} check;\n\tdma_addr_t rx_le_map;\n\tdma_addr_t tx_le_map;\n\tu16 advertising;\n\tu16 speed;\n\tu8 wol;\n\tu8 duplex;\n\tu16 flags;\n\tenum flow_control flow_mode;\n\tenum flow_control flow_status;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct sky2_hw {\n\tvoid *regs;\n\tstruct pci_dev *pdev;\n\tstruct napi_struct napi;\n\tstruct net_device *dev[2];\n\tlong unsigned int flags;\n\tu8 chip_id;\n\tu8 chip_rev;\n\tu8 pmd_type;\n\tu8 ports;\n\tstruct sky2_status_le *st_le;\n\tu32 st_size;\n\tu32 st_idx;\n\tdma_addr_t st_dma;\n\tstruct timer_list watchdog_timer;\n\tstruct work_struct restart_work;\n\twait_queue_head_t msi_wait;\n\tchar irq_name[0];\n};\n\nstruct sky2_stat {\n\tchar name[32];\n\tu16 offset;\n};\n\nstruct vlan_ethhdr {\n\tunsigned char h_dest[6];\n\tunsigned char h_source[6];\n\t__be16 h_vlan_proto;\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\nenum {\n\tNvRegIrqStatus = 0,\n\tNvRegIrqMask = 4,\n\tNvRegUnknownSetupReg6 = 8,\n\tNvRegPollingInterval = 12,\n\tNvRegMSIMap0 = 32,\n\tNvRegMSIMap1 = 36,\n\tNvRegMSIIrqMask = 48,\n\tNvRegMisc1 = 128,\n\tNvRegMacReset = 52,\n\tNvRegTransmitterControl = 132,\n\tNvRegTransmitterStatus = 136,\n\tNvRegPacketFilterFlags = 140,\n\tNvRegOffloadConfig = 144,\n\tNvRegReceiverControl = 148,\n\tNvRegReceiverStatus = 152,\n\tNvRegSlotTime = 156,\n\tNvRegTxDeferral = 160,\n\tNvRegRxDeferral = 164,\n\tNvRegMacAddrA = 168,\n\tNvRegMacAddrB = 172,\n\tNvRegMulticastAddrA = 176,\n\tNvRegMulticastAddrB = 180,\n\tNvRegMulticastMaskA = 184,\n\tNvRegMulticastMaskB = 188,\n\tNvRegPhyInterface = 192,\n\tNvRegBackOffControl = 196,\n\tNvRegTxRingPhysAddr = 256,\n\tNvRegRxRingPhysAddr = 260,\n\tNvRegRingSizes = 264,\n\tNvRegTransmitPoll = 268,\n\tNvRegLinkSpeed = 272,\n\tNvRegUnknownSetupReg5 = 304,\n\tNvRegTxWatermark = 316,\n\tNvRegTxRxControl = 324,\n\tNvRegTxRingPhysAddrHigh = 328,\n\tNvRegRxRingPhysAddrHigh = 332,\n\tNvRegTxPauseFrame = 368,\n\tNvRegTxPauseFrameLimit = 372,\n\tNvRegMIIStatus = 384,\n\tNvRegMIIMask = 388,\n\tNvRegAdapterControl = 392,\n\tNvRegMIISpeed = 396,\n\tNvRegMIIControl = 400,\n\tNvRegMIIData = 404,\n\tNvRegTxUnicast = 416,\n\tNvRegTxMulticast = 420,\n\tNvRegTxBroadcast = 424,\n\tNvRegWakeUpFlags = 512,\n\tNvRegMgmtUnitGetVersion = 516,\n\tNvRegMgmtUnitVersion = 520,\n\tNvRegPowerCap = 616,\n\tNvRegPowerState = 620,\n\tNvRegMgmtUnitControl = 632,\n\tNvRegTxCnt = 640,\n\tNvRegTxZeroReXmt = 644,\n\tNvRegTxOneReXmt = 648,\n\tNvRegTxManyReXmt = 652,\n\tNvRegTxLateCol = 656,\n\tNvRegTxUnderflow = 660,\n\tNvRegTxLossCarrier = 664,\n\tNvRegTxExcessDef = 668,\n\tNvRegTxRetryErr = 672,\n\tNvRegRxFrameErr = 676,\n\tNvRegRxExtraByte = 680,\n\tNvRegRxLateCol = 684,\n\tNvRegRxRunt = 688,\n\tNvRegRxFrameTooLong = 692,\n\tNvRegRxOverflow = 696,\n\tNvRegRxFCSErr = 700,\n\tNvRegRxFrameAlignErr = 704,\n\tNvRegRxLenErr = 708,\n\tNvRegRxUnicast = 712,\n\tNvRegRxMulticast = 716,\n\tNvRegRxBroadcast = 720,\n\tNvRegTxDef = 724,\n\tNvRegTxFrame = 728,\n\tNvRegRxCnt = 732,\n\tNvRegTxPause = 736,\n\tNvRegRxPause = 740,\n\tNvRegRxDropFrame = 744,\n\tNvRegVlanControl = 768,\n\tNvRegMSIXMap0 = 992,\n\tNvRegMSIXMap1 = 996,\n\tNvRegMSIXIrqStatus = 1008,\n\tNvRegPowerState2 = 1536,\n};\n\nstruct ring_desc {\n\t__le32 buf;\n\t__le32 flaglen;\n};\n\nstruct ring_desc_ex {\n\t__le32 bufhigh;\n\t__le32 buflow;\n\t__le32 txvlan;\n\t__le32 flaglen;\n};\n\nunion ring_type {\n\tstruct ring_desc *orig;\n\tstruct ring_desc_ex *ex;\n};\n\nstruct nv_ethtool_str {\n\tchar name[32];\n};\n\nstruct nv_ethtool_stats {\n\tu64 tx_bytes;\n\tu64 tx_zero_rexmt;\n\tu64 tx_one_rexmt;\n\tu64 tx_many_rexmt;\n\tu64 tx_late_collision;\n\tu64 tx_fifo_errors;\n\tu64 tx_carrier_errors;\n\tu64 tx_excess_deferral;\n\tu64 tx_retry_error;\n\tu64 rx_frame_error;\n\tu64 rx_extra_byte;\n\tu64 rx_late_collision;\n\tu64 rx_runt;\n\tu64 rx_frame_too_long;\n\tu64 rx_over_errors;\n\tu64 rx_crc_errors;\n\tu64 rx_frame_align_error;\n\tu64 rx_length_error;\n\tu64 rx_unicast;\n\tu64 rx_multicast;\n\tu64 rx_broadcast;\n\tu64 rx_packets;\n\tu64 rx_errors_total;\n\tu64 tx_errors_total;\n\tu64 tx_deferral;\n\tu64 tx_packets;\n\tu64 rx_bytes;\n\tu64 tx_pause;\n\tu64 rx_pause;\n\tu64 rx_drop_frame;\n\tu64 tx_unicast;\n\tu64 tx_multicast;\n\tu64 tx_broadcast;\n};\n\nstruct register_test {\n\t__u32 reg;\n\t__u32 mask;\n};\n\nstruct nv_skb_map {\n\tstruct sk_buff *skb;\n\tdma_addr_t dma;\n\tunsigned int dma_len: 31;\n\tunsigned int dma_single: 1;\n\tstruct ring_desc_ex *first_tx_desc;\n\tstruct nv_skb_map *next_tx_ctx;\n};\n\nstruct nv_txrx_stats {\n\tu64 stat_rx_packets;\n\tu64 stat_rx_bytes;\n\tu64 stat_rx_missed_errors;\n\tu64 stat_rx_dropped;\n\tu64 stat_tx_packets;\n\tu64 stat_tx_bytes;\n\tu64 stat_tx_dropped;\n};\n\nstruct fe_priv {\n\tspinlock_t lock;\n\tstruct net_device *dev;\n\tstruct napi_struct napi;\n\tspinlock_t hwstats_lock;\n\tstruct nv_ethtool_stats estats;\n\tint in_shutdown;\n\tu32 linkspeed;\n\tint duplex;\n\tint autoneg;\n\tint fixed_mode;\n\tint phyaddr;\n\tint wolenabled;\n\tunsigned int phy_oui;\n\tunsigned int phy_model;\n\tunsigned int phy_rev;\n\tu16 gigabit;\n\tint intr_test;\n\tint recover_error;\n\tint quiet_count;\n\tdma_addr_t ring_addr;\n\tstruct pci_dev *pci_dev;\n\tu32 orig_mac[2];\n\tu32 events;\n\tu32 irqmask;\n\tu32 desc_ver;\n\tu32 txrxctl_bits;\n\tu32 vlanctl_bits;\n\tu32 driver_data;\n\tu32 device_id;\n\tu32 register_size;\n\tu32 mac_in_use;\n\tint mgmt_version;\n\tint mgmt_sema;\n\tvoid *base;\n\tunion ring_type get_rx;\n\tunion ring_type put_rx;\n\tunion ring_type last_rx;\n\tstruct nv_skb_map *get_rx_ctx;\n\tstruct nv_skb_map *put_rx_ctx;\n\tstruct nv_skb_map *last_rx_ctx;\n\tstruct nv_skb_map *rx_skb;\n\tunion ring_type rx_ring;\n\tunsigned int rx_buf_sz;\n\tunsigned int pkt_limit;\n\tstruct timer_list oom_kick;\n\tstruct timer_list nic_poll;\n\tstruct timer_list stats_poll;\n\tu32 nic_poll_irq;\n\tint rx_ring_size;\n\tstruct u64_stats_sync swstats_rx_syncp;\n\tstruct nv_txrx_stats *txrx_stats;\n\tint need_linktimer;\n\tlong unsigned int link_timeout;\n\tunion ring_type get_tx;\n\tunion ring_type put_tx;\n\tunion ring_type last_tx;\n\tstruct nv_skb_map *get_tx_ctx;\n\tstruct nv_skb_map *put_tx_ctx;\n\tstruct nv_skb_map *last_tx_ctx;\n\tstruct nv_skb_map *tx_skb;\n\tunion ring_type tx_ring;\n\tu32 tx_flags;\n\tint tx_ring_size;\n\tint tx_limit;\n\tu32 tx_pkts_in_progress;\n\tstruct nv_skb_map *tx_change_owner;\n\tstruct nv_skb_map *tx_end_flip;\n\tint tx_stop;\n\tstruct u64_stats_sync swstats_tx_syncp;\n\tu32 msi_flags;\n\tstruct msix_entry msi_x_entry[8];\n\tu32 pause_flags;\n\tu32 saved_config_space[385];\n\tchar name_rx[19];\n\tchar name_tx[19];\n\tchar name_other[22];\n};\n\nenum {\n\tNV_OPTIMIZATION_MODE_THROUGHPUT = 0,\n\tNV_OPTIMIZATION_MODE_CPU = 1,\n\tNV_OPTIMIZATION_MODE_DYNAMIC = 2,\n};\n\nenum {\n\tNV_MSI_INT_DISABLED = 0,\n\tNV_MSI_INT_ENABLED = 1,\n};\n\nenum {\n\tNV_MSIX_INT_DISABLED = 0,\n\tNV_MSIX_INT_ENABLED = 1,\n};\n\nenum {\n\tNV_DMA_64BIT_DISABLED = 0,\n\tNV_DMA_64BIT_ENABLED = 1,\n};\n\nenum {\n\tNV_CROSSOVER_DETECTION_DISABLED = 0,\n\tNV_CROSSOVER_DETECTION_ENABLED = 1,\n};\n\nenum {\n\tHAS_MII_XCVR = 65536,\n\tHAS_CHIP_XCVR = 131072,\n\tHAS_LNK_CHNG = 262144,\n};\n\nenum {\n\tRTL8139 = 0,\n\tRTL8129 = 1,\n};\n\nenum RTL8139_registers {\n\tMAC0 = 0,\n\tMAR0 = 8,\n\tTxStatus0 = 16,\n\tTxAddr0 = 32,\n\tRxBuf = 48,\n\tChipCmd = 55,\n\tRxBufPtr = 56,\n\tRxBufAddr = 58,\n\tIntrMask = 60,\n\tIntrStatus = 62,\n\tTxConfig = 64,\n\tRxConfig = 68,\n\tTimer = 72,\n\tRxMissed = 76,\n\tCfg9346 = 80,\n\tConfig0 = 81,\n\tConfig1 = 82,\n\tTimerInt = 84,\n\tMediaStatus = 88,\n\tConfig3 = 89,\n\tConfig4 = 90,\n\tHltClk = 91,\n\tMultiIntr = 92,\n\tTxSummary = 96,\n\tBasicModeCtrl = 98,\n\tBasicModeStatus = 100,\n\tNWayAdvert = 102,\n\tNWayLPAR = 104,\n\tNWayExpansion = 106,\n\tFIFOTMS = 112,\n\tCSCR = 116,\n\tPARA78 = 120,\n\tFlashReg = 212,\n\tPARA7c = 124,\n\tConfig5 = 216,\n};\n\nenum ClearBitMasks {\n\tMultiIntrClear = 61440,\n\tChipCmdClear = 226,\n\tConfig1Clear = 206,\n};\n\nenum ChipCmdBits {\n\tCmdReset = 16,\n\tCmdRxEnb = 8,\n\tCmdTxEnb = 4,\n\tRxBufEmpty = 1,\n};\n\nenum IntrStatusBits {\n\tPCIErr = 32768,\n\tPCSTimeout = 16384,\n\tRxFIFOOver = 64,\n\tRxUnderrun = 32,\n\tRxOverflow = 16,\n\tTxErr = 8,\n\tTxOK = 4,\n\tRxErr = 2,\n\tRxOK = 1,\n\tRxAckBits = 81,\n};\n\nenum TxStatusBits {\n\tTxHostOwns = 8192,\n\tTxUnderrun = 16384,\n\tTxStatOK = 32768,\n\tTxOutOfWindow = 536870912,\n\tTxAborted = 1073741824,\n\tTxCarrierLost = 2147483648,\n};\n\nenum RxStatusBits {\n\tRxMulticast = 32768,\n\tRxPhysical = 16384,\n\tRxBroadcast = 8192,\n\tRxBadSymbol = 32,\n\tRxRunt = 16,\n\tRxTooLong = 8,\n\tRxCRCErr = 4,\n\tRxBadAlign = 2,\n\tRxStatusOK = 1,\n};\n\nenum rx_mode_bits {\n\tAcceptErr = 32,\n\tAcceptRunt = 16,\n\tAcceptBroadcast = 8,\n\tAcceptMulticast = 4,\n\tAcceptMyPhys = 2,\n\tAcceptAllPhys = 1,\n};\n\nenum tx_config_bits {\n\tTxIFGShift = 24,\n\tTxIFG84 = 0,\n\tTxIFG88 = 16777216,\n\tTxIFG92 = 33554432,\n\tTxIFG96 = 50331648,\n\tTxLoopBack = 393216,\n\tTxCRC = 65536,\n\tTxClearAbt = 1,\n\tTxDMAShift = 8,\n\tTxRetryShift = 4,\n\tTxVersionMask = 2088763392,\n};\n\nenum Config1Bits {\n\tCfg1_PM_Enable = 1,\n\tCfg1_VPD_Enable = 2,\n\tCfg1_PIO = 4,\n\tCfg1_MMIO = 8,\n\tLWAKE = 16,\n\tCfg1_Driver_Load = 32,\n\tCfg1_LED0 = 64,\n\tCfg1_LED1 = 128,\n\tSLEEP = 2,\n\tPWRDN = 1,\n};\n\nenum Config3Bits {\n\tCfg3_FBtBEn = 1,\n\tCfg3_FuncRegEn = 2,\n\tCfg3_CLKRUN_En = 4,\n\tCfg3_CardB_En = 8,\n\tCfg3_LinkUp = 16,\n\tCfg3_Magic = 32,\n\tCfg3_PARM_En = 64,\n\tCfg3_GNTSel = 128,\n};\n\nenum Config4Bits {\n\tLWPTN = 4,\n};\n\nenum Config5Bits {\n\tCfg5_PME_STS = 1,\n\tCfg5_LANWake = 2,\n\tCfg5_LDPS = 4,\n\tCfg5_FIFOAddrPtr = 8,\n\tCfg5_UWF = 16,\n\tCfg5_MWF = 32,\n\tCfg5_BWF = 64,\n};\n\nenum CSCRBits {\n\tCSCR_LinkOKBit = 1024,\n\tCSCR_LinkChangeBit = 2048,\n\tCSCR_LinkStatusBits = 61440,\n\tCSCR_LinkDownOffCmd = 960,\n\tCSCR_LinkDownCmd = 62400,\n};\n\nenum Cfg9346Bits {\n\tCfg9346_Lock = 0,\n\tCfg9346_Unlock = 192,\n};\n\ntypedef enum {\n\tCH_8139 = 0,\n\tCH_8139_K = 1,\n\tCH_8139A = 2,\n\tCH_8139A_G = 3,\n\tCH_8139B = 4,\n\tCH_8130 = 5,\n\tCH_8139C = 6,\n\tCH_8100 = 7,\n\tCH_8100B_8139D = 8,\n\tCH_8101 = 9,\n} chip_t;\n\nenum chip_flags {\n\tHasHltClk = 1,\n\tHasLWake = 2,\n};\n\nstruct rtl_extra_stats {\n\tlong unsigned int early_rx;\n\tlong unsigned int tx_buf_mapped;\n\tlong unsigned int tx_timeouts;\n\tlong unsigned int rx_lost_in_ring;\n};\n\nstruct rtl8139_stats {\n\tu64 packets;\n\tu64 bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct rtl8139_private {\n\tvoid *mmio_addr;\n\tint drv_flags;\n\tstruct pci_dev *pci_dev;\n\tu32 msg_enable;\n\tstruct napi_struct napi;\n\tstruct net_device *dev;\n\tunsigned char *rx_ring;\n\tunsigned int cur_rx;\n\tstruct rtl8139_stats rx_stats;\n\tdma_addr_t rx_ring_dma;\n\tunsigned int tx_flag;\n\tlong unsigned int cur_tx;\n\tlong unsigned int dirty_tx;\n\tstruct rtl8139_stats tx_stats;\n\tunsigned char *tx_buf[4];\n\tunsigned char *tx_bufs;\n\tdma_addr_t tx_bufs_dma;\n\tsigned char phys[4];\n\tchar twistie;\n\tchar twist_row;\n\tchar twist_col;\n\tunsigned int watchdog_fired: 1;\n\tunsigned int default_port: 4;\n\tunsigned int have_thread: 1;\n\tspinlock_t lock;\n\tspinlock_t rx_lock;\n\tchip_t chipset;\n\tu32 rx_config;\n\tstruct rtl_extra_stats xstats;\n\tstruct delayed_work thread;\n\tstruct mii_if_info mii;\n\tunsigned int regs_len;\n\tlong unsigned int fifo_copy_timeout;\n};\n\nenum mac_version {\n\tRTL_GIGA_MAC_VER_02 = 0,\n\tRTL_GIGA_MAC_VER_03 = 1,\n\tRTL_GIGA_MAC_VER_04 = 2,\n\tRTL_GIGA_MAC_VER_05 = 3,\n\tRTL_GIGA_MAC_VER_06 = 4,\n\tRTL_GIGA_MAC_VER_07 = 5,\n\tRTL_GIGA_MAC_VER_08 = 6,\n\tRTL_GIGA_MAC_VER_09 = 7,\n\tRTL_GIGA_MAC_VER_10 = 8,\n\tRTL_GIGA_MAC_VER_11 = 9,\n\tRTL_GIGA_MAC_VER_12 = 10,\n\tRTL_GIGA_MAC_VER_13 = 11,\n\tRTL_GIGA_MAC_VER_14 = 12,\n\tRTL_GIGA_MAC_VER_15 = 13,\n\tRTL_GIGA_MAC_VER_16 = 14,\n\tRTL_GIGA_MAC_VER_17 = 15,\n\tRTL_GIGA_MAC_VER_18 = 16,\n\tRTL_GIGA_MAC_VER_19 = 17,\n\tRTL_GIGA_MAC_VER_20 = 18,\n\tRTL_GIGA_MAC_VER_21 = 19,\n\tRTL_GIGA_MAC_VER_22 = 20,\n\tRTL_GIGA_MAC_VER_23 = 21,\n\tRTL_GIGA_MAC_VER_24 = 22,\n\tRTL_GIGA_MAC_VER_25 = 23,\n\tRTL_GIGA_MAC_VER_26 = 24,\n\tRTL_GIGA_MAC_VER_27 = 25,\n\tRTL_GIGA_MAC_VER_28 = 26,\n\tRTL_GIGA_MAC_VER_29 = 27,\n\tRTL_GIGA_MAC_VER_30 = 28,\n\tRTL_GIGA_MAC_VER_31 = 29,\n\tRTL_GIGA_MAC_VER_32 = 30,\n\tRTL_GIGA_MAC_VER_33 = 31,\n\tRTL_GIGA_MAC_VER_34 = 32,\n\tRTL_GIGA_MAC_VER_35 = 33,\n\tRTL_GIGA_MAC_VER_36 = 34,\n\tRTL_GIGA_MAC_VER_37 = 35,\n\tRTL_GIGA_MAC_VER_38 = 36,\n\tRTL_GIGA_MAC_VER_39 = 37,\n\tRTL_GIGA_MAC_VER_40 = 38,\n\tRTL_GIGA_MAC_VER_41 = 39,\n\tRTL_GIGA_MAC_VER_42 = 40,\n\tRTL_GIGA_MAC_VER_43 = 41,\n\tRTL_GIGA_MAC_VER_44 = 42,\n\tRTL_GIGA_MAC_VER_45 = 43,\n\tRTL_GIGA_MAC_VER_46 = 44,\n\tRTL_GIGA_MAC_VER_47 = 45,\n\tRTL_GIGA_MAC_VER_48 = 46,\n\tRTL_GIGA_MAC_VER_49 = 47,\n\tRTL_GIGA_MAC_VER_50 = 48,\n\tRTL_GIGA_MAC_VER_51 = 49,\n\tRTL_GIGA_MAC_VER_52 = 50,\n\tRTL_GIGA_MAC_VER_60 = 51,\n\tRTL_GIGA_MAC_VER_61 = 52,\n\tRTL_GIGA_MAC_NONE = 53,\n};\n\nstruct rtl8169_private;\n\ntypedef void (*rtl_fw_write_t)(struct rtl8169_private *, int, int);\n\nstruct rtl8169_stats {\n\tu64 packets;\n\tu64 bytes;\n\tstruct u64_stats_sync syncp;\n};\n\nstruct ring_info___2 {\n\tstruct sk_buff *skb;\n\tu32 len;\n};\n\nstruct rtl8169_tc_offsets {\n\tbool inited;\n\t__le64 tx_errors;\n\t__le32 tx_multi_collision;\n\t__le16 tx_aborted;\n\t__le16 rx_missed;\n};\n\nstruct TxDesc;\n\nstruct RxDesc;\n\nstruct rtl8169_counters;\n\nstruct rtl_fw;\n\nstruct rtl8169_private {\n\tvoid *mmio_addr;\n\tstruct pci_dev *pci_dev;\n\tstruct net_device *dev;\n\tstruct phy_device *phydev;\n\tstruct napi_struct napi;\n\tenum mac_version mac_version;\n\tu32 cur_rx;\n\tu32 cur_tx;\n\tu32 dirty_tx;\n\tstruct rtl8169_stats rx_stats;\n\tstruct rtl8169_stats tx_stats;\n\tstruct TxDesc *TxDescArray;\n\tstruct RxDesc *RxDescArray;\n\tdma_addr_t TxPhyAddr;\n\tdma_addr_t RxPhyAddr;\n\tstruct page *Rx_databuff[256];\n\tstruct ring_info___2 tx_skb[64];\n\tu16 cp_cmd;\n\tu32 irq_mask;\n\tstruct clk *clk;\n\tstruct {\n\t\tlong unsigned int flags[1];\n\t\tstruct mutex mutex;\n\t\tstruct work_struct work;\n\t} wk;\n\tunsigned int irq_enabled: 1;\n\tunsigned int supports_gmii: 1;\n\tunsigned int aspm_manageable: 1;\n\tdma_addr_t counters_phys_addr;\n\tstruct rtl8169_counters *counters;\n\tstruct rtl8169_tc_offsets tc_offset;\n\tu32 saved_wolopts;\n\tint eee_adv;\n\tconst char *fw_name;\n\tstruct rtl_fw *rtl_fw;\n\tu32 ocp_base;\n};\n\ntypedef int (*rtl_fw_read_t)(struct rtl8169_private *, int);\n\nstruct rtl_fw_phy_action {\n\t__le32 *code;\n\tsize_t size;\n};\n\nstruct rtl_fw {\n\trtl_fw_write_t phy_write;\n\trtl_fw_read_t phy_read;\n\trtl_fw_write_t mac_mcu_write;\n\trtl_fw_read_t mac_mcu_read;\n\tconst struct firmware *fw;\n\tconst char *fw_name;\n\tstruct device *dev;\n\tchar version[32];\n\tstruct rtl_fw_phy_action phy_action;\n};\n\nenum rtl_registers {\n\tMAC0___2 = 0,\n\tMAC4 = 4,\n\tMAR0___2 = 8,\n\tCounterAddrLow = 16,\n\tCounterAddrHigh = 20,\n\tTxDescStartAddrLow = 32,\n\tTxDescStartAddrHigh = 36,\n\tTxHDescStartAddrLow = 40,\n\tTxHDescStartAddrHigh = 44,\n\tFLASH = 48,\n\tERSR = 54,\n\tChipCmd___2 = 55,\n\tTxPoll = 56,\n\tIntrMask___2 = 60,\n\tIntrStatus___2 = 62,\n\tTxConfig___2 = 64,\n\tRxConfig___2 = 68,\n\tCfg9346___2 = 80,\n\tConfig0___2 = 81,\n\tConfig1___2 = 82,\n\tConfig2 = 83,\n\tConfig3___2 = 84,\n\tConfig4___2 = 85,\n\tConfig5___2 = 86,\n\tPHYAR = 96,\n\tPHYstatus = 108,\n\tRxMaxSize = 218,\n\tCPlusCmd = 224,\n\tIntrMitigate = 226,\n\tRxDescAddrLow = 228,\n\tRxDescAddrHigh = 232,\n\tEarlyTxThres = 236,\n\tMaxTxPacketSize = 236,\n\tFuncEvent = 240,\n\tFuncEventMask = 244,\n\tFuncPresetState = 248,\n\tIBCR0 = 248,\n\tIBCR2 = 249,\n\tIBIMR0 = 250,\n\tIBISR0 = 251,\n\tFuncForceEvent = 252,\n};\n\nenum rtl8168_8101_registers {\n\tCSIDR = 100,\n\tCSIAR = 104,\n\tPMCH = 111,\n\tEPHYAR = 128,\n\tDLLPR = 208,\n\tDBG_REG = 209,\n\tTWSI = 210,\n\tMCU = 211,\n\tEFUSEAR = 220,\n\tMISC_1 = 242,\n};\n\nenum rtl8168_registers {\n\tLED_FREQ = 26,\n\tEEE_LED = 27,\n\tERIDR = 112,\n\tERIAR = 116,\n\tEPHY_RXER_NUM = 124,\n\tOCPDR = 176,\n\tOCPAR = 180,\n\tGPHY_OCP = 184,\n\tRDSAR1 = 208,\n\tMISC = 240,\n};\n\nenum rtl8125_registers {\n\tIntrMask_8125 = 56,\n\tIntrStatus_8125 = 60,\n\tTxPoll_8125 = 144,\n\tMAC0_BKP = 6624,\n};\n\nenum rtl_register_content {\n\tSYSErr = 32768,\n\tPCSTimeout___2 = 16384,\n\tSWInt = 256,\n\tTxDescUnavail = 128,\n\tRxFIFOOver___2 = 64,\n\tLinkChg = 32,\n\tRxOverflow___2 = 16,\n\tTxErr___2 = 8,\n\tTxOK___2 = 4,\n\tRxErr___2 = 2,\n\tRxOK___2 = 1,\n\tRxRWT = 4194304,\n\tRxRES = 2097152,\n\tRxRUNT = 1048576,\n\tRxCRC = 524288,\n\tStopReq = 128,\n\tCmdReset___2 = 16,\n\tCmdRxEnb___2 = 8,\n\tCmdTxEnb___2 = 4,\n\tRxBufEmpty___2 = 1,\n\tHPQ = 128,\n\tNPQ = 64,\n\tFSWInt = 1,\n\tCfg9346_Lock___2 = 0,\n\tCfg9346_Unlock___2 = 192,\n\tAcceptErr___2 = 32,\n\tAcceptRunt___2 = 16,\n\tAcceptBroadcast___2 = 8,\n\tAcceptMulticast___2 = 4,\n\tAcceptMyPhys___2 = 2,\n\tAcceptAllPhys___2 = 1,\n\tTxInterFrameGapShift = 24,\n\tTxDMAShift___2 = 8,\n\tLEDS1 = 128,\n\tLEDS0 = 64,\n\tSpeed_down = 16,\n\tMEMMAP = 8,\n\tIOMAP = 4,\n\tVPD = 2,\n\tPMEnable = 1,\n\tClkReqEn = 128,\n\tMSIEnable = 32,\n\tPCI_Clock_66MHz = 1,\n\tPCI_Clock_33MHz = 0,\n\tMagicPacket = 32,\n\tLinkUp = 16,\n\tJumbo_En0 = 4,\n\tRdy_to_L23 = 2,\n\tBeacon_en = 1,\n\tJumbo_En1 = 2,\n\tBWF = 64,\n\tMWF = 32,\n\tUWF = 16,\n\tSpi_en = 8,\n\tLanWake = 2,\n\tPMEStatus = 1,\n\tASPM_en = 1,\n\tEnableBist = 32768,\n\tMac_dbgo_oe = 16384,\n\tEnAnaPLL = 16384,\n\tNormal_mode = 8192,\n\tForce_half_dup = 4096,\n\tForce_rxflow_en = 2048,\n\tForce_txflow_en = 1024,\n\tCxpl_dbg_sel = 512,\n\tASF = 256,\n\tPktCntrDisable = 128,\n\tMac_dbgo_sel = 28,\n\tRxVlan = 64,\n\tRxChkSum = 32,\n\tPCIDAC = 16,\n\tPCIMulRW = 8,\n\tTBI_Enable = 128,\n\tTxFlowCtrl = 64,\n\tRxFlowCtrl = 32,\n\t_1000bpsF = 16,\n\t_100bps = 8,\n\t_10bps = 4,\n\tLinkStatus = 2,\n\tFullDup = 1,\n\tCounterReset = 1,\n\tCounterDump = 8,\n\tMagicPacket_v2 = 65536,\n};\n\nenum rtl_desc_bit {\n\tDescOwn = 2147483648,\n\tRingEnd = 1073741824,\n\tFirstFrag = 536870912,\n\tLastFrag = 268435456,\n};\n\nenum rtl_tx_desc_bit {\n\tTD_LSO = 134217728,\n\tTxVlanTag = 131072,\n};\n\nenum rtl_tx_desc_bit_0 {\n\tTD0_TCP_CS = 65536,\n\tTD0_UDP_CS = 131072,\n\tTD0_IP_CS = 262144,\n};\n\nenum rtl_tx_desc_bit_1 {\n\tTD1_GTSENV4 = 67108864,\n\tTD1_GTSENV6 = 33554432,\n\tTD1_IPv6_CS = 268435456,\n\tTD1_IPv4_CS = 536870912,\n\tTD1_TCP_CS = 1073741824,\n\tTD1_UDP_CS = 2147483648,\n};\n\nenum rtl_rx_desc_bit {\n\tPID1 = 262144,\n\tPID0 = 131072,\n\tIPFail = 65536,\n\tUDPFail = 32768,\n\tTCPFail = 16384,\n\tRxVlanTag = 65536,\n};\n\nstruct TxDesc {\n\t__le32 opts1;\n\t__le32 opts2;\n\t__le64 addr;\n};\n\nstruct RxDesc {\n\t__le32 opts1;\n\t__le32 opts2;\n\t__le64 addr;\n};\n\nstruct rtl8169_counters {\n\t__le64 tx_packets;\n\t__le64 rx_packets;\n\t__le64 tx_errors;\n\t__le32 rx_errors;\n\t__le16 rx_missed;\n\t__le16 align_errors;\n\t__le32 tx_one_collision;\n\t__le32 tx_multi_collision;\n\t__le64 rx_unicast;\n\t__le64 rx_broadcast;\n\t__le32 rx_multicast;\n\t__le16 tx_aborted;\n\t__le16 tx_underun;\n};\n\nenum rtl_flag {\n\tRTL_FLAG_TASK_ENABLED = 0,\n\tRTL_FLAG_TASK_RESET_PENDING = 1,\n\tRTL_FLAG_MAX = 2,\n};\n\ntypedef void (*rtl_generic_fct)(struct rtl8169_private *);\n\nstruct rtl_cond {\n\tbool (*check)(struct rtl8169_private *);\n\tconst char *msg;\n};\n\nstruct rtl_coalesce_info {\n\tu32 speed;\n\tu32 scale_nsecs[4];\n};\n\nstruct ephy_info {\n\tunsigned int offset;\n\tu16 mask;\n\tu16 bits;\n};\n\nstruct rtl_mac_info {\n\tu16 mask;\n\tu16 val;\n\tenum mac_version ver;\n};\n\nenum rtl_fw_opcode {\n\tPHY_READ = 0,\n\tPHY_DATA_OR = 1,\n\tPHY_DATA_AND = 2,\n\tPHY_BJMPN = 3,\n\tPHY_MDIO_CHG = 4,\n\tPHY_CLEAR_READCOUNT = 7,\n\tPHY_WRITE = 8,\n\tPHY_READCOUNT_EQ_SKIP = 9,\n\tPHY_COMP_EQ_SKIPN = 10,\n\tPHY_COMP_NEQ_SKIPN = 11,\n\tPHY_WRITE_PREVIOUS = 12,\n\tPHY_SKIPN = 13,\n\tPHY_DELAY_MS = 14,\n};\n\nstruct fw_info {\n\tu32 magic;\n\tchar version[32];\n\t__le32 fw_start;\n\t__le32 fw_len;\n\tu8 chksum;\n} __attribute__((packed));\n\ntypedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *, struct phy_device *);\n\nstruct phy_reg {\n\tu16 reg;\n\tu16 val;\n};\n\nstruct ohci {\n\tvoid *registers;\n};\n\nstruct cdrom_msf {\n\t__u8 cdmsf_min0;\n\t__u8 cdmsf_sec0;\n\t__u8 cdmsf_frame0;\n\t__u8 cdmsf_min1;\n\t__u8 cdmsf_sec1;\n\t__u8 cdmsf_frame1;\n};\n\nstruct cdrom_volctrl {\n\t__u8 channel0;\n\t__u8 channel1;\n\t__u8 channel2;\n\t__u8 channel3;\n};\n\nstruct cdrom_subchnl {\n\t__u8 cdsc_format;\n\t__u8 cdsc_audiostatus;\n\t__u8 cdsc_adr: 4;\n\t__u8 cdsc_ctrl: 4;\n\t__u8 cdsc_trk;\n\t__u8 cdsc_ind;\n\tunion cdrom_addr cdsc_absaddr;\n\tunion cdrom_addr cdsc_reladdr;\n};\n\nstruct cdrom_read_audio {\n\tunion cdrom_addr addr;\n\t__u8 addr_format;\n\tint nframes;\n\t__u8 *buf;\n};\n\nstruct cdrom_blk {\n\tunsigned int from;\n\tshort unsigned int len;\n};\n\nstruct dvd_layer {\n\t__u8 book_version: 4;\n\t__u8 book_type: 4;\n\t__u8 min_rate: 4;\n\t__u8 disc_size: 4;\n\t__u8 layer_type: 4;\n\t__u8 track_path: 1;\n\t__u8 nlayers: 2;\n\tchar: 1;\n\t__u8 track_density: 4;\n\t__u8 linear_density: 4;\n\t__u8 bca: 1;\n\t__u32 start_sector;\n\t__u32 end_sector;\n\t__u32 end_sector_l0;\n};\n\nstruct dvd_physical {\n\t__u8 type;\n\t__u8 layer_num;\n\tstruct dvd_layer layer[4];\n};\n\nstruct dvd_copyright {\n\t__u8 type;\n\t__u8 layer_num;\n\t__u8 cpst;\n\t__u8 rmi;\n};\n\nstruct dvd_disckey {\n\t__u8 type;\n\tunsigned int agid: 2;\n\t__u8 value[2048];\n};\n\nstruct dvd_bca {\n\t__u8 type;\n\tint len;\n\t__u8 value[188];\n};\n\nstruct dvd_manufact {\n\t__u8 type;\n\t__u8 layer_num;\n\tint len;\n\t__u8 value[2048];\n};\n\ntypedef union {\n\t__u8 type;\n\tstruct dvd_physical physical;\n\tstruct dvd_copyright copyright;\n\tstruct dvd_disckey disckey;\n\tstruct dvd_bca bca;\n\tstruct dvd_manufact manufact;\n} dvd_struct;\n\ntypedef __u8 dvd_key[5];\n\ntypedef __u8 dvd_challenge[10];\n\nstruct dvd_lu_send_agid {\n\t__u8 type;\n\tunsigned int agid: 2;\n};\n\nstruct dvd_host_send_challenge {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_challenge chal;\n};\n\nstruct dvd_send_key {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_key key;\n};\n\nstruct dvd_lu_send_challenge {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_challenge chal;\n};\n\nstruct dvd_lu_send_title_key {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tdvd_key title_key;\n\tint lba;\n\tunsigned int cpm: 1;\n\tunsigned int cp_sec: 1;\n\tunsigned int cgms: 2;\n};\n\nstruct dvd_lu_send_asf {\n\t__u8 type;\n\tunsigned int agid: 2;\n\tunsigned int asf: 1;\n};\n\nstruct dvd_host_send_rpcstate {\n\t__u8 type;\n\t__u8 pdrc;\n};\n\nstruct dvd_lu_send_rpcstate {\n\t__u8 type: 2;\n\t__u8 vra: 3;\n\t__u8 ucca: 3;\n\t__u8 region_mask;\n\t__u8 rpc_scheme;\n};\n\ntypedef union {\n\t__u8 type;\n\tstruct dvd_lu_send_agid lsa;\n\tstruct dvd_host_send_challenge hsc;\n\tstruct dvd_send_key lsk;\n\tstruct dvd_lu_send_challenge lsc;\n\tstruct dvd_send_key hsk;\n\tstruct dvd_lu_send_title_key lstk;\n\tstruct dvd_lu_send_asf lsasf;\n\tstruct dvd_host_send_rpcstate hrpcs;\n\tstruct dvd_lu_send_rpcstate lrpcs;\n} dvd_authinfo;\n\nstruct mrw_feature_desc {\n\t__be16 feature_code;\n\t__u8 curr: 1;\n\t__u8 persistent: 1;\n\t__u8 feature_version: 4;\n\t__u8 reserved1: 2;\n\t__u8 add_len;\n\t__u8 write: 1;\n\t__u8 reserved2: 7;\n\t__u8 reserved3;\n\t__u8 reserved4;\n\t__u8 reserved5;\n};\n\nstruct rwrt_feature_desc {\n\t__be16 feature_code;\n\t__u8 curr: 1;\n\t__u8 persistent: 1;\n\t__u8 feature_version: 4;\n\t__u8 reserved1: 2;\n\t__u8 add_len;\n\t__u32 last_lba;\n\t__u32 block_size;\n\t__u16 blocking;\n\t__u8 page_present: 1;\n\t__u8 reserved2: 7;\n\t__u8 reserved3;\n};\n\ntypedef struct {\n\t__be16 disc_information_length;\n\t__u8 disc_status: 2;\n\t__u8 border_status: 2;\n\t__u8 erasable: 1;\n\t__u8 reserved1: 3;\n\t__u8 n_first_track;\n\t__u8 n_sessions_lsb;\n\t__u8 first_track_lsb;\n\t__u8 last_track_lsb;\n\t__u8 mrw_status: 2;\n\t__u8 dbit: 1;\n\t__u8 reserved2: 2;\n\t__u8 uru: 1;\n\t__u8 dbc_v: 1;\n\t__u8 did_v: 1;\n\t__u8 disc_type;\n\t__u8 n_sessions_msb;\n\t__u8 first_track_msb;\n\t__u8 last_track_msb;\n\t__u32 disc_id;\n\t__u32 lead_in;\n\t__u32 lead_out;\n\t__u8 disc_bar_code[8];\n\t__u8 reserved3;\n\t__u8 n_opc;\n} disc_information;\n\ntypedef struct {\n\t__be16 track_information_length;\n\t__u8 track_lsb;\n\t__u8 session_lsb;\n\t__u8 reserved1;\n\t__u8 track_mode: 4;\n\t__u8 copy: 1;\n\t__u8 damage: 1;\n\t__u8 reserved2: 2;\n\t__u8 data_mode: 4;\n\t__u8 fp: 1;\n\t__u8 packet: 1;\n\t__u8 blank: 1;\n\t__u8 rt: 1;\n\t__u8 nwa_v: 1;\n\t__u8 lra_v: 1;\n\t__u8 reserved3: 6;\n\t__be32 track_start;\n\t__be32 next_writable;\n\t__be32 free_blocks;\n\t__be32 fixed_packet_size;\n\t__be32 track_size;\n\t__be32 last_rec_address;\n} track_information;\n\nstruct mode_page_header {\n\t__be16 mode_data_length;\n\t__u8 medium_type;\n\t__u8 reserved1;\n\t__u8 reserved2;\n\t__u8 reserved3;\n\t__be16 desc_length;\n};\n\ntypedef struct {\n\tint data;\n\tint audio;\n\tint cdi;\n\tint xa;\n\tlong int error;\n} tracktype;\n\nstruct cdrom_mechstat_header {\n\t__u8 curslot: 5;\n\t__u8 changer_state: 2;\n\t__u8 fault: 1;\n\t__u8 reserved1: 4;\n\t__u8 door_open: 1;\n\t__u8 mech_state: 3;\n\t__u8 curlba[3];\n\t__u8 nslots;\n\t__u16 slot_tablelen;\n};\n\nstruct cdrom_slot {\n\t__u8 change: 1;\n\t__u8 reserved1: 6;\n\t__u8 disc_present: 1;\n\t__u8 reserved2[3];\n};\n\nstruct cdrom_changer_info {\n\tstruct cdrom_mechstat_header hdr;\n\tstruct cdrom_slot slots[256];\n};\n\nstruct modesel_head {\n\t__u8 reserved1;\n\t__u8 medium;\n\t__u8 reserved2;\n\t__u8 block_desc_length;\n\t__u8 density;\n\t__u8 number_of_blocks_hi;\n\t__u8 number_of_blocks_med;\n\t__u8 number_of_blocks_lo;\n\t__u8 reserved3;\n\t__u8 block_length_hi;\n\t__u8 block_length_med;\n\t__u8 block_length_lo;\n};\n\ntypedef struct {\n\t__u16 report_key_length;\n\t__u8 reserved1;\n\t__u8 reserved2;\n\t__u8 ucca: 3;\n\t__u8 vra: 3;\n\t__u8 type_code: 2;\n\t__u8 region_mask;\n\t__u8 rpc_scheme;\n\t__u8 reserved3;\n} rpc_state_t;\n\nstruct cdrom_sysctl_settings {\n\tchar info[1000];\n\tint autoclose;\n\tint autoeject;\n\tint debug;\n\tint lock;\n\tint check;\n};\n\nenum cdrom_print_option {\n\tCTL_NAME = 0,\n\tCTL_SPEED = 1,\n\tCTL_SLOTS = 2,\n\tCTL_CAPABILITY = 3,\n};\n\nstruct compat_cdrom_read_audio {\n\tunion cdrom_addr addr;\n\tu8 addr_format;\n\tcompat_int_t nframes;\n\tcompat_caddr_t buf;\n};\n\nstruct socket_state_t {\n\tu_int flags;\n\tu_int csc_mask;\n\tu_char Vcc;\n\tu_char Vpp;\n\tu_char io_irq;\n};\n\ntypedef struct socket_state_t socket_state_t;\n\nstruct pccard_io_map {\n\tu_char map;\n\tu_char flags;\n\tu_short speed;\n\tphys_addr_t start;\n\tphys_addr_t stop;\n};\n\nstruct pccard_mem_map {\n\tu_char map;\n\tu_char flags;\n\tu_short speed;\n\tphys_addr_t static_start;\n\tu_int card_start;\n\tstruct resource *res;\n};\n\ntypedef struct pccard_mem_map pccard_mem_map;\n\nstruct io_window_t {\n\tu_int InUse;\n\tu_int Config;\n\tstruct resource *res;\n};\n\ntypedef struct io_window_t io_window_t;\n\nstruct pcmcia_socket;\n\nstruct pccard_operations {\n\tint (*init)(struct pcmcia_socket *);\n\tint (*suspend)(struct pcmcia_socket *);\n\tint (*get_status)(struct pcmcia_socket *, u_int *);\n\tint (*set_socket)(struct pcmcia_socket *, socket_state_t *);\n\tint (*set_io_map)(struct pcmcia_socket *, struct pccard_io_map *);\n\tint (*set_mem_map)(struct pcmcia_socket *, struct pccard_mem_map *);\n};\n\nstruct pccard_resource_ops;\n\nstruct pcmcia_callback;\n\nstruct pcmcia_socket {\n\tstruct module *owner;\n\tsocket_state_t socket;\n\tu_int state;\n\tu_int suspended_state;\n\tu_short functions;\n\tu_short lock_count;\n\tpccard_mem_map cis_mem;\n\tvoid *cis_virt;\n\tio_window_t io[2];\n\tpccard_mem_map win[4];\n\tstruct list_head cis_cache;\n\tsize_t fake_cis_len;\n\tu8 *fake_cis;\n\tstruct list_head socket_list;\n\tstruct completion socket_released;\n\tunsigned int sock;\n\tu_int features;\n\tu_int irq_mask;\n\tu_int map_size;\n\tu_int io_offset;\n\tu_int pci_irq;\n\tstruct pci_dev *cb_dev;\n\tu8 resource_setup_done;\n\tstruct pccard_operations *ops;\n\tstruct pccard_resource_ops *resource_ops;\n\tvoid *resource_data;\n\tvoid (*zoom_video)(struct pcmcia_socket *, int);\n\tint (*power_hook)(struct pcmcia_socket *, int);\n\tvoid (*tune_bridge)(struct pcmcia_socket *, struct pci_bus *);\n\tstruct task_struct *thread;\n\tstruct completion thread_done;\n\tunsigned int thread_events;\n\tunsigned int sysfs_events;\n\tstruct mutex skt_mutex;\n\tstruct mutex ops_mutex;\n\tspinlock_t thread_lock;\n\tstruct pcmcia_callback *callback;\n\tstruct list_head devices_list;\n\tu8 device_count;\n\tu8 pcmcia_pfc;\n\tatomic_t present;\n\tunsigned int pcmcia_irq;\n\tstruct device dev;\n\tvoid *driver_data;\n\tint resume_status;\n};\n\nstruct pccard_resource_ops {\n\tint (*validate_mem)(struct pcmcia_socket *);\n\tint (*find_io)(struct pcmcia_socket *, unsigned int, unsigned int *, unsigned int, unsigned int, struct resource **);\n\tstruct resource * (*find_mem)(long unsigned int, long unsigned int, long unsigned int, int, struct pcmcia_socket *);\n\tint (*init)(struct pcmcia_socket *);\n\tvoid (*exit)(struct pcmcia_socket *);\n};\n\nstruct pcmcia_callback {\n\tstruct module *owner;\n\tint (*add)(struct pcmcia_socket *);\n\tint (*remove)(struct pcmcia_socket *);\n\tvoid (*requery)(struct pcmcia_socket *);\n\tint (*validate)(struct pcmcia_socket *, unsigned int *);\n\tint (*suspend)(struct pcmcia_socket *);\n\tint (*early_resume)(struct pcmcia_socket *);\n\tint (*resume)(struct pcmcia_socket *);\n};\n\nenum {\n\tPCMCIA_IOPORT_0 = 0,\n\tPCMCIA_IOPORT_1 = 1,\n\tPCMCIA_IOMEM_0 = 2,\n\tPCMCIA_IOMEM_1 = 3,\n\tPCMCIA_IOMEM_2 = 4,\n\tPCMCIA_IOMEM_3 = 5,\n\tPCMCIA_NUM_RESOURCES = 6,\n};\n\nstruct cistpl_longlink_mfc_t {\n\tu_char nfn;\n\tstruct {\n\t\tu_char space;\n\t\tu_int addr;\n\t} fn[8];\n};\n\ntypedef struct cistpl_longlink_mfc_t cistpl_longlink_mfc_t;\n\nstruct cistpl_vers_1_t {\n\tu_char major;\n\tu_char minor;\n\tu_char ns;\n\tu_char ofs[4];\n\tchar str[254];\n};\n\ntypedef struct cistpl_vers_1_t cistpl_vers_1_t;\n\nstruct cistpl_manfid_t {\n\tu_short manf;\n\tu_short card;\n};\n\ntypedef struct cistpl_manfid_t cistpl_manfid_t;\n\nstruct cistpl_funcid_t {\n\tu_char func;\n\tu_char sysinit;\n};\n\ntypedef struct cistpl_funcid_t cistpl_funcid_t;\n\nstruct cistpl_config_t {\n\tu_char last_idx;\n\tu_int base;\n\tu_int rmask[4];\n\tu_char subtuples;\n};\n\ntypedef struct cistpl_config_t cistpl_config_t;\n\nstruct cistpl_device_geo_t {\n\tu_char ngeo;\n\tstruct {\n\t\tu_char buswidth;\n\t\tu_int erase_block;\n\t\tu_int read_block;\n\t\tu_int write_block;\n\t\tu_int partition;\n\t\tu_int interleave;\n\t} geo[4];\n};\n\ntypedef struct cistpl_device_geo_t cistpl_device_geo_t;\n\nstruct pcmcia_device_id {\n\t__u16 match_flags;\n\t__u16 manf_id;\n\t__u16 card_id;\n\t__u8 func_id;\n\t__u8 function;\n\t__u8 device_no;\n\t__u32 prod_id_hash[4];\n\tconst char *prod_id[4];\n\tkernel_ulong_t driver_info;\n\tchar *cisfile;\n};\n\nstruct pcmcia_dynids {\n\tstruct mutex lock;\n\tstruct list_head list;\n};\n\nstruct pcmcia_device;\n\nstruct pcmcia_driver {\n\tconst char *name;\n\tint (*probe)(struct pcmcia_device *);\n\tvoid (*remove)(struct pcmcia_device *);\n\tint (*suspend)(struct pcmcia_device *);\n\tint (*resume)(struct pcmcia_device *);\n\tstruct module *owner;\n\tconst struct pcmcia_device_id *id_table;\n\tstruct device_driver drv;\n\tstruct pcmcia_dynids dynids;\n};\n\nstruct config_t;\n\nstruct pcmcia_device {\n\tstruct pcmcia_socket *socket;\n\tchar *devname;\n\tu8 device_no;\n\tu8 func;\n\tstruct config_t *function_config;\n\tstruct list_head socket_device_list;\n\tunsigned int irq;\n\tstruct resource *resource[6];\n\tresource_size_t card_addr;\n\tunsigned int vpp;\n\tunsigned int config_flags;\n\tunsigned int config_base;\n\tunsigned int config_index;\n\tunsigned int config_regs;\n\tunsigned int io_lines;\n\tu16 suspended: 1;\n\tu16 _irq: 1;\n\tu16 _io: 1;\n\tu16 _win: 4;\n\tu16 _locked: 1;\n\tu16 allow_func_id_match: 1;\n\tu16 has_manf_id: 1;\n\tu16 has_card_id: 1;\n\tu16 has_func_id: 1;\n\tu16 reserved: 4;\n\tu8 func_id;\n\tu16 manf_id;\n\tu16 card_id;\n\tchar *prod_id[4];\n\tu64 dma_mask;\n\tstruct device dev;\n\tvoid *priv;\n\tunsigned int open;\n};\n\nstruct config_t {\n\tstruct kref ref;\n\tunsigned int state;\n\tstruct resource io[2];\n\tstruct resource mem[4];\n};\n\ntypedef struct config_t config_t;\n\nstruct pcmcia_dynid {\n\tstruct list_head node;\n\tstruct pcmcia_device_id id;\n};\n\ntypedef long unsigned int u_long;\n\ntypedef struct pccard_io_map pccard_io_map;\n\ntypedef unsigned char cisdata_t;\n\nstruct cistpl_longlink_t {\n\tu_int addr;\n};\n\ntypedef struct cistpl_longlink_t cistpl_longlink_t;\n\nstruct cistpl_checksum_t {\n\tu_short addr;\n\tu_short len;\n\tu_char sum;\n};\n\ntypedef struct cistpl_checksum_t cistpl_checksum_t;\n\nstruct cistpl_altstr_t {\n\tu_char ns;\n\tu_char ofs[4];\n\tchar str[254];\n};\n\ntypedef struct cistpl_altstr_t cistpl_altstr_t;\n\nstruct cistpl_device_t {\n\tu_char ndev;\n\tstruct {\n\t\tu_char type;\n\t\tu_char wp;\n\t\tu_int speed;\n\t\tu_int size;\n\t} dev[4];\n};\n\ntypedef struct cistpl_device_t cistpl_device_t;\n\nstruct cistpl_jedec_t {\n\tu_char nid;\n\tstruct {\n\t\tu_char mfr;\n\t\tu_char info;\n\t} id[4];\n};\n\ntypedef struct cistpl_jedec_t cistpl_jedec_t;\n\nstruct cistpl_funce_t {\n\tu_char type;\n\tu_char data[0];\n};\n\ntypedef struct cistpl_funce_t cistpl_funce_t;\n\nstruct cistpl_bar_t {\n\tu_char attr;\n\tu_int size;\n};\n\ntypedef struct cistpl_bar_t cistpl_bar_t;\n\nstruct cistpl_power_t {\n\tu_char present;\n\tu_char flags;\n\tu_int param[7];\n};\n\ntypedef struct cistpl_power_t cistpl_power_t;\n\nstruct cistpl_timing_t {\n\tu_int wait;\n\tu_int waitscale;\n\tu_int ready;\n\tu_int rdyscale;\n\tu_int reserved;\n\tu_int rsvscale;\n};\n\ntypedef struct cistpl_timing_t cistpl_timing_t;\n\nstruct cistpl_io_t {\n\tu_char flags;\n\tu_char nwin;\n\tstruct {\n\t\tu_int base;\n\t\tu_int len;\n\t} win[16];\n};\n\ntypedef struct cistpl_io_t cistpl_io_t;\n\nstruct cistpl_irq_t {\n\tu_int IRQInfo1;\n\tu_int IRQInfo2;\n};\n\ntypedef struct cistpl_irq_t cistpl_irq_t;\n\nstruct cistpl_mem_t {\n\tu_char flags;\n\tu_char nwin;\n\tstruct {\n\t\tu_int len;\n\t\tu_int card_addr;\n\t\tu_int host_addr;\n\t} win[8];\n};\n\ntypedef struct cistpl_mem_t cistpl_mem_t;\n\nstruct cistpl_cftable_entry_t {\n\tu_char index;\n\tu_short flags;\n\tu_char interface;\n\tcistpl_power_t vcc;\n\tcistpl_power_t vpp1;\n\tcistpl_power_t vpp2;\n\tcistpl_timing_t timing;\n\tcistpl_io_t io;\n\tcistpl_irq_t irq;\n\tcistpl_mem_t mem;\n\tu_char subtuples;\n};\n\ntypedef struct cistpl_cftable_entry_t cistpl_cftable_entry_t;\n\nstruct cistpl_cftable_entry_cb_t {\n\tu_char index;\n\tu_int flags;\n\tcistpl_power_t vcc;\n\tcistpl_power_t vpp1;\n\tcistpl_power_t vpp2;\n\tu_char io;\n\tcistpl_irq_t irq;\n\tu_char mem;\n\tu_char subtuples;\n};\n\ntypedef struct cistpl_cftable_entry_cb_t cistpl_cftable_entry_cb_t;\n\nstruct cistpl_vers_2_t {\n\tu_char vers;\n\tu_char comply;\n\tu_short dindex;\n\tu_char vspec8;\n\tu_char vspec9;\n\tu_char nhdr;\n\tu_char vendor;\n\tu_char info;\n\tchar str[244];\n};\n\ntypedef struct cistpl_vers_2_t cistpl_vers_2_t;\n\nstruct cistpl_org_t {\n\tu_char data_org;\n\tchar desc[30];\n};\n\ntypedef struct cistpl_org_t cistpl_org_t;\n\nstruct cistpl_format_t {\n\tu_char type;\n\tu_char edc;\n\tu_int offset;\n\tu_int length;\n};\n\ntypedef struct cistpl_format_t cistpl_format_t;\n\nunion cisparse_t {\n\tcistpl_device_t device;\n\tcistpl_checksum_t checksum;\n\tcistpl_longlink_t longlink;\n\tcistpl_longlink_mfc_t longlink_mfc;\n\tcistpl_vers_1_t version_1;\n\tcistpl_altstr_t altstr;\n\tcistpl_jedec_t jedec;\n\tcistpl_manfid_t manfid;\n\tcistpl_funcid_t funcid;\n\tcistpl_funce_t funce;\n\tcistpl_bar_t bar;\n\tcistpl_config_t config;\n\tcistpl_cftable_entry_t cftable_entry;\n\tcistpl_cftable_entry_cb_t cftable_entry_cb;\n\tcistpl_device_geo_t device_geo;\n\tcistpl_vers_2_t vers_2;\n\tcistpl_org_t org;\n\tcistpl_format_t format;\n};\n\ntypedef union cisparse_t cisparse_t;\n\nstruct tuple_t {\n\tu_int Attributes;\n\tcisdata_t DesiredTuple;\n\tu_int Flags;\n\tu_int LinkOffset;\n\tu_int CISOffset;\n\tcisdata_t TupleCode;\n\tcisdata_t TupleLink;\n\tcisdata_t TupleOffset;\n\tcisdata_t TupleDataMax;\n\tcisdata_t TupleDataLen;\n\tcisdata_t *TupleData;\n};\n\ntypedef struct tuple_t tuple_t;\n\nstruct cis_cache_entry {\n\tstruct list_head node;\n\tunsigned int addr;\n\tunsigned int len;\n\tunsigned int attr;\n\tunsigned char cache[0];\n};\n\nstruct tuple_flags {\n\tu_int link_space: 4;\n\tu_int has_link: 1;\n\tu_int mfc_fn: 3;\n\tu_int space: 4;\n};\n\nstruct pcmcia_cfg_mem {\n\tstruct pcmcia_device *p_dev;\n\tint (*conf_check)(struct pcmcia_device *, void *);\n\tvoid *priv_data;\n\tcisparse_t parse;\n\tcistpl_cftable_entry_t dflt;\n};\n\nstruct pcmcia_loop_mem {\n\tstruct pcmcia_device *p_dev;\n\tvoid *priv_data;\n\tint (*loop_tuple)(struct pcmcia_device *, tuple_t *, void *);\n};\n\nstruct pcmcia_loop_get {\n\tsize_t len;\n\tcisdata_t **buf;\n};\n\nstruct resource_map {\n\tu_long base;\n\tu_long num;\n\tstruct resource_map *next;\n};\n\nstruct socket_data {\n\tstruct resource_map mem_db;\n\tstruct resource_map mem_db_valid;\n\tstruct resource_map io_db;\n};\n\nstruct pcmcia_align_data {\n\tlong unsigned int mask;\n\tlong unsigned int offset;\n\tstruct resource_map *map;\n};\n\nstruct yenta_socket;\n\nstruct cardbus_type {\n\tint (*override)(struct yenta_socket *);\n\tvoid (*save_state)(struct yenta_socket *);\n\tvoid (*restore_state)(struct yenta_socket *);\n\tint (*sock_init)(struct yenta_socket *);\n};\n\nstruct yenta_socket {\n\tstruct pci_dev *dev;\n\tint cb_irq;\n\tint io_irq;\n\tvoid *base;\n\tstruct timer_list poll_timer;\n\tstruct pcmcia_socket socket;\n\tstruct cardbus_type *type;\n\tu32 flags;\n\tunsigned int probe_status;\n\tunsigned int private[8];\n\tu32 saved_state[2];\n};\n\nenum {\n\tCARDBUS_TYPE_DEFAULT = 4294967295,\n\tCARDBUS_TYPE_TI = 0,\n\tCARDBUS_TYPE_TI113X = 1,\n\tCARDBUS_TYPE_TI12XX = 2,\n\tCARDBUS_TYPE_TI1250 = 3,\n\tCARDBUS_TYPE_RICOH = 4,\n\tCARDBUS_TYPE_TOPIC95 = 5,\n\tCARDBUS_TYPE_TOPIC97 = 6,\n\tCARDBUS_TYPE_O2MICRO = 7,\n\tCARDBUS_TYPE_ENE = 8,\n};\n\nenum usb_device_speed {\n\tUSB_SPEED_UNKNOWN = 0,\n\tUSB_SPEED_LOW = 1,\n\tUSB_SPEED_FULL = 2,\n\tUSB_SPEED_HIGH = 3,\n\tUSB_SPEED_WIRELESS = 4,\n\tUSB_SPEED_SUPER = 5,\n\tUSB_SPEED_SUPER_PLUS = 6,\n};\n\nenum usb_device_state {\n\tUSB_STATE_NOTATTACHED = 0,\n\tUSB_STATE_ATTACHED = 1,\n\tUSB_STATE_POWERED = 2,\n\tUSB_STATE_RECONNECTING = 3,\n\tUSB_STATE_UNAUTHENTICATED = 4,\n\tUSB_STATE_DEFAULT = 5,\n\tUSB_STATE_ADDRESS = 6,\n\tUSB_STATE_CONFIGURED = 7,\n\tUSB_STATE_SUSPENDED = 8,\n};\n\nenum usb_otg_state {\n\tOTG_STATE_UNDEFINED = 0,\n\tOTG_STATE_B_IDLE = 1,\n\tOTG_STATE_B_SRP_INIT = 2,\n\tOTG_STATE_B_PERIPHERAL = 3,\n\tOTG_STATE_B_WAIT_ACON = 4,\n\tOTG_STATE_B_HOST = 5,\n\tOTG_STATE_A_IDLE = 6,\n\tOTG_STATE_A_WAIT_VRISE = 7,\n\tOTG_STATE_A_WAIT_BCON = 8,\n\tOTG_STATE_A_HOST = 9,\n\tOTG_STATE_A_SUSPEND = 10,\n\tOTG_STATE_A_PERIPHERAL = 11,\n\tOTG_STATE_A_WAIT_VFALL = 12,\n\tOTG_STATE_A_VBUS_ERR = 13,\n};\n\nenum usb_dr_mode {\n\tUSB_DR_MODE_UNKNOWN = 0,\n\tUSB_DR_MODE_HOST = 1,\n\tUSB_DR_MODE_PERIPHERAL = 2,\n\tUSB_DR_MODE_OTG = 3,\n};\n\nstruct usb_device_id {\n\t__u16 match_flags;\n\t__u16 idVendor;\n\t__u16 idProduct;\n\t__u16 bcdDevice_lo;\n\t__u16 bcdDevice_hi;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bInterfaceClass;\n\t__u8 bInterfaceSubClass;\n\t__u8 bInterfaceProtocol;\n\t__u8 bInterfaceNumber;\n\tkernel_ulong_t driver_info;\n};\n\nstruct usb_descriptor_header {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n};\n\nstruct usb_device_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdUSB;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bMaxPacketSize0;\n\t__le16 idVendor;\n\t__le16 idProduct;\n\t__le16 bcdDevice;\n\t__u8 iManufacturer;\n\t__u8 iProduct;\n\t__u8 iSerialNumber;\n\t__u8 bNumConfigurations;\n};\n\nstruct usb_config_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wTotalLength;\n\t__u8 bNumInterfaces;\n\t__u8 bConfigurationValue;\n\t__u8 iConfiguration;\n\t__u8 bmAttributes;\n\t__u8 bMaxPower;\n} __attribute__((packed));\n\nstruct usb_interface_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bInterfaceNumber;\n\t__u8 bAlternateSetting;\n\t__u8 bNumEndpoints;\n\t__u8 bInterfaceClass;\n\t__u8 bInterfaceSubClass;\n\t__u8 bInterfaceProtocol;\n\t__u8 iInterface;\n};\n\nstruct usb_endpoint_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bEndpointAddress;\n\t__u8 bmAttributes;\n\t__le16 wMaxPacketSize;\n\t__u8 bInterval;\n\t__u8 bRefresh;\n\t__u8 bSynchAddress;\n} __attribute__((packed));\n\nstruct usb_ssp_isoc_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wReseved;\n\t__le32 dwBytesPerInterval;\n};\n\nstruct usb_ss_ep_comp_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bMaxBurst;\n\t__u8 bmAttributes;\n\t__le16 wBytesPerInterval;\n};\n\nstruct usb_interface_assoc_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bFirstInterface;\n\t__u8 bInterfaceCount;\n\t__u8 bFunctionClass;\n\t__u8 bFunctionSubClass;\n\t__u8 bFunctionProtocol;\n\t__u8 iFunction;\n};\n\nstruct usb_bos_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 wTotalLength;\n\t__u8 bNumDeviceCaps;\n} __attribute__((packed));\n\nstruct usb_ext_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__le32 bmAttributes;\n} __attribute__((packed));\n\nstruct usb_ss_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bmAttributes;\n\t__le16 wSpeedSupported;\n\t__u8 bFunctionalitySupport;\n\t__u8 bU1devExitLat;\n\t__le16 bU2DevExitLat;\n};\n\nstruct usb_ss_container_id_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bReserved;\n\t__u8 ContainerID[16];\n};\n\nstruct usb_ssp_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n\t__u8 bReserved;\n\t__le32 bmAttributes;\n\t__le16 wFunctionalitySupport;\n\t__le16 wReserved;\n\t__le32 bmSublinkSpeedAttr[1];\n};\n\nstruct usb_ptm_cap_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n};\n\nenum usb3_link_state {\n\tUSB3_LPM_U0 = 0,\n\tUSB3_LPM_U1 = 1,\n\tUSB3_LPM_U2 = 2,\n\tUSB3_LPM_U3 = 3,\n};\n\nstruct ep_device;\n\nstruct usb_host_endpoint {\n\tstruct usb_endpoint_descriptor desc;\n\tstruct usb_ss_ep_comp_descriptor ss_ep_comp;\n\tstruct usb_ssp_isoc_ep_comp_descriptor ssp_isoc_ep_comp;\n\tchar: 8;\n\tstruct list_head urb_list;\n\tvoid *hcpriv;\n\tstruct ep_device *ep_dev;\n\tunsigned char *extra;\n\tint extralen;\n\tint enabled;\n\tint streams;\n\tint: 32;\n} __attribute__((packed));\n\nstruct usb_host_interface {\n\tstruct usb_interface_descriptor desc;\n\tint extralen;\n\tunsigned char *extra;\n\tstruct usb_host_endpoint *endpoint;\n\tchar *string;\n};\n\nenum usb_interface_condition {\n\tUSB_INTERFACE_UNBOUND = 0,\n\tUSB_INTERFACE_BINDING = 1,\n\tUSB_INTERFACE_BOUND = 2,\n\tUSB_INTERFACE_UNBINDING = 3,\n};\n\nstruct usb_interface {\n\tstruct usb_host_interface *altsetting;\n\tstruct usb_host_interface *cur_altsetting;\n\tunsigned int num_altsetting;\n\tstruct usb_interface_assoc_descriptor *intf_assoc;\n\tint minor;\n\tenum usb_interface_condition condition;\n\tunsigned int sysfs_files_created: 1;\n\tunsigned int ep_devs_created: 1;\n\tunsigned int unregistering: 1;\n\tunsigned int needs_remote_wakeup: 1;\n\tunsigned int needs_altsetting0: 1;\n\tunsigned int needs_binding: 1;\n\tunsigned int resetting_device: 1;\n\tunsigned int authorized: 1;\n\tstruct device dev;\n\tstruct device *usb_dev;\n\tstruct work_struct reset_ws;\n};\n\nstruct usb_interface_cache {\n\tunsigned int num_altsetting;\n\tstruct kref ref;\n\tstruct usb_host_interface altsetting[0];\n};\n\nstruct usb_host_config {\n\tstruct usb_config_descriptor desc;\n\tchar *string;\n\tstruct usb_interface_assoc_descriptor *intf_assoc[16];\n\tstruct usb_interface *interface[32];\n\tstruct usb_interface_cache *intf_cache[32];\n\tunsigned char *extra;\n\tint extralen;\n};\n\nstruct usb_host_bos {\n\tstruct usb_bos_descriptor *desc;\n\tstruct usb_ext_cap_descriptor *ext_cap;\n\tstruct usb_ss_cap_descriptor *ss_cap;\n\tstruct usb_ssp_cap_descriptor *ssp_cap;\n\tstruct usb_ss_container_id_descriptor *ss_id;\n\tstruct usb_ptm_cap_descriptor *ptm_cap;\n};\n\nstruct usb_devmap {\n\tlong unsigned int devicemap[2];\n};\n\nstruct usb_device;\n\nstruct mon_bus;\n\nstruct usb_bus {\n\tstruct device *controller;\n\tstruct device *sysdev;\n\tint busnum;\n\tconst char *bus_name;\n\tu8 uses_pio_for_control;\n\tu8 otg_port;\n\tunsigned int is_b_host: 1;\n\tunsigned int b_hnp_enable: 1;\n\tunsigned int no_stop_on_short: 1;\n\tunsigned int no_sg_constraint: 1;\n\tunsigned int sg_tablesize;\n\tint devnum_next;\n\tstruct mutex devnum_next_mutex;\n\tstruct usb_devmap devmap;\n\tstruct usb_device *root_hub;\n\tstruct usb_bus *hs_companion;\n\tint bandwidth_allocated;\n\tint bandwidth_int_reqs;\n\tint bandwidth_isoc_reqs;\n\tunsigned int resuming_ports;\n\tstruct mon_bus *mon_bus;\n\tint monitored;\n};\n\nstruct wusb_dev;\n\nenum usb_device_removable {\n\tUSB_DEVICE_REMOVABLE_UNKNOWN = 0,\n\tUSB_DEVICE_REMOVABLE = 1,\n\tUSB_DEVICE_FIXED = 2,\n};\n\nstruct usb2_lpm_parameters {\n\tunsigned int besl;\n\tint timeout;\n};\n\nstruct usb3_lpm_parameters {\n\tunsigned int mel;\n\tunsigned int pel;\n\tunsigned int sel;\n\tint timeout;\n};\n\nstruct usb_tt;\n\nstruct usb_device {\n\tint devnum;\n\tchar devpath[16];\n\tu32 route;\n\tenum usb_device_state state;\n\tenum usb_device_speed speed;\n\tunsigned int rx_lanes;\n\tunsigned int tx_lanes;\n\tstruct usb_tt *tt;\n\tint ttport;\n\tunsigned int toggle[2];\n\tstruct usb_device *parent;\n\tstruct usb_bus *bus;\n\tstruct usb_host_endpoint ep0;\n\tstruct device dev;\n\tstruct usb_device_descriptor descriptor;\n\tstruct usb_host_bos *bos;\n\tstruct usb_host_config *config;\n\tstruct usb_host_config *actconfig;\n\tstruct usb_host_endpoint *ep_in[16];\n\tstruct usb_host_endpoint *ep_out[16];\n\tchar **rawdescriptors;\n\tshort unsigned int bus_mA;\n\tu8 portnum;\n\tu8 level;\n\tu8 devaddr;\n\tunsigned int can_submit: 1;\n\tunsigned int persist_enabled: 1;\n\tunsigned int have_langid: 1;\n\tunsigned int authorized: 1;\n\tunsigned int authenticated: 1;\n\tunsigned int wusb: 1;\n\tunsigned int lpm_capable: 1;\n\tunsigned int usb2_hw_lpm_capable: 1;\n\tunsigned int usb2_hw_lpm_besl_capable: 1;\n\tunsigned int usb2_hw_lpm_enabled: 1;\n\tunsigned int usb2_hw_lpm_allowed: 1;\n\tunsigned int usb3_lpm_u1_enabled: 1;\n\tunsigned int usb3_lpm_u2_enabled: 1;\n\tint string_langid;\n\tchar *product;\n\tchar *manufacturer;\n\tchar *serial;\n\tstruct list_head filelist;\n\tint maxchild;\n\tu32 quirks;\n\tatomic_t urbnum;\n\tlong unsigned int active_duration;\n\tlong unsigned int connect_time;\n\tunsigned int do_remote_wakeup: 1;\n\tunsigned int reset_resume: 1;\n\tunsigned int port_is_suspended: 1;\n\tstruct wusb_dev *wusb_dev;\n\tint slot_id;\n\tenum usb_device_removable removable;\n\tstruct usb2_lpm_parameters l1_params;\n\tstruct usb3_lpm_parameters u1_params;\n\tstruct usb3_lpm_parameters u2_params;\n\tunsigned int lpm_disable_count;\n\tu16 hub_delay;\n\tunsigned int use_generic_driver: 1;\n};\n\nenum usb_port_connect_type {\n\tUSB_PORT_CONNECT_TYPE_UNKNOWN = 0,\n\tUSB_PORT_CONNECT_TYPE_HOT_PLUG = 1,\n\tUSB_PORT_CONNECT_TYPE_HARD_WIRED = 2,\n\tUSB_PORT_NOT_USED = 3,\n};\n\nstruct usb_tt {\n\tstruct usb_device *hub;\n\tint multi;\n\tunsigned int think_time;\n\tvoid *hcpriv;\n\tspinlock_t lock;\n\tstruct list_head clear_list;\n\tstruct work_struct clear_work;\n};\n\nstruct usb_dynids {\n\tspinlock_t lock;\n\tstruct list_head list;\n};\n\nstruct usbdrv_wrap {\n\tstruct device_driver driver;\n\tint for_devices;\n};\n\nstruct usb_driver {\n\tconst char *name;\n\tint (*probe)(struct usb_interface *, const struct usb_device_id *);\n\tvoid (*disconnect)(struct usb_interface *);\n\tint (*unlocked_ioctl)(struct usb_interface *, unsigned int, void *);\n\tint (*suspend)(struct usb_interface *, pm_message_t);\n\tint (*resume)(struct usb_interface *);\n\tint (*reset_resume)(struct usb_interface *);\n\tint (*pre_reset)(struct usb_interface *);\n\tint (*post_reset)(struct usb_interface *);\n\tconst struct usb_device_id *id_table;\n\tconst struct attribute_group **dev_groups;\n\tstruct usb_dynids dynids;\n\tstruct usbdrv_wrap drvwrap;\n\tunsigned int no_dynamic_id: 1;\n\tunsigned int supports_autosuspend: 1;\n\tunsigned int disable_hub_initiated_lpm: 1;\n\tunsigned int soft_unbind: 1;\n};\n\nstruct usb_device_driver {\n\tconst char *name;\n\tbool (*match)(struct usb_device *);\n\tint (*probe)(struct usb_device *);\n\tvoid (*disconnect)(struct usb_device *);\n\tint (*suspend)(struct usb_device *, pm_message_t);\n\tint (*resume)(struct usb_device *, pm_message_t);\n\tconst struct attribute_group **dev_groups;\n\tstruct usbdrv_wrap drvwrap;\n\tconst struct usb_device_id *id_table;\n\tunsigned int supports_autosuspend: 1;\n\tunsigned int generic_subclass: 1;\n};\n\nstruct usb_iso_packet_descriptor {\n\tunsigned int offset;\n\tunsigned int length;\n\tunsigned int actual_length;\n\tint status;\n};\n\nstruct usb_anchor {\n\tstruct list_head urb_list;\n\twait_queue_head_t wait;\n\tspinlock_t lock;\n\tatomic_t suspend_wakeups;\n\tunsigned int poisoned: 1;\n};\n\nstruct urb;\n\ntypedef void (*usb_complete_t)(struct urb *);\n\nstruct urb {\n\tstruct kref kref;\n\tint unlinked;\n\tvoid *hcpriv;\n\tatomic_t use_count;\n\tatomic_t reject;\n\tstruct list_head urb_list;\n\tstruct list_head anchor_list;\n\tstruct usb_anchor *anchor;\n\tstruct usb_device *dev;\n\tstruct usb_host_endpoint *ep;\n\tunsigned int pipe;\n\tunsigned int stream_id;\n\tint status;\n\tunsigned int transfer_flags;\n\tvoid *transfer_buffer;\n\tdma_addr_t transfer_dma;\n\tstruct scatterlist *sg;\n\tint num_mapped_sgs;\n\tint num_sgs;\n\tu32 transfer_buffer_length;\n\tu32 actual_length;\n\tunsigned char *setup_packet;\n\tdma_addr_t setup_dma;\n\tint start_frame;\n\tint number_of_packets;\n\tint interval;\n\tint error_count;\n\tvoid *context;\n\tusb_complete_t complete;\n\tstruct usb_iso_packet_descriptor iso_frame_desc[0];\n};\n\nstruct giveback_urb_bh {\n\tbool running;\n\tspinlock_t lock;\n\tstruct list_head head;\n\tstruct tasklet_struct bh;\n\tstruct usb_host_endpoint *completing_ep;\n};\n\nenum usb_dev_authorize_policy {\n\tUSB_DEVICE_AUTHORIZE_NONE = 0,\n\tUSB_DEVICE_AUTHORIZE_ALL = 1,\n\tUSB_DEVICE_AUTHORIZE_INTERNAL = 2,\n};\n\nstruct usb_phy_roothub;\n\nstruct hc_driver;\n\nstruct usb_phy;\n\nstruct usb_hcd {\n\tstruct usb_bus self;\n\tstruct kref kref;\n\tconst char *product_desc;\n\tint speed;\n\tchar irq_descr[24];\n\tstruct timer_list rh_timer;\n\tstruct urb *status_urb;\n\tstruct work_struct wakeup_work;\n\tstruct work_struct died_work;\n\tconst struct hc_driver *driver;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_phy_roothub *phy_roothub;\n\tlong unsigned int flags;\n\tenum usb_dev_authorize_policy dev_policy;\n\tunsigned int rh_registered: 1;\n\tunsigned int rh_pollable: 1;\n\tunsigned int msix_enabled: 1;\n\tunsigned int msi_enabled: 1;\n\tunsigned int skip_phy_initialization: 1;\n\tunsigned int uses_new_polling: 1;\n\tunsigned int wireless: 1;\n\tunsigned int has_tt: 1;\n\tunsigned int amd_resume_bug: 1;\n\tunsigned int can_do_streams: 1;\n\tunsigned int tpl_support: 1;\n\tunsigned int cant_recv_wakeups: 1;\n\tunsigned int irq;\n\tvoid *regs;\n\tresource_size_t rsrc_start;\n\tresource_size_t rsrc_len;\n\tunsigned int power_budget;\n\tstruct giveback_urb_bh high_prio_bh;\n\tstruct giveback_urb_bh low_prio_bh;\n\tstruct mutex *address0_mutex;\n\tstruct mutex *bandwidth_mutex;\n\tstruct usb_hcd *shared_hcd;\n\tstruct usb_hcd *primary_hcd;\n\tstruct dma_pool___2 *pool[4];\n\tint state;\n\tstruct gen_pool *localmem_pool;\n\tlong unsigned int hcd_priv[0];\n};\n\nstruct hc_driver {\n\tconst char *description;\n\tconst char *product_desc;\n\tsize_t hcd_priv_size;\n\tirqreturn_t (*irq)(struct usb_hcd *);\n\tint flags;\n\tint (*reset)(struct usb_hcd *);\n\tint (*start)(struct usb_hcd *);\n\tint (*pci_suspend)(struct usb_hcd *, bool);\n\tint (*pci_resume)(struct usb_hcd *, bool);\n\tvoid (*stop)(struct usb_hcd *);\n\tvoid (*shutdown)(struct usb_hcd *);\n\tint (*get_frame_number)(struct usb_hcd *);\n\tint (*urb_enqueue)(struct usb_hcd *, struct urb *, gfp_t);\n\tint (*urb_dequeue)(struct usb_hcd *, struct urb *, int);\n\tint (*map_urb_for_dma)(struct usb_hcd *, struct urb *, gfp_t);\n\tvoid (*unmap_urb_for_dma)(struct usb_hcd *, struct urb *);\n\tvoid (*endpoint_disable)(struct usb_hcd *, struct usb_host_endpoint *);\n\tvoid (*endpoint_reset)(struct usb_hcd *, struct usb_host_endpoint *);\n\tint (*hub_status_data)(struct usb_hcd *, char *);\n\tint (*hub_control)(struct usb_hcd *, u16, u16, u16, char *, u16);\n\tint (*bus_suspend)(struct usb_hcd *);\n\tint (*bus_resume)(struct usb_hcd *);\n\tint (*start_port_reset)(struct usb_hcd *, unsigned int);\n\tlong unsigned int (*get_resuming_ports)(struct usb_hcd *);\n\tvoid (*relinquish_port)(struct usb_hcd *, int);\n\tint (*port_handed_over)(struct usb_hcd *, int);\n\tvoid (*clear_tt_buffer_complete)(struct usb_hcd *, struct usb_host_endpoint *);\n\tint (*alloc_dev)(struct usb_hcd *, struct usb_device *);\n\tvoid (*free_dev)(struct usb_hcd *, struct usb_device *);\n\tint (*alloc_streams)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint **, unsigned int, unsigned int, gfp_t);\n\tint (*free_streams)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint **, unsigned int, gfp_t);\n\tint (*add_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*drop_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);\n\tint (*check_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tvoid (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);\n\tint (*address_device)(struct usb_hcd *, struct usb_device *);\n\tint (*enable_device)(struct usb_hcd *, struct usb_device *);\n\tint (*update_hub_device)(struct usb_hcd *, struct usb_device *, struct usb_tt *, gfp_t);\n\tint (*reset_device)(struct usb_hcd *, struct usb_device *);\n\tint (*update_device)(struct usb_hcd *, struct usb_device *);\n\tint (*set_usb2_hw_lpm)(struct usb_hcd *, struct usb_device *, int);\n\tint (*enable_usb3_lpm_timeout)(struct usb_hcd *, struct usb_device *, enum usb3_link_state);\n\tint (*disable_usb3_lpm_timeout)(struct usb_hcd *, struct usb_device *, enum usb3_link_state);\n\tint (*find_raw_port_number)(struct usb_hcd *, int);\n\tint (*port_power)(struct usb_hcd *, int, bool);\n};\n\nenum usb_phy_type {\n\tUSB_PHY_TYPE_UNDEFINED = 0,\n\tUSB_PHY_TYPE_USB2 = 1,\n\tUSB_PHY_TYPE_USB3 = 2,\n};\n\nenum usb_phy_events {\n\tUSB_EVENT_NONE = 0,\n\tUSB_EVENT_VBUS = 1,\n\tUSB_EVENT_ID = 2,\n\tUSB_EVENT_CHARGER = 3,\n\tUSB_EVENT_ENUMERATED = 4,\n};\n\nstruct extcon_dev;\n\nenum usb_charger_type {\n\tUNKNOWN_TYPE = 0,\n\tSDP_TYPE = 1,\n\tDCP_TYPE = 2,\n\tCDP_TYPE = 3,\n\tACA_TYPE = 4,\n};\n\nenum usb_charger_state {\n\tUSB_CHARGER_DEFAULT = 0,\n\tUSB_CHARGER_PRESENT = 1,\n\tUSB_CHARGER_ABSENT = 2,\n};\n\nstruct usb_charger_current {\n\tunsigned int sdp_min;\n\tunsigned int sdp_max;\n\tunsigned int dcp_min;\n\tunsigned int dcp_max;\n\tunsigned int cdp_min;\n\tunsigned int cdp_max;\n\tunsigned int aca_min;\n\tunsigned int aca_max;\n};\n\nstruct usb_otg;\n\nstruct usb_phy_io_ops;\n\nstruct usb_phy {\n\tstruct device *dev;\n\tconst char *label;\n\tunsigned int flags;\n\tenum usb_phy_type type;\n\tenum usb_phy_events last_event;\n\tstruct usb_otg *otg;\n\tstruct device *io_dev;\n\tstruct usb_phy_io_ops *io_ops;\n\tvoid *io_priv;\n\tstruct extcon_dev *edev;\n\tstruct extcon_dev *id_edev;\n\tstruct notifier_block vbus_nb;\n\tstruct notifier_block id_nb;\n\tstruct notifier_block type_nb;\n\tenum usb_charger_type chg_type;\n\tenum usb_charger_state chg_state;\n\tstruct usb_charger_current chg_cur;\n\tstruct work_struct chg_work;\n\tstruct atomic_notifier_head notifier;\n\tu16 port_status;\n\tu16 port_change;\n\tstruct list_head head;\n\tint (*init)(struct usb_phy *);\n\tvoid (*shutdown)(struct usb_phy *);\n\tint (*set_vbus)(struct usb_phy *, int);\n\tint (*set_power)(struct usb_phy *, unsigned int);\n\tint (*set_suspend)(struct usb_phy *, int);\n\tint (*set_wakeup)(struct usb_phy *, bool);\n\tint (*notify_connect)(struct usb_phy *, enum usb_device_speed);\n\tint (*notify_disconnect)(struct usb_phy *, enum usb_device_speed);\n\tenum usb_charger_type (*charger_detect)(struct usb_phy *);\n};\n\nstruct usb_port_status {\n\t__le16 wPortStatus;\n\t__le16 wPortChange;\n\t__le32 dwExtPortStatus;\n};\n\nstruct usb_hub_status {\n\t__le16 wHubStatus;\n\t__le16 wHubChange;\n};\n\nstruct usb_hub_descriptor {\n\t__u8 bDescLength;\n\t__u8 bDescriptorType;\n\t__u8 bNbrPorts;\n\t__le16 wHubCharacteristics;\n\t__u8 bPwrOn2PwrGood;\n\t__u8 bHubContrCurrent;\n\tunion {\n\t\tstruct {\n\t\t\t__u8 DeviceRemovable[4];\n\t\t\t__u8 PortPwrCtrlMask[4];\n\t\t} hs;\n\t\tstruct {\n\t\t\t__u8 bHubHdrDecLat;\n\t\t\t__le16 wHubDelay;\n\t\t\t__le16 DeviceRemovable;\n\t\t} __attribute__((packed)) ss;\n\t} u;\n} __attribute__((packed));\n\nstruct usb_mon_operations {\n\tvoid (*urb_submit)(struct usb_bus *, struct urb *);\n\tvoid (*urb_submit_error)(struct usb_bus *, struct urb *, int);\n\tvoid (*urb_complete)(struct usb_bus *, struct urb *, int);\n};\n\nstruct usb_phy_io_ops {\n\tint (*read)(struct usb_phy *, u32);\n\tint (*write)(struct usb_phy *, u32, u32);\n};\n\nstruct usb_gadget;\n\nstruct usb_otg {\n\tu8 default_a;\n\tstruct phy___2 *phy;\n\tstruct usb_phy *usb_phy;\n\tstruct usb_bus *host;\n\tstruct usb_gadget *gadget;\n\tenum usb_otg_state state;\n\tint (*set_host)(struct usb_otg *, struct usb_bus *);\n\tint (*set_peripheral)(struct usb_otg *, struct usb_gadget *);\n\tint (*set_vbus)(struct usb_otg *, bool);\n\tint (*start_srp)(struct usb_otg *);\n\tint (*start_hnp)(struct usb_otg *);\n};\n\ntypedef u32 usb_port_location_t;\n\nstruct usb_port;\n\nstruct usb_hub {\n\tstruct device *intfdev;\n\tstruct usb_device *hdev;\n\tstruct kref kref;\n\tstruct urb *urb;\n\tu8 (*buffer)[8];\n\tunion {\n\t\tstruct usb_hub_status hub;\n\t\tstruct usb_port_status port;\n\t} *status;\n\tstruct mutex status_mutex;\n\tint error;\n\tint nerrors;\n\tlong unsigned int event_bits[1];\n\tlong unsigned int change_bits[1];\n\tlong unsigned int removed_bits[1];\n\tlong unsigned int wakeup_bits[1];\n\tlong unsigned int power_bits[1];\n\tlong unsigned int child_usage_bits[1];\n\tlong unsigned int warm_reset_bits[1];\n\tstruct usb_hub_descriptor *descriptor;\n\tstruct usb_tt tt;\n\tunsigned int mA_per_port;\n\tunsigned int wakeup_enabled_descendants;\n\tunsigned int limited_power: 1;\n\tunsigned int quiescing: 1;\n\tunsigned int disconnected: 1;\n\tunsigned int in_reset: 1;\n\tunsigned int quirk_disable_autosuspend: 1;\n\tunsigned int quirk_check_port_auto_suspend: 1;\n\tunsigned int has_indicators: 1;\n\tu8 indicator[31];\n\tstruct delayed_work leds;\n\tstruct delayed_work init_work;\n\tstruct work_struct events;\n\tspinlock_t irq_urb_lock;\n\tstruct timer_list irq_urb_retry;\n\tstruct usb_port **ports;\n};\n\nstruct usb_dev_state;\n\nstruct usb_port {\n\tstruct usb_device *child;\n\tstruct device dev;\n\tstruct usb_dev_state *port_owner;\n\tstruct usb_port *peer;\n\tstruct dev_pm_qos_request *req;\n\tenum usb_port_connect_type connect_type;\n\tusb_port_location_t location;\n\tstruct mutex status_lock;\n\tu32 over_current_count;\n\tu8 portnum;\n\tu32 quirks;\n\tunsigned int is_superspeed: 1;\n\tunsigned int usb3_lpm_u1_permit: 1;\n\tunsigned int usb3_lpm_u2_permit: 1;\n};\n\nstruct find_interface_arg {\n\tint minor;\n\tstruct device_driver *drv;\n};\n\nstruct each_dev_arg {\n\tvoid *data;\n\tint (*fn)(struct usb_device *, void *);\n};\n\nstruct usb_qualifier_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdUSB;\n\t__u8 bDeviceClass;\n\t__u8 bDeviceSubClass;\n\t__u8 bDeviceProtocol;\n\t__u8 bMaxPacketSize0;\n\t__u8 bNumConfigurations;\n\t__u8 bRESERVED;\n};\n\nstruct usb_set_sel_req {\n\t__u8 u1_sel;\n\t__u8 u1_pel;\n\t__le16 u2_sel;\n\t__le16 u2_pel;\n};\n\nstruct usbdevfs_hub_portinfo {\n\tchar nports;\n\tchar port[127];\n};\n\nenum hub_led_mode {\n\tINDICATOR_AUTO = 0,\n\tINDICATOR_CYCLE = 1,\n\tINDICATOR_GREEN_BLINK = 2,\n\tINDICATOR_GREEN_BLINK_OFF = 3,\n\tINDICATOR_AMBER_BLINK = 4,\n\tINDICATOR_AMBER_BLINK_OFF = 5,\n\tINDICATOR_ALT_BLINK = 6,\n\tINDICATOR_ALT_BLINK_OFF = 7,\n};\n\nstruct usb_tt_clear {\n\tstruct list_head clear_list;\n\tunsigned int tt;\n\tu16 devinfo;\n\tstruct usb_hcd *hcd;\n\tstruct usb_host_endpoint *ep;\n};\n\nenum hub_activation_type {\n\tHUB_INIT = 0,\n\tHUB_INIT2 = 1,\n\tHUB_INIT3 = 2,\n\tHUB_POST_RESET = 3,\n\tHUB_RESUME = 4,\n\tHUB_RESET_RESUME = 5,\n};\n\nenum hub_quiescing_type {\n\tHUB_DISCONNECT = 0,\n\tHUB_PRE_RESET = 1,\n\tHUB_SUSPEND = 2,\n};\n\nstruct usb_ctrlrequest {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__le16 wValue;\n\t__le16 wIndex;\n\t__le16 wLength;\n};\n\nenum usb_led_event {\n\tUSB_LED_EVENT_HOST = 0,\n\tUSB_LED_EVENT_GADGET = 1,\n};\n\nstruct usb_sg_request {\n\tint status;\n\tsize_t bytes;\n\tspinlock_t lock;\n\tstruct usb_device *dev;\n\tint pipe;\n\tint entries;\n\tstruct urb **urbs;\n\tint count;\n\tstruct completion complete;\n};\n\nstruct usb_cdc_header_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdCDC;\n} __attribute__((packed));\n\nstruct usb_cdc_call_mgmt_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bmCapabilities;\n\t__u8 bDataInterface;\n};\n\nstruct usb_cdc_acm_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bmCapabilities;\n};\n\nstruct usb_cdc_union_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bMasterInterface0;\n\t__u8 bSlaveInterface0;\n};\n\nstruct usb_cdc_country_functional_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 iCountryCodeRelDate;\n\t__le16 wCountyCode0;\n};\n\nstruct usb_cdc_network_terminal_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bEntityId;\n\t__u8 iName;\n\t__u8 bChannelIndex;\n\t__u8 bPhysicalInterface;\n};\n\nstruct usb_cdc_ether_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 iMACAddress;\n\t__le32 bmEthernetStatistics;\n\t__le16 wMaxSegmentSize;\n\t__le16 wNumberMCFilters;\n\t__u8 bNumberPowerFilters;\n} __attribute__((packed));\n\nstruct usb_cdc_dmm_desc {\n\t__u8 bFunctionLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubtype;\n\t__u16 bcdVersion;\n\t__le16 wMaxCommand;\n} __attribute__((packed));\n\nstruct usb_cdc_mdlm_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdVersion;\n\t__u8 bGUID[16];\n} __attribute__((packed));\n\nstruct usb_cdc_mdlm_detail_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__u8 bGuidDescriptorType;\n\t__u8 bDetailData[0];\n};\n\nstruct usb_cdc_obex_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdVersion;\n} __attribute__((packed));\n\nstruct usb_cdc_ncm_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdNcmVersion;\n\t__u8 bmNetworkCapabilities;\n} __attribute__((packed));\n\nstruct usb_cdc_mbim_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdMBIMVersion;\n\t__le16 wMaxControlMessage;\n\t__u8 bNumberFilters;\n\t__u8 bMaxFilterSize;\n\t__le16 wMaxSegmentSize;\n\t__u8 bmNetworkCapabilities;\n} __attribute__((packed));\n\nstruct usb_cdc_mbim_extended_desc {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDescriptorSubType;\n\t__le16 bcdMBIMExtendedVersion;\n\t__u8 bMaxOutstandingCommandMessages;\n\t__le16 wMTU;\n} __attribute__((packed));\n\nstruct usb_cdc_parsed_header {\n\tstruct usb_cdc_union_desc *usb_cdc_union_desc;\n\tstruct usb_cdc_header_desc *usb_cdc_header_desc;\n\tstruct usb_cdc_call_mgmt_descriptor *usb_cdc_call_mgmt_descriptor;\n\tstruct usb_cdc_acm_descriptor *usb_cdc_acm_descriptor;\n\tstruct usb_cdc_country_functional_desc *usb_cdc_country_functional_desc;\n\tstruct usb_cdc_network_terminal_desc *usb_cdc_network_terminal_desc;\n\tstruct usb_cdc_ether_desc *usb_cdc_ether_desc;\n\tstruct usb_cdc_dmm_desc *usb_cdc_dmm_desc;\n\tstruct usb_cdc_mdlm_desc *usb_cdc_mdlm_desc;\n\tstruct usb_cdc_mdlm_detail_desc *usb_cdc_mdlm_detail_desc;\n\tstruct usb_cdc_obex_desc *usb_cdc_obex_desc;\n\tstruct usb_cdc_ncm_desc *usb_cdc_ncm_desc;\n\tstruct usb_cdc_mbim_desc *usb_cdc_mbim_desc;\n\tstruct usb_cdc_mbim_extended_desc *usb_cdc_mbim_extended_desc;\n\tbool phonet_magic_present;\n};\n\nstruct api_context {\n\tstruct completion done;\n\tint status;\n};\n\nstruct set_config_request {\n\tstruct usb_device *udev;\n\tint config;\n\tstruct work_struct work;\n\tstruct list_head node;\n};\n\nstruct usb_dynid {\n\tstruct list_head node;\n\tstruct usb_device_id id;\n};\n\nstruct usb_dev_cap_header {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDevCapabilityType;\n};\n\nstruct usb_class_driver {\n\tchar *name;\n\tchar * (*devnode)(struct device *, umode_t *);\n\tconst struct file_operations *fops;\n\tint minor_base;\n};\n\nstruct usb_class {\n\tstruct kref kref;\n\tstruct class *class;\n};\n\nstruct ep_device {\n\tstruct usb_endpoint_descriptor *desc;\n\tstruct usb_device *udev;\n\tstruct device dev;\n};\n\nstruct usbdevfs_ctrltransfer {\n\t__u8 bRequestType;\n\t__u8 bRequest;\n\t__u16 wValue;\n\t__u16 wIndex;\n\t__u16 wLength;\n\t__u32 timeout;\n\tvoid *data;\n};\n\nstruct usbdevfs_bulktransfer {\n\tunsigned int ep;\n\tunsigned int len;\n\tunsigned int timeout;\n\tvoid *data;\n};\n\nstruct usbdevfs_setinterface {\n\tunsigned int interface;\n\tunsigned int altsetting;\n};\n\nstruct usbdevfs_disconnectsignal {\n\tunsigned int signr;\n\tvoid *context;\n};\n\nstruct usbdevfs_getdriver {\n\tunsigned int interface;\n\tchar driver[256];\n};\n\nstruct usbdevfs_connectinfo {\n\tunsigned int devnum;\n\tunsigned char slow;\n};\n\nstruct usbdevfs_conninfo_ex {\n\t__u32 size;\n\t__u32 busnum;\n\t__u32 devnum;\n\t__u32 speed;\n\t__u8 num_ports;\n\t__u8 ports[7];\n};\n\nstruct usbdevfs_iso_packet_desc {\n\tunsigned int length;\n\tunsigned int actual_length;\n\tunsigned int status;\n};\n\nstruct usbdevfs_urb {\n\tunsigned char type;\n\tunsigned char endpoint;\n\tint status;\n\tunsigned int flags;\n\tvoid *buffer;\n\tint buffer_length;\n\tint actual_length;\n\tint start_frame;\n\tunion {\n\t\tint number_of_packets;\n\t\tunsigned int stream_id;\n\t};\n\tint error_count;\n\tunsigned int signr;\n\tvoid *usercontext;\n\tstruct usbdevfs_iso_packet_desc iso_frame_desc[0];\n};\n\nstruct usbdevfs_ioctl {\n\tint ifno;\n\tint ioctl_code;\n\tvoid *data;\n};\n\nstruct usbdevfs_disconnect_claim {\n\tunsigned int interface;\n\tunsigned int flags;\n\tchar driver[256];\n};\n\nstruct usbdevfs_streams {\n\tunsigned int num_streams;\n\tunsigned int num_eps;\n\tunsigned char eps[0];\n};\n\nstruct usbdevfs_ctrltransfer32 {\n\tu8 bRequestType;\n\tu8 bRequest;\n\tu16 wValue;\n\tu16 wIndex;\n\tu16 wLength;\n\tu32 timeout;\n\tcompat_caddr_t data;\n};\n\nstruct usbdevfs_bulktransfer32 {\n\tcompat_uint_t ep;\n\tcompat_uint_t len;\n\tcompat_uint_t timeout;\n\tcompat_caddr_t data;\n};\n\nstruct usbdevfs_disconnectsignal32 {\n\tcompat_int_t signr;\n\tcompat_caddr_t context;\n};\n\nstruct usbdevfs_urb32 {\n\tunsigned char type;\n\tunsigned char endpoint;\n\tcompat_int_t status;\n\tcompat_uint_t flags;\n\tcompat_caddr_t buffer;\n\tcompat_int_t buffer_length;\n\tcompat_int_t actual_length;\n\tcompat_int_t start_frame;\n\tcompat_int_t number_of_packets;\n\tcompat_int_t error_count;\n\tcompat_uint_t signr;\n\tcompat_caddr_t usercontext;\n\tstruct usbdevfs_iso_packet_desc iso_frame_desc[0];\n};\n\nstruct usbdevfs_ioctl32 {\n\ts32 ifno;\n\ts32 ioctl_code;\n\tcompat_caddr_t data;\n};\n\nstruct usb_dev_state___2 {\n\tstruct list_head list;\n\tstruct usb_device *dev;\n\tstruct file *file;\n\tspinlock_t lock;\n\tstruct list_head async_pending;\n\tstruct list_head async_completed;\n\tstruct list_head memory_list;\n\twait_queue_head_t wait;\n\twait_queue_head_t wait_for_resume;\n\tunsigned int discsignr;\n\tstruct pid *disc_pid;\n\tconst struct cred *cred;\n\tsigval_t disccontext;\n\tlong unsigned int ifclaimed;\n\tu32 disabled_bulk_eps;\n\tlong unsigned int interface_allowed_mask;\n\tint not_yet_resumed;\n\tbool suspend_allowed;\n\tbool privileges_dropped;\n};\n\nstruct usb_memory {\n\tstruct list_head memlist;\n\tint vma_use_count;\n\tint urb_use_count;\n\tu32 size;\n\tvoid *mem;\n\tdma_addr_t dma_handle;\n\tlong unsigned int vm_start;\n\tstruct usb_dev_state___2 *ps;\n};\n\nstruct async {\n\tstruct list_head asynclist;\n\tstruct usb_dev_state___2 *ps;\n\tstruct pid *pid;\n\tconst struct cred *cred;\n\tunsigned int signr;\n\tunsigned int ifnum;\n\tvoid *userbuffer;\n\tvoid *userurb;\n\tsigval_t userurb_sigval;\n\tstruct urb *urb;\n\tstruct usb_memory *usbm;\n\tunsigned int mem_usage;\n\tint status;\n\tu8 bulk_addr;\n\tu8 bulk_status;\n};\n\nenum snoop_when {\n\tSUBMIT = 0,\n\tCOMPLETE = 1,\n};\n\nstruct quirk_entry {\n\tu16 vid;\n\tu16 pid;\n\tu32 flags;\n};\n\nstruct device_connect_event {\n\tatomic_t count;\n\twait_queue_head_t wait;\n};\n\nstruct class_info {\n\tint class;\n\tchar *class_name;\n};\n\nstruct usb_phy_roothub___2 {\n\tstruct phy___2 *phy;\n\tstruct list_head list;\n};\n\ntypedef void (*companion_fn)(struct pci_dev *, struct usb_hcd *, struct pci_dev *, struct usb_hcd *);\n\nstruct mon_bus {\n\tstruct list_head bus_link;\n\tspinlock_t lock;\n\tstruct usb_bus *u_bus;\n\tint text_inited;\n\tint bin_inited;\n\tstruct dentry *dent_s;\n\tstruct dentry *dent_t;\n\tstruct dentry *dent_u;\n\tstruct device *classdev;\n\tint nreaders;\n\tstruct list_head r_list;\n\tstruct kref ref;\n\tunsigned int cnt_events;\n\tunsigned int cnt_text_lost;\n};\n\nstruct mon_reader {\n\tstruct list_head r_link;\n\tstruct mon_bus *m_bus;\n\tvoid *r_data;\n\tvoid (*rnf_submit)(void *, struct urb *);\n\tvoid (*rnf_error)(void *, struct urb *, int);\n\tvoid (*rnf_complete)(void *, struct urb *, int);\n};\n\nstruct snap {\n\tint slen;\n\tchar str[80];\n};\n\nstruct mon_iso_desc {\n\tint status;\n\tunsigned int offset;\n\tunsigned int length;\n};\n\nstruct mon_event_text {\n\tstruct list_head e_link;\n\tint type;\n\tlong unsigned int id;\n\tunsigned int tstamp;\n\tint busnum;\n\tchar devnum;\n\tchar epnum;\n\tchar is_in;\n\tchar xfertype;\n\tint length;\n\tint status;\n\tint interval;\n\tint start_frame;\n\tint error_count;\n\tchar setup_flag;\n\tchar data_flag;\n\tint numdesc;\n\tstruct mon_iso_desc isodesc[5];\n\tunsigned char setup[8];\n\tunsigned char data[32];\n};\n\nstruct mon_reader_text {\n\tstruct kmem_cache *e_slab;\n\tint nevents;\n\tstruct list_head e_list;\n\tstruct mon_reader r;\n\twait_queue_head_t wait;\n\tint printf_size;\n\tsize_t printf_offset;\n\tsize_t printf_togo;\n\tchar *printf_buf;\n\tstruct mutex printf_lock;\n\tchar slab_name[30];\n};\n\nstruct mon_text_ptr {\n\tint cnt;\n\tint limit;\n\tchar *pbuf;\n};\n\nenum {\n\tNAMESZ = 10,\n};\n\nstruct iso_rec {\n\tint error_count;\n\tint numdesc;\n};\n\nstruct mon_bin_hdr {\n\tu64 id;\n\tunsigned char type;\n\tunsigned char xfer_type;\n\tunsigned char epnum;\n\tunsigned char devnum;\n\tshort unsigned int busnum;\n\tchar flag_setup;\n\tchar flag_data;\n\ts64 ts_sec;\n\ts32 ts_usec;\n\tint status;\n\tunsigned int len_urb;\n\tunsigned int len_cap;\n\tunion {\n\t\tunsigned char setup[8];\n\t\tstruct iso_rec iso;\n\t} s;\n\tint interval;\n\tint start_frame;\n\tunsigned int xfer_flags;\n\tunsigned int ndesc;\n};\n\nstruct mon_bin_isodesc {\n\tint iso_status;\n\tunsigned int iso_off;\n\tunsigned int iso_len;\n\tu32 _pad;\n};\n\nstruct mon_bin_stats {\n\tu32 queued;\n\tu32 dropped;\n};\n\nstruct mon_bin_get {\n\tstruct mon_bin_hdr *hdr;\n\tvoid *data;\n\tsize_t alloc;\n};\n\nstruct mon_bin_mfetch {\n\tu32 *offvec;\n\tu32 nfetch;\n\tu32 nflush;\n};\n\nstruct mon_bin_get32 {\n\tu32 hdr32;\n\tu32 data32;\n\tu32 alloc32;\n};\n\nstruct mon_bin_mfetch32 {\n\tu32 offvec32;\n\tu32 nfetch32;\n\tu32 nflush32;\n};\n\nstruct mon_pgmap {\n\tstruct page *pg;\n\tunsigned char *ptr;\n};\n\nstruct mon_reader_bin {\n\tspinlock_t b_lock;\n\tunsigned int b_size;\n\tunsigned int b_cnt;\n\tunsigned int b_in;\n\tunsigned int b_out;\n\tunsigned int b_read;\n\tstruct mon_pgmap *b_vec;\n\twait_queue_head_t b_wait;\n\tstruct mutex fetch_lock;\n\tint mmap_active;\n\tstruct mon_reader r;\n\tunsigned int cnt_lost;\n};\n\nenum amd_chipset_gen {\n\tNOT_AMD_CHIPSET = 0,\n\tAMD_CHIPSET_SB600 = 1,\n\tAMD_CHIPSET_SB700 = 2,\n\tAMD_CHIPSET_SB800 = 3,\n\tAMD_CHIPSET_HUDSON2 = 4,\n\tAMD_CHIPSET_BOLTON = 5,\n\tAMD_CHIPSET_YANGTZE = 6,\n\tAMD_CHIPSET_TAISHAN = 7,\n\tAMD_CHIPSET_UNKNOWN = 8,\n};\n\nstruct amd_chipset_type {\n\tenum amd_chipset_gen gen;\n\tu8 rev;\n};\n\nstruct amd_chipset_info {\n\tstruct pci_dev *nb_dev;\n\tstruct pci_dev *smbus_dev;\n\tint nb_type;\n\tstruct amd_chipset_type sb_type;\n\tint isoc_reqs;\n\tint probe_count;\n\tbool need_pll_quirk;\n};\n\nstruct ehci_per_sched {\n\tstruct usb_device *udev;\n\tstruct usb_host_endpoint *ep;\n\tstruct list_head ps_list;\n\tu16 tt_usecs;\n\tu16 cs_mask;\n\tu16 period;\n\tu16 phase;\n\tu8 bw_phase;\n\tu8 phase_uf;\n\tu8 usecs;\n\tu8 c_usecs;\n\tu8 bw_uperiod;\n\tu8 bw_period;\n};\n\nenum ehci_rh_state {\n\tEHCI_RH_HALTED = 0,\n\tEHCI_RH_SUSPENDED = 1,\n\tEHCI_RH_RUNNING = 2,\n\tEHCI_RH_STOPPING = 3,\n};\n\nenum ehci_hrtimer_event {\n\tEHCI_HRTIMER_POLL_ASS = 0,\n\tEHCI_HRTIMER_POLL_PSS = 1,\n\tEHCI_HRTIMER_POLL_DEAD = 2,\n\tEHCI_HRTIMER_UNLINK_INTR = 3,\n\tEHCI_HRTIMER_FREE_ITDS = 4,\n\tEHCI_HRTIMER_ACTIVE_UNLINK = 5,\n\tEHCI_HRTIMER_START_UNLINK_INTR = 6,\n\tEHCI_HRTIMER_ASYNC_UNLINKS = 7,\n\tEHCI_HRTIMER_IAA_WATCHDOG = 8,\n\tEHCI_HRTIMER_DISABLE_PERIODIC = 9,\n\tEHCI_HRTIMER_DISABLE_ASYNC = 10,\n\tEHCI_HRTIMER_IO_WATCHDOG = 11,\n\tEHCI_HRTIMER_NUM_EVENTS = 12,\n};\n\nstruct ehci_caps;\n\nstruct ehci_regs;\n\nstruct ehci_dbg_port;\n\nstruct ehci_qh;\n\nunion ehci_shadow;\n\nstruct ehci_itd;\n\nstruct ehci_sitd;\n\nstruct ehci_hcd {\n\tenum ehci_hrtimer_event next_hrtimer_event;\n\tunsigned int enabled_hrtimer_events;\n\tktime_t hr_timeouts[12];\n\tstruct hrtimer hrtimer;\n\tint PSS_poll_count;\n\tint ASS_poll_count;\n\tint died_poll_count;\n\tstruct ehci_caps *caps;\n\tstruct ehci_regs *regs;\n\tstruct ehci_dbg_port *debug;\n\t__u32 hcs_params;\n\tspinlock_t lock;\n\tenum ehci_rh_state rh_state;\n\tbool scanning: 1;\n\tbool need_rescan: 1;\n\tbool intr_unlinking: 1;\n\tbool iaa_in_progress: 1;\n\tbool async_unlinking: 1;\n\tbool shutdown: 1;\n\tstruct ehci_qh *qh_scan_next;\n\tstruct ehci_qh *async;\n\tstruct ehci_qh *dummy;\n\tstruct list_head async_unlink;\n\tstruct list_head async_idle;\n\tunsigned int async_unlink_cycle;\n\tunsigned int async_count;\n\t__le32 old_current;\n\t__le32 old_token;\n\tunsigned int periodic_size;\n\t__le32 *periodic;\n\tdma_addr_t periodic_dma;\n\tstruct list_head intr_qh_list;\n\tunsigned int i_thresh;\n\tunion ehci_shadow *pshadow;\n\tstruct list_head intr_unlink_wait;\n\tstruct list_head intr_unlink;\n\tunsigned int intr_unlink_wait_cycle;\n\tunsigned int intr_unlink_cycle;\n\tunsigned int now_frame;\n\tunsigned int last_iso_frame;\n\tunsigned int intr_count;\n\tunsigned int isoc_count;\n\tunsigned int periodic_count;\n\tunsigned int uframe_periodic_max;\n\tstruct list_head cached_itd_list;\n\tstruct ehci_itd *last_itd_to_free;\n\tstruct list_head cached_sitd_list;\n\tstruct ehci_sitd *last_sitd_to_free;\n\tlong unsigned int reset_done[15];\n\tlong unsigned int bus_suspended;\n\tlong unsigned int companion_ports;\n\tlong unsigned int owned_ports;\n\tlong unsigned int port_c_suspend;\n\tlong unsigned int suspended_ports;\n\tlong unsigned int resuming_ports;\n\tstruct dma_pool___2 *qh_pool;\n\tstruct dma_pool___2 *qtd_pool;\n\tstruct dma_pool___2 *itd_pool;\n\tstruct dma_pool___2 *sitd_pool;\n\tunsigned int random_frame;\n\tlong unsigned int next_statechange;\n\tktime_t last_periodic_enable;\n\tu32 command;\n\tunsigned int no_selective_suspend: 1;\n\tunsigned int has_fsl_port_bug: 1;\n\tunsigned int has_fsl_hs_errata: 1;\n\tunsigned int has_fsl_susp_errata: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int big_endian_desc: 1;\n\tunsigned int big_endian_capbase: 1;\n\tunsigned int has_amcc_usb23: 1;\n\tunsigned int need_io_watchdog: 1;\n\tunsigned int amd_pll_fix: 1;\n\tunsigned int use_dummy_qh: 1;\n\tunsigned int has_synopsys_hc_bug: 1;\n\tunsigned int frame_index_bug: 1;\n\tunsigned int need_oc_pp_cycle: 1;\n\tunsigned int imx28_write_fix: 1;\n\t__le32 *ohci_hcctrl_reg;\n\tunsigned int has_hostpc: 1;\n\tunsigned int has_tdi_phy_lpm: 1;\n\tunsigned int has_ppcd: 1;\n\tu8 sbrn;\n\tu8 bandwidth[64];\n\tu8 tt_budget[64];\n\tstruct list_head tt_list;\n\tlong unsigned int priv[0];\n};\n\nstruct ehci_caps {\n\tu32 hc_capbase;\n\tu32 hcs_params;\n\tu32 hcc_params;\n\tu8 portroute[8];\n};\n\nstruct ehci_regs {\n\tu32 command;\n\tu32 status;\n\tu32 intr_enable;\n\tu32 frame_index;\n\tu32 segment;\n\tu32 frame_list;\n\tu32 async_next;\n\tu32 reserved1[2];\n\tu32 txfill_tuning;\n\tu32 reserved2[6];\n\tu32 configured_flag;\n\tu32 port_status[0];\n\tu32 reserved3[9];\n\tu32 usbmode;\n\tu32 reserved4[6];\n\tu32 hostpc[0];\n\tu32 reserved5[17];\n\tu32 usbmode_ex;\n};\n\nstruct ehci_dbg_port {\n\tu32 control;\n\tu32 pids;\n\tu32 data03;\n\tu32 data47;\n\tu32 address;\n};\n\nstruct ehci_fstn;\n\nunion ehci_shadow {\n\tstruct ehci_qh *qh;\n\tstruct ehci_itd *itd;\n\tstruct ehci_sitd *sitd;\n\tstruct ehci_fstn *fstn;\n\t__le32 *hw_next;\n\tvoid *ptr;\n};\n\nstruct ehci_qh_hw;\n\nstruct ehci_qtd;\n\nstruct ehci_qh {\n\tstruct ehci_qh_hw *hw;\n\tdma_addr_t qh_dma;\n\tunion ehci_shadow qh_next;\n\tstruct list_head qtd_list;\n\tstruct list_head intr_node;\n\tstruct ehci_qtd *dummy;\n\tstruct list_head unlink_node;\n\tstruct ehci_per_sched ps;\n\tunsigned int unlink_cycle;\n\tu8 qh_state;\n\tu8 xacterrs;\n\tu8 unlink_reason;\n\tu8 gap_uf;\n\tunsigned int is_out: 1;\n\tunsigned int clearing_tt: 1;\n\tunsigned int dequeue_during_giveback: 1;\n\tunsigned int should_be_inactive: 1;\n};\n\nstruct ehci_iso_stream;\n\nstruct ehci_itd {\n\t__le32 hw_next;\n\t__le32 hw_transaction[8];\n\t__le32 hw_bufp[7];\n\t__le32 hw_bufp_hi[7];\n\tdma_addr_t itd_dma;\n\tunion ehci_shadow itd_next;\n\tstruct urb *urb;\n\tstruct ehci_iso_stream *stream;\n\tstruct list_head itd_list;\n\tunsigned int frame;\n\tunsigned int pg;\n\tunsigned int index[8];\n\tlong: 64;\n};\n\nstruct ehci_sitd {\n\t__le32 hw_next;\n\t__le32 hw_fullspeed_ep;\n\t__le32 hw_uframe;\n\t__le32 hw_results;\n\t__le32 hw_buf[2];\n\t__le32 hw_backpointer;\n\t__le32 hw_buf_hi[2];\n\tdma_addr_t sitd_dma;\n\tunion ehci_shadow sitd_next;\n\tstruct urb *urb;\n\tstruct ehci_iso_stream *stream;\n\tstruct list_head sitd_list;\n\tunsigned int frame;\n\tunsigned int index;\n};\n\nstruct ehci_qtd {\n\t__le32 hw_next;\n\t__le32 hw_alt_next;\n\t__le32 hw_token;\n\t__le32 hw_buf[5];\n\t__le32 hw_buf_hi[5];\n\tdma_addr_t qtd_dma;\n\tstruct list_head qtd_list;\n\tstruct urb *urb;\n\tsize_t length;\n};\n\nstruct ehci_fstn {\n\t__le32 hw_next;\n\t__le32 hw_prev;\n\tdma_addr_t fstn_dma;\n\tunion ehci_shadow fstn_next;\n\tlong: 64;\n};\n\nstruct ehci_qh_hw {\n\t__le32 hw_next;\n\t__le32 hw_info1;\n\t__le32 hw_info2;\n\t__le32 hw_current;\n\t__le32 hw_qtd_next;\n\t__le32 hw_alt_next;\n\t__le32 hw_token;\n\t__le32 hw_buf[5];\n\t__le32 hw_buf_hi[5];\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct ehci_iso_packet {\n\tu64 bufp;\n\t__le32 transaction;\n\tu8 cross;\n\tu32 buf1;\n};\n\nstruct ehci_iso_sched {\n\tstruct list_head td_list;\n\tunsigned int span;\n\tunsigned int first_packet;\n\tstruct ehci_iso_packet packet[0];\n};\n\nstruct ehci_iso_stream {\n\tstruct ehci_qh_hw *hw;\n\tu8 bEndpointAddress;\n\tu8 highspeed;\n\tstruct list_head td_list;\n\tstruct list_head free_list;\n\tstruct ehci_per_sched ps;\n\tunsigned int next_uframe;\n\t__le32 splits;\n\tu16 uperiod;\n\tu16 maxp;\n\tunsigned int bandwidth;\n\t__le32 buf0;\n\t__le32 buf1;\n\t__le32 buf2;\n\t__le32 address;\n};\n\nstruct ehci_tt {\n\tu16 bandwidth[8];\n\tstruct list_head tt_list;\n\tstruct list_head ps_list;\n\tstruct usb_tt *usb_tt;\n\tint tt_port;\n};\n\nstruct ehci_driver_overrides {\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n\tint (*port_power)(struct usb_hcd *, int, bool);\n};\n\ntypedef __u32 __hc32;\n\ntypedef __u16 __hc16;\n\nstruct td;\n\nstruct ed {\n\t__hc32 hwINFO;\n\t__hc32 hwTailP;\n\t__hc32 hwHeadP;\n\t__hc32 hwNextED;\n\tdma_addr_t dma;\n\tstruct td *dummy;\n\tstruct ed *ed_next;\n\tstruct ed *ed_prev;\n\tstruct list_head td_list;\n\tstruct list_head in_use_list;\n\tu8 state;\n\tu8 type;\n\tu8 branch;\n\tu16 interval;\n\tu16 load;\n\tu16 last_iso;\n\tu16 tick;\n\tunsigned int takeback_wdh_cnt;\n\tstruct td *pending_td;\n\tlong: 64;\n};\n\nstruct td {\n\t__hc32 hwINFO;\n\t__hc32 hwCBP;\n\t__hc32 hwNextTD;\n\t__hc32 hwBE;\n\t__hc16 hwPSW[2];\n\t__u8 index;\n\tstruct ed *ed;\n\tstruct td *td_hash;\n\tstruct td *next_dl_td;\n\tstruct urb *urb;\n\tdma_addr_t td_dma;\n\tdma_addr_t data_dma;\n\tstruct list_head td_list;\n\tlong: 64;\n};\n\nstruct ohci_hcca {\n\t__hc32 int_table[32];\n\t__hc32 frame_no;\n\t__hc32 done_head;\n\tu8 reserved_for_hc[116];\n\tu8 what[4];\n};\n\nstruct ohci_roothub_regs {\n\t__hc32 a;\n\t__hc32 b;\n\t__hc32 status;\n\t__hc32 portstatus[15];\n};\n\nstruct ohci_regs {\n\t__hc32 revision;\n\t__hc32 control;\n\t__hc32 cmdstatus;\n\t__hc32 intrstatus;\n\t__hc32 intrenable;\n\t__hc32 intrdisable;\n\t__hc32 hcca;\n\t__hc32 ed_periodcurrent;\n\t__hc32 ed_controlhead;\n\t__hc32 ed_controlcurrent;\n\t__hc32 ed_bulkhead;\n\t__hc32 ed_bulkcurrent;\n\t__hc32 donehead;\n\t__hc32 fminterval;\n\t__hc32 fmremaining;\n\t__hc32 fmnumber;\n\t__hc32 periodicstart;\n\t__hc32 lsthresh;\n\tstruct ohci_roothub_regs roothub;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct urb_priv {\n\tstruct ed *ed;\n\tu16 length;\n\tu16 td_cnt;\n\tstruct list_head pending;\n\tstruct td *td[0];\n};\n\ntypedef struct urb_priv urb_priv_t;\n\nenum ohci_rh_state {\n\tOHCI_RH_HALTED = 0,\n\tOHCI_RH_SUSPENDED = 1,\n\tOHCI_RH_RUNNING = 2,\n};\n\nstruct ohci_hcd {\n\tspinlock_t lock;\n\tstruct ohci_regs *regs;\n\tstruct ohci_hcca *hcca;\n\tdma_addr_t hcca_dma;\n\tstruct ed *ed_rm_list;\n\tstruct ed *ed_bulktail;\n\tstruct ed *ed_controltail;\n\tstruct ed *periodic[32];\n\tvoid (*start_hnp)(struct ohci_hcd *);\n\tstruct dma_pool___2 *td_cache;\n\tstruct dma_pool___2 *ed_cache;\n\tstruct td *td_hash[64];\n\tstruct td *dl_start;\n\tstruct td *dl_end;\n\tstruct list_head pending;\n\tstruct list_head eds_in_use;\n\tenum ohci_rh_state rh_state;\n\tint num_ports;\n\tint load[32];\n\tu32 hc_control;\n\tlong unsigned int next_statechange;\n\tu32 fminterval;\n\tunsigned int autostop: 1;\n\tunsigned int working: 1;\n\tunsigned int restart_work: 1;\n\tlong unsigned int flags;\n\tunsigned int prev_frame_no;\n\tunsigned int wdh_cnt;\n\tunsigned int prev_wdh_cnt;\n\tu32 prev_donehead;\n\tstruct timer_list io_watchdog;\n\tstruct work_struct nec_work;\n\tstruct dentry *debug_dir;\n\tlong unsigned int priv[0];\n};\n\nstruct ohci_driver_overrides {\n\tconst char *product_desc;\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n};\n\nstruct debug_buffer {\n\tssize_t (*fill_func)(struct debug_buffer *);\n\tstruct ohci_hcd *ohci;\n\tstruct mutex mutex;\n\tsize_t count;\n\tchar *page;\n};\n\nstruct uhci_td;\n\nstruct uhci_qh {\n\t__le32 link;\n\t__le32 element;\n\tdma_addr_t dma_handle;\n\tstruct list_head node;\n\tstruct usb_host_endpoint *hep;\n\tstruct usb_device *udev;\n\tstruct list_head queue;\n\tstruct uhci_td *dummy_td;\n\tstruct uhci_td *post_td;\n\tstruct usb_iso_packet_descriptor *iso_packet_desc;\n\tlong unsigned int advance_jiffies;\n\tunsigned int unlink_frame;\n\tunsigned int period;\n\tshort int phase;\n\tshort int load;\n\tunsigned int iso_frame;\n\tint state;\n\tint type;\n\tint skel;\n\tunsigned int initial_toggle: 1;\n\tunsigned int needs_fixup: 1;\n\tunsigned int is_stopped: 1;\n\tunsigned int wait_expired: 1;\n\tunsigned int bandwidth_reserved: 1;\n};\n\nstruct uhci_td {\n\t__le32 link;\n\t__le32 status;\n\t__le32 token;\n\t__le32 buffer;\n\tdma_addr_t dma_handle;\n\tstruct list_head list;\n\tint frame;\n\tstruct list_head fl_list;\n};\n\nenum uhci_rh_state {\n\tUHCI_RH_RESET = 0,\n\tUHCI_RH_SUSPENDED = 1,\n\tUHCI_RH_AUTO_STOPPED = 2,\n\tUHCI_RH_RESUMING = 3,\n\tUHCI_RH_SUSPENDING = 4,\n\tUHCI_RH_RUNNING = 5,\n\tUHCI_RH_RUNNING_NODEVS = 6,\n};\n\nstruct uhci_hcd {\n\tstruct dentry *dentry;\n\tlong unsigned int io_addr;\n\tvoid *regs;\n\tstruct dma_pool___2 *qh_pool;\n\tstruct dma_pool___2 *td_pool;\n\tstruct uhci_td *term_td;\n\tstruct uhci_qh *skelqh[11];\n\tstruct uhci_qh *next_qh;\n\tspinlock_t lock;\n\tdma_addr_t frame_dma_handle;\n\t__le32 *frame;\n\tvoid **frame_cpu;\n\tenum uhci_rh_state rh_state;\n\tlong unsigned int auto_stop_time;\n\tunsigned int frame_number;\n\tunsigned int is_stopped;\n\tunsigned int last_iso_frame;\n\tunsigned int cur_iso_frame;\n\tunsigned int scan_in_progress: 1;\n\tunsigned int need_rescan: 1;\n\tunsigned int dead: 1;\n\tunsigned int RD_enable: 1;\n\tunsigned int is_initialized: 1;\n\tunsigned int fsbr_is_on: 1;\n\tunsigned int fsbr_is_wanted: 1;\n\tunsigned int fsbr_expiring: 1;\n\tstruct timer_list fsbr_timer;\n\tunsigned int oc_low: 1;\n\tunsigned int wait_for_hp: 1;\n\tunsigned int big_endian_mmio: 1;\n\tunsigned int big_endian_desc: 1;\n\tunsigned int is_aspeed: 1;\n\tlong unsigned int port_c_suspend;\n\tlong unsigned int resuming_ports;\n\tlong unsigned int ports_timeout;\n\tstruct list_head idle_qh_list;\n\tint rh_numports;\n\twait_queue_head_t waitqh;\n\tint num_waiting;\n\tint total_load;\n\tshort int load[32];\n\tstruct clk *clk;\n\tvoid (*reset_hc)(struct uhci_hcd *);\n\tint (*check_and_reset_hc)(struct uhci_hcd *);\n\tvoid (*configure_hc)(struct uhci_hcd *);\n\tint (*resume_detect_interrupts_are_broken)(struct uhci_hcd *);\n\tint (*global_suspend_mode_is_broken)(struct uhci_hcd *);\n};\n\nstruct urb_priv___2 {\n\tstruct list_head node;\n\tstruct urb *urb;\n\tstruct uhci_qh *qh;\n\tstruct list_head td_list;\n\tunsigned int fsbr: 1;\n};\n\nstruct xhci_cap_regs {\n\t__le32 hc_capbase;\n\t__le32 hcs_params1;\n\t__le32 hcs_params2;\n\t__le32 hcs_params3;\n\t__le32 hcc_params;\n\t__le32 db_off;\n\t__le32 run_regs_off;\n\t__le32 hcc_params2;\n};\n\nstruct xhci_op_regs {\n\t__le32 command;\n\t__le32 status;\n\t__le32 page_size;\n\t__le32 reserved1;\n\t__le32 reserved2;\n\t__le32 dev_notification;\n\t__le64 cmd_ring;\n\t__le32 reserved3[4];\n\t__le64 dcbaa_ptr;\n\t__le32 config_reg;\n\t__le32 reserved4[241];\n\t__le32 port_status_base;\n\t__le32 port_power_base;\n\t__le32 port_link_base;\n\t__le32 reserved5;\n\t__le32 reserved6[1016];\n};\n\nstruct xhci_intr_reg {\n\t__le32 irq_pending;\n\t__le32 irq_control;\n\t__le32 erst_size;\n\t__le32 rsvd;\n\t__le64 erst_base;\n\t__le64 erst_dequeue;\n};\n\nstruct xhci_run_regs {\n\t__le32 microframe_index;\n\t__le32 rsvd[7];\n\tstruct xhci_intr_reg ir_set[128];\n};\n\nstruct xhci_doorbell_array {\n\t__le32 doorbell[256];\n};\n\nstruct xhci_container_ctx {\n\tunsigned int type;\n\tint size;\n\tu8 *bytes;\n\tdma_addr_t dma;\n};\n\nstruct xhci_slot_ctx {\n\t__le32 dev_info;\n\t__le32 dev_info2;\n\t__le32 tt_info;\n\t__le32 dev_state;\n\t__le32 reserved[4];\n};\n\nstruct xhci_ep_ctx {\n\t__le32 ep_info;\n\t__le32 ep_info2;\n\t__le64 deq;\n\t__le32 tx_info;\n\t__le32 reserved[3];\n};\n\nstruct xhci_input_control_ctx {\n\t__le32 drop_flags;\n\t__le32 add_flags;\n\t__le32 rsvd2[6];\n};\n\nunion xhci_trb;\n\nstruct xhci_command {\n\tstruct xhci_container_ctx *in_ctx;\n\tu32 status;\n\tint slot_id;\n\tstruct completion *completion;\n\tunion xhci_trb *command_trb;\n\tstruct list_head cmd_list;\n};\n\nstruct xhci_link_trb {\n\t__le64 segment_ptr;\n\t__le32 intr_target;\n\t__le32 control;\n};\n\nstruct xhci_transfer_event {\n\t__le64 buffer;\n\t__le32 transfer_len;\n\t__le32 flags;\n};\n\nstruct xhci_event_cmd {\n\t__le64 cmd_trb;\n\t__le32 status;\n\t__le32 flags;\n};\n\nstruct xhci_generic_trb {\n\t__le32 field[4];\n};\n\nunion xhci_trb {\n\tstruct xhci_link_trb link;\n\tstruct xhci_transfer_event trans_event;\n\tstruct xhci_event_cmd event_cmd;\n\tstruct xhci_generic_trb generic;\n};\n\nstruct xhci_stream_ctx {\n\t__le64 stream_ring;\n\t__le32 reserved[2];\n};\n\nstruct xhci_ring;\n\nstruct xhci_stream_info {\n\tstruct xhci_ring **stream_rings;\n\tunsigned int num_streams;\n\tstruct xhci_stream_ctx *stream_ctx_array;\n\tunsigned int num_stream_ctxs;\n\tdma_addr_t ctx_array_dma;\n\tstruct xarray trb_address_map;\n\tstruct xhci_command *free_streams_command;\n};\n\nenum xhci_ring_type {\n\tTYPE_CTRL = 0,\n\tTYPE_ISOC = 1,\n\tTYPE_BULK = 2,\n\tTYPE_INTR = 3,\n\tTYPE_STREAM = 4,\n\tTYPE_COMMAND = 5,\n\tTYPE_EVENT = 6,\n};\n\nstruct xhci_segment;\n\nstruct xhci_ring {\n\tstruct xhci_segment *first_seg;\n\tstruct xhci_segment *last_seg;\n\tunion xhci_trb *enqueue;\n\tstruct xhci_segment *enq_seg;\n\tunion xhci_trb *dequeue;\n\tstruct xhci_segment *deq_seg;\n\tstruct list_head td_list;\n\tu32 cycle_state;\n\tunsigned int err_count;\n\tunsigned int stream_id;\n\tunsigned int num_segs;\n\tunsigned int num_trbs_free;\n\tunsigned int num_trbs_free_temp;\n\tunsigned int bounce_buf_len;\n\tenum xhci_ring_type type;\n\tbool last_td_was_short;\n\tstruct xarray *trb_address_map;\n};\n\nstruct xhci_bw_info {\n\tunsigned int ep_interval;\n\tunsigned int mult;\n\tunsigned int num_packets;\n\tunsigned int max_packet_size;\n\tunsigned int max_esit_payload;\n\tunsigned int type;\n};\n\nstruct xhci_hcd;\n\nstruct xhci_virt_ep {\n\tstruct xhci_ring *ring;\n\tstruct xhci_stream_info *stream_info;\n\tstruct xhci_ring *new_ring;\n\tunsigned int ep_state;\n\tstruct list_head cancelled_td_list;\n\tstruct timer_list stop_cmd_timer;\n\tstruct xhci_hcd *xhci;\n\tstruct xhci_segment *queued_deq_seg;\n\tunion xhci_trb *queued_deq_ptr;\n\tbool skip;\n\tstruct xhci_bw_info bw_info;\n\tstruct list_head bw_endpoint_list;\n\tint next_frame_id;\n\tbool use_extended_tbc;\n};\n\nstruct xhci_erst_entry;\n\nstruct xhci_erst {\n\tstruct xhci_erst_entry *entries;\n\tunsigned int num_entries;\n\tdma_addr_t erst_dma_addr;\n\tunsigned int erst_size;\n};\n\nstruct s3_save {\n\tu32 command;\n\tu32 dev_nt;\n\tu64 dcbaa_ptr;\n\tu32 config_reg;\n\tu32 irq_pending;\n\tu32 irq_control;\n\tu32 erst_size;\n\tu64 erst_base;\n\tu64 erst_dequeue;\n};\n\nstruct xhci_bus_state {\n\tlong unsigned int bus_suspended;\n\tlong unsigned int next_statechange;\n\tu32 port_c_suspend;\n\tu32 suspended_ports;\n\tu32 port_remote_wakeup;\n\tlong unsigned int resume_done[31];\n\tlong unsigned int resuming_ports;\n\tlong unsigned int rexit_ports;\n\tstruct completion rexit_done[31];\n\tstruct completion u3exit_done[31];\n};\n\nstruct xhci_port;\n\nstruct xhci_hub {\n\tstruct xhci_port **ports;\n\tunsigned int num_ports;\n\tstruct usb_hcd *hcd;\n\tstruct xhci_bus_state bus_state;\n\tu8 maj_rev;\n\tu8 min_rev;\n};\n\nstruct xhci_device_context_array;\n\nstruct xhci_scratchpad;\n\nstruct xhci_virt_device;\n\nstruct xhci_root_port_bw_info;\n\nstruct xhci_port_cap;\n\nstruct xhci_hcd {\n\tstruct usb_hcd *main_hcd;\n\tstruct usb_hcd *shared_hcd;\n\tstruct xhci_cap_regs *cap_regs;\n\tstruct xhci_op_regs *op_regs;\n\tstruct xhci_run_regs *run_regs;\n\tstruct xhci_doorbell_array *dba;\n\tstruct xhci_intr_reg *ir_set;\n\t__u32 hcs_params1;\n\t__u32 hcs_params2;\n\t__u32 hcs_params3;\n\t__u32 hcc_params;\n\t__u32 hcc_params2;\n\tspinlock_t lock;\n\tu8 sbrn;\n\tu16 hci_version;\n\tu8 max_slots;\n\tu8 max_interrupters;\n\tu8 max_ports;\n\tu8 isoc_threshold;\n\tu32 imod_interval;\n\tint event_ring_max;\n\tint page_size;\n\tint page_shift;\n\tint msix_count;\n\tstruct clk *clk;\n\tstruct clk *reg_clk;\n\tstruct xhci_device_context_array *dcbaa;\n\tstruct xhci_ring *cmd_ring;\n\tunsigned int cmd_ring_state;\n\tstruct list_head cmd_list;\n\tunsigned int cmd_ring_reserved_trbs;\n\tstruct delayed_work cmd_timer;\n\tstruct completion cmd_ring_stop_completion;\n\tstruct xhci_command *current_cmd;\n\tstruct xhci_ring *event_ring;\n\tstruct xhci_erst erst;\n\tstruct xhci_scratchpad *scratchpad;\n\tstruct list_head lpm_failed_devs;\n\tstruct mutex mutex;\n\tstruct xhci_command *lpm_command;\n\tstruct xhci_virt_device *devs[256];\n\tstruct xhci_root_port_bw_info *rh_bw;\n\tstruct dma_pool___2 *device_pool;\n\tstruct dma_pool___2 *segment_pool;\n\tstruct dma_pool___2 *small_streams_pool;\n\tstruct dma_pool___2 *medium_streams_pool;\n\tunsigned int xhc_state;\n\tu32 command;\n\tstruct s3_save s3;\n\tlong long unsigned int quirks;\n\tunsigned int num_active_eps;\n\tunsigned int limit_active_eps;\n\tstruct xhci_port *hw_ports;\n\tstruct xhci_hub usb2_rhub;\n\tstruct xhci_hub usb3_rhub;\n\tunsigned int hw_lpm_support: 1;\n\tunsigned int broken_suspend: 1;\n\tu32 *ext_caps;\n\tunsigned int num_ext_caps;\n\tstruct xhci_port_cap *port_caps;\n\tunsigned int num_port_caps;\n\tstruct timer_list comp_mode_recovery_timer;\n\tu32 port_status_u0;\n\tu16 test_mode;\n\tstruct dentry *debugfs_root;\n\tstruct dentry *debugfs_slots;\n\tstruct list_head regset_list;\n\tvoid *dbc;\n\tlong unsigned int priv[0];\n};\n\nstruct xhci_segment {\n\tunion xhci_trb *trbs;\n\tstruct xhci_segment *next;\n\tdma_addr_t dma;\n\tdma_addr_t bounce_dma;\n\tvoid *bounce_buf;\n\tunsigned int bounce_offs;\n\tunsigned int bounce_len;\n};\n\nenum xhci_overhead_type {\n\tLS_OVERHEAD_TYPE = 0,\n\tFS_OVERHEAD_TYPE = 1,\n\tHS_OVERHEAD_TYPE = 2,\n};\n\nstruct xhci_interval_bw {\n\tunsigned int num_packets;\n\tstruct list_head endpoints;\n\tunsigned int overhead[3];\n};\n\nstruct xhci_interval_bw_table {\n\tunsigned int interval0_esit_payload;\n\tstruct xhci_interval_bw interval_bw[16];\n\tunsigned int bw_used;\n\tunsigned int ss_bw_in;\n\tunsigned int ss_bw_out;\n};\n\nstruct xhci_tt_bw_info;\n\nstruct xhci_virt_device {\n\tstruct usb_device *udev;\n\tstruct xhci_container_ctx *out_ctx;\n\tstruct xhci_container_ctx *in_ctx;\n\tstruct xhci_virt_ep eps[31];\n\tu8 fake_port;\n\tu8 real_port;\n\tstruct xhci_interval_bw_table *bw_table;\n\tstruct xhci_tt_bw_info *tt_info;\n\tlong unsigned int flags;\n\tu16 current_mel;\n\tvoid *debugfs_private;\n};\n\nstruct xhci_tt_bw_info {\n\tstruct list_head tt_list;\n\tint slot_id;\n\tint ttport;\n\tstruct xhci_interval_bw_table bw_table;\n\tint active_eps;\n};\n\nstruct xhci_root_port_bw_info {\n\tstruct list_head tts;\n\tunsigned int num_active_tts;\n\tstruct xhci_interval_bw_table bw_table;\n};\n\nstruct xhci_device_context_array {\n\t__le64 dev_context_ptrs[256];\n\tdma_addr_t dma;\n};\n\nenum xhci_setup_dev {\n\tSETUP_CONTEXT_ONLY = 0,\n\tSETUP_CONTEXT_ADDRESS = 1,\n};\n\nstruct xhci_td {\n\tstruct list_head td_list;\n\tstruct list_head cancelled_td_list;\n\tstruct urb *urb;\n\tstruct xhci_segment *start_seg;\n\tunion xhci_trb *first_trb;\n\tunion xhci_trb *last_trb;\n\tstruct xhci_segment *bounce_seg;\n\tbool urb_length_set;\n};\n\nstruct xhci_dequeue_state {\n\tstruct xhci_segment *new_deq_seg;\n\tunion xhci_trb *new_deq_ptr;\n\tint new_cycle_state;\n\tunsigned int stream_id;\n};\n\nstruct xhci_erst_entry {\n\t__le64 seg_addr;\n\t__le32 seg_size;\n\t__le32 rsvd;\n};\n\nstruct xhci_scratchpad {\n\tu64 *sp_array;\n\tdma_addr_t sp_dma;\n\tvoid **sp_buffers;\n};\n\nstruct urb_priv___3 {\n\tint num_tds;\n\tint num_tds_done;\n\tstruct xhci_td td[0];\n};\n\nstruct xhci_port_cap {\n\tu32 *psi;\n\tu8 psi_count;\n\tu8 psi_uid_count;\n\tu8 maj_rev;\n\tu8 min_rev;\n};\n\nstruct xhci_port {\n\t__le32 *addr;\n\tint hw_portnum;\n\tint hcd_portnum;\n\tstruct xhci_hub *rhub;\n\tstruct xhci_port_cap *port_cap;\n};\n\nstruct xhci_driver_overrides {\n\tsize_t extra_priv_size;\n\tint (*reset)(struct usb_hcd *);\n\tint (*start)(struct usb_hcd *);\n};\n\ntypedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);\n\nenum xhci_ep_reset_type {\n\tEP_HARD_RESET = 0,\n\tEP_SOFT_RESET = 1,\n};\n\nstruct kfifo {\n\tunion {\n\t\tstruct __kfifo kfifo;\n\t\tunsigned char *type;\n\t\tconst unsigned char *const_type;\n\t\tchar (*rectype)[0];\n\t\tvoid *ptr;\n\t\tconst void *ptr_const;\n\t};\n\tunsigned char buf[0];\n};\n\nstruct dbc_regs {\n\t__le32 capability;\n\t__le32 doorbell;\n\t__le32 ersts;\n\t__le32 __reserved_0;\n\t__le64 erstba;\n\t__le64 erdp;\n\t__le32 control;\n\t__le32 status;\n\t__le32 portsc;\n\t__le32 __reserved_1;\n\t__le64 dccp;\n\t__le32 devinfo1;\n\t__le32 devinfo2;\n};\n\nstruct dbc_str_descs {\n\tchar string0[64];\n\tchar manufacturer[64];\n\tchar product[64];\n\tchar serial[64];\n};\n\nenum dbc_state {\n\tDS_DISABLED = 0,\n\tDS_INITIALIZED = 1,\n\tDS_ENABLED = 2,\n\tDS_CONNECTED = 3,\n\tDS_CONFIGURED = 4,\n\tDS_STALLED = 5,\n};\n\nstruct dbc_ep;\n\nstruct dbc_request {\n\tvoid *buf;\n\tunsigned int length;\n\tdma_addr_t dma;\n\tvoid (*complete)(struct xhci_hcd *, struct dbc_request *);\n\tstruct list_head list_pool;\n\tint status;\n\tunsigned int actual;\n\tstruct dbc_ep *dep;\n\tstruct list_head list_pending;\n\tdma_addr_t trb_dma;\n\tunion xhci_trb *trb;\n\tunsigned int direction: 1;\n};\n\nstruct xhci_dbc;\n\nstruct dbc_ep {\n\tstruct xhci_dbc *dbc;\n\tstruct list_head list_pending;\n\tstruct xhci_ring *ring;\n\tunsigned int direction: 1;\n};\n\nstruct dbc_port {\n\tstruct tty_port port;\n\tspinlock_t port_lock;\n\tstruct list_head read_pool;\n\tstruct list_head read_queue;\n\tunsigned int n_read;\n\tstruct tasklet_struct push;\n\tstruct list_head write_pool;\n\tstruct kfifo write_fifo;\n\tbool registered;\n\tstruct dbc_ep *in;\n\tstruct dbc_ep *out;\n};\n\nstruct xhci_dbc {\n\tspinlock_t lock;\n\tstruct xhci_hcd *xhci;\n\tstruct dbc_regs *regs;\n\tstruct xhci_ring *ring_evt;\n\tstruct xhci_ring *ring_in;\n\tstruct xhci_ring *ring_out;\n\tstruct xhci_erst erst;\n\tstruct xhci_container_ctx *ctx;\n\tstruct dbc_str_descs *string;\n\tdma_addr_t string_dma;\n\tsize_t string_size;\n\tenum dbc_state state;\n\tstruct delayed_work event_work;\n\tunsigned int resume_required: 1;\n\tstruct dbc_ep eps[2];\n\tstruct dbc_port port;\n};\n\nstruct trace_event_raw_xhci_log_msg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ctx {\n\tstruct trace_entry ent;\n\tint ctx_64;\n\tunsigned int ctx_type;\n\tdma_addr_t ctx_dma;\n\tu8 *ctx_va;\n\tunsigned int ctx_ep_num;\n\tint slot_id;\n\tu32 __data_loc_ctx_data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_trb {\n\tstruct trace_entry ent;\n\tu32 type;\n\tu32 field0;\n\tu32 field1;\n\tu32 field2;\n\tu32 field3;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_free_virt_dev {\n\tstruct trace_entry ent;\n\tvoid *vdev;\n\tlong long unsigned int out_ctx;\n\tlong long unsigned int in_ctx;\n\tu8 fake_port;\n\tu8 real_port;\n\tu16 current_mel;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_virt_dev {\n\tstruct trace_entry ent;\n\tvoid *vdev;\n\tlong long unsigned int out_ctx;\n\tlong long unsigned int in_ctx;\n\tint devnum;\n\tint state;\n\tint speed;\n\tu8 portnum;\n\tu8 level;\n\tint slot_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_urb {\n\tstruct trace_entry ent;\n\tvoid *urb;\n\tunsigned int pipe;\n\tunsigned int stream;\n\tint status;\n\tunsigned int flags;\n\tint num_mapped_sgs;\n\tint num_sgs;\n\tint length;\n\tint actual;\n\tint epnum;\n\tint dir_in;\n\tint type;\n\tint slot_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ep_ctx {\n\tstruct trace_entry ent;\n\tu32 info;\n\tu32 info2;\n\tu64 deq;\n\tu32 tx_info;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_slot_ctx {\n\tstruct trace_entry ent;\n\tu32 info;\n\tu32 info2;\n\tu32 tt_info;\n\tu32 state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ctrl_ctx {\n\tstruct trace_entry ent;\n\tu32 drop;\n\tu32 add;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_ring {\n\tstruct trace_entry ent;\n\tu32 type;\n\tvoid *ring;\n\tdma_addr_t enq;\n\tdma_addr_t deq;\n\tdma_addr_t enq_seg;\n\tdma_addr_t deq_seg;\n\tunsigned int num_segs;\n\tunsigned int stream_id;\n\tunsigned int cycle_state;\n\tunsigned int num_trbs_free;\n\tunsigned int bounce_buf_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_portsc {\n\tstruct trace_entry ent;\n\tu32 portnum;\n\tu32 portsc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_log_doorbell {\n\tstruct trace_entry ent;\n\tu32 slot;\n\tu32 doorbell;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xhci_dbc_log_request {\n\tstruct trace_entry ent;\n\tstruct dbc_request *req;\n\tbool dir;\n\tunsigned int actual;\n\tunsigned int length;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_xhci_log_msg {\n\tu32 msg;\n};\n\nstruct trace_event_data_offsets_xhci_log_ctx {\n\tu32 ctx_data;\n};\n\nstruct trace_event_data_offsets_xhci_log_trb {};\n\nstruct trace_event_data_offsets_xhci_log_free_virt_dev {};\n\nstruct trace_event_data_offsets_xhci_log_virt_dev {};\n\nstruct trace_event_data_offsets_xhci_log_urb {};\n\nstruct trace_event_data_offsets_xhci_log_ep_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_slot_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_ctrl_ctx {};\n\nstruct trace_event_data_offsets_xhci_log_ring {};\n\nstruct trace_event_data_offsets_xhci_log_portsc {};\n\nstruct trace_event_data_offsets_xhci_log_doorbell {};\n\nstruct trace_event_data_offsets_xhci_dbc_log_request {};\n\ntypedef void (*btf_trace_xhci_dbg_address)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_context_change)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_quirks)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_reset_ep)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_cancel_urb)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_init)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_dbg_ring_expansion)(void *, struct va_format *);\n\ntypedef void (*btf_trace_xhci_address_ctx)(void *, struct xhci_hcd *, struct xhci_container_ctx *, unsigned int);\n\ntypedef void (*btf_trace_xhci_handle_event)(void *, struct xhci_ring *, struct xhci_generic_trb *);\n\ntypedef void (*btf_trace_xhci_handle_command)(void *, struct xhci_ring *, struct xhci_generic_trb *);\n\ntypedef void (*btf_trace_xhci_handle_transfer)(void *, struct xhci_ring *, struct xhci_generic_trb *);\n\ntypedef void (*btf_trace_xhci_queue_trb)(void *, struct xhci_ring *, struct xhci_generic_trb *);\n\ntypedef void (*btf_trace_xhci_dbc_handle_event)(void *, struct xhci_ring *, struct xhci_generic_trb *);\n\ntypedef void (*btf_trace_xhci_dbc_handle_transfer)(void *, struct xhci_ring *, struct xhci_generic_trb *);\n\ntypedef void (*btf_trace_xhci_dbc_gadget_ep_queue)(void *, struct xhci_ring *, struct xhci_generic_trb *);\n\ntypedef void (*btf_trace_xhci_free_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_alloc_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_setup_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_setup_addressable_virt_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_stop_device)(void *, struct xhci_virt_device *);\n\ntypedef void (*btf_trace_xhci_urb_enqueue)(void *, struct urb *);\n\ntypedef void (*btf_trace_xhci_urb_giveback)(void *, struct urb *);\n\ntypedef void (*btf_trace_xhci_urb_dequeue)(void *, struct urb *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_stop_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_set_deq_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_reset_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_config_ep)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_add_endpoint)(void *, struct xhci_ep_ctx *);\n\ntypedef void (*btf_trace_xhci_alloc_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_free_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_disable_slot)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_discover_or_reset_device)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_setup_device_slot)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_addr_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_reset_dev)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_handle_cmd_set_deq)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_configure_endpoint)(void *, struct xhci_slot_ctx *);\n\ntypedef void (*btf_trace_xhci_address_ctrl_ctx)(void *, struct xhci_input_control_ctx *);\n\ntypedef void (*btf_trace_xhci_configure_endpoint_ctrl_ctx)(void *, struct xhci_input_control_ctx *);\n\ntypedef void (*btf_trace_xhci_ring_alloc)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_ring_free)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_ring_expansion)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_inc_enq)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_inc_deq)(void *, struct xhci_ring *);\n\ntypedef void (*btf_trace_xhci_handle_port_status)(void *, u32, u32);\n\ntypedef void (*btf_trace_xhci_get_port_status)(void *, u32, u32);\n\ntypedef void (*btf_trace_xhci_hub_status_data)(void *, u32, u32);\n\ntypedef void (*btf_trace_xhci_ring_ep_doorbell)(void *, u32, u32);\n\ntypedef void (*btf_trace_xhci_ring_host_doorbell)(void *, u32, u32);\n\ntypedef void (*btf_trace_xhci_dbc_alloc_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_free_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_queue_request)(void *, struct dbc_request *);\n\ntypedef void (*btf_trace_xhci_dbc_giveback_request)(void *, struct dbc_request *);\n\nstruct xhci_regset {\n\tchar name[32];\n\tstruct debugfs_regset32 regset;\n\tsize_t nregs;\n\tstruct list_head list;\n};\n\nstruct xhci_file_map {\n\tconst char *name;\n\tint (*show)(struct seq_file *, void *);\n};\n\nstruct xhci_ep_priv {\n\tchar name[32];\n\tstruct dentry *root;\n};\n\nstruct xhci_slot_priv {\n\tchar name[32];\n\tstruct dentry *root;\n\tstruct xhci_ep_priv *eps[31];\n\tstruct xhci_virt_device *dev;\n};\n\nstruct xhci_driver_data {\n\tu64 quirks;\n\tconst char *firmware;\n};\n\nstruct usblp {\n\tstruct usb_device *dev;\n\tstruct mutex wmut;\n\tstruct mutex mut;\n\tspinlock_t lock;\n\tchar *readbuf;\n\tchar *statusbuf;\n\tstruct usb_anchor urbs;\n\twait_queue_head_t rwait;\n\twait_queue_head_t wwait;\n\tint readcount;\n\tint ifnum;\n\tstruct usb_interface *intf;\n\tstruct {\n\t\tint alt_setting;\n\t\tstruct usb_endpoint_descriptor *epwrite;\n\t\tstruct usb_endpoint_descriptor *epread;\n\t} protocol[4];\n\tint current_protocol;\n\tint minor;\n\tint wcomplete;\n\tint rcomplete;\n\tint wstatus;\n\tint rstatus;\n\tunsigned int quirks;\n\tunsigned int flags;\n\tunsigned char used;\n\tunsigned char present;\n\tunsigned char bidir;\n\tunsigned char no_paper;\n\tunsigned char *device_id_string;\n};\n\nstruct quirk_printer_struct {\n\t__u16 vendorId;\n\t__u16 productId;\n\tunsigned int quirks;\n};\n\nenum {\n\tUS_FL_SINGLE_LUN = 1,\n\tUS_FL_NEED_OVERRIDE = 2,\n\tUS_FL_SCM_MULT_TARG = 4,\n\tUS_FL_FIX_INQUIRY = 8,\n\tUS_FL_FIX_CAPACITY = 16,\n\tUS_FL_IGNORE_RESIDUE = 32,\n\tUS_FL_BULK32 = 64,\n\tUS_FL_NOT_LOCKABLE = 128,\n\tUS_FL_GO_SLOW = 256,\n\tUS_FL_NO_WP_DETECT = 512,\n\tUS_FL_MAX_SECTORS_64 = 1024,\n\tUS_FL_IGNORE_DEVICE = 2048,\n\tUS_FL_CAPACITY_HEURISTICS = 4096,\n\tUS_FL_MAX_SECTORS_MIN = 8192,\n\tUS_FL_BULK_IGNORE_TAG = 16384,\n\tUS_FL_SANE_SENSE = 32768,\n\tUS_FL_CAPACITY_OK = 65536,\n\tUS_FL_BAD_SENSE = 131072,\n\tUS_FL_NO_READ_DISC_INFO = 262144,\n\tUS_FL_NO_READ_CAPACITY_16 = 524288,\n\tUS_FL_INITIAL_READ10 = 1048576,\n\tUS_FL_WRITE_CACHE = 2097152,\n\tUS_FL_NEEDS_CAP16 = 4194304,\n\tUS_FL_IGNORE_UAS = 8388608,\n\tUS_FL_BROKEN_FUA = 16777216,\n\tUS_FL_NO_ATA_1X = 33554432,\n\tUS_FL_NO_REPORT_OPCODES = 67108864,\n\tUS_FL_MAX_SECTORS_240 = 134217728,\n\tUS_FL_NO_REPORT_LUNS = 268435456,\n\tUS_FL_ALWAYS_SYNC = 536870912,\n};\n\nstruct us_data;\n\nstruct us_unusual_dev {\n\tconst char *vendorName;\n\tconst char *productName;\n\t__u8 useProtocol;\n\t__u8 useTransport;\n\tint (*initFunction)(struct us_data *);\n};\n\ntypedef int (*trans_cmnd)(struct scsi_cmnd *, struct us_data *);\n\ntypedef int (*trans_reset)(struct us_data *);\n\ntypedef void (*proto_cmnd)(struct scsi_cmnd *, struct us_data *);\n\ntypedef void (*extra_data_destructor)(void *);\n\ntypedef void (*pm_hook)(struct us_data *, int);\n\nstruct us_data {\n\tstruct mutex dev_mutex;\n\tstruct usb_device *pusb_dev;\n\tstruct usb_interface *pusb_intf;\n\tconst struct us_unusual_dev *unusual_dev;\n\tlong unsigned int fflags;\n\tlong unsigned int dflags;\n\tunsigned int send_bulk_pipe;\n\tunsigned int recv_bulk_pipe;\n\tunsigned int send_ctrl_pipe;\n\tunsigned int recv_ctrl_pipe;\n\tunsigned int recv_intr_pipe;\n\tchar *transport_name;\n\tchar *protocol_name;\n\t__le32 bcs_signature;\n\tu8 subclass;\n\tu8 protocol;\n\tu8 max_lun;\n\tu8 ifnum;\n\tu8 ep_bInterval;\n\ttrans_cmnd transport;\n\ttrans_reset transport_reset;\n\tproto_cmnd proto_handler;\n\tstruct scsi_cmnd *srb;\n\tunsigned int tag;\n\tchar scsi_name[32];\n\tstruct urb *current_urb;\n\tstruct usb_ctrlrequest *cr;\n\tstruct usb_sg_request current_sg;\n\tunsigned char *iobuf;\n\tdma_addr_t iobuf_dma;\n\tstruct task_struct *ctl_thread;\n\tstruct completion cmnd_ready;\n\tstruct completion notify;\n\twait_queue_head_t delay_wait;\n\tstruct delayed_work scan_dwork;\n\tvoid *extra;\n\textra_data_destructor extra_destructor;\n\tpm_hook suspend_resume_hook;\n\tint use_last_sector_hacks;\n\tint last_sector_retries;\n};\n\nenum xfer_buf_dir {\n\tTO_XFER_BUF = 0,\n\tFROM_XFER_BUF = 1,\n};\n\nstruct bulk_cb_wrap {\n\t__le32 Signature;\n\t__u32 Tag;\n\t__le32 DataTransferLength;\n\t__u8 Flags;\n\t__u8 Lun;\n\t__u8 Length;\n\t__u8 CDB[16];\n};\n\nstruct bulk_cs_wrap {\n\t__le32 Signature;\n\t__u32 Tag;\n\t__le32 Residue;\n\t__u8 Status;\n};\n\nstruct swoc_info {\n\t__u8 rev;\n\t__u8 reserved[8];\n\t__u16 LinuxSKU;\n\t__u16 LinuxVer;\n\t__u8 reserved2[47];\n} __attribute__((packed));\n\nstruct ignore_entry {\n\tu16 vid;\n\tu16 pid;\n\tu16 bcdmin;\n\tu16 bcdmax;\n};\n\nstruct usb_debug_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__u8 bDebugInEndpoint;\n\t__u8 bDebugOutEndpoint;\n};\n\nstruct ehci_dev {\n\tu32 bus;\n\tu32 slot;\n\tu32 func;\n};\n\ntypedef void (*set_debug_port_t)(int);\n\nstruct usb_hcd___2;\n\nstruct serio_device_id {\n\t__u8 type;\n\t__u8 extra;\n\t__u8 id;\n\t__u8 proto;\n};\n\nstruct serio_driver;\n\nstruct serio {\n\tvoid *port_data;\n\tchar name[32];\n\tchar phys[32];\n\tchar firmware_id[128];\n\tbool manual_bind;\n\tstruct serio_device_id id;\n\tspinlock_t lock;\n\tint (*write)(struct serio *, unsigned char);\n\tint (*open)(struct serio *);\n\tvoid (*close)(struct serio *);\n\tint (*start)(struct serio *);\n\tvoid (*stop)(struct serio *);\n\tstruct serio *parent;\n\tstruct list_head child_node;\n\tstruct list_head children;\n\tunsigned int depth;\n\tstruct serio_driver *drv;\n\tstruct mutex drv_mutex;\n\tstruct device dev;\n\tstruct list_head node;\n\tstruct mutex *ps2_cmd_mutex;\n};\n\nstruct serio_driver {\n\tconst char *description;\n\tconst struct serio_device_id *id_table;\n\tbool manual_bind;\n\tvoid (*write_wakeup)(struct serio *);\n\tirqreturn_t (*interrupt)(struct serio *, unsigned char, unsigned int);\n\tint (*connect)(struct serio *, struct serio_driver *);\n\tint (*reconnect)(struct serio *);\n\tint (*fast_reconnect)(struct serio *);\n\tvoid (*disconnect)(struct serio *);\n\tvoid (*cleanup)(struct serio *);\n\tstruct device_driver driver;\n};\n\nenum serio_event_type {\n\tSERIO_RESCAN_PORT = 0,\n\tSERIO_RECONNECT_PORT = 1,\n\tSERIO_RECONNECT_SUBTREE = 2,\n\tSERIO_REGISTER_PORT = 3,\n\tSERIO_ATTACH_DRIVER = 4,\n};\n\nstruct serio_event {\n\tenum serio_event_type type;\n\tvoid *object;\n\tstruct module *owner;\n\tstruct list_head node;\n};\n\nenum i8042_controller_reset_mode {\n\tI8042_RESET_NEVER = 0,\n\tI8042_RESET_ALWAYS = 1,\n\tI8042_RESET_ON_S2RAM = 2,\n};\n\nstruct i8042_port {\n\tstruct serio *serio;\n\tint irq;\n\tbool exists;\n\tbool driver_bound;\n\tsigned char mux;\n};\n\nstruct serport {\n\tstruct tty_struct *tty;\n\twait_queue_head_t wait;\n\tstruct serio *serio;\n\tstruct serio_device_id id;\n\tspinlock_t lock;\n\tlong unsigned int flags;\n};\n\nstruct ps2dev {\n\tstruct serio *serio;\n\tstruct mutex cmd_mutex;\n\twait_queue_head_t wait;\n\tlong unsigned int flags;\n\tu8 cmdbuf[8];\n\tu8 cmdcnt;\n\tu8 nak;\n};\n\nstruct input_mt_slot {\n\tint abs[14];\n\tunsigned int frame;\n\tunsigned int key;\n};\n\nstruct input_mt {\n\tint trkid;\n\tint num_slots;\n\tint slot;\n\tunsigned int flags;\n\tunsigned int frame;\n\tint *red;\n\tstruct input_mt_slot slots[0];\n};\n\nunion input_seq_state {\n\tstruct {\n\t\tshort unsigned int pos;\n\t\tbool mutex_acquired;\n\t};\n\tvoid *p;\n};\n\nstruct input_devres {\n\tstruct input_dev *input;\n};\n\nstruct input_event {\n\t__kernel_ulong_t __sec;\n\t__kernel_ulong_t __usec;\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct input_event_compat {\n\tcompat_ulong_t sec;\n\tcompat_ulong_t usec;\n\t__u16 type;\n\t__u16 code;\n\t__s32 value;\n};\n\nstruct ff_periodic_effect_compat {\n\t__u16 waveform;\n\t__u16 period;\n\t__s16 magnitude;\n\t__s16 offset;\n\t__u16 phase;\n\tstruct ff_envelope envelope;\n\t__u32 custom_len;\n\tcompat_uptr_t custom_data;\n};\n\nstruct ff_effect_compat {\n\t__u16 type;\n\t__s16 id;\n\t__u16 direction;\n\tstruct ff_trigger trigger;\n\tstruct ff_replay replay;\n\tunion {\n\t\tstruct ff_constant_effect constant;\n\t\tstruct ff_ramp_effect ramp;\n\t\tstruct ff_periodic_effect_compat periodic;\n\t\tstruct ff_condition_effect condition[2];\n\t\tstruct ff_rumble_effect rumble;\n\t} u;\n};\n\nstruct input_mt_pos {\n\ts16 x;\n\ts16 y;\n};\n\nstruct input_dev_poller {\n\tvoid (*poll)(struct input_dev *);\n\tunsigned int poll_interval;\n\tunsigned int poll_interval_max;\n\tunsigned int poll_interval_min;\n\tstruct input_dev *input;\n\tstruct delayed_work work;\n};\n\nstruct ml_effect_state {\n\tstruct ff_effect *effect;\n\tlong unsigned int flags;\n\tint count;\n\tlong unsigned int play_at;\n\tlong unsigned int stop_at;\n\tlong unsigned int adj_at;\n};\n\nstruct ml_device {\n\tvoid *private;\n\tstruct ml_effect_state states[16];\n\tint gain;\n\tstruct timer_list timer;\n\tstruct input_dev *dev;\n\tint (*play_effect)(struct input_dev *, void *, struct ff_effect *);\n};\n\nstruct input_polled_dev {\n\tvoid *private;\n\tvoid (*open)(struct input_polled_dev *);\n\tvoid (*close)(struct input_polled_dev *);\n\tvoid (*poll)(struct input_polled_dev *);\n\tunsigned int poll_interval;\n\tunsigned int poll_interval_max;\n\tunsigned int poll_interval_min;\n\tstruct input_dev *input;\n\tstruct delayed_work work;\n\tbool devres_managed;\n};\n\nstruct input_polled_devres {\n\tstruct input_polled_dev *polldev;\n};\n\nstruct key_entry {\n\tint type;\n\tu32 code;\n\tunion {\n\t\tu16 keycode;\n\t\tstruct {\n\t\t\tu8 code;\n\t\t\tu8 value;\n\t\t} sw;\n\t};\n};\n\nstruct input_led {\n\tstruct led_classdev cdev;\n\tstruct input_handle *handle;\n\tunsigned int code;\n};\n\nstruct input_leds {\n\tstruct input_handle handle;\n\tunsigned int num_leds;\n\tstruct input_led leds[0];\n};\n\nstruct input_mask {\n\t__u32 type;\n\t__u32 codes_size;\n\t__u64 codes_ptr;\n};\n\nstruct evdev_client;\n\nstruct evdev {\n\tint open;\n\tstruct input_handle handle;\n\twait_queue_head_t wait;\n\tstruct evdev_client *grab;\n\tstruct list_head client_list;\n\tspinlock_t client_lock;\n\tstruct mutex mutex;\n\tstruct device dev;\n\tstruct cdev cdev;\n\tbool exist;\n};\n\nstruct evdev_client {\n\tunsigned int head;\n\tunsigned int tail;\n\tunsigned int packet_head;\n\tspinlock_t buffer_lock;\n\tstruct fasync_struct *fasync;\n\tstruct evdev *evdev;\n\tstruct list_head node;\n\tenum input_clock_type clk_type;\n\tbool revoked;\n\tlong unsigned int *evmasks[32];\n\tunsigned int bufsize;\n\tstruct input_event buffer[0];\n};\n\nstruct atkbd {\n\tstruct ps2dev ps2dev;\n\tstruct input_dev *dev;\n\tchar name[64];\n\tchar phys[32];\n\tshort unsigned int id;\n\tshort unsigned int keycode[512];\n\tlong unsigned int force_release_mask[8];\n\tunsigned char set;\n\tbool translated;\n\tbool extra;\n\tbool write;\n\tbool softrepeat;\n\tbool softraw;\n\tbool scroll;\n\tbool enabled;\n\tunsigned char emul;\n\tbool resend;\n\tbool release;\n\tlong unsigned int xl_bit;\n\tunsigned int last;\n\tlong unsigned int time;\n\tlong unsigned int err_count;\n\tstruct delayed_work event_work;\n\tlong unsigned int event_jiffies;\n\tlong unsigned int event_mask;\n\tstruct mutex mutex;\n\tu32 function_row_physmap[24];\n\tint num_function_row_keys;\n};\n\nenum psmouse_state {\n\tPSMOUSE_IGNORE = 0,\n\tPSMOUSE_INITIALIZING = 1,\n\tPSMOUSE_RESYNCING = 2,\n\tPSMOUSE_CMD_MODE = 3,\n\tPSMOUSE_ACTIVATED = 4,\n};\n\ntypedef enum {\n\tPSMOUSE_BAD_DATA = 0,\n\tPSMOUSE_GOOD_DATA = 1,\n\tPSMOUSE_FULL_PACKET = 2,\n} psmouse_ret_t;\n\nenum psmouse_scale {\n\tPSMOUSE_SCALE11 = 0,\n\tPSMOUSE_SCALE21 = 1,\n};\n\nenum psmouse_type {\n\tPSMOUSE_NONE = 0,\n\tPSMOUSE_PS2 = 1,\n\tPSMOUSE_PS2PP = 2,\n\tPSMOUSE_THINKPS = 3,\n\tPSMOUSE_GENPS = 4,\n\tPSMOUSE_IMPS = 5,\n\tPSMOUSE_IMEX = 6,\n\tPSMOUSE_SYNAPTICS = 7,\n\tPSMOUSE_ALPS = 8,\n\tPSMOUSE_LIFEBOOK = 9,\n\tPSMOUSE_TRACKPOINT = 10,\n\tPSMOUSE_TOUCHKIT_PS2 = 11,\n\tPSMOUSE_CORTRON = 12,\n\tPSMOUSE_HGPK = 13,\n\tPSMOUSE_ELANTECH = 14,\n\tPSMOUSE_FSP = 15,\n\tPSMOUSE_SYNAPTICS_RELATIVE = 16,\n\tPSMOUSE_CYPRESS = 17,\n\tPSMOUSE_FOCALTECH = 18,\n\tPSMOUSE_VMMOUSE = 19,\n\tPSMOUSE_BYD = 20,\n\tPSMOUSE_SYNAPTICS_SMBUS = 21,\n\tPSMOUSE_ELANTECH_SMBUS = 22,\n\tPSMOUSE_AUTO = 23,\n};\n\nstruct psmouse;\n\nstruct psmouse_protocol {\n\tenum psmouse_type type;\n\tbool maxproto;\n\tbool ignore_parity;\n\tbool try_passthru;\n\tbool smbus_companion;\n\tconst char *name;\n\tconst char *alias;\n\tint (*detect)(struct psmouse *, bool);\n\tint (*init)(struct psmouse *);\n};\n\nstruct psmouse {\n\tvoid *private;\n\tstruct input_dev *dev;\n\tstruct ps2dev ps2dev;\n\tstruct delayed_work resync_work;\n\tconst char *vendor;\n\tconst char *name;\n\tconst struct psmouse_protocol *protocol;\n\tunsigned char packet[8];\n\tunsigned char badbyte;\n\tunsigned char pktcnt;\n\tunsigned char pktsize;\n\tunsigned char oob_data_type;\n\tunsigned char extra_buttons;\n\tbool acks_disable_command;\n\tunsigned int model;\n\tlong unsigned int last;\n\tlong unsigned int out_of_sync_cnt;\n\tlong unsigned int num_resyncs;\n\tenum psmouse_state state;\n\tchar devname[64];\n\tchar phys[32];\n\tunsigned int rate;\n\tunsigned int resolution;\n\tunsigned int resetafter;\n\tunsigned int resync_time;\n\tbool smartscroll;\n\tpsmouse_ret_t (*protocol_handler)(struct psmouse *);\n\tvoid (*set_rate)(struct psmouse *, unsigned int);\n\tvoid (*set_resolution)(struct psmouse *, unsigned int);\n\tvoid (*set_scale)(struct psmouse *, enum psmouse_scale);\n\tint (*reconnect)(struct psmouse *);\n\tint (*fast_reconnect)(struct psmouse *);\n\tvoid (*disconnect)(struct psmouse *);\n\tvoid (*cleanup)(struct psmouse *);\n\tint (*poll)(struct psmouse *);\n\tvoid (*pt_activate)(struct psmouse *);\n\tvoid (*pt_deactivate)(struct psmouse *);\n};\n\nstruct psmouse_attribute {\n\tstruct device_attribute dattr;\n\tvoid *data;\n\tssize_t (*show)(struct psmouse *, void *, char *);\n\tssize_t (*set)(struct psmouse *, void *, const char *, size_t);\n\tbool protect;\n};\n\nstruct rmi_2d_axis_alignment {\n\tbool swap_axes;\n\tbool flip_x;\n\tbool flip_y;\n\tu16 clip_x_low;\n\tu16 clip_y_low;\n\tu16 clip_x_high;\n\tu16 clip_y_high;\n\tu16 offset_x;\n\tu16 offset_y;\n\tu8 delta_x_threshold;\n\tu8 delta_y_threshold;\n};\n\nenum rmi_sensor_type {\n\trmi_sensor_default = 0,\n\trmi_sensor_touchscreen = 1,\n\trmi_sensor_touchpad = 2,\n};\n\nstruct rmi_2d_sensor_platform_data {\n\tstruct rmi_2d_axis_alignment axis_align;\n\tenum rmi_sensor_type sensor_type;\n\tint x_mm;\n\tint y_mm;\n\tint disable_report_mask;\n\tu16 rezero_wait;\n\tbool topbuttonpad;\n\tbool kernel_tracking;\n\tint dmax;\n\tint dribble;\n\tint palm_detect;\n};\n\nstruct rmi_f30_data {\n\tbool buttonpad;\n\tbool trackstick_buttons;\n\tbool disable;\n};\n\nenum rmi_reg_state {\n\tRMI_REG_STATE_DEFAULT = 0,\n\tRMI_REG_STATE_OFF = 1,\n\tRMI_REG_STATE_ON = 2,\n};\n\nstruct rmi_f01_power_management {\n\tenum rmi_reg_state nosleep;\n\tu8 wakeup_threshold;\n\tu8 doze_holdoff;\n\tu8 doze_interval;\n};\n\nstruct rmi_device_platform_data_spi {\n\tu32 block_delay_us;\n\tu32 split_read_block_delay_us;\n\tu32 read_delay_us;\n\tu32 write_delay_us;\n\tu32 split_read_byte_delay_us;\n\tu32 pre_delay_us;\n\tu32 post_delay_us;\n\tu8 bits_per_word;\n\tu16 mode;\n\tvoid *cs_assert_data;\n\tint (*cs_assert)(const void *, const bool);\n};\n\nstruct rmi_device_platform_data {\n\tint reset_delay_ms;\n\tint irq;\n\tstruct rmi_device_platform_data_spi spi_data;\n\tstruct rmi_2d_sensor_platform_data sensor_pdata;\n\tstruct rmi_f01_power_management power_management;\n\tstruct rmi_f30_data f30_data;\n};\n\nenum synaptics_pkt_type {\n\tSYN_NEWABS = 0,\n\tSYN_NEWABS_STRICT = 1,\n\tSYN_NEWABS_RELAXED = 2,\n\tSYN_OLDABS = 3,\n};\n\nstruct synaptics_hw_state {\n\tint x;\n\tint y;\n\tint z;\n\tint w;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int up: 1;\n\tunsigned int down: 1;\n\tu8 ext_buttons;\n\ts8 scroll;\n};\n\nstruct synaptics_device_info {\n\tu32 model_id;\n\tu32 firmware_id;\n\tu32 board_id;\n\tu32 capabilities;\n\tu32 ext_cap;\n\tu32 ext_cap_0c;\n\tu32 ext_cap_10;\n\tu32 identity;\n\tu32 x_res;\n\tu32 y_res;\n\tu32 x_max;\n\tu32 y_max;\n\tu32 x_min;\n\tu32 y_min;\n};\n\nstruct synaptics_data {\n\tstruct synaptics_device_info info;\n\tenum synaptics_pkt_type pkt_type;\n\tu8 mode;\n\tint scroll;\n\tbool absolute_mode;\n\tbool disable_gesture;\n\tstruct serio *pt_port;\n\tstruct synaptics_hw_state agm;\n\tunsigned int agm_count;\n\tlong unsigned int press_start;\n\tbool press;\n\tbool report_press;\n\tbool is_forcepad;\n};\n\nstruct min_max_quirk {\n\tconst char * const *pnp_ids;\n\tstruct {\n\t\tu32 min;\n\t\tu32 max;\n\t} board_id;\n\tu32 x_min;\n\tu32 x_max;\n\tu32 y_min;\n\tu32 y_max;\n};\n\nenum {\n\tSYNAPTICS_INTERTOUCH_NOT_SET = 4294967295,\n\tSYNAPTICS_INTERTOUCH_OFF = 0,\n\tSYNAPTICS_INTERTOUCH_ON = 1,\n};\n\nstruct focaltech_finger_state {\n\tbool active;\n\tbool valid;\n\tunsigned int x;\n\tunsigned int y;\n};\n\nstruct focaltech_hw_state {\n\tstruct focaltech_finger_state fingers[5];\n\tunsigned int width;\n\tbool pressed;\n};\n\nstruct focaltech_data {\n\tunsigned int x_max;\n\tunsigned int y_max;\n\tstruct focaltech_hw_state state;\n};\n\nenum SS4_PACKET_ID {\n\tSS4_PACKET_ID_IDLE = 0,\n\tSS4_PACKET_ID_ONE = 1,\n\tSS4_PACKET_ID_TWO = 2,\n\tSS4_PACKET_ID_MULTI = 3,\n\tSS4_PACKET_ID_STICK = 4,\n};\n\nenum V7_PACKET_ID {\n\tV7_PACKET_ID_IDLE = 0,\n\tV7_PACKET_ID_TWO = 1,\n\tV7_PACKET_ID_MULTI = 2,\n\tV7_PACKET_ID_NEW = 3,\n\tV7_PACKET_ID_UNKNOWN = 4,\n};\n\nstruct alps_protocol_info {\n\tu16 version;\n\tu8 byte0;\n\tu8 mask0;\n\tunsigned int flags;\n};\n\nstruct alps_model_info {\n\tu8 signature[3];\n\tstruct alps_protocol_info protocol_info;\n};\n\nstruct alps_nibble_commands {\n\tint command;\n\tunsigned char data;\n};\n\nstruct alps_bitmap_point {\n\tint start_bit;\n\tint num_bits;\n};\n\nstruct alps_fields {\n\tunsigned int x_map;\n\tunsigned int y_map;\n\tunsigned int fingers;\n\tint pressure;\n\tstruct input_mt_pos st;\n\tstruct input_mt_pos mt[4];\n\tunsigned int first_mp: 1;\n\tunsigned int is_mp: 1;\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int ts_left: 1;\n\tunsigned int ts_right: 1;\n\tunsigned int ts_middle: 1;\n};\n\nstruct alps_data {\n\tstruct psmouse *psmouse;\n\tstruct input_dev *dev2;\n\tstruct input_dev *dev3;\n\tchar phys2[32];\n\tchar phys3[32];\n\tstruct delayed_work dev3_register_work;\n\tconst struct alps_nibble_commands *nibble_commands;\n\tint addr_command;\n\tu16 proto_version;\n\tu8 byte0;\n\tu8 mask0;\n\tu8 dev_id[3];\n\tu8 fw_ver[3];\n\tint flags;\n\tint x_max;\n\tint y_max;\n\tint x_bits;\n\tint y_bits;\n\tunsigned int x_res;\n\tunsigned int y_res;\n\tint (*hw_init)(struct psmouse *);\n\tvoid (*process_packet)(struct psmouse *);\n\tint (*decode_fields)(struct alps_fields *, unsigned char *, struct psmouse *);\n\tvoid (*set_abs_params)(struct alps_data *, struct input_dev *);\n\tint prev_fin;\n\tint multi_packet;\n\tint second_touch;\n\tunsigned char multi_data[6];\n\tstruct alps_fields f;\n\tu8 quirks;\n\tstruct timer_list timer;\n};\n\nstruct byd_data {\n\tstruct timer_list timer;\n\tstruct psmouse *psmouse;\n\ts32 abs_x;\n\ts32 abs_y;\n\tvolatile long unsigned int last_touch_time;\n\tbool btn_left;\n\tbool btn_right;\n\tbool touch;\n};\n\nstruct ps2pp_info {\n\tu8 model;\n\tu8 kind;\n\tu16 features;\n};\n\nstruct lifebook_data {\n\tstruct input_dev *dev2;\n\tchar phys[32];\n};\n\nstruct trackpoint_data {\n\tu8 variant_id;\n\tu8 firmware_id;\n\tu8 sensitivity;\n\tu8 speed;\n\tu8 inertia;\n\tu8 reach;\n\tu8 draghys;\n\tu8 mindrag;\n\tu8 thresh;\n\tu8 upthresh;\n\tu8 ztime;\n\tu8 jenks;\n\tu8 drift_time;\n\tbool press_to_select;\n\tbool skipback;\n\tbool ext_dev;\n};\n\nstruct trackpoint_attr_data {\n\tsize_t field_offset;\n\tu8 command;\n\tu8 mask;\n\tbool inverted;\n\tu8 power_on_default;\n};\n\nstruct cytp_contact {\n\tint x;\n\tint y;\n\tint z;\n};\n\nstruct cytp_report_data {\n\tint contact_cnt;\n\tstruct cytp_contact contacts[2];\n\tunsigned int left: 1;\n\tunsigned int right: 1;\n\tunsigned int middle: 1;\n\tunsigned int tap: 1;\n};\n\nstruct cytp_data {\n\tint fw_version;\n\tint pkt_size;\n\tint mode;\n\tint tp_min_pressure;\n\tint tp_max_pressure;\n\tint tp_width;\n\tint tp_high;\n\tint tp_max_abs_x;\n\tint tp_max_abs_y;\n\tint tp_res_x;\n\tint tp_res_y;\n\tint tp_metrics_supported;\n};\n\nstruct psmouse_smbus_dev {\n\tstruct i2c_board_info board;\n\tstruct psmouse *psmouse;\n\tstruct i2c_client *client;\n\tstruct list_head node;\n\tbool dead;\n\tbool need_deactivate;\n};\n\nstruct psmouse_smbus_removal_work {\n\tstruct work_struct work;\n\tstruct i2c_client *client;\n};\n\nstruct touchscreen_properties {\n\tunsigned int max_x;\n\tunsigned int max_y;\n\tbool invert_x;\n\tbool invert_y;\n\tbool swap_x_y;\n};\n\nstruct trace_event_raw_rtc_time_alarm_class {\n\tstruct trace_entry ent;\n\ttime64_t secs;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_irq_set_freq {\n\tstruct trace_entry ent;\n\tint freq;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_irq_set_state {\n\tstruct trace_entry ent;\n\tint enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_alarm_irq_enable {\n\tstruct trace_entry ent;\n\tunsigned int enabled;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_offset_class {\n\tstruct trace_entry ent;\n\tlong int offset;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rtc_timer_class {\n\tstruct trace_entry ent;\n\tstruct rtc_timer *timer;\n\tktime_t expires;\n\tktime_t period;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_rtc_time_alarm_class {};\n\nstruct trace_event_data_offsets_rtc_irq_set_freq {};\n\nstruct trace_event_data_offsets_rtc_irq_set_state {};\n\nstruct trace_event_data_offsets_rtc_alarm_irq_enable {};\n\nstruct trace_event_data_offsets_rtc_offset_class {};\n\nstruct trace_event_data_offsets_rtc_timer_class {};\n\ntypedef void (*btf_trace_rtc_set_time)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_read_time)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_set_alarm)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_read_alarm)(void *, time64_t, int);\n\ntypedef void (*btf_trace_rtc_irq_set_freq)(void *, int, int);\n\ntypedef void (*btf_trace_rtc_irq_set_state)(void *, int, int);\n\ntypedef void (*btf_trace_rtc_alarm_irq_enable)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_rtc_set_offset)(void *, long int, int);\n\ntypedef void (*btf_trace_rtc_read_offset)(void *, long int, int);\n\ntypedef void (*btf_trace_rtc_timer_enqueue)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_rtc_timer_dequeue)(void *, struct rtc_timer *);\n\ntypedef void (*btf_trace_rtc_timer_fired)(void *, struct rtc_timer *);\n\nenum {\n\tnone = 0,\n\tday = 1,\n\tmonth = 2,\n\tyear = 3,\n};\n\nstruct nvmem_cell_info {\n\tconst char *name;\n\tunsigned int offset;\n\tunsigned int bytes;\n\tunsigned int bit_offset;\n\tunsigned int nbits;\n};\n\ntypedef int (*nvmem_reg_read_t)(void *, unsigned int, void *, size_t);\n\ntypedef int (*nvmem_reg_write_t)(void *, unsigned int, void *, size_t);\n\nenum nvmem_type {\n\tNVMEM_TYPE_UNKNOWN = 0,\n\tNVMEM_TYPE_EEPROM = 1,\n\tNVMEM_TYPE_OTP = 2,\n\tNVMEM_TYPE_BATTERY_BACKED = 3,\n};\n\nstruct nvmem_config {\n\tstruct device *dev;\n\tconst char *name;\n\tint id;\n\tstruct module *owner;\n\tstruct gpio_desc *wp_gpio;\n\tconst struct nvmem_cell_info *cells;\n\tint ncells;\n\tenum nvmem_type type;\n\tbool read_only;\n\tbool root_only;\n\tbool no_of_node;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tint size;\n\tint word_size;\n\tint stride;\n\tvoid *priv;\n\tbool compat;\n\tstruct device *base_dev;\n};\n\nstruct nvmem_device;\n\nstruct cmos_rtc_board_info {\n\tvoid (*wake_on)(struct device *);\n\tvoid (*wake_off)(struct device *);\n\tu32 flags;\n\tint address_space;\n\tu8 rtc_day_alarm;\n\tu8 rtc_mon_alarm;\n\tu8 rtc_century;\n};\n\nstruct cmos_rtc {\n\tstruct rtc_device *rtc;\n\tstruct device *dev;\n\tint irq;\n\tstruct resource *iomem;\n\ttime64_t alarm_expires;\n\tvoid (*wake_on)(struct device *);\n\tvoid (*wake_off)(struct device *);\n\tu8 enabled_wake;\n\tu8 suspend_ctrl;\n\tu8 day_alrm;\n\tu8 mon_alrm;\n\tu8 century;\n\tstruct rtc_wkalrm saved_wkalrm;\n};\n\nstruct i2c_devinfo {\n\tstruct list_head list;\n\tint busnum;\n\tstruct i2c_board_info board_info;\n};\n\nstruct i2c_device_identity {\n\tu16 manufacturer_id;\n\tu16 part_id;\n\tu8 die_revision;\n};\n\nstruct i2c_timings {\n\tu32 bus_freq_hz;\n\tu32 scl_rise_ns;\n\tu32 scl_fall_ns;\n\tu32 scl_int_delay_ns;\n\tu32 sda_fall_ns;\n\tu32 sda_hold_ns;\n\tu32 digital_filter_width_ns;\n\tu32 analog_filter_cutoff_freq_hz;\n};\n\nstruct trace_event_raw_i2c_write {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_read {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_reply {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 msg_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u16 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_i2c_result {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 nr_msgs;\n\t__s16 ret;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_i2c_write {\n\tu32 buf;\n};\n\nstruct trace_event_data_offsets_i2c_read {};\n\nstruct trace_event_data_offsets_i2c_reply {\n\tu32 buf;\n};\n\nstruct trace_event_data_offsets_i2c_result {};\n\ntypedef void (*btf_trace_i2c_write)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_read)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_reply)(void *, const struct i2c_adapter *, const struct i2c_msg *, int);\n\ntypedef void (*btf_trace_i2c_result)(void *, const struct i2c_adapter *, int, int);\n\nstruct i2c_dummy_devres {\n\tstruct i2c_client *client;\n};\n\nstruct class_compat___2;\n\nstruct i2c_cmd_arg {\n\tunsigned int cmd;\n\tvoid *arg;\n};\n\nstruct i2c_smbus_alert_setup {\n\tint irq;\n};\n\nstruct trace_event_raw_smbus_write {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 command;\n\t__u8 len;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_read {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 flags;\n\t__u16 addr;\n\t__u8 command;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_reply {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 command;\n\t__u8 len;\n\t__u32 protocol;\n\t__u8 buf[34];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_smbus_result {\n\tstruct trace_entry ent;\n\tint adapter_nr;\n\t__u16 addr;\n\t__u16 flags;\n\t__u8 read_write;\n\t__u8 command;\n\t__s16 res;\n\t__u32 protocol;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_smbus_write {};\n\nstruct trace_event_data_offsets_smbus_read {};\n\nstruct trace_event_data_offsets_smbus_reply {};\n\nstruct trace_event_data_offsets_smbus_result {};\n\ntypedef void (*btf_trace_smbus_write)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, const union i2c_smbus_data *);\n\ntypedef void (*btf_trace_smbus_read)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int);\n\ntypedef void (*btf_trace_smbus_reply)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, const union i2c_smbus_data *, int);\n\ntypedef void (*btf_trace_smbus_result)(void *, const struct i2c_adapter *, u16, short unsigned int, char, u8, int, int);\n\nstruct i2c_acpi_handler_data {\n\tstruct acpi_connection_info info;\n\tstruct i2c_adapter *adapter;\n};\n\nstruct gsb_buffer {\n\tu8 status;\n\tu8 len;\n\tunion {\n\t\tu16 wdata;\n\t\tu8 bdata;\n\t\tu8 data[0];\n\t};\n};\n\nstruct i2c_acpi_lookup {\n\tstruct i2c_board_info *info;\n\tacpi_handle adapter_handle;\n\tacpi_handle device_handle;\n\tacpi_handle search_handle;\n\tint n;\n\tint index;\n\tu32 speed;\n\tu32 min_speed;\n\tu32 force_speed;\n};\n\nstruct i2c_smbus_alert {\n\tstruct work_struct alert;\n\tstruct i2c_client *ara;\n};\n\nstruct alert_data {\n\tshort unsigned int addr;\n\tenum i2c_alert_protocol type;\n\tunsigned int data;\n};\n\nstruct itco_wdt_platform_data {\n\tchar name[32];\n\tunsigned int version;\n\tbool no_reboot_use_pmc;\n};\n\nstruct i801_priv {\n\tstruct i2c_adapter adapter;\n\tlong unsigned int smba;\n\tunsigned char original_hstcfg;\n\tunsigned char original_slvcmd;\n\tstruct pci_dev *pci_dev;\n\tunsigned int features;\n\twait_queue_head_t waitq;\n\tu8 status;\n\tu8 cmd;\n\tbool is_read;\n\tint count;\n\tint len;\n\tu8 *data;\n\tstruct platform_device *tco_pdev;\n\tbool acpi_reserved;\n\tstruct mutex acpi_lock;\n};\n\nstruct dmi_onboard_device_info {\n\tconst char *name;\n\tu8 type;\n\tshort unsigned int i2c_addr;\n\tconst char *i2c_type;\n};\n\nstruct pps_ktime {\n\t__s64 sec;\n\t__s32 nsec;\n\t__u32 flags;\n};\n\nstruct pps_ktime_compat {\n\t__s64 sec;\n\t__s32 nsec;\n\t__u32 flags;\n};\n\nstruct pps_kinfo {\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime assert_tu;\n\tstruct pps_ktime clear_tu;\n\tint current_mode;\n};\n\nstruct pps_kinfo_compat {\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime_compat assert_tu;\n\tstruct pps_ktime_compat clear_tu;\n\tint current_mode;\n} __attribute__((packed));\n\nstruct pps_kparams {\n\tint api_version;\n\tint mode;\n\tstruct pps_ktime assert_off_tu;\n\tstruct pps_ktime clear_off_tu;\n};\n\nstruct pps_fdata {\n\tstruct pps_kinfo info;\n\tstruct pps_ktime timeout;\n};\n\nstruct pps_fdata_compat {\n\tstruct pps_kinfo_compat info;\n\tstruct pps_ktime_compat timeout;\n} __attribute__((packed));\n\nstruct pps_bind_args {\n\tint tsformat;\n\tint edge;\n\tint consumer;\n};\n\nstruct pps_device;\n\nstruct pps_source_info {\n\tchar name[32];\n\tchar path[32];\n\tint mode;\n\tvoid (*echo)(struct pps_device *, int, void *);\n\tstruct module *owner;\n\tstruct device *dev;\n};\n\nstruct pps_device {\n\tstruct pps_source_info info;\n\tstruct pps_kparams params;\n\t__u32 assert_sequence;\n\t__u32 clear_sequence;\n\tstruct pps_ktime assert_tu;\n\tstruct pps_ktime clear_tu;\n\tint current_mode;\n\tunsigned int last_ev;\n\twait_queue_head_t queue;\n\tunsigned int id;\n\tconst void *lookup_cookie;\n\tstruct cdev cdev;\n\tstruct device *dev;\n\tstruct fasync_struct *async_queue;\n\tspinlock_t lock;\n};\n\nstruct pps_event_time {\n\tstruct timespec64 ts_real;\n};\n\nstruct ptp_extts_event {\n\tstruct ptp_clock_time t;\n\tunsigned int index;\n\tunsigned int flags;\n\tunsigned int rsv[2];\n};\n\nenum ptp_clock_events {\n\tPTP_CLOCK_ALARM = 0,\n\tPTP_CLOCK_EXTTS = 1,\n\tPTP_CLOCK_PPS = 2,\n\tPTP_CLOCK_PPSUSR = 3,\n};\n\nstruct ptp_clock_event {\n\tint type;\n\tint index;\n\tunion {\n\t\tu64 timestamp;\n\t\tstruct pps_event_time pps_times;\n\t};\n};\n\nstruct timestamp_event_queue {\n\tstruct ptp_extts_event buf[128];\n\tint head;\n\tint tail;\n\tspinlock_t lock;\n};\n\nstruct ptp_clock___2 {\n\tstruct posix_clock clock;\n\tstruct device dev;\n\tstruct ptp_clock_info *info;\n\tdev_t devid;\n\tint index;\n\tstruct pps_device *pps_source;\n\tlong int dialed_frequency;\n\tstruct timestamp_event_queue tsevq;\n\tstruct mutex tsevq_mux;\n\tstruct mutex pincfg_mux;\n\twait_queue_head_t tsev_wq;\n\tint defunct;\n\tstruct device_attribute *pin_dev_attr;\n\tstruct attribute **pin_attr;\n\tstruct attribute_group pin_attr_group;\n\tconst struct attribute_group *pin_attr_groups[2];\n\tstruct kthread_worker *kworker;\n\tstruct kthread_delayed_work aux_work;\n};\n\nstruct ptp_clock_caps {\n\tint max_adj;\n\tint n_alarm;\n\tint n_ext_ts;\n\tint n_per_out;\n\tint pps;\n\tint n_pins;\n\tint cross_timestamping;\n\tint adjust_phase;\n\tint rsv[12];\n};\n\nstruct ptp_sys_offset {\n\tunsigned int n_samples;\n\tunsigned int rsv[3];\n\tstruct ptp_clock_time ts[51];\n};\n\nstruct ptp_sys_offset_extended {\n\tunsigned int n_samples;\n\tunsigned int rsv[3];\n\tstruct ptp_clock_time ts[75];\n};\n\nstruct ptp_sys_offset_precise {\n\tstruct ptp_clock_time device;\n\tstruct ptp_clock_time sys_realtime;\n\tstruct ptp_clock_time sys_monoraw;\n\tunsigned int rsv[4];\n};\n\nenum power_supply_notifier_events {\n\tPSY_EVENT_PROP_CHANGED = 0,\n};\n\nstruct power_supply_battery_ocv_table {\n\tint ocv;\n\tint capacity;\n};\n\nstruct power_supply_resistance_temp_table {\n\tint temp;\n\tint resistance;\n};\n\nstruct power_supply_battery_info {\n\tint energy_full_design_uwh;\n\tint charge_full_design_uah;\n\tint voltage_min_design_uv;\n\tint voltage_max_design_uv;\n\tint tricklecharge_current_ua;\n\tint precharge_current_ua;\n\tint precharge_voltage_max_uv;\n\tint charge_term_current_ua;\n\tint charge_restart_voltage_uv;\n\tint overvoltage_limit_uv;\n\tint constant_charge_current_max_ua;\n\tint constant_charge_voltage_max_uv;\n\tint factory_internal_resistance_uohm;\n\tint ocv_temp[20];\n\tstruct power_supply_battery_ocv_table *ocv_table[20];\n\tint ocv_table_size[20];\n\tstruct power_supply_resistance_temp_table *resist_table;\n\tint resist_table_size;\n};\n\nstruct psy_am_i_supplied_data {\n\tstruct power_supply *psy;\n\tunsigned int count;\n};\n\nenum {\n\tPOWER_SUPPLY_CHARGE_TYPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_CHARGE_TYPE_NONE = 1,\n\tPOWER_SUPPLY_CHARGE_TYPE_TRICKLE = 2,\n\tPOWER_SUPPLY_CHARGE_TYPE_FAST = 3,\n\tPOWER_SUPPLY_CHARGE_TYPE_STANDARD = 4,\n\tPOWER_SUPPLY_CHARGE_TYPE_ADAPTIVE = 5,\n\tPOWER_SUPPLY_CHARGE_TYPE_CUSTOM = 6,\n};\n\nenum {\n\tPOWER_SUPPLY_HEALTH_UNKNOWN = 0,\n\tPOWER_SUPPLY_HEALTH_GOOD = 1,\n\tPOWER_SUPPLY_HEALTH_OVERHEAT = 2,\n\tPOWER_SUPPLY_HEALTH_DEAD = 3,\n\tPOWER_SUPPLY_HEALTH_OVERVOLTAGE = 4,\n\tPOWER_SUPPLY_HEALTH_UNSPEC_FAILURE = 5,\n\tPOWER_SUPPLY_HEALTH_COLD = 6,\n\tPOWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE = 7,\n\tPOWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE = 8,\n\tPOWER_SUPPLY_HEALTH_OVERCURRENT = 9,\n\tPOWER_SUPPLY_HEALTH_CALIBRATION_REQUIRED = 10,\n};\n\nenum {\n\tPOWER_SUPPLY_SCOPE_UNKNOWN = 0,\n\tPOWER_SUPPLY_SCOPE_SYSTEM = 1,\n\tPOWER_SUPPLY_SCOPE_DEVICE = 2,\n};\n\nstruct power_supply_attr {\n\tconst char *prop_name;\n\tchar attr_name[31];\n\tstruct device_attribute dev_attr;\n\tconst char * const *text_values;\n\tint text_values_len;\n};\n\nenum hwmon_sensor_types {\n\thwmon_chip = 0,\n\thwmon_temp = 1,\n\thwmon_in = 2,\n\thwmon_curr = 3,\n\thwmon_power = 4,\n\thwmon_energy = 5,\n\thwmon_humidity = 6,\n\thwmon_fan = 7,\n\thwmon_pwm = 8,\n\thwmon_intrusion = 9,\n\thwmon_max = 10,\n};\n\nenum hwmon_temp_attributes {\n\thwmon_temp_enable = 0,\n\thwmon_temp_input = 1,\n\thwmon_temp_type = 2,\n\thwmon_temp_lcrit = 3,\n\thwmon_temp_lcrit_hyst = 4,\n\thwmon_temp_min = 5,\n\thwmon_temp_min_hyst = 6,\n\thwmon_temp_max = 7,\n\thwmon_temp_max_hyst = 8,\n\thwmon_temp_crit = 9,\n\thwmon_temp_crit_hyst = 10,\n\thwmon_temp_emergency = 11,\n\thwmon_temp_emergency_hyst = 12,\n\thwmon_temp_alarm = 13,\n\thwmon_temp_lcrit_alarm = 14,\n\thwmon_temp_min_alarm = 15,\n\thwmon_temp_max_alarm = 16,\n\thwmon_temp_crit_alarm = 17,\n\thwmon_temp_emergency_alarm = 18,\n\thwmon_temp_fault = 19,\n\thwmon_temp_offset = 20,\n\thwmon_temp_label = 21,\n\thwmon_temp_lowest = 22,\n\thwmon_temp_highest = 23,\n\thwmon_temp_reset_history = 24,\n};\n\nenum hwmon_in_attributes {\n\thwmon_in_enable = 0,\n\thwmon_in_input = 1,\n\thwmon_in_min = 2,\n\thwmon_in_max = 3,\n\thwmon_in_lcrit = 4,\n\thwmon_in_crit = 5,\n\thwmon_in_average = 6,\n\thwmon_in_lowest = 7,\n\thwmon_in_highest = 8,\n\thwmon_in_reset_history = 9,\n\thwmon_in_label = 10,\n\thwmon_in_alarm = 11,\n\thwmon_in_min_alarm = 12,\n\thwmon_in_max_alarm = 13,\n\thwmon_in_lcrit_alarm = 14,\n\thwmon_in_crit_alarm = 15,\n};\n\nenum hwmon_curr_attributes {\n\thwmon_curr_enable = 0,\n\thwmon_curr_input = 1,\n\thwmon_curr_min = 2,\n\thwmon_curr_max = 3,\n\thwmon_curr_lcrit = 4,\n\thwmon_curr_crit = 5,\n\thwmon_curr_average = 6,\n\thwmon_curr_lowest = 7,\n\thwmon_curr_highest = 8,\n\thwmon_curr_reset_history = 9,\n\thwmon_curr_label = 10,\n\thwmon_curr_alarm = 11,\n\thwmon_curr_min_alarm = 12,\n\thwmon_curr_max_alarm = 13,\n\thwmon_curr_lcrit_alarm = 14,\n\thwmon_curr_crit_alarm = 15,\n};\n\nstruct hwmon_ops {\n\tumode_t (*is_visible)(const void *, enum hwmon_sensor_types, u32, int);\n\tint (*read)(struct device *, enum hwmon_sensor_types, u32, int, long int *);\n\tint (*read_string)(struct device *, enum hwmon_sensor_types, u32, int, const char **);\n\tint (*write)(struct device *, enum hwmon_sensor_types, u32, int, long int);\n};\n\nstruct hwmon_channel_info {\n\tenum hwmon_sensor_types type;\n\tconst u32 *config;\n};\n\nstruct hwmon_chip_info {\n\tconst struct hwmon_ops *ops;\n\tconst struct hwmon_channel_info **info;\n};\n\nstruct power_supply_hwmon {\n\tstruct power_supply *psy;\n\tlong unsigned int *props;\n};\n\nstruct hwmon_type_attr_list {\n\tconst u32 *attrs;\n\tsize_t n_attrs;\n};\n\nenum hwmon_chip_attributes {\n\thwmon_chip_temp_reset_history = 0,\n\thwmon_chip_in_reset_history = 1,\n\thwmon_chip_curr_reset_history = 2,\n\thwmon_chip_power_reset_history = 3,\n\thwmon_chip_register_tz = 4,\n\thwmon_chip_update_interval = 5,\n\thwmon_chip_alarms = 6,\n\thwmon_chip_samples = 7,\n\thwmon_chip_curr_samples = 8,\n\thwmon_chip_in_samples = 9,\n\thwmon_chip_power_samples = 10,\n\thwmon_chip_temp_samples = 11,\n};\n\nenum hwmon_power_attributes {\n\thwmon_power_enable = 0,\n\thwmon_power_average = 1,\n\thwmon_power_average_interval = 2,\n\thwmon_power_average_interval_max = 3,\n\thwmon_power_average_interval_min = 4,\n\thwmon_power_average_highest = 5,\n\thwmon_power_average_lowest = 6,\n\thwmon_power_average_max = 7,\n\thwmon_power_average_min = 8,\n\thwmon_power_input = 9,\n\thwmon_power_input_highest = 10,\n\thwmon_power_input_lowest = 11,\n\thwmon_power_reset_history = 12,\n\thwmon_power_accuracy = 13,\n\thwmon_power_cap = 14,\n\thwmon_power_cap_hyst = 15,\n\thwmon_power_cap_max = 16,\n\thwmon_power_cap_min = 17,\n\thwmon_power_min = 18,\n\thwmon_power_max = 19,\n\thwmon_power_crit = 20,\n\thwmon_power_lcrit = 21,\n\thwmon_power_label = 22,\n\thwmon_power_alarm = 23,\n\thwmon_power_cap_alarm = 24,\n\thwmon_power_min_alarm = 25,\n\thwmon_power_max_alarm = 26,\n\thwmon_power_lcrit_alarm = 27,\n\thwmon_power_crit_alarm = 28,\n};\n\nenum hwmon_energy_attributes {\n\thwmon_energy_enable = 0,\n\thwmon_energy_input = 1,\n\thwmon_energy_label = 2,\n};\n\nenum hwmon_humidity_attributes {\n\thwmon_humidity_enable = 0,\n\thwmon_humidity_input = 1,\n\thwmon_humidity_label = 2,\n\thwmon_humidity_min = 3,\n\thwmon_humidity_min_hyst = 4,\n\thwmon_humidity_max = 5,\n\thwmon_humidity_max_hyst = 6,\n\thwmon_humidity_alarm = 7,\n\thwmon_humidity_fault = 8,\n};\n\nenum hwmon_fan_attributes {\n\thwmon_fan_enable = 0,\n\thwmon_fan_input = 1,\n\thwmon_fan_label = 2,\n\thwmon_fan_min = 3,\n\thwmon_fan_max = 4,\n\thwmon_fan_div = 5,\n\thwmon_fan_pulses = 6,\n\thwmon_fan_target = 7,\n\thwmon_fan_alarm = 8,\n\thwmon_fan_min_alarm = 9,\n\thwmon_fan_max_alarm = 10,\n\thwmon_fan_fault = 11,\n};\n\nenum hwmon_pwm_attributes {\n\thwmon_pwm_input = 0,\n\thwmon_pwm_enable = 1,\n\thwmon_pwm_mode = 2,\n\thwmon_pwm_freq = 3,\n};\n\nenum hwmon_intrusion_attributes {\n\thwmon_intrusion_alarm = 0,\n\thwmon_intrusion_beep = 1,\n};\n\nstruct trace_event_raw_hwmon_attr_class {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 __data_loc_attr_name;\n\tlong int val;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hwmon_attr_show_string {\n\tstruct trace_entry ent;\n\tint index;\n\tu32 __data_loc_attr_name;\n\tu32 __data_loc_label;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_hwmon_attr_class {\n\tu32 attr_name;\n};\n\nstruct trace_event_data_offsets_hwmon_attr_show_string {\n\tu32 attr_name;\n\tu32 label;\n};\n\ntypedef void (*btf_trace_hwmon_attr_show)(void *, int, const char *, long int);\n\ntypedef void (*btf_trace_hwmon_attr_store)(void *, int, const char *, long int);\n\ntypedef void (*btf_trace_hwmon_attr_show_string)(void *, int, const char *, const char *);\n\nstruct hwmon_device {\n\tconst char *name;\n\tstruct device dev;\n\tconst struct hwmon_chip_info *chip;\n\tstruct list_head tzdata;\n\tstruct attribute_group group;\n\tconst struct attribute_group **groups;\n};\n\nstruct hwmon_device_attribute {\n\tstruct device_attribute dev_attr;\n\tconst struct hwmon_ops *ops;\n\tenum hwmon_sensor_types type;\n\tu32 attr;\n\tint index;\n\tchar name[32];\n};\n\nstruct thermal_attr {\n\tstruct device_attribute attr;\n\tchar name[20];\n};\n\nstruct trace_event_raw_thermal_temperature {\n\tstruct trace_entry ent;\n\tu32 __data_loc_thermal_zone;\n\tint id;\n\tint temp_prev;\n\tint temp;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cdev_update {\n\tstruct trace_entry ent;\n\tu32 __data_loc_type;\n\tlong unsigned int target;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_thermal_zone_trip {\n\tstruct trace_entry ent;\n\tu32 __data_loc_thermal_zone;\n\tint id;\n\tint trip;\n\tenum thermal_trip_type trip_type;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_thermal_temperature {\n\tu32 thermal_zone;\n};\n\nstruct trace_event_data_offsets_cdev_update {\n\tu32 type;\n};\n\nstruct trace_event_data_offsets_thermal_zone_trip {\n\tu32 thermal_zone;\n};\n\ntypedef void (*btf_trace_thermal_temperature)(void *, struct thermal_zone_device *);\n\ntypedef void (*btf_trace_cdev_update)(void *, struct thermal_cooling_device *, long unsigned int);\n\ntypedef void (*btf_trace_thermal_zone_trip)(void *, struct thermal_zone_device *, int, enum thermal_trip_type);\n\nstruct thermal_instance {\n\tint id;\n\tchar name[20];\n\tstruct thermal_zone_device *tz;\n\tstruct thermal_cooling_device *cdev;\n\tint trip;\n\tbool initialized;\n\tlong unsigned int upper;\n\tlong unsigned int lower;\n\tlong unsigned int target;\n\tchar attr_name[20];\n\tstruct device_attribute attr;\n\tchar weight_attr_name[20];\n\tstruct device_attribute weight_attr;\n\tstruct list_head tz_node;\n\tstruct list_head cdev_node;\n\tunsigned int weight;\n};\n\nstruct thermal_hwmon_device {\n\tchar type[20];\n\tstruct device *device;\n\tint count;\n\tstruct list_head tz_list;\n\tstruct list_head node;\n};\n\nstruct thermal_hwmon_attr {\n\tstruct device_attribute attr;\n\tchar name[16];\n};\n\nstruct thermal_hwmon_temp {\n\tstruct list_head hwmon_node;\n\tstruct thermal_zone_device *tz;\n\tstruct thermal_hwmon_attr temp_input;\n\tstruct thermal_hwmon_attr temp_crit;\n};\n\nstruct mdp_device_descriptor_s {\n\t__u32 number;\n\t__u32 major;\n\t__u32 minor;\n\t__u32 raid_disk;\n\t__u32 state;\n\t__u32 reserved[27];\n};\n\ntypedef struct mdp_device_descriptor_s mdp_disk_t;\n\nstruct mdp_superblock_s {\n\t__u32 md_magic;\n\t__u32 major_version;\n\t__u32 minor_version;\n\t__u32 patch_version;\n\t__u32 gvalid_words;\n\t__u32 set_uuid0;\n\t__u32 ctime;\n\t__u32 level;\n\t__u32 size;\n\t__u32 nr_disks;\n\t__u32 raid_disks;\n\t__u32 md_minor;\n\t__u32 not_persistent;\n\t__u32 set_uuid1;\n\t__u32 set_uuid2;\n\t__u32 set_uuid3;\n\t__u32 gstate_creserved[16];\n\t__u32 utime;\n\t__u32 state;\n\t__u32 active_disks;\n\t__u32 working_disks;\n\t__u32 failed_disks;\n\t__u32 spare_disks;\n\t__u32 sb_csum;\n\t__u32 events_lo;\n\t__u32 events_hi;\n\t__u32 cp_events_lo;\n\t__u32 cp_events_hi;\n\t__u32 recovery_cp;\n\t__u64 reshape_position;\n\t__u32 new_level;\n\t__u32 delta_disks;\n\t__u32 new_layout;\n\t__u32 new_chunk;\n\t__u32 gstate_sreserved[14];\n\t__u32 layout;\n\t__u32 chunk_size;\n\t__u32 root_pv;\n\t__u32 root_block;\n\t__u32 pstate_reserved[60];\n\tmdp_disk_t disks[27];\n\t__u32 reserved[0];\n\tmdp_disk_t this_disk;\n};\n\ntypedef struct mdp_superblock_s mdp_super_t;\n\nstruct mdp_superblock_1 {\n\t__le32 magic;\n\t__le32 major_version;\n\t__le32 feature_map;\n\t__le32 pad0;\n\t__u8 set_uuid[16];\n\tchar set_name[32];\n\t__le64 ctime;\n\t__le32 level;\n\t__le32 layout;\n\t__le64 size;\n\t__le32 chunksize;\n\t__le32 raid_disks;\n\tunion {\n\t\t__le32 bitmap_offset;\n\t\tstruct {\n\t\t\t__le16 offset;\n\t\t\t__le16 size;\n\t\t} ppl;\n\t};\n\t__le32 new_level;\n\t__le64 reshape_position;\n\t__le32 delta_disks;\n\t__le32 new_layout;\n\t__le32 new_chunk;\n\t__le32 new_offset;\n\t__le64 data_offset;\n\t__le64 data_size;\n\t__le64 super_offset;\n\tunion {\n\t\t__le64 recovery_offset;\n\t\t__le64 journal_tail;\n\t};\n\t__le32 dev_number;\n\t__le32 cnt_corrected_read;\n\t__u8 device_uuid[16];\n\t__u8 devflags;\n\t__u8 bblog_shift;\n\t__le16 bblog_size;\n\t__le32 bblog_offset;\n\t__le64 utime;\n\t__le64 events;\n\t__le64 resync_offset;\n\t__le32 sb_csum;\n\t__le32 max_dev;\n\t__u8 pad3[32];\n\t__le16 dev_roles[0];\n};\n\nstruct mdu_version_s {\n\tint major;\n\tint minor;\n\tint patchlevel;\n};\n\ntypedef struct mdu_version_s mdu_version_t;\n\nstruct mdu_bitmap_file_s {\n\tchar pathname[4096];\n};\n\ntypedef struct mdu_bitmap_file_s mdu_bitmap_file_t;\n\nstruct mddev;\n\nstruct md_rdev;\n\nstruct md_cluster_operations {\n\tint (*join)(struct mddev *, int);\n\tint (*leave)(struct mddev *);\n\tint (*slot_number)(struct mddev *);\n\tint (*resync_info_update)(struct mddev *, sector_t, sector_t);\n\tvoid (*resync_info_get)(struct mddev *, sector_t *, sector_t *);\n\tint (*metadata_update_start)(struct mddev *);\n\tint (*metadata_update_finish)(struct mddev *);\n\tvoid (*metadata_update_cancel)(struct mddev *);\n\tint (*resync_start)(struct mddev *);\n\tint (*resync_finish)(struct mddev *);\n\tint (*area_resyncing)(struct mddev *, int, sector_t, sector_t);\n\tint (*add_new_disk)(struct mddev *, struct md_rdev *);\n\tvoid (*add_new_disk_cancel)(struct mddev *);\n\tint (*new_disk_ack)(struct mddev *, bool);\n\tint (*remove_disk)(struct mddev *, struct md_rdev *);\n\tvoid (*load_bitmaps)(struct mddev *, int);\n\tint (*gather_bitmaps)(struct md_rdev *);\n\tint (*resize_bitmaps)(struct mddev *, sector_t, sector_t);\n\tint (*lock_all_bitmaps)(struct mddev *);\n\tvoid (*unlock_all_bitmaps)(struct mddev *);\n\tvoid (*update_size)(struct mddev *, sector_t);\n};\n\nstruct md_cluster_info;\n\nstruct md_personality;\n\nstruct md_thread;\n\nstruct bitmap;\n\nstruct mddev {\n\tvoid *private;\n\tstruct md_personality *pers;\n\tdev_t unit;\n\tint md_minor;\n\tstruct list_head disks;\n\tlong unsigned int flags;\n\tlong unsigned int sb_flags;\n\tint suspended;\n\tatomic_t active_io;\n\tint ro;\n\tint sysfs_active;\n\tstruct gendisk *gendisk;\n\tstruct kobject kobj;\n\tint hold_active;\n\tint major_version;\n\tint minor_version;\n\tint patch_version;\n\tint persistent;\n\tint external;\n\tchar metadata_type[17];\n\tint chunk_sectors;\n\ttime64_t ctime;\n\ttime64_t utime;\n\tint level;\n\tint layout;\n\tchar clevel[16];\n\tint raid_disks;\n\tint max_disks;\n\tsector_t dev_sectors;\n\tsector_t array_sectors;\n\tint external_size;\n\t__u64 events;\n\tint can_decrease_events;\n\tchar uuid[16];\n\tsector_t reshape_position;\n\tint delta_disks;\n\tint new_level;\n\tint new_layout;\n\tint new_chunk_sectors;\n\tint reshape_backwards;\n\tstruct md_thread *thread;\n\tstruct md_thread *sync_thread;\n\tchar *last_sync_action;\n\tsector_t curr_resync;\n\tsector_t curr_resync_completed;\n\tlong unsigned int resync_mark;\n\tsector_t resync_mark_cnt;\n\tsector_t curr_mark_cnt;\n\tsector_t resync_max_sectors;\n\tatomic64_t resync_mismatches;\n\tsector_t suspend_lo;\n\tsector_t suspend_hi;\n\tint sync_speed_min;\n\tint sync_speed_max;\n\tint parallel_resync;\n\tint ok_start_degraded;\n\tlong unsigned int recovery;\n\tint recovery_disabled;\n\tint in_sync;\n\tstruct mutex open_mutex;\n\tstruct mutex reconfig_mutex;\n\tatomic_t active;\n\tatomic_t openers;\n\tint changed;\n\tint degraded;\n\tatomic_t recovery_active;\n\twait_queue_head_t recovery_wait;\n\tsector_t recovery_cp;\n\tsector_t resync_min;\n\tsector_t resync_max;\n\tstruct kernfs_node *sysfs_state;\n\tstruct kernfs_node *sysfs_action;\n\tstruct work_struct del_work;\n\tspinlock_t lock;\n\twait_queue_head_t sb_wait;\n\tatomic_t pending_writes;\n\tunsigned int safemode;\n\tunsigned int safemode_delay;\n\tstruct timer_list safemode_timer;\n\tstruct percpu_ref writes_pending;\n\tint sync_checkers;\n\tstruct request_queue *queue;\n\tstruct bitmap *bitmap;\n\tstruct {\n\t\tstruct file *file;\n\t\tloff_t offset;\n\t\tlong unsigned int space;\n\t\tloff_t default_offset;\n\t\tlong unsigned int default_space;\n\t\tstruct mutex mutex;\n\t\tlong unsigned int chunksize;\n\t\tlong unsigned int daemon_sleep;\n\t\tlong unsigned int max_write_behind;\n\t\tint external;\n\t\tint nodes;\n\t\tchar cluster_name[64];\n\t} bitmap_info;\n\tatomic_t max_corr_read_errors;\n\tstruct list_head all_mddevs;\n\tstruct attribute_group *to_remove;\n\tstruct bio_set bio_set;\n\tstruct bio_set sync_set;\n\tstruct bio *flush_bio;\n\tatomic_t flush_pending;\n\tktime_t start_flush;\n\tktime_t last_flush;\n\tstruct work_struct flush_work;\n\tstruct work_struct event_work;\n\tmempool_t *serial_info_pool;\n\tvoid (*sync_super)(struct mddev *, struct md_rdev *);\n\tstruct md_cluster_info *cluster_info;\n\tunsigned int good_device_nr;\n\tunsigned int noio_flag;\n\tbool has_superblocks: 1;\n\tbool fail_last_dev: 1;\n\tbool serialize_policy: 1;\n};\n\nstruct serial_in_rdev;\n\nstruct md_rdev {\n\tstruct list_head same_set;\n\tsector_t sectors;\n\tstruct mddev *mddev;\n\tint last_events;\n\tstruct block_device *meta_bdev;\n\tstruct block_device *bdev;\n\tstruct page *sb_page;\n\tstruct page *bb_page;\n\tint sb_loaded;\n\t__u64 sb_events;\n\tsector_t data_offset;\n\tsector_t new_data_offset;\n\tsector_t sb_start;\n\tint sb_size;\n\tint preferred_minor;\n\tstruct kobject kobj;\n\tlong unsigned int flags;\n\twait_queue_head_t blocked_wait;\n\tint desc_nr;\n\tint raid_disk;\n\tint new_raid_disk;\n\tint saved_raid_disk;\n\tunion {\n\t\tsector_t recovery_offset;\n\t\tsector_t journal_tail;\n\t};\n\tatomic_t nr_pending;\n\tatomic_t read_errors;\n\ttime64_t last_read_error;\n\tatomic_t corrected_errors;\n\tstruct serial_in_rdev *serial;\n\tstruct work_struct del_work;\n\tstruct kernfs_node *sysfs_state;\n\tstruct badblocks badblocks;\n\tstruct {\n\t\tshort int offset;\n\t\tunsigned int size;\n\t\tsector_t sector;\n\t} ppl;\n};\n\nstruct serial_in_rdev {\n\tstruct rb_root_cached serial_rb;\n\tspinlock_t serial_lock;\n\twait_queue_head_t serial_io_wait;\n};\n\nenum flag_bits {\n\tFaulty = 0,\n\tIn_sync = 1,\n\tBitmap_sync = 2,\n\tWriteMostly = 3,\n\tAutoDetected = 4,\n\tBlocked = 5,\n\tWriteErrorSeen = 6,\n\tFaultRecorded = 7,\n\tBlockedBadBlocks = 8,\n\tWantReplacement = 9,\n\tReplacement = 10,\n\tCandidate = 11,\n\tJournal = 12,\n\tClusterRemove = 13,\n\tRemoveSynchronized = 14,\n\tExternalBbl = 15,\n\tFailFast = 16,\n\tLastDev = 17,\n\tCollisionCheck = 18,\n};\n\nenum mddev_flags {\n\tMD_ARRAY_FIRST_USE = 0,\n\tMD_CLOSING = 1,\n\tMD_JOURNAL_CLEAN = 2,\n\tMD_HAS_JOURNAL = 3,\n\tMD_CLUSTER_RESYNC_LOCKED = 4,\n\tMD_FAILFAST_SUPPORTED = 5,\n\tMD_HAS_PPL = 6,\n\tMD_HAS_MULTIPLE_PPLS = 7,\n\tMD_ALLOW_SB_UPDATE = 8,\n\tMD_UPDATING_SB = 9,\n\tMD_NOT_READY = 10,\n\tMD_BROKEN = 11,\n};\n\nenum mddev_sb_flags {\n\tMD_SB_CHANGE_DEVS = 0,\n\tMD_SB_CHANGE_CLEAN = 1,\n\tMD_SB_CHANGE_PENDING = 2,\n\tMD_SB_NEED_REWRITE = 3,\n};\n\nstruct md_personality {\n\tchar *name;\n\tint level;\n\tstruct list_head list;\n\tstruct module *owner;\n\tbool (*make_request)(struct mddev *, struct bio *);\n\tint (*run)(struct mddev *);\n\tint (*start)(struct mddev *);\n\tvoid (*free)(struct mddev *, void *);\n\tvoid (*status)(struct seq_file *, struct mddev *);\n\tvoid (*error_handler)(struct mddev *, struct md_rdev *);\n\tint (*hot_add_disk)(struct mddev *, struct md_rdev *);\n\tint (*hot_remove_disk)(struct mddev *, struct md_rdev *);\n\tint (*spare_active)(struct mddev *);\n\tsector_t (*sync_request)(struct mddev *, sector_t, int *);\n\tint (*resize)(struct mddev *, sector_t);\n\tsector_t (*size)(struct mddev *, sector_t, int);\n\tint (*check_reshape)(struct mddev *);\n\tint (*start_reshape)(struct mddev *);\n\tvoid (*finish_reshape)(struct mddev *);\n\tvoid (*update_reshape_pos)(struct mddev *);\n\tvoid (*quiesce)(struct mddev *, int);\n\tvoid * (*takeover)(struct mddev *);\n\tint (*congested)(struct mddev *, int);\n\tint (*change_consistency_policy)(struct mddev *, const char *);\n};\n\nstruct md_thread {\n\tvoid (*run)(struct md_thread *);\n\tstruct mddev *mddev;\n\twait_queue_head_t wqueue;\n\tlong unsigned int flags;\n\tstruct task_struct *tsk;\n\tlong unsigned int timeout;\n\tvoid *private;\n};\n\nstruct bitmap_page;\n\nstruct bitmap_counts {\n\tspinlock_t lock;\n\tstruct bitmap_page *bp;\n\tlong unsigned int pages;\n\tlong unsigned int missing_pages;\n\tlong unsigned int chunkshift;\n\tlong unsigned int chunks;\n};\n\nstruct bitmap_storage {\n\tstruct file *file;\n\tstruct page *sb_page;\n\tstruct page **filemap;\n\tlong unsigned int *filemap_attr;\n\tlong unsigned int file_pages;\n\tlong unsigned int bytes;\n};\n\nstruct bitmap {\n\tstruct bitmap_counts counts;\n\tstruct mddev *mddev;\n\t__u64 events_cleared;\n\tint need_sync;\n\tstruct bitmap_storage storage;\n\tlong unsigned int flags;\n\tint allclean;\n\tatomic_t behind_writes;\n\tlong unsigned int behind_writes_used;\n\tlong unsigned int daemon_lastrun;\n\tlong unsigned int last_end_sync;\n\tatomic_t pending_writes;\n\twait_queue_head_t write_wait;\n\twait_queue_head_t overflow_wait;\n\twait_queue_head_t behind_wait;\n\tstruct kernfs_node *sysfs_can_clear;\n\tint cluster_slot;\n};\n\nenum recovery_flags {\n\tMD_RECOVERY_RUNNING = 0,\n\tMD_RECOVERY_SYNC = 1,\n\tMD_RECOVERY_RECOVER = 2,\n\tMD_RECOVERY_INTR = 3,\n\tMD_RECOVERY_DONE = 4,\n\tMD_RECOVERY_NEEDED = 5,\n\tMD_RECOVERY_REQUESTED = 6,\n\tMD_RECOVERY_CHECK = 7,\n\tMD_RECOVERY_RESHAPE = 8,\n\tMD_RECOVERY_FROZEN = 9,\n\tMD_RECOVERY_ERROR = 10,\n\tMD_RECOVERY_WAIT = 11,\n\tMD_RESYNCING_REMOTE = 12,\n};\n\nstruct md_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct mddev *, char *);\n\tssize_t (*store)(struct mddev *, const char *, size_t);\n};\n\nstruct bitmap_page {\n\tchar *map;\n\tunsigned int hijacked: 1;\n\tunsigned int pending: 1;\n\tunsigned int count: 30;\n};\n\nstruct super_type {\n\tchar *name;\n\tstruct module *owner;\n\tint (*load_super)(struct md_rdev *, struct md_rdev *, int);\n\tint (*validate_super)(struct mddev *, struct md_rdev *);\n\tvoid (*sync_super)(struct mddev *, struct md_rdev *);\n\tlong long unsigned int (*rdev_size_change)(struct md_rdev *, sector_t);\n\tint (*allow_new_offset)(struct md_rdev *, long long unsigned int);\n};\n\nstruct rdev_sysfs_entry {\n\tstruct attribute attr;\n\tssize_t (*show)(struct md_rdev *, char *);\n\tssize_t (*store)(struct md_rdev *, const char *, size_t);\n};\n\nenum array_state {\n\tclear = 0,\n\tinactive = 1,\n\tsuspended = 2,\n\treadonly = 3,\n\tread_auto = 4,\n\tclean = 5,\n\tactive = 6,\n\twrite_pending = 7,\n\tactive_idle = 8,\n\tbroken = 9,\n\tbad_word = 10,\n};\n\nstruct detected_devices_node {\n\tstruct list_head list;\n\tdev_t dev;\n};\n\ntypedef __u16 bitmap_counter_t;\n\nenum bitmap_state {\n\tBITMAP_STALE = 1,\n\tBITMAP_WRITE_ERROR = 2,\n\tBITMAP_HOSTENDIAN = 15,\n};\n\nstruct bitmap_super_s {\n\t__le32 magic;\n\t__le32 version;\n\t__u8 uuid[16];\n\t__le64 events;\n\t__le64 events_cleared;\n\t__le64 sync_size;\n\t__le32 state;\n\t__le32 chunksize;\n\t__le32 daemon_sleep;\n\t__le32 write_behind;\n\t__le32 sectors_reserved;\n\t__le32 nodes;\n\t__u8 cluster_name[64];\n\t__u8 pad[120];\n};\n\ntypedef struct bitmap_super_s bitmap_super_t;\n\nenum bitmap_page_attr {\n\tBITMAP_PAGE_DIRTY = 0,\n\tBITMAP_PAGE_PENDING = 1,\n\tBITMAP_PAGE_NEEDWRITE = 2,\n};\n\nenum dm_queue_mode {\n\tDM_TYPE_NONE = 0,\n\tDM_TYPE_BIO_BASED = 1,\n\tDM_TYPE_REQUEST_BASED = 2,\n\tDM_TYPE_DAX_BIO_BASED = 3,\n\tDM_TYPE_NVME_BIO_BASED = 4,\n};\n\ntypedef enum {\n\tSTATUSTYPE_INFO = 0,\n\tSTATUSTYPE_TABLE = 1,\n} status_type_t;\n\nunion map_info___2 {\n\tvoid *ptr;\n};\n\nstruct dm_target;\n\ntypedef int (*dm_ctr_fn)(struct dm_target *, unsigned int, char **);\n\nstruct dm_table;\n\nstruct target_type;\n\nstruct dm_target {\n\tstruct dm_table *table;\n\tstruct target_type *type;\n\tsector_t begin;\n\tsector_t len;\n\tuint32_t max_io_len;\n\tunsigned int num_flush_bios;\n\tunsigned int num_discard_bios;\n\tunsigned int num_secure_erase_bios;\n\tunsigned int num_write_same_bios;\n\tunsigned int num_write_zeroes_bios;\n\tunsigned int per_io_data_size;\n\tvoid *private;\n\tchar *error;\n\tbool flush_supported: 1;\n\tbool discards_supported: 1;\n};\n\ntypedef void (*dm_dtr_fn)(struct dm_target *);\n\ntypedef int (*dm_map_fn)(struct dm_target *, struct bio *);\n\ntypedef int (*dm_clone_and_map_request_fn)(struct dm_target *, struct request *, union map_info___2 *, struct request **);\n\ntypedef void (*dm_release_clone_request_fn)(struct request *, union map_info___2 *);\n\ntypedef int (*dm_endio_fn)(struct dm_target *, struct bio *, blk_status_t *);\n\ntypedef int (*dm_request_endio_fn)(struct dm_target *, struct request *, blk_status_t, union map_info___2 *);\n\ntypedef void (*dm_presuspend_fn)(struct dm_target *);\n\ntypedef void (*dm_presuspend_undo_fn)(struct dm_target *);\n\ntypedef void (*dm_postsuspend_fn)(struct dm_target *);\n\ntypedef int (*dm_preresume_fn)(struct dm_target *);\n\ntypedef void (*dm_resume_fn)(struct dm_target *);\n\ntypedef void (*dm_status_fn)(struct dm_target *, status_type_t, unsigned int, char *, unsigned int);\n\ntypedef int (*dm_message_fn)(struct dm_target *, unsigned int, char **, char *, unsigned int);\n\ntypedef int (*dm_prepare_ioctl_fn)(struct dm_target *, struct block_device **);\n\nstruct dm_dev;\n\ntypedef int (*iterate_devices_callout_fn)(struct dm_target *, struct dm_dev *, sector_t, sector_t, void *);\n\nstruct dm_dev {\n\tstruct block_device *bdev;\n\tstruct dax_device *dax_dev;\n\tfmode_t mode;\n\tchar name[16];\n};\n\ntypedef int (*dm_iterate_devices_fn)(struct dm_target *, iterate_devices_callout_fn, void *);\n\ntypedef void (*dm_io_hints_fn)(struct dm_target *, struct queue_limits *);\n\ntypedef int (*dm_busy_fn)(struct dm_target *);\n\ntypedef long int (*dm_dax_direct_access_fn)(struct dm_target *, long unsigned int, long int, void **, pfn_t *);\n\ntypedef size_t (*dm_dax_copy_iter_fn)(struct dm_target *, long unsigned int, void *, size_t, struct iov_iter *);\n\ntypedef int (*dm_dax_zero_page_range_fn)(struct dm_target *, long unsigned int, size_t);\n\nstruct target_type {\n\tuint64_t features;\n\tconst char *name;\n\tstruct module *module;\n\tunsigned int version[3];\n\tdm_ctr_fn ctr;\n\tdm_dtr_fn dtr;\n\tdm_map_fn map;\n\tdm_clone_and_map_request_fn clone_and_map_rq;\n\tdm_release_clone_request_fn release_clone_rq;\n\tdm_endio_fn end_io;\n\tdm_request_endio_fn rq_end_io;\n\tdm_presuspend_fn presuspend;\n\tdm_presuspend_undo_fn presuspend_undo;\n\tdm_postsuspend_fn postsuspend;\n\tdm_preresume_fn preresume;\n\tdm_resume_fn resume;\n\tdm_status_fn status;\n\tdm_message_fn message;\n\tdm_prepare_ioctl_fn prepare_ioctl;\n\tdm_busy_fn busy;\n\tdm_iterate_devices_fn iterate_devices;\n\tdm_io_hints_fn io_hints;\n\tdm_dax_direct_access_fn direct_access;\n\tdm_dax_copy_iter_fn dax_copy_from_iter;\n\tdm_dax_copy_iter_fn dax_copy_to_iter;\n\tdm_dax_zero_page_range_fn dax_zero_page_range;\n\tstruct list_head list;\n};\n\nstruct dm_stats_last_position;\n\nstruct dm_stats {\n\tstruct mutex mutex;\n\tstruct list_head list;\n\tstruct dm_stats_last_position *last;\n\tsector_t last_sector;\n\tunsigned int last_rw;\n};\n\nstruct dm_stats_aux {\n\tbool merged;\n\tlong long unsigned int duration_ns;\n};\n\nstruct dm_kobject_holder {\n\tstruct kobject kobj;\n\tstruct completion completion;\n};\n\nstruct mapped_device {\n\tstruct mutex suspend_lock;\n\tstruct mutex table_devices_lock;\n\tstruct list_head table_devices;\n\tvoid *map;\n\tlong unsigned int flags;\n\tstruct mutex type_lock;\n\tenum dm_queue_mode type;\n\tint numa_node_id;\n\tstruct request_queue *queue;\n\tatomic_t holders;\n\tatomic_t open_count;\n\tstruct dm_target *immutable_target;\n\tstruct target_type *immutable_target_type;\n\tchar name[16];\n\tstruct gendisk *disk;\n\tstruct dax_device *dax_dev;\n\tstruct work_struct work;\n\twait_queue_head_t wait;\n\tspinlock_t deferred_lock;\n\tstruct bio_list deferred;\n\tvoid *interface_ptr;\n\twait_queue_head_t eventq;\n\tatomic_t event_nr;\n\tatomic_t uevent_seq;\n\tstruct list_head uevent_list;\n\tspinlock_t uevent_lock;\n\tunsigned int internal_suspend_count;\n\tstruct bio_set io_bs;\n\tstruct bio_set bs;\n\tstruct workqueue_struct *wq;\n\tstruct super_block *frozen_sb;\n\tstruct hd_geometry geometry;\n\tstruct dm_kobject_holder kobj_holder;\n\tstruct block_device *bdev;\n\tstruct dm_stats stats;\n\tstruct blk_mq_tag_set *tag_set;\n\tbool init_tio_pdu: 1;\n\tstruct srcu_struct io_barrier;\n};\n\nstruct dax_operations {\n\tlong int (*direct_access)(struct dax_device *, long unsigned int, long int, void **, pfn_t *);\n\tbool (*dax_supported)(struct dax_device *, struct block_device *, int, sector_t, sector_t);\n\tsize_t (*copy_from_iter)(struct dax_device *, long unsigned int, void *, size_t, struct iov_iter *);\n\tsize_t (*copy_to_iter)(struct dax_device *, long unsigned int, void *, size_t, struct iov_iter *);\n\tint (*zero_page_range)(struct dax_device *, long unsigned int, size_t);\n};\n\nstruct dm_io;\n\nstruct clone_info {\n\tstruct dm_table *map;\n\tstruct bio *bio;\n\tstruct dm_io *io;\n\tsector_t sector;\n\tunsigned int sector_count;\n};\n\nstruct dm_target_io {\n\tunsigned int magic;\n\tstruct dm_io *io;\n\tstruct dm_target *ti;\n\tunsigned int target_bio_nr;\n\tunsigned int *len_ptr;\n\tbool inside_dm_io;\n\tstruct bio clone;\n};\n\nstruct dm_io {\n\tunsigned int magic;\n\tstruct mapped_device *md;\n\tblk_status_t status;\n\tatomic_t io_count;\n\tstruct bio *orig_bio;\n\tlong unsigned int start_time;\n\tspinlock_t endio_lock;\n\tstruct dm_stats_aux stats_aux;\n\tstruct dm_target_io tio;\n};\n\nstruct dm_md_mempools {\n\tstruct bio_set bs;\n\tstruct bio_set io_bs;\n};\n\nstruct table_device {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct dm_dev dm_dev;\n};\n\nstruct dm_pr {\n\tu64 old_key;\n\tu64 new_key;\n\tu32 flags;\n\tbool fail_early;\n};\n\nstruct dm_md_mempools___2;\n\nstruct dm_table {\n\tstruct mapped_device *md;\n\tenum dm_queue_mode type;\n\tunsigned int depth;\n\tunsigned int counts[16];\n\tsector_t *index[16];\n\tunsigned int num_targets;\n\tunsigned int num_allocated;\n\tsector_t *highs;\n\tstruct dm_target *targets;\n\tstruct target_type *immutable_target_type;\n\tbool integrity_supported: 1;\n\tbool singleton: 1;\n\tunsigned int integrity_added: 1;\n\tfmode_t mode;\n\tstruct list_head devices;\n\tvoid (*event_fn)(void *);\n\tvoid *event_context;\n\tstruct dm_md_mempools___2 *mempools;\n\tstruct list_head target_callbacks;\n};\n\nstruct dm_target_callbacks {\n\tstruct list_head list;\n\tint (*congested_fn)(struct dm_target_callbacks *, int);\n};\n\nstruct dm_arg_set {\n\tunsigned int argc;\n\tchar **argv;\n};\n\nstruct dm_arg {\n\tunsigned int min;\n\tunsigned int max;\n\tchar *error;\n};\n\nstruct dm_dev_internal {\n\tstruct list_head list;\n\trefcount_t count;\n\tstruct dm_dev *dm_dev;\n};\n\nenum suspend_mode {\n\tPRESUSPEND = 0,\n\tPRESUSPEND_UNDO = 1,\n\tPOSTSUSPEND = 2,\n};\n\nstruct linear_c {\n\tstruct dm_dev *dev;\n\tsector_t start;\n};\n\nstruct stripe {\n\tstruct dm_dev *dev;\n\tsector_t physical_start;\n\tatomic_t error_count;\n};\n\nstruct stripe_c {\n\tuint32_t stripes;\n\tint stripes_shift;\n\tsector_t stripe_width;\n\tuint32_t chunk_size;\n\tint chunk_size_shift;\n\tstruct dm_target *ti;\n\tstruct work_struct trigger_event;\n\tstruct stripe stripe[0];\n};\n\nstruct dm_ioctl {\n\t__u32 version[3];\n\t__u32 data_size;\n\t__u32 data_start;\n\t__u32 target_count;\n\t__s32 open_count;\n\t__u32 flags;\n\t__u32 event_nr;\n\t__u32 padding;\n\t__u64 dev;\n\tchar name[128];\n\tchar uuid[129];\n\tchar data[7];\n};\n\nstruct dm_target_spec {\n\t__u64 sector_start;\n\t__u64 length;\n\t__s32 status;\n\t__u32 next;\n\tchar target_type[16];\n};\n\nstruct dm_target_deps {\n\t__u32 count;\n\t__u32 padding;\n\t__u64 dev[0];\n};\n\nstruct dm_name_list {\n\t__u64 dev;\n\t__u32 next;\n\tchar name[0];\n};\n\nstruct dm_target_versions {\n\t__u32 next;\n\t__u32 version[3];\n\tchar name[0];\n};\n\nstruct dm_target_msg {\n\t__u64 sector;\n\tchar message[0];\n};\n\nenum {\n\tDM_VERSION_CMD = 0,\n\tDM_REMOVE_ALL_CMD = 1,\n\tDM_LIST_DEVICES_CMD = 2,\n\tDM_DEV_CREATE_CMD = 3,\n\tDM_DEV_REMOVE_CMD = 4,\n\tDM_DEV_RENAME_CMD = 5,\n\tDM_DEV_SUSPEND_CMD = 6,\n\tDM_DEV_STATUS_CMD = 7,\n\tDM_DEV_WAIT_CMD = 8,\n\tDM_TABLE_LOAD_CMD = 9,\n\tDM_TABLE_CLEAR_CMD = 10,\n\tDM_TABLE_DEPS_CMD = 11,\n\tDM_TABLE_STATUS_CMD = 12,\n\tDM_LIST_VERSIONS_CMD = 13,\n\tDM_TARGET_MSG_CMD = 14,\n\tDM_DEV_SET_GEOMETRY_CMD = 15,\n\tDM_DEV_ARM_POLL_CMD = 16,\n\tDM_GET_TARGET_VERSION_CMD = 17,\n};\n\nstruct dm_file {\n\tvolatile unsigned int global_event_nr;\n};\n\nstruct hash_cell {\n\tstruct list_head name_list;\n\tstruct list_head uuid_list;\n\tchar *name;\n\tchar *uuid;\n\tstruct mapped_device *md;\n\tstruct dm_table *new_map;\n};\n\nstruct vers_iter {\n\tsize_t param_size;\n\tstruct dm_target_versions *vers;\n\tstruct dm_target_versions *old_vers;\n\tchar *end;\n\tuint32_t flags;\n};\n\ntypedef int (*ioctl_fn___2)(struct file *, struct dm_ioctl *, size_t);\n\nstruct dm_io_region {\n\tstruct block_device *bdev;\n\tsector_t sector;\n\tsector_t count;\n};\n\nstruct page_list {\n\tstruct page_list *next;\n\tstruct page *page;\n};\n\ntypedef void (*io_notify_fn)(long unsigned int, void *);\n\nenum dm_io_mem_type {\n\tDM_IO_PAGE_LIST = 0,\n\tDM_IO_BIO = 1,\n\tDM_IO_VMA = 2,\n\tDM_IO_KMEM = 3,\n};\n\nstruct dm_io_memory {\n\tenum dm_io_mem_type type;\n\tunsigned int offset;\n\tunion {\n\t\tstruct page_list *pl;\n\t\tstruct bio *bio;\n\t\tvoid *vma;\n\t\tvoid *addr;\n\t} ptr;\n};\n\nstruct dm_io_notify {\n\tio_notify_fn fn;\n\tvoid *context;\n};\n\nstruct dm_io_client;\n\nstruct dm_io_request {\n\tint bi_op;\n\tint bi_op_flags;\n\tstruct dm_io_memory mem;\n\tstruct dm_io_notify notify;\n\tstruct dm_io_client *client;\n};\n\nstruct dm_io_client {\n\tmempool_t pool;\n\tstruct bio_set bios;\n};\n\nstruct io {\n\tlong unsigned int error_bits;\n\tatomic_t count;\n\tstruct dm_io_client *client;\n\tio_notify_fn callback;\n\tvoid *context;\n\tvoid *vma_invalidate_address;\n\tlong unsigned int vma_invalidate_size;\n\tlong: 64;\n};\n\nstruct dpages {\n\tvoid (*get_page)(struct dpages *, struct page **, long unsigned int *, unsigned int *);\n\tvoid (*next_page)(struct dpages *);\n\tunion {\n\t\tunsigned int context_u;\n\t\tstruct bvec_iter context_bi;\n\t};\n\tvoid *context_ptr;\n\tvoid *vma_invalidate_address;\n\tlong unsigned int vma_invalidate_size;\n};\n\nstruct sync_io {\n\tlong unsigned int error_bits;\n\tstruct completion wait;\n};\n\nstruct dm_kcopyd_throttle {\n\tunsigned int throttle;\n\tunsigned int num_io_jobs;\n\tunsigned int io_period;\n\tunsigned int total_period;\n\tunsigned int last_jiffies;\n};\n\ntypedef void (*dm_kcopyd_notify_fn)(int, long unsigned int, void *);\n\nstruct dm_kcopyd_client {\n\tstruct page_list *pages;\n\tunsigned int nr_reserved_pages;\n\tunsigned int nr_free_pages;\n\tunsigned int sub_job_size;\n\tstruct dm_io_client *io_client;\n\twait_queue_head_t destroyq;\n\tmempool_t job_pool;\n\tstruct workqueue_struct *kcopyd_wq;\n\tstruct work_struct kcopyd_work;\n\tstruct dm_kcopyd_throttle *throttle;\n\tatomic_t nr_jobs;\n\tspinlock_t job_lock;\n\tstruct list_head callback_jobs;\n\tstruct list_head complete_jobs;\n\tstruct list_head io_jobs;\n\tstruct list_head pages_jobs;\n};\n\nstruct kcopyd_job {\n\tstruct dm_kcopyd_client *kc;\n\tstruct list_head list;\n\tlong unsigned int flags;\n\tint read_err;\n\tlong unsigned int write_err;\n\tint rw;\n\tstruct dm_io_region source;\n\tunsigned int num_dests;\n\tstruct dm_io_region dests[8];\n\tstruct page_list *pages;\n\tdm_kcopyd_notify_fn fn;\n\tvoid *context;\n\tstruct mutex lock;\n\tatomic_t sub_jobs;\n\tsector_t progress;\n\tsector_t write_offset;\n\tstruct kcopyd_job *master_job;\n};\n\nstruct dm_sysfs_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct mapped_device *, char *);\n\tssize_t (*store)(struct mapped_device *, const char *, size_t);\n};\n\nstruct dm_stats_last_position {\n\tsector_t last_sector;\n\tunsigned int last_rw;\n};\n\nstruct dm_stat_percpu {\n\tlong long unsigned int sectors[2];\n\tlong long unsigned int ios[2];\n\tlong long unsigned int merges[2];\n\tlong long unsigned int ticks[2];\n\tlong long unsigned int io_ticks[2];\n\tlong long unsigned int io_ticks_total;\n\tlong long unsigned int time_in_queue;\n\tlong long unsigned int *histogram;\n};\n\nstruct dm_stat_shared {\n\tatomic_t in_flight[2];\n\tlong long unsigned int stamp;\n\tstruct dm_stat_percpu tmp;\n};\n\nstruct dm_stat {\n\tstruct list_head list_entry;\n\tint id;\n\tunsigned int stat_flags;\n\tsize_t n_entries;\n\tsector_t start;\n\tsector_t end;\n\tsector_t step;\n\tunsigned int n_histogram_entries;\n\tlong long unsigned int *histogram_boundaries;\n\tconst char *program_id;\n\tconst char *aux_data;\n\tstruct callback_head callback_head;\n\tsize_t shared_alloc_size;\n\tsize_t percpu_alloc_size;\n\tsize_t histogram_alloc_size;\n\tstruct dm_stat_percpu *stat_percpu[64];\n\tstruct dm_stat_shared stat_shared[0];\n};\n\nstruct dm_rq_target_io;\n\nstruct dm_rq_clone_bio_info {\n\tstruct bio *orig;\n\tstruct dm_rq_target_io *tio;\n\tstruct bio clone;\n};\n\nstruct dm_rq_target_io {\n\tstruct mapped_device *md;\n\tstruct dm_target *ti;\n\tstruct request *orig;\n\tstruct request *clone;\n\tstruct kthread_work work;\n\tblk_status_t error;\n\tunion map_info___2 info;\n\tstruct dm_stats_aux stats_aux;\n\tlong unsigned int duration_jiffies;\n\tunsigned int n_sectors;\n\tunsigned int completed;\n};\n\nstruct dm_bio_details {\n\tstruct gendisk *bi_disk;\n\tu8 bi_partno;\n\tint __bi_remaining;\n\tlong unsigned int bi_flags;\n\tstruct bvec_iter bi_iter;\n\tbio_end_io_t *bi_end_io;\n};\n\ntypedef sector_t region_t;\n\nstruct dm_dirty_log_type;\n\nstruct dm_dirty_log {\n\tstruct dm_dirty_log_type *type;\n\tint (*flush_callback_fn)(struct dm_target *);\n\tvoid *context;\n};\n\nstruct dm_dirty_log_type {\n\tconst char *name;\n\tstruct module *module;\n\tstruct list_head list;\n\tint (*ctr)(struct dm_dirty_log *, struct dm_target *, unsigned int, char **);\n\tvoid (*dtr)(struct dm_dirty_log *);\n\tint (*presuspend)(struct dm_dirty_log *);\n\tint (*postsuspend)(struct dm_dirty_log *);\n\tint (*resume)(struct dm_dirty_log *);\n\tuint32_t (*get_region_size)(struct dm_dirty_log *);\n\tint (*is_clean)(struct dm_dirty_log *, region_t);\n\tint (*in_sync)(struct dm_dirty_log *, region_t, int);\n\tint (*flush)(struct dm_dirty_log *);\n\tvoid (*mark_region)(struct dm_dirty_log *, region_t);\n\tvoid (*clear_region)(struct dm_dirty_log *, region_t);\n\tint (*get_resync_work)(struct dm_dirty_log *, region_t *);\n\tvoid (*set_region_sync)(struct dm_dirty_log *, region_t, int);\n\tregion_t (*get_sync_count)(struct dm_dirty_log *);\n\tint (*status)(struct dm_dirty_log *, status_type_t, char *, unsigned int);\n\tint (*is_remote_recovering)(struct dm_dirty_log *, region_t);\n};\n\nenum dm_rh_region_states {\n\tDM_RH_CLEAN = 1,\n\tDM_RH_DIRTY = 2,\n\tDM_RH_NOSYNC = 4,\n\tDM_RH_RECOVERING = 8,\n};\n\nenum dm_raid1_error {\n\tDM_RAID1_WRITE_ERROR = 0,\n\tDM_RAID1_FLUSH_ERROR = 1,\n\tDM_RAID1_SYNC_ERROR = 2,\n\tDM_RAID1_READ_ERROR = 3,\n};\n\nstruct mirror_set;\n\nstruct mirror {\n\tstruct mirror_set *ms;\n\tatomic_t error_count;\n\tlong unsigned int error_type;\n\tstruct dm_dev *dev;\n\tsector_t offset;\n};\n\nstruct dm_region_hash;\n\nstruct dm_kcopyd_client___2;\n\nstruct mirror_set {\n\tstruct dm_target *ti;\n\tstruct list_head list;\n\tuint64_t features;\n\tspinlock_t lock;\n\tstruct bio_list reads;\n\tstruct bio_list writes;\n\tstruct bio_list failures;\n\tstruct bio_list holds;\n\tstruct dm_region_hash *rh;\n\tstruct dm_kcopyd_client___2 *kcopyd_client;\n\tstruct dm_io_client *io_client;\n\tregion_t nr_regions;\n\tint in_sync;\n\tint log_failure;\n\tint leg_failure;\n\tatomic_t suspend;\n\tatomic_t default_mirror;\n\tstruct workqueue_struct *kmirrord_wq;\n\tstruct work_struct kmirrord_work;\n\tstruct timer_list timer;\n\tlong unsigned int timer_pending;\n\tstruct work_struct trigger_event;\n\tunsigned int nr_mirrors;\n\tstruct mirror mirror[0];\n};\n\nstruct dm_raid1_bio_record {\n\tstruct mirror *m;\n\tstruct dm_bio_details details;\n\tregion_t write_region;\n};\n\nstruct dm_region;\n\nstruct log_header_disk {\n\t__le32 magic;\n\t__le32 version;\n\t__le64 nr_regions;\n};\n\nstruct log_header_core {\n\tuint32_t magic;\n\tuint32_t version;\n\tuint64_t nr_regions;\n};\n\nenum sync {\n\tDEFAULTSYNC = 0,\n\tNOSYNC = 1,\n\tFORCESYNC = 2,\n};\n\nstruct log_c {\n\tstruct dm_target *ti;\n\tint touched_dirtied;\n\tint touched_cleaned;\n\tint flush_failed;\n\tuint32_t region_size;\n\tunsigned int region_count;\n\tregion_t sync_count;\n\tunsigned int bitset_uint32_count;\n\tuint32_t *clean_bits;\n\tuint32_t *sync_bits;\n\tuint32_t *recovering_bits;\n\tint sync_search;\n\tenum sync sync;\n\tstruct dm_io_request io_req;\n\tint log_dev_failed;\n\tint log_dev_flush_failed;\n\tstruct dm_dev *log_dev;\n\tstruct log_header_core header;\n\tstruct dm_io_region header_location;\n\tstruct log_header_disk *disk_header;\n};\n\nstruct dm_region_hash___2 {\n\tuint32_t region_size;\n\tunsigned int region_shift;\n\tstruct dm_dirty_log *log;\n\trwlock_t hash_lock;\n\tunsigned int mask;\n\tunsigned int nr_buckets;\n\tunsigned int prime;\n\tunsigned int shift;\n\tstruct list_head *buckets;\n\tint flush_failure;\n\tunsigned int max_recovery;\n\tspinlock_t region_lock;\n\tatomic_t recovery_in_flight;\n\tstruct list_head clean_regions;\n\tstruct list_head quiesced_regions;\n\tstruct list_head recovered_regions;\n\tstruct list_head failed_recovered_regions;\n\tstruct semaphore recovery_count;\n\tmempool_t region_pool;\n\tvoid *context;\n\tsector_t target_begin;\n\tvoid (*dispatch_bios)(void *, struct bio_list *);\n\tvoid (*wakeup_workers)(void *);\n\tvoid (*wakeup_all_recovery_waiters)(void *);\n};\n\nstruct dm_region___2 {\n\tstruct dm_region_hash___2 *rh;\n\tregion_t key;\n\tint state;\n\tstruct list_head hash_list;\n\tstruct list_head list;\n\tatomic_t pending;\n\tstruct bio_list delayed_bios;\n};\n\nenum dev_type {\n\tDEV_UNKNOWN = 0,\n\tDEV_X1 = 1,\n\tDEV_X2 = 2,\n\tDEV_X4 = 3,\n\tDEV_X8 = 4,\n\tDEV_X16 = 5,\n\tDEV_X32 = 6,\n\tDEV_X64 = 7,\n};\n\nenum hw_event_mc_err_type {\n\tHW_EVENT_ERR_CORRECTED = 0,\n\tHW_EVENT_ERR_UNCORRECTED = 1,\n\tHW_EVENT_ERR_DEFERRED = 2,\n\tHW_EVENT_ERR_FATAL = 3,\n\tHW_EVENT_ERR_INFO = 4,\n};\n\nenum mem_type {\n\tMEM_EMPTY = 0,\n\tMEM_RESERVED = 1,\n\tMEM_UNKNOWN = 2,\n\tMEM_FPM = 3,\n\tMEM_EDO = 4,\n\tMEM_BEDO = 5,\n\tMEM_SDR = 6,\n\tMEM_RDR = 7,\n\tMEM_DDR = 8,\n\tMEM_RDDR = 9,\n\tMEM_RMBS = 10,\n\tMEM_DDR2 = 11,\n\tMEM_FB_DDR2 = 12,\n\tMEM_RDDR2 = 13,\n\tMEM_XDR = 14,\n\tMEM_DDR3 = 15,\n\tMEM_RDDR3 = 16,\n\tMEM_LRDDR3 = 17,\n\tMEM_DDR4 = 18,\n\tMEM_RDDR4 = 19,\n\tMEM_LRDDR4 = 20,\n\tMEM_NVDIMM = 21,\n};\n\nenum edac_type {\n\tEDAC_UNKNOWN = 0,\n\tEDAC_NONE = 1,\n\tEDAC_RESERVED = 2,\n\tEDAC_PARITY = 3,\n\tEDAC_EC = 4,\n\tEDAC_SECDED = 5,\n\tEDAC_S2ECD2ED = 6,\n\tEDAC_S4ECD4ED = 7,\n\tEDAC_S8ECD8ED = 8,\n\tEDAC_S16ECD16ED = 9,\n};\n\nenum scrub_type {\n\tSCRUB_UNKNOWN = 0,\n\tSCRUB_NONE = 1,\n\tSCRUB_SW_PROG = 2,\n\tSCRUB_SW_SRC = 3,\n\tSCRUB_SW_PROG_SRC = 4,\n\tSCRUB_SW_TUNABLE = 5,\n\tSCRUB_HW_PROG = 6,\n\tSCRUB_HW_SRC = 7,\n\tSCRUB_HW_PROG_SRC = 8,\n\tSCRUB_HW_TUNABLE = 9,\n};\n\nenum edac_mc_layer_type {\n\tEDAC_MC_LAYER_BRANCH = 0,\n\tEDAC_MC_LAYER_CHANNEL = 1,\n\tEDAC_MC_LAYER_SLOT = 2,\n\tEDAC_MC_LAYER_CHIP_SELECT = 3,\n\tEDAC_MC_LAYER_ALL_MEM = 4,\n};\n\nstruct edac_mc_layer {\n\tenum edac_mc_layer_type type;\n\tunsigned int size;\n\tbool is_virt_csrow;\n};\n\nstruct mem_ctl_info;\n\nstruct dimm_info {\n\tstruct device dev;\n\tchar label[32];\n\tunsigned int location[3];\n\tstruct mem_ctl_info *mci;\n\tunsigned int idx;\n\tu32 grain;\n\tenum dev_type dtype;\n\tenum mem_type mtype;\n\tenum edac_type edac_mode;\n\tu32 nr_pages;\n\tunsigned int csrow;\n\tunsigned int cschannel;\n\tu16 smbios_handle;\n\tu32 ce_count;\n\tu32 ue_count;\n};\n\nstruct mcidev_sysfs_attribute;\n\nstruct edac_raw_error_desc {\n\tchar location[256];\n\tchar label[296];\n\tlong int grain;\n\tu16 error_count;\n\tenum hw_event_mc_err_type type;\n\tint top_layer;\n\tint mid_layer;\n\tint low_layer;\n\tlong unsigned int page_frame_number;\n\tlong unsigned int offset_in_page;\n\tlong unsigned int syndrome;\n\tconst char *msg;\n\tconst char *other_detail;\n};\n\nstruct csrow_info;\n\nstruct mem_ctl_info {\n\tstruct device dev;\n\tstruct bus_type *bus;\n\tstruct list_head link;\n\tstruct module *owner;\n\tlong unsigned int mtype_cap;\n\tlong unsigned int edac_ctl_cap;\n\tlong unsigned int edac_cap;\n\tlong unsigned int scrub_cap;\n\tenum scrub_type scrub_mode;\n\tint (*set_sdram_scrub_rate)(struct mem_ctl_info *, u32);\n\tint (*get_sdram_scrub_rate)(struct mem_ctl_info *);\n\tvoid (*edac_check)(struct mem_ctl_info *);\n\tlong unsigned int (*ctl_page_to_phys)(struct mem_ctl_info *, long unsigned int);\n\tint mc_idx;\n\tstruct csrow_info **csrows;\n\tunsigned int nr_csrows;\n\tunsigned int num_cschannel;\n\tunsigned int n_layers;\n\tstruct edac_mc_layer *layers;\n\tbool csbased;\n\tunsigned int tot_dimms;\n\tstruct dimm_info **dimms;\n\tstruct device *pdev;\n\tconst char *mod_name;\n\tconst char *ctl_name;\n\tconst char *dev_name;\n\tvoid *pvt_info;\n\tlong unsigned int start_time;\n\tu32 ce_noinfo_count;\n\tu32 ue_noinfo_count;\n\tu32 ue_mc;\n\tu32 ce_mc;\n\tstruct completion complete;\n\tconst struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;\n\tstruct delayed_work work;\n\tstruct edac_raw_error_desc error_desc;\n\tint op_state;\n\tstruct dentry *debugfs;\n\tu8 fake_inject_layer[3];\n\tbool fake_inject_ue;\n\tu16 fake_inject_count;\n};\n\nstruct rank_info {\n\tint chan_idx;\n\tstruct csrow_info *csrow;\n\tstruct dimm_info *dimm;\n\tu32 ce_count;\n};\n\nstruct csrow_info {\n\tstruct device dev;\n\tlong unsigned int first_page;\n\tlong unsigned int last_page;\n\tlong unsigned int page_mask;\n\tint csrow_idx;\n\tu32 ue_count;\n\tu32 ce_count;\n\tstruct mem_ctl_info *mci;\n\tu32 nr_channels;\n\tstruct rank_info **channels;\n};\n\nstruct edac_device_counter {\n\tu32 ue_count;\n\tu32 ce_count;\n};\n\nstruct edac_device_ctl_info;\n\nstruct edac_dev_sysfs_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_device_ctl_info *, char *);\n\tssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);\n};\n\nstruct edac_device_instance;\n\nstruct edac_device_ctl_info {\n\tstruct list_head link;\n\tstruct module *owner;\n\tint dev_idx;\n\tint log_ue;\n\tint log_ce;\n\tint panic_on_ue;\n\tunsigned int poll_msec;\n\tlong unsigned int delay;\n\tstruct edac_dev_sysfs_attribute *sysfs_attributes;\n\tstruct bus_type *edac_subsys;\n\tint op_state;\n\tstruct delayed_work work;\n\tvoid (*edac_check)(struct edac_device_ctl_info *);\n\tstruct device *dev;\n\tconst char *mod_name;\n\tconst char *ctl_name;\n\tconst char *dev_name;\n\tvoid *pvt_info;\n\tlong unsigned int start_time;\n\tstruct completion removal_complete;\n\tchar name[32];\n\tu32 nr_instances;\n\tstruct edac_device_instance *instances;\n\tstruct edac_device_counter counters;\n\tstruct kobject kobj;\n};\n\nstruct edac_device_block;\n\nstruct edac_dev_sysfs_block_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct kobject *, struct attribute *, char *);\n\tssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t);\n\tstruct edac_device_block *block;\n\tunsigned int value;\n};\n\nstruct edac_device_block {\n\tstruct edac_device_instance *instance;\n\tchar name[32];\n\tstruct edac_device_counter counters;\n\tint nr_attribs;\n\tstruct edac_dev_sysfs_block_attribute *block_attributes;\n\tstruct kobject kobj;\n};\n\nstruct edac_device_instance {\n\tstruct edac_device_ctl_info *ctl;\n\tchar name[35];\n\tstruct edac_device_counter counters;\n\tu32 nr_blocks;\n\tstruct edac_device_block *blocks;\n\tstruct kobject kobj;\n};\n\nstruct dev_ch_attribute {\n\tstruct device_attribute attr;\n\tunsigned int channel;\n};\n\nstruct ctl_info_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_device_ctl_info *, char *);\n\tssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);\n};\n\nstruct instance_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_device_instance *, char *);\n\tssize_t (*store)(struct edac_device_instance *, const char *, size_t);\n};\n\nstruct edac_pci_counter {\n\tatomic_t pe_count;\n\tatomic_t npe_count;\n};\n\nstruct edac_pci_ctl_info {\n\tstruct list_head link;\n\tint pci_idx;\n\tstruct bus_type *edac_subsys;\n\tint op_state;\n\tstruct delayed_work work;\n\tvoid (*edac_check)(struct edac_pci_ctl_info *);\n\tstruct device *dev;\n\tconst char *mod_name;\n\tconst char *ctl_name;\n\tconst char *dev_name;\n\tvoid *pvt_info;\n\tlong unsigned int start_time;\n\tstruct completion complete;\n\tchar name[32];\n\tstruct edac_pci_counter counters;\n\tstruct kobject kobj;\n};\n\nstruct edac_pci_gen_data {\n\tint edac_idx;\n};\n\nstruct instance_attribute___2 {\n\tstruct attribute attr;\n\tssize_t (*show)(struct edac_pci_ctl_info *, char *);\n\tssize_t (*store)(struct edac_pci_ctl_info *, const char *, size_t);\n};\n\nstruct edac_pci_dev_attribute {\n\tstruct attribute attr;\n\tvoid *value;\n\tssize_t (*show)(void *, char *);\n\tssize_t (*store)(void *, const char *, size_t);\n};\n\ntypedef void (*pci_parity_check_fn_t)(struct pci_dev *);\n\nenum tt_ids {\n\tTT_INSTR = 0,\n\tTT_DATA = 1,\n\tTT_GEN = 2,\n\tTT_RESV = 3,\n};\n\nenum ll_ids {\n\tLL_RESV = 0,\n\tLL_L1 = 1,\n\tLL_L2 = 2,\n\tLL_LG = 3,\n};\n\nenum ii_ids {\n\tII_MEM = 0,\n\tII_RESV = 1,\n\tII_IO = 2,\n\tII_GEN = 3,\n};\n\nenum rrrr_ids {\n\tR4_GEN = 0,\n\tR4_RD = 1,\n\tR4_WR = 2,\n\tR4_DRD = 3,\n\tR4_DWR = 4,\n\tR4_IRD = 5,\n\tR4_PREF = 6,\n\tR4_EVICT = 7,\n\tR4_SNOOP = 8,\n};\n\nstruct amd_decoder_ops {\n\tbool (*mc0_mce)(u16, u8);\n\tbool (*mc1_mce)(u16, u8);\n\tbool (*mc2_mce)(u16, u8);\n};\n\nstruct smca_mce_desc {\n\tconst char * const *descs;\n\tunsigned int num_descs;\n};\n\nstruct cpufreq_policy_data {\n\tstruct cpufreq_cpuinfo cpuinfo;\n\tstruct cpufreq_frequency_table *freq_table;\n\tunsigned int cpu;\n\tunsigned int min;\n\tunsigned int max;\n};\n\nstruct cpufreq_driver {\n\tchar name[16];\n\tu8 flags;\n\tvoid *driver_data;\n\tint (*init)(struct cpufreq_policy *);\n\tint (*verify)(struct cpufreq_policy_data *);\n\tint (*setpolicy)(struct cpufreq_policy *);\n\tint (*target)(struct cpufreq_policy *, unsigned int, unsigned int);\n\tint (*target_index)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*fast_switch)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*resolve_freq)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*get_intermediate)(struct cpufreq_policy *, unsigned int);\n\tint (*target_intermediate)(struct cpufreq_policy *, unsigned int);\n\tunsigned int (*get)(unsigned int);\n\tvoid (*update_limits)(unsigned int);\n\tint (*bios_limit)(int, unsigned int *);\n\tint (*online)(struct cpufreq_policy *);\n\tint (*offline)(struct cpufreq_policy *);\n\tint (*exit)(struct cpufreq_policy *);\n\tvoid (*stop_cpu)(struct cpufreq_policy *);\n\tint (*suspend)(struct cpufreq_policy *);\n\tint (*resume)(struct cpufreq_policy *);\n\tvoid (*ready)(struct cpufreq_policy *);\n\tstruct freq_attr **attr;\n\tbool boost_enabled;\n\tint (*set_boost)(struct cpufreq_policy *, int);\n};\n\nenum {\n\tOD_NORMAL_SAMPLE = 0,\n\tOD_SUB_SAMPLE = 1,\n};\n\nstruct dbs_data {\n\tstruct gov_attr_set attr_set;\n\tvoid *tuners;\n\tunsigned int ignore_nice_load;\n\tunsigned int sampling_rate;\n\tunsigned int sampling_down_factor;\n\tunsigned int up_threshold;\n\tunsigned int io_is_busy;\n};\n\nstruct policy_dbs_info {\n\tstruct cpufreq_policy *policy;\n\tstruct mutex update_mutex;\n\tu64 last_sample_time;\n\ts64 sample_delay_ns;\n\tatomic_t work_count;\n\tstruct irq_work irq_work;\n\tstruct work_struct work;\n\tstruct dbs_data *dbs_data;\n\tstruct list_head list;\n\tunsigned int rate_mult;\n\tunsigned int idle_periods;\n\tbool is_shared;\n\tbool work_in_progress;\n};\n\nstruct dbs_governor {\n\tstruct cpufreq_governor gov;\n\tstruct kobj_type kobj_type;\n\tstruct dbs_data *gdbs_data;\n\tunsigned int (*gov_dbs_update)(struct cpufreq_policy *);\n\tstruct policy_dbs_info * (*alloc)();\n\tvoid (*free)(struct policy_dbs_info *);\n\tint (*init)(struct dbs_data *);\n\tvoid (*exit)(struct dbs_data *);\n\tvoid (*start)(struct cpufreq_policy *);\n};\n\nstruct od_ops {\n\tunsigned int (*powersave_bias_target)(struct cpufreq_policy *, unsigned int, unsigned int);\n};\n\nstruct od_policy_dbs_info {\n\tstruct policy_dbs_info policy_dbs;\n\tunsigned int freq_lo;\n\tunsigned int freq_lo_delay_us;\n\tunsigned int freq_hi_delay_us;\n\tunsigned int sample_type: 1;\n};\n\nstruct od_dbs_tuners {\n\tunsigned int powersave_bias;\n};\n\nstruct cpu_dbs_info {\n\tu64 prev_cpu_idle;\n\tu64 prev_update_time;\n\tu64 prev_cpu_nice;\n\tunsigned int prev_load;\n\tstruct update_util_data update_util;\n\tstruct policy_dbs_info *policy_dbs;\n};\n\nenum {\n\tUNDEFINED_CAPABLE = 0,\n\tSYSTEM_INTEL_MSR_CAPABLE = 1,\n\tSYSTEM_AMD_MSR_CAPABLE = 2,\n\tSYSTEM_IO_CAPABLE = 3,\n};\n\nstruct acpi_cpufreq_data {\n\tunsigned int resume;\n\tunsigned int cpu_feature;\n\tunsigned int acpi_perf_cpu;\n\tcpumask_var_t freqdomain_cpus;\n\tvoid (*cpu_freq_write)(struct acpi_pct_register *, u32);\n\tu32 (*cpu_freq_read)(struct acpi_pct_register *);\n};\n\nstruct drv_cmd {\n\tstruct acpi_pct_register *reg;\n\tu32 val;\n\tunion {\n\t\tvoid (*write)(struct acpi_pct_register *, u32);\n\t\tu32 (*read)(struct acpi_pct_register *);\n\t} func;\n};\n\nenum acpi_preferred_pm_profiles {\n\tPM_UNSPECIFIED = 0,\n\tPM_DESKTOP = 1,\n\tPM_MOBILE = 2,\n\tPM_WORKSTATION = 3,\n\tPM_ENTERPRISE_SERVER = 4,\n\tPM_SOHO_SERVER = 5,\n\tPM_APPLIANCE_PC = 6,\n\tPM_PERFORMANCE_SERVER = 7,\n\tPM_TABLET = 8,\n};\n\nstruct sample {\n\tint32_t core_avg_perf;\n\tint32_t busy_scaled;\n\tu64 aperf;\n\tu64 mperf;\n\tu64 tsc;\n\tu64 time;\n};\n\nstruct pstate_data {\n\tint current_pstate;\n\tint min_pstate;\n\tint max_pstate;\n\tint max_pstate_physical;\n\tint scaling;\n\tint turbo_pstate;\n\tunsigned int max_freq;\n\tunsigned int turbo_freq;\n};\n\nstruct vid_data {\n\tint min;\n\tint max;\n\tint turbo;\n\tint32_t ratio;\n};\n\nstruct global_params {\n\tbool no_turbo;\n\tbool turbo_disabled;\n\tbool turbo_disabled_mf;\n\tint max_perf_pct;\n\tint min_perf_pct;\n};\n\nstruct cpudata {\n\tint cpu;\n\tunsigned int policy;\n\tstruct update_util_data update_util;\n\tbool update_util_set;\n\tstruct pstate_data pstate;\n\tstruct vid_data vid;\n\tu64 last_update;\n\tu64 last_sample_time;\n\tu64 aperf_mperf_shift;\n\tu64 prev_aperf;\n\tu64 prev_mperf;\n\tu64 prev_tsc;\n\tu64 prev_cummulative_iowait;\n\tstruct sample sample;\n\tint32_t min_perf_ratio;\n\tint32_t max_perf_ratio;\n\tstruct acpi_processor_performance acpi_perf_data;\n\tbool valid_pss_table;\n\tunsigned int iowait_boost;\n\ts16 epp_powersave;\n\ts16 epp_policy;\n\ts16 epp_default;\n\ts16 epp_saved;\n\tu64 hwp_req_cached;\n\tu64 hwp_cap_cached;\n\tu64 last_io_update;\n\tunsigned int sched_flags;\n\tu32 hwp_boost_min;\n};\n\nstruct pstate_funcs {\n\tint (*get_max)();\n\tint (*get_max_physical)();\n\tint (*get_min)();\n\tint (*get_turbo)();\n\tint (*get_scaling)();\n\tint (*get_aperf_mperf_shift)();\n\tu64 (*get_val)(struct cpudata *, int);\n\tvoid (*get_vid)(struct cpudata *);\n};\n\nenum {\n\tPSS = 0,\n\tPPC = 1,\n};\n\nstruct cpuidle_governor {\n\tchar name[16];\n\tstruct list_head governor_list;\n\tunsigned int rating;\n\tint (*enable)(struct cpuidle_driver___2 *, struct cpuidle_device *);\n\tvoid (*disable)(struct cpuidle_driver___2 *, struct cpuidle_device *);\n\tint (*select)(struct cpuidle_driver___2 *, struct cpuidle_device *, bool *);\n\tvoid (*reflect)(struct cpuidle_device *, int);\n};\n\nstruct cpuidle_state_kobj {\n\tstruct cpuidle_state *state;\n\tstruct cpuidle_state_usage *state_usage;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n\tstruct cpuidle_device *device;\n};\n\nstruct cpuidle_device_kobj {\n\tstruct cpuidle_device *dev;\n\tstruct completion kobj_unregister;\n\tstruct kobject kobj;\n};\n\nstruct cpuidle_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_device *, char *);\n\tssize_t (*store)(struct cpuidle_device *, const char *, size_t);\n};\n\nstruct cpuidle_state_attr {\n\tstruct attribute attr;\n\tssize_t (*show)(struct cpuidle_state *, struct cpuidle_state_usage *, char *);\n\tssize_t (*store)(struct cpuidle_state *, struct cpuidle_state_usage *, const char *, size_t);\n};\n\nstruct menu_device {\n\tint needs_update;\n\tint tick_wakeup;\n\tu64 next_timer_ns;\n\tunsigned int bucket;\n\tunsigned int correction_factor[12];\n\tunsigned int intervals[8];\n\tint interval_ptr;\n};\n\nstruct led_init_data {\n\tstruct fwnode_handle *fwnode;\n\tconst char *default_label;\n\tconst char *devicename;\n\tbool devname_mandatory;\n};\n\nstruct led_properties {\n\tu32 color;\n\tbool color_present;\n\tconst char *function;\n\tu32 func_enum;\n\tbool func_enum_present;\n\tconst char *label;\n};\n\nstruct dmi_memdev_info {\n\tconst char *device;\n\tconst char *bank;\n\tu64 size;\n\tu16 handle;\n\tu8 type;\n};\n\nstruct dmi_device_attribute {\n\tstruct device_attribute dev_attr;\n\tint field;\n};\n\nstruct mafield {\n\tconst char *prefix;\n\tint field;\n};\n\nstruct firmware_map_entry {\n\tu64 start;\n\tu64 end;\n\tconst char *type;\n\tstruct list_head list;\n\tstruct kobject kobj;\n};\n\nstruct memmap_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct firmware_map_entry *, char *);\n};\n\nstruct bmp_header {\n\tu16 id;\n\tu32 size;\n} __attribute__((packed));\n\ntypedef efi_status_t efi_query_variable_store_t(u32, long unsigned int, bool);\n\ntypedef struct {\n\tefi_guid_t guid;\n\tu32 table;\n} efi_config_table_32_t;\n\ntypedef union {\n\tstruct {\n\t\tefi_guid_t guid;\n\t\tvoid *table;\n\t};\n\tefi_config_table_32_t mixed_mode;\n} efi_config_table_t;\n\ntypedef struct {\n\tu16 version;\n\tu16 length;\n\tu32 runtime_services_supported;\n} efi_rt_properties_table_t;\n\nstruct efivar_operations {\n\tefi_get_variable_t *get_variable;\n\tefi_get_next_variable_t *get_next_variable;\n\tefi_set_variable_t *set_variable;\n\tefi_set_variable_t *set_variable_nonblocking;\n\tefi_query_variable_store_t *query_variable_store;\n};\n\nstruct efivars {\n\tstruct kset *kset;\n\tstruct kobject *kobject;\n\tconst struct efivar_operations *ops;\n};\n\nstruct efi_variable {\n\tefi_char16_t VariableName[512];\n\tefi_guid_t VendorGuid;\n\tlong unsigned int DataSize;\n\t__u8 Data[1024];\n\tefi_status_t Status;\n\t__u32 Attributes;\n} __attribute__((packed));\n\nstruct efivar_entry {\n\tstruct efi_variable var;\n\tstruct list_head list;\n\tstruct kobject kobj;\n\tbool scanning;\n\tbool deleting;\n};\n\nstruct linux_efi_random_seed {\n\tu32 size;\n\tu8 bits[0];\n};\n\nstruct linux_efi_memreserve {\n\tint size;\n\tatomic_t count;\n\tphys_addr_t next;\n\tstruct {\n\t\tphys_addr_t base;\n\t\tphys_addr_t size;\n\t} entry[0];\n};\n\nstruct efi_generic_dev_path {\n\tu8 type;\n\tu8 sub_type;\n\tu16 length;\n};\n\nstruct variable_validate {\n\tefi_guid_t vendor;\n\tchar *name;\n\tbool (*validate)(efi_char16_t *, int, u8 *, long unsigned int);\n};\n\ntypedef struct {\n\tu32 version;\n\tu32 num_entries;\n\tu32 desc_size;\n\tu32 reserved;\n\tefi_memory_desc_t entry[0];\n} efi_memory_attributes_table_t;\n\ntypedef int (*efi_memattr_perm_setter)(struct mm_struct *, efi_memory_desc_t *);\n\nstruct linux_efi_tpm_eventlog {\n\tu32 size;\n\tu32 final_events_preboot_size;\n\tu8 version;\n\tu8 log[0];\n};\n\nstruct efi_tcg2_final_events_table {\n\tu64 version;\n\tu64 nr_events;\n\tu8 events[0];\n};\n\nstruct tpm_digest {\n\tu16 alg_id;\n\tu8 digest[64];\n};\n\nenum tpm_duration {\n\tTPM_SHORT = 0,\n\tTPM_MEDIUM = 1,\n\tTPM_LONG = 2,\n\tTPM_LONG_LONG = 3,\n\tTPM_UNDEFINED = 4,\n\tTPM_NUM_DURATIONS = 4,\n};\n\nenum tcpa_event_types {\n\tPREBOOT = 0,\n\tPOST_CODE = 1,\n\tUNUSED = 2,\n\tNO_ACTION = 3,\n\tSEPARATOR = 4,\n\tACTION = 5,\n\tEVENT_TAG = 6,\n\tSCRTM_CONTENTS = 7,\n\tSCRTM_VERSION = 8,\n\tCPU_MICROCODE = 9,\n\tPLATFORM_CONFIG_FLAGS = 10,\n\tTABLE_OF_DEVICES = 11,\n\tCOMPACT_HASH = 12,\n\tIPL = 13,\n\tIPL_PARTITION_DATA = 14,\n\tNONHOST_CODE = 15,\n\tNONHOST_CONFIG = 16,\n\tNONHOST_INFO = 17,\n};\n\nstruct tcg_efi_specid_event_algs {\n\tu16 alg_id;\n\tu16 digest_size;\n};\n\nstruct tcg_efi_specid_event_head {\n\tu8 signature[16];\n\tu32 platform_class;\n\tu8 spec_version_minor;\n\tu8 spec_version_major;\n\tu8 spec_errata;\n\tu8 uintnsize;\n\tu32 num_algs;\n\tstruct tcg_efi_specid_event_algs digest_sizes[0];\n};\n\nstruct tcg_pcr_event {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu8 digest[20];\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tcg_event_field {\n\tu32 event_size;\n\tu8 event[0];\n};\n\nstruct tcg_pcr_event2_head {\n\tu32 pcr_idx;\n\tu32 event_type;\n\tu32 count;\n\tstruct tpm_digest digests[0];\n};\n\ntypedef u64 efi_physical_addr_t;\n\ntypedef struct {\n\tu64 length;\n\tu64 data;\n} efi_capsule_block_desc_t;\n\nstruct compat_efi_variable {\n\tefi_char16_t VariableName[512];\n\tefi_guid_t VendorGuid;\n\t__u32 DataSize;\n\t__u8 Data[1024];\n\t__u32 Status;\n\t__u32 Attributes;\n};\n\nstruct efivar_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct efivar_entry *, char *);\n\tssize_t (*store)(struct efivar_entry *, const char *, size_t);\n};\n\nstruct efi_system_resource_entry_v1 {\n\tefi_guid_t fw_class;\n\tu32 fw_type;\n\tu32 fw_version;\n\tu32 lowest_supported_fw_version;\n\tu32 capsule_flags;\n\tu32 last_attempt_version;\n\tu32 last_attempt_status;\n};\n\nstruct efi_system_resource_table {\n\tu32 fw_resource_count;\n\tu32 fw_resource_count_max;\n\tu64 fw_resource_version;\n\tu8 entries[0];\n};\n\nstruct esre_entry {\n\tunion {\n\t\tstruct efi_system_resource_entry_v1 *esre1;\n\t} esre;\n\tstruct kobject kobj;\n\tstruct list_head list;\n};\n\nstruct esre_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct esre_entry *, char *);\n\tssize_t (*store)(struct esre_entry *, const char *, size_t);\n};\n\nstruct efi_runtime_map_entry {\n\tefi_memory_desc_t md;\n\tstruct kobject kobj;\n};\n\nstruct map_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct efi_runtime_map_entry *, char *);\n};\n\nstruct hid_device_id {\n\t__u16 bus;\n\t__u16 group;\n\t__u32 vendor;\n\t__u32 product;\n\tkernel_ulong_t driver_data;\n};\n\nstruct hid_item {\n\tunsigned int format;\n\t__u8 size;\n\t__u8 type;\n\t__u8 tag;\n\tunion {\n\t\t__u8 u8;\n\t\t__s8 s8;\n\t\t__u16 u16;\n\t\t__s16 s16;\n\t\t__u32 u32;\n\t\t__s32 s32;\n\t\t__u8 *longdata;\n\t} data;\n};\n\nstruct hid_global {\n\tunsigned int usage_page;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__s32 unit_exponent;\n\tunsigned int unit;\n\tunsigned int report_id;\n\tunsigned int report_size;\n\tunsigned int report_count;\n};\n\nstruct hid_local {\n\tunsigned int usage[12288];\n\tu8 usage_size[12288];\n\tunsigned int collection_index[12288];\n\tunsigned int usage_index;\n\tunsigned int usage_minimum;\n\tunsigned int delimiter_depth;\n\tunsigned int delimiter_branch;\n};\n\nstruct hid_collection {\n\tint parent_idx;\n\tunsigned int type;\n\tunsigned int usage;\n\tunsigned int level;\n};\n\nstruct hid_usage {\n\tunsigned int hid;\n\tunsigned int collection_index;\n\tunsigned int usage_index;\n\t__s8 resolution_multiplier;\n\t__s8 wheel_factor;\n\t__u16 code;\n\t__u8 type;\n\t__s8 hat_min;\n\t__s8 hat_max;\n\t__s8 hat_dir;\n\t__s16 wheel_accumulated;\n};\n\nstruct hid_report;\n\nstruct hid_input;\n\nstruct hid_field {\n\tunsigned int physical;\n\tunsigned int logical;\n\tunsigned int application;\n\tstruct hid_usage *usage;\n\tunsigned int maxusage;\n\tunsigned int flags;\n\tunsigned int report_offset;\n\tunsigned int report_size;\n\tunsigned int report_count;\n\tunsigned int report_type;\n\t__s32 *value;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__s32 unit_exponent;\n\tunsigned int unit;\n\tstruct hid_report *report;\n\tunsigned int index;\n\tstruct hid_input *hidinput;\n\t__u16 dpad;\n};\n\nstruct hid_device;\n\nstruct hid_report {\n\tstruct list_head list;\n\tstruct list_head hidinput_list;\n\tunsigned int id;\n\tunsigned int type;\n\tunsigned int application;\n\tstruct hid_field *field[256];\n\tunsigned int maxfield;\n\tunsigned int size;\n\tstruct hid_device *device;\n};\n\nstruct hid_input {\n\tstruct list_head list;\n\tstruct hid_report *report;\n\tstruct input_dev *input;\n\tconst char *name;\n\tbool registered;\n\tstruct list_head reports;\n\tunsigned int application;\n};\n\nenum hid_type {\n\tHID_TYPE_OTHER = 0,\n\tHID_TYPE_USBMOUSE = 1,\n\tHID_TYPE_USBNONE = 2,\n};\n\nstruct hid_report_enum {\n\tunsigned int numbered;\n\tstruct list_head report_list;\n\tstruct hid_report *report_id_hash[256];\n};\n\nstruct hid_driver;\n\nstruct hid_ll_driver;\n\nstruct hid_device {\n\t__u8 *dev_rdesc;\n\tunsigned int dev_rsize;\n\t__u8 *rdesc;\n\tunsigned int rsize;\n\tstruct hid_collection *collection;\n\tunsigned int collection_size;\n\tunsigned int maxcollection;\n\tunsigned int maxapplication;\n\t__u16 bus;\n\t__u16 group;\n\t__u32 vendor;\n\t__u32 product;\n\t__u32 version;\n\tenum hid_type type;\n\tunsigned int country;\n\tstruct hid_report_enum report_enum[3];\n\tstruct work_struct led_work;\n\tstruct semaphore driver_input_lock;\n\tstruct device dev;\n\tstruct hid_driver *driver;\n\tstruct hid_ll_driver *ll_driver;\n\tstruct mutex ll_open_lock;\n\tunsigned int ll_open_count;\n\tlong unsigned int status;\n\tunsigned int claimed;\n\tunsigned int quirks;\n\tbool io_started;\n\tstruct list_head inputs;\n\tvoid *hiddev;\n\tvoid *hidraw;\n\tchar name[128];\n\tchar phys[64];\n\tchar uniq[64];\n\tvoid *driver_data;\n\tint (*ff_init)(struct hid_device *);\n\tint (*hiddev_connect)(struct hid_device *, unsigned int);\n\tvoid (*hiddev_disconnect)(struct hid_device *);\n\tvoid (*hiddev_hid_event)(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);\n\tvoid (*hiddev_report_event)(struct hid_device *, struct hid_report *);\n\tshort unsigned int debug;\n\tstruct dentry *debug_dir;\n\tstruct dentry *debug_rdesc;\n\tstruct dentry *debug_events;\n\tstruct list_head debug_list;\n\tspinlock_t debug_list_lock;\n\twait_queue_head_t debug_wait;\n};\n\nstruct hid_report_id;\n\nstruct hid_usage_id;\n\nstruct hid_driver {\n\tchar *name;\n\tconst struct hid_device_id *id_table;\n\tstruct list_head dyn_list;\n\tspinlock_t dyn_lock;\n\tbool (*match)(struct hid_device *, bool);\n\tint (*probe)(struct hid_device *, const struct hid_device_id *);\n\tvoid (*remove)(struct hid_device *);\n\tconst struct hid_report_id *report_table;\n\tint (*raw_event)(struct hid_device *, struct hid_report *, u8 *, int);\n\tconst struct hid_usage_id *usage_table;\n\tint (*event)(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);\n\tvoid (*report)(struct hid_device *, struct hid_report *);\n\t__u8 * (*report_fixup)(struct hid_device *, __u8 *, unsigned int *);\n\tint (*input_mapping)(struct hid_device *, struct hid_input *, struct hid_field *, struct hid_usage *, long unsigned int **, int *);\n\tint (*input_mapped)(struct hid_device *, struct hid_input *, struct hid_field *, struct hid_usage *, long unsigned int **, int *);\n\tint (*input_configured)(struct hid_device *, struct hid_input *);\n\tvoid (*feature_mapping)(struct hid_device *, struct hid_field *, struct hid_usage *);\n\tint (*suspend)(struct hid_device *, pm_message_t);\n\tint (*resume)(struct hid_device *);\n\tint (*reset_resume)(struct hid_device *);\n\tstruct device_driver driver;\n};\n\nstruct hid_ll_driver {\n\tint (*start)(struct hid_device *);\n\tvoid (*stop)(struct hid_device *);\n\tint (*open)(struct hid_device *);\n\tvoid (*close)(struct hid_device *);\n\tint (*power)(struct hid_device *, int);\n\tint (*parse)(struct hid_device *);\n\tvoid (*request)(struct hid_device *, struct hid_report *, int);\n\tint (*wait)(struct hid_device *);\n\tint (*raw_request)(struct hid_device *, unsigned char, __u8 *, size_t, unsigned char, int);\n\tint (*output_report)(struct hid_device *, __u8 *, size_t);\n\tint (*idle)(struct hid_device *, int, int, int);\n};\n\nstruct hid_parser {\n\tstruct hid_global global;\n\tstruct hid_global global_stack[4];\n\tunsigned int global_stack_ptr;\n\tstruct hid_local local;\n\tunsigned int *collection_stack;\n\tunsigned int collection_stack_ptr;\n\tunsigned int collection_stack_size;\n\tstruct hid_device *device;\n\tunsigned int scan_flags;\n};\n\nstruct hid_report_id {\n\t__u32 report_type;\n};\n\nstruct hid_usage_id {\n\t__u32 usage_hid;\n\t__u32 usage_type;\n\t__u32 usage_code;\n};\n\nstruct hiddev {\n\tint minor;\n\tint exist;\n\tint open;\n\tstruct mutex existancelock;\n\twait_queue_head_t wait;\n\tstruct hid_device *hid;\n\tstruct list_head list;\n\tspinlock_t list_lock;\n\tbool initialized;\n};\n\nstruct hidraw {\n\tunsigned int minor;\n\tint exist;\n\tint open;\n\twait_queue_head_t wait;\n\tstruct hid_device *hid;\n\tstruct device *dev;\n\tspinlock_t list_lock;\n\tstruct list_head list;\n};\n\nstruct hid_dynid {\n\tstruct list_head list;\n\tstruct hid_device_id id;\n};\n\ntypedef bool (*hid_usage_cmp_t)(struct hid_usage *, unsigned int, unsigned int);\n\nstruct quirks_list_struct {\n\tstruct hid_device_id hid_bl_item;\n\tstruct list_head node;\n};\n\nstruct hid_debug_list {\n\tstruct {\n\t\tunion {\n\t\t\tstruct __kfifo kfifo;\n\t\t\tchar *type;\n\t\t\tconst char *const_type;\n\t\t\tchar (*rectype)[0];\n\t\t\tchar *ptr;\n\t\t\tconst char *ptr_const;\n\t\t};\n\t\tchar buf[0];\n\t} hid_debug_fifo;\n\tstruct fasync_struct *fasync;\n\tstruct hid_device *hdev;\n\tstruct list_head node;\n\tstruct mutex read_mutex;\n};\n\nstruct hid_usage_entry {\n\tunsigned int page;\n\tunsigned int usage;\n\tconst char *description;\n};\n\nstruct hidraw_devinfo {\n\t__u32 bustype;\n\t__s16 vendor;\n\t__s16 product;\n};\n\nstruct hidraw_report {\n\t__u8 *value;\n\tint len;\n};\n\nstruct hidraw_list {\n\tstruct hidraw_report buffer[64];\n\tint head;\n\tint tail;\n\tstruct fasync_struct *fasync;\n\tstruct hidraw *hidraw;\n\tstruct list_head node;\n\tstruct mutex read_mutex;\n};\n\nstruct a4tech_sc {\n\tlong unsigned int quirks;\n\tunsigned int hw_wheel;\n\t__s32 delayed_value;\n};\n\nstruct apple_sc {\n\tlong unsigned int quirks;\n\tunsigned int fn_on;\n\tunsigned int fn_found;\n\tlong unsigned int pressed_numlock[12];\n};\n\nstruct apple_key_translation {\n\tu16 from;\n\tu16 to;\n\tu8 flags;\n};\n\nstruct lg_drv_data {\n\tlong unsigned int quirks;\n\tvoid *device_props;\n};\n\nstruct dev_type___2 {\n\tu16 idVendor;\n\tu16 idProduct;\n\tconst short int *ff;\n};\n\nstruct lg4ff_wheel_data {\n\tconst u32 product_id;\n\tu16 combine;\n\tu16 range;\n\tconst u16 min_range;\n\tconst u16 max_range;\n\tu8 led_state;\n\tstruct led_classdev *led[5];\n\tconst u32 alternate_modes;\n\tconst char * const real_tag;\n\tconst char * const real_name;\n\tconst u16 real_product_id;\n\tvoid (*set_range)(struct hid_device *, u16);\n};\n\nstruct lg4ff_device_entry {\n\tspinlock_t report_lock;\n\tstruct hid_report *report;\n\tstruct lg4ff_wheel_data wdata;\n};\n\nstruct lg4ff_wheel {\n\tconst u32 product_id;\n\tconst short int *ff_effects;\n\tconst u16 min_range;\n\tconst u16 max_range;\n\tvoid (*set_range)(struct hid_device *, u16);\n};\n\nstruct lg4ff_compat_mode_switch {\n\tconst u8 cmd_count;\n\tconst u8 cmd[0];\n};\n\nstruct lg4ff_wheel_ident_info {\n\tconst u32 modes;\n\tconst u16 mask;\n\tconst u16 result;\n\tconst u16 real_product_id;\n};\n\nstruct lg4ff_multimode_wheel {\n\tconst u16 product_id;\n\tconst u32 alternate_modes;\n\tconst char *real_tag;\n\tconst char *real_name;\n};\n\nstruct lg4ff_alternate_mode {\n\tconst u16 product_id;\n\tconst char *tag;\n\tconst char *name;\n};\n\nenum lg_g15_model {\n\tLG_G15 = 0,\n\tLG_G15_V2 = 1,\n\tLG_G510 = 2,\n\tLG_G510_USB_AUDIO = 3,\n};\n\nenum lg_g15_led_type {\n\tLG_G15_KBD_BRIGHTNESS = 0,\n\tLG_G15_LCD_BRIGHTNESS = 1,\n\tLG_G15_BRIGHTNESS_MAX = 2,\n\tLG_G15_MACRO_PRESET1 = 2,\n\tLG_G15_MACRO_PRESET2 = 3,\n\tLG_G15_MACRO_PRESET3 = 4,\n\tLG_G15_MACRO_RECORD = 5,\n\tLG_G15_LED_MAX = 6,\n};\n\nstruct lg_g15_led {\n\tstruct led_classdev cdev;\n\tenum led_brightness brightness;\n\tenum lg_g15_led_type led;\n\tu8 red;\n\tu8 green;\n\tu8 blue;\n};\n\nstruct lg_g15_data {\n\tu8 transfer_buf[20];\n\tstruct mutex mutex;\n\tstruct work_struct work;\n\tstruct input_dev *input;\n\tstruct hid_device *hdev;\n\tenum lg_g15_model model;\n\tstruct lg_g15_led leds[6];\n\tbool game_mode_enabled;\n};\n\nstruct ms_data {\n\tlong unsigned int quirks;\n\tstruct hid_device *hdev;\n\tstruct work_struct ff_worker;\n\t__u8 strong;\n\t__u8 weak;\n\tvoid *output_report_dmabuf;\n};\n\nenum {\n\tMAGNITUDE_STRONG = 2,\n\tMAGNITUDE_WEAK = 3,\n\tMAGNITUDE_NUM = 4,\n};\n\nstruct xb1s_ff_report {\n\t__u8 report_id;\n\t__u8 enable;\n\t__u8 magnitude[4];\n\t__u8 duration_10ms;\n\t__u8 start_delay_10ms;\n\t__u8 loop_count;\n};\n\nstruct ntrig_data {\n\t__u16 x;\n\t__u16 y;\n\t__u16 w;\n\t__u16 h;\n\t__u16 id;\n\tbool tipswitch;\n\tbool confidence;\n\tbool first_contact_touch;\n\tbool reading_mt;\n\t__u8 mt_footer[4];\n\t__u8 mt_foot_count;\n\t__s8 act_state;\n\t__s8 deactivate_slack;\n\t__s8 activate_slack;\n\t__u16 min_width;\n\t__u16 min_height;\n\t__u16 activation_width;\n\t__u16 activation_height;\n\t__u16 sensor_logical_width;\n\t__u16 sensor_logical_height;\n\t__u16 sensor_physical_width;\n\t__u16 sensor_physical_height;\n};\n\nstruct plff_device {\n\tstruct hid_report *report;\n\ts32 maxval;\n\ts32 *strong;\n\ts32 *weak;\n};\n\nstruct sixaxis_led {\n\tu8 time_enabled;\n\tu8 duty_length;\n\tu8 enabled;\n\tu8 duty_off;\n\tu8 duty_on;\n};\n\nstruct sixaxis_rumble {\n\tu8 padding;\n\tu8 right_duration;\n\tu8 right_motor_on;\n\tu8 left_duration;\n\tu8 left_motor_force;\n};\n\nstruct sixaxis_output_report {\n\tu8 report_id;\n\tstruct sixaxis_rumble rumble;\n\tu8 padding[4];\n\tu8 leds_bitmap;\n\tstruct sixaxis_led led[4];\n\tstruct sixaxis_led _reserved;\n};\n\nunion sixaxis_output_report_01 {\n\tstruct sixaxis_output_report data;\n\tu8 buf[36];\n};\n\nstruct motion_output_report_02 {\n\tu8 type;\n\tu8 zero;\n\tu8 r;\n\tu8 g;\n\tu8 b;\n\tu8 zero2;\n\tu8 rumble;\n};\n\nstruct ds4_calibration_data {\n\tint abs_code;\n\tshort int bias;\n\tint sens_numer;\n\tint sens_denom;\n};\n\nenum ds4_dongle_state {\n\tDONGLE_DISCONNECTED = 0,\n\tDONGLE_CALIBRATING = 1,\n\tDONGLE_CONNECTED = 2,\n\tDONGLE_DISABLED = 3,\n};\n\nenum sony_worker {\n\tSONY_WORKER_STATE = 0,\n\tSONY_WORKER_HOTPLUG = 1,\n};\n\nstruct sony_sc {\n\tspinlock_t lock;\n\tstruct list_head list_node;\n\tstruct hid_device *hdev;\n\tstruct input_dev *touchpad;\n\tstruct input_dev *sensor_dev;\n\tstruct led_classdev *leds[4];\n\tlong unsigned int quirks;\n\tstruct work_struct hotplug_worker;\n\tstruct work_struct state_worker;\n\tvoid (*send_output_report)(struct sony_sc *);\n\tstruct power_supply *battery;\n\tstruct power_supply_desc battery_desc;\n\tint device_id;\n\tunsigned int fw_version;\n\tunsigned int hw_version;\n\tu8 *output_report_dmabuf;\n\tu8 mac_address[6];\n\tu8 hotplug_worker_initialized;\n\tu8 state_worker_initialized;\n\tu8 defer_initialization;\n\tu8 cable_state;\n\tu8 battery_charging;\n\tu8 battery_capacity;\n\tu8 led_state[4];\n\tu8 led_delay_on[4];\n\tu8 led_delay_off[4];\n\tu8 led_count;\n\tbool timestamp_initialized;\n\tu16 prev_timestamp;\n\tunsigned int timestamp_us;\n\tu8 ds4_bt_poll_interval;\n\tenum ds4_dongle_state ds4_dongle_state;\n\tstruct ds4_calibration_data ds4_calib_data[6];\n};\n\nstruct hid_control_fifo {\n\tunsigned char dir;\n\tstruct hid_report *report;\n\tchar *raw_report;\n};\n\nstruct hid_output_fifo {\n\tstruct hid_report *report;\n\tchar *raw_report;\n};\n\nstruct hid_class_descriptor {\n\t__u8 bDescriptorType;\n\t__le16 wDescriptorLength;\n} __attribute__((packed));\n\nstruct hid_descriptor {\n\t__u8 bLength;\n\t__u8 bDescriptorType;\n\t__le16 bcdHID;\n\t__u8 bCountryCode;\n\t__u8 bNumDescriptors;\n\tstruct hid_class_descriptor desc[1];\n} __attribute__((packed));\n\nstruct usbhid_device {\n\tstruct hid_device *hid;\n\tstruct usb_interface *intf;\n\tint ifnum;\n\tunsigned int bufsize;\n\tstruct urb *urbin;\n\tchar *inbuf;\n\tdma_addr_t inbuf_dma;\n\tstruct urb *urbctrl;\n\tstruct usb_ctrlrequest *cr;\n\tstruct hid_control_fifo ctrl[256];\n\tunsigned char ctrlhead;\n\tunsigned char ctrltail;\n\tchar *ctrlbuf;\n\tdma_addr_t ctrlbuf_dma;\n\tlong unsigned int last_ctrl;\n\tstruct urb *urbout;\n\tstruct hid_output_fifo out[256];\n\tunsigned char outhead;\n\tunsigned char outtail;\n\tchar *outbuf;\n\tdma_addr_t outbuf_dma;\n\tlong unsigned int last_out;\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tlong unsigned int iofl;\n\tstruct timer_list io_retry;\n\tlong unsigned int stop_retry;\n\tunsigned int retry_delay;\n\tstruct work_struct reset_work;\n\twait_queue_head_t wait;\n};\n\nstruct hiddev_event {\n\tunsigned int hid;\n\tint value;\n};\n\nstruct hiddev_devinfo {\n\t__u32 bustype;\n\t__u32 busnum;\n\t__u32 devnum;\n\t__u32 ifnum;\n\t__s16 vendor;\n\t__s16 product;\n\t__s16 version;\n\t__u32 num_applications;\n};\n\nstruct hiddev_collection_info {\n\t__u32 index;\n\t__u32 type;\n\t__u32 usage;\n\t__u32 level;\n};\n\nstruct hiddev_report_info {\n\t__u32 report_type;\n\t__u32 report_id;\n\t__u32 num_fields;\n};\n\nstruct hiddev_field_info {\n\t__u32 report_type;\n\t__u32 report_id;\n\t__u32 field_index;\n\t__u32 maxusage;\n\t__u32 flags;\n\t__u32 physical;\n\t__u32 logical;\n\t__u32 application;\n\t__s32 logical_minimum;\n\t__s32 logical_maximum;\n\t__s32 physical_minimum;\n\t__s32 physical_maximum;\n\t__u32 unit_exponent;\n\t__u32 unit;\n};\n\nstruct hiddev_usage_ref {\n\t__u32 report_type;\n\t__u32 report_id;\n\t__u32 field_index;\n\t__u32 usage_index;\n\t__u32 usage_code;\n\t__s32 value;\n};\n\nstruct hiddev_usage_ref_multi {\n\tstruct hiddev_usage_ref uref;\n\t__u32 num_values;\n\t__s32 values[1024];\n};\n\nstruct hiddev_list {\n\tstruct hiddev_usage_ref buffer[2048];\n\tint head;\n\tint tail;\n\tunsigned int flags;\n\tstruct fasync_struct *fasync;\n\tstruct hiddev *hiddev;\n\tstruct list_head node;\n\tstruct mutex thread_lock;\n};\n\nstruct pidff_usage {\n\tstruct hid_field *field;\n\ts32 *value;\n};\n\nstruct pidff_device {\n\tstruct hid_device *hid;\n\tstruct hid_report *reports[13];\n\tstruct pidff_usage set_effect[7];\n\tstruct pidff_usage set_envelope[5];\n\tstruct pidff_usage set_condition[8];\n\tstruct pidff_usage set_periodic[5];\n\tstruct pidff_usage set_constant[2];\n\tstruct pidff_usage set_ramp[3];\n\tstruct pidff_usage device_gain[1];\n\tstruct pidff_usage block_load[2];\n\tstruct pidff_usage pool[3];\n\tstruct pidff_usage effect_operation[2];\n\tstruct pidff_usage block_free[1];\n\tstruct hid_field *create_new_effect_type;\n\tstruct hid_field *set_effect_type;\n\tstruct hid_field *effect_direction;\n\tstruct hid_field *device_control;\n\tstruct hid_field *block_load_status;\n\tstruct hid_field *effect_operation_status;\n\tint control_id[2];\n\tint type_id[11];\n\tint status_id[2];\n\tint operation_id[2];\n\tint pid_id[64];\n};\n\nenum rfkill_type {\n\tRFKILL_TYPE_ALL = 0,\n\tRFKILL_TYPE_WLAN = 1,\n\tRFKILL_TYPE_BLUETOOTH = 2,\n\tRFKILL_TYPE_UWB = 3,\n\tRFKILL_TYPE_WIMAX = 4,\n\tRFKILL_TYPE_WWAN = 5,\n\tRFKILL_TYPE_GPS = 6,\n\tRFKILL_TYPE_FM = 7,\n\tRFKILL_TYPE_NFC = 8,\n\tNUM_RFKILL_TYPES = 9,\n};\n\nstruct rfkill;\n\nstruct rfkill_ops {\n\tvoid (*poll)(struct rfkill *, void *);\n\tvoid (*query)(struct rfkill *, void *);\n\tint (*set_block)(void *, bool);\n};\n\nenum {\n\tDISABLE_ASL_WLAN = 1,\n\tDISABLE_ASL_BLUETOOTH = 2,\n\tDISABLE_ASL_IRDA = 4,\n\tDISABLE_ASL_CAMERA = 8,\n\tDISABLE_ASL_TV = 16,\n\tDISABLE_ASL_GPS = 32,\n\tDISABLE_ASL_DISPLAYSWITCH = 64,\n\tDISABLE_ASL_MODEM = 128,\n\tDISABLE_ASL_CARDREADER = 256,\n\tDISABLE_ASL_3G = 512,\n\tDISABLE_ASL_WIMAX = 1024,\n\tDISABLE_ASL_HWCF = 2048,\n};\n\nenum {\n\tCM_ASL_WLAN = 0,\n\tCM_ASL_BLUETOOTH = 1,\n\tCM_ASL_IRDA = 2,\n\tCM_ASL_1394 = 3,\n\tCM_ASL_CAMERA = 4,\n\tCM_ASL_TV = 5,\n\tCM_ASL_GPS = 6,\n\tCM_ASL_DVDROM = 7,\n\tCM_ASL_DISPLAYSWITCH = 8,\n\tCM_ASL_PANELBRIGHT = 9,\n\tCM_ASL_BIOSFLASH = 10,\n\tCM_ASL_ACPIFLASH = 11,\n\tCM_ASL_CPUFV = 12,\n\tCM_ASL_CPUTEMPERATURE = 13,\n\tCM_ASL_FANCPU = 14,\n\tCM_ASL_FANCHASSIS = 15,\n\tCM_ASL_USBPORT1 = 16,\n\tCM_ASL_USBPORT2 = 17,\n\tCM_ASL_USBPORT3 = 18,\n\tCM_ASL_MODEM = 19,\n\tCM_ASL_CARDREADER = 20,\n\tCM_ASL_3G = 21,\n\tCM_ASL_WIMAX = 22,\n\tCM_ASL_HWCF = 23,\n\tCM_ASL_LID = 24,\n\tCM_ASL_TYPE = 25,\n\tCM_ASL_PANELPOWER = 26,\n\tCM_ASL_TPD = 27,\n};\n\nstruct eeepc_laptop {\n\tacpi_handle handle;\n\tu32 cm_supported;\n\tbool cpufv_disabled;\n\tbool hotplug_disabled;\n\tu16 event_count[128];\n\tstruct platform_device *platform_device;\n\tstruct acpi_device *device;\n\tstruct backlight_device *backlight_device;\n\tstruct input_dev *inputdev;\n\tstruct rfkill *wlan_rfkill;\n\tstruct rfkill *bluetooth_rfkill;\n\tstruct rfkill *wwan3g_rfkill;\n\tstruct rfkill *wimax_rfkill;\n\tstruct hotplug_slot hotplug_slot;\n\tstruct mutex hotplug_lock;\n\tstruct led_classdev tpd_led;\n\tint tpd_led_wk;\n\tstruct workqueue_struct *led_workqueue;\n\tstruct work_struct tpd_led_work;\n};\n\nstruct eeepc_cpufv {\n\tint num;\n\tint cur;\n};\n\nstruct pmc_bit_map {\n\tconst char *name;\n\tu32 bit_mask;\n};\n\nstruct pmc_reg_map {\n\tconst struct pmc_bit_map *d3_sts_0;\n\tconst struct pmc_bit_map *d3_sts_1;\n\tconst struct pmc_bit_map *func_dis;\n\tconst struct pmc_bit_map *func_dis_2;\n\tconst struct pmc_bit_map *pss;\n};\n\nstruct pmc_data {\n\tconst struct pmc_reg_map *map;\n\tconst struct pmc_clk *clks;\n};\n\nstruct pmc_dev {\n\tu32 base_addr;\n\tvoid *regmap;\n\tconst struct pmc_reg_map *map;\n\tstruct dentry *dbgfs_dir;\n\tbool init;\n};\n\nstruct acpi_table_pcct {\n\tstruct acpi_table_header header;\n\tu32 flags;\n\tu64 reserved;\n};\n\nenum acpi_pcct_type {\n\tACPI_PCCT_TYPE_GENERIC_SUBSPACE = 0,\n\tACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE = 1,\n\tACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE_TYPE2 = 2,\n\tACPI_PCCT_TYPE_EXT_PCC_MASTER_SUBSPACE = 3,\n\tACPI_PCCT_TYPE_EXT_PCC_SLAVE_SUBSPACE = 4,\n\tACPI_PCCT_TYPE_RESERVED = 5,\n};\n\nstruct acpi_pcct_subspace {\n\tstruct acpi_subtable_header header;\n\tu8 reserved[6];\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n} __attribute__((packed));\n\nstruct acpi_pcct_hw_reduced_type2 {\n\tstruct acpi_subtable_header header;\n\tu32 platform_interrupt;\n\tu8 flags;\n\tu8 reserved;\n\tu64 base_address;\n\tu64 length;\n\tstruct acpi_generic_address doorbell_register;\n\tu64 preserve_mask;\n\tu64 write_mask;\n\tu32 latency;\n\tu32 max_access_rate;\n\tu16 min_turnaround_time;\n\tstruct acpi_generic_address platform_ack_register;\n\tu64 ack_preserve_mask;\n\tu64 ack_write_mask;\n} __attribute__((packed));\n\nstruct cper_sec_proc_arm {\n\tu32 validation_bits;\n\tu16 err_info_num;\n\tu16 context_info_num;\n\tu32 section_length;\n\tu8 affinity_level;\n\tu8 reserved[3];\n\tu64 mpidr;\n\tu64 midr;\n\tu32 running_state;\n\tu32 psci_state;\n};\n\nstruct trace_event_raw_mc_event {\n\tstruct trace_entry ent;\n\tunsigned int error_type;\n\tu32 __data_loc_msg;\n\tu32 __data_loc_label;\n\tu16 error_count;\n\tu8 mc_index;\n\ts8 top_layer;\n\ts8 middle_layer;\n\ts8 lower_layer;\n\tlong int address;\n\tu8 grain_bits;\n\tlong int syndrome;\n\tu32 __data_loc_driver_detail;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_arm_event {\n\tstruct trace_entry ent;\n\tu64 mpidr;\n\tu64 midr;\n\tu32 running_state;\n\tu32 psci_state;\n\tu8 affinity;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_non_standard_event {\n\tstruct trace_entry ent;\n\tchar sec_type[16];\n\tchar fru_id[16];\n\tu32 __data_loc_fru_text;\n\tu8 sev;\n\tu32 len;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_aer_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev_name;\n\tu32 status;\n\tu8 severity;\n\tu8 tlp_header_valid;\n\tu32 tlp_header[4];\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_mc_event {\n\tu32 msg;\n\tu32 label;\n\tu32 driver_detail;\n};\n\nstruct trace_event_data_offsets_arm_event {};\n\nstruct trace_event_data_offsets_non_standard_event {\n\tu32 fru_text;\n\tu32 buf;\n};\n\nstruct trace_event_data_offsets_aer_event {\n\tu32 dev_name;\n};\n\ntypedef void (*btf_trace_mc_event)(void *, const unsigned int, const char *, const char *, const int, const u8, const s8, const s8, const s8, long unsigned int, const u8, long unsigned int, const char *);\n\ntypedef void (*btf_trace_arm_event)(void *, const struct cper_sec_proc_arm *);\n\ntypedef void (*btf_trace_non_standard_event)(void *, const guid_t *, const guid_t *, const char *, const u8, const u8 *, const u32);\n\ntypedef void (*btf_trace_aer_event)(void *, const char *, const u32, const u8, const u8, struct aer_header_log_regs *);\n\nstruct nvmem_cell_lookup {\n\tconst char *nvmem_name;\n\tconst char *cell_name;\n\tconst char *dev_id;\n\tconst char *con_id;\n\tstruct list_head node;\n};\n\nenum {\n\tNVMEM_ADD = 1,\n\tNVMEM_REMOVE = 2,\n\tNVMEM_CELL_ADD = 3,\n\tNVMEM_CELL_REMOVE = 4,\n};\n\nstruct nvmem_cell_table {\n\tconst char *nvmem_name;\n\tconst struct nvmem_cell_info *cells;\n\tsize_t ncells;\n\tstruct list_head node;\n};\n\nstruct nvmem_device___2 {\n\tstruct module *owner;\n\tstruct device dev;\n\tint stride;\n\tint word_size;\n\tint id;\n\tstruct kref refcnt;\n\tsize_t size;\n\tbool read_only;\n\tbool root_only;\n\tint flags;\n\tenum nvmem_type type;\n\tstruct bin_attribute eeprom;\n\tstruct device *base_dev;\n\tstruct list_head cells;\n\tnvmem_reg_read_t reg_read;\n\tnvmem_reg_write_t reg_write;\n\tstruct gpio_desc *wp_gpio;\n\tvoid *priv;\n};\n\nstruct nvmem_cell {\n\tconst char *name;\n\tint offset;\n\tint bytes;\n\tint bit_offset;\n\tint nbits;\n\tstruct device_node *np;\n\tstruct nvmem_device___2 *nvmem;\n\tstruct list_head node;\n};\n\nstruct snd_shutdown_f_ops;\n\nstruct snd_info_entry;\n\nstruct snd_card {\n\tint number;\n\tchar id[16];\n\tchar driver[16];\n\tchar shortname[32];\n\tchar longname[80];\n\tchar irq_descr[32];\n\tchar mixername[80];\n\tchar components[128];\n\tstruct module *module;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_card *);\n\tstruct list_head devices;\n\tstruct device ctl_dev;\n\tunsigned int last_numid;\n\tstruct rw_semaphore controls_rwsem;\n\trwlock_t ctl_files_rwlock;\n\tint controls_count;\n\tint user_ctl_count;\n\tstruct list_head controls;\n\tstruct list_head ctl_files;\n\tstruct snd_info_entry *proc_root;\n\tstruct proc_dir_entry *proc_root_link;\n\tstruct list_head files_list;\n\tstruct snd_shutdown_f_ops *s_f_ops;\n\tspinlock_t files_lock;\n\tint shutdown;\n\tstruct completion *release_completion;\n\tstruct device *dev;\n\tstruct device card_dev;\n\tconst struct attribute_group *dev_groups[4];\n\tbool registered;\n\tint sync_irq;\n\twait_queue_head_t remove_sleep;\n\tsize_t total_pcm_alloc_bytes;\n\tstruct mutex memory_mutex;\n\tunsigned int power_state;\n\twait_queue_head_t power_sleep;\n};\n\nstruct snd_info_buffer;\n\nstruct snd_info_entry_text {\n\tvoid (*read)(struct snd_info_entry *, struct snd_info_buffer *);\n\tvoid (*write)(struct snd_info_entry *, struct snd_info_buffer *);\n};\n\nstruct snd_info_entry_ops;\n\nstruct snd_info_entry {\n\tconst char *name;\n\tumode_t mode;\n\tlong int size;\n\tshort unsigned int content;\n\tunion {\n\t\tstruct snd_info_entry_text text;\n\t\tconst struct snd_info_entry_ops *ops;\n\t} c;\n\tstruct snd_info_entry *parent;\n\tstruct module *module;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_info_entry *);\n\tstruct proc_dir_entry *p;\n\tstruct mutex access;\n\tstruct list_head children;\n\tstruct list_head list;\n};\n\nstruct snd_minor {\n\tint type;\n\tint card;\n\tint device;\n\tconst struct file_operations *f_ops;\n\tvoid *private_data;\n\tstruct device *dev;\n\tstruct snd_card *card_ptr;\n};\n\nstruct snd_info_buffer {\n\tchar *buffer;\n\tunsigned int curr;\n\tunsigned int size;\n\tunsigned int len;\n\tint stop;\n\tint error;\n};\n\nstruct snd_info_entry_ops {\n\tint (*open)(struct snd_info_entry *, short unsigned int, void **);\n\tint (*release)(struct snd_info_entry *, short unsigned int, void *);\n\tssize_t (*read)(struct snd_info_entry *, void *, struct file *, char *, size_t, loff_t);\n\tssize_t (*write)(struct snd_info_entry *, void *, struct file *, const char *, size_t, loff_t);\n\tloff_t (*llseek)(struct snd_info_entry *, void *, struct file *, loff_t, int);\n\t__poll_t (*poll)(struct snd_info_entry *, void *, struct file *, poll_table *);\n\tint (*ioctl)(struct snd_info_entry *, void *, struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct snd_info_entry *, void *, struct inode *, struct file *, struct vm_area_struct *);\n};\n\nenum {\n\tSND_CTL_SUBDEV_PCM = 0,\n\tSND_CTL_SUBDEV_RAWMIDI = 1,\n\tSND_CTL_SUBDEV_ITEMS = 2,\n};\n\nstruct snd_monitor_file {\n\tstruct file *file;\n\tconst struct file_operations *disconnected_f_op;\n\tstruct list_head shutdown_list;\n\tstruct list_head list;\n};\n\nenum snd_device_type {\n\tSNDRV_DEV_LOWLEVEL = 0,\n\tSNDRV_DEV_INFO = 1,\n\tSNDRV_DEV_BUS = 2,\n\tSNDRV_DEV_CODEC = 3,\n\tSNDRV_DEV_PCM = 4,\n\tSNDRV_DEV_COMPRESS = 5,\n\tSNDRV_DEV_RAWMIDI = 6,\n\tSNDRV_DEV_TIMER = 7,\n\tSNDRV_DEV_SEQUENCER = 8,\n\tSNDRV_DEV_HWDEP = 9,\n\tSNDRV_DEV_JACK = 10,\n\tSNDRV_DEV_CONTROL = 11,\n};\n\nenum snd_device_state {\n\tSNDRV_DEV_BUILD = 0,\n\tSNDRV_DEV_REGISTERED = 1,\n\tSNDRV_DEV_DISCONNECTED = 2,\n};\n\nstruct snd_device;\n\nstruct snd_device_ops {\n\tint (*dev_free)(struct snd_device *);\n\tint (*dev_register)(struct snd_device *);\n\tint (*dev_disconnect)(struct snd_device *);\n};\n\nstruct snd_device {\n\tstruct list_head list;\n\tstruct snd_card *card;\n\tenum snd_device_state state;\n\tenum snd_device_type type;\n\tvoid *device_data;\n\tconst struct snd_device_ops *ops;\n};\n\nstruct snd_aes_iec958 {\n\tunsigned char status[24];\n\tunsigned char subcode[147];\n\tunsigned char pad;\n\tunsigned char dig_subframe[4];\n};\n\nstruct snd_ctl_card_info {\n\tint card;\n\tint pad;\n\tunsigned char id[16];\n\tunsigned char driver[16];\n\tunsigned char name[32];\n\tunsigned char longname[80];\n\tunsigned char reserved_[16];\n\tunsigned char mixername[80];\n\tunsigned char components[128];\n};\n\ntypedef int snd_ctl_elem_type_t;\n\ntypedef int snd_ctl_elem_iface_t;\n\nstruct snd_ctl_elem_id {\n\tunsigned int numid;\n\tsnd_ctl_elem_iface_t iface;\n\tunsigned int device;\n\tunsigned int subdevice;\n\tunsigned char name[44];\n\tunsigned int index;\n};\n\nstruct snd_ctl_elem_list {\n\tunsigned int offset;\n\tunsigned int space;\n\tunsigned int used;\n\tunsigned int count;\n\tstruct snd_ctl_elem_id *pids;\n\tunsigned char reserved[50];\n};\n\nstruct snd_ctl_elem_info {\n\tstruct snd_ctl_elem_id id;\n\tsnd_ctl_elem_type_t type;\n\tunsigned int access;\n\tunsigned int count;\n\t__kernel_pid_t owner;\n\tunion {\n\t\tstruct {\n\t\t\tlong int min;\n\t\t\tlong int max;\n\t\t\tlong int step;\n\t\t} integer;\n\t\tstruct {\n\t\t\tlong long int min;\n\t\t\tlong long int max;\n\t\t\tlong long int step;\n\t\t} integer64;\n\t\tstruct {\n\t\t\tunsigned int items;\n\t\t\tunsigned int item;\n\t\t\tchar name[64];\n\t\t\t__u64 names_ptr;\n\t\t\tunsigned int names_length;\n\t\t} enumerated;\n\t\tunsigned char reserved[128];\n\t} value;\n\tunsigned char reserved[64];\n};\n\nstruct snd_ctl_elem_value {\n\tstruct snd_ctl_elem_id id;\n\tunsigned int indirect: 1;\n\tunion {\n\t\tunion {\n\t\t\tlong int value[128];\n\t\t\tlong int *value_ptr;\n\t\t} integer;\n\t\tunion {\n\t\t\tlong long int value[64];\n\t\t\tlong long int *value_ptr;\n\t\t} integer64;\n\t\tunion {\n\t\t\tunsigned int item[128];\n\t\t\tunsigned int *item_ptr;\n\t\t} enumerated;\n\t\tunion {\n\t\t\tunsigned char data[512];\n\t\t\tunsigned char *data_ptr;\n\t\t} bytes;\n\t\tstruct snd_aes_iec958 iec958;\n\t} value;\n\tunsigned char reserved[128];\n};\n\nstruct snd_ctl_tlv {\n\tunsigned int numid;\n\tunsigned int length;\n\tunsigned int tlv[0];\n};\n\nenum sndrv_ctl_event_type {\n\tSNDRV_CTL_EVENT_ELEM = 0,\n\tSNDRV_CTL_EVENT_LAST = 0,\n};\n\nstruct snd_ctl_event {\n\tint type;\n\tunion {\n\t\tstruct {\n\t\t\tunsigned int mask;\n\t\t\tstruct snd_ctl_elem_id id;\n\t\t} elem;\n\t\tunsigned char data8[60];\n\t} data;\n};\n\nstruct snd_kcontrol;\n\ntypedef int snd_kcontrol_info_t(struct snd_kcontrol *, struct snd_ctl_elem_info *);\n\ntypedef int snd_kcontrol_get_t(struct snd_kcontrol *, struct snd_ctl_elem_value *);\n\ntypedef int snd_kcontrol_put_t(struct snd_kcontrol *, struct snd_ctl_elem_value *);\n\ntypedef int snd_kcontrol_tlv_rw_t(struct snd_kcontrol *, int, unsigned int, unsigned int *);\n\nstruct snd_ctl_file;\n\nstruct snd_kcontrol_volatile {\n\tstruct snd_ctl_file *owner;\n\tunsigned int access;\n};\n\nstruct snd_kcontrol {\n\tstruct list_head list;\n\tstruct snd_ctl_elem_id id;\n\tunsigned int count;\n\tsnd_kcontrol_info_t *info;\n\tsnd_kcontrol_get_t *get;\n\tsnd_kcontrol_put_t *put;\n\tunion {\n\t\tsnd_kcontrol_tlv_rw_t *c;\n\t\tconst unsigned int *p;\n\t} tlv;\n\tlong unsigned int private_value;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_kcontrol *);\n\tstruct snd_kcontrol_volatile vd[0];\n};\n\nenum {\n\tSNDRV_CTL_TLV_OP_READ = 0,\n\tSNDRV_CTL_TLV_OP_WRITE = 1,\n\tSNDRV_CTL_TLV_OP_CMD = 4294967295,\n};\n\nstruct snd_kcontrol_new {\n\tsnd_ctl_elem_iface_t iface;\n\tunsigned int device;\n\tunsigned int subdevice;\n\tconst unsigned char *name;\n\tunsigned int index;\n\tunsigned int access;\n\tunsigned int count;\n\tsnd_kcontrol_info_t *info;\n\tsnd_kcontrol_get_t *get;\n\tsnd_kcontrol_put_t *put;\n\tunion {\n\t\tsnd_kcontrol_tlv_rw_t *c;\n\t\tconst unsigned int *p;\n\t} tlv;\n\tlong unsigned int private_value;\n};\n\nstruct snd_ctl_file {\n\tstruct list_head list;\n\tstruct snd_card *card;\n\tstruct pid *pid;\n\tint preferred_subdevice[2];\n\twait_queue_head_t change_sleep;\n\tspinlock_t read_lock;\n\tstruct fasync_struct *fasync;\n\tint subscribed;\n\tstruct list_head events;\n};\n\nstruct snd_kctl_event {\n\tstruct list_head list;\n\tstruct snd_ctl_elem_id id;\n\tunsigned int mask;\n};\n\ntypedef int (*snd_kctl_ioctl_func_t)(struct snd_card *, struct snd_ctl_file *, unsigned int, long unsigned int);\n\nstruct snd_kctl_ioctl {\n\tstruct list_head list;\n\tsnd_kctl_ioctl_func_t fioctl;\n};\n\nenum snd_ctl_add_mode {\n\tCTL_ADD_EXCLUSIVE = 0,\n\tCTL_REPLACE = 1,\n\tCTL_ADD_ON_REPLACE = 2,\n};\n\nstruct user_element {\n\tstruct snd_ctl_elem_info info;\n\tstruct snd_card *card;\n\tchar *elem_data;\n\tlong unsigned int elem_data_size;\n\tvoid *tlv_data;\n\tlong unsigned int tlv_data_size;\n\tvoid *priv_data;\n};\n\nstruct snd_ctl_elem_list32 {\n\tu32 offset;\n\tu32 space;\n\tu32 used;\n\tu32 count;\n\tu32 pids;\n\tunsigned char reserved[50];\n};\n\nstruct snd_ctl_elem_info32 {\n\tstruct snd_ctl_elem_id id;\n\ts32 type;\n\tu32 access;\n\tu32 count;\n\ts32 owner;\n\tunion {\n\t\tstruct {\n\t\t\ts32 min;\n\t\t\ts32 max;\n\t\t\ts32 step;\n\t\t} integer;\n\t\tstruct {\n\t\t\tu64 min;\n\t\t\tu64 max;\n\t\t\tu64 step;\n\t\t} integer64;\n\t\tstruct {\n\t\t\tu32 items;\n\t\t\tu32 item;\n\t\t\tchar name[64];\n\t\t\tu64 names_ptr;\n\t\t\tu32 names_length;\n\t\t} enumerated;\n\t\tunsigned char reserved[128];\n\t} value;\n\tunsigned char reserved[64];\n};\n\nstruct snd_ctl_elem_value32 {\n\tstruct snd_ctl_elem_id id;\n\tunsigned int indirect;\n\tunion {\n\t\ts32 integer[128];\n\t\tunsigned char data[512];\n\t} value;\n\tunsigned char reserved[128];\n};\n\nenum {\n\tSNDRV_CTL_IOCTL_ELEM_LIST32 = 3225965840,\n\tSNDRV_CTL_IOCTL_ELEM_INFO32 = 3239073041,\n\tSNDRV_CTL_IOCTL_ELEM_READ32 = 3267646738,\n\tSNDRV_CTL_IOCTL_ELEM_WRITE32 = 3267646739,\n\tSNDRV_CTL_IOCTL_ELEM_ADD32 = 3239073047,\n\tSNDRV_CTL_IOCTL_ELEM_REPLACE32 = 3239073048,\n};\n\nstruct snd_pci_quirk {\n\tshort unsigned int subvendor;\n\tshort unsigned int subdevice;\n\tshort unsigned int subdevice_mask;\n\tint value;\n};\n\nstruct snd_info_private_data {\n\tstruct snd_info_buffer *rbuffer;\n\tstruct snd_info_buffer *wbuffer;\n\tstruct snd_info_entry *entry;\n\tvoid *file_private_data;\n};\n\nstruct link_ctl_info {\n\tsnd_ctl_elem_type_t type;\n\tint count;\n\tint min_val;\n\tint max_val;\n};\n\nstruct link_master {\n\tstruct list_head slaves;\n\tstruct link_ctl_info info;\n\tint val;\n\tunsigned int tlv[4];\n\tvoid (*hook)(void *, int);\n\tvoid *hook_private_data;\n};\n\nstruct link_slave {\n\tstruct list_head list;\n\tstruct link_master *master;\n\tstruct link_ctl_info info;\n\tint vals[2];\n\tunsigned int flags;\n\tstruct snd_kcontrol *kctl;\n\tstruct snd_kcontrol slave;\n};\n\nenum snd_jack_types {\n\tSND_JACK_HEADPHONE = 1,\n\tSND_JACK_MICROPHONE = 2,\n\tSND_JACK_HEADSET = 3,\n\tSND_JACK_LINEOUT = 4,\n\tSND_JACK_MECHANICAL = 8,\n\tSND_JACK_VIDEOOUT = 16,\n\tSND_JACK_AVOUT = 20,\n\tSND_JACK_LINEIN = 32,\n\tSND_JACK_BTN_0 = 16384,\n\tSND_JACK_BTN_1 = 8192,\n\tSND_JACK_BTN_2 = 4096,\n\tSND_JACK_BTN_3 = 2048,\n\tSND_JACK_BTN_4 = 1024,\n\tSND_JACK_BTN_5 = 512,\n};\n\nstruct snd_jack {\n\tstruct list_head kctl_list;\n\tstruct snd_card *card;\n\tconst char *id;\n\tstruct input_dev *input_dev;\n\tint registered;\n\tint type;\n\tchar name[100];\n\tunsigned int key[6];\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_jack *);\n};\n\nstruct snd_jack_kctl {\n\tstruct snd_kcontrol *kctl;\n\tstruct list_head list;\n\tunsigned int mask_bits;\n};\n\nstruct snd_hwdep_info {\n\tunsigned int device;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tint iface;\n\tunsigned char reserved[64];\n};\n\nstruct snd_hwdep_dsp_status {\n\tunsigned int version;\n\tunsigned char id[32];\n\tunsigned int num_dsps;\n\tunsigned int dsp_loaded;\n\tunsigned int chip_ready;\n\tunsigned char reserved[16];\n};\n\nstruct snd_hwdep_dsp_image {\n\tunsigned int index;\n\tunsigned char name[64];\n\tunsigned char *image;\n\tsize_t length;\n\tlong unsigned int driver_data;\n};\n\nstruct snd_hwdep;\n\nstruct snd_hwdep_ops {\n\tlong long int (*llseek)(struct snd_hwdep *, struct file *, long long int, int);\n\tlong int (*read)(struct snd_hwdep *, char *, long int, loff_t *);\n\tlong int (*write)(struct snd_hwdep *, const char *, long int, loff_t *);\n\tint (*open)(struct snd_hwdep *, struct file *);\n\tint (*release)(struct snd_hwdep *, struct file *);\n\t__poll_t (*poll)(struct snd_hwdep *, struct file *, poll_table *);\n\tint (*ioctl)(struct snd_hwdep *, struct file *, unsigned int, long unsigned int);\n\tint (*ioctl_compat)(struct snd_hwdep *, struct file *, unsigned int, long unsigned int);\n\tint (*mmap)(struct snd_hwdep *, struct file *, struct vm_area_struct *);\n\tint (*dsp_status)(struct snd_hwdep *, struct snd_hwdep_dsp_status *);\n\tint (*dsp_load)(struct snd_hwdep *, struct snd_hwdep_dsp_image *);\n};\n\nstruct snd_hwdep {\n\tstruct snd_card *card;\n\tstruct list_head list;\n\tint device;\n\tchar id[32];\n\tchar name[80];\n\tint iface;\n\tstruct snd_hwdep_ops ops;\n\twait_queue_head_t open_wait;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_hwdep *);\n\tstruct device dev;\n\tstruct mutex open_mutex;\n\tint used;\n\tunsigned int dsp_loaded;\n\tunsigned int exclusive: 1;\n};\n\nstruct snd_hwdep_dsp_image32 {\n\tu32 index;\n\tunsigned char name[64];\n\tu32 image;\n\tu32 length;\n\tu32 driver_data;\n};\n\nenum {\n\tSNDRV_HWDEP_IOCTL_DSP_LOAD32 = 1079003139,\n};\n\nenum {\n\tSNDRV_TIMER_CLASS_NONE = 4294967295,\n\tSNDRV_TIMER_CLASS_SLAVE = 0,\n\tSNDRV_TIMER_CLASS_GLOBAL = 1,\n\tSNDRV_TIMER_CLASS_CARD = 2,\n\tSNDRV_TIMER_CLASS_PCM = 3,\n\tSNDRV_TIMER_CLASS_LAST = 3,\n};\n\nenum {\n\tSNDRV_TIMER_SCLASS_NONE = 0,\n\tSNDRV_TIMER_SCLASS_APPLICATION = 1,\n\tSNDRV_TIMER_SCLASS_SEQUENCER = 2,\n\tSNDRV_TIMER_SCLASS_OSS_SEQUENCER = 3,\n\tSNDRV_TIMER_SCLASS_LAST = 3,\n};\n\nstruct snd_timer_id {\n\tint dev_class;\n\tint dev_sclass;\n\tint card;\n\tint device;\n\tint subdevice;\n};\n\nstruct snd_timer_ginfo {\n\tstruct snd_timer_id tid;\n\tunsigned int flags;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tlong unsigned int reserved0;\n\tlong unsigned int resolution;\n\tlong unsigned int resolution_min;\n\tlong unsigned int resolution_max;\n\tunsigned int clients;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_gparams {\n\tstruct snd_timer_id tid;\n\tlong unsigned int period_num;\n\tlong unsigned int period_den;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_gstatus {\n\tstruct snd_timer_id tid;\n\tlong unsigned int resolution;\n\tlong unsigned int resolution_num;\n\tlong unsigned int resolution_den;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_select {\n\tstruct snd_timer_id id;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_info {\n\tunsigned int flags;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tlong unsigned int reserved0;\n\tlong unsigned int resolution;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_params {\n\tunsigned int flags;\n\tunsigned int ticks;\n\tunsigned int queue_size;\n\tunsigned int reserved0;\n\tunsigned int filter;\n\tunsigned char reserved[60];\n};\n\nstruct snd_timer_read {\n\tunsigned int resolution;\n\tunsigned int ticks;\n};\n\nenum {\n\tSNDRV_TIMER_EVENT_RESOLUTION = 0,\n\tSNDRV_TIMER_EVENT_TICK = 1,\n\tSNDRV_TIMER_EVENT_START = 2,\n\tSNDRV_TIMER_EVENT_STOP = 3,\n\tSNDRV_TIMER_EVENT_CONTINUE = 4,\n\tSNDRV_TIMER_EVENT_PAUSE = 5,\n\tSNDRV_TIMER_EVENT_EARLY = 6,\n\tSNDRV_TIMER_EVENT_SUSPEND = 7,\n\tSNDRV_TIMER_EVENT_RESUME = 8,\n\tSNDRV_TIMER_EVENT_MSTART = 12,\n\tSNDRV_TIMER_EVENT_MSTOP = 13,\n\tSNDRV_TIMER_EVENT_MCONTINUE = 14,\n\tSNDRV_TIMER_EVENT_MPAUSE = 15,\n\tSNDRV_TIMER_EVENT_MSUSPEND = 17,\n\tSNDRV_TIMER_EVENT_MRESUME = 18,\n};\n\nstruct snd_timer;\n\nstruct snd_timer_hardware {\n\tunsigned int flags;\n\tlong unsigned int resolution;\n\tlong unsigned int resolution_min;\n\tlong unsigned int resolution_max;\n\tlong unsigned int ticks;\n\tint (*open)(struct snd_timer *);\n\tint (*close)(struct snd_timer *);\n\tlong unsigned int (*c_resolution)(struct snd_timer *);\n\tint (*start)(struct snd_timer *);\n\tint (*stop)(struct snd_timer *);\n\tint (*set_period)(struct snd_timer *, long unsigned int, long unsigned int);\n\tint (*precise_resolution)(struct snd_timer *, long unsigned int *, long unsigned int *);\n};\n\nstruct snd_timer {\n\tint tmr_class;\n\tstruct snd_card *card;\n\tstruct module *module;\n\tint tmr_device;\n\tint tmr_subdevice;\n\tchar id[64];\n\tchar name[80];\n\tunsigned int flags;\n\tint running;\n\tlong unsigned int sticks;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_timer *);\n\tstruct snd_timer_hardware hw;\n\tspinlock_t lock;\n\tstruct list_head device_list;\n\tstruct list_head open_list_head;\n\tstruct list_head active_list_head;\n\tstruct list_head ack_list_head;\n\tstruct list_head sack_list_head;\n\tstruct tasklet_struct task_queue;\n\tint max_instances;\n\tint num_instances;\n};\n\nstruct snd_timer_instance {\n\tstruct snd_timer *timer;\n\tchar *owner;\n\tunsigned int flags;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_timer_instance *);\n\tvoid (*callback)(struct snd_timer_instance *, long unsigned int, long unsigned int);\n\tvoid (*ccallback)(struct snd_timer_instance *, int, struct timespec64 *, long unsigned int);\n\tvoid (*disconnect)(struct snd_timer_instance *);\n\tvoid *callback_data;\n\tlong unsigned int ticks;\n\tlong unsigned int cticks;\n\tlong unsigned int pticks;\n\tlong unsigned int resolution;\n\tlong unsigned int lost;\n\tint slave_class;\n\tunsigned int slave_id;\n\tstruct list_head open_list;\n\tstruct list_head active_list;\n\tstruct list_head ack_list;\n\tstruct list_head slave_list_head;\n\tstruct list_head slave_active_head;\n\tstruct snd_timer_instance *master;\n};\n\nenum timer_tread_format {\n\tTREAD_FORMAT_NONE = 0,\n\tTREAD_FORMAT_TIME64 = 1,\n\tTREAD_FORMAT_TIME32 = 2,\n};\n\nstruct snd_timer_tread32 {\n\tint event;\n\ts32 tstamp_sec;\n\ts32 tstamp_nsec;\n\tunsigned int val;\n};\n\nstruct snd_timer_tread64 {\n\tint event;\n\tu8 pad1[4];\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tunsigned int val;\n\tu8 pad2[4];\n};\n\nstruct snd_timer_user {\n\tstruct snd_timer_instance *timeri;\n\tint tread;\n\tlong unsigned int ticks;\n\tlong unsigned int overrun;\n\tint qhead;\n\tint qtail;\n\tint qused;\n\tint queue_size;\n\tbool disconnected;\n\tstruct snd_timer_read *queue;\n\tstruct snd_timer_tread64 *tqueue;\n\tspinlock_t qlock;\n\tlong unsigned int last_resolution;\n\tunsigned int filter;\n\tstruct timespec64 tstamp;\n\twait_queue_head_t qchange_sleep;\n\tstruct fasync_struct *fasync;\n\tstruct mutex ioctl_lock;\n};\n\nstruct snd_timer_status32 {\n\ts32 tstamp_sec;\n\ts32 tstamp_nsec;\n\tunsigned int resolution;\n\tunsigned int lost;\n\tunsigned int overrun;\n\tunsigned int queue;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_status64 {\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tunsigned int resolution;\n\tunsigned int lost;\n\tunsigned int overrun;\n\tunsigned int queue;\n\tunsigned char reserved[64];\n};\n\nstruct snd_timer_system_private {\n\tstruct timer_list tlist;\n\tstruct snd_timer *snd_timer;\n\tlong unsigned int last_expires;\n\tlong unsigned int last_jiffies;\n\tlong unsigned int correction;\n};\n\nenum {\n\tSNDRV_TIMER_IOCTL_START_OLD = 21536,\n\tSNDRV_TIMER_IOCTL_STOP_OLD = 21537,\n\tSNDRV_TIMER_IOCTL_CONTINUE_OLD = 21538,\n\tSNDRV_TIMER_IOCTL_PAUSE_OLD = 21539,\n};\n\nstruct snd_timer_gparams32 {\n\tstruct snd_timer_id tid;\n\tu32 period_num;\n\tu32 period_den;\n\tunsigned char reserved[32];\n};\n\nstruct snd_timer_info32 {\n\tu32 flags;\n\ts32 card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tu32 reserved0;\n\tu32 resolution;\n\tunsigned char reserved[64];\n};\n\nenum {\n\tSNDRV_TIMER_IOCTL_GPARAMS32 = 1077695492,\n\tSNDRV_TIMER_IOCTL_INFO32 = 2162185233,\n\tSNDRV_TIMER_IOCTL_STATUS_COMPAT32 = 1079530516,\n\tSNDRV_TIMER_IOCTL_STATUS_COMPAT64 = 1080054804,\n};\n\nstruct snd_hrtimer {\n\tstruct snd_timer *timer;\n\tstruct hrtimer hrt;\n\tbool in_callback;\n};\n\ntypedef long unsigned int snd_pcm_uframes_t;\n\ntypedef long int snd_pcm_sframes_t;\n\nenum {\n\tSNDRV_PCM_CLASS_GENERIC = 0,\n\tSNDRV_PCM_CLASS_MULTI = 1,\n\tSNDRV_PCM_CLASS_MODEM = 2,\n\tSNDRV_PCM_CLASS_DIGITIZER = 3,\n\tSNDRV_PCM_CLASS_LAST = 3,\n};\n\nenum {\n\tSNDRV_PCM_STREAM_PLAYBACK = 0,\n\tSNDRV_PCM_STREAM_CAPTURE = 1,\n\tSNDRV_PCM_STREAM_LAST = 1,\n};\n\ntypedef int snd_pcm_access_t;\n\ntypedef int snd_pcm_format_t;\n\ntypedef int snd_pcm_subformat_t;\n\ntypedef int snd_pcm_state_t;\n\nunion snd_pcm_sync_id {\n\tunsigned char id[16];\n\tshort unsigned int id16[8];\n\tunsigned int id32[4];\n};\n\nstruct snd_pcm_info {\n\tunsigned int device;\n\tunsigned int subdevice;\n\tint stream;\n\tint card;\n\tunsigned char id[64];\n\tunsigned char name[80];\n\tunsigned char subname[32];\n\tint dev_class;\n\tint dev_subclass;\n\tunsigned int subdevices_count;\n\tunsigned int subdevices_avail;\n\tunion snd_pcm_sync_id sync;\n\tunsigned char reserved[64];\n};\n\nstruct snd_interval {\n\tunsigned int min;\n\tunsigned int max;\n\tunsigned int openmin: 1;\n\tunsigned int openmax: 1;\n\tunsigned int integer: 1;\n\tunsigned int empty: 1;\n};\n\nstruct snd_mask {\n\t__u32 bits[8];\n};\n\nstruct snd_pcm_hw_params {\n\tunsigned int flags;\n\tstruct snd_mask masks[3];\n\tstruct snd_mask mres[5];\n\tstruct snd_interval intervals[12];\n\tstruct snd_interval ires[9];\n\tunsigned int rmask;\n\tunsigned int cmask;\n\tunsigned int info;\n\tunsigned int msbits;\n\tunsigned int rate_num;\n\tunsigned int rate_den;\n\tsnd_pcm_uframes_t fifo_size;\n\tunsigned char reserved[64];\n};\n\nenum {\n\tSNDRV_PCM_TSTAMP_NONE = 0,\n\tSNDRV_PCM_TSTAMP_ENABLE = 1,\n\tSNDRV_PCM_TSTAMP_LAST = 1,\n};\n\ntypedef char __pad_before_uframe[0];\n\ntypedef char __pad_after_uframe[0];\n\nstruct snd_pcm_mmap_status {\n\tsnd_pcm_state_t state;\n\t__u32 pad1;\n\t__pad_before_uframe __pad1;\n\tsnd_pcm_uframes_t hw_ptr;\n\t__pad_after_uframe __pad2;\n\tstruct __kernel_timespec tstamp;\n\tsnd_pcm_state_t suspended_state;\n\t__u32 pad3;\n\tstruct __kernel_timespec audio_tstamp;\n};\n\nstruct snd_pcm_mmap_control {\n\t__pad_before_uframe __pad1;\n\tsnd_pcm_uframes_t appl_ptr;\n\t__pad_before_uframe __pad2;\n\t__pad_before_uframe __pad3;\n\tsnd_pcm_uframes_t avail_min;\n\t__pad_after_uframe __pad4;\n};\n\nstruct snd_dma_device {\n\tint type;\n\tstruct device *dev;\n};\n\nstruct snd_dma_buffer {\n\tstruct snd_dma_device dev;\n\tunsigned char *area;\n\tdma_addr_t addr;\n\tsize_t bytes;\n\tvoid *private_data;\n};\n\nstruct snd_pcm_hardware {\n\tunsigned int info;\n\tu64 formats;\n\tunsigned int rates;\n\tunsigned int rate_min;\n\tunsigned int rate_max;\n\tunsigned int channels_min;\n\tunsigned int channels_max;\n\tsize_t buffer_bytes_max;\n\tsize_t period_bytes_min;\n\tsize_t period_bytes_max;\n\tunsigned int periods_min;\n\tunsigned int periods_max;\n\tsize_t fifo_size;\n};\n\nstruct snd_pcm_substream;\n\nstruct snd_pcm_audio_tstamp_config;\n\nstruct snd_pcm_audio_tstamp_report;\n\nstruct snd_pcm_ops {\n\tint (*open)(struct snd_pcm_substream *);\n\tint (*close)(struct snd_pcm_substream *);\n\tint (*ioctl)(struct snd_pcm_substream *, unsigned int, void *);\n\tint (*hw_params)(struct snd_pcm_substream *, struct snd_pcm_hw_params *);\n\tint (*hw_free)(struct snd_pcm_substream *);\n\tint (*prepare)(struct snd_pcm_substream *);\n\tint (*trigger)(struct snd_pcm_substream *, int);\n\tint (*sync_stop)(struct snd_pcm_substream *);\n\tsnd_pcm_uframes_t (*pointer)(struct snd_pcm_substream *);\n\tint (*get_time_info)(struct snd_pcm_substream *, struct timespec64 *, struct timespec64 *, struct snd_pcm_audio_tstamp_config *, struct snd_pcm_audio_tstamp_report *);\n\tint (*fill_silence)(struct snd_pcm_substream *, int, long unsigned int, long unsigned int);\n\tint (*copy_user)(struct snd_pcm_substream *, int, long unsigned int, void *, long unsigned int);\n\tint (*copy_kernel)(struct snd_pcm_substream *, int, long unsigned int, void *, long unsigned int);\n\tstruct page * (*page)(struct snd_pcm_substream *, long unsigned int);\n\tint (*mmap)(struct snd_pcm_substream *, struct vm_area_struct *);\n\tint (*ack)(struct snd_pcm_substream *);\n};\n\nstruct snd_pcm_group {\n\tspinlock_t lock;\n\tstruct mutex mutex;\n\tstruct list_head substreams;\n\trefcount_t refs;\n};\n\nstruct snd_pcm;\n\nstruct snd_pcm_str;\n\nstruct snd_pcm_runtime;\n\nstruct snd_pcm_substream {\n\tstruct snd_pcm *pcm;\n\tstruct snd_pcm_str *pstr;\n\tvoid *private_data;\n\tint number;\n\tchar name[32];\n\tint stream;\n\tstruct pm_qos_request latency_pm_qos_req;\n\tsize_t buffer_bytes_max;\n\tstruct snd_dma_buffer dma_buffer;\n\tsize_t dma_max;\n\tconst struct snd_pcm_ops *ops;\n\tstruct snd_pcm_runtime *runtime;\n\tstruct snd_timer *timer;\n\tunsigned int timer_running: 1;\n\tlong int wait_time;\n\tstruct snd_pcm_substream *next;\n\tstruct list_head link_list;\n\tstruct snd_pcm_group self_group;\n\tstruct snd_pcm_group *group;\n\tint ref_count;\n\tatomic_t mmap_count;\n\tunsigned int f_flags;\n\tvoid (*pcm_release)(struct snd_pcm_substream *);\n\tstruct pid *pid;\n\tstruct snd_info_entry *proc_root;\n\tunsigned int hw_opened: 1;\n\tunsigned int managed_buffer_alloc: 1;\n};\n\nstruct snd_pcm_audio_tstamp_config {\n\tu32 type_requested: 4;\n\tu32 report_delay: 1;\n};\n\nstruct snd_pcm_audio_tstamp_report {\n\tu32 valid: 1;\n\tu32 actual_type: 4;\n\tu32 accuracy_report: 1;\n\tu32 accuracy;\n};\n\nstruct snd_pcm_hw_rule;\n\ntypedef int (*snd_pcm_hw_rule_func_t)(struct snd_pcm_hw_params *, struct snd_pcm_hw_rule *);\n\nstruct snd_pcm_hw_rule {\n\tunsigned int cond;\n\tint var;\n\tint deps[4];\n\tsnd_pcm_hw_rule_func_t func;\n\tvoid *private;\n};\n\nstruct snd_pcm_hw_constraints {\n\tstruct snd_mask masks[3];\n\tstruct snd_interval intervals[12];\n\tunsigned int rules_num;\n\tunsigned int rules_all;\n\tstruct snd_pcm_hw_rule *rules;\n};\n\nstruct snd_pcm_hw_constraint_list {\n\tconst unsigned int *list;\n\tunsigned int count;\n\tunsigned int mask;\n};\n\nstruct snd_pcm_runtime {\n\tstruct snd_pcm_substream *trigger_master;\n\tstruct timespec64 trigger_tstamp;\n\tbool trigger_tstamp_latched;\n\tint overrange;\n\tsnd_pcm_uframes_t avail_max;\n\tsnd_pcm_uframes_t hw_ptr_base;\n\tsnd_pcm_uframes_t hw_ptr_interrupt;\n\tlong unsigned int hw_ptr_jiffies;\n\tlong unsigned int hw_ptr_buffer_jiffies;\n\tsnd_pcm_sframes_t delay;\n\tu64 hw_ptr_wrap;\n\tsnd_pcm_access_t access;\n\tsnd_pcm_format_t format;\n\tsnd_pcm_subformat_t subformat;\n\tunsigned int rate;\n\tunsigned int channels;\n\tsnd_pcm_uframes_t period_size;\n\tunsigned int periods;\n\tsnd_pcm_uframes_t buffer_size;\n\tsnd_pcm_uframes_t min_align;\n\tsize_t byte_align;\n\tunsigned int frame_bits;\n\tunsigned int sample_bits;\n\tunsigned int info;\n\tunsigned int rate_num;\n\tunsigned int rate_den;\n\tunsigned int no_period_wakeup: 1;\n\tint tstamp_mode;\n\tunsigned int period_step;\n\tsnd_pcm_uframes_t start_threshold;\n\tsnd_pcm_uframes_t stop_threshold;\n\tsnd_pcm_uframes_t silence_threshold;\n\tsnd_pcm_uframes_t silence_size;\n\tsnd_pcm_uframes_t boundary;\n\tsnd_pcm_uframes_t silence_start;\n\tsnd_pcm_uframes_t silence_filled;\n\tunion snd_pcm_sync_id sync;\n\tstruct snd_pcm_mmap_status *status;\n\tstruct snd_pcm_mmap_control *control;\n\tsnd_pcm_uframes_t twake;\n\twait_queue_head_t sleep;\n\twait_queue_head_t tsleep;\n\tstruct fasync_struct *fasync;\n\tbool stop_operating;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_pcm_runtime *);\n\tstruct snd_pcm_hardware hw;\n\tstruct snd_pcm_hw_constraints hw_constraints;\n\tunsigned int timer_resolution;\n\tint tstamp_type;\n\tunsigned char *dma_area;\n\tdma_addr_t dma_addr;\n\tsize_t dma_bytes;\n\tstruct snd_dma_buffer *dma_buffer_p;\n\tunsigned int buffer_changed: 1;\n\tstruct snd_pcm_audio_tstamp_config audio_tstamp_config;\n\tstruct snd_pcm_audio_tstamp_report audio_tstamp_report;\n\tstruct timespec64 driver_tstamp;\n};\n\nstruct snd_pcm_str {\n\tint stream;\n\tstruct snd_pcm *pcm;\n\tunsigned int substream_count;\n\tunsigned int substream_opened;\n\tstruct snd_pcm_substream *substream;\n\tstruct snd_info_entry *proc_root;\n\tstruct snd_kcontrol *chmap_kctl;\n\tstruct device dev;\n};\n\nstruct snd_pcm {\n\tstruct snd_card *card;\n\tstruct list_head list;\n\tint device;\n\tunsigned int info_flags;\n\tshort unsigned int dev_class;\n\tshort unsigned int dev_subclass;\n\tchar id[64];\n\tchar name[80];\n\tstruct snd_pcm_str streams[2];\n\tstruct mutex open_mutex;\n\twait_queue_head_t open_wait;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_pcm *);\n\tbool internal;\n\tbool nonatomic;\n\tbool no_device_suspend;\n};\n\nstruct snd_pcm_chmap_elem {\n\tunsigned char channels;\n\tunsigned char map[15];\n};\n\nstruct snd_pcm_status64 {\n\tsnd_pcm_state_t state;\n\tu8 rsvd[4];\n\ts64 trigger_tstamp_sec;\n\ts64 trigger_tstamp_nsec;\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tsnd_pcm_uframes_t appl_ptr;\n\tsnd_pcm_uframes_t hw_ptr;\n\tsnd_pcm_sframes_t delay;\n\tsnd_pcm_uframes_t avail;\n\tsnd_pcm_uframes_t avail_max;\n\tsnd_pcm_uframes_t overrange;\n\tsnd_pcm_state_t suspended_state;\n\t__u32 audio_tstamp_data;\n\ts64 audio_tstamp_sec;\n\ts64 audio_tstamp_nsec;\n\ts64 driver_tstamp_sec;\n\ts64 driver_tstamp_nsec;\n\t__u32 audio_tstamp_accuracy;\n\tunsigned char reserved[20];\n};\n\nenum {\n\tSNDRV_PCM_MMAP_OFFSET_DATA = 0,\n\tSNDRV_PCM_MMAP_OFFSET_STATUS_OLD = 2147483648,\n\tSNDRV_PCM_MMAP_OFFSET_CONTROL_OLD = 2164260864,\n\tSNDRV_PCM_MMAP_OFFSET_STATUS_NEW = 2181038080,\n\tSNDRV_PCM_MMAP_OFFSET_CONTROL_NEW = 2197815296,\n\tSNDRV_PCM_MMAP_OFFSET_STATUS = 2181038080,\n\tSNDRV_PCM_MMAP_OFFSET_CONTROL = 2197815296,\n};\n\ntypedef int snd_pcm_hw_param_t;\n\nstruct snd_pcm_sw_params {\n\tint tstamp_mode;\n\tunsigned int period_step;\n\tunsigned int sleep_min;\n\tsnd_pcm_uframes_t avail_min;\n\tsnd_pcm_uframes_t xfer_align;\n\tsnd_pcm_uframes_t start_threshold;\n\tsnd_pcm_uframes_t stop_threshold;\n\tsnd_pcm_uframes_t silence_threshold;\n\tsnd_pcm_uframes_t silence_size;\n\tsnd_pcm_uframes_t boundary;\n\tunsigned int proto;\n\tunsigned int tstamp_type;\n\tunsigned char reserved[56];\n};\n\nstruct snd_pcm_channel_info {\n\tunsigned int channel;\n\t__kernel_off_t offset;\n\tunsigned int first;\n\tunsigned int step;\n};\n\nenum {\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_COMPAT = 0,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT = 1,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK = 2,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ABSOLUTE = 3,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ESTIMATED = 4,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED = 5,\n\tSNDRV_PCM_AUDIO_TSTAMP_TYPE_LAST = 5,\n};\n\nstruct snd_pcm_sync_ptr {\n\t__u32 flags;\n\t__u32 pad1;\n\tunion {\n\t\tstruct snd_pcm_mmap_status status;\n\t\tunsigned char reserved[64];\n\t} s;\n\tunion {\n\t\tstruct snd_pcm_mmap_control control;\n\t\tunsigned char reserved[64];\n\t} c;\n};\n\nstruct snd_xferi {\n\tsnd_pcm_sframes_t result;\n\tvoid *buf;\n\tsnd_pcm_uframes_t frames;\n};\n\nstruct snd_xfern {\n\tsnd_pcm_sframes_t result;\n\tvoid **bufs;\n\tsnd_pcm_uframes_t frames;\n};\n\nenum {\n\tSNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0,\n\tSNDRV_PCM_TSTAMP_TYPE_MONOTONIC = 1,\n\tSNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW = 2,\n\tSNDRV_PCM_TSTAMP_TYPE_LAST = 2,\n};\n\nstruct snd_pcm_file {\n\tstruct snd_pcm_substream *substream;\n\tint no_compat_mmap;\n\tunsigned int user_pversion;\n};\n\nstruct snd_pcm_status32 {\n\tsnd_pcm_state_t state;\n\ts32 trigger_tstamp_sec;\n\ts32 trigger_tstamp_nsec;\n\ts32 tstamp_sec;\n\ts32 tstamp_nsec;\n\tu32 appl_ptr;\n\tu32 hw_ptr;\n\ts32 delay;\n\tu32 avail;\n\tu32 avail_max;\n\tu32 overrange;\n\tsnd_pcm_state_t suspended_state;\n\tu32 audio_tstamp_data;\n\ts32 audio_tstamp_sec;\n\ts32 audio_tstamp_nsec;\n\ts32 driver_tstamp_sec;\n\ts32 driver_tstamp_nsec;\n\tu32 audio_tstamp_accuracy;\n\tunsigned char reserved[36];\n};\n\nstruct snd_pcm_hw_params_old {\n\tunsigned int flags;\n\tunsigned int masks[3];\n\tstruct snd_interval intervals[12];\n\tunsigned int rmask;\n\tunsigned int cmask;\n\tunsigned int info;\n\tunsigned int msbits;\n\tunsigned int rate_num;\n\tunsigned int rate_den;\n\tsnd_pcm_uframes_t fifo_size;\n\tunsigned char reserved[64];\n};\n\nstruct action_ops {\n\tint (*pre_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n\tint (*do_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n\tvoid (*undo_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n\tvoid (*post_action)(struct snd_pcm_substream *, snd_pcm_state_t);\n};\n\nstruct snd_pcm_mmap_status32 {\n\tsnd_pcm_state_t state;\n\ts32 pad1;\n\tu32 hw_ptr;\n\ts32 tstamp_sec;\n\ts32 tstamp_nsec;\n\tsnd_pcm_state_t suspended_state;\n\ts32 audio_tstamp_sec;\n\ts32 audio_tstamp_nsec;\n};\n\nstruct snd_pcm_mmap_control32 {\n\tu32 appl_ptr;\n\tu32 avail_min;\n};\n\nstruct snd_pcm_sync_ptr32 {\n\tu32 flags;\n\tunion {\n\t\tstruct snd_pcm_mmap_status32 status;\n\t\tunsigned char reserved[64];\n\t} s;\n\tunion {\n\t\tstruct snd_pcm_mmap_control32 control;\n\t\tunsigned char reserved[64];\n\t} c;\n};\n\nstruct snd_pcm_hw_params32 {\n\tu32 flags;\n\tstruct snd_mask masks[3];\n\tstruct snd_mask mres[5];\n\tstruct snd_interval intervals[12];\n\tstruct snd_interval ires[9];\n\tu32 rmask;\n\tu32 cmask;\n\tu32 info;\n\tu32 msbits;\n\tu32 rate_num;\n\tu32 rate_den;\n\tu32 fifo_size;\n\tunsigned char reserved[64];\n};\n\nstruct snd_pcm_sw_params32 {\n\ts32 tstamp_mode;\n\tu32 period_step;\n\tu32 sleep_min;\n\tu32 avail_min;\n\tu32 xfer_align;\n\tu32 start_threshold;\n\tu32 stop_threshold;\n\tu32 silence_threshold;\n\tu32 silence_size;\n\tu32 boundary;\n\tu32 proto;\n\tu32 tstamp_type;\n\tunsigned char reserved[56];\n};\n\nstruct snd_pcm_channel_info32 {\n\tu32 channel;\n\tu32 offset;\n\tu32 first;\n\tu32 step;\n};\n\nstruct compat_snd_pcm_status64 {\n\tsnd_pcm_state_t state;\n\tu8 rsvd[4];\n\ts64 trigger_tstamp_sec;\n\ts64 trigger_tstamp_nsec;\n\ts64 tstamp_sec;\n\ts64 tstamp_nsec;\n\tu32 appl_ptr;\n\tu32 hw_ptr;\n\ts32 delay;\n\tu32 avail;\n\tu32 avail_max;\n\tu32 overrange;\n\tsnd_pcm_state_t suspended_state;\n\tu32 audio_tstamp_data;\n\ts64 audio_tstamp_sec;\n\ts64 audio_tstamp_nsec;\n\ts64 driver_tstamp_sec;\n\ts64 driver_tstamp_nsec;\n\tu32 audio_tstamp_accuracy;\n\tunsigned char reserved[20];\n};\n\nstruct snd_xferi32 {\n\ts32 result;\n\tu32 buf;\n\tu32 frames;\n};\n\nstruct snd_xfern32 {\n\ts32 result;\n\tu32 bufs;\n\tu32 frames;\n};\n\nenum {\n\tSNDRV_PCM_IOCTL_HW_REFINE32 = 3260825872,\n\tSNDRV_PCM_IOCTL_HW_PARAMS32 = 3260825873,\n\tSNDRV_PCM_IOCTL_SW_PARAMS32 = 3228057875,\n\tSNDRV_PCM_IOCTL_STATUS_COMPAT32 = 2154578208,\n\tSNDRV_PCM_IOCTL_STATUS_EXT_COMPAT32 = 3228320036,\n\tSNDRV_PCM_IOCTL_DELAY32 = 2147762465,\n\tSNDRV_PCM_IOCTL_CHANNEL_INFO32 = 2148548914,\n\tSNDRV_PCM_IOCTL_REWIND32 = 1074020678,\n\tSNDRV_PCM_IOCTL_FORWARD32 = 1074020681,\n\tSNDRV_PCM_IOCTL_WRITEI_FRAMES32 = 1074544976,\n\tSNDRV_PCM_IOCTL_READI_FRAMES32 = 2148286801,\n\tSNDRV_PCM_IOCTL_WRITEN_FRAMES32 = 1074544978,\n\tSNDRV_PCM_IOCTL_READN_FRAMES32 = 2148286803,\n\tSNDRV_PCM_IOCTL_STATUS_COMPAT64 = 2155888928,\n\tSNDRV_PCM_IOCTL_STATUS_EXT_COMPAT64 = 3229630756,\n};\n\nenum {\n\tSNDRV_CHMAP_UNKNOWN = 0,\n\tSNDRV_CHMAP_NA = 1,\n\tSNDRV_CHMAP_MONO = 2,\n\tSNDRV_CHMAP_FL = 3,\n\tSNDRV_CHMAP_FR = 4,\n\tSNDRV_CHMAP_RL = 5,\n\tSNDRV_CHMAP_RR = 6,\n\tSNDRV_CHMAP_FC = 7,\n\tSNDRV_CHMAP_LFE = 8,\n\tSNDRV_CHMAP_SL = 9,\n\tSNDRV_CHMAP_SR = 10,\n\tSNDRV_CHMAP_RC = 11,\n\tSNDRV_CHMAP_FLC = 12,\n\tSNDRV_CHMAP_FRC = 13,\n\tSNDRV_CHMAP_RLC = 14,\n\tSNDRV_CHMAP_RRC = 15,\n\tSNDRV_CHMAP_FLW = 16,\n\tSNDRV_CHMAP_FRW = 17,\n\tSNDRV_CHMAP_FLH = 18,\n\tSNDRV_CHMAP_FCH = 19,\n\tSNDRV_CHMAP_FRH = 20,\n\tSNDRV_CHMAP_TC = 21,\n\tSNDRV_CHMAP_TFL = 22,\n\tSNDRV_CHMAP_TFR = 23,\n\tSNDRV_CHMAP_TFC = 24,\n\tSNDRV_CHMAP_TRL = 25,\n\tSNDRV_CHMAP_TRR = 26,\n\tSNDRV_CHMAP_TRC = 27,\n\tSNDRV_CHMAP_TFLC = 28,\n\tSNDRV_CHMAP_TFRC = 29,\n\tSNDRV_CHMAP_TSL = 30,\n\tSNDRV_CHMAP_TSR = 31,\n\tSNDRV_CHMAP_LLFE = 32,\n\tSNDRV_CHMAP_RLFE = 33,\n\tSNDRV_CHMAP_BC = 34,\n\tSNDRV_CHMAP_BLC = 35,\n\tSNDRV_CHMAP_BRC = 36,\n\tSNDRV_CHMAP_LAST = 36,\n};\n\nstruct snd_ratnum {\n\tunsigned int num;\n\tunsigned int den_min;\n\tunsigned int den_max;\n\tunsigned int den_step;\n};\n\nstruct snd_ratden {\n\tunsigned int num_min;\n\tunsigned int num_max;\n\tunsigned int num_step;\n\tunsigned int den;\n};\n\nstruct snd_pcm_hw_constraint_ratnums {\n\tint nrats;\n\tconst struct snd_ratnum *rats;\n};\n\nstruct snd_pcm_hw_constraint_ratdens {\n\tint nrats;\n\tconst struct snd_ratden *rats;\n};\n\nstruct snd_pcm_hw_constraint_ranges {\n\tunsigned int count;\n\tconst struct snd_interval *ranges;\n\tunsigned int mask;\n};\n\nstruct snd_pcm_chmap {\n\tstruct snd_pcm *pcm;\n\tint stream;\n\tstruct snd_kcontrol *kctl;\n\tconst struct snd_pcm_chmap_elem *chmap;\n\tunsigned int max_channels;\n\tunsigned int channel_mask;\n\tvoid *private_data;\n};\n\ntypedef int (*pcm_transfer_f)(struct snd_pcm_substream *, int, long unsigned int, void *, long unsigned int);\n\ntypedef int (*pcm_copy_f)(struct snd_pcm_substream *, snd_pcm_uframes_t, void *, snd_pcm_uframes_t, snd_pcm_uframes_t, pcm_transfer_f);\n\nstruct pcm_format_data {\n\tunsigned char width;\n\tunsigned char phys;\n\tsigned char le;\n\tsigned char signd;\n\tunsigned char silence[8];\n};\n\nstruct snd_sg_page {\n\tvoid *buf;\n\tdma_addr_t addr;\n};\n\nstruct snd_sg_buf {\n\tint size;\n\tint pages;\n\tint tblsize;\n\tstruct snd_sg_page *table;\n\tstruct page **page_table;\n\tstruct device *dev;\n};\n\nstruct snd_seq_device {\n\tstruct snd_card *card;\n\tint device;\n\tconst char *id;\n\tchar name[80];\n\tint argsize;\n\tvoid *driver_data;\n\tvoid *private_data;\n\tvoid (*private_free)(struct snd_seq_device *);\n\tstruct device dev;\n};\n\nstruct snd_seq_driver {\n\tstruct device_driver driver;\n\tchar *id;\n\tint argsize;\n};\n\ntypedef atomic_t snd_use_lock_t;\n\ntypedef unsigned char snd_seq_event_type_t;\n\nstruct snd_seq_addr {\n\tunsigned char client;\n\tunsigned char port;\n};\n\nstruct snd_seq_connect {\n\tstruct snd_seq_addr sender;\n\tstruct snd_seq_addr dest;\n};\n\nstruct snd_seq_ev_note {\n\tunsigned char channel;\n\tunsigned char note;\n\tunsigned char velocity;\n\tunsigned char off_velocity;\n\tunsigned int duration;\n};\n\nstruct snd_seq_ev_ctrl {\n\tunsigned char channel;\n\tunsigned char unused1;\n\tunsigned char unused2;\n\tunsigned char unused3;\n\tunsigned int param;\n\tint value;\n};\n\nstruct snd_seq_ev_raw8 {\n\tunsigned char d[12];\n};\n\nstruct snd_seq_ev_raw32 {\n\tunsigned int d[3];\n};\n\nstruct snd_seq_ev_ext {\n\tunsigned int len;\n\tvoid *ptr;\n} __attribute__((packed));\n\nstruct snd_seq_result {\n\tint event;\n\tint result;\n};\n\nstruct snd_seq_real_time {\n\tunsigned int tv_sec;\n\tunsigned int tv_nsec;\n};\n\ntypedef unsigned int snd_seq_tick_time_t;\n\nunion snd_seq_timestamp {\n\tsnd_seq_tick_time_t tick;\n\tstruct snd_seq_real_time time;\n};\n\nstruct snd_seq_queue_skew {\n\tunsigned int value;\n\tunsigned int base;\n};\n\nstruct snd_seq_ev_queue_control {\n\tunsigned char queue;\n\tunsigned char pad[3];\n\tunion {\n\t\tint value;\n\t\tunion snd_seq_timestamp time;\n\t\tunsigned int position;\n\t\tstruct snd_seq_queue_skew skew;\n\t\tunsigned int d32[2];\n\t\tunsigned char d8[8];\n\t} param;\n};\n\nstruct snd_seq_event;\n\nstruct snd_seq_ev_quote {\n\tstruct snd_seq_addr origin;\n\tshort unsigned int value;\n\tstruct snd_seq_event *event;\n} __attribute__((packed));\n\nstruct snd_seq_event {\n\tsnd_seq_event_type_t type;\n\tunsigned char flags;\n\tchar tag;\n\tunsigned char queue;\n\tunion snd_seq_timestamp time;\n\tstruct snd_seq_addr source;\n\tstruct snd_seq_addr dest;\n\tunion {\n\t\tstruct snd_seq_ev_note note;\n\t\tstruct snd_seq_ev_ctrl control;\n\t\tstruct snd_seq_ev_raw8 raw8;\n\t\tstruct snd_seq_ev_raw32 raw32;\n\t\tstruct snd_seq_ev_ext ext;\n\t\tstruct snd_seq_ev_queue_control queue;\n\t\tunion snd_seq_timestamp time;\n\t\tstruct snd_seq_addr addr;\n\t\tstruct snd_seq_connect connect;\n\t\tstruct snd_seq_result result;\n\t\tstruct snd_seq_ev_quote quote;\n\t} data;\n} __attribute__((packed));\n\nstruct snd_seq_system_info {\n\tint queues;\n\tint clients;\n\tint ports;\n\tint channels;\n\tint cur_clients;\n\tint cur_queues;\n\tchar reserved[24];\n};\n\nstruct snd_seq_running_info {\n\tunsigned char client;\n\tunsigned char big_endian;\n\tunsigned char cpu_mode;\n\tunsigned char pad;\n\tunsigned char reserved[12];\n};\n\ntypedef int snd_seq_client_type_t;\n\nstruct snd_seq_client_info {\n\tint client;\n\tsnd_seq_client_type_t type;\n\tchar name[64];\n\tunsigned int filter;\n\tunsigned char multicast_filter[8];\n\tunsigned char event_filter[32];\n\tint num_ports;\n\tint event_lost;\n\tint card;\n\tint pid;\n\tchar reserved[56];\n};\n\nstruct snd_seq_client_pool {\n\tint client;\n\tint output_pool;\n\tint input_pool;\n\tint output_room;\n\tint output_free;\n\tint input_free;\n\tchar reserved[64];\n};\n\nstruct snd_seq_remove_events {\n\tunsigned int remove_mode;\n\tunion snd_seq_timestamp time;\n\tunsigned char queue;\n\tstruct snd_seq_addr dest;\n\tunsigned char channel;\n\tint type;\n\tchar tag;\n\tint reserved[10];\n};\n\nstruct snd_seq_port_info {\n\tstruct snd_seq_addr addr;\n\tchar name[64];\n\tunsigned int capability;\n\tunsigned int type;\n\tint midi_channels;\n\tint midi_voices;\n\tint synth_voices;\n\tint read_use;\n\tint write_use;\n\tvoid *kernel;\n\tunsigned int flags;\n\tunsigned char time_queue;\n\tchar reserved[59];\n};\n\nstruct snd_seq_queue_info {\n\tint queue;\n\tint owner;\n\tunsigned int locked: 1;\n\tchar name[64];\n\tunsigned int flags;\n\tchar reserved[60];\n};\n\nstruct snd_seq_queue_status {\n\tint queue;\n\tint events;\n\tsnd_seq_tick_time_t tick;\n\tstruct snd_seq_real_time time;\n\tint running;\n\tint flags;\n\tchar reserved[64];\n};\n\nstruct snd_seq_queue_tempo {\n\tint queue;\n\tunsigned int tempo;\n\tint ppq;\n\tunsigned int skew_value;\n\tunsigned int skew_base;\n\tchar reserved[24];\n};\n\nstruct snd_seq_queue_timer {\n\tint queue;\n\tint type;\n\tunion {\n\t\tstruct {\n\t\t\tstruct snd_timer_id id;\n\t\t\tunsigned int resolution;\n\t\t} alsa;\n\t} u;\n\tchar reserved[64];\n};\n\nstruct snd_seq_queue_client {\n\tint queue;\n\tint client;\n\tint used;\n\tchar reserved[64];\n};\n\nstruct snd_seq_port_subscribe {\n\tstruct snd_seq_addr sender;\n\tstruct snd_seq_addr dest;\n\tunsigned int voices;\n\tunsigned int flags;\n\tunsigned char queue;\n\tunsigned char pad[3];\n\tchar reserved[64];\n};\n\nstruct snd_seq_query_subs {\n\tstruct snd_seq_addr root;\n\tint type;\n\tint index;\n\tint num_subs;\n\tstruct snd_seq_addr addr;\n\tunsigned char queue;\n\tunsigned int flags;\n\tchar reserved[64];\n};\n\ntypedef struct snd_seq_real_time snd_seq_real_time_t;\n\nstruct snd_seq_port_callback {\n\tstruct module *owner;\n\tvoid *private_data;\n\tint (*subscribe)(void *, struct snd_seq_port_subscribe *);\n\tint (*unsubscribe)(void *, struct snd_seq_port_subscribe *);\n\tint (*use)(void *, struct snd_seq_port_subscribe *);\n\tint (*unuse)(void *, struct snd_seq_port_subscribe *);\n\tint (*event_input)(struct snd_seq_event *, int, void *, int, int);\n\tvoid (*private_free)(void *);\n};\n\nstruct snd_seq_pool;\n\nstruct snd_seq_event_cell {\n\tstruct snd_seq_event event;\n\tstruct snd_seq_pool *pool;\n\tstruct snd_seq_event_cell *next;\n};\n\nstruct snd_seq_pool {\n\tstruct snd_seq_event_cell *ptr;\n\tstruct snd_seq_event_cell *free;\n\tint total_elements;\n\tatomic_t counter;\n\tint size;\n\tint room;\n\tint closing;\n\tint max_used;\n\tint event_alloc_nopool;\n\tint event_alloc_failures;\n\tint event_alloc_success;\n\twait_queue_head_t output_sleep;\n\tspinlock_t lock;\n};\n\nstruct snd_seq_fifo {\n\tstruct snd_seq_pool *pool;\n\tstruct snd_seq_event_cell *head;\n\tstruct snd_seq_event_cell *tail;\n\tint cells;\n\tspinlock_t lock;\n\tsnd_use_lock_t use_lock;\n\twait_queue_head_t input_sleep;\n\tatomic_t overflow;\n};\n\nstruct snd_seq_subscribers {\n\tstruct snd_seq_port_subscribe info;\n\tstruct list_head src_list;\n\tstruct list_head dest_list;\n\tatomic_t ref_count;\n};\n\nstruct snd_seq_port_subs_info {\n\tstruct list_head list_head;\n\tunsigned int count;\n\tunsigned int exclusive: 1;\n\tstruct rw_semaphore list_mutex;\n\trwlock_t list_lock;\n\tint (*open)(void *, struct snd_seq_port_subscribe *);\n\tint (*close)(void *, struct snd_seq_port_subscribe *);\n};\n\nstruct snd_seq_client_port {\n\tstruct snd_seq_addr addr;\n\tstruct module *owner;\n\tchar name[64];\n\tstruct list_head list;\n\tsnd_use_lock_t use_lock;\n\tstruct snd_seq_port_subs_info c_src;\n\tstruct snd_seq_port_subs_info c_dest;\n\tint (*event_input)(struct snd_seq_event *, int, void *, int, int);\n\tvoid (*private_free)(void *);\n\tvoid *private_data;\n\tunsigned int closing: 1;\n\tunsigned int timestamping: 1;\n\tunsigned int time_real: 1;\n\tint time_queue;\n\tunsigned int capability;\n\tunsigned int type;\n\tint midi_channels;\n\tint midi_voices;\n\tint synth_voices;\n};\n\nstruct snd_seq_user_client {\n\tstruct file *file;\n\tstruct pid *owner;\n\tstruct snd_seq_fifo *fifo;\n\tint fifo_pool_size;\n};\n\nstruct snd_seq_kernel_client {\n\tstruct snd_card *card;\n};\n\nstruct snd_seq_client {\n\tsnd_seq_client_type_t type;\n\tunsigned int accept_input: 1;\n\tunsigned int accept_output: 1;\n\tchar name[64];\n\tint number;\n\tunsigned int filter;\n\tlong unsigned int event_filter[4];\n\tsnd_use_lock_t use_lock;\n\tint event_lost;\n\tint num_ports;\n\tstruct list_head ports_list_head;\n\trwlock_t ports_lock;\n\tstruct mutex ports_mutex;\n\tstruct mutex ioctl_mutex;\n\tint convert32;\n\tstruct snd_seq_pool *pool;\n\tunion {\n\t\tstruct snd_seq_user_client user;\n\t\tstruct snd_seq_kernel_client kernel;\n\t} data;\n};\n\nstruct snd_seq_usage {\n\tint cur;\n\tint peak;\n};\n\nstruct snd_seq_prioq {\n\tstruct snd_seq_event_cell *head;\n\tstruct snd_seq_event_cell *tail;\n\tint cells;\n\tspinlock_t lock;\n};\n\nstruct snd_seq_timer_tick {\n\tsnd_seq_tick_time_t cur_tick;\n\tlong unsigned int resolution;\n\tlong unsigned int fraction;\n};\n\nstruct snd_seq_timer {\n\tunsigned int running: 1;\n\tunsigned int initialized: 1;\n\tunsigned int tempo;\n\tint ppq;\n\tsnd_seq_real_time_t cur_time;\n\tstruct snd_seq_timer_tick tick;\n\tint tick_updated;\n\tint type;\n\tstruct snd_timer_id alsa_id;\n\tstruct snd_timer_instance *timeri;\n\tunsigned int ticks;\n\tlong unsigned int preferred_resolution;\n\tunsigned int skew;\n\tunsigned int skew_base;\n\tstruct timespec64 last_update;\n\tspinlock_t lock;\n};\n\nstruct snd_seq_queue {\n\tint queue;\n\tchar name[64];\n\tstruct snd_seq_prioq *tickq;\n\tstruct snd_seq_prioq *timeq;\n\tstruct snd_seq_timer *timer;\n\tint owner;\n\tunsigned int locked: 1;\n\tunsigned int klocked: 1;\n\tunsigned int check_again: 1;\n\tunsigned int check_blocked: 1;\n\tunsigned int flags;\n\tunsigned int info_flags;\n\tspinlock_t owner_lock;\n\tspinlock_t check_lock;\n\tlong unsigned int clients_bitmap[3];\n\tunsigned int clients;\n\tstruct mutex timer_mutex;\n\tsnd_use_lock_t use_lock;\n};\n\nstruct ioctl_handler {\n\tunsigned int cmd;\n\tint (*func)(struct snd_seq_client *, void *);\n};\n\nstruct snd_seq_port_info32 {\n\tstruct snd_seq_addr addr;\n\tchar name[64];\n\tu32 capability;\n\tu32 type;\n\ts32 midi_channels;\n\ts32 midi_voices;\n\ts32 synth_voices;\n\ts32 read_use;\n\ts32 write_use;\n\tu32 kernel;\n\tu32 flags;\n\tunsigned char time_queue;\n\tchar reserved[59];\n};\n\nenum {\n\tSNDRV_SEQ_IOCTL_CREATE_PORT32 = 3231994656,\n\tSNDRV_SEQ_IOCTL_DELETE_PORT32 = 1084511009,\n\tSNDRV_SEQ_IOCTL_GET_PORT_INFO32 = 3231994658,\n\tSNDRV_SEQ_IOCTL_SET_PORT_INFO32 = 1084511011,\n\tSNDRV_SEQ_IOCTL_QUERY_NEXT_PORT32 = 3231994706,\n};\n\ntypedef int (*snd_seq_dump_func_t)(void *, void *, int);\n\nstruct snd_seq_dummy_port {\n\tint client;\n\tint port;\n\tint duplex;\n\tint connect;\n};\n\nstruct hda_device_id {\n\t__u32 vendor_id;\n\t__u32 rev_id;\n\t__u8 api_version;\n\tconst char *name;\n\tlong unsigned int driver_data;\n};\n\ntypedef u16 hda_nid_t;\n\nstruct snd_array {\n\tunsigned int used;\n\tunsigned int alloced;\n\tunsigned int elem_size;\n\tunsigned int alloc_align;\n\tvoid *list;\n};\n\nstruct regmap___2;\n\nstruct hdac_bus;\n\nstruct hdac_widget_tree;\n\nstruct hdac_device {\n\tstruct device dev;\n\tint type;\n\tstruct hdac_bus *bus;\n\tunsigned int addr;\n\tstruct list_head list;\n\thda_nid_t afg;\n\thda_nid_t mfg;\n\tunsigned int vendor_id;\n\tunsigned int subsystem_id;\n\tunsigned int revision_id;\n\tunsigned int afg_function_id;\n\tunsigned int mfg_function_id;\n\tunsigned int afg_unsol: 1;\n\tunsigned int mfg_unsol: 1;\n\tunsigned int power_caps;\n\tconst char *vendor_name;\n\tconst char *chip_name;\n\tint (*exec_verb)(struct hdac_device *, unsigned int, unsigned int, unsigned int *);\n\tunsigned int num_nodes;\n\thda_nid_t start_nid;\n\thda_nid_t end_nid;\n\tatomic_t in_pm;\n\tstruct mutex widget_lock;\n\tstruct hdac_widget_tree *widgets;\n\tstruct regmap___2 *regmap;\n\tstruct mutex regmap_lock;\n\tstruct snd_array vendor_verbs;\n\tbool lazy_cache: 1;\n\tbool caps_overwriting: 1;\n\tbool cache_coef: 1;\n};\n\nstruct hdac_rb {\n\t__le32 *buf;\n\tdma_addr_t addr;\n\tshort unsigned int rp;\n\tshort unsigned int wp;\n\tint cmds[8];\n\tu32 res[8];\n};\n\nstruct hdac_bus_ops;\n\nstruct hdac_ext_bus_ops;\n\nstruct hdac_bus {\n\tstruct device *dev;\n\tconst struct hdac_bus_ops *ops;\n\tconst struct hdac_ext_bus_ops *ext_ops;\n\tlong unsigned int addr;\n\tvoid *remap_addr;\n\tint irq;\n\tvoid *ppcap;\n\tvoid *spbcap;\n\tvoid *mlcap;\n\tvoid *gtscap;\n\tvoid *drsmcap;\n\tstruct list_head codec_list;\n\tunsigned int num_codecs;\n\tstruct hdac_device *caddr_tbl[16];\n\tu32 unsol_queue[128];\n\tunsigned int unsol_rp;\n\tunsigned int unsol_wp;\n\tstruct work_struct unsol_work;\n\tlong unsigned int codec_mask;\n\tlong unsigned int codec_powered;\n\tstruct hdac_rb corb;\n\tstruct hdac_rb rirb;\n\tunsigned int last_cmd[8];\n\twait_queue_head_t rirb_wq;\n\tstruct snd_dma_buffer rb;\n\tstruct snd_dma_buffer posbuf;\n\tint dma_type;\n\tstruct list_head stream_list;\n\tbool chip_init: 1;\n\tbool aligned_mmio: 1;\n\tbool sync_write: 1;\n\tbool use_posbuf: 1;\n\tbool snoop: 1;\n\tbool align_bdle_4k: 1;\n\tbool reverse_assign: 1;\n\tbool corbrp_self_clear: 1;\n\tbool polling_mode: 1;\n\tbool needs_damn_long_delay: 1;\n\tint poll_count;\n\tint bdl_pos_adj;\n\tspinlock_t reg_lock;\n\tstruct mutex cmd_mutex;\n\tstruct mutex lock;\n\tstruct drm_audio_component *audio_component;\n\tlong int display_power_status;\n\tlong unsigned int display_power_active;\n\tint num_streams;\n\tint idx;\n\tstruct list_head hlink_list;\n\tbool cmd_dma_state;\n\tunsigned int sdo_limit;\n};\n\nenum {\n\tHDA_DEV_CORE = 0,\n\tHDA_DEV_LEGACY = 1,\n\tHDA_DEV_ASOC = 2,\n};\n\nstruct hdac_driver {\n\tstruct device_driver driver;\n\tint type;\n\tconst struct hda_device_id *id_table;\n\tint (*match)(struct hdac_device *, struct hdac_driver *);\n\tvoid (*unsol_event)(struct hdac_device *, unsigned int);\n\tint (*probe)(struct hdac_device *);\n\tint (*remove)(struct hdac_device *);\n\tvoid (*shutdown)(struct hdac_device *);\n};\n\nstruct hdac_bus_ops {\n\tint (*command)(struct hdac_bus *, unsigned int);\n\tint (*get_response)(struct hdac_bus *, unsigned int, unsigned int *);\n};\n\nstruct hdac_ext_bus_ops {\n\tint (*hdev_attach)(struct hdac_device *);\n\tint (*hdev_detach)(struct hdac_device *);\n};\n\nstruct hda_bus {\n\tstruct hdac_bus core;\n\tstruct snd_card *card;\n\tstruct pci_dev *pci;\n\tconst char *modelname;\n\tstruct mutex prepare_mutex;\n\tlong unsigned int pcm_dev_bits[1];\n\tunsigned int allow_bus_reset: 1;\n\tunsigned int shutdown: 1;\n\tunsigned int response_reset: 1;\n\tunsigned int in_reset: 1;\n\tunsigned int no_response_fallback: 1;\n\tunsigned int bus_probing: 1;\n\tunsigned int keep_power: 1;\n\tint primary_dig_out_type;\n\tunsigned int mixer_assigned;\n};\n\nstruct hda_codec;\n\ntypedef int (*hda_codec_patch_t)(struct hda_codec *);\n\nstruct hda_codec_ops {\n\tint (*build_controls)(struct hda_codec *);\n\tint (*build_pcms)(struct hda_codec *);\n\tint (*init)(struct hda_codec *);\n\tvoid (*free)(struct hda_codec *);\n\tvoid (*unsol_event)(struct hda_codec *, unsigned int);\n\tvoid (*set_power_state)(struct hda_codec *, hda_nid_t, unsigned int);\n\tint (*suspend)(struct hda_codec *);\n\tint (*resume)(struct hda_codec *);\n\tint (*check_power_status)(struct hda_codec *, hda_nid_t);\n\tvoid (*reboot_notify)(struct hda_codec *);\n\tvoid (*stream_pm)(struct hda_codec *, hda_nid_t, bool);\n};\n\nstruct hda_beep;\n\nstruct hda_fixup;\n\nstruct hda_codec {\n\tstruct hdac_device core;\n\tstruct hda_bus *bus;\n\tstruct snd_card *card;\n\tunsigned int addr;\n\tu32 probe_id;\n\tconst struct hda_device_id *preset;\n\tconst char *modelname;\n\tstruct hda_codec_ops patch_ops;\n\tstruct list_head pcm_list_head;\n\tvoid *spec;\n\tstruct hda_beep *beep;\n\tunsigned int beep_mode;\n\tu32 *wcaps;\n\tstruct snd_array mixers;\n\tstruct snd_array nids;\n\tstruct list_head conn_list;\n\tstruct mutex spdif_mutex;\n\tstruct mutex control_mutex;\n\tstruct snd_array spdif_out;\n\tunsigned int spdif_in_enable;\n\tconst hda_nid_t *slave_dig_outs;\n\tstruct snd_array init_pins;\n\tstruct snd_array driver_pins;\n\tstruct snd_array cvt_setups;\n\tstruct mutex user_mutex;\n\tstruct snd_hwdep *hwdep;\n\tunsigned int in_freeing: 1;\n\tunsigned int registered: 1;\n\tunsigned int display_power_control: 1;\n\tunsigned int spdif_status_reset: 1;\n\tunsigned int pin_amp_workaround: 1;\n\tunsigned int single_adc_amp: 1;\n\tunsigned int no_sticky_stream: 1;\n\tunsigned int pins_shutup: 1;\n\tunsigned int no_trigger_sense: 1;\n\tunsigned int no_jack_detect: 1;\n\tunsigned int inv_eapd: 1;\n\tunsigned int inv_jack_detect: 1;\n\tunsigned int pcm_format_first: 1;\n\tunsigned int cached_write: 1;\n\tunsigned int dp_mst: 1;\n\tunsigned int dump_coef: 1;\n\tunsigned int power_save_node: 1;\n\tunsigned int auto_runtime_pm: 1;\n\tunsigned int force_pin_prefix: 1;\n\tunsigned int link_down_at_suspend: 1;\n\tunsigned int relaxed_resume: 1;\n\tunsigned int mst_no_extra_pcms: 1;\n\tlong unsigned int power_on_acct;\n\tlong unsigned int power_off_acct;\n\tlong unsigned int power_jiffies;\n\tunsigned int (*power_filter)(struct hda_codec *, hda_nid_t, unsigned int);\n\tvoid (*proc_widget_hook)(struct snd_info_buffer *, struct hda_codec *, hda_nid_t);\n\tstruct snd_array jacktbl;\n\tlong unsigned int jackpoll_interval;\n\tstruct delayed_work jackpoll_work;\n\tint depop_delay;\n\tint fixup_id;\n\tconst struct hda_fixup *fixup_list;\n\tconst char *fixup_name;\n\tstruct snd_array verbs;\n};\n\nstruct hda_codec_driver {\n\tstruct hdac_driver core;\n\tconst struct hda_device_id *id;\n};\n\nstruct hda_pintbl;\n\nstruct hda_verb;\n\nstruct hda_fixup {\n\tint type;\n\tbool chained: 1;\n\tbool chained_before: 1;\n\tint chain_id;\n\tunion {\n\t\tconst struct hda_pintbl *pins;\n\t\tconst struct hda_verb *verbs;\n\t\tvoid (*func)(struct hda_codec *, const struct hda_fixup *, int);\n\t} v;\n};\n\nstruct hda_verb {\n\thda_nid_t nid;\n\tu32 verb;\n\tu32 param;\n};\n\nstruct hda_pintbl {\n\thda_nid_t nid;\n\tu32 val;\n};\n\nenum {\n\tAC_WID_AUD_OUT = 0,\n\tAC_WID_AUD_IN = 1,\n\tAC_WID_AUD_MIX = 2,\n\tAC_WID_AUD_SEL = 3,\n\tAC_WID_PIN = 4,\n\tAC_WID_POWER = 5,\n\tAC_WID_VOL_KNB = 6,\n\tAC_WID_BEEP = 7,\n\tAC_WID_VENDOR = 15,\n};\n\nenum {\n\tHDA_INPUT = 0,\n\tHDA_OUTPUT = 1,\n};\n\nstruct hda_pcm_stream;\n\nstruct hda_pcm_ops {\n\tint (*open)(struct hda_pcm_stream *, struct hda_codec *, struct snd_pcm_substream *);\n\tint (*close)(struct hda_pcm_stream *, struct hda_codec *, struct snd_pcm_substream *);\n\tint (*prepare)(struct hda_pcm_stream *, struct hda_codec *, unsigned int, unsigned int, struct snd_pcm_substream *);\n\tint (*cleanup)(struct hda_pcm_stream *, struct hda_codec *, struct snd_pcm_substream *);\n\tunsigned int (*get_delay)(struct hda_pcm_stream *, struct hda_codec *, struct snd_pcm_substream *);\n};\n\nstruct hda_pcm_stream {\n\tunsigned int substreams;\n\tunsigned int channels_min;\n\tunsigned int channels_max;\n\thda_nid_t nid;\n\tu32 rates;\n\tu64 formats;\n\tunsigned int maxbps;\n\tconst struct snd_pcm_chmap_elem *chmap;\n\tstruct hda_pcm_ops ops;\n};\n\nenum {\n\tHDA_PCM_TYPE_AUDIO = 0,\n\tHDA_PCM_TYPE_SPDIF = 1,\n\tHDA_PCM_TYPE_HDMI = 2,\n\tHDA_PCM_TYPE_MODEM = 3,\n\tHDA_PCM_NTYPES = 4,\n};\n\nstruct hda_pcm {\n\tchar *name;\n\tstruct hda_pcm_stream stream[2];\n\tunsigned int pcm_type;\n\tint device;\n\tstruct snd_pcm *pcm;\n\tbool own_chmap;\n\tstruct hda_codec *codec;\n\tstruct kref kref;\n\tstruct list_head list;\n};\n\nstruct hda_beep {\n\tstruct input_dev *dev;\n\tstruct hda_codec *codec;\n\tchar phys[32];\n\tint tone;\n\thda_nid_t nid;\n\tunsigned int registered: 1;\n\tunsigned int enabled: 1;\n\tunsigned int linear_tone: 1;\n\tunsigned int playing: 1;\n\tstruct work_struct beep_work;\n\tstruct mutex mutex;\n\tvoid (*power_hook)(struct hda_beep *, bool);\n};\n\nstruct hda_pincfg {\n\thda_nid_t nid;\n\tunsigned char ctrl;\n\tunsigned char target;\n\tunsigned int cfg;\n};\n\nstruct hda_spdif_out {\n\thda_nid_t nid;\n\tunsigned int status;\n\tshort unsigned int ctls;\n};\n\nenum {\n\tHDA_VMUTE_OFF = 0,\n\tHDA_VMUTE_ON = 1,\n\tHDA_VMUTE_FOLLOW_MASTER = 2,\n};\n\nstruct hda_vmaster_mute_hook {\n\tstruct snd_kcontrol *sw_kctl;\n\tvoid (*hook)(void *, int);\n\tunsigned int mute_mode;\n\tstruct hda_codec *codec;\n};\n\nstruct hda_input_mux_item {\n\tchar label[32];\n\tunsigned int index;\n};\n\nstruct hda_input_mux {\n\tunsigned int num_items;\n\tstruct hda_input_mux_item items[16];\n};\n\nenum {\n\tHDA_FRONT = 0,\n\tHDA_REAR = 1,\n\tHDA_CLFE = 2,\n\tHDA_SIDE = 3,\n};\n\nenum {\n\tHDA_DIG_NONE = 0,\n\tHDA_DIG_EXCLUSIVE = 1,\n\tHDA_DIG_ANALOG_DUP = 2,\n};\n\nstruct hda_multi_out {\n\tint num_dacs;\n\tconst hda_nid_t *dac_nids;\n\thda_nid_t hp_nid;\n\thda_nid_t hp_out_nid[5];\n\thda_nid_t extra_out_nid[5];\n\thda_nid_t dig_out_nid;\n\tconst hda_nid_t *slave_dig_outs;\n\tint max_channels;\n\tint dig_out_used;\n\tint no_share_stream;\n\tint share_spdif;\n\tunsigned int analog_rates;\n\tunsigned int analog_maxbps;\n\tu64 analog_formats;\n\tunsigned int spdif_rates;\n\tunsigned int spdif_maxbps;\n\tu64 spdif_formats;\n};\n\nstruct hda_nid_item {\n\tstruct snd_kcontrol *kctl;\n\tunsigned int index;\n\thda_nid_t nid;\n\tshort unsigned int flags;\n};\n\nstruct hda_amp_list {\n\thda_nid_t nid;\n\tunsigned char dir;\n\tunsigned char idx;\n};\n\nstruct hda_loopback_check {\n\tconst struct hda_amp_list *amplist;\n\tint power_on;\n};\n\nstruct hda_conn_list {\n\tstruct list_head list;\n\tint len;\n\thda_nid_t nid;\n\thda_nid_t conns[0];\n};\n\nstruct hda_cvt_setup {\n\thda_nid_t nid;\n\tu8 stream_tag;\n\tu8 channel_id;\n\tu16 format_id;\n\tunsigned char active;\n\tunsigned char dirty;\n};\n\ntypedef int (*map_slave_func_t)(struct hda_codec *, void *, struct snd_kcontrol *);\n\nstruct slave_init_arg {\n\tstruct hda_codec *codec;\n\tint step;\n};\n\nenum {\n\tAC_JACK_LINE_OUT = 0,\n\tAC_JACK_SPEAKER = 1,\n\tAC_JACK_HP_OUT = 2,\n\tAC_JACK_CD = 3,\n\tAC_JACK_SPDIF_OUT = 4,\n\tAC_JACK_DIG_OTHER_OUT = 5,\n\tAC_JACK_MODEM_LINE_SIDE = 6,\n\tAC_JACK_MODEM_HAND_SIDE = 7,\n\tAC_JACK_LINE_IN = 8,\n\tAC_JACK_AUX = 9,\n\tAC_JACK_MIC_IN = 10,\n\tAC_JACK_TELEPHONY = 11,\n\tAC_JACK_SPDIF_IN = 12,\n\tAC_JACK_DIG_OTHER_IN = 13,\n\tAC_JACK_OTHER = 15,\n};\n\nenum {\n\tAC_JACK_PORT_COMPLEX = 0,\n\tAC_JACK_PORT_NONE = 1,\n\tAC_JACK_PORT_FIXED = 2,\n\tAC_JACK_PORT_BOTH = 3,\n};\n\nenum {\n\tAUTO_PIN_LINE_OUT = 0,\n\tAUTO_PIN_SPEAKER_OUT = 1,\n\tAUTO_PIN_HP_OUT = 2,\n};\n\nstruct auto_pin_cfg_item {\n\thda_nid_t pin;\n\tint type;\n\tunsigned int is_headset_mic: 1;\n\tunsigned int is_headphone_mic: 1;\n\tunsigned int has_boost_on_pin: 1;\n};\n\nstruct auto_pin_cfg {\n\tint line_outs;\n\thda_nid_t line_out_pins[5];\n\tint speaker_outs;\n\thda_nid_t speaker_pins[5];\n\tint hp_outs;\n\tint line_out_type;\n\thda_nid_t hp_pins[5];\n\tint num_inputs;\n\tstruct auto_pin_cfg_item inputs[8];\n\tint dig_outs;\n\thda_nid_t dig_out_pins[2];\n\thda_nid_t dig_in_pin;\n\thda_nid_t mono_out_pin;\n\tint dig_out_type[2];\n\tint dig_in_type;\n};\n\nstruct hda_jack_callback;\n\ntypedef void (*hda_jack_callback_fn)(struct hda_codec *, struct hda_jack_callback *);\n\nstruct hda_jack_tbl;\n\nstruct hda_jack_callback {\n\thda_nid_t nid;\n\tint dev_id;\n\thda_jack_callback_fn func;\n\tunsigned int private_data;\n\tunsigned int unsol_res;\n\tstruct hda_jack_tbl *jack;\n\tstruct hda_jack_callback *next;\n};\n\nstruct hda_jack_tbl {\n\thda_nid_t nid;\n\tint dev_id;\n\tunsigned char tag;\n\tstruct hda_jack_callback *callback;\n\tunsigned int pin_sense;\n\tunsigned int jack_detect: 1;\n\tunsigned int jack_dirty: 1;\n\tunsigned int phantom_jack: 1;\n\tunsigned int block_report: 1;\n\thda_nid_t gating_jack;\n\thda_nid_t gated_jack;\n\tint type;\n\tint button_state;\n\tstruct snd_jack *jack;\n};\n\nstruct hda_jack_keymap {\n\tenum snd_jack_types type;\n\tint key;\n};\n\nenum {\n\tHDA_JACK_NOT_PRESENT = 0,\n\tHDA_JACK_PRESENT = 1,\n\tHDA_JACK_PHANTOM = 2,\n};\n\nenum {\n\tAC_JACK_LOC_NONE = 0,\n\tAC_JACK_LOC_REAR = 1,\n\tAC_JACK_LOC_FRONT = 2,\n\tAC_JACK_LOC_LEFT = 3,\n\tAC_JACK_LOC_RIGHT = 4,\n\tAC_JACK_LOC_TOP = 5,\n\tAC_JACK_LOC_BOTTOM = 6,\n};\n\nenum {\n\tAC_JACK_LOC_EXTERNAL = 0,\n\tAC_JACK_LOC_INTERNAL = 16,\n\tAC_JACK_LOC_SEPARATE = 32,\n\tAC_JACK_LOC_OTHER = 48,\n};\n\nenum {\n\tAC_JACK_LOC_REAR_PANEL = 7,\n\tAC_JACK_LOC_DRIVE_BAY = 8,\n\tAC_JACK_LOC_RISER = 23,\n\tAC_JACK_LOC_HDMI = 24,\n\tAC_JACK_LOC_ATAPI = 25,\n\tAC_JACK_LOC_MOBILE_IN = 55,\n\tAC_JACK_LOC_MOBILE_OUT = 56,\n};\n\nstruct hda_model_fixup {\n\tconst int id;\n\tconst char *name;\n};\n\nstruct snd_hda_pin_quirk {\n\tunsigned int codec;\n\tshort unsigned int subvendor;\n\tconst struct hda_pintbl *pins;\n\tint value;\n};\n\nenum {\n\tHDA_FIXUP_INVALID = 0,\n\tHDA_FIXUP_PINS = 1,\n\tHDA_FIXUP_VERBS = 2,\n\tHDA_FIXUP_FUNC = 3,\n\tHDA_FIXUP_PINCTLS = 4,\n};\n\nenum {\n\tHDA_FIXUP_ACT_PRE_PROBE = 0,\n\tHDA_FIXUP_ACT_PROBE = 1,\n\tHDA_FIXUP_ACT_INIT = 2,\n\tHDA_FIXUP_ACT_BUILD = 3,\n\tHDA_FIXUP_ACT_FREE = 4,\n};\n\nenum {\n\tAUTO_PIN_MIC = 0,\n\tAUTO_PIN_LINE_IN = 1,\n\tAUTO_PIN_CD = 2,\n\tAUTO_PIN_AUX = 3,\n\tAUTO_PIN_LAST = 4,\n};\n\nenum {\n\tINPUT_PIN_ATTR_UNUSED = 0,\n\tINPUT_PIN_ATTR_INT = 1,\n\tINPUT_PIN_ATTR_DOCK = 2,\n\tINPUT_PIN_ATTR_NORMAL = 3,\n\tINPUT_PIN_ATTR_REAR = 4,\n\tINPUT_PIN_ATTR_FRONT = 5,\n\tINPUT_PIN_ATTR_LAST = 5,\n};\n\nstruct auto_out_pin {\n\thda_nid_t pin;\n\tshort int seq;\n};\n\nstruct snd_compr_stream;\n\nstruct hdac_stream {\n\tstruct hdac_bus *bus;\n\tstruct snd_dma_buffer bdl;\n\t__le32 *posbuf;\n\tint direction;\n\tunsigned int bufsize;\n\tunsigned int period_bytes;\n\tunsigned int frags;\n\tunsigned int fifo_size;\n\tvoid *sd_addr;\n\tu32 sd_int_sta_mask;\n\tstruct snd_pcm_substream *substream;\n\tstruct snd_compr_stream *cstream;\n\tunsigned int format_val;\n\tunsigned char stream_tag;\n\tunsigned char index;\n\tint assigned_key;\n\tbool opened: 1;\n\tbool running: 1;\n\tbool prepared: 1;\n\tbool no_period_wakeup: 1;\n\tbool locked: 1;\n\tbool stripe: 1;\n\tu64 curr_pos;\n\tlong unsigned int start_wallclk;\n\tlong unsigned int period_wallclk;\n\tstruct timecounter tc;\n\tstruct cyclecounter cc;\n\tint delay_negative_threshold;\n\tstruct list_head list;\n};\n\nstruct azx_dev {\n\tstruct hdac_stream core;\n\tunsigned int irq_pending: 1;\n\tunsigned int insufficient: 1;\n};\n\nstruct azx;\n\nstruct hda_controller_ops {\n\tint (*disable_msi_reset_irq)(struct azx *);\n\tvoid (*pcm_mmap_prepare)(struct snd_pcm_substream *, struct vm_area_struct *);\n\tint (*position_check)(struct azx *, struct azx_dev *);\n\tint (*link_power)(struct azx *, bool);\n};\n\ntypedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *);\n\ntypedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int);\n\nstruct azx {\n\tstruct hda_bus bus;\n\tstruct snd_card *card;\n\tstruct pci_dev *pci;\n\tint dev_index;\n\tint driver_type;\n\tunsigned int driver_caps;\n\tint playback_streams;\n\tint playback_index_offset;\n\tint capture_streams;\n\tint capture_index_offset;\n\tint num_streams;\n\tint jackpoll_interval;\n\tconst struct hda_controller_ops *ops;\n\tazx_get_pos_callback_t get_position[2];\n\tazx_get_delay_callback_t get_delay[2];\n\tstruct mutex open_mutex;\n\tstruct list_head pcm_list;\n\tint codec_probe_mask;\n\tunsigned int beep_mode;\n\tint bdl_pos_adj;\n\tunsigned int running: 1;\n\tunsigned int fallback_to_single_cmd: 1;\n\tunsigned int single_cmd: 1;\n\tunsigned int msi: 1;\n\tunsigned int probing: 1;\n\tunsigned int snoop: 1;\n\tunsigned int uc_buffer: 1;\n\tunsigned int align_buffer_size: 1;\n\tunsigned int region_requested: 1;\n\tunsigned int disabled: 1;\n\tunsigned int gts_present: 1;\n};\n\nstruct azx_pcm {\n\tstruct azx *chip;\n\tstruct snd_pcm *pcm;\n\tstruct hda_codec *codec;\n\tstruct hda_pcm *info;\n\tstruct list_head list;\n};\n\nstruct trace_event_raw_azx_pcm_trigger {\n\tstruct trace_entry ent;\n\tint card;\n\tint idx;\n\tint cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_azx_get_position {\n\tstruct trace_entry ent;\n\tint card;\n\tint idx;\n\tunsigned int pos;\n\tunsigned int delay;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_azx_pcm {\n\tstruct trace_entry ent;\n\tunsigned char stream_tag;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_azx_pcm_trigger {};\n\nstruct trace_event_data_offsets_azx_get_position {};\n\nstruct trace_event_data_offsets_azx_pcm {};\n\ntypedef void (*btf_trace_azx_pcm_trigger)(void *, struct azx *, struct azx_dev *, int);\n\ntypedef void (*btf_trace_azx_get_position)(void *, struct azx *, struct azx_dev *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_azx_pcm_open)(void *, struct azx *, struct azx_dev *);\n\ntypedef void (*btf_trace_azx_pcm_close)(void *, struct azx *, struct azx_dev *);\n\ntypedef void (*btf_trace_azx_pcm_hw_params)(void *, struct azx *, struct azx_dev *);\n\ntypedef void (*btf_trace_azx_pcm_prepare)(void *, struct azx *, struct azx_dev *);\n\nenum {\n\tSNDRV_HWDEP_IFACE_OPL2 = 0,\n\tSNDRV_HWDEP_IFACE_OPL3 = 1,\n\tSNDRV_HWDEP_IFACE_OPL4 = 2,\n\tSNDRV_HWDEP_IFACE_SB16CSP = 3,\n\tSNDRV_HWDEP_IFACE_EMU10K1 = 4,\n\tSNDRV_HWDEP_IFACE_YSS225 = 5,\n\tSNDRV_HWDEP_IFACE_ICS2115 = 6,\n\tSNDRV_HWDEP_IFACE_SSCAPE = 7,\n\tSNDRV_HWDEP_IFACE_VX = 8,\n\tSNDRV_HWDEP_IFACE_MIXART = 9,\n\tSNDRV_HWDEP_IFACE_USX2Y = 10,\n\tSNDRV_HWDEP_IFACE_EMUX_WAVETABLE = 11,\n\tSNDRV_HWDEP_IFACE_BLUETOOTH = 12,\n\tSNDRV_HWDEP_IFACE_USX2Y_PCM = 13,\n\tSNDRV_HWDEP_IFACE_PCXHR = 14,\n\tSNDRV_HWDEP_IFACE_SB_RC = 15,\n\tSNDRV_HWDEP_IFACE_HDA = 16,\n\tSNDRV_HWDEP_IFACE_USB_STREAM = 17,\n\tSNDRV_HWDEP_IFACE_FW_DICE = 18,\n\tSNDRV_HWDEP_IFACE_FW_FIREWORKS = 19,\n\tSNDRV_HWDEP_IFACE_FW_BEBOB = 20,\n\tSNDRV_HWDEP_IFACE_FW_OXFW = 21,\n\tSNDRV_HWDEP_IFACE_FW_DIGI00X = 22,\n\tSNDRV_HWDEP_IFACE_FW_TASCAM = 23,\n\tSNDRV_HWDEP_IFACE_LINE6 = 24,\n\tSNDRV_HWDEP_IFACE_FW_MOTU = 25,\n\tSNDRV_HWDEP_IFACE_FW_FIREFACE = 26,\n\tSNDRV_HWDEP_IFACE_LAST = 26,\n};\n\nstruct hda_verb_ioctl {\n\tu32 verb;\n\tu32 res;\n};\n\nenum {\n\tSND_INTEL_DSP_DRIVER_ANY = 0,\n\tSND_INTEL_DSP_DRIVER_LEGACY = 1,\n\tSND_INTEL_DSP_DRIVER_SST = 2,\n\tSND_INTEL_DSP_DRIVER_SOF = 3,\n\tSND_INTEL_DSP_DRIVER_LAST = 3,\n};\n\nenum {\n\tAZX_SNOOP_TYPE_NONE = 0,\n\tAZX_SNOOP_TYPE_SCH = 1,\n\tAZX_SNOOP_TYPE_ATI = 2,\n\tAZX_SNOOP_TYPE_NVIDIA = 3,\n};\n\nstruct hda_intel {\n\tstruct azx chip;\n\tstruct work_struct irq_pending_work;\n\tstruct completion probe_wait;\n\tstruct work_struct probe_work;\n\tstruct list_head list;\n\tunsigned int irq_pending_warned: 1;\n\tunsigned int probe_continued: 1;\n\tunsigned int use_vga_switcheroo: 1;\n\tunsigned int vga_switcheroo_registered: 1;\n\tunsigned int init_failed: 1;\n\tunsigned int freed: 1;\n\tbool need_i915_power: 1;\n};\n\nstruct trace_event_raw_hda_pm {\n\tstruct trace_entry ent;\n\tint dev_index;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_hda_pm {};\n\ntypedef void (*btf_trace_azx_suspend)(void *, struct azx *);\n\ntypedef void (*btf_trace_azx_resume)(void *, struct azx *);\n\ntypedef void (*btf_trace_azx_runtime_suspend)(void *, struct azx *);\n\ntypedef void (*btf_trace_azx_runtime_resume)(void *, struct azx *);\n\nenum {\n\tPOS_FIX_AUTO = 0,\n\tPOS_FIX_LPIB = 1,\n\tPOS_FIX_POSBUF = 2,\n\tPOS_FIX_VIACOMBO = 3,\n\tPOS_FIX_COMBO = 4,\n\tPOS_FIX_SKL = 5,\n\tPOS_FIX_FIFO = 6,\n};\n\nenum {\n\tAZX_DRIVER_ICH = 0,\n\tAZX_DRIVER_PCH = 1,\n\tAZX_DRIVER_SCH = 2,\n\tAZX_DRIVER_SKL = 3,\n\tAZX_DRIVER_HDMI = 4,\n\tAZX_DRIVER_ATI = 5,\n\tAZX_DRIVER_ATIHDMI = 6,\n\tAZX_DRIVER_ATIHDMI_NS = 7,\n\tAZX_DRIVER_VIA = 8,\n\tAZX_DRIVER_SIS = 9,\n\tAZX_DRIVER_ULI = 10,\n\tAZX_DRIVER_NVIDIA = 11,\n\tAZX_DRIVER_TERA = 12,\n\tAZX_DRIVER_CTX = 13,\n\tAZX_DRIVER_CTHDA = 14,\n\tAZX_DRIVER_CMEDIA = 15,\n\tAZX_DRIVER_ZHAOXIN = 16,\n\tAZX_DRIVER_GENERIC = 17,\n\tAZX_NUM_DRIVERS = 18,\n};\n\nenum {\n\tAC_GRP_AUDIO_FUNCTION = 1,\n\tAC_GRP_MODEM_FUNCTION = 2,\n};\n\nstruct hda_vendor_id {\n\tunsigned int id;\n\tconst char *name;\n};\n\nstruct hda_rate_tbl {\n\tunsigned int hz;\n\tunsigned int alsa_bits;\n\tunsigned int hda_fmt;\n};\n\nstruct hdac_widget_tree {\n\tstruct kobject *root;\n\tstruct kobject *afg;\n\tstruct kobject **nodes;\n};\n\nstruct widget_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct hdac_device *, hda_nid_t, struct widget_attribute *, char *);\n\tssize_t (*store)(struct hdac_device *, hda_nid_t, struct widget_attribute *, const char *, size_t);\n};\n\nstruct hdac_cea_channel_speaker_allocation {\n\tint ca_index;\n\tint speakers[8];\n\tint channels;\n\tint spk_mask;\n};\n\nstruct hdac_chmap;\n\nstruct hdac_chmap_ops {\n\tint (*chmap_cea_alloc_validate_get_type)(struct hdac_chmap *, struct hdac_cea_channel_speaker_allocation *, int);\n\tvoid (*cea_alloc_to_tlv_chmap)(struct hdac_chmap *, struct hdac_cea_channel_speaker_allocation *, unsigned int *, int);\n\tint (*chmap_validate)(struct hdac_chmap *, int, int, unsigned char *);\n\tint (*get_spk_alloc)(struct hdac_device *, int);\n\tvoid (*get_chmap)(struct hdac_device *, int, unsigned char *);\n\tvoid (*set_chmap)(struct hdac_device *, int, unsigned char *, int);\n\tbool (*is_pcm_attached)(struct hdac_device *, int);\n\tint (*pin_get_slot_channel)(struct hdac_device *, hda_nid_t, int);\n\tint (*pin_set_slot_channel)(struct hdac_device *, hda_nid_t, int, int);\n\tvoid (*set_channel_count)(struct hdac_device *, hda_nid_t, int);\n};\n\nstruct hdac_chmap {\n\tunsigned int channels_max;\n\tstruct hdac_chmap_ops ops;\n\tstruct hdac_device *hdac;\n};\n\nenum cea_speaker_placement {\n\tFL = 1,\n\tFC = 2,\n\tFR = 4,\n\tFLC = 8,\n\tFRC = 16,\n\tRL = 32,\n\tRC = 64,\n\tRR = 128,\n\tRLC = 256,\n\tRRC = 512,\n\tLFE = 1024,\n\tFLW = 2048,\n\tFRW = 4096,\n\tFLH = 8192,\n\tFCH = 16384,\n\tFRH = 32768,\n\tTC = 65536,\n};\n\nstruct channel_map_table {\n\tunsigned char map;\n\tint spk_mask;\n};\n\nstruct trace_event_raw_hda_send_cmd {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hda_get_response {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hda_unsol_event {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_hdac_stream {\n\tstruct trace_entry ent;\n\tunsigned char stream_tag;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_hda_send_cmd {\n\tu32 msg;\n};\n\nstruct trace_event_data_offsets_hda_get_response {\n\tu32 msg;\n};\n\nstruct trace_event_data_offsets_hda_unsol_event {\n\tu32 msg;\n};\n\nstruct trace_event_data_offsets_hdac_stream {};\n\ntypedef void (*btf_trace_hda_send_cmd)(void *, struct hdac_bus *, unsigned int);\n\ntypedef void (*btf_trace_hda_get_response)(void *, struct hdac_bus *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_hda_unsol_event)(void *, struct hdac_bus *, u32, u32);\n\ntypedef void (*btf_trace_snd_hdac_stream_start)(void *, struct hdac_bus *, struct hdac_stream *);\n\ntypedef void (*btf_trace_snd_hdac_stream_stop)(void *, struct hdac_bus *, struct hdac_stream *);\n\nstruct component_match___2;\n\nstruct nhlt_specific_cfg {\n\tu32 size;\n\tu8 caps[0];\n};\n\nstruct nhlt_endpoint {\n\tu32 length;\n\tu8 linktype;\n\tu8 instance_id;\n\tu16 vendor_id;\n\tu16 device_id;\n\tu16 revision_id;\n\tu32 subsystem_id;\n\tu8 device_type;\n\tu8 direction;\n\tu8 virtual_bus_id;\n\tstruct nhlt_specific_cfg config;\n} __attribute__((packed));\n\nstruct nhlt_acpi_table {\n\tstruct acpi_table_header header;\n\tu8 endpoint_count;\n\tstruct nhlt_endpoint desc[0];\n} __attribute__((packed));\n\nstruct config_entry {\n\tu32 flags;\n\tu16 device;\n\tconst struct dmi_system_id *dmi_table;\n};\n\nenum nhlt_link_type {\n\tNHLT_LINK_HDA = 0,\n\tNHLT_LINK_DSP = 1,\n\tNHLT_LINK_DMIC = 2,\n\tNHLT_LINK_SSP = 3,\n\tNHLT_LINK_INVALID = 4,\n};\n\nstruct nhlt_device_specific_config {\n\tu8 virtual_slot;\n\tu8 config_type;\n};\n\nstruct nhlt_dmic_array_config {\n\tstruct nhlt_device_specific_config device_config;\n\tu8 array_type;\n};\n\nstruct nhlt_vendor_dmic_array_config {\n\tstruct nhlt_dmic_array_config dmic_config;\n\tu8 nb_mics;\n};\n\nenum {\n\tNHLT_MIC_ARRAY_2CH_SMALL = 10,\n\tNHLT_MIC_ARRAY_2CH_BIG = 11,\n\tNHLT_MIC_ARRAY_4CH_1ST_GEOM = 12,\n\tNHLT_MIC_ARRAY_4CH_L_SHAPED = 13,\n\tNHLT_MIC_ARRAY_4CH_2ND_GEOM = 14,\n\tNHLT_MIC_ARRAY_VENDOR_DEFINED = 15,\n};\n\nstruct net_device_devres {\n\tstruct net_device *ndev;\n};\n\nstruct __kernel_old_timespec {\n\t__kernel_old_time_t tv_sec;\n\tlong int tv_nsec;\n};\n\nstruct __kernel_sock_timeval {\n\t__s64 tv_sec;\n\t__s64 tv_usec;\n};\n\nstruct mmsghdr {\n\tstruct user_msghdr msg_hdr;\n\tunsigned int msg_len;\n};\n\nstruct scm_timestamping_internal {\n\tstruct timespec64 ts[3];\n};\n\nenum sock_shutdown_cmd {\n\tSHUT_RD = 0,\n\tSHUT_WR = 1,\n\tSHUT_RDWR = 2,\n};\n\nstruct net_proto_family {\n\tint family;\n\tint (*create)(struct net *, struct socket *, int, int);\n\tstruct module *owner;\n};\n\nenum {\n\tSOCK_WAKE_IO = 0,\n\tSOCK_WAKE_WAITD = 1,\n\tSOCK_WAKE_SPACE = 2,\n\tSOCK_WAKE_URG = 3,\n};\n\nstruct ifconf {\n\tint ifc_len;\n\tunion {\n\t\tchar *ifcu_buf;\n\t\tstruct ifreq *ifcu_req;\n\t} ifc_ifcu;\n};\n\nstruct compat_ifmap {\n\tcompat_ulong_t mem_start;\n\tcompat_ulong_t mem_end;\n\tshort unsigned int base_addr;\n\tunsigned char irq;\n\tunsigned char dma;\n\tunsigned char port;\n};\n\nstruct compat_if_settings {\n\tunsigned int type;\n\tunsigned int size;\n\tcompat_uptr_t ifs_ifsu;\n};\n\nstruct compat_ifreq {\n\tunion {\n\t\tchar ifrn_name[16];\n\t} ifr_ifrn;\n\tunion {\n\t\tstruct sockaddr ifru_addr;\n\t\tstruct sockaddr ifru_dstaddr;\n\t\tstruct sockaddr ifru_broadaddr;\n\t\tstruct sockaddr ifru_netmask;\n\t\tstruct sockaddr ifru_hwaddr;\n\t\tshort int ifru_flags;\n\t\tcompat_int_t ifru_ivalue;\n\t\tcompat_int_t ifru_mtu;\n\t\tstruct compat_ifmap ifru_map;\n\t\tchar ifru_slave[16];\n\t\tchar ifru_newname[16];\n\t\tcompat_caddr_t ifru_data;\n\t\tstruct compat_if_settings ifru_settings;\n\t} ifr_ifru;\n};\n\nstruct compat_ifconf {\n\tcompat_int_t ifc_len;\n\tcompat_caddr_t ifcbuf;\n};\n\nstruct compat_ethtool_rx_flow_spec {\n\tu32 flow_type;\n\tunion ethtool_flow_union h_u;\n\tstruct ethtool_flow_ext h_ext;\n\tunion ethtool_flow_union m_u;\n\tstruct ethtool_flow_ext m_ext;\n\tcompat_u64 ring_cookie;\n\tu32 location;\n} __attribute__((packed));\n\nstruct compat_ethtool_rxnfc {\n\tu32 cmd;\n\tu32 flow_type;\n\tcompat_u64 data;\n\tstruct compat_ethtool_rx_flow_spec fs;\n\tu32 rule_cnt;\n\tu32 rule_locs[0];\n} __attribute__((packed));\n\nstruct compat_mmsghdr {\n\tstruct compat_msghdr msg_hdr;\n\tcompat_uint_t msg_len;\n};\n\nstruct scm_ts_pktinfo {\n\t__u32 if_index;\n\t__u32 pkt_length;\n\t__u32 reserved[2];\n};\n\nstruct sock_skb_cb {\n\tu32 dropcount;\n};\n\nstruct sock_extended_err {\n\t__u32 ee_errno;\n\t__u8 ee_origin;\n\t__u8 ee_type;\n\t__u8 ee_code;\n\t__u8 ee_pad;\n\t__u32 ee_info;\n\t__u32 ee_data;\n};\n\nstruct sock_exterr_skb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tstruct sock_extended_err ee;\n\tu16 addr_offset;\n\t__be16 port;\n\tu8 opt_stats: 1;\n\tu8 unused: 7;\n};\n\nstruct used_address {\n\tstruct __kernel_sockaddr_storage name;\n\tunsigned int name_len;\n};\n\nstruct linger {\n\tint l_onoff;\n\tint l_linger;\n};\n\nstruct cmsghdr {\n\t__kernel_size_t cmsg_len;\n\tint cmsg_level;\n\tint cmsg_type;\n};\n\nstruct ucred {\n\t__u32 pid;\n\t__u32 uid;\n\t__u32 gid;\n};\n\nstruct mmpin {\n\tstruct user_struct *user;\n\tunsigned int num_pg;\n};\n\nstruct ubuf_info {\n\tvoid (*callback)(struct ubuf_info *, bool);\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int desc;\n\t\t\tvoid *ctx;\n\t\t};\n\t\tstruct {\n\t\t\tu32 id;\n\t\t\tu16 len;\n\t\t\tu16 zerocopy: 1;\n\t\t\tu32 bytelen;\n\t\t};\n\t};\n\trefcount_t refcnt;\n\tstruct mmpin mmp;\n};\n\nstruct prot_inuse {\n\tint val[64];\n};\n\nstruct rt6key {\n\tstruct in6_addr addr;\n\tint plen;\n};\n\nstruct rtable;\n\nstruct fnhe_hash_bucket;\n\nstruct fib_nh_common {\n\tstruct net_device *nhc_dev;\n\tint nhc_oif;\n\tunsigned char nhc_scope;\n\tu8 nhc_family;\n\tu8 nhc_gw_family;\n\tunsigned char nhc_flags;\n\tstruct lwtunnel_state *nhc_lwtstate;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} nhc_gw;\n\tint nhc_weight;\n\tatomic_t nhc_upper_bound;\n\tstruct rtable **nhc_pcpu_rth_output;\n\tstruct rtable *nhc_rth_input;\n\tstruct fnhe_hash_bucket *nhc_exceptions;\n};\n\nstruct rt6_exception_bucket;\n\nstruct fib6_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct rt6_info **rt6i_pcpu;\n\tstruct rt6_exception_bucket *rt6i_exception_bucket;\n};\n\nstruct fib6_node;\n\nstruct nexthop;\n\nstruct fib6_info {\n\tstruct fib6_table *fib6_table;\n\tstruct fib6_info *fib6_next;\n\tstruct fib6_node *fib6_node;\n\tunion {\n\t\tstruct list_head fib6_siblings;\n\t\tstruct list_head nh_list;\n\t};\n\tunsigned int fib6_nsiblings;\n\trefcount_t fib6_ref;\n\tlong unsigned int expires;\n\tstruct dst_metrics *fib6_metrics;\n\tstruct rt6key fib6_dst;\n\tu32 fib6_flags;\n\tstruct rt6key fib6_src;\n\tstruct rt6key fib6_prefsrc;\n\tu32 fib6_metric;\n\tu8 fib6_protocol;\n\tu8 fib6_type;\n\tu8 should_flush: 1;\n\tu8 dst_nocount: 1;\n\tu8 dst_nopolicy: 1;\n\tu8 fib6_destroying: 1;\n\tu8 offload: 1;\n\tu8 trap: 1;\n\tu8 unused: 2;\n\tstruct callback_head rcu;\n\tstruct nexthop *nh;\n\tstruct fib6_nh fib6_nh[0];\n};\n\nstruct uncached_list;\n\nstruct rt6_info {\n\tstruct dst_entry dst;\n\tstruct fib6_info *from;\n\tint sernum;\n\tstruct rt6key rt6i_dst;\n\tstruct rt6key rt6i_src;\n\tstruct in6_addr rt6i_gateway;\n\tstruct inet6_dev *rt6i_idev;\n\tu32 rt6i_flags;\n\tstruct list_head rt6i_uncached;\n\tstruct uncached_list *rt6i_uncached_list;\n\tshort unsigned int rt6i_nfheader_len;\n};\n\nstruct rt6_statistics {\n\t__u32 fib_nodes;\n\t__u32 fib_route_nodes;\n\t__u32 fib_rt_entries;\n\t__u32 fib_rt_cache;\n\t__u32 fib_discarded_routes;\n\tatomic_t fib_rt_alloc;\n\tatomic_t fib_rt_uncache;\n};\n\nstruct fib6_node {\n\tstruct fib6_node *parent;\n\tstruct fib6_node *left;\n\tstruct fib6_node *right;\n\tstruct fib6_info *leaf;\n\t__u16 fn_bit;\n\t__u16 fn_flags;\n\tint fn_sernum;\n\tstruct fib6_info *rr_ptr;\n\tstruct callback_head rcu;\n};\n\nstruct fib6_table {\n\tstruct hlist_node tb6_hlist;\n\tu32 tb6_id;\n\tspinlock_t tb6_lock;\n\tstruct fib6_node tb6_root;\n\tstruct inet_peer_base tb6_peers;\n\tunsigned int flags;\n\tunsigned int fib_seq;\n};\n\ntypedef union {\n\t__be32 a4;\n\t__be32 a6[4];\n\tstruct in6_addr in6;\n} xfrm_address_t;\n\nstruct xfrm_id {\n\txfrm_address_t daddr;\n\t__be32 spi;\n\t__u8 proto;\n};\n\nstruct xfrm_sec_ctx {\n\t__u8 ctx_doi;\n\t__u8 ctx_alg;\n\t__u16 ctx_len;\n\t__u32 ctx_sid;\n\tchar ctx_str[0];\n};\n\nstruct xfrm_selector {\n\txfrm_address_t daddr;\n\txfrm_address_t saddr;\n\t__be16 dport;\n\t__be16 dport_mask;\n\t__be16 sport;\n\t__be16 sport_mask;\n\t__u16 family;\n\t__u8 prefixlen_d;\n\t__u8 prefixlen_s;\n\t__u8 proto;\n\tint ifindex;\n\t__kernel_uid32_t user;\n};\n\nstruct xfrm_lifetime_cfg {\n\t__u64 soft_byte_limit;\n\t__u64 hard_byte_limit;\n\t__u64 soft_packet_limit;\n\t__u64 hard_packet_limit;\n\t__u64 soft_add_expires_seconds;\n\t__u64 hard_add_expires_seconds;\n\t__u64 soft_use_expires_seconds;\n\t__u64 hard_use_expires_seconds;\n};\n\nstruct xfrm_lifetime_cur {\n\t__u64 bytes;\n\t__u64 packets;\n\t__u64 add_time;\n\t__u64 use_time;\n};\n\nstruct xfrm_replay_state {\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 bitmap;\n};\n\nstruct xfrm_replay_state_esn {\n\tunsigned int bmp_len;\n\t__u32 oseq;\n\t__u32 seq;\n\t__u32 oseq_hi;\n\t__u32 seq_hi;\n\t__u32 replay_window;\n\t__u32 bmp[0];\n};\n\nstruct xfrm_algo {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_auth {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_trunc_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_algo_aead {\n\tchar alg_name[64];\n\tunsigned int alg_key_len;\n\tunsigned int alg_icv_len;\n\tchar alg_key[0];\n};\n\nstruct xfrm_stats {\n\t__u32 replay_window;\n\t__u32 replay;\n\t__u32 integrity_failed;\n};\n\nenum {\n\tXFRM_POLICY_TYPE_MAIN = 0,\n\tXFRM_POLICY_TYPE_SUB = 1,\n\tXFRM_POLICY_TYPE_MAX = 2,\n\tXFRM_POLICY_TYPE_ANY = 255,\n};\n\nstruct xfrm_encap_tmpl {\n\t__u16 encap_type;\n\t__be16 encap_sport;\n\t__be16 encap_dport;\n\txfrm_address_t encap_oa;\n};\n\nstruct xfrm_mark {\n\t__u32 v;\n\t__u32 m;\n};\n\nstruct xfrm_address_filter {\n\txfrm_address_t saddr;\n\txfrm_address_t daddr;\n\t__u16 family;\n\t__u8 splen;\n\t__u8 dplen;\n};\n\nstruct offload_callbacks {\n\tstruct sk_buff * (*gso_segment)(struct sk_buff *, netdev_features_t);\n\tstruct sk_buff * (*gro_receive)(struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sk_buff *, int);\n};\n\nstruct xfrm_state_walk {\n\tstruct list_head all;\n\tu8 state;\n\tu8 dying;\n\tu8 proto;\n\tu32 seq;\n\tstruct xfrm_address_filter *filter;\n};\n\nstruct xfrm_state_offload {\n\tstruct net_device *dev;\n\tlong unsigned int offload_handle;\n\tunsigned int num_exthdrs;\n\tu8 flags;\n};\n\nstruct xfrm_mode {\n\tu8 encap;\n\tu8 family;\n\tu8 flags;\n};\n\nstruct xfrm_replay;\n\nstruct xfrm_type;\n\nstruct xfrm_type_offload;\n\nstruct xfrm_state {\n\tpossible_net_t xs_net;\n\tunion {\n\t\tstruct hlist_node gclist;\n\t\tstruct hlist_node bydst;\n\t};\n\tstruct hlist_node bysrc;\n\tstruct hlist_node byspi;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tstruct xfrm_id id;\n\tstruct xfrm_selector sel;\n\tstruct xfrm_mark mark;\n\tu32 if_id;\n\tu32 tfcpad;\n\tu32 genid;\n\tstruct xfrm_state_walk km;\n\tstruct {\n\t\tu32 reqid;\n\t\tu8 mode;\n\t\tu8 replay_window;\n\t\tu8 aalgo;\n\t\tu8 ealgo;\n\t\tu8 calgo;\n\t\tu8 flags;\n\t\tu16 family;\n\t\txfrm_address_t saddr;\n\t\tint header_len;\n\t\tint trailer_len;\n\t\tu32 extra_flags;\n\t\tstruct xfrm_mark smark;\n\t} props;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_algo_auth *aalg;\n\tstruct xfrm_algo *ealg;\n\tstruct xfrm_algo *calg;\n\tstruct xfrm_algo_aead *aead;\n\tconst char *geniv;\n\tstruct xfrm_encap_tmpl *encap;\n\tstruct sock *encap_sk;\n\txfrm_address_t *coaddr;\n\tstruct xfrm_state *tunnel;\n\tatomic_t tunnel_users;\n\tstruct xfrm_replay_state replay;\n\tstruct xfrm_replay_state_esn *replay_esn;\n\tstruct xfrm_replay_state preplay;\n\tstruct xfrm_replay_state_esn *preplay_esn;\n\tconst struct xfrm_replay *repl;\n\tu32 xflags;\n\tu32 replay_maxage;\n\tu32 replay_maxdiff;\n\tstruct timer_list rtimer;\n\tstruct xfrm_stats stats;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct hrtimer mtimer;\n\tstruct xfrm_state_offload xso;\n\tlong int saved_tmo;\n\ttime64_t lastused;\n\tstruct page_frag xfrag;\n\tconst struct xfrm_type *type;\n\tstruct xfrm_mode inner_mode;\n\tstruct xfrm_mode inner_mode_iaf;\n\tstruct xfrm_mode outer_mode;\n\tconst struct xfrm_type_offload *type_offload;\n\tstruct xfrm_sec_ctx *security;\n\tvoid *data;\n};\n\nenum txtime_flags {\n\tSOF_TXTIME_DEADLINE_MODE = 1,\n\tSOF_TXTIME_REPORT_ERRORS = 2,\n\tSOF_TXTIME_FLAGS_LAST = 2,\n\tSOF_TXTIME_FLAGS_MASK = 3,\n};\n\nstruct sock_txtime {\n\t__kernel_clockid_t clockid;\n\t__u32 flags;\n};\n\nstruct xfrm_policy_walk_entry {\n\tstruct list_head all;\n\tu8 dead;\n};\n\nstruct xfrm_policy_queue {\n\tstruct sk_buff_head hold_queue;\n\tstruct timer_list hold_timer;\n\tlong unsigned int timeout;\n};\n\nstruct xfrm_tmpl {\n\tstruct xfrm_id id;\n\txfrm_address_t saddr;\n\tshort unsigned int encap_family;\n\tu32 reqid;\n\tu8 mode;\n\tu8 share;\n\tu8 optional;\n\tu8 allalgs;\n\tu32 aalgos;\n\tu32 ealgos;\n\tu32 calgos;\n};\n\nstruct xfrm_policy {\n\tpossible_net_t xp_net;\n\tstruct hlist_node bydst;\n\tstruct hlist_node byidx;\n\trwlock_t lock;\n\trefcount_t refcnt;\n\tu32 pos;\n\tstruct timer_list timer;\n\tatomic_t genid;\n\tu32 priority;\n\tu32 index;\n\tu32 if_id;\n\tstruct xfrm_mark mark;\n\tstruct xfrm_selector selector;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct xfrm_policy_walk_entry walk;\n\tstruct xfrm_policy_queue polq;\n\tbool bydst_reinsert;\n\tu8 type;\n\tu8 action;\n\tu8 flags;\n\tu8 xfrm_nr;\n\tu16 family;\n\tstruct xfrm_sec_ctx *security;\n\tstruct xfrm_tmpl xfrm_vec[6];\n\tstruct hlist_node bydst_inexact_list;\n\tstruct callback_head rcu;\n};\n\nenum sk_pacing {\n\tSK_PACING_NONE = 0,\n\tSK_PACING_NEEDED = 1,\n\tSK_PACING_FQ = 2,\n};\n\nstruct sockcm_cookie {\n\tu64 transmit_time;\n\tu32 mark;\n\tu16 tsflags;\n};\n\nstruct fastopen_queue {\n\tstruct request_sock *rskq_rst_head;\n\tstruct request_sock *rskq_rst_tail;\n\tspinlock_t lock;\n\tint qlen;\n\tint max_qlen;\n\tstruct tcp_fastopen_context *ctx;\n};\n\nstruct request_sock_queue {\n\tspinlock_t rskq_lock;\n\tu8 rskq_defer_accept;\n\tu32 synflood_warned;\n\tatomic_t qlen;\n\tatomic_t young;\n\tstruct request_sock *rskq_accept_head;\n\tstruct request_sock *rskq_accept_tail;\n\tstruct fastopen_queue fastopenq;\n};\n\nstruct inet_connection_sock_af_ops {\n\tint (*queue_xmit)(struct sock *, struct sk_buff *, struct flowi *);\n\tvoid (*send_check)(struct sock *, struct sk_buff *);\n\tint (*rebuild_header)(struct sock *);\n\tvoid (*sk_rx_dst_set)(struct sock *, const struct sk_buff *);\n\tint (*conn_request)(struct sock *, struct sk_buff *);\n\tstruct sock * (*syn_recv_sock)(const struct sock *, struct sk_buff *, struct request_sock *, struct dst_entry *, struct request_sock *, bool *);\n\tu16 net_header_len;\n\tu16 net_frag_header_len;\n\tu16 sockaddr_len;\n\tint (*setsockopt)(struct sock *, int, int, char *, unsigned int);\n\tint (*getsockopt)(struct sock *, int, int, char *, int *);\n\tint (*compat_setsockopt)(struct sock *, int, int, char *, unsigned int);\n\tint (*compat_getsockopt)(struct sock *, int, int, char *, int *);\n\tvoid (*addr2sockaddr)(struct sock *, struct sockaddr *);\n\tvoid (*mtu_reduced)(struct sock *);\n};\n\nstruct inet_bind_bucket;\n\nstruct tcp_ulp_ops;\n\nstruct inet_connection_sock {\n\tstruct inet_sock icsk_inet;\n\tstruct request_sock_queue icsk_accept_queue;\n\tstruct inet_bind_bucket *icsk_bind_hash;\n\tlong unsigned int icsk_timeout;\n\tstruct timer_list icsk_retransmit_timer;\n\tstruct timer_list icsk_delack_timer;\n\t__u32 icsk_rto;\n\t__u32 icsk_pmtu_cookie;\n\tconst struct tcp_congestion_ops *icsk_ca_ops;\n\tconst struct inet_connection_sock_af_ops *icsk_af_ops;\n\tconst struct tcp_ulp_ops *icsk_ulp_ops;\n\tvoid *icsk_ulp_data;\n\tvoid (*icsk_clean_acked)(struct sock *, u32);\n\tstruct hlist_node icsk_listen_portaddr_node;\n\tunsigned int (*icsk_sync_mss)(struct sock *, u32);\n\t__u8 icsk_ca_state: 6;\n\t__u8 icsk_ca_setsockopt: 1;\n\t__u8 icsk_ca_dst_locked: 1;\n\t__u8 icsk_retransmits;\n\t__u8 icsk_pending;\n\t__u8 icsk_backoff;\n\t__u8 icsk_syn_retries;\n\t__u8 icsk_probes_out;\n\t__u16 icsk_ext_hdr_len;\n\tstruct {\n\t\t__u8 pending;\n\t\t__u8 quick;\n\t\t__u8 pingpong;\n\t\t__u8 blocked;\n\t\t__u32 ato;\n\t\tlong unsigned int timeout;\n\t\t__u32 lrcvtime;\n\t\t__u16 last_seg_size;\n\t\t__u16 rcv_mss;\n\t} icsk_ack;\n\tstruct {\n\t\tint enabled;\n\t\tint search_high;\n\t\tint search_low;\n\t\tint probe_size;\n\t\tu32 probe_timestamp;\n\t} icsk_mtup;\n\tu32 icsk_user_timeout;\n\tu64 icsk_ca_priv[13];\n};\n\nstruct inet_bind_bucket {\n\tpossible_net_t ib_net;\n\tint l3mdev;\n\tshort unsigned int port;\n\tsigned char fastreuse;\n\tsigned char fastreuseport;\n\tkuid_t fastuid;\n\tstruct in6_addr fast_v6_rcv_saddr;\n\t__be32 fast_rcv_saddr;\n\tshort unsigned int fast_sk_family;\n\tbool fast_ipv6_only;\n\tstruct hlist_node node;\n\tstruct hlist_head owners;\n};\n\nstruct tcp_ulp_ops {\n\tstruct list_head list;\n\tint (*init)(struct sock *);\n\tvoid (*update)(struct sock *, struct proto *, void (*)(struct sock *));\n\tvoid (*release)(struct sock *);\n\tint (*get_info)(const struct sock *, struct sk_buff *);\n\tsize_t (*get_info_size)(const struct sock *);\n\tvoid (*clone)(const struct request_sock *, struct sock *, const gfp_t);\n\tchar name[16];\n\tstruct module *owner;\n};\n\nstruct tcp_sack_block {\n\tu32 start_seq;\n\tu32 end_seq;\n};\n\nstruct tcp_options_received {\n\tint ts_recent_stamp;\n\tu32 ts_recent;\n\tu32 rcv_tsval;\n\tu32 rcv_tsecr;\n\tu16 saw_tstamp: 1;\n\tu16 tstamp_ok: 1;\n\tu16 dsack: 1;\n\tu16 wscale_ok: 1;\n\tu16 sack_ok: 3;\n\tu16 smc_ok: 1;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu8 num_sacks;\n\tu16 user_mss;\n\tu16 mss_clamp;\n};\n\nstruct tcp_rack {\n\tu64 mstamp;\n\tu32 rtt_us;\n\tu32 end_seq;\n\tu32 last_delivered;\n\tu8 reo_wnd_steps;\n\tu8 reo_wnd_persist: 5;\n\tu8 dsack_seen: 1;\n\tu8 advanced: 1;\n};\n\nstruct tcp_sock_af_ops;\n\nstruct tcp_md5sig_info;\n\nstruct tcp_fastopen_request;\n\nstruct tcp_sock {\n\tstruct inet_connection_sock inet_conn;\n\tu16 tcp_header_len;\n\tu16 gso_segs;\n\t__be32 pred_flags;\n\tu64 bytes_received;\n\tu32 segs_in;\n\tu32 data_segs_in;\n\tu32 rcv_nxt;\n\tu32 copied_seq;\n\tu32 rcv_wup;\n\tu32 snd_nxt;\n\tu32 segs_out;\n\tu32 data_segs_out;\n\tu64 bytes_sent;\n\tu64 bytes_acked;\n\tu32 dsack_dups;\n\tu32 snd_una;\n\tu32 snd_sml;\n\tu32 rcv_tstamp;\n\tu32 lsndtime;\n\tu32 last_oow_ack_time;\n\tu32 compressed_ack_rcv_nxt;\n\tu32 tsoffset;\n\tstruct list_head tsq_node;\n\tstruct list_head tsorted_sent_queue;\n\tu32 snd_wl1;\n\tu32 snd_wnd;\n\tu32 max_window;\n\tu32 mss_cache;\n\tu32 window_clamp;\n\tu32 rcv_ssthresh;\n\tstruct tcp_rack rack;\n\tu16 advmss;\n\tu8 compressed_ack;\n\tu8 dup_ack_counter: 2;\n\tu8 tlp_retrans: 1;\n\tu8 unused: 5;\n\tu32 chrono_start;\n\tu32 chrono_stat[3];\n\tu8 chrono_type: 2;\n\tu8 rate_app_limited: 1;\n\tu8 fastopen_connect: 1;\n\tu8 fastopen_no_cookie: 1;\n\tu8 is_sack_reneg: 1;\n\tu8 fastopen_client_fail: 2;\n\tu8 nonagle: 4;\n\tu8 thin_lto: 1;\n\tu8 recvmsg_inq: 1;\n\tu8 repair: 1;\n\tu8 frto: 1;\n\tu8 repair_queue;\n\tu8 syn_data: 1;\n\tu8 syn_fastopen: 1;\n\tu8 syn_fastopen_exp: 1;\n\tu8 syn_fastopen_ch: 1;\n\tu8 syn_data_acked: 1;\n\tu8 save_syn: 1;\n\tu8 is_cwnd_limited: 1;\n\tu8 syn_smc: 1;\n\tu32 tlp_high_seq;\n\tu32 tcp_tx_delay;\n\tu64 tcp_wstamp_ns;\n\tu64 tcp_clock_cache;\n\tu64 tcp_mstamp;\n\tu32 srtt_us;\n\tu32 mdev_us;\n\tu32 mdev_max_us;\n\tu32 rttvar_us;\n\tu32 rtt_seq;\n\tstruct minmax rtt_min;\n\tu32 packets_out;\n\tu32 retrans_out;\n\tu32 max_packets_out;\n\tu32 max_packets_seq;\n\tu16 urg_data;\n\tu8 ecn_flags;\n\tu8 keepalive_probes;\n\tu32 reordering;\n\tu32 reord_seen;\n\tu32 snd_up;\n\tstruct tcp_options_received rx_opt;\n\tu32 snd_ssthresh;\n\tu32 snd_cwnd;\n\tu32 snd_cwnd_cnt;\n\tu32 snd_cwnd_clamp;\n\tu32 snd_cwnd_used;\n\tu32 snd_cwnd_stamp;\n\tu32 prior_cwnd;\n\tu32 prr_delivered;\n\tu32 prr_out;\n\tu32 delivered;\n\tu32 delivered_ce;\n\tu32 lost;\n\tu32 app_limited;\n\tu64 first_tx_mstamp;\n\tu64 delivered_mstamp;\n\tu32 rate_delivered;\n\tu32 rate_interval_us;\n\tu32 rcv_wnd;\n\tu32 write_seq;\n\tu32 notsent_lowat;\n\tu32 pushed_seq;\n\tu32 lost_out;\n\tu32 sacked_out;\n\tstruct hrtimer pacing_timer;\n\tstruct hrtimer compressed_ack_timer;\n\tstruct sk_buff *lost_skb_hint;\n\tstruct sk_buff *retransmit_skb_hint;\n\tstruct rb_root out_of_order_queue;\n\tstruct sk_buff *ooo_last_skb;\n\tstruct tcp_sack_block duplicate_sack[1];\n\tstruct tcp_sack_block selective_acks[4];\n\tstruct tcp_sack_block recv_sack_cache[4];\n\tstruct sk_buff *highest_sack;\n\tint lost_cnt_hint;\n\tu32 prior_ssthresh;\n\tu32 high_seq;\n\tu32 retrans_stamp;\n\tu32 undo_marker;\n\tint undo_retrans;\n\tu64 bytes_retrans;\n\tu32 total_retrans;\n\tu32 urg_seq;\n\tunsigned int keepalive_time;\n\tunsigned int keepalive_intvl;\n\tint linger2;\n\tu8 bpf_sock_ops_cb_flags;\n\tu16 timeout_rehash;\n\tu32 rcv_ooopack;\n\tu32 rcv_rtt_last_tsecr;\n\tstruct {\n\t\tu32 rtt_us;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcv_rtt_est;\n\tstruct {\n\t\tu32 space;\n\t\tu32 seq;\n\t\tu64 time;\n\t} rcvq_space;\n\tstruct {\n\t\tu32 probe_seq_start;\n\t\tu32 probe_seq_end;\n\t} mtu_probe;\n\tu32 mtu_info;\n\tconst struct tcp_sock_af_ops *af_specific;\n\tstruct tcp_md5sig_info *md5sig_info;\n\tstruct tcp_fastopen_request *fastopen_req;\n\tstruct request_sock *fastopen_rsk;\n\tu32 *saved_syn;\n};\n\nstruct tcp_sock_af_ops {\n\tstruct tcp_md5sig_key * (*md5_lookup)(const struct sock *, const struct sock *);\n\tint (*calc_md5_hash)(char *, const struct tcp_md5sig_key *, const struct sock *, const struct sk_buff *);\n\tint (*md5_parse)(struct sock *, int, char *, int);\n};\n\nstruct tcp_md5sig_info {\n\tstruct hlist_head head;\n\tstruct callback_head rcu;\n};\n\nstruct tcp_fastopen_request {\n\tstruct tcp_fastopen_cookie cookie;\n\tstruct msghdr *data;\n\tsize_t size;\n\tint copied;\n\tstruct ubuf_info *uarg;\n};\n\nstruct fib6_config {\n\tu32 fc_table;\n\tu32 fc_metric;\n\tint fc_dst_len;\n\tint fc_src_len;\n\tint fc_ifindex;\n\tu32 fc_flags;\n\tu32 fc_protocol;\n\tu16 fc_type;\n\tu16 fc_delete_all_nh: 1;\n\tu16 fc_ignore_dev_down: 1;\n\tu16 __unused: 14;\n\tu32 fc_nh_id;\n\tstruct in6_addr fc_dst;\n\tstruct in6_addr fc_src;\n\tstruct in6_addr fc_prefsrc;\n\tstruct in6_addr fc_gateway;\n\tlong unsigned int fc_expires;\n\tstruct nlattr *fc_mx;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tstruct nlattr *fc_mp;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n\tbool fc_is_fdb;\n};\n\nstruct fib_nh_exception {\n\tstruct fib_nh_exception *fnhe_next;\n\tint fnhe_genid;\n\t__be32 fnhe_daddr;\n\tu32 fnhe_pmtu;\n\tbool fnhe_mtu_locked;\n\t__be32 fnhe_gw;\n\tlong unsigned int fnhe_expires;\n\tstruct rtable *fnhe_rth_input;\n\tstruct rtable *fnhe_rth_output;\n\tlong unsigned int fnhe_stamp;\n\tstruct callback_head rcu;\n};\n\nstruct rtable {\n\tstruct dst_entry dst;\n\tint rt_genid;\n\tunsigned int rt_flags;\n\t__u16 rt_type;\n\t__u8 rt_is_input;\n\t__u8 rt_uses_gateway;\n\tint rt_iif;\n\tu8 rt_gw_family;\n\tunion {\n\t\t__be32 rt_gw4;\n\t\tstruct in6_addr rt_gw6;\n\t};\n\tu32 rt_mtu_locked: 1;\n\tu32 rt_pmtu: 31;\n\tstruct list_head rt_uncached;\n\tstruct uncached_list *rt_uncached_list;\n};\n\nstruct fnhe_hash_bucket {\n\tstruct fib_nh_exception *chain;\n};\n\nstruct net_protocol {\n\tint (*early_demux)(struct sk_buff *);\n\tint (*early_demux_handler)(struct sk_buff *);\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tunsigned int no_policy: 1;\n\tunsigned int netns_ok: 1;\n\tunsigned int icmp_strict_tag_validation: 1;\n};\n\nstruct inet6_protocol {\n\tvoid (*early_demux)(struct sk_buff *);\n\tvoid (*early_demux_handler)(struct sk_buff *);\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n\tunsigned int flags;\n};\n\nstruct net_offload {\n\tstruct offload_callbacks callbacks;\n\tunsigned int flags;\n};\n\nstruct rt6_exception_bucket {\n\tstruct hlist_head chain;\n\tint depth;\n};\n\nstruct xfrm_replay {\n\tvoid (*advance)(struct xfrm_state *, __be32);\n\tint (*check)(struct xfrm_state *, struct sk_buff *, __be32);\n\tint (*recheck)(struct xfrm_state *, struct sk_buff *, __be32);\n\tvoid (*notify)(struct xfrm_state *, int);\n\tint (*overflow)(struct xfrm_state *, struct sk_buff *);\n};\n\nstruct xfrm_type {\n\tchar *description;\n\tstruct module *owner;\n\tu8 proto;\n\tu8 flags;\n\tint (*init_state)(struct xfrm_state *);\n\tvoid (*destructor)(struct xfrm_state *);\n\tint (*input)(struct xfrm_state *, struct sk_buff *);\n\tint (*output)(struct xfrm_state *, struct sk_buff *);\n\tint (*reject)(struct xfrm_state *, struct sk_buff *, const struct flowi *);\n\tint (*hdr_offset)(struct xfrm_state *, struct sk_buff *, u8 **);\n};\n\nstruct xfrm_type_offload {\n\tchar *description;\n\tstruct module *owner;\n\tu8 proto;\n\tvoid (*encap)(struct xfrm_state *, struct sk_buff *);\n\tint (*input_tail)(struct xfrm_state *, struct sk_buff *);\n\tint (*xmit)(struct xfrm_state *, struct sk_buff *, netdev_features_t);\n};\n\nenum {\n\tSK_MEMINFO_RMEM_ALLOC = 0,\n\tSK_MEMINFO_RCVBUF = 1,\n\tSK_MEMINFO_WMEM_ALLOC = 2,\n\tSK_MEMINFO_SNDBUF = 3,\n\tSK_MEMINFO_FWD_ALLOC = 4,\n\tSK_MEMINFO_WMEM_QUEUED = 5,\n\tSK_MEMINFO_OPTMEM = 6,\n\tSK_MEMINFO_BACKLOG = 7,\n\tSK_MEMINFO_DROPS = 8,\n\tSK_MEMINFO_VARS = 9,\n};\n\nenum sknetlink_groups {\n\tSKNLGRP_NONE = 0,\n\tSKNLGRP_INET_TCP_DESTROY = 1,\n\tSKNLGRP_INET_UDP_DESTROY = 2,\n\tSKNLGRP_INET6_TCP_DESTROY = 3,\n\tSKNLGRP_INET6_UDP_DESTROY = 4,\n\t__SKNLGRP_MAX = 5,\n};\n\nstruct inet_request_sock {\n\tstruct request_sock req;\n\tu16 snd_wscale: 4;\n\tu16 rcv_wscale: 4;\n\tu16 tstamp_ok: 1;\n\tu16 sack_ok: 1;\n\tu16 wscale_ok: 1;\n\tu16 ecn_ok: 1;\n\tu16 acked: 1;\n\tu16 no_srccheck: 1;\n\tu16 smc_ok: 1;\n\tu32 ir_mark;\n\tunion {\n\t\tstruct ip_options_rcu *ireq_opt;\n\t\tstruct {\n\t\t\tstruct ipv6_txoptions *ipv6_opt;\n\t\t\tstruct sk_buff *pktopts;\n\t\t};\n\t};\n};\n\nstruct tcp_request_sock {\n\tstruct inet_request_sock req;\n\tconst struct tcp_request_sock_ops *af_specific;\n\tu64 snt_synack;\n\tbool tfo_listener;\n\tbool is_mptcp;\n\tu32 txhash;\n\tu32 rcv_isn;\n\tu32 snt_isn;\n\tu32 ts_off;\n\tu32 last_oow_ack_time;\n\tu32 rcv_nxt;\n};\n\nstruct ts_state {\n\tunsigned int offset;\n\tchar cb[40];\n};\n\nstruct ts_config;\n\nstruct ts_ops {\n\tconst char *name;\n\tstruct ts_config * (*init)(const void *, unsigned int, gfp_t, int);\n\tunsigned int (*find)(struct ts_config *, struct ts_state *);\n\tvoid (*destroy)(struct ts_config *);\n\tvoid * (*get_pattern)(struct ts_config *);\n\tunsigned int (*get_pattern_len)(struct ts_config *);\n\tstruct module *owner;\n\tstruct list_head list;\n};\n\nstruct ts_config {\n\tstruct ts_ops *ops;\n\tint flags;\n\tunsigned int (*get_next_block)(unsigned int, const u8 **, struct ts_config *, struct ts_state *);\n\tvoid (*finish)(struct ts_config *, struct ts_state *);\n};\n\nenum {\n\tSKB_FCLONE_UNAVAILABLE = 0,\n\tSKB_FCLONE_ORIG = 1,\n\tSKB_FCLONE_CLONE = 2,\n};\n\nstruct sk_buff_fclones {\n\tstruct sk_buff skb1;\n\tstruct sk_buff skb2;\n\trefcount_t fclone_ref;\n};\n\nstruct skb_seq_state {\n\t__u32 lower_offset;\n\t__u32 upper_offset;\n\t__u32 frag_idx;\n\t__u32 stepped_offset;\n\tstruct sk_buff *root_skb;\n\tstruct sk_buff *cur_skb;\n\t__u8 *frag_data;\n};\n\nstruct skb_gso_cb {\n\tunion {\n\t\tint mac_offset;\n\t\tint data_offset;\n\t};\n\tint encap_level;\n\t__wsum csum;\n\t__u16 csum_start;\n};\n\nstruct napi_gro_cb {\n\tvoid *frag0;\n\tunsigned int frag0_len;\n\tint data_offset;\n\tu16 flush;\n\tu16 flush_id;\n\tu16 count;\n\tu16 gro_remcsum_start;\n\tlong unsigned int age;\n\tu16 proto;\n\tu8 same_flow: 1;\n\tu8 encap_mark: 1;\n\tu8 csum_valid: 1;\n\tu8 csum_cnt: 3;\n\tu8 free: 2;\n\tu8 is_ipv6: 1;\n\tu8 is_fou: 1;\n\tu8 is_atomic: 1;\n\tu8 recursion_counter: 4;\n\tu8 is_flist: 1;\n\t__wsum csum;\n\tstruct sk_buff *last;\n};\n\nstruct ip_auth_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__be16 reserved;\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 auth_data[0];\n};\n\nstruct frag_hdr {\n\t__u8 nexthdr;\n\t__u8 reserved;\n\t__be16 frag_off;\n\t__be32 identification;\n};\n\nenum {\n\tSCM_TSTAMP_SND = 0,\n\tSCM_TSTAMP_SCHED = 1,\n\tSCM_TSTAMP_ACK = 2,\n};\n\nstruct xfrm_offload {\n\tstruct {\n\t\t__u32 low;\n\t\t__u32 hi;\n\t} seq;\n\t__u32 flags;\n\t__u32 status;\n\t__u8 proto;\n};\n\nstruct sec_path {\n\tint len;\n\tint olen;\n\tstruct xfrm_state *xvec[6];\n\tstruct xfrm_offload ovec[1];\n};\n\nstruct mpls_shim_hdr {\n\t__be32 label_stack_entry;\n};\n\nstruct napi_alloc_cache {\n\tstruct page_frag_cache page;\n\tunsigned int skb_count;\n\tvoid *skb_cache[64];\n};\n\nstruct scm_cookie {\n\tstruct pid *pid;\n\tstruct scm_fp_list *fp;\n\tstruct scm_creds creds;\n\tu32 secid;\n};\n\nstruct scm_timestamping {\n\tstruct __kernel_old_timespec ts[3];\n};\n\nstruct scm_timestamping64 {\n\tstruct __kernel_timespec ts[3];\n};\n\nenum {\n\tTCA_STATS_UNSPEC = 0,\n\tTCA_STATS_BASIC = 1,\n\tTCA_STATS_RATE_EST = 2,\n\tTCA_STATS_QUEUE = 3,\n\tTCA_STATS_APP = 4,\n\tTCA_STATS_RATE_EST64 = 5,\n\tTCA_STATS_PAD = 6,\n\tTCA_STATS_BASIC_HW = 7,\n\tTCA_STATS_PKT64 = 8,\n\t__TCA_STATS_MAX = 9,\n};\n\nstruct gnet_stats_basic {\n\t__u64 bytes;\n\t__u32 packets;\n};\n\nstruct gnet_stats_rate_est {\n\t__u32 bps;\n\t__u32 pps;\n};\n\nstruct gnet_stats_rate_est64 {\n\t__u64 bps;\n\t__u64 pps;\n};\n\nstruct gnet_estimator {\n\tsigned char interval;\n\tunsigned char ewma_log;\n};\n\nstruct net_rate_estimator {\n\tstruct gnet_stats_basic_packed *bstats;\n\tspinlock_t *stats_lock;\n\tseqcount_t *running;\n\tstruct gnet_stats_basic_cpu *cpu_bstats;\n\tu8 ewma_log;\n\tu8 intvl_log;\n\tseqcount_t seq;\n\tu64 last_packets;\n\tu64 last_bytes;\n\tu64 avpps;\n\tu64 avbps;\n\tlong unsigned int next_jiffies;\n\tstruct timer_list timer;\n\tstruct callback_head rcu;\n};\n\nstruct rtgenmsg {\n\tunsigned char rtgen_family;\n};\n\nenum rtnetlink_groups {\n\tRTNLGRP_NONE = 0,\n\tRTNLGRP_LINK = 1,\n\tRTNLGRP_NOTIFY = 2,\n\tRTNLGRP_NEIGH = 3,\n\tRTNLGRP_TC = 4,\n\tRTNLGRP_IPV4_IFADDR = 5,\n\tRTNLGRP_IPV4_MROUTE = 6,\n\tRTNLGRP_IPV4_ROUTE = 7,\n\tRTNLGRP_IPV4_RULE = 8,\n\tRTNLGRP_IPV6_IFADDR = 9,\n\tRTNLGRP_IPV6_MROUTE = 10,\n\tRTNLGRP_IPV6_ROUTE = 11,\n\tRTNLGRP_IPV6_IFINFO = 12,\n\tRTNLGRP_DECnet_IFADDR = 13,\n\tRTNLGRP_NOP2 = 14,\n\tRTNLGRP_DECnet_ROUTE = 15,\n\tRTNLGRP_DECnet_RULE = 16,\n\tRTNLGRP_NOP4 = 17,\n\tRTNLGRP_IPV6_PREFIX = 18,\n\tRTNLGRP_IPV6_RULE = 19,\n\tRTNLGRP_ND_USEROPT = 20,\n\tRTNLGRP_PHONET_IFADDR = 21,\n\tRTNLGRP_PHONET_ROUTE = 22,\n\tRTNLGRP_DCB = 23,\n\tRTNLGRP_IPV4_NETCONF = 24,\n\tRTNLGRP_IPV6_NETCONF = 25,\n\tRTNLGRP_MDB = 26,\n\tRTNLGRP_MPLS_ROUTE = 27,\n\tRTNLGRP_NSID = 28,\n\tRTNLGRP_MPLS_NETCONF = 29,\n\tRTNLGRP_IPV4_MROUTE_R = 30,\n\tRTNLGRP_IPV6_MROUTE_R = 31,\n\tRTNLGRP_NEXTHOP = 32,\n\tRTNLGRP_BRVLAN = 33,\n\t__RTNLGRP_MAX = 34,\n};\n\nenum {\n\tNETNSA_NONE = 0,\n\tNETNSA_NSID = 1,\n\tNETNSA_PID = 2,\n\tNETNSA_FD = 3,\n\tNETNSA_TARGET_NSID = 4,\n\tNETNSA_CURRENT_NSID = 5,\n\t__NETNSA_MAX = 6,\n};\n\nenum rtnl_link_flags {\n\tRTNL_FLAG_DOIT_UNLOCKED = 1,\n};\n\nstruct net_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint flags;\n\tint cmd;\n\tint nsid;\n\tbool add_ref;\n\tint ref_nsid;\n};\n\nstruct rtnl_net_dump_cb {\n\tstruct net *tgt_net;\n\tstruct net *ref_net;\n\tstruct sk_buff *skb;\n\tstruct net_fill_args fillargs;\n\tint idx;\n\tint s_idx;\n};\n\nstruct flow_dissector_key_control {\n\tu16 thoff;\n\tu16 addr_type;\n\tu32 flags;\n};\n\nenum flow_dissect_ret {\n\tFLOW_DISSECT_RET_OUT_GOOD = 0,\n\tFLOW_DISSECT_RET_OUT_BAD = 1,\n\tFLOW_DISSECT_RET_PROTO_AGAIN = 2,\n\tFLOW_DISSECT_RET_IPPROTO_AGAIN = 3,\n\tFLOW_DISSECT_RET_CONTINUE = 4,\n};\n\nstruct flow_dissector_key_basic {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n};\n\nstruct flow_dissector_key_tags {\n\tu32 flow_label;\n};\n\nstruct flow_dissector_key_vlan {\n\tunion {\n\t\tstruct {\n\t\t\tu16 vlan_id: 12;\n\t\t\tu16 vlan_dei: 1;\n\t\t\tu16 vlan_priority: 3;\n\t\t};\n\t\t__be16 vlan_tci;\n\t};\n\t__be16 vlan_tpid;\n};\n\nstruct flow_dissector_mpls_lse {\n\tu32 mpls_ttl: 8;\n\tu32 mpls_bos: 1;\n\tu32 mpls_tc: 3;\n\tu32 mpls_label: 20;\n};\n\nstruct flow_dissector_key_mpls {\n\tstruct flow_dissector_mpls_lse ls[7];\n\tu8 used_lses;\n};\n\nstruct flow_dissector_key_enc_opts {\n\tu8 data[255];\n\tu8 len;\n\t__be16 dst_opt_type;\n};\n\nstruct flow_dissector_key_keyid {\n\t__be32 keyid;\n};\n\nstruct flow_dissector_key_ipv4_addrs {\n\t__be32 src;\n\t__be32 dst;\n};\n\nstruct flow_dissector_key_ipv6_addrs {\n\tstruct in6_addr src;\n\tstruct in6_addr dst;\n};\n\nstruct flow_dissector_key_tipc {\n\t__be32 key;\n};\n\nstruct flow_dissector_key_addrs {\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs v4addrs;\n\t\tstruct flow_dissector_key_ipv6_addrs v6addrs;\n\t\tstruct flow_dissector_key_tipc tipckey;\n\t};\n};\n\nstruct flow_dissector_key_arp {\n\t__u32 sip;\n\t__u32 tip;\n\t__u8 op;\n\tunsigned char sha[6];\n\tunsigned char tha[6];\n};\n\nstruct flow_dissector_key_ports {\n\tunion {\n\t\t__be32 ports;\n\t\tstruct {\n\t\t\t__be16 src;\n\t\t\t__be16 dst;\n\t\t};\n\t};\n};\n\nstruct flow_dissector_key_icmp {\n\tstruct {\n\t\tu8 type;\n\t\tu8 code;\n\t};\n\tu16 id;\n};\n\nstruct flow_dissector_key_eth_addrs {\n\tunsigned char dst[6];\n\tunsigned char src[6];\n};\n\nstruct flow_dissector_key_tcp {\n\t__be16 flags;\n};\n\nstruct flow_dissector_key_ip {\n\t__u8 tos;\n\t__u8 ttl;\n};\n\nstruct flow_dissector_key_meta {\n\tint ingress_ifindex;\n\tu16 ingress_iftype;\n};\n\nstruct flow_dissector_key_ct {\n\tu16 ct_state;\n\tu16 ct_zone;\n\tu32 ct_mark;\n\tu32 ct_labels[4];\n};\n\nstruct flow_dissector_key {\n\tenum flow_dissector_key_id key_id;\n\tsize_t offset;\n};\n\nstruct flow_keys_basic {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n};\n\nstruct flow_keys {\n\tstruct flow_dissector_key_control control;\n\tstruct flow_dissector_key_basic basic;\n\tstruct flow_dissector_key_tags tags;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_vlan cvlan;\n\tstruct flow_dissector_key_keyid keyid;\n\tstruct flow_dissector_key_ports ports;\n\tstruct flow_dissector_key_icmp icmp;\n\tstruct flow_dissector_key_addrs addrs;\n\tint: 32;\n};\n\nstruct flow_keys_digest {\n\tu8 data[16];\n};\n\nstruct xt_table_info;\n\nstruct xt_table {\n\tstruct list_head list;\n\tunsigned int valid_hooks;\n\tstruct xt_table_info *private;\n\tstruct module *me;\n\tu_int8_t af;\n\tint priority;\n\tint (*table_init)(struct net *);\n\tconst char name[32];\n};\n\nenum bpf_ret_code {\n\tBPF_OK = 0,\n\tBPF_DROP = 2,\n\tBPF_REDIRECT = 7,\n\tBPF_LWT_REROUTE = 128,\n};\n\nenum {\n\tBPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG = 1,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL = 2,\n\tBPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP = 4,\n};\n\nenum devlink_port_type {\n\tDEVLINK_PORT_TYPE_NOTSET = 0,\n\tDEVLINK_PORT_TYPE_AUTO = 1,\n\tDEVLINK_PORT_TYPE_ETH = 2,\n\tDEVLINK_PORT_TYPE_IB = 3,\n};\n\nenum devlink_port_flavour {\n\tDEVLINK_PORT_FLAVOUR_PHYSICAL = 0,\n\tDEVLINK_PORT_FLAVOUR_CPU = 1,\n\tDEVLINK_PORT_FLAVOUR_DSA = 2,\n\tDEVLINK_PORT_FLAVOUR_PCI_PF = 3,\n\tDEVLINK_PORT_FLAVOUR_PCI_VF = 4,\n\tDEVLINK_PORT_FLAVOUR_VIRTUAL = 5,\n};\n\nstruct devlink_port_phys_attrs {\n\tu32 port_number;\n\tu32 split_subport_number;\n};\n\nstruct devlink_port_pci_pf_attrs {\n\tu16 pf;\n};\n\nstruct devlink_port_pci_vf_attrs {\n\tu16 pf;\n\tu16 vf;\n};\n\nstruct devlink_port_attrs {\n\tu8 set: 1;\n\tu8 split: 1;\n\tu8 switch_port: 1;\n\tenum devlink_port_flavour flavour;\n\tstruct netdev_phys_item_id switch_id;\n\tunion {\n\t\tstruct devlink_port_phys_attrs phys;\n\t\tstruct devlink_port_pci_pf_attrs pci_pf;\n\t\tstruct devlink_port_pci_vf_attrs pci_vf;\n\t};\n};\n\nstruct devlink;\n\nstruct devlink_port {\n\tstruct list_head list;\n\tstruct list_head param_list;\n\tstruct devlink *devlink;\n\tunsigned int index;\n\tbool registered;\n\tspinlock_t type_lock;\n\tenum devlink_port_type type;\n\tenum devlink_port_type desired_type;\n\tvoid *type_dev;\n\tstruct devlink_port_attrs attrs;\n\tstruct delayed_work type_warn_dw;\n};\n\nstruct ip_tunnel_parm {\n\tchar name[16];\n\tint link;\n\t__be16 i_flags;\n\t__be16 o_flags;\n\t__be32 i_key;\n\t__be32 o_key;\n\tstruct iphdr iph;\n};\n\nstruct ip_tunnel_key {\n\t__be64 tun_id;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 src;\n\t\t\t__be32 dst;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\tstruct in6_addr src;\n\t\t\tstruct in6_addr dst;\n\t\t} ipv6;\n\t} u;\n\t__be16 tun_flags;\n\tu8 tos;\n\tu8 ttl;\n\t__be32 label;\n\t__be16 tp_src;\n\t__be16 tp_dst;\n};\n\nstruct dst_cache_pcpu;\n\nstruct dst_cache {\n\tstruct dst_cache_pcpu *cache;\n\tlong unsigned int reset_ts;\n};\n\nstruct ip_tunnel_info {\n\tstruct ip_tunnel_key key;\n\tstruct dst_cache dst_cache;\n\tu8 options_len;\n\tu8 mode;\n};\n\nstruct lwtunnel_state {\n\t__u16 type;\n\t__u16 flags;\n\t__u16 headroom;\n\tatomic_t refcnt;\n\tint (*orig_output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*orig_input)(struct sk_buff *);\n\tstruct callback_head rcu;\n\t__u8 data[0];\n};\n\nunion tcp_word_hdr {\n\tstruct tcphdr hdr;\n\t__be32 words[5];\n};\n\nenum devlink_sb_pool_type {\n\tDEVLINK_SB_POOL_TYPE_INGRESS = 0,\n\tDEVLINK_SB_POOL_TYPE_EGRESS = 1,\n};\n\nenum devlink_sb_threshold_type {\n\tDEVLINK_SB_THRESHOLD_TYPE_STATIC = 0,\n\tDEVLINK_SB_THRESHOLD_TYPE_DYNAMIC = 1,\n};\n\nenum devlink_eswitch_encap_mode {\n\tDEVLINK_ESWITCH_ENCAP_MODE_NONE = 0,\n\tDEVLINK_ESWITCH_ENCAP_MODE_BASIC = 1,\n};\n\nenum devlink_trap_action {\n\tDEVLINK_TRAP_ACTION_DROP = 0,\n\tDEVLINK_TRAP_ACTION_TRAP = 1,\n\tDEVLINK_TRAP_ACTION_MIRROR = 2,\n};\n\nenum devlink_trap_type {\n\tDEVLINK_TRAP_TYPE_DROP = 0,\n\tDEVLINK_TRAP_TYPE_EXCEPTION = 1,\n\tDEVLINK_TRAP_TYPE_CONTROL = 2,\n};\n\nenum devlink_dpipe_field_mapping_type {\n\tDEVLINK_DPIPE_FIELD_MAPPING_TYPE_NONE = 0,\n\tDEVLINK_DPIPE_FIELD_MAPPING_TYPE_IFINDEX = 1,\n};\n\nstruct devlink_dpipe_headers;\n\nstruct devlink_ops;\n\nstruct devlink {\n\tstruct list_head list;\n\tstruct list_head port_list;\n\tstruct list_head sb_list;\n\tstruct list_head dpipe_table_list;\n\tstruct list_head resource_list;\n\tstruct list_head param_list;\n\tstruct list_head region_list;\n\tstruct list_head reporter_list;\n\tstruct mutex reporters_lock;\n\tstruct devlink_dpipe_headers *dpipe_headers;\n\tstruct list_head trap_list;\n\tstruct list_head trap_group_list;\n\tstruct list_head trap_policer_list;\n\tconst struct devlink_ops *ops;\n\tstruct xarray snapshot_ids;\n\tstruct device *dev;\n\tpossible_net_t _net;\n\tstruct mutex lock;\n\tu8 reload_failed: 1;\n\tu8 reload_enabled: 1;\n\tu8 registered: 1;\n\tlong: 61;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tchar priv[0];\n};\n\nstruct devlink_dpipe_header;\n\nstruct devlink_dpipe_headers {\n\tstruct devlink_dpipe_header **headers;\n\tunsigned int headers_count;\n};\n\nstruct devlink_info_req;\n\nstruct devlink_sb_pool_info;\n\nstruct devlink_trap;\n\nstruct devlink_trap_group;\n\nstruct devlink_trap_policer;\n\nstruct devlink_ops {\n\tint (*reload_down)(struct devlink *, bool, struct netlink_ext_ack *);\n\tint (*reload_up)(struct devlink *, struct netlink_ext_ack *);\n\tint (*port_type_set)(struct devlink_port *, enum devlink_port_type);\n\tint (*port_split)(struct devlink *, unsigned int, unsigned int, struct netlink_ext_ack *);\n\tint (*port_unsplit)(struct devlink *, unsigned int, struct netlink_ext_ack *);\n\tint (*sb_pool_get)(struct devlink *, unsigned int, u16, struct devlink_sb_pool_info *);\n\tint (*sb_pool_set)(struct devlink *, unsigned int, u16, u32, enum devlink_sb_threshold_type, struct netlink_ext_ack *);\n\tint (*sb_port_pool_get)(struct devlink_port *, unsigned int, u16, u32 *);\n\tint (*sb_port_pool_set)(struct devlink_port *, unsigned int, u16, u32, struct netlink_ext_ack *);\n\tint (*sb_tc_pool_bind_get)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u16 *, u32 *);\n\tint (*sb_tc_pool_bind_set)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u16, u32, struct netlink_ext_ack *);\n\tint (*sb_occ_snapshot)(struct devlink *, unsigned int);\n\tint (*sb_occ_max_clear)(struct devlink *, unsigned int);\n\tint (*sb_occ_port_pool_get)(struct devlink_port *, unsigned int, u16, u32 *, u32 *);\n\tint (*sb_occ_tc_port_bind_get)(struct devlink_port *, unsigned int, u16, enum devlink_sb_pool_type, u32 *, u32 *);\n\tint (*eswitch_mode_get)(struct devlink *, u16 *);\n\tint (*eswitch_mode_set)(struct devlink *, u16, struct netlink_ext_ack *);\n\tint (*eswitch_inline_mode_get)(struct devlink *, u8 *);\n\tint (*eswitch_inline_mode_set)(struct devlink *, u8, struct netlink_ext_ack *);\n\tint (*eswitch_encap_mode_get)(struct devlink *, enum devlink_eswitch_encap_mode *);\n\tint (*eswitch_encap_mode_set)(struct devlink *, enum devlink_eswitch_encap_mode, struct netlink_ext_ack *);\n\tint (*info_get)(struct devlink *, struct devlink_info_req *, struct netlink_ext_ack *);\n\tint (*flash_update)(struct devlink *, const char *, const char *, struct netlink_ext_ack *);\n\tint (*trap_init)(struct devlink *, const struct devlink_trap *, void *);\n\tvoid (*trap_fini)(struct devlink *, const struct devlink_trap *, void *);\n\tint (*trap_action_set)(struct devlink *, const struct devlink_trap *, enum devlink_trap_action);\n\tint (*trap_group_init)(struct devlink *, const struct devlink_trap_group *);\n\tint (*trap_group_set)(struct devlink *, const struct devlink_trap_group *, const struct devlink_trap_policer *);\n\tint (*trap_policer_init)(struct devlink *, const struct devlink_trap_policer *);\n\tvoid (*trap_policer_fini)(struct devlink *, const struct devlink_trap_policer *);\n\tint (*trap_policer_set)(struct devlink *, const struct devlink_trap_policer *, u64, u64, struct netlink_ext_ack *);\n\tint (*trap_policer_counter_get)(struct devlink *, const struct devlink_trap_policer *, u64 *);\n};\n\nstruct devlink_sb_pool_info {\n\tenum devlink_sb_pool_type pool_type;\n\tu32 size;\n\tenum devlink_sb_threshold_type threshold_type;\n\tu32 cell_size;\n};\n\nstruct devlink_dpipe_field {\n\tconst char *name;\n\tunsigned int id;\n\tunsigned int bitwidth;\n\tenum devlink_dpipe_field_mapping_type mapping_type;\n};\n\nstruct devlink_dpipe_header {\n\tconst char *name;\n\tunsigned int id;\n\tstruct devlink_dpipe_field *fields;\n\tunsigned int fields_count;\n\tbool global;\n};\n\nstruct devlink_trap_policer {\n\tu32 id;\n\tu64 init_rate;\n\tu64 init_burst;\n\tu64 max_rate;\n\tu64 min_rate;\n\tu64 max_burst;\n\tu64 min_burst;\n};\n\nstruct devlink_trap_group {\n\tconst char *name;\n\tu16 id;\n\tbool generic;\n\tu32 init_policer_id;\n};\n\nstruct devlink_trap {\n\tenum devlink_trap_type type;\n\tenum devlink_trap_action init_action;\n\tbool generic;\n\tu16 id;\n\tconst char *name;\n\tu16 init_group_id;\n\tu32 metadata_cap;\n};\n\nstruct arphdr {\n\t__be16 ar_hrd;\n\t__be16 ar_pro;\n\tunsigned char ar_hln;\n\tunsigned char ar_pln;\n\t__be16 ar_op;\n};\n\nstruct fib_info;\n\nstruct fib_nh {\n\tstruct fib_nh_common nh_common;\n\tstruct hlist_node nh_hash;\n\tstruct fib_info *nh_parent;\n\t__be32 nh_saddr;\n\tint nh_saddr_genid;\n};\n\nstruct fib_info {\n\tstruct hlist_node fib_hash;\n\tstruct hlist_node fib_lhash;\n\tstruct list_head nh_list;\n\tstruct net *fib_net;\n\tint fib_treeref;\n\trefcount_t fib_clntref;\n\tunsigned int fib_flags;\n\tunsigned char fib_dead;\n\tunsigned char fib_protocol;\n\tunsigned char fib_scope;\n\tunsigned char fib_type;\n\t__be32 fib_prefsrc;\n\tu32 fib_tb_id;\n\tu32 fib_priority;\n\tstruct dst_metrics *fib_metrics;\n\tint fib_nhs;\n\tbool fib_nh_is_v6;\n\tbool nh_updated;\n\tstruct nexthop *nh;\n\tstruct callback_head rcu;\n\tstruct fib_nh fib_nh[0];\n};\n\nstruct nh_info;\n\nstruct nh_group;\n\nstruct nexthop {\n\tstruct rb_node rb_node;\n\tstruct list_head fi_list;\n\tstruct list_head f6i_list;\n\tstruct list_head fdb_list;\n\tstruct list_head grp_list;\n\tstruct net *net;\n\tu32 id;\n\tu8 protocol;\n\tu8 nh_flags;\n\tbool is_group;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n\tunion {\n\t\tstruct nh_info *nh_info;\n\t\tstruct nh_group *nh_grp;\n\t};\n};\n\nstruct nh_info {\n\tstruct hlist_node dev_hash;\n\tstruct nexthop *nh_parent;\n\tu8 family;\n\tbool reject_nh;\n\tbool fdb_nh;\n\tunion {\n\t\tstruct fib_nh_common fib_nhc;\n\t\tstruct fib_nh fib_nh;\n\t\tstruct fib6_nh fib6_nh;\n\t};\n};\n\nstruct nh_grp_entry {\n\tstruct nexthop *nh;\n\tu8 weight;\n\tatomic_t upper_bound;\n\tstruct list_head nh_list;\n\tstruct nexthop *nh_parent;\n};\n\nstruct nh_group {\n\tstruct nh_group *spare;\n\tu16 num_nh;\n\tbool mpath;\n\tbool fdb_nh;\n\tbool has_v4;\n\tstruct nh_grp_entry nh_entries[0];\n};\n\nstruct ip_tunnel_encap {\n\tu16 type;\n\tu16 flags;\n\t__be16 sport;\n\t__be16 dport;\n};\n\nstruct ip_tunnel_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi4 *);\n\tint (*err_handler)(struct sk_buff *, u32);\n};\n\nenum metadata_type {\n\tMETADATA_IP_TUNNEL = 0,\n\tMETADATA_HW_PORT_MUX = 1,\n};\n\nstruct hw_port_info {\n\tstruct net_device *lower_dev;\n\tu32 port_id;\n};\n\nstruct metadata_dst {\n\tstruct dst_entry dst;\n\tenum metadata_type type;\n\tunion {\n\t\tstruct ip_tunnel_info tun_info;\n\t\tstruct hw_port_info port_info;\n\t} u;\n};\n\nstruct gre_base_hdr {\n\t__be16 flags;\n\t__be16 protocol;\n};\n\nstruct gre_full_hdr {\n\tstruct gre_base_hdr fixed_header;\n\t__be16 csum;\n\t__be16 reserved1;\n\t__be32 key;\n\t__be32 seq;\n};\n\nstruct pptp_gre_header {\n\tstruct gre_base_hdr gre_hd;\n\t__be16 payload_len;\n\t__be16 call_id;\n\t__be32 seq;\n\t__be32 ack;\n};\n\nstruct tipc_basic_hdr {\n\t__be32 w[4];\n};\n\nstruct icmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 checksum;\n\tunion {\n\t\tstruct {\n\t\t\t__be16 id;\n\t\t\t__be16 sequence;\n\t\t} echo;\n\t\t__be32 gateway;\n\t\tstruct {\n\t\t\t__be16 __unused;\n\t\t\t__be16 mtu;\n\t\t} frag;\n\t\t__u8 reserved[4];\n\t} un;\n};\n\nenum l2tp_debug_flags {\n\tL2TP_MSG_DEBUG = 1,\n\tL2TP_MSG_CONTROL = 2,\n\tL2TP_MSG_SEQ = 4,\n\tL2TP_MSG_DATA = 8,\n};\n\nstruct pppoe_tag {\n\t__be16 tag_type;\n\t__be16 tag_len;\n\tchar tag_data[0];\n};\n\nstruct pppoe_hdr {\n\t__u8 type: 4;\n\t__u8 ver: 4;\n\t__u8 code;\n\t__be16 sid;\n\t__be16 length;\n\tstruct pppoe_tag tag[0];\n};\n\nstruct mpls_label {\n\t__be32 entry;\n};\n\nenum batadv_packettype {\n\tBATADV_IV_OGM = 0,\n\tBATADV_BCAST = 1,\n\tBATADV_CODED = 2,\n\tBATADV_ELP = 3,\n\tBATADV_OGM2 = 4,\n\tBATADV_UNICAST = 64,\n\tBATADV_UNICAST_FRAG = 65,\n\tBATADV_UNICAST_4ADDR = 66,\n\tBATADV_ICMP = 67,\n\tBATADV_UNICAST_TVLV = 68,\n};\n\nstruct batadv_unicast_packet {\n\t__u8 packet_type;\n\t__u8 version;\n\t__u8 ttl;\n\t__u8 ttvn;\n\t__u8 dest[6];\n};\n\nstruct xt_table_info {\n\tunsigned int size;\n\tunsigned int number;\n\tunsigned int initial_entries;\n\tunsigned int hook_entry[5];\n\tunsigned int underflow[5];\n\tunsigned int stacksize;\n\tvoid ***jumpstack;\n\tunsigned char entries[0];\n};\n\nstruct nf_conntrack_l4proto {\n\tu_int8_t l4proto;\n\tbool allow_clash;\n\tu16 nlattr_size;\n\tbool (*can_early_drop)(const struct nf_conn *);\n\tint (*to_nlattr)(struct sk_buff *, struct nlattr *, struct nf_conn *);\n\tint (*from_nlattr)(struct nlattr **, struct nf_conn *);\n\tint (*tuple_to_nlattr)(struct sk_buff *, const struct nf_conntrack_tuple *);\n\tunsigned int (*nlattr_tuple_size)();\n\tint (*nlattr_to_tuple)(struct nlattr **, struct nf_conntrack_tuple *, u_int32_t);\n\tconst struct nla_policy *nla_policy;\n\tstruct {\n\t\tint (*nlattr_to_obj)(struct nlattr **, struct net *, void *);\n\t\tint (*obj_to_nlattr)(struct sk_buff *, const void *);\n\t\tu16 obj_size;\n\t\tu16 nlattr_max;\n\t\tconst struct nla_policy *nla_policy;\n\t} ctnl_timeout;\n\tvoid (*print_conntrack)(struct seq_file *, struct nf_conn *);\n};\n\nstruct nf_ct_ext {\n\tu8 offset[4];\n\tu8 len;\n\tchar data[0];\n};\n\nenum nf_ct_ext_id {\n\tNF_CT_EXT_HELPER = 0,\n\tNF_CT_EXT_NAT = 1,\n\tNF_CT_EXT_SEQADJ = 2,\n\tNF_CT_EXT_ACCT = 3,\n\tNF_CT_EXT_NUM = 4,\n};\n\nstruct nf_conn_labels {\n\tlong unsigned int bits[2];\n};\n\nstruct _flow_keys_digest_data {\n\t__be16 n_proto;\n\tu8 ip_proto;\n\tu8 padding;\n\t__be32 ports;\n\t__be32 src;\n\t__be32 dst;\n};\n\nenum {\n\tIF_OPER_UNKNOWN = 0,\n\tIF_OPER_NOTPRESENT = 1,\n\tIF_OPER_DOWN = 2,\n\tIF_OPER_LOWERLAYERDOWN = 3,\n\tIF_OPER_TESTING = 4,\n\tIF_OPER_DORMANT = 5,\n\tIF_OPER_UP = 6,\n};\n\nenum nf_dev_hooks {\n\tNF_NETDEV_INGRESS = 0,\n\tNF_NETDEV_NUMHOOKS = 1,\n};\n\nstruct ifbond {\n\t__s32 bond_mode;\n\t__s32 num_slaves;\n\t__s32 miimon;\n};\n\ntypedef struct ifbond ifbond;\n\nstruct ifslave {\n\t__s32 slave_id;\n\tchar slave_name[16];\n\t__s8 link;\n\t__s8 state;\n\t__u32 link_failure_count;\n};\n\ntypedef struct ifslave ifslave;\n\nstruct netdev_boot_setup {\n\tchar name[16];\n\tstruct ifmap map;\n};\n\nenum {\n\tNAPIF_STATE_SCHED = 1,\n\tNAPIF_STATE_MISSED = 2,\n\tNAPIF_STATE_DISABLE = 4,\n\tNAPIF_STATE_NPSVC = 8,\n\tNAPIF_STATE_HASHED = 16,\n\tNAPIF_STATE_NO_BUSY_POLL = 32,\n\tNAPIF_STATE_IN_BUSY_POLL = 64,\n};\n\nenum gro_result {\n\tGRO_MERGED = 0,\n\tGRO_MERGED_FREE = 1,\n\tGRO_HELD = 2,\n\tGRO_NORMAL = 3,\n\tGRO_DROP = 4,\n\tGRO_CONSUMED = 5,\n};\n\ntypedef enum gro_result gro_result_t;\n\nstruct netdev_net_notifier {\n\tstruct list_head list;\n\tstruct notifier_block *nb;\n};\n\nstruct udp_tunnel_info {\n\tshort unsigned int type;\n\tsa_family_t sa_family;\n\t__be16 port;\n};\n\nstruct packet_type {\n\t__be16 type;\n\tbool ignore_outgoing;\n\tstruct net_device *dev;\n\tint (*func)(struct sk_buff *, struct net_device *, struct packet_type *, struct net_device *);\n\tvoid (*list_func)(struct list_head *, struct packet_type *, struct net_device *);\n\tbool (*id_match)(struct packet_type *, struct sock *);\n\tvoid *af_packet_priv;\n\tstruct list_head list;\n};\n\nstruct packet_offload {\n\t__be16 type;\n\tu16 priority;\n\tstruct offload_callbacks callbacks;\n\tstruct list_head list;\n};\n\nstruct netdev_notifier_info_ext {\n\tstruct netdev_notifier_info info;\n\tunion {\n\t\tu32 mtu;\n\t} ext;\n};\n\nstruct netdev_notifier_change_info {\n\tstruct netdev_notifier_info info;\n\tunsigned int flags_changed;\n};\n\nstruct netdev_notifier_changeupper_info {\n\tstruct netdev_notifier_info info;\n\tstruct net_device *upper_dev;\n\tbool master;\n\tbool linking;\n\tvoid *upper_info;\n};\n\nstruct netdev_notifier_changelowerstate_info {\n\tstruct netdev_notifier_info info;\n\tvoid *lower_state_info;\n};\n\nstruct netdev_notifier_pre_changeaddr_info {\n\tstruct netdev_notifier_info info;\n\tconst unsigned char *dev_addr;\n};\n\ntypedef int (*bpf_op_t)(struct net_device *, struct netdev_bpf *);\n\nstruct netdev_bonding_info {\n\tifslave slave;\n\tifbond master;\n};\n\nstruct netdev_notifier_bonding_info {\n\tstruct netdev_notifier_info info;\n\tstruct netdev_bonding_info bonding_info;\n};\n\nenum qdisc_state_t {\n\t__QDISC_STATE_SCHED = 0,\n\t__QDISC_STATE_DEACTIVATED = 1,\n};\n\nstruct tcf_walker {\n\tint stop;\n\tint skip;\n\tint count;\n\tbool nonempty;\n\tlong unsigned int cookie;\n\tint (*fn)(struct tcf_proto *, void *, struct tcf_walker *);\n};\n\nstruct udp_hslot;\n\nstruct udp_table {\n\tstruct udp_hslot *hash;\n\tstruct udp_hslot *hash2;\n\tunsigned int mask;\n\tunsigned int log;\n};\n\nenum {\n\tIPV4_DEVCONF_FORWARDING = 1,\n\tIPV4_DEVCONF_MC_FORWARDING = 2,\n\tIPV4_DEVCONF_PROXY_ARP = 3,\n\tIPV4_DEVCONF_ACCEPT_REDIRECTS = 4,\n\tIPV4_DEVCONF_SECURE_REDIRECTS = 5,\n\tIPV4_DEVCONF_SEND_REDIRECTS = 6,\n\tIPV4_DEVCONF_SHARED_MEDIA = 7,\n\tIPV4_DEVCONF_RP_FILTER = 8,\n\tIPV4_DEVCONF_ACCEPT_SOURCE_ROUTE = 9,\n\tIPV4_DEVCONF_BOOTP_RELAY = 10,\n\tIPV4_DEVCONF_LOG_MARTIANS = 11,\n\tIPV4_DEVCONF_TAG = 12,\n\tIPV4_DEVCONF_ARPFILTER = 13,\n\tIPV4_DEVCONF_MEDIUM_ID = 14,\n\tIPV4_DEVCONF_NOXFRM = 15,\n\tIPV4_DEVCONF_NOPOLICY = 16,\n\tIPV4_DEVCONF_FORCE_IGMP_VERSION = 17,\n\tIPV4_DEVCONF_ARP_ANNOUNCE = 18,\n\tIPV4_DEVCONF_ARP_IGNORE = 19,\n\tIPV4_DEVCONF_PROMOTE_SECONDARIES = 20,\n\tIPV4_DEVCONF_ARP_ACCEPT = 21,\n\tIPV4_DEVCONF_ARP_NOTIFY = 22,\n\tIPV4_DEVCONF_ACCEPT_LOCAL = 23,\n\tIPV4_DEVCONF_SRC_VMARK = 24,\n\tIPV4_DEVCONF_PROXY_ARP_PVLAN = 25,\n\tIPV4_DEVCONF_ROUTE_LOCALNET = 26,\n\tIPV4_DEVCONF_IGMPV2_UNSOLICITED_REPORT_INTERVAL = 27,\n\tIPV4_DEVCONF_IGMPV3_UNSOLICITED_REPORT_INTERVAL = 28,\n\tIPV4_DEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 29,\n\tIPV4_DEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 30,\n\tIPV4_DEVCONF_DROP_GRATUITOUS_ARP = 31,\n\tIPV4_DEVCONF_BC_FORWARDING = 32,\n\t__IPV4_DEVCONF_MAX = 33,\n};\n\nstruct udp_hslot {\n\tstruct hlist_head head;\n\tint count;\n\tspinlock_t lock;\n};\n\nstruct dev_kfree_skb_cb {\n\tenum skb_free_reason reason;\n};\n\nstruct netdev_adjacent {\n\tstruct net_device *dev;\n\tbool master;\n\tbool ignore;\n\tu16 ref_nr;\n\tvoid *private;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\ntypedef struct sk_buff *pto_T_____24;\n\ntypedef u16 pao_T_____9;\n\nstruct xfrm_dst {\n\tunion {\n\t\tstruct dst_entry dst;\n\t\tstruct rtable rt;\n\t\tstruct rt6_info rt6;\n\t} u;\n\tstruct dst_entry *route;\n\tstruct dst_entry *child;\n\tstruct dst_entry *path;\n\tstruct xfrm_policy *pols[2];\n\tint num_pols;\n\tint num_xfrms;\n\tu32 xfrm_genid;\n\tu32 policy_genid;\n\tu32 route_mtu_cached;\n\tu32 child_mtu_cached;\n\tu32 route_cookie;\n\tu32 path_cookie;\n};\n\nenum {\n\tNDA_UNSPEC = 0,\n\tNDA_DST = 1,\n\tNDA_LLADDR = 2,\n\tNDA_CACHEINFO = 3,\n\tNDA_PROBES = 4,\n\tNDA_VLAN = 5,\n\tNDA_PORT = 6,\n\tNDA_VNI = 7,\n\tNDA_IFINDEX = 8,\n\tNDA_MASTER = 9,\n\tNDA_LINK_NETNSID = 10,\n\tNDA_SRC_VNI = 11,\n\tNDA_PROTOCOL = 12,\n\tNDA_NH_ID = 13,\n\t__NDA_MAX = 14,\n};\n\nstruct nda_cacheinfo {\n\t__u32 ndm_confirmed;\n\t__u32 ndm_used;\n\t__u32 ndm_updated;\n\t__u32 ndm_refcnt;\n};\n\nstruct ndt_stats {\n\t__u64 ndts_allocs;\n\t__u64 ndts_destroys;\n\t__u64 ndts_hash_grows;\n\t__u64 ndts_res_failed;\n\t__u64 ndts_lookups;\n\t__u64 ndts_hits;\n\t__u64 ndts_rcv_probes_mcast;\n\t__u64 ndts_rcv_probes_ucast;\n\t__u64 ndts_periodic_gc_runs;\n\t__u64 ndts_forced_gc_runs;\n\t__u64 ndts_table_fulls;\n};\n\nenum {\n\tNDTPA_UNSPEC = 0,\n\tNDTPA_IFINDEX = 1,\n\tNDTPA_REFCNT = 2,\n\tNDTPA_REACHABLE_TIME = 3,\n\tNDTPA_BASE_REACHABLE_TIME = 4,\n\tNDTPA_RETRANS_TIME = 5,\n\tNDTPA_GC_STALETIME = 6,\n\tNDTPA_DELAY_PROBE_TIME = 7,\n\tNDTPA_QUEUE_LEN = 8,\n\tNDTPA_APP_PROBES = 9,\n\tNDTPA_UCAST_PROBES = 10,\n\tNDTPA_MCAST_PROBES = 11,\n\tNDTPA_ANYCAST_DELAY = 12,\n\tNDTPA_PROXY_DELAY = 13,\n\tNDTPA_PROXY_QLEN = 14,\n\tNDTPA_LOCKTIME = 15,\n\tNDTPA_QUEUE_LENBYTES = 16,\n\tNDTPA_MCAST_REPROBES = 17,\n\tNDTPA_PAD = 18,\n\t__NDTPA_MAX = 19,\n};\n\nstruct ndtmsg {\n\t__u8 ndtm_family;\n\t__u8 ndtm_pad1;\n\t__u16 ndtm_pad2;\n};\n\nstruct ndt_config {\n\t__u16 ndtc_key_len;\n\t__u16 ndtc_entry_size;\n\t__u32 ndtc_entries;\n\t__u32 ndtc_last_flush;\n\t__u32 ndtc_last_rand;\n\t__u32 ndtc_hash_rnd;\n\t__u32 ndtc_hash_mask;\n\t__u32 ndtc_hash_chain_gc;\n\t__u32 ndtc_proxy_qlen;\n};\n\nenum {\n\tNDTA_UNSPEC = 0,\n\tNDTA_NAME = 1,\n\tNDTA_THRESH1 = 2,\n\tNDTA_THRESH2 = 3,\n\tNDTA_THRESH3 = 4,\n\tNDTA_CONFIG = 5,\n\tNDTA_PARMS = 6,\n\tNDTA_STATS = 7,\n\tNDTA_GC_INTERVAL = 8,\n\tNDTA_PAD = 9,\n\t__NDTA_MAX = 10,\n};\n\nenum {\n\tRTN_UNSPEC = 0,\n\tRTN_UNICAST = 1,\n\tRTN_LOCAL = 2,\n\tRTN_BROADCAST = 3,\n\tRTN_ANYCAST = 4,\n\tRTN_MULTICAST = 5,\n\tRTN_BLACKHOLE = 6,\n\tRTN_UNREACHABLE = 7,\n\tRTN_PROHIBIT = 8,\n\tRTN_THROW = 9,\n\tRTN_NAT = 10,\n\tRTN_XRESOLVE = 11,\n\t__RTN_MAX = 12,\n};\n\nenum {\n\tNEIGH_ARP_TABLE = 0,\n\tNEIGH_ND_TABLE = 1,\n\tNEIGH_DN_TABLE = 2,\n\tNEIGH_NR_TABLES = 3,\n\tNEIGH_LINK_TABLE = 3,\n};\n\nstruct neigh_seq_state {\n\tstruct seq_net_private p;\n\tstruct neigh_table *tbl;\n\tstruct neigh_hash_table *nht;\n\tvoid * (*neigh_sub_iter)(struct neigh_seq_state *, struct neighbour *, loff_t *);\n\tunsigned int bucket;\n\tunsigned int flags;\n};\n\nstruct neighbour_cb {\n\tlong unsigned int sched_next;\n\tunsigned int flags;\n};\n\nenum netevent_notif_type {\n\tNETEVENT_NEIGH_UPDATE = 1,\n\tNETEVENT_REDIRECT = 2,\n\tNETEVENT_DELAY_PROBE_TIME_UPDATE = 3,\n\tNETEVENT_IPV4_MPATH_HASH_UPDATE = 4,\n\tNETEVENT_IPV6_MPATH_HASH_UPDATE = 5,\n\tNETEVENT_IPV4_FWD_UPDATE_PRIORITY_UPDATE = 6,\n};\n\nstruct neigh_dump_filter {\n\tint master_idx;\n\tint dev_idx;\n};\n\nstruct neigh_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table neigh_vars[21];\n};\n\nstruct netlink_dump_control {\n\tint (*start)(struct netlink_callback *);\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tvoid *data;\n\tstruct module *module;\n\tu16 min_dump_alloc;\n};\n\nstruct rtnl_link_stats {\n\t__u32 rx_packets;\n\t__u32 tx_packets;\n\t__u32 rx_bytes;\n\t__u32 tx_bytes;\n\t__u32 rx_errors;\n\t__u32 tx_errors;\n\t__u32 rx_dropped;\n\t__u32 tx_dropped;\n\t__u32 multicast;\n\t__u32 collisions;\n\t__u32 rx_length_errors;\n\t__u32 rx_over_errors;\n\t__u32 rx_crc_errors;\n\t__u32 rx_frame_errors;\n\t__u32 rx_fifo_errors;\n\t__u32 rx_missed_errors;\n\t__u32 tx_aborted_errors;\n\t__u32 tx_carrier_errors;\n\t__u32 tx_fifo_errors;\n\t__u32 tx_heartbeat_errors;\n\t__u32 tx_window_errors;\n\t__u32 rx_compressed;\n\t__u32 tx_compressed;\n\t__u32 rx_nohandler;\n};\n\nstruct rtnl_link_ifmap {\n\t__u64 mem_start;\n\t__u64 mem_end;\n\t__u64 base_addr;\n\t__u16 irq;\n\t__u8 dma;\n\t__u8 port;\n};\n\nenum {\n\tIFLA_UNSPEC = 0,\n\tIFLA_ADDRESS = 1,\n\tIFLA_BROADCAST = 2,\n\tIFLA_IFNAME = 3,\n\tIFLA_MTU = 4,\n\tIFLA_LINK = 5,\n\tIFLA_QDISC = 6,\n\tIFLA_STATS = 7,\n\tIFLA_COST = 8,\n\tIFLA_PRIORITY = 9,\n\tIFLA_MASTER = 10,\n\tIFLA_WIRELESS = 11,\n\tIFLA_PROTINFO = 12,\n\tIFLA_TXQLEN = 13,\n\tIFLA_MAP = 14,\n\tIFLA_WEIGHT = 15,\n\tIFLA_OPERSTATE = 16,\n\tIFLA_LINKMODE = 17,\n\tIFLA_LINKINFO = 18,\n\tIFLA_NET_NS_PID = 19,\n\tIFLA_IFALIAS = 20,\n\tIFLA_NUM_VF = 21,\n\tIFLA_VFINFO_LIST = 22,\n\tIFLA_STATS64 = 23,\n\tIFLA_VF_PORTS = 24,\n\tIFLA_PORT_SELF = 25,\n\tIFLA_AF_SPEC = 26,\n\tIFLA_GROUP = 27,\n\tIFLA_NET_NS_FD = 28,\n\tIFLA_EXT_MASK = 29,\n\tIFLA_PROMISCUITY = 30,\n\tIFLA_NUM_TX_QUEUES = 31,\n\tIFLA_NUM_RX_QUEUES = 32,\n\tIFLA_CARRIER = 33,\n\tIFLA_PHYS_PORT_ID = 34,\n\tIFLA_CARRIER_CHANGES = 35,\n\tIFLA_PHYS_SWITCH_ID = 36,\n\tIFLA_LINK_NETNSID = 37,\n\tIFLA_PHYS_PORT_NAME = 38,\n\tIFLA_PROTO_DOWN = 39,\n\tIFLA_GSO_MAX_SEGS = 40,\n\tIFLA_GSO_MAX_SIZE = 41,\n\tIFLA_PAD = 42,\n\tIFLA_XDP = 43,\n\tIFLA_EVENT = 44,\n\tIFLA_NEW_NETNSID = 45,\n\tIFLA_IF_NETNSID = 46,\n\tIFLA_TARGET_NETNSID = 46,\n\tIFLA_CARRIER_UP_COUNT = 47,\n\tIFLA_CARRIER_DOWN_COUNT = 48,\n\tIFLA_NEW_IFINDEX = 49,\n\tIFLA_MIN_MTU = 50,\n\tIFLA_MAX_MTU = 51,\n\tIFLA_PROP_LIST = 52,\n\tIFLA_ALT_IFNAME = 53,\n\tIFLA_PERM_ADDRESS = 54,\n\t__IFLA_MAX = 55,\n};\n\nenum {\n\tIFLA_BRPORT_UNSPEC = 0,\n\tIFLA_BRPORT_STATE = 1,\n\tIFLA_BRPORT_PRIORITY = 2,\n\tIFLA_BRPORT_COST = 3,\n\tIFLA_BRPORT_MODE = 4,\n\tIFLA_BRPORT_GUARD = 5,\n\tIFLA_BRPORT_PROTECT = 6,\n\tIFLA_BRPORT_FAST_LEAVE = 7,\n\tIFLA_BRPORT_LEARNING = 8,\n\tIFLA_BRPORT_UNICAST_FLOOD = 9,\n\tIFLA_BRPORT_PROXYARP = 10,\n\tIFLA_BRPORT_LEARNING_SYNC = 11,\n\tIFLA_BRPORT_PROXYARP_WIFI = 12,\n\tIFLA_BRPORT_ROOT_ID = 13,\n\tIFLA_BRPORT_BRIDGE_ID = 14,\n\tIFLA_BRPORT_DESIGNATED_PORT = 15,\n\tIFLA_BRPORT_DESIGNATED_COST = 16,\n\tIFLA_BRPORT_ID = 17,\n\tIFLA_BRPORT_NO = 18,\n\tIFLA_BRPORT_TOPOLOGY_CHANGE_ACK = 19,\n\tIFLA_BRPORT_CONFIG_PENDING = 20,\n\tIFLA_BRPORT_MESSAGE_AGE_TIMER = 21,\n\tIFLA_BRPORT_FORWARD_DELAY_TIMER = 22,\n\tIFLA_BRPORT_HOLD_TIMER = 23,\n\tIFLA_BRPORT_FLUSH = 24,\n\tIFLA_BRPORT_MULTICAST_ROUTER = 25,\n\tIFLA_BRPORT_PAD = 26,\n\tIFLA_BRPORT_MCAST_FLOOD = 27,\n\tIFLA_BRPORT_MCAST_TO_UCAST = 28,\n\tIFLA_BRPORT_VLAN_TUNNEL = 29,\n\tIFLA_BRPORT_BCAST_FLOOD = 30,\n\tIFLA_BRPORT_GROUP_FWD_MASK = 31,\n\tIFLA_BRPORT_NEIGH_SUPPRESS = 32,\n\tIFLA_BRPORT_ISOLATED = 33,\n\tIFLA_BRPORT_BACKUP_PORT = 34,\n\tIFLA_BRPORT_MRP_RING_OPEN = 35,\n\t__IFLA_BRPORT_MAX = 36,\n};\n\nenum {\n\tIFLA_INFO_UNSPEC = 0,\n\tIFLA_INFO_KIND = 1,\n\tIFLA_INFO_DATA = 2,\n\tIFLA_INFO_XSTATS = 3,\n\tIFLA_INFO_SLAVE_KIND = 4,\n\tIFLA_INFO_SLAVE_DATA = 5,\n\t__IFLA_INFO_MAX = 6,\n};\n\nenum {\n\tIFLA_VF_INFO_UNSPEC = 0,\n\tIFLA_VF_INFO = 1,\n\t__IFLA_VF_INFO_MAX = 2,\n};\n\nenum {\n\tIFLA_VF_UNSPEC = 0,\n\tIFLA_VF_MAC = 1,\n\tIFLA_VF_VLAN = 2,\n\tIFLA_VF_TX_RATE = 3,\n\tIFLA_VF_SPOOFCHK = 4,\n\tIFLA_VF_LINK_STATE = 5,\n\tIFLA_VF_RATE = 6,\n\tIFLA_VF_RSS_QUERY_EN = 7,\n\tIFLA_VF_STATS = 8,\n\tIFLA_VF_TRUST = 9,\n\tIFLA_VF_IB_NODE_GUID = 10,\n\tIFLA_VF_IB_PORT_GUID = 11,\n\tIFLA_VF_VLAN_LIST = 12,\n\tIFLA_VF_BROADCAST = 13,\n\t__IFLA_VF_MAX = 14,\n};\n\nstruct ifla_vf_mac {\n\t__u32 vf;\n\t__u8 mac[32];\n};\n\nstruct ifla_vf_broadcast {\n\t__u8 broadcast[32];\n};\n\nstruct ifla_vf_vlan {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n};\n\nenum {\n\tIFLA_VF_VLAN_INFO_UNSPEC = 0,\n\tIFLA_VF_VLAN_INFO = 1,\n\t__IFLA_VF_VLAN_INFO_MAX = 2,\n};\n\nstruct ifla_vf_vlan_info {\n\t__u32 vf;\n\t__u32 vlan;\n\t__u32 qos;\n\t__be16 vlan_proto;\n};\n\nstruct ifla_vf_tx_rate {\n\t__u32 vf;\n\t__u32 rate;\n};\n\nstruct ifla_vf_rate {\n\t__u32 vf;\n\t__u32 min_tx_rate;\n\t__u32 max_tx_rate;\n};\n\nstruct ifla_vf_spoofchk {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nstruct ifla_vf_link_state {\n\t__u32 vf;\n\t__u32 link_state;\n};\n\nstruct ifla_vf_rss_query_en {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nenum {\n\tIFLA_VF_STATS_RX_PACKETS = 0,\n\tIFLA_VF_STATS_TX_PACKETS = 1,\n\tIFLA_VF_STATS_RX_BYTES = 2,\n\tIFLA_VF_STATS_TX_BYTES = 3,\n\tIFLA_VF_STATS_BROADCAST = 4,\n\tIFLA_VF_STATS_MULTICAST = 5,\n\tIFLA_VF_STATS_PAD = 6,\n\tIFLA_VF_STATS_RX_DROPPED = 7,\n\tIFLA_VF_STATS_TX_DROPPED = 8,\n\t__IFLA_VF_STATS_MAX = 9,\n};\n\nstruct ifla_vf_trust {\n\t__u32 vf;\n\t__u32 setting;\n};\n\nenum {\n\tIFLA_VF_PORT_UNSPEC = 0,\n\tIFLA_VF_PORT = 1,\n\t__IFLA_VF_PORT_MAX = 2,\n};\n\nenum {\n\tIFLA_PORT_UNSPEC = 0,\n\tIFLA_PORT_VF = 1,\n\tIFLA_PORT_PROFILE = 2,\n\tIFLA_PORT_VSI_TYPE = 3,\n\tIFLA_PORT_INSTANCE_UUID = 4,\n\tIFLA_PORT_HOST_UUID = 5,\n\tIFLA_PORT_REQUEST = 6,\n\tIFLA_PORT_RESPONSE = 7,\n\t__IFLA_PORT_MAX = 8,\n};\n\nstruct if_stats_msg {\n\t__u8 family;\n\t__u8 pad1;\n\t__u16 pad2;\n\t__u32 ifindex;\n\t__u32 filter_mask;\n};\n\nenum {\n\tIFLA_STATS_UNSPEC = 0,\n\tIFLA_STATS_LINK_64 = 1,\n\tIFLA_STATS_LINK_XSTATS = 2,\n\tIFLA_STATS_LINK_XSTATS_SLAVE = 3,\n\tIFLA_STATS_LINK_OFFLOAD_XSTATS = 4,\n\tIFLA_STATS_AF_SPEC = 5,\n\t__IFLA_STATS_MAX = 6,\n};\n\nenum {\n\tIFLA_OFFLOAD_XSTATS_UNSPEC = 0,\n\tIFLA_OFFLOAD_XSTATS_CPU_HIT = 1,\n\t__IFLA_OFFLOAD_XSTATS_MAX = 2,\n};\n\nenum {\n\tXDP_ATTACHED_NONE = 0,\n\tXDP_ATTACHED_DRV = 1,\n\tXDP_ATTACHED_SKB = 2,\n\tXDP_ATTACHED_HW = 3,\n\tXDP_ATTACHED_MULTI = 4,\n};\n\nenum {\n\tIFLA_XDP_UNSPEC = 0,\n\tIFLA_XDP_FD = 1,\n\tIFLA_XDP_ATTACHED = 2,\n\tIFLA_XDP_FLAGS = 3,\n\tIFLA_XDP_PROG_ID = 4,\n\tIFLA_XDP_DRV_PROG_ID = 5,\n\tIFLA_XDP_SKB_PROG_ID = 6,\n\tIFLA_XDP_HW_PROG_ID = 7,\n\tIFLA_XDP_EXPECTED_FD = 8,\n\t__IFLA_XDP_MAX = 9,\n};\n\nenum {\n\tIFLA_EVENT_NONE = 0,\n\tIFLA_EVENT_REBOOT = 1,\n\tIFLA_EVENT_FEATURES = 2,\n\tIFLA_EVENT_BONDING_FAILOVER = 3,\n\tIFLA_EVENT_NOTIFY_PEERS = 4,\n\tIFLA_EVENT_IGMP_RESEND = 5,\n\tIFLA_EVENT_BONDING_OPTIONS = 6,\n};\n\nenum {\n\tIFLA_BRIDGE_FLAGS = 0,\n\tIFLA_BRIDGE_MODE = 1,\n\tIFLA_BRIDGE_VLAN_INFO = 2,\n\tIFLA_BRIDGE_VLAN_TUNNEL_INFO = 3,\n\tIFLA_BRIDGE_MRP = 4,\n\t__IFLA_BRIDGE_MAX = 5,\n};\n\nenum {\n\tBR_MCAST_DIR_RX = 0,\n\tBR_MCAST_DIR_TX = 1,\n\tBR_MCAST_DIR_SIZE = 2,\n};\n\nenum rtattr_type_t {\n\tRTA_UNSPEC = 0,\n\tRTA_DST = 1,\n\tRTA_SRC = 2,\n\tRTA_IIF = 3,\n\tRTA_OIF = 4,\n\tRTA_GATEWAY = 5,\n\tRTA_PRIORITY = 6,\n\tRTA_PREFSRC = 7,\n\tRTA_METRICS = 8,\n\tRTA_MULTIPATH = 9,\n\tRTA_PROTOINFO = 10,\n\tRTA_FLOW = 11,\n\tRTA_CACHEINFO = 12,\n\tRTA_SESSION = 13,\n\tRTA_MP_ALGO = 14,\n\tRTA_TABLE = 15,\n\tRTA_MARK = 16,\n\tRTA_MFC_STATS = 17,\n\tRTA_VIA = 18,\n\tRTA_NEWDST = 19,\n\tRTA_PREF = 20,\n\tRTA_ENCAP_TYPE = 21,\n\tRTA_ENCAP = 22,\n\tRTA_EXPIRES = 23,\n\tRTA_PAD = 24,\n\tRTA_UID = 25,\n\tRTA_TTL_PROPAGATE = 26,\n\tRTA_IP_PROTO = 27,\n\tRTA_SPORT = 28,\n\tRTA_DPORT = 29,\n\tRTA_NH_ID = 30,\n\t__RTA_MAX = 31,\n};\n\nstruct rta_cacheinfo {\n\t__u32 rta_clntref;\n\t__u32 rta_lastuse;\n\t__s32 rta_expires;\n\t__u32 rta_error;\n\t__u32 rta_used;\n\t__u32 rta_id;\n\t__u32 rta_ts;\n\t__u32 rta_tsage;\n};\n\nstruct ifinfomsg {\n\tunsigned char ifi_family;\n\tunsigned char __ifi_pad;\n\tshort unsigned int ifi_type;\n\tint ifi_index;\n\tunsigned int ifi_flags;\n\tunsigned int ifi_change;\n};\n\ntypedef int (*rtnl_doit_func)(struct sk_buff *, struct nlmsghdr *, struct netlink_ext_ack *);\n\ntypedef int (*rtnl_dumpit_func)(struct sk_buff *, struct netlink_callback *);\n\nstruct rtnl_af_ops {\n\tstruct list_head list;\n\tint family;\n\tint (*fill_link_af)(struct sk_buff *, const struct net_device *, u32);\n\tsize_t (*get_link_af_size)(const struct net_device *, u32);\n\tint (*validate_link_af)(const struct net_device *, const struct nlattr *);\n\tint (*set_link_af)(struct net_device *, const struct nlattr *);\n\tint (*fill_stats_af)(struct sk_buff *, const struct net_device *);\n\tsize_t (*get_stats_af_size)(const struct net_device *);\n};\n\nstruct rtnl_link {\n\trtnl_doit_func doit;\n\trtnl_dumpit_func dumpit;\n\tstruct module *owner;\n\tunsigned int flags;\n\tstruct callback_head rcu;\n};\n\nenum {\n\tIF_LINK_MODE_DEFAULT = 0,\n\tIF_LINK_MODE_DORMANT = 1,\n\tIF_LINK_MODE_TESTING = 2,\n};\n\nenum lw_bits {\n\tLW_URGENT = 0,\n};\n\nstruct seg6_pernet_data {\n\tstruct mutex lock;\n\tstruct in6_addr *tun_src;\n};\n\nenum {\n\tBPF_F_RECOMPUTE_CSUM = 1,\n\tBPF_F_INVALIDATE_HASH = 2,\n};\n\nenum {\n\tBPF_F_HDR_FIELD_MASK = 15,\n};\n\nenum {\n\tBPF_F_PSEUDO_HDR = 16,\n\tBPF_F_MARK_MANGLED_0 = 32,\n\tBPF_F_MARK_ENFORCE = 64,\n};\n\nenum {\n\tBPF_F_INGRESS = 1,\n};\n\nenum {\n\tBPF_F_TUNINFO_IPV6 = 1,\n};\n\nenum {\n\tBPF_F_ZERO_CSUM_TX = 2,\n\tBPF_F_DONT_FRAGMENT = 4,\n\tBPF_F_SEQ_NUMBER = 8,\n};\n\nenum {\n\tBPF_CSUM_LEVEL_QUERY = 0,\n\tBPF_CSUM_LEVEL_INC = 1,\n\tBPF_CSUM_LEVEL_DEC = 2,\n\tBPF_CSUM_LEVEL_RESET = 3,\n};\n\nenum {\n\tBPF_F_ADJ_ROOM_FIXED_GSO = 1,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV4 = 2,\n\tBPF_F_ADJ_ROOM_ENCAP_L3_IPV6 = 4,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_GRE = 8,\n\tBPF_F_ADJ_ROOM_ENCAP_L4_UDP = 16,\n\tBPF_F_ADJ_ROOM_NO_CSUM_RESET = 32,\n};\n\nenum {\n\tBPF_ADJ_ROOM_ENCAP_L2_MASK = 255,\n\tBPF_ADJ_ROOM_ENCAP_L2_SHIFT = 56,\n};\n\nenum bpf_adj_room_mode {\n\tBPF_ADJ_ROOM_NET = 0,\n\tBPF_ADJ_ROOM_MAC = 1,\n};\n\nenum bpf_hdr_start_off {\n\tBPF_HDR_START_MAC = 0,\n\tBPF_HDR_START_NET = 1,\n};\n\nenum bpf_lwt_encap_mode {\n\tBPF_LWT_ENCAP_SEG6 = 0,\n\tBPF_LWT_ENCAP_SEG6_INLINE = 1,\n\tBPF_LWT_ENCAP_IP = 2,\n};\n\nstruct bpf_tunnel_key {\n\t__u32 tunnel_id;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n\t__u8 tunnel_tos;\n\t__u8 tunnel_ttl;\n\t__u16 tunnel_ext;\n\t__u32 tunnel_label;\n};\n\nstruct bpf_xfrm_state {\n\t__u32 reqid;\n\t__u32 spi;\n\t__u16 family;\n\t__u16 ext;\n\tunion {\n\t\t__u32 remote_ipv4;\n\t\t__u32 remote_ipv6[4];\n\t};\n};\n\nstruct bpf_tcp_sock {\n\t__u32 snd_cwnd;\n\t__u32 srtt_us;\n\t__u32 rtt_min;\n\t__u32 snd_ssthresh;\n\t__u32 rcv_nxt;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 mss_cache;\n\t__u32 ecn_flags;\n\t__u32 rate_delivered;\n\t__u32 rate_interval_us;\n\t__u32 packets_out;\n\t__u32 retrans_out;\n\t__u32 total_retrans;\n\t__u32 segs_in;\n\t__u32 data_segs_in;\n\t__u32 segs_out;\n\t__u32 data_segs_out;\n\t__u32 lost_out;\n\t__u32 sacked_out;\n\t__u64 bytes_received;\n\t__u64 bytes_acked;\n\t__u32 dsack_dups;\n\t__u32 delivered;\n\t__u32 delivered_ce;\n\t__u32 icsk_retransmits;\n};\n\nstruct bpf_sock_tuple {\n\tunion {\n\t\tstruct {\n\t\t\t__be32 saddr;\n\t\t\t__be32 daddr;\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv4;\n\t\tstruct {\n\t\t\t__be32 saddr[4];\n\t\t\t__be32 daddr[4];\n\t\t\t__be16 sport;\n\t\t\t__be16 dport;\n\t\t} ipv6;\n\t};\n};\n\nstruct bpf_xdp_sock {\n\t__u32 queue_id;\n};\n\nenum sk_action {\n\tSK_DROP = 0,\n\tSK_PASS = 1,\n};\n\nenum {\n\tBPF_SOCK_OPS_RTO_CB_FLAG = 1,\n\tBPF_SOCK_OPS_RETRANS_CB_FLAG = 2,\n\tBPF_SOCK_OPS_STATE_CB_FLAG = 4,\n\tBPF_SOCK_OPS_RTT_CB_FLAG = 8,\n\tBPF_SOCK_OPS_ALL_CB_FLAGS = 15,\n};\n\nenum {\n\tBPF_SOCK_OPS_VOID = 0,\n\tBPF_SOCK_OPS_TIMEOUT_INIT = 1,\n\tBPF_SOCK_OPS_RWND_INIT = 2,\n\tBPF_SOCK_OPS_TCP_CONNECT_CB = 3,\n\tBPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB = 4,\n\tBPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB = 5,\n\tBPF_SOCK_OPS_NEEDS_ECN = 6,\n\tBPF_SOCK_OPS_BASE_RTT = 7,\n\tBPF_SOCK_OPS_RTO_CB = 8,\n\tBPF_SOCK_OPS_RETRANS_CB = 9,\n\tBPF_SOCK_OPS_STATE_CB = 10,\n\tBPF_SOCK_OPS_TCP_LISTEN_CB = 11,\n\tBPF_SOCK_OPS_RTT_CB = 12,\n};\n\nenum {\n\tTCP_BPF_IW = 1001,\n\tTCP_BPF_SNDCWND_CLAMP = 1002,\n};\n\nenum {\n\tBPF_FIB_LOOKUP_DIRECT = 1,\n\tBPF_FIB_LOOKUP_OUTPUT = 2,\n};\n\nenum {\n\tBPF_FIB_LKUP_RET_SUCCESS = 0,\n\tBPF_FIB_LKUP_RET_BLACKHOLE = 1,\n\tBPF_FIB_LKUP_RET_UNREACHABLE = 2,\n\tBPF_FIB_LKUP_RET_PROHIBIT = 3,\n\tBPF_FIB_LKUP_RET_NOT_FWDED = 4,\n\tBPF_FIB_LKUP_RET_FWD_DISABLED = 5,\n\tBPF_FIB_LKUP_RET_UNSUPP_LWT = 6,\n\tBPF_FIB_LKUP_RET_NO_NEIGH = 7,\n\tBPF_FIB_LKUP_RET_FRAG_NEEDED = 8,\n};\n\nstruct bpf_fib_lookup {\n\t__u8 family;\n\t__u8 l4_protocol;\n\t__be16 sport;\n\t__be16 dport;\n\t__u16 tot_len;\n\t__u32 ifindex;\n\tunion {\n\t\t__u8 tos;\n\t\t__be32 flowinfo;\n\t\t__u32 rt_metric;\n\t};\n\tunion {\n\t\t__be32 ipv4_src;\n\t\t__u32 ipv6_src[4];\n\t};\n\tunion {\n\t\t__be32 ipv4_dst;\n\t\t__u32 ipv6_dst[4];\n\t};\n\t__be16 h_vlan_proto;\n\t__be16 h_vlan_TCI;\n\t__u8 smac[6];\n\t__u8 dmac[6];\n};\n\nstruct xsk_queue;\n\nstruct xsk_buff_pool;\n\nstruct xdp_umem {\n\tstruct xsk_queue *fq;\n\tstruct xsk_queue *cq;\n\tstruct xsk_buff_pool *pool;\n\tu64 size;\n\tu32 headroom;\n\tu32 chunk_size;\n\tstruct user_struct *user;\n\trefcount_t users;\n\tstruct work_struct work;\n\tstruct page **pgs;\n\tu32 npgs;\n\tu16 queue_id;\n\tu8 need_wakeup;\n\tu8 flags;\n\tint id;\n\tstruct net_device *dev;\n\tbool zc;\n\tspinlock_t xsk_tx_list_lock;\n\tstruct list_head xsk_tx_list;\n};\n\nenum rt_scope_t {\n\tRT_SCOPE_UNIVERSE = 0,\n\tRT_SCOPE_SITE = 200,\n\tRT_SCOPE_LINK = 253,\n\tRT_SCOPE_HOST = 254,\n\tRT_SCOPE_NOWHERE = 255,\n};\n\nenum rt_class_t {\n\tRT_TABLE_UNSPEC = 0,\n\tRT_TABLE_COMPAT = 252,\n\tRT_TABLE_DEFAULT = 253,\n\tRT_TABLE_MAIN = 254,\n\tRT_TABLE_LOCAL = 255,\n\tRT_TABLE_MAX = 4294967295,\n};\n\ntypedef int (*bpf_aux_classic_check_t)(struct sock_filter *, unsigned int);\n\nstruct fib_result {\n\t__be32 prefix;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tu32 tclassid;\n\tstruct fib_nh_common *nhc;\n\tstruct fib_info *fi;\n\tstruct fib_table *table;\n\tstruct hlist_head *fa_head;\n};\n\nenum {\n\tINET_ECN_NOT_ECT = 0,\n\tINET_ECN_ECT_1 = 1,\n\tINET_ECN_ECT_0 = 2,\n\tINET_ECN_CE = 3,\n\tINET_ECN_MASK = 3,\n};\n\nstruct tcp_skb_cb {\n\t__u32 seq;\n\t__u32 end_seq;\n\tunion {\n\t\t__u32 tcp_tw_isn;\n\t\tstruct {\n\t\t\tu16 tcp_gso_segs;\n\t\t\tu16 tcp_gso_size;\n\t\t};\n\t};\n\t__u8 tcp_flags;\n\t__u8 sacked;\n\t__u8 ip_dsfield;\n\t__u8 txstamp_ack: 1;\n\t__u8 eor: 1;\n\t__u8 has_rxtstamp: 1;\n\t__u8 unused: 5;\n\t__u32 ack_seq;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 in_flight: 30;\n\t\t\t__u32 is_app_limited: 1;\n\t\t\t__u32 unused: 1;\n\t\t\t__u32 delivered;\n\t\t\tu64 first_tx_mstamp;\n\t\t\tu64 delivered_mstamp;\n\t\t} tx;\n\t\tunion {\n\t\t\tstruct inet_skb_parm h4;\n\t\t\tstruct inet6_skb_parm h6;\n\t\t} header;\n\t\tstruct {\n\t\t\t__u32 flags;\n\t\t\tstruct sock *sk_redir;\n\t\t\tvoid *data_end;\n\t\t} bpf;\n\t};\n};\n\nstruct xdp_sock;\n\nstruct xsk_map {\n\tstruct bpf_map map;\n\tspinlock_t lock;\n\tstruct xdp_sock *xsk_map[0];\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xdp_sock {\n\tstruct sock sk;\n\tstruct xsk_queue *rx;\n\tstruct net_device *dev;\n\tstruct xdp_umem *umem;\n\tstruct list_head flush_node;\n\tu16 queue_id;\n\tbool zc;\n\tenum {\n\t\tXSK_READY = 0,\n\t\tXSK_BOUND = 1,\n\t\tXSK_UNBOUND = 2,\n\t} state;\n\tstruct mutex mutex;\n\tstruct xsk_queue *tx;\n\tstruct list_head list;\n\tspinlock_t tx_completion_lock;\n\tspinlock_t rx_lock;\n\tu64 rx_dropped;\n\tstruct list_head map_list;\n\tspinlock_t map_list_lock;\n};\n\nstruct ipv6_sr_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n\t__u8 first_segment;\n\t__u8 flags;\n\t__u16 tag;\n\tstruct in6_addr segments[0];\n};\n\nenum {\n\tSEG6_LOCAL_ACTION_UNSPEC = 0,\n\tSEG6_LOCAL_ACTION_END = 1,\n\tSEG6_LOCAL_ACTION_END_X = 2,\n\tSEG6_LOCAL_ACTION_END_T = 3,\n\tSEG6_LOCAL_ACTION_END_DX2 = 4,\n\tSEG6_LOCAL_ACTION_END_DX6 = 5,\n\tSEG6_LOCAL_ACTION_END_DX4 = 6,\n\tSEG6_LOCAL_ACTION_END_DT6 = 7,\n\tSEG6_LOCAL_ACTION_END_DT4 = 8,\n\tSEG6_LOCAL_ACTION_END_B6 = 9,\n\tSEG6_LOCAL_ACTION_END_B6_ENCAP = 10,\n\tSEG6_LOCAL_ACTION_END_BM = 11,\n\tSEG6_LOCAL_ACTION_END_S = 12,\n\tSEG6_LOCAL_ACTION_END_AS = 13,\n\tSEG6_LOCAL_ACTION_END_AM = 14,\n\tSEG6_LOCAL_ACTION_END_BPF = 15,\n\t__SEG6_LOCAL_ACTION_MAX = 16,\n};\n\nstruct seg6_bpf_srh_state {\n\tstruct ipv6_sr_hdr *srh;\n\tu16 hdrlen;\n\tbool valid;\n};\n\ntypedef u64 (*btf_bpf_skb_get_pay_offset)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_get_nlattr_nest)(struct sk_buff *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_8_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_16_no_cache)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32)(const struct sk_buff *, const void *, int, int);\n\ntypedef u64 (*btf_bpf_skb_load_helper_32_no_cache)(const struct sk_buff *, int);\n\nstruct bpf_scratchpad {\n\tunion {\n\t\t__be32 diff[128];\n\t\tu8 buff[512];\n\t};\n};\n\ntypedef u64 (*btf_bpf_skb_store_bytes)(struct sk_buff *, u32, const void *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_load_bytes)(const struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_flow_dissector_load_bytes)(const struct bpf_flow_dissector *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_skb_load_bytes_relative)(const struct sk_buff *, u32, void *, u32, u32);\n\ntypedef u64 (*btf_bpf_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_sk_fullsock)(struct sock *);\n\ntypedef u64 (*btf_sk_skb_pull_data)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_l3_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_l4_csum_replace)(struct sk_buff *, u32, u64, u64, u64);\n\ntypedef u64 (*btf_bpf_csum_diff)(__be32 *, u32, __be32 *, u32, __wsum);\n\ntypedef u64 (*btf_bpf_csum_update)(struct sk_buff *, __wsum);\n\ntypedef u64 (*btf_bpf_csum_level)(struct sk_buff *, u64);\n\ntypedef u64 (*btf_bpf_clone_redirect)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_msg_apply_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_cork_bytes)(struct sk_msg *, u32);\n\ntypedef u64 (*btf_bpf_msg_pull_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_push_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_pop_data)(struct sk_msg *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_get_cgroup_classid)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_route_realm)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_hash_recalc)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_set_hash_invalid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_set_hash)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_vlan_push)(struct sk_buff *, __be16, u16);\n\ntypedef u64 (*btf_bpf_skb_vlan_pop)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_change_proto)(struct sk_buff *, __be16, u64);\n\ntypedef u64 (*btf_bpf_skb_change_type)(struct sk_buff *, u32);\n\ntypedef u64 (*btf_bpf_skb_adjust_room)(struct sk_buff *, s32, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_tail)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_sk_skb_change_head)(struct sk_buff *, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_adjust_head)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_tail)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_adjust_meta)(struct xdp_buff *, int);\n\ntypedef u64 (*btf_bpf_xdp_redirect)(u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_redirect_map)(struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_event_output)(struct sk_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_key)(struct sk_buff *, struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_get_tunnel_opt)(struct sk_buff *, u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_key)(struct sk_buff *, const struct bpf_tunnel_key *, u32, u64);\n\ntypedef u64 (*btf_bpf_skb_set_tunnel_opt)(struct sk_buff *, const u8 *, u32);\n\ntypedef u64 (*btf_bpf_skb_under_cgroup)(struct sk_buff *, struct bpf_map *, u32);\n\ntypedef u64 (*btf_bpf_skb_cgroup_id)(const struct sk_buff *);\n\ntypedef u64 (*btf_bpf_skb_ancestor_cgroup_id)(const struct sk_buff *, int);\n\ntypedef u64 (*btf_bpf_sk_cgroup_id)(struct sock *);\n\ntypedef u64 (*btf_bpf_sk_ancestor_cgroup_id)(struct sock *, int);\n\ntypedef u64 (*btf_bpf_xdp_event_output)(struct xdp_buff *, struct bpf_map *, u64, void *, u64);\n\ntypedef u64 (*btf_bpf_get_socket_cookie)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_socket_cookie_sock_ops)(struct bpf_sock_ops_kern *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_netns_cookie_sock_addr)(struct bpf_sock_addr_kern *);\n\ntypedef u64 (*btf_bpf_get_socket_uid)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_sock_addr_setsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_addr_getsockopt)(struct bpf_sock_addr_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_setsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_getsockopt)(struct bpf_sock_ops_kern *, int, int, char *, int);\n\ntypedef u64 (*btf_bpf_sock_ops_cb_flags_set)(struct bpf_sock_ops_kern *, int);\n\ntypedef u64 (*btf_bpf_bind)(struct bpf_sock_addr_kern *, struct sockaddr *, int);\n\ntypedef u64 (*btf_bpf_skb_get_xfrm_state)(struct sk_buff *, u32, struct bpf_xfrm_state *, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_fib_lookup)(struct xdp_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_skb_fib_lookup)(struct sk_buff *, struct bpf_fib_lookup *, int, u32);\n\ntypedef u64 (*btf_bpf_lwt_in_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_lwt_xmit_push_encap)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_lwt_seg6_store_bytes)(struct sk_buff *, u32, const void *, u32);\n\ntypedef u64 (*btf_bpf_lwt_seg6_action)(struct sk_buff *, u32, void *, u32);\n\ntypedef u64 (*btf_bpf_lwt_seg6_adjust_srh)(struct sk_buff *, u32, s32);\n\ntypedef u64 (*btf_bpf_skc_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_tcp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_lookup_udp)(struct sk_buff *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sk_release)(struct sock *);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_udp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_skc_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_xdp_sk_lookup_tcp)(struct xdp_buff *, struct bpf_sock_tuple *, u32, u32, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_skc_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_tcp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_sock_addr_sk_lookup_udp)(struct bpf_sock_addr_kern *, struct bpf_sock_tuple *, u32, u64, u64);\n\ntypedef u64 (*btf_bpf_tcp_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_get_listener_sock)(struct sock *);\n\ntypedef u64 (*btf_bpf_skb_ecn_set_ce)(struct sk_buff *);\n\ntypedef u64 (*btf_bpf_tcp_check_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_tcp_gen_syncookie)(struct sock *, void *, u32, struct tcphdr *, u32);\n\ntypedef u64 (*btf_bpf_sk_assign)(struct sk_buff *, struct sock *, u64);\n\ntypedef u64 (*btf_sk_select_reuseport)(struct sk_reuseport_kern *, struct bpf_map *, void *, u32);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes)(const struct sk_reuseport_kern *, u32, void *, u32);\n\ntypedef u64 (*btf_sk_reuseport_load_bytes_relative)(const struct sk_reuseport_kern *, u32, void *, u32, u32);\n\nstruct bpf_dtab_netdev___2;\n\nenum {\n\tINET_DIAG_REQ_NONE = 0,\n\tINET_DIAG_REQ_BYTECODE = 1,\n\tINET_DIAG_REQ_SK_BPF_STORAGES = 2,\n\t__INET_DIAG_REQ_MAX = 3,\n};\n\nstruct sock_diag_req {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n};\n\nstruct sock_diag_handler {\n\t__u8 family;\n\tint (*dump)(struct sk_buff *, struct nlmsghdr *);\n\tint (*get_info)(struct sk_buff *, struct sock *);\n\tint (*destroy)(struct sk_buff *, struct nlmsghdr *);\n};\n\nstruct broadcast_sk {\n\tstruct sock *sk;\n\tstruct work_struct work;\n};\n\ntypedef int gifconf_func_t(struct net_device *, char *, int, int);\n\nstruct tso_t {\n\tint next_frag_idx;\n\tvoid *data;\n\tsize_t size;\n\tu16 ip_id;\n\tbool ipv6;\n\tu32 tcp_seq;\n};\n\nstruct fib_notifier_info {\n\tint family;\n\tstruct netlink_ext_ack *extack;\n};\n\nenum fib_event_type {\n\tFIB_EVENT_ENTRY_REPLACE = 0,\n\tFIB_EVENT_ENTRY_APPEND = 1,\n\tFIB_EVENT_ENTRY_ADD = 2,\n\tFIB_EVENT_ENTRY_DEL = 3,\n\tFIB_EVENT_RULE_ADD = 4,\n\tFIB_EVENT_RULE_DEL = 5,\n\tFIB_EVENT_NH_ADD = 6,\n\tFIB_EVENT_NH_DEL = 7,\n\tFIB_EVENT_VIF_ADD = 8,\n\tFIB_EVENT_VIF_DEL = 9,\n};\n\nstruct fib_notifier_net {\n\tstruct list_head fib_notifier_ops;\n\tstruct atomic_notifier_head fib_chain;\n};\n\nstruct xdp_attachment_info {\n\tstruct bpf_prog *prog;\n\tu32 flags;\n};\n\nstruct pp_alloc_cache {\n\tu32 count;\n\tvoid *cache[128];\n};\n\nstruct page_pool_params {\n\tunsigned int flags;\n\tunsigned int order;\n\tunsigned int pool_size;\n\tint nid;\n\tstruct device *dev;\n\tenum dma_data_direction dma_dir;\n\tunsigned int max_len;\n\tunsigned int offset;\n};\n\nstruct page_pool {\n\tstruct page_pool_params p;\n\tstruct delayed_work release_dw;\n\tvoid (*disconnect)(void *);\n\tlong unsigned int defer_start;\n\tlong unsigned int defer_warn;\n\tu32 pages_state_hold_cnt;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct pp_alloc_cache alloc;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct ptr_ring ring;\n\tatomic_t pages_state_release_cnt;\n\trefcount_t user_cnt;\n\tu64 destroy_cnt;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xdp_buff_xsk;\n\nstruct xsk_buff_pool {\n\tstruct xsk_queue *fq;\n\tstruct list_head free_list;\n\tdma_addr_t *dma_pages;\n\tstruct xdp_buff_xsk *heads;\n\tu64 chunk_mask;\n\tu64 addrs_cnt;\n\tu32 free_list_cnt;\n\tu32 dma_pages_cnt;\n\tu32 heads_cnt;\n\tu32 free_heads_cnt;\n\tu32 headroom;\n\tu32 chunk_size;\n\tu32 frame_len;\n\tbool dma_need_sync;\n\tbool unaligned;\n\tvoid *addrs;\n\tstruct device *dev;\n\tstruct xdp_buff_xsk *free_heads[0];\n};\n\nstruct xdp_buff_xsk {\n\tstruct xdp_buff xdp;\n\tdma_addr_t dma;\n\tdma_addr_t frame_dma;\n\tstruct xsk_buff_pool *pool;\n\tbool unaligned;\n\tu64 orig_addr;\n\tstruct list_head free_list_node;\n};\n\nstruct flow_match {\n\tstruct flow_dissector *dissector;\n\tvoid *mask;\n\tvoid *key;\n};\n\nstruct flow_match_meta {\n\tstruct flow_dissector_key_meta *key;\n\tstruct flow_dissector_key_meta *mask;\n};\n\nstruct flow_match_basic {\n\tstruct flow_dissector_key_basic *key;\n\tstruct flow_dissector_key_basic *mask;\n};\n\nstruct flow_match_control {\n\tstruct flow_dissector_key_control *key;\n\tstruct flow_dissector_key_control *mask;\n};\n\nstruct flow_match_eth_addrs {\n\tstruct flow_dissector_key_eth_addrs *key;\n\tstruct flow_dissector_key_eth_addrs *mask;\n};\n\nstruct flow_match_vlan {\n\tstruct flow_dissector_key_vlan *key;\n\tstruct flow_dissector_key_vlan *mask;\n};\n\nstruct flow_match_ipv4_addrs {\n\tstruct flow_dissector_key_ipv4_addrs *key;\n\tstruct flow_dissector_key_ipv4_addrs *mask;\n};\n\nstruct flow_match_ipv6_addrs {\n\tstruct flow_dissector_key_ipv6_addrs *key;\n\tstruct flow_dissector_key_ipv6_addrs *mask;\n};\n\nstruct flow_match_ip {\n\tstruct flow_dissector_key_ip *key;\n\tstruct flow_dissector_key_ip *mask;\n};\n\nstruct flow_match_ports {\n\tstruct flow_dissector_key_ports *key;\n\tstruct flow_dissector_key_ports *mask;\n};\n\nstruct flow_match_icmp {\n\tstruct flow_dissector_key_icmp *key;\n\tstruct flow_dissector_key_icmp *mask;\n};\n\nstruct flow_match_tcp {\n\tstruct flow_dissector_key_tcp *key;\n\tstruct flow_dissector_key_tcp *mask;\n};\n\nstruct flow_match_mpls {\n\tstruct flow_dissector_key_mpls *key;\n\tstruct flow_dissector_key_mpls *mask;\n};\n\nstruct flow_match_enc_keyid {\n\tstruct flow_dissector_key_keyid *key;\n\tstruct flow_dissector_key_keyid *mask;\n};\n\nstruct flow_match_enc_opts {\n\tstruct flow_dissector_key_enc_opts *key;\n\tstruct flow_dissector_key_enc_opts *mask;\n};\n\nstruct flow_match_ct {\n\tstruct flow_dissector_key_ct *key;\n\tstruct flow_dissector_key_ct *mask;\n};\n\nenum flow_action_id {\n\tFLOW_ACTION_ACCEPT = 0,\n\tFLOW_ACTION_DROP = 1,\n\tFLOW_ACTION_TRAP = 2,\n\tFLOW_ACTION_GOTO = 3,\n\tFLOW_ACTION_REDIRECT = 4,\n\tFLOW_ACTION_MIRRED = 5,\n\tFLOW_ACTION_REDIRECT_INGRESS = 6,\n\tFLOW_ACTION_MIRRED_INGRESS = 7,\n\tFLOW_ACTION_VLAN_PUSH = 8,\n\tFLOW_ACTION_VLAN_POP = 9,\n\tFLOW_ACTION_VLAN_MANGLE = 10,\n\tFLOW_ACTION_TUNNEL_ENCAP = 11,\n\tFLOW_ACTION_TUNNEL_DECAP = 12,\n\tFLOW_ACTION_MANGLE = 13,\n\tFLOW_ACTION_ADD = 14,\n\tFLOW_ACTION_CSUM = 15,\n\tFLOW_ACTION_MARK = 16,\n\tFLOW_ACTION_PTYPE = 17,\n\tFLOW_ACTION_PRIORITY = 18,\n\tFLOW_ACTION_WAKE = 19,\n\tFLOW_ACTION_QUEUE = 20,\n\tFLOW_ACTION_SAMPLE = 21,\n\tFLOW_ACTION_POLICE = 22,\n\tFLOW_ACTION_CT = 23,\n\tFLOW_ACTION_CT_METADATA = 24,\n\tFLOW_ACTION_MPLS_PUSH = 25,\n\tFLOW_ACTION_MPLS_POP = 26,\n\tFLOW_ACTION_MPLS_MANGLE = 27,\n\tFLOW_ACTION_GATE = 28,\n\tNUM_FLOW_ACTIONS = 29,\n};\n\nenum flow_action_mangle_base {\n\tFLOW_ACT_MANGLE_UNSPEC = 0,\n\tFLOW_ACT_MANGLE_HDR_TYPE_ETH = 1,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP4 = 2,\n\tFLOW_ACT_MANGLE_HDR_TYPE_IP6 = 3,\n\tFLOW_ACT_MANGLE_HDR_TYPE_TCP = 4,\n\tFLOW_ACT_MANGLE_HDR_TYPE_UDP = 5,\n};\n\nenum flow_action_hw_stats {\n\tFLOW_ACTION_HW_STATS_IMMEDIATE = 1,\n\tFLOW_ACTION_HW_STATS_DELAYED = 2,\n\tFLOW_ACTION_HW_STATS_ANY = 3,\n\tFLOW_ACTION_HW_STATS_DISABLED = 4,\n\tFLOW_ACTION_HW_STATS_DONT_CARE = 7,\n};\n\ntypedef void (*action_destr)(void *);\n\nstruct flow_action_cookie {\n\tu32 cookie_len;\n\tu8 cookie[0];\n};\n\nstruct nf_flowtable;\n\nstruct psample_group;\n\nstruct action_gate_entry;\n\nstruct flow_action_entry {\n\tenum flow_action_id id;\n\tenum flow_action_hw_stats hw_stats;\n\taction_destr destructor;\n\tvoid *destructor_priv;\n\tunion {\n\t\tu32 chain_index;\n\t\tstruct net_device *dev;\n\t\tstruct {\n\t\t\tu16 vid;\n\t\t\t__be16 proto;\n\t\t\tu8 prio;\n\t\t} vlan;\n\t\tstruct {\n\t\t\tenum flow_action_mangle_base htype;\n\t\t\tu32 offset;\n\t\t\tu32 mask;\n\t\t\tu32 val;\n\t\t} mangle;\n\t\tstruct ip_tunnel_info *tunnel;\n\t\tu32 csum_flags;\n\t\tu32 mark;\n\t\tu16 ptype;\n\t\tu32 priority;\n\t\tstruct {\n\t\t\tu32 ctx;\n\t\t\tu32 index;\n\t\t\tu8 vf;\n\t\t} queue;\n\t\tstruct {\n\t\t\tstruct psample_group *psample_group;\n\t\t\tu32 rate;\n\t\t\tu32 trunc_size;\n\t\t\tbool truncate;\n\t\t} sample;\n\t\tstruct {\n\t\t\ts64 burst;\n\t\t\tu64 rate_bytes_ps;\n\t\t} police;\n\t\tstruct {\n\t\t\tint action;\n\t\t\tu16 zone;\n\t\t\tstruct nf_flowtable *flow_table;\n\t\t} ct;\n\t\tstruct {\n\t\t\tlong unsigned int cookie;\n\t\t\tu32 mark;\n\t\t\tu32 labels[4];\n\t\t} ct_metadata;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\t__be16 proto;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_push;\n\t\tstruct {\n\t\t\t__be16 proto;\n\t\t} mpls_pop;\n\t\tstruct {\n\t\t\tu32 label;\n\t\t\tu8 tc;\n\t\t\tu8 bos;\n\t\t\tu8 ttl;\n\t\t} mpls_mangle;\n\t\tstruct {\n\t\t\tu32 index;\n\t\t\ts32 prio;\n\t\t\tu64 basetime;\n\t\t\tu64 cycletime;\n\t\t\tu64 cycletimeext;\n\t\t\tu32 num_entries;\n\t\t\tstruct action_gate_entry *entries;\n\t\t} gate;\n\t};\n\tstruct flow_action_cookie *cookie;\n};\n\nstruct flow_action {\n\tunsigned int num_entries;\n\tstruct flow_action_entry entries[0];\n};\n\nstruct flow_rule {\n\tstruct flow_match match;\n\tstruct flow_action action;\n};\n\nenum flow_block_command {\n\tFLOW_BLOCK_BIND = 0,\n\tFLOW_BLOCK_UNBIND = 1,\n};\n\nenum flow_block_binder_type {\n\tFLOW_BLOCK_BINDER_TYPE_UNSPEC = 0,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS = 1,\n\tFLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS = 2,\n};\n\nstruct flow_block_offload {\n\tenum flow_block_command command;\n\tenum flow_block_binder_type binder_type;\n\tbool block_shared;\n\tbool unlocked_driver_cb;\n\tstruct net *net;\n\tstruct flow_block *block;\n\tstruct list_head cb_list;\n\tstruct list_head *driver_block_list;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct flow_block_cb;\n\nstruct flow_block_indr {\n\tstruct list_head list;\n\tstruct net_device *dev;\n\tenum flow_block_binder_type binder_type;\n\tvoid *data;\n\tvoid *cb_priv;\n\tvoid (*cleanup)(struct flow_block_cb *);\n};\n\nstruct flow_block_cb {\n\tstruct list_head driver_list;\n\tstruct list_head list;\n\tflow_setup_cb_t *cb;\n\tvoid *cb_ident;\n\tvoid *cb_priv;\n\tvoid (*release)(void *);\n\tstruct flow_block_indr indr;\n\tunsigned int refcnt;\n};\n\ntypedef int flow_indr_block_bind_cb_t(struct net_device *, void *, enum tc_setup_type, void *, void *, void (*)(struct flow_block_cb *));\n\nstruct flow_indr_dev {\n\tstruct list_head list;\n\tflow_indr_block_bind_cb_t *cb;\n\tvoid *cb_priv;\n\trefcount_t refcnt;\n\tstruct callback_head rcu;\n};\n\nstruct rx_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct netdev_rx_queue *, char *);\n\tssize_t (*store)(struct netdev_rx_queue *, const char *, size_t);\n};\n\nstruct netdev_queue_attribute {\n\tstruct attribute attr;\n\tssize_t (*show)(struct netdev_queue *, char *);\n\tssize_t (*store)(struct netdev_queue *, const char *, size_t);\n};\n\nstruct strp_stats {\n\tlong long unsigned int msgs;\n\tlong long unsigned int bytes;\n\tunsigned int mem_fail;\n\tunsigned int need_more_hdr;\n\tunsigned int msg_too_big;\n\tunsigned int msg_timeouts;\n\tunsigned int bad_hdr_len;\n};\n\nstruct strparser;\n\nstruct strp_callbacks {\n\tint (*parse_msg)(struct strparser *, struct sk_buff *);\n\tvoid (*rcv_msg)(struct strparser *, struct sk_buff *);\n\tint (*read_sock_done)(struct strparser *, int);\n\tvoid (*abort_parser)(struct strparser *, int);\n\tvoid (*lock)(struct strparser *);\n\tvoid (*unlock)(struct strparser *);\n};\n\nstruct strparser {\n\tstruct sock *sk;\n\tu32 stopped: 1;\n\tu32 paused: 1;\n\tu32 aborted: 1;\n\tu32 interrupted: 1;\n\tu32 unrecov_intr: 1;\n\tstruct sk_buff **skb_nextp;\n\tstruct sk_buff *skb_head;\n\tunsigned int need_bytes;\n\tstruct delayed_work msg_timer_work;\n\tstruct work_struct work;\n\tstruct strp_stats stats;\n\tstruct strp_callbacks cb;\n};\n\nenum __sk_action {\n\t__SK_DROP = 0,\n\t__SK_PASS = 1,\n\t__SK_REDIRECT = 2,\n\t__SK_NONE = 3,\n};\n\nstruct sk_psock_progs {\n\tstruct bpf_prog *msg_parser;\n\tstruct bpf_prog *skb_parser;\n\tstruct bpf_prog *skb_verdict;\n};\n\nenum sk_psock_state_bits {\n\tSK_PSOCK_TX_ENABLED = 0,\n};\n\nstruct sk_psock_link {\n\tstruct list_head list;\n\tstruct bpf_map *map;\n\tvoid *link_raw;\n};\n\nstruct sk_psock_parser {\n\tstruct strparser strp;\n\tbool enabled;\n\tvoid (*saved_data_ready)(struct sock *);\n};\n\nstruct sk_psock_work_state {\n\tstruct sk_buff *skb;\n\tu32 len;\n\tu32 off;\n};\n\nstruct sk_psock {\n\tstruct sock *sk;\n\tstruct sock *sk_redir;\n\tu32 apply_bytes;\n\tu32 cork_bytes;\n\tu32 eval;\n\tstruct sk_msg *cork;\n\tstruct sk_psock_progs progs;\n\tstruct sk_psock_parser parser;\n\tstruct sk_buff_head ingress_skb;\n\tstruct list_head ingress_msg;\n\tlong unsigned int state;\n\tstruct list_head link;\n\tspinlock_t link_lock;\n\trefcount_t refcnt;\n\tvoid (*saved_unhash)(struct sock *);\n\tvoid (*saved_close)(struct sock *, long int);\n\tvoid (*saved_write_space)(struct sock *);\n\tstruct proto *sk_proto;\n\tstruct sk_psock_work_state work_state;\n\tstruct work_struct work;\n\tunion {\n\t\tstruct callback_head rcu;\n\t\tstruct work_struct gc;\n\t};\n};\n\nstruct tls_crypto_info {\n\t__u16 version;\n\t__u16 cipher_type;\n};\n\nstruct tls12_crypto_info_aes_gcm_128 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[16];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls12_crypto_info_aes_gcm_256 {\n\tstruct tls_crypto_info info;\n\tunsigned char iv[8];\n\tunsigned char key[32];\n\tunsigned char salt[4];\n\tunsigned char rec_seq[8];\n};\n\nstruct tls_sw_context_rx {\n\tstruct crypto_aead *aead_recv;\n\tstruct crypto_wait async_wait;\n\tstruct strparser strp;\n\tstruct sk_buff_head rx_list;\n\tvoid (*saved_data_ready)(struct sock *);\n\tstruct sk_buff *recv_pkt;\n\tu8 control;\n\tu8 async_capable: 1;\n\tu8 decrypted: 1;\n\tatomic_t decrypt_pending;\n\tspinlock_t decrypt_compl_lock;\n\tbool async_notify;\n};\n\nstruct cipher_context {\n\tchar *iv;\n\tchar *rec_seq;\n};\n\nunion tls_crypto_context {\n\tstruct tls_crypto_info info;\n\tunion {\n\t\tstruct tls12_crypto_info_aes_gcm_128 aes_gcm_128;\n\t\tstruct tls12_crypto_info_aes_gcm_256 aes_gcm_256;\n\t};\n};\n\nstruct tls_prot_info {\n\tu16 version;\n\tu16 cipher_type;\n\tu16 prepend_size;\n\tu16 tag_size;\n\tu16 overhead_size;\n\tu16 iv_size;\n\tu16 salt_size;\n\tu16 rec_seq_size;\n\tu16 aad_size;\n\tu16 tail_size;\n};\n\nstruct tls_context {\n\tstruct tls_prot_info prot_info;\n\tu8 tx_conf: 3;\n\tu8 rx_conf: 3;\n\tint (*push_pending_record)(struct sock *, int);\n\tvoid (*sk_write_space)(struct sock *);\n\tvoid *priv_ctx_tx;\n\tvoid *priv_ctx_rx;\n\tstruct net_device *netdev;\n\tstruct cipher_context tx;\n\tstruct cipher_context rx;\n\tstruct scatterlist *partially_sent_record;\n\tu16 partially_sent_offset;\n\tbool in_tcp_sendpages;\n\tbool pending_open_record_frags;\n\tstruct mutex tx_lock;\n\tlong unsigned int flags;\n\tstruct proto *sk_proto;\n\tvoid (*sk_destruct)(struct sock *);\n\tunion tls_crypto_context crypto_send;\n\tunion tls_crypto_context crypto_recv;\n\tstruct list_head list;\n\trefcount_t refcount;\n\tstruct callback_head rcu;\n};\n\nstruct fib_rule_uid_range {\n\t__u32 start;\n\t__u32 end;\n};\n\nenum {\n\tFRA_UNSPEC = 0,\n\tFRA_DST = 1,\n\tFRA_SRC = 2,\n\tFRA_IIFNAME = 3,\n\tFRA_GOTO = 4,\n\tFRA_UNUSED2 = 5,\n\tFRA_PRIORITY = 6,\n\tFRA_UNUSED3 = 7,\n\tFRA_UNUSED4 = 8,\n\tFRA_UNUSED5 = 9,\n\tFRA_FWMARK = 10,\n\tFRA_FLOW = 11,\n\tFRA_TUN_ID = 12,\n\tFRA_SUPPRESS_IFGROUP = 13,\n\tFRA_SUPPRESS_PREFIXLEN = 14,\n\tFRA_TABLE = 15,\n\tFRA_FWMASK = 16,\n\tFRA_OIFNAME = 17,\n\tFRA_PAD = 18,\n\tFRA_L3MDEV = 19,\n\tFRA_UID_RANGE = 20,\n\tFRA_PROTOCOL = 21,\n\tFRA_IP_PROTO = 22,\n\tFRA_SPORT_RANGE = 23,\n\tFRA_DPORT_RANGE = 24,\n\t__FRA_MAX = 25,\n};\n\nenum {\n\tFR_ACT_UNSPEC = 0,\n\tFR_ACT_TO_TBL = 1,\n\tFR_ACT_GOTO = 2,\n\tFR_ACT_NOP = 3,\n\tFR_ACT_RES3 = 4,\n\tFR_ACT_RES4 = 5,\n\tFR_ACT_BLACKHOLE = 6,\n\tFR_ACT_UNREACHABLE = 7,\n\tFR_ACT_PROHIBIT = 8,\n\t__FR_ACT_MAX = 9,\n};\n\nstruct fib_rule_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib_rule *rule;\n};\n\nstruct trace_event_raw_kfree_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tvoid *location;\n\tshort unsigned int protocol;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_consume_skb {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_skb_copy_datagram_iovec {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tint len;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_kfree_skb {};\n\nstruct trace_event_data_offsets_consume_skb {};\n\nstruct trace_event_data_offsets_skb_copy_datagram_iovec {};\n\ntypedef void (*btf_trace_kfree_skb)(void *, struct sk_buff *, void *);\n\ntypedef void (*btf_trace_consume_skb)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_skb_copy_datagram_iovec)(void *, const struct sk_buff *, int);\n\nstruct trace_event_raw_net_dev_start_xmit {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tunsigned int len;\n\tunsigned int data_len;\n\tint network_offset;\n\tbool transport_offset_valid;\n\tint transport_offset;\n\tu8 tx_flags;\n\tu16 gso_size;\n\tu16 gso_segs;\n\tu16 gso_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tint rc;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_xmit_timeout {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tu32 __data_loc_driver;\n\tint queue_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_template {\n\tstruct trace_entry ent;\n\tvoid *skbaddr;\n\tunsigned int len;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_verbose_template {\n\tstruct trace_entry ent;\n\tu32 __data_loc_name;\n\tunsigned int napi_id;\n\tu16 queue_mapping;\n\tconst void *skbaddr;\n\tbool vlan_tagged;\n\tu16 vlan_proto;\n\tu16 vlan_tci;\n\tu16 protocol;\n\tu8 ip_summed;\n\tu32 hash;\n\tbool l4_hash;\n\tunsigned int len;\n\tunsigned int data_len;\n\tunsigned int truesize;\n\tbool mac_header_valid;\n\tint mac_header;\n\tunsigned char nr_frags;\n\tu16 gso_size;\n\tu16 gso_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_net_dev_rx_exit_template {\n\tstruct trace_entry ent;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_net_dev_start_xmit {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_net_dev_xmit_timeout {\n\tu32 name;\n\tu32 driver;\n};\n\nstruct trace_event_data_offsets_net_dev_template {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_net_dev_rx_verbose_template {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_net_dev_rx_exit_template {};\n\ntypedef void (*btf_trace_net_dev_start_xmit)(void *, const struct sk_buff *, const struct net_device *);\n\ntypedef void (*btf_trace_net_dev_xmit)(void *, struct sk_buff *, int, struct net_device *, unsigned int);\n\ntypedef void (*btf_trace_net_dev_xmit_timeout)(void *, struct net_device *, int);\n\ntypedef void (*btf_trace_net_dev_queue)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx)(void *, struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_frags_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_receive_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_receive_skb_list_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_netif_rx_ni_entry)(void *, const struct sk_buff *);\n\ntypedef void (*btf_trace_napi_gro_frags_exit)(void *, int);\n\ntypedef void (*btf_trace_napi_gro_receive_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_receive_skb_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_rx_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_rx_ni_exit)(void *, int);\n\ntypedef void (*btf_trace_netif_receive_skb_list_exit)(void *, int);\n\nstruct trace_event_raw_napi_poll {\n\tstruct trace_entry ent;\n\tstruct napi_struct *napi;\n\tu32 __data_loc_dev_name;\n\tint work;\n\tint budget;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_napi_poll {\n\tu32 dev_name;\n};\n\ntypedef void (*btf_trace_napi_poll)(void *, struct napi_struct *, int, int);\n\nenum tcp_ca_state {\n\tTCP_CA_Open = 0,\n\tTCP_CA_Disorder = 1,\n\tTCP_CA_CWR = 2,\n\tTCP_CA_Recovery = 3,\n\tTCP_CA_Loss = 4,\n};\n\nstruct trace_event_raw_sock_rcvqueue_full {\n\tstruct trace_entry ent;\n\tint rmem_alloc;\n\tunsigned int truesize;\n\tint sk_rcvbuf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sock_exceed_buf_limit {\n\tstruct trace_entry ent;\n\tchar name[32];\n\tlong int *sysctl_mem;\n\tlong int allocated;\n\tint sysctl_rmem;\n\tint rmem_alloc;\n\tint sysctl_wmem;\n\tint wmem_alloc;\n\tint wmem_queued;\n\tint kind;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_inet_sock_set_state {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tint oldstate;\n\tint newstate;\n\t__u16 sport;\n\t__u16 dport;\n\t__u16 family;\n\t__u16 protocol;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_sock_rcvqueue_full {};\n\nstruct trace_event_data_offsets_sock_exceed_buf_limit {};\n\nstruct trace_event_data_offsets_inet_sock_set_state {};\n\ntypedef void (*btf_trace_sock_rcvqueue_full)(void *, struct sock *, struct sk_buff *);\n\ntypedef void (*btf_trace_sock_exceed_buf_limit)(void *, struct sock *, struct proto *, long int, int);\n\ntypedef void (*btf_trace_inet_sock_set_state)(void *, const struct sock *, const int, const int);\n\nstruct trace_event_raw_udp_fail_queue_rcv_skb {\n\tstruct trace_entry ent;\n\tint rc;\n\t__u16 lport;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_udp_fail_queue_rcv_skb {};\n\ntypedef void (*btf_trace_udp_fail_queue_rcv_skb)(void *, int, struct sock *);\n\nstruct trace_event_raw_tcp_event_sk_skb {\n\tstruct trace_entry ent;\n\tconst void *skbaddr;\n\tconst void *skaddr;\n\tint state;\n\t__u16 sport;\n\t__u16 dport;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_event_sk {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\t__u16 sport;\n\t__u16 dport;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_retransmit_synack {\n\tstruct trace_entry ent;\n\tconst void *skaddr;\n\tconst void *req;\n\t__u16 sport;\n\t__u16 dport;\n\t__u8 saddr[4];\n\t__u8 daddr[4];\n\t__u8 saddr_v6[16];\n\t__u8 daddr_v6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tcp_probe {\n\tstruct trace_entry ent;\n\t__u8 saddr[28];\n\t__u8 daddr[28];\n\t__u16 sport;\n\t__u16 dport;\n\t__u32 mark;\n\t__u16 data_len;\n\t__u32 snd_nxt;\n\t__u32 snd_una;\n\t__u32 snd_cwnd;\n\t__u32 ssthresh;\n\t__u32 snd_wnd;\n\t__u32 srtt;\n\t__u32 rcv_wnd;\n\t__u64 sock_cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_tcp_event_sk_skb {};\n\nstruct trace_event_data_offsets_tcp_event_sk {};\n\nstruct trace_event_data_offsets_tcp_retransmit_synack {};\n\nstruct trace_event_data_offsets_tcp_probe {};\n\ntypedef void (*btf_trace_tcp_retransmit_skb)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_send_reset)(void *, const struct sock *, const struct sk_buff *);\n\ntypedef void (*btf_trace_tcp_receive_reset)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_destroy_sock)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_rcv_space_adjust)(void *, struct sock *);\n\ntypedef void (*btf_trace_tcp_retransmit_synack)(void *, const struct sock *, const struct request_sock *);\n\ntypedef void (*btf_trace_tcp_probe)(void *, struct sock *, struct sk_buff *);\n\nstruct trace_event_raw_fib_table_lookup {\n\tstruct trace_entry ent;\n\tu32 tb_id;\n\tint err;\n\tint oif;\n\tint iif;\n\tu8 proto;\n\t__u8 tos;\n\t__u8 scope;\n\t__u8 flags;\n\t__u8 src[4];\n\t__u8 dst[4];\n\t__u8 gw4[4];\n\t__u8 gw6[16];\n\tu16 sport;\n\tu16 dport;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_fib_table_lookup {\n\tu32 name;\n};\n\ntypedef void (*btf_trace_fib_table_lookup)(void *, u32, const struct flowi4 *, const struct fib_nh_common *, int);\n\nstruct trace_event_raw_qdisc_dequeue {\n\tstruct trace_entry ent;\n\tstruct Qdisc *qdisc;\n\tconst struct netdev_queue *txq;\n\tint packets;\n\tvoid *skbaddr;\n\tint ifindex;\n\tu32 handle;\n\tu32 parent;\n\tlong unsigned int txq_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_reset {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_destroy {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tu32 handle;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_qdisc_create {\n\tstruct trace_entry ent;\n\tu32 __data_loc_dev;\n\tu32 __data_loc_kind;\n\tu32 parent;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_qdisc_dequeue {};\n\nstruct trace_event_data_offsets_qdisc_reset {\n\tu32 dev;\n\tu32 kind;\n};\n\nstruct trace_event_data_offsets_qdisc_destroy {\n\tu32 dev;\n\tu32 kind;\n};\n\nstruct trace_event_data_offsets_qdisc_create {\n\tu32 dev;\n\tu32 kind;\n};\n\ntypedef void (*btf_trace_qdisc_dequeue)(void *, struct Qdisc *, const struct netdev_queue *, int, struct sk_buff *);\n\ntypedef void (*btf_trace_qdisc_reset)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_qdisc_destroy)(void *, struct Qdisc *);\n\ntypedef void (*btf_trace_qdisc_create)(void *, const struct Qdisc_ops *, struct net_device *, u32);\n\nstruct trace_event_raw_neigh_create {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tint entries;\n\tu8 created;\n\tu8 gc_exempt;\n\tu8 primary_key4[4];\n\tu8 primary_key6[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh_update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu8 new_lladdr[32];\n\tu8 new_state;\n\tu32 update_flags;\n\tu32 pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_neigh__update {\n\tstruct trace_entry ent;\n\tu32 family;\n\tu32 __data_loc_dev;\n\tu8 lladdr[32];\n\tu8 lladdr_len;\n\tu8 flags;\n\tu8 nud_state;\n\tu8 type;\n\tu8 dead;\n\tint refcnt;\n\t__u8 primary_key4[4];\n\t__u8 primary_key6[16];\n\tlong unsigned int confirmed;\n\tlong unsigned int updated;\n\tlong unsigned int used;\n\tu32 err;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_neigh_create {\n\tu32 dev;\n};\n\nstruct trace_event_data_offsets_neigh_update {\n\tu32 dev;\n};\n\nstruct trace_event_data_offsets_neigh__update {\n\tu32 dev;\n};\n\ntypedef void (*btf_trace_neigh_create)(void *, struct neigh_table *, struct net_device *, const void *, const struct neighbour *, bool);\n\ntypedef void (*btf_trace_neigh_update)(void *, struct neighbour *, const u8 *, u8, u32, u32);\n\ntypedef void (*btf_trace_neigh_update_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_timer_handler)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_event_send_done)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_event_send_dead)(void *, struct neighbour *, int);\n\ntypedef void (*btf_trace_neigh_cleanup_and_release)(void *, struct neighbour *, int);\n\nenum lwtunnel_encap_types {\n\tLWTUNNEL_ENCAP_NONE = 0,\n\tLWTUNNEL_ENCAP_MPLS = 1,\n\tLWTUNNEL_ENCAP_IP = 2,\n\tLWTUNNEL_ENCAP_ILA = 3,\n\tLWTUNNEL_ENCAP_IP6 = 4,\n\tLWTUNNEL_ENCAP_SEG6 = 5,\n\tLWTUNNEL_ENCAP_BPF = 6,\n\tLWTUNNEL_ENCAP_SEG6_LOCAL = 7,\n\tLWTUNNEL_ENCAP_RPL = 8,\n\t__LWTUNNEL_ENCAP_MAX = 9,\n};\n\nstruct rtnexthop {\n\tshort unsigned int rtnh_len;\n\tunsigned char rtnh_flags;\n\tunsigned char rtnh_hops;\n\tint rtnh_ifindex;\n};\n\nstruct lwtunnel_encap_ops {\n\tint (*build_state)(struct net *, struct nlattr *, unsigned int, const void *, struct lwtunnel_state **, struct netlink_ext_ack *);\n\tvoid (*destroy_state)(struct lwtunnel_state *);\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*input)(struct sk_buff *);\n\tint (*fill_encap)(struct sk_buff *, struct lwtunnel_state *);\n\tint (*get_encap_size)(struct lwtunnel_state *);\n\tint (*cmp_encap)(struct lwtunnel_state *, struct lwtunnel_state *);\n\tint (*xmit)(struct sk_buff *);\n\tstruct module *owner;\n};\n\nenum {\n\tLWT_BPF_PROG_UNSPEC = 0,\n\tLWT_BPF_PROG_FD = 1,\n\tLWT_BPF_PROG_NAME = 2,\n\t__LWT_BPF_PROG_MAX = 3,\n};\n\nenum {\n\tLWT_BPF_UNSPEC = 0,\n\tLWT_BPF_IN = 1,\n\tLWT_BPF_OUT = 2,\n\tLWT_BPF_XMIT = 3,\n\tLWT_BPF_XMIT_HEADROOM = 4,\n\t__LWT_BPF_MAX = 5,\n};\n\nenum {\n\tLWTUNNEL_XMIT_DONE = 0,\n\tLWTUNNEL_XMIT_CONTINUE = 1,\n};\n\nstruct bpf_lwt_prog {\n\tstruct bpf_prog *prog;\n\tchar *name;\n};\n\nstruct bpf_lwt {\n\tstruct bpf_lwt_prog in;\n\tstruct bpf_lwt_prog out;\n\tstruct bpf_lwt_prog xmit;\n\tint family;\n};\n\nstruct bpf_stab {\n\tstruct bpf_map map;\n\tstruct sock **sks;\n\tstruct sk_psock_progs progs;\n\traw_spinlock_t lock;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef u64 (*btf_bpf_sock_map_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_map)(struct sk_buff *, struct bpf_map *, u32, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_map)(struct sk_msg *, struct bpf_map *, u32, u64);\n\nstruct bpf_htab_elem {\n\tstruct callback_head rcu;\n\tu32 hash;\n\tstruct sock *sk;\n\tstruct hlist_node node;\n\tu8 key[0];\n};\n\nstruct bpf_htab_bucket {\n\tstruct hlist_head head;\n\traw_spinlock_t lock;\n};\n\nstruct bpf_htab___2 {\n\tstruct bpf_map map;\n\tstruct bpf_htab_bucket *buckets;\n\tu32 buckets_num;\n\tu32 elem_size;\n\tstruct sk_psock_progs progs;\n\tatomic_t count;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef u64 (*btf_bpf_sock_hash_update)(struct bpf_sock_ops_kern *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_sk_redirect_hash)(struct sk_buff *, struct bpf_map *, void *, u64);\n\ntypedef u64 (*btf_bpf_msg_redirect_hash)(struct sk_msg *, struct bpf_map *, void *, u64);\n\nstruct dst_cache_pcpu {\n\tlong unsigned int refresh_ts;\n\tstruct dst_entry *dst;\n\tu32 cookie;\n\tunion {\n\t\tstruct in_addr in_saddr;\n\t\tstruct in6_addr in6_saddr;\n\t};\n};\n\nstruct gro_cell;\n\nstruct gro_cells {\n\tstruct gro_cell *cells;\n};\n\nstruct gro_cell {\n\tstruct sk_buff_head napi_skbs;\n\tstruct napi_struct napi;\n};\n\nenum {\n\tBPF_SK_STORAGE_GET_F_CREATE = 1,\n};\n\nstruct bpf_sk_storage_data;\n\nstruct bpf_sk_storage {\n\tstruct bpf_sk_storage_data *cache[16];\n\tstruct hlist_head list;\n\tstruct sock *sk;\n\tstruct callback_head rcu;\n\traw_spinlock_t lock;\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REQ_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_REQ_MAP_FD = 1,\n\t__SK_DIAG_BPF_STORAGE_REQ_MAX = 2,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_REP_NONE = 0,\n\tSK_DIAG_BPF_STORAGE = 1,\n\t__SK_DIAG_BPF_STORAGE_REP_MAX = 2,\n};\n\nenum {\n\tSK_DIAG_BPF_STORAGE_NONE = 0,\n\tSK_DIAG_BPF_STORAGE_PAD = 1,\n\tSK_DIAG_BPF_STORAGE_MAP_ID = 2,\n\tSK_DIAG_BPF_STORAGE_MAP_VALUE = 3,\n\t__SK_DIAG_BPF_STORAGE_MAX = 4,\n};\n\nstruct bucket___2 {\n\tstruct hlist_head list;\n\traw_spinlock_t lock;\n};\n\nstruct bpf_sk_storage_map {\n\tstruct bpf_map map;\n\tstruct bucket___2 *buckets;\n\tu32 bucket_log;\n\tu16 elem_size;\n\tu16 cache_idx;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct bpf_sk_storage_data {\n\tstruct bpf_sk_storage_map *smap;\n\tu8 data[0];\n};\n\nstruct bpf_sk_storage_elem {\n\tstruct hlist_node map_node;\n\tstruct hlist_node snode;\n\tstruct bpf_sk_storage *sk_storage;\n\tstruct callback_head rcu;\n\tlong: 64;\n\tstruct bpf_sk_storage_data sdata;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\ntypedef u64 (*btf_bpf_sk_storage_get)(struct bpf_map *, struct sock *, void *, u64);\n\ntypedef u64 (*btf_bpf_sk_storage_delete)(struct bpf_map *, struct sock *);\n\nstruct bpf_sk_storage_diag {\n\tu32 nr_maps;\n\tstruct bpf_map *maps[0];\n};\n\nstruct compat_cmsghdr {\n\tcompat_size_t cmsg_len;\n\tcompat_int_t cmsg_level;\n\tcompat_int_t cmsg_type;\n};\n\ntypedef struct sk_buff * (*gro_receive_t)(struct list_head *, struct sk_buff *);\n\nstruct nvmem_cell___2;\n\nstruct fddi_8022_1_hdr {\n\t__u8 dsap;\n\t__u8 ssap;\n\t__u8 ctrl;\n};\n\nstruct fddi_8022_2_hdr {\n\t__u8 dsap;\n\t__u8 ssap;\n\t__u8 ctrl_1;\n\t__u8 ctrl_2;\n};\n\nstruct fddi_snap_hdr {\n\t__u8 dsap;\n\t__u8 ssap;\n\t__u8 ctrl;\n\t__u8 oui[3];\n\t__be16 ethertype;\n};\n\nstruct fddihdr {\n\t__u8 fc;\n\t__u8 daddr[6];\n\t__u8 saddr[6];\n\tunion {\n\t\tstruct fddi_8022_1_hdr llc_8022_1;\n\t\tstruct fddi_8022_2_hdr llc_8022_2;\n\t\tstruct fddi_snap_hdr llc_snap;\n\t} hdr;\n} __attribute__((packed));\n\nstruct tc_ratespec {\n\tunsigned char cell_log;\n\t__u8 linklayer;\n\tshort unsigned int overhead;\n\tshort int cell_align;\n\tshort unsigned int mpu;\n\t__u32 rate;\n};\n\nstruct tc_prio_qopt {\n\tint bands;\n\t__u8 priomap[16];\n};\n\nenum {\n\tTCA_UNSPEC = 0,\n\tTCA_KIND = 1,\n\tTCA_OPTIONS = 2,\n\tTCA_STATS = 3,\n\tTCA_XSTATS = 4,\n\tTCA_RATE = 5,\n\tTCA_FCNT = 6,\n\tTCA_STATS2 = 7,\n\tTCA_STAB = 8,\n\tTCA_PAD = 9,\n\tTCA_DUMP_INVISIBLE = 10,\n\tTCA_CHAIN = 11,\n\tTCA_HW_OFFLOAD = 12,\n\tTCA_INGRESS_BLOCK = 13,\n\tTCA_EGRESS_BLOCK = 14,\n\tTCA_DUMP_FLAGS = 15,\n\t__TCA_MAX = 16,\n};\n\nstruct skb_array {\n\tstruct ptr_ring ring;\n};\n\nstruct psched_ratecfg {\n\tu64 rate_bytes_ps;\n\tu32 mult;\n\tu16 overhead;\n\tu8 linklayer;\n\tu8 shift;\n};\n\nstruct mini_Qdisc_pair {\n\tstruct mini_Qdisc miniq1;\n\tstruct mini_Qdisc miniq2;\n\tstruct mini_Qdisc **p_miniq;\n};\n\nstruct pfifo_fast_priv {\n\tstruct skb_array q[3];\n};\n\nstruct tc_qopt_offload_stats {\n\tstruct gnet_stats_basic_packed *bstats;\n\tstruct gnet_stats_queue *qstats;\n};\n\nenum tc_mq_command {\n\tTC_MQ_CREATE = 0,\n\tTC_MQ_DESTROY = 1,\n\tTC_MQ_STATS = 2,\n\tTC_MQ_GRAFT = 3,\n};\n\nstruct tc_mq_opt_offload_graft_params {\n\tlong unsigned int queue;\n\tu32 child_handle;\n};\n\nstruct tc_mq_qopt_offload {\n\tenum tc_mq_command command;\n\tu32 handle;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t\tstruct tc_mq_opt_offload_graft_params graft_params;\n\t};\n};\n\nstruct mq_sched {\n\tstruct Qdisc **qdiscs;\n};\n\nenum tc_link_layer {\n\tTC_LINKLAYER_UNAWARE = 0,\n\tTC_LINKLAYER_ETHERNET = 1,\n\tTC_LINKLAYER_ATM = 2,\n};\n\nenum {\n\tTCA_STAB_UNSPEC = 0,\n\tTCA_STAB_BASE = 1,\n\tTCA_STAB_DATA = 2,\n\t__TCA_STAB_MAX = 3,\n};\n\nstruct qdisc_rate_table {\n\tstruct tc_ratespec rate;\n\tu32 data[256];\n\tstruct qdisc_rate_table *next;\n\tint refcnt;\n};\n\nstruct Qdisc_class_common {\n\tu32 classid;\n\tstruct hlist_node hnode;\n};\n\nstruct Qdisc_class_hash {\n\tstruct hlist_head *hash;\n\tunsigned int hashsize;\n\tunsigned int hashmask;\n\tunsigned int hashelems;\n};\n\nstruct qdisc_watchdog {\n\tu64 last_expires;\n\tstruct hrtimer timer;\n\tstruct Qdisc *qdisc;\n};\n\nenum tc_root_command {\n\tTC_ROOT_GRAFT = 0,\n};\n\nstruct tc_root_qopt_offload {\n\tenum tc_root_command command;\n\tu32 handle;\n\tbool ingress;\n};\n\nstruct check_loop_arg {\n\tstruct qdisc_walker w;\n\tstruct Qdisc *p;\n\tint depth;\n};\n\nstruct tcf_bind_args {\n\tstruct tcf_walker w;\n\tlong unsigned int base;\n\tlong unsigned int cl;\n\tu32 classid;\n};\n\nstruct tc_bind_class_args {\n\tstruct qdisc_walker w;\n\tlong unsigned int new_cl;\n\tu32 portid;\n\tu32 clid;\n};\n\nstruct qdisc_dump_args {\n\tstruct qdisc_walker w;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n};\n\nenum net_xmit_qdisc_t {\n\t__NET_XMIT_STOLEN = 65536,\n\t__NET_XMIT_BYPASS = 131072,\n};\n\nenum {\n\tTCA_ACT_UNSPEC = 0,\n\tTCA_ACT_KIND = 1,\n\tTCA_ACT_OPTIONS = 2,\n\tTCA_ACT_INDEX = 3,\n\tTCA_ACT_STATS = 4,\n\tTCA_ACT_PAD = 5,\n\tTCA_ACT_COOKIE = 6,\n\tTCA_ACT_FLAGS = 7,\n\tTCA_ACT_HW_STATS = 8,\n\tTCA_ACT_USED_HW_STATS = 9,\n\t__TCA_ACT_MAX = 10,\n};\n\nenum tca_id {\n\tTCA_ID_UNSPEC = 0,\n\tTCA_ID_POLICE = 1,\n\tTCA_ID_GACT = 5,\n\tTCA_ID_IPT = 6,\n\tTCA_ID_PEDIT = 7,\n\tTCA_ID_MIRRED = 8,\n\tTCA_ID_NAT = 9,\n\tTCA_ID_XT = 10,\n\tTCA_ID_SKBEDIT = 11,\n\tTCA_ID_VLAN = 12,\n\tTCA_ID_BPF = 13,\n\tTCA_ID_CONNMARK = 14,\n\tTCA_ID_SKBMOD = 15,\n\tTCA_ID_CSUM = 16,\n\tTCA_ID_TUNNEL_KEY = 17,\n\tTCA_ID_SIMP = 22,\n\tTCA_ID_IFE = 25,\n\tTCA_ID_SAMPLE = 26,\n\tTCA_ID_CTINFO = 27,\n\tTCA_ID_MPLS = 28,\n\tTCA_ID_CT = 29,\n\tTCA_ID_GATE = 30,\n\t__TCA_ID_MAX = 255,\n};\n\nstruct tcf_t {\n\t__u64 install;\n\t__u64 lastuse;\n\t__u64 expires;\n\t__u64 firstuse;\n};\n\nstruct psample_group {\n\tstruct list_head list;\n\tstruct net *net;\n\tu32 group_num;\n\tu32 refcount;\n\tu32 seq;\n\tstruct callback_head rcu;\n};\n\nstruct action_gate_entry {\n\tu8 gate_state;\n\tu32 interval;\n\ts32 ipv;\n\ts32 maxoctets;\n};\n\nenum qdisc_class_ops_flags {\n\tQDISC_CLASS_OPS_DOIT_UNLOCKED = 1,\n};\n\nenum tcf_proto_ops_flags {\n\tTCF_PROTO_OPS_DOIT_UNLOCKED = 1,\n};\n\ntypedef void tcf_chain_head_change_t(struct tcf_proto *, void *);\n\nstruct tcf_idrinfo {\n\tstruct mutex lock;\n\tstruct idr action_idr;\n\tstruct net *net;\n};\n\nstruct tc_action_ops;\n\nstruct tc_cookie;\n\nstruct tc_action {\n\tconst struct tc_action_ops *ops;\n\t__u32 type;\n\tstruct tcf_idrinfo *idrinfo;\n\tu32 tcfa_index;\n\trefcount_t tcfa_refcnt;\n\tatomic_t tcfa_bindcnt;\n\tint tcfa_action;\n\tstruct tcf_t tcfa_tm;\n\tstruct gnet_stats_basic_packed tcfa_bstats;\n\tstruct gnet_stats_basic_packed tcfa_bstats_hw;\n\tstruct gnet_stats_queue tcfa_qstats;\n\tstruct net_rate_estimator *tcfa_rate_est;\n\tspinlock_t tcfa_lock;\n\tstruct gnet_stats_basic_cpu *cpu_bstats;\n\tstruct gnet_stats_basic_cpu *cpu_bstats_hw;\n\tstruct gnet_stats_queue *cpu_qstats;\n\tstruct tc_cookie *act_cookie;\n\tstruct tcf_chain *goto_chain;\n\tu32 tcfa_flags;\n\tu8 hw_stats;\n\tu8 used_hw_stats;\n\tbool used_hw_stats_valid;\n};\n\ntypedef void (*tc_action_priv_destructor)(void *);\n\nstruct tc_action_ops {\n\tstruct list_head head;\n\tchar kind[16];\n\tenum tca_id id;\n\tsize_t size;\n\tstruct module *owner;\n\tint (*act)(struct sk_buff *, const struct tc_action *, struct tcf_result *);\n\tint (*dump)(struct sk_buff *, struct tc_action *, int, int);\n\tvoid (*cleanup)(struct tc_action *);\n\tint (*lookup)(struct net *, struct tc_action **, u32);\n\tint (*init)(struct net *, struct nlattr *, struct nlattr *, struct tc_action **, int, int, bool, struct tcf_proto *, u32, struct netlink_ext_ack *);\n\tint (*walk)(struct net *, struct sk_buff *, struct netlink_callback *, int, const struct tc_action_ops *, struct netlink_ext_ack *);\n\tvoid (*stats_update)(struct tc_action *, u64, u32, u64, bool);\n\tsize_t (*get_fill_size)(const struct tc_action *);\n\tstruct net_device * (*get_dev)(const struct tc_action *, tc_action_priv_destructor *);\n\tstruct psample_group * (*get_psample_group)(const struct tc_action *, tc_action_priv_destructor *);\n};\n\nstruct tc_cookie {\n\tu8 *data;\n\tu32 len;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_block_ext_info {\n\tenum flow_block_binder_type binder_type;\n\ttcf_chain_head_change_t *chain_head_change;\n\tvoid *chain_head_change_priv;\n\tu32 block_index;\n};\n\nstruct tcf_exts {\n\t__u32 type;\n\tint nr_actions;\n\tstruct tc_action **actions;\n\tstruct net *net;\n\tint action;\n\tint police;\n};\n\nenum pedit_header_type {\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK = 0,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_ETH = 1,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_IP4 = 2,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_IP6 = 3,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_TCP = 4,\n\tTCA_PEDIT_KEY_EX_HDR_TYPE_UDP = 5,\n\t__PEDIT_HDR_TYPE_MAX = 6,\n};\n\nenum pedit_cmd {\n\tTCA_PEDIT_KEY_EX_CMD_SET = 0,\n\tTCA_PEDIT_KEY_EX_CMD_ADD = 1,\n\t__PEDIT_CMD_MAX = 2,\n};\n\nstruct tc_pedit_key {\n\t__u32 mask;\n\t__u32 val;\n\t__u32 off;\n\t__u32 at;\n\t__u32 offmask;\n\t__u32 shift;\n};\n\nstruct tcf_pedit_key_ex {\n\tenum pedit_header_type htype;\n\tenum pedit_cmd cmd;\n};\n\nstruct tcf_pedit {\n\tstruct tc_action common;\n\tunsigned char tcfp_nkeys;\n\tunsigned char tcfp_flags;\n\tstruct tc_pedit_key *tcfp_keys;\n\tstruct tcf_pedit_key_ex *tcfp_keys_ex;\n};\n\nstruct tcf_mirred {\n\tstruct tc_action common;\n\tint tcfm_eaction;\n\tbool tcfm_mac_header_xmit;\n\tstruct net_device *tcfm_dev;\n\tstruct list_head tcfm_list;\n};\n\nstruct tcf_vlan_params {\n\tint tcfv_action;\n\tu16 tcfv_push_vid;\n\t__be16 tcfv_push_proto;\n\tu8 tcfv_push_prio;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_vlan {\n\tstruct tc_action common;\n\tstruct tcf_vlan_params *vlan_p;\n};\n\nstruct tcf_tunnel_key_params {\n\tstruct callback_head rcu;\n\tint tcft_action;\n\tstruct metadata_dst *tcft_enc_metadata;\n};\n\nstruct tcf_tunnel_key {\n\tstruct tc_action common;\n\tstruct tcf_tunnel_key_params *params;\n};\n\nstruct tcf_csum_params {\n\tu32 update_flags;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_csum {\n\tstruct tc_action common;\n\tstruct tcf_csum_params *params;\n};\n\nstruct tcf_gact {\n\tstruct tc_action common;\n};\n\nstruct tcf_police_params {\n\tint tcfp_result;\n\tu32 tcfp_ewma_rate;\n\ts64 tcfp_burst;\n\tu32 tcfp_mtu;\n\ts64 tcfp_mtu_ptoks;\n\tstruct psched_ratecfg rate;\n\tbool rate_present;\n\tstruct psched_ratecfg peak;\n\tbool peak_present;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_police {\n\tstruct tc_action common;\n\tstruct tcf_police_params *params;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tspinlock_t tcfp_lock;\n\ts64 tcfp_toks;\n\ts64 tcfp_ptoks;\n\ts64 tcfp_t_c;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct tcf_sample {\n\tstruct tc_action common;\n\tu32 rate;\n\tbool truncate;\n\tu32 trunc_size;\n\tstruct psample_group *psample_group;\n\tu32 psample_group_num;\n\tstruct list_head tcfm_list;\n};\n\nstruct tcf_skbedit_params {\n\tu32 flags;\n\tu32 priority;\n\tu32 mark;\n\tu32 mask;\n\tu16 queue_mapping;\n\tu16 ptype;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_skbedit {\n\tstruct tc_action common;\n\tstruct tcf_skbedit_params *params;\n};\n\nstruct nf_conntrack_tuple_mask {\n\tstruct {\n\t\tunion nf_inet_addr u3;\n\t\tunion nf_conntrack_man_proto u;\n\t} src;\n};\n\nstruct nf_conntrack_l4proto___2;\n\nstruct nf_conntrack_helper;\n\nstruct nf_conntrack_expect {\n\tstruct hlist_node lnode;\n\tstruct hlist_node hnode;\n\tstruct nf_conntrack_tuple tuple;\n\tstruct nf_conntrack_tuple_mask mask;\n\tvoid (*expectfn)(struct nf_conn *, struct nf_conntrack_expect *);\n\tstruct nf_conntrack_helper *helper;\n\tstruct nf_conn *master;\n\tstruct timer_list timeout;\n\trefcount_t use;\n\tunsigned int flags;\n\tunsigned int class;\n\tunion nf_inet_addr saved_addr;\n\tunion nf_conntrack_man_proto saved_proto;\n\tenum ip_conntrack_dir dir;\n\tstruct callback_head rcu;\n};\n\nstruct PptpControlHeader {\n\t__be16 messageType;\n\t__u16 reserved;\n};\n\nstruct PptpStartSessionRequest {\n\t__be16 protocolVersion;\n\t__u16 reserved1;\n\t__be32 framingCapability;\n\t__be32 bearerCapability;\n\t__be16 maxChannels;\n\t__be16 firmwareRevision;\n\t__u8 hostName[64];\n\t__u8 vendorString[64];\n};\n\nstruct PptpStartSessionReply {\n\t__be16 protocolVersion;\n\t__u8 resultCode;\n\t__u8 generalErrorCode;\n\t__be32 framingCapability;\n\t__be32 bearerCapability;\n\t__be16 maxChannels;\n\t__be16 firmwareRevision;\n\t__u8 hostName[64];\n\t__u8 vendorString[64];\n};\n\nstruct PptpStopSessionRequest {\n\t__u8 reason;\n\t__u8 reserved1;\n\t__u16 reserved2;\n};\n\nstruct PptpStopSessionReply {\n\t__u8 resultCode;\n\t__u8 generalErrorCode;\n\t__u16 reserved1;\n};\n\nstruct PptpOutCallRequest {\n\t__be16 callID;\n\t__be16 callSerialNumber;\n\t__be32 minBPS;\n\t__be32 maxBPS;\n\t__be32 bearerType;\n\t__be32 framingType;\n\t__be16 packetWindow;\n\t__be16 packetProcDelay;\n\t__be16 phoneNumberLength;\n\t__u16 reserved1;\n\t__u8 phoneNumber[64];\n\t__u8 subAddress[64];\n};\n\nstruct PptpOutCallReply {\n\t__be16 callID;\n\t__be16 peersCallID;\n\t__u8 resultCode;\n\t__u8 generalErrorCode;\n\t__be16 causeCode;\n\t__be32 connectSpeed;\n\t__be16 packetWindow;\n\t__be16 packetProcDelay;\n\t__be32 physChannelID;\n};\n\nstruct PptpInCallRequest {\n\t__be16 callID;\n\t__be16 callSerialNumber;\n\t__be32 callBearerType;\n\t__be32 physChannelID;\n\t__be16 dialedNumberLength;\n\t__be16 dialingNumberLength;\n\t__u8 dialedNumber[64];\n\t__u8 dialingNumber[64];\n\t__u8 subAddress[64];\n};\n\nstruct PptpInCallReply {\n\t__be16 callID;\n\t__be16 peersCallID;\n\t__u8 resultCode;\n\t__u8 generalErrorCode;\n\t__be16 packetWindow;\n\t__be16 packetProcDelay;\n\t__u16 reserved;\n};\n\nstruct PptpInCallConnected {\n\t__be16 peersCallID;\n\t__u16 reserved;\n\t__be32 connectSpeed;\n\t__be16 packetWindow;\n\t__be16 packetProcDelay;\n\t__be32 callFramingType;\n};\n\nstruct PptpClearCallRequest {\n\t__be16 callID;\n\t__u16 reserved;\n};\n\nstruct PptpCallDisconnectNotify {\n\t__be16 callID;\n\t__u8 resultCode;\n\t__u8 generalErrorCode;\n\t__be16 causeCode;\n\t__u16 reserved;\n\t__u8 callStatistics[128];\n};\n\nstruct PptpWanErrorNotify {\n\t__be16 peersCallID;\n\t__u16 reserved;\n\t__be32 crcErrors;\n\t__be32 framingErrors;\n\t__be32 hardwareOverRuns;\n\t__be32 bufferOverRuns;\n\t__be32 timeoutErrors;\n\t__be32 alignmentErrors;\n};\n\nstruct PptpSetLinkInfo {\n\t__be16 peersCallID;\n\t__u16 reserved;\n\t__be32 sendAccm;\n\t__be32 recvAccm;\n};\n\nunion pptp_ctrl_union {\n\tstruct PptpStartSessionRequest sreq;\n\tstruct PptpStartSessionReply srep;\n\tstruct PptpStopSessionRequest streq;\n\tstruct PptpStopSessionReply strep;\n\tstruct PptpOutCallRequest ocreq;\n\tstruct PptpOutCallReply ocack;\n\tstruct PptpInCallRequest icreq;\n\tstruct PptpInCallReply icack;\n\tstruct PptpInCallConnected iccon;\n\tstruct PptpClearCallRequest clrreq;\n\tstruct PptpCallDisconnectNotify disc;\n\tstruct PptpWanErrorNotify wanerr;\n\tstruct PptpSetLinkInfo setlink;\n};\n\nstruct nf_nat_range2 {\n\tunsigned int flags;\n\tunion nf_inet_addr min_addr;\n\tunion nf_inet_addr max_addr;\n\tunion nf_conntrack_man_proto min_proto;\n\tunion nf_conntrack_man_proto max_proto;\n\tunion nf_conntrack_man_proto base_proto;\n};\n\nstruct tcf_ct_flow_table;\n\nstruct tcf_ct_params {\n\tstruct nf_conn *tmpl;\n\tu16 zone;\n\tu32 mark;\n\tu32 mark_mask;\n\tu32 labels[4];\n\tu32 labels_mask[4];\n\tstruct nf_nat_range2 range;\n\tbool ipv4_range;\n\tu16 ct_action;\n\tstruct callback_head rcu;\n\tstruct tcf_ct_flow_table *ct_ft;\n\tstruct nf_flowtable *nf_ft;\n};\n\nstruct tcf_ct {\n\tstruct tc_action common;\n\tstruct tcf_ct_params *params;\n};\n\nstruct tcf_mpls_params {\n\tint tcfm_action;\n\tu32 tcfm_label;\n\tu8 tcfm_tc;\n\tu8 tcfm_ttl;\n\tu8 tcfm_bos;\n\t__be16 tcfm_proto;\n\tstruct callback_head rcu;\n};\n\nstruct tcf_mpls {\n\tstruct tc_action common;\n\tstruct tcf_mpls_params *mpls_p;\n};\n\nstruct tcfg_gate_entry {\n\tint index;\n\tu8 gate_state;\n\tu32 interval;\n\ts32 ipv;\n\ts32 maxoctets;\n\tstruct list_head list;\n};\n\nstruct tcf_gate_params {\n\ts32 tcfg_priority;\n\tu64 tcfg_basetime;\n\tu64 tcfg_cycletime;\n\tu64 tcfg_cycletime_ext;\n\tu32 tcfg_flags;\n\ts32 tcfg_clockid;\n\tsize_t num_entries;\n\tstruct list_head entries;\n};\n\nstruct tcf_gate {\n\tstruct tc_action common;\n\tstruct tcf_gate_params param;\n\tu8 current_gate_status;\n\tktime_t current_close_time;\n\tu32 current_entry_octets;\n\ts32 current_max_octets;\n\tstruct tcfg_gate_entry *next_entry;\n\tstruct hrtimer hitimer;\n\tenum tk_offsets tk_offset;\n};\n\nstruct tcf_filter_chain_list_item {\n\tstruct list_head list;\n\ttcf_chain_head_change_t *chain_head_change;\n\tvoid *chain_head_change_priv;\n};\n\nstruct tcf_net {\n\tspinlock_t idr_lock;\n\tstruct idr idr;\n};\n\nstruct tcf_block_owner_item {\n\tstruct list_head list;\n\tstruct Qdisc *q;\n\tenum flow_block_binder_type binder_type;\n};\n\nstruct tcf_chain_info {\n\tstruct tcf_proto **pprev;\n\tstruct tcf_proto *next;\n};\n\nstruct tcf_dump_args {\n\tstruct tcf_walker w;\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tstruct tcf_block *block;\n\tstruct Qdisc *q;\n\tu32 parent;\n\tbool terse_dump;\n};\n\nstruct tcamsg {\n\tunsigned char tca_family;\n\tunsigned char tca__pad1;\n\tshort unsigned int tca__pad2;\n};\n\nenum {\n\tTCA_ROOT_UNSPEC = 0,\n\tTCA_ROOT_TAB = 1,\n\tTCA_ROOT_FLAGS = 2,\n\tTCA_ROOT_COUNT = 3,\n\tTCA_ROOT_TIME_DELTA = 4,\n\t__TCA_ROOT_MAX = 5,\n};\n\nstruct tc_action_net {\n\tstruct tcf_idrinfo *idrinfo;\n\tconst struct tc_action_ops *ops;\n};\n\nstruct tc_act_bpf {\n\t__u32 index;\n\t__u32 capab;\n\tint action;\n\tint refcnt;\n\tint bindcnt;\n};\n\nenum {\n\tTCA_ACT_BPF_UNSPEC = 0,\n\tTCA_ACT_BPF_TM = 1,\n\tTCA_ACT_BPF_PARMS = 2,\n\tTCA_ACT_BPF_OPS_LEN = 3,\n\tTCA_ACT_BPF_OPS = 4,\n\tTCA_ACT_BPF_FD = 5,\n\tTCA_ACT_BPF_NAME = 6,\n\tTCA_ACT_BPF_PAD = 7,\n\tTCA_ACT_BPF_TAG = 8,\n\tTCA_ACT_BPF_ID = 9,\n\t__TCA_ACT_BPF_MAX = 10,\n};\n\nstruct tcf_bpf {\n\tstruct tc_action common;\n\tstruct bpf_prog *filter;\n\tunion {\n\t\tu32 bpf_fd;\n\t\tu16 bpf_num_ops;\n\t};\n\tstruct sock_filter *bpf_ops;\n\tconst char *bpf_name;\n};\n\nstruct tcf_bpf_cfg {\n\tstruct bpf_prog *filter;\n\tstruct sock_filter *bpf_ops;\n\tconst char *bpf_name;\n\tu16 bpf_num_ops;\n\tbool is_ebpf;\n};\n\nstruct tc_fifo_qopt {\n\t__u32 limit;\n};\n\nenum tc_fifo_command {\n\tTC_FIFO_REPLACE = 0,\n\tTC_FIFO_DESTROY = 1,\n\tTC_FIFO_STATS = 2,\n};\n\nstruct tc_fifo_qopt_offload {\n\tenum tc_fifo_command command;\n\tu32 handle;\n\tu32 parent;\n\tunion {\n\t\tstruct tc_qopt_offload_stats stats;\n\t};\n};\n\nenum {\n\tTCA_BPF_UNSPEC = 0,\n\tTCA_BPF_ACT = 1,\n\tTCA_BPF_POLICE = 2,\n\tTCA_BPF_CLASSID = 3,\n\tTCA_BPF_OPS_LEN = 4,\n\tTCA_BPF_OPS = 5,\n\tTCA_BPF_FD = 6,\n\tTCA_BPF_NAME = 7,\n\tTCA_BPF_FLAGS = 8,\n\tTCA_BPF_FLAGS_GEN = 9,\n\tTCA_BPF_TAG = 10,\n\tTCA_BPF_ID = 11,\n\t__TCA_BPF_MAX = 12,\n};\n\nstruct flow_cls_common_offload {\n\tu32 chain_index;\n\t__be16 protocol;\n\tu32 prio;\n\tstruct netlink_ext_ack *extack;\n};\n\nenum tc_clsbpf_command {\n\tTC_CLSBPF_OFFLOAD = 0,\n\tTC_CLSBPF_STATS = 1,\n};\n\nstruct tc_cls_bpf_offload {\n\tstruct flow_cls_common_offload common;\n\tenum tc_clsbpf_command command;\n\tstruct tcf_exts *exts;\n\tstruct bpf_prog *prog;\n\tstruct bpf_prog *oldprog;\n\tconst char *name;\n\tbool exts_integrated;\n};\n\nstruct cls_bpf_head {\n\tstruct list_head plist;\n\tstruct idr handle_idr;\n\tstruct callback_head rcu;\n};\n\nstruct cls_bpf_prog {\n\tstruct bpf_prog *filter;\n\tstruct list_head link;\n\tstruct tcf_result res;\n\tbool exts_integrated;\n\tu32 gen_flags;\n\tunsigned int in_hw_count;\n\tstruct tcf_exts exts;\n\tu32 handle;\n\tu16 bpf_num_ops;\n\tstruct sock_filter *bpf_ops;\n\tconst char *bpf_name;\n\tstruct tcf_proto *tp;\n\tstruct rcu_work rwork;\n};\n\nstruct tcf_ematch_tree_hdr {\n\t__u16 nmatches;\n\t__u16 progid;\n};\n\nenum {\n\tTCA_EMATCH_TREE_UNSPEC = 0,\n\tTCA_EMATCH_TREE_HDR = 1,\n\tTCA_EMATCH_TREE_LIST = 2,\n\t__TCA_EMATCH_TREE_MAX = 3,\n};\n\nstruct tcf_ematch_hdr {\n\t__u16 matchid;\n\t__u16 kind;\n\t__u16 flags;\n\t__u16 pad;\n};\n\nstruct tcf_pkt_info {\n\tunsigned char *ptr;\n\tint nexthdr;\n};\n\nstruct tcf_ematch_ops;\n\nstruct tcf_ematch {\n\tstruct tcf_ematch_ops *ops;\n\tlong unsigned int data;\n\tunsigned int datalen;\n\tu16 matchid;\n\tu16 flags;\n\tstruct net *net;\n};\n\nstruct tcf_ematch_ops {\n\tint kind;\n\tint datalen;\n\tint (*change)(struct net *, void *, int, struct tcf_ematch *);\n\tint (*match)(struct sk_buff *, struct tcf_ematch *, struct tcf_pkt_info *);\n\tvoid (*destroy)(struct tcf_ematch *);\n\tint (*dump)(struct sk_buff *, struct tcf_ematch *);\n\tstruct module *owner;\n\tstruct list_head link;\n};\n\nstruct tcf_ematch_tree {\n\tstruct tcf_ematch_tree_hdr hdr;\n\tstruct tcf_ematch *matches;\n};\n\nstruct sockaddr_nl {\n\t__kernel_sa_family_t nl_family;\n\tshort unsigned int nl_pad;\n\t__u32 nl_pid;\n\t__u32 nl_groups;\n};\n\nstruct nlmsgerr {\n\tint error;\n\tstruct nlmsghdr msg;\n};\n\nenum nlmsgerr_attrs {\n\tNLMSGERR_ATTR_UNUSED = 0,\n\tNLMSGERR_ATTR_MSG = 1,\n\tNLMSGERR_ATTR_OFFS = 2,\n\tNLMSGERR_ATTR_COOKIE = 3,\n\t__NLMSGERR_ATTR_MAX = 4,\n\tNLMSGERR_ATTR_MAX = 3,\n};\n\nstruct nl_pktinfo {\n\t__u32 group;\n};\n\nenum {\n\tNETLINK_UNCONNECTED = 0,\n\tNETLINK_CONNECTED = 1,\n};\n\nenum netlink_skb_flags {\n\tNETLINK_SKB_DST = 8,\n};\n\nstruct netlink_notify {\n\tstruct net *net;\n\tu32 portid;\n\tint protocol;\n};\n\nstruct netlink_tap {\n\tstruct net_device *dev;\n\tstruct module *module;\n\tstruct list_head list;\n};\n\nstruct netlink_sock {\n\tstruct sock sk;\n\tu32 portid;\n\tu32 dst_portid;\n\tu32 dst_group;\n\tu32 flags;\n\tu32 subscriptions;\n\tu32 ngroups;\n\tlong unsigned int *groups;\n\tlong unsigned int state;\n\tsize_t max_recvmsg_len;\n\twait_queue_head_t wait;\n\tbool bound;\n\tbool cb_running;\n\tint dump_done_errno;\n\tstruct netlink_callback cb;\n\tstruct mutex *cb_mutex;\n\tstruct mutex cb_def_mutex;\n\tvoid (*netlink_rcv)(struct sk_buff *);\n\tint (*netlink_bind)(struct net *, int);\n\tvoid (*netlink_unbind)(struct net *, int);\n\tstruct module *module;\n\tstruct rhash_head node;\n\tstruct callback_head rcu;\n\tstruct work_struct work;\n};\n\nstruct listeners;\n\nstruct netlink_table {\n\tstruct rhashtable hash;\n\tstruct hlist_head mc_list;\n\tstruct listeners *listeners;\n\tunsigned int flags;\n\tunsigned int groups;\n\tstruct mutex *cb_mutex;\n\tstruct module *module;\n\tint (*bind)(struct net *, int);\n\tvoid (*unbind)(struct net *, int);\n\tbool (*compare)(struct net *, struct sock *);\n\tint registered;\n};\n\nstruct listeners {\n\tstruct callback_head rcu;\n\tlong unsigned int masks[0];\n};\n\nstruct netlink_tap_net {\n\tstruct list_head netlink_tap_all;\n\tstruct mutex netlink_tap_lock;\n};\n\nstruct netlink_compare_arg {\n\tpossible_net_t pnet;\n\tu32 portid;\n};\n\nstruct netlink_broadcast_data {\n\tstruct sock *exclude_sk;\n\tstruct net *net;\n\tu32 portid;\n\tu32 group;\n\tint failure;\n\tint delivery_failure;\n\tint congested;\n\tint delivered;\n\tgfp_t allocation;\n\tstruct sk_buff *skb;\n\tstruct sk_buff *skb2;\n\tint (*tx_filter)(struct sock *, struct sk_buff *, void *);\n\tvoid *tx_data;\n};\n\nstruct netlink_set_err_data {\n\tstruct sock *exclude_sk;\n\tu32 portid;\n\tu32 group;\n\tint code;\n};\n\nstruct nl_seq_iter {\n\tstruct seq_net_private p;\n\tstruct rhashtable_iter hti;\n\tint link;\n};\n\nstruct bpf_iter__netlink {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct netlink_sock *sk;\n\t};\n};\n\nenum {\n\tCTRL_CMD_UNSPEC = 0,\n\tCTRL_CMD_NEWFAMILY = 1,\n\tCTRL_CMD_DELFAMILY = 2,\n\tCTRL_CMD_GETFAMILY = 3,\n\tCTRL_CMD_NEWOPS = 4,\n\tCTRL_CMD_DELOPS = 5,\n\tCTRL_CMD_GETOPS = 6,\n\tCTRL_CMD_NEWMCAST_GRP = 7,\n\tCTRL_CMD_DELMCAST_GRP = 8,\n\tCTRL_CMD_GETMCAST_GRP = 9,\n\tCTRL_CMD_GETPOLICY = 10,\n\t__CTRL_CMD_MAX = 11,\n};\n\nenum {\n\tCTRL_ATTR_UNSPEC = 0,\n\tCTRL_ATTR_FAMILY_ID = 1,\n\tCTRL_ATTR_FAMILY_NAME = 2,\n\tCTRL_ATTR_VERSION = 3,\n\tCTRL_ATTR_HDRSIZE = 4,\n\tCTRL_ATTR_MAXATTR = 5,\n\tCTRL_ATTR_OPS = 6,\n\tCTRL_ATTR_MCAST_GROUPS = 7,\n\tCTRL_ATTR_POLICY = 8,\n\t__CTRL_ATTR_MAX = 9,\n};\n\nenum {\n\tCTRL_ATTR_OP_UNSPEC = 0,\n\tCTRL_ATTR_OP_ID = 1,\n\tCTRL_ATTR_OP_FLAGS = 2,\n\t__CTRL_ATTR_OP_MAX = 3,\n};\n\nenum {\n\tCTRL_ATTR_MCAST_GRP_UNSPEC = 0,\n\tCTRL_ATTR_MCAST_GRP_NAME = 1,\n\tCTRL_ATTR_MCAST_GRP_ID = 2,\n\t__CTRL_ATTR_MCAST_GRP_MAX = 3,\n};\n\nstruct genl_dumpit_info {\n\tconst struct genl_family *family;\n\tconst struct genl_ops *ops;\n\tstruct nlattr **attrs;\n};\n\nstruct genl_start_context {\n\tconst struct genl_family *family;\n\tstruct nlmsghdr *nlh;\n\tstruct netlink_ext_ack *extack;\n\tconst struct genl_ops *ops;\n\tint hdrlen;\n};\n\nenum netlink_attribute_type {\n\tNL_ATTR_TYPE_INVALID = 0,\n\tNL_ATTR_TYPE_FLAG = 1,\n\tNL_ATTR_TYPE_U8 = 2,\n\tNL_ATTR_TYPE_U16 = 3,\n\tNL_ATTR_TYPE_U32 = 4,\n\tNL_ATTR_TYPE_U64 = 5,\n\tNL_ATTR_TYPE_S8 = 6,\n\tNL_ATTR_TYPE_S16 = 7,\n\tNL_ATTR_TYPE_S32 = 8,\n\tNL_ATTR_TYPE_S64 = 9,\n\tNL_ATTR_TYPE_BINARY = 10,\n\tNL_ATTR_TYPE_STRING = 11,\n\tNL_ATTR_TYPE_NUL_STRING = 12,\n\tNL_ATTR_TYPE_NESTED = 13,\n\tNL_ATTR_TYPE_NESTED_ARRAY = 14,\n\tNL_ATTR_TYPE_BITFIELD32 = 15,\n};\n\nenum netlink_policy_type_attr {\n\tNL_POLICY_TYPE_ATTR_UNSPEC = 0,\n\tNL_POLICY_TYPE_ATTR_TYPE = 1,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_S = 2,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_S = 3,\n\tNL_POLICY_TYPE_ATTR_MIN_VALUE_U = 4,\n\tNL_POLICY_TYPE_ATTR_MAX_VALUE_U = 5,\n\tNL_POLICY_TYPE_ATTR_MIN_LENGTH = 6,\n\tNL_POLICY_TYPE_ATTR_MAX_LENGTH = 7,\n\tNL_POLICY_TYPE_ATTR_POLICY_IDX = 8,\n\tNL_POLICY_TYPE_ATTR_POLICY_MAXTYPE = 9,\n\tNL_POLICY_TYPE_ATTR_BITFIELD32_MASK = 10,\n\tNL_POLICY_TYPE_ATTR_PAD = 11,\n\t__NL_POLICY_TYPE_ATTR_MAX = 12,\n\tNL_POLICY_TYPE_ATTR_MAX = 11,\n};\n\nstruct nl_policy_dump {\n\tunsigned int policy_idx;\n\tunsigned int attr_idx;\n\tunsigned int n_alloc;\n\tstruct {\n\t\tconst struct nla_policy *policy;\n\t\tunsigned int maxtype;\n\t} policies[0];\n};\n\nstruct trace_event_raw_bpf_test_finish {\n\tstruct trace_entry ent;\n\tint err;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_bpf_test_finish {};\n\ntypedef void (*btf_trace_bpf_test_finish)(void *, int *);\n\nstruct bpf_fentry_test_t {\n\tstruct bpf_fentry_test_t *a;\n};\n\nstruct ethtool_value {\n\t__u32 cmd;\n\t__u32 data;\n};\n\nenum tunable_id {\n\tETHTOOL_ID_UNSPEC = 0,\n\tETHTOOL_RX_COPYBREAK = 1,\n\tETHTOOL_TX_COPYBREAK = 2,\n\tETHTOOL_PFC_PREVENTION_TOUT = 3,\n\t__ETHTOOL_TUNABLE_COUNT = 4,\n};\n\nenum tunable_type_id {\n\tETHTOOL_TUNABLE_UNSPEC = 0,\n\tETHTOOL_TUNABLE_U8 = 1,\n\tETHTOOL_TUNABLE_U16 = 2,\n\tETHTOOL_TUNABLE_U32 = 3,\n\tETHTOOL_TUNABLE_U64 = 4,\n\tETHTOOL_TUNABLE_STRING = 5,\n\tETHTOOL_TUNABLE_S8 = 6,\n\tETHTOOL_TUNABLE_S16 = 7,\n\tETHTOOL_TUNABLE_S32 = 8,\n\tETHTOOL_TUNABLE_S64 = 9,\n};\n\nenum phy_tunable_id {\n\tETHTOOL_PHY_ID_UNSPEC = 0,\n\tETHTOOL_PHY_DOWNSHIFT = 1,\n\tETHTOOL_PHY_FAST_LINK_DOWN = 2,\n\tETHTOOL_PHY_EDPD = 3,\n\t__ETHTOOL_PHY_TUNABLE_COUNT = 4,\n};\n\nstruct ethtool_gstrings {\n\t__u32 cmd;\n\t__u32 string_set;\n\t__u32 len;\n\t__u8 data[0];\n};\n\nstruct ethtool_sset_info {\n\t__u32 cmd;\n\t__u32 reserved;\n\t__u64 sset_mask;\n\t__u32 data[0];\n};\n\nstruct ethtool_perm_addr {\n\t__u32 cmd;\n\t__u32 size;\n\t__u8 data[0];\n};\n\nenum ethtool_flags {\n\tETH_FLAG_TXVLAN = 128,\n\tETH_FLAG_RXVLAN = 256,\n\tETH_FLAG_LRO = 32768,\n\tETH_FLAG_NTUPLE = 134217728,\n\tETH_FLAG_RXHASH = 268435456,\n};\n\nstruct ethtool_rxfh {\n\t__u32 cmd;\n\t__u32 rss_context;\n\t__u32 indir_size;\n\t__u32 key_size;\n\t__u8 hfunc;\n\t__u8 rsvd8[3];\n\t__u32 rsvd32;\n\t__u32 rss_config[0];\n};\n\nstruct ethtool_get_features_block {\n\t__u32 available;\n\t__u32 requested;\n\t__u32 active;\n\t__u32 never_changed;\n};\n\nstruct ethtool_gfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_get_features_block features[0];\n};\n\nstruct ethtool_set_features_block {\n\t__u32 valid;\n\t__u32 requested;\n};\n\nstruct ethtool_sfeatures {\n\t__u32 cmd;\n\t__u32 size;\n\tstruct ethtool_set_features_block features[0];\n};\n\nenum ethtool_sfeatures_retval_bits {\n\tETHTOOL_F_UNSUPPORTED__BIT = 0,\n\tETHTOOL_F_WISH__BIT = 1,\n\tETHTOOL_F_COMPAT__BIT = 2,\n};\n\nstruct ethtool_per_queue_op {\n\t__u32 cmd;\n\t__u32 sub_command;\n\t__u32 queue_mask[128];\n\tchar data[0];\n};\n\nstruct ethtool_rx_flow_rule {\n\tstruct flow_rule *rule;\n\tlong unsigned int priv[0];\n};\n\nstruct ethtool_rx_flow_spec_input {\n\tconst struct ethtool_rx_flow_spec *fs;\n\tu32 rss_ctx;\n};\n\nstruct ethtool_link_usettings {\n\tstruct ethtool_link_settings base;\n\tstruct {\n\t\t__u32 supported[3];\n\t\t__u32 advertising[3];\n\t\t__u32 lp_advertising[3];\n\t} link_modes;\n};\n\nstruct ethtool_rx_flow_key {\n\tstruct flow_dissector_key_basic basic;\n\tunion {\n\t\tstruct flow_dissector_key_ipv4_addrs ipv4;\n\t\tstruct flow_dissector_key_ipv6_addrs ipv6;\n\t};\n\tstruct flow_dissector_key_ports tp;\n\tstruct flow_dissector_key_ip ip;\n\tstruct flow_dissector_key_vlan vlan;\n\tstruct flow_dissector_key_eth_addrs eth_addrs;\n\tlong: 48;\n};\n\nstruct ethtool_rx_flow_match {\n\tstruct flow_dissector dissector;\n\tint: 32;\n\tstruct ethtool_rx_flow_key key;\n\tstruct ethtool_rx_flow_key mask;\n};\n\nenum {\n\tETHTOOL_MSG_USER_NONE = 0,\n\tETHTOOL_MSG_STRSET_GET = 1,\n\tETHTOOL_MSG_LINKINFO_GET = 2,\n\tETHTOOL_MSG_LINKINFO_SET = 3,\n\tETHTOOL_MSG_LINKMODES_GET = 4,\n\tETHTOOL_MSG_LINKMODES_SET = 5,\n\tETHTOOL_MSG_LINKSTATE_GET = 6,\n\tETHTOOL_MSG_DEBUG_GET = 7,\n\tETHTOOL_MSG_DEBUG_SET = 8,\n\tETHTOOL_MSG_WOL_GET = 9,\n\tETHTOOL_MSG_WOL_SET = 10,\n\tETHTOOL_MSG_FEATURES_GET = 11,\n\tETHTOOL_MSG_FEATURES_SET = 12,\n\tETHTOOL_MSG_PRIVFLAGS_GET = 13,\n\tETHTOOL_MSG_PRIVFLAGS_SET = 14,\n\tETHTOOL_MSG_RINGS_GET = 15,\n\tETHTOOL_MSG_RINGS_SET = 16,\n\tETHTOOL_MSG_CHANNELS_GET = 17,\n\tETHTOOL_MSG_CHANNELS_SET = 18,\n\tETHTOOL_MSG_COALESCE_GET = 19,\n\tETHTOOL_MSG_COALESCE_SET = 20,\n\tETHTOOL_MSG_PAUSE_GET = 21,\n\tETHTOOL_MSG_PAUSE_SET = 22,\n\tETHTOOL_MSG_EEE_GET = 23,\n\tETHTOOL_MSG_EEE_SET = 24,\n\tETHTOOL_MSG_TSINFO_GET = 25,\n\tETHTOOL_MSG_CABLE_TEST_ACT = 26,\n\tETHTOOL_MSG_CABLE_TEST_TDR_ACT = 27,\n\t__ETHTOOL_MSG_USER_CNT = 28,\n\tETHTOOL_MSG_USER_MAX = 27,\n};\n\nenum {\n\tETHTOOL_A_HEADER_UNSPEC = 0,\n\tETHTOOL_A_HEADER_DEV_INDEX = 1,\n\tETHTOOL_A_HEADER_DEV_NAME = 2,\n\tETHTOOL_A_HEADER_FLAGS = 3,\n\t__ETHTOOL_A_HEADER_CNT = 4,\n\tETHTOOL_A_HEADER_MAX = 3,\n};\n\nenum ethtool_multicast_groups {\n\tETHNL_MCGRP_MONITOR = 0,\n};\n\nstruct ethnl_req_info {\n\tstruct net_device *dev;\n\tu32 flags;\n};\n\nstruct ethnl_reply_data {\n\tstruct net_device *dev;\n};\n\nstruct ethnl_request_ops {\n\tu8 request_cmd;\n\tu8 reply_cmd;\n\tu16 hdr_attr;\n\tunsigned int max_attr;\n\tunsigned int req_info_size;\n\tunsigned int reply_data_size;\n\tconst struct nla_policy *request_policy;\n\tbool allow_nodev_do;\n\tint (*parse_request)(struct ethnl_req_info *, struct nlattr **, struct netlink_ext_ack *);\n\tint (*prepare_data)(const struct ethnl_req_info *, struct ethnl_reply_data *, struct genl_info *);\n\tint (*reply_size)(const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tint (*fill_reply)(struct sk_buff *, const struct ethnl_req_info *, const struct ethnl_reply_data *);\n\tvoid (*cleanup_data)(struct ethnl_reply_data *);\n};\n\nstruct ethnl_dump_ctx {\n\tconst struct ethnl_request_ops *ops;\n\tstruct ethnl_req_info *req_info;\n\tstruct ethnl_reply_data *reply_data;\n\tint pos_hash;\n\tint pos_idx;\n};\n\ntypedef void (*ethnl_notify_handler_t)(struct net_device *, unsigned int, const void *);\n\nenum {\n\tETHTOOL_A_BITSET_BIT_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BIT_INDEX = 1,\n\tETHTOOL_A_BITSET_BIT_NAME = 2,\n\tETHTOOL_A_BITSET_BIT_VALUE = 3,\n\t__ETHTOOL_A_BITSET_BIT_CNT = 4,\n\tETHTOOL_A_BITSET_BIT_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_BITSET_BITS_UNSPEC = 0,\n\tETHTOOL_A_BITSET_BITS_BIT = 1,\n\t__ETHTOOL_A_BITSET_BITS_CNT = 2,\n\tETHTOOL_A_BITSET_BITS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_BITSET_UNSPEC = 0,\n\tETHTOOL_A_BITSET_NOMASK = 1,\n\tETHTOOL_A_BITSET_SIZE = 2,\n\tETHTOOL_A_BITSET_BITS = 3,\n\tETHTOOL_A_BITSET_VALUE = 4,\n\tETHTOOL_A_BITSET_MASK = 5,\n\t__ETHTOOL_A_BITSET_CNT = 6,\n\tETHTOOL_A_BITSET_MAX = 5,\n};\n\ntypedef const char (* const ethnl_string_array_t)[32];\n\nenum {\n\tETHTOOL_A_STRING_UNSPEC = 0,\n\tETHTOOL_A_STRING_INDEX = 1,\n\tETHTOOL_A_STRING_VALUE = 2,\n\t__ETHTOOL_A_STRING_CNT = 3,\n\tETHTOOL_A_STRING_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_STRINGS_UNSPEC = 0,\n\tETHTOOL_A_STRINGS_STRING = 1,\n\t__ETHTOOL_A_STRINGS_CNT = 2,\n\tETHTOOL_A_STRINGS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRINGSET_UNSPEC = 0,\n\tETHTOOL_A_STRINGSET_ID = 1,\n\tETHTOOL_A_STRINGSET_COUNT = 2,\n\tETHTOOL_A_STRINGSET_STRINGS = 3,\n\t__ETHTOOL_A_STRINGSET_CNT = 4,\n\tETHTOOL_A_STRINGSET_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_STRINGSETS_UNSPEC = 0,\n\tETHTOOL_A_STRINGSETS_STRINGSET = 1,\n\t__ETHTOOL_A_STRINGSETS_CNT = 2,\n\tETHTOOL_A_STRINGSETS_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_STRSET_UNSPEC = 0,\n\tETHTOOL_A_STRSET_HEADER = 1,\n\tETHTOOL_A_STRSET_STRINGSETS = 2,\n\tETHTOOL_A_STRSET_COUNTS_ONLY = 3,\n\t__ETHTOOL_A_STRSET_CNT = 4,\n\tETHTOOL_A_STRSET_MAX = 3,\n};\n\nstruct strset_info {\n\tbool per_dev;\n\tbool free_strings;\n\tunsigned int count;\n\tconst char (*strings)[32];\n};\n\nstruct strset_req_info {\n\tstruct ethnl_req_info base;\n\tu32 req_ids;\n\tbool counts_only;\n};\n\nstruct strset_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct strset_info sets[15];\n};\n\nenum {\n\tETHTOOL_A_LINKINFO_UNSPEC = 0,\n\tETHTOOL_A_LINKINFO_HEADER = 1,\n\tETHTOOL_A_LINKINFO_PORT = 2,\n\tETHTOOL_A_LINKINFO_PHYADDR = 3,\n\tETHTOOL_A_LINKINFO_TP_MDIX = 4,\n\tETHTOOL_A_LINKINFO_TP_MDIX_CTRL = 5,\n\tETHTOOL_A_LINKINFO_TRANSCEIVER = 6,\n\t__ETHTOOL_A_LINKINFO_CNT = 7,\n\tETHTOOL_A_LINKINFO_MAX = 6,\n};\n\nstruct linkinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n};\n\nenum {\n\tETHTOOL_A_LINKMODES_UNSPEC = 0,\n\tETHTOOL_A_LINKMODES_HEADER = 1,\n\tETHTOOL_A_LINKMODES_AUTONEG = 2,\n\tETHTOOL_A_LINKMODES_OURS = 3,\n\tETHTOOL_A_LINKMODES_PEER = 4,\n\tETHTOOL_A_LINKMODES_SPEED = 5,\n\tETHTOOL_A_LINKMODES_DUPLEX = 6,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG = 7,\n\tETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE = 8,\n\t__ETHTOOL_A_LINKMODES_CNT = 9,\n\tETHTOOL_A_LINKMODES_MAX = 8,\n};\n\nstruct linkmodes_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_link_ksettings ksettings;\n\tstruct ethtool_link_settings *lsettings;\n\tbool peer_empty;\n};\n\nstruct link_mode_info {\n\tint speed;\n\tu8 duplex;\n};\n\nenum {\n\tETHTOOL_A_LINKSTATE_UNSPEC = 0,\n\tETHTOOL_A_LINKSTATE_HEADER = 1,\n\tETHTOOL_A_LINKSTATE_LINK = 2,\n\tETHTOOL_A_LINKSTATE_SQI = 3,\n\tETHTOOL_A_LINKSTATE_SQI_MAX = 4,\n\t__ETHTOOL_A_LINKSTATE_CNT = 5,\n\tETHTOOL_A_LINKSTATE_MAX = 4,\n};\n\nstruct linkstate_reply_data {\n\tstruct ethnl_reply_data base;\n\tint link;\n\tint sqi;\n\tint sqi_max;\n};\n\nenum {\n\tETHTOOL_A_DEBUG_UNSPEC = 0,\n\tETHTOOL_A_DEBUG_HEADER = 1,\n\tETHTOOL_A_DEBUG_MSGMASK = 2,\n\t__ETHTOOL_A_DEBUG_CNT = 3,\n\tETHTOOL_A_DEBUG_MAX = 2,\n};\n\nstruct debug_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 msg_mask;\n};\n\nenum {\n\tETHTOOL_A_WOL_UNSPEC = 0,\n\tETHTOOL_A_WOL_HEADER = 1,\n\tETHTOOL_A_WOL_MODES = 2,\n\tETHTOOL_A_WOL_SOPASS = 3,\n\t__ETHTOOL_A_WOL_CNT = 4,\n\tETHTOOL_A_WOL_MAX = 3,\n};\n\nstruct wol_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_wolinfo wol;\n\tbool show_sopass;\n};\n\nenum {\n\tETHTOOL_A_FEATURES_UNSPEC = 0,\n\tETHTOOL_A_FEATURES_HEADER = 1,\n\tETHTOOL_A_FEATURES_HW = 2,\n\tETHTOOL_A_FEATURES_WANTED = 3,\n\tETHTOOL_A_FEATURES_ACTIVE = 4,\n\tETHTOOL_A_FEATURES_NOCHANGE = 5,\n\t__ETHTOOL_A_FEATURES_CNT = 6,\n\tETHTOOL_A_FEATURES_MAX = 5,\n};\n\nstruct features_reply_data {\n\tstruct ethnl_reply_data base;\n\tu32 hw[2];\n\tu32 wanted[2];\n\tu32 active[2];\n\tu32 nochange[2];\n\tu32 all[2];\n};\n\nenum {\n\tETHTOOL_A_PRIVFLAGS_UNSPEC = 0,\n\tETHTOOL_A_PRIVFLAGS_HEADER = 1,\n\tETHTOOL_A_PRIVFLAGS_FLAGS = 2,\n\t__ETHTOOL_A_PRIVFLAGS_CNT = 3,\n\tETHTOOL_A_PRIVFLAGS_MAX = 2,\n};\n\nstruct privflags_reply_data {\n\tstruct ethnl_reply_data base;\n\tconst char (*priv_flag_names)[32];\n\tunsigned int n_priv_flags;\n\tu32 priv_flags;\n};\n\nenum {\n\tETHTOOL_A_RINGS_UNSPEC = 0,\n\tETHTOOL_A_RINGS_HEADER = 1,\n\tETHTOOL_A_RINGS_RX_MAX = 2,\n\tETHTOOL_A_RINGS_RX_MINI_MAX = 3,\n\tETHTOOL_A_RINGS_RX_JUMBO_MAX = 4,\n\tETHTOOL_A_RINGS_TX_MAX = 5,\n\tETHTOOL_A_RINGS_RX = 6,\n\tETHTOOL_A_RINGS_RX_MINI = 7,\n\tETHTOOL_A_RINGS_RX_JUMBO = 8,\n\tETHTOOL_A_RINGS_TX = 9,\n\t__ETHTOOL_A_RINGS_CNT = 10,\n\tETHTOOL_A_RINGS_MAX = 9,\n};\n\nstruct rings_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_ringparam ringparam;\n};\n\nenum {\n\tETHTOOL_A_CHANNELS_UNSPEC = 0,\n\tETHTOOL_A_CHANNELS_HEADER = 1,\n\tETHTOOL_A_CHANNELS_RX_MAX = 2,\n\tETHTOOL_A_CHANNELS_TX_MAX = 3,\n\tETHTOOL_A_CHANNELS_OTHER_MAX = 4,\n\tETHTOOL_A_CHANNELS_COMBINED_MAX = 5,\n\tETHTOOL_A_CHANNELS_RX_COUNT = 6,\n\tETHTOOL_A_CHANNELS_TX_COUNT = 7,\n\tETHTOOL_A_CHANNELS_OTHER_COUNT = 8,\n\tETHTOOL_A_CHANNELS_COMBINED_COUNT = 9,\n\t__ETHTOOL_A_CHANNELS_CNT = 10,\n\tETHTOOL_A_CHANNELS_MAX = 9,\n};\n\nstruct channels_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_channels channels;\n};\n\nenum {\n\tETHTOOL_A_COALESCE_UNSPEC = 0,\n\tETHTOOL_A_COALESCE_HEADER = 1,\n\tETHTOOL_A_COALESCE_RX_USECS = 2,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES = 3,\n\tETHTOOL_A_COALESCE_RX_USECS_IRQ = 4,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_IRQ = 5,\n\tETHTOOL_A_COALESCE_TX_USECS = 6,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES = 7,\n\tETHTOOL_A_COALESCE_TX_USECS_IRQ = 8,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_IRQ = 9,\n\tETHTOOL_A_COALESCE_STATS_BLOCK_USECS = 10,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_RX = 11,\n\tETHTOOL_A_COALESCE_USE_ADAPTIVE_TX = 12,\n\tETHTOOL_A_COALESCE_PKT_RATE_LOW = 13,\n\tETHTOOL_A_COALESCE_RX_USECS_LOW = 14,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_LOW = 15,\n\tETHTOOL_A_COALESCE_TX_USECS_LOW = 16,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_LOW = 17,\n\tETHTOOL_A_COALESCE_PKT_RATE_HIGH = 18,\n\tETHTOOL_A_COALESCE_RX_USECS_HIGH = 19,\n\tETHTOOL_A_COALESCE_RX_MAX_FRAMES_HIGH = 20,\n\tETHTOOL_A_COALESCE_TX_USECS_HIGH = 21,\n\tETHTOOL_A_COALESCE_TX_MAX_FRAMES_HIGH = 22,\n\tETHTOOL_A_COALESCE_RATE_SAMPLE_INTERVAL = 23,\n\t__ETHTOOL_A_COALESCE_CNT = 24,\n\tETHTOOL_A_COALESCE_MAX = 23,\n};\n\nstruct coalesce_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_coalesce coalesce;\n\tu32 supported_params;\n};\n\nenum {\n\tETHTOOL_A_PAUSE_UNSPEC = 0,\n\tETHTOOL_A_PAUSE_HEADER = 1,\n\tETHTOOL_A_PAUSE_AUTONEG = 2,\n\tETHTOOL_A_PAUSE_RX = 3,\n\tETHTOOL_A_PAUSE_TX = 4,\n\t__ETHTOOL_A_PAUSE_CNT = 5,\n\tETHTOOL_A_PAUSE_MAX = 4,\n};\n\nstruct pause_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_pauseparam pauseparam;\n};\n\nenum {\n\tETHTOOL_A_EEE_UNSPEC = 0,\n\tETHTOOL_A_EEE_HEADER = 1,\n\tETHTOOL_A_EEE_MODES_OURS = 2,\n\tETHTOOL_A_EEE_MODES_PEER = 3,\n\tETHTOOL_A_EEE_ACTIVE = 4,\n\tETHTOOL_A_EEE_ENABLED = 5,\n\tETHTOOL_A_EEE_TX_LPI_ENABLED = 6,\n\tETHTOOL_A_EEE_TX_LPI_TIMER = 7,\n\t__ETHTOOL_A_EEE_CNT = 8,\n\tETHTOOL_A_EEE_MAX = 7,\n};\n\nstruct eee_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_eee eee;\n};\n\nenum {\n\tETHTOOL_A_TSINFO_UNSPEC = 0,\n\tETHTOOL_A_TSINFO_HEADER = 1,\n\tETHTOOL_A_TSINFO_TIMESTAMPING = 2,\n\tETHTOOL_A_TSINFO_TX_TYPES = 3,\n\tETHTOOL_A_TSINFO_RX_FILTERS = 4,\n\tETHTOOL_A_TSINFO_PHC_INDEX = 5,\n\t__ETHTOOL_A_TSINFO_CNT = 6,\n\tETHTOOL_A_TSINFO_MAX = 5,\n};\n\nstruct tsinfo_reply_data {\n\tstruct ethnl_reply_data base;\n\tstruct ethtool_ts_info ts_info;\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_HEADER = 1,\n\t__ETHTOOL_A_CABLE_TEST_CNT = 2,\n\tETHTOOL_A_CABLE_TEST_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PAIR_A = 0,\n\tETHTOOL_A_CABLE_PAIR_B = 1,\n\tETHTOOL_A_CABLE_PAIR_C = 2,\n\tETHTOOL_A_CABLE_PAIR_D = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_RESULT_UNSPEC = 0,\n\tETHTOOL_A_CABLE_RESULT_PAIR = 1,\n\tETHTOOL_A_CABLE_RESULT_CODE = 2,\n\t__ETHTOOL_A_CABLE_RESULT_CNT = 3,\n\tETHTOOL_A_CABLE_RESULT_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_FAULT_LENGTH_UNSPEC = 0,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_PAIR = 1,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_CM = 2,\n\t__ETHTOOL_A_CABLE_FAULT_LENGTH_CNT = 3,\n\tETHTOOL_A_CABLE_FAULT_LENGTH_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_STARTED = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS_COMPLETED = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_NEST_RESULT = 1,\n\tETHTOOL_A_CABLE_NEST_FAULT_LENGTH = 2,\n\t__ETHTOOL_A_CABLE_NEST_CNT = 3,\n\tETHTOOL_A_CABLE_NEST_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_NTF_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_NTF_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_NTF_STATUS = 2,\n\tETHTOOL_A_CABLE_TEST_NTF_NEST = 3,\n\t__ETHTOOL_A_CABLE_TEST_NTF_CNT = 4,\n\tETHTOOL_A_CABLE_TEST_NTF_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_FIRST = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_LAST = 2,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_STEP = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_PAIR = 4,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CFG_CNT = 5,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG_MAX = 4,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TEST_TDR_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TEST_TDR_HEADER = 1,\n\tETHTOOL_A_CABLE_TEST_TDR_CFG = 2,\n\t__ETHTOOL_A_CABLE_TEST_TDR_CNT = 3,\n\tETHTOOL_A_CABLE_TEST_TDR_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_AMPLITUDE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_AMPLITUDE_PAIR = 1,\n\tETHTOOL_A_CABLE_AMPLITUDE_mV = 2,\n\t__ETHTOOL_A_CABLE_AMPLITUDE_CNT = 3,\n\tETHTOOL_A_CABLE_AMPLITUDE_MAX = 2,\n};\n\nenum {\n\tETHTOOL_A_CABLE_PULSE_UNSPEC = 0,\n\tETHTOOL_A_CABLE_PULSE_mV = 1,\n\t__ETHTOOL_A_CABLE_PULSE_CNT = 2,\n\tETHTOOL_A_CABLE_PULSE_MAX = 1,\n};\n\nenum {\n\tETHTOOL_A_CABLE_STEP_UNSPEC = 0,\n\tETHTOOL_A_CABLE_STEP_FIRST_DISTANCE = 1,\n\tETHTOOL_A_CABLE_STEP_LAST_DISTANCE = 2,\n\tETHTOOL_A_CABLE_STEP_STEP_DISTANCE = 3,\n\t__ETHTOOL_A_CABLE_STEP_CNT = 4,\n\tETHTOOL_A_CABLE_STEP_MAX = 3,\n};\n\nenum {\n\tETHTOOL_A_CABLE_TDR_NEST_UNSPEC = 0,\n\tETHTOOL_A_CABLE_TDR_NEST_STEP = 1,\n\tETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE = 2,\n\tETHTOOL_A_CABLE_TDR_NEST_PULSE = 3,\n\t__ETHTOOL_A_CABLE_TDR_NEST_CNT = 4,\n\tETHTOOL_A_CABLE_TDR_NEST_MAX = 3,\n};\n\nstruct nf_hook_entries_rcu_head {\n\tstruct callback_head head;\n\tvoid *allocation;\n};\n\nstruct nf_loginfo {\n\tu_int8_t type;\n\tunion {\n\t\tstruct {\n\t\t\tu_int32_t copy_len;\n\t\t\tu_int16_t group;\n\t\t\tu_int16_t qthreshold;\n\t\t\tu_int16_t flags;\n\t\t} ulog;\n\t\tstruct {\n\t\t\tu_int8_t level;\n\t\t\tu_int8_t logflags;\n\t\t} log;\n\t} u;\n};\n\nstruct nf_log_buf {\n\tunsigned int count;\n\tchar buf[1020];\n};\n\nstruct ip_rt_info {\n\t__be32 daddr;\n\t__be32 saddr;\n\tu_int8_t tos;\n\tu_int32_t mark;\n};\n\nstruct ip6_rt_info {\n\tstruct in6_addr daddr;\n\tstruct in6_addr saddr;\n\tu_int32_t mark;\n};\n\nstruct nf_sockopt_ops {\n\tstruct list_head list;\n\tu_int8_t pf;\n\tint set_optmin;\n\tint set_optmax;\n\tint (*set)(struct sock *, int, void *, unsigned int);\n\tint (*compat_set)(struct sock *, int, void *, unsigned int);\n\tint get_optmin;\n\tint get_optmax;\n\tint (*get)(struct sock *, int, void *, int *);\n\tint (*compat_get)(struct sock *, int, void *, int *);\n\tstruct module *owner;\n};\n\nenum nfnetlink_groups {\n\tNFNLGRP_NONE = 0,\n\tNFNLGRP_CONNTRACK_NEW = 1,\n\tNFNLGRP_CONNTRACK_UPDATE = 2,\n\tNFNLGRP_CONNTRACK_DESTROY = 3,\n\tNFNLGRP_CONNTRACK_EXP_NEW = 4,\n\tNFNLGRP_CONNTRACK_EXP_UPDATE = 5,\n\tNFNLGRP_CONNTRACK_EXP_DESTROY = 6,\n\tNFNLGRP_NFTABLES = 7,\n\tNFNLGRP_ACCT_QUOTA = 8,\n\tNFNLGRP_NFTRACE = 9,\n\t__NFNLGRP_MAX = 10,\n};\n\nstruct nfgenmsg {\n\t__u8 nfgen_family;\n\t__u8 version;\n\t__be16 res_id;\n};\n\nenum nfnl_batch_attributes {\n\tNFNL_BATCH_UNSPEC = 0,\n\tNFNL_BATCH_GENID = 1,\n\t__NFNL_BATCH_MAX = 2,\n};\n\nstruct nfnl_callback {\n\tint (*call)(struct net *, struct sock *, struct sk_buff *, const struct nlmsghdr *, const struct nlattr * const *, struct netlink_ext_ack *);\n\tint (*call_rcu)(struct net *, struct sock *, struct sk_buff *, const struct nlmsghdr *, const struct nlattr * const *, struct netlink_ext_ack *);\n\tint (*call_batch)(struct net *, struct sock *, struct sk_buff *, const struct nlmsghdr *, const struct nlattr * const *, struct netlink_ext_ack *);\n\tconst struct nla_policy *policy;\n\tconst u_int16_t attr_count;\n};\n\nstruct nfnetlink_subsystem {\n\tconst char *name;\n\t__u8 subsys_id;\n\t__u8 cb_count;\n\tconst struct nfnl_callback *cb;\n\tstruct module *owner;\n\tint (*commit)(struct net *, struct sk_buff *);\n\tint (*abort)(struct net *, struct sk_buff *, bool);\n\tvoid (*cleanup)(struct net *);\n\tbool (*valid_genid)(struct net *, u32);\n};\n\nstruct nfnl_err {\n\tstruct list_head head;\n\tstruct nlmsghdr *nlh;\n\tint err;\n\tstruct netlink_ext_ack extack;\n};\n\nenum {\n\tNFNL_BATCH_FAILURE = 1,\n\tNFNL_BATCH_DONE = 2,\n\tNFNL_BATCH_REPLAY = 4,\n};\n\nenum nfulnl_msg_types {\n\tNFULNL_MSG_PACKET = 0,\n\tNFULNL_MSG_CONFIG = 1,\n\tNFULNL_MSG_MAX = 2,\n};\n\nstruct nfulnl_msg_packet_hdr {\n\t__be16 hw_protocol;\n\t__u8 hook;\n\t__u8 _pad;\n};\n\nstruct nfulnl_msg_packet_hw {\n\t__be16 hw_addrlen;\n\t__u16 _pad;\n\t__u8 hw_addr[8];\n};\n\nstruct nfulnl_msg_packet_timestamp {\n\t__be64 sec;\n\t__be64 usec;\n};\n\nenum nfulnl_vlan_attr {\n\tNFULA_VLAN_UNSPEC = 0,\n\tNFULA_VLAN_PROTO = 1,\n\tNFULA_VLAN_TCI = 2,\n\t__NFULA_VLAN_MAX = 3,\n};\n\nenum nfulnl_attr_type {\n\tNFULA_UNSPEC = 0,\n\tNFULA_PACKET_HDR = 1,\n\tNFULA_MARK = 2,\n\tNFULA_TIMESTAMP = 3,\n\tNFULA_IFINDEX_INDEV = 4,\n\tNFULA_IFINDEX_OUTDEV = 5,\n\tNFULA_IFINDEX_PHYSINDEV = 6,\n\tNFULA_IFINDEX_PHYSOUTDEV = 7,\n\tNFULA_HWADDR = 8,\n\tNFULA_PAYLOAD = 9,\n\tNFULA_PREFIX = 10,\n\tNFULA_UID = 11,\n\tNFULA_SEQ = 12,\n\tNFULA_SEQ_GLOBAL = 13,\n\tNFULA_GID = 14,\n\tNFULA_HWTYPE = 15,\n\tNFULA_HWHEADER = 16,\n\tNFULA_HWLEN = 17,\n\tNFULA_CT = 18,\n\tNFULA_CT_INFO = 19,\n\tNFULA_VLAN = 20,\n\tNFULA_L2HDR = 21,\n\t__NFULA_MAX = 22,\n};\n\nenum nfulnl_msg_config_cmds {\n\tNFULNL_CFG_CMD_NONE = 0,\n\tNFULNL_CFG_CMD_BIND = 1,\n\tNFULNL_CFG_CMD_UNBIND = 2,\n\tNFULNL_CFG_CMD_PF_BIND = 3,\n\tNFULNL_CFG_CMD_PF_UNBIND = 4,\n};\n\nstruct nfulnl_msg_config_cmd {\n\t__u8 command;\n};\n\nstruct nfulnl_msg_config_mode {\n\t__be32 copy_range;\n\t__u8 copy_mode;\n\t__u8 _pad;\n} __attribute__((packed));\n\nenum nfulnl_attr_config {\n\tNFULA_CFG_UNSPEC = 0,\n\tNFULA_CFG_CMD = 1,\n\tNFULA_CFG_MODE = 2,\n\tNFULA_CFG_NLBUFSIZ = 3,\n\tNFULA_CFG_TIMEOUT = 4,\n\tNFULA_CFG_QTHRESH = 5,\n\tNFULA_CFG_FLAGS = 6,\n\t__NFULA_CFG_MAX = 7,\n};\n\nstruct nfulnl_instance {\n\tstruct hlist_node hlist;\n\tspinlock_t lock;\n\trefcount_t use;\n\tunsigned int qlen;\n\tstruct sk_buff *skb;\n\tstruct timer_list timer;\n\tstruct net *net;\n\tstruct user_namespace *peer_user_ns;\n\tu32 peer_portid;\n\tunsigned int flushtimeout;\n\tunsigned int nlbufsiz;\n\tunsigned int qthreshold;\n\tu_int32_t copy_range;\n\tu_int32_t seq;\n\tu_int16_t group_num;\n\tu_int16_t flags;\n\tu_int8_t copy_mode;\n\tstruct callback_head rcu;\n};\n\nstruct nfnl_log_net {\n\tspinlock_t instances_lock;\n\tstruct hlist_head instance_table[16];\n\tatomic_t global_seq;\n};\n\nstruct iter_state {\n\tstruct seq_net_private p;\n\tunsigned int bucket;\n};\n\nenum ip_conntrack_status {\n\tIPS_EXPECTED_BIT = 0,\n\tIPS_EXPECTED = 1,\n\tIPS_SEEN_REPLY_BIT = 1,\n\tIPS_SEEN_REPLY = 2,\n\tIPS_ASSURED_BIT = 2,\n\tIPS_ASSURED = 4,\n\tIPS_CONFIRMED_BIT = 3,\n\tIPS_CONFIRMED = 8,\n\tIPS_SRC_NAT_BIT = 4,\n\tIPS_SRC_NAT = 16,\n\tIPS_DST_NAT_BIT = 5,\n\tIPS_DST_NAT = 32,\n\tIPS_NAT_MASK = 48,\n\tIPS_SEQ_ADJUST_BIT = 6,\n\tIPS_SEQ_ADJUST = 64,\n\tIPS_SRC_NAT_DONE_BIT = 7,\n\tIPS_SRC_NAT_DONE = 128,\n\tIPS_DST_NAT_DONE_BIT = 8,\n\tIPS_DST_NAT_DONE = 256,\n\tIPS_NAT_DONE_MASK = 384,\n\tIPS_DYING_BIT = 9,\n\tIPS_DYING = 512,\n\tIPS_FIXED_TIMEOUT_BIT = 10,\n\tIPS_FIXED_TIMEOUT = 1024,\n\tIPS_TEMPLATE_BIT = 11,\n\tIPS_TEMPLATE = 2048,\n\tIPS_UNTRACKED_BIT = 12,\n\tIPS_UNTRACKED = 4096,\n\tIPS_NAT_CLASH_BIT = 12,\n\tIPS_NAT_CLASH = 4096,\n\tIPS_HELPER_BIT = 13,\n\tIPS_HELPER = 8192,\n\tIPS_OFFLOAD_BIT = 14,\n\tIPS_OFFLOAD = 16384,\n\tIPS_HW_OFFLOAD_BIT = 15,\n\tIPS_HW_OFFLOAD = 32768,\n\tIPS_UNCHANGEABLE_MASK = 56313,\n\t__IPS_MAX_BIT = 16,\n};\n\nenum ip_conntrack_events {\n\tIPCT_NEW = 0,\n\tIPCT_RELATED = 1,\n\tIPCT_DESTROY = 2,\n\tIPCT_REPLY = 3,\n\tIPCT_ASSURED = 4,\n\tIPCT_PROTOINFO = 5,\n\tIPCT_HELPER = 6,\n\tIPCT_MARK = 7,\n\tIPCT_SEQADJ = 8,\n\tIPCT_NATSEQADJ = 8,\n\tIPCT_SECMARK = 9,\n\tIPCT_LABEL = 10,\n\tIPCT_SYNPROXY = 11,\n\t__IPCT_MAX = 12,\n};\n\nstruct nf_conntrack_expect_policy;\n\nstruct nf_conntrack_helper {\n\tstruct hlist_node hnode;\n\tchar name[16];\n\trefcount_t refcnt;\n\tstruct module *me;\n\tconst struct nf_conntrack_expect_policy *expect_policy;\n\tstruct nf_conntrack_tuple tuple;\n\tint (*help)(struct sk_buff *, unsigned int, struct nf_conn *, enum ip_conntrack_info);\n\tvoid (*destroy)(struct nf_conn *);\n\tint (*from_nlattr)(struct nlattr *, struct nf_conn *);\n\tint (*to_nlattr)(struct sk_buff *, const struct nf_conn *);\n\tunsigned int expect_class_max;\n\tunsigned int flags;\n\tunsigned int queue_num;\n\tu16 data_len;\n\tchar nat_mod_name[16];\n};\n\nstruct nf_conntrack_expect_policy {\n\tunsigned int max_expected;\n\tunsigned int timeout;\n\tchar name[16];\n};\n\nenum nf_ct_helper_flags {\n\tNF_CT_HELPER_F_USERSPACE = 1,\n\tNF_CT_HELPER_F_CONFIGURED = 2,\n};\n\nstruct nf_conn_help {\n\tstruct nf_conntrack_helper *helper;\n\tstruct hlist_head expectations;\n\tu8 expecting[4];\n\tint: 32;\n\tchar data[32];\n};\n\nenum nf_ct_ecache_state {\n\tNFCT_ECACHE_UNKNOWN = 0,\n\tNFCT_ECACHE_DESTROY_FAIL = 1,\n\tNFCT_ECACHE_DESTROY_SENT = 2,\n};\n\nstruct nf_conntrack_ecache {\n\tlong unsigned int cache;\n\tu16 missed;\n\tu16 ctmask;\n\tu16 expmask;\n\tenum nf_ct_ecache_state state: 8;\n\tu32 portid;\n};\n\nstruct nf_conn_counter {\n\tatomic64_t packets;\n\tatomic64_t bytes;\n};\n\nstruct nf_conn_acct {\n\tstruct nf_conn_counter counter[2];\n};\n\nstruct nf_conn_tstamp {\n\tu_int64_t start;\n\tu_int64_t stop;\n};\n\nstruct nf_ct_timeout {\n\t__u16 l3num;\n\tconst struct nf_conntrack_l4proto *l4proto;\n\tchar data[0];\n};\n\nstruct nf_conn_timeout {\n\tstruct nf_ct_timeout *timeout;\n};\n\nstruct conntrack_gc_work {\n\tstruct delayed_work dwork;\n\tu32 last_bucket;\n\tbool exiting;\n\tbool early_drop;\n\tlong int next_gc_run;\n};\n\nenum ctattr_l4proto {\n\tCTA_PROTO_UNSPEC = 0,\n\tCTA_PROTO_NUM = 1,\n\tCTA_PROTO_SRC_PORT = 2,\n\tCTA_PROTO_DST_PORT = 3,\n\tCTA_PROTO_ICMP_ID = 4,\n\tCTA_PROTO_ICMP_TYPE = 5,\n\tCTA_PROTO_ICMP_CODE = 6,\n\tCTA_PROTO_ICMPV6_ID = 7,\n\tCTA_PROTO_ICMPV6_TYPE = 8,\n\tCTA_PROTO_ICMPV6_CODE = 9,\n\t__CTA_PROTO_MAX = 10,\n};\n\nstruct iter_data {\n\tint (*iter)(struct nf_conn *, void *);\n\tvoid *data;\n\tstruct net *net;\n};\n\nstruct ct_iter_state {\n\tstruct seq_net_private p;\n\tstruct hlist_nulls_head *hash;\n\tunsigned int htable_size;\n\tunsigned int bucket;\n\tu_int64_t time_now;\n};\n\nenum nf_ct_sysctl_index {\n\tNF_SYSCTL_CT_MAX = 0,\n\tNF_SYSCTL_CT_COUNT = 1,\n\tNF_SYSCTL_CT_BUCKETS = 2,\n\tNF_SYSCTL_CT_CHECKSUM = 3,\n\tNF_SYSCTL_CT_LOG_INVALID = 4,\n\tNF_SYSCTL_CT_EXPECT_MAX = 5,\n\tNF_SYSCTL_CT_ACCT = 6,\n\tNF_SYSCTL_CT_HELPER = 7,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_GENERIC = 8,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_SYN_SENT = 9,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_SYN_RECV = 10,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_ESTABLISHED = 11,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_FIN_WAIT = 12,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_CLOSE_WAIT = 13,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_LAST_ACK = 14,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_TIME_WAIT = 15,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_CLOSE = 16,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_RETRANS = 17,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_UNACK = 18,\n\tNF_SYSCTL_CT_PROTO_TCP_LOOSE = 19,\n\tNF_SYSCTL_CT_PROTO_TCP_LIBERAL = 20,\n\tNF_SYSCTL_CT_PROTO_TCP_MAX_RETRANS = 21,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_UDP = 22,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_UDP_STREAM = 23,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_ICMP = 24,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_ICMPV6 = 25,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_CLOSED = 26,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_COOKIE_WAIT = 27,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_COOKIE_ECHOED = 28,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_ESTABLISHED = 29,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_SHUTDOWN_SENT = 30,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_SHUTDOWN_RECD = 31,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_SHUTDOWN_ACK_SENT = 32,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_HEARTBEAT_SENT = 33,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_SCTP_HEARTBEAT_ACKED = 34,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_DCCP_REQUEST = 35,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_DCCP_RESPOND = 36,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_DCCP_PARTOPEN = 37,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_DCCP_OPEN = 38,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_DCCP_CLOSEREQ = 39,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_DCCP_CLOSING = 40,\n\tNF_SYSCTL_CT_PROTO_TIMEOUT_DCCP_TIMEWAIT = 41,\n\tNF_SYSCTL_CT_PROTO_DCCP_LOOSE = 42,\n\t__NF_SYSCTL_CT_LAST_SYSCTL = 43,\n};\n\nenum ip_conntrack_expect_events {\n\tIPEXP_NEW = 0,\n\tIPEXP_DESTROY = 1,\n};\n\nstruct ct_expect_iter_state {\n\tstruct seq_net_private p;\n\tunsigned int bucket;\n};\n\nstruct nf_ct_ext_type {\n\tvoid (*destroy)(struct nf_conn *);\n\tenum nf_ct_ext_id id;\n\tu8 len;\n\tu8 align;\n};\n\nstruct nf_ct_helper_expectfn {\n\tstruct list_head head;\n\tconst char *name;\n\tvoid (*expectfn)(struct nf_conn *, struct nf_conntrack_expect *);\n};\n\nstruct nf_conntrack_nat_helper {\n\tstruct list_head list;\n\tchar mod_name[16];\n\tstruct module *module;\n};\n\nstruct nf_conntrack_net {\n\tunsigned int users4;\n\tunsigned int users6;\n\tunsigned int users_bridge;\n};\n\nstruct nf_ct_bridge_info {\n\tstruct nf_hook_ops *ops;\n\tunsigned int ops_size;\n\tstruct module *me;\n};\n\nstruct nf_ct_tcp_flags {\n\t__u8 flags;\n\t__u8 mask;\n};\n\nenum {\n\tTCP_FLAG_CWR = 32768,\n\tTCP_FLAG_ECE = 16384,\n\tTCP_FLAG_URG = 8192,\n\tTCP_FLAG_ACK = 4096,\n\tTCP_FLAG_PSH = 2048,\n\tTCP_FLAG_RST = 1024,\n\tTCP_FLAG_SYN = 512,\n\tTCP_FLAG_FIN = 256,\n\tTCP_RESERVED_BITS = 15,\n\tTCP_DATA_OFFSET = 240,\n};\n\nstruct nf_conn_synproxy {\n\tu32 isn;\n\tu32 its;\n\tu32 tsoff;\n};\n\nenum tcp_bit_set {\n\tTCP_SYN_SET = 0,\n\tTCP_SYNACK_SET = 1,\n\tTCP_FIN_SET = 2,\n\tTCP_ACK_SET = 3,\n\tTCP_RST_SET = 4,\n\tTCP_NONE_SET = 5,\n};\n\nenum ctattr_protoinfo {\n\tCTA_PROTOINFO_UNSPEC = 0,\n\tCTA_PROTOINFO_TCP = 1,\n\tCTA_PROTOINFO_DCCP = 2,\n\tCTA_PROTOINFO_SCTP = 3,\n\t__CTA_PROTOINFO_MAX = 4,\n};\n\nenum ctattr_protoinfo_tcp {\n\tCTA_PROTOINFO_TCP_UNSPEC = 0,\n\tCTA_PROTOINFO_TCP_STATE = 1,\n\tCTA_PROTOINFO_TCP_WSCALE_ORIGINAL = 2,\n\tCTA_PROTOINFO_TCP_WSCALE_REPLY = 3,\n\tCTA_PROTOINFO_TCP_FLAGS_ORIGINAL = 4,\n\tCTA_PROTOINFO_TCP_FLAGS_REPLY = 5,\n\t__CTA_PROTOINFO_TCP_MAX = 6,\n};\n\nstruct tcp_sack_block_wire {\n\t__be32 start_seq;\n\t__be32 end_seq;\n};\n\nstruct nf_ct_seqadj {\n\tu32 correction_pos;\n\ts32 offset_before;\n\ts32 offset_after;\n};\n\nstruct nf_conn_seqadj {\n\tstruct nf_ct_seqadj seq[2];\n};\n\nstruct icmpv6_echo {\n\t__be16 identifier;\n\t__be16 sequence;\n};\n\nstruct icmpv6_nd_advt {\n\t__u32 reserved: 5;\n\t__u32 override: 1;\n\t__u32 solicited: 1;\n\t__u32 router: 1;\n\t__u32 reserved2: 24;\n};\n\nstruct icmpv6_nd_ra {\n\t__u8 hop_limit;\n\t__u8 reserved: 3;\n\t__u8 router_pref: 2;\n\t__u8 home_agent: 1;\n\t__u8 other: 1;\n\t__u8 managed: 1;\n\t__be16 rt_lifetime;\n};\n\nstruct icmp6hdr {\n\t__u8 icmp6_type;\n\t__u8 icmp6_code;\n\t__sum16 icmp6_cksum;\n\tunion {\n\t\t__be32 un_data32[1];\n\t\t__be16 un_data16[2];\n\t\t__u8 un_data8[4];\n\t\tstruct icmpv6_echo u_echo;\n\t\tstruct icmpv6_nd_advt u_nd_advt;\n\t\tstruct icmpv6_nd_ra u_nd_ra;\n\t} icmp6_dataun;\n};\n\nenum ct_dccp_roles {\n\tCT_DCCP_ROLE_CLIENT = 0,\n\tCT_DCCP_ROLE_SERVER = 1,\n\t__CT_DCCP_ROLE_MAX = 2,\n};\n\nstruct dccp_hdr_ext {\n\t__be32 dccph_seq_low;\n};\n\nstruct dccp_hdr_ack_bits {\n\t__be16 dccph_reserved1;\n\t__be16 dccph_ack_nr_high;\n\t__be32 dccph_ack_nr_low;\n};\n\nenum dccp_pkt_type {\n\tDCCP_PKT_REQUEST = 0,\n\tDCCP_PKT_RESPONSE = 1,\n\tDCCP_PKT_DATA = 2,\n\tDCCP_PKT_ACK = 3,\n\tDCCP_PKT_DATAACK = 4,\n\tDCCP_PKT_CLOSEREQ = 5,\n\tDCCP_PKT_CLOSE = 6,\n\tDCCP_PKT_RESET = 7,\n\tDCCP_PKT_SYNC = 8,\n\tDCCP_PKT_SYNCACK = 9,\n\tDCCP_PKT_INVALID = 10,\n};\n\nenum ctattr_protoinfo_dccp {\n\tCTA_PROTOINFO_DCCP_UNSPEC = 0,\n\tCTA_PROTOINFO_DCCP_STATE = 1,\n\tCTA_PROTOINFO_DCCP_ROLE = 2,\n\tCTA_PROTOINFO_DCCP_HANDSHAKE_SEQ = 3,\n\tCTA_PROTOINFO_DCCP_PAD = 4,\n\t__CTA_PROTOINFO_DCCP_MAX = 5,\n};\n\nenum {\n\tSCTP_CHUNK_FLAG_T = 1,\n};\n\nenum {\n\tSCTP_MIB_NUM = 0,\n\tSCTP_MIB_CURRESTAB = 1,\n\tSCTP_MIB_ACTIVEESTABS = 2,\n\tSCTP_MIB_PASSIVEESTABS = 3,\n\tSCTP_MIB_ABORTEDS = 4,\n\tSCTP_MIB_SHUTDOWNS = 5,\n\tSCTP_MIB_OUTOFBLUES = 6,\n\tSCTP_MIB_CHECKSUMERRORS = 7,\n\tSCTP_MIB_OUTCTRLCHUNKS = 8,\n\tSCTP_MIB_OUTORDERCHUNKS = 9,\n\tSCTP_MIB_OUTUNORDERCHUNKS = 10,\n\tSCTP_MIB_INCTRLCHUNKS = 11,\n\tSCTP_MIB_INORDERCHUNKS = 12,\n\tSCTP_MIB_INUNORDERCHUNKS = 13,\n\tSCTP_MIB_FRAGUSRMSGS = 14,\n\tSCTP_MIB_REASMUSRMSGS = 15,\n\tSCTP_MIB_OUTSCTPPACKS = 16,\n\tSCTP_MIB_INSCTPPACKS = 17,\n\tSCTP_MIB_T1_INIT_EXPIREDS = 18,\n\tSCTP_MIB_T1_COOKIE_EXPIREDS = 19,\n\tSCTP_MIB_T2_SHUTDOWN_EXPIREDS = 20,\n\tSCTP_MIB_T3_RTX_EXPIREDS = 21,\n\tSCTP_MIB_T4_RTO_EXPIREDS = 22,\n\tSCTP_MIB_T5_SHUTDOWN_GUARD_EXPIREDS = 23,\n\tSCTP_MIB_DELAY_SACK_EXPIREDS = 24,\n\tSCTP_MIB_AUTOCLOSE_EXPIREDS = 25,\n\tSCTP_MIB_T1_RETRANSMITS = 26,\n\tSCTP_MIB_T3_RETRANSMITS = 27,\n\tSCTP_MIB_PMTUD_RETRANSMITS = 28,\n\tSCTP_MIB_FAST_RETRANSMITS = 29,\n\tSCTP_MIB_IN_PKT_SOFTIRQ = 30,\n\tSCTP_MIB_IN_PKT_BACKLOG = 31,\n\tSCTP_MIB_IN_PKT_DISCARDS = 32,\n\tSCTP_MIB_IN_DATA_CHUNK_DISCARDS = 33,\n\t__SCTP_MIB_MAX = 34,\n};\n\nenum ctattr_protoinfo_sctp {\n\tCTA_PROTOINFO_SCTP_UNSPEC = 0,\n\tCTA_PROTOINFO_SCTP_STATE = 1,\n\tCTA_PROTOINFO_SCTP_VTAG_ORIGINAL = 2,\n\tCTA_PROTOINFO_SCTP_VTAG_REPLY = 3,\n\t__CTA_PROTOINFO_SCTP_MAX = 4,\n};\n\nenum cntl_msg_types {\n\tIPCTNL_MSG_CT_NEW = 0,\n\tIPCTNL_MSG_CT_GET = 1,\n\tIPCTNL_MSG_CT_DELETE = 2,\n\tIPCTNL_MSG_CT_GET_CTRZERO = 3,\n\tIPCTNL_MSG_CT_GET_STATS_CPU = 4,\n\tIPCTNL_MSG_CT_GET_STATS = 5,\n\tIPCTNL_MSG_CT_GET_DYING = 6,\n\tIPCTNL_MSG_CT_GET_UNCONFIRMED = 7,\n\tIPCTNL_MSG_MAX = 8,\n};\n\nenum ctnl_exp_msg_types {\n\tIPCTNL_MSG_EXP_NEW = 0,\n\tIPCTNL_MSG_EXP_GET = 1,\n\tIPCTNL_MSG_EXP_DELETE = 2,\n\tIPCTNL_MSG_EXP_GET_STATS_CPU = 3,\n\tIPCTNL_MSG_EXP_MAX = 4,\n};\n\nenum ctattr_type {\n\tCTA_UNSPEC = 0,\n\tCTA_TUPLE_ORIG = 1,\n\tCTA_TUPLE_REPLY = 2,\n\tCTA_STATUS = 3,\n\tCTA_PROTOINFO = 4,\n\tCTA_HELP = 5,\n\tCTA_NAT_SRC = 6,\n\tCTA_TIMEOUT = 7,\n\tCTA_MARK = 8,\n\tCTA_COUNTERS_ORIG = 9,\n\tCTA_COUNTERS_REPLY = 10,\n\tCTA_USE = 11,\n\tCTA_ID = 12,\n\tCTA_NAT_DST = 13,\n\tCTA_TUPLE_MASTER = 14,\n\tCTA_SEQ_ADJ_ORIG = 15,\n\tCTA_NAT_SEQ_ADJ_ORIG = 15,\n\tCTA_SEQ_ADJ_REPLY = 16,\n\tCTA_NAT_SEQ_ADJ_REPLY = 16,\n\tCTA_SECMARK = 17,\n\tCTA_ZONE = 18,\n\tCTA_SECCTX = 19,\n\tCTA_TIMESTAMP = 20,\n\tCTA_MARK_MASK = 21,\n\tCTA_LABELS = 22,\n\tCTA_LABELS_MASK = 23,\n\tCTA_SYNPROXY = 24,\n\tCTA_FILTER = 25,\n\t__CTA_MAX = 26,\n};\n\nenum ctattr_tuple {\n\tCTA_TUPLE_UNSPEC = 0,\n\tCTA_TUPLE_IP = 1,\n\tCTA_TUPLE_PROTO = 2,\n\tCTA_TUPLE_ZONE = 3,\n\t__CTA_TUPLE_MAX = 4,\n};\n\nenum ctattr_ip {\n\tCTA_IP_UNSPEC = 0,\n\tCTA_IP_V4_SRC = 1,\n\tCTA_IP_V4_DST = 2,\n\tCTA_IP_V6_SRC = 3,\n\tCTA_IP_V6_DST = 4,\n\t__CTA_IP_MAX = 5,\n};\n\nenum ctattr_counters {\n\tCTA_COUNTERS_UNSPEC = 0,\n\tCTA_COUNTERS_PACKETS = 1,\n\tCTA_COUNTERS_BYTES = 2,\n\tCTA_COUNTERS32_PACKETS = 3,\n\tCTA_COUNTERS32_BYTES = 4,\n\tCTA_COUNTERS_PAD = 5,\n\t__CTA_COUNTERS_MAX = 6,\n};\n\nenum ctattr_tstamp {\n\tCTA_TIMESTAMP_UNSPEC = 0,\n\tCTA_TIMESTAMP_START = 1,\n\tCTA_TIMESTAMP_STOP = 2,\n\tCTA_TIMESTAMP_PAD = 3,\n\t__CTA_TIMESTAMP_MAX = 4,\n};\n\nenum ctattr_seqadj {\n\tCTA_SEQADJ_UNSPEC = 0,\n\tCTA_SEQADJ_CORRECTION_POS = 1,\n\tCTA_SEQADJ_OFFSET_BEFORE = 2,\n\tCTA_SEQADJ_OFFSET_AFTER = 3,\n\t__CTA_SEQADJ_MAX = 4,\n};\n\nenum ctattr_synproxy {\n\tCTA_SYNPROXY_UNSPEC = 0,\n\tCTA_SYNPROXY_ISN = 1,\n\tCTA_SYNPROXY_ITS = 2,\n\tCTA_SYNPROXY_TSOFF = 3,\n\t__CTA_SYNPROXY_MAX = 4,\n};\n\nenum ctattr_expect {\n\tCTA_EXPECT_UNSPEC = 0,\n\tCTA_EXPECT_MASTER = 1,\n\tCTA_EXPECT_TUPLE = 2,\n\tCTA_EXPECT_MASK = 3,\n\tCTA_EXPECT_TIMEOUT = 4,\n\tCTA_EXPECT_ID = 5,\n\tCTA_EXPECT_HELP_NAME = 6,\n\tCTA_EXPECT_ZONE = 7,\n\tCTA_EXPECT_FLAGS = 8,\n\tCTA_EXPECT_CLASS = 9,\n\tCTA_EXPECT_NAT = 10,\n\tCTA_EXPECT_FN = 11,\n\t__CTA_EXPECT_MAX = 12,\n};\n\nenum ctattr_expect_nat {\n\tCTA_EXPECT_NAT_UNSPEC = 0,\n\tCTA_EXPECT_NAT_DIR = 1,\n\tCTA_EXPECT_NAT_TUPLE = 2,\n\t__CTA_EXPECT_NAT_MAX = 3,\n};\n\nenum ctattr_help {\n\tCTA_HELP_UNSPEC = 0,\n\tCTA_HELP_NAME = 1,\n\tCTA_HELP_INFO = 2,\n\t__CTA_HELP_MAX = 3,\n};\n\nenum ctattr_secctx {\n\tCTA_SECCTX_UNSPEC = 0,\n\tCTA_SECCTX_NAME = 1,\n\t__CTA_SECCTX_MAX = 2,\n};\n\nenum ctattr_stats_cpu {\n\tCTA_STATS_UNSPEC = 0,\n\tCTA_STATS_SEARCHED = 1,\n\tCTA_STATS_FOUND = 2,\n\tCTA_STATS_NEW = 3,\n\tCTA_STATS_INVALID = 4,\n\tCTA_STATS_IGNORE = 5,\n\tCTA_STATS_DELETE = 6,\n\tCTA_STATS_DELETE_LIST = 7,\n\tCTA_STATS_INSERT = 8,\n\tCTA_STATS_INSERT_FAILED = 9,\n\tCTA_STATS_DROP = 10,\n\tCTA_STATS_EARLY_DROP = 11,\n\tCTA_STATS_ERROR = 12,\n\tCTA_STATS_SEARCH_RESTART = 13,\n\t__CTA_STATS_MAX = 14,\n};\n\nenum ctattr_stats_global {\n\tCTA_STATS_GLOBAL_UNSPEC = 0,\n\tCTA_STATS_GLOBAL_ENTRIES = 1,\n\tCTA_STATS_GLOBAL_MAX_ENTRIES = 2,\n\t__CTA_STATS_GLOBAL_MAX = 3,\n};\n\nenum ctattr_expect_stats {\n\tCTA_STATS_EXP_UNSPEC = 0,\n\tCTA_STATS_EXP_NEW = 1,\n\tCTA_STATS_EXP_CREATE = 2,\n\tCTA_STATS_EXP_DELETE = 3,\n\t__CTA_STATS_EXP_MAX = 4,\n};\n\nenum ctattr_filter {\n\tCTA_FILTER_UNSPEC = 0,\n\tCTA_FILTER_ORIG_FLAGS = 1,\n\tCTA_FILTER_REPLY_FLAGS = 2,\n\t__CTA_FILTER_MAX = 3,\n};\n\nstruct ctnetlink_filter {\n\tu_int32_t cta_flags;\n\tu8 family;\n\tu_int32_t orig_flags;\n\tu_int32_t reply_flags;\n\tstruct nf_conntrack_tuple orig;\n\tstruct nf_conntrack_tuple reply;\n\tstruct nf_conntrack_zone zone;\n\tstruct {\n\t\tu_int32_t val;\n\t\tu_int32_t mask;\n\t} mark;\n};\n\nenum nf_ct_ftp_type {\n\tNF_CT_FTP_PORT = 0,\n\tNF_CT_FTP_PASV = 1,\n\tNF_CT_FTP_EPRT = 2,\n\tNF_CT_FTP_EPSV = 3,\n};\n\nstruct nf_ct_ftp_master {\n\tu_int32_t seq_aft_nl[4];\n\tu_int16_t seq_aft_nl_num[2];\n\tu_int16_t flags[2];\n};\n\nstruct ftp_search {\n\tconst char *pattern;\n\tsize_t plen;\n\tchar skip;\n\tchar term;\n\tenum nf_ct_ftp_type ftptype;\n\tint (*getnum)(const char *, size_t, struct nf_conntrack_man *, char, unsigned int *);\n};\n\nstruct nf_ct_sip_master {\n\tunsigned int register_cseq;\n\tunsigned int invite_cseq;\n\t__be16 forced_dport;\n};\n\nenum sip_expectation_classes {\n\tSIP_EXPECT_SIGNALLING = 0,\n\tSIP_EXPECT_AUDIO = 1,\n\tSIP_EXPECT_VIDEO = 2,\n\tSIP_EXPECT_IMAGE = 3,\n\t__SIP_EXPECT_MAX = 4,\n};\n\nstruct sdp_media_type {\n\tconst char *name;\n\tunsigned int len;\n\tenum sip_expectation_classes class;\n};\n\nstruct sip_handler {\n\tconst char *method;\n\tunsigned int len;\n\tint (*request)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *, unsigned int);\n\tint (*response)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *, unsigned int, unsigned int);\n};\n\nstruct sip_header {\n\tconst char *name;\n\tconst char *cname;\n\tconst char *search;\n\tunsigned int len;\n\tunsigned int clen;\n\tunsigned int slen;\n\tint (*match_len)(const struct nf_conn *, const char *, const char *, int *);\n};\n\nenum sip_header_types {\n\tSIP_HDR_CSEQ = 0,\n\tSIP_HDR_FROM = 1,\n\tSIP_HDR_TO = 2,\n\tSIP_HDR_CONTACT = 3,\n\tSIP_HDR_VIA_UDP = 4,\n\tSIP_HDR_VIA_TCP = 5,\n\tSIP_HDR_EXPIRES = 6,\n\tSIP_HDR_CONTENT_LENGTH = 7,\n\tSIP_HDR_CALL_ID = 8,\n};\n\nenum sdp_header_types {\n\tSDP_HDR_UNSPEC = 0,\n\tSDP_HDR_VERSION = 1,\n\tSDP_HDR_OWNER = 2,\n\tSDP_HDR_CONNECTION = 3,\n\tSDP_HDR_MEDIA = 4,\n};\n\nstruct nf_nat_sip_hooks {\n\tunsigned int (*msg)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *);\n\tvoid (*seq_adjust)(struct sk_buff *, unsigned int, s16);\n\tunsigned int (*expect)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *, struct nf_conntrack_expect *, unsigned int, unsigned int);\n\tunsigned int (*sdp_addr)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *, unsigned int, enum sdp_header_types, enum sdp_header_types, const union nf_inet_addr *);\n\tunsigned int (*sdp_port)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *, unsigned int, unsigned int, u_int16_t);\n\tunsigned int (*sdp_session)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *, unsigned int, const union nf_inet_addr *);\n\tunsigned int (*sdp_media)(struct sk_buff *, unsigned int, unsigned int, const char **, unsigned int *, struct nf_conntrack_expect *, struct nf_conntrack_expect *, unsigned int, unsigned int, union nf_inet_addr *);\n};\n\nunion nf_conntrack_nat_help {};\n\nstruct nf_conn_nat {\n\tunion nf_conntrack_nat_help help;\n\tint masq_index;\n};\n\nstruct nf_nat_lookup_hook_priv {\n\tstruct nf_hook_entries *entries;\n\tstruct callback_head callback_head;\n};\n\nstruct nf_nat_hooks_net {\n\tstruct nf_hook_ops *nat_hook_ops;\n\tunsigned int users;\n};\n\nstruct nat_net {\n\tstruct nf_nat_hooks_net nat_proto_net[13];\n};\n\nstruct nf_nat_proto_clean {\n\tu8 l3proto;\n\tu8 l4proto;\n};\n\nenum ctattr_nat {\n\tCTA_NAT_UNSPEC = 0,\n\tCTA_NAT_V4_MINIP = 1,\n\tCTA_NAT_V4_MAXIP = 2,\n\tCTA_NAT_PROTO = 3,\n\tCTA_NAT_V6_MINIP = 4,\n\tCTA_NAT_V6_MAXIP = 5,\n\t__CTA_NAT_MAX = 6,\n};\n\nenum ctattr_protonat {\n\tCTA_PROTONAT_UNSPEC = 0,\n\tCTA_PROTONAT_PORT_MIN = 1,\n\tCTA_PROTONAT_PORT_MAX = 2,\n\t__CTA_PROTONAT_MAX = 3,\n};\n\nstruct masq_dev_work {\n\tstruct work_struct work;\n\tstruct net *net;\n\tstruct in6_addr addr;\n\tint ifindex;\n};\n\nstruct xt_action_param;\n\nstruct xt_mtchk_param;\n\nstruct xt_mtdtor_param;\n\nstruct xt_match {\n\tstruct list_head list;\n\tconst char name[29];\n\tu_int8_t revision;\n\tbool (*match)(const struct sk_buff *, struct xt_action_param *);\n\tint (*checkentry)(const struct xt_mtchk_param *);\n\tvoid (*destroy)(const struct xt_mtdtor_param *);\n\tvoid (*compat_from_user)(void *, const void *);\n\tint (*compat_to_user)(void *, const void *);\n\tstruct module *me;\n\tconst char *table;\n\tunsigned int matchsize;\n\tunsigned int usersize;\n\tunsigned int compatsize;\n\tunsigned int hooks;\n\tshort unsigned int proto;\n\tshort unsigned int family;\n};\n\nstruct xt_entry_match {\n\tunion {\n\t\tstruct {\n\t\t\t__u16 match_size;\n\t\t\tchar name[29];\n\t\t\t__u8 revision;\n\t\t} user;\n\t\tstruct {\n\t\t\t__u16 match_size;\n\t\t\tstruct xt_match *match;\n\t\t} kernel;\n\t\t__u16 match_size;\n\t} u;\n\tunsigned char data[0];\n};\n\nstruct xt_tgchk_param;\n\nstruct xt_tgdtor_param;\n\nstruct xt_target {\n\tstruct list_head list;\n\tconst char name[29];\n\tu_int8_t revision;\n\tunsigned int (*target)(struct sk_buff *, const struct xt_action_param *);\n\tint (*checkentry)(const struct xt_tgchk_param *);\n\tvoid (*destroy)(const struct xt_tgdtor_param *);\n\tvoid (*compat_from_user)(void *, const void *);\n\tint (*compat_to_user)(void *, const void *);\n\tstruct module *me;\n\tconst char *table;\n\tunsigned int targetsize;\n\tunsigned int usersize;\n\tunsigned int compatsize;\n\tunsigned int hooks;\n\tshort unsigned int proto;\n\tshort unsigned int family;\n};\n\nstruct xt_entry_target {\n\tunion {\n\t\tstruct {\n\t\t\t__u16 target_size;\n\t\t\tchar name[29];\n\t\t\t__u8 revision;\n\t\t} user;\n\t\tstruct {\n\t\t\t__u16 target_size;\n\t\t\tstruct xt_target *target;\n\t\t} kernel;\n\t\t__u16 target_size;\n\t} u;\n\tunsigned char data[0];\n};\n\nstruct xt_standard_target {\n\tstruct xt_entry_target target;\n\tint verdict;\n};\n\nstruct xt_error_target {\n\tstruct xt_entry_target target;\n\tchar errorname[30];\n};\n\nstruct xt_counters {\n\t__u64 pcnt;\n\t__u64 bcnt;\n};\n\nstruct xt_counters_info {\n\tchar name[32];\n\tunsigned int num_counters;\n\tstruct xt_counters counters[0];\n};\n\nstruct xt_action_param {\n\tunion {\n\t\tconst struct xt_match *match;\n\t\tconst struct xt_target *target;\n\t};\n\tunion {\n\t\tconst void *matchinfo;\n\t\tconst void *targinfo;\n\t};\n\tconst struct nf_hook_state *state;\n\tint fragoff;\n\tunsigned int thoff;\n\tbool hotdrop;\n};\n\nstruct xt_mtchk_param {\n\tstruct net *net;\n\tconst char *table;\n\tconst void *entryinfo;\n\tconst struct xt_match *match;\n\tvoid *matchinfo;\n\tunsigned int hook_mask;\n\tu_int8_t family;\n\tbool nft_compat;\n};\n\nstruct xt_mtdtor_param {\n\tstruct net *net;\n\tconst struct xt_match *match;\n\tvoid *matchinfo;\n\tu_int8_t family;\n};\n\nstruct xt_tgchk_param {\n\tstruct net *net;\n\tconst char *table;\n\tconst void *entryinfo;\n\tconst struct xt_target *target;\n\tvoid *targinfo;\n\tunsigned int hook_mask;\n\tu_int8_t family;\n\tbool nft_compat;\n};\n\nstruct xt_tgdtor_param {\n\tstruct net *net;\n\tconst struct xt_target *target;\n\tvoid *targinfo;\n\tu_int8_t family;\n};\n\nstruct xt_percpu_counter_alloc_state {\n\tunsigned int off;\n\tconst char *mem;\n};\n\nstruct compat_xt_entry_match {\n\tunion {\n\t\tstruct {\n\t\t\tu_int16_t match_size;\n\t\t\tchar name[29];\n\t\t\tu_int8_t revision;\n\t\t} user;\n\t\tstruct {\n\t\t\tu_int16_t match_size;\n\t\t\tcompat_uptr_t match;\n\t\t} kernel;\n\t\tu_int16_t match_size;\n\t} u;\n\tunsigned char data[0];\n};\n\nstruct compat_xt_entry_target {\n\tunion {\n\t\tstruct {\n\t\t\tu_int16_t target_size;\n\t\t\tchar name[29];\n\t\t\tu_int8_t revision;\n\t\t} user;\n\t\tstruct {\n\t\t\tu_int16_t target_size;\n\t\t\tcompat_uptr_t target;\n\t\t} kernel;\n\t\tu_int16_t target_size;\n\t} u;\n\tunsigned char data[0];\n};\n\nstruct compat_xt_counters {\n\tcompat_u64 pcnt;\n\tcompat_u64 bcnt;\n};\n\nstruct compat_xt_counters_info {\n\tchar name[32];\n\tcompat_uint_t num_counters;\n\tstruct compat_xt_counters counters[0];\n} __attribute__((packed));\n\nstruct compat_delta {\n\tunsigned int offset;\n\tint delta;\n};\n\nstruct xt_af {\n\tstruct mutex mutex;\n\tstruct list_head match;\n\tstruct list_head target;\n\tstruct mutex compat_mutex;\n\tstruct compat_delta *compat_tab;\n\tunsigned int number;\n\tunsigned int cur;\n};\n\nstruct compat_xt_standard_target {\n\tstruct compat_xt_entry_target t;\n\tcompat_uint_t verdict;\n};\n\nstruct compat_xt_error_target {\n\tstruct compat_xt_entry_target t;\n\tchar errorname[30];\n};\n\nstruct nf_mttg_trav {\n\tstruct list_head *head;\n\tstruct list_head *curr;\n\tuint8_t class;\n};\n\nenum {\n\tMTTG_TRAV_INIT = 0,\n\tMTTG_TRAV_NFP_UNSPEC = 1,\n\tMTTG_TRAV_NFP_SPEC = 2,\n\tMTTG_TRAV_DONE = 3,\n};\n\nstruct xt_tcp {\n\t__u16 spts[2];\n\t__u16 dpts[2];\n\t__u8 option;\n\t__u8 flg_mask;\n\t__u8 flg_cmp;\n\t__u8 invflags;\n};\n\nstruct xt_udp {\n\t__u16 spts[2];\n\t__u16 dpts[2];\n\t__u8 invflags;\n};\n\nenum {\n\tCONNSECMARK_SAVE = 1,\n\tCONNSECMARK_RESTORE = 2,\n};\n\nstruct xt_connsecmark_target_info {\n\t__u8 mode;\n};\n\nstruct xt_nflog_info {\n\t__u32 len;\n\t__u16 group;\n\t__u16 threshold;\n\t__u16 flags;\n\t__u16 pad;\n\tchar prefix[64];\n};\n\nstruct xt_secmark_target_info {\n\t__u8 mode;\n\t__u32 secid;\n\tchar secctx[256];\n};\n\nstruct ipt_ip {\n\tstruct in_addr src;\n\tstruct in_addr dst;\n\tstruct in_addr smsk;\n\tstruct in_addr dmsk;\n\tchar iniface[16];\n\tchar outiface[16];\n\tunsigned char iniface_mask[16];\n\tunsigned char outiface_mask[16];\n\t__u16 proto;\n\t__u8 flags;\n\t__u8 invflags;\n};\n\nstruct ipt_entry {\n\tstruct ipt_ip ip;\n\tunsigned int nfcache;\n\t__u16 target_offset;\n\t__u16 next_offset;\n\tunsigned int comefrom;\n\tstruct xt_counters counters;\n\tunsigned char elems[0];\n};\n\nstruct ip6t_ip6 {\n\tstruct in6_addr src;\n\tstruct in6_addr dst;\n\tstruct in6_addr smsk;\n\tstruct in6_addr dmsk;\n\tchar iniface[16];\n\tchar outiface[16];\n\tunsigned char iniface_mask[16];\n\tunsigned char outiface_mask[16];\n\t__u16 proto;\n\t__u8 tos;\n\t__u8 flags;\n\t__u8 invflags;\n};\n\nstruct ip6t_entry {\n\tstruct ip6t_ip6 ipv6;\n\tunsigned int nfcache;\n\t__u16 target_offset;\n\t__u16 next_offset;\n\tunsigned int comefrom;\n\tstruct xt_counters counters;\n\tunsigned char elems[0];\n};\n\nstruct xt_tcpmss_info {\n\t__u16 mss;\n};\n\nstruct xt_bpf_info {\n\t__u16 bpf_program_num_elem;\n\tstruct sock_filter bpf_program[64];\n\tstruct bpf_prog *filter;\n};\n\nenum xt_bpf_modes {\n\tXT_BPF_MODE_BYTECODE = 0,\n\tXT_BPF_MODE_FD_PINNED = 1,\n\tXT_BPF_MODE_FD_ELF = 2,\n};\n\nstruct xt_bpf_info_v1 {\n\t__u16 mode;\n\t__u16 bpf_program_num_elem;\n\t__s32 fd;\n\tunion {\n\t\tstruct sock_filter bpf_program[64];\n\t\tchar path[512];\n\t};\n\tstruct bpf_prog *filter;\n};\n\nenum {\n\tXT_CONNTRACK_STATE = 1,\n\tXT_CONNTRACK_PROTO = 2,\n\tXT_CONNTRACK_ORIGSRC = 4,\n\tXT_CONNTRACK_ORIGDST = 8,\n\tXT_CONNTRACK_REPLSRC = 16,\n\tXT_CONNTRACK_REPLDST = 32,\n\tXT_CONNTRACK_STATUS = 64,\n\tXT_CONNTRACK_EXPIRES = 128,\n\tXT_CONNTRACK_ORIGSRC_PORT = 256,\n\tXT_CONNTRACK_ORIGDST_PORT = 512,\n\tXT_CONNTRACK_REPLSRC_PORT = 1024,\n\tXT_CONNTRACK_REPLDST_PORT = 2048,\n\tXT_CONNTRACK_DIRECTION = 4096,\n\tXT_CONNTRACK_STATE_ALIAS = 8192,\n};\n\nstruct xt_conntrack_mtinfo1 {\n\tunion nf_inet_addr origsrc_addr;\n\tunion nf_inet_addr origsrc_mask;\n\tunion nf_inet_addr origdst_addr;\n\tunion nf_inet_addr origdst_mask;\n\tunion nf_inet_addr replsrc_addr;\n\tunion nf_inet_addr replsrc_mask;\n\tunion nf_inet_addr repldst_addr;\n\tunion nf_inet_addr repldst_mask;\n\t__u32 expires_min;\n\t__u32 expires_max;\n\t__u16 l4proto;\n\t__be16 origsrc_port;\n\t__be16 origdst_port;\n\t__be16 replsrc_port;\n\t__be16 repldst_port;\n\t__u16 match_flags;\n\t__u16 invert_flags;\n\t__u8 state_mask;\n\t__u8 status_mask;\n};\n\nstruct xt_conntrack_mtinfo2 {\n\tunion nf_inet_addr origsrc_addr;\n\tunion nf_inet_addr origsrc_mask;\n\tunion nf_inet_addr origdst_addr;\n\tunion nf_inet_addr origdst_mask;\n\tunion nf_inet_addr replsrc_addr;\n\tunion nf_inet_addr replsrc_mask;\n\tunion nf_inet_addr repldst_addr;\n\tunion nf_inet_addr repldst_mask;\n\t__u32 expires_min;\n\t__u32 expires_max;\n\t__u16 l4proto;\n\t__be16 origsrc_port;\n\t__be16 origdst_port;\n\t__be16 replsrc_port;\n\t__be16 repldst_port;\n\t__u16 match_flags;\n\t__u16 invert_flags;\n\t__u16 state_mask;\n\t__u16 status_mask;\n};\n\nstruct xt_conntrack_mtinfo3 {\n\tunion nf_inet_addr origsrc_addr;\n\tunion nf_inet_addr origsrc_mask;\n\tunion nf_inet_addr origdst_addr;\n\tunion nf_inet_addr origdst_mask;\n\tunion nf_inet_addr replsrc_addr;\n\tunion nf_inet_addr replsrc_mask;\n\tunion nf_inet_addr repldst_addr;\n\tunion nf_inet_addr repldst_mask;\n\t__u32 expires_min;\n\t__u32 expires_max;\n\t__u16 l4proto;\n\t__u16 origsrc_port;\n\t__u16 origdst_port;\n\t__u16 replsrc_port;\n\t__u16 repldst_port;\n\t__u16 match_flags;\n\t__u16 invert_flags;\n\t__u16 state_mask;\n\t__u16 status_mask;\n\t__u16 origsrc_port_high;\n\t__u16 origdst_port_high;\n\t__u16 replsrc_port_high;\n\t__u16 repldst_port_high;\n};\n\nenum xt_policy_flags {\n\tXT_POLICY_MATCH_IN = 1,\n\tXT_POLICY_MATCH_OUT = 2,\n\tXT_POLICY_MATCH_NONE = 4,\n\tXT_POLICY_MATCH_STRICT = 8,\n};\n\nstruct xt_policy_spec {\n\t__u8 saddr: 1;\n\t__u8 daddr: 1;\n\t__u8 proto: 1;\n\t__u8 mode: 1;\n\t__u8 spi: 1;\n\t__u8 reqid: 1;\n};\n\nstruct xt_policy_elem {\n\tunion {\n\t\tstruct {\n\t\t\tunion nf_inet_addr saddr;\n\t\t\tunion nf_inet_addr smask;\n\t\t\tunion nf_inet_addr daddr;\n\t\t\tunion nf_inet_addr dmask;\n\t\t};\n\t};\n\t__be32 spi;\n\t__u32 reqid;\n\t__u8 proto;\n\t__u8 mode;\n\tstruct xt_policy_spec match;\n\tstruct xt_policy_spec invert;\n};\n\nstruct xt_policy_info {\n\tstruct xt_policy_elem pol[4];\n\t__u16 flags;\n\t__u16 len;\n};\n\nstruct xt_state_info {\n\tunsigned int statemask;\n};\n\nstruct ip_mreqn {\n\tstruct in_addr imr_multiaddr;\n\tstruct in_addr imr_address;\n\tint imr_ifindex;\n};\n\nstruct mr_table_ops {\n\tconst struct rhashtable_params *rht_params;\n\tvoid *cmparg_any;\n};\n\nstruct vif_device {\n\tstruct net_device *dev;\n\tlong unsigned int bytes_in;\n\tlong unsigned int bytes_out;\n\tlong unsigned int pkt_in;\n\tlong unsigned int pkt_out;\n\tlong unsigned int rate_limit;\n\tunsigned char threshold;\n\tshort unsigned int flags;\n\tint link;\n\tstruct netdev_phys_item_id dev_parent_id;\n\t__be32 local;\n\t__be32 remote;\n};\n\nstruct mr_table {\n\tstruct list_head list;\n\tpossible_net_t net;\n\tstruct mr_table_ops ops;\n\tu32 id;\n\tstruct sock *mroute_sk;\n\tstruct timer_list ipmr_expire_timer;\n\tstruct list_head mfc_unres_queue;\n\tstruct vif_device vif_table[32];\n\tstruct rhltable mfc_hash;\n\tstruct list_head mfc_cache_list;\n\tint maxvif;\n\tatomic_t cache_resolve_queue_len;\n\tbool mroute_do_assert;\n\tbool mroute_do_pim;\n\tbool mroute_do_wrvifwhole;\n\tint mroute_reg_vif_num;\n};\n\nstruct rtmsg {\n\tunsigned char rtm_family;\n\tunsigned char rtm_dst_len;\n\tunsigned char rtm_src_len;\n\tunsigned char rtm_tos;\n\tunsigned char rtm_table;\n\tunsigned char rtm_protocol;\n\tunsigned char rtm_scope;\n\tunsigned char rtm_type;\n\tunsigned int rtm_flags;\n};\n\nstruct rtvia {\n\t__kernel_sa_family_t rtvia_family;\n\t__u8 rtvia_addr[0];\n};\n\nstruct ip_sf_list;\n\nstruct ip_mc_list {\n\tstruct in_device *interface;\n\t__be32 multiaddr;\n\tunsigned int sfmode;\n\tstruct ip_sf_list *sources;\n\tstruct ip_sf_list *tomb;\n\tlong unsigned int sfcount[2];\n\tunion {\n\t\tstruct ip_mc_list *next;\n\t\tstruct ip_mc_list *next_rcu;\n\t};\n\tstruct ip_mc_list *next_hash;\n\tstruct timer_list timer;\n\tint users;\n\trefcount_t refcnt;\n\tspinlock_t lock;\n\tchar tm_running;\n\tchar reporter;\n\tchar unsolicit_count;\n\tchar loaded;\n\tunsigned char gsquery;\n\tunsigned char crcount;\n\tstruct callback_head rcu;\n};\n\nstruct ip_sf_socklist {\n\tunsigned int sl_max;\n\tunsigned int sl_count;\n\tstruct callback_head rcu;\n\t__be32 sl_addr[0];\n};\n\nstruct ip_mc_socklist {\n\tstruct ip_mc_socklist *next_rcu;\n\tstruct ip_mreqn multi;\n\tunsigned int sfmode;\n\tstruct ip_sf_socklist *sflist;\n\tstruct callback_head rcu;\n};\n\nstruct ip_sf_list {\n\tstruct ip_sf_list *sf_next;\n\tlong unsigned int sf_count[2];\n\t__be32 sf_inaddr;\n\tunsigned char sf_gsresp;\n\tunsigned char sf_oldin;\n\tunsigned char sf_crcount;\n};\n\nstruct ipv4_addr_key {\n\t__be32 addr;\n\tint vif;\n};\n\nstruct inetpeer_addr {\n\tunion {\n\t\tstruct ipv4_addr_key a4;\n\t\tstruct in6_addr a6;\n\t\tu32 key[4];\n\t};\n\t__u16 family;\n};\n\nstruct inet_peer {\n\tstruct rb_node rb_node;\n\tstruct inetpeer_addr daddr;\n\tu32 metrics[17];\n\tu32 rate_tokens;\n\tu32 n_redirects;\n\tlong unsigned int rate_last;\n\tunion {\n\t\tstruct {\n\t\t\tatomic_t rid;\n\t\t};\n\t\tstruct callback_head rcu;\n\t};\n\t__u32 dtime;\n\trefcount_t refcnt;\n};\n\nstruct fib_rt_info {\n\tstruct fib_info *fi;\n\tu32 tb_id;\n\t__be32 dst;\n\tint dst_len;\n\tu8 tos;\n\tu8 type;\n\tu8 offload: 1;\n\tu8 trap: 1;\n\tu8 unused: 6;\n};\n\nstruct uncached_list {\n\tspinlock_t lock;\n\tstruct list_head head;\n};\n\nstruct rt_cache_stat {\n\tunsigned int in_slow_tot;\n\tunsigned int in_slow_mc;\n\tunsigned int in_no_route;\n\tunsigned int in_brd;\n\tunsigned int in_martian_dst;\n\tunsigned int in_martian_src;\n\tunsigned int out_slow_tot;\n\tunsigned int out_slow_mc;\n};\n\nstruct fib_alias {\n\tstruct hlist_node fa_list;\n\tstruct fib_info *fa_info;\n\tu8 fa_tos;\n\tu8 fa_type;\n\tu8 fa_state;\n\tu8 fa_slen;\n\tu32 tb_id;\n\ts16 fa_default;\n\tu8 offload: 1;\n\tu8 trap: 1;\n\tu8 unused: 6;\n\tstruct callback_head rcu;\n};\n\nstruct fib_prop {\n\tint error;\n\tu8 scope;\n};\n\nstruct raw_hashinfo {\n\trwlock_t lock;\n\tstruct hlist_head ht[256];\n};\n\nenum ip_defrag_users {\n\tIP_DEFRAG_LOCAL_DELIVER = 0,\n\tIP_DEFRAG_CALL_RA_CHAIN = 1,\n\tIP_DEFRAG_CONNTRACK_IN = 2,\n\t__IP_DEFRAG_CONNTRACK_IN_END = 65537,\n\tIP_DEFRAG_CONNTRACK_OUT = 65538,\n\t__IP_DEFRAG_CONNTRACK_OUT_END = 131073,\n\tIP_DEFRAG_CONNTRACK_BRIDGE_IN = 131074,\n\t__IP_DEFRAG_CONNTRACK_BRIDGE_IN = 196609,\n\tIP_DEFRAG_VS_IN = 196610,\n\tIP_DEFRAG_VS_OUT = 196611,\n\tIP_DEFRAG_VS_FWD = 196612,\n\tIP_DEFRAG_AF_PACKET = 196613,\n\tIP_DEFRAG_MACVLAN = 196614,\n};\n\nenum {\n\tINET_FRAG_FIRST_IN = 1,\n\tINET_FRAG_LAST_IN = 2,\n\tINET_FRAG_COMPLETE = 4,\n\tINET_FRAG_HASH_DEAD = 8,\n};\n\nstruct ipq {\n\tstruct inet_frag_queue q;\n\tu8 ecn;\n\tu16 max_df_size;\n\tint iif;\n\tunsigned int rid;\n\tstruct inet_peer *peer;\n};\n\nstruct ip_options_data {\n\tstruct ip_options_rcu opt;\n\tchar data[40];\n};\n\nstruct ipcm_cookie {\n\tstruct sockcm_cookie sockc;\n\t__be32 addr;\n\tint oif;\n\tstruct ip_options_rcu *opt;\n\t__u8 ttl;\n\t__s16 tos;\n\tchar priority;\n\t__u16 gso_size;\n};\n\nstruct ip_fraglist_iter {\n\tstruct sk_buff *frag;\n\tstruct iphdr *iph;\n\tint offset;\n\tunsigned int hlen;\n};\n\nstruct ip_frag_state {\n\tbool DF;\n\tunsigned int hlen;\n\tunsigned int ll_rs;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\t__be16 not_last_frag;\n};\n\nstruct ip_reply_arg {\n\tstruct kvec iov[1];\n\tint flags;\n\t__wsum csum;\n\tint csumoffset;\n\tint bound_dev_if;\n\tu8 tos;\n\tkuid_t uid;\n};\n\nstruct ip_mreq_source {\n\t__be32 imr_multiaddr;\n\t__be32 imr_interface;\n\t__be32 imr_sourceaddr;\n};\n\nstruct ip_msfilter {\n\t__be32 imsf_multiaddr;\n\t__be32 imsf_interface;\n\t__u32 imsf_fmode;\n\t__u32 imsf_numsrc;\n\t__be32 imsf_slist[1];\n};\n\nstruct group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n};\n\nstruct group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n};\n\nstruct group_filter {\n\t__u32 gf_interface;\n\tstruct __kernel_sockaddr_storage gf_group;\n\t__u32 gf_fmode;\n\t__u32 gf_numsrc;\n\tstruct __kernel_sockaddr_storage gf_slist[1];\n};\n\nstruct in_pktinfo {\n\tint ipi_ifindex;\n\tstruct in_addr ipi_spec_dst;\n\tstruct in_addr ipi_addr;\n};\n\nstruct compat_group_req {\n\t__u32 gr_interface;\n\tstruct __kernel_sockaddr_storage gr_group;\n} __attribute__((packed));\n\nstruct compat_group_source_req {\n\t__u32 gsr_interface;\n\tstruct __kernel_sockaddr_storage gsr_group;\n\tstruct __kernel_sockaddr_storage gsr_source;\n} __attribute__((packed));\n\nstruct compat_group_filter {\n\t__u32 gf_interface;\n\tstruct __kernel_sockaddr_storage gf_group;\n\t__u32 gf_fmode;\n\t__u32 gf_numsrc;\n\tstruct __kernel_sockaddr_storage gf_slist[1];\n} __attribute__((packed));\n\nenum {\n\tBPFILTER_IPT_SO_SET_REPLACE = 64,\n\tBPFILTER_IPT_SO_SET_ADD_COUNTERS = 65,\n\tBPFILTER_IPT_SET_MAX = 66,\n};\n\nenum {\n\tBPFILTER_IPT_SO_GET_INFO = 64,\n\tBPFILTER_IPT_SO_GET_ENTRIES = 65,\n\tBPFILTER_IPT_SO_GET_REVISION_MATCH = 66,\n\tBPFILTER_IPT_SO_GET_REVISION_TARGET = 67,\n\tBPFILTER_IPT_GET_MAX = 68,\n};\n\nstruct bpfilter_umh_ops {\n\tstruct umh_info info;\n\tstruct mutex lock;\n\tint (*sockopt)(struct sock *, int, char *, unsigned int, bool);\n\tint (*start)();\n\tbool stop;\n};\n\nstruct inet_timewait_sock {\n\tstruct sock_common __tw_common;\n\t__u32 tw_mark;\n\tvolatile unsigned char tw_substate;\n\tunsigned char tw_rcv_wscale;\n\t__be16 tw_sport;\n\tunsigned int tw_kill: 1;\n\tunsigned int tw_transparent: 1;\n\tunsigned int tw_flowlabel: 20;\n\tunsigned int tw_pad: 2;\n\tunsigned int tw_tos: 8;\n\tu32 tw_txhash;\n\tu32 tw_priority;\n\tstruct timer_list tw_timer;\n\tstruct inet_bind_bucket *tw_tb;\n};\n\nstruct tcpvegas_info {\n\t__u32 tcpv_enabled;\n\t__u32 tcpv_rttcnt;\n\t__u32 tcpv_rtt;\n\t__u32 tcpv_minrtt;\n};\n\nstruct tcp_dctcp_info {\n\t__u16 dctcp_enabled;\n\t__u16 dctcp_ce_state;\n\t__u32 dctcp_alpha;\n\t__u32 dctcp_ab_ecn;\n\t__u32 dctcp_ab_tot;\n};\n\nstruct tcp_bbr_info {\n\t__u32 bbr_bw_lo;\n\t__u32 bbr_bw_hi;\n\t__u32 bbr_min_rtt;\n\t__u32 bbr_pacing_gain;\n\t__u32 bbr_cwnd_gain;\n};\n\nunion tcp_cc_info {\n\tstruct tcpvegas_info vegas;\n\tstruct tcp_dctcp_info dctcp;\n\tstruct tcp_bbr_info bbr;\n};\n\nenum {\n\tBPF_TCP_ESTABLISHED = 1,\n\tBPF_TCP_SYN_SENT = 2,\n\tBPF_TCP_SYN_RECV = 3,\n\tBPF_TCP_FIN_WAIT1 = 4,\n\tBPF_TCP_FIN_WAIT2 = 5,\n\tBPF_TCP_TIME_WAIT = 6,\n\tBPF_TCP_CLOSE = 7,\n\tBPF_TCP_CLOSE_WAIT = 8,\n\tBPF_TCP_LAST_ACK = 9,\n\tBPF_TCP_LISTEN = 10,\n\tBPF_TCP_CLOSING = 11,\n\tBPF_TCP_NEW_SYN_RECV = 12,\n\tBPF_TCP_MAX_STATES = 13,\n};\n\nenum inet_csk_ack_state_t {\n\tICSK_ACK_SCHED = 1,\n\tICSK_ACK_TIMER = 2,\n\tICSK_ACK_PUSHED = 4,\n\tICSK_ACK_PUSHED2 = 8,\n\tICSK_ACK_NOW = 16,\n};\n\nstruct tcp_repair_opt {\n\t__u32 opt_code;\n\t__u32 opt_val;\n};\n\nstruct tcp_repair_window {\n\t__u32 snd_wl1;\n\t__u32 snd_wnd;\n\t__u32 max_window;\n\t__u32 rcv_wnd;\n\t__u32 rcv_wup;\n};\n\nenum {\n\tTCP_NO_QUEUE = 0,\n\tTCP_RECV_QUEUE = 1,\n\tTCP_SEND_QUEUE = 2,\n\tTCP_QUEUES_NR = 3,\n};\n\nstruct tcp_info {\n\t__u8 tcpi_state;\n\t__u8 tcpi_ca_state;\n\t__u8 tcpi_retransmits;\n\t__u8 tcpi_probes;\n\t__u8 tcpi_backoff;\n\t__u8 tcpi_options;\n\t__u8 tcpi_snd_wscale: 4;\n\t__u8 tcpi_rcv_wscale: 4;\n\t__u8 tcpi_delivery_rate_app_limited: 1;\n\t__u8 tcpi_fastopen_client_fail: 2;\n\t__u32 tcpi_rto;\n\t__u32 tcpi_ato;\n\t__u32 tcpi_snd_mss;\n\t__u32 tcpi_rcv_mss;\n\t__u32 tcpi_unacked;\n\t__u32 tcpi_sacked;\n\t__u32 tcpi_lost;\n\t__u32 tcpi_retrans;\n\t__u32 tcpi_fackets;\n\t__u32 tcpi_last_data_sent;\n\t__u32 tcpi_last_ack_sent;\n\t__u32 tcpi_last_data_recv;\n\t__u32 tcpi_last_ack_recv;\n\t__u32 tcpi_pmtu;\n\t__u32 tcpi_rcv_ssthresh;\n\t__u32 tcpi_rtt;\n\t__u32 tcpi_rttvar;\n\t__u32 tcpi_snd_ssthresh;\n\t__u32 tcpi_snd_cwnd;\n\t__u32 tcpi_advmss;\n\t__u32 tcpi_reordering;\n\t__u32 tcpi_rcv_rtt;\n\t__u32 tcpi_rcv_space;\n\t__u32 tcpi_total_retrans;\n\t__u64 tcpi_pacing_rate;\n\t__u64 tcpi_max_pacing_rate;\n\t__u64 tcpi_bytes_acked;\n\t__u64 tcpi_bytes_received;\n\t__u32 tcpi_segs_out;\n\t__u32 tcpi_segs_in;\n\t__u32 tcpi_notsent_bytes;\n\t__u32 tcpi_min_rtt;\n\t__u32 tcpi_data_segs_in;\n\t__u32 tcpi_data_segs_out;\n\t__u64 tcpi_delivery_rate;\n\t__u64 tcpi_busy_time;\n\t__u64 tcpi_rwnd_limited;\n\t__u64 tcpi_sndbuf_limited;\n\t__u32 tcpi_delivered;\n\t__u32 tcpi_delivered_ce;\n\t__u64 tcpi_bytes_sent;\n\t__u64 tcpi_bytes_retrans;\n\t__u32 tcpi_dsack_dups;\n\t__u32 tcpi_reord_seen;\n\t__u32 tcpi_rcv_ooopack;\n\t__u32 tcpi_snd_wnd;\n};\n\nenum {\n\tTCP_NLA_PAD = 0,\n\tTCP_NLA_BUSY = 1,\n\tTCP_NLA_RWND_LIMITED = 2,\n\tTCP_NLA_SNDBUF_LIMITED = 3,\n\tTCP_NLA_DATA_SEGS_OUT = 4,\n\tTCP_NLA_TOTAL_RETRANS = 5,\n\tTCP_NLA_PACING_RATE = 6,\n\tTCP_NLA_DELIVERY_RATE = 7,\n\tTCP_NLA_SND_CWND = 8,\n\tTCP_NLA_REORDERING = 9,\n\tTCP_NLA_MIN_RTT = 10,\n\tTCP_NLA_RECUR_RETRANS = 11,\n\tTCP_NLA_DELIVERY_RATE_APP_LMT = 12,\n\tTCP_NLA_SNDQ_SIZE = 13,\n\tTCP_NLA_CA_STATE = 14,\n\tTCP_NLA_SND_SSTHRESH = 15,\n\tTCP_NLA_DELIVERED = 16,\n\tTCP_NLA_DELIVERED_CE = 17,\n\tTCP_NLA_BYTES_SENT = 18,\n\tTCP_NLA_BYTES_RETRANS = 19,\n\tTCP_NLA_DSACK_DUPS = 20,\n\tTCP_NLA_REORD_SEEN = 21,\n\tTCP_NLA_SRTT = 22,\n\tTCP_NLA_TIMEOUT_REHASH = 23,\n\tTCP_NLA_BYTES_NOTSENT = 24,\n};\n\nstruct tcp_zerocopy_receive {\n\t__u64 address;\n\t__u32 length;\n\t__u32 recv_skip_hint;\n\t__u32 inq;\n\t__s32 err;\n};\n\nstruct tcp_md5sig_pool {\n\tstruct ahash_request *md5_req;\n\tvoid *scratch;\n};\n\nenum tcp_chrono {\n\tTCP_CHRONO_UNSPEC = 0,\n\tTCP_CHRONO_BUSY = 1,\n\tTCP_CHRONO_RWND_LIMITED = 2,\n\tTCP_CHRONO_SNDBUF_LIMITED = 3,\n\t__TCP_CHRONO_MAX = 4,\n};\n\nstruct tcp_splice_state {\n\tstruct pipe_inode_info *pipe;\n\tsize_t len;\n\tunsigned int flags;\n};\n\nenum tcp_fastopen_client_fail {\n\tTFO_STATUS_UNSPEC = 0,\n\tTFO_COOKIE_UNAVAILABLE = 1,\n\tTFO_DATA_NOT_ACKED = 2,\n\tTFO_SYN_RETRANSMITTED = 3,\n};\n\nenum tcp_queue {\n\tTCP_FRAG_IN_WRITE_QUEUE = 0,\n\tTCP_FRAG_IN_RTX_QUEUE = 1,\n};\n\nenum tcp_ca_ack_event_flags {\n\tCA_ACK_SLOWPATH = 1,\n\tCA_ACK_WIN_UPDATE = 2,\n\tCA_ACK_ECE = 4,\n};\n\nstruct tcp_sacktag_state {\n\tu32 reord;\n\tu64 first_sackt;\n\tu64 last_sackt;\n\tstruct rate_sample *rate;\n\tint flag;\n\tunsigned int mss_now;\n};\n\nenum tsq_flags {\n\tTSQF_THROTTLED = 1,\n\tTSQF_QUEUED = 2,\n\tTCPF_TSQ_DEFERRED = 4,\n\tTCPF_WRITE_TIMER_DEFERRED = 8,\n\tTCPF_DELACK_TIMER_DEFERRED = 16,\n\tTCPF_MTU_REDUCED_DEFERRED = 32,\n};\n\nstruct mptcp_out_options {};\n\nstruct tcp_out_options {\n\tu16 options;\n\tu16 mss;\n\tu8 ws;\n\tu8 num_sack_blocks;\n\tu8 hash_size;\n\t__u8 *hash_location;\n\t__u32 tsval;\n\t__u32 tsecr;\n\tstruct tcp_fastopen_cookie *fastopen_cookie;\n\tstruct mptcp_out_options mptcp;\n};\n\nstruct tsq_tasklet {\n\tstruct tasklet_struct tasklet;\n\tstruct list_head head;\n};\n\nstruct tcp_md5sig {\n\tstruct __kernel_sockaddr_storage tcpm_addr;\n\t__u8 tcpm_flags;\n\t__u8 tcpm_prefixlen;\n\t__u16 tcpm_keylen;\n\tint tcpm_ifindex;\n\t__u8 tcpm_key[80];\n};\n\nstruct tcp_timewait_sock {\n\tstruct inet_timewait_sock tw_sk;\n\tu32 tw_rcv_wnd;\n\tu32 tw_ts_offset;\n\tu32 tw_ts_recent;\n\tu32 tw_last_oow_ack_time;\n\tint tw_ts_recent_stamp;\n\tu32 tw_tx_delay;\n\tstruct tcp_md5sig_key *tw_md5_key;\n};\n\nenum tcp_tw_status {\n\tTCP_TW_SUCCESS = 0,\n\tTCP_TW_RST = 1,\n\tTCP_TW_ACK = 2,\n\tTCP_TW_SYN = 3,\n};\n\nstruct tcp4_pseudohdr {\n\t__be32 saddr;\n\t__be32 daddr;\n\t__u8 pad;\n\t__u8 protocol;\n\t__be16 len;\n};\n\nenum tcp_seq_states {\n\tTCP_SEQ_STATE_LISTENING = 0,\n\tTCP_SEQ_STATE_ESTABLISHED = 1,\n};\n\nstruct tcp_seq_afinfo {\n\tsa_family_t family;\n};\n\nstruct tcp_iter_state {\n\tstruct seq_net_private p;\n\tenum tcp_seq_states state;\n\tstruct sock *syn_wait_sk;\n\tint bucket;\n\tint offset;\n\tint sbucket;\n\tint num;\n\tloff_t last_pos;\n};\n\nenum tcp_metric_index {\n\tTCP_METRIC_RTT = 0,\n\tTCP_METRIC_RTTVAR = 1,\n\tTCP_METRIC_SSTHRESH = 2,\n\tTCP_METRIC_CWND = 3,\n\tTCP_METRIC_REORDERING = 4,\n\tTCP_METRIC_RTT_US = 5,\n\tTCP_METRIC_RTTVAR_US = 6,\n\t__TCP_METRIC_MAX = 7,\n};\n\nenum {\n\tTCP_METRICS_ATTR_UNSPEC = 0,\n\tTCP_METRICS_ATTR_ADDR_IPV4 = 1,\n\tTCP_METRICS_ATTR_ADDR_IPV6 = 2,\n\tTCP_METRICS_ATTR_AGE = 3,\n\tTCP_METRICS_ATTR_TW_TSVAL = 4,\n\tTCP_METRICS_ATTR_TW_TS_STAMP = 5,\n\tTCP_METRICS_ATTR_VALS = 6,\n\tTCP_METRICS_ATTR_FOPEN_MSS = 7,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROPS = 8,\n\tTCP_METRICS_ATTR_FOPEN_SYN_DROP_TS = 9,\n\tTCP_METRICS_ATTR_FOPEN_COOKIE = 10,\n\tTCP_METRICS_ATTR_SADDR_IPV4 = 11,\n\tTCP_METRICS_ATTR_SADDR_IPV6 = 12,\n\tTCP_METRICS_ATTR_PAD = 13,\n\t__TCP_METRICS_ATTR_MAX = 14,\n};\n\nenum {\n\tTCP_METRICS_CMD_UNSPEC = 0,\n\tTCP_METRICS_CMD_GET = 1,\n\tTCP_METRICS_CMD_DEL = 2,\n\t__TCP_METRICS_CMD_MAX = 3,\n};\n\nstruct tcp_fastopen_metrics {\n\tu16 mss;\n\tu16 syn_loss: 10;\n\tu16 try_exp: 2;\n\tlong unsigned int last_syn_loss;\n\tstruct tcp_fastopen_cookie cookie;\n};\n\nstruct tcp_metrics_block {\n\tstruct tcp_metrics_block *tcpm_next;\n\tpossible_net_t tcpm_net;\n\tstruct inetpeer_addr tcpm_saddr;\n\tstruct inetpeer_addr tcpm_daddr;\n\tlong unsigned int tcpm_stamp;\n\tu32 tcpm_lock;\n\tu32 tcpm_vals[5];\n\tstruct tcp_fastopen_metrics tcpm_fastopen;\n\tstruct callback_head callback_head;\n};\n\nstruct tcpm_hash_bucket {\n\tstruct tcp_metrics_block *chain;\n};\n\nstruct icmp_filter {\n\t__u32 data;\n};\n\nstruct raw_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct raw_sock {\n\tstruct inet_sock inet;\n\tstruct icmp_filter filter;\n\tu32 ipmr_table;\n};\n\nstruct raw_frag_vec {\n\tstruct msghdr *msg;\n\tunion {\n\t\tstruct icmphdr icmph;\n\t\tchar c[1];\n\t} hdr;\n\tint hlen;\n};\n\nstruct udp_sock {\n\tstruct inet_sock inet;\n\tint pending;\n\tunsigned int corkflag;\n\t__u8 encap_type;\n\tunsigned char no_check6_tx: 1;\n\tunsigned char no_check6_rx: 1;\n\tunsigned char encap_enabled: 1;\n\tunsigned char gro_enabled: 1;\n\t__u16 len;\n\t__u16 gso_size;\n\t__u16 pcslen;\n\t__u16 pcrlen;\n\t__u8 pcflag;\n\t__u8 unused[3];\n\tint (*encap_rcv)(struct sock *, struct sk_buff *);\n\tint (*encap_err_lookup)(struct sock *, struct sk_buff *);\n\tvoid (*encap_destroy)(struct sock *);\n\tstruct sk_buff * (*gro_receive)(struct sock *, struct list_head *, struct sk_buff *);\n\tint (*gro_complete)(struct sock *, struct sk_buff *, int);\n\tstruct sk_buff_head reader_queue;\n\tint forward_deficit;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct udp_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\t__u16 cscov;\n\t__u8 partial_cov;\n};\n\nstruct udp_dev_scratch {\n\tu32 _tsize_state;\n\tu16 len;\n\tbool is_linear;\n\tbool csum_unnecessary;\n};\n\nstruct udp_seq_afinfo {\n\tsa_family_t family;\n\tstruct udp_table *udp_table;\n};\n\nstruct udp_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n};\n\nstruct inet_protosw {\n\tstruct list_head list;\n\tshort unsigned int type;\n\tshort unsigned int protocol;\n\tstruct proto *prot;\n\tconst struct proto_ops *ops;\n\tunsigned char flags;\n};\n\ntypedef struct sk_buff * (*gro_receive_sk_t)(struct sock *, struct list_head *, struct sk_buff *);\n\ntypedef struct sock * (*udp_lookup_t)(struct sk_buff *, __be16, __be16);\n\nstruct arpreq {\n\tstruct sockaddr arp_pa;\n\tstruct sockaddr arp_ha;\n\tint arp_flags;\n\tstruct sockaddr arp_netmask;\n\tchar arp_dev[16];\n};\n\ntypedef struct {\n\tchar ax25_call[7];\n} ax25_address;\n\nenum {\n\tAX25_VALUES_IPDEFMODE = 0,\n\tAX25_VALUES_AXDEFMODE = 1,\n\tAX25_VALUES_BACKOFF = 2,\n\tAX25_VALUES_CONMODE = 3,\n\tAX25_VALUES_WINDOW = 4,\n\tAX25_VALUES_EWINDOW = 5,\n\tAX25_VALUES_T1 = 6,\n\tAX25_VALUES_T2 = 7,\n\tAX25_VALUES_T3 = 8,\n\tAX25_VALUES_IDLE = 9,\n\tAX25_VALUES_N2 = 10,\n\tAX25_VALUES_PACLEN = 11,\n\tAX25_VALUES_PROTOCOL = 12,\n\tAX25_VALUES_DS_TIMEOUT = 13,\n\tAX25_MAX_VALUES = 14,\n};\n\nstruct ax25_dev {\n\tstruct ax25_dev *next;\n\tstruct net_device *dev;\n\tstruct net_device *forward;\n\tstruct ctl_table_header *sysheader;\n\tint values[14];\n};\n\ntypedef struct ax25_dev ax25_dev;\n\nenum {\n\tXFRM_LOOKUP_ICMP = 1,\n\tXFRM_LOOKUP_QUEUE = 2,\n\tXFRM_LOOKUP_KEEP_DST_REF = 4,\n};\n\nstruct pingv6_ops {\n\tint (*ipv6_recv_error)(struct sock *, struct msghdr *, int, int *);\n\tvoid (*ip6_datagram_recv_common_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tvoid (*ip6_datagram_recv_specific_ctl)(struct sock *, struct msghdr *, struct sk_buff *);\n\tint (*icmpv6_err_convert)(u8, u8, int *);\n\tvoid (*ipv6_icmp_error)(struct sock *, struct sk_buff *, int, __be16, u32, u8 *);\n\tint (*ipv6_chk_addr)(struct net *, const struct in6_addr *, const struct net_device *, int);\n};\n\nstruct icmp_bxm {\n\tstruct sk_buff *skb;\n\tint offset;\n\tint data_len;\n\tstruct {\n\t\tstruct icmphdr icmph;\n\t\t__be32 times[3];\n\t} data;\n\tint head_len;\n\tstruct ip_options_data replyopts;\n};\n\nstruct icmp_control {\n\tbool (*handler)(struct sk_buff *);\n\tshort int error;\n};\n\nstruct ifaddrmsg {\n\t__u8 ifa_family;\n\t__u8 ifa_prefixlen;\n\t__u8 ifa_flags;\n\t__u8 ifa_scope;\n\t__u32 ifa_index;\n};\n\nenum {\n\tIFA_UNSPEC = 0,\n\tIFA_ADDRESS = 1,\n\tIFA_LOCAL = 2,\n\tIFA_LABEL = 3,\n\tIFA_BROADCAST = 4,\n\tIFA_ANYCAST = 5,\n\tIFA_CACHEINFO = 6,\n\tIFA_MULTICAST = 7,\n\tIFA_FLAGS = 8,\n\tIFA_RT_PRIORITY = 9,\n\tIFA_TARGET_NETNSID = 10,\n\t__IFA_MAX = 11,\n};\n\nstruct ifa_cacheinfo {\n\t__u32 ifa_prefered;\n\t__u32 ifa_valid;\n\t__u32 cstamp;\n\t__u32 tstamp;\n};\n\nenum {\n\tIFLA_INET_UNSPEC = 0,\n\tIFLA_INET_CONF = 1,\n\t__IFLA_INET_MAX = 2,\n};\n\nstruct in_validator_info {\n\t__be32 ivi_addr;\n\tstruct in_device *ivi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct netconfmsg {\n\t__u8 ncm_family;\n};\n\nenum {\n\tNETCONFA_UNSPEC = 0,\n\tNETCONFA_IFINDEX = 1,\n\tNETCONFA_FORWARDING = 2,\n\tNETCONFA_RP_FILTER = 3,\n\tNETCONFA_MC_FORWARDING = 4,\n\tNETCONFA_PROXY_NEIGH = 5,\n\tNETCONFA_IGNORE_ROUTES_WITH_LINKDOWN = 6,\n\tNETCONFA_INPUT = 7,\n\tNETCONFA_BC_FORWARDING = 8,\n\t__NETCONFA_MAX = 9,\n};\n\nstruct inet_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n};\n\nstruct devinet_sysctl_table {\n\tstruct ctl_table_header *sysctl_header;\n\tstruct ctl_table devinet_vars[33];\n};\n\nstruct rtentry {\n\tlong unsigned int rt_pad1;\n\tstruct sockaddr rt_dst;\n\tstruct sockaddr rt_gateway;\n\tstruct sockaddr rt_genmask;\n\tshort unsigned int rt_flags;\n\tshort int rt_pad2;\n\tlong unsigned int rt_pad3;\n\tvoid *rt_pad4;\n\tshort int rt_metric;\n\tchar *rt_dev;\n\tlong unsigned int rt_mtu;\n\tlong unsigned int rt_window;\n\tshort unsigned int rt_irtt;\n};\n\nstruct compat_rtentry {\n\tu32 rt_pad1;\n\tstruct sockaddr rt_dst;\n\tstruct sockaddr rt_gateway;\n\tstruct sockaddr rt_genmask;\n\tshort unsigned int rt_flags;\n\tshort int rt_pad2;\n\tu32 rt_pad3;\n\tunsigned char rt_tos;\n\tunsigned char rt_class;\n\tshort int rt_pad4;\n\tshort int rt_metric;\n\tcompat_uptr_t rt_dev;\n\tu32 rt_mtu;\n\tu32 rt_window;\n\tshort unsigned int rt_irtt;\n};\n\nstruct igmphdr {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n};\n\nstruct igmpv3_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\t__be32 grec_mca;\n\t__be32 grec_src[0];\n};\n\nstruct igmpv3_report {\n\t__u8 type;\n\t__u8 resv1;\n\t__sum16 csum;\n\t__be16 resv2;\n\t__be16 ngrec;\n\tstruct igmpv3_grec grec[0];\n};\n\nstruct igmpv3_query {\n\t__u8 type;\n\t__u8 code;\n\t__sum16 csum;\n\t__be32 group;\n\t__u8 qrv: 3;\n\t__u8 suppress: 1;\n\t__u8 resv: 4;\n\t__u8 qqic;\n\t__be16 nsrcs;\n\t__be32 srcs[0];\n};\n\nstruct igmp_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *in_dev;\n};\n\nstruct igmp_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct in_device *idev;\n\tstruct ip_mc_list *im;\n};\n\nstruct fib_config {\n\tu8 fc_dst_len;\n\tu8 fc_tos;\n\tu8 fc_protocol;\n\tu8 fc_scope;\n\tu8 fc_type;\n\tu8 fc_gw_family;\n\tu32 fc_table;\n\t__be32 fc_dst;\n\tunion {\n\t\t__be32 fc_gw4;\n\t\tstruct in6_addr fc_gw6;\n\t};\n\tint fc_oif;\n\tu32 fc_flags;\n\tu32 fc_priority;\n\t__be32 fc_prefsrc;\n\tu32 fc_nh_id;\n\tstruct nlattr *fc_mx;\n\tstruct rtnexthop *fc_mp;\n\tint fc_mx_len;\n\tint fc_mp_len;\n\tu32 fc_flow;\n\tu32 fc_nlflags;\n\tstruct nl_info fc_nlinfo;\n\tstruct nlattr *fc_encap;\n\tu16 fc_encap_type;\n};\n\nstruct fib_result_nl {\n\t__be32 fl_addr;\n\tu32 fl_mark;\n\tunsigned char fl_tos;\n\tunsigned char fl_scope;\n\tunsigned char tb_id_in;\n\tunsigned char tb_id;\n\tunsigned char prefixlen;\n\tunsigned char nh_sel;\n\tunsigned char type;\n\tunsigned char scope;\n\tint err;\n};\n\nstruct fib_dump_filter {\n\tu32 table_id;\n\tbool filter_set;\n\tbool dump_routes;\n\tbool dump_exceptions;\n\tunsigned char protocol;\n\tunsigned char rt_type;\n\tunsigned int flags;\n\tstruct net_device *dev;\n};\n\nstruct fib_nh_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib_nh *fib_nh;\n};\n\nstruct fib_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tu32 dst;\n\tint dst_len;\n\tstruct fib_info *fi;\n\tu8 tos;\n\tu8 type;\n\tu32 tb_id;\n};\n\ntypedef unsigned int t_key;\n\nstruct key_vector {\n\tt_key key;\n\tunsigned char pos;\n\tunsigned char bits;\n\tunsigned char slen;\n\tunion {\n\t\tstruct hlist_head leaf;\n\t\tstruct key_vector *tnode[0];\n\t};\n};\n\nstruct tnode {\n\tstruct callback_head rcu;\n\tt_key empty_children;\n\tt_key full_children;\n\tstruct key_vector *parent;\n\tstruct key_vector kv[1];\n};\n\nstruct trie_stat {\n\tunsigned int totdepth;\n\tunsigned int maxdepth;\n\tunsigned int tnodes;\n\tunsigned int leaves;\n\tunsigned int nullpointers;\n\tunsigned int prefixes;\n\tunsigned int nodesizes[32];\n};\n\nstruct trie {\n\tstruct key_vector kv[1];\n};\n\nstruct fib_trie_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *tb;\n\tstruct key_vector *tnode;\n\tunsigned int index;\n\tunsigned int depth;\n};\n\nstruct fib_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib_table *main_tb;\n\tstruct key_vector *tnode;\n\tloff_t pos;\n\tt_key key;\n};\n\nstruct ipfrag_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t};\n\tstruct sk_buff *next_frag;\n\tint frag_run_len;\n};\n\nstruct ping_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tsa_family_t family;\n};\n\nstruct pingfakehdr {\n\tstruct icmphdr icmph;\n\tstruct msghdr *msg;\n\tsa_family_t family;\n\t__wsum wcheck;\n};\n\nstruct ping_table {\n\tstruct hlist_nulls_head hash[64];\n\trwlock_t lock;\n};\n\nenum lwtunnel_ip_t {\n\tLWTUNNEL_IP_UNSPEC = 0,\n\tLWTUNNEL_IP_ID = 1,\n\tLWTUNNEL_IP_DST = 2,\n\tLWTUNNEL_IP_SRC = 3,\n\tLWTUNNEL_IP_TTL = 4,\n\tLWTUNNEL_IP_TOS = 5,\n\tLWTUNNEL_IP_FLAGS = 6,\n\tLWTUNNEL_IP_PAD = 7,\n\tLWTUNNEL_IP_OPTS = 8,\n\t__LWTUNNEL_IP_MAX = 9,\n};\n\nenum lwtunnel_ip6_t {\n\tLWTUNNEL_IP6_UNSPEC = 0,\n\tLWTUNNEL_IP6_ID = 1,\n\tLWTUNNEL_IP6_DST = 2,\n\tLWTUNNEL_IP6_SRC = 3,\n\tLWTUNNEL_IP6_HOPLIMIT = 4,\n\tLWTUNNEL_IP6_TC = 5,\n\tLWTUNNEL_IP6_FLAGS = 6,\n\tLWTUNNEL_IP6_PAD = 7,\n\tLWTUNNEL_IP6_OPTS = 8,\n\t__LWTUNNEL_IP6_MAX = 9,\n};\n\nenum {\n\tLWTUNNEL_IP_OPTS_UNSPEC = 0,\n\tLWTUNNEL_IP_OPTS_GENEVE = 1,\n\tLWTUNNEL_IP_OPTS_VXLAN = 2,\n\tLWTUNNEL_IP_OPTS_ERSPAN = 3,\n\t__LWTUNNEL_IP_OPTS_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_GENEVE_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_GENEVE_CLASS = 1,\n\tLWTUNNEL_IP_OPT_GENEVE_TYPE = 2,\n\tLWTUNNEL_IP_OPT_GENEVE_DATA = 3,\n\t__LWTUNNEL_IP_OPT_GENEVE_MAX = 4,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_VXLAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_VXLAN_GBP = 1,\n\t__LWTUNNEL_IP_OPT_VXLAN_MAX = 2,\n};\n\nenum {\n\tLWTUNNEL_IP_OPT_ERSPAN_UNSPEC = 0,\n\tLWTUNNEL_IP_OPT_ERSPAN_VER = 1,\n\tLWTUNNEL_IP_OPT_ERSPAN_INDEX = 2,\n\tLWTUNNEL_IP_OPT_ERSPAN_DIR = 3,\n\tLWTUNNEL_IP_OPT_ERSPAN_HWID = 4,\n\t__LWTUNNEL_IP_OPT_ERSPAN_MAX = 5,\n};\n\nstruct ip6_tnl_encap_ops {\n\tsize_t (*encap_hlen)(struct ip_tunnel_encap *);\n\tint (*build_header)(struct sk_buff *, struct ip_tunnel_encap *, u8 *, struct flowi6 *);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n};\n\nstruct geneve_opt {\n\t__be16 opt_class;\n\tu8 type;\n\tu8 length: 5;\n\tu8 r3: 1;\n\tu8 r2: 1;\n\tu8 r1: 1;\n\tu8 opt_data[0];\n};\n\nstruct vxlan_metadata {\n\tu32 gbp;\n};\n\nstruct erspan_md2 {\n\t__be32 timestamp;\n\t__be16 sgt;\n\t__u8 hwid_upper: 2;\n\t__u8 ft: 5;\n\t__u8 p: 1;\n\t__u8 o: 1;\n\t__u8 gra: 2;\n\t__u8 dir: 1;\n\t__u8 hwid: 4;\n};\n\nstruct erspan_metadata {\n\tint version;\n\tunion {\n\t\t__be32 index;\n\t\tstruct erspan_md2 md2;\n\t} u;\n};\n\nstruct nhmsg {\n\tunsigned char nh_family;\n\tunsigned char nh_scope;\n\tunsigned char nh_protocol;\n\tunsigned char resvd;\n\tunsigned int nh_flags;\n};\n\nstruct nexthop_grp {\n\t__u32 id;\n\t__u8 weight;\n\t__u8 resvd1;\n\t__u16 resvd2;\n};\n\nenum {\n\tNEXTHOP_GRP_TYPE_MPATH = 0,\n\t__NEXTHOP_GRP_TYPE_MAX = 1,\n};\n\nenum {\n\tNHA_UNSPEC = 0,\n\tNHA_ID = 1,\n\tNHA_GROUP = 2,\n\tNHA_GROUP_TYPE = 3,\n\tNHA_BLACKHOLE = 4,\n\tNHA_OIF = 5,\n\tNHA_GATEWAY = 6,\n\tNHA_ENCAP_TYPE = 7,\n\tNHA_ENCAP = 8,\n\tNHA_GROUPS = 9,\n\tNHA_MASTER = 10,\n\tNHA_FDB = 11,\n\t__NHA_MAX = 12,\n};\n\nstruct nh_config {\n\tu32 nh_id;\n\tu8 nh_family;\n\tu8 nh_protocol;\n\tu8 nh_blackhole;\n\tu8 nh_fdb;\n\tu32 nh_flags;\n\tint nh_ifindex;\n\tstruct net_device *dev;\n\tunion {\n\t\t__be32 ipv4;\n\t\tstruct in6_addr ipv6;\n\t} gw;\n\tstruct nlattr *nh_grp;\n\tu16 nh_grp_type;\n\tstruct nlattr *nh_encap;\n\tu16 nh_encap_type;\n\tu32 nlflags;\n\tstruct nl_info nlinfo;\n};\n\nenum nexthop_event_type {\n\tNEXTHOP_EVENT_ADD = 0,\n\tNEXTHOP_EVENT_DEL = 1,\n};\n\nenum tunnel_encap_types {\n\tTUNNEL_ENCAP_NONE = 0,\n\tTUNNEL_ENCAP_FOU = 1,\n\tTUNNEL_ENCAP_GUE = 2,\n\tTUNNEL_ENCAP_MPLS = 3,\n};\n\nstruct ip_tunnel_prl_entry {\n\tstruct ip_tunnel_prl_entry *next;\n\t__be32 addr;\n\tu16 flags;\n\tstruct callback_head callback_head;\n};\n\nstruct ip_tunnel {\n\tstruct ip_tunnel *next;\n\tstruct hlist_node hash_node;\n\tstruct net_device *dev;\n\tstruct net *net;\n\tlong unsigned int err_time;\n\tint err_count;\n\tu32 i_seqno;\n\tu32 o_seqno;\n\tint tun_hlen;\n\tu32 index;\n\tu8 erspan_ver;\n\tu8 dir;\n\tu16 hwid;\n\tstruct dst_cache dst_cache;\n\tstruct ip_tunnel_parm parms;\n\tint mlink;\n\tint encap_hlen;\n\tint hlen;\n\tstruct ip_tunnel_encap encap;\n\tstruct ip_tunnel_prl_entry *prl;\n\tunsigned int prl_count;\n\tunsigned int ip_tnl_net_id;\n\tstruct gro_cells gro_cells;\n\t__u32 fwmark;\n\tbool collect_md;\n\tbool ignore_df;\n};\n\nstruct tnl_ptk_info {\n\t__be16 flags;\n\t__be16 proto;\n\t__be32 key;\n\t__be32 seq;\n\tint hdr_len;\n};\n\nstruct ip_tunnel_net {\n\tstruct net_device *fb_tunnel_dev;\n\tstruct rtnl_link_ops *rtnl_link_ops;\n\tstruct hlist_head tunnels[128];\n\tstruct ip_tunnel *collect_md_tun;\n\tint type;\n};\n\nstruct snmp_mib {\n\tconst char *name;\n\tint entry;\n};\n\nstruct fib4_rule {\n\tstruct fib_rule common;\n\tu8 dst_len;\n\tu8 src_len;\n\tu8 tos;\n\t__be32 src;\n\t__be32 srcmask;\n\t__be32 dst;\n\t__be32 dstmask;\n};\n\nenum {\n\tPIM_TYPE_HELLO = 0,\n\tPIM_TYPE_REGISTER = 1,\n\tPIM_TYPE_REGISTER_STOP = 2,\n\tPIM_TYPE_JOIN_PRUNE = 3,\n\tPIM_TYPE_BOOTSTRAP = 4,\n\tPIM_TYPE_ASSERT = 5,\n\tPIM_TYPE_GRAFT = 6,\n\tPIM_TYPE_GRAFT_ACK = 7,\n\tPIM_TYPE_CANDIDATE_RP_ADV = 8,\n};\n\nstruct pimreghdr {\n\t__u8 type;\n\t__u8 reserved;\n\t__be16 csum;\n\t__be32 flags;\n};\n\ntypedef short unsigned int vifi_t;\n\nstruct vifctl {\n\tvifi_t vifc_vifi;\n\tunsigned char vifc_flags;\n\tunsigned char vifc_threshold;\n\tunsigned int vifc_rate_limit;\n\tunion {\n\t\tstruct in_addr vifc_lcl_addr;\n\t\tint vifc_lcl_ifindex;\n\t};\n\tstruct in_addr vifc_rmt_addr;\n};\n\nstruct mfcctl {\n\tstruct in_addr mfcc_origin;\n\tstruct in_addr mfcc_mcastgrp;\n\tvifi_t mfcc_parent;\n\tunsigned char mfcc_ttls[32];\n\tunsigned int mfcc_pkt_cnt;\n\tunsigned int mfcc_byte_cnt;\n\tunsigned int mfcc_wrong_if;\n\tint mfcc_expire;\n};\n\nstruct sioc_sg_req {\n\tstruct in_addr src;\n\tstruct in_addr grp;\n\tlong unsigned int pktcnt;\n\tlong unsigned int bytecnt;\n\tlong unsigned int wrong_if;\n};\n\nstruct sioc_vif_req {\n\tvifi_t vifi;\n\tlong unsigned int icount;\n\tlong unsigned int ocount;\n\tlong unsigned int ibytes;\n\tlong unsigned int obytes;\n};\n\nstruct igmpmsg {\n\t__u32 unused1;\n\t__u32 unused2;\n\tunsigned char im_msgtype;\n\tunsigned char im_mbz;\n\tunsigned char im_vif;\n\tunsigned char unused3;\n\tstruct in_addr im_src;\n\tstruct in_addr im_dst;\n};\n\nenum {\n\tIPMRA_TABLE_UNSPEC = 0,\n\tIPMRA_TABLE_ID = 1,\n\tIPMRA_TABLE_CACHE_RES_QUEUE_LEN = 2,\n\tIPMRA_TABLE_MROUTE_REG_VIF_NUM = 3,\n\tIPMRA_TABLE_MROUTE_DO_ASSERT = 4,\n\tIPMRA_TABLE_MROUTE_DO_PIM = 5,\n\tIPMRA_TABLE_VIFS = 6,\n\tIPMRA_TABLE_MROUTE_DO_WRVIFWHOLE = 7,\n\t__IPMRA_TABLE_MAX = 8,\n};\n\nenum {\n\tIPMRA_VIF_UNSPEC = 0,\n\tIPMRA_VIF = 1,\n\t__IPMRA_VIF_MAX = 2,\n};\n\nenum {\n\tIPMRA_VIFA_UNSPEC = 0,\n\tIPMRA_VIFA_IFINDEX = 1,\n\tIPMRA_VIFA_VIF_ID = 2,\n\tIPMRA_VIFA_FLAGS = 3,\n\tIPMRA_VIFA_BYTES_IN = 4,\n\tIPMRA_VIFA_BYTES_OUT = 5,\n\tIPMRA_VIFA_PACKETS_IN = 6,\n\tIPMRA_VIFA_PACKETS_OUT = 7,\n\tIPMRA_VIFA_LOCAL_ADDR = 8,\n\tIPMRA_VIFA_REMOTE_ADDR = 9,\n\tIPMRA_VIFA_PAD = 10,\n\t__IPMRA_VIFA_MAX = 11,\n};\n\nenum {\n\tIPMRA_CREPORT_UNSPEC = 0,\n\tIPMRA_CREPORT_MSGTYPE = 1,\n\tIPMRA_CREPORT_VIF_ID = 2,\n\tIPMRA_CREPORT_SRC_ADDR = 3,\n\tIPMRA_CREPORT_DST_ADDR = 4,\n\tIPMRA_CREPORT_PKT = 5,\n\t__IPMRA_CREPORT_MAX = 6,\n};\n\nstruct vif_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct net_device *dev;\n\tshort unsigned int vif_index;\n\tshort unsigned int vif_flags;\n\tu32 tb_id;\n};\n\nenum {\n\tMFC_STATIC = 1,\n\tMFC_OFFLOAD = 2,\n};\n\nstruct mr_mfc {\n\tstruct rhlist_head mnode;\n\tshort unsigned int mfc_parent;\n\tint mfc_flags;\n\tunion {\n\t\tstruct {\n\t\t\tlong unsigned int expires;\n\t\t\tstruct sk_buff_head unresolved;\n\t\t} unres;\n\t\tstruct {\n\t\t\tlong unsigned int last_assert;\n\t\t\tint minvif;\n\t\t\tint maxvif;\n\t\t\tlong unsigned int bytes;\n\t\t\tlong unsigned int pkt;\n\t\t\tlong unsigned int wrong_if;\n\t\t\tlong unsigned int lastuse;\n\t\t\tunsigned char ttls[32];\n\t\t\trefcount_t refcount;\n\t\t} res;\n\t} mfc_un;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n\tvoid (*free)(struct callback_head *);\n};\n\nstruct mfc_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct mr_mfc *mfc;\n\tu32 tb_id;\n};\n\nstruct mr_vif_iter {\n\tstruct seq_net_private p;\n\tstruct mr_table *mrt;\n\tint ct;\n};\n\nstruct mr_mfc_iter {\n\tstruct seq_net_private p;\n\tstruct mr_table *mrt;\n\tstruct list_head *cache;\n\tspinlock_t *lock;\n};\n\nstruct mfc_cache_cmp_arg {\n\t__be32 mfc_mcastgrp;\n\t__be32 mfc_origin;\n};\n\nstruct mfc_cache {\n\tstruct mr_mfc _c;\n\tunion {\n\t\tstruct {\n\t\t\t__be32 mfc_mcastgrp;\n\t\t\t__be32 mfc_origin;\n\t\t};\n\t\tstruct mfc_cache_cmp_arg cmparg;\n\t};\n};\n\nstruct compat_sioc_sg_req {\n\tstruct in_addr src;\n\tstruct in_addr grp;\n\tcompat_ulong_t pktcnt;\n\tcompat_ulong_t bytecnt;\n\tcompat_ulong_t wrong_if;\n};\n\nstruct compat_sioc_vif_req {\n\tvifi_t vifi;\n\tcompat_ulong_t icount;\n\tcompat_ulong_t ocount;\n\tcompat_ulong_t ibytes;\n\tcompat_ulong_t obytes;\n};\n\nstruct rta_mfc_stats {\n\t__u64 mfcs_packets;\n\t__u64 mfcs_bytes;\n\t__u64 mfcs_wrong_if;\n};\n\nstruct xfrm_tunnel {\n\tint (*handler)(struct sk_buff *);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tstruct xfrm_tunnel *next;\n\tint priority;\n};\n\nstruct ic_device {\n\tstruct ic_device *next;\n\tstruct net_device *dev;\n\tshort unsigned int flags;\n\tshort int able;\n\t__be32 xid;\n};\n\nstruct bootp_pkt {\n\tstruct iphdr iph;\n\tstruct udphdr udph;\n\tu8 op;\n\tu8 htype;\n\tu8 hlen;\n\tu8 hops;\n\t__be32 xid;\n\t__be16 secs;\n\t__be16 flags;\n\t__be32 client_ip;\n\t__be32 your_ip;\n\t__be32 server_ip;\n\t__be32 relay_ip;\n\tu8 hw_addr[16];\n\tu8 serv_name[64];\n\tu8 boot_file[128];\n\tu8 exten[312];\n};\n\nstruct xt_get_revision {\n\tchar name[29];\n\t__u8 revision;\n};\n\nstruct ipt_icmp {\n\t__u8 type;\n\t__u8 code[2];\n\t__u8 invflags;\n};\n\nstruct ipt_getinfo {\n\tchar name[32];\n\tunsigned int valid_hooks;\n\tunsigned int hook_entry[5];\n\tunsigned int underflow[5];\n\tunsigned int num_entries;\n\tunsigned int size;\n};\n\nstruct ipt_replace {\n\tchar name[32];\n\tunsigned int valid_hooks;\n\tunsigned int num_entries;\n\tunsigned int size;\n\tunsigned int hook_entry[5];\n\tunsigned int underflow[5];\n\tunsigned int num_counters;\n\tstruct xt_counters *counters;\n\tstruct ipt_entry entries[0];\n};\n\nstruct ipt_get_entries {\n\tchar name[32];\n\tunsigned int size;\n\tstruct ipt_entry entrytable[0];\n};\n\nstruct ipt_standard {\n\tstruct ipt_entry entry;\n\tstruct xt_standard_target target;\n};\n\nstruct ipt_error {\n\tstruct ipt_entry entry;\n\tstruct xt_error_target target;\n};\n\nstruct compat_ipt_entry {\n\tstruct ipt_ip ip;\n\tcompat_uint_t nfcache;\n\t__u16 target_offset;\n\t__u16 next_offset;\n\tcompat_uint_t comefrom;\n\tstruct compat_xt_counters counters;\n\tunsigned char elems[0];\n};\n\nstruct compat_ipt_replace {\n\tchar name[32];\n\tu32 valid_hooks;\n\tu32 num_entries;\n\tu32 size;\n\tu32 hook_entry[5];\n\tu32 underflow[5];\n\tu32 num_counters;\n\tcompat_uptr_t counters;\n\tstruct compat_ipt_entry entries[0];\n} __attribute__((packed));\n\nstruct compat_ipt_get_entries {\n\tchar name[32];\n\tcompat_uint_t size;\n\tstruct compat_ipt_entry entrytable[0];\n} __attribute__((packed));\n\nenum ipt_reject_with {\n\tIPT_ICMP_NET_UNREACHABLE = 0,\n\tIPT_ICMP_HOST_UNREACHABLE = 1,\n\tIPT_ICMP_PROT_UNREACHABLE = 2,\n\tIPT_ICMP_PORT_UNREACHABLE = 3,\n\tIPT_ICMP_ECHOREPLY = 4,\n\tIPT_ICMP_NET_PROHIBITED = 5,\n\tIPT_ICMP_HOST_PROHIBITED = 6,\n\tIPT_TCP_RESET = 7,\n\tIPT_ICMP_ADMIN_PROHIBITED = 8,\n};\n\nstruct ipt_reject_info {\n\tenum ipt_reject_with with;\n};\n\nstruct bictcp {\n\tu32 cnt;\n\tu32 last_max_cwnd;\n\tu32 last_cwnd;\n\tu32 last_time;\n\tu32 bic_origin_point;\n\tu32 bic_K;\n\tu32 delay_min;\n\tu32 epoch_start;\n\tu32 ack_cnt;\n\tu32 tcp_cwnd;\n\tu16 unused;\n\tu8 sample_cnt;\n\tu8 found;\n\tu32 round_start;\n\tu32 end_seq;\n\tu32 last_ack;\n\tu32 curr_rtt;\n};\n\nstruct tls_rec {\n\tstruct list_head list;\n\tint tx_ready;\n\tint tx_flags;\n\tstruct sk_msg msg_plaintext;\n\tstruct sk_msg msg_encrypted;\n\tstruct scatterlist sg_aead_in[2];\n\tstruct scatterlist sg_aead_out[2];\n\tchar content_type;\n\tstruct scatterlist sg_content_type;\n\tchar aad_space[13];\n\tu8 iv_data[16];\n\tstruct aead_request aead_req;\n\tu8 aead_req_ctx[0];\n};\n\nstruct tx_work {\n\tstruct delayed_work work;\n\tstruct sock *sk;\n};\n\nstruct tls_sw_context_tx {\n\tstruct crypto_aead *aead_send;\n\tstruct crypto_wait async_wait;\n\tstruct tx_work tx_work;\n\tstruct tls_rec *open_rec;\n\tstruct list_head tx_list;\n\tatomic_t encrypt_pending;\n\tspinlock_t encrypt_compl_lock;\n\tint async_notify;\n\tu8 async_capable: 1;\n\tlong unsigned int tx_bitmask;\n};\n\nenum {\n\tTCP_BPF_IPV4 = 0,\n\tTCP_BPF_IPV6 = 1,\n\tTCP_BPF_NUM_PROTS = 2,\n};\n\nenum {\n\tTCP_BPF_BASE = 0,\n\tTCP_BPF_TX = 1,\n\tTCP_BPF_NUM_CFGS = 2,\n};\n\nenum {\n\tUDP_BPF_IPV4 = 0,\n\tUDP_BPF_IPV6 = 1,\n\tUDP_BPF_NUM_PROTS = 2,\n};\n\nstruct netlbl_audit {\n\tu32 secid;\n\tkuid_t loginuid;\n\tunsigned int sessionid;\n};\n\nstruct cipso_v4_std_map_tbl {\n\tstruct {\n\t\tu32 *cipso;\n\t\tu32 *local;\n\t\tu32 cipso_size;\n\t\tu32 local_size;\n\t} lvl;\n\tstruct {\n\t\tu32 *cipso;\n\t\tu32 *local;\n\t\tu32 cipso_size;\n\t\tu32 local_size;\n\t} cat;\n};\n\nstruct cipso_v4_doi {\n\tu32 doi;\n\tu32 type;\n\tunion {\n\t\tstruct cipso_v4_std_map_tbl *std;\n\t} map;\n\tu8 tags[5];\n\trefcount_t refcount;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct cipso_v4_map_cache_bkt {\n\tspinlock_t lock;\n\tu32 size;\n\tstruct list_head list;\n};\n\nstruct cipso_v4_map_cache_entry {\n\tu32 hash;\n\tunsigned char *key;\n\tsize_t key_len;\n\tstruct netlbl_lsm_cache *lsm_data;\n\tu32 activity;\n\tstruct list_head list;\n};\n\nstruct xfrm_policy_afinfo {\n\tstruct dst_ops *dst_ops;\n\tstruct dst_entry * (*dst_lookup)(struct net *, int, int, const xfrm_address_t *, const xfrm_address_t *, u32);\n\tint (*get_saddr)(struct net *, int, xfrm_address_t *, xfrm_address_t *, u32);\n\tint (*fill_dst)(struct xfrm_dst *, struct net_device *, const struct flowi *);\n\tstruct dst_entry * (*blackhole_route)(struct net *, struct dst_entry *);\n};\n\nstruct xfrm_state_afinfo {\n\tu8 family;\n\tu8 proto;\n\tconst struct xfrm_type_offload *type_offload_esp;\n\tconst struct xfrm_type *type_esp;\n\tconst struct xfrm_type *type_ipip;\n\tconst struct xfrm_type *type_ipip6;\n\tconst struct xfrm_type *type_comp;\n\tconst struct xfrm_type *type_ah;\n\tconst struct xfrm_type *type_routing;\n\tconst struct xfrm_type *type_dstopts;\n\tint (*output)(struct net *, struct sock *, struct sk_buff *);\n\tint (*transport_finish)(struct sk_buff *, int);\n\tvoid (*local_error)(struct sk_buff *, u32);\n};\n\nstruct ip6_tnl;\n\nstruct xfrm_tunnel_skb_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tunion {\n\t\tstruct ip_tunnel *ip4;\n\t\tstruct ip6_tnl *ip6;\n\t} tunnel;\n};\n\nstruct xfrm_mode_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\t__be16 id;\n\t__be16 frag_off;\n\tu8 ihl;\n\tu8 tos;\n\tu8 ttl;\n\tu8 protocol;\n\tu8 optlen;\n\tu8 flow_lbl[3];\n};\n\nstruct xfrm_spi_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\tunsigned int daddroff;\n\tunsigned int family;\n\t__be32 seq;\n};\n\nstruct xfrm_input_afinfo {\n\tunsigned int family;\n\tint (*callback)(struct sk_buff *, u8, int);\n};\n\nstruct xfrm4_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*input_handler)(struct sk_buff *, int, __be32, int);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, u32);\n\tstruct xfrm4_protocol *next;\n\tint priority;\n};\n\ntypedef u64 (*btf_bpf_tcp_send_ack)(struct tcp_sock *, u32);\n\nenum {\n\tXFRM_STATE_VOID = 0,\n\tXFRM_STATE_ACQ = 1,\n\tXFRM_STATE_VALID = 2,\n\tXFRM_STATE_ERROR = 3,\n\tXFRM_STATE_EXPIRED = 4,\n\tXFRM_STATE_DEAD = 5,\n};\n\nstruct xfrm_if;\n\nstruct xfrm_if_cb {\n\tstruct xfrm_if * (*decode_session)(struct sk_buff *, short unsigned int);\n};\n\nstruct xfrm_if_parms {\n\tint link;\n\tu32 if_id;\n};\n\nstruct xfrm_if {\n\tstruct xfrm_if *next;\n\tstruct net_device *dev;\n\tstruct net *net;\n\tstruct xfrm_if_parms p;\n\tstruct gro_cells gro_cells;\n};\n\nstruct xfrm_policy_walk {\n\tstruct xfrm_policy_walk_entry walk;\n\tu8 type;\n\tu32 seq;\n};\n\nstruct xfrmk_spdinfo {\n\tu32 incnt;\n\tu32 outcnt;\n\tu32 fwdcnt;\n\tu32 inscnt;\n\tu32 outscnt;\n\tu32 fwdscnt;\n\tu32 spdhcnt;\n\tu32 spdhmcnt;\n};\n\nstruct xfrm_flo {\n\tstruct dst_entry *dst_orig;\n\tu8 flags;\n};\n\nstruct xfrm_pol_inexact_node {\n\tstruct rb_node node;\n\tunion {\n\t\txfrm_address_t addr;\n\t\tstruct callback_head rcu;\n\t};\n\tu8 prefixlen;\n\tstruct rb_root root;\n\tstruct hlist_head hhead;\n};\n\nstruct xfrm_pol_inexact_key {\n\tpossible_net_t net;\n\tu32 if_id;\n\tu16 family;\n\tu8 dir;\n\tu8 type;\n};\n\nstruct xfrm_pol_inexact_bin {\n\tstruct xfrm_pol_inexact_key k;\n\tstruct rhash_head head;\n\tstruct hlist_head hhead;\n\tseqcount_t count;\n\tstruct rb_root root_d;\n\tstruct rb_root root_s;\n\tstruct list_head inexact_bins;\n\tstruct callback_head rcu;\n};\n\nenum xfrm_pol_inexact_candidate_type {\n\tXFRM_POL_CAND_BOTH = 0,\n\tXFRM_POL_CAND_SADDR = 1,\n\tXFRM_POL_CAND_DADDR = 2,\n\tXFRM_POL_CAND_ANY = 3,\n\tXFRM_POL_CAND_MAX = 4,\n};\n\nstruct xfrm_pol_inexact_candidates {\n\tstruct hlist_head *res[4];\n};\n\nenum xfrm_ae_ftype_t {\n\tXFRM_AE_UNSPEC = 0,\n\tXFRM_AE_RTHR = 1,\n\tXFRM_AE_RVAL = 2,\n\tXFRM_AE_LVAL = 4,\n\tXFRM_AE_ETHR = 8,\n\tXFRM_AE_CR = 16,\n\tXFRM_AE_CE = 32,\n\tXFRM_AE_CU = 64,\n\t__XFRM_AE_MAX = 65,\n};\n\nenum xfrm_nlgroups {\n\tXFRMNLGRP_NONE = 0,\n\tXFRMNLGRP_ACQUIRE = 1,\n\tXFRMNLGRP_EXPIRE = 2,\n\tXFRMNLGRP_SA = 3,\n\tXFRMNLGRP_POLICY = 4,\n\tXFRMNLGRP_AEVENTS = 5,\n\tXFRMNLGRP_REPORT = 6,\n\tXFRMNLGRP_MIGRATE = 7,\n\tXFRMNLGRP_MAPPING = 8,\n\t__XFRMNLGRP_MAX = 9,\n};\n\nenum {\n\tXFRM_MODE_FLAG_TUNNEL = 1,\n};\n\nstruct km_event {\n\tunion {\n\t\tu32 hard;\n\t\tu32 proto;\n\t\tu32 byid;\n\t\tu32 aevent;\n\t\tu32 type;\n\t} data;\n\tu32 seq;\n\tu32 portid;\n\tu32 event;\n\tstruct net *net;\n};\n\nstruct xfrm_kmaddress {\n\txfrm_address_t local;\n\txfrm_address_t remote;\n\tu32 reserved;\n\tu16 family;\n};\n\nstruct xfrm_migrate {\n\txfrm_address_t old_daddr;\n\txfrm_address_t old_saddr;\n\txfrm_address_t new_daddr;\n\txfrm_address_t new_saddr;\n\tu8 proto;\n\tu8 mode;\n\tu16 reserved;\n\tu32 reqid;\n\tu16 old_family;\n\tu16 new_family;\n};\n\nstruct xfrm_mgr {\n\tstruct list_head list;\n\tint (*notify)(struct xfrm_state *, const struct km_event *);\n\tint (*acquire)(struct xfrm_state *, struct xfrm_tmpl *, struct xfrm_policy *);\n\tstruct xfrm_policy * (*compile_policy)(struct sock *, int, u8 *, int, int *);\n\tint (*new_mapping)(struct xfrm_state *, xfrm_address_t *, __be16);\n\tint (*notify_policy)(struct xfrm_policy *, int, const struct km_event *);\n\tint (*report)(struct net *, u8, struct xfrm_selector *, xfrm_address_t *);\n\tint (*migrate)(const struct xfrm_selector *, u8, u8, const struct xfrm_migrate *, int, const struct xfrm_kmaddress *, const struct xfrm_encap_tmpl *);\n\tbool (*is_alive)(const struct km_event *);\n};\n\nstruct xfrmk_sadinfo {\n\tu32 sadhcnt;\n\tu32 sadhmcnt;\n\tu32 sadcnt;\n};\n\nstruct ip_beet_phdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 padlen;\n\t__u8 reserved;\n};\n\nstruct __ip6_tnl_parm {\n\tchar name[16];\n\tint link;\n\t__u8 proto;\n\t__u8 encap_limit;\n\t__u8 hop_limit;\n\tbool collect_md;\n\t__be32 flowinfo;\n\t__u32 flags;\n\tstruct in6_addr laddr;\n\tstruct in6_addr raddr;\n\t__be16 i_flags;\n\t__be16 o_flags;\n\t__be32 i_key;\n\t__be32 o_key;\n\t__u32 fwmark;\n\t__u32 index;\n\t__u8 erspan_ver;\n\t__u8 dir;\n\t__u16 hwid;\n};\n\nstruct ip6_tnl {\n\tstruct ip6_tnl *next;\n\tstruct net_device *dev;\n\tstruct net *net;\n\tstruct __ip6_tnl_parm parms;\n\tstruct flowi fl;\n\tstruct dst_cache dst_cache;\n\tstruct gro_cells gro_cells;\n\tint err_count;\n\tlong unsigned int err_time;\n\t__u32 i_seqno;\n\t__u32 o_seqno;\n\tint hlen;\n\tint tun_hlen;\n\tint encap_hlen;\n\tstruct ip_tunnel_encap encap;\n\tint mlink;\n};\n\nstruct xfrm_skb_cb {\n\tstruct xfrm_tunnel_skb_cb header;\n\tunion {\n\t\tstruct {\n\t\t\t__u32 low;\n\t\t\t__u32 hi;\n\t\t} output;\n\t\tstruct {\n\t\t\t__be32 low;\n\t\t\t__be32 hi;\n\t\t} input;\n\t} seq;\n};\n\nstruct xfrm_trans_tasklet {\n\tstruct tasklet_struct tasklet;\n\tstruct sk_buff_head queue;\n};\n\nstruct xfrm_trans_cb {\n\tunion {\n\t\tstruct inet_skb_parm h4;\n\t\tstruct inet6_skb_parm h6;\n\t} header;\n\tint (*finish)(struct net *, struct sock *, struct sk_buff *);\n\tstruct net *net;\n};\n\nstruct sadb_alg {\n\t__u8 sadb_alg_id;\n\t__u8 sadb_alg_ivlen;\n\t__u16 sadb_alg_minbits;\n\t__u16 sadb_alg_maxbits;\n\t__u16 sadb_alg_reserved;\n};\n\nstruct xfrm_algo_aead_info {\n\tchar *geniv;\n\tu16 icv_truncbits;\n};\n\nstruct xfrm_algo_auth_info {\n\tu16 icv_truncbits;\n\tu16 icv_fullbits;\n};\n\nstruct xfrm_algo_encr_info {\n\tchar *geniv;\n\tu16 blockbits;\n\tu16 defkeybits;\n};\n\nstruct xfrm_algo_comp_info {\n\tu16 threshold;\n};\n\nstruct xfrm_algo_desc {\n\tchar *name;\n\tchar *compat;\n\tu8 available: 1;\n\tu8 pfkey_supported: 1;\n\tunion {\n\t\tstruct xfrm_algo_aead_info aead;\n\t\tstruct xfrm_algo_auth_info auth;\n\t\tstruct xfrm_algo_encr_info encr;\n\t\tstruct xfrm_algo_comp_info comp;\n\t} uinfo;\n\tstruct sadb_alg desc;\n};\n\nstruct xfrm_algo_list {\n\tstruct xfrm_algo_desc *algs;\n\tint entries;\n\tu32 type;\n\tu32 mask;\n};\n\nstruct xfrm_aead_name {\n\tconst char *name;\n\tint icvbits;\n};\n\nenum {\n\tXFRM_SHARE_ANY = 0,\n\tXFRM_SHARE_SESSION = 1,\n\tXFRM_SHARE_USER = 2,\n\tXFRM_SHARE_UNIQUE = 3,\n};\n\nstruct xfrm_user_sec_ctx {\n\t__u16 len;\n\t__u16 exttype;\n\t__u8 ctx_alg;\n\t__u8 ctx_doi;\n\t__u16 ctx_len;\n};\n\nstruct xfrm_user_tmpl {\n\tstruct xfrm_id id;\n\t__u16 family;\n\txfrm_address_t saddr;\n\t__u32 reqid;\n\t__u8 mode;\n\t__u8 share;\n\t__u8 optional;\n\t__u32 aalgos;\n\t__u32 ealgos;\n\t__u32 calgos;\n};\n\nstruct xfrm_userpolicy_type {\n\t__u8 type;\n\t__u16 reserved1;\n\t__u8 reserved2;\n};\n\nenum xfrm_attr_type_t {\n\tXFRMA_UNSPEC = 0,\n\tXFRMA_ALG_AUTH = 1,\n\tXFRMA_ALG_CRYPT = 2,\n\tXFRMA_ALG_COMP = 3,\n\tXFRMA_ENCAP = 4,\n\tXFRMA_TMPL = 5,\n\tXFRMA_SA = 6,\n\tXFRMA_POLICY = 7,\n\tXFRMA_SEC_CTX = 8,\n\tXFRMA_LTIME_VAL = 9,\n\tXFRMA_REPLAY_VAL = 10,\n\tXFRMA_REPLAY_THRESH = 11,\n\tXFRMA_ETIMER_THRESH = 12,\n\tXFRMA_SRCADDR = 13,\n\tXFRMA_COADDR = 14,\n\tXFRMA_LASTUSED = 15,\n\tXFRMA_POLICY_TYPE = 16,\n\tXFRMA_MIGRATE = 17,\n\tXFRMA_ALG_AEAD = 18,\n\tXFRMA_KMADDRESS = 19,\n\tXFRMA_ALG_AUTH_TRUNC = 20,\n\tXFRMA_MARK = 21,\n\tXFRMA_TFCPAD = 22,\n\tXFRMA_REPLAY_ESN_VAL = 23,\n\tXFRMA_SA_EXTRA_FLAGS = 24,\n\tXFRMA_PROTO = 25,\n\tXFRMA_ADDRESS_FILTER = 26,\n\tXFRMA_PAD = 27,\n\tXFRMA_OFFLOAD_DEV = 28,\n\tXFRMA_SET_MARK = 29,\n\tXFRMA_SET_MARK_MASK = 30,\n\tXFRMA_IF_ID = 31,\n\t__XFRMA_MAX = 32,\n};\n\nenum xfrm_sadattr_type_t {\n\tXFRMA_SAD_UNSPEC = 0,\n\tXFRMA_SAD_CNT = 1,\n\tXFRMA_SAD_HINFO = 2,\n\t__XFRMA_SAD_MAX = 3,\n};\n\nstruct xfrmu_sadhinfo {\n\t__u32 sadhcnt;\n\t__u32 sadhmcnt;\n};\n\nenum xfrm_spdattr_type_t {\n\tXFRMA_SPD_UNSPEC = 0,\n\tXFRMA_SPD_INFO = 1,\n\tXFRMA_SPD_HINFO = 2,\n\tXFRMA_SPD_IPV4_HTHRESH = 3,\n\tXFRMA_SPD_IPV6_HTHRESH = 4,\n\t__XFRMA_SPD_MAX = 5,\n};\n\nstruct xfrmu_spdinfo {\n\t__u32 incnt;\n\t__u32 outcnt;\n\t__u32 fwdcnt;\n\t__u32 inscnt;\n\t__u32 outscnt;\n\t__u32 fwdscnt;\n};\n\nstruct xfrmu_spdhinfo {\n\t__u32 spdhcnt;\n\t__u32 spdhmcnt;\n};\n\nstruct xfrmu_spdhthresh {\n\t__u8 lbits;\n\t__u8 rbits;\n};\n\nstruct xfrm_usersa_info {\n\tstruct xfrm_selector sel;\n\tstruct xfrm_id id;\n\txfrm_address_t saddr;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_lifetime_cur curlft;\n\tstruct xfrm_stats stats;\n\t__u32 seq;\n\t__u32 reqid;\n\t__u16 family;\n\t__u8 mode;\n\t__u8 replay_window;\n\t__u8 flags;\n};\n\nstruct xfrm_usersa_id {\n\txfrm_address_t daddr;\n\t__be32 spi;\n\t__u16 family;\n\t__u8 proto;\n};\n\nstruct xfrm_aevent_id {\n\tstruct xfrm_usersa_id sa_id;\n\txfrm_address_t saddr;\n\t__u32 flags;\n\t__u32 reqid;\n};\n\nstruct xfrm_userspi_info {\n\tstruct xfrm_usersa_info info;\n\t__u32 min;\n\t__u32 max;\n};\n\nstruct xfrm_userpolicy_info {\n\tstruct xfrm_selector sel;\n\tstruct xfrm_lifetime_cfg lft;\n\tstruct xfrm_lifetime_cur curlft;\n\t__u32 priority;\n\t__u32 index;\n\t__u8 dir;\n\t__u8 action;\n\t__u8 flags;\n\t__u8 share;\n};\n\nstruct xfrm_userpolicy_id {\n\tstruct xfrm_selector sel;\n\t__u32 index;\n\t__u8 dir;\n};\n\nstruct xfrm_user_acquire {\n\tstruct xfrm_id id;\n\txfrm_address_t saddr;\n\tstruct xfrm_selector sel;\n\tstruct xfrm_userpolicy_info policy;\n\t__u32 aalgos;\n\t__u32 ealgos;\n\t__u32 calgos;\n\t__u32 seq;\n};\n\nstruct xfrm_user_expire {\n\tstruct xfrm_usersa_info state;\n\t__u8 hard;\n};\n\nstruct xfrm_user_polexpire {\n\tstruct xfrm_userpolicy_info pol;\n\t__u8 hard;\n};\n\nstruct xfrm_usersa_flush {\n\t__u8 proto;\n};\n\nstruct xfrm_user_report {\n\t__u8 proto;\n\tstruct xfrm_selector sel;\n};\n\nstruct xfrm_user_mapping {\n\tstruct xfrm_usersa_id id;\n\t__u32 reqid;\n\txfrm_address_t old_saddr;\n\txfrm_address_t new_saddr;\n\t__be16 old_sport;\n\t__be16 new_sport;\n};\n\nstruct xfrm_user_offload {\n\tint ifindex;\n\t__u8 flags;\n};\n\nstruct xfrm_dump_info {\n\tstruct sk_buff *in_skb;\n\tstruct sk_buff *out_skb;\n\tu32 nlmsg_seq;\n\tu16 nlmsg_flags;\n};\n\nstruct xfrm_link {\n\tint (*doit)(struct sk_buff *, struct nlmsghdr *, struct nlattr **);\n\tint (*start)(struct netlink_callback *);\n\tint (*dump)(struct sk_buff *, struct netlink_callback *);\n\tint (*done)(struct netlink_callback *);\n\tconst struct nla_policy *nla_pol;\n\tint nla_max;\n};\n\nstruct unix_stream_read_state {\n\tint (*recv_actor)(struct sk_buff *, int, int, struct unix_stream_read_state *);\n\tstruct socket *socket;\n\tstruct msghdr *msg;\n\tstruct pipe_inode_info *pipe;\n\tsize_t size;\n\tint flags;\n\tunsigned int splice_flags;\n};\n\nenum flowlabel_reflect {\n\tFLOWLABEL_REFLECT_ESTABLISHED = 1,\n\tFLOWLABEL_REFLECT_TCP_RESET = 2,\n\tFLOWLABEL_REFLECT_ICMPV6_ECHO_REPLIES = 4,\n};\n\nstruct in6_rtmsg {\n\tstruct in6_addr rtmsg_dst;\n\tstruct in6_addr rtmsg_src;\n\tstruct in6_addr rtmsg_gateway;\n\t__u32 rtmsg_type;\n\t__u16 rtmsg_dst_len;\n\t__u16 rtmsg_src_len;\n\t__u32 rtmsg_metric;\n\tlong unsigned int rtmsg_info;\n\t__u32 rtmsg_flags;\n\tint rtmsg_ifindex;\n};\n\nstruct compat_in6_rtmsg {\n\tstruct in6_addr rtmsg_dst;\n\tstruct in6_addr rtmsg_src;\n\tstruct in6_addr rtmsg_gateway;\n\tu32 rtmsg_type;\n\tu16 rtmsg_dst_len;\n\tu16 rtmsg_src_len;\n\tu32 rtmsg_metric;\n\tu32 rtmsg_info;\n\tu32 rtmsg_flags;\n\ts32 rtmsg_ifindex;\n};\n\nstruct ac6_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n};\n\nstruct ip6_fraglist_iter {\n\tstruct ipv6hdr *tmp_hdr;\n\tstruct sk_buff *frag;\n\tint offset;\n\tunsigned int hlen;\n\t__be32 frag_id;\n\tu8 nexthdr;\n};\n\nstruct ip6_frag_state {\n\tu8 *prevhdr;\n\tunsigned int hlen;\n\tunsigned int mtu;\n\tunsigned int left;\n\tint offset;\n\tint ptr;\n\tint hroom;\n\tint troom;\n\t__be32 frag_id;\n\tu8 nexthdr;\n};\n\nstruct ipcm6_cookie {\n\tstruct sockcm_cookie sockc;\n\t__s16 hlimit;\n\t__s16 tclass;\n\t__s8 dontfrag;\n\tstruct ipv6_txoptions *opt;\n\t__u16 gso_size;\n};\n\nenum {\n\tIFLA_INET6_UNSPEC = 0,\n\tIFLA_INET6_FLAGS = 1,\n\tIFLA_INET6_CONF = 2,\n\tIFLA_INET6_STATS = 3,\n\tIFLA_INET6_MCAST = 4,\n\tIFLA_INET6_CACHEINFO = 5,\n\tIFLA_INET6_ICMP6STATS = 6,\n\tIFLA_INET6_TOKEN = 7,\n\tIFLA_INET6_ADDR_GEN_MODE = 8,\n\t__IFLA_INET6_MAX = 9,\n};\n\nenum in6_addr_gen_mode {\n\tIN6_ADDR_GEN_MODE_EUI64 = 0,\n\tIN6_ADDR_GEN_MODE_NONE = 1,\n\tIN6_ADDR_GEN_MODE_STABLE_PRIVACY = 2,\n\tIN6_ADDR_GEN_MODE_RANDOM = 3,\n};\n\nstruct ifla_cacheinfo {\n\t__u32 max_reasm_len;\n\t__u32 tstamp;\n\t__u32 reachable_time;\n\t__u32 retrans_time;\n};\n\nstruct wpan_phy;\n\nstruct wpan_dev_header_ops;\n\nstruct wpan_dev {\n\tstruct wpan_phy *wpan_phy;\n\tint iftype;\n\tstruct list_head list;\n\tstruct net_device *netdev;\n\tconst struct wpan_dev_header_ops *header_ops;\n\tstruct net_device *lowpan_dev;\n\tu32 identifier;\n\t__le16 pan_id;\n\t__le16 short_addr;\n\t__le64 extended_addr;\n\tatomic_t bsn;\n\tatomic_t dsn;\n\tu8 min_be;\n\tu8 max_be;\n\tu8 csma_retries;\n\ts8 frame_retries;\n\tbool lbt;\n\tbool promiscuous_mode;\n\tbool ackreq;\n};\n\nstruct prefixmsg {\n\tunsigned char prefix_family;\n\tunsigned char prefix_pad1;\n\tshort unsigned int prefix_pad2;\n\tint prefix_ifindex;\n\tunsigned char prefix_type;\n\tunsigned char prefix_len;\n\tunsigned char prefix_flags;\n\tunsigned char prefix_pad3;\n};\n\nenum {\n\tPREFIX_UNSPEC = 0,\n\tPREFIX_ADDRESS = 1,\n\tPREFIX_CACHEINFO = 2,\n\t__PREFIX_MAX = 3,\n};\n\nstruct prefix_cacheinfo {\n\t__u32 preferred_time;\n\t__u32 valid_time;\n};\n\nstruct in6_ifreq {\n\tstruct in6_addr ifr6_addr;\n\t__u32 ifr6_prefixlen;\n\tint ifr6_ifindex;\n};\n\nenum {\n\tDEVCONF_FORWARDING = 0,\n\tDEVCONF_HOPLIMIT = 1,\n\tDEVCONF_MTU6 = 2,\n\tDEVCONF_ACCEPT_RA = 3,\n\tDEVCONF_ACCEPT_REDIRECTS = 4,\n\tDEVCONF_AUTOCONF = 5,\n\tDEVCONF_DAD_TRANSMITS = 6,\n\tDEVCONF_RTR_SOLICITS = 7,\n\tDEVCONF_RTR_SOLICIT_INTERVAL = 8,\n\tDEVCONF_RTR_SOLICIT_DELAY = 9,\n\tDEVCONF_USE_TEMPADDR = 10,\n\tDEVCONF_TEMP_VALID_LFT = 11,\n\tDEVCONF_TEMP_PREFERED_LFT = 12,\n\tDEVCONF_REGEN_MAX_RETRY = 13,\n\tDEVCONF_MAX_DESYNC_FACTOR = 14,\n\tDEVCONF_MAX_ADDRESSES = 15,\n\tDEVCONF_FORCE_MLD_VERSION = 16,\n\tDEVCONF_ACCEPT_RA_DEFRTR = 17,\n\tDEVCONF_ACCEPT_RA_PINFO = 18,\n\tDEVCONF_ACCEPT_RA_RTR_PREF = 19,\n\tDEVCONF_RTR_PROBE_INTERVAL = 20,\n\tDEVCONF_ACCEPT_RA_RT_INFO_MAX_PLEN = 21,\n\tDEVCONF_PROXY_NDP = 22,\n\tDEVCONF_OPTIMISTIC_DAD = 23,\n\tDEVCONF_ACCEPT_SOURCE_ROUTE = 24,\n\tDEVCONF_MC_FORWARDING = 25,\n\tDEVCONF_DISABLE_IPV6 = 26,\n\tDEVCONF_ACCEPT_DAD = 27,\n\tDEVCONF_FORCE_TLLAO = 28,\n\tDEVCONF_NDISC_NOTIFY = 29,\n\tDEVCONF_MLDV1_UNSOLICITED_REPORT_INTERVAL = 30,\n\tDEVCONF_MLDV2_UNSOLICITED_REPORT_INTERVAL = 31,\n\tDEVCONF_SUPPRESS_FRAG_NDISC = 32,\n\tDEVCONF_ACCEPT_RA_FROM_LOCAL = 33,\n\tDEVCONF_USE_OPTIMISTIC = 34,\n\tDEVCONF_ACCEPT_RA_MTU = 35,\n\tDEVCONF_STABLE_SECRET = 36,\n\tDEVCONF_USE_OIF_ADDRS_ONLY = 37,\n\tDEVCONF_ACCEPT_RA_MIN_HOP_LIMIT = 38,\n\tDEVCONF_IGNORE_ROUTES_WITH_LINKDOWN = 39,\n\tDEVCONF_DROP_UNICAST_IN_L2_MULTICAST = 40,\n\tDEVCONF_DROP_UNSOLICITED_NA = 41,\n\tDEVCONF_KEEP_ADDR_ON_DOWN = 42,\n\tDEVCONF_RTR_SOLICIT_MAX_INTERVAL = 43,\n\tDEVCONF_SEG6_ENABLED = 44,\n\tDEVCONF_SEG6_REQUIRE_HMAC = 45,\n\tDEVCONF_ENHANCED_DAD = 46,\n\tDEVCONF_ADDR_GEN_MODE = 47,\n\tDEVCONF_DISABLE_POLICY = 48,\n\tDEVCONF_ACCEPT_RA_RT_INFO_MIN_PLEN = 49,\n\tDEVCONF_NDISC_TCLASS = 50,\n\tDEVCONF_RPL_SEG_ENABLED = 51,\n\tDEVCONF_MAX = 52,\n};\n\nenum {\n\tINET6_IFADDR_STATE_PREDAD = 0,\n\tINET6_IFADDR_STATE_DAD = 1,\n\tINET6_IFADDR_STATE_POSTDAD = 2,\n\tINET6_IFADDR_STATE_ERRDAD = 3,\n\tINET6_IFADDR_STATE_DEAD = 4,\n};\n\nenum nl802154_cca_modes {\n\t__NL802154_CCA_INVALID = 0,\n\tNL802154_CCA_ENERGY = 1,\n\tNL802154_CCA_CARRIER = 2,\n\tNL802154_CCA_ENERGY_CARRIER = 3,\n\tNL802154_CCA_ALOHA = 4,\n\tNL802154_CCA_UWB_SHR = 5,\n\tNL802154_CCA_UWB_MULTIPLEXED = 6,\n\t__NL802154_CCA_ATTR_AFTER_LAST = 7,\n\tNL802154_CCA_ATTR_MAX = 6,\n};\n\nenum nl802154_cca_opts {\n\tNL802154_CCA_OPT_ENERGY_CARRIER_AND = 0,\n\tNL802154_CCA_OPT_ENERGY_CARRIER_OR = 1,\n\t__NL802154_CCA_OPT_ATTR_AFTER_LAST = 2,\n\tNL802154_CCA_OPT_ATTR_MAX = 1,\n};\n\nenum nl802154_supported_bool_states {\n\tNL802154_SUPPORTED_BOOL_FALSE = 0,\n\tNL802154_SUPPORTED_BOOL_TRUE = 1,\n\t__NL802154_SUPPORTED_BOOL_INVALD = 2,\n\tNL802154_SUPPORTED_BOOL_BOTH = 3,\n\t__NL802154_SUPPORTED_BOOL_AFTER_LAST = 4,\n\tNL802154_SUPPORTED_BOOL_MAX = 3,\n};\n\nstruct wpan_phy_supported {\n\tu32 channels[32];\n\tu32 cca_modes;\n\tu32 cca_opts;\n\tu32 iftypes;\n\tenum nl802154_supported_bool_states lbt;\n\tu8 min_minbe;\n\tu8 max_minbe;\n\tu8 min_maxbe;\n\tu8 max_maxbe;\n\tu8 min_csma_backoffs;\n\tu8 max_csma_backoffs;\n\ts8 min_frame_retries;\n\ts8 max_frame_retries;\n\tsize_t tx_powers_size;\n\tsize_t cca_ed_levels_size;\n\tconst s32 *tx_powers;\n\tconst s32 *cca_ed_levels;\n};\n\nstruct wpan_phy_cca {\n\tenum nl802154_cca_modes mode;\n\tenum nl802154_cca_opts opt;\n};\n\nstruct wpan_phy {\n\tconst void *privid;\n\tu32 flags;\n\tu8 current_channel;\n\tu8 current_page;\n\tstruct wpan_phy_supported supported;\n\ts32 transmit_power;\n\tstruct wpan_phy_cca cca;\n\t__le64 perm_extended_addr;\n\ts32 cca_ed_level;\n\tu8 symbol_duration;\n\tu16 lifs_period;\n\tu16 sifs_period;\n\tstruct device dev;\n\tpossible_net_t _net;\n\tlong: 64;\n\tchar priv[0];\n};\n\nstruct ieee802154_addr {\n\tu8 mode;\n\t__le16 pan_id;\n\tunion {\n\t\t__le16 short_addr;\n\t\t__le64 extended_addr;\n\t};\n};\n\nstruct wpan_dev_header_ops {\n\tint (*create)(struct sk_buff *, struct net_device *, const struct ieee802154_addr *, const struct ieee802154_addr *, unsigned int);\n};\n\nunion fwnet_hwaddr {\n\tu8 u[16];\n\tstruct {\n\t\t__be64 uniq_id;\n\t\tu8 max_rec;\n\t\tu8 sspd;\n\t\t__be16 fifo_hi;\n\t\t__be32 fifo_lo;\n\t} uc;\n};\n\nstruct in6_validator_info {\n\tstruct in6_addr i6vi_addr;\n\tstruct inet6_dev *i6vi_dev;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct ifa6_config {\n\tconst struct in6_addr *pfx;\n\tunsigned int plen;\n\tconst struct in6_addr *peer_pfx;\n\tu32 rt_priority;\n\tu32 ifa_flags;\n\tu32 preferred_lft;\n\tu32 valid_lft;\n\tu16 scope;\n};\n\nenum cleanup_prefix_rt_t {\n\tCLEANUP_PREFIX_RT_NOP = 0,\n\tCLEANUP_PREFIX_RT_DEL = 1,\n\tCLEANUP_PREFIX_RT_EXPIRE = 2,\n};\n\nenum {\n\tIPV6_SADDR_RULE_INIT = 0,\n\tIPV6_SADDR_RULE_LOCAL = 1,\n\tIPV6_SADDR_RULE_SCOPE = 2,\n\tIPV6_SADDR_RULE_PREFERRED = 3,\n\tIPV6_SADDR_RULE_OIF = 4,\n\tIPV6_SADDR_RULE_LABEL = 5,\n\tIPV6_SADDR_RULE_PRIVACY = 6,\n\tIPV6_SADDR_RULE_ORCHID = 7,\n\tIPV6_SADDR_RULE_PREFIX = 8,\n\tIPV6_SADDR_RULE_MAX = 9,\n};\n\nstruct ipv6_saddr_score {\n\tint rule;\n\tint addr_type;\n\tstruct inet6_ifaddr *ifa;\n\tlong unsigned int scorebits[1];\n\tint scopedist;\n\tint matchlen;\n};\n\nstruct ipv6_saddr_dst {\n\tconst struct in6_addr *addr;\n\tint ifindex;\n\tint scope;\n\tint label;\n\tunsigned int prefs;\n};\n\nstruct if6_iter_state {\n\tstruct seq_net_private p;\n\tint bucket;\n\tint offset;\n};\n\nenum addr_type_t {\n\tUNICAST_ADDR = 0,\n\tMULTICAST_ADDR = 1,\n\tANYCAST_ADDR = 2,\n};\n\nstruct inet6_fill_args {\n\tu32 portid;\n\tu32 seq;\n\tint event;\n\tunsigned int flags;\n\tint netnsid;\n\tint ifindex;\n\tenum addr_type_t type;\n};\n\nenum {\n\tDAD_PROCESS = 0,\n\tDAD_BEGIN = 1,\n\tDAD_ABORT = 2,\n};\n\nstruct ifaddrlblmsg {\n\t__u8 ifal_family;\n\t__u8 __ifal_reserved;\n\t__u8 ifal_prefixlen;\n\t__u8 ifal_flags;\n\t__u32 ifal_index;\n\t__u32 ifal_seq;\n};\n\nenum {\n\tIFAL_ADDRESS = 1,\n\tIFAL_LABEL = 2,\n\t__IFAL_MAX = 3,\n};\n\nstruct ip6addrlbl_entry {\n\tstruct in6_addr prefix;\n\tint prefixlen;\n\tint ifindex;\n\tint addrtype;\n\tu32 label;\n\tstruct hlist_node list;\n\tstruct callback_head rcu;\n};\n\nstruct ip6addrlbl_init_table {\n\tconst struct in6_addr *prefix;\n\tint prefixlen;\n\tu32 label;\n};\n\nstruct rd_msg {\n\tstruct icmp6hdr icmph;\n\tstruct in6_addr target;\n\tstruct in6_addr dest;\n\t__u8 opt[0];\n};\n\nstruct fib6_gc_args {\n\tint timeout;\n\tint more;\n};\n\nstruct rt6_exception {\n\tstruct hlist_node hlist;\n\tstruct rt6_info *rt6i;\n\tlong unsigned int stamp;\n\tstruct callback_head rcu;\n};\n\nstruct rt6_rtnl_dump_arg {\n\tstruct sk_buff *skb;\n\tstruct netlink_callback *cb;\n\tstruct net *net;\n\tstruct fib_dump_filter filter;\n};\n\nstruct netevent_redirect {\n\tstruct dst_entry *old;\n\tstruct dst_entry *new;\n\tstruct neighbour *neigh;\n\tconst void *daddr;\n};\n\nstruct trace_event_raw_fib6_table_lookup {\n\tstruct trace_entry ent;\n\tu32 tb_id;\n\tint err;\n\tint oif;\n\tint iif;\n\t__u8 tos;\n\t__u8 scope;\n\t__u8 flags;\n\t__u8 src[16];\n\t__u8 dst[16];\n\tu16 sport;\n\tu16 dport;\n\tu8 proto;\n\tu8 rt_type;\n\tu32 __data_loc_name;\n\t__u8 gw[16];\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_fib6_table_lookup {\n\tu32 name;\n};\n\ntypedef void (*btf_trace_fib6_table_lookup)(void *, const struct net *, const struct fib6_result *, struct fib6_table *, const struct flowi6 *);\n\nenum rt6_nud_state {\n\tRT6_NUD_FAIL_HARD = 4294967293,\n\tRT6_NUD_FAIL_PROBE = 4294967294,\n\tRT6_NUD_FAIL_DO_RR = 4294967295,\n\tRT6_NUD_SUCCEED = 1,\n};\n\nstruct fib6_nh_dm_arg {\n\tstruct net *net;\n\tconst struct in6_addr *saddr;\n\tint oif;\n\tint flags;\n\tstruct fib6_nh *nh;\n};\n\nstruct fib6_nh_frl_arg {\n\tu32 flags;\n\tint oif;\n\tint strict;\n\tint *mpri;\n\tbool *do_rr;\n\tstruct fib6_nh *nh;\n};\n\nstruct fib6_nh_excptn_arg {\n\tstruct rt6_info *rt;\n\tint plen;\n};\n\nstruct fib6_nh_match_arg {\n\tconst struct net_device *dev;\n\tconst struct in6_addr *gw;\n\tstruct fib6_nh *match;\n};\n\nstruct fib6_nh_age_excptn_arg {\n\tstruct fib6_gc_args *gc_args;\n\tlong unsigned int now;\n};\n\nstruct fib6_nh_rd_arg {\n\tstruct fib6_result *res;\n\tstruct flowi6 *fl6;\n\tconst struct in6_addr *gw;\n\tstruct rt6_info **ret;\n};\n\nstruct ip6rd_flowi {\n\tstruct flowi6 fl6;\n\tstruct in6_addr gateway;\n};\n\nstruct fib6_nh_del_cached_rt_arg {\n\tstruct fib6_config *cfg;\n\tstruct fib6_info *f6i;\n};\n\nstruct arg_dev_net_ip {\n\tstruct net_device *dev;\n\tstruct net *net;\n\tstruct in6_addr *addr;\n};\n\nstruct arg_netdev_event {\n\tconst struct net_device *dev;\n\tunion {\n\t\tunsigned char nh_flags;\n\t\tlong unsigned int event;\n\t};\n};\n\nstruct rt6_mtu_change_arg {\n\tstruct net_device *dev;\n\tunsigned int mtu;\n\tstruct fib6_info *f6i;\n};\n\nstruct rt6_nh {\n\tstruct fib6_info *fib6_info;\n\tstruct fib6_config r_cfg;\n\tstruct list_head next;\n};\n\nstruct fib6_nh_exception_dump_walker {\n\tstruct rt6_rtnl_dump_arg *dump;\n\tstruct fib6_info *rt;\n\tunsigned int flags;\n\tunsigned int skip;\n\tunsigned int count;\n};\n\nenum fib6_walk_state {\n\tFWS_L = 0,\n\tFWS_R = 1,\n\tFWS_C = 2,\n\tFWS_U = 3,\n};\n\nstruct fib6_walker {\n\tstruct list_head lh;\n\tstruct fib6_node *root;\n\tstruct fib6_node *node;\n\tstruct fib6_info *leaf;\n\tenum fib6_walk_state state;\n\tunsigned int skip;\n\tunsigned int count;\n\tunsigned int skip_in_node;\n\tint (*func)(struct fib6_walker *);\n\tvoid *args;\n};\n\nstruct fib6_entry_notifier_info {\n\tstruct fib_notifier_info info;\n\tstruct fib6_info *rt;\n\tunsigned int nsiblings;\n};\n\nstruct ipv6_route_iter {\n\tstruct seq_net_private p;\n\tstruct fib6_walker w;\n\tloff_t skip;\n\tstruct fib6_table *tbl;\n\tint sernum;\n};\n\nstruct bpf_iter__ipv6_route {\n\tunion {\n\t\tstruct bpf_iter_meta *meta;\n\t};\n\tunion {\n\t\tstruct fib6_info *rt;\n\t};\n};\n\nstruct fib6_cleaner {\n\tstruct fib6_walker w;\n\tstruct net *net;\n\tint (*func)(struct fib6_info *, void *);\n\tint sernum;\n\tvoid *arg;\n\tbool skip_notify;\n};\n\nenum {\n\tFIB6_NO_SERNUM_CHANGE = 0,\n};\n\nstruct fib6_dump_arg {\n\tstruct net *net;\n\tstruct notifier_block *nb;\n\tstruct netlink_ext_ack *extack;\n};\n\nstruct fib6_nh_pcpu_arg {\n\tstruct fib6_info *from;\n\tconst struct fib6_table *table;\n};\n\nstruct lookup_args {\n\tint offset;\n\tconst struct in6_addr *addr;\n};\n\nstruct ipv6_mreq {\n\tstruct in6_addr ipv6mr_multiaddr;\n\tint ipv6mr_ifindex;\n};\n\nstruct in6_flowlabel_req {\n\tstruct in6_addr flr_dst;\n\t__be32 flr_label;\n\t__u8 flr_action;\n\t__u8 flr_share;\n\t__u16 flr_flags;\n\t__u16 flr_expires;\n\t__u16 flr_linger;\n\t__u32 __flr_pad;\n};\n\nstruct ip6_mtuinfo {\n\tstruct sockaddr_in6 ip6m_addr;\n\t__u32 ip6m_mtu;\n};\n\nstruct nduseroptmsg {\n\tunsigned char nduseropt_family;\n\tunsigned char nduseropt_pad1;\n\tshort unsigned int nduseropt_opts_len;\n\tint nduseropt_ifindex;\n\t__u8 nduseropt_icmp_type;\n\t__u8 nduseropt_icmp_code;\n\tshort unsigned int nduseropt_pad2;\n\tunsigned int nduseropt_pad3;\n};\n\nenum {\n\tNDUSEROPT_UNSPEC = 0,\n\tNDUSEROPT_SRCADDR = 1,\n\t__NDUSEROPT_MAX = 2,\n};\n\nstruct nd_msg {\n\tstruct icmp6hdr icmph;\n\tstruct in6_addr target;\n\t__u8 opt[0];\n};\n\nstruct rs_msg {\n\tstruct icmp6hdr icmph;\n\t__u8 opt[0];\n};\n\nstruct ra_msg {\n\tstruct icmp6hdr icmph;\n\t__be32 reachable_time;\n\t__be32 retrans_timer;\n};\n\nstruct icmp6_filter {\n\t__u32 data[8];\n};\n\nstruct raw6_sock {\n\tstruct inet_sock inet;\n\t__u32 checksum;\n\t__u32 offset;\n\tstruct icmp6_filter filter;\n\t__u32 ip6mr_table;\n\tstruct ipv6_pinfo inet6;\n};\n\nstruct raw6_frag_vec {\n\tstruct msghdr *msg;\n\tint hlen;\n\tchar c[4];\n};\n\nstruct icmpv6_msg {\n\tstruct sk_buff *skb;\n\tint offset;\n\tuint8_t type;\n};\n\nstruct icmp6_err {\n\tint err;\n\tint fatal;\n};\n\nstruct mld_msg {\n\tstruct icmp6hdr mld_hdr;\n\tstruct in6_addr mld_mca;\n};\n\nstruct mld2_grec {\n\t__u8 grec_type;\n\t__u8 grec_auxwords;\n\t__be16 grec_nsrcs;\n\tstruct in6_addr grec_mca;\n\tstruct in6_addr grec_src[0];\n};\n\nstruct mld2_report {\n\tstruct icmp6hdr mld2r_hdr;\n\tstruct mld2_grec mld2r_grec[0];\n};\n\nstruct mld2_query {\n\tstruct icmp6hdr mld2q_hdr;\n\tstruct in6_addr mld2q_mca;\n\t__u8 mld2q_qrv: 3;\n\t__u8 mld2q_suppress: 1;\n\t__u8 mld2q_resv2: 4;\n\t__u8 mld2q_qqic;\n\t__be16 mld2q_nsrcs;\n\tstruct in6_addr mld2q_srcs[0];\n};\n\nstruct igmp6_mc_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n};\n\nstruct igmp6_mcf_iter_state {\n\tstruct seq_net_private p;\n\tstruct net_device *dev;\n\tstruct inet6_dev *idev;\n\tstruct ifmcaddr6 *im;\n};\n\nenum ip6_defrag_users {\n\tIP6_DEFRAG_LOCAL_DELIVER = 0,\n\tIP6_DEFRAG_CONNTRACK_IN = 1,\n\t__IP6_DEFRAG_CONNTRACK_IN = 65536,\n\tIP6_DEFRAG_CONNTRACK_OUT = 65537,\n\t__IP6_DEFRAG_CONNTRACK_OUT = 131072,\n\tIP6_DEFRAG_CONNTRACK_BRIDGE_IN = 131073,\n\t__IP6_DEFRAG_CONNTRACK_BRIDGE_IN = 196608,\n};\n\nstruct frag_queue {\n\tstruct inet_frag_queue q;\n\tint iif;\n\t__u16 nhoffset;\n\tu8 ecn;\n};\n\nstruct tcp6_pseudohdr {\n\tstruct in6_addr saddr;\n\tstruct in6_addr daddr;\n\t__be32 len;\n\t__be32 protocol;\n};\n\nstruct rt0_hdr {\n\tstruct ipv6_rt_hdr rt_hdr;\n\t__u32 reserved;\n\tstruct in6_addr addr[0];\n};\n\nstruct ipv6_rpl_sr_hdr {\n\t__u8 nexthdr;\n\t__u8 hdrlen;\n\t__u8 type;\n\t__u8 segments_left;\n\t__u32 cmpre: 4;\n\t__u32 cmpri: 4;\n\t__u32 reserved: 4;\n\t__u32 pad: 4;\n\t__u32 reserved1: 16;\n\tunion {\n\t\tstruct in6_addr addr[0];\n\t\t__u8 data[0];\n\t} segments;\n};\n\nstruct tlvtype_proc {\n\tint type;\n\tbool (*func)(struct sk_buff *, int);\n};\n\nstruct ip6fl_iter_state {\n\tstruct seq_net_private p;\n\tstruct pid_namespace *pid_ns;\n\tint bucket;\n};\n\nstruct sr6_tlv {\n\t__u8 type;\n\t__u8 len;\n\t__u8 data[0];\n};\n\nenum {\n\tSEG6_ATTR_UNSPEC = 0,\n\tSEG6_ATTR_DST = 1,\n\tSEG6_ATTR_DSTLEN = 2,\n\tSEG6_ATTR_HMACKEYID = 3,\n\tSEG6_ATTR_SECRET = 4,\n\tSEG6_ATTR_SECRETLEN = 5,\n\tSEG6_ATTR_ALGID = 6,\n\tSEG6_ATTR_HMACINFO = 7,\n\t__SEG6_ATTR_MAX = 8,\n};\n\nenum {\n\tSEG6_CMD_UNSPEC = 0,\n\tSEG6_CMD_SETHMAC = 1,\n\tSEG6_CMD_DUMPHMAC = 2,\n\tSEG6_CMD_SET_TUNSRC = 3,\n\tSEG6_CMD_GET_TUNSRC = 4,\n\t__SEG6_CMD_MAX = 5,\n};\n\nstruct xfrm6_protocol {\n\tint (*handler)(struct sk_buff *);\n\tint (*input_handler)(struct sk_buff *, int, __be32, int);\n\tint (*cb_handler)(struct sk_buff *, int);\n\tint (*err_handler)(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32);\n\tstruct xfrm6_protocol *next;\n\tint priority;\n};\n\nstruct br_input_skb_cb {\n\tstruct net_device *brdev;\n\tu16 frag_max_size;\n\tu8 proxyarp_replied: 1;\n\tu8 src_port_isolated: 1;\n};\n\nstruct nf_br_ops {\n\tint (*br_dev_xmit_hook)(struct sk_buff *);\n};\n\nstruct nf_bridge_frag_data;\n\ntypedef struct rt6_info * (*pol_lookup_t)(struct net *, struct fib6_table *, struct flowi6 *, const struct sk_buff *, int);\n\nstruct fib6_rule {\n\tstruct fib_rule common;\n\tstruct rt6key src;\n\tstruct rt6key dst;\n\tu8 tclass;\n};\n\nstruct calipso_doi;\n\nstruct netlbl_calipso_ops {\n\tint (*doi_add)(struct calipso_doi *, struct netlbl_audit *);\n\tvoid (*doi_free)(struct calipso_doi *);\n\tint (*doi_remove)(u32, struct netlbl_audit *);\n\tstruct calipso_doi * (*doi_getdef)(u32);\n\tvoid (*doi_putdef)(struct calipso_doi *);\n\tint (*doi_walk)(u32 *, int (*)(struct calipso_doi *, void *), void *);\n\tint (*sock_getattr)(struct sock *, struct netlbl_lsm_secattr *);\n\tint (*sock_setattr)(struct sock *, const struct calipso_doi *, const struct netlbl_lsm_secattr *);\n\tvoid (*sock_delattr)(struct sock *);\n\tint (*req_setattr)(struct request_sock *, const struct calipso_doi *, const struct netlbl_lsm_secattr *);\n\tvoid (*req_delattr)(struct request_sock *);\n\tint (*opt_getattr)(const unsigned char *, struct netlbl_lsm_secattr *);\n\tunsigned char * (*skbuff_optptr)(const struct sk_buff *);\n\tint (*skbuff_setattr)(struct sk_buff *, const struct calipso_doi *, const struct netlbl_lsm_secattr *);\n\tint (*skbuff_delattr)(struct sk_buff *);\n\tvoid (*cache_invalidate)();\n\tint (*cache_add)(const unsigned char *, const struct netlbl_lsm_secattr *);\n};\n\nstruct calipso_doi {\n\tu32 doi;\n\tu32 type;\n\trefcount_t refcount;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct calipso_map_cache_bkt {\n\tspinlock_t lock;\n\tu32 size;\n\tstruct list_head list;\n};\n\nstruct calipso_map_cache_entry {\n\tu32 hash;\n\tunsigned char *key;\n\tsize_t key_len;\n\tstruct netlbl_lsm_cache *lsm_data;\n\tu32 activity;\n\tstruct list_head list;\n};\n\nenum {\n\tSEG6_IPTUNNEL_UNSPEC = 0,\n\tSEG6_IPTUNNEL_SRH = 1,\n\t__SEG6_IPTUNNEL_MAX = 2,\n};\n\nstruct seg6_iptunnel_encap {\n\tint mode;\n\tstruct ipv6_sr_hdr srh[0];\n};\n\nenum {\n\tSEG6_IPTUN_MODE_INLINE = 0,\n\tSEG6_IPTUN_MODE_ENCAP = 1,\n\tSEG6_IPTUN_MODE_L2ENCAP = 2,\n};\n\nstruct seg6_lwt {\n\tstruct dst_cache cache;\n\tstruct seg6_iptunnel_encap tuninfo[0];\n};\n\nenum {\n\tSEG6_LOCAL_UNSPEC = 0,\n\tSEG6_LOCAL_ACTION = 1,\n\tSEG6_LOCAL_SRH = 2,\n\tSEG6_LOCAL_TABLE = 3,\n\tSEG6_LOCAL_NH4 = 4,\n\tSEG6_LOCAL_NH6 = 5,\n\tSEG6_LOCAL_IIF = 6,\n\tSEG6_LOCAL_OIF = 7,\n\tSEG6_LOCAL_BPF = 8,\n\t__SEG6_LOCAL_MAX = 9,\n};\n\nenum {\n\tSEG6_LOCAL_BPF_PROG_UNSPEC = 0,\n\tSEG6_LOCAL_BPF_PROG = 1,\n\tSEG6_LOCAL_BPF_PROG_NAME = 2,\n\t__SEG6_LOCAL_BPF_PROG_MAX = 3,\n};\n\nstruct seg6_local_lwt;\n\nstruct seg6_action_desc {\n\tint action;\n\tlong unsigned int attrs;\n\tint (*input)(struct sk_buff *, struct seg6_local_lwt *);\n\tint static_headroom;\n};\n\nstruct seg6_local_lwt {\n\tint action;\n\tstruct ipv6_sr_hdr *srh;\n\tint table;\n\tstruct in_addr nh4;\n\tstruct in6_addr nh6;\n\tint iif;\n\tint oif;\n\tstruct bpf_lwt_prog bpf;\n\tint headroom;\n\tstruct seg6_action_desc *desc;\n};\n\nstruct seg6_action_param {\n\tint (*parse)(struct nlattr **, struct seg6_local_lwt *);\n\tint (*put)(struct sk_buff *, struct seg6_local_lwt *);\n\tint (*cmp)(struct seg6_local_lwt *, struct seg6_local_lwt *);\n};\n\nstruct ah_data {\n\tint icv_full_len;\n\tint icv_trunc_len;\n\tstruct crypto_ahash *ahash;\n};\n\nstruct tmp_ext {\n\tstruct in6_addr daddr;\n\tchar hdrs[0];\n};\n\nstruct ah_skb_cb {\n\tstruct xfrm_skb_cb xfrm;\n\tvoid *tmp;\n};\n\nstruct ip_esp_hdr {\n\t__be32 spi;\n\t__be32 seq_no;\n\t__u8 enc_data[0];\n};\n\nstruct esp_info {\n\tstruct ip_esp_hdr *esph;\n\t__be64 seqno;\n\tint tfclen;\n\tint tailen;\n\tint plen;\n\tint clen;\n\tint len;\n\tint nfrags;\n\t__u8 proto;\n\tbool inplace;\n};\n\nstruct esp_skb_cb {\n\tstruct xfrm_skb_cb xfrm;\n\tvoid *tmp;\n};\n\nstruct esp_output_extra {\n\t__be32 seqhi;\n\tu32 esphoff;\n};\n\nstruct ip6t_standard {\n\tstruct ip6t_entry entry;\n\tstruct xt_standard_target target;\n};\n\nstruct ip6t_error {\n\tstruct ip6t_entry entry;\n\tstruct xt_error_target target;\n};\n\nstruct ip6t_icmp {\n\t__u8 type;\n\t__u8 code[2];\n\t__u8 invflags;\n};\n\nstruct ip6t_getinfo {\n\tchar name[32];\n\tunsigned int valid_hooks;\n\tunsigned int hook_entry[5];\n\tunsigned int underflow[5];\n\tunsigned int num_entries;\n\tunsigned int size;\n};\n\nstruct ip6t_replace {\n\tchar name[32];\n\tunsigned int valid_hooks;\n\tunsigned int num_entries;\n\tunsigned int size;\n\tunsigned int hook_entry[5];\n\tunsigned int underflow[5];\n\tunsigned int num_counters;\n\tstruct xt_counters *counters;\n\tstruct ip6t_entry entries[0];\n};\n\nstruct ip6t_get_entries {\n\tchar name[32];\n\tunsigned int size;\n\tstruct ip6t_entry entrytable[0];\n};\n\nstruct compat_ip6t_entry {\n\tstruct ip6t_ip6 ipv6;\n\tcompat_uint_t nfcache;\n\t__u16 target_offset;\n\t__u16 next_offset;\n\tcompat_uint_t comefrom;\n\tstruct compat_xt_counters counters;\n\tunsigned char elems[0];\n} __attribute__((packed));\n\nstruct compat_ip6t_replace {\n\tchar name[32];\n\tu32 valid_hooks;\n\tu32 num_entries;\n\tu32 size;\n\tu32 hook_entry[5];\n\tu32 underflow[5];\n\tu32 num_counters;\n\tcompat_uptr_t counters;\n\tstruct compat_ip6t_entry entries[0];\n} __attribute__((packed));\n\nstruct compat_ip6t_get_entries {\n\tchar name[32];\n\tcompat_uint_t size;\n\tstruct compat_ip6t_entry entrytable[0];\n} __attribute__((packed));\n\nstruct ip6t_ipv6header_info {\n\t__u8 matchflags;\n\t__u8 invflags;\n\t__u8 modeflag;\n};\n\nenum ip6t_reject_with {\n\tIP6T_ICMP6_NO_ROUTE = 0,\n\tIP6T_ICMP6_ADM_PROHIBITED = 1,\n\tIP6T_ICMP6_NOT_NEIGHBOUR = 2,\n\tIP6T_ICMP6_ADDR_UNREACH = 3,\n\tIP6T_ICMP6_PORT_UNREACH = 4,\n\tIP6T_ICMP6_ECHOREPLY = 5,\n\tIP6T_TCP_RESET = 6,\n\tIP6T_ICMP6_POLICY_FAIL = 7,\n\tIP6T_ICMP6_REJECT_ROUTE = 8,\n};\n\nstruct ip6t_reject_info {\n\t__u32 with;\n};\n\nenum {\n\tIFLA_IPTUN_UNSPEC = 0,\n\tIFLA_IPTUN_LINK = 1,\n\tIFLA_IPTUN_LOCAL = 2,\n\tIFLA_IPTUN_REMOTE = 3,\n\tIFLA_IPTUN_TTL = 4,\n\tIFLA_IPTUN_TOS = 5,\n\tIFLA_IPTUN_ENCAP_LIMIT = 6,\n\tIFLA_IPTUN_FLOWINFO = 7,\n\tIFLA_IPTUN_FLAGS = 8,\n\tIFLA_IPTUN_PROTO = 9,\n\tIFLA_IPTUN_PMTUDISC = 10,\n\tIFLA_IPTUN_6RD_PREFIX = 11,\n\tIFLA_IPTUN_6RD_RELAY_PREFIX = 12,\n\tIFLA_IPTUN_6RD_PREFIXLEN = 13,\n\tIFLA_IPTUN_6RD_RELAY_PREFIXLEN = 14,\n\tIFLA_IPTUN_ENCAP_TYPE = 15,\n\tIFLA_IPTUN_ENCAP_FLAGS = 16,\n\tIFLA_IPTUN_ENCAP_SPORT = 17,\n\tIFLA_IPTUN_ENCAP_DPORT = 18,\n\tIFLA_IPTUN_COLLECT_METADATA = 19,\n\tIFLA_IPTUN_FWMARK = 20,\n\t__IFLA_IPTUN_MAX = 21,\n};\n\nstruct ip_tunnel_prl {\n\t__be32 addr;\n\t__u16 flags;\n\t__u16 __reserved;\n\t__u32 datalen;\n\t__u32 __reserved2;\n};\n\nstruct sit_net {\n\tstruct ip_tunnel *tunnels_r_l[16];\n\tstruct ip_tunnel *tunnels_r[16];\n\tstruct ip_tunnel *tunnels_l[16];\n\tstruct ip_tunnel *tunnels_wc[1];\n\tstruct ip_tunnel **tunnels[4];\n\tstruct net_device *fb_tunnel_dev;\n};\n\nenum {\n\tIP6_FH_F_FRAG = 1,\n\tIP6_FH_F_AUTH = 2,\n\tIP6_FH_F_SKIP_RH = 4,\n};\n\ntypedef void ip6_icmp_send_t(struct sk_buff *, u8, u8, __u32, const struct in6_addr *);\n\nstruct sockaddr_pkt {\n\tshort unsigned int spkt_family;\n\tunsigned char spkt_device[14];\n\t__be16 spkt_protocol;\n};\n\nstruct sockaddr_ll {\n\tshort unsigned int sll_family;\n\t__be16 sll_protocol;\n\tint sll_ifindex;\n\tshort unsigned int sll_hatype;\n\tunsigned char sll_pkttype;\n\tunsigned char sll_halen;\n\tunsigned char sll_addr[8];\n};\n\nstruct tpacket_stats {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n};\n\nstruct tpacket_stats_v3 {\n\tunsigned int tp_packets;\n\tunsigned int tp_drops;\n\tunsigned int tp_freeze_q_cnt;\n};\n\nstruct tpacket_rollover_stats {\n\t__u64 tp_all;\n\t__u64 tp_huge;\n\t__u64 tp_failed;\n};\n\nunion tpacket_stats_u {\n\tstruct tpacket_stats stats1;\n\tstruct tpacket_stats_v3 stats3;\n};\n\nstruct tpacket_auxdata {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n};\n\nstruct tpacket_hdr {\n\tlong unsigned int tp_status;\n\tunsigned int tp_len;\n\tunsigned int tp_snaplen;\n\tshort unsigned int tp_mac;\n\tshort unsigned int tp_net;\n\tunsigned int tp_sec;\n\tunsigned int tp_usec;\n};\n\nstruct tpacket2_hdr {\n\t__u32 tp_status;\n\t__u32 tp_len;\n\t__u32 tp_snaplen;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u16 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u8 tp_padding[4];\n};\n\nstruct tpacket_hdr_variant1 {\n\t__u32 tp_rxhash;\n\t__u32 tp_vlan_tci;\n\t__u16 tp_vlan_tpid;\n\t__u16 tp_padding;\n};\n\nstruct tpacket3_hdr {\n\t__u32 tp_next_offset;\n\t__u32 tp_sec;\n\t__u32 tp_nsec;\n\t__u32 tp_snaplen;\n\t__u32 tp_len;\n\t__u32 tp_status;\n\t__u16 tp_mac;\n\t__u16 tp_net;\n\tunion {\n\t\tstruct tpacket_hdr_variant1 hv1;\n\t};\n\t__u8 tp_padding[8];\n};\n\nstruct tpacket_bd_ts {\n\tunsigned int ts_sec;\n\tunion {\n\t\tunsigned int ts_usec;\n\t\tunsigned int ts_nsec;\n\t};\n};\n\nstruct tpacket_hdr_v1 {\n\t__u32 block_status;\n\t__u32 num_pkts;\n\t__u32 offset_to_first_pkt;\n\t__u32 blk_len;\n\t__u64 seq_num;\n\tstruct tpacket_bd_ts ts_first_pkt;\n\tstruct tpacket_bd_ts ts_last_pkt;\n};\n\nunion tpacket_bd_header_u {\n\tstruct tpacket_hdr_v1 bh1;\n};\n\nstruct tpacket_block_desc {\n\t__u32 version;\n\t__u32 offset_to_priv;\n\tunion tpacket_bd_header_u hdr;\n};\n\nenum tpacket_versions {\n\tTPACKET_V1 = 0,\n\tTPACKET_V2 = 1,\n\tTPACKET_V3 = 2,\n};\n\nstruct tpacket_req {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n};\n\nstruct tpacket_req3 {\n\tunsigned int tp_block_size;\n\tunsigned int tp_block_nr;\n\tunsigned int tp_frame_size;\n\tunsigned int tp_frame_nr;\n\tunsigned int tp_retire_blk_tov;\n\tunsigned int tp_sizeof_priv;\n\tunsigned int tp_feature_req_word;\n};\n\nunion tpacket_req_u {\n\tstruct tpacket_req req;\n\tstruct tpacket_req3 req3;\n};\n\ntypedef __u16 __virtio16;\n\nstruct virtio_net_hdr {\n\t__u8 flags;\n\t__u8 gso_type;\n\t__virtio16 hdr_len;\n\t__virtio16 gso_size;\n\t__virtio16 csum_start;\n\t__virtio16 csum_offset;\n};\n\nstruct packet_mclist {\n\tstruct packet_mclist *next;\n\tint ifindex;\n\tint count;\n\tshort unsigned int type;\n\tshort unsigned int alen;\n\tunsigned char addr[32];\n};\n\nstruct pgv;\n\nstruct tpacket_kbdq_core {\n\tstruct pgv *pkbdq;\n\tunsigned int feature_req_word;\n\tunsigned int hdrlen;\n\tunsigned char reset_pending_on_curr_blk;\n\tunsigned char delete_blk_timer;\n\tshort unsigned int kactive_blk_num;\n\tshort unsigned int blk_sizeof_priv;\n\tshort unsigned int last_kactive_blk_num;\n\tchar *pkblk_start;\n\tchar *pkblk_end;\n\tint kblk_size;\n\tunsigned int max_frame_len;\n\tunsigned int knum_blocks;\n\tuint64_t knxt_seq_num;\n\tchar *prev;\n\tchar *nxt_offset;\n\tstruct sk_buff *skb;\n\tatomic_t blk_fill_in_prog;\n\tshort unsigned int retire_blk_tov;\n\tshort unsigned int version;\n\tlong unsigned int tov_in_jiffies;\n\tstruct timer_list retire_blk_timer;\n};\n\nstruct pgv {\n\tchar *buffer;\n};\n\nstruct packet_ring_buffer {\n\tstruct pgv *pg_vec;\n\tunsigned int head;\n\tunsigned int frames_per_block;\n\tunsigned int frame_size;\n\tunsigned int frame_max;\n\tunsigned int pg_vec_order;\n\tunsigned int pg_vec_pages;\n\tunsigned int pg_vec_len;\n\tunsigned int *pending_refcnt;\n\tunion {\n\t\tlong unsigned int *rx_owner_map;\n\t\tstruct tpacket_kbdq_core prb_bdqc;\n\t};\n};\n\nstruct packet_fanout {\n\tpossible_net_t net;\n\tunsigned int num_members;\n\tu16 id;\n\tu8 type;\n\tu8 flags;\n\tunion {\n\t\tatomic_t rr_cur;\n\t\tstruct bpf_prog *bpf_prog;\n\t};\n\tstruct list_head list;\n\tstruct sock *arr[256];\n\tspinlock_t lock;\n\trefcount_t sk_ref;\n\tlong: 64;\n\tlong: 64;\n\tstruct packet_type prot_hook;\n};\n\nstruct packet_rollover {\n\tint sock;\n\tatomic_long_t num;\n\tatomic_long_t num_huge;\n\tatomic_long_t num_failed;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 history[16];\n};\n\nstruct packet_sock {\n\tstruct sock sk;\n\tstruct packet_fanout *fanout;\n\tunion tpacket_stats_u stats;\n\tstruct packet_ring_buffer rx_ring;\n\tstruct packet_ring_buffer tx_ring;\n\tint copy_thresh;\n\tspinlock_t bind_lock;\n\tstruct mutex pg_vec_lock;\n\tunsigned int running;\n\tunsigned int auxdata: 1;\n\tunsigned int origdev: 1;\n\tunsigned int has_vnet_hdr: 1;\n\tunsigned int tp_loss: 1;\n\tunsigned int tp_tx_has_off: 1;\n\tint pressure;\n\tint ifindex;\n\t__be16 num;\n\tstruct packet_rollover *rollover;\n\tstruct packet_mclist *mclist;\n\tatomic_t mapped;\n\tenum tpacket_versions tp_version;\n\tunsigned int tp_hdrlen;\n\tunsigned int tp_reserve;\n\tunsigned int tp_tstamp;\n\tstruct completion skb_completion;\n\tstruct net_device *cached_dev;\n\tint (*xmit)(struct sk_buff *);\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tstruct packet_type prot_hook;\n\tatomic_t tp_drops;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct packet_mreq_max {\n\tint mr_ifindex;\n\tshort unsigned int mr_type;\n\tshort unsigned int mr_alen;\n\tunsigned char mr_address[32];\n};\n\nunion tpacket_uhdr {\n\tstruct tpacket_hdr *h1;\n\tstruct tpacket2_hdr *h2;\n\tstruct tpacket3_hdr *h3;\n\tvoid *raw;\n};\n\nstruct packet_skb_cb {\n\tunion {\n\t\tstruct sockaddr_pkt pkt;\n\t\tunion {\n\t\t\tunsigned int origlen;\n\t\t\tstruct sockaddr_ll ll;\n\t\t};\n\t} sa;\n};\n\nenum rpc_msg_type {\n\tRPC_CALL = 0,\n\tRPC_REPLY = 1,\n};\n\nenum rpc_reply_stat {\n\tRPC_MSG_ACCEPTED = 0,\n\tRPC_MSG_DENIED = 1,\n};\n\nenum rpc_reject_stat {\n\tRPC_MISMATCH = 0,\n\tRPC_AUTH_ERROR = 1,\n};\n\nenum {\n\tSUNRPC_PIPEFS_NFS_PRIO = 0,\n\tSUNRPC_PIPEFS_RPC_PRIO = 1,\n};\n\nenum {\n\tRPC_PIPEFS_MOUNT = 0,\n\tRPC_PIPEFS_UMOUNT = 1,\n};\n\nstruct rpc_add_xprt_test {\n\tvoid (*add_xprt_test)(struct rpc_clnt *, struct rpc_xprt *, void *);\n\tvoid *data;\n};\n\nstruct sunrpc_net {\n\tstruct proc_dir_entry *proc_net_rpc;\n\tstruct cache_detail *ip_map_cache;\n\tstruct cache_detail *unix_gid_cache;\n\tstruct cache_detail *rsc_cache;\n\tstruct cache_detail *rsi_cache;\n\tstruct super_block *pipefs_sb;\n\tstruct rpc_pipe *gssd_dummy;\n\tstruct mutex pipefs_sb_lock;\n\tstruct list_head all_clients;\n\tspinlock_t rpc_client_lock;\n\tstruct rpc_clnt *rpcb_local_clnt;\n\tstruct rpc_clnt *rpcb_local_clnt4;\n\tspinlock_t rpcb_clnt_lock;\n\tunsigned int rpcb_users;\n\tunsigned int rpcb_is_af_local: 1;\n\tstruct mutex gssp_lock;\n\tstruct rpc_clnt *gssp_clnt;\n\tint use_gss_proxy;\n\tint pipe_version;\n\tatomic_t pipe_users;\n\tstruct proc_dir_entry *use_gssp_proc;\n};\n\nstruct rpc_cb_add_xprt_calldata {\n\tstruct rpc_xprt_switch *xps;\n\tstruct rpc_xprt *xprt;\n};\n\nstruct connect_timeout_data {\n\tlong unsigned int connect_timeout;\n\tlong unsigned int reconnect_timeout;\n};\n\nstruct xprt_class {\n\tstruct list_head list;\n\tint ident;\n\tstruct rpc_xprt * (*setup)(struct xprt_create *);\n\tstruct module *owner;\n\tchar name[32];\n};\n\nenum xprt_xid_rb_cmp {\n\tXID_RB_EQUAL = 0,\n\tXID_RB_LEFT = 1,\n\tXID_RB_RIGHT = 2,\n};\n\ntypedef __be32 rpc_fraghdr;\n\nstruct xdr_skb_reader {\n\tstruct sk_buff *skb;\n\tunsigned int offset;\n\tsize_t count;\n\t__wsum csum;\n};\n\ntypedef size_t (*xdr_skb_read_actor)(struct xdr_skb_reader *, void *, size_t);\n\nstruct svc_sock {\n\tstruct svc_xprt sk_xprt;\n\tstruct socket *sk_sock;\n\tstruct sock *sk_sk;\n\tvoid (*sk_ostate)(struct sock *);\n\tvoid (*sk_odata)(struct sock *);\n\tvoid (*sk_owspace)(struct sock *);\n\t__be32 sk_marker;\n\tu32 sk_tcplen;\n\tu32 sk_datalen;\n\tstruct page *sk_pages[259];\n};\n\nstruct sock_xprt {\n\tstruct rpc_xprt xprt;\n\tstruct socket *sock;\n\tstruct sock *inet;\n\tstruct file *file;\n\tstruct {\n\t\tstruct {\n\t\t\t__be32 fraghdr;\n\t\t\t__be32 xid;\n\t\t\t__be32 calldir;\n\t\t};\n\t\tu32 offset;\n\t\tu32 len;\n\t\tlong unsigned int copied;\n\t} recv;\n\tstruct {\n\t\tu32 offset;\n\t} xmit;\n\tlong unsigned int sock_state;\n\tstruct delayed_work connect_worker;\n\tstruct work_struct error_worker;\n\tstruct work_struct recv_worker;\n\tstruct mutex recv_mutex;\n\tstruct __kernel_sockaddr_storage srcaddr;\n\tshort unsigned int srcport;\n\tint xprt_err;\n\tsize_t rcvsize;\n\tsize_t sndsize;\n\tstruct rpc_timeout tcp_timeout;\n\tvoid (*old_data_ready)(struct sock *);\n\tvoid (*old_state_change)(struct sock *);\n\tvoid (*old_write_space)(struct sock *);\n\tvoid (*old_error_report)(struct sock *);\n};\n\nstruct rpc_buffer {\n\tsize_t len;\n\tchar data[0];\n};\n\ntypedef void (*rpc_action)(struct rpc_task *);\n\nstruct trace_event_raw_rpc_xdr_buf_class {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_class {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_new {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tu32 __data_loc_program;\n\tu32 __data_loc_server;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_new_err {\n\tstruct trace_entry ent;\n\tint error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_server;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_clnt_clone_err {\n\tstruct trace_entry ent;\n\tunsigned int client_id;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_status {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_request {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tbool async;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_running {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tconst void *action;\n\tlong unsigned int runstate;\n\tint status;\n\tshort unsigned int flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_task_queued {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tlong unsigned int timeout;\n\tlong unsigned int runstate;\n\tint status;\n\tshort unsigned int flags;\n\tu32 __data_loc_q_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_failure {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_reply_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 __data_loc_progname;\n\tu32 version;\n\tu32 __data_loc_procname;\n\tu32 __data_loc_servername;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_call_rpcerror {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint tk_status;\n\tint rpc_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_stats_latency {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tint version;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procname;\n\tlong unsigned int backlog;\n\tlong unsigned int rtt;\n\tlong unsigned int execute;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_overflow {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tsize_t requested;\n\tconst void *end;\n\tconst void *p;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int len;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xdr_alignment {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tint version;\n\tsize_t offset;\n\tunsigned int copied;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int len;\n\tu32 __data_loc_progname;\n\tu32 __data_loc_procedure;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_socket_event {\n\tstruct trace_entry ent;\n\tunsigned int socket_state;\n\tunsigned int sock_state;\n\tlong long unsigned int ino;\n\tu32 __data_loc_dstaddr;\n\tu32 __data_loc_dstport;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_socket_event_done {\n\tstruct trace_entry ent;\n\tint error;\n\tunsigned int socket_state;\n\tunsigned int sock_state;\n\tlong long unsigned int ino;\n\tu32 __data_loc_dstaddr;\n\tu32 __data_loc_dstport;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xprt_lifetime_class {\n\tstruct trace_entry ent;\n\tlong unsigned int state;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpc_xprt_event {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tint status;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_transmit {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seqno;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_enq_xmit {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seqno;\n\tint stage;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_ping {\n\tstruct trace_entry ent;\n\tint status;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_writelock_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int snd_task_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xprt_cong_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tunsigned int snd_task_id;\n\tlong unsigned int cong;\n\tlong unsigned int cwnd;\n\tbool wait;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_stream_read_data {\n\tstruct trace_entry ent;\n\tssize_t err;\n\tsize_t total;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_xs_stream_read_request {\n\tstruct trace_entry ent;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_port;\n\tu32 xid;\n\tlong unsigned int copied;\n\tunsigned int reclen;\n\tunsigned int offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xdr_buf_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tconst void *head_base;\n\tsize_t head_len;\n\tconst void *tail_base;\n\tsize_t tail_len;\n\tunsigned int page_len;\n\tunsigned int msg_len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_recv {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tint len;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_authenticate {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tlong unsigned int svc_status;\n\tlong unsigned int auth_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_process {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 vers;\n\tu32 proc;\n\tu32 __data_loc_service;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_rqst_event {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_rqst_status {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tint status;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_create_err {\n\tstruct trace_entry ent;\n\tlong int error;\n\tu32 __data_loc_program;\n\tu32 __data_loc_protocol;\n\tunsigned char addr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_do_enqueue {\n\tstruct trace_entry ent;\n\tint pid;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_event {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_accept {\n\tstruct trace_entry ent;\n\tu32 __data_loc_addr;\n\tu32 __data_loc_protocol;\n\tu32 __data_loc_service;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_xprt_dequeue {\n\tstruct trace_entry ent;\n\tlong unsigned int flags;\n\tlong unsigned int wakeup;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_wake_up {\n\tstruct trace_entry ent;\n\tint pid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_handle_xprt {\n\tstruct trace_entry ent;\n\tint len;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_stats_latency {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tlong unsigned int execute;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_deferred_event {\n\tstruct trace_entry ent;\n\tconst void *dr;\n\tu32 xid;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_new_socket {\n\tstruct trace_entry ent;\n\tlong unsigned int type;\n\tlong unsigned int family;\n\tbool listener;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_marker {\n\tstruct trace_entry ent;\n\tunsigned int length;\n\tbool last;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_class {\n\tstruct trace_entry ent;\n\tssize_t result;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_tcp_recv_short {\n\tstruct trace_entry ent;\n\tu32 expected;\n\tu32 received;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_tcp_state {\n\tstruct trace_entry ent;\n\tlong unsigned int socket_state;\n\tlong unsigned int sock_state;\n\tlong unsigned int flags;\n\tu32 __data_loc_addr;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svcsock_accept_class {\n\tstruct trace_entry ent;\n\tlong int status;\n\tu32 __data_loc_service;\n\tunsigned char addr[28];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cache_event {\n\tstruct trace_entry ent;\n\tconst struct cache_head *h;\n\tu32 __data_loc_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_register_class {\n\tstruct trace_entry ent;\n\tu32 version;\n\tlong unsigned int family;\n\tshort unsigned int protocol;\n\tshort unsigned int port;\n\tint error;\n\tu32 __data_loc_program;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_svc_unregister {\n\tstruct trace_entry ent;\n\tu32 version;\n\tint error;\n\tu32 __data_loc_program;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_rpc_xdr_buf_class {};\n\nstruct trace_event_data_offsets_rpc_clnt_class {};\n\nstruct trace_event_data_offsets_rpc_clnt_new {\n\tu32 addr;\n\tu32 port;\n\tu32 program;\n\tu32 server;\n};\n\nstruct trace_event_data_offsets_rpc_clnt_new_err {\n\tu32 program;\n\tu32 server;\n};\n\nstruct trace_event_data_offsets_rpc_clnt_clone_err {};\n\nstruct trace_event_data_offsets_rpc_task_status {};\n\nstruct trace_event_data_offsets_rpc_request {\n\tu32 progname;\n\tu32 procname;\n};\n\nstruct trace_event_data_offsets_rpc_task_running {};\n\nstruct trace_event_data_offsets_rpc_task_queued {\n\tu32 q_name;\n};\n\nstruct trace_event_data_offsets_rpc_failure {};\n\nstruct trace_event_data_offsets_rpc_reply_event {\n\tu32 progname;\n\tu32 procname;\n\tu32 servername;\n};\n\nstruct trace_event_data_offsets_rpc_call_rpcerror {};\n\nstruct trace_event_data_offsets_rpc_stats_latency {\n\tu32 progname;\n\tu32 procname;\n};\n\nstruct trace_event_data_offsets_rpc_xdr_overflow {\n\tu32 progname;\n\tu32 procedure;\n};\n\nstruct trace_event_data_offsets_rpc_xdr_alignment {\n\tu32 progname;\n\tu32 procedure;\n};\n\nstruct trace_event_data_offsets_xs_socket_event {\n\tu32 dstaddr;\n\tu32 dstport;\n};\n\nstruct trace_event_data_offsets_xs_socket_event_done {\n\tu32 dstaddr;\n\tu32 dstport;\n};\n\nstruct trace_event_data_offsets_rpc_xprt_lifetime_class {\n\tu32 addr;\n\tu32 port;\n};\n\nstruct trace_event_data_offsets_rpc_xprt_event {\n\tu32 addr;\n\tu32 port;\n};\n\nstruct trace_event_data_offsets_xprt_transmit {};\n\nstruct trace_event_data_offsets_xprt_enq_xmit {};\n\nstruct trace_event_data_offsets_xprt_ping {\n\tu32 addr;\n\tu32 port;\n};\n\nstruct trace_event_data_offsets_xprt_writelock_event {};\n\nstruct trace_event_data_offsets_xprt_cong_event {};\n\nstruct trace_event_data_offsets_xs_stream_read_data {\n\tu32 addr;\n\tu32 port;\n};\n\nstruct trace_event_data_offsets_xs_stream_read_request {\n\tu32 addr;\n\tu32 port;\n};\n\nstruct trace_event_data_offsets_svc_xdr_buf_class {};\n\nstruct trace_event_data_offsets_svc_recv {\n\tu32 addr;\n};\n\nstruct trace_event_data_offsets_svc_authenticate {};\n\nstruct trace_event_data_offsets_svc_process {\n\tu32 service;\n\tu32 addr;\n};\n\nstruct trace_event_data_offsets_svc_rqst_event {\n\tu32 addr;\n};\n\nstruct trace_event_data_offsets_svc_rqst_status {\n\tu32 addr;\n};\n\nstruct trace_event_data_offsets_svc_xprt_create_err {\n\tu32 program;\n\tu32 protocol;\n};\n\nstruct trace_event_data_offsets_svc_xprt_do_enqueue {\n\tu32 addr;\n};\n\nstruct trace_event_data_offsets_svc_xprt_event {\n\tu32 addr;\n};\n\nstruct trace_event_data_offsets_svc_xprt_accept {\n\tu32 addr;\n\tu32 protocol;\n\tu32 service;\n};\n\nstruct trace_event_data_offsets_svc_xprt_dequeue {\n\tu32 addr;\n};\n\nstruct trace_event_data_offsets_svc_wake_up {};\n\nstruct trace_event_data_offsets_svc_handle_xprt {\n\tu32 addr;\n};\n\nstruct trace_event_data_offsets_svc_stats_latency {\n\tu32 addr;\n};\n\nstruct trace_event_data_offsets_svc_deferred_event {\n\tu32 addr;\n};\n\nstruct trace_event_data_offsets_svcsock_new_socket {};\n\nstruct trace_event_data_offsets_svcsock_marker {\n\tu32 addr;\n};\n\nstruct trace_event_data_offsets_svcsock_class {\n\tu32 addr;\n};\n\nstruct trace_event_data_offsets_svcsock_tcp_recv_short {\n\tu32 addr;\n};\n\nstruct trace_event_data_offsets_svcsock_tcp_state {\n\tu32 addr;\n};\n\nstruct trace_event_data_offsets_svcsock_accept_class {\n\tu32 service;\n};\n\nstruct trace_event_data_offsets_cache_event {\n\tu32 name;\n};\n\nstruct trace_event_data_offsets_register_class {\n\tu32 program;\n};\n\nstruct trace_event_data_offsets_svc_unregister {\n\tu32 program;\n};\n\ntypedef void (*btf_trace_rpc_xdr_sendto)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpc_xdr_recvfrom)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpc_xdr_reply_pages)(void *, const struct rpc_task *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_rpc_clnt_free)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_killall)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_shutdown)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_release)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_replace_xprt)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_replace_xprt_err)(void *, const struct rpc_clnt *);\n\ntypedef void (*btf_trace_rpc_clnt_new)(void *, const struct rpc_clnt *, const struct rpc_xprt *, const char *, const char *);\n\ntypedef void (*btf_trace_rpc_clnt_new_err)(void *, const char *, const char *, int);\n\ntypedef void (*btf_trace_rpc_clnt_clone_err)(void *, const struct rpc_clnt *, int);\n\ntypedef void (*btf_trace_rpc_call_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_bind_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_connect_status)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_request)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_task_begin)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_run_action)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_complete)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_signalled)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_end)(void *, const struct rpc_task *, const void *);\n\ntypedef void (*btf_trace_rpc_task_sleep)(void *, const struct rpc_task *, const struct rpc_wait_queue *);\n\ntypedef void (*btf_trace_rpc_task_wakeup)(void *, const struct rpc_task *, const struct rpc_wait_queue *);\n\ntypedef void (*btf_trace_rpc_bad_callhdr)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_bad_verifier)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__prog_unavail)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__prog_mismatch)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__proc_unavail)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__garbage_args)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__unparsable)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__mismatch)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__stale_creds)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__bad_creds)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc__auth_tooweak)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpc_call_rpcerror)(void *, const struct rpc_task *, int, int);\n\ntypedef void (*btf_trace_rpc_stats_latency)(void *, const struct rpc_task *, ktime_t, ktime_t, ktime_t);\n\ntypedef void (*btf_trace_rpc_xdr_overflow)(void *, const struct xdr_stream *, size_t);\n\ntypedef void (*btf_trace_rpc_xdr_alignment)(void *, const struct xdr_stream *, size_t, unsigned int);\n\ntypedef void (*btf_trace_rpc_socket_state_change)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_socket_connect)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_error)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_reset_connection)(void *, struct rpc_xprt *, struct socket *, int);\n\ntypedef void (*btf_trace_rpc_socket_close)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_rpc_socket_shutdown)(void *, struct rpc_xprt *, struct socket *);\n\ntypedef void (*btf_trace_xprt_create)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_auto)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_done)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_force)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_disconnect_cleanup)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_destroy)(void *, const struct rpc_xprt *);\n\ntypedef void (*btf_trace_xprt_timer)(void *, const struct rpc_xprt *, __be32, int);\n\ntypedef void (*btf_trace_xprt_lookup_rqst)(void *, const struct rpc_xprt *, __be32, int);\n\ntypedef void (*btf_trace_xprt_complete_rqst)(void *, const struct rpc_xprt *, __be32, int);\n\ntypedef void (*btf_trace_xprt_transmit)(void *, const struct rpc_rqst *, int);\n\ntypedef void (*btf_trace_xprt_enq_xmit)(void *, const struct rpc_task *, int);\n\ntypedef void (*btf_trace_xprt_ping)(void *, const struct rpc_xprt *, int);\n\ntypedef void (*btf_trace_xprt_reserve_xprt)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_release_xprt)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_reserve_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_release_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_get_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xprt_put_cong)(void *, const struct rpc_xprt *, const struct rpc_task *);\n\ntypedef void (*btf_trace_xs_stream_read_data)(void *, struct rpc_xprt *, ssize_t, size_t);\n\ntypedef void (*btf_trace_xs_stream_read_request)(void *, struct sock_xprt *);\n\ntypedef void (*btf_trace_svc_xdr_recvfrom)(void *, const struct svc_rqst *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_svc_xdr_sendto)(void *, const struct svc_rqst *, const struct xdr_buf *);\n\ntypedef void (*btf_trace_svc_recv)(void *, struct svc_rqst *, int);\n\ntypedef void (*btf_trace_svc_authenticate)(void *, const struct svc_rqst *, int, __be32);\n\ntypedef void (*btf_trace_svc_process)(void *, const struct svc_rqst *, const char *);\n\ntypedef void (*btf_trace_svc_defer)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_drop)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_send)(void *, struct svc_rqst *, int);\n\ntypedef void (*btf_trace_svc_xprt_create_err)(void *, const char *, const char *, struct sockaddr *, const struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_do_enqueue)(void *, struct svc_xprt *, struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_xprt_no_write_space)(void *, struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_close)(void *, struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_detach)(void *, struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_free)(void *, struct svc_xprt *);\n\ntypedef void (*btf_trace_svc_xprt_accept)(void *, const struct svc_xprt *, const char *);\n\ntypedef void (*btf_trace_svc_xprt_dequeue)(void *, struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_wake_up)(void *, int);\n\ntypedef void (*btf_trace_svc_handle_xprt)(void *, struct svc_xprt *, int);\n\ntypedef void (*btf_trace_svc_stats_latency)(void *, const struct svc_rqst *);\n\ntypedef void (*btf_trace_svc_defer_drop)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_defer_queue)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svc_defer_recv)(void *, const struct svc_deferred_req *);\n\ntypedef void (*btf_trace_svcsock_new_socket)(void *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_marker)(void *, const struct svc_xprt *, __be32);\n\ntypedef void (*btf_trace_svcsock_udp_send)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_udp_recv)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_udp_recv_err)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_send)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_eagain)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_err)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_data_ready)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_write_space)(void *, const struct svc_xprt *, ssize_t);\n\ntypedef void (*btf_trace_svcsock_tcp_recv_short)(void *, const struct svc_xprt *, u32, u32);\n\ntypedef void (*btf_trace_svcsock_tcp_state)(void *, const struct svc_xprt *, const struct socket *);\n\ntypedef void (*btf_trace_svcsock_accept_err)(void *, const struct svc_xprt *, const char *, long int);\n\ntypedef void (*btf_trace_svcsock_getpeername_err)(void *, const struct svc_xprt *, const char *, long int);\n\ntypedef void (*btf_trace_cache_entry_expired)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_upcall)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_update)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_make_negative)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_cache_entry_no_listener)(void *, const struct cache_detail *, const struct cache_head *);\n\ntypedef void (*btf_trace_svc_register)(void *, const char *, const u32, const int, const short unsigned int, const short unsigned int, int);\n\ntypedef void (*btf_trace_svc_noregister)(void *, const char *, const u32, const int, const short unsigned int, const short unsigned int, int);\n\ntypedef void (*btf_trace_svc_unregister)(void *, const char *, const u32, int);\n\nstruct rpc_cred_cache {\n\tstruct hlist_head *hashtable;\n\tunsigned int hashbits;\n\tspinlock_t lock;\n};\n\nenum {\n\tSVC_POOL_AUTO = 4294967295,\n\tSVC_POOL_GLOBAL = 0,\n\tSVC_POOL_PERCPU = 1,\n\tSVC_POOL_PERNODE = 2,\n};\n\nstruct unix_domain {\n\tstruct auth_domain h;\n};\n\nstruct ip_map {\n\tstruct cache_head h;\n\tchar m_class[8];\n\tstruct in6_addr m_addr;\n\tstruct unix_domain *m_client;\n\tstruct callback_head m_rcu;\n};\n\nstruct unix_gid {\n\tstruct cache_head h;\n\tkuid_t uid;\n\tstruct group_info *gi;\n\tstruct callback_head rcu;\n};\n\nenum {\n\tRPCBPROC_NULL = 0,\n\tRPCBPROC_SET = 1,\n\tRPCBPROC_UNSET = 2,\n\tRPCBPROC_GETPORT = 3,\n\tRPCBPROC_GETADDR = 3,\n\tRPCBPROC_DUMP = 4,\n\tRPCBPROC_CALLIT = 5,\n\tRPCBPROC_BCAST = 5,\n\tRPCBPROC_GETTIME = 6,\n\tRPCBPROC_UADDR2TADDR = 7,\n\tRPCBPROC_TADDR2UADDR = 8,\n\tRPCBPROC_GETVERSADDR = 9,\n\tRPCBPROC_INDIRECT = 10,\n\tRPCBPROC_GETADDRLIST = 11,\n\tRPCBPROC_GETSTAT = 12,\n};\n\nstruct rpcbind_args {\n\tstruct rpc_xprt *r_xprt;\n\tu32 r_prog;\n\tu32 r_vers;\n\tu32 r_prot;\n\tshort unsigned int r_port;\n\tconst char *r_netid;\n\tconst char *r_addr;\n\tconst char *r_owner;\n\tint r_status;\n};\n\nstruct rpcb_info {\n\tu32 rpc_vers;\n\tconst struct rpc_procinfo *rpc_proc;\n};\n\nstruct thread_deferred_req {\n\tstruct cache_deferred_req handle;\n\tstruct completion completion;\n};\n\nstruct cache_queue {\n\tstruct list_head list;\n\tint reader;\n};\n\nstruct cache_request {\n\tstruct cache_queue q;\n\tstruct cache_head *item;\n\tchar *buf;\n\tint len;\n\tint readers;\n};\n\nstruct cache_reader {\n\tstruct cache_queue q;\n\tint offset;\n};\n\nstruct rpc_filelist {\n\tconst char *name;\n\tconst struct file_operations *i_fop;\n\tumode_t mode;\n};\n\nenum {\n\tRPCAUTH_info = 0,\n\tRPCAUTH_EOF = 1,\n};\n\nenum {\n\tRPCAUTH_lockd = 0,\n\tRPCAUTH_mount = 1,\n\tRPCAUTH_nfs = 2,\n\tRPCAUTH_portmap = 3,\n\tRPCAUTH_statd = 4,\n\tRPCAUTH_nfsd4_cb = 5,\n\tRPCAUTH_cache = 6,\n\tRPCAUTH_nfsd = 7,\n\tRPCAUTH_gssd = 8,\n\tRPCAUTH_RootEOF = 9,\n};\n\nstruct svc_xpt_user {\n\tstruct list_head list;\n\tvoid (*callback)(struct svc_xpt_user *);\n};\n\ntypedef struct rpc_xprt * (*xprt_switch_find_xprt_t)(struct rpc_xprt_switch *, const struct rpc_xprt *);\n\nenum rpc_gss_proc {\n\tRPC_GSS_PROC_DATA = 0,\n\tRPC_GSS_PROC_INIT = 1,\n\tRPC_GSS_PROC_CONTINUE_INIT = 2,\n\tRPC_GSS_PROC_DESTROY = 3,\n};\n\nenum rpc_gss_svc {\n\tRPC_GSS_SVC_NONE = 1,\n\tRPC_GSS_SVC_INTEGRITY = 2,\n\tRPC_GSS_SVC_PRIVACY = 3,\n};\n\nstruct gss_cl_ctx {\n\trefcount_t count;\n\tenum rpc_gss_proc gc_proc;\n\tu32 gc_seq;\n\tu32 gc_seq_xmit;\n\tspinlock_t gc_seq_lock;\n\tstruct gss_ctx *gc_gss_ctx;\n\tstruct xdr_netobj gc_wire_ctx;\n\tstruct xdr_netobj gc_acceptor;\n\tu32 gc_win;\n\tlong unsigned int gc_expiry;\n\tstruct callback_head gc_rcu;\n};\n\nstruct gss_upcall_msg;\n\nstruct gss_cred {\n\tstruct rpc_cred gc_base;\n\tenum rpc_gss_svc gc_service;\n\tstruct gss_cl_ctx *gc_ctx;\n\tstruct gss_upcall_msg *gc_upcall;\n\tconst char *gc_principal;\n\tlong unsigned int gc_upcall_timestamp;\n};\n\nstruct gss_auth;\n\nstruct gss_upcall_msg {\n\trefcount_t count;\n\tkuid_t uid;\n\tconst char *service_name;\n\tstruct rpc_pipe_msg msg;\n\tstruct list_head list;\n\tstruct gss_auth *auth;\n\tstruct rpc_pipe *pipe;\n\tstruct rpc_wait_queue rpc_waitqueue;\n\twait_queue_head_t waitqueue;\n\tstruct gss_cl_ctx *ctx;\n\tchar databuf[256];\n};\n\ntypedef unsigned int OM_uint32;\n\nstruct gss_pipe {\n\tstruct rpc_pipe_dir_object pdo;\n\tstruct rpc_pipe *pipe;\n\tstruct rpc_clnt *clnt;\n\tconst char *name;\n\tstruct kref kref;\n};\n\nstruct gss_auth {\n\tstruct kref kref;\n\tstruct hlist_node hash;\n\tstruct rpc_auth rpc_auth;\n\tstruct gss_api_mech *mech;\n\tenum rpc_gss_svc service;\n\tstruct rpc_clnt *client;\n\tstruct net *net;\n\tstruct gss_pipe *gss_pipe[2];\n\tconst char *target_name;\n};\n\nstruct gss_alloc_pdo {\n\tstruct rpc_clnt *clnt;\n\tconst char *name;\n\tconst struct rpc_pipe_ops *upcall_ops;\n};\n\nstruct rpc_gss_wire_cred {\n\tu32 gc_v;\n\tu32 gc_proc;\n\tu32 gc_seq;\n\tu32 gc_svc;\n\tstruct xdr_netobj gc_ctx;\n};\n\nstruct gssp_in_token {\n\tstruct page **pages;\n\tunsigned int page_base;\n\tunsigned int page_len;\n};\n\nstruct gssp_upcall_data {\n\tstruct xdr_netobj in_handle;\n\tstruct gssp_in_token in_token;\n\tstruct xdr_netobj out_handle;\n\tstruct xdr_netobj out_token;\n\tstruct rpcsec_gss_oid mech_oid;\n\tstruct svc_cred creds;\n\tint found_creds;\n\tint major_status;\n\tint minor_status;\n};\n\nstruct rsi {\n\tstruct cache_head h;\n\tstruct xdr_netobj in_handle;\n\tstruct xdr_netobj in_token;\n\tstruct xdr_netobj out_handle;\n\tstruct xdr_netobj out_token;\n\tint major_status;\n\tint minor_status;\n\tstruct callback_head callback_head;\n};\n\nstruct gss_svc_seq_data {\n\tint sd_max;\n\tlong unsigned int sd_win[2];\n\tspinlock_t sd_lock;\n};\n\nstruct rsc {\n\tstruct cache_head h;\n\tstruct xdr_netobj handle;\n\tstruct svc_cred cred;\n\tstruct gss_svc_seq_data seqdata;\n\tstruct gss_ctx *mechctx;\n\tstruct callback_head callback_head;\n};\n\nstruct gss_domain {\n\tstruct auth_domain h;\n\tu32 pseudoflavor;\n};\n\nstruct gss_svc_data {\n\tstruct rpc_gss_wire_cred clcred;\n\t__be32 *verf_start;\n\tstruct rsc *rsci;\n};\n\ntypedef struct xdr_netobj gssx_buffer;\n\ntypedef struct xdr_netobj utf8string;\n\ntypedef struct xdr_netobj gssx_OID;\n\nstruct gssx_option {\n\tgssx_buffer option;\n\tgssx_buffer value;\n};\n\nstruct gssx_option_array {\n\tu32 count;\n\tstruct gssx_option *data;\n};\n\nstruct gssx_status {\n\tu64 major_status;\n\tgssx_OID mech;\n\tu64 minor_status;\n\tutf8string major_status_string;\n\tutf8string minor_status_string;\n\tgssx_buffer server_ctx;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_call_ctx {\n\tutf8string locale;\n\tgssx_buffer server_ctx;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_name {\n\tgssx_buffer display_name;\n};\n\ntypedef struct gssx_name gssx_name;\n\nstruct gssx_cred_element {\n\tgssx_name MN;\n\tgssx_OID mech;\n\tu32 cred_usage;\n\tu64 initiator_time_rec;\n\tu64 acceptor_time_rec;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_cred_element_array {\n\tu32 count;\n\tstruct gssx_cred_element *data;\n};\n\nstruct gssx_cred {\n\tgssx_name desired_name;\n\tstruct gssx_cred_element_array elements;\n\tgssx_buffer cred_handle_reference;\n\tu32 needs_release;\n};\n\nstruct gssx_ctx {\n\tgssx_buffer exported_context_token;\n\tgssx_buffer state;\n\tu32 need_release;\n\tgssx_OID mech;\n\tgssx_name src_name;\n\tgssx_name targ_name;\n\tu64 lifetime;\n\tu64 ctx_flags;\n\tu32 locally_initiated;\n\tu32 open;\n\tstruct gssx_option_array options;\n};\n\nstruct gssx_cb {\n\tu64 initiator_addrtype;\n\tgssx_buffer initiator_address;\n\tu64 acceptor_addrtype;\n\tgssx_buffer acceptor_address;\n\tgssx_buffer application_data;\n};\n\nstruct gssx_arg_accept_sec_context {\n\tstruct gssx_call_ctx call_ctx;\n\tstruct gssx_ctx *context_handle;\n\tstruct gssx_cred *cred_handle;\n\tstruct gssp_in_token input_token;\n\tstruct gssx_cb *input_cb;\n\tu32 ret_deleg_cred;\n\tstruct gssx_option_array options;\n\tstruct page **pages;\n\tunsigned int npages;\n};\n\nstruct gssx_res_accept_sec_context {\n\tstruct gssx_status status;\n\tstruct gssx_ctx *context_handle;\n\tgssx_buffer *output_token;\n\tstruct gssx_option_array options;\n};\n\nenum {\n\tGSSX_NULL = 0,\n\tGSSX_INDICATE_MECHS = 1,\n\tGSSX_GET_CALL_CONTEXT = 2,\n\tGSSX_IMPORT_AND_CANON_NAME = 3,\n\tGSSX_EXPORT_CRED = 4,\n\tGSSX_IMPORT_CRED = 5,\n\tGSSX_ACQUIRE_CRED = 6,\n\tGSSX_STORE_CRED = 7,\n\tGSSX_INIT_SEC_CONTEXT = 8,\n\tGSSX_ACCEPT_SEC_CONTEXT = 9,\n\tGSSX_RELEASE_HANDLE = 10,\n\tGSSX_GET_MIC = 11,\n\tGSSX_VERIFY = 12,\n\tGSSX_WRAP = 13,\n\tGSSX_UNWRAP = 14,\n\tGSSX_WRAP_SIZE_LIMIT = 15,\n};\n\nstruct gssx_name_attr {\n\tgssx_buffer attr;\n\tgssx_buffer value;\n\tstruct gssx_option_array extensions;\n};\n\nstruct gssx_name_attr_array {\n\tu32 count;\n\tstruct gssx_name_attr *data;\n};\n\nstruct trace_event_raw_rpcgss_gssapi_event {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 maj_stat;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_import_ctx {\n\tstruct trace_entry ent;\n\tint status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_ctx_class {\n\tstruct trace_entry ent;\n\tconst void *cred;\n\tlong unsigned int service;\n\tu32 __data_loc_principal;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_accept_upcall {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 minor_status;\n\tlong unsigned int major_status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_accept {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tsize_t len;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_unwrap_failed {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_bad_seqno {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 expected;\n\tu32 received;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_seqno {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_need_reencode {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tu32 seq_xmit;\n\tu32 seqno;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_update_slack {\n\tstruct trace_entry ent;\n\tunsigned int task_id;\n\tunsigned int client_id;\n\tu32 xid;\n\tconst void *auth;\n\tunsigned int rslack;\n\tunsigned int ralign;\n\tunsigned int verfsize;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_svc_seqno_class {\n\tstruct trace_entry ent;\n\tu32 xid;\n\tu32 seqno;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_upcall_msg {\n\tstruct trace_entry ent;\n\tu32 __data_loc_msg;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_upcall_result {\n\tstruct trace_entry ent;\n\tu32 uid;\n\tint result;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_context {\n\tstruct trace_entry ent;\n\tlong unsigned int expiry;\n\tlong unsigned int now;\n\tunsigned int timeout;\n\tu32 window_size;\n\tint len;\n\tu32 __data_loc_acceptor;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_createauth {\n\tstruct trace_entry ent;\n\tunsigned int flavor;\n\tint error;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rpcgss_oid_to_mech {\n\tstruct trace_entry ent;\n\tu32 __data_loc_oid;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_rpcgss_gssapi_event {};\n\nstruct trace_event_data_offsets_rpcgss_import_ctx {};\n\nstruct trace_event_data_offsets_rpcgss_ctx_class {\n\tu32 principal;\n};\n\nstruct trace_event_data_offsets_rpcgss_svc_accept_upcall {};\n\nstruct trace_event_data_offsets_rpcgss_svc_accept {};\n\nstruct trace_event_data_offsets_rpcgss_unwrap_failed {};\n\nstruct trace_event_data_offsets_rpcgss_bad_seqno {};\n\nstruct trace_event_data_offsets_rpcgss_seqno {};\n\nstruct trace_event_data_offsets_rpcgss_need_reencode {};\n\nstruct trace_event_data_offsets_rpcgss_update_slack {};\n\nstruct trace_event_data_offsets_rpcgss_svc_seqno_class {};\n\nstruct trace_event_data_offsets_rpcgss_upcall_msg {\n\tu32 msg;\n};\n\nstruct trace_event_data_offsets_rpcgss_upcall_result {};\n\nstruct trace_event_data_offsets_rpcgss_context {\n\tu32 acceptor;\n};\n\nstruct trace_event_data_offsets_rpcgss_createauth {};\n\nstruct trace_event_data_offsets_rpcgss_oid_to_mech {\n\tu32 oid;\n};\n\ntypedef void (*btf_trace_rpcgss_import_ctx)(void *, int);\n\ntypedef void (*btf_trace_rpcgss_get_mic)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_verify_mic)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_wrap)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_unwrap)(void *, const struct rpc_task *, u32);\n\ntypedef void (*btf_trace_rpcgss_ctx_init)(void *, const struct gss_cred *);\n\ntypedef void (*btf_trace_rpcgss_ctx_destroy)(void *, const struct gss_cred *);\n\ntypedef void (*btf_trace_rpcgss_svc_accept_upcall)(void *, __be32, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_accept)(void *, __be32, size_t);\n\ntypedef void (*btf_trace_rpcgss_unwrap_failed)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcgss_bad_seqno)(void *, const struct rpc_task *, u32, u32);\n\ntypedef void (*btf_trace_rpcgss_seqno)(void *, const struct rpc_task *);\n\ntypedef void (*btf_trace_rpcgss_need_reencode)(void *, const struct rpc_task *, u32, bool);\n\ntypedef void (*btf_trace_rpcgss_update_slack)(void *, const struct rpc_task *, const struct rpc_auth *);\n\ntypedef void (*btf_trace_rpcgss_svc_large_seqno)(void *, __be32, u32);\n\ntypedef void (*btf_trace_rpcgss_svc_old_seqno)(void *, __be32, u32);\n\ntypedef void (*btf_trace_rpcgss_upcall_msg)(void *, const char *);\n\ntypedef void (*btf_trace_rpcgss_upcall_result)(void *, u32, int);\n\ntypedef void (*btf_trace_rpcgss_context)(void *, u32, long unsigned int, long unsigned int, unsigned int, unsigned int, const u8 *);\n\ntypedef void (*btf_trace_rpcgss_createauth)(void *, unsigned int, int);\n\ntypedef void (*btf_trace_rpcgss_oid_to_mech)(void *, const char *);\n\nstruct strp_msg {\n\tint full_len;\n\tint offset;\n};\n\nstruct _strp_msg {\n\tstruct strp_msg strp;\n\tint accum_len;\n};\n\nenum nl80211_commands {\n\tNL80211_CMD_UNSPEC = 0,\n\tNL80211_CMD_GET_WIPHY = 1,\n\tNL80211_CMD_SET_WIPHY = 2,\n\tNL80211_CMD_NEW_WIPHY = 3,\n\tNL80211_CMD_DEL_WIPHY = 4,\n\tNL80211_CMD_GET_INTERFACE = 5,\n\tNL80211_CMD_SET_INTERFACE = 6,\n\tNL80211_CMD_NEW_INTERFACE = 7,\n\tNL80211_CMD_DEL_INTERFACE = 8,\n\tNL80211_CMD_GET_KEY = 9,\n\tNL80211_CMD_SET_KEY = 10,\n\tNL80211_CMD_NEW_KEY = 11,\n\tNL80211_CMD_DEL_KEY = 12,\n\tNL80211_CMD_GET_BEACON = 13,\n\tNL80211_CMD_SET_BEACON = 14,\n\tNL80211_CMD_START_AP = 15,\n\tNL80211_CMD_NEW_BEACON = 15,\n\tNL80211_CMD_STOP_AP = 16,\n\tNL80211_CMD_DEL_BEACON = 16,\n\tNL80211_CMD_GET_STATION = 17,\n\tNL80211_CMD_SET_STATION = 18,\n\tNL80211_CMD_NEW_STATION = 19,\n\tNL80211_CMD_DEL_STATION = 20,\n\tNL80211_CMD_GET_MPATH = 21,\n\tNL80211_CMD_SET_MPATH = 22,\n\tNL80211_CMD_NEW_MPATH = 23,\n\tNL80211_CMD_DEL_MPATH = 24,\n\tNL80211_CMD_SET_BSS = 25,\n\tNL80211_CMD_SET_REG = 26,\n\tNL80211_CMD_REQ_SET_REG = 27,\n\tNL80211_CMD_GET_MESH_CONFIG = 28,\n\tNL80211_CMD_SET_MESH_CONFIG = 29,\n\tNL80211_CMD_SET_MGMT_EXTRA_IE = 30,\n\tNL80211_CMD_GET_REG = 31,\n\tNL80211_CMD_GET_SCAN = 32,\n\tNL80211_CMD_TRIGGER_SCAN = 33,\n\tNL80211_CMD_NEW_SCAN_RESULTS = 34,\n\tNL80211_CMD_SCAN_ABORTED = 35,\n\tNL80211_CMD_REG_CHANGE = 36,\n\tNL80211_CMD_AUTHENTICATE = 37,\n\tNL80211_CMD_ASSOCIATE = 38,\n\tNL80211_CMD_DEAUTHENTICATE = 39,\n\tNL80211_CMD_DISASSOCIATE = 40,\n\tNL80211_CMD_MICHAEL_MIC_FAILURE = 41,\n\tNL80211_CMD_REG_BEACON_HINT = 42,\n\tNL80211_CMD_JOIN_IBSS = 43,\n\tNL80211_CMD_LEAVE_IBSS = 44,\n\tNL80211_CMD_TESTMODE = 45,\n\tNL80211_CMD_CONNECT = 46,\n\tNL80211_CMD_ROAM = 47,\n\tNL80211_CMD_DISCONNECT = 48,\n\tNL80211_CMD_SET_WIPHY_NETNS = 49,\n\tNL80211_CMD_GET_SURVEY = 50,\n\tNL80211_CMD_NEW_SURVEY_RESULTS = 51,\n\tNL80211_CMD_SET_PMKSA = 52,\n\tNL80211_CMD_DEL_PMKSA = 53,\n\tNL80211_CMD_FLUSH_PMKSA = 54,\n\tNL80211_CMD_REMAIN_ON_CHANNEL = 55,\n\tNL80211_CMD_CANCEL_REMAIN_ON_CHANNEL = 56,\n\tNL80211_CMD_SET_TX_BITRATE_MASK = 57,\n\tNL80211_CMD_REGISTER_FRAME = 58,\n\tNL80211_CMD_REGISTER_ACTION = 58,\n\tNL80211_CMD_FRAME = 59,\n\tNL80211_CMD_ACTION = 59,\n\tNL80211_CMD_FRAME_TX_STATUS = 60,\n\tNL80211_CMD_ACTION_TX_STATUS = 60,\n\tNL80211_CMD_SET_POWER_SAVE = 61,\n\tNL80211_CMD_GET_POWER_SAVE = 62,\n\tNL80211_CMD_SET_CQM = 63,\n\tNL80211_CMD_NOTIFY_CQM = 64,\n\tNL80211_CMD_SET_CHANNEL = 65,\n\tNL80211_CMD_SET_WDS_PEER = 66,\n\tNL80211_CMD_FRAME_WAIT_CANCEL = 67,\n\tNL80211_CMD_JOIN_MESH = 68,\n\tNL80211_CMD_LEAVE_MESH = 69,\n\tNL80211_CMD_UNPROT_DEAUTHENTICATE = 70,\n\tNL80211_CMD_UNPROT_DISASSOCIATE = 71,\n\tNL80211_CMD_NEW_PEER_CANDIDATE = 72,\n\tNL80211_CMD_GET_WOWLAN = 73,\n\tNL80211_CMD_SET_WOWLAN = 74,\n\tNL80211_CMD_START_SCHED_SCAN = 75,\n\tNL80211_CMD_STOP_SCHED_SCAN = 76,\n\tNL80211_CMD_SCHED_SCAN_RESULTS = 77,\n\tNL80211_CMD_SCHED_SCAN_STOPPED = 78,\n\tNL80211_CMD_SET_REKEY_OFFLOAD = 79,\n\tNL80211_CMD_PMKSA_CANDIDATE = 80,\n\tNL80211_CMD_TDLS_OPER = 81,\n\tNL80211_CMD_TDLS_MGMT = 82,\n\tNL80211_CMD_UNEXPECTED_FRAME = 83,\n\tNL80211_CMD_PROBE_CLIENT = 84,\n\tNL80211_CMD_REGISTER_BEACONS = 85,\n\tNL80211_CMD_UNEXPECTED_4ADDR_FRAME = 86,\n\tNL80211_CMD_SET_NOACK_MAP = 87,\n\tNL80211_CMD_CH_SWITCH_NOTIFY = 88,\n\tNL80211_CMD_START_P2P_DEVICE = 89,\n\tNL80211_CMD_STOP_P2P_DEVICE = 90,\n\tNL80211_CMD_CONN_FAILED = 91,\n\tNL80211_CMD_SET_MCAST_RATE = 92,\n\tNL80211_CMD_SET_MAC_ACL = 93,\n\tNL80211_CMD_RADAR_DETECT = 94,\n\tNL80211_CMD_GET_PROTOCOL_FEATURES = 95,\n\tNL80211_CMD_UPDATE_FT_IES = 96,\n\tNL80211_CMD_FT_EVENT = 97,\n\tNL80211_CMD_CRIT_PROTOCOL_START = 98,\n\tNL80211_CMD_CRIT_PROTOCOL_STOP = 99,\n\tNL80211_CMD_GET_COALESCE = 100,\n\tNL80211_CMD_SET_COALESCE = 101,\n\tNL80211_CMD_CHANNEL_SWITCH = 102,\n\tNL80211_CMD_VENDOR = 103,\n\tNL80211_CMD_SET_QOS_MAP = 104,\n\tNL80211_CMD_ADD_TX_TS = 105,\n\tNL80211_CMD_DEL_TX_TS = 106,\n\tNL80211_CMD_GET_MPP = 107,\n\tNL80211_CMD_JOIN_OCB = 108,\n\tNL80211_CMD_LEAVE_OCB = 109,\n\tNL80211_CMD_CH_SWITCH_STARTED_NOTIFY = 110,\n\tNL80211_CMD_TDLS_CHANNEL_SWITCH = 111,\n\tNL80211_CMD_TDLS_CANCEL_CHANNEL_SWITCH = 112,\n\tNL80211_CMD_WIPHY_REG_CHANGE = 113,\n\tNL80211_CMD_ABORT_SCAN = 114,\n\tNL80211_CMD_START_NAN = 115,\n\tNL80211_CMD_STOP_NAN = 116,\n\tNL80211_CMD_ADD_NAN_FUNCTION = 117,\n\tNL80211_CMD_DEL_NAN_FUNCTION = 118,\n\tNL80211_CMD_CHANGE_NAN_CONFIG = 119,\n\tNL80211_CMD_NAN_MATCH = 120,\n\tNL80211_CMD_SET_MULTICAST_TO_UNICAST = 121,\n\tNL80211_CMD_UPDATE_CONNECT_PARAMS = 122,\n\tNL80211_CMD_SET_PMK = 123,\n\tNL80211_CMD_DEL_PMK = 124,\n\tNL80211_CMD_PORT_AUTHORIZED = 125,\n\tNL80211_CMD_RELOAD_REGDB = 126,\n\tNL80211_CMD_EXTERNAL_AUTH = 127,\n\tNL80211_CMD_STA_OPMODE_CHANGED = 128,\n\tNL80211_CMD_CONTROL_PORT_FRAME = 129,\n\tNL80211_CMD_GET_FTM_RESPONDER_STATS = 130,\n\tNL80211_CMD_PEER_MEASUREMENT_START = 131,\n\tNL80211_CMD_PEER_MEASUREMENT_RESULT = 132,\n\tNL80211_CMD_PEER_MEASUREMENT_COMPLETE = 133,\n\tNL80211_CMD_NOTIFY_RADAR = 134,\n\tNL80211_CMD_UPDATE_OWE_INFO = 135,\n\tNL80211_CMD_PROBE_MESH_LINK = 136,\n\tNL80211_CMD_SET_TID_CONFIG = 137,\n\tNL80211_CMD_UNPROT_BEACON = 138,\n\tNL80211_CMD_CONTROL_PORT_FRAME_TX_STATUS = 139,\n\t__NL80211_CMD_AFTER_LAST = 140,\n\tNL80211_CMD_MAX = 139,\n};\n\nenum nl80211_iftype {\n\tNL80211_IFTYPE_UNSPECIFIED = 0,\n\tNL80211_IFTYPE_ADHOC = 1,\n\tNL80211_IFTYPE_STATION = 2,\n\tNL80211_IFTYPE_AP = 3,\n\tNL80211_IFTYPE_AP_VLAN = 4,\n\tNL80211_IFTYPE_WDS = 5,\n\tNL80211_IFTYPE_MONITOR = 6,\n\tNL80211_IFTYPE_MESH_POINT = 7,\n\tNL80211_IFTYPE_P2P_CLIENT = 8,\n\tNL80211_IFTYPE_P2P_GO = 9,\n\tNL80211_IFTYPE_P2P_DEVICE = 10,\n\tNL80211_IFTYPE_OCB = 11,\n\tNL80211_IFTYPE_NAN = 12,\n\tNUM_NL80211_IFTYPES = 13,\n\tNL80211_IFTYPE_MAX = 12,\n};\n\nstruct nl80211_sta_flag_update {\n\t__u32 mask;\n\t__u32 set;\n};\n\nenum nl80211_reg_initiator {\n\tNL80211_REGDOM_SET_BY_CORE = 0,\n\tNL80211_REGDOM_SET_BY_USER = 1,\n\tNL80211_REGDOM_SET_BY_DRIVER = 2,\n\tNL80211_REGDOM_SET_BY_COUNTRY_IE = 3,\n};\n\nenum nl80211_dfs_regions {\n\tNL80211_DFS_UNSET = 0,\n\tNL80211_DFS_FCC = 1,\n\tNL80211_DFS_ETSI = 2,\n\tNL80211_DFS_JP = 3,\n};\n\nenum nl80211_user_reg_hint_type {\n\tNL80211_USER_REG_HINT_USER = 0,\n\tNL80211_USER_REG_HINT_CELL_BASE = 1,\n\tNL80211_USER_REG_HINT_INDOOR = 2,\n};\n\nenum nl80211_mntr_flags {\n\t__NL80211_MNTR_FLAG_INVALID = 0,\n\tNL80211_MNTR_FLAG_FCSFAIL = 1,\n\tNL80211_MNTR_FLAG_PLCPFAIL = 2,\n\tNL80211_MNTR_FLAG_CONTROL = 3,\n\tNL80211_MNTR_FLAG_OTHER_BSS = 4,\n\tNL80211_MNTR_FLAG_COOK_FRAMES = 5,\n\tNL80211_MNTR_FLAG_ACTIVE = 6,\n\t__NL80211_MNTR_FLAG_AFTER_LAST = 7,\n\tNL80211_MNTR_FLAG_MAX = 6,\n};\n\nenum nl80211_mesh_power_mode {\n\tNL80211_MESH_POWER_UNKNOWN = 0,\n\tNL80211_MESH_POWER_ACTIVE = 1,\n\tNL80211_MESH_POWER_LIGHT_SLEEP = 2,\n\tNL80211_MESH_POWER_DEEP_SLEEP = 3,\n\t__NL80211_MESH_POWER_AFTER_LAST = 4,\n\tNL80211_MESH_POWER_MAX = 3,\n};\n\nenum nl80211_ac {\n\tNL80211_AC_VO = 0,\n\tNL80211_AC_VI = 1,\n\tNL80211_AC_BE = 2,\n\tNL80211_AC_BK = 3,\n\tNL80211_NUM_ACS = 4,\n};\n\nenum nl80211_key_mode {\n\tNL80211_KEY_RX_TX = 0,\n\tNL80211_KEY_NO_TX = 1,\n\tNL80211_KEY_SET_TX = 2,\n};\n\nenum nl80211_chan_width {\n\tNL80211_CHAN_WIDTH_20_NOHT = 0,\n\tNL80211_CHAN_WIDTH_20 = 1,\n\tNL80211_CHAN_WIDTH_40 = 2,\n\tNL80211_CHAN_WIDTH_80 = 3,\n\tNL80211_CHAN_WIDTH_80P80 = 4,\n\tNL80211_CHAN_WIDTH_160 = 5,\n\tNL80211_CHAN_WIDTH_5 = 6,\n\tNL80211_CHAN_WIDTH_10 = 7,\n};\n\nenum nl80211_bss_scan_width {\n\tNL80211_BSS_CHAN_WIDTH_20 = 0,\n\tNL80211_BSS_CHAN_WIDTH_10 = 1,\n\tNL80211_BSS_CHAN_WIDTH_5 = 2,\n};\n\nenum nl80211_auth_type {\n\tNL80211_AUTHTYPE_OPEN_SYSTEM = 0,\n\tNL80211_AUTHTYPE_SHARED_KEY = 1,\n\tNL80211_AUTHTYPE_FT = 2,\n\tNL80211_AUTHTYPE_NETWORK_EAP = 3,\n\tNL80211_AUTHTYPE_SAE = 4,\n\tNL80211_AUTHTYPE_FILS_SK = 5,\n\tNL80211_AUTHTYPE_FILS_SK_PFS = 6,\n\tNL80211_AUTHTYPE_FILS_PK = 7,\n\t__NL80211_AUTHTYPE_NUM = 8,\n\tNL80211_AUTHTYPE_MAX = 7,\n\tNL80211_AUTHTYPE_AUTOMATIC = 8,\n};\n\nenum nl80211_mfp {\n\tNL80211_MFP_NO = 0,\n\tNL80211_MFP_REQUIRED = 1,\n\tNL80211_MFP_OPTIONAL = 2,\n};\n\nenum nl80211_txrate_gi {\n\tNL80211_TXRATE_DEFAULT_GI = 0,\n\tNL80211_TXRATE_FORCE_SGI = 1,\n\tNL80211_TXRATE_FORCE_LGI = 2,\n};\n\nenum nl80211_band {\n\tNL80211_BAND_2GHZ = 0,\n\tNL80211_BAND_5GHZ = 1,\n\tNL80211_BAND_60GHZ = 2,\n\tNL80211_BAND_6GHZ = 3,\n\tNUM_NL80211_BANDS = 4,\n};\n\nenum nl80211_tx_power_setting {\n\tNL80211_TX_POWER_AUTOMATIC = 0,\n\tNL80211_TX_POWER_LIMITED = 1,\n\tNL80211_TX_POWER_FIXED = 2,\n};\n\nenum nl80211_tid_config {\n\tNL80211_TID_CONFIG_ENABLE = 0,\n\tNL80211_TID_CONFIG_DISABLE = 1,\n};\n\nenum nl80211_tx_rate_setting {\n\tNL80211_TX_RATE_AUTOMATIC = 0,\n\tNL80211_TX_RATE_LIMITED = 1,\n\tNL80211_TX_RATE_FIXED = 2,\n};\n\nstruct nl80211_wowlan_tcp_data_seq {\n\t__u32 start;\n\t__u32 offset;\n\t__u32 len;\n};\n\nstruct nl80211_wowlan_tcp_data_token {\n\t__u32 offset;\n\t__u32 len;\n\t__u8 token_stream[0];\n};\n\nstruct nl80211_wowlan_tcp_data_token_feature {\n\t__u32 min_len;\n\t__u32 max_len;\n\t__u32 bufsize;\n};\n\nenum nl80211_coalesce_condition {\n\tNL80211_COALESCE_CONDITION_MATCH = 0,\n\tNL80211_COALESCE_CONDITION_NO_MATCH = 1,\n};\n\nenum nl80211_hidden_ssid {\n\tNL80211_HIDDEN_SSID_NOT_IN_USE = 0,\n\tNL80211_HIDDEN_SSID_ZERO_LEN = 1,\n\tNL80211_HIDDEN_SSID_ZERO_CONTENTS = 2,\n};\n\nenum nl80211_tdls_operation {\n\tNL80211_TDLS_DISCOVERY_REQ = 0,\n\tNL80211_TDLS_SETUP = 1,\n\tNL80211_TDLS_TEARDOWN = 2,\n\tNL80211_TDLS_ENABLE_LINK = 3,\n\tNL80211_TDLS_DISABLE_LINK = 4,\n};\n\nenum nl80211_feature_flags {\n\tNL80211_FEATURE_SK_TX_STATUS = 1,\n\tNL80211_FEATURE_HT_IBSS = 2,\n\tNL80211_FEATURE_INACTIVITY_TIMER = 4,\n\tNL80211_FEATURE_CELL_BASE_REG_HINTS = 8,\n\tNL80211_FEATURE_P2P_DEVICE_NEEDS_CHANNEL = 16,\n\tNL80211_FEATURE_SAE = 32,\n\tNL80211_FEATURE_LOW_PRIORITY_SCAN = 64,\n\tNL80211_FEATURE_SCAN_FLUSH = 128,\n\tNL80211_FEATURE_AP_SCAN = 256,\n\tNL80211_FEATURE_VIF_TXPOWER = 512,\n\tNL80211_FEATURE_NEED_OBSS_SCAN = 1024,\n\tNL80211_FEATURE_P2P_GO_CTWIN = 2048,\n\tNL80211_FEATURE_P2P_GO_OPPPS = 4096,\n\tNL80211_FEATURE_ADVERTISE_CHAN_LIMITS = 16384,\n\tNL80211_FEATURE_FULL_AP_CLIENT_STATE = 32768,\n\tNL80211_FEATURE_USERSPACE_MPM = 65536,\n\tNL80211_FEATURE_ACTIVE_MONITOR = 131072,\n\tNL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE = 262144,\n\tNL80211_FEATURE_DS_PARAM_SET_IE_IN_PROBES = 524288,\n\tNL80211_FEATURE_WFA_TPC_IE_IN_PROBES = 1048576,\n\tNL80211_FEATURE_QUIET = 2097152,\n\tNL80211_FEATURE_TX_POWER_INSERTION = 4194304,\n\tNL80211_FEATURE_ACKTO_ESTIMATION = 8388608,\n\tNL80211_FEATURE_STATIC_SMPS = 16777216,\n\tNL80211_FEATURE_DYNAMIC_SMPS = 33554432,\n\tNL80211_FEATURE_SUPPORTS_WMM_ADMISSION = 67108864,\n\tNL80211_FEATURE_MAC_ON_CREATE = 134217728,\n\tNL80211_FEATURE_TDLS_CHANNEL_SWITCH = 268435456,\n\tNL80211_FEATURE_SCAN_RANDOM_MAC_ADDR = 536870912,\n\tNL80211_FEATURE_SCHED_SCAN_RANDOM_MAC_ADDR = 1073741824,\n\tNL80211_FEATURE_ND_RANDOM_MAC_ADDR = 2147483648,\n};\n\nenum nl80211_ext_feature_index {\n\tNL80211_EXT_FEATURE_VHT_IBSS = 0,\n\tNL80211_EXT_FEATURE_RRM = 1,\n\tNL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER = 2,\n\tNL80211_EXT_FEATURE_SCAN_START_TIME = 3,\n\tNL80211_EXT_FEATURE_BSS_PARENT_TSF = 4,\n\tNL80211_EXT_FEATURE_SET_SCAN_DWELL = 5,\n\tNL80211_EXT_FEATURE_BEACON_RATE_LEGACY = 6,\n\tNL80211_EXT_FEATURE_BEACON_RATE_HT = 7,\n\tNL80211_EXT_FEATURE_BEACON_RATE_VHT = 8,\n\tNL80211_EXT_FEATURE_FILS_STA = 9,\n\tNL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA = 10,\n\tNL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA_CONNECTED = 11,\n\tNL80211_EXT_FEATURE_SCHED_SCAN_RELATIVE_RSSI = 12,\n\tNL80211_EXT_FEATURE_CQM_RSSI_LIST = 13,\n\tNL80211_EXT_FEATURE_FILS_SK_OFFLOAD = 14,\n\tNL80211_EXT_FEATURE_4WAY_HANDSHAKE_STA_PSK = 15,\n\tNL80211_EXT_FEATURE_4WAY_HANDSHAKE_STA_1X = 16,\n\tNL80211_EXT_FEATURE_FILS_MAX_CHANNEL_TIME = 17,\n\tNL80211_EXT_FEATURE_ACCEPT_BCAST_PROBE_RESP = 18,\n\tNL80211_EXT_FEATURE_OCE_PROBE_REQ_HIGH_TX_RATE = 19,\n\tNL80211_EXT_FEATURE_OCE_PROBE_REQ_DEFERRAL_SUPPRESSION = 20,\n\tNL80211_EXT_FEATURE_MFP_OPTIONAL = 21,\n\tNL80211_EXT_FEATURE_LOW_SPAN_SCAN = 22,\n\tNL80211_EXT_FEATURE_LOW_POWER_SCAN = 23,\n\tNL80211_EXT_FEATURE_HIGH_ACCURACY_SCAN = 24,\n\tNL80211_EXT_FEATURE_DFS_OFFLOAD = 25,\n\tNL80211_EXT_FEATURE_CONTROL_PORT_OVER_NL80211 = 26,\n\tNL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT = 27,\n\tNL80211_EXT_FEATURE_DATA_ACK_SIGNAL_SUPPORT = 27,\n\tNL80211_EXT_FEATURE_TXQS = 28,\n\tNL80211_EXT_FEATURE_SCAN_RANDOM_SN = 29,\n\tNL80211_EXT_FEATURE_SCAN_MIN_PREQ_CONTENT = 30,\n\tNL80211_EXT_FEATURE_CAN_REPLACE_PTK0 = 31,\n\tNL80211_EXT_FEATURE_ENABLE_FTM_RESPONDER = 32,\n\tNL80211_EXT_FEATURE_AIRTIME_FAIRNESS = 33,\n\tNL80211_EXT_FEATURE_AP_PMKSA_CACHING = 34,\n\tNL80211_EXT_FEATURE_SCHED_SCAN_BAND_SPECIFIC_RSSI_THOLD = 35,\n\tNL80211_EXT_FEATURE_EXT_KEY_ID = 36,\n\tNL80211_EXT_FEATURE_STA_TX_PWR = 37,\n\tNL80211_EXT_FEATURE_SAE_OFFLOAD = 38,\n\tNL80211_EXT_FEATURE_VLAN_OFFLOAD = 39,\n\tNL80211_EXT_FEATURE_AQL = 40,\n\tNL80211_EXT_FEATURE_BEACON_PROTECTION = 41,\n\tNL80211_EXT_FEATURE_CONTROL_PORT_NO_PREAUTH = 42,\n\tNL80211_EXT_FEATURE_PROTECTED_TWT = 43,\n\tNL80211_EXT_FEATURE_DEL_IBSS_STA = 44,\n\tNL80211_EXT_FEATURE_MULTICAST_REGISTRATIONS = 45,\n\tNL80211_EXT_FEATURE_BEACON_PROTECTION_CLIENT = 46,\n\tNL80211_EXT_FEATURE_SCAN_FREQ_KHZ = 47,\n\tNL80211_EXT_FEATURE_CONTROL_PORT_OVER_NL80211_TX_STATUS = 48,\n\tNUM_NL80211_EXT_FEATURES = 49,\n\tMAX_NL80211_EXT_FEATURES = 48,\n};\n\nenum nl80211_timeout_reason {\n\tNL80211_TIMEOUT_UNSPECIFIED = 0,\n\tNL80211_TIMEOUT_SCAN = 1,\n\tNL80211_TIMEOUT_AUTH = 2,\n\tNL80211_TIMEOUT_ASSOC = 3,\n};\n\nenum nl80211_acl_policy {\n\tNL80211_ACL_POLICY_ACCEPT_UNLESS_LISTED = 0,\n\tNL80211_ACL_POLICY_DENY_UNLESS_LISTED = 1,\n};\n\nenum nl80211_smps_mode {\n\tNL80211_SMPS_OFF = 0,\n\tNL80211_SMPS_STATIC = 1,\n\tNL80211_SMPS_DYNAMIC = 2,\n\t__NL80211_SMPS_AFTER_LAST = 3,\n\tNL80211_SMPS_MAX = 2,\n};\n\nenum nl80211_radar_event {\n\tNL80211_RADAR_DETECTED = 0,\n\tNL80211_RADAR_CAC_FINISHED = 1,\n\tNL80211_RADAR_CAC_ABORTED = 2,\n\tNL80211_RADAR_NOP_FINISHED = 3,\n\tNL80211_RADAR_PRE_CAC_EXPIRED = 4,\n\tNL80211_RADAR_CAC_STARTED = 5,\n};\n\nenum nl80211_dfs_state {\n\tNL80211_DFS_USABLE = 0,\n\tNL80211_DFS_UNAVAILABLE = 1,\n\tNL80211_DFS_AVAILABLE = 2,\n};\n\nenum nl80211_crit_proto_id {\n\tNL80211_CRIT_PROTO_UNSPEC = 0,\n\tNL80211_CRIT_PROTO_DHCP = 1,\n\tNL80211_CRIT_PROTO_EAPOL = 2,\n\tNL80211_CRIT_PROTO_APIPA = 3,\n\tNUM_NL80211_CRIT_PROTO = 4,\n};\n\nstruct nl80211_vendor_cmd_info {\n\t__u32 vendor_id;\n\t__u32 subcmd;\n};\n\nenum nl80211_bss_select_attr {\n\t__NL80211_BSS_SELECT_ATTR_INVALID = 0,\n\tNL80211_BSS_SELECT_ATTR_RSSI = 1,\n\tNL80211_BSS_SELECT_ATTR_BAND_PREF = 2,\n\tNL80211_BSS_SELECT_ATTR_RSSI_ADJUST = 3,\n\t__NL80211_BSS_SELECT_ATTR_AFTER_LAST = 4,\n\tNL80211_BSS_SELECT_ATTR_MAX = 3,\n};\n\nenum nl80211_nan_function_type {\n\tNL80211_NAN_FUNC_PUBLISH = 0,\n\tNL80211_NAN_FUNC_SUBSCRIBE = 1,\n\tNL80211_NAN_FUNC_FOLLOW_UP = 2,\n\t__NL80211_NAN_FUNC_TYPE_AFTER_LAST = 3,\n\tNL80211_NAN_FUNC_MAX_TYPE = 2,\n};\n\nenum nl80211_external_auth_action {\n\tNL80211_EXTERNAL_AUTH_START = 0,\n\tNL80211_EXTERNAL_AUTH_ABORT = 1,\n};\n\nenum nl80211_preamble {\n\tNL80211_PREAMBLE_LEGACY = 0,\n\tNL80211_PREAMBLE_HT = 1,\n\tNL80211_PREAMBLE_VHT = 2,\n\tNL80211_PREAMBLE_DMG = 3,\n\tNL80211_PREAMBLE_HE = 4,\n};\n\nenum ieee80211_bss_type {\n\tIEEE80211_BSS_TYPE_ESS = 0,\n\tIEEE80211_BSS_TYPE_PBSS = 1,\n\tIEEE80211_BSS_TYPE_IBSS = 2,\n\tIEEE80211_BSS_TYPE_MBSS = 3,\n\tIEEE80211_BSS_TYPE_ANY = 4,\n};\n\nenum ieee80211_edmg_bw_config {\n\tIEEE80211_EDMG_BW_CONFIG_4 = 4,\n\tIEEE80211_EDMG_BW_CONFIG_5 = 5,\n\tIEEE80211_EDMG_BW_CONFIG_6 = 6,\n\tIEEE80211_EDMG_BW_CONFIG_7 = 7,\n\tIEEE80211_EDMG_BW_CONFIG_8 = 8,\n\tIEEE80211_EDMG_BW_CONFIG_9 = 9,\n\tIEEE80211_EDMG_BW_CONFIG_10 = 10,\n\tIEEE80211_EDMG_BW_CONFIG_11 = 11,\n\tIEEE80211_EDMG_BW_CONFIG_12 = 12,\n\tIEEE80211_EDMG_BW_CONFIG_13 = 13,\n\tIEEE80211_EDMG_BW_CONFIG_14 = 14,\n\tIEEE80211_EDMG_BW_CONFIG_15 = 15,\n};\n\nstruct ieee80211_edmg {\n\tu8 channels;\n\tenum ieee80211_edmg_bw_config bw_config;\n};\n\nstruct ieee80211_channel;\n\nstruct cfg80211_chan_def {\n\tstruct ieee80211_channel *chan;\n\tenum nl80211_chan_width width;\n\tu32 center_freq1;\n\tu32 center_freq2;\n\tstruct ieee80211_edmg edmg;\n\tu16 freq1_offset;\n};\n\nstruct wiphy;\n\nstruct cfg80211_conn;\n\nstruct cfg80211_cached_keys;\n\nstruct cfg80211_internal_bss;\n\nstruct cfg80211_cqm_config;\n\nstruct wireless_dev {\n\tstruct wiphy *wiphy;\n\tenum nl80211_iftype iftype;\n\tstruct list_head list;\n\tstruct net_device *netdev;\n\tu32 identifier;\n\tstruct list_head mgmt_registrations;\n\tspinlock_t mgmt_registrations_lock;\n\tu8 mgmt_registrations_need_update: 1;\n\tstruct mutex mtx;\n\tbool use_4addr;\n\tbool is_running;\n\tu8 address[6];\n\tu8 ssid[32];\n\tu8 ssid_len;\n\tu8 mesh_id_len;\n\tu8 mesh_id_up_len;\n\tstruct cfg80211_conn *conn;\n\tstruct cfg80211_cached_keys *connect_keys;\n\tenum ieee80211_bss_type conn_bss_type;\n\tu32 conn_owner_nlportid;\n\tstruct work_struct disconnect_wk;\n\tu8 disconnect_bssid[6];\n\tstruct list_head event_list;\n\tspinlock_t event_lock;\n\tstruct cfg80211_internal_bss *current_bss;\n\tstruct cfg80211_chan_def preset_chandef;\n\tstruct cfg80211_chan_def chandef;\n\tbool ibss_fixed;\n\tbool ibss_dfs_possible;\n\tbool ps;\n\tint ps_timeout;\n\tint beacon_interval;\n\tu32 ap_unexpected_nlportid;\n\tu32 owner_nlportid;\n\tbool nl_owner_dead;\n\tbool cac_started;\n\tlong unsigned int cac_start_time;\n\tunsigned int cac_time_ms;\n\tstruct cfg80211_cqm_config *cqm_config;\n\tstruct list_head pmsr_list;\n\tspinlock_t pmsr_lock;\n\tstruct work_struct pmsr_free_wk;\n\tlong unsigned int unprot_beacon_reported;\n};\n\nstruct ieee80211_mcs_info {\n\tu8 rx_mask[10];\n\t__le16 rx_highest;\n\tu8 tx_params;\n\tu8 reserved[3];\n};\n\nstruct ieee80211_ht_cap {\n\t__le16 cap_info;\n\tu8 ampdu_params_info;\n\tstruct ieee80211_mcs_info mcs;\n\t__le16 extended_ht_cap_info;\n\t__le32 tx_BF_cap_info;\n\tu8 antenna_selection_info;\n} __attribute__((packed));\n\nstruct ieee80211_vht_mcs_info {\n\t__le16 rx_mcs_map;\n\t__le16 rx_highest;\n\t__le16 tx_mcs_map;\n\t__le16 tx_highest;\n};\n\nstruct ieee80211_vht_cap {\n\t__le32 vht_cap_info;\n\tstruct ieee80211_vht_mcs_info supp_mcs;\n};\n\nstruct ieee80211_he_cap_elem {\n\tu8 mac_cap_info[6];\n\tu8 phy_cap_info[11];\n};\n\nstruct ieee80211_he_mcs_nss_supp {\n\t__le16 rx_mcs_80;\n\t__le16 tx_mcs_80;\n\t__le16 rx_mcs_160;\n\t__le16 tx_mcs_160;\n\t__le16 rx_mcs_80p80;\n\t__le16 tx_mcs_80p80;\n};\n\nstruct ieee80211_he_operation {\n\t__le32 he_oper_params;\n\t__le16 he_mcs_nss_set;\n\tu8 optional[0];\n} __attribute__((packed));\n\nenum ieee80211_reasoncode {\n\tWLAN_REASON_UNSPECIFIED = 1,\n\tWLAN_REASON_PREV_AUTH_NOT_VALID = 2,\n\tWLAN_REASON_DEAUTH_LEAVING = 3,\n\tWLAN_REASON_DISASSOC_DUE_TO_INACTIVITY = 4,\n\tWLAN_REASON_DISASSOC_AP_BUSY = 5,\n\tWLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA = 6,\n\tWLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA = 7,\n\tWLAN_REASON_DISASSOC_STA_HAS_LEFT = 8,\n\tWLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH = 9,\n\tWLAN_REASON_DISASSOC_BAD_POWER = 10,\n\tWLAN_REASON_DISASSOC_BAD_SUPP_CHAN = 11,\n\tWLAN_REASON_INVALID_IE = 13,\n\tWLAN_REASON_MIC_FAILURE = 14,\n\tWLAN_REASON_4WAY_HANDSHAKE_TIMEOUT = 15,\n\tWLAN_REASON_GROUP_KEY_HANDSHAKE_TIMEOUT = 16,\n\tWLAN_REASON_IE_DIFFERENT = 17,\n\tWLAN_REASON_INVALID_GROUP_CIPHER = 18,\n\tWLAN_REASON_INVALID_PAIRWISE_CIPHER = 19,\n\tWLAN_REASON_INVALID_AKMP = 20,\n\tWLAN_REASON_UNSUPP_RSN_VERSION = 21,\n\tWLAN_REASON_INVALID_RSN_IE_CAP = 22,\n\tWLAN_REASON_IEEE8021X_FAILED = 23,\n\tWLAN_REASON_CIPHER_SUITE_REJECTED = 24,\n\tWLAN_REASON_TDLS_TEARDOWN_UNREACHABLE = 25,\n\tWLAN_REASON_TDLS_TEARDOWN_UNSPECIFIED = 26,\n\tWLAN_REASON_DISASSOC_UNSPECIFIED_QOS = 32,\n\tWLAN_REASON_DISASSOC_QAP_NO_BANDWIDTH = 33,\n\tWLAN_REASON_DISASSOC_LOW_ACK = 34,\n\tWLAN_REASON_DISASSOC_QAP_EXCEED_TXOP = 35,\n\tWLAN_REASON_QSTA_LEAVE_QBSS = 36,\n\tWLAN_REASON_QSTA_NOT_USE = 37,\n\tWLAN_REASON_QSTA_REQUIRE_SETUP = 38,\n\tWLAN_REASON_QSTA_TIMEOUT = 39,\n\tWLAN_REASON_QSTA_CIPHER_NOT_SUPP = 45,\n\tWLAN_REASON_MESH_PEER_CANCELED = 52,\n\tWLAN_REASON_MESH_MAX_PEERS = 53,\n\tWLAN_REASON_MESH_CONFIG = 54,\n\tWLAN_REASON_MESH_CLOSE = 55,\n\tWLAN_REASON_MESH_MAX_RETRIES = 56,\n\tWLAN_REASON_MESH_CONFIRM_TIMEOUT = 57,\n\tWLAN_REASON_MESH_INVALID_GTK = 58,\n\tWLAN_REASON_MESH_INCONSISTENT_PARAM = 59,\n\tWLAN_REASON_MESH_INVALID_SECURITY = 60,\n\tWLAN_REASON_MESH_PATH_ERROR = 61,\n\tWLAN_REASON_MESH_PATH_NOFORWARD = 62,\n\tWLAN_REASON_MESH_PATH_DEST_UNREACHABLE = 63,\n\tWLAN_REASON_MAC_EXISTS_IN_MBSS = 64,\n\tWLAN_REASON_MESH_CHAN_REGULATORY = 65,\n\tWLAN_REASON_MESH_CHAN = 66,\n};\n\nenum ieee80211_key_len {\n\tWLAN_KEY_LEN_WEP40 = 5,\n\tWLAN_KEY_LEN_WEP104 = 13,\n\tWLAN_KEY_LEN_CCMP = 16,\n\tWLAN_KEY_LEN_CCMP_256 = 32,\n\tWLAN_KEY_LEN_TKIP = 32,\n\tWLAN_KEY_LEN_AES_CMAC = 16,\n\tWLAN_KEY_LEN_SMS4 = 32,\n\tWLAN_KEY_LEN_GCMP = 16,\n\tWLAN_KEY_LEN_GCMP_256 = 32,\n\tWLAN_KEY_LEN_BIP_CMAC_256 = 32,\n\tWLAN_KEY_LEN_BIP_GMAC_128 = 16,\n\tWLAN_KEY_LEN_BIP_GMAC_256 = 32,\n};\n\nstruct ieee80211_he_6ghz_capa {\n\t__le16 capa;\n};\n\nenum environment_cap {\n\tENVIRON_ANY = 0,\n\tENVIRON_INDOOR = 1,\n\tENVIRON_OUTDOOR = 2,\n};\n\nstruct regulatory_request {\n\tstruct callback_head callback_head;\n\tint wiphy_idx;\n\tenum nl80211_reg_initiator initiator;\n\tenum nl80211_user_reg_hint_type user_reg_hint_type;\n\tchar alpha2[3];\n\tenum nl80211_dfs_regions dfs_region;\n\tbool intersect;\n\tbool processed;\n\tenum environment_cap country_ie_env;\n\tstruct list_head list;\n};\n\nenum ieee80211_regulatory_flags {\n\tREGULATORY_CUSTOM_REG = 1,\n\tREGULATORY_STRICT_REG = 2,\n\tREGULATORY_DISABLE_BEACON_HINTS = 4,\n\tREGULATORY_COUNTRY_IE_FOLLOW_POWER = 8,\n\tREGULATORY_COUNTRY_IE_IGNORE = 16,\n\tREGULATORY_ENABLE_RELAX_NO_IR = 32,\n\tREGULATORY_IGNORE_STALE_KICKOFF = 64,\n\tREGULATORY_WIPHY_SELF_MANAGED = 128,\n};\n\nstruct ieee80211_freq_range {\n\tu32 start_freq_khz;\n\tu32 end_freq_khz;\n\tu32 max_bandwidth_khz;\n};\n\nstruct ieee80211_power_rule {\n\tu32 max_antenna_gain;\n\tu32 max_eirp;\n};\n\nstruct ieee80211_wmm_ac {\n\tu16 cw_min;\n\tu16 cw_max;\n\tu16 cot;\n\tu8 aifsn;\n};\n\nstruct ieee80211_wmm_rule {\n\tstruct ieee80211_wmm_ac client[4];\n\tstruct ieee80211_wmm_ac ap[4];\n};\n\nstruct ieee80211_reg_rule {\n\tstruct ieee80211_freq_range freq_range;\n\tstruct ieee80211_power_rule power_rule;\n\tstruct ieee80211_wmm_rule wmm_rule;\n\tu32 flags;\n\tu32 dfs_cac_ms;\n\tbool has_wmm;\n};\n\nstruct ieee80211_regdomain {\n\tstruct callback_head callback_head;\n\tu32 n_reg_rules;\n\tchar alpha2[3];\n\tenum nl80211_dfs_regions dfs_region;\n\tstruct ieee80211_reg_rule reg_rules[0];\n};\n\nstruct ieee80211_channel {\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tu16 hw_value;\n\tu32 flags;\n\tint max_antenna_gain;\n\tint max_power;\n\tint max_reg_power;\n\tbool beacon_found;\n\tu32 orig_flags;\n\tint orig_mag;\n\tint orig_mpwr;\n\tenum nl80211_dfs_state dfs_state;\n\tlong unsigned int dfs_state_entered;\n\tunsigned int dfs_cac_ms;\n};\n\nstruct ieee80211_rate {\n\tu32 flags;\n\tu16 bitrate;\n\tu16 hw_value;\n\tu16 hw_value_short;\n};\n\nstruct ieee80211_he_obss_pd {\n\tbool enable;\n\tu8 min_offset;\n\tu8 max_offset;\n};\n\nstruct cfg80211_he_bss_color {\n\tu8 color;\n\tbool disabled;\n\tbool partial;\n};\n\nstruct ieee80211_sta_ht_cap {\n\tu16 cap;\n\tbool ht_supported;\n\tu8 ampdu_factor;\n\tu8 ampdu_density;\n\tstruct ieee80211_mcs_info mcs;\n\tchar: 8;\n} __attribute__((packed));\n\nstruct ieee80211_sta_vht_cap {\n\tbool vht_supported;\n\tu32 cap;\n\tstruct ieee80211_vht_mcs_info vht_mcs;\n};\n\nstruct ieee80211_sta_he_cap {\n\tbool has_he;\n\tstruct ieee80211_he_cap_elem he_cap_elem;\n\tstruct ieee80211_he_mcs_nss_supp he_mcs_nss_supp;\n\tu8 ppe_thres[25];\n} __attribute__((packed));\n\nstruct ieee80211_sband_iftype_data {\n\tu16 types_mask;\n\tstruct ieee80211_sta_he_cap he_cap;\n\tstruct ieee80211_he_6ghz_capa he_6ghz_capa;\n\tchar: 8;\n} __attribute__((packed));\n\nstruct ieee80211_supported_band {\n\tstruct ieee80211_channel *channels;\n\tstruct ieee80211_rate *bitrates;\n\tenum nl80211_band band;\n\tint n_channels;\n\tint n_bitrates;\n\tstruct ieee80211_sta_ht_cap ht_cap;\n\tstruct ieee80211_sta_vht_cap vht_cap;\n\tstruct ieee80211_edmg edmg_cap;\n\tu16 n_iftype_data;\n\tconst struct ieee80211_sband_iftype_data *iftype_data;\n};\n\nstruct vif_params {\n\tu32 flags;\n\tint use_4addr;\n\tu8 macaddr[6];\n\tconst u8 *vht_mumimo_groups;\n\tconst u8 *vht_mumimo_follow_addr;\n};\n\nstruct key_params {\n\tconst u8 *key;\n\tconst u8 *seq;\n\tint key_len;\n\tint seq_len;\n\tu16 vlan_id;\n\tu32 cipher;\n\tenum nl80211_key_mode mode;\n};\n\nstruct cfg80211_bitrate_mask {\n\tstruct {\n\t\tu32 legacy;\n\t\tu8 ht_mcs[10];\n\t\tu16 vht_mcs[8];\n\t\tenum nl80211_txrate_gi gi;\n\t} control[4];\n};\n\nstruct cfg80211_tid_cfg {\n\tbool config_override;\n\tu8 tids;\n\tu64 mask;\n\tenum nl80211_tid_config noack;\n\tu8 retry_long;\n\tu8 retry_short;\n\tenum nl80211_tid_config ampdu;\n\tenum nl80211_tid_config rtscts;\n\tenum nl80211_tid_config amsdu;\n\tenum nl80211_tx_rate_setting txrate_type;\n\tstruct cfg80211_bitrate_mask txrate_mask;\n};\n\nstruct cfg80211_tid_config {\n\tconst u8 *peer;\n\tu32 n_tid_conf;\n\tstruct cfg80211_tid_cfg tid_conf[0];\n};\n\nstruct survey_info {\n\tstruct ieee80211_channel *channel;\n\tu64 time;\n\tu64 time_busy;\n\tu64 time_ext_busy;\n\tu64 time_rx;\n\tu64 time_tx;\n\tu64 time_scan;\n\tu64 time_bss_rx;\n\tu32 filled;\n\ts8 noise;\n};\n\nstruct cfg80211_crypto_settings {\n\tu32 wpa_versions;\n\tu32 cipher_group;\n\tint n_ciphers_pairwise;\n\tu32 ciphers_pairwise[5];\n\tint n_akm_suites;\n\tu32 akm_suites[2];\n\tbool control_port;\n\t__be16 control_port_ethertype;\n\tbool control_port_no_encrypt;\n\tbool control_port_over_nl80211;\n\tbool control_port_no_preauth;\n\tstruct key_params *wep_keys;\n\tint wep_tx_key;\n\tconst u8 *psk;\n\tconst u8 *sae_pwd;\n\tu8 sae_pwd_len;\n};\n\nstruct cfg80211_beacon_data {\n\tconst u8 *head;\n\tconst u8 *tail;\n\tconst u8 *beacon_ies;\n\tconst u8 *proberesp_ies;\n\tconst u8 *assocresp_ies;\n\tconst u8 *probe_resp;\n\tconst u8 *lci;\n\tconst u8 *civicloc;\n\ts8 ftm_responder;\n\tsize_t head_len;\n\tsize_t tail_len;\n\tsize_t beacon_ies_len;\n\tsize_t proberesp_ies_len;\n\tsize_t assocresp_ies_len;\n\tsize_t probe_resp_len;\n\tsize_t lci_len;\n\tsize_t civicloc_len;\n};\n\nstruct mac_address {\n\tu8 addr[6];\n};\n\nstruct cfg80211_acl_data {\n\tenum nl80211_acl_policy acl_policy;\n\tint n_acl_entries;\n\tstruct mac_address mac_addrs[0];\n};\n\nstruct cfg80211_ap_settings {\n\tstruct cfg80211_chan_def chandef;\n\tstruct cfg80211_beacon_data beacon;\n\tint beacon_interval;\n\tint dtim_period;\n\tconst u8 *ssid;\n\tsize_t ssid_len;\n\tenum nl80211_hidden_ssid hidden_ssid;\n\tstruct cfg80211_crypto_settings crypto;\n\tbool privacy;\n\tenum nl80211_auth_type auth_type;\n\tenum nl80211_smps_mode smps_mode;\n\tint inactivity_timeout;\n\tu8 p2p_ctwindow;\n\tbool p2p_opp_ps;\n\tconst struct cfg80211_acl_data *acl;\n\tbool pbss;\n\tstruct cfg80211_bitrate_mask beacon_rate;\n\tconst struct ieee80211_ht_cap *ht_cap;\n\tconst struct ieee80211_vht_cap *vht_cap;\n\tconst struct ieee80211_he_cap_elem *he_cap;\n\tconst struct ieee80211_he_operation *he_oper;\n\tbool ht_required;\n\tbool vht_required;\n\tbool he_required;\n\tbool twt_responder;\n\tu32 flags;\n\tstruct ieee80211_he_obss_pd he_obss_pd;\n\tstruct cfg80211_he_bss_color he_bss_color;\n};\n\nstruct cfg80211_csa_settings {\n\tstruct cfg80211_chan_def chandef;\n\tstruct cfg80211_beacon_data beacon_csa;\n\tconst u16 *counter_offsets_beacon;\n\tconst u16 *counter_offsets_presp;\n\tunsigned int n_counter_offsets_beacon;\n\tunsigned int n_counter_offsets_presp;\n\tstruct cfg80211_beacon_data beacon_after;\n\tbool radar_required;\n\tbool block_tx;\n\tu8 count;\n};\n\nstruct sta_txpwr {\n\ts16 power;\n\tenum nl80211_tx_power_setting type;\n};\n\nstruct station_parameters {\n\tconst u8 *supported_rates;\n\tstruct net_device *vlan;\n\tu32 sta_flags_mask;\n\tu32 sta_flags_set;\n\tu32 sta_modify_mask;\n\tint listen_interval;\n\tu16 aid;\n\tu16 vlan_id;\n\tu16 peer_aid;\n\tu8 supported_rates_len;\n\tu8 plink_action;\n\tu8 plink_state;\n\tconst struct ieee80211_ht_cap *ht_capa;\n\tconst struct ieee80211_vht_cap *vht_capa;\n\tu8 uapsd_queues;\n\tu8 max_sp;\n\tenum nl80211_mesh_power_mode local_pm;\n\tu16 capability;\n\tconst u8 *ext_capab;\n\tu8 ext_capab_len;\n\tconst u8 *supported_channels;\n\tu8 supported_channels_len;\n\tconst u8 *supported_oper_classes;\n\tu8 supported_oper_classes_len;\n\tu8 opmode_notif;\n\tbool opmode_notif_used;\n\tint support_p2p_ps;\n\tconst struct ieee80211_he_cap_elem *he_capa;\n\tu8 he_capa_len;\n\tu16 airtime_weight;\n\tstruct sta_txpwr txpwr;\n\tconst struct ieee80211_he_6ghz_capa *he_6ghz_capa;\n};\n\nstruct station_del_parameters {\n\tconst u8 *mac;\n\tu8 subtype;\n\tu16 reason_code;\n};\n\nstruct rate_info {\n\tu8 flags;\n\tu8 mcs;\n\tu16 legacy;\n\tu8 nss;\n\tu8 bw;\n\tu8 he_gi;\n\tu8 he_dcm;\n\tu8 he_ru_alloc;\n\tu8 n_bonded_ch;\n};\n\nstruct sta_bss_parameters {\n\tu8 flags;\n\tu8 dtim_period;\n\tu16 beacon_interval;\n};\n\nstruct cfg80211_txq_stats {\n\tu32 filled;\n\tu32 backlog_bytes;\n\tu32 backlog_packets;\n\tu32 flows;\n\tu32 drops;\n\tu32 ecn_marks;\n\tu32 overlimit;\n\tu32 overmemory;\n\tu32 collisions;\n\tu32 tx_bytes;\n\tu32 tx_packets;\n\tu32 max_flows;\n};\n\nstruct cfg80211_tid_stats {\n\tu32 filled;\n\tu64 rx_msdu;\n\tu64 tx_msdu;\n\tu64 tx_msdu_retries;\n\tu64 tx_msdu_failed;\n\tstruct cfg80211_txq_stats txq_stats;\n};\n\nstruct station_info {\n\tu64 filled;\n\tu32 connected_time;\n\tu32 inactive_time;\n\tu64 assoc_at;\n\tu64 rx_bytes;\n\tu64 tx_bytes;\n\tu16 llid;\n\tu16 plid;\n\tu8 plink_state;\n\ts8 signal;\n\ts8 signal_avg;\n\tu8 chains;\n\ts8 chain_signal[4];\n\ts8 chain_signal_avg[4];\n\tstruct rate_info txrate;\n\tstruct rate_info rxrate;\n\tu32 rx_packets;\n\tu32 tx_packets;\n\tu32 tx_retries;\n\tu32 tx_failed;\n\tu32 rx_dropped_misc;\n\tstruct sta_bss_parameters bss_param;\n\tstruct nl80211_sta_flag_update sta_flags;\n\tint generation;\n\tconst u8 *assoc_req_ies;\n\tsize_t assoc_req_ies_len;\n\tu32 beacon_loss_count;\n\ts64 t_offset;\n\tenum nl80211_mesh_power_mode local_pm;\n\tenum nl80211_mesh_power_mode peer_pm;\n\tenum nl80211_mesh_power_mode nonpeer_pm;\n\tu32 expected_throughput;\n\tu64 tx_duration;\n\tu64 rx_duration;\n\tu64 rx_beacon;\n\tu8 rx_beacon_signal_avg;\n\tu8 connected_to_gate;\n\tstruct cfg80211_tid_stats *pertid;\n\ts8 ack_signal;\n\ts8 avg_ack_signal;\n\tu16 airtime_weight;\n\tu32 rx_mpdu_count;\n\tu32 fcs_err_count;\n\tu32 airtime_link_metric;\n};\n\nstruct mpath_info {\n\tu32 filled;\n\tu32 frame_qlen;\n\tu32 sn;\n\tu32 metric;\n\tu32 exptime;\n\tu32 discovery_timeout;\n\tu8 discovery_retries;\n\tu8 flags;\n\tu8 hop_count;\n\tu32 path_change_count;\n\tint generation;\n};\n\nstruct bss_parameters {\n\tint use_cts_prot;\n\tint use_short_preamble;\n\tint use_short_slot_time;\n\tconst u8 *basic_rates;\n\tu8 basic_rates_len;\n\tint ap_isolate;\n\tint ht_opmode;\n\ts8 p2p_ctwindow;\n\ts8 p2p_opp_ps;\n};\n\nstruct mesh_config {\n\tu16 dot11MeshRetryTimeout;\n\tu16 dot11MeshConfirmTimeout;\n\tu16 dot11MeshHoldingTimeout;\n\tu16 dot11MeshMaxPeerLinks;\n\tu8 dot11MeshMaxRetries;\n\tu8 dot11MeshTTL;\n\tu8 element_ttl;\n\tbool auto_open_plinks;\n\tu32 dot11MeshNbrOffsetMaxNeighbor;\n\tu8 dot11MeshHWMPmaxPREQretries;\n\tu32 path_refresh_time;\n\tu16 min_discovery_timeout;\n\tu32 dot11MeshHWMPactivePathTimeout;\n\tu16 dot11MeshHWMPpreqMinInterval;\n\tu16 dot11MeshHWMPperrMinInterval;\n\tu16 dot11MeshHWMPnetDiameterTraversalTime;\n\tu8 dot11MeshHWMPRootMode;\n\tbool dot11MeshConnectedToMeshGate;\n\tu16 dot11MeshHWMPRannInterval;\n\tbool dot11MeshGateAnnouncementProtocol;\n\tbool dot11MeshForwarding;\n\ts32 rssi_threshold;\n\tu16 ht_opmode;\n\tu32 dot11MeshHWMPactivePathToRootTimeout;\n\tu16 dot11MeshHWMProotInterval;\n\tu16 dot11MeshHWMPconfirmationInterval;\n\tenum nl80211_mesh_power_mode power_mode;\n\tu16 dot11MeshAwakeWindowDuration;\n\tu32 plink_timeout;\n};\n\nstruct mesh_setup {\n\tstruct cfg80211_chan_def chandef;\n\tconst u8 *mesh_id;\n\tu8 mesh_id_len;\n\tu8 sync_method;\n\tu8 path_sel_proto;\n\tu8 path_metric;\n\tu8 auth_id;\n\tconst u8 *ie;\n\tu8 ie_len;\n\tbool is_authenticated;\n\tbool is_secure;\n\tbool user_mpm;\n\tu8 dtim_period;\n\tu16 beacon_interval;\n\tint mcast_rate[4];\n\tu32 basic_rates;\n\tstruct cfg80211_bitrate_mask beacon_rate;\n\tbool userspace_handles_dfs;\n\tbool control_port_over_nl80211;\n};\n\nstruct ocb_setup {\n\tstruct cfg80211_chan_def chandef;\n};\n\nstruct ieee80211_txq_params {\n\tenum nl80211_ac ac;\n\tu16 txop;\n\tu16 cwmin;\n\tu16 cwmax;\n\tu8 aifs;\n};\n\nstruct cfg80211_ssid {\n\tu8 ssid[32];\n\tu8 ssid_len;\n};\n\nstruct cfg80211_scan_info {\n\tu64 scan_start_tsf;\n\tu8 tsf_bssid[6];\n\tbool aborted;\n};\n\nstruct cfg80211_scan_request {\n\tstruct cfg80211_ssid *ssids;\n\tint n_ssids;\n\tu32 n_channels;\n\tenum nl80211_bss_scan_width scan_width;\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tu16 duration;\n\tbool duration_mandatory;\n\tu32 flags;\n\tu32 rates[4];\n\tstruct wireless_dev *wdev;\n\tu8 mac_addr[6];\n\tu8 mac_addr_mask[6];\n\tu8 bssid[6];\n\tstruct wiphy *wiphy;\n\tlong unsigned int scan_start;\n\tstruct cfg80211_scan_info info;\n\tbool notified;\n\tbool no_cck;\n\tstruct ieee80211_channel *channels[0];\n};\n\nenum cfg80211_signal_type {\n\tCFG80211_SIGNAL_TYPE_NONE = 0,\n\tCFG80211_SIGNAL_TYPE_MBM = 1,\n\tCFG80211_SIGNAL_TYPE_UNSPEC = 2,\n};\n\nstruct ieee80211_txrx_stypes;\n\nstruct ieee80211_iface_combination;\n\nstruct wiphy_iftype_akm_suites;\n\nstruct wiphy_wowlan_support;\n\nstruct cfg80211_wowlan;\n\nstruct wiphy_iftype_ext_capab;\n\nstruct wiphy_coalesce_support;\n\nstruct wiphy_vendor_command;\n\nstruct cfg80211_pmsr_capabilities;\n\nstruct wiphy {\n\tu8 perm_addr[6];\n\tu8 addr_mask[6];\n\tstruct mac_address *addresses;\n\tconst struct ieee80211_txrx_stypes *mgmt_stypes;\n\tconst struct ieee80211_iface_combination *iface_combinations;\n\tint n_iface_combinations;\n\tu16 software_iftypes;\n\tu16 n_addresses;\n\tu16 interface_modes;\n\tu16 max_acl_mac_addrs;\n\tu32 flags;\n\tu32 regulatory_flags;\n\tu32 features;\n\tu8 ext_features[7];\n\tu32 ap_sme_capa;\n\tenum cfg80211_signal_type signal_type;\n\tint bss_priv_size;\n\tu8 max_scan_ssids;\n\tu8 max_sched_scan_reqs;\n\tu8 max_sched_scan_ssids;\n\tu8 max_match_sets;\n\tu16 max_scan_ie_len;\n\tu16 max_sched_scan_ie_len;\n\tu32 max_sched_scan_plans;\n\tu32 max_sched_scan_plan_interval;\n\tu32 max_sched_scan_plan_iterations;\n\tint n_cipher_suites;\n\tconst u32 *cipher_suites;\n\tint n_akm_suites;\n\tconst u32 *akm_suites;\n\tconst struct wiphy_iftype_akm_suites *iftype_akm_suites;\n\tunsigned int num_iftype_akm_suites;\n\tu8 retry_short;\n\tu8 retry_long;\n\tu32 frag_threshold;\n\tu32 rts_threshold;\n\tu8 coverage_class;\n\tchar fw_version[32];\n\tu32 hw_version;\n\tconst struct wiphy_wowlan_support *wowlan;\n\tstruct cfg80211_wowlan *wowlan_config;\n\tu16 max_remain_on_channel_duration;\n\tu8 max_num_pmkids;\n\tu32 available_antennas_tx;\n\tu32 available_antennas_rx;\n\tu32 probe_resp_offload;\n\tconst u8 *extended_capabilities;\n\tconst u8 *extended_capabilities_mask;\n\tu8 extended_capabilities_len;\n\tconst struct wiphy_iftype_ext_capab *iftype_ext_capab;\n\tunsigned int num_iftype_ext_capab;\n\tconst void *privid;\n\tstruct ieee80211_supported_band *bands[4];\n\tvoid (*reg_notifier)(struct wiphy *, struct regulatory_request *);\n\tconst struct ieee80211_regdomain *regd;\n\tstruct device dev;\n\tbool registered;\n\tstruct dentry *debugfsdir;\n\tconst struct ieee80211_ht_cap *ht_capa_mod_mask;\n\tconst struct ieee80211_vht_cap *vht_capa_mod_mask;\n\tstruct list_head wdev_list;\n\tpossible_net_t _net;\n\tconst struct wiphy_coalesce_support *coalesce;\n\tconst struct wiphy_vendor_command *vendor_commands;\n\tconst struct nl80211_vendor_cmd_info *vendor_events;\n\tint n_vendor_commands;\n\tint n_vendor_events;\n\tu16 max_ap_assoc_sta;\n\tu8 max_num_csa_counters;\n\tu32 bss_select_support;\n\tu8 nan_supported_bands;\n\tu32 txq_limit;\n\tu32 txq_memory_limit;\n\tu32 txq_quantum;\n\tlong unsigned int tx_queue_len;\n\tu8 support_mbssid: 1;\n\tu8 support_only_he_mbssid: 1;\n\tconst struct cfg80211_pmsr_capabilities *pmsr_capa;\n\tstruct {\n\t\tu64 peer;\n\t\tu64 vif;\n\t\tu8 max_retry;\n\t} tid_config_support;\n\tu8 max_data_retry_count;\n\tlong: 56;\n\tlong: 64;\n\tlong: 64;\n\tchar priv[0];\n};\n\nstruct cfg80211_match_set {\n\tstruct cfg80211_ssid ssid;\n\tu8 bssid[6];\n\ts32 rssi_thold;\n\ts32 per_band_rssi_thold[4];\n};\n\nstruct cfg80211_sched_scan_plan {\n\tu32 interval;\n\tu32 iterations;\n};\n\nstruct cfg80211_bss_select_adjust {\n\tenum nl80211_band band;\n\ts8 delta;\n};\n\nstruct cfg80211_sched_scan_request {\n\tu64 reqid;\n\tstruct cfg80211_ssid *ssids;\n\tint n_ssids;\n\tu32 n_channels;\n\tenum nl80211_bss_scan_width scan_width;\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tu32 flags;\n\tstruct cfg80211_match_set *match_sets;\n\tint n_match_sets;\n\ts32 min_rssi_thold;\n\tu32 delay;\n\tstruct cfg80211_sched_scan_plan *scan_plans;\n\tint n_scan_plans;\n\tu8 mac_addr[6];\n\tu8 mac_addr_mask[6];\n\tbool relative_rssi_set;\n\ts8 relative_rssi;\n\tstruct cfg80211_bss_select_adjust rssi_adjust;\n\tstruct wiphy *wiphy;\n\tstruct net_device *dev;\n\tlong unsigned int scan_start;\n\tbool report_results;\n\tstruct callback_head callback_head;\n\tu32 owner_nlportid;\n\tbool nl_owner_dead;\n\tstruct list_head list;\n\tstruct ieee80211_channel *channels[0];\n};\n\nstruct cfg80211_bss_ies {\n\tu64 tsf;\n\tstruct callback_head callback_head;\n\tint len;\n\tbool from_beacon;\n\tu8 data[0];\n};\n\nstruct cfg80211_bss {\n\tstruct ieee80211_channel *channel;\n\tenum nl80211_bss_scan_width scan_width;\n\tconst struct cfg80211_bss_ies *ies;\n\tconst struct cfg80211_bss_ies *beacon_ies;\n\tconst struct cfg80211_bss_ies *proberesp_ies;\n\tstruct cfg80211_bss *hidden_beacon_bss;\n\tstruct cfg80211_bss *transmitted_bss;\n\tstruct list_head nontrans_list;\n\ts32 signal;\n\tu16 beacon_interval;\n\tu16 capability;\n\tu8 bssid[6];\n\tu8 chains;\n\ts8 chain_signal[4];\n\tu8 bssid_index;\n\tu8 max_bssid_indicator;\n\tint: 24;\n\tu8 priv[0];\n};\n\nstruct cfg80211_auth_request {\n\tstruct cfg80211_bss *bss;\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tenum nl80211_auth_type auth_type;\n\tconst u8 *key;\n\tu8 key_len;\n\tu8 key_idx;\n\tconst u8 *auth_data;\n\tsize_t auth_data_len;\n};\n\nstruct cfg80211_assoc_request {\n\tstruct cfg80211_bss *bss;\n\tconst u8 *ie;\n\tconst u8 *prev_bssid;\n\tsize_t ie_len;\n\tstruct cfg80211_crypto_settings crypto;\n\tbool use_mfp;\n\tint: 24;\n\tu32 flags;\n\tstruct ieee80211_ht_cap ht_capa;\n\tstruct ieee80211_ht_cap ht_capa_mask;\n\tstruct ieee80211_vht_cap vht_capa;\n\tstruct ieee80211_vht_cap vht_capa_mask;\n\tint: 32;\n\tconst u8 *fils_kek;\n\tsize_t fils_kek_len;\n\tconst u8 *fils_nonces;\n} __attribute__((packed));\n\nstruct cfg80211_deauth_request {\n\tconst u8 *bssid;\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tu16 reason_code;\n\tbool local_state_change;\n};\n\nstruct cfg80211_disassoc_request {\n\tstruct cfg80211_bss *bss;\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tu16 reason_code;\n\tbool local_state_change;\n};\n\nstruct cfg80211_ibss_params {\n\tconst u8 *ssid;\n\tconst u8 *bssid;\n\tstruct cfg80211_chan_def chandef;\n\tconst u8 *ie;\n\tu8 ssid_len;\n\tu8 ie_len;\n\tu16 beacon_interval;\n\tu32 basic_rates;\n\tbool channel_fixed;\n\tbool privacy;\n\tbool control_port;\n\tbool control_port_over_nl80211;\n\tbool userspace_handles_dfs;\n\tint: 24;\n\tint mcast_rate[4];\n\tstruct ieee80211_ht_cap ht_capa;\n\tstruct ieee80211_ht_cap ht_capa_mask;\n\tint: 32;\n\tstruct key_params *wep_keys;\n\tint wep_tx_key;\n\tint: 32;\n} __attribute__((packed));\n\nstruct cfg80211_bss_selection {\n\tenum nl80211_bss_select_attr behaviour;\n\tunion {\n\t\tenum nl80211_band band_pref;\n\t\tstruct cfg80211_bss_select_adjust adjust;\n\t} param;\n};\n\nstruct cfg80211_connect_params {\n\tstruct ieee80211_channel *channel;\n\tstruct ieee80211_channel *channel_hint;\n\tconst u8 *bssid;\n\tconst u8 *bssid_hint;\n\tconst u8 *ssid;\n\tsize_t ssid_len;\n\tenum nl80211_auth_type auth_type;\n\tint: 32;\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tbool privacy;\n\tint: 24;\n\tenum nl80211_mfp mfp;\n\tstruct cfg80211_crypto_settings crypto;\n\tconst u8 *key;\n\tu8 key_len;\n\tu8 key_idx;\n\tshort: 16;\n\tu32 flags;\n\tint bg_scan_period;\n\tstruct ieee80211_ht_cap ht_capa;\n\tstruct ieee80211_ht_cap ht_capa_mask;\n\tstruct ieee80211_vht_cap vht_capa;\n\tstruct ieee80211_vht_cap vht_capa_mask;\n\tbool pbss;\n\tint: 24;\n\tstruct cfg80211_bss_selection bss_select;\n\tconst u8 *prev_bssid;\n\tconst u8 *fils_erp_username;\n\tsize_t fils_erp_username_len;\n\tconst u8 *fils_erp_realm;\n\tsize_t fils_erp_realm_len;\n\tu16 fils_erp_next_seq_num;\n\tlong: 48;\n\tconst u8 *fils_erp_rrk;\n\tsize_t fils_erp_rrk_len;\n\tbool want_1x;\n\tint: 24;\n\tstruct ieee80211_edmg edmg;\n\tint: 32;\n} __attribute__((packed));\n\nstruct cfg80211_pmksa {\n\tconst u8 *bssid;\n\tconst u8 *pmkid;\n\tconst u8 *pmk;\n\tsize_t pmk_len;\n\tconst u8 *ssid;\n\tsize_t ssid_len;\n\tconst u8 *cache_id;\n\tu32 pmk_lifetime;\n\tu8 pmk_reauth_threshold;\n};\n\nstruct cfg80211_pkt_pattern {\n\tconst u8 *mask;\n\tconst u8 *pattern;\n\tint pattern_len;\n\tint pkt_offset;\n};\n\nstruct cfg80211_wowlan_tcp {\n\tstruct socket *sock;\n\t__be32 src;\n\t__be32 dst;\n\tu16 src_port;\n\tu16 dst_port;\n\tu8 dst_mac[6];\n\tint payload_len;\n\tconst u8 *payload;\n\tstruct nl80211_wowlan_tcp_data_seq payload_seq;\n\tu32 data_interval;\n\tu32 wake_len;\n\tconst u8 *wake_data;\n\tconst u8 *wake_mask;\n\tu32 tokens_size;\n\tstruct nl80211_wowlan_tcp_data_token payload_tok;\n};\n\nstruct cfg80211_wowlan {\n\tbool any;\n\tbool disconnect;\n\tbool magic_pkt;\n\tbool gtk_rekey_failure;\n\tbool eap_identity_req;\n\tbool four_way_handshake;\n\tbool rfkill_release;\n\tstruct cfg80211_pkt_pattern *patterns;\n\tstruct cfg80211_wowlan_tcp *tcp;\n\tint n_patterns;\n\tstruct cfg80211_sched_scan_request *nd_config;\n};\n\nstruct cfg80211_coalesce_rules {\n\tint delay;\n\tenum nl80211_coalesce_condition condition;\n\tstruct cfg80211_pkt_pattern *patterns;\n\tint n_patterns;\n};\n\nstruct cfg80211_coalesce {\n\tstruct cfg80211_coalesce_rules *rules;\n\tint n_rules;\n};\n\nstruct cfg80211_gtk_rekey_data {\n\tconst u8 *kek;\n\tconst u8 *kck;\n\tconst u8 *replay_ctr;\n\tu32 akm;\n\tu8 kek_len;\n\tu8 kck_len;\n};\n\nstruct cfg80211_update_ft_ies_params {\n\tu16 md;\n\tconst u8 *ie;\n\tsize_t ie_len;\n};\n\nstruct cfg80211_mgmt_tx_params {\n\tstruct ieee80211_channel *chan;\n\tbool offchan;\n\tunsigned int wait;\n\tconst u8 *buf;\n\tsize_t len;\n\tbool no_cck;\n\tbool dont_wait_for_ack;\n\tint n_csa_offsets;\n\tconst u16 *csa_offsets;\n};\n\nstruct cfg80211_dscp_exception {\n\tu8 dscp;\n\tu8 up;\n};\n\nstruct cfg80211_dscp_range {\n\tu8 low;\n\tu8 high;\n};\n\nstruct cfg80211_qos_map {\n\tu8 num_des;\n\tstruct cfg80211_dscp_exception dscp_exception[21];\n\tstruct cfg80211_dscp_range up[8];\n};\n\nstruct cfg80211_nan_conf {\n\tu8 master_pref;\n\tu8 bands;\n};\n\nstruct cfg80211_nan_func_filter {\n\tconst u8 *filter;\n\tu8 len;\n};\n\nstruct cfg80211_nan_func {\n\tenum nl80211_nan_function_type type;\n\tu8 service_id[6];\n\tu8 publish_type;\n\tbool close_range;\n\tbool publish_bcast;\n\tbool subscribe_active;\n\tu8 followup_id;\n\tu8 followup_reqid;\n\tstruct mac_address followup_dest;\n\tu32 ttl;\n\tconst u8 *serv_spec_info;\n\tu8 serv_spec_info_len;\n\tbool srf_include;\n\tconst u8 *srf_bf;\n\tu8 srf_bf_len;\n\tu8 srf_bf_idx;\n\tstruct mac_address *srf_macs;\n\tint srf_num_macs;\n\tstruct cfg80211_nan_func_filter *rx_filters;\n\tstruct cfg80211_nan_func_filter *tx_filters;\n\tu8 num_tx_filters;\n\tu8 num_rx_filters;\n\tu8 instance_id;\n\tu64 cookie;\n};\n\nstruct cfg80211_pmk_conf {\n\tconst u8 *aa;\n\tu8 pmk_len;\n\tconst u8 *pmk;\n\tconst u8 *pmk_r0_name;\n};\n\nstruct cfg80211_external_auth_params {\n\tenum nl80211_external_auth_action action;\n\tu8 bssid[6];\n\tstruct cfg80211_ssid ssid;\n\tunsigned int key_mgmt_suite;\n\tu16 status;\n\tconst u8 *pmkid;\n};\n\nstruct cfg80211_ftm_responder_stats {\n\tu32 filled;\n\tu32 success_num;\n\tu32 partial_num;\n\tu32 failed_num;\n\tu32 asap_num;\n\tu32 non_asap_num;\n\tu64 total_duration_ms;\n\tu32 unknown_triggers_num;\n\tu32 reschedule_requests_num;\n\tu32 out_of_window_triggers_num;\n};\n\nstruct cfg80211_pmsr_ftm_request_peer {\n\tenum nl80211_preamble preamble;\n\tu16 burst_period;\n\tu8 requested: 1;\n\tu8 asap: 1;\n\tu8 request_lci: 1;\n\tu8 request_civicloc: 1;\n\tu8 trigger_based: 1;\n\tu8 non_trigger_based: 1;\n\tu8 num_bursts_exp;\n\tu8 burst_duration;\n\tu8 ftms_per_burst;\n\tu8 ftmr_retries;\n};\n\nstruct cfg80211_pmsr_request_peer {\n\tu8 addr[6];\n\tstruct cfg80211_chan_def chandef;\n\tu8 report_ap_tsf: 1;\n\tstruct cfg80211_pmsr_ftm_request_peer ftm;\n};\n\nstruct cfg80211_pmsr_request {\n\tu64 cookie;\n\tvoid *drv_data;\n\tu32 n_peers;\n\tu32 nl_portid;\n\tu32 timeout;\n\tu8 mac_addr[6];\n\tu8 mac_addr_mask[6];\n\tstruct list_head list;\n\tstruct cfg80211_pmsr_request_peer peers[0];\n};\n\nstruct cfg80211_update_owe_info {\n\tu8 peer[6];\n\tu16 status;\n\tconst u8 *ie;\n\tsize_t ie_len;\n};\n\nstruct mgmt_frame_regs {\n\tu32 global_stypes;\n\tu32 interface_stypes;\n\tu32 global_mcast_stypes;\n\tu32 interface_mcast_stypes;\n};\n\nstruct cfg80211_ops {\n\tint (*suspend)(struct wiphy *, struct cfg80211_wowlan *);\n\tint (*resume)(struct wiphy *);\n\tvoid (*set_wakeup)(struct wiphy *, bool);\n\tstruct wireless_dev * (*add_virtual_intf)(struct wiphy *, const char *, unsigned char, enum nl80211_iftype, struct vif_params *);\n\tint (*del_virtual_intf)(struct wiphy *, struct wireless_dev *);\n\tint (*change_virtual_intf)(struct wiphy *, struct net_device *, enum nl80211_iftype, struct vif_params *);\n\tint (*add_key)(struct wiphy *, struct net_device *, u8, bool, const u8 *, struct key_params *);\n\tint (*get_key)(struct wiphy *, struct net_device *, u8, bool, const u8 *, void *, void (*)(void *, struct key_params *));\n\tint (*del_key)(struct wiphy *, struct net_device *, u8, bool, const u8 *);\n\tint (*set_default_key)(struct wiphy *, struct net_device *, u8, bool, bool);\n\tint (*set_default_mgmt_key)(struct wiphy *, struct net_device *, u8);\n\tint (*set_default_beacon_key)(struct wiphy *, struct net_device *, u8);\n\tint (*start_ap)(struct wiphy *, struct net_device *, struct cfg80211_ap_settings *);\n\tint (*change_beacon)(struct wiphy *, struct net_device *, struct cfg80211_beacon_data *);\n\tint (*stop_ap)(struct wiphy *, struct net_device *);\n\tint (*add_station)(struct wiphy *, struct net_device *, const u8 *, struct station_parameters *);\n\tint (*del_station)(struct wiphy *, struct net_device *, struct station_del_parameters *);\n\tint (*change_station)(struct wiphy *, struct net_device *, const u8 *, struct station_parameters *);\n\tint (*get_station)(struct wiphy *, struct net_device *, const u8 *, struct station_info *);\n\tint (*dump_station)(struct wiphy *, struct net_device *, int, u8 *, struct station_info *);\n\tint (*add_mpath)(struct wiphy *, struct net_device *, const u8 *, const u8 *);\n\tint (*del_mpath)(struct wiphy *, struct net_device *, const u8 *);\n\tint (*change_mpath)(struct wiphy *, struct net_device *, const u8 *, const u8 *);\n\tint (*get_mpath)(struct wiphy *, struct net_device *, u8 *, u8 *, struct mpath_info *);\n\tint (*dump_mpath)(struct wiphy *, struct net_device *, int, u8 *, u8 *, struct mpath_info *);\n\tint (*get_mpp)(struct wiphy *, struct net_device *, u8 *, u8 *, struct mpath_info *);\n\tint (*dump_mpp)(struct wiphy *, struct net_device *, int, u8 *, u8 *, struct mpath_info *);\n\tint (*get_mesh_config)(struct wiphy *, struct net_device *, struct mesh_config *);\n\tint (*update_mesh_config)(struct wiphy *, struct net_device *, u32, const struct mesh_config *);\n\tint (*join_mesh)(struct wiphy *, struct net_device *, const struct mesh_config *, const struct mesh_setup *);\n\tint (*leave_mesh)(struct wiphy *, struct net_device *);\n\tint (*join_ocb)(struct wiphy *, struct net_device *, struct ocb_setup *);\n\tint (*leave_ocb)(struct wiphy *, struct net_device *);\n\tint (*change_bss)(struct wiphy *, struct net_device *, struct bss_parameters *);\n\tint (*set_txq_params)(struct wiphy *, struct net_device *, struct ieee80211_txq_params *);\n\tint (*libertas_set_mesh_channel)(struct wiphy *, struct net_device *, struct ieee80211_channel *);\n\tint (*set_monitor_channel)(struct wiphy *, struct cfg80211_chan_def *);\n\tint (*scan)(struct wiphy *, struct cfg80211_scan_request *);\n\tvoid (*abort_scan)(struct wiphy *, struct wireless_dev *);\n\tint (*auth)(struct wiphy *, struct net_device *, struct cfg80211_auth_request *);\n\tint (*assoc)(struct wiphy *, struct net_device *, struct cfg80211_assoc_request *);\n\tint (*deauth)(struct wiphy *, struct net_device *, struct cfg80211_deauth_request *);\n\tint (*disassoc)(struct wiphy *, struct net_device *, struct cfg80211_disassoc_request *);\n\tint (*connect)(struct wiphy *, struct net_device *, struct cfg80211_connect_params *);\n\tint (*update_connect_params)(struct wiphy *, struct net_device *, struct cfg80211_connect_params *, u32);\n\tint (*disconnect)(struct wiphy *, struct net_device *, u16);\n\tint (*join_ibss)(struct wiphy *, struct net_device *, struct cfg80211_ibss_params *);\n\tint (*leave_ibss)(struct wiphy *, struct net_device *);\n\tint (*set_mcast_rate)(struct wiphy *, struct net_device *, int *);\n\tint (*set_wiphy_params)(struct wiphy *, u32);\n\tint (*set_tx_power)(struct wiphy *, struct wireless_dev *, enum nl80211_tx_power_setting, int);\n\tint (*get_tx_power)(struct wiphy *, struct wireless_dev *, int *);\n\tint (*set_wds_peer)(struct wiphy *, struct net_device *, const u8 *);\n\tvoid (*rfkill_poll)(struct wiphy *);\n\tint (*set_bitrate_mask)(struct wiphy *, struct net_device *, const u8 *, const struct cfg80211_bitrate_mask *);\n\tint (*dump_survey)(struct wiphy *, struct net_device *, int, struct survey_info *);\n\tint (*set_pmksa)(struct wiphy *, struct net_device *, struct cfg80211_pmksa *);\n\tint (*del_pmksa)(struct wiphy *, struct net_device *, struct cfg80211_pmksa *);\n\tint (*flush_pmksa)(struct wiphy *, struct net_device *);\n\tint (*remain_on_channel)(struct wiphy *, struct wireless_dev *, struct ieee80211_channel *, unsigned int, u64 *);\n\tint (*cancel_remain_on_channel)(struct wiphy *, struct wireless_dev *, u64);\n\tint (*mgmt_tx)(struct wiphy *, struct wireless_dev *, struct cfg80211_mgmt_tx_params *, u64 *);\n\tint (*mgmt_tx_cancel_wait)(struct wiphy *, struct wireless_dev *, u64);\n\tint (*set_power_mgmt)(struct wiphy *, struct net_device *, bool, int);\n\tint (*set_cqm_rssi_config)(struct wiphy *, struct net_device *, s32, u32);\n\tint (*set_cqm_rssi_range_config)(struct wiphy *, struct net_device *, s32, s32);\n\tint (*set_cqm_txe_config)(struct wiphy *, struct net_device *, u32, u32, u32);\n\tvoid (*update_mgmt_frame_registrations)(struct wiphy *, struct wireless_dev *, struct mgmt_frame_regs *);\n\tint (*set_antenna)(struct wiphy *, u32, u32);\n\tint (*get_antenna)(struct wiphy *, u32 *, u32 *);\n\tint (*sched_scan_start)(struct wiphy *, struct net_device *, struct cfg80211_sched_scan_request *);\n\tint (*sched_scan_stop)(struct wiphy *, struct net_device *, u64);\n\tint (*set_rekey_data)(struct wiphy *, struct net_device *, struct cfg80211_gtk_rekey_data *);\n\tint (*tdls_mgmt)(struct wiphy *, struct net_device *, const u8 *, u8, u8, u16, u32, bool, const u8 *, size_t);\n\tint (*tdls_oper)(struct wiphy *, struct net_device *, const u8 *, enum nl80211_tdls_operation);\n\tint (*probe_client)(struct wiphy *, struct net_device *, const u8 *, u64 *);\n\tint (*set_noack_map)(struct wiphy *, struct net_device *, u16);\n\tint (*get_channel)(struct wiphy *, struct wireless_dev *, struct cfg80211_chan_def *);\n\tint (*start_p2p_device)(struct wiphy *, struct wireless_dev *);\n\tvoid (*stop_p2p_device)(struct wiphy *, struct wireless_dev *);\n\tint (*set_mac_acl)(struct wiphy *, struct net_device *, const struct cfg80211_acl_data *);\n\tint (*start_radar_detection)(struct wiphy *, struct net_device *, struct cfg80211_chan_def *, u32);\n\tvoid (*end_cac)(struct wiphy *, struct net_device *);\n\tint (*update_ft_ies)(struct wiphy *, struct net_device *, struct cfg80211_update_ft_ies_params *);\n\tint (*crit_proto_start)(struct wiphy *, struct wireless_dev *, enum nl80211_crit_proto_id, u16);\n\tvoid (*crit_proto_stop)(struct wiphy *, struct wireless_dev *);\n\tint (*set_coalesce)(struct wiphy *, struct cfg80211_coalesce *);\n\tint (*channel_switch)(struct wiphy *, struct net_device *, struct cfg80211_csa_settings *);\n\tint (*set_qos_map)(struct wiphy *, struct net_device *, struct cfg80211_qos_map *);\n\tint (*set_ap_chanwidth)(struct wiphy *, struct net_device *, struct cfg80211_chan_def *);\n\tint (*add_tx_ts)(struct wiphy *, struct net_device *, u8, const u8 *, u8, u16);\n\tint (*del_tx_ts)(struct wiphy *, struct net_device *, u8, const u8 *);\n\tint (*tdls_channel_switch)(struct wiphy *, struct net_device *, const u8 *, u8, struct cfg80211_chan_def *);\n\tvoid (*tdls_cancel_channel_switch)(struct wiphy *, struct net_device *, const u8 *);\n\tint (*start_nan)(struct wiphy *, struct wireless_dev *, struct cfg80211_nan_conf *);\n\tvoid (*stop_nan)(struct wiphy *, struct wireless_dev *);\n\tint (*add_nan_func)(struct wiphy *, struct wireless_dev *, struct cfg80211_nan_func *);\n\tvoid (*del_nan_func)(struct wiphy *, struct wireless_dev *, u64);\n\tint (*nan_change_conf)(struct wiphy *, struct wireless_dev *, struct cfg80211_nan_conf *, u32);\n\tint (*set_multicast_to_unicast)(struct wiphy *, struct net_device *, const bool);\n\tint (*get_txq_stats)(struct wiphy *, struct wireless_dev *, struct cfg80211_txq_stats *);\n\tint (*set_pmk)(struct wiphy *, struct net_device *, const struct cfg80211_pmk_conf *);\n\tint (*del_pmk)(struct wiphy *, struct net_device *, const u8 *);\n\tint (*external_auth)(struct wiphy *, struct net_device *, struct cfg80211_external_auth_params *);\n\tint (*tx_control_port)(struct wiphy *, struct net_device *, const u8 *, size_t, const u8 *, const __be16, const bool, u64 *);\n\tint (*get_ftm_responder_stats)(struct wiphy *, struct net_device *, struct cfg80211_ftm_responder_stats *);\n\tint (*start_pmsr)(struct wiphy *, struct wireless_dev *, struct cfg80211_pmsr_request *);\n\tvoid (*abort_pmsr)(struct wiphy *, struct wireless_dev *, struct cfg80211_pmsr_request *);\n\tint (*update_owe_info)(struct wiphy *, struct net_device *, struct cfg80211_update_owe_info *);\n\tint (*probe_mesh_link)(struct wiphy *, struct net_device *, const u8 *, size_t);\n\tint (*set_tid_config)(struct wiphy *, struct net_device *, struct cfg80211_tid_config *);\n\tint (*reset_tid_config)(struct wiphy *, struct net_device *, const u8 *, u8);\n};\n\nenum wiphy_flags {\n\tWIPHY_FLAG_SUPPORTS_EXT_KEK_KCK = 1,\n\tWIPHY_FLAG_NETNS_OK = 8,\n\tWIPHY_FLAG_PS_ON_BY_DEFAULT = 16,\n\tWIPHY_FLAG_4ADDR_AP = 32,\n\tWIPHY_FLAG_4ADDR_STATION = 64,\n\tWIPHY_FLAG_CONTROL_PORT_PROTOCOL = 128,\n\tWIPHY_FLAG_IBSS_RSN = 256,\n\tWIPHY_FLAG_MESH_AUTH = 1024,\n\tWIPHY_FLAG_SUPPORTS_FW_ROAM = 8192,\n\tWIPHY_FLAG_AP_UAPSD = 16384,\n\tWIPHY_FLAG_SUPPORTS_TDLS = 32768,\n\tWIPHY_FLAG_TDLS_EXTERNAL_SETUP = 65536,\n\tWIPHY_FLAG_HAVE_AP_SME = 131072,\n\tWIPHY_FLAG_REPORTS_OBSS = 262144,\n\tWIPHY_FLAG_AP_PROBE_RESP_OFFLOAD = 524288,\n\tWIPHY_FLAG_OFFCHAN_TX = 1048576,\n\tWIPHY_FLAG_HAS_REMAIN_ON_CHANNEL = 2097152,\n\tWIPHY_FLAG_SUPPORTS_5_10_MHZ = 4194304,\n\tWIPHY_FLAG_HAS_CHANNEL_SWITCH = 8388608,\n\tWIPHY_FLAG_HAS_STATIC_WEP = 16777216,\n};\n\nstruct ieee80211_iface_limit {\n\tu16 max;\n\tu16 types;\n};\n\nstruct ieee80211_iface_combination {\n\tconst struct ieee80211_iface_limit *limits;\n\tu32 num_different_channels;\n\tu16 max_interfaces;\n\tu8 n_limits;\n\tbool beacon_int_infra_match;\n\tu8 radar_detect_widths;\n\tu8 radar_detect_regions;\n\tu32 beacon_int_min_gcd;\n};\n\nstruct ieee80211_txrx_stypes {\n\tu16 tx;\n\tu16 rx;\n};\n\nenum wiphy_wowlan_support_flags {\n\tWIPHY_WOWLAN_ANY = 1,\n\tWIPHY_WOWLAN_MAGIC_PKT = 2,\n\tWIPHY_WOWLAN_DISCONNECT = 4,\n\tWIPHY_WOWLAN_SUPPORTS_GTK_REKEY = 8,\n\tWIPHY_WOWLAN_GTK_REKEY_FAILURE = 16,\n\tWIPHY_WOWLAN_EAP_IDENTITY_REQ = 32,\n\tWIPHY_WOWLAN_4WAY_HANDSHAKE = 64,\n\tWIPHY_WOWLAN_RFKILL_RELEASE = 128,\n\tWIPHY_WOWLAN_NET_DETECT = 256,\n};\n\nstruct wiphy_wowlan_tcp_support {\n\tconst struct nl80211_wowlan_tcp_data_token_feature *tok;\n\tu32 data_payload_max;\n\tu32 data_interval_max;\n\tu32 wake_payload_max;\n\tbool seq;\n};\n\nstruct wiphy_wowlan_support {\n\tu32 flags;\n\tint n_patterns;\n\tint pattern_max_len;\n\tint pattern_min_len;\n\tint max_pkt_offset;\n\tint max_nd_match_sets;\n\tconst struct wiphy_wowlan_tcp_support *tcp;\n};\n\nstruct wiphy_coalesce_support {\n\tint n_rules;\n\tint max_delay;\n\tint n_patterns;\n\tint pattern_max_len;\n\tint pattern_min_len;\n\tint max_pkt_offset;\n};\n\nstruct wiphy_vendor_command {\n\tstruct nl80211_vendor_cmd_info info;\n\tu32 flags;\n\tint (*doit)(struct wiphy *, struct wireless_dev *, const void *, int);\n\tint (*dumpit)(struct wiphy *, struct wireless_dev *, struct sk_buff *, const void *, int, long unsigned int *);\n\tconst struct nla_policy *policy;\n\tunsigned int maxattr;\n};\n\nstruct wiphy_iftype_ext_capab {\n\tenum nl80211_iftype iftype;\n\tconst u8 *extended_capabilities;\n\tconst u8 *extended_capabilities_mask;\n\tu8 extended_capabilities_len;\n};\n\nstruct cfg80211_pmsr_capabilities {\n\tunsigned int max_peers;\n\tu8 report_ap_tsf: 1;\n\tu8 randomize_mac_addr: 1;\n\tstruct {\n\t\tu32 preambles;\n\t\tu32 bandwidths;\n\t\ts8 max_bursts_exponent;\n\t\tu8 max_ftms_per_burst;\n\t\tu8 supported: 1;\n\t\tu8 asap: 1;\n\t\tu8 non_asap: 1;\n\t\tu8 request_lci: 1;\n\t\tu8 request_civicloc: 1;\n\t\tu8 trigger_based: 1;\n\t\tu8 non_trigger_based: 1;\n\t} ftm;\n};\n\nstruct wiphy_iftype_akm_suites {\n\tu16 iftypes_mask;\n\tconst u32 *akm_suites;\n\tint n_akm_suites;\n};\n\nstruct cfg80211_cached_keys {\n\tstruct key_params params[4];\n\tu8 data[52];\n\tint def;\n};\n\nstruct cfg80211_internal_bss {\n\tstruct list_head list;\n\tstruct list_head hidden_list;\n\tstruct rb_node rbn;\n\tu64 ts_boottime;\n\tlong unsigned int ts;\n\tlong unsigned int refcount;\n\tatomic_t hold;\n\tu64 parent_tsf;\n\tu8 parent_bssid[6];\n\tstruct cfg80211_bss pub;\n};\n\nstruct cfg80211_cqm_config {\n\tu32 rssi_hyst;\n\ts32 last_rssi_event_value;\n\tint n_rssi_thresholds;\n\ts32 rssi_thresholds[0];\n};\n\nstruct cfg80211_fils_resp_params {\n\tconst u8 *kek;\n\tsize_t kek_len;\n\tbool update_erp_next_seq_num;\n\tu16 erp_next_seq_num;\n\tconst u8 *pmk;\n\tsize_t pmk_len;\n\tconst u8 *pmkid;\n};\n\nstruct cfg80211_connect_resp_params {\n\tint status;\n\tconst u8 *bssid;\n\tstruct cfg80211_bss *bss;\n\tconst u8 *req_ie;\n\tsize_t req_ie_len;\n\tconst u8 *resp_ie;\n\tsize_t resp_ie_len;\n\tstruct cfg80211_fils_resp_params fils;\n\tenum nl80211_timeout_reason timeout_reason;\n};\n\nstruct cfg80211_roam_info {\n\tstruct ieee80211_channel *channel;\n\tstruct cfg80211_bss *bss;\n\tconst u8 *bssid;\n\tconst u8 *req_ie;\n\tsize_t req_ie_len;\n\tconst u8 *resp_ie;\n\tsize_t resp_ie_len;\n\tstruct cfg80211_fils_resp_params fils;\n};\n\nstruct cfg80211_registered_device {\n\tconst struct cfg80211_ops *ops;\n\tstruct list_head list;\n\tstruct rfkill_ops rfkill_ops;\n\tstruct rfkill *rfkill;\n\tstruct work_struct rfkill_block;\n\tchar country_ie_alpha2[2];\n\tconst struct ieee80211_regdomain *requested_regd;\n\tenum environment_cap env;\n\tint wiphy_idx;\n\tint devlist_generation;\n\tint wdev_id;\n\tint opencount;\n\twait_queue_head_t dev_wait;\n\tstruct list_head beacon_registrations;\n\tspinlock_t beacon_registrations_lock;\n\tint num_running_ifaces;\n\tint num_running_monitor_ifaces;\n\tu64 cookie_counter;\n\tspinlock_t bss_lock;\n\tstruct list_head bss_list;\n\tstruct rb_root bss_tree;\n\tu32 bss_generation;\n\tu32 bss_entries;\n\tstruct cfg80211_scan_request *scan_req;\n\tstruct sk_buff *scan_msg;\n\tstruct list_head sched_scan_req_list;\n\ttime64_t suspend_at;\n\tstruct work_struct scan_done_wk;\n\tstruct genl_info *cur_cmd_info;\n\tstruct work_struct conn_work;\n\tstruct work_struct event_work;\n\tstruct delayed_work dfs_update_channels_wk;\n\tu32 crit_proto_nlportid;\n\tstruct cfg80211_coalesce *coalesce;\n\tstruct work_struct destroy_work;\n\tstruct work_struct sched_scan_stop_wk;\n\tstruct work_struct sched_scan_res_wk;\n\tstruct cfg80211_chan_def radar_chandef;\n\tstruct work_struct propagate_radar_detect_wk;\n\tstruct cfg80211_chan_def cac_done_chandef;\n\tstruct work_struct propagate_cac_done_wk;\n\tstruct work_struct mgmt_registrations_update_wk;\n\tstruct wiphy wiphy;\n};\n\nenum cfg80211_event_type {\n\tEVENT_CONNECT_RESULT = 0,\n\tEVENT_ROAMED = 1,\n\tEVENT_DISCONNECTED = 2,\n\tEVENT_IBSS_JOINED = 3,\n\tEVENT_STOPPED = 4,\n\tEVENT_PORT_AUTHORIZED = 5,\n};\n\nstruct cfg80211_event {\n\tstruct list_head list;\n\tenum cfg80211_event_type type;\n\tunion {\n\t\tstruct cfg80211_connect_resp_params cr;\n\t\tstruct cfg80211_roam_info rm;\n\t\tstruct {\n\t\t\tconst u8 *ie;\n\t\t\tsize_t ie_len;\n\t\t\tu16 reason;\n\t\t\tbool locally_generated;\n\t\t} dc;\n\t\tstruct {\n\t\t\tu8 bssid[6];\n\t\t\tstruct ieee80211_channel *channel;\n\t\t} ij;\n\t\tstruct {\n\t\t\tu8 bssid[6];\n\t\t} pa;\n\t};\n};\n\nstruct cfg80211_beacon_registration {\n\tstruct list_head list;\n\tu32 nlportid;\n};\n\nstruct iw_param {\n\t__s32 value;\n\t__u8 fixed;\n\t__u8 disabled;\n\t__u16 flags;\n};\n\nstruct iw_point {\n\tvoid *pointer;\n\t__u16 length;\n\t__u16 flags;\n};\n\nstruct iw_freq {\n\t__s32 m;\n\t__s16 e;\n\t__u8 i;\n\t__u8 flags;\n};\n\nstruct iw_quality {\n\t__u8 qual;\n\t__u8 level;\n\t__u8 noise;\n\t__u8 updated;\n};\n\nstruct iw_discarded {\n\t__u32 nwid;\n\t__u32 code;\n\t__u32 fragment;\n\t__u32 retries;\n\t__u32 misc;\n};\n\nstruct iw_missed {\n\t__u32 beacon;\n};\n\nstruct iw_statistics {\n\t__u16 status;\n\tstruct iw_quality qual;\n\tstruct iw_discarded discard;\n\tstruct iw_missed miss;\n};\n\nunion iwreq_data {\n\tchar name[16];\n\tstruct iw_point essid;\n\tstruct iw_param nwid;\n\tstruct iw_freq freq;\n\tstruct iw_param sens;\n\tstruct iw_param bitrate;\n\tstruct iw_param txpower;\n\tstruct iw_param rts;\n\tstruct iw_param frag;\n\t__u32 mode;\n\tstruct iw_param retry;\n\tstruct iw_point encoding;\n\tstruct iw_param power;\n\tstruct iw_quality qual;\n\tstruct sockaddr ap_addr;\n\tstruct sockaddr addr;\n\tstruct iw_param param;\n\tstruct iw_point data;\n};\n\nstruct iw_request_info {\n\t__u16 cmd;\n\t__u16 flags;\n};\n\ntypedef int (*iw_handler)(struct net_device *, struct iw_request_info *, union iwreq_data *, char *);\n\nstruct iw_handler_def {\n\tconst iw_handler *standard;\n\t__u16 num_standard;\n\tstruct iw_statistics * (*get_wireless_stats)(struct net_device *);\n};\n\nstruct radiotap_align_size {\n\tuint8_t align: 4;\n\tuint8_t size: 4;\n};\n\nstruct ieee80211_radiotap_namespace {\n\tconst struct radiotap_align_size *align_size;\n\tint n_bits;\n\tuint32_t oui;\n\tuint8_t subns;\n};\n\nstruct ieee80211_radiotap_vendor_namespaces {\n\tconst struct ieee80211_radiotap_namespace *ns;\n\tint n_ns;\n};\n\nstruct ieee80211_radiotap_header;\n\nstruct ieee80211_radiotap_iterator {\n\tstruct ieee80211_radiotap_header *_rtheader;\n\tconst struct ieee80211_radiotap_vendor_namespaces *_vns;\n\tconst struct ieee80211_radiotap_namespace *current_namespace;\n\tunsigned char *_arg;\n\tunsigned char *_next_ns_data;\n\t__le32 *_next_bitmap;\n\tunsigned char *this_arg;\n\tint this_arg_index;\n\tint this_arg_size;\n\tint is_radiotap_ns;\n\tint _max_length;\n\tint _arg_index;\n\tuint32_t _bitmap_shifter;\n\tint _reset_on_ext;\n};\n\nstruct ieee80211_radiotap_header {\n\tuint8_t it_version;\n\tuint8_t it_pad;\n\t__le16 it_len;\n\t__le32 it_present;\n};\n\nenum ieee80211_radiotap_presence {\n\tIEEE80211_RADIOTAP_TSFT = 0,\n\tIEEE80211_RADIOTAP_FLAGS = 1,\n\tIEEE80211_RADIOTAP_RATE = 2,\n\tIEEE80211_RADIOTAP_CHANNEL = 3,\n\tIEEE80211_RADIOTAP_FHSS = 4,\n\tIEEE80211_RADIOTAP_DBM_ANTSIGNAL = 5,\n\tIEEE80211_RADIOTAP_DBM_ANTNOISE = 6,\n\tIEEE80211_RADIOTAP_LOCK_QUALITY = 7,\n\tIEEE80211_RADIOTAP_TX_ATTENUATION = 8,\n\tIEEE80211_RADIOTAP_DB_TX_ATTENUATION = 9,\n\tIEEE80211_RADIOTAP_DBM_TX_POWER = 10,\n\tIEEE80211_RADIOTAP_ANTENNA = 11,\n\tIEEE80211_RADIOTAP_DB_ANTSIGNAL = 12,\n\tIEEE80211_RADIOTAP_DB_ANTNOISE = 13,\n\tIEEE80211_RADIOTAP_RX_FLAGS = 14,\n\tIEEE80211_RADIOTAP_TX_FLAGS = 15,\n\tIEEE80211_RADIOTAP_RTS_RETRIES = 16,\n\tIEEE80211_RADIOTAP_DATA_RETRIES = 17,\n\tIEEE80211_RADIOTAP_MCS = 19,\n\tIEEE80211_RADIOTAP_AMPDU_STATUS = 20,\n\tIEEE80211_RADIOTAP_VHT = 21,\n\tIEEE80211_RADIOTAP_TIMESTAMP = 22,\n\tIEEE80211_RADIOTAP_HE = 23,\n\tIEEE80211_RADIOTAP_HE_MU = 24,\n\tIEEE80211_RADIOTAP_ZERO_LEN_PSDU = 26,\n\tIEEE80211_RADIOTAP_LSIG = 27,\n\tIEEE80211_RADIOTAP_RADIOTAP_NAMESPACE = 29,\n\tIEEE80211_RADIOTAP_VENDOR_NAMESPACE = 30,\n\tIEEE80211_RADIOTAP_EXT = 31,\n};\n\nstruct ieee80211_hdr {\n\t__le16 frame_control;\n\t__le16 duration_id;\n\tu8 addr1[6];\n\tu8 addr2[6];\n\tu8 addr3[6];\n\t__le16 seq_ctrl;\n\tu8 addr4[6];\n};\n\nstruct ieee80211s_hdr {\n\tu8 flags;\n\tu8 ttl;\n\t__le32 seqnum;\n\tu8 eaddr1[6];\n\tu8 eaddr2[6];\n} __attribute__((packed));\n\nenum ieee80211_p2p_attr_id {\n\tIEEE80211_P2P_ATTR_STATUS = 0,\n\tIEEE80211_P2P_ATTR_MINOR_REASON = 1,\n\tIEEE80211_P2P_ATTR_CAPABILITY = 2,\n\tIEEE80211_P2P_ATTR_DEVICE_ID = 3,\n\tIEEE80211_P2P_ATTR_GO_INTENT = 4,\n\tIEEE80211_P2P_ATTR_GO_CONFIG_TIMEOUT = 5,\n\tIEEE80211_P2P_ATTR_LISTEN_CHANNEL = 6,\n\tIEEE80211_P2P_ATTR_GROUP_BSSID = 7,\n\tIEEE80211_P2P_ATTR_EXT_LISTEN_TIMING = 8,\n\tIEEE80211_P2P_ATTR_INTENDED_IFACE_ADDR = 9,\n\tIEEE80211_P2P_ATTR_MANAGABILITY = 10,\n\tIEEE80211_P2P_ATTR_CHANNEL_LIST = 11,\n\tIEEE80211_P2P_ATTR_ABSENCE_NOTICE = 12,\n\tIEEE80211_P2P_ATTR_DEVICE_INFO = 13,\n\tIEEE80211_P2P_ATTR_GROUP_INFO = 14,\n\tIEEE80211_P2P_ATTR_GROUP_ID = 15,\n\tIEEE80211_P2P_ATTR_INTERFACE = 16,\n\tIEEE80211_P2P_ATTR_OPER_CHANNEL = 17,\n\tIEEE80211_P2P_ATTR_INVITE_FLAGS = 18,\n\tIEEE80211_P2P_ATTR_VENDOR_SPECIFIC = 221,\n\tIEEE80211_P2P_ATTR_MAX = 222,\n};\n\nenum ieee80211_vht_chanwidth {\n\tIEEE80211_VHT_CHANWIDTH_USE_HT = 0,\n\tIEEE80211_VHT_CHANWIDTH_80MHZ = 1,\n\tIEEE80211_VHT_CHANWIDTH_160MHZ = 2,\n\tIEEE80211_VHT_CHANWIDTH_80P80MHZ = 3,\n};\n\nenum ieee80211_statuscode {\n\tWLAN_STATUS_SUCCESS = 0,\n\tWLAN_STATUS_UNSPECIFIED_FAILURE = 1,\n\tWLAN_STATUS_CAPS_UNSUPPORTED = 10,\n\tWLAN_STATUS_REASSOC_NO_ASSOC = 11,\n\tWLAN_STATUS_ASSOC_DENIED_UNSPEC = 12,\n\tWLAN_STATUS_NOT_SUPPORTED_AUTH_ALG = 13,\n\tWLAN_STATUS_UNKNOWN_AUTH_TRANSACTION = 14,\n\tWLAN_STATUS_CHALLENGE_FAIL = 15,\n\tWLAN_STATUS_AUTH_TIMEOUT = 16,\n\tWLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA = 17,\n\tWLAN_STATUS_ASSOC_DENIED_RATES = 18,\n\tWLAN_STATUS_ASSOC_DENIED_NOSHORTPREAMBLE = 19,\n\tWLAN_STATUS_ASSOC_DENIED_NOPBCC = 20,\n\tWLAN_STATUS_ASSOC_DENIED_NOAGILITY = 21,\n\tWLAN_STATUS_ASSOC_DENIED_NOSPECTRUM = 22,\n\tWLAN_STATUS_ASSOC_REJECTED_BAD_POWER = 23,\n\tWLAN_STATUS_ASSOC_REJECTED_BAD_SUPP_CHAN = 24,\n\tWLAN_STATUS_ASSOC_DENIED_NOSHORTTIME = 25,\n\tWLAN_STATUS_ASSOC_DENIED_NODSSSOFDM = 26,\n\tWLAN_STATUS_ASSOC_REJECTED_TEMPORARILY = 30,\n\tWLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION = 31,\n\tWLAN_STATUS_INVALID_IE = 40,\n\tWLAN_STATUS_INVALID_GROUP_CIPHER = 41,\n\tWLAN_STATUS_INVALID_PAIRWISE_CIPHER = 42,\n\tWLAN_STATUS_INVALID_AKMP = 43,\n\tWLAN_STATUS_UNSUPP_RSN_VERSION = 44,\n\tWLAN_STATUS_INVALID_RSN_IE_CAP = 45,\n\tWLAN_STATUS_CIPHER_SUITE_REJECTED = 46,\n\tWLAN_STATUS_UNSPECIFIED_QOS = 32,\n\tWLAN_STATUS_ASSOC_DENIED_NOBANDWIDTH = 33,\n\tWLAN_STATUS_ASSOC_DENIED_LOWACK = 34,\n\tWLAN_STATUS_ASSOC_DENIED_UNSUPP_QOS = 35,\n\tWLAN_STATUS_REQUEST_DECLINED = 37,\n\tWLAN_STATUS_INVALID_QOS_PARAM = 38,\n\tWLAN_STATUS_CHANGE_TSPEC = 39,\n\tWLAN_STATUS_WAIT_TS_DELAY = 47,\n\tWLAN_STATUS_NO_DIRECT_LINK = 48,\n\tWLAN_STATUS_STA_NOT_PRESENT = 49,\n\tWLAN_STATUS_STA_NOT_QSTA = 50,\n\tWLAN_STATUS_ANTI_CLOG_REQUIRED = 76,\n\tWLAN_STATUS_FCG_NOT_SUPP = 78,\n\tWLAN_STATUS_STA_NO_TBTT = 78,\n\tWLAN_STATUS_REJECTED_WITH_SUGGESTED_CHANGES = 39,\n\tWLAN_STATUS_REJECTED_FOR_DELAY_PERIOD = 47,\n\tWLAN_STATUS_REJECT_WITH_SCHEDULE = 83,\n\tWLAN_STATUS_PENDING_ADMITTING_FST_SESSION = 86,\n\tWLAN_STATUS_PERFORMING_FST_NOW = 87,\n\tWLAN_STATUS_PENDING_GAP_IN_BA_WINDOW = 88,\n\tWLAN_STATUS_REJECT_U_PID_SETTING = 89,\n\tWLAN_STATUS_REJECT_DSE_BAND = 96,\n\tWLAN_STATUS_DENIED_WITH_SUGGESTED_BAND_AND_CHANNEL = 99,\n\tWLAN_STATUS_DENIED_DUE_TO_SPECTRUM_MANAGEMENT = 103,\n\tWLAN_STATUS_FILS_AUTHENTICATION_FAILURE = 108,\n\tWLAN_STATUS_UNKNOWN_AUTHENTICATION_SERVER = 109,\n};\n\nenum ieee80211_eid {\n\tWLAN_EID_SSID = 0,\n\tWLAN_EID_SUPP_RATES = 1,\n\tWLAN_EID_FH_PARAMS = 2,\n\tWLAN_EID_DS_PARAMS = 3,\n\tWLAN_EID_CF_PARAMS = 4,\n\tWLAN_EID_TIM = 5,\n\tWLAN_EID_IBSS_PARAMS = 6,\n\tWLAN_EID_COUNTRY = 7,\n\tWLAN_EID_REQUEST = 10,\n\tWLAN_EID_QBSS_LOAD = 11,\n\tWLAN_EID_EDCA_PARAM_SET = 12,\n\tWLAN_EID_TSPEC = 13,\n\tWLAN_EID_TCLAS = 14,\n\tWLAN_EID_SCHEDULE = 15,\n\tWLAN_EID_CHALLENGE = 16,\n\tWLAN_EID_PWR_CONSTRAINT = 32,\n\tWLAN_EID_PWR_CAPABILITY = 33,\n\tWLAN_EID_TPC_REQUEST = 34,\n\tWLAN_EID_TPC_REPORT = 35,\n\tWLAN_EID_SUPPORTED_CHANNELS = 36,\n\tWLAN_EID_CHANNEL_SWITCH = 37,\n\tWLAN_EID_MEASURE_REQUEST = 38,\n\tWLAN_EID_MEASURE_REPORT = 39,\n\tWLAN_EID_QUIET = 40,\n\tWLAN_EID_IBSS_DFS = 41,\n\tWLAN_EID_ERP_INFO = 42,\n\tWLAN_EID_TS_DELAY = 43,\n\tWLAN_EID_TCLAS_PROCESSING = 44,\n\tWLAN_EID_HT_CAPABILITY = 45,\n\tWLAN_EID_QOS_CAPA = 46,\n\tWLAN_EID_RSN = 48,\n\tWLAN_EID_802_15_COEX = 49,\n\tWLAN_EID_EXT_SUPP_RATES = 50,\n\tWLAN_EID_AP_CHAN_REPORT = 51,\n\tWLAN_EID_NEIGHBOR_REPORT = 52,\n\tWLAN_EID_RCPI = 53,\n\tWLAN_EID_MOBILITY_DOMAIN = 54,\n\tWLAN_EID_FAST_BSS_TRANSITION = 55,\n\tWLAN_EID_TIMEOUT_INTERVAL = 56,\n\tWLAN_EID_RIC_DATA = 57,\n\tWLAN_EID_DSE_REGISTERED_LOCATION = 58,\n\tWLAN_EID_SUPPORTED_REGULATORY_CLASSES = 59,\n\tWLAN_EID_EXT_CHANSWITCH_ANN = 60,\n\tWLAN_EID_HT_OPERATION = 61,\n\tWLAN_EID_SECONDARY_CHANNEL_OFFSET = 62,\n\tWLAN_EID_BSS_AVG_ACCESS_DELAY = 63,\n\tWLAN_EID_ANTENNA_INFO = 64,\n\tWLAN_EID_RSNI = 65,\n\tWLAN_EID_MEASUREMENT_PILOT_TX_INFO = 66,\n\tWLAN_EID_BSS_AVAILABLE_CAPACITY = 67,\n\tWLAN_EID_BSS_AC_ACCESS_DELAY = 68,\n\tWLAN_EID_TIME_ADVERTISEMENT = 69,\n\tWLAN_EID_RRM_ENABLED_CAPABILITIES = 70,\n\tWLAN_EID_MULTIPLE_BSSID = 71,\n\tWLAN_EID_BSS_COEX_2040 = 72,\n\tWLAN_EID_BSS_INTOLERANT_CHL_REPORT = 73,\n\tWLAN_EID_OVERLAP_BSS_SCAN_PARAM = 74,\n\tWLAN_EID_RIC_DESCRIPTOR = 75,\n\tWLAN_EID_MMIE = 76,\n\tWLAN_EID_ASSOC_COMEBACK_TIME = 77,\n\tWLAN_EID_EVENT_REQUEST = 78,\n\tWLAN_EID_EVENT_REPORT = 79,\n\tWLAN_EID_DIAGNOSTIC_REQUEST = 80,\n\tWLAN_EID_DIAGNOSTIC_REPORT = 81,\n\tWLAN_EID_LOCATION_PARAMS = 82,\n\tWLAN_EID_NON_TX_BSSID_CAP = 83,\n\tWLAN_EID_SSID_LIST = 84,\n\tWLAN_EID_MULTI_BSSID_IDX = 85,\n\tWLAN_EID_FMS_DESCRIPTOR = 86,\n\tWLAN_EID_FMS_REQUEST = 87,\n\tWLAN_EID_FMS_RESPONSE = 88,\n\tWLAN_EID_QOS_TRAFFIC_CAPA = 89,\n\tWLAN_EID_BSS_MAX_IDLE_PERIOD = 90,\n\tWLAN_EID_TSF_REQUEST = 91,\n\tWLAN_EID_TSF_RESPOSNE = 92,\n\tWLAN_EID_WNM_SLEEP_MODE = 93,\n\tWLAN_EID_TIM_BCAST_REQ = 94,\n\tWLAN_EID_TIM_BCAST_RESP = 95,\n\tWLAN_EID_COLL_IF_REPORT = 96,\n\tWLAN_EID_CHANNEL_USAGE = 97,\n\tWLAN_EID_TIME_ZONE = 98,\n\tWLAN_EID_DMS_REQUEST = 99,\n\tWLAN_EID_DMS_RESPONSE = 100,\n\tWLAN_EID_LINK_ID = 101,\n\tWLAN_EID_WAKEUP_SCHEDUL = 102,\n\tWLAN_EID_CHAN_SWITCH_TIMING = 104,\n\tWLAN_EID_PTI_CONTROL = 105,\n\tWLAN_EID_PU_BUFFER_STATUS = 106,\n\tWLAN_EID_INTERWORKING = 107,\n\tWLAN_EID_ADVERTISEMENT_PROTOCOL = 108,\n\tWLAN_EID_EXPEDITED_BW_REQ = 109,\n\tWLAN_EID_QOS_MAP_SET = 110,\n\tWLAN_EID_ROAMING_CONSORTIUM = 111,\n\tWLAN_EID_EMERGENCY_ALERT = 112,\n\tWLAN_EID_MESH_CONFIG = 113,\n\tWLAN_EID_MESH_ID = 114,\n\tWLAN_EID_LINK_METRIC_REPORT = 115,\n\tWLAN_EID_CONGESTION_NOTIFICATION = 116,\n\tWLAN_EID_PEER_MGMT = 117,\n\tWLAN_EID_CHAN_SWITCH_PARAM = 118,\n\tWLAN_EID_MESH_AWAKE_WINDOW = 119,\n\tWLAN_EID_BEACON_TIMING = 120,\n\tWLAN_EID_MCCAOP_SETUP_REQ = 121,\n\tWLAN_EID_MCCAOP_SETUP_RESP = 122,\n\tWLAN_EID_MCCAOP_ADVERT = 123,\n\tWLAN_EID_MCCAOP_TEARDOWN = 124,\n\tWLAN_EID_GANN = 125,\n\tWLAN_EID_RANN = 126,\n\tWLAN_EID_EXT_CAPABILITY = 127,\n\tWLAN_EID_PREQ = 130,\n\tWLAN_EID_PREP = 131,\n\tWLAN_EID_PERR = 132,\n\tWLAN_EID_PXU = 137,\n\tWLAN_EID_PXUC = 138,\n\tWLAN_EID_AUTH_MESH_PEER_EXCH = 139,\n\tWLAN_EID_MIC = 140,\n\tWLAN_EID_DESTINATION_URI = 141,\n\tWLAN_EID_UAPSD_COEX = 142,\n\tWLAN_EID_WAKEUP_SCHEDULE = 143,\n\tWLAN_EID_EXT_SCHEDULE = 144,\n\tWLAN_EID_STA_AVAILABILITY = 145,\n\tWLAN_EID_DMG_TSPEC = 146,\n\tWLAN_EID_DMG_AT = 147,\n\tWLAN_EID_DMG_CAP = 148,\n\tWLAN_EID_CISCO_VENDOR_SPECIFIC = 150,\n\tWLAN_EID_DMG_OPERATION = 151,\n\tWLAN_EID_DMG_BSS_PARAM_CHANGE = 152,\n\tWLAN_EID_DMG_BEAM_REFINEMENT = 153,\n\tWLAN_EID_CHANNEL_MEASURE_FEEDBACK = 154,\n\tWLAN_EID_AWAKE_WINDOW = 157,\n\tWLAN_EID_MULTI_BAND = 158,\n\tWLAN_EID_ADDBA_EXT = 159,\n\tWLAN_EID_NEXT_PCP_LIST = 160,\n\tWLAN_EID_PCP_HANDOVER = 161,\n\tWLAN_EID_DMG_LINK_MARGIN = 162,\n\tWLAN_EID_SWITCHING_STREAM = 163,\n\tWLAN_EID_SESSION_TRANSITION = 164,\n\tWLAN_EID_DYN_TONE_PAIRING_REPORT = 165,\n\tWLAN_EID_CLUSTER_REPORT = 166,\n\tWLAN_EID_RELAY_CAP = 167,\n\tWLAN_EID_RELAY_XFER_PARAM_SET = 168,\n\tWLAN_EID_BEAM_LINK_MAINT = 169,\n\tWLAN_EID_MULTIPLE_MAC_ADDR = 170,\n\tWLAN_EID_U_PID = 171,\n\tWLAN_EID_DMG_LINK_ADAPT_ACK = 172,\n\tWLAN_EID_MCCAOP_ADV_OVERVIEW = 174,\n\tWLAN_EID_QUIET_PERIOD_REQ = 175,\n\tWLAN_EID_QUIET_PERIOD_RESP = 177,\n\tWLAN_EID_EPAC_POLICY = 182,\n\tWLAN_EID_CLISTER_TIME_OFF = 183,\n\tWLAN_EID_INTER_AC_PRIO = 184,\n\tWLAN_EID_SCS_DESCRIPTOR = 185,\n\tWLAN_EID_QLOAD_REPORT = 186,\n\tWLAN_EID_HCCA_TXOP_UPDATE_COUNT = 187,\n\tWLAN_EID_HL_STREAM_ID = 188,\n\tWLAN_EID_GCR_GROUP_ADDR = 189,\n\tWLAN_EID_ANTENNA_SECTOR_ID_PATTERN = 190,\n\tWLAN_EID_VHT_CAPABILITY = 191,\n\tWLAN_EID_VHT_OPERATION = 192,\n\tWLAN_EID_EXTENDED_BSS_LOAD = 193,\n\tWLAN_EID_WIDE_BW_CHANNEL_SWITCH = 194,\n\tWLAN_EID_VHT_TX_POWER_ENVELOPE = 195,\n\tWLAN_EID_CHANNEL_SWITCH_WRAPPER = 196,\n\tWLAN_EID_AID = 197,\n\tWLAN_EID_QUIET_CHANNEL = 198,\n\tWLAN_EID_OPMODE_NOTIF = 199,\n\tWLAN_EID_REDUCED_NEIGHBOR_REPORT = 201,\n\tWLAN_EID_S1G_BCN_COMPAT = 213,\n\tWLAN_EID_S1G_SHORT_BCN_INTERVAL = 214,\n\tWLAN_EID_S1G_CAPABILITIES = 217,\n\tWLAN_EID_VENDOR_SPECIFIC = 221,\n\tWLAN_EID_QOS_PARAMETER = 222,\n\tWLAN_EID_S1G_OPERATION = 232,\n\tWLAN_EID_CAG_NUMBER = 237,\n\tWLAN_EID_AP_CSN = 239,\n\tWLAN_EID_FILS_INDICATION = 240,\n\tWLAN_EID_DILS = 241,\n\tWLAN_EID_FRAGMENT = 242,\n\tWLAN_EID_RSNX = 244,\n\tWLAN_EID_EXTENSION = 255,\n};\n\nstruct element {\n\tu8 id;\n\tu8 datalen;\n\tu8 data[0];\n};\n\nenum nl80211_he_gi {\n\tNL80211_RATE_INFO_HE_GI_0_8 = 0,\n\tNL80211_RATE_INFO_HE_GI_1_6 = 1,\n\tNL80211_RATE_INFO_HE_GI_3_2 = 2,\n};\n\nenum nl80211_he_ru_alloc {\n\tNL80211_RATE_INFO_HE_RU_ALLOC_26 = 0,\n\tNL80211_RATE_INFO_HE_RU_ALLOC_52 = 1,\n\tNL80211_RATE_INFO_HE_RU_ALLOC_106 = 2,\n\tNL80211_RATE_INFO_HE_RU_ALLOC_242 = 3,\n\tNL80211_RATE_INFO_HE_RU_ALLOC_484 = 4,\n\tNL80211_RATE_INFO_HE_RU_ALLOC_996 = 5,\n\tNL80211_RATE_INFO_HE_RU_ALLOC_2x996 = 6,\n};\n\nenum ieee80211_rate_flags {\n\tIEEE80211_RATE_SHORT_PREAMBLE = 1,\n\tIEEE80211_RATE_MANDATORY_A = 2,\n\tIEEE80211_RATE_MANDATORY_B = 4,\n\tIEEE80211_RATE_MANDATORY_G = 8,\n\tIEEE80211_RATE_ERP_G = 16,\n\tIEEE80211_RATE_SUPPORTS_5MHZ = 32,\n\tIEEE80211_RATE_SUPPORTS_10MHZ = 64,\n};\n\nstruct iface_combination_params {\n\tint num_different_channels;\n\tu8 radar_detect;\n\tint iftype_num[13];\n\tu32 new_beacon_int;\n};\n\nenum rate_info_flags {\n\tRATE_INFO_FLAGS_MCS = 1,\n\tRATE_INFO_FLAGS_VHT_MCS = 2,\n\tRATE_INFO_FLAGS_SHORT_GI = 4,\n\tRATE_INFO_FLAGS_DMG = 8,\n\tRATE_INFO_FLAGS_HE_MCS = 16,\n\tRATE_INFO_FLAGS_EDMG = 32,\n};\n\nenum rate_info_bw {\n\tRATE_INFO_BW_20 = 0,\n\tRATE_INFO_BW_5 = 1,\n\tRATE_INFO_BW_10 = 2,\n\tRATE_INFO_BW_40 = 3,\n\tRATE_INFO_BW_80 = 4,\n\tRATE_INFO_BW_160 = 5,\n\tRATE_INFO_BW_HE_RU = 6,\n};\n\nstruct iapp_layer2_update {\n\tu8 da[6];\n\tu8 sa[6];\n\t__be16 len;\n\tu8 dsap;\n\tu8 ssap;\n\tu8 control;\n\tu8 xid_info[3];\n};\n\nenum nl80211_reg_rule_flags {\n\tNL80211_RRF_NO_OFDM = 1,\n\tNL80211_RRF_NO_CCK = 2,\n\tNL80211_RRF_NO_INDOOR = 4,\n\tNL80211_RRF_NO_OUTDOOR = 8,\n\tNL80211_RRF_DFS = 16,\n\tNL80211_RRF_PTP_ONLY = 32,\n\tNL80211_RRF_PTMP_ONLY = 64,\n\tNL80211_RRF_NO_IR = 128,\n\t__NL80211_RRF_NO_IBSS = 256,\n\tNL80211_RRF_AUTO_BW = 2048,\n\tNL80211_RRF_IR_CONCURRENT = 4096,\n\tNL80211_RRF_NO_HT40MINUS = 8192,\n\tNL80211_RRF_NO_HT40PLUS = 16384,\n\tNL80211_RRF_NO_80MHZ = 32768,\n\tNL80211_RRF_NO_160MHZ = 65536,\n\tNL80211_RRF_NO_HE = 131072,\n};\n\nenum nl80211_channel_type {\n\tNL80211_CHAN_NO_HT = 0,\n\tNL80211_CHAN_HT20 = 1,\n\tNL80211_CHAN_HT40MINUS = 2,\n\tNL80211_CHAN_HT40PLUS = 3,\n};\n\nenum ieee80211_channel_flags {\n\tIEEE80211_CHAN_DISABLED = 1,\n\tIEEE80211_CHAN_NO_IR = 2,\n\tIEEE80211_CHAN_RADAR = 8,\n\tIEEE80211_CHAN_NO_HT40PLUS = 16,\n\tIEEE80211_CHAN_NO_HT40MINUS = 32,\n\tIEEE80211_CHAN_NO_OFDM = 64,\n\tIEEE80211_CHAN_NO_80MHZ = 128,\n\tIEEE80211_CHAN_NO_160MHZ = 256,\n\tIEEE80211_CHAN_INDOOR_ONLY = 512,\n\tIEEE80211_CHAN_IR_CONCURRENT = 1024,\n\tIEEE80211_CHAN_NO_20MHZ = 2048,\n\tIEEE80211_CHAN_NO_10MHZ = 4096,\n\tIEEE80211_CHAN_NO_HE = 8192,\n};\n\nenum ieee80211_regd_source {\n\tREGD_SOURCE_INTERNAL_DB = 0,\n\tREGD_SOURCE_CRDA = 1,\n\tREGD_SOURCE_CACHED = 2,\n};\n\nenum reg_request_treatment {\n\tREG_REQ_OK = 0,\n\tREG_REQ_IGNORE = 1,\n\tREG_REQ_INTERSECT = 2,\n\tREG_REQ_ALREADY_SET = 3,\n};\n\nstruct reg_beacon {\n\tstruct list_head list;\n\tstruct ieee80211_channel chan;\n};\n\nstruct reg_regdb_apply_request {\n\tstruct list_head list;\n\tconst struct ieee80211_regdomain *regdom;\n};\n\nstruct fwdb_country {\n\tu8 alpha2[2];\n\t__be16 coll_ptr;\n};\n\nstruct fwdb_header {\n\t__be32 magic;\n\t__be32 version;\n\tstruct fwdb_country country[0];\n};\n\nstruct fwdb_collection {\n\tu8 len;\n\tu8 n_rules;\n\tu8 dfs_region;\n\tchar: 8;\n};\n\nenum fwdb_flags {\n\tFWDB_FLAG_NO_OFDM = 1,\n\tFWDB_FLAG_NO_OUTDOOR = 2,\n\tFWDB_FLAG_DFS = 4,\n\tFWDB_FLAG_NO_IR = 8,\n\tFWDB_FLAG_AUTO_BW = 16,\n};\n\nstruct fwdb_wmm_ac {\n\tu8 ecw;\n\tu8 aifsn;\n\t__be16 cot;\n};\n\nstruct fwdb_wmm_rule {\n\tstruct fwdb_wmm_ac client[4];\n\tstruct fwdb_wmm_ac ap[4];\n};\n\nstruct fwdb_rule {\n\tu8 len;\n\tu8 flags;\n\t__be16 max_eirp;\n\t__be32 start;\n\t__be32 end;\n\t__be32 max_bw;\n\t__be16 cac_timeout;\n\t__be16 wmm_ptr;\n};\n\nenum nl80211_scan_flags {\n\tNL80211_SCAN_FLAG_LOW_PRIORITY = 1,\n\tNL80211_SCAN_FLAG_FLUSH = 2,\n\tNL80211_SCAN_FLAG_AP = 4,\n\tNL80211_SCAN_FLAG_RANDOM_ADDR = 8,\n\tNL80211_SCAN_FLAG_FILS_MAX_CHANNEL_TIME = 16,\n\tNL80211_SCAN_FLAG_ACCEPT_BCAST_PROBE_RESP = 32,\n\tNL80211_SCAN_FLAG_OCE_PROBE_REQ_HIGH_TX_RATE = 64,\n\tNL80211_SCAN_FLAG_OCE_PROBE_REQ_DEFERRAL_SUPPRESSION = 128,\n\tNL80211_SCAN_FLAG_LOW_SPAN = 256,\n\tNL80211_SCAN_FLAG_LOW_POWER = 512,\n\tNL80211_SCAN_FLAG_HIGH_ACCURACY = 1024,\n\tNL80211_SCAN_FLAG_RANDOM_SN = 2048,\n\tNL80211_SCAN_FLAG_MIN_PREQ_CONTENT = 4096,\n\tNL80211_SCAN_FLAG_FREQ_KHZ = 8192,\n};\n\nstruct ieee80211_msrment_ie {\n\tu8 token;\n\tu8 mode;\n\tu8 type;\n\tu8 request[0];\n};\n\nstruct ieee80211_ext_chansw_ie {\n\tu8 mode;\n\tu8 new_operating_class;\n\tu8 new_ch_num;\n\tu8 count;\n};\n\nstruct ieee80211_tpc_report_ie {\n\tu8 tx_power;\n\tu8 link_margin;\n};\n\nstruct ieee80211_mgmt {\n\t__le16 frame_control;\n\t__le16 duration;\n\tu8 da[6];\n\tu8 sa[6];\n\tu8 bssid[6];\n\t__le16 seq_ctrl;\n\tunion {\n\t\tstruct {\n\t\t\t__le16 auth_alg;\n\t\t\t__le16 auth_transaction;\n\t\t\t__le16 status_code;\n\t\t\tu8 variable[0];\n\t\t} auth;\n\t\tstruct {\n\t\t\t__le16 reason_code;\n\t\t} deauth;\n\t\tstruct {\n\t\t\t__le16 capab_info;\n\t\t\t__le16 listen_interval;\n\t\t\tu8 variable[0];\n\t\t} assoc_req;\n\t\tstruct {\n\t\t\t__le16 capab_info;\n\t\t\t__le16 status_code;\n\t\t\t__le16 aid;\n\t\t\tu8 variable[0];\n\t\t} assoc_resp;\n\t\tstruct {\n\t\t\t__le16 capab_info;\n\t\t\t__le16 status_code;\n\t\t\t__le16 aid;\n\t\t\tu8 variable[0];\n\t\t} reassoc_resp;\n\t\tstruct {\n\t\t\t__le16 capab_info;\n\t\t\t__le16 listen_interval;\n\t\t\tu8 current_ap[6];\n\t\t\tu8 variable[0];\n\t\t} reassoc_req;\n\t\tstruct {\n\t\t\t__le16 reason_code;\n\t\t} disassoc;\n\t\tstruct {\n\t\t\t__le64 timestamp;\n\t\t\t__le16 beacon_int;\n\t\t\t__le16 capab_info;\n\t\t\tu8 variable[0];\n\t\t} __attribute__((packed)) beacon;\n\t\tstruct {\n\t\t\tu8 variable[0];\n\t\t} probe_req;\n\t\tstruct {\n\t\t\t__le64 timestamp;\n\t\t\t__le16 beacon_int;\n\t\t\t__le16 capab_info;\n\t\t\tu8 variable[0];\n\t\t} __attribute__((packed)) probe_resp;\n\t\tstruct {\n\t\t\tu8 category;\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 status_code;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} wme_action;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} chan_switch;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tstruct ieee80211_ext_chansw_ie data;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} ext_chan_switch;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 element_id;\n\t\t\t\t\tu8 length;\n\t\t\t\t\tstruct ieee80211_msrment_ie msr_elem;\n\t\t\t\t} measurement;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\t__le16 capab;\n\t\t\t\t\t__le16 timeout;\n\t\t\t\t\t__le16 start_seq_num;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} addba_req;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\t__le16 status;\n\t\t\t\t\t__le16 capab;\n\t\t\t\t\t__le16 timeout;\n\t\t\t\t} addba_resp;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\t__le16 params;\n\t\t\t\t\t__le16 reason_code;\n\t\t\t\t} __attribute__((packed)) delba;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} self_prot;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} mesh_action;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action;\n\t\t\t\t\tu8 trans_id[2];\n\t\t\t\t} sa_query;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action;\n\t\t\t\t\tu8 smps_control;\n\t\t\t\t} ht_smps;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 chanwidth;\n\t\t\t\t} ht_notify_cw;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\t__le16 capability;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} tdls_discover_resp;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 operating_mode;\n\t\t\t\t} vht_opmode_notif;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 membership[8];\n\t\t\t\t\tu8 position[16];\n\t\t\t\t} vht_group_notif;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 tpc_elem_id;\n\t\t\t\t\tu8 tpc_elem_length;\n\t\t\t\t\tstruct ieee80211_tpc_report_ie tpc;\n\t\t\t\t} tpc_report;\n\t\t\t\tstruct {\n\t\t\t\t\tu8 action_code;\n\t\t\t\t\tu8 dialog_token;\n\t\t\t\t\tu8 follow_up;\n\t\t\t\t\tu8 tod[6];\n\t\t\t\t\tu8 toa[6];\n\t\t\t\t\t__le16 tod_error;\n\t\t\t\t\t__le16 toa_error;\n\t\t\t\t\tu8 variable[0];\n\t\t\t\t} __attribute__((packed)) ftm;\n\t\t\t} u;\n\t\t} __attribute__((packed)) action;\n\t} u;\n} __attribute__((packed));\n\nstruct ieee80211_ht_operation {\n\tu8 primary_chan;\n\tu8 ht_param;\n\t__le16 operation_mode;\n\t__le16 stbc_param;\n\tu8 basic_set[16];\n};\n\nenum ieee80211_eid_ext {\n\tWLAN_EID_EXT_ASSOC_DELAY_INFO = 1,\n\tWLAN_EID_EXT_FILS_REQ_PARAMS = 2,\n\tWLAN_EID_EXT_FILS_KEY_CONFIRM = 3,\n\tWLAN_EID_EXT_FILS_SESSION = 4,\n\tWLAN_EID_EXT_FILS_HLP_CONTAINER = 5,\n\tWLAN_EID_EXT_FILS_IP_ADDR_ASSIGN = 6,\n\tWLAN_EID_EXT_KEY_DELIVERY = 7,\n\tWLAN_EID_EXT_FILS_WRAPPED_DATA = 8,\n\tWLAN_EID_EXT_FILS_PUBLIC_KEY = 12,\n\tWLAN_EID_EXT_FILS_NONCE = 13,\n\tWLAN_EID_EXT_FUTURE_CHAN_GUIDANCE = 14,\n\tWLAN_EID_EXT_HE_CAPABILITY = 35,\n\tWLAN_EID_EXT_HE_OPERATION = 36,\n\tWLAN_EID_EXT_UORA = 37,\n\tWLAN_EID_EXT_HE_MU_EDCA = 38,\n\tWLAN_EID_EXT_HE_SPR = 39,\n\tWLAN_EID_EXT_NDP_FEEDBACK_REPORT_PARAMSET = 41,\n\tWLAN_EID_EXT_BSS_COLOR_CHG_ANN = 42,\n\tWLAN_EID_EXT_QUIET_TIME_PERIOD_SETUP = 43,\n\tWLAN_EID_EXT_ESS_REPORT = 45,\n\tWLAN_EID_EXT_OPS = 46,\n\tWLAN_EID_EXT_HE_BSS_LOAD = 47,\n\tWLAN_EID_EXT_MAX_CHANNEL_SWITCH_TIME = 52,\n\tWLAN_EID_EXT_MULTIPLE_BSSID_CONFIGURATION = 55,\n\tWLAN_EID_EXT_NON_INHERITANCE = 56,\n\tWLAN_EID_EXT_KNOWN_BSSID = 57,\n\tWLAN_EID_EXT_SHORT_SSID_LIST = 58,\n\tWLAN_EID_EXT_HE_6GHZ_CAPA = 59,\n\tWLAN_EID_EXT_UL_MU_POWER_CAPA = 60,\n};\n\nenum ieee80211_privacy {\n\tIEEE80211_PRIVACY_ON = 0,\n\tIEEE80211_PRIVACY_OFF = 1,\n\tIEEE80211_PRIVACY_ANY = 2,\n};\n\nstruct cfg80211_inform_bss {\n\tstruct ieee80211_channel *chan;\n\tenum nl80211_bss_scan_width scan_width;\n\ts32 signal;\n\tu64 boottime_ns;\n\tu64 parent_tsf;\n\tu8 parent_bssid[6];\n\tu8 chains;\n\ts8 chain_signal[4];\n};\n\nenum cfg80211_bss_frame_type {\n\tCFG80211_BSS_FTYPE_UNKNOWN = 0,\n\tCFG80211_BSS_FTYPE_BEACON = 1,\n\tCFG80211_BSS_FTYPE_PRESP = 2,\n};\n\nenum bss_compare_mode {\n\tBSS_CMP_REGULAR = 0,\n\tBSS_CMP_HIDE_ZLEN = 1,\n\tBSS_CMP_HIDE_NUL = 2,\n};\n\nstruct cfg80211_non_tx_bss {\n\tstruct cfg80211_bss *tx_bss;\n\tu8 max_bssid_indicator;\n\tu8 bssid_index;\n};\n\nenum ieee80211_vht_mcs_support {\n\tIEEE80211_VHT_MCS_SUPPORT_0_7 = 0,\n\tIEEE80211_VHT_MCS_SUPPORT_0_8 = 1,\n\tIEEE80211_VHT_MCS_SUPPORT_0_9 = 2,\n\tIEEE80211_VHT_MCS_NOT_SUPPORTED = 3,\n};\n\nenum ieee80211_mesh_sync_method {\n\tIEEE80211_SYNC_METHOD_NEIGHBOR_OFFSET = 1,\n\tIEEE80211_SYNC_METHOD_VENDOR = 255,\n};\n\nenum ieee80211_mesh_path_protocol {\n\tIEEE80211_PATH_PROTOCOL_HWMP = 1,\n\tIEEE80211_PATH_PROTOCOL_VENDOR = 255,\n};\n\nenum ieee80211_mesh_path_metric {\n\tIEEE80211_PATH_METRIC_AIRTIME = 1,\n\tIEEE80211_PATH_METRIC_VENDOR = 255,\n};\n\nenum nl80211_attrs {\n\tNL80211_ATTR_UNSPEC = 0,\n\tNL80211_ATTR_WIPHY = 1,\n\tNL80211_ATTR_WIPHY_NAME = 2,\n\tNL80211_ATTR_IFINDEX = 3,\n\tNL80211_ATTR_IFNAME = 4,\n\tNL80211_ATTR_IFTYPE = 5,\n\tNL80211_ATTR_MAC = 6,\n\tNL80211_ATTR_KEY_DATA = 7,\n\tNL80211_ATTR_KEY_IDX = 8,\n\tNL80211_ATTR_KEY_CIPHER = 9,\n\tNL80211_ATTR_KEY_SEQ = 10,\n\tNL80211_ATTR_KEY_DEFAULT = 11,\n\tNL80211_ATTR_BEACON_INTERVAL = 12,\n\tNL80211_ATTR_DTIM_PERIOD = 13,\n\tNL80211_ATTR_BEACON_HEAD = 14,\n\tNL80211_ATTR_BEACON_TAIL = 15,\n\tNL80211_ATTR_STA_AID = 16,\n\tNL80211_ATTR_STA_FLAGS = 17,\n\tNL80211_ATTR_STA_LISTEN_INTERVAL = 18,\n\tNL80211_ATTR_STA_SUPPORTED_RATES = 19,\n\tNL80211_ATTR_STA_VLAN = 20,\n\tNL80211_ATTR_STA_INFO = 21,\n\tNL80211_ATTR_WIPHY_BANDS = 22,\n\tNL80211_ATTR_MNTR_FLAGS = 23,\n\tNL80211_ATTR_MESH_ID = 24,\n\tNL80211_ATTR_STA_PLINK_ACTION = 25,\n\tNL80211_ATTR_MPATH_NEXT_HOP = 26,\n\tNL80211_ATTR_MPATH_INFO = 27,\n\tNL80211_ATTR_BSS_CTS_PROT = 28,\n\tNL80211_ATTR_BSS_SHORT_PREAMBLE = 29,\n\tNL80211_ATTR_BSS_SHORT_SLOT_TIME = 30,\n\tNL80211_ATTR_HT_CAPABILITY = 31,\n\tNL80211_ATTR_SUPPORTED_IFTYPES = 32,\n\tNL80211_ATTR_REG_ALPHA2 = 33,\n\tNL80211_ATTR_REG_RULES = 34,\n\tNL80211_ATTR_MESH_CONFIG = 35,\n\tNL80211_ATTR_BSS_BASIC_RATES = 36,\n\tNL80211_ATTR_WIPHY_TXQ_PARAMS = 37,\n\tNL80211_ATTR_WIPHY_FREQ = 38,\n\tNL80211_ATTR_WIPHY_CHANNEL_TYPE = 39,\n\tNL80211_ATTR_KEY_DEFAULT_MGMT = 40,\n\tNL80211_ATTR_MGMT_SUBTYPE = 41,\n\tNL80211_ATTR_IE = 42,\n\tNL80211_ATTR_MAX_NUM_SCAN_SSIDS = 43,\n\tNL80211_ATTR_SCAN_FREQUENCIES = 44,\n\tNL80211_ATTR_SCAN_SSIDS = 45,\n\tNL80211_ATTR_GENERATION = 46,\n\tNL80211_ATTR_BSS = 47,\n\tNL80211_ATTR_REG_INITIATOR = 48,\n\tNL80211_ATTR_REG_TYPE = 49,\n\tNL80211_ATTR_SUPPORTED_COMMANDS = 50,\n\tNL80211_ATTR_FRAME = 51,\n\tNL80211_ATTR_SSID = 52,\n\tNL80211_ATTR_AUTH_TYPE = 53,\n\tNL80211_ATTR_REASON_CODE = 54,\n\tNL80211_ATTR_KEY_TYPE = 55,\n\tNL80211_ATTR_MAX_SCAN_IE_LEN = 56,\n\tNL80211_ATTR_CIPHER_SUITES = 57,\n\tNL80211_ATTR_FREQ_BEFORE = 58,\n\tNL80211_ATTR_FREQ_AFTER = 59,\n\tNL80211_ATTR_FREQ_FIXED = 60,\n\tNL80211_ATTR_WIPHY_RETRY_SHORT = 61,\n\tNL80211_ATTR_WIPHY_RETRY_LONG = 62,\n\tNL80211_ATTR_WIPHY_FRAG_THRESHOLD = 63,\n\tNL80211_ATTR_WIPHY_RTS_THRESHOLD = 64,\n\tNL80211_ATTR_TIMED_OUT = 65,\n\tNL80211_ATTR_USE_MFP = 66,\n\tNL80211_ATTR_STA_FLAGS2 = 67,\n\tNL80211_ATTR_CONTROL_PORT = 68,\n\tNL80211_ATTR_TESTDATA = 69,\n\tNL80211_ATTR_PRIVACY = 70,\n\tNL80211_ATTR_DISCONNECTED_BY_AP = 71,\n\tNL80211_ATTR_STATUS_CODE = 72,\n\tNL80211_ATTR_CIPHER_SUITES_PAIRWISE = 73,\n\tNL80211_ATTR_CIPHER_SUITE_GROUP = 74,\n\tNL80211_ATTR_WPA_VERSIONS = 75,\n\tNL80211_ATTR_AKM_SUITES = 76,\n\tNL80211_ATTR_REQ_IE = 77,\n\tNL80211_ATTR_RESP_IE = 78,\n\tNL80211_ATTR_PREV_BSSID = 79,\n\tNL80211_ATTR_KEY = 80,\n\tNL80211_ATTR_KEYS = 81,\n\tNL80211_ATTR_PID = 82,\n\tNL80211_ATTR_4ADDR = 83,\n\tNL80211_ATTR_SURVEY_INFO = 84,\n\tNL80211_ATTR_PMKID = 85,\n\tNL80211_ATTR_MAX_NUM_PMKIDS = 86,\n\tNL80211_ATTR_DURATION = 87,\n\tNL80211_ATTR_COOKIE = 88,\n\tNL80211_ATTR_WIPHY_COVERAGE_CLASS = 89,\n\tNL80211_ATTR_TX_RATES = 90,\n\tNL80211_ATTR_FRAME_MATCH = 91,\n\tNL80211_ATTR_ACK = 92,\n\tNL80211_ATTR_PS_STATE = 93,\n\tNL80211_ATTR_CQM = 94,\n\tNL80211_ATTR_LOCAL_STATE_CHANGE = 95,\n\tNL80211_ATTR_AP_ISOLATE = 96,\n\tNL80211_ATTR_WIPHY_TX_POWER_SETTING = 97,\n\tNL80211_ATTR_WIPHY_TX_POWER_LEVEL = 98,\n\tNL80211_ATTR_TX_FRAME_TYPES = 99,\n\tNL80211_ATTR_RX_FRAME_TYPES = 100,\n\tNL80211_ATTR_FRAME_TYPE = 101,\n\tNL80211_ATTR_CONTROL_PORT_ETHERTYPE = 102,\n\tNL80211_ATTR_CONTROL_PORT_NO_ENCRYPT = 103,\n\tNL80211_ATTR_SUPPORT_IBSS_RSN = 104,\n\tNL80211_ATTR_WIPHY_ANTENNA_TX = 105,\n\tNL80211_ATTR_WIPHY_ANTENNA_RX = 106,\n\tNL80211_ATTR_MCAST_RATE = 107,\n\tNL80211_ATTR_OFFCHANNEL_TX_OK = 108,\n\tNL80211_ATTR_BSS_HT_OPMODE = 109,\n\tNL80211_ATTR_KEY_DEFAULT_TYPES = 110,\n\tNL80211_ATTR_MAX_REMAIN_ON_CHANNEL_DURATION = 111,\n\tNL80211_ATTR_MESH_SETUP = 112,\n\tNL80211_ATTR_WIPHY_ANTENNA_AVAIL_TX = 113,\n\tNL80211_ATTR_WIPHY_ANTENNA_AVAIL_RX = 114,\n\tNL80211_ATTR_SUPPORT_MESH_AUTH = 115,\n\tNL80211_ATTR_STA_PLINK_STATE = 116,\n\tNL80211_ATTR_WOWLAN_TRIGGERS = 117,\n\tNL80211_ATTR_WOWLAN_TRIGGERS_SUPPORTED = 118,\n\tNL80211_ATTR_SCHED_SCAN_INTERVAL = 119,\n\tNL80211_ATTR_INTERFACE_COMBINATIONS = 120,\n\tNL80211_ATTR_SOFTWARE_IFTYPES = 121,\n\tNL80211_ATTR_REKEY_DATA = 122,\n\tNL80211_ATTR_MAX_NUM_SCHED_SCAN_SSIDS = 123,\n\tNL80211_ATTR_MAX_SCHED_SCAN_IE_LEN = 124,\n\tNL80211_ATTR_SCAN_SUPP_RATES = 125,\n\tNL80211_ATTR_HIDDEN_SSID = 126,\n\tNL80211_ATTR_IE_PROBE_RESP = 127,\n\tNL80211_ATTR_IE_ASSOC_RESP = 128,\n\tNL80211_ATTR_STA_WME = 129,\n\tNL80211_ATTR_SUPPORT_AP_UAPSD = 130,\n\tNL80211_ATTR_ROAM_SUPPORT = 131,\n\tNL80211_ATTR_SCHED_SCAN_MATCH = 132,\n\tNL80211_ATTR_MAX_MATCH_SETS = 133,\n\tNL80211_ATTR_PMKSA_CANDIDATE = 134,\n\tNL80211_ATTR_TX_NO_CCK_RATE = 135,\n\tNL80211_ATTR_TDLS_ACTION = 136,\n\tNL80211_ATTR_TDLS_DIALOG_TOKEN = 137,\n\tNL80211_ATTR_TDLS_OPERATION = 138,\n\tNL80211_ATTR_TDLS_SUPPORT = 139,\n\tNL80211_ATTR_TDLS_EXTERNAL_SETUP = 140,\n\tNL80211_ATTR_DEVICE_AP_SME = 141,\n\tNL80211_ATTR_DONT_WAIT_FOR_ACK = 142,\n\tNL80211_ATTR_FEATURE_FLAGS = 143,\n\tNL80211_ATTR_PROBE_RESP_OFFLOAD = 144,\n\tNL80211_ATTR_PROBE_RESP = 145,\n\tNL80211_ATTR_DFS_REGION = 146,\n\tNL80211_ATTR_DISABLE_HT = 147,\n\tNL80211_ATTR_HT_CAPABILITY_MASK = 148,\n\tNL80211_ATTR_NOACK_MAP = 149,\n\tNL80211_ATTR_INACTIVITY_TIMEOUT = 150,\n\tNL80211_ATTR_RX_SIGNAL_DBM = 151,\n\tNL80211_ATTR_BG_SCAN_PERIOD = 152,\n\tNL80211_ATTR_WDEV = 153,\n\tNL80211_ATTR_USER_REG_HINT_TYPE = 154,\n\tNL80211_ATTR_CONN_FAILED_REASON = 155,\n\tNL80211_ATTR_AUTH_DATA = 156,\n\tNL80211_ATTR_VHT_CAPABILITY = 157,\n\tNL80211_ATTR_SCAN_FLAGS = 158,\n\tNL80211_ATTR_CHANNEL_WIDTH = 159,\n\tNL80211_ATTR_CENTER_FREQ1 = 160,\n\tNL80211_ATTR_CENTER_FREQ2 = 161,\n\tNL80211_ATTR_P2P_CTWINDOW = 162,\n\tNL80211_ATTR_P2P_OPPPS = 163,\n\tNL80211_ATTR_LOCAL_MESH_POWER_MODE = 164,\n\tNL80211_ATTR_ACL_POLICY = 165,\n\tNL80211_ATTR_MAC_ADDRS = 166,\n\tNL80211_ATTR_MAC_ACL_MAX = 167,\n\tNL80211_ATTR_RADAR_EVENT = 168,\n\tNL80211_ATTR_EXT_CAPA = 169,\n\tNL80211_ATTR_EXT_CAPA_MASK = 170,\n\tNL80211_ATTR_STA_CAPABILITY = 171,\n\tNL80211_ATTR_STA_EXT_CAPABILITY = 172,\n\tNL80211_ATTR_PROTOCOL_FEATURES = 173,\n\tNL80211_ATTR_SPLIT_WIPHY_DUMP = 174,\n\tNL80211_ATTR_DISABLE_VHT = 175,\n\tNL80211_ATTR_VHT_CAPABILITY_MASK = 176,\n\tNL80211_ATTR_MDID = 177,\n\tNL80211_ATTR_IE_RIC = 178,\n\tNL80211_ATTR_CRIT_PROT_ID = 179,\n\tNL80211_ATTR_MAX_CRIT_PROT_DURATION = 180,\n\tNL80211_ATTR_PEER_AID = 181,\n\tNL80211_ATTR_COALESCE_RULE = 182,\n\tNL80211_ATTR_CH_SWITCH_COUNT = 183,\n\tNL80211_ATTR_CH_SWITCH_BLOCK_TX = 184,\n\tNL80211_ATTR_CSA_IES = 185,\n\tNL80211_ATTR_CSA_C_OFF_BEACON = 186,\n\tNL80211_ATTR_CSA_C_OFF_PRESP = 187,\n\tNL80211_ATTR_RXMGMT_FLAGS = 188,\n\tNL80211_ATTR_STA_SUPPORTED_CHANNELS = 189,\n\tNL80211_ATTR_STA_SUPPORTED_OPER_CLASSES = 190,\n\tNL80211_ATTR_HANDLE_DFS = 191,\n\tNL80211_ATTR_SUPPORT_5_MHZ = 192,\n\tNL80211_ATTR_SUPPORT_10_MHZ = 193,\n\tNL80211_ATTR_OPMODE_NOTIF = 194,\n\tNL80211_ATTR_VENDOR_ID = 195,\n\tNL80211_ATTR_VENDOR_SUBCMD = 196,\n\tNL80211_ATTR_VENDOR_DATA = 197,\n\tNL80211_ATTR_VENDOR_EVENTS = 198,\n\tNL80211_ATTR_QOS_MAP = 199,\n\tNL80211_ATTR_MAC_HINT = 200,\n\tNL80211_ATTR_WIPHY_FREQ_HINT = 201,\n\tNL80211_ATTR_MAX_AP_ASSOC_STA = 202,\n\tNL80211_ATTR_TDLS_PEER_CAPABILITY = 203,\n\tNL80211_ATTR_SOCKET_OWNER = 204,\n\tNL80211_ATTR_CSA_C_OFFSETS_TX = 205,\n\tNL80211_ATTR_MAX_CSA_COUNTERS = 206,\n\tNL80211_ATTR_TDLS_INITIATOR = 207,\n\tNL80211_ATTR_USE_RRM = 208,\n\tNL80211_ATTR_WIPHY_DYN_ACK = 209,\n\tNL80211_ATTR_TSID = 210,\n\tNL80211_ATTR_USER_PRIO = 211,\n\tNL80211_ATTR_ADMITTED_TIME = 212,\n\tNL80211_ATTR_SMPS_MODE = 213,\n\tNL80211_ATTR_OPER_CLASS = 214,\n\tNL80211_ATTR_MAC_MASK = 215,\n\tNL80211_ATTR_WIPHY_SELF_MANAGED_REG = 216,\n\tNL80211_ATTR_EXT_FEATURES = 217,\n\tNL80211_ATTR_SURVEY_RADIO_STATS = 218,\n\tNL80211_ATTR_NETNS_FD = 219,\n\tNL80211_ATTR_SCHED_SCAN_DELAY = 220,\n\tNL80211_ATTR_REG_INDOOR = 221,\n\tNL80211_ATTR_MAX_NUM_SCHED_SCAN_PLANS = 222,\n\tNL80211_ATTR_MAX_SCAN_PLAN_INTERVAL = 223,\n\tNL80211_ATTR_MAX_SCAN_PLAN_ITERATIONS = 224,\n\tNL80211_ATTR_SCHED_SCAN_PLANS = 225,\n\tNL80211_ATTR_PBSS = 226,\n\tNL80211_ATTR_BSS_SELECT = 227,\n\tNL80211_ATTR_STA_SUPPORT_P2P_PS = 228,\n\tNL80211_ATTR_PAD = 229,\n\tNL80211_ATTR_IFTYPE_EXT_CAPA = 230,\n\tNL80211_ATTR_MU_MIMO_GROUP_DATA = 231,\n\tNL80211_ATTR_MU_MIMO_FOLLOW_MAC_ADDR = 232,\n\tNL80211_ATTR_SCAN_START_TIME_TSF = 233,\n\tNL80211_ATTR_SCAN_START_TIME_TSF_BSSID = 234,\n\tNL80211_ATTR_MEASUREMENT_DURATION = 235,\n\tNL80211_ATTR_MEASUREMENT_DURATION_MANDATORY = 236,\n\tNL80211_ATTR_MESH_PEER_AID = 237,\n\tNL80211_ATTR_NAN_MASTER_PREF = 238,\n\tNL80211_ATTR_BANDS = 239,\n\tNL80211_ATTR_NAN_FUNC = 240,\n\tNL80211_ATTR_NAN_MATCH = 241,\n\tNL80211_ATTR_FILS_KEK = 242,\n\tNL80211_ATTR_FILS_NONCES = 243,\n\tNL80211_ATTR_MULTICAST_TO_UNICAST_ENABLED = 244,\n\tNL80211_ATTR_BSSID = 245,\n\tNL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI = 246,\n\tNL80211_ATTR_SCHED_SCAN_RSSI_ADJUST = 247,\n\tNL80211_ATTR_TIMEOUT_REASON = 248,\n\tNL80211_ATTR_FILS_ERP_USERNAME = 249,\n\tNL80211_ATTR_FILS_ERP_REALM = 250,\n\tNL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM = 251,\n\tNL80211_ATTR_FILS_ERP_RRK = 252,\n\tNL80211_ATTR_FILS_CACHE_ID = 253,\n\tNL80211_ATTR_PMK = 254,\n\tNL80211_ATTR_SCHED_SCAN_MULTI = 255,\n\tNL80211_ATTR_SCHED_SCAN_MAX_REQS = 256,\n\tNL80211_ATTR_WANT_1X_4WAY_HS = 257,\n\tNL80211_ATTR_PMKR0_NAME = 258,\n\tNL80211_ATTR_PORT_AUTHORIZED = 259,\n\tNL80211_ATTR_EXTERNAL_AUTH_ACTION = 260,\n\tNL80211_ATTR_EXTERNAL_AUTH_SUPPORT = 261,\n\tNL80211_ATTR_NSS = 262,\n\tNL80211_ATTR_ACK_SIGNAL = 263,\n\tNL80211_ATTR_CONTROL_PORT_OVER_NL80211 = 264,\n\tNL80211_ATTR_TXQ_STATS = 265,\n\tNL80211_ATTR_TXQ_LIMIT = 266,\n\tNL80211_ATTR_TXQ_MEMORY_LIMIT = 267,\n\tNL80211_ATTR_TXQ_QUANTUM = 268,\n\tNL80211_ATTR_HE_CAPABILITY = 269,\n\tNL80211_ATTR_FTM_RESPONDER = 270,\n\tNL80211_ATTR_FTM_RESPONDER_STATS = 271,\n\tNL80211_ATTR_TIMEOUT = 272,\n\tNL80211_ATTR_PEER_MEASUREMENTS = 273,\n\tNL80211_ATTR_AIRTIME_WEIGHT = 274,\n\tNL80211_ATTR_STA_TX_POWER_SETTING = 275,\n\tNL80211_ATTR_STA_TX_POWER = 276,\n\tNL80211_ATTR_SAE_PASSWORD = 277,\n\tNL80211_ATTR_TWT_RESPONDER = 278,\n\tNL80211_ATTR_HE_OBSS_PD = 279,\n\tNL80211_ATTR_WIPHY_EDMG_CHANNELS = 280,\n\tNL80211_ATTR_WIPHY_EDMG_BW_CONFIG = 281,\n\tNL80211_ATTR_VLAN_ID = 282,\n\tNL80211_ATTR_HE_BSS_COLOR = 283,\n\tNL80211_ATTR_IFTYPE_AKM_SUITES = 284,\n\tNL80211_ATTR_TID_CONFIG = 285,\n\tNL80211_ATTR_CONTROL_PORT_NO_PREAUTH = 286,\n\tNL80211_ATTR_PMK_LIFETIME = 287,\n\tNL80211_ATTR_PMK_REAUTH_THRESHOLD = 288,\n\tNL80211_ATTR_RECEIVE_MULTICAST = 289,\n\tNL80211_ATTR_WIPHY_FREQ_OFFSET = 290,\n\tNL80211_ATTR_CENTER_FREQ1_OFFSET = 291,\n\tNL80211_ATTR_SCAN_FREQ_KHZ = 292,\n\tNL80211_ATTR_HE_6GHZ_CAPABILITY = 293,\n\t__NL80211_ATTR_AFTER_LAST = 294,\n\tNUM_NL80211_ATTR = 294,\n\tNL80211_ATTR_MAX = 293,\n};\n\nenum nl80211_sta_flags {\n\t__NL80211_STA_FLAG_INVALID = 0,\n\tNL80211_STA_FLAG_AUTHORIZED = 1,\n\tNL80211_STA_FLAG_SHORT_PREAMBLE = 2,\n\tNL80211_STA_FLAG_WME = 3,\n\tNL80211_STA_FLAG_MFP = 4,\n\tNL80211_STA_FLAG_AUTHENTICATED = 5,\n\tNL80211_STA_FLAG_TDLS_PEER = 6,\n\tNL80211_STA_FLAG_ASSOCIATED = 7,\n\t__NL80211_STA_FLAG_AFTER_LAST = 8,\n\tNL80211_STA_FLAG_MAX = 7,\n};\n\nenum nl80211_sta_p2p_ps_status {\n\tNL80211_P2P_PS_UNSUPPORTED = 0,\n\tNL80211_P2P_PS_SUPPORTED = 1,\n\tNUM_NL80211_P2P_PS_STATUS = 2,\n};\n\nenum nl80211_rate_info {\n\t__NL80211_RATE_INFO_INVALID = 0,\n\tNL80211_RATE_INFO_BITRATE = 1,\n\tNL80211_RATE_INFO_MCS = 2,\n\tNL80211_RATE_INFO_40_MHZ_WIDTH = 3,\n\tNL80211_RATE_INFO_SHORT_GI = 4,\n\tNL80211_RATE_INFO_BITRATE32 = 5,\n\tNL80211_RATE_INFO_VHT_MCS = 6,\n\tNL80211_RATE_INFO_VHT_NSS = 7,\n\tNL80211_RATE_INFO_80_MHZ_WIDTH = 8,\n\tNL80211_RATE_INFO_80P80_MHZ_WIDTH = 9,\n\tNL80211_RATE_INFO_160_MHZ_WIDTH = 10,\n\tNL80211_RATE_INFO_10_MHZ_WIDTH = 11,\n\tNL80211_RATE_INFO_5_MHZ_WIDTH = 12,\n\tNL80211_RATE_INFO_HE_MCS = 13,\n\tNL80211_RATE_INFO_HE_NSS = 14,\n\tNL80211_RATE_INFO_HE_GI = 15,\n\tNL80211_RATE_INFO_HE_DCM = 16,\n\tNL80211_RATE_INFO_HE_RU_ALLOC = 17,\n\t__NL80211_RATE_INFO_AFTER_LAST = 18,\n\tNL80211_RATE_INFO_MAX = 17,\n};\n\nenum nl80211_sta_bss_param {\n\t__NL80211_STA_BSS_PARAM_INVALID = 0,\n\tNL80211_STA_BSS_PARAM_CTS_PROT = 1,\n\tNL80211_STA_BSS_PARAM_SHORT_PREAMBLE = 2,\n\tNL80211_STA_BSS_PARAM_SHORT_SLOT_TIME = 3,\n\tNL80211_STA_BSS_PARAM_DTIM_PERIOD = 4,\n\tNL80211_STA_BSS_PARAM_BEACON_INTERVAL = 5,\n\t__NL80211_STA_BSS_PARAM_AFTER_LAST = 6,\n\tNL80211_STA_BSS_PARAM_MAX = 5,\n};\n\nenum nl80211_sta_info {\n\t__NL80211_STA_INFO_INVALID = 0,\n\tNL80211_STA_INFO_INACTIVE_TIME = 1,\n\tNL80211_STA_INFO_RX_BYTES = 2,\n\tNL80211_STA_INFO_TX_BYTES = 3,\n\tNL80211_STA_INFO_LLID = 4,\n\tNL80211_STA_INFO_PLID = 5,\n\tNL80211_STA_INFO_PLINK_STATE = 6,\n\tNL80211_STA_INFO_SIGNAL = 7,\n\tNL80211_STA_INFO_TX_BITRATE = 8,\n\tNL80211_STA_INFO_RX_PACKETS = 9,\n\tNL80211_STA_INFO_TX_PACKETS = 10,\n\tNL80211_STA_INFO_TX_RETRIES = 11,\n\tNL80211_STA_INFO_TX_FAILED = 12,\n\tNL80211_STA_INFO_SIGNAL_AVG = 13,\n\tNL80211_STA_INFO_RX_BITRATE = 14,\n\tNL80211_STA_INFO_BSS_PARAM = 15,\n\tNL80211_STA_INFO_CONNECTED_TIME = 16,\n\tNL80211_STA_INFO_STA_FLAGS = 17,\n\tNL80211_STA_INFO_BEACON_LOSS = 18,\n\tNL80211_STA_INFO_T_OFFSET = 19,\n\tNL80211_STA_INFO_LOCAL_PM = 20,\n\tNL80211_STA_INFO_PEER_PM = 21,\n\tNL80211_STA_INFO_NONPEER_PM = 22,\n\tNL80211_STA_INFO_RX_BYTES64 = 23,\n\tNL80211_STA_INFO_TX_BYTES64 = 24,\n\tNL80211_STA_INFO_CHAIN_SIGNAL = 25,\n\tNL80211_STA_INFO_CHAIN_SIGNAL_AVG = 26,\n\tNL80211_STA_INFO_EXPECTED_THROUGHPUT = 27,\n\tNL80211_STA_INFO_RX_DROP_MISC = 28,\n\tNL80211_STA_INFO_BEACON_RX = 29,\n\tNL80211_STA_INFO_BEACON_SIGNAL_AVG = 30,\n\tNL80211_STA_INFO_TID_STATS = 31,\n\tNL80211_STA_INFO_RX_DURATION = 32,\n\tNL80211_STA_INFO_PAD = 33,\n\tNL80211_STA_INFO_ACK_SIGNAL = 34,\n\tNL80211_STA_INFO_ACK_SIGNAL_AVG = 35,\n\tNL80211_STA_INFO_RX_MPDUS = 36,\n\tNL80211_STA_INFO_FCS_ERROR_COUNT = 37,\n\tNL80211_STA_INFO_CONNECTED_TO_GATE = 38,\n\tNL80211_STA_INFO_TX_DURATION = 39,\n\tNL80211_STA_INFO_AIRTIME_WEIGHT = 40,\n\tNL80211_STA_INFO_AIRTIME_LINK_METRIC = 41,\n\tNL80211_STA_INFO_ASSOC_AT_BOOTTIME = 42,\n\t__NL80211_STA_INFO_AFTER_LAST = 43,\n\tNL80211_STA_INFO_MAX = 42,\n};\n\nenum nl80211_tid_stats {\n\t__NL80211_TID_STATS_INVALID = 0,\n\tNL80211_TID_STATS_RX_MSDU = 1,\n\tNL80211_TID_STATS_TX_MSDU = 2,\n\tNL80211_TID_STATS_TX_MSDU_RETRIES = 3,\n\tNL80211_TID_STATS_TX_MSDU_FAILED = 4,\n\tNL80211_TID_STATS_PAD = 5,\n\tNL80211_TID_STATS_TXQ_STATS = 6,\n\tNUM_NL80211_TID_STATS = 7,\n\tNL80211_TID_STATS_MAX = 6,\n};\n\nenum nl80211_txq_stats {\n\t__NL80211_TXQ_STATS_INVALID = 0,\n\tNL80211_TXQ_STATS_BACKLOG_BYTES = 1,\n\tNL80211_TXQ_STATS_BACKLOG_PACKETS = 2,\n\tNL80211_TXQ_STATS_FLOWS = 3,\n\tNL80211_TXQ_STATS_DROPS = 4,\n\tNL80211_TXQ_STATS_ECN_MARKS = 5,\n\tNL80211_TXQ_STATS_OVERLIMIT = 6,\n\tNL80211_TXQ_STATS_OVERMEMORY = 7,\n\tNL80211_TXQ_STATS_COLLISIONS = 8,\n\tNL80211_TXQ_STATS_TX_BYTES = 9,\n\tNL80211_TXQ_STATS_TX_PACKETS = 10,\n\tNL80211_TXQ_STATS_MAX_FLOWS = 11,\n\tNUM_NL80211_TXQ_STATS = 12,\n\tNL80211_TXQ_STATS_MAX = 11,\n};\n\nenum nl80211_mpath_info {\n\t__NL80211_MPATH_INFO_INVALID = 0,\n\tNL80211_MPATH_INFO_FRAME_QLEN = 1,\n\tNL80211_MPATH_INFO_SN = 2,\n\tNL80211_MPATH_INFO_METRIC = 3,\n\tNL80211_MPATH_INFO_EXPTIME = 4,\n\tNL80211_MPATH_INFO_FLAGS = 5,\n\tNL80211_MPATH_INFO_DISCOVERY_TIMEOUT = 6,\n\tNL80211_MPATH_INFO_DISCOVERY_RETRIES = 7,\n\tNL80211_MPATH_INFO_HOP_COUNT = 8,\n\tNL80211_MPATH_INFO_PATH_CHANGE = 9,\n\t__NL80211_MPATH_INFO_AFTER_LAST = 10,\n\tNL80211_MPATH_INFO_MAX = 9,\n};\n\nenum nl80211_band_iftype_attr {\n\t__NL80211_BAND_IFTYPE_ATTR_INVALID = 0,\n\tNL80211_BAND_IFTYPE_ATTR_IFTYPES = 1,\n\tNL80211_BAND_IFTYPE_ATTR_HE_CAP_MAC = 2,\n\tNL80211_BAND_IFTYPE_ATTR_HE_CAP_PHY = 3,\n\tNL80211_BAND_IFTYPE_ATTR_HE_CAP_MCS_SET = 4,\n\tNL80211_BAND_IFTYPE_ATTR_HE_CAP_PPE = 5,\n\tNL80211_BAND_IFTYPE_ATTR_HE_6GHZ_CAPA = 6,\n\t__NL80211_BAND_IFTYPE_ATTR_AFTER_LAST = 7,\n\tNL80211_BAND_IFTYPE_ATTR_MAX = 6,\n};\n\nenum nl80211_band_attr {\n\t__NL80211_BAND_ATTR_INVALID = 0,\n\tNL80211_BAND_ATTR_FREQS = 1,\n\tNL80211_BAND_ATTR_RATES = 2,\n\tNL80211_BAND_ATTR_HT_MCS_SET = 3,\n\tNL80211_BAND_ATTR_HT_CAPA = 4,\n\tNL80211_BAND_ATTR_HT_AMPDU_FACTOR = 5,\n\tNL80211_BAND_ATTR_HT_AMPDU_DENSITY = 6,\n\tNL80211_BAND_ATTR_VHT_MCS_SET = 7,\n\tNL80211_BAND_ATTR_VHT_CAPA = 8,\n\tNL80211_BAND_ATTR_IFTYPE_DATA = 9,\n\tNL80211_BAND_ATTR_EDMG_CHANNELS = 10,\n\tNL80211_BAND_ATTR_EDMG_BW_CONFIG = 11,\n\t__NL80211_BAND_ATTR_AFTER_LAST = 12,\n\tNL80211_BAND_ATTR_MAX = 11,\n};\n\nenum nl80211_wmm_rule {\n\t__NL80211_WMMR_INVALID = 0,\n\tNL80211_WMMR_CW_MIN = 1,\n\tNL80211_WMMR_CW_MAX = 2,\n\tNL80211_WMMR_AIFSN = 3,\n\tNL80211_WMMR_TXOP = 4,\n\t__NL80211_WMMR_LAST = 5,\n\tNL80211_WMMR_MAX = 4,\n};\n\nenum nl80211_frequency_attr {\n\t__NL80211_FREQUENCY_ATTR_INVALID = 0,\n\tNL80211_FREQUENCY_ATTR_FREQ = 1,\n\tNL80211_FREQUENCY_ATTR_DISABLED = 2,\n\tNL80211_FREQUENCY_ATTR_NO_IR = 3,\n\t__NL80211_FREQUENCY_ATTR_NO_IBSS = 4,\n\tNL80211_FREQUENCY_ATTR_RADAR = 5,\n\tNL80211_FREQUENCY_ATTR_MAX_TX_POWER = 6,\n\tNL80211_FREQUENCY_ATTR_DFS_STATE = 7,\n\tNL80211_FREQUENCY_ATTR_DFS_TIME = 8,\n\tNL80211_FREQUENCY_ATTR_NO_HT40_MINUS = 9,\n\tNL80211_FREQUENCY_ATTR_NO_HT40_PLUS = 10,\n\tNL80211_FREQUENCY_ATTR_NO_80MHZ = 11,\n\tNL80211_FREQUENCY_ATTR_NO_160MHZ = 12,\n\tNL80211_FREQUENCY_ATTR_DFS_CAC_TIME = 13,\n\tNL80211_FREQUENCY_ATTR_INDOOR_ONLY = 14,\n\tNL80211_FREQUENCY_ATTR_IR_CONCURRENT = 15,\n\tNL80211_FREQUENCY_ATTR_NO_20MHZ = 16,\n\tNL80211_FREQUENCY_ATTR_NO_10MHZ = 17,\n\tNL80211_FREQUENCY_ATTR_WMM = 18,\n\tNL80211_FREQUENCY_ATTR_NO_HE = 19,\n\tNL80211_FREQUENCY_ATTR_OFFSET = 20,\n\t__NL80211_FREQUENCY_ATTR_AFTER_LAST = 21,\n\tNL80211_FREQUENCY_ATTR_MAX = 20,\n};\n\nenum nl80211_bitrate_attr {\n\t__NL80211_BITRATE_ATTR_INVALID = 0,\n\tNL80211_BITRATE_ATTR_RATE = 1,\n\tNL80211_BITRATE_ATTR_2GHZ_SHORTPREAMBLE = 2,\n\t__NL80211_BITRATE_ATTR_AFTER_LAST = 3,\n\tNL80211_BITRATE_ATTR_MAX = 2,\n};\n\nenum nl80211_reg_type {\n\tNL80211_REGDOM_TYPE_COUNTRY = 0,\n\tNL80211_REGDOM_TYPE_WORLD = 1,\n\tNL80211_REGDOM_TYPE_CUSTOM_WORLD = 2,\n\tNL80211_REGDOM_TYPE_INTERSECTION = 3,\n};\n\nenum nl80211_reg_rule_attr {\n\t__NL80211_REG_RULE_ATTR_INVALID = 0,\n\tNL80211_ATTR_REG_RULE_FLAGS = 1,\n\tNL80211_ATTR_FREQ_RANGE_START = 2,\n\tNL80211_ATTR_FREQ_RANGE_END = 3,\n\tNL80211_ATTR_FREQ_RANGE_MAX_BW = 4,\n\tNL80211_ATTR_POWER_RULE_MAX_ANT_GAIN = 5,\n\tNL80211_ATTR_POWER_RULE_MAX_EIRP = 6,\n\tNL80211_ATTR_DFS_CAC_TIME = 7,\n\t__NL80211_REG_RULE_ATTR_AFTER_LAST = 8,\n\tNL80211_REG_RULE_ATTR_MAX = 7,\n};\n\nenum nl80211_sched_scan_match_attr {\n\t__NL80211_SCHED_SCAN_MATCH_ATTR_INVALID = 0,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_SSID = 1,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_RSSI = 2,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_RELATIVE_RSSI = 3,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_RSSI_ADJUST = 4,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_BSSID = 5,\n\tNL80211_SCHED_SCAN_MATCH_PER_BAND_RSSI = 6,\n\t__NL80211_SCHED_SCAN_MATCH_ATTR_AFTER_LAST = 7,\n\tNL80211_SCHED_SCAN_MATCH_ATTR_MAX = 6,\n};\n\nenum nl80211_survey_info {\n\t__NL80211_SURVEY_INFO_INVALID = 0,\n\tNL80211_SURVEY_INFO_FREQUENCY = 1,\n\tNL80211_SURVEY_INFO_NOISE = 2,\n\tNL80211_SURVEY_INFO_IN_USE = 3,\n\tNL80211_SURVEY_INFO_TIME = 4,\n\tNL80211_SURVEY_INFO_TIME_BUSY = 5,\n\tNL80211_SURVEY_INFO_TIME_EXT_BUSY = 6,\n\tNL80211_SURVEY_INFO_TIME_RX = 7,\n\tNL80211_SURVEY_INFO_TIME_TX = 8,\n\tNL80211_SURVEY_INFO_TIME_SCAN = 9,\n\tNL80211_SURVEY_INFO_PAD = 10,\n\tNL80211_SURVEY_INFO_TIME_BSS_RX = 11,\n\t__NL80211_SURVEY_INFO_AFTER_LAST = 12,\n\tNL80211_SURVEY_INFO_MAX = 11,\n};\n\nenum nl80211_meshconf_params {\n\t__NL80211_MESHCONF_INVALID = 0,\n\tNL80211_MESHCONF_RETRY_TIMEOUT = 1,\n\tNL80211_MESHCONF_CONFIRM_TIMEOUT = 2,\n\tNL80211_MESHCONF_HOLDING_TIMEOUT = 3,\n\tNL80211_MESHCONF_MAX_PEER_LINKS = 4,\n\tNL80211_MESHCONF_MAX_RETRIES = 5,\n\tNL80211_MESHCONF_TTL = 6,\n\tNL80211_MESHCONF_AUTO_OPEN_PLINKS = 7,\n\tNL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES = 8,\n\tNL80211_MESHCONF_PATH_REFRESH_TIME = 9,\n\tNL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT = 10,\n\tNL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT = 11,\n\tNL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL = 12,\n\tNL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME = 13,\n\tNL80211_MESHCONF_HWMP_ROOTMODE = 14,\n\tNL80211_MESHCONF_ELEMENT_TTL = 15,\n\tNL80211_MESHCONF_HWMP_RANN_INTERVAL = 16,\n\tNL80211_MESHCONF_GATE_ANNOUNCEMENTS = 17,\n\tNL80211_MESHCONF_HWMP_PERR_MIN_INTERVAL = 18,\n\tNL80211_MESHCONF_FORWARDING = 19,\n\tNL80211_MESHCONF_RSSI_THRESHOLD = 20,\n\tNL80211_MESHCONF_SYNC_OFFSET_MAX_NEIGHBOR = 21,\n\tNL80211_MESHCONF_HT_OPMODE = 22,\n\tNL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT = 23,\n\tNL80211_MESHCONF_HWMP_ROOT_INTERVAL = 24,\n\tNL80211_MESHCONF_HWMP_CONFIRMATION_INTERVAL = 25,\n\tNL80211_MESHCONF_POWER_MODE = 26,\n\tNL80211_MESHCONF_AWAKE_WINDOW = 27,\n\tNL80211_MESHCONF_PLINK_TIMEOUT = 28,\n\tNL80211_MESHCONF_CONNECTED_TO_GATE = 29,\n\t__NL80211_MESHCONF_ATTR_AFTER_LAST = 30,\n\tNL80211_MESHCONF_ATTR_MAX = 29,\n};\n\nenum nl80211_mesh_setup_params {\n\t__NL80211_MESH_SETUP_INVALID = 0,\n\tNL80211_MESH_SETUP_ENABLE_VENDOR_PATH_SEL = 1,\n\tNL80211_MESH_SETUP_ENABLE_VENDOR_METRIC = 2,\n\tNL80211_MESH_SETUP_IE = 3,\n\tNL80211_MESH_SETUP_USERSPACE_AUTH = 4,\n\tNL80211_MESH_SETUP_USERSPACE_AMPE = 5,\n\tNL80211_MESH_SETUP_ENABLE_VENDOR_SYNC = 6,\n\tNL80211_MESH_SETUP_USERSPACE_MPM = 7,\n\tNL80211_MESH_SETUP_AUTH_PROTOCOL = 8,\n\t__NL80211_MESH_SETUP_ATTR_AFTER_LAST = 9,\n\tNL80211_MESH_SETUP_ATTR_MAX = 8,\n};\n\nenum nl80211_txq_attr {\n\t__NL80211_TXQ_ATTR_INVALID = 0,\n\tNL80211_TXQ_ATTR_AC = 1,\n\tNL80211_TXQ_ATTR_TXOP = 2,\n\tNL80211_TXQ_ATTR_CWMIN = 3,\n\tNL80211_TXQ_ATTR_CWMAX = 4,\n\tNL80211_TXQ_ATTR_AIFS = 5,\n\t__NL80211_TXQ_ATTR_AFTER_LAST = 6,\n\tNL80211_TXQ_ATTR_MAX = 5,\n};\n\nenum nl80211_bss {\n\t__NL80211_BSS_INVALID = 0,\n\tNL80211_BSS_BSSID = 1,\n\tNL80211_BSS_FREQUENCY = 2,\n\tNL80211_BSS_TSF = 3,\n\tNL80211_BSS_BEACON_INTERVAL = 4,\n\tNL80211_BSS_CAPABILITY = 5,\n\tNL80211_BSS_INFORMATION_ELEMENTS = 6,\n\tNL80211_BSS_SIGNAL_MBM = 7,\n\tNL80211_BSS_SIGNAL_UNSPEC = 8,\n\tNL80211_BSS_STATUS = 9,\n\tNL80211_BSS_SEEN_MS_AGO = 10,\n\tNL80211_BSS_BEACON_IES = 11,\n\tNL80211_BSS_CHAN_WIDTH = 12,\n\tNL80211_BSS_BEACON_TSF = 13,\n\tNL80211_BSS_PRESP_DATA = 14,\n\tNL80211_BSS_LAST_SEEN_BOOTTIME = 15,\n\tNL80211_BSS_PAD = 16,\n\tNL80211_BSS_PARENT_TSF = 17,\n\tNL80211_BSS_PARENT_BSSID = 18,\n\tNL80211_BSS_CHAIN_SIGNAL = 19,\n\tNL80211_BSS_FREQUENCY_OFFSET = 20,\n\t__NL80211_BSS_AFTER_LAST = 21,\n\tNL80211_BSS_MAX = 20,\n};\n\nenum nl80211_bss_status {\n\tNL80211_BSS_STATUS_AUTHENTICATED = 0,\n\tNL80211_BSS_STATUS_ASSOCIATED = 1,\n\tNL80211_BSS_STATUS_IBSS_JOINED = 2,\n};\n\nenum nl80211_key_type {\n\tNL80211_KEYTYPE_GROUP = 0,\n\tNL80211_KEYTYPE_PAIRWISE = 1,\n\tNL80211_KEYTYPE_PEERKEY = 2,\n\tNUM_NL80211_KEYTYPES = 3,\n};\n\nenum nl80211_wpa_versions {\n\tNL80211_WPA_VERSION_1 = 1,\n\tNL80211_WPA_VERSION_2 = 2,\n\tNL80211_WPA_VERSION_3 = 4,\n};\n\nenum nl80211_key_default_types {\n\t__NL80211_KEY_DEFAULT_TYPE_INVALID = 0,\n\tNL80211_KEY_DEFAULT_TYPE_UNICAST = 1,\n\tNL80211_KEY_DEFAULT_TYPE_MULTICAST = 2,\n\tNUM_NL80211_KEY_DEFAULT_TYPES = 3,\n};\n\nenum nl80211_key_attributes {\n\t__NL80211_KEY_INVALID = 0,\n\tNL80211_KEY_DATA = 1,\n\tNL80211_KEY_IDX = 2,\n\tNL80211_KEY_CIPHER = 3,\n\tNL80211_KEY_SEQ = 4,\n\tNL80211_KEY_DEFAULT = 5,\n\tNL80211_KEY_DEFAULT_MGMT = 6,\n\tNL80211_KEY_TYPE = 7,\n\tNL80211_KEY_DEFAULT_TYPES = 8,\n\tNL80211_KEY_MODE = 9,\n\tNL80211_KEY_DEFAULT_BEACON = 10,\n\t__NL80211_KEY_AFTER_LAST = 11,\n\tNL80211_KEY_MAX = 10,\n};\n\nenum nl80211_tx_rate_attributes {\n\t__NL80211_TXRATE_INVALID = 0,\n\tNL80211_TXRATE_LEGACY = 1,\n\tNL80211_TXRATE_HT = 2,\n\tNL80211_TXRATE_VHT = 3,\n\tNL80211_TXRATE_GI = 4,\n\t__NL80211_TXRATE_AFTER_LAST = 5,\n\tNL80211_TXRATE_MAX = 4,\n};\n\nstruct nl80211_txrate_vht {\n\t__u16 mcs[8];\n};\n\nenum nl80211_ps_state {\n\tNL80211_PS_DISABLED = 0,\n\tNL80211_PS_ENABLED = 1,\n};\n\nenum nl80211_attr_cqm {\n\t__NL80211_ATTR_CQM_INVALID = 0,\n\tNL80211_ATTR_CQM_RSSI_THOLD = 1,\n\tNL80211_ATTR_CQM_RSSI_HYST = 2,\n\tNL80211_ATTR_CQM_RSSI_THRESHOLD_EVENT = 3,\n\tNL80211_ATTR_CQM_PKT_LOSS_EVENT = 4,\n\tNL80211_ATTR_CQM_TXE_RATE = 5,\n\tNL80211_ATTR_CQM_TXE_PKTS = 6,\n\tNL80211_ATTR_CQM_TXE_INTVL = 7,\n\tNL80211_ATTR_CQM_BEACON_LOSS_EVENT = 8,\n\tNL80211_ATTR_CQM_RSSI_LEVEL = 9,\n\t__NL80211_ATTR_CQM_AFTER_LAST = 10,\n\tNL80211_ATTR_CQM_MAX = 9,\n};\n\nenum nl80211_cqm_rssi_threshold_event {\n\tNL80211_CQM_RSSI_THRESHOLD_EVENT_LOW = 0,\n\tNL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH = 1,\n\tNL80211_CQM_RSSI_BEACON_LOSS_EVENT = 2,\n};\n\nenum nl80211_tid_config_attr {\n\t__NL80211_TID_CONFIG_ATTR_INVALID = 0,\n\tNL80211_TID_CONFIG_ATTR_PAD = 1,\n\tNL80211_TID_CONFIG_ATTR_VIF_SUPP = 2,\n\tNL80211_TID_CONFIG_ATTR_PEER_SUPP = 3,\n\tNL80211_TID_CONFIG_ATTR_OVERRIDE = 4,\n\tNL80211_TID_CONFIG_ATTR_TIDS = 5,\n\tNL80211_TID_CONFIG_ATTR_NOACK = 6,\n\tNL80211_TID_CONFIG_ATTR_RETRY_SHORT = 7,\n\tNL80211_TID_CONFIG_ATTR_RETRY_LONG = 8,\n\tNL80211_TID_CONFIG_ATTR_AMPDU_CTRL = 9,\n\tNL80211_TID_CONFIG_ATTR_RTSCTS_CTRL = 10,\n\tNL80211_TID_CONFIG_ATTR_AMSDU_CTRL = 11,\n\tNL80211_TID_CONFIG_ATTR_TX_RATE_TYPE = 12,\n\tNL80211_TID_CONFIG_ATTR_TX_RATE = 13,\n\t__NL80211_TID_CONFIG_ATTR_AFTER_LAST = 14,\n\tNL80211_TID_CONFIG_ATTR_MAX = 13,\n};\n\nenum nl80211_packet_pattern_attr {\n\t__NL80211_PKTPAT_INVALID = 0,\n\tNL80211_PKTPAT_MASK = 1,\n\tNL80211_PKTPAT_PATTERN = 2,\n\tNL80211_PKTPAT_OFFSET = 3,\n\tNUM_NL80211_PKTPAT = 4,\n\tMAX_NL80211_PKTPAT = 3,\n};\n\nstruct nl80211_pattern_support {\n\t__u32 max_patterns;\n\t__u32 min_pattern_len;\n\t__u32 max_pattern_len;\n\t__u32 max_pkt_offset;\n};\n\nenum nl80211_wowlan_triggers {\n\t__NL80211_WOWLAN_TRIG_INVALID = 0,\n\tNL80211_WOWLAN_TRIG_ANY = 1,\n\tNL80211_WOWLAN_TRIG_DISCONNECT = 2,\n\tNL80211_WOWLAN_TRIG_MAGIC_PKT = 3,\n\tNL80211_WOWLAN_TRIG_PKT_PATTERN = 4,\n\tNL80211_WOWLAN_TRIG_GTK_REKEY_SUPPORTED = 5,\n\tNL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE = 6,\n\tNL80211_WOWLAN_TRIG_EAP_IDENT_REQUEST = 7,\n\tNL80211_WOWLAN_TRIG_4WAY_HANDSHAKE = 8,\n\tNL80211_WOWLAN_TRIG_RFKILL_RELEASE = 9,\n\tNL80211_WOWLAN_TRIG_WAKEUP_PKT_80211 = 10,\n\tNL80211_WOWLAN_TRIG_WAKEUP_PKT_80211_LEN = 11,\n\tNL80211_WOWLAN_TRIG_WAKEUP_PKT_8023 = 12,\n\tNL80211_WOWLAN_TRIG_WAKEUP_PKT_8023_LEN = 13,\n\tNL80211_WOWLAN_TRIG_TCP_CONNECTION = 14,\n\tNL80211_WOWLAN_TRIG_WAKEUP_TCP_MATCH = 15,\n\tNL80211_WOWLAN_TRIG_WAKEUP_TCP_CONNLOST = 16,\n\tNL80211_WOWLAN_TRIG_WAKEUP_TCP_NOMORETOKENS = 17,\n\tNL80211_WOWLAN_TRIG_NET_DETECT = 18,\n\tNL80211_WOWLAN_TRIG_NET_DETECT_RESULTS = 19,\n\tNUM_NL80211_WOWLAN_TRIG = 20,\n\tMAX_NL80211_WOWLAN_TRIG = 19,\n};\n\nenum nl80211_wowlan_tcp_attrs {\n\t__NL80211_WOWLAN_TCP_INVALID = 0,\n\tNL80211_WOWLAN_TCP_SRC_IPV4 = 1,\n\tNL80211_WOWLAN_TCP_DST_IPV4 = 2,\n\tNL80211_WOWLAN_TCP_DST_MAC = 3,\n\tNL80211_WOWLAN_TCP_SRC_PORT = 4,\n\tNL80211_WOWLAN_TCP_DST_PORT = 5,\n\tNL80211_WOWLAN_TCP_DATA_PAYLOAD = 6,\n\tNL80211_WOWLAN_TCP_DATA_PAYLOAD_SEQ = 7,\n\tNL80211_WOWLAN_TCP_DATA_PAYLOAD_TOKEN = 8,\n\tNL80211_WOWLAN_TCP_DATA_INTERVAL = 9,\n\tNL80211_WOWLAN_TCP_WAKE_PAYLOAD = 10,\n\tNL80211_WOWLAN_TCP_WAKE_MASK = 11,\n\tNUM_NL80211_WOWLAN_TCP = 12,\n\tMAX_NL80211_WOWLAN_TCP = 11,\n};\n\nstruct nl80211_coalesce_rule_support {\n\t__u32 max_rules;\n\tstruct nl80211_pattern_support pat;\n\t__u32 max_delay;\n};\n\nenum nl80211_attr_coalesce_rule {\n\t__NL80211_COALESCE_RULE_INVALID = 0,\n\tNL80211_ATTR_COALESCE_RULE_DELAY = 1,\n\tNL80211_ATTR_COALESCE_RULE_CONDITION = 2,\n\tNL80211_ATTR_COALESCE_RULE_PKT_PATTERN = 3,\n\tNUM_NL80211_ATTR_COALESCE_RULE = 4,\n\tNL80211_ATTR_COALESCE_RULE_MAX = 3,\n};\n\nenum nl80211_iface_limit_attrs {\n\tNL80211_IFACE_LIMIT_UNSPEC = 0,\n\tNL80211_IFACE_LIMIT_MAX = 1,\n\tNL80211_IFACE_LIMIT_TYPES = 2,\n\tNUM_NL80211_IFACE_LIMIT = 3,\n\tMAX_NL80211_IFACE_LIMIT = 2,\n};\n\nenum nl80211_if_combination_attrs {\n\tNL80211_IFACE_COMB_UNSPEC = 0,\n\tNL80211_IFACE_COMB_LIMITS = 1,\n\tNL80211_IFACE_COMB_MAXNUM = 2,\n\tNL80211_IFACE_COMB_STA_AP_BI_MATCH = 3,\n\tNL80211_IFACE_COMB_NUM_CHANNELS = 4,\n\tNL80211_IFACE_COMB_RADAR_DETECT_WIDTHS = 5,\n\tNL80211_IFACE_COMB_RADAR_DETECT_REGIONS = 6,\n\tNL80211_IFACE_COMB_BI_MIN_GCD = 7,\n\tNUM_NL80211_IFACE_COMB = 8,\n\tMAX_NL80211_IFACE_COMB = 7,\n};\n\nenum nl80211_plink_state {\n\tNL80211_PLINK_LISTEN = 0,\n\tNL80211_PLINK_OPN_SNT = 1,\n\tNL80211_PLINK_OPN_RCVD = 2,\n\tNL80211_PLINK_CNF_RCVD = 3,\n\tNL80211_PLINK_ESTAB = 4,\n\tNL80211_PLINK_HOLDING = 5,\n\tNL80211_PLINK_BLOCKED = 6,\n\tNUM_NL80211_PLINK_STATES = 7,\n\tMAX_NL80211_PLINK_STATES = 6,\n};\n\nenum plink_actions {\n\tNL80211_PLINK_ACTION_NO_ACTION = 0,\n\tNL80211_PLINK_ACTION_OPEN = 1,\n\tNL80211_PLINK_ACTION_BLOCK = 2,\n\tNUM_NL80211_PLINK_ACTIONS = 3,\n};\n\nenum nl80211_rekey_data {\n\t__NL80211_REKEY_DATA_INVALID = 0,\n\tNL80211_REKEY_DATA_KEK = 1,\n\tNL80211_REKEY_DATA_KCK = 2,\n\tNL80211_REKEY_DATA_REPLAY_CTR = 3,\n\tNL80211_REKEY_DATA_AKM = 4,\n\tNUM_NL80211_REKEY_DATA = 5,\n\tMAX_NL80211_REKEY_DATA = 4,\n};\n\nenum nl80211_sta_wme_attr {\n\t__NL80211_STA_WME_INVALID = 0,\n\tNL80211_STA_WME_UAPSD_QUEUES = 1,\n\tNL80211_STA_WME_MAX_SP = 2,\n\t__NL80211_STA_WME_AFTER_LAST = 3,\n\tNL80211_STA_WME_MAX = 2,\n};\n\nenum nl80211_pmksa_candidate_attr {\n\t__NL80211_PMKSA_CANDIDATE_INVALID = 0,\n\tNL80211_PMKSA_CANDIDATE_INDEX = 1,\n\tNL80211_PMKSA_CANDIDATE_BSSID = 2,\n\tNL80211_PMKSA_CANDIDATE_PREAUTH = 3,\n\tNUM_NL80211_PMKSA_CANDIDATE = 4,\n\tMAX_NL80211_PMKSA_CANDIDATE = 3,\n};\n\nenum nl80211_connect_failed_reason {\n\tNL80211_CONN_FAIL_MAX_CLIENTS = 0,\n\tNL80211_CONN_FAIL_BLOCKED_CLIENT = 1,\n};\n\nenum nl80211_protocol_features {\n\tNL80211_PROTOCOL_FEATURE_SPLIT_WIPHY_DUMP = 1,\n};\n\nenum nl80211_sched_scan_plan {\n\t__NL80211_SCHED_SCAN_PLAN_INVALID = 0,\n\tNL80211_SCHED_SCAN_PLAN_INTERVAL = 1,\n\tNL80211_SCHED_SCAN_PLAN_ITERATIONS = 2,\n\t__NL80211_SCHED_SCAN_PLAN_AFTER_LAST = 3,\n\tNL80211_SCHED_SCAN_PLAN_MAX = 2,\n};\n\nstruct nl80211_bss_select_rssi_adjust {\n\t__u8 band;\n\t__s8 delta;\n};\n\nenum nl80211_nan_publish_type {\n\tNL80211_NAN_SOLICITED_PUBLISH = 1,\n\tNL80211_NAN_UNSOLICITED_PUBLISH = 2,\n};\n\nenum nl80211_nan_func_term_reason {\n\tNL80211_NAN_FUNC_TERM_REASON_USER_REQUEST = 0,\n\tNL80211_NAN_FUNC_TERM_REASON_TTL_EXPIRED = 1,\n\tNL80211_NAN_FUNC_TERM_REASON_ERROR = 2,\n};\n\nenum nl80211_nan_func_attributes {\n\t__NL80211_NAN_FUNC_INVALID = 0,\n\tNL80211_NAN_FUNC_TYPE = 1,\n\tNL80211_NAN_FUNC_SERVICE_ID = 2,\n\tNL80211_NAN_FUNC_PUBLISH_TYPE = 3,\n\tNL80211_NAN_FUNC_PUBLISH_BCAST = 4,\n\tNL80211_NAN_FUNC_SUBSCRIBE_ACTIVE = 5,\n\tNL80211_NAN_FUNC_FOLLOW_UP_ID = 6,\n\tNL80211_NAN_FUNC_FOLLOW_UP_REQ_ID = 7,\n\tNL80211_NAN_FUNC_FOLLOW_UP_DEST = 8,\n\tNL80211_NAN_FUNC_CLOSE_RANGE = 9,\n\tNL80211_NAN_FUNC_TTL = 10,\n\tNL80211_NAN_FUNC_SERVICE_INFO = 11,\n\tNL80211_NAN_FUNC_SRF = 12,\n\tNL80211_NAN_FUNC_RX_MATCH_FILTER = 13,\n\tNL80211_NAN_FUNC_TX_MATCH_FILTER = 14,\n\tNL80211_NAN_FUNC_INSTANCE_ID = 15,\n\tNL80211_NAN_FUNC_TERM_REASON = 16,\n\tNUM_NL80211_NAN_FUNC_ATTR = 17,\n\tNL80211_NAN_FUNC_ATTR_MAX = 16,\n};\n\nenum nl80211_nan_srf_attributes {\n\t__NL80211_NAN_SRF_INVALID = 0,\n\tNL80211_NAN_SRF_INCLUDE = 1,\n\tNL80211_NAN_SRF_BF = 2,\n\tNL80211_NAN_SRF_BF_IDX = 3,\n\tNL80211_NAN_SRF_MAC_ADDRS = 4,\n\tNUM_NL80211_NAN_SRF_ATTR = 5,\n\tNL80211_NAN_SRF_ATTR_MAX = 4,\n};\n\nenum nl80211_nan_match_attributes {\n\t__NL80211_NAN_MATCH_INVALID = 0,\n\tNL80211_NAN_MATCH_FUNC_LOCAL = 1,\n\tNL80211_NAN_MATCH_FUNC_PEER = 2,\n\tNUM_NL80211_NAN_MATCH_ATTR = 3,\n\tNL80211_NAN_MATCH_ATTR_MAX = 2,\n};\n\nenum nl80211_ftm_responder_attributes {\n\t__NL80211_FTM_RESP_ATTR_INVALID = 0,\n\tNL80211_FTM_RESP_ATTR_ENABLED = 1,\n\tNL80211_FTM_RESP_ATTR_LCI = 2,\n\tNL80211_FTM_RESP_ATTR_CIVICLOC = 3,\n\t__NL80211_FTM_RESP_ATTR_LAST = 4,\n\tNL80211_FTM_RESP_ATTR_MAX = 3,\n};\n\nenum nl80211_ftm_responder_stats {\n\t__NL80211_FTM_STATS_INVALID = 0,\n\tNL80211_FTM_STATS_SUCCESS_NUM = 1,\n\tNL80211_FTM_STATS_PARTIAL_NUM = 2,\n\tNL80211_FTM_STATS_FAILED_NUM = 3,\n\tNL80211_FTM_STATS_ASAP_NUM = 4,\n\tNL80211_FTM_STATS_NON_ASAP_NUM = 5,\n\tNL80211_FTM_STATS_TOTAL_DURATION_MSEC = 6,\n\tNL80211_FTM_STATS_UNKNOWN_TRIGGERS_NUM = 7,\n\tNL80211_FTM_STATS_RESCHEDULE_REQUESTS_NUM = 8,\n\tNL80211_FTM_STATS_OUT_OF_WINDOW_TRIGGERS_NUM = 9,\n\tNL80211_FTM_STATS_PAD = 10,\n\t__NL80211_FTM_STATS_AFTER_LAST = 11,\n\tNL80211_FTM_STATS_MAX = 10,\n};\n\nenum nl80211_peer_measurement_type {\n\tNL80211_PMSR_TYPE_INVALID = 0,\n\tNL80211_PMSR_TYPE_FTM = 1,\n\tNUM_NL80211_PMSR_TYPES = 2,\n\tNL80211_PMSR_TYPE_MAX = 1,\n};\n\nenum nl80211_peer_measurement_req {\n\t__NL80211_PMSR_REQ_ATTR_INVALID = 0,\n\tNL80211_PMSR_REQ_ATTR_DATA = 1,\n\tNL80211_PMSR_REQ_ATTR_GET_AP_TSF = 2,\n\tNUM_NL80211_PMSR_REQ_ATTRS = 3,\n\tNL80211_PMSR_REQ_ATTR_MAX = 2,\n};\n\nenum nl80211_peer_measurement_peer_attrs {\n\t__NL80211_PMSR_PEER_ATTR_INVALID = 0,\n\tNL80211_PMSR_PEER_ATTR_ADDR = 1,\n\tNL80211_PMSR_PEER_ATTR_CHAN = 2,\n\tNL80211_PMSR_PEER_ATTR_REQ = 3,\n\tNL80211_PMSR_PEER_ATTR_RESP = 4,\n\tNUM_NL80211_PMSR_PEER_ATTRS = 5,\n\tNL80211_PMSR_PEER_ATTR_MAX = 4,\n};\n\nenum nl80211_peer_measurement_attrs {\n\t__NL80211_PMSR_ATTR_INVALID = 0,\n\tNL80211_PMSR_ATTR_MAX_PEERS = 1,\n\tNL80211_PMSR_ATTR_REPORT_AP_TSF = 2,\n\tNL80211_PMSR_ATTR_RANDOMIZE_MAC_ADDR = 3,\n\tNL80211_PMSR_ATTR_TYPE_CAPA = 4,\n\tNL80211_PMSR_ATTR_PEERS = 5,\n\tNUM_NL80211_PMSR_ATTR = 6,\n\tNL80211_PMSR_ATTR_MAX = 5,\n};\n\nenum nl80211_peer_measurement_ftm_capa {\n\t__NL80211_PMSR_FTM_CAPA_ATTR_INVALID = 0,\n\tNL80211_PMSR_FTM_CAPA_ATTR_ASAP = 1,\n\tNL80211_PMSR_FTM_CAPA_ATTR_NON_ASAP = 2,\n\tNL80211_PMSR_FTM_CAPA_ATTR_REQ_LCI = 3,\n\tNL80211_PMSR_FTM_CAPA_ATTR_REQ_CIVICLOC = 4,\n\tNL80211_PMSR_FTM_CAPA_ATTR_PREAMBLES = 5,\n\tNL80211_PMSR_FTM_CAPA_ATTR_BANDWIDTHS = 6,\n\tNL80211_PMSR_FTM_CAPA_ATTR_MAX_BURSTS_EXPONENT = 7,\n\tNL80211_PMSR_FTM_CAPA_ATTR_MAX_FTMS_PER_BURST = 8,\n\tNL80211_PMSR_FTM_CAPA_ATTR_TRIGGER_BASED = 9,\n\tNL80211_PMSR_FTM_CAPA_ATTR_NON_TRIGGER_BASED = 10,\n\tNUM_NL80211_PMSR_FTM_CAPA_ATTR = 11,\n\tNL80211_PMSR_FTM_CAPA_ATTR_MAX = 10,\n};\n\nenum nl80211_peer_measurement_ftm_req {\n\t__NL80211_PMSR_FTM_REQ_ATTR_INVALID = 0,\n\tNL80211_PMSR_FTM_REQ_ATTR_ASAP = 1,\n\tNL80211_PMSR_FTM_REQ_ATTR_PREAMBLE = 2,\n\tNL80211_PMSR_FTM_REQ_ATTR_NUM_BURSTS_EXP = 3,\n\tNL80211_PMSR_FTM_REQ_ATTR_BURST_PERIOD = 4,\n\tNL80211_PMSR_FTM_REQ_ATTR_BURST_DURATION = 5,\n\tNL80211_PMSR_FTM_REQ_ATTR_FTMS_PER_BURST = 6,\n\tNL80211_PMSR_FTM_REQ_ATTR_NUM_FTMR_RETRIES = 7,\n\tNL80211_PMSR_FTM_REQ_ATTR_REQUEST_LCI = 8,\n\tNL80211_PMSR_FTM_REQ_ATTR_REQUEST_CIVICLOC = 9,\n\tNL80211_PMSR_FTM_REQ_ATTR_TRIGGER_BASED = 10,\n\tNL80211_PMSR_FTM_REQ_ATTR_NON_TRIGGER_BASED = 11,\n\tNUM_NL80211_PMSR_FTM_REQ_ATTR = 12,\n\tNL80211_PMSR_FTM_REQ_ATTR_MAX = 11,\n};\n\nenum nl80211_obss_pd_attributes {\n\t__NL80211_HE_OBSS_PD_ATTR_INVALID = 0,\n\tNL80211_HE_OBSS_PD_ATTR_MIN_OFFSET = 1,\n\tNL80211_HE_OBSS_PD_ATTR_MAX_OFFSET = 2,\n\t__NL80211_HE_OBSS_PD_ATTR_LAST = 3,\n\tNL80211_HE_OBSS_PD_ATTR_MAX = 2,\n};\n\nenum nl80211_bss_color_attributes {\n\t__NL80211_HE_BSS_COLOR_ATTR_INVALID = 0,\n\tNL80211_HE_BSS_COLOR_ATTR_COLOR = 1,\n\tNL80211_HE_BSS_COLOR_ATTR_DISABLED = 2,\n\tNL80211_HE_BSS_COLOR_ATTR_PARTIAL = 3,\n\t__NL80211_HE_BSS_COLOR_ATTR_LAST = 4,\n\tNL80211_HE_BSS_COLOR_ATTR_MAX = 3,\n};\n\nenum nl80211_iftype_akm_attributes {\n\t__NL80211_IFTYPE_AKM_ATTR_INVALID = 0,\n\tNL80211_IFTYPE_AKM_ATTR_IFTYPES = 1,\n\tNL80211_IFTYPE_AKM_ATTR_SUITES = 2,\n\t__NL80211_IFTYPE_AKM_ATTR_LAST = 3,\n\tNL80211_IFTYPE_AKM_ATTR_MAX = 2,\n};\n\nenum survey_info_flags {\n\tSURVEY_INFO_NOISE_DBM = 1,\n\tSURVEY_INFO_IN_USE = 2,\n\tSURVEY_INFO_TIME = 4,\n\tSURVEY_INFO_TIME_BUSY = 8,\n\tSURVEY_INFO_TIME_EXT_BUSY = 16,\n\tSURVEY_INFO_TIME_RX = 32,\n\tSURVEY_INFO_TIME_TX = 64,\n\tSURVEY_INFO_TIME_SCAN = 128,\n\tSURVEY_INFO_TIME_BSS_RX = 256,\n};\n\nenum cfg80211_ap_settings_flags {\n\tAP_SETTINGS_EXTERNAL_AUTH_SUPPORT = 1,\n};\n\nenum station_parameters_apply_mask {\n\tSTATION_PARAM_APPLY_UAPSD = 1,\n\tSTATION_PARAM_APPLY_CAPABILITY = 2,\n\tSTATION_PARAM_APPLY_PLINK_STATE = 4,\n\tSTATION_PARAM_APPLY_STA_TXPOWER = 8,\n};\n\nenum cfg80211_station_type {\n\tCFG80211_STA_AP_CLIENT = 0,\n\tCFG80211_STA_AP_CLIENT_UNASSOC = 1,\n\tCFG80211_STA_AP_MLME_CLIENT = 2,\n\tCFG80211_STA_AP_STA = 3,\n\tCFG80211_STA_IBSS = 4,\n\tCFG80211_STA_TDLS_PEER_SETUP = 5,\n\tCFG80211_STA_TDLS_PEER_ACTIVE = 6,\n\tCFG80211_STA_MESH_PEER_KERNEL = 7,\n\tCFG80211_STA_MESH_PEER_USER = 8,\n};\n\nenum bss_param_flags {\n\tBSS_PARAM_FLAGS_CTS_PROT = 1,\n\tBSS_PARAM_FLAGS_SHORT_PREAMBLE = 2,\n\tBSS_PARAM_FLAGS_SHORT_SLOT_TIME = 4,\n};\n\nenum monitor_flags {\n\tMONITOR_FLAG_CHANGED = 1,\n\tMONITOR_FLAG_FCSFAIL = 2,\n\tMONITOR_FLAG_PLCPFAIL = 4,\n\tMONITOR_FLAG_CONTROL = 8,\n\tMONITOR_FLAG_OTHER_BSS = 16,\n\tMONITOR_FLAG_COOK_FRAMES = 32,\n\tMONITOR_FLAG_ACTIVE = 64,\n};\n\nenum mpath_info_flags {\n\tMPATH_INFO_FRAME_QLEN = 1,\n\tMPATH_INFO_SN = 2,\n\tMPATH_INFO_METRIC = 4,\n\tMPATH_INFO_EXPTIME = 8,\n\tMPATH_INFO_DISCOVERY_TIMEOUT = 16,\n\tMPATH_INFO_DISCOVERY_RETRIES = 32,\n\tMPATH_INFO_FLAGS = 64,\n\tMPATH_INFO_HOP_COUNT = 128,\n\tMPATH_INFO_PATH_CHANGE = 256,\n};\n\nenum cfg80211_assoc_req_flags {\n\tASSOC_REQ_DISABLE_HT = 1,\n\tASSOC_REQ_DISABLE_VHT = 2,\n\tASSOC_REQ_USE_RRM = 4,\n\tCONNECT_REQ_EXTERNAL_AUTH_SUPPORT = 8,\n};\n\nenum cfg80211_connect_params_changed {\n\tUPDATE_ASSOC_IES = 1,\n\tUPDATE_FILS_ERP_INFO = 2,\n\tUPDATE_AUTH_TYPE = 4,\n};\n\nenum wiphy_params_flags {\n\tWIPHY_PARAM_RETRY_SHORT = 1,\n\tWIPHY_PARAM_RETRY_LONG = 2,\n\tWIPHY_PARAM_FRAG_THRESHOLD = 4,\n\tWIPHY_PARAM_RTS_THRESHOLD = 8,\n\tWIPHY_PARAM_COVERAGE_CLASS = 16,\n\tWIPHY_PARAM_DYN_ACK = 32,\n\tWIPHY_PARAM_TXQ_LIMIT = 64,\n\tWIPHY_PARAM_TXQ_MEMORY_LIMIT = 128,\n\tWIPHY_PARAM_TXQ_QUANTUM = 256,\n};\n\nstruct cfg80211_wowlan_nd_match {\n\tstruct cfg80211_ssid ssid;\n\tint n_channels;\n\tu32 channels[0];\n};\n\nstruct cfg80211_wowlan_nd_info {\n\tint n_matches;\n\tstruct cfg80211_wowlan_nd_match *matches[0];\n};\n\nstruct cfg80211_wowlan_wakeup {\n\tbool disconnect;\n\tbool magic_pkt;\n\tbool gtk_rekey_failure;\n\tbool eap_identity_req;\n\tbool four_way_handshake;\n\tbool rfkill_release;\n\tbool packet_80211;\n\tbool tcp_match;\n\tbool tcp_connlost;\n\tbool tcp_nomoretokens;\n\ts32 pattern_idx;\n\tu32 packet_present_len;\n\tu32 packet_len;\n\tconst void *packet;\n\tstruct cfg80211_wowlan_nd_info *net_detect;\n};\n\nenum cfg80211_nan_conf_changes {\n\tCFG80211_NAN_CONF_CHANGED_PREF = 1,\n\tCFG80211_NAN_CONF_CHANGED_BANDS = 2,\n};\n\nenum wiphy_vendor_command_flags {\n\tWIPHY_VENDOR_CMD_NEED_WDEV = 1,\n\tWIPHY_VENDOR_CMD_NEED_NETDEV = 2,\n\tWIPHY_VENDOR_CMD_NEED_RUNNING = 4,\n};\n\nenum wiphy_opmode_flag {\n\tSTA_OPMODE_MAX_BW_CHANGED = 1,\n\tSTA_OPMODE_SMPS_MODE_CHANGED = 2,\n\tSTA_OPMODE_N_SS_CHANGED = 4,\n};\n\nstruct sta_opmode_info {\n\tu32 changed;\n\tenum nl80211_smps_mode smps_mode;\n\tenum nl80211_chan_width bw;\n\tu8 rx_nss;\n};\n\nstruct cfg80211_ft_event_params {\n\tconst u8 *ies;\n\tsize_t ies_len;\n\tconst u8 *target_ap;\n\tconst u8 *ric_ies;\n\tsize_t ric_ies_len;\n};\n\nstruct cfg80211_nan_match_params {\n\tenum nl80211_nan_function_type type;\n\tu8 inst_id;\n\tu8 peer_inst_id;\n\tconst u8 *addr;\n\tu8 info_len;\n\tconst u8 *info;\n\tu64 cookie;\n};\n\nenum nl80211_multicast_groups {\n\tNL80211_MCGRP_CONFIG = 0,\n\tNL80211_MCGRP_SCAN = 1,\n\tNL80211_MCGRP_REGULATORY = 2,\n\tNL80211_MCGRP_MLME = 3,\n\tNL80211_MCGRP_VENDOR = 4,\n\tNL80211_MCGRP_NAN = 5,\n\tNL80211_MCGRP_TESTMODE = 6,\n};\n\nstruct key_parse {\n\tstruct key_params p;\n\tint idx;\n\tint type;\n\tbool def;\n\tbool defmgmt;\n\tbool defbeacon;\n\tbool def_uni;\n\tbool def_multi;\n};\n\nstruct nl80211_dump_wiphy_state {\n\ts64 filter_wiphy;\n\tlong int start;\n\tlong int split_start;\n\tlong int band_start;\n\tlong int chan_start;\n\tlong int capa_start;\n\tbool split;\n};\n\nstruct get_key_cookie {\n\tstruct sk_buff *msg;\n\tint error;\n\tint idx;\n};\n\nenum ieee80211_category {\n\tWLAN_CATEGORY_SPECTRUM_MGMT = 0,\n\tWLAN_CATEGORY_QOS = 1,\n\tWLAN_CATEGORY_DLS = 2,\n\tWLAN_CATEGORY_BACK = 3,\n\tWLAN_CATEGORY_PUBLIC = 4,\n\tWLAN_CATEGORY_RADIO_MEASUREMENT = 5,\n\tWLAN_CATEGORY_HT = 7,\n\tWLAN_CATEGORY_SA_QUERY = 8,\n\tWLAN_CATEGORY_PROTECTED_DUAL_OF_ACTION = 9,\n\tWLAN_CATEGORY_WNM = 10,\n\tWLAN_CATEGORY_WNM_UNPROTECTED = 11,\n\tWLAN_CATEGORY_TDLS = 12,\n\tWLAN_CATEGORY_MESH_ACTION = 13,\n\tWLAN_CATEGORY_MULTIHOP_ACTION = 14,\n\tWLAN_CATEGORY_SELF_PROTECTED = 15,\n\tWLAN_CATEGORY_DMG = 16,\n\tWLAN_CATEGORY_WMM = 17,\n\tWLAN_CATEGORY_FST = 18,\n\tWLAN_CATEGORY_UNPROT_DMG = 20,\n\tWLAN_CATEGORY_VHT = 21,\n\tWLAN_CATEGORY_VENDOR_SPECIFIC_PROTECTED = 126,\n\tWLAN_CATEGORY_VENDOR_SPECIFIC = 127,\n};\n\nstruct cfg80211_mgmt_registration {\n\tstruct list_head list;\n\tstruct wireless_dev *wdev;\n\tu32 nlportid;\n\tint match_len;\n\t__le16 frame_type;\n\tbool multicast_rx;\n\tu8 match[0];\n};\n\nstruct cfg80211_conn {\n\tstruct cfg80211_connect_params params;\n\tenum {\n\t\tCFG80211_CONN_SCANNING = 0,\n\t\tCFG80211_CONN_SCAN_AGAIN = 1,\n\t\tCFG80211_CONN_AUTHENTICATE_NEXT = 2,\n\t\tCFG80211_CONN_AUTHENTICATING = 3,\n\t\tCFG80211_CONN_AUTH_FAILED_TIMEOUT = 4,\n\t\tCFG80211_CONN_ASSOCIATE_NEXT = 5,\n\t\tCFG80211_CONN_ASSOCIATING = 6,\n\t\tCFG80211_CONN_ASSOC_FAILED = 7,\n\t\tCFG80211_CONN_ASSOC_FAILED_TIMEOUT = 8,\n\t\tCFG80211_CONN_DEAUTH = 9,\n\t\tCFG80211_CONN_ABANDON = 10,\n\t\tCFG80211_CONN_CONNECTED = 11,\n\t} state;\n\tu8 bssid[6];\n\tu8 prev_bssid[6];\n\tconst u8 *ie;\n\tsize_t ie_len;\n\tbool auto_auth;\n\tbool prev_bssid_valid;\n};\n\nenum cfg80211_chan_mode {\n\tCHAN_MODE_UNDEFINED = 0,\n\tCHAN_MODE_SHARED = 1,\n\tCHAN_MODE_EXCLUSIVE = 2,\n};\n\nstruct trace_event_raw_rdev_suspend {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tbool any;\n\tbool disconnect;\n\tbool magic_pkt;\n\tbool gtk_rekey_failure;\n\tbool eap_identity_req;\n\tbool four_way_handshake;\n\tbool rfkill_release;\n\tbool valid_wow;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_scan {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_only_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_enabled_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tbool enabled;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_add_virtual_intf {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 __data_loc_vir_intf_name;\n\tenum nl80211_iftype type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_wdev_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_wdev_cookie_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu64 cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_change_virtual_intf {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_iftype type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_key_handle {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 mac_addr[6];\n\tu8 key_index;\n\tbool pairwise;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_add_key {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 mac_addr[6];\n\tu8 key_index;\n\tbool pairwise;\n\tu8 mode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_default_key {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 key_index;\n\tbool unicast;\n\tbool multicast;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_default_mgmt_key {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 key_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_default_beacon_key {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 key_index;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_start_ap {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tint beacon_interval;\n\tint dtim_period;\n\tchar ssid[33];\n\tenum nl80211_hidden_ssid hidden_ssid;\n\tu32 wpa_ver;\n\tbool privacy;\n\tenum nl80211_auth_type auth_type;\n\tint inactivity_timeout;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_change_beacon {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu32 __data_loc_head;\n\tu32 __data_loc_tail;\n\tu32 __data_loc_beacon_ies;\n\tu32 __data_loc_proberesp_ies;\n\tu32 __data_loc_assocresp_ies;\n\tu32 __data_loc_probe_resp;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_netdev_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_station_add_change {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 sta_mac[6];\n\tu32 sta_flags_mask;\n\tu32 sta_flags_set;\n\tu32 sta_modify_mask;\n\tint listen_interval;\n\tu16 capability;\n\tu16 aid;\n\tu8 plink_action;\n\tu8 plink_state;\n\tu8 uapsd_queues;\n\tu8 max_sp;\n\tu8 opmode_notif;\n\tbool opmode_notif_used;\n\tu8 ht_capa[26];\n\tu8 vht_capa[12];\n\tchar vlan[16];\n\tu32 __data_loc_supported_rates;\n\tu32 __data_loc_ext_capab;\n\tu32 __data_loc_supported_channels;\n\tu32 __data_loc_supported_oper_classes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_netdev_mac_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 sta_mac[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_station_del {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 sta_mac[6];\n\tu8 subtype;\n\tu16 reason_code;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_dump_station {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 sta_mac[6];\n\tint idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int_station_info {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tint generation;\n\tu32 connected_time;\n\tu32 inactive_time;\n\tu32 rx_bytes;\n\tu32 tx_bytes;\n\tu32 rx_packets;\n\tu32 tx_packets;\n\tu32 tx_retries;\n\tu32 tx_failed;\n\tu32 rx_dropped_misc;\n\tu32 beacon_loss_count;\n\tu16 llid;\n\tu16 plid;\n\tu8 plink_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_mpath_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 dst[6];\n\tu8 next_hop[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_dump_mpath {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 dst[6];\n\tu8 next_hop[6];\n\tint idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_get_mpp {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 dst[6];\n\tu8 mpp[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_dump_mpp {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 dst[6];\n\tu8 mpp[6];\n\tint idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int_mpath_info {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tint generation;\n\tu32 filled;\n\tu32 frame_qlen;\n\tu32 sn;\n\tu32 metric;\n\tu32 exptime;\n\tu32 discovery_timeout;\n\tu8 discovery_retries;\n\tu8 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int_mesh_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu16 dot11MeshRetryTimeout;\n\tu16 dot11MeshConfirmTimeout;\n\tu16 dot11MeshHoldingTimeout;\n\tu16 dot11MeshMaxPeerLinks;\n\tu8 dot11MeshMaxRetries;\n\tu8 dot11MeshTTL;\n\tu8 element_ttl;\n\tbool auto_open_plinks;\n\tu32 dot11MeshNbrOffsetMaxNeighbor;\n\tu8 dot11MeshHWMPmaxPREQretries;\n\tu32 path_refresh_time;\n\tu32 dot11MeshHWMPactivePathTimeout;\n\tu16 min_discovery_timeout;\n\tu16 dot11MeshHWMPpreqMinInterval;\n\tu16 dot11MeshHWMPperrMinInterval;\n\tu16 dot11MeshHWMPnetDiameterTraversalTime;\n\tu8 dot11MeshHWMPRootMode;\n\tu16 dot11MeshHWMPRannInterval;\n\tbool dot11MeshGateAnnouncementProtocol;\n\tbool dot11MeshForwarding;\n\ts32 rssi_threshold;\n\tu16 ht_opmode;\n\tu32 dot11MeshHWMPactivePathToRootTimeout;\n\tu16 dot11MeshHWMProotInterval;\n\tu16 dot11MeshHWMPconfirmationInterval;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_update_mesh_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu16 dot11MeshRetryTimeout;\n\tu16 dot11MeshConfirmTimeout;\n\tu16 dot11MeshHoldingTimeout;\n\tu16 dot11MeshMaxPeerLinks;\n\tu8 dot11MeshMaxRetries;\n\tu8 dot11MeshTTL;\n\tu8 element_ttl;\n\tbool auto_open_plinks;\n\tu32 dot11MeshNbrOffsetMaxNeighbor;\n\tu8 dot11MeshHWMPmaxPREQretries;\n\tu32 path_refresh_time;\n\tu32 dot11MeshHWMPactivePathTimeout;\n\tu16 min_discovery_timeout;\n\tu16 dot11MeshHWMPpreqMinInterval;\n\tu16 dot11MeshHWMPperrMinInterval;\n\tu16 dot11MeshHWMPnetDiameterTraversalTime;\n\tu8 dot11MeshHWMPRootMode;\n\tu16 dot11MeshHWMPRannInterval;\n\tbool dot11MeshGateAnnouncementProtocol;\n\tbool dot11MeshForwarding;\n\ts32 rssi_threshold;\n\tu16 ht_opmode;\n\tu32 dot11MeshHWMPactivePathToRootTimeout;\n\tu16 dot11MeshHWMProotInterval;\n\tu16 dot11MeshHWMPconfirmationInterval;\n\tu32 mask;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_join_mesh {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu16 dot11MeshRetryTimeout;\n\tu16 dot11MeshConfirmTimeout;\n\tu16 dot11MeshHoldingTimeout;\n\tu16 dot11MeshMaxPeerLinks;\n\tu8 dot11MeshMaxRetries;\n\tu8 dot11MeshTTL;\n\tu8 element_ttl;\n\tbool auto_open_plinks;\n\tu32 dot11MeshNbrOffsetMaxNeighbor;\n\tu8 dot11MeshHWMPmaxPREQretries;\n\tu32 path_refresh_time;\n\tu32 dot11MeshHWMPactivePathTimeout;\n\tu16 min_discovery_timeout;\n\tu16 dot11MeshHWMPpreqMinInterval;\n\tu16 dot11MeshHWMPperrMinInterval;\n\tu16 dot11MeshHWMPnetDiameterTraversalTime;\n\tu8 dot11MeshHWMPRootMode;\n\tu16 dot11MeshHWMPRannInterval;\n\tbool dot11MeshGateAnnouncementProtocol;\n\tbool dot11MeshForwarding;\n\ts32 rssi_threshold;\n\tu16 ht_opmode;\n\tu32 dot11MeshHWMPactivePathToRootTimeout;\n\tu16 dot11MeshHWMProotInterval;\n\tu16 dot11MeshHWMPconfirmationInterval;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_change_bss {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tint use_cts_prot;\n\tint use_short_preamble;\n\tint use_short_slot_time;\n\tint ap_isolate;\n\tint ht_opmode;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_txq_params {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_ac ac;\n\tu16 txop;\n\tu16 cwmin;\n\tu16 cwmax;\n\tu8 aifs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_libertas_set_mesh_channel {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_monitor_channel {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_auth {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tenum nl80211_auth_type auth_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_assoc {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tu8 prev_bssid[6];\n\tbool use_mfp;\n\tu32 flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_deauth {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tu16 reason_code;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_disassoc {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tu16 reason_code;\n\tbool local_state_change;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_mgmt_tx_cancel_wait {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu64 cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_power_mgmt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tbool enabled;\n\tint timeout;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_connect {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tchar ssid[33];\n\tenum nl80211_auth_type auth_type;\n\tbool privacy;\n\tu32 wpa_versions;\n\tu32 flags;\n\tu8 prev_bssid[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_update_connect_params {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu32 changed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_cqm_rssi_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\ts32 rssi_thold;\n\tu32 rssi_hyst;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_cqm_rssi_range_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\ts32 rssi_low;\n\ts32 rssi_high;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_cqm_txe_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu32 rate;\n\tu32 pkts;\n\tu32 intvl;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_disconnect {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu16 reason_code;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_join_ibss {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tchar ssid[33];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_join_ocb {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_wiphy_params {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 changed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_tx_power {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tenum nl80211_tx_power_setting type;\n\tint mbm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int_int {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint func_ret;\n\tint func_fill;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_bitrate_mask {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_update_mgmt_frame_registrations {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu16 global_stypes;\n\tu16 interface_stypes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int_tx_rx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tu32 tx;\n\tu32 rx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_void_tx_rx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 tx;\n\tu32 tx_max;\n\tu32 rx;\n\tu32 rx_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_tx_rx_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 tx;\n\tu32 rx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_netdev_id_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu64 id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_tdls_mgmt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tu8 action_code;\n\tu8 dialog_token;\n\tu16 status_code;\n\tu32 peer_capability;\n\tbool initiator;\n\tu32 __data_loc_buf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_dump_survey {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tint idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int_survey_info {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tint ret;\n\tu64 time;\n\tu64 time_busy;\n\tu64 time_ext_busy;\n\tu64 time_rx;\n\tu64 time_tx;\n\tu64 time_scan;\n\tu32 filled;\n\ts8 noise;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_tdls_oper {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tenum nl80211_tdls_operation oper;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_pmksa {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_probe_client {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_remain_on_channel {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tunsigned int duration;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_int_cookie {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tu64 cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_cancel_remain_on_channel {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu64 cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_mgmt_tx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tbool offchan;\n\tunsigned int wait;\n\tbool no_cck;\n\tbool dont_wait_for_ack;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_tx_control_port {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 dest[6];\n\t__be16 proto;\n\tbool unencrypted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_noack_map {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu16 noack_map;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_return_chandef {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_start_nan {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu8 master_pref;\n\tu8 bands;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_nan_change_conf {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu8 master_pref;\n\tu8 bands;\n\tu32 changes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_add_nan_func {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu8 func_type;\n\tu64 cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_del_nan_func {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu64 cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_mac_acl {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu32 acl_policy;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_update_ft_ies {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu16 md;\n\tu32 __data_loc_ie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_crit_proto_start {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu16 proto;\n\tu16 duration;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_crit_proto_stop {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_channel_switch {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tbool radar_required;\n\tbool block_tx;\n\tu8 count;\n\tu32 __data_loc_bcn_ofs;\n\tu32 __data_loc_pres_ofs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_qos_map {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 num_des;\n\tu8 dscp_exception[42];\n\tu8 up[16];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_ap_chanwidth {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_add_tx_ts {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tu8 tsid;\n\tu8 user_prio;\n\tu16 admitted_time;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_del_tx_ts {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tu8 tsid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_tdls_channel_switch {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 addr[6];\n\tu8 oper_class;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_tdls_cancel_channel_switch {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_pmk {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 aa[6];\n\tu8 pmk_len;\n\tu8 pmk_r0_name_len;\n\tu32 __data_loc_pmk;\n\tu32 __data_loc_pmk_r0_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_del_pmk {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 aa[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_external_auth {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tu8 ssid[33];\n\tu16 status;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_start_radar_detection {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu32 cac_time_ms;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_mcast_rate {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tint mcast_rate[4];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_coalesce {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint n_rules;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_multicast_to_unicast {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tbool enabled;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_get_ftm_responder_stats {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu64 timestamp;\n\tu32 success_num;\n\tu32 partial_num;\n\tu32 failed_num;\n\tu32 asap_num;\n\tu32 non_asap_num;\n\tu64 duration;\n\tu32 unknown_triggers;\n\tu32 reschedule;\n\tu32 out_of_window;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_return_bool {\n\tstruct trace_entry ent;\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_netdev_mac_evt {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 macaddr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netdev_evt_only {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_send_rx_assoc {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netdev_frame_event {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu32 __data_loc_frame;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_tx_mlme_mgmt {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu32 __data_loc_frame;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_netdev_mac_evt {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 mac[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_michael_mic_failure {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 addr[6];\n\tenum nl80211_key_type key_type;\n\tint key_id;\n\tu8 tsc[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_ready_on_channel {\n\tstruct trace_entry ent;\n\tu32 id;\n\tu64 cookie;\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tunsigned int duration;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_ready_on_channel_expired {\n\tstruct trace_entry ent;\n\tu32 id;\n\tu64 cookie;\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_tx_mgmt_expired {\n\tstruct trace_entry ent;\n\tu32 id;\n\tu64 cookie;\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_new_sta {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 mac_addr[6];\n\tint generation;\n\tu32 connected_time;\n\tu32 inactive_time;\n\tu32 rx_bytes;\n\tu32 tx_bytes;\n\tu32 rx_packets;\n\tu32 tx_packets;\n\tu32 tx_retries;\n\tu32 tx_failed;\n\tu32 rx_dropped_misc;\n\tu32 beacon_loss_count;\n\tu16 llid;\n\tu16 plid;\n\tu8 plink_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_rx_mgmt {\n\tstruct trace_entry ent;\n\tu32 id;\n\tint freq;\n\tint sig_dbm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_mgmt_tx_status {\n\tstruct trace_entry ent;\n\tu32 id;\n\tu64 cookie;\n\tbool ack;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_control_port_tx_status {\n\tstruct trace_entry ent;\n\tu32 id;\n\tu64 cookie;\n\tbool ack;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_rx_control_port {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tint len;\n\tu8 from[6];\n\tu16 proto;\n\tbool unencrypted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_cqm_rssi_notify {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_cqm_rssi_threshold_event rssi_event;\n\ts32 rssi_level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_reg_can_beacon {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tenum nl80211_iftype iftype;\n\tbool check_no_ir;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_chandef_dfs_required {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_ch_switch_notify {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_ch_switch_started_notify {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_radar_event {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_band band;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_cac_event {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tenum nl80211_radar_event evt;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_rx_evt {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_ibss_joined {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 bssid[6];\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_probe_status {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 addr[6];\n\tu64 cookie;\n\tbool acked;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_cqm_pktloss_notify {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tu32 num_packets;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_pmksa_candidate_notify {\n\tstruct trace_entry ent;\n\tchar name[16];\n\tint ifindex;\n\tint index;\n\tu8 bssid[6];\n\tbool preauth;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_report_obss_beacon {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint freq;\n\tint sig_dbm;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_tdls_oper_request {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tenum nl80211_tdls_operation oper;\n\tu16 reason_code;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_scan_done {\n\tstruct trace_entry ent;\n\tu32 n_channels;\n\tu32 __data_loc_ie;\n\tu32 rates[4];\n\tu32 wdev_id;\n\tu8 wiphy_mac[6];\n\tbool no_cck;\n\tbool aborted;\n\tu64 scan_start_tsf;\n\tu8 tsf_bssid[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wiphy_id_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu64 id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_get_bss {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tu8 bssid[6];\n\tu32 __data_loc_ssid;\n\tenum ieee80211_bss_type bss_type;\n\tenum ieee80211_privacy privacy;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_inform_bss_frame {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tenum nl80211_bss_scan_width scan_width;\n\tu32 __data_loc_mgmt;\n\ts32 signal;\n\tu64 ts_boottime;\n\tu64 parent_tsf;\n\tu8 parent_bssid[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_bss_evt {\n\tstruct trace_entry ent;\n\tu8 bssid[6];\n\tenum nl80211_band band;\n\tu32 center_freq;\n\tu16 freq_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_return_uint {\n\tstruct trace_entry ent;\n\tunsigned int ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_return_u32 {\n\tstruct trace_entry ent;\n\tu32 ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_report_wowlan_wakeup {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tbool non_wireless;\n\tbool disconnect;\n\tbool magic_pkt;\n\tbool gtk_rekey_failure;\n\tbool eap_identity_req;\n\tbool four_way_handshake;\n\tbool rfkill_release;\n\ts32 pattern_idx;\n\tu32 packet_len;\n\tu32 __data_loc_packet;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_ft_event {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu32 __data_loc_ies;\n\tu8 target_ap[6];\n\tu32 __data_loc_ric_ies;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_stop_iface {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_pmsr_report {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu64 cookie;\n\tu8 addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_pmsr_complete {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 id;\n\tu64 cookie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_update_owe_info {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tu16 status;\n\tu32 __data_loc_ie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_cfg80211_update_owe_info_event {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tu32 __data_loc_ie;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_probe_mesh_link {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 dest[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_set_tid_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_rdev_reset_tid_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar name[16];\n\tint ifindex;\n\tu8 peer[6];\n\tu8 tids;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_rdev_suspend {};\n\nstruct trace_event_data_offsets_rdev_return_int {};\n\nstruct trace_event_data_offsets_rdev_scan {};\n\nstruct trace_event_data_offsets_wiphy_only_evt {};\n\nstruct trace_event_data_offsets_wiphy_enabled_evt {};\n\nstruct trace_event_data_offsets_rdev_add_virtual_intf {\n\tu32 vir_intf_name;\n};\n\nstruct trace_event_data_offsets_wiphy_wdev_evt {};\n\nstruct trace_event_data_offsets_wiphy_wdev_cookie_evt {};\n\nstruct trace_event_data_offsets_rdev_change_virtual_intf {};\n\nstruct trace_event_data_offsets_key_handle {};\n\nstruct trace_event_data_offsets_rdev_add_key {};\n\nstruct trace_event_data_offsets_rdev_set_default_key {};\n\nstruct trace_event_data_offsets_rdev_set_default_mgmt_key {};\n\nstruct trace_event_data_offsets_rdev_set_default_beacon_key {};\n\nstruct trace_event_data_offsets_rdev_start_ap {};\n\nstruct trace_event_data_offsets_rdev_change_beacon {\n\tu32 head;\n\tu32 tail;\n\tu32 beacon_ies;\n\tu32 proberesp_ies;\n\tu32 assocresp_ies;\n\tu32 probe_resp;\n};\n\nstruct trace_event_data_offsets_wiphy_netdev_evt {};\n\nstruct trace_event_data_offsets_station_add_change {\n\tu32 supported_rates;\n\tu32 ext_capab;\n\tu32 supported_channels;\n\tu32 supported_oper_classes;\n};\n\nstruct trace_event_data_offsets_wiphy_netdev_mac_evt {};\n\nstruct trace_event_data_offsets_station_del {};\n\nstruct trace_event_data_offsets_rdev_dump_station {};\n\nstruct trace_event_data_offsets_rdev_return_int_station_info {};\n\nstruct trace_event_data_offsets_mpath_evt {};\n\nstruct trace_event_data_offsets_rdev_dump_mpath {};\n\nstruct trace_event_data_offsets_rdev_get_mpp {};\n\nstruct trace_event_data_offsets_rdev_dump_mpp {};\n\nstruct trace_event_data_offsets_rdev_return_int_mpath_info {};\n\nstruct trace_event_data_offsets_rdev_return_int_mesh_config {};\n\nstruct trace_event_data_offsets_rdev_update_mesh_config {};\n\nstruct trace_event_data_offsets_rdev_join_mesh {};\n\nstruct trace_event_data_offsets_rdev_change_bss {};\n\nstruct trace_event_data_offsets_rdev_set_txq_params {};\n\nstruct trace_event_data_offsets_rdev_libertas_set_mesh_channel {};\n\nstruct trace_event_data_offsets_rdev_set_monitor_channel {};\n\nstruct trace_event_data_offsets_rdev_auth {};\n\nstruct trace_event_data_offsets_rdev_assoc {};\n\nstruct trace_event_data_offsets_rdev_deauth {};\n\nstruct trace_event_data_offsets_rdev_disassoc {};\n\nstruct trace_event_data_offsets_rdev_mgmt_tx_cancel_wait {};\n\nstruct trace_event_data_offsets_rdev_set_power_mgmt {};\n\nstruct trace_event_data_offsets_rdev_connect {};\n\nstruct trace_event_data_offsets_rdev_update_connect_params {};\n\nstruct trace_event_data_offsets_rdev_set_cqm_rssi_config {};\n\nstruct trace_event_data_offsets_rdev_set_cqm_rssi_range_config {};\n\nstruct trace_event_data_offsets_rdev_set_cqm_txe_config {};\n\nstruct trace_event_data_offsets_rdev_disconnect {};\n\nstruct trace_event_data_offsets_rdev_join_ibss {};\n\nstruct trace_event_data_offsets_rdev_join_ocb {};\n\nstruct trace_event_data_offsets_rdev_set_wiphy_params {};\n\nstruct trace_event_data_offsets_rdev_set_tx_power {};\n\nstruct trace_event_data_offsets_rdev_return_int_int {};\n\nstruct trace_event_data_offsets_rdev_set_bitrate_mask {};\n\nstruct trace_event_data_offsets_rdev_update_mgmt_frame_registrations {};\n\nstruct trace_event_data_offsets_rdev_return_int_tx_rx {};\n\nstruct trace_event_data_offsets_rdev_return_void_tx_rx {};\n\nstruct trace_event_data_offsets_tx_rx_evt {};\n\nstruct trace_event_data_offsets_wiphy_netdev_id_evt {};\n\nstruct trace_event_data_offsets_rdev_tdls_mgmt {\n\tu32 buf;\n};\n\nstruct trace_event_data_offsets_rdev_dump_survey {};\n\nstruct trace_event_data_offsets_rdev_return_int_survey_info {};\n\nstruct trace_event_data_offsets_rdev_tdls_oper {};\n\nstruct trace_event_data_offsets_rdev_pmksa {};\n\nstruct trace_event_data_offsets_rdev_probe_client {};\n\nstruct trace_event_data_offsets_rdev_remain_on_channel {};\n\nstruct trace_event_data_offsets_rdev_return_int_cookie {};\n\nstruct trace_event_data_offsets_rdev_cancel_remain_on_channel {};\n\nstruct trace_event_data_offsets_rdev_mgmt_tx {};\n\nstruct trace_event_data_offsets_rdev_tx_control_port {};\n\nstruct trace_event_data_offsets_rdev_set_noack_map {};\n\nstruct trace_event_data_offsets_rdev_return_chandef {};\n\nstruct trace_event_data_offsets_rdev_start_nan {};\n\nstruct trace_event_data_offsets_rdev_nan_change_conf {};\n\nstruct trace_event_data_offsets_rdev_add_nan_func {};\n\nstruct trace_event_data_offsets_rdev_del_nan_func {};\n\nstruct trace_event_data_offsets_rdev_set_mac_acl {};\n\nstruct trace_event_data_offsets_rdev_update_ft_ies {\n\tu32 ie;\n};\n\nstruct trace_event_data_offsets_rdev_crit_proto_start {};\n\nstruct trace_event_data_offsets_rdev_crit_proto_stop {};\n\nstruct trace_event_data_offsets_rdev_channel_switch {\n\tu32 bcn_ofs;\n\tu32 pres_ofs;\n};\n\nstruct trace_event_data_offsets_rdev_set_qos_map {};\n\nstruct trace_event_data_offsets_rdev_set_ap_chanwidth {};\n\nstruct trace_event_data_offsets_rdev_add_tx_ts {};\n\nstruct trace_event_data_offsets_rdev_del_tx_ts {};\n\nstruct trace_event_data_offsets_rdev_tdls_channel_switch {};\n\nstruct trace_event_data_offsets_rdev_tdls_cancel_channel_switch {};\n\nstruct trace_event_data_offsets_rdev_set_pmk {\n\tu32 pmk;\n\tu32 pmk_r0_name;\n};\n\nstruct trace_event_data_offsets_rdev_del_pmk {};\n\nstruct trace_event_data_offsets_rdev_external_auth {};\n\nstruct trace_event_data_offsets_rdev_start_radar_detection {};\n\nstruct trace_event_data_offsets_rdev_set_mcast_rate {};\n\nstruct trace_event_data_offsets_rdev_set_coalesce {};\n\nstruct trace_event_data_offsets_rdev_set_multicast_to_unicast {};\n\nstruct trace_event_data_offsets_rdev_get_ftm_responder_stats {};\n\nstruct trace_event_data_offsets_cfg80211_return_bool {};\n\nstruct trace_event_data_offsets_cfg80211_netdev_mac_evt {};\n\nstruct trace_event_data_offsets_netdev_evt_only {};\n\nstruct trace_event_data_offsets_cfg80211_send_rx_assoc {};\n\nstruct trace_event_data_offsets_netdev_frame_event {\n\tu32 frame;\n};\n\nstruct trace_event_data_offsets_cfg80211_tx_mlme_mgmt {\n\tu32 frame;\n};\n\nstruct trace_event_data_offsets_netdev_mac_evt {};\n\nstruct trace_event_data_offsets_cfg80211_michael_mic_failure {};\n\nstruct trace_event_data_offsets_cfg80211_ready_on_channel {};\n\nstruct trace_event_data_offsets_cfg80211_ready_on_channel_expired {};\n\nstruct trace_event_data_offsets_cfg80211_tx_mgmt_expired {};\n\nstruct trace_event_data_offsets_cfg80211_new_sta {};\n\nstruct trace_event_data_offsets_cfg80211_rx_mgmt {};\n\nstruct trace_event_data_offsets_cfg80211_mgmt_tx_status {};\n\nstruct trace_event_data_offsets_cfg80211_control_port_tx_status {};\n\nstruct trace_event_data_offsets_cfg80211_rx_control_port {};\n\nstruct trace_event_data_offsets_cfg80211_cqm_rssi_notify {};\n\nstruct trace_event_data_offsets_cfg80211_reg_can_beacon {};\n\nstruct trace_event_data_offsets_cfg80211_chandef_dfs_required {};\n\nstruct trace_event_data_offsets_cfg80211_ch_switch_notify {};\n\nstruct trace_event_data_offsets_cfg80211_ch_switch_started_notify {};\n\nstruct trace_event_data_offsets_cfg80211_radar_event {};\n\nstruct trace_event_data_offsets_cfg80211_cac_event {};\n\nstruct trace_event_data_offsets_cfg80211_rx_evt {};\n\nstruct trace_event_data_offsets_cfg80211_ibss_joined {};\n\nstruct trace_event_data_offsets_cfg80211_probe_status {};\n\nstruct trace_event_data_offsets_cfg80211_cqm_pktloss_notify {};\n\nstruct trace_event_data_offsets_cfg80211_pmksa_candidate_notify {};\n\nstruct trace_event_data_offsets_cfg80211_report_obss_beacon {};\n\nstruct trace_event_data_offsets_cfg80211_tdls_oper_request {};\n\nstruct trace_event_data_offsets_cfg80211_scan_done {\n\tu32 ie;\n};\n\nstruct trace_event_data_offsets_wiphy_id_evt {};\n\nstruct trace_event_data_offsets_cfg80211_get_bss {\n\tu32 ssid;\n};\n\nstruct trace_event_data_offsets_cfg80211_inform_bss_frame {\n\tu32 mgmt;\n};\n\nstruct trace_event_data_offsets_cfg80211_bss_evt {};\n\nstruct trace_event_data_offsets_cfg80211_return_uint {};\n\nstruct trace_event_data_offsets_cfg80211_return_u32 {};\n\nstruct trace_event_data_offsets_cfg80211_report_wowlan_wakeup {\n\tu32 packet;\n};\n\nstruct trace_event_data_offsets_cfg80211_ft_event {\n\tu32 ies;\n\tu32 ric_ies;\n};\n\nstruct trace_event_data_offsets_cfg80211_stop_iface {};\n\nstruct trace_event_data_offsets_cfg80211_pmsr_report {};\n\nstruct trace_event_data_offsets_cfg80211_pmsr_complete {};\n\nstruct trace_event_data_offsets_rdev_update_owe_info {\n\tu32 ie;\n};\n\nstruct trace_event_data_offsets_cfg80211_update_owe_info_event {\n\tu32 ie;\n};\n\nstruct trace_event_data_offsets_rdev_probe_mesh_link {};\n\nstruct trace_event_data_offsets_rdev_set_tid_config {};\n\nstruct trace_event_data_offsets_rdev_reset_tid_config {};\n\ntypedef void (*btf_trace_rdev_suspend)(void *, struct wiphy *, struct cfg80211_wowlan *);\n\ntypedef void (*btf_trace_rdev_return_int)(void *, struct wiphy *, int);\n\ntypedef void (*btf_trace_rdev_scan)(void *, struct wiphy *, struct cfg80211_scan_request *);\n\ntypedef void (*btf_trace_rdev_resume)(void *, struct wiphy *);\n\ntypedef void (*btf_trace_rdev_return_void)(void *, struct wiphy *);\n\ntypedef void (*btf_trace_rdev_get_antenna)(void *, struct wiphy *);\n\ntypedef void (*btf_trace_rdev_rfkill_poll)(void *, struct wiphy *);\n\ntypedef void (*btf_trace_rdev_set_wakeup)(void *, struct wiphy *, bool);\n\ntypedef void (*btf_trace_rdev_add_virtual_intf)(void *, struct wiphy *, char *, enum nl80211_iftype);\n\ntypedef void (*btf_trace_rdev_return_wdev)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_del_virtual_intf)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_change_virtual_intf)(void *, struct wiphy *, struct net_device *, enum nl80211_iftype);\n\ntypedef void (*btf_trace_rdev_get_key)(void *, struct wiphy *, struct net_device *, u8, bool, const u8 *);\n\ntypedef void (*btf_trace_rdev_del_key)(void *, struct wiphy *, struct net_device *, u8, bool, const u8 *);\n\ntypedef void (*btf_trace_rdev_add_key)(void *, struct wiphy *, struct net_device *, u8, bool, const u8 *, u8);\n\ntypedef void (*btf_trace_rdev_set_default_key)(void *, struct wiphy *, struct net_device *, u8, bool, bool);\n\ntypedef void (*btf_trace_rdev_set_default_mgmt_key)(void *, struct wiphy *, struct net_device *, u8);\n\ntypedef void (*btf_trace_rdev_set_default_beacon_key)(void *, struct wiphy *, struct net_device *, u8);\n\ntypedef void (*btf_trace_rdev_start_ap)(void *, struct wiphy *, struct net_device *, struct cfg80211_ap_settings *);\n\ntypedef void (*btf_trace_rdev_change_beacon)(void *, struct wiphy *, struct net_device *, struct cfg80211_beacon_data *);\n\ntypedef void (*btf_trace_rdev_stop_ap)(void *, struct wiphy *, struct net_device *);\n\ntypedef void (*btf_trace_rdev_set_rekey_data)(void *, struct wiphy *, struct net_device *);\n\ntypedef void (*btf_trace_rdev_get_mesh_config)(void *, struct wiphy *, struct net_device *);\n\ntypedef void (*btf_trace_rdev_leave_mesh)(void *, struct wiphy *, struct net_device *);\n\ntypedef void (*btf_trace_rdev_leave_ibss)(void *, struct wiphy *, struct net_device *);\n\ntypedef void (*btf_trace_rdev_leave_ocb)(void *, struct wiphy *, struct net_device *);\n\ntypedef void (*btf_trace_rdev_flush_pmksa)(void *, struct wiphy *, struct net_device *);\n\ntypedef void (*btf_trace_rdev_end_cac)(void *, struct wiphy *, struct net_device *);\n\ntypedef void (*btf_trace_rdev_add_station)(void *, struct wiphy *, struct net_device *, u8 *, struct station_parameters *);\n\ntypedef void (*btf_trace_rdev_change_station)(void *, struct wiphy *, struct net_device *, u8 *, struct station_parameters *);\n\ntypedef void (*btf_trace_rdev_del_station)(void *, struct wiphy *, struct net_device *, struct station_del_parameters *);\n\ntypedef void (*btf_trace_rdev_get_station)(void *, struct wiphy *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_rdev_del_mpath)(void *, struct wiphy *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_rdev_set_wds_peer)(void *, struct wiphy *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_rdev_dump_station)(void *, struct wiphy *, struct net_device *, int, u8 *);\n\ntypedef void (*btf_trace_rdev_return_int_station_info)(void *, struct wiphy *, int, struct station_info *);\n\ntypedef void (*btf_trace_rdev_add_mpath)(void *, struct wiphy *, struct net_device *, u8 *, u8 *);\n\ntypedef void (*btf_trace_rdev_change_mpath)(void *, struct wiphy *, struct net_device *, u8 *, u8 *);\n\ntypedef void (*btf_trace_rdev_get_mpath)(void *, struct wiphy *, struct net_device *, u8 *, u8 *);\n\ntypedef void (*btf_trace_rdev_dump_mpath)(void *, struct wiphy *, struct net_device *, int, u8 *, u8 *);\n\ntypedef void (*btf_trace_rdev_get_mpp)(void *, struct wiphy *, struct net_device *, u8 *, u8 *);\n\ntypedef void (*btf_trace_rdev_dump_mpp)(void *, struct wiphy *, struct net_device *, int, u8 *, u8 *);\n\ntypedef void (*btf_trace_rdev_return_int_mpath_info)(void *, struct wiphy *, int, struct mpath_info *);\n\ntypedef void (*btf_trace_rdev_return_int_mesh_config)(void *, struct wiphy *, int, struct mesh_config *);\n\ntypedef void (*btf_trace_rdev_update_mesh_config)(void *, struct wiphy *, struct net_device *, u32, const struct mesh_config *);\n\ntypedef void (*btf_trace_rdev_join_mesh)(void *, struct wiphy *, struct net_device *, const struct mesh_config *, const struct mesh_setup *);\n\ntypedef void (*btf_trace_rdev_change_bss)(void *, struct wiphy *, struct net_device *, struct bss_parameters *);\n\ntypedef void (*btf_trace_rdev_set_txq_params)(void *, struct wiphy *, struct net_device *, struct ieee80211_txq_params *);\n\ntypedef void (*btf_trace_rdev_libertas_set_mesh_channel)(void *, struct wiphy *, struct net_device *, struct ieee80211_channel *);\n\ntypedef void (*btf_trace_rdev_set_monitor_channel)(void *, struct wiphy *, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_rdev_auth)(void *, struct wiphy *, struct net_device *, struct cfg80211_auth_request *);\n\ntypedef void (*btf_trace_rdev_assoc)(void *, struct wiphy *, struct net_device *, struct cfg80211_assoc_request *);\n\ntypedef void (*btf_trace_rdev_deauth)(void *, struct wiphy *, struct net_device *, struct cfg80211_deauth_request *);\n\ntypedef void (*btf_trace_rdev_disassoc)(void *, struct wiphy *, struct net_device *, struct cfg80211_disassoc_request *);\n\ntypedef void (*btf_trace_rdev_mgmt_tx_cancel_wait)(void *, struct wiphy *, struct wireless_dev *, u64);\n\ntypedef void (*btf_trace_rdev_set_power_mgmt)(void *, struct wiphy *, struct net_device *, bool, int);\n\ntypedef void (*btf_trace_rdev_connect)(void *, struct wiphy *, struct net_device *, struct cfg80211_connect_params *);\n\ntypedef void (*btf_trace_rdev_update_connect_params)(void *, struct wiphy *, struct net_device *, struct cfg80211_connect_params *, u32);\n\ntypedef void (*btf_trace_rdev_set_cqm_rssi_config)(void *, struct wiphy *, struct net_device *, s32, u32);\n\ntypedef void (*btf_trace_rdev_set_cqm_rssi_range_config)(void *, struct wiphy *, struct net_device *, s32, s32);\n\ntypedef void (*btf_trace_rdev_set_cqm_txe_config)(void *, struct wiphy *, struct net_device *, u32, u32, u32);\n\ntypedef void (*btf_trace_rdev_disconnect)(void *, struct wiphy *, struct net_device *, u16);\n\ntypedef void (*btf_trace_rdev_join_ibss)(void *, struct wiphy *, struct net_device *, struct cfg80211_ibss_params *);\n\ntypedef void (*btf_trace_rdev_join_ocb)(void *, struct wiphy *, struct net_device *, const struct ocb_setup *);\n\ntypedef void (*btf_trace_rdev_set_wiphy_params)(void *, struct wiphy *, u32);\n\ntypedef void (*btf_trace_rdev_get_tx_power)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_set_tx_power)(void *, struct wiphy *, struct wireless_dev *, enum nl80211_tx_power_setting, int);\n\ntypedef void (*btf_trace_rdev_return_int_int)(void *, struct wiphy *, int, int);\n\ntypedef void (*btf_trace_rdev_set_bitrate_mask)(void *, struct wiphy *, struct net_device *, const u8 *, const struct cfg80211_bitrate_mask *);\n\ntypedef void (*btf_trace_rdev_update_mgmt_frame_registrations)(void *, struct wiphy *, struct wireless_dev *, struct mgmt_frame_regs *);\n\ntypedef void (*btf_trace_rdev_return_int_tx_rx)(void *, struct wiphy *, int, u32, u32);\n\ntypedef void (*btf_trace_rdev_return_void_tx_rx)(void *, struct wiphy *, u32, u32, u32, u32);\n\ntypedef void (*btf_trace_rdev_set_antenna)(void *, struct wiphy *, u32, u32);\n\ntypedef void (*btf_trace_rdev_sched_scan_start)(void *, struct wiphy *, struct net_device *, u64);\n\ntypedef void (*btf_trace_rdev_sched_scan_stop)(void *, struct wiphy *, struct net_device *, u64);\n\ntypedef void (*btf_trace_rdev_tdls_mgmt)(void *, struct wiphy *, struct net_device *, u8 *, u8, u8, u16, u32, bool, const u8 *, size_t);\n\ntypedef void (*btf_trace_rdev_dump_survey)(void *, struct wiphy *, struct net_device *, int);\n\ntypedef void (*btf_trace_rdev_return_int_survey_info)(void *, struct wiphy *, int, struct survey_info *);\n\ntypedef void (*btf_trace_rdev_tdls_oper)(void *, struct wiphy *, struct net_device *, u8 *, enum nl80211_tdls_operation);\n\ntypedef void (*btf_trace_rdev_probe_client)(void *, struct wiphy *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_rdev_set_pmksa)(void *, struct wiphy *, struct net_device *, struct cfg80211_pmksa *);\n\ntypedef void (*btf_trace_rdev_del_pmksa)(void *, struct wiphy *, struct net_device *, struct cfg80211_pmksa *);\n\ntypedef void (*btf_trace_rdev_remain_on_channel)(void *, struct wiphy *, struct wireless_dev *, struct ieee80211_channel *, unsigned int);\n\ntypedef void (*btf_trace_rdev_return_int_cookie)(void *, struct wiphy *, int, u64);\n\ntypedef void (*btf_trace_rdev_cancel_remain_on_channel)(void *, struct wiphy *, struct wireless_dev *, u64);\n\ntypedef void (*btf_trace_rdev_mgmt_tx)(void *, struct wiphy *, struct wireless_dev *, struct cfg80211_mgmt_tx_params *);\n\ntypedef void (*btf_trace_rdev_tx_control_port)(void *, struct wiphy *, struct net_device *, const u8 *, size_t, const u8 *, __be16, bool);\n\ntypedef void (*btf_trace_rdev_set_noack_map)(void *, struct wiphy *, struct net_device *, u16);\n\ntypedef void (*btf_trace_rdev_get_channel)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_return_chandef)(void *, struct wiphy *, int, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_rdev_start_p2p_device)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_stop_p2p_device)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_start_nan)(void *, struct wiphy *, struct wireless_dev *, struct cfg80211_nan_conf *);\n\ntypedef void (*btf_trace_rdev_nan_change_conf)(void *, struct wiphy *, struct wireless_dev *, struct cfg80211_nan_conf *, u32);\n\ntypedef void (*btf_trace_rdev_stop_nan)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_add_nan_func)(void *, struct wiphy *, struct wireless_dev *, const struct cfg80211_nan_func *);\n\ntypedef void (*btf_trace_rdev_del_nan_func)(void *, struct wiphy *, struct wireless_dev *, u64);\n\ntypedef void (*btf_trace_rdev_set_mac_acl)(void *, struct wiphy *, struct net_device *, struct cfg80211_acl_data *);\n\ntypedef void (*btf_trace_rdev_update_ft_ies)(void *, struct wiphy *, struct net_device *, struct cfg80211_update_ft_ies_params *);\n\ntypedef void (*btf_trace_rdev_crit_proto_start)(void *, struct wiphy *, struct wireless_dev *, enum nl80211_crit_proto_id, u16);\n\ntypedef void (*btf_trace_rdev_crit_proto_stop)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_channel_switch)(void *, struct wiphy *, struct net_device *, struct cfg80211_csa_settings *);\n\ntypedef void (*btf_trace_rdev_set_qos_map)(void *, struct wiphy *, struct net_device *, struct cfg80211_qos_map *);\n\ntypedef void (*btf_trace_rdev_set_ap_chanwidth)(void *, struct wiphy *, struct net_device *, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_rdev_add_tx_ts)(void *, struct wiphy *, struct net_device *, u8, const u8 *, u8, u16);\n\ntypedef void (*btf_trace_rdev_del_tx_ts)(void *, struct wiphy *, struct net_device *, u8, const u8 *);\n\ntypedef void (*btf_trace_rdev_tdls_channel_switch)(void *, struct wiphy *, struct net_device *, const u8 *, u8, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_rdev_tdls_cancel_channel_switch)(void *, struct wiphy *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_rdev_set_pmk)(void *, struct wiphy *, struct net_device *, struct cfg80211_pmk_conf *);\n\ntypedef void (*btf_trace_rdev_del_pmk)(void *, struct wiphy *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_rdev_external_auth)(void *, struct wiphy *, struct net_device *, struct cfg80211_external_auth_params *);\n\ntypedef void (*btf_trace_rdev_start_radar_detection)(void *, struct wiphy *, struct net_device *, struct cfg80211_chan_def *, u32);\n\ntypedef void (*btf_trace_rdev_set_mcast_rate)(void *, struct wiphy *, struct net_device *, int *);\n\ntypedef void (*btf_trace_rdev_set_coalesce)(void *, struct wiphy *, struct cfg80211_coalesce *);\n\ntypedef void (*btf_trace_rdev_abort_scan)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_set_multicast_to_unicast)(void *, struct wiphy *, struct net_device *, const bool);\n\ntypedef void (*btf_trace_rdev_get_txq_stats)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_rdev_get_ftm_responder_stats)(void *, struct wiphy *, struct net_device *, struct cfg80211_ftm_responder_stats *);\n\ntypedef void (*btf_trace_rdev_start_pmsr)(void *, struct wiphy *, struct wireless_dev *, u64);\n\ntypedef void (*btf_trace_rdev_abort_pmsr)(void *, struct wiphy *, struct wireless_dev *, u64);\n\ntypedef void (*btf_trace_cfg80211_return_bool)(void *, bool);\n\ntypedef void (*btf_trace_cfg80211_notify_new_peer_candidate)(void *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_send_rx_auth)(void *, struct net_device *);\n\ntypedef void (*btf_trace_cfg80211_send_rx_assoc)(void *, struct net_device *, struct cfg80211_bss *);\n\ntypedef void (*btf_trace_cfg80211_rx_unprot_mlme_mgmt)(void *, struct net_device *, const u8 *, int);\n\ntypedef void (*btf_trace_cfg80211_rx_mlme_mgmt)(void *, struct net_device *, const u8 *, int);\n\ntypedef void (*btf_trace_cfg80211_tx_mlme_mgmt)(void *, struct net_device *, const u8 *, int);\n\ntypedef void (*btf_trace_cfg80211_send_auth_timeout)(void *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_send_assoc_timeout)(void *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_michael_mic_failure)(void *, struct net_device *, const u8 *, enum nl80211_key_type, int, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_ready_on_channel)(void *, struct wireless_dev *, u64, struct ieee80211_channel *, unsigned int);\n\ntypedef void (*btf_trace_cfg80211_ready_on_channel_expired)(void *, struct wireless_dev *, u64, struct ieee80211_channel *);\n\ntypedef void (*btf_trace_cfg80211_tx_mgmt_expired)(void *, struct wireless_dev *, u64, struct ieee80211_channel *);\n\ntypedef void (*btf_trace_cfg80211_new_sta)(void *, struct net_device *, const u8 *, struct station_info *);\n\ntypedef void (*btf_trace_cfg80211_del_sta)(void *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_rx_mgmt)(void *, struct wireless_dev *, int, int);\n\ntypedef void (*btf_trace_cfg80211_mgmt_tx_status)(void *, struct wireless_dev *, u64, bool);\n\ntypedef void (*btf_trace_cfg80211_control_port_tx_status)(void *, struct wireless_dev *, u64, bool);\n\ntypedef void (*btf_trace_cfg80211_rx_control_port)(void *, struct net_device *, struct sk_buff *, bool);\n\ntypedef void (*btf_trace_cfg80211_cqm_rssi_notify)(void *, struct net_device *, enum nl80211_cqm_rssi_threshold_event, s32);\n\ntypedef void (*btf_trace_cfg80211_reg_can_beacon)(void *, struct wiphy *, struct cfg80211_chan_def *, enum nl80211_iftype, bool);\n\ntypedef void (*btf_trace_cfg80211_chandef_dfs_required)(void *, struct wiphy *, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_cfg80211_ch_switch_notify)(void *, struct net_device *, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_cfg80211_ch_switch_started_notify)(void *, struct net_device *, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_cfg80211_radar_event)(void *, struct wiphy *, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_cfg80211_cac_event)(void *, struct net_device *, enum nl80211_radar_event);\n\ntypedef void (*btf_trace_cfg80211_rx_spurious_frame)(void *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_rx_unexpected_4addr_frame)(void *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_ibss_joined)(void *, struct net_device *, const u8 *, struct ieee80211_channel *);\n\ntypedef void (*btf_trace_cfg80211_probe_status)(void *, struct net_device *, const u8 *, u64, bool);\n\ntypedef void (*btf_trace_cfg80211_cqm_pktloss_notify)(void *, struct net_device *, const u8 *, u32);\n\ntypedef void (*btf_trace_cfg80211_gtk_rekey_notify)(void *, struct net_device *, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_pmksa_candidate_notify)(void *, struct net_device *, int, const u8 *, bool);\n\ntypedef void (*btf_trace_cfg80211_report_obss_beacon)(void *, struct wiphy *, const u8 *, size_t, int, int);\n\ntypedef void (*btf_trace_cfg80211_tdls_oper_request)(void *, struct wiphy *, struct net_device *, const u8 *, enum nl80211_tdls_operation, u16);\n\ntypedef void (*btf_trace_cfg80211_scan_done)(void *, struct cfg80211_scan_request *, struct cfg80211_scan_info *);\n\ntypedef void (*btf_trace_cfg80211_sched_scan_stopped)(void *, struct wiphy *, u64);\n\ntypedef void (*btf_trace_cfg80211_sched_scan_results)(void *, struct wiphy *, u64);\n\ntypedef void (*btf_trace_cfg80211_get_bss)(void *, struct wiphy *, struct ieee80211_channel *, const u8 *, const u8 *, size_t, enum ieee80211_bss_type, enum ieee80211_privacy);\n\ntypedef void (*btf_trace_cfg80211_inform_bss_frame)(void *, struct wiphy *, struct cfg80211_inform_bss *, struct ieee80211_mgmt *, size_t);\n\ntypedef void (*btf_trace_cfg80211_return_bss)(void *, struct cfg80211_bss *);\n\ntypedef void (*btf_trace_cfg80211_return_uint)(void *, unsigned int);\n\ntypedef void (*btf_trace_cfg80211_return_u32)(void *, u32);\n\ntypedef void (*btf_trace_cfg80211_report_wowlan_wakeup)(void *, struct wiphy *, struct wireless_dev *, struct cfg80211_wowlan_wakeup *);\n\ntypedef void (*btf_trace_cfg80211_ft_event)(void *, struct wiphy *, struct net_device *, struct cfg80211_ft_event_params *);\n\ntypedef void (*btf_trace_cfg80211_stop_iface)(void *, struct wiphy *, struct wireless_dev *);\n\ntypedef void (*btf_trace_cfg80211_pmsr_report)(void *, struct wiphy *, struct wireless_dev *, u64, const u8 *);\n\ntypedef void (*btf_trace_cfg80211_pmsr_complete)(void *, struct wiphy *, struct wireless_dev *, u64);\n\ntypedef void (*btf_trace_rdev_update_owe_info)(void *, struct wiphy *, struct net_device *, struct cfg80211_update_owe_info *);\n\ntypedef void (*btf_trace_cfg80211_update_owe_info_event)(void *, struct wiphy *, struct net_device *, struct cfg80211_update_owe_info *);\n\ntypedef void (*btf_trace_rdev_probe_mesh_link)(void *, struct wiphy *, struct net_device *, const u8 *, const u8 *, size_t);\n\ntypedef void (*btf_trace_rdev_set_tid_config)(void *, struct wiphy *, struct net_device *, struct cfg80211_tid_config *);\n\ntypedef void (*btf_trace_rdev_reset_tid_config)(void *, struct wiphy *, struct net_device *, const u8 *, u8);\n\nenum nl80211_peer_measurement_status {\n\tNL80211_PMSR_STATUS_SUCCESS = 0,\n\tNL80211_PMSR_STATUS_REFUSED = 1,\n\tNL80211_PMSR_STATUS_TIMEOUT = 2,\n\tNL80211_PMSR_STATUS_FAILURE = 3,\n};\n\nenum nl80211_peer_measurement_resp {\n\t__NL80211_PMSR_RESP_ATTR_INVALID = 0,\n\tNL80211_PMSR_RESP_ATTR_DATA = 1,\n\tNL80211_PMSR_RESP_ATTR_STATUS = 2,\n\tNL80211_PMSR_RESP_ATTR_HOST_TIME = 3,\n\tNL80211_PMSR_RESP_ATTR_AP_TSF = 4,\n\tNL80211_PMSR_RESP_ATTR_FINAL = 5,\n\tNL80211_PMSR_RESP_ATTR_PAD = 6,\n\tNUM_NL80211_PMSR_RESP_ATTRS = 7,\n\tNL80211_PMSR_RESP_ATTR_MAX = 6,\n};\n\nenum nl80211_peer_measurement_ftm_failure_reasons {\n\tNL80211_PMSR_FTM_FAILURE_UNSPECIFIED = 0,\n\tNL80211_PMSR_FTM_FAILURE_NO_RESPONSE = 1,\n\tNL80211_PMSR_FTM_FAILURE_REJECTED = 2,\n\tNL80211_PMSR_FTM_FAILURE_WRONG_CHANNEL = 3,\n\tNL80211_PMSR_FTM_FAILURE_PEER_NOT_CAPABLE = 4,\n\tNL80211_PMSR_FTM_FAILURE_INVALID_TIMESTAMP = 5,\n\tNL80211_PMSR_FTM_FAILURE_PEER_BUSY = 6,\n\tNL80211_PMSR_FTM_FAILURE_BAD_CHANGED_PARAMS = 7,\n};\n\nenum nl80211_peer_measurement_ftm_resp {\n\t__NL80211_PMSR_FTM_RESP_ATTR_INVALID = 0,\n\tNL80211_PMSR_FTM_RESP_ATTR_FAIL_REASON = 1,\n\tNL80211_PMSR_FTM_RESP_ATTR_BURST_INDEX = 2,\n\tNL80211_PMSR_FTM_RESP_ATTR_NUM_FTMR_ATTEMPTS = 3,\n\tNL80211_PMSR_FTM_RESP_ATTR_NUM_FTMR_SUCCESSES = 4,\n\tNL80211_PMSR_FTM_RESP_ATTR_BUSY_RETRY_TIME = 5,\n\tNL80211_PMSR_FTM_RESP_ATTR_NUM_BURSTS_EXP = 6,\n\tNL80211_PMSR_FTM_RESP_ATTR_BURST_DURATION = 7,\n\tNL80211_PMSR_FTM_RESP_ATTR_FTMS_PER_BURST = 8,\n\tNL80211_PMSR_FTM_RESP_ATTR_RSSI_AVG = 9,\n\tNL80211_PMSR_FTM_RESP_ATTR_RSSI_SPREAD = 10,\n\tNL80211_PMSR_FTM_RESP_ATTR_TX_RATE = 11,\n\tNL80211_PMSR_FTM_RESP_ATTR_RX_RATE = 12,\n\tNL80211_PMSR_FTM_RESP_ATTR_RTT_AVG = 13,\n\tNL80211_PMSR_FTM_RESP_ATTR_RTT_VARIANCE = 14,\n\tNL80211_PMSR_FTM_RESP_ATTR_RTT_SPREAD = 15,\n\tNL80211_PMSR_FTM_RESP_ATTR_DIST_AVG = 16,\n\tNL80211_PMSR_FTM_RESP_ATTR_DIST_VARIANCE = 17,\n\tNL80211_PMSR_FTM_RESP_ATTR_DIST_SPREAD = 18,\n\tNL80211_PMSR_FTM_RESP_ATTR_LCI = 19,\n\tNL80211_PMSR_FTM_RESP_ATTR_CIVICLOC = 20,\n\tNL80211_PMSR_FTM_RESP_ATTR_PAD = 21,\n\tNUM_NL80211_PMSR_FTM_RESP_ATTR = 22,\n\tNL80211_PMSR_FTM_RESP_ATTR_MAX = 21,\n};\n\nstruct cfg80211_pmsr_ftm_result {\n\tconst u8 *lci;\n\tconst u8 *civicloc;\n\tunsigned int lci_len;\n\tunsigned int civicloc_len;\n\tenum nl80211_peer_measurement_ftm_failure_reasons failure_reason;\n\tu32 num_ftmr_attempts;\n\tu32 num_ftmr_successes;\n\ts16 burst_index;\n\tu8 busy_retry_time;\n\tu8 num_bursts_exp;\n\tu8 burst_duration;\n\tu8 ftms_per_burst;\n\ts32 rssi_avg;\n\ts32 rssi_spread;\n\tstruct rate_info tx_rate;\n\tstruct rate_info rx_rate;\n\ts64 rtt_avg;\n\ts64 rtt_variance;\n\ts64 rtt_spread;\n\ts64 dist_avg;\n\ts64 dist_variance;\n\ts64 dist_spread;\n\tu16 num_ftmr_attempts_valid: 1;\n\tu16 num_ftmr_successes_valid: 1;\n\tu16 rssi_avg_valid: 1;\n\tu16 rssi_spread_valid: 1;\n\tu16 tx_rate_valid: 1;\n\tu16 rx_rate_valid: 1;\n\tu16 rtt_avg_valid: 1;\n\tu16 rtt_variance_valid: 1;\n\tu16 rtt_spread_valid: 1;\n\tu16 dist_avg_valid: 1;\n\tu16 dist_variance_valid: 1;\n\tu16 dist_spread_valid: 1;\n};\n\nstruct cfg80211_pmsr_result {\n\tu64 host_time;\n\tu64 ap_tsf;\n\tenum nl80211_peer_measurement_status status;\n\tu8 addr[6];\n\tu8 final: 1;\n\tu8 ap_tsf_valid: 1;\n\tenum nl80211_peer_measurement_type type;\n\tunion {\n\t\tstruct cfg80211_pmsr_ftm_result ftm;\n\t};\n};\n\nstruct ieee80211_channel_sw_ie {\n\tu8 mode;\n\tu8 new_ch_num;\n\tu8 count;\n};\n\nstruct ieee80211_sec_chan_offs_ie {\n\tu8 sec_chan_offs;\n};\n\nstruct ieee80211_mesh_chansw_params_ie {\n\tu8 mesh_ttl;\n\tu8 mesh_flags;\n\t__le16 mesh_reason;\n\t__le16 mesh_pre_value;\n};\n\nstruct ieee80211_wide_bw_chansw_ie {\n\tu8 new_channel_width;\n\tu8 new_center_freq_seg0;\n\tu8 new_center_freq_seg1;\n};\n\nstruct ieee80211_tim_ie {\n\tu8 dtim_count;\n\tu8 dtim_period;\n\tu8 bitmap_ctrl;\n\tu8 virtual_map[1];\n};\n\nstruct ieee80211_meshconf_ie {\n\tu8 meshconf_psel;\n\tu8 meshconf_pmetric;\n\tu8 meshconf_congest;\n\tu8 meshconf_synch;\n\tu8 meshconf_auth;\n\tu8 meshconf_form;\n\tu8 meshconf_cap;\n};\n\nstruct ieee80211_rann_ie {\n\tu8 rann_flags;\n\tu8 rann_hopcount;\n\tu8 rann_ttl;\n\tu8 rann_addr[6];\n\t__le32 rann_seq;\n\t__le32 rann_interval;\n\t__le32 rann_metric;\n} __attribute__((packed));\n\nstruct ieee80211_addba_ext_ie {\n\tu8 data;\n};\n\nstruct ieee80211_ch_switch_timing {\n\t__le16 switch_time;\n\t__le16 switch_timeout;\n};\n\nstruct ieee80211_tdls_lnkie {\n\tu8 ie_type;\n\tu8 ie_len;\n\tu8 bssid[6];\n\tu8 init_sta[6];\n\tu8 resp_sta[6];\n};\n\nstruct ieee80211_p2p_noa_desc {\n\tu8 count;\n\t__le32 duration;\n\t__le32 interval;\n\t__le32 start_time;\n} __attribute__((packed));\n\nstruct ieee80211_p2p_noa_attr {\n\tu8 index;\n\tu8 oppps_ctwindow;\n\tstruct ieee80211_p2p_noa_desc desc[4];\n} __attribute__((packed));\n\nstruct ieee80211_vht_operation {\n\tu8 chan_width;\n\tu8 center_freq_seg0_idx;\n\tu8 center_freq_seg1_idx;\n\t__le16 basic_mcs_set;\n} __attribute__((packed));\n\nstruct ieee80211_he_spr {\n\tu8 he_sr_control;\n\tu8 optional[0];\n};\n\nstruct ieee80211_he_mu_edca_param_ac_rec {\n\tu8 aifsn;\n\tu8 ecw_min_max;\n\tu8 mu_edca_timer;\n};\n\nstruct ieee80211_mu_edca_param_set {\n\tu8 mu_qos_info;\n\tstruct ieee80211_he_mu_edca_param_ac_rec ac_be;\n\tstruct ieee80211_he_mu_edca_param_ac_rec ac_bk;\n\tstruct ieee80211_he_mu_edca_param_ac_rec ac_vi;\n\tstruct ieee80211_he_mu_edca_param_ac_rec ac_vo;\n};\n\nstruct ieee80211_timeout_interval_ie {\n\tu8 type;\n\t__le32 value;\n} __attribute__((packed));\n\nstruct ieee80211_bss_max_idle_period_ie {\n\t__le16 max_idle_period;\n\tu8 idle_options;\n} __attribute__((packed));\n\nstruct ieee80211_bssid_index {\n\tu8 bssid_index;\n\tu8 dtim_period;\n\tu8 dtim_count;\n};\n\nstruct ieee80211_multiple_bssid_configuration {\n\tu8 bssid_count;\n\tu8 profile_periodicity;\n};\n\ntypedef u32 codel_time_t;\n\nstruct codel_params {\n\tcodel_time_t target;\n\tcodel_time_t ce_threshold;\n\tcodel_time_t interval;\n\tu32 mtu;\n\tbool ecn;\n};\n\nstruct codel_vars {\n\tu32 count;\n\tu32 lastcount;\n\tbool dropping;\n\tu16 rec_inv_sqrt;\n\tcodel_time_t first_above_time;\n\tcodel_time_t drop_next;\n\tcodel_time_t ldelay;\n};\n\nenum ieee80211_radiotap_mcs_have {\n\tIEEE80211_RADIOTAP_MCS_HAVE_BW = 1,\n\tIEEE80211_RADIOTAP_MCS_HAVE_MCS = 2,\n\tIEEE80211_RADIOTAP_MCS_HAVE_GI = 4,\n\tIEEE80211_RADIOTAP_MCS_HAVE_FMT = 8,\n\tIEEE80211_RADIOTAP_MCS_HAVE_FEC = 16,\n\tIEEE80211_RADIOTAP_MCS_HAVE_STBC = 32,\n};\n\nenum ieee80211_radiotap_vht_known {\n\tIEEE80211_RADIOTAP_VHT_KNOWN_STBC = 1,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_TXOP_PS_NA = 2,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_GI = 4,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_SGI_NSYM_DIS = 8,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_LDPC_EXTRA_OFDM_SYM = 16,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED = 32,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH = 64,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_GROUP_ID = 128,\n\tIEEE80211_RADIOTAP_VHT_KNOWN_PARTIAL_AID = 256,\n};\n\nenum ieee80211_max_queues {\n\tIEEE80211_MAX_QUEUES = 16,\n\tIEEE80211_MAX_QUEUE_MAP = 65535,\n};\n\nstruct ieee80211_tx_queue_params {\n\tu16 txop;\n\tu16 cw_min;\n\tu16 cw_max;\n\tu8 aifs;\n\tbool acm;\n\tbool uapsd;\n\tbool mu_edca;\n\tstruct ieee80211_he_mu_edca_param_ac_rec mu_edca_param_rec;\n};\n\nstruct ieee80211_low_level_stats {\n\tunsigned int dot11ACKFailureCount;\n\tunsigned int dot11RTSFailureCount;\n\tunsigned int dot11FCSErrorCount;\n\tunsigned int dot11RTSSuccessCount;\n};\n\nstruct ieee80211_chanctx_conf {\n\tstruct cfg80211_chan_def def;\n\tstruct cfg80211_chan_def min_def;\n\tu8 rx_chains_static;\n\tu8 rx_chains_dynamic;\n\tbool radar_enabled;\n\tlong: 40;\n\tu8 drv_priv[0];\n};\n\nenum ieee80211_chanctx_switch_mode {\n\tCHANCTX_SWMODE_REASSIGN_VIF = 0,\n\tCHANCTX_SWMODE_SWAP_CONTEXTS = 1,\n};\n\nstruct ieee80211_vif;\n\nstruct ieee80211_vif_chanctx_switch {\n\tstruct ieee80211_vif *vif;\n\tstruct ieee80211_chanctx_conf *old_ctx;\n\tstruct ieee80211_chanctx_conf *new_ctx;\n};\n\nstruct ieee80211_mu_group_data {\n\tu8 membership[8];\n\tu8 position[16];\n};\n\nstruct ieee80211_ftm_responder_params;\n\nstruct ieee80211_bss_conf {\n\tconst u8 *bssid;\n\tu8 htc_trig_based_pkt_ext;\n\tbool multi_sta_back_32bit;\n\tbool uora_exists;\n\tbool ack_enabled;\n\tu8 uora_ocw_range;\n\tu16 frame_time_rts_th;\n\tbool he_support;\n\tbool twt_requester;\n\tbool twt_responder;\n\tbool twt_protected;\n\tbool assoc;\n\tbool ibss_joined;\n\tbool ibss_creator;\n\tu16 aid;\n\tbool use_cts_prot;\n\tbool use_short_preamble;\n\tbool use_short_slot;\n\tbool enable_beacon;\n\tu8 dtim_period;\n\tu16 beacon_int;\n\tu16 assoc_capability;\n\tu64 sync_tsf;\n\tu32 sync_device_ts;\n\tu8 sync_dtim_count;\n\tu32 basic_rates;\n\tstruct ieee80211_rate *beacon_rate;\n\tint mcast_rate[4];\n\tu16 ht_operation_mode;\n\ts32 cqm_rssi_thold;\n\tu32 cqm_rssi_hyst;\n\ts32 cqm_rssi_low;\n\ts32 cqm_rssi_high;\n\tstruct cfg80211_chan_def chandef;\n\tstruct ieee80211_mu_group_data mu_group;\n\t__be32 arp_addr_list[4];\n\tint arp_addr_cnt;\n\tbool qos;\n\tbool idle;\n\tbool ps;\n\tu8 ssid[32];\n\tsize_t ssid_len;\n\tbool hidden_ssid;\n\tint txpower;\n\tenum nl80211_tx_power_setting txpower_type;\n\tstruct ieee80211_p2p_noa_attr p2p_noa_attr;\n\tbool allow_p2p_go_ps;\n\tu16 max_idle_period;\n\tbool protected_keep_alive;\n\tbool ftm_responder;\n\tstruct ieee80211_ftm_responder_params *ftmr_params;\n\tbool nontransmitted;\n\tu8 transmitter_bssid[6];\n\tu8 bssid_index;\n\tu8 bssid_indicator;\n\tbool ema_ap;\n\tu8 profile_periodicity;\n\tstruct {\n\t\tu32 params;\n\t\tu16 nss_set;\n\t} he_oper;\n\tstruct ieee80211_he_obss_pd he_obss_pd;\n\tstruct cfg80211_he_bss_color he_bss_color;\n};\n\nstruct ieee80211_txq;\n\nstruct ieee80211_vif {\n\tenum nl80211_iftype type;\n\tstruct ieee80211_bss_conf bss_conf;\n\tu8 addr[6];\n\tbool p2p;\n\tbool csa_active;\n\tbool mu_mimo_owner;\n\tu8 cab_queue;\n\tu8 hw_queue[4];\n\tstruct ieee80211_txq *txq;\n\tstruct ieee80211_chanctx_conf *chanctx_conf;\n\tu32 driver_flags;\n\tbool probe_req_reg;\n\tbool rx_mcast_action_reg;\n\tbool txqs_stopped[4];\n\tlong: 48;\n\tu8 drv_priv[0];\n};\n\nenum ieee80211_bss_change {\n\tBSS_CHANGED_ASSOC = 1,\n\tBSS_CHANGED_ERP_CTS_PROT = 2,\n\tBSS_CHANGED_ERP_PREAMBLE = 4,\n\tBSS_CHANGED_ERP_SLOT = 8,\n\tBSS_CHANGED_HT = 16,\n\tBSS_CHANGED_BASIC_RATES = 32,\n\tBSS_CHANGED_BEACON_INT = 64,\n\tBSS_CHANGED_BSSID = 128,\n\tBSS_CHANGED_BEACON = 256,\n\tBSS_CHANGED_BEACON_ENABLED = 512,\n\tBSS_CHANGED_CQM = 1024,\n\tBSS_CHANGED_IBSS = 2048,\n\tBSS_CHANGED_ARP_FILTER = 4096,\n\tBSS_CHANGED_QOS = 8192,\n\tBSS_CHANGED_IDLE = 16384,\n\tBSS_CHANGED_SSID = 32768,\n\tBSS_CHANGED_AP_PROBE_RESP = 65536,\n\tBSS_CHANGED_PS = 131072,\n\tBSS_CHANGED_TXPOWER = 262144,\n\tBSS_CHANGED_P2P_PS = 524288,\n\tBSS_CHANGED_BEACON_INFO = 1048576,\n\tBSS_CHANGED_BANDWIDTH = 2097152,\n\tBSS_CHANGED_OCB = 4194304,\n\tBSS_CHANGED_MU_GROUPS = 8388608,\n\tBSS_CHANGED_KEEP_ALIVE = 16777216,\n\tBSS_CHANGED_MCAST_RATE = 33554432,\n\tBSS_CHANGED_FTM_RESPONDER = 67108864,\n\tBSS_CHANGED_TWT = 134217728,\n\tBSS_CHANGED_HE_OBSS_PD = 268435456,\n\tBSS_CHANGED_HE_BSS_COLOR = 536870912,\n};\n\nenum ieee80211_event_type {\n\tRSSI_EVENT = 0,\n\tMLME_EVENT = 1,\n\tBAR_RX_EVENT = 2,\n\tBA_FRAME_TIMEOUT = 3,\n};\n\nenum ieee80211_rssi_event_data {\n\tRSSI_EVENT_HIGH = 0,\n\tRSSI_EVENT_LOW = 1,\n};\n\nstruct ieee80211_rssi_event {\n\tenum ieee80211_rssi_event_data data;\n};\n\nenum ieee80211_mlme_event_data {\n\tAUTH_EVENT = 0,\n\tASSOC_EVENT = 1,\n\tDEAUTH_RX_EVENT = 2,\n\tDEAUTH_TX_EVENT = 3,\n};\n\nenum ieee80211_mlme_event_status {\n\tMLME_SUCCESS = 0,\n\tMLME_DENIED = 1,\n\tMLME_TIMEOUT = 2,\n};\n\nstruct ieee80211_mlme_event {\n\tenum ieee80211_mlme_event_data data;\n\tenum ieee80211_mlme_event_status status;\n\tu16 reason;\n};\n\nstruct ieee80211_sta;\n\nstruct ieee80211_ba_event {\n\tstruct ieee80211_sta *sta;\n\tu16 tid;\n\tu16 ssn;\n};\n\nenum ieee80211_sta_rx_bandwidth {\n\tIEEE80211_STA_RX_BW_20 = 0,\n\tIEEE80211_STA_RX_BW_40 = 1,\n\tIEEE80211_STA_RX_BW_80 = 2,\n\tIEEE80211_STA_RX_BW_160 = 3,\n};\n\nenum ieee80211_smps_mode {\n\tIEEE80211_SMPS_AUTOMATIC = 0,\n\tIEEE80211_SMPS_OFF = 1,\n\tIEEE80211_SMPS_STATIC = 2,\n\tIEEE80211_SMPS_DYNAMIC = 3,\n\tIEEE80211_SMPS_NUM_MODES = 4,\n};\n\nstruct ieee80211_sta_txpwr {\n\ts16 power;\n\tenum nl80211_tx_power_setting type;\n};\n\nstruct ieee80211_sta_rates;\n\nstruct ieee80211_sta {\n\tu32 supp_rates[4];\n\tu8 addr[6];\n\tu16 aid;\n\tstruct ieee80211_sta_ht_cap ht_cap;\n\tshort: 16;\n\tstruct ieee80211_sta_vht_cap vht_cap;\n\tstruct ieee80211_sta_he_cap he_cap;\n\tstruct ieee80211_he_6ghz_capa he_6ghz_capa;\n\tchar: 8;\n\tu16 max_rx_aggregation_subframes;\n\tbool wme;\n\tu8 uapsd_queues;\n\tu8 max_sp;\n\tu8 rx_nss;\n\tenum ieee80211_sta_rx_bandwidth bandwidth;\n\tenum ieee80211_smps_mode smps_mode;\n\tstruct ieee80211_sta_rates *rates;\n\tbool tdls;\n\tbool tdls_initiator;\n\tbool mfp;\n\tu8 max_amsdu_subframes;\n\tu16 max_amsdu_len;\n\tbool support_p2p_ps;\n\tchar: 8;\n\tu16 max_rc_amsdu_len;\n\tu16 max_tid_amsdu_len[16];\n\tshort: 16;\n\tstruct ieee80211_sta_txpwr txpwr;\n\tint: 32;\n\tstruct ieee80211_txq *txq[17];\n\tu8 drv_priv[0];\n} __attribute__((packed));\n\nstruct ieee80211_event {\n\tenum ieee80211_event_type type;\n\tunion {\n\t\tstruct ieee80211_rssi_event rssi;\n\t\tstruct ieee80211_mlme_event mlme;\n\t\tstruct ieee80211_ba_event ba;\n\t} u;\n};\n\nstruct ieee80211_ftm_responder_params {\n\tconst u8 *lci;\n\tconst u8 *civicloc;\n\tsize_t lci_len;\n\tsize_t civicloc_len;\n};\n\nstruct ieee80211_tx_rate {\n\ts8 idx;\n\tu16 count: 5;\n\tu16 flags: 11;\n} __attribute__((packed));\n\nstruct ieee80211_key_conf {\n\tatomic64_t tx_pn;\n\tu32 cipher;\n\tu8 icv_len;\n\tu8 iv_len;\n\tu8 hw_key_idx;\n\ts8 keyidx;\n\tu16 flags;\n\tu8 keylen;\n\tu8 key[0];\n};\n\nstruct ieee80211_tx_info {\n\tu32 flags;\n\tu32 band: 3;\n\tu32 ack_frame_id: 13;\n\tu32 hw_queue: 4;\n\tu32 tx_time_est: 10;\n\tunion {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tstruct ieee80211_tx_rate rates[4];\n\t\t\t\t\ts8 rts_cts_rate_idx;\n\t\t\t\t\tu8 use_rts: 1;\n\t\t\t\t\tu8 use_cts_prot: 1;\n\t\t\t\t\tu8 short_preamble: 1;\n\t\t\t\t\tu8 skip_table: 1;\n\t\t\t\t};\n\t\t\t\tlong unsigned int jiffies;\n\t\t\t};\n\t\t\tstruct ieee80211_vif *vif;\n\t\t\tstruct ieee80211_key_conf *hw_key;\n\t\t\tu32 flags;\n\t\t\tcodel_time_t enqueue_time;\n\t\t} control;\n\t\tstruct {\n\t\t\tu64 cookie;\n\t\t} ack;\n\t\tstruct {\n\t\t\tstruct ieee80211_tx_rate rates[4];\n\t\t\ts32 ack_signal;\n\t\t\tu8 ampdu_ack_len;\n\t\t\tu8 ampdu_len;\n\t\t\tu8 antenna;\n\t\t\tu16 tx_time;\n\t\t\tbool is_valid_ack_signal;\n\t\t\tvoid *status_driver_data[2];\n\t\t} status;\n\t\tstruct {\n\t\t\tstruct ieee80211_tx_rate driver_rates[4];\n\t\t\tu8 pad[4];\n\t\t\tvoid *rate_driver_data[3];\n\t\t};\n\t\tvoid *driver_data[5];\n\t};\n};\n\nstruct ieee80211_tx_status {\n\tstruct ieee80211_sta *sta;\n\tstruct ieee80211_tx_info *info;\n\tstruct sk_buff *skb;\n\tstruct rate_info *rate;\n};\n\nstruct ieee80211_scan_ies {\n\tconst u8 *ies[4];\n\tsize_t len[4];\n\tconst u8 *common_ies;\n\tsize_t common_ie_len;\n};\n\nstruct ieee80211_rx_status {\n\tu64 mactime;\n\tu64 boottime_ns;\n\tu32 device_timestamp;\n\tu32 ampdu_reference;\n\tu32 flag;\n\tu16 freq: 13;\n\tu16 freq_offset: 1;\n\tu8 enc_flags;\n\tu8 encoding: 2;\n\tu8 bw: 3;\n\tu8 he_ru: 3;\n\tu8 he_gi: 2;\n\tu8 he_dcm: 1;\n\tu8 rate_idx;\n\tu8 nss;\n\tu8 rx_flags;\n\tu8 band;\n\tu8 antenna;\n\ts8 signal;\n\tu8 chains;\n\ts8 chain_signal[4];\n\tu8 ampdu_delimiter_crc;\n\tu8 zero_length_psdu_type;\n};\n\nenum ieee80211_conf_flags {\n\tIEEE80211_CONF_MONITOR = 1,\n\tIEEE80211_CONF_PS = 2,\n\tIEEE80211_CONF_IDLE = 4,\n\tIEEE80211_CONF_OFFCHANNEL = 8,\n};\n\nenum ieee80211_conf_changed {\n\tIEEE80211_CONF_CHANGE_SMPS = 2,\n\tIEEE80211_CONF_CHANGE_LISTEN_INTERVAL = 4,\n\tIEEE80211_CONF_CHANGE_MONITOR = 8,\n\tIEEE80211_CONF_CHANGE_PS = 16,\n\tIEEE80211_CONF_CHANGE_POWER = 32,\n\tIEEE80211_CONF_CHANGE_CHANNEL = 64,\n\tIEEE80211_CONF_CHANGE_RETRY_LIMITS = 128,\n\tIEEE80211_CONF_CHANGE_IDLE = 256,\n};\n\nstruct ieee80211_conf {\n\tu32 flags;\n\tint power_level;\n\tint dynamic_ps_timeout;\n\tu16 listen_interval;\n\tu8 ps_dtim_period;\n\tu8 long_frame_max_tx_count;\n\tu8 short_frame_max_tx_count;\n\tstruct cfg80211_chan_def chandef;\n\tbool radar_enabled;\n\tenum ieee80211_smps_mode smps_mode;\n};\n\nstruct ieee80211_channel_switch {\n\tu64 timestamp;\n\tu32 device_timestamp;\n\tbool block_tx;\n\tstruct cfg80211_chan_def chandef;\n\tu8 count;\n\tu32 delay;\n};\n\nstruct ieee80211_txq {\n\tstruct ieee80211_vif *vif;\n\tstruct ieee80211_sta *sta;\n\tu8 tid;\n\tu8 ac;\n\tlong: 48;\n\tu8 drv_priv[0];\n};\n\nstruct ieee80211_key_seq {\n\tunion {\n\t\tstruct {\n\t\t\tu32 iv32;\n\t\t\tu16 iv16;\n\t\t} tkip;\n\t\tstruct {\n\t\t\tu8 pn[6];\n\t\t} ccmp;\n\t\tstruct {\n\t\t\tu8 pn[6];\n\t\t} aes_cmac;\n\t\tstruct {\n\t\t\tu8 pn[6];\n\t\t} aes_gmac;\n\t\tstruct {\n\t\t\tu8 pn[6];\n\t\t} gcmp;\n\t\tstruct {\n\t\t\tu8 seq[16];\n\t\t\tu8 seq_len;\n\t\t} hw;\n\t};\n};\n\nstruct ieee80211_cipher_scheme {\n\tu32 cipher;\n\tu16 iftype;\n\tu8 hdr_len;\n\tu8 pn_len;\n\tu8 pn_off;\n\tu8 key_idx_off;\n\tu8 key_idx_mask;\n\tu8 key_idx_shift;\n\tu8 mic_len;\n};\n\nenum set_key_cmd {\n\tSET_KEY = 0,\n\tDISABLE_KEY = 1,\n};\n\nenum ieee80211_sta_state {\n\tIEEE80211_STA_NOTEXIST = 0,\n\tIEEE80211_STA_NONE = 1,\n\tIEEE80211_STA_AUTH = 2,\n\tIEEE80211_STA_ASSOC = 3,\n\tIEEE80211_STA_AUTHORIZED = 4,\n};\n\nstruct ieee80211_sta_rates {\n\tstruct callback_head callback_head;\n\tstruct {\n\t\ts8 idx;\n\t\tu8 count;\n\t\tu8 count_cts;\n\t\tu8 count_rts;\n\t\tu16 flags;\n\t} rate[4];\n};\n\nenum sta_notify_cmd {\n\tSTA_NOTIFY_SLEEP = 0,\n\tSTA_NOTIFY_AWAKE = 1,\n};\n\nstruct ieee80211_tx_control {\n\tstruct ieee80211_sta *sta;\n};\n\nenum ieee80211_hw_flags {\n\tIEEE80211_HW_HAS_RATE_CONTROL = 0,\n\tIEEE80211_HW_RX_INCLUDES_FCS = 1,\n\tIEEE80211_HW_HOST_BROADCAST_PS_BUFFERING = 2,\n\tIEEE80211_HW_SIGNAL_UNSPEC = 3,\n\tIEEE80211_HW_SIGNAL_DBM = 4,\n\tIEEE80211_HW_NEED_DTIM_BEFORE_ASSOC = 5,\n\tIEEE80211_HW_SPECTRUM_MGMT = 6,\n\tIEEE80211_HW_AMPDU_AGGREGATION = 7,\n\tIEEE80211_HW_SUPPORTS_PS = 8,\n\tIEEE80211_HW_PS_NULLFUNC_STACK = 9,\n\tIEEE80211_HW_SUPPORTS_DYNAMIC_PS = 10,\n\tIEEE80211_HW_MFP_CAPABLE = 11,\n\tIEEE80211_HW_WANT_MONITOR_VIF = 12,\n\tIEEE80211_HW_NO_AUTO_VIF = 13,\n\tIEEE80211_HW_SW_CRYPTO_CONTROL = 14,\n\tIEEE80211_HW_SUPPORT_FAST_XMIT = 15,\n\tIEEE80211_HW_REPORTS_TX_ACK_STATUS = 16,\n\tIEEE80211_HW_CONNECTION_MONITOR = 17,\n\tIEEE80211_HW_QUEUE_CONTROL = 18,\n\tIEEE80211_HW_SUPPORTS_PER_STA_GTK = 19,\n\tIEEE80211_HW_AP_LINK_PS = 20,\n\tIEEE80211_HW_TX_AMPDU_SETUP_IN_HW = 21,\n\tIEEE80211_HW_SUPPORTS_RC_TABLE = 22,\n\tIEEE80211_HW_P2P_DEV_ADDR_FOR_INTF = 23,\n\tIEEE80211_HW_TIMING_BEACON_ONLY = 24,\n\tIEEE80211_HW_SUPPORTS_HT_CCK_RATES = 25,\n\tIEEE80211_HW_CHANCTX_STA_CSA = 26,\n\tIEEE80211_HW_SUPPORTS_CLONED_SKBS = 27,\n\tIEEE80211_HW_SINGLE_SCAN_ON_ALL_BANDS = 28,\n\tIEEE80211_HW_TDLS_WIDER_BW = 29,\n\tIEEE80211_HW_SUPPORTS_AMSDU_IN_AMPDU = 30,\n\tIEEE80211_HW_BEACON_TX_STATUS = 31,\n\tIEEE80211_HW_NEEDS_UNIQUE_STA_ADDR = 32,\n\tIEEE80211_HW_SUPPORTS_REORDERING_BUFFER = 33,\n\tIEEE80211_HW_USES_RSS = 34,\n\tIEEE80211_HW_TX_AMSDU = 35,\n\tIEEE80211_HW_TX_FRAG_LIST = 36,\n\tIEEE80211_HW_REPORTS_LOW_ACK = 37,\n\tIEEE80211_HW_SUPPORTS_TX_FRAG = 38,\n\tIEEE80211_HW_SUPPORTS_TDLS_BUFFER_STA = 39,\n\tIEEE80211_HW_DEAUTH_NEED_MGD_TX_PREP = 40,\n\tIEEE80211_HW_DOESNT_SUPPORT_QOS_NDP = 41,\n\tIEEE80211_HW_BUFF_MMPDU_TXQ = 42,\n\tIEEE80211_HW_SUPPORTS_VHT_EXT_NSS_BW = 43,\n\tIEEE80211_HW_STA_MMPDU_TXQ = 44,\n\tIEEE80211_HW_TX_STATUS_NO_AMPDU_LEN = 45,\n\tIEEE80211_HW_SUPPORTS_MULTI_BSSID = 46,\n\tIEEE80211_HW_SUPPORTS_ONLY_HE_MULTI_BSSID = 47,\n\tIEEE80211_HW_AMPDU_KEYBORDER_SUPPORT = 48,\n\tNUM_IEEE80211_HW_FLAGS = 49,\n};\n\nstruct ieee80211_hw {\n\tstruct ieee80211_conf conf;\n\tstruct wiphy *wiphy;\n\tconst char *rate_control_algorithm;\n\tvoid *priv;\n\tlong unsigned int flags[1];\n\tunsigned int extra_tx_headroom;\n\tunsigned int extra_beacon_tailroom;\n\tint vif_data_size;\n\tint sta_data_size;\n\tint chanctx_data_size;\n\tint txq_data_size;\n\tu16 queues;\n\tu16 max_listen_interval;\n\ts8 max_signal;\n\tu8 max_rates;\n\tu8 max_report_rates;\n\tu8 max_rate_tries;\n\tu16 max_rx_aggregation_subframes;\n\tu16 max_tx_aggregation_subframes;\n\tu8 max_tx_fragments;\n\tu8 offchannel_tx_hw_queue;\n\tu8 radiotap_mcs_details;\n\tu16 radiotap_vht_details;\n\tstruct {\n\t\tint units_pos;\n\t\ts16 accuracy;\n\t} radiotap_timestamp;\n\tnetdev_features_t netdev_features;\n\tu8 uapsd_queues;\n\tu8 uapsd_max_sp_len;\n\tu8 n_cipher_schemes;\n\tconst struct ieee80211_cipher_scheme *cipher_schemes;\n\tu8 max_nan_de_entries;\n\tu8 tx_sk_pacing_shift;\n\tu8 weight_multiplier;\n\tu32 max_mtu;\n};\n\nstruct ieee80211_scan_request {\n\tstruct ieee80211_scan_ies ies;\n\tstruct cfg80211_scan_request req;\n};\n\nstruct ieee80211_tdls_ch_sw_params {\n\tstruct ieee80211_sta *sta;\n\tstruct cfg80211_chan_def *chandef;\n\tu8 action_code;\n\tu32 status;\n\tu32 timestamp;\n\tu16 switch_time;\n\tu16 switch_timeout;\n\tstruct sk_buff *tmpl_skb;\n\tu32 ch_sw_tm_ie;\n};\n\nenum ieee80211_filter_flags {\n\tFIF_ALLMULTI = 2,\n\tFIF_FCSFAIL = 4,\n\tFIF_PLCPFAIL = 8,\n\tFIF_BCN_PRBRESP_PROMISC = 16,\n\tFIF_CONTROL = 32,\n\tFIF_OTHER_BSS = 64,\n\tFIF_PSPOLL = 128,\n\tFIF_PROBE_REQ = 256,\n\tFIF_MCAST_ACTION = 512,\n};\n\nenum ieee80211_ampdu_mlme_action {\n\tIEEE80211_AMPDU_RX_START = 0,\n\tIEEE80211_AMPDU_RX_STOP = 1,\n\tIEEE80211_AMPDU_TX_START = 2,\n\tIEEE80211_AMPDU_TX_STOP_CONT = 3,\n\tIEEE80211_AMPDU_TX_STOP_FLUSH = 4,\n\tIEEE80211_AMPDU_TX_STOP_FLUSH_CONT = 5,\n\tIEEE80211_AMPDU_TX_OPERATIONAL = 6,\n};\n\nstruct ieee80211_ampdu_params {\n\tenum ieee80211_ampdu_mlme_action action;\n\tstruct ieee80211_sta *sta;\n\tu16 tid;\n\tu16 ssn;\n\tu16 buf_size;\n\tbool amsdu;\n\tu16 timeout;\n};\n\nenum ieee80211_frame_release_type {\n\tIEEE80211_FRAME_RELEASE_PSPOLL = 0,\n\tIEEE80211_FRAME_RELEASE_UAPSD = 1,\n};\n\nenum ieee80211_roc_type {\n\tIEEE80211_ROC_TYPE_NORMAL = 0,\n\tIEEE80211_ROC_TYPE_MGMT_TX = 1,\n};\n\nenum ieee80211_reconfig_type {\n\tIEEE80211_RECONFIG_TYPE_RESTART = 0,\n\tIEEE80211_RECONFIG_TYPE_SUSPEND = 1,\n};\n\nstruct ieee80211_ops {\n\tvoid (*tx)(struct ieee80211_hw *, struct ieee80211_tx_control *, struct sk_buff *);\n\tint (*start)(struct ieee80211_hw *);\n\tvoid (*stop)(struct ieee80211_hw *);\n\tint (*suspend)(struct ieee80211_hw *, struct cfg80211_wowlan *);\n\tint (*resume)(struct ieee80211_hw *);\n\tvoid (*set_wakeup)(struct ieee80211_hw *, bool);\n\tint (*add_interface)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*change_interface)(struct ieee80211_hw *, struct ieee80211_vif *, enum nl80211_iftype, bool);\n\tvoid (*remove_interface)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*config)(struct ieee80211_hw *, u32);\n\tvoid (*bss_info_changed)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_bss_conf *, u32);\n\tint (*start_ap)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tvoid (*stop_ap)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tu64 (*prepare_multicast)(struct ieee80211_hw *, struct netdev_hw_addr_list *);\n\tvoid (*configure_filter)(struct ieee80211_hw *, unsigned int, unsigned int *, u64);\n\tvoid (*config_iface_filter)(struct ieee80211_hw *, struct ieee80211_vif *, unsigned int, unsigned int);\n\tint (*set_tim)(struct ieee80211_hw *, struct ieee80211_sta *, bool);\n\tint (*set_key)(struct ieee80211_hw *, enum set_key_cmd, struct ieee80211_vif *, struct ieee80211_sta *, struct ieee80211_key_conf *);\n\tvoid (*update_tkip_key)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_key_conf *, struct ieee80211_sta *, u32, u16 *);\n\tvoid (*set_rekey_data)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_gtk_rekey_data *);\n\tvoid (*set_default_unicast_key)(struct ieee80211_hw *, struct ieee80211_vif *, int);\n\tint (*hw_scan)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_scan_request *);\n\tvoid (*cancel_hw_scan)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*sched_scan_start)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_sched_scan_request *, struct ieee80211_scan_ies *);\n\tint (*sched_scan_stop)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tvoid (*sw_scan_start)(struct ieee80211_hw *, struct ieee80211_vif *, const u8 *);\n\tvoid (*sw_scan_complete)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*get_stats)(struct ieee80211_hw *, struct ieee80211_low_level_stats *);\n\tvoid (*get_key_seq)(struct ieee80211_hw *, struct ieee80211_key_conf *, struct ieee80211_key_seq *);\n\tint (*set_frag_threshold)(struct ieee80211_hw *, u32);\n\tint (*set_rts_threshold)(struct ieee80211_hw *, u32);\n\tint (*sta_add)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *);\n\tint (*sta_remove)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *);\n\tvoid (*sta_notify)(struct ieee80211_hw *, struct ieee80211_vif *, enum sta_notify_cmd, struct ieee80211_sta *);\n\tint (*sta_set_txpwr)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *);\n\tint (*sta_state)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, enum ieee80211_sta_state, enum ieee80211_sta_state);\n\tvoid (*sta_pre_rcu_remove)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *);\n\tvoid (*sta_rc_update)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, u32);\n\tvoid (*sta_rate_tbl_update)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *);\n\tvoid (*sta_statistics)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, struct station_info *);\n\tint (*conf_tx)(struct ieee80211_hw *, struct ieee80211_vif *, u16, const struct ieee80211_tx_queue_params *);\n\tu64 (*get_tsf)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tvoid (*set_tsf)(struct ieee80211_hw *, struct ieee80211_vif *, u64);\n\tvoid (*offset_tsf)(struct ieee80211_hw *, struct ieee80211_vif *, s64);\n\tvoid (*reset_tsf)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*tx_last_beacon)(struct ieee80211_hw *);\n\tint (*ampdu_action)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_ampdu_params *);\n\tint (*get_survey)(struct ieee80211_hw *, int, struct survey_info *);\n\tvoid (*rfkill_poll)(struct ieee80211_hw *);\n\tvoid (*set_coverage_class)(struct ieee80211_hw *, s16);\n\tvoid (*flush)(struct ieee80211_hw *, struct ieee80211_vif *, u32, bool);\n\tvoid (*channel_switch)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_channel_switch *);\n\tint (*set_antenna)(struct ieee80211_hw *, u32, u32);\n\tint (*get_antenna)(struct ieee80211_hw *, u32 *, u32 *);\n\tint (*remain_on_channel)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_channel *, int, enum ieee80211_roc_type);\n\tint (*cancel_remain_on_channel)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*set_ringparam)(struct ieee80211_hw *, u32, u32);\n\tvoid (*get_ringparam)(struct ieee80211_hw *, u32 *, u32 *, u32 *, u32 *);\n\tbool (*tx_frames_pending)(struct ieee80211_hw *);\n\tint (*set_bitrate_mask)(struct ieee80211_hw *, struct ieee80211_vif *, const struct cfg80211_bitrate_mask *);\n\tvoid (*event_callback)(struct ieee80211_hw *, struct ieee80211_vif *, const struct ieee80211_event *);\n\tvoid (*allow_buffered_frames)(struct ieee80211_hw *, struct ieee80211_sta *, u16, int, enum ieee80211_frame_release_type, bool);\n\tvoid (*release_buffered_frames)(struct ieee80211_hw *, struct ieee80211_sta *, u16, int, enum ieee80211_frame_release_type, bool);\n\tint (*get_et_sset_count)(struct ieee80211_hw *, struct ieee80211_vif *, int);\n\tvoid (*get_et_stats)(struct ieee80211_hw *, struct ieee80211_vif *, struct ethtool_stats *, u64 *);\n\tvoid (*get_et_strings)(struct ieee80211_hw *, struct ieee80211_vif *, u32, u8 *);\n\tvoid (*mgd_prepare_tx)(struct ieee80211_hw *, struct ieee80211_vif *, u16);\n\tvoid (*mgd_protect_tdls_discover)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*add_chanctx)(struct ieee80211_hw *, struct ieee80211_chanctx_conf *);\n\tvoid (*remove_chanctx)(struct ieee80211_hw *, struct ieee80211_chanctx_conf *);\n\tvoid (*change_chanctx)(struct ieee80211_hw *, struct ieee80211_chanctx_conf *, u32);\n\tint (*assign_vif_chanctx)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_chanctx_conf *);\n\tvoid (*unassign_vif_chanctx)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_chanctx_conf *);\n\tint (*switch_vif_chanctx)(struct ieee80211_hw *, struct ieee80211_vif_chanctx_switch *, int, enum ieee80211_chanctx_switch_mode);\n\tvoid (*reconfig_complete)(struct ieee80211_hw *, enum ieee80211_reconfig_type);\n\tvoid (*ipv6_addr_change)(struct ieee80211_hw *, struct ieee80211_vif *, struct inet6_dev *);\n\tvoid (*channel_switch_beacon)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_chan_def *);\n\tint (*pre_channel_switch)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_channel_switch *);\n\tint (*post_channel_switch)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tvoid (*abort_channel_switch)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tvoid (*channel_switch_rx_beacon)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_channel_switch *);\n\tint (*join_ibss)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tvoid (*leave_ibss)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tu32 (*get_expected_throughput)(struct ieee80211_hw *, struct ieee80211_sta *);\n\tint (*get_txpower)(struct ieee80211_hw *, struct ieee80211_vif *, int *);\n\tint (*tdls_channel_switch)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, u8, struct cfg80211_chan_def *, struct sk_buff *, u32);\n\tvoid (*tdls_cancel_channel_switch)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *);\n\tvoid (*tdls_recv_channel_switch)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_tdls_ch_sw_params *);\n\tvoid (*wake_tx_queue)(struct ieee80211_hw *, struct ieee80211_txq *);\n\tvoid (*sync_rx_queues)(struct ieee80211_hw *);\n\tint (*start_nan)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_nan_conf *);\n\tint (*stop_nan)(struct ieee80211_hw *, struct ieee80211_vif *);\n\tint (*nan_change_conf)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_nan_conf *, u32);\n\tint (*add_nan_func)(struct ieee80211_hw *, struct ieee80211_vif *, const struct cfg80211_nan_func *);\n\tvoid (*del_nan_func)(struct ieee80211_hw *, struct ieee80211_vif *, u8);\n\tbool (*can_aggregate_in_amsdu)(struct ieee80211_hw *, struct sk_buff *, struct sk_buff *);\n\tint (*get_ftm_responder_stats)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_ftm_responder_stats *);\n\tint (*start_pmsr)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_pmsr_request *);\n\tvoid (*abort_pmsr)(struct ieee80211_hw *, struct ieee80211_vif *, struct cfg80211_pmsr_request *);\n\tint (*set_tid_config)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, struct cfg80211_tid_config *);\n\tint (*reset_tid_config)(struct ieee80211_hw *, struct ieee80211_vif *, struct ieee80211_sta *, u8);\n};\n\nstruct ieee80211_tpt_blink {\n\tint throughput;\n\tint blink_time;\n};\n\nstruct ieee80211_tx_rate_control {\n\tstruct ieee80211_hw *hw;\n\tstruct ieee80211_supported_band *sband;\n\tstruct ieee80211_bss_conf *bss_conf;\n\tstruct sk_buff *skb;\n\tstruct ieee80211_tx_rate reported_rate;\n\tbool rts;\n\tbool short_preamble;\n\tu32 rate_idx_mask;\n\tu8 *rate_idx_mcs_mask;\n\tbool bss;\n};\n\nenum rate_control_capabilities {\n\tRATE_CTRL_CAPA_VHT_EXT_NSS_BW = 1,\n};\n\nstruct rate_control_ops {\n\tlong unsigned int capa;\n\tconst char *name;\n\tvoid * (*alloc)(struct ieee80211_hw *);\n\tvoid (*add_debugfs)(struct ieee80211_hw *, void *, struct dentry *);\n\tvoid (*free)(void *);\n\tvoid * (*alloc_sta)(void *, struct ieee80211_sta *, gfp_t);\n\tvoid (*rate_init)(void *, struct ieee80211_supported_band *, struct cfg80211_chan_def *, struct ieee80211_sta *, void *);\n\tvoid (*rate_update)(void *, struct ieee80211_supported_band *, struct cfg80211_chan_def *, struct ieee80211_sta *, void *, u32);\n\tvoid (*free_sta)(void *, struct ieee80211_sta *, void *);\n\tvoid (*tx_status_ext)(void *, struct ieee80211_supported_band *, void *, struct ieee80211_tx_status *);\n\tvoid (*tx_status)(void *, struct ieee80211_supported_band *, struct ieee80211_sta *, void *, struct sk_buff *);\n\tvoid (*get_rate)(void *, struct ieee80211_sta *, void *, struct ieee80211_tx_rate_control *);\n\tvoid (*add_sta_debugfs)(void *, void *, struct dentry *);\n\tu32 (*get_expected_throughput)(void *);\n};\n\nstruct fq_tin;\n\nstruct fq_flow {\n\tstruct fq_tin *tin;\n\tstruct list_head flowchain;\n\tstruct list_head backlogchain;\n\tstruct sk_buff_head queue;\n\tu32 backlog;\n\tint deficit;\n};\n\nstruct fq_tin {\n\tstruct list_head new_flows;\n\tstruct list_head old_flows;\n\tu32 backlog_bytes;\n\tu32 backlog_packets;\n\tu32 overlimit;\n\tu32 collisions;\n\tu32 flows;\n\tu32 tx_bytes;\n\tu32 tx_packets;\n};\n\nstruct fq {\n\tstruct fq_flow *flows;\n\tstruct list_head backlogs;\n\tspinlock_t lock;\n\tu32 flows_cnt;\n\tsiphash_key_t perturbation;\n\tu32 limit;\n\tu32 memory_limit;\n\tu32 memory_usage;\n\tu32 quantum;\n\tu32 backlog;\n\tu32 overlimit;\n\tu32 overmemory;\n\tu32 collisions;\n};\n\nenum ieee80211_internal_tkip_state {\n\tTKIP_STATE_NOT_INIT = 0,\n\tTKIP_STATE_PHASE1_DONE = 1,\n\tTKIP_STATE_PHASE1_HW_UPLOADED = 2,\n};\n\nstruct tkip_ctx {\n\tu16 p1k[5];\n\tu32 p1k_iv32;\n\tenum ieee80211_internal_tkip_state state;\n};\n\nstruct tkip_ctx_rx {\n\tstruct tkip_ctx ctx;\n\tu32 iv32;\n\tu16 iv16;\n};\n\nstruct ieee80211_local;\n\nstruct ieee80211_sub_if_data;\n\nstruct sta_info;\n\nstruct ieee80211_key {\n\tstruct ieee80211_local *local;\n\tstruct ieee80211_sub_if_data *sdata;\n\tstruct sta_info *sta;\n\tstruct list_head list;\n\tunsigned int flags;\n\tunion {\n\t\tstruct {\n\t\t\tspinlock_t txlock;\n\t\t\tstruct tkip_ctx tx;\n\t\t\tstruct tkip_ctx_rx rx[16];\n\t\t\tu32 mic_failures;\n\t\t} tkip;\n\t\tstruct {\n\t\t\tu8 rx_pn[102];\n\t\t\tstruct crypto_aead *tfm;\n\t\t\tu32 replays;\n\t\t} ccmp;\n\t\tstruct {\n\t\t\tu8 rx_pn[6];\n\t\t\tstruct crypto_shash *tfm;\n\t\t\tu32 replays;\n\t\t\tu32 icverrors;\n\t\t} aes_cmac;\n\t\tstruct {\n\t\t\tu8 rx_pn[6];\n\t\t\tstruct crypto_aead *tfm;\n\t\t\tu32 replays;\n\t\t\tu32 icverrors;\n\t\t} aes_gmac;\n\t\tstruct {\n\t\t\tu8 rx_pn[102];\n\t\t\tstruct crypto_aead *tfm;\n\t\t\tu32 replays;\n\t\t} gcmp;\n\t\tstruct {\n\t\t\tu8 rx_pn[272];\n\t\t} gen;\n\t} u;\n\tstruct ieee80211_key_conf conf;\n};\n\nenum mac80211_scan_state {\n\tSCAN_DECISION = 0,\n\tSCAN_SET_CHANNEL = 1,\n\tSCAN_SEND_PROBE = 2,\n\tSCAN_SUSPEND = 3,\n\tSCAN_RESUME = 4,\n\tSCAN_ABORT = 5,\n};\n\nstruct rate_control_ref;\n\nstruct tpt_led_trigger;\n\nstruct ieee80211_local {\n\tstruct ieee80211_hw hw;\n\tstruct fq fq;\n\tstruct codel_vars *cvars;\n\tstruct codel_params cparams;\n\tspinlock_t active_txq_lock[4];\n\tstruct list_head active_txqs[4];\n\tu16 schedule_round[4];\n\tu16 airtime_flags;\n\tu32 aql_txq_limit_low[4];\n\tu32 aql_txq_limit_high[4];\n\tu32 aql_threshold;\n\tatomic_t aql_total_pending_airtime;\n\tconst struct ieee80211_ops *ops;\n\tstruct workqueue_struct *workqueue;\n\tlong unsigned int queue_stop_reasons[16];\n\tint q_stop_reasons[160];\n\tspinlock_t queue_stop_reason_lock;\n\tint open_count;\n\tint monitors;\n\tint cooked_mntrs;\n\tint fif_fcsfail;\n\tint fif_plcpfail;\n\tint fif_control;\n\tint fif_other_bss;\n\tint fif_pspoll;\n\tint fif_probe_req;\n\tbool probe_req_reg;\n\tbool rx_mcast_action_reg;\n\tunsigned int filter_flags;\n\tbool wiphy_ciphers_allocated;\n\tbool use_chanctx;\n\tspinlock_t filter_lock;\n\tstruct work_struct reconfig_filter;\n\tstruct netdev_hw_addr_list mc_list;\n\tbool tim_in_locked_section;\n\tbool suspended;\n\tbool resuming;\n\tbool quiescing;\n\tbool started;\n\tbool in_reconfig;\n\tbool wowlan;\n\tstruct work_struct radar_detected_work;\n\tu8 rx_chains;\n\tu8 sband_allocated;\n\tint tx_headroom;\n\tstruct tasklet_struct tasklet;\n\tstruct sk_buff_head skb_queue;\n\tstruct sk_buff_head skb_queue_unreliable;\n\tspinlock_t rx_path_lock;\n\tstruct mutex sta_mtx;\n\tspinlock_t tim_lock;\n\tlong unsigned int num_sta;\n\tstruct list_head sta_list;\n\tstruct rhltable sta_hash;\n\tstruct timer_list sta_cleanup;\n\tint sta_generation;\n\tstruct sk_buff_head pending[16];\n\tstruct tasklet_struct tx_pending_tasklet;\n\tstruct tasklet_struct wake_txqs_tasklet;\n\tatomic_t agg_queue_stop[16];\n\tatomic_t iff_allmultis;\n\tstruct rate_control_ref *rate_ctrl;\n\tstruct arc4_ctx wep_tx_ctx;\n\tstruct arc4_ctx wep_rx_ctx;\n\tu32 wep_iv;\n\tstruct list_head interfaces;\n\tstruct list_head mon_list;\n\tstruct mutex iflist_mtx;\n\tstruct mutex key_mtx;\n\tstruct mutex mtx;\n\tlong unsigned int scanning;\n\tstruct cfg80211_ssid scan_ssid;\n\tstruct cfg80211_scan_request *int_scan_req;\n\tstruct cfg80211_scan_request *scan_req;\n\tstruct ieee80211_scan_request *hw_scan_req;\n\tstruct cfg80211_chan_def scan_chandef;\n\tenum nl80211_band hw_scan_band;\n\tint scan_channel_idx;\n\tint scan_ies_len;\n\tint hw_scan_ies_bufsize;\n\tstruct cfg80211_scan_info scan_info;\n\tstruct work_struct sched_scan_stopped_work;\n\tstruct ieee80211_sub_if_data *sched_scan_sdata;\n\tstruct cfg80211_sched_scan_request *sched_scan_req;\n\tu8 scan_addr[6];\n\tlong unsigned int leave_oper_channel_time;\n\tenum mac80211_scan_state next_scan_state;\n\tstruct delayed_work scan_work;\n\tstruct ieee80211_sub_if_data *scan_sdata;\n\tstruct cfg80211_chan_def _oper_chandef;\n\tstruct ieee80211_channel *tmp_channel;\n\tstruct list_head chanctx_list;\n\tstruct mutex chanctx_mtx;\n\tstruct led_trigger tx_led;\n\tstruct led_trigger rx_led;\n\tstruct led_trigger assoc_led;\n\tstruct led_trigger radio_led;\n\tstruct led_trigger tpt_led;\n\tatomic_t tx_led_active;\n\tatomic_t rx_led_active;\n\tatomic_t assoc_led_active;\n\tatomic_t radio_led_active;\n\tatomic_t tpt_led_active;\n\tstruct tpt_led_trigger *tpt_led_trigger;\n\tint total_ps_buffered;\n\tbool pspolling;\n\tbool offchannel_ps_enabled;\n\tstruct ieee80211_sub_if_data *ps_sdata;\n\tstruct work_struct dynamic_ps_enable_work;\n\tstruct work_struct dynamic_ps_disable_work;\n\tstruct timer_list dynamic_ps_timer;\n\tstruct notifier_block ifa_notifier;\n\tstruct notifier_block ifa6_notifier;\n\tint dynamic_ps_forced_timeout;\n\tint user_power_level;\n\tenum ieee80211_smps_mode smps_mode;\n\tstruct work_struct restart_work;\n\tstruct delayed_work roc_work;\n\tstruct list_head roc_list;\n\tstruct work_struct hw_roc_start;\n\tstruct work_struct hw_roc_done;\n\tlong unsigned int hw_roc_start_time;\n\tu64 roc_cookie_counter;\n\tstruct idr ack_status_frames;\n\tspinlock_t ack_status_lock;\n\tstruct ieee80211_sub_if_data *p2p_sdata;\n\tstruct ieee80211_sub_if_data *monitor_sdata;\n\tstruct cfg80211_chan_def monitor_chandef;\n\tu8 ext_capa[8];\n\tstruct work_struct tdls_chsw_work;\n\tstruct sk_buff_head skb_queue_tdls_chsw;\n};\n\nstruct ieee80211_fragment_entry {\n\tstruct sk_buff_head skb_list;\n\tlong unsigned int first_frag_time;\n\tu16 seq;\n\tu16 extra_len;\n\tu16 last_frag;\n\tu8 rx_queue;\n\tbool check_sequential_pn;\n\tu8 last_pn[6];\n};\n\nstruct ps_data {\n\tu8 tim[256];\n\tstruct sk_buff_head bc_buf;\n\tatomic_t num_sta_ps;\n\tint dtim_count;\n\tbool dtim_bc_mc;\n};\n\nstruct beacon_data;\n\nstruct probe_resp;\n\nstruct ieee80211_if_ap {\n\tstruct beacon_data *beacon;\n\tstruct probe_resp *probe_resp;\n\tstruct cfg80211_beacon_data *next_beacon;\n\tstruct list_head vlans;\n\tstruct ps_data ps;\n\tatomic_t num_mcast_sta;\n\tbool multicast_to_unicast;\n};\n\nstruct ieee80211_if_wds {\n\tstruct sta_info *sta;\n\tu8 remote_addr[6];\n};\n\nstruct ieee80211_if_vlan {\n\tstruct list_head list;\n\tstruct sta_info *sta;\n\tatomic_t num_mcast_sta;\n};\n\nstruct ewma_beacon_signal {\n\tlong unsigned int internal;\n};\n\nstruct ieee80211_sta_tx_tspec {\n\tlong unsigned int time_slice_start;\n\tu32 admitted_time;\n\tu8 tsid;\n\ts8 up;\n\tu32 consumed_tx_time;\n\tenum {\n\t\tTX_TSPEC_ACTION_NONE = 0,\n\t\tTX_TSPEC_ACTION_DOWNGRADE = 1,\n\t\tTX_TSPEC_ACTION_STOP_DOWNGRADE = 2,\n\t} action;\n\tbool downgraded;\n};\n\nstruct ieee80211_mgd_auth_data;\n\nstruct ieee80211_mgd_assoc_data;\n\nstruct ieee80211_if_managed {\n\tstruct timer_list timer;\n\tstruct timer_list conn_mon_timer;\n\tstruct timer_list bcn_mon_timer;\n\tstruct timer_list chswitch_timer;\n\tstruct work_struct monitor_work;\n\tstruct work_struct chswitch_work;\n\tstruct work_struct beacon_connection_loss_work;\n\tstruct work_struct csa_connection_drop_work;\n\tlong unsigned int beacon_timeout;\n\tlong unsigned int probe_timeout;\n\tint probe_send_count;\n\tbool nullfunc_failed;\n\tbool connection_loss;\n\tshort: 16;\n\tstruct cfg80211_bss *associated;\n\tstruct ieee80211_mgd_auth_data *auth_data;\n\tstruct ieee80211_mgd_assoc_data *assoc_data;\n\tu8 bssid[6];\n\tbool powersave;\n\tbool broken_ap;\n\tbool have_beacon;\n\tu8 dtim_period;\n\tshort: 16;\n\tenum ieee80211_smps_mode req_smps;\n\tenum ieee80211_smps_mode driver_smps_mode;\n\tint: 32;\n\tstruct work_struct request_smps_work;\n\tunsigned int flags;\n\tbool csa_waiting_bcn;\n\tbool csa_ignored_same_chan;\n\tbool beacon_crc_valid;\n\tchar: 8;\n\tu32 beacon_crc;\n\tbool status_acked;\n\tbool status_received;\n\t__le16 status_fc;\n\tenum {\n\t\tIEEE80211_MFP_DISABLED = 0,\n\t\tIEEE80211_MFP_OPTIONAL = 1,\n\t\tIEEE80211_MFP_REQUIRED = 2,\n\t} mfp;\n\tunsigned int uapsd_queues;\n\tunsigned int uapsd_max_sp_len;\n\tint wmm_last_param_set;\n\tint mu_edca_last_param_set;\n\tu8 use_4addr;\n\tchar: 8;\n\ts16 p2p_noa_index;\n\tstruct ewma_beacon_signal ave_beacon_signal;\n\tunsigned int count_beacon_signal;\n\tunsigned int beacon_loss_count;\n\tint last_cqm_event_signal;\n\tint rssi_min_thold;\n\tint rssi_max_thold;\n\tint last_ave_beacon_signal;\n\tstruct ieee80211_ht_cap ht_capa;\n\tstruct ieee80211_ht_cap ht_capa_mask;\n\tstruct ieee80211_vht_cap vht_capa;\n\tstruct ieee80211_vht_cap vht_capa_mask;\n\tu8 tdls_peer[6];\n\tlong: 48;\n\tstruct delayed_work tdls_peer_del_work;\n\tstruct sk_buff *orig_teardown_skb;\n\tstruct sk_buff *teardown_skb;\n\tspinlock_t teardown_lock;\n\tbool tdls_chan_switch_prohibited;\n\tbool tdls_wider_bw_prohibited;\n\tshort: 16;\n\tstruct ieee80211_sta_tx_tspec tx_tspec[4];\n\tstruct delayed_work tx_tspec_wk;\n\tu8 *assoc_req_ies;\n\tsize_t assoc_req_ies_len;\n} __attribute__((packed));\n\nstruct ieee80211_if_ibss {\n\tstruct timer_list timer;\n\tstruct work_struct csa_connection_drop_work;\n\tlong unsigned int last_scan_completed;\n\tu32 basic_rates;\n\tbool fixed_bssid;\n\tbool fixed_channel;\n\tbool privacy;\n\tbool control_port;\n\tbool userspace_handles_dfs;\n\tchar: 8;\n\tu8 bssid[6];\n\tu8 ssid[32];\n\tu8 ssid_len;\n\tu8 ie_len;\n\tlong: 48;\n\tu8 *ie;\n\tstruct cfg80211_chan_def chandef;\n\tlong unsigned int ibss_join_req;\n\tstruct beacon_data *presp;\n\tstruct ieee80211_ht_cap ht_capa;\n\tstruct ieee80211_ht_cap ht_capa_mask;\n\tspinlock_t incomplete_lock;\n\tstruct list_head incomplete_stations;\n\tenum {\n\t\tIEEE80211_IBSS_MLME_SEARCH = 0,\n\t\tIEEE80211_IBSS_MLME_JOINED = 1,\n\t} state;\n\tint: 32;\n} __attribute__((packed));\n\nstruct mesh_preq_queue {\n\tstruct list_head list;\n\tu8 dst[6];\n\tu8 flags;\n};\n\nstruct mesh_stats {\n\t__u32 fwded_mcast;\n\t__u32 fwded_unicast;\n\t__u32 fwded_frames;\n\t__u32 dropped_frames_ttl;\n\t__u32 dropped_frames_no_route;\n\t__u32 dropped_frames_congestion;\n};\n\nstruct mesh_rmc;\n\nstruct ieee80211_mesh_sync_ops;\n\nstruct mesh_csa_settings;\n\nstruct mesh_table;\n\nstruct ieee80211_if_mesh {\n\tstruct timer_list housekeeping_timer;\n\tstruct timer_list mesh_path_timer;\n\tstruct timer_list mesh_path_root_timer;\n\tlong unsigned int wrkq_flags;\n\tlong unsigned int mbss_changed;\n\tbool userspace_handles_dfs;\n\tu8 mesh_id[32];\n\tsize_t mesh_id_len;\n\tu8 mesh_pp_id;\n\tu8 mesh_pm_id;\n\tu8 mesh_cc_id;\n\tu8 mesh_sp_id;\n\tu8 mesh_auth_id;\n\tu32 sn;\n\tu32 preq_id;\n\tatomic_t mpaths;\n\tlong unsigned int last_sn_update;\n\tlong unsigned int next_perr;\n\tlong unsigned int last_preq;\n\tstruct mesh_rmc *rmc;\n\tspinlock_t mesh_preq_queue_lock;\n\tstruct mesh_preq_queue preq_queue;\n\tint preq_queue_len;\n\tstruct mesh_stats mshstats;\n\tstruct mesh_config mshcfg;\n\tatomic_t estab_plinks;\n\tu32 mesh_seqnum;\n\tbool accepting_plinks;\n\tint num_gates;\n\tstruct beacon_data *beacon;\n\tconst u8 *ie;\n\tu8 ie_len;\n\tenum {\n\t\tIEEE80211_MESH_SEC_NONE = 0,\n\t\tIEEE80211_MESH_SEC_AUTHED = 1,\n\t\tIEEE80211_MESH_SEC_SECURED = 2,\n\t} security;\n\tbool user_mpm;\n\tconst struct ieee80211_mesh_sync_ops *sync_ops;\n\ts64 sync_offset_clockdrift_max;\n\tspinlock_t sync_offset_lock;\n\tenum nl80211_mesh_power_mode nonpeer_pm;\n\tint ps_peers_light_sleep;\n\tint ps_peers_deep_sleep;\n\tstruct ps_data ps;\n\tstruct mesh_csa_settings *csa;\n\tenum {\n\t\tIEEE80211_MESH_CSA_ROLE_NONE = 0,\n\t\tIEEE80211_MESH_CSA_ROLE_INIT = 1,\n\t\tIEEE80211_MESH_CSA_ROLE_REPEATER = 2,\n\t} csa_role;\n\tu8 chsw_ttl;\n\tu16 pre_value;\n\tint meshconf_offset;\n\tstruct mesh_table *mesh_paths;\n\tstruct mesh_table *mpp_paths;\n\tint mesh_paths_generation;\n\tint mpp_paths_generation;\n};\n\nstruct ieee80211_if_ocb {\n\tstruct timer_list housekeeping_timer;\n\tlong unsigned int wrkq_flags;\n\tspinlock_t incomplete_lock;\n\tstruct list_head incomplete_stations;\n\tbool joined;\n};\n\nstruct ieee80211_if_mntr {\n\tu32 flags;\n\tu8 mu_follow_addr[6];\n\tstruct list_head list;\n};\n\nstruct ieee80211_if_nan {\n\tstruct cfg80211_nan_conf conf;\n\tspinlock_t func_lock;\n\tstruct idr function_inst_ids;\n};\n\nstruct mac80211_qos_map;\n\nstruct ieee80211_chanctx;\n\nstruct ieee80211_sub_if_data {\n\tstruct list_head list;\n\tstruct wireless_dev wdev;\n\tstruct list_head key_list;\n\tint crypto_tx_tailroom_needed_cnt;\n\tint crypto_tx_tailroom_pending_dec;\n\tstruct delayed_work dec_tailroom_needed_wk;\n\tstruct net_device *dev;\n\tstruct ieee80211_local *local;\n\tunsigned int flags;\n\tlong unsigned int state;\n\tchar name[16];\n\tstruct ieee80211_fragment_entry fragments[4];\n\tunsigned int fragment_next;\n\tu16 noack_map;\n\tu8 wmm_acm;\n\tstruct ieee80211_key *keys[8];\n\tstruct ieee80211_key *default_unicast_key;\n\tstruct ieee80211_key *default_multicast_key;\n\tstruct ieee80211_key *default_mgmt_key;\n\tstruct ieee80211_key *default_beacon_key;\n\tu16 sequence_number;\n\t__be16 control_port_protocol;\n\tbool control_port_no_encrypt;\n\tbool control_port_no_preauth;\n\tbool control_port_over_nl80211;\n\tint encrypt_headroom;\n\tatomic_t num_tx_queued;\n\tstruct ieee80211_tx_queue_params tx_conf[4];\n\tstruct mac80211_qos_map *qos_map;\n\tstruct work_struct csa_finalize_work;\n\tbool csa_block_tx;\n\tstruct cfg80211_chan_def csa_chandef;\n\tstruct list_head assigned_chanctx_list;\n\tstruct list_head reserved_chanctx_list;\n\tstruct ieee80211_chanctx *reserved_chanctx;\n\tstruct cfg80211_chan_def reserved_chandef;\n\tbool reserved_radar_required;\n\tbool reserved_ready;\n\tstruct work_struct recalc_smps;\n\tstruct work_struct work;\n\tstruct sk_buff_head skb_queue;\n\tu8 needed_rx_chains;\n\tenum ieee80211_smps_mode smps_mode;\n\tint user_power_level;\n\tint ap_power_level;\n\tbool radar_required;\n\tstruct delayed_work dfs_cac_timer_work;\n\tstruct ieee80211_if_ap *bss;\n\tu32 rc_rateidx_mask[4];\n\tbool rc_has_mcs_mask[4];\n\tu8 rc_rateidx_mcs_mask[40];\n\tbool rc_has_vht_mcs_mask[4];\n\tu16 rc_rateidx_vht_mcs_mask[32];\n\tu32 beacon_rateidx_mask[4];\n\tbool beacon_rate_set;\n\tunion {\n\t\tstruct ieee80211_if_ap ap;\n\t\tstruct ieee80211_if_wds wds;\n\t\tstruct ieee80211_if_vlan vlan;\n\t\tstruct ieee80211_if_managed mgd;\n\t\tstruct ieee80211_if_ibss ibss;\n\t\tstruct ieee80211_if_mesh mesh;\n\t\tstruct ieee80211_if_ocb ocb;\n\t\tstruct ieee80211_if_mntr mntr;\n\t\tstruct ieee80211_if_nan nan;\n\t} u;\n\tbool hw_80211_encap;\n\tstruct ieee80211_vif vif;\n};\n\nstruct ieee80211_sta_rx_stats {\n\tlong unsigned int packets;\n\tlong unsigned int last_rx;\n\tlong unsigned int num_duplicates;\n\tlong unsigned int fragments;\n\tlong unsigned int dropped;\n\tint last_signal;\n\tu8 chains;\n\ts8 chain_signal_last[4];\n\tu32 last_rate;\n\tstruct u64_stats_sync syncp;\n\tu64 bytes;\n\tu64 msdu[17];\n};\n\nstruct ewma_signal {\n\tlong unsigned int internal;\n};\n\nstruct ewma_avg_signal {\n\tlong unsigned int internal;\n};\n\nstruct airtime_info {\n\tu64 rx_airtime;\n\tu64 tx_airtime;\n\ts64 deficit;\n\tatomic_t aql_tx_pending;\n\tu32 aql_limit_low;\n\tu32 aql_limit_high;\n};\n\nstruct tid_ampdu_rx;\n\nstruct tid_ampdu_tx;\n\nstruct sta_ampdu_mlme {\n\tstruct mutex mtx;\n\tstruct tid_ampdu_rx *tid_rx[16];\n\tu8 tid_rx_token[16];\n\tlong unsigned int tid_rx_timer_expired[1];\n\tlong unsigned int tid_rx_stop_requested[1];\n\tlong unsigned int tid_rx_manage_offl[1];\n\tlong unsigned int agg_session_valid[1];\n\tlong unsigned int unexpected_agg[1];\n\tstruct work_struct work;\n\tstruct tid_ampdu_tx *tid_tx[16];\n\tstruct tid_ampdu_tx *tid_start_tx[16];\n\tlong unsigned int last_addba_req_time[16];\n\tu8 addba_req_num[16];\n\tu8 dialog_token_allocator;\n};\n\nstruct ieee80211_fast_tx;\n\nstruct ieee80211_fast_rx;\n\nstruct sta_info {\n\tstruct list_head list;\n\tstruct list_head free_list;\n\tstruct callback_head callback_head;\n\tstruct rhlist_head hash_node;\n\tu8 addr[6];\n\tstruct ieee80211_local *local;\n\tstruct ieee80211_sub_if_data *sdata;\n\tstruct ieee80211_key *gtk[8];\n\tstruct ieee80211_key *ptk[4];\n\tu8 ptk_idx;\n\tstruct rate_control_ref *rate_ctrl;\n\tvoid *rate_ctrl_priv;\n\tspinlock_t rate_ctrl_lock;\n\tspinlock_t lock;\n\tstruct ieee80211_fast_tx *fast_tx;\n\tstruct ieee80211_fast_rx *fast_rx;\n\tstruct ieee80211_sta_rx_stats *pcpu_rx_stats;\n\tstruct work_struct drv_deliver_wk;\n\tu16 listen_interval;\n\tbool dead;\n\tbool removed;\n\tbool uploaded;\n\tenum ieee80211_sta_state sta_state;\n\tlong unsigned int _flags;\n\tspinlock_t ps_lock;\n\tstruct sk_buff_head ps_tx_buf[4];\n\tstruct sk_buff_head tx_filtered[4];\n\tlong unsigned int driver_buffered_tids;\n\tlong unsigned int txq_buffered_tids;\n\tu64 assoc_at;\n\tlong int last_connected;\n\tstruct ieee80211_sta_rx_stats rx_stats;\n\tstruct {\n\t\tstruct ewma_signal signal;\n\t\tstruct ewma_signal chain_signal[4];\n\t} rx_stats_avg;\n\t__le16 last_seq_ctrl[17];\n\tstruct {\n\t\tlong unsigned int filtered;\n\t\tlong unsigned int retry_failed;\n\t\tlong unsigned int retry_count;\n\t\tunsigned int lost_packets;\n\t\tlong unsigned int last_tdls_pkt_time;\n\t\tu64 msdu_retries[17];\n\t\tu64 msdu_failed[17];\n\t\tlong unsigned int last_ack;\n\t\ts8 last_ack_signal;\n\t\tbool ack_signal_filled;\n\t\tstruct ewma_avg_signal avg_ack_signal;\n\t} status_stats;\n\tstruct {\n\t\tu64 packets[4];\n\t\tu64 bytes[4];\n\t\tstruct ieee80211_tx_rate last_rate;\n\t\tu64 msdu[17];\n\t} tx_stats;\n\tu16 tid_seq[16];\n\tstruct airtime_info airtime[4];\n\tu16 airtime_weight;\n\tstruct sta_ampdu_mlme ampdu_mlme;\n\tenum ieee80211_sta_rx_bandwidth cur_max_bandwidth;\n\tenum ieee80211_smps_mode known_smps_mode;\n\tconst struct ieee80211_cipher_scheme *cipher_scheme;\n\tstruct codel_params cparams;\n\tu8 reserved_tid;\n\tstruct cfg80211_chan_def tdls_chandef;\n\tstruct ieee80211_sta sta;\n};\n\nstruct tid_ampdu_tx {\n\tstruct callback_head callback_head;\n\tstruct timer_list session_timer;\n\tstruct timer_list addba_resp_timer;\n\tstruct sk_buff_head pending;\n\tstruct sta_info *sta;\n\tlong unsigned int state;\n\tlong unsigned int last_tx;\n\tu16 timeout;\n\tu8 dialog_token;\n\tu8 stop_initiator;\n\tbool tx_stop;\n\tu16 buf_size;\n\tu16 failed_bar_ssn;\n\tbool bar_pending;\n\tbool amsdu;\n\tu8 tid;\n};\n\nstruct tid_ampdu_rx {\n\tstruct callback_head callback_head;\n\tspinlock_t reorder_lock;\n\tu64 reorder_buf_filtered;\n\tstruct sk_buff_head *reorder_buf;\n\tlong unsigned int *reorder_time;\n\tstruct sta_info *sta;\n\tstruct timer_list session_timer;\n\tstruct timer_list reorder_timer;\n\tlong unsigned int last_rx;\n\tu16 head_seq_num;\n\tu16 stored_mpdu_num;\n\tu16 ssn;\n\tu16 buf_size;\n\tu16 timeout;\n\tu8 tid;\n\tu8 auto_seq: 1;\n\tu8 removed: 1;\n\tu8 started: 1;\n};\n\nstruct ieee80211_fast_tx {\n\tstruct ieee80211_key *key;\n\tu8 hdr_len;\n\tu8 sa_offs;\n\tu8 da_offs;\n\tu8 pn_offs;\n\tu8 band;\n\tchar: 8;\n\tu8 hdr[56];\n\tstruct callback_head callback_head;\n};\n\nstruct ieee80211_fast_rx {\n\tstruct net_device *dev;\n\tenum nl80211_iftype vif_type;\n\tu8 vif_addr[6];\n\tu8 rfc1042_hdr[6];\n\t__be16 control_port_protocol;\n\t__le16 expected_ds_bits;\n\tu8 icv_len;\n\tu8 key: 1;\n\tu8 sta_notify: 1;\n\tu8 internal_forward: 1;\n\tu8 uses_rss: 1;\n\tu8 da_offs;\n\tu8 sa_offs;\n\tstruct callback_head callback_head;\n};\n\nstruct rate_control_ref {\n\tconst struct rate_control_ops *ops;\n\tvoid *priv;\n};\n\nstruct beacon_data {\n\tu8 *head;\n\tu8 *tail;\n\tint head_len;\n\tint tail_len;\n\tstruct ieee80211_meshconf_ie *meshconf;\n\tu16 csa_counter_offsets[2];\n\tu8 csa_current_counter;\n\tstruct callback_head callback_head;\n};\n\nstruct probe_resp {\n\tstruct callback_head callback_head;\n\tint len;\n\tu16 csa_counter_offsets[2];\n\tu8 data[0];\n};\n\nstruct ieee80211_mgd_auth_data {\n\tstruct cfg80211_bss *bss;\n\tlong unsigned int timeout;\n\tint tries;\n\tu16 algorithm;\n\tu16 expected_transaction;\n\tu8 key[13];\n\tu8 key_len;\n\tu8 key_idx;\n\tbool done;\n\tbool peer_confirmed;\n\tbool timeout_started;\n\tu16 sae_trans;\n\tu16 sae_status;\n\tsize_t data_len;\n\tu8 data[0];\n};\n\nstruct ieee80211_mgd_assoc_data {\n\tstruct cfg80211_bss *bss;\n\tconst u8 *supp_rates;\n\tlong unsigned int timeout;\n\tint tries;\n\tu16 capability;\n\tu8 prev_bssid[6];\n\tu8 ssid[32];\n\tu8 ssid_len;\n\tu8 supp_rates_len;\n\tbool wmm;\n\tbool uapsd;\n\tbool need_beacon;\n\tbool synced;\n\tbool timeout_started;\n\tu8 ap_ht_param;\n\tstruct ieee80211_vht_cap ap_vht_cap;\n\tu8 fils_nonces[32];\n\tu8 fils_kek[64];\n\tsize_t fils_kek_len;\n\tsize_t ie_len;\n\tu8 ie[0];\n};\n\nstruct ieee802_11_elems;\n\nstruct ieee80211_mesh_sync_ops {\n\tvoid (*rx_bcn_presp)(struct ieee80211_sub_if_data *, u16, struct ieee80211_mgmt *, struct ieee802_11_elems *, struct ieee80211_rx_status *);\n\tvoid (*adjust_tsf)(struct ieee80211_sub_if_data *, struct beacon_data *);\n};\n\nstruct ieee802_11_elems {\n\tconst u8 *ie_start;\n\tsize_t total_len;\n\tconst struct ieee80211_tdls_lnkie *lnk_id;\n\tconst struct ieee80211_ch_switch_timing *ch_sw_timing;\n\tconst u8 *ext_capab;\n\tconst u8 *ssid;\n\tconst u8 *supp_rates;\n\tconst u8 *ds_params;\n\tconst struct ieee80211_tim_ie *tim;\n\tconst u8 *challenge;\n\tconst u8 *rsn;\n\tconst u8 *rsnx;\n\tconst u8 *erp_info;\n\tconst u8 *ext_supp_rates;\n\tconst u8 *wmm_info;\n\tconst u8 *wmm_param;\n\tconst struct ieee80211_ht_cap *ht_cap_elem;\n\tconst struct ieee80211_ht_operation *ht_operation;\n\tconst struct ieee80211_vht_cap *vht_cap_elem;\n\tconst struct ieee80211_vht_operation *vht_operation;\n\tconst struct ieee80211_meshconf_ie *mesh_config;\n\tconst u8 *he_cap;\n\tconst struct ieee80211_he_operation *he_operation;\n\tconst struct ieee80211_he_spr *he_spr;\n\tconst struct ieee80211_mu_edca_param_set *mu_edca_param_set;\n\tconst struct ieee80211_he_6ghz_capa *he_6ghz_capa;\n\tconst u8 *uora_element;\n\tconst u8 *mesh_id;\n\tconst u8 *peering;\n\tconst __le16 *awake_window;\n\tconst u8 *preq;\n\tconst u8 *prep;\n\tconst u8 *perr;\n\tconst struct ieee80211_rann_ie *rann;\n\tconst struct ieee80211_channel_sw_ie *ch_switch_ie;\n\tconst struct ieee80211_ext_chansw_ie *ext_chansw_ie;\n\tconst struct ieee80211_wide_bw_chansw_ie *wide_bw_chansw_ie;\n\tconst u8 *max_channel_switch_time;\n\tconst u8 *country_elem;\n\tconst u8 *pwr_constr_elem;\n\tconst u8 *cisco_dtpc_elem;\n\tconst struct ieee80211_timeout_interval_ie *timeout_int;\n\tconst u8 *opmode_notif;\n\tconst struct ieee80211_sec_chan_offs_ie *sec_chan_offs;\n\tstruct ieee80211_mesh_chansw_params_ie *mesh_chansw_params_ie;\n\tconst struct ieee80211_bss_max_idle_period_ie *max_idle_period_ie;\n\tconst struct ieee80211_multiple_bssid_configuration *mbssid_config_ie;\n\tconst struct ieee80211_bssid_index *bssid_index;\n\tu8 max_bssid_indicator;\n\tu8 dtim_count;\n\tu8 dtim_period;\n\tconst struct ieee80211_addba_ext_ie *addba_ext_ie;\n\tu8 ext_capab_len;\n\tu8 ssid_len;\n\tu8 supp_rates_len;\n\tu8 tim_len;\n\tu8 challenge_len;\n\tu8 rsn_len;\n\tu8 rsnx_len;\n\tu8 ext_supp_rates_len;\n\tu8 wmm_info_len;\n\tu8 wmm_param_len;\n\tu8 he_cap_len;\n\tu8 mesh_id_len;\n\tu8 peering_len;\n\tu8 preq_len;\n\tu8 prep_len;\n\tu8 perr_len;\n\tu8 country_elem_len;\n\tu8 bssid_index_len;\n\tbool parse_error;\n};\n\nstruct mesh_csa_settings {\n\tstruct callback_head callback_head;\n\tstruct cfg80211_csa_settings settings;\n};\n\nstruct mesh_rmc {\n\tstruct hlist_head bucket[256];\n\tu32 idx_mask;\n};\n\nstruct mesh_table {\n\tstruct hlist_head known_gates;\n\tspinlock_t gates_lock;\n\tstruct rhashtable rhead;\n\tstruct hlist_head walk_head;\n\tspinlock_t walk_lock;\n\tatomic_t entries;\n};\n\nenum ieee80211_sub_if_data_flags {\n\tIEEE80211_SDATA_ALLMULTI = 1,\n\tIEEE80211_SDATA_OPERATING_GMODE = 4,\n\tIEEE80211_SDATA_DONT_BRIDGE_PACKETS = 8,\n\tIEEE80211_SDATA_DISCONNECT_RESUME = 16,\n\tIEEE80211_SDATA_IN_DRIVER = 32,\n};\n\nenum ieee80211_chanctx_mode {\n\tIEEE80211_CHANCTX_SHARED = 0,\n\tIEEE80211_CHANCTX_EXCLUSIVE = 1,\n};\n\nenum ieee80211_chanctx_replace_state {\n\tIEEE80211_CHANCTX_REPLACE_NONE = 0,\n\tIEEE80211_CHANCTX_WILL_BE_REPLACED = 1,\n\tIEEE80211_CHANCTX_REPLACES_OTHER = 2,\n};\n\nstruct ieee80211_chanctx {\n\tstruct list_head list;\n\tstruct callback_head callback_head;\n\tstruct list_head assigned_vifs;\n\tstruct list_head reserved_vifs;\n\tenum ieee80211_chanctx_replace_state replace_state;\n\tstruct ieee80211_chanctx *replace_ctx;\n\tenum ieee80211_chanctx_mode mode;\n\tbool driver_present;\n\tstruct ieee80211_chanctx_conf conf;\n};\n\nstruct mac80211_qos_map {\n\tstruct cfg80211_qos_map qos_map;\n\tstruct callback_head callback_head;\n};\n\nenum {\n\tIEEE80211_RX_MSG = 1,\n\tIEEE80211_TX_STATUS_MSG = 2,\n};\n\nenum queue_stop_reason {\n\tIEEE80211_QUEUE_STOP_REASON_DRIVER = 0,\n\tIEEE80211_QUEUE_STOP_REASON_PS = 1,\n\tIEEE80211_QUEUE_STOP_REASON_CSA = 2,\n\tIEEE80211_QUEUE_STOP_REASON_AGGREGATION = 3,\n\tIEEE80211_QUEUE_STOP_REASON_SUSPEND = 4,\n\tIEEE80211_QUEUE_STOP_REASON_SKB_ADD = 5,\n\tIEEE80211_QUEUE_STOP_REASON_OFFCHANNEL = 6,\n\tIEEE80211_QUEUE_STOP_REASON_FLUSH = 7,\n\tIEEE80211_QUEUE_STOP_REASON_TDLS_TEARDOWN = 8,\n\tIEEE80211_QUEUE_STOP_REASON_RESERVE_TID = 9,\n\tIEEE80211_QUEUE_STOP_REASONS = 10,\n};\n\nstruct tpt_led_trigger {\n\tchar name[32];\n\tconst struct ieee80211_tpt_blink *blink_table;\n\tunsigned int blink_table_len;\n\tstruct timer_list timer;\n\tstruct ieee80211_local *local;\n\tlong unsigned int prev_traffic;\n\tlong unsigned int tx_bytes;\n\tlong unsigned int rx_bytes;\n\tunsigned int active;\n\tunsigned int want;\n\tbool running;\n};\n\nenum {\n\tSCAN_SW_SCANNING = 0,\n\tSCAN_HW_SCANNING = 1,\n\tSCAN_ONCHANNEL_SCANNING = 2,\n\tSCAN_COMPLETED = 3,\n\tSCAN_ABORTED = 4,\n\tSCAN_HW_CANCELLED = 5,\n};\n\nstruct ieee80211_bar {\n\t__le16 frame_control;\n\t__le16 duration;\n\t__u8 ra[6];\n\t__u8 ta[6];\n\t__le16 control;\n\t__le16 start_seq_num;\n};\n\nenum ieee80211_ht_actioncode {\n\tWLAN_HT_ACTION_NOTIFY_CHANWIDTH = 0,\n\tWLAN_HT_ACTION_SMPS = 1,\n\tWLAN_HT_ACTION_PSMP = 2,\n\tWLAN_HT_ACTION_PCO_PHASE = 3,\n\tWLAN_HT_ACTION_CSI = 4,\n\tWLAN_HT_ACTION_NONCOMPRESSED_BF = 5,\n\tWLAN_HT_ACTION_COMPRESSED_BF = 6,\n\tWLAN_HT_ACTION_ASEL_IDX_FEEDBACK = 7,\n};\n\nenum ieee80211_tdls_actioncode {\n\tWLAN_TDLS_SETUP_REQUEST = 0,\n\tWLAN_TDLS_SETUP_RESPONSE = 1,\n\tWLAN_TDLS_SETUP_CONFIRM = 2,\n\tWLAN_TDLS_TEARDOWN = 3,\n\tWLAN_TDLS_PEER_TRAFFIC_INDICATION = 4,\n\tWLAN_TDLS_CHANNEL_SWITCH_REQUEST = 5,\n\tWLAN_TDLS_CHANNEL_SWITCH_RESPONSE = 6,\n\tWLAN_TDLS_PEER_PSM_REQUEST = 7,\n\tWLAN_TDLS_PEER_PSM_RESPONSE = 8,\n\tWLAN_TDLS_PEER_TRAFFIC_RESPONSE = 9,\n\tWLAN_TDLS_DISCOVERY_REQUEST = 10,\n};\n\nenum ieee80211_radiotap_tx_flags {\n\tIEEE80211_RADIOTAP_F_TX_FAIL = 1,\n\tIEEE80211_RADIOTAP_F_TX_CTS = 2,\n\tIEEE80211_RADIOTAP_F_TX_RTS = 4,\n\tIEEE80211_RADIOTAP_F_TX_NOACK = 8,\n};\n\nenum ieee80211_radiotap_mcs_flags {\n\tIEEE80211_RADIOTAP_MCS_BW_MASK = 3,\n\tIEEE80211_RADIOTAP_MCS_BW_20 = 0,\n\tIEEE80211_RADIOTAP_MCS_BW_40 = 1,\n\tIEEE80211_RADIOTAP_MCS_BW_20L = 2,\n\tIEEE80211_RADIOTAP_MCS_BW_20U = 3,\n\tIEEE80211_RADIOTAP_MCS_SGI = 4,\n\tIEEE80211_RADIOTAP_MCS_FMT_GF = 8,\n\tIEEE80211_RADIOTAP_MCS_FEC_LDPC = 16,\n\tIEEE80211_RADIOTAP_MCS_STBC_MASK = 96,\n\tIEEE80211_RADIOTAP_MCS_STBC_1 = 1,\n\tIEEE80211_RADIOTAP_MCS_STBC_2 = 2,\n\tIEEE80211_RADIOTAP_MCS_STBC_3 = 3,\n\tIEEE80211_RADIOTAP_MCS_STBC_SHIFT = 5,\n};\n\nenum ieee80211_radiotap_vht_flags {\n\tIEEE80211_RADIOTAP_VHT_FLAG_STBC = 1,\n\tIEEE80211_RADIOTAP_VHT_FLAG_TXOP_PS_NA = 2,\n\tIEEE80211_RADIOTAP_VHT_FLAG_SGI = 4,\n\tIEEE80211_RADIOTAP_VHT_FLAG_SGI_NSYM_M10_9 = 8,\n\tIEEE80211_RADIOTAP_VHT_FLAG_LDPC_EXTRA_OFDM_SYM = 16,\n\tIEEE80211_RADIOTAP_VHT_FLAG_BEAMFORMED = 32,\n};\n\nstruct ieee80211_radiotap_he {\n\t__le16 data1;\n\t__le16 data2;\n\t__le16 data3;\n\t__le16 data4;\n\t__le16 data5;\n\t__le16 data6;\n};\n\nenum ieee80211_radiotap_he_bits {\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_MASK = 3,\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU = 0,\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_EXT_SU = 1,\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU = 2,\n\tIEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG = 3,\n\tIEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN = 4,\n\tIEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN = 8,\n\tIEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN = 16,\n\tIEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN = 32,\n\tIEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN = 64,\n\tIEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN = 128,\n\tIEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN = 256,\n\tIEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN = 512,\n\tIEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN = 1024,\n\tIEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE2_KNOWN = 2048,\n\tIEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE3_KNOWN = 4096,\n\tIEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE4_KNOWN = 8192,\n\tIEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN = 16384,\n\tIEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN = 32768,\n\tIEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_KNOWN = 1,\n\tIEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN = 2,\n\tIEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN = 4,\n\tIEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN = 8,\n\tIEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN = 16,\n\tIEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN = 32,\n\tIEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN = 64,\n\tIEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN = 128,\n\tIEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET = 16128,\n\tIEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET_KNOWN = 16384,\n\tIEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_SEC = 32768,\n\tIEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR = 63,\n\tIEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE = 64,\n\tIEEE80211_RADIOTAP_HE_DATA3_UL_DL = 128,\n\tIEEE80211_RADIOTAP_HE_DATA3_DATA_MCS = 3840,\n\tIEEE80211_RADIOTAP_HE_DATA3_DATA_DCM = 4096,\n\tIEEE80211_RADIOTAP_HE_DATA3_CODING = 8192,\n\tIEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG = 16384,\n\tIEEE80211_RADIOTAP_HE_DATA3_STBC = 32768,\n\tIEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE = 15,\n\tIEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID = 32752,\n\tIEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE1 = 15,\n\tIEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE2 = 240,\n\tIEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE3 = 3840,\n\tIEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE4 = 61440,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC = 15,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_20MHZ = 0,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_40MHZ = 1,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_80MHZ = 2,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_160MHZ = 3,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_26T = 4,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_52T = 5,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_106T = 6,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_242T = 7,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_484T = 8,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_996T = 9,\n\tIEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_2x996T = 10,\n\tIEEE80211_RADIOTAP_HE_DATA5_GI = 48,\n\tIEEE80211_RADIOTAP_HE_DATA5_GI_0_8 = 0,\n\tIEEE80211_RADIOTAP_HE_DATA5_GI_1_6 = 1,\n\tIEEE80211_RADIOTAP_HE_DATA5_GI_3_2 = 2,\n\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE = 192,\n\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_UNKNOWN = 0,\n\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_1X = 1,\n\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_2X = 2,\n\tIEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_4X = 3,\n\tIEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS = 1792,\n\tIEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD = 12288,\n\tIEEE80211_RADIOTAP_HE_DATA5_TXBF = 16384,\n\tIEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG = 32768,\n\tIEEE80211_RADIOTAP_HE_DATA6_NSTS = 15,\n\tIEEE80211_RADIOTAP_HE_DATA6_DOPPLER = 16,\n\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_KNOWN = 32,\n\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW = 192,\n\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_20MHZ = 0,\n\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_40MHZ = 1,\n\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_80MHZ = 2,\n\tIEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_160MHZ = 3,\n\tIEEE80211_RADIOTAP_HE_DATA6_TXOP = 32512,\n\tIEEE80211_RADIOTAP_HE_DATA6_MIDAMBLE_PDCTY = 32768,\n};\n\nenum ieee80211_ac_numbers {\n\tIEEE80211_AC_VO = 0,\n\tIEEE80211_AC_VI = 1,\n\tIEEE80211_AC_BE = 2,\n\tIEEE80211_AC_BK = 3,\n};\n\nenum mac80211_tx_info_flags {\n\tIEEE80211_TX_CTL_REQ_TX_STATUS = 1,\n\tIEEE80211_TX_CTL_ASSIGN_SEQ = 2,\n\tIEEE80211_TX_CTL_NO_ACK = 4,\n\tIEEE80211_TX_CTL_CLEAR_PS_FILT = 8,\n\tIEEE80211_TX_CTL_FIRST_FRAGMENT = 16,\n\tIEEE80211_TX_CTL_SEND_AFTER_DTIM = 32,\n\tIEEE80211_TX_CTL_AMPDU = 64,\n\tIEEE80211_TX_CTL_INJECTED = 128,\n\tIEEE80211_TX_STAT_TX_FILTERED = 256,\n\tIEEE80211_TX_STAT_ACK = 512,\n\tIEEE80211_TX_STAT_AMPDU = 1024,\n\tIEEE80211_TX_STAT_AMPDU_NO_BACK = 2048,\n\tIEEE80211_TX_CTL_RATE_CTRL_PROBE = 4096,\n\tIEEE80211_TX_INTFL_OFFCHAN_TX_OK = 8192,\n\tIEEE80211_TX_INTFL_NEED_TXPROCESSING = 16384,\n\tIEEE80211_TX_INTFL_RETRIED = 32768,\n\tIEEE80211_TX_INTFL_DONT_ENCRYPT = 65536,\n\tIEEE80211_TX_CTL_NO_PS_BUFFER = 131072,\n\tIEEE80211_TX_CTL_MORE_FRAMES = 262144,\n\tIEEE80211_TX_INTFL_RETRANSMISSION = 524288,\n\tIEEE80211_TX_INTFL_MLME_CONN_TX = 1048576,\n\tIEEE80211_TX_INTFL_NL80211_FRAME_TX = 2097152,\n\tIEEE80211_TX_CTL_LDPC = 4194304,\n\tIEEE80211_TX_CTL_STBC = 25165824,\n\tIEEE80211_TX_CTL_TX_OFFCHAN = 33554432,\n\tIEEE80211_TX_INTFL_TKIP_MIC_FAILURE = 67108864,\n\tIEEE80211_TX_CTL_NO_CCK_RATE = 134217728,\n\tIEEE80211_TX_STATUS_EOSP = 268435456,\n\tIEEE80211_TX_CTL_USE_MINRATE = 536870912,\n\tIEEE80211_TX_CTL_DONTFRAG = 1073741824,\n\tIEEE80211_TX_STAT_NOACK_TRANSMITTED = 2147483648,\n};\n\nenum mac80211_rate_control_flags {\n\tIEEE80211_TX_RC_USE_RTS_CTS = 1,\n\tIEEE80211_TX_RC_USE_CTS_PROTECT = 2,\n\tIEEE80211_TX_RC_USE_SHORT_PREAMBLE = 4,\n\tIEEE80211_TX_RC_MCS = 8,\n\tIEEE80211_TX_RC_GREEN_FIELD = 16,\n\tIEEE80211_TX_RC_40_MHZ_WIDTH = 32,\n\tIEEE80211_TX_RC_DUP_DATA = 64,\n\tIEEE80211_TX_RC_SHORT_GI = 128,\n\tIEEE80211_TX_RC_VHT_MCS = 256,\n\tIEEE80211_TX_RC_80_MHZ_WIDTH = 512,\n\tIEEE80211_TX_RC_160_MHZ_WIDTH = 1024,\n};\n\nenum ieee80211_sta_info_flags {\n\tWLAN_STA_AUTH = 0,\n\tWLAN_STA_ASSOC = 1,\n\tWLAN_STA_PS_STA = 2,\n\tWLAN_STA_AUTHORIZED = 3,\n\tWLAN_STA_SHORT_PREAMBLE = 4,\n\tWLAN_STA_WDS = 5,\n\tWLAN_STA_CLEAR_PS_FILT = 6,\n\tWLAN_STA_MFP = 7,\n\tWLAN_STA_BLOCK_BA = 8,\n\tWLAN_STA_PS_DRIVER = 9,\n\tWLAN_STA_PSPOLL = 10,\n\tWLAN_STA_TDLS_PEER = 11,\n\tWLAN_STA_TDLS_PEER_AUTH = 12,\n\tWLAN_STA_TDLS_INITIATOR = 13,\n\tWLAN_STA_TDLS_CHAN_SWITCH = 14,\n\tWLAN_STA_TDLS_OFF_CHANNEL = 15,\n\tWLAN_STA_TDLS_WIDER_BW = 16,\n\tWLAN_STA_UAPSD = 17,\n\tWLAN_STA_SP = 18,\n\tWLAN_STA_4ADDR_EVENT = 19,\n\tWLAN_STA_INSERTED = 20,\n\tWLAN_STA_RATE_CONTROL = 21,\n\tWLAN_STA_TOFFSET_KNOWN = 22,\n\tWLAN_STA_MPSP_OWNER = 23,\n\tWLAN_STA_MPSP_RECIPIENT = 24,\n\tWLAN_STA_PS_DELIVER = 25,\n\tWLAN_STA_USES_ENCRYPTION = 26,\n\tNUM_WLAN_STA_FLAGS = 27,\n};\n\nenum ieee80211_sta_flags {\n\tIEEE80211_STA_CONNECTION_POLL = 2,\n\tIEEE80211_STA_CONTROL_PORT = 4,\n\tIEEE80211_STA_DISABLE_HT = 16,\n\tIEEE80211_STA_MFP_ENABLED = 64,\n\tIEEE80211_STA_UAPSD_ENABLED = 128,\n\tIEEE80211_STA_NULLFUNC_ACKED = 256,\n\tIEEE80211_STA_RESET_SIGNAL_AVE = 512,\n\tIEEE80211_STA_DISABLE_40MHZ = 1024,\n\tIEEE80211_STA_DISABLE_VHT = 2048,\n\tIEEE80211_STA_DISABLE_80P80MHZ = 4096,\n\tIEEE80211_STA_DISABLE_160MHZ = 8192,\n\tIEEE80211_STA_DISABLE_WMM = 16384,\n\tIEEE80211_STA_ENABLE_RRM = 32768,\n\tIEEE80211_STA_DISABLE_HE = 65536,\n};\n\nenum ieee80211_sdata_state_bits {\n\tSDATA_STATE_RUNNING = 0,\n\tSDATA_STATE_OFFCHANNEL = 1,\n\tSDATA_STATE_OFFCHANNEL_BEACON_STOPPED = 2,\n};\n\nenum ieee80211_rate_control_changed {\n\tIEEE80211_RC_BW_CHANGED = 1,\n\tIEEE80211_RC_SMPS_CHANGED = 2,\n\tIEEE80211_RC_SUPP_RATES_CHANGED = 4,\n\tIEEE80211_RC_NSS_CHANGED = 8,\n};\n\nstruct codel_stats {\n\tu32 maxpacket;\n\tu32 drop_count;\n\tu32 drop_len;\n\tu32 ecn_mark;\n\tu32 ce_mark;\n};\n\nstruct ieee80211_qos_hdr {\n\t__le16 frame_control;\n\t__le16 duration_id;\n\tu8 addr1[6];\n\tu8 addr2[6];\n\tu8 addr3[6];\n\t__le16 seq_ctrl;\n\t__le16 qos_ctrl;\n};\n\nenum mac80211_tx_control_flags {\n\tIEEE80211_TX_CTRL_PORT_CTRL_PROTO = 1,\n\tIEEE80211_TX_CTRL_PS_RESPONSE = 2,\n\tIEEE80211_TX_CTRL_RATE_INJECT = 4,\n\tIEEE80211_TX_CTRL_AMSDU = 8,\n\tIEEE80211_TX_CTRL_FAST_XMIT = 16,\n\tIEEE80211_TX_CTRL_SKIP_MPATH_LOOKUP = 32,\n\tIEEE80211_TX_CTRL_HW_80211_ENCAP = 64,\n};\n\nenum ieee80211_vif_flags {\n\tIEEE80211_VIF_BEACON_FILTER = 1,\n\tIEEE80211_VIF_SUPPORTS_CQM_RSSI = 2,\n\tIEEE80211_VIF_SUPPORTS_UAPSD = 4,\n\tIEEE80211_VIF_GET_NOA_UPDATE = 8,\n};\n\nenum ieee80211_agg_stop_reason {\n\tAGG_STOP_DECLINED = 0,\n\tAGG_STOP_LOCAL_REQUEST = 1,\n\tAGG_STOP_PEER_REQUEST = 2,\n\tAGG_STOP_DESTROY_STA = 3,\n};\n\nenum sta_stats_type {\n\tSTA_STATS_RATE_TYPE_INVALID = 0,\n\tSTA_STATS_RATE_TYPE_LEGACY = 1,\n\tSTA_STATS_RATE_TYPE_HT = 2,\n\tSTA_STATS_RATE_TYPE_VHT = 3,\n\tSTA_STATS_RATE_TYPE_HE = 4,\n};\n\nstruct txq_info {\n\tstruct fq_tin tin;\n\tstruct fq_flow def_flow;\n\tstruct codel_vars def_cvars;\n\tstruct codel_stats cstats;\n\tstruct sk_buff_head frags;\n\tstruct list_head schedule_order;\n\tu16 schedule_round;\n\tlong unsigned int flags;\n\tstruct ieee80211_txq txq;\n};\n\nenum mac80211_rx_flags {\n\tRX_FLAG_MMIC_ERROR = 1,\n\tRX_FLAG_DECRYPTED = 2,\n\tRX_FLAG_MACTIME_PLCP_START = 4,\n\tRX_FLAG_MMIC_STRIPPED = 8,\n\tRX_FLAG_IV_STRIPPED = 16,\n\tRX_FLAG_FAILED_FCS_CRC = 32,\n\tRX_FLAG_FAILED_PLCP_CRC = 64,\n\tRX_FLAG_MACTIME_START = 128,\n\tRX_FLAG_NO_SIGNAL_VAL = 256,\n\tRX_FLAG_AMPDU_DETAILS = 512,\n\tRX_FLAG_PN_VALIDATED = 1024,\n\tRX_FLAG_DUP_VALIDATED = 2048,\n\tRX_FLAG_AMPDU_LAST_KNOWN = 4096,\n\tRX_FLAG_AMPDU_IS_LAST = 8192,\n\tRX_FLAG_AMPDU_DELIM_CRC_ERROR = 16384,\n\tRX_FLAG_AMPDU_DELIM_CRC_KNOWN = 32768,\n\tRX_FLAG_MACTIME_END = 65536,\n\tRX_FLAG_ONLY_MONITOR = 131072,\n\tRX_FLAG_SKIP_MONITOR = 262144,\n\tRX_FLAG_AMSDU_MORE = 524288,\n\tRX_FLAG_RADIOTAP_VENDOR_DATA = 1048576,\n\tRX_FLAG_MIC_STRIPPED = 2097152,\n\tRX_FLAG_ALLOW_SAME_PN = 4194304,\n\tRX_FLAG_ICV_STRIPPED = 8388608,\n\tRX_FLAG_AMPDU_EOF_BIT = 16777216,\n\tRX_FLAG_AMPDU_EOF_BIT_KNOWN = 33554432,\n\tRX_FLAG_RADIOTAP_HE = 67108864,\n\tRX_FLAG_RADIOTAP_HE_MU = 134217728,\n\tRX_FLAG_RADIOTAP_LSIG = 268435456,\n\tRX_FLAG_NO_PSDU = 536870912,\n};\n\nenum ieee80211_key_flags {\n\tIEEE80211_KEY_FLAG_GENERATE_IV_MGMT = 1,\n\tIEEE80211_KEY_FLAG_GENERATE_IV = 2,\n\tIEEE80211_KEY_FLAG_GENERATE_MMIC = 4,\n\tIEEE80211_KEY_FLAG_PAIRWISE = 8,\n\tIEEE80211_KEY_FLAG_SW_MGMT_TX = 16,\n\tIEEE80211_KEY_FLAG_PUT_IV_SPACE = 32,\n\tIEEE80211_KEY_FLAG_RX_MGMT = 64,\n\tIEEE80211_KEY_FLAG_RESERVE_TAILROOM = 128,\n\tIEEE80211_KEY_FLAG_PUT_MIC_SPACE = 256,\n\tIEEE80211_KEY_FLAG_NO_AUTO_TX = 512,\n\tIEEE80211_KEY_FLAG_GENERATE_MMIE = 1024,\n};\n\ntypedef unsigned int ieee80211_tx_result;\n\nstruct ieee80211_tx_data {\n\tstruct sk_buff *skb;\n\tstruct sk_buff_head skbs;\n\tstruct ieee80211_local *local;\n\tstruct ieee80211_sub_if_data *sdata;\n\tstruct sta_info *sta;\n\tstruct ieee80211_key *key;\n\tstruct ieee80211_tx_rate rate;\n\tunsigned int flags;\n};\n\ntypedef unsigned int ieee80211_rx_result;\n\nstruct ieee80211_rx_data {\n\tstruct napi_struct *napi;\n\tstruct sk_buff *skb;\n\tstruct ieee80211_local *local;\n\tstruct ieee80211_sub_if_data *sdata;\n\tstruct sta_info *sta;\n\tstruct ieee80211_key *key;\n\tunsigned int flags;\n\tint seqno_idx;\n\tint security_idx;\n\tu32 tkip_iv32;\n\tu16 tkip_iv16;\n};\n\nstruct ieee80211_mmie {\n\tu8 element_id;\n\tu8 length;\n\t__le16 key_id;\n\tu8 sequence_number[6];\n\tu8 mic[8];\n};\n\nstruct ieee80211_mmie_16 {\n\tu8 element_id;\n\tu8 length;\n\t__le16 key_id;\n\tu8 sequence_number[6];\n\tu8 mic[16];\n};\n\nenum ieee80211_internal_key_flags {\n\tKEY_FLAG_UPLOADED_TO_HARDWARE = 1,\n\tKEY_FLAG_TAINTED = 2,\n\tKEY_FLAG_CIPHER_SCHEME = 4,\n};\n\nenum {\n\tTKIP_DECRYPT_OK = 0,\n\tTKIP_DECRYPT_NO_EXT_IV = 4294967295,\n\tTKIP_DECRYPT_INVALID_KEYIDX = 4294967294,\n\tTKIP_DECRYPT_REPLAY = 4294967293,\n};\n\nenum mac80211_rx_encoding {\n\tRX_ENC_LEGACY = 0,\n\tRX_ENC_HT = 1,\n\tRX_ENC_VHT = 2,\n\tRX_ENC_HE = 3,\n};\n\nstruct ieee80211_bss {\n\tu32 device_ts_beacon;\n\tu32 device_ts_presp;\n\tbool wmm_used;\n\tbool uapsd_supported;\n\tu8 supp_rates[32];\n\tsize_t supp_rates_len;\n\tstruct ieee80211_rate *beacon_rate;\n\tu32 vht_cap_info;\n\tbool has_erp_value;\n\tu8 erp_value;\n\tu8 corrupt_data;\n\tu8 valid_data;\n};\n\nenum ieee80211_bss_corrupt_data_flags {\n\tIEEE80211_BSS_CORRUPT_BEACON = 1,\n\tIEEE80211_BSS_CORRUPT_PROBE_RESP = 2,\n};\n\nenum ieee80211_bss_valid_data_flags {\n\tIEEE80211_BSS_VALID_WMM = 2,\n\tIEEE80211_BSS_VALID_RATES = 4,\n\tIEEE80211_BSS_VALID_ERP = 8,\n};\n\nenum {\n\tIEEE80211_PROBE_FLAG_DIRECTED = 1,\n\tIEEE80211_PROBE_FLAG_MIN_CONTENT = 2,\n\tIEEE80211_PROBE_FLAG_RANDOM_SN = 4,\n};\n\nstruct ieee80211_roc_work {\n\tstruct list_head list;\n\tstruct ieee80211_sub_if_data *sdata;\n\tstruct ieee80211_channel *chan;\n\tbool started;\n\tbool abort;\n\tbool hw_begun;\n\tbool notified;\n\tbool on_channel;\n\tlong unsigned int start_time;\n\tu32 duration;\n\tu32 req_duration;\n\tstruct sk_buff *frame;\n\tu64 cookie;\n\tu64 mgmt_tx_cookie;\n\tenum ieee80211_roc_type type;\n};\n\nenum ieee80211_back_actioncode {\n\tWLAN_ACTION_ADDBA_REQ = 0,\n\tWLAN_ACTION_ADDBA_RESP = 1,\n\tWLAN_ACTION_DELBA = 2,\n};\n\nenum ieee80211_back_parties {\n\tWLAN_BACK_RECIPIENT = 0,\n\tWLAN_BACK_INITIATOR = 1,\n};\n\nenum txq_info_flags {\n\tIEEE80211_TXQ_STOP = 0,\n\tIEEE80211_TXQ_AMPDU = 1,\n\tIEEE80211_TXQ_NO_AMSDU = 2,\n\tIEEE80211_TXQ_STOP_NETIF_TX = 3,\n};\n\nenum ieee80211_vht_opmode_bits {\n\tIEEE80211_OPMODE_NOTIF_CHANWIDTH_MASK = 3,\n\tIEEE80211_OPMODE_NOTIF_CHANWIDTH_20MHZ = 0,\n\tIEEE80211_OPMODE_NOTIF_CHANWIDTH_40MHZ = 1,\n\tIEEE80211_OPMODE_NOTIF_CHANWIDTH_80MHZ = 2,\n\tIEEE80211_OPMODE_NOTIF_CHANWIDTH_160MHZ = 3,\n\tIEEE80211_OPMODE_NOTIF_BW_160_80P80 = 4,\n\tIEEE80211_OPMODE_NOTIF_RX_NSS_MASK = 112,\n\tIEEE80211_OPMODE_NOTIF_RX_NSS_SHIFT = 4,\n\tIEEE80211_OPMODE_NOTIF_RX_NSS_TYPE_BF = 128,\n};\n\nenum ieee80211_spectrum_mgmt_actioncode {\n\tWLAN_ACTION_SPCT_MSR_REQ = 0,\n\tWLAN_ACTION_SPCT_MSR_RPRT = 1,\n\tWLAN_ACTION_SPCT_TPC_REQ = 2,\n\tWLAN_ACTION_SPCT_TPC_RPRT = 3,\n\tWLAN_ACTION_SPCT_CHL_SWITCH = 4,\n};\n\nstruct ieee80211_csa_ie {\n\tstruct cfg80211_chan_def chandef;\n\tu8 mode;\n\tu8 count;\n\tu8 ttl;\n\tu16 pre_value;\n\tu16 reason_code;\n\tu32 max_switch_time;\n};\n\nenum ieee80211_vht_actioncode {\n\tWLAN_VHT_ACTION_COMPRESSED_BF = 0,\n\tWLAN_VHT_ACTION_GROUPID_MGMT = 1,\n\tWLAN_VHT_ACTION_OPMODE_NOTIF = 2,\n};\n\nenum ieee80211_tpt_led_trigger_flags {\n\tIEEE80211_TPT_LEDTRIG_FL_RADIO = 1,\n\tIEEE80211_TPT_LEDTRIG_FL_WORK = 2,\n\tIEEE80211_TPT_LEDTRIG_FL_CONNECTED = 4,\n};\n\nstruct rate_control_alg {\n\tstruct list_head list;\n\tconst struct rate_control_ops *ops;\n};\n\nstruct michael_mic_ctx {\n\tu32 l;\n\tu32 r;\n};\n\nstruct ieee80211_csa_settings {\n\tconst u16 *counter_offsets_beacon;\n\tconst u16 *counter_offsets_presp;\n\tint n_counter_offsets_beacon;\n\tint n_counter_offsets_presp;\n\tu8 count;\n};\n\nstruct ieee80211_hdr_3addr {\n\t__le16 frame_control;\n\t__le16 duration_id;\n\tu8 addr1[6];\n\tu8 addr2[6];\n\tu8 addr3[6];\n\t__le16 seq_ctrl;\n};\n\nenum ieee80211_ht_chanwidth_values {\n\tIEEE80211_HT_CHANWIDTH_20MHZ = 0,\n\tIEEE80211_HT_CHANWIDTH_ANY = 1,\n};\n\nstruct ieee80211_tdls_data {\n\tu8 da[6];\n\tu8 sa[6];\n\t__be16 ether_type;\n\tu8 payload_type;\n\tu8 category;\n\tu8 action_code;\n\tunion {\n\t\tstruct {\n\t\t\tu8 dialog_token;\n\t\t\t__le16 capability;\n\t\t\tu8 variable[0];\n\t\t} __attribute__((packed)) setup_req;\n\t\tstruct {\n\t\t\t__le16 status_code;\n\t\t\tu8 dialog_token;\n\t\t\t__le16 capability;\n\t\t\tu8 variable[0];\n\t\t} __attribute__((packed)) setup_resp;\n\t\tstruct {\n\t\t\t__le16 status_code;\n\t\t\tu8 dialog_token;\n\t\t\tu8 variable[0];\n\t\t} __attribute__((packed)) setup_cfm;\n\t\tstruct {\n\t\t\t__le16 reason_code;\n\t\t\tu8 variable[0];\n\t\t} teardown;\n\t\tstruct {\n\t\t\tu8 dialog_token;\n\t\t\tu8 variable[0];\n\t\t} discover_req;\n\t\tstruct {\n\t\t\tu8 target_channel;\n\t\t\tu8 oper_class;\n\t\t\tu8 variable[0];\n\t\t} chan_switch_req;\n\t\tstruct {\n\t\t\t__le16 status_code;\n\t\t\tu8 variable[0];\n\t\t} chan_switch_resp;\n\t} u;\n} __attribute__((packed));\n\nenum ieee80211_self_protected_actioncode {\n\tWLAN_SP_RESERVED = 0,\n\tWLAN_SP_MESH_PEERING_OPEN = 1,\n\tWLAN_SP_MESH_PEERING_CONFIRM = 2,\n\tWLAN_SP_MESH_PEERING_CLOSE = 3,\n\tWLAN_SP_MGK_INFORM = 4,\n\tWLAN_SP_MGK_ACK = 5,\n};\n\nenum ieee80211_pub_actioncode {\n\tWLAN_PUB_ACTION_20_40_BSS_COEX = 0,\n\tWLAN_PUB_ACTION_DSE_ENABLEMENT = 1,\n\tWLAN_PUB_ACTION_DSE_DEENABLEMENT = 2,\n\tWLAN_PUB_ACTION_DSE_REG_LOC_ANN = 3,\n\tWLAN_PUB_ACTION_EXT_CHANSW_ANN = 4,\n\tWLAN_PUB_ACTION_DSE_MSMT_REQ = 5,\n\tWLAN_PUB_ACTION_DSE_MSMT_RESP = 6,\n\tWLAN_PUB_ACTION_MSMT_PILOT = 7,\n\tWLAN_PUB_ACTION_DSE_PC = 8,\n\tWLAN_PUB_ACTION_VENDOR_SPECIFIC = 9,\n\tWLAN_PUB_ACTION_GAS_INITIAL_REQ = 10,\n\tWLAN_PUB_ACTION_GAS_INITIAL_RESP = 11,\n\tWLAN_PUB_ACTION_GAS_COMEBACK_REQ = 12,\n\tWLAN_PUB_ACTION_GAS_COMEBACK_RESP = 13,\n\tWLAN_PUB_ACTION_TDLS_DISCOVER_RES = 14,\n\tWLAN_PUB_ACTION_LOC_TRACK_NOTI = 15,\n\tWLAN_PUB_ACTION_QAB_REQUEST_FRAME = 16,\n\tWLAN_PUB_ACTION_QAB_RESPONSE_FRAME = 17,\n\tWLAN_PUB_ACTION_QMF_POLICY = 18,\n\tWLAN_PUB_ACTION_QMF_POLICY_CHANGE = 19,\n\tWLAN_PUB_ACTION_QLOAD_REQUEST = 20,\n\tWLAN_PUB_ACTION_QLOAD_REPORT = 21,\n\tWLAN_PUB_ACTION_HCCA_TXOP_ADVERT = 22,\n\tWLAN_PUB_ACTION_HCCA_TXOP_RESPONSE = 23,\n\tWLAN_PUB_ACTION_PUBLIC_KEY = 24,\n\tWLAN_PUB_ACTION_CHANNEL_AVAIL_QUERY = 25,\n\tWLAN_PUB_ACTION_CHANNEL_SCHEDULE_MGMT = 26,\n\tWLAN_PUB_ACTION_CONTACT_VERI_SIGNAL = 27,\n\tWLAN_PUB_ACTION_GDD_ENABLEMENT_REQ = 28,\n\tWLAN_PUB_ACTION_GDD_ENABLEMENT_RESP = 29,\n\tWLAN_PUB_ACTION_NETWORK_CHANNEL_CONTROL = 30,\n\tWLAN_PUB_ACTION_WHITE_SPACE_MAP_ANN = 31,\n\tWLAN_PUB_ACTION_FTM_REQUEST = 32,\n\tWLAN_PUB_ACTION_FTM = 33,\n\tWLAN_PUB_ACTION_FILS_DISCOVERY = 34,\n};\n\nenum ieee80211_sa_query_action {\n\tWLAN_ACTION_SA_QUERY_REQUEST = 0,\n\tWLAN_ACTION_SA_QUERY_RESPONSE = 1,\n};\n\nenum ieee80211_radiotap_flags {\n\tIEEE80211_RADIOTAP_F_CFP = 1,\n\tIEEE80211_RADIOTAP_F_SHORTPRE = 2,\n\tIEEE80211_RADIOTAP_F_WEP = 4,\n\tIEEE80211_RADIOTAP_F_FRAG = 8,\n\tIEEE80211_RADIOTAP_F_FCS = 16,\n\tIEEE80211_RADIOTAP_F_DATAPAD = 32,\n\tIEEE80211_RADIOTAP_F_BADFCS = 64,\n};\n\nenum ieee80211_radiotap_channel_flags {\n\tIEEE80211_CHAN_CCK = 32,\n\tIEEE80211_CHAN_OFDM = 64,\n\tIEEE80211_CHAN_2GHZ = 128,\n\tIEEE80211_CHAN_5GHZ = 256,\n\tIEEE80211_CHAN_DYN = 1024,\n\tIEEE80211_CHAN_HALF = 16384,\n\tIEEE80211_CHAN_QUARTER = 32768,\n};\n\nenum ieee80211_radiotap_rx_flags {\n\tIEEE80211_RADIOTAP_F_RX_BADPLCP = 2,\n};\n\nenum ieee80211_radiotap_ampdu_flags {\n\tIEEE80211_RADIOTAP_AMPDU_REPORT_ZEROLEN = 1,\n\tIEEE80211_RADIOTAP_AMPDU_IS_ZEROLEN = 2,\n\tIEEE80211_RADIOTAP_AMPDU_LAST_KNOWN = 4,\n\tIEEE80211_RADIOTAP_AMPDU_IS_LAST = 8,\n\tIEEE80211_RADIOTAP_AMPDU_DELIM_CRC_ERR = 16,\n\tIEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN = 32,\n\tIEEE80211_RADIOTAP_AMPDU_EOF = 64,\n\tIEEE80211_RADIOTAP_AMPDU_EOF_KNOWN = 128,\n};\n\nenum ieee80211_radiotap_vht_coding {\n\tIEEE80211_RADIOTAP_CODING_LDPC_USER0 = 1,\n\tIEEE80211_RADIOTAP_CODING_LDPC_USER1 = 2,\n\tIEEE80211_RADIOTAP_CODING_LDPC_USER2 = 4,\n\tIEEE80211_RADIOTAP_CODING_LDPC_USER3 = 8,\n};\n\nenum ieee80211_radiotap_timestamp_flags {\n\tIEEE80211_RADIOTAP_TIMESTAMP_FLAG_64BIT = 0,\n\tIEEE80211_RADIOTAP_TIMESTAMP_FLAG_32BIT = 1,\n\tIEEE80211_RADIOTAP_TIMESTAMP_FLAG_ACCURACY = 2,\n};\n\nstruct ieee80211_radiotap_he_mu {\n\t__le16 flags1;\n\t__le16 flags2;\n\tu8 ru_ch1[4];\n\tu8 ru_ch2[4];\n};\n\nstruct ieee80211_radiotap_lsig {\n\t__le16 data1;\n\t__le16 data2;\n};\n\nenum mac80211_rx_encoding_flags {\n\tRX_ENC_FLAG_SHORTPRE = 1,\n\tRX_ENC_FLAG_SHORT_GI = 4,\n\tRX_ENC_FLAG_HT_GF = 8,\n\tRX_ENC_FLAG_STBC_MASK = 48,\n\tRX_ENC_FLAG_LDPC = 64,\n\tRX_ENC_FLAG_BF = 128,\n};\n\nstruct ieee80211_vendor_radiotap {\n\tu32 present;\n\tu8 align;\n\tu8 oui[3];\n\tu8 subns;\n\tu8 pad;\n\tu16 len;\n\tu8 data[0];\n};\n\nenum ieee80211_packet_rx_flags {\n\tIEEE80211_RX_AMSDU = 8,\n\tIEEE80211_RX_MALFORMED_ACTION_FRM = 16,\n\tIEEE80211_RX_DEFERRED_RELEASE = 32,\n};\n\nenum ieee80211_rx_flags {\n\tIEEE80211_RX_CMNTR = 1,\n\tIEEE80211_RX_BEACON_REPORTED = 2,\n};\n\nstruct ieee80211_rts {\n\t__le16 frame_control;\n\t__le16 duration;\n\tu8 ra[6];\n\tu8 ta[6];\n};\n\nstruct ieee80211_cts {\n\t__le16 frame_control;\n\t__le16 duration;\n\tu8 ra[6];\n};\n\nstruct ieee80211_pspoll {\n\t__le16 frame_control;\n\t__le16 aid;\n\tu8 bssid[6];\n\tu8 ta[6];\n};\n\ntypedef u32 (*codel_skb_len_t)(const struct sk_buff *);\n\ntypedef codel_time_t (*codel_skb_time_t)(const struct sk_buff *);\n\ntypedef void (*codel_skb_drop_t)(struct sk_buff *, void *);\n\ntypedef struct sk_buff * (*codel_skb_dequeue_t)(struct codel_vars *, void *);\n\nstruct ieee80211_mutable_offsets {\n\tu16 tim_offset;\n\tu16 tim_length;\n\tu16 csa_counter_offs[2];\n};\n\ntypedef struct sk_buff *fq_tin_dequeue_t(struct fq *, struct fq_tin *, struct fq_flow *);\n\ntypedef void fq_skb_free_t(struct fq *, struct fq_tin *, struct fq_flow *, struct sk_buff *);\n\ntypedef bool fq_skb_filter_t(struct fq *, struct fq_tin *, struct fq_flow *, struct sk_buff *, void *);\n\ntypedef struct fq_flow *fq_flow_get_default_t(struct fq *, struct fq_tin *, int, struct sk_buff *);\n\nenum mesh_path_flags {\n\tMESH_PATH_ACTIVE = 1,\n\tMESH_PATH_RESOLVING = 2,\n\tMESH_PATH_SN_VALID = 4,\n\tMESH_PATH_FIXED = 8,\n\tMESH_PATH_RESOLVED = 16,\n\tMESH_PATH_REQ_QUEUED = 32,\n\tMESH_PATH_DELETED = 64,\n};\n\nstruct mesh_path {\n\tu8 dst[6];\n\tu8 mpp[6];\n\tstruct rhash_head rhash;\n\tstruct hlist_node walk_list;\n\tstruct hlist_node gate_list;\n\tstruct ieee80211_sub_if_data *sdata;\n\tstruct sta_info *next_hop;\n\tstruct timer_list timer;\n\tstruct sk_buff_head frame_queue;\n\tstruct callback_head rcu;\n\tu32 sn;\n\tu32 metric;\n\tu8 hop_count;\n\tlong unsigned int exp_time;\n\tu32 discovery_timeout;\n\tu8 discovery_retries;\n\tenum mesh_path_flags flags;\n\tspinlock_t state_lock;\n\tu8 rann_snd_addr[6];\n\tu32 rann_metric;\n\tlong unsigned int last_preq_to_root;\n\tbool is_root;\n\tbool is_gate;\n\tu32 path_change_count;\n};\n\nstruct ieee80211_he_6ghz_oper {\n\tu8 primary;\n\tu8 control;\n\tu8 ccfs0;\n\tu8 ccfs1;\n\tu8 minrate;\n};\n\nenum ieee80211_interface_iteration_flags {\n\tIEEE80211_IFACE_ITER_NORMAL = 0,\n\tIEEE80211_IFACE_ITER_RESUME_ALL = 1,\n\tIEEE80211_IFACE_ITER_ACTIVE = 2,\n};\n\nstruct ieee80211_noa_data {\n\tu32 next_tsf;\n\tbool has_next_tsf;\n\tu8 absent;\n\tu8 count[4];\n\tstruct {\n\t\tu32 start;\n\t\tu32 duration;\n\t\tu32 interval;\n\t} desc[4];\n};\n\nenum ieee80211_chanctx_change {\n\tIEEE80211_CHANCTX_CHANGE_WIDTH = 1,\n\tIEEE80211_CHANCTX_CHANGE_RX_CHAINS = 2,\n\tIEEE80211_CHANCTX_CHANGE_RADAR = 4,\n\tIEEE80211_CHANCTX_CHANGE_CHANNEL = 8,\n\tIEEE80211_CHANCTX_CHANGE_MIN_WIDTH = 16,\n};\n\nstruct trace_vif_entry {\n\tenum nl80211_iftype vif_type;\n\tbool p2p;\n\tchar vif_name[16];\n} __attribute__((packed));\n\nstruct trace_chandef_entry {\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n};\n\nstruct trace_switch_entry {\n\tstruct trace_vif_entry vif;\n\tstruct trace_chandef_entry old_chandef;\n\tstruct trace_chandef_entry new_chandef;\n} __attribute__((packed));\n\nstruct trace_event_raw_local_only_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_local_sdata_addr_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_local_u32_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_local_sdata_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_return_int {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_return_bool {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tbool ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_return_u32 {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_return_u64 {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu64 ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_wakeup {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tbool enabled;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_change_interface {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 new_type;\n\tbool new_p2p;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_config {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 changed;\n\tu32 flags;\n\tint power_level;\n\tint dynamic_ps_timeout;\n\tu16 listen_interval;\n\tu8 long_frame_max_tx_count;\n\tu8 short_frame_max_tx_count;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tint smps;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_bss_info_changed {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 changed;\n\tbool assoc;\n\tbool ibss_joined;\n\tbool ibss_creator;\n\tu16 aid;\n\tbool cts;\n\tbool shortpre;\n\tbool shortslot;\n\tbool enable_beacon;\n\tu8 dtimper;\n\tu16 bcnint;\n\tu16 assoc_cap;\n\tu64 sync_tsf;\n\tu32 sync_device_ts;\n\tu8 sync_dtim_count;\n\tu32 basic_rates;\n\tint mcast_rate[4];\n\tu16 ht_operation_mode;\n\ts32 cqm_rssi_thold;\n\ts32 cqm_rssi_hyst;\n\tu32 channel_width;\n\tu32 channel_cfreq1;\n\tu32 channel_cfreq1_offset;\n\tu32 __data_loc_arp_addr_list;\n\tint arp_addr_cnt;\n\tbool qos;\n\tbool idle;\n\tbool ps;\n\tu32 __data_loc_ssid;\n\tbool hidden_ssid;\n\tint txpower;\n\tu8 p2p_oppps_ctwindow;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_prepare_multicast {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint mc_count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_configure_filter {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tunsigned int changed;\n\tunsigned int total;\n\tu64 multicast;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_config_iface_filter {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tunsigned int filter_flags;\n\tunsigned int changed_flags;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_tim {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar sta_addr[6];\n\tbool set;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_key {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu32 cipher;\n\tu8 hw_key_idx;\n\tu8 flags;\n\ts8 keyidx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_update_tkip_key {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu32 iv32;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_sw_scan_start {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar mac_addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_stats {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint ret;\n\tunsigned int ackfail;\n\tunsigned int rtsfail;\n\tunsigned int fcserr;\n\tunsigned int rtssucc;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_key_seq {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 cipher;\n\tu8 hw_key_idx;\n\tu8 flags;\n\ts8 keyidx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_coverage_class {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\ts16 value;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_sta_notify {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu32 cmd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_sta_state {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu32 old_state;\n\tu32 new_state;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_sta_set_txpwr {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\ts16 txpwr;\n\tu8 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_sta_rc_update {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu32 changed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_sta_event {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_conf_tx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu16 ac;\n\tu16 txop;\n\tu16 cw_min;\n\tu16 cw_max;\n\tu8 aifs;\n\tbool uapsd;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_tsf {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu64 tsf;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_offset_tsf {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\ts64 tsf_offset;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_ampdu_action {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tenum ieee80211_ampdu_mlme_action ieee80211_ampdu_mlme_action;\n\tchar sta_addr[6];\n\tu16 tid;\n\tu16 ssn;\n\tu16 buf_size;\n\tbool amsdu;\n\tu16 timeout;\n\tu16 action;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_survey {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_flush {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tbool drop;\n\tu32 queues;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_channel_switch {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu64 timestamp;\n\tu32 device_timestamp;\n\tbool block_tx;\n\tu8 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_antenna {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 tx_ant;\n\tu32 rx_ant;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_antenna {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 tx_ant;\n\tu32 rx_ant;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_remain_on_channel {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tint center_freq;\n\tint freq_offset;\n\tunsigned int duration;\n\tu32 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_ringparam {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 tx;\n\tu32 rx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_ringparam {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 tx;\n\tu32 tx_max;\n\tu32 rx;\n\tu32 rx_max;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_bitrate_mask {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 legacy_2g;\n\tu32 legacy_5g;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_rekey_data {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 kek[16];\n\tu8 kck[16];\n\tu8 replay_ctr[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_event_callback {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_release_evt {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar sta_addr[6];\n\tu16 tids;\n\tint num_frames;\n\tint reason;\n\tbool more_data;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_mgd_prepare_tx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 duration;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_local_chanctx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu32 min_control_freq;\n\tu32 min_freq_offset;\n\tu32 min_chan_width;\n\tu32 min_center_freq1;\n\tu32 min_freq1_offset;\n\tu32 min_center_freq2;\n\tu8 rx_chains_static;\n\tu8 rx_chains_dynamic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_change_chanctx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu32 min_control_freq;\n\tu32 min_freq_offset;\n\tu32 min_chan_width;\n\tu32 min_center_freq1;\n\tu32 min_freq1_offset;\n\tu32 min_center_freq2;\n\tu8 rx_chains_static;\n\tu8 rx_chains_dynamic;\n\tu32 changed;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_switch_vif_chanctx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tint n_vifs;\n\tu32 mode;\n\tu32 __data_loc_vifs;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_local_sdata_chanctx {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu32 min_control_freq;\n\tu32 min_freq_offset;\n\tu32 min_chan_width;\n\tu32 min_center_freq1;\n\tu32 min_freq1_offset;\n\tu32 min_center_freq2;\n\tu8 rx_chains_static;\n\tu8 rx_chains_dynamic;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_start_ap {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 dtimper;\n\tu16 bcnint;\n\tu32 __data_loc_ssid;\n\tbool hidden_ssid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_reconfig_complete {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu8 reconfig_type;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_join_ibss {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 dtimper;\n\tu16 bcnint;\n\tu32 __data_loc_ssid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_expected_throughput {\n\tstruct trace_entry ent;\n\tchar sta_addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_start_nan {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 master_pref;\n\tu8 bands;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_stop_nan {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_nan_change_conf {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 master_pref;\n\tu8 bands;\n\tu32 changes;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_add_nan_func {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 type;\n\tu8 inst_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_del_nan_func {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 instance_id;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_start_tx_ba_session {\n\tstruct trace_entry ent;\n\tchar sta_addr[6];\n\tu16 tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_start_tx_ba_cb {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 ra[6];\n\tu16 tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_stop_tx_ba_session {\n\tstruct trace_entry ent;\n\tchar sta_addr[6];\n\tu16 tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_stop_tx_ba_cb {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 ra[6];\n\tu16 tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_beacon_loss {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_connection_loss {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_cqm_rssi_notify {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 rssi_event;\n\ts32 rssi_level;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_scan_completed {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tbool aborted;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_sched_scan_results {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_sched_scan_stopped {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_sta_block_awake {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar sta_addr[6];\n\tbool block;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_chswitch_done {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tbool success;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_gtk_rekey_notify {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 bssid[6];\n\tu8 replay_ctr[8];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_enable_rssi_reports {\n\tstruct trace_entry ent;\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tint rssi_min_thold;\n\tint rssi_max_thold;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_eosp {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar sta_addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_send_eosp_nullfunc {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar sta_addr[6];\n\tu8 tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_sta_set_buffered {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar sta_addr[6];\n\tu8 tid;\n\tbool buffered;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_wake_queue {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu16 queue;\n\tu32 reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_stop_queue {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tu16 queue;\n\tu32 reason;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_set_default_unicast_key {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tint key_idx;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_api_radar_detected {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_channel_switch_beacon {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_pre_channel_switch {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu64 timestamp;\n\tu32 device_timestamp;\n\tbool block_tx;\n\tu8 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_channel_switch_rx_beacon {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu64 timestamp;\n\tu32 device_timestamp;\n\tbool block_tx;\n\tu8 count;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_txpower {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tint dbm;\n\tint ret;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_tdls_channel_switch {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu8 oper_class;\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_tdls_cancel_channel_switch {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_tdls_recv_channel_switch {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tu8 action_code;\n\tchar sta_addr[6];\n\tu32 control_freq;\n\tu32 freq_offset;\n\tu32 chan_width;\n\tu32 center_freq1;\n\tu32 freq1_offset;\n\tu32 center_freq2;\n\tu32 status;\n\tbool peer_initiator;\n\tu32 timestamp;\n\tu16 switch_time;\n\tu16 switch_timeout;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_wake_tx_queue {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar sta_addr[6];\n\tu8 ac;\n\tu8 tid;\n\tchar __data[0];\n};\n\nstruct trace_event_raw_drv_get_ftm_responder_stats {\n\tstruct trace_entry ent;\n\tchar wiphy_name[32];\n\tenum nl80211_iftype vif_type;\n\tvoid *sdata;\n\tbool p2p;\n\tu32 __data_loc_vif_name;\n\tchar __data[0];\n};\n\nstruct trace_event_data_offsets_local_only_evt {};\n\nstruct trace_event_data_offsets_local_sdata_addr_evt {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_local_u32_evt {};\n\nstruct trace_event_data_offsets_local_sdata_evt {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_return_int {};\n\nstruct trace_event_data_offsets_drv_return_bool {};\n\nstruct trace_event_data_offsets_drv_return_u32 {};\n\nstruct trace_event_data_offsets_drv_return_u64 {};\n\nstruct trace_event_data_offsets_drv_set_wakeup {};\n\nstruct trace_event_data_offsets_drv_change_interface {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_config {};\n\nstruct trace_event_data_offsets_drv_bss_info_changed {\n\tu32 vif_name;\n\tu32 arp_addr_list;\n\tu32 ssid;\n};\n\nstruct trace_event_data_offsets_drv_prepare_multicast {};\n\nstruct trace_event_data_offsets_drv_configure_filter {};\n\nstruct trace_event_data_offsets_drv_config_iface_filter {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_set_tim {};\n\nstruct trace_event_data_offsets_drv_set_key {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_update_tkip_key {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_sw_scan_start {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_get_stats {};\n\nstruct trace_event_data_offsets_drv_get_key_seq {};\n\nstruct trace_event_data_offsets_drv_set_coverage_class {};\n\nstruct trace_event_data_offsets_drv_sta_notify {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_sta_state {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_sta_set_txpwr {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_sta_rc_update {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_sta_event {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_conf_tx {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_set_tsf {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_offset_tsf {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_ampdu_action {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_get_survey {};\n\nstruct trace_event_data_offsets_drv_flush {};\n\nstruct trace_event_data_offsets_drv_channel_switch {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_set_antenna {};\n\nstruct trace_event_data_offsets_drv_get_antenna {};\n\nstruct trace_event_data_offsets_drv_remain_on_channel {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_set_ringparam {};\n\nstruct trace_event_data_offsets_drv_get_ringparam {};\n\nstruct trace_event_data_offsets_drv_set_bitrate_mask {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_set_rekey_data {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_event_callback {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_release_evt {};\n\nstruct trace_event_data_offsets_drv_mgd_prepare_tx {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_local_chanctx {};\n\nstruct trace_event_data_offsets_drv_change_chanctx {};\n\nstruct trace_event_data_offsets_drv_switch_vif_chanctx {\n\tu32 vifs;\n};\n\nstruct trace_event_data_offsets_local_sdata_chanctx {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_start_ap {\n\tu32 vif_name;\n\tu32 ssid;\n};\n\nstruct trace_event_data_offsets_drv_reconfig_complete {};\n\nstruct trace_event_data_offsets_drv_join_ibss {\n\tu32 vif_name;\n\tu32 ssid;\n};\n\nstruct trace_event_data_offsets_drv_get_expected_throughput {};\n\nstruct trace_event_data_offsets_drv_start_nan {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_stop_nan {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_nan_change_conf {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_add_nan_func {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_del_nan_func {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_api_start_tx_ba_session {};\n\nstruct trace_event_data_offsets_api_start_tx_ba_cb {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_api_stop_tx_ba_session {};\n\nstruct trace_event_data_offsets_api_stop_tx_ba_cb {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_api_beacon_loss {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_api_connection_loss {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_api_cqm_rssi_notify {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_api_scan_completed {};\n\nstruct trace_event_data_offsets_api_sched_scan_results {};\n\nstruct trace_event_data_offsets_api_sched_scan_stopped {};\n\nstruct trace_event_data_offsets_api_sta_block_awake {};\n\nstruct trace_event_data_offsets_api_chswitch_done {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_api_gtk_rekey_notify {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_api_enable_rssi_reports {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_api_eosp {};\n\nstruct trace_event_data_offsets_api_send_eosp_nullfunc {};\n\nstruct trace_event_data_offsets_api_sta_set_buffered {};\n\nstruct trace_event_data_offsets_wake_queue {};\n\nstruct trace_event_data_offsets_stop_queue {};\n\nstruct trace_event_data_offsets_drv_set_default_unicast_key {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_api_radar_detected {};\n\nstruct trace_event_data_offsets_drv_channel_switch_beacon {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_pre_channel_switch {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_channel_switch_rx_beacon {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_get_txpower {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_tdls_channel_switch {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_tdls_cancel_channel_switch {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_tdls_recv_channel_switch {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_wake_tx_queue {\n\tu32 vif_name;\n};\n\nstruct trace_event_data_offsets_drv_get_ftm_responder_stats {\n\tu32 vif_name;\n};\n\ntypedef void (*btf_trace_drv_return_void)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_return_int)(void *, struct ieee80211_local *, int);\n\ntypedef void (*btf_trace_drv_return_bool)(void *, struct ieee80211_local *, bool);\n\ntypedef void (*btf_trace_drv_return_u32)(void *, struct ieee80211_local *, u32);\n\ntypedef void (*btf_trace_drv_return_u64)(void *, struct ieee80211_local *, u64);\n\ntypedef void (*btf_trace_drv_start)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_get_et_strings)(void *, struct ieee80211_local *, u32);\n\ntypedef void (*btf_trace_drv_get_et_sset_count)(void *, struct ieee80211_local *, u32);\n\ntypedef void (*btf_trace_drv_get_et_stats)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_suspend)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_resume)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_set_wakeup)(void *, struct ieee80211_local *, bool);\n\ntypedef void (*btf_trace_drv_stop)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_add_interface)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_change_interface)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, enum nl80211_iftype, bool);\n\ntypedef void (*btf_trace_drv_remove_interface)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_config)(void *, struct ieee80211_local *, u32);\n\ntypedef void (*btf_trace_drv_bss_info_changed)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_bss_conf *, u32);\n\ntypedef void (*btf_trace_drv_prepare_multicast)(void *, struct ieee80211_local *, int);\n\ntypedef void (*btf_trace_drv_configure_filter)(void *, struct ieee80211_local *, unsigned int, unsigned int *, u64);\n\ntypedef void (*btf_trace_drv_config_iface_filter)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, unsigned int, unsigned int);\n\ntypedef void (*btf_trace_drv_set_tim)(void *, struct ieee80211_local *, struct ieee80211_sta *, bool);\n\ntypedef void (*btf_trace_drv_set_key)(void *, struct ieee80211_local *, enum set_key_cmd, struct ieee80211_sub_if_data *, struct ieee80211_sta *, struct ieee80211_key_conf *);\n\ntypedef void (*btf_trace_drv_update_tkip_key)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_key_conf *, struct ieee80211_sta *, u32);\n\ntypedef void (*btf_trace_drv_hw_scan)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_cancel_hw_scan)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_sched_scan_start)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_sched_scan_stop)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_sw_scan_start)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, const u8 *);\n\ntypedef void (*btf_trace_drv_sw_scan_complete)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_get_stats)(void *, struct ieee80211_local *, struct ieee80211_low_level_stats *, int);\n\ntypedef void (*btf_trace_drv_get_key_seq)(void *, struct ieee80211_local *, struct ieee80211_key_conf *);\n\ntypedef void (*btf_trace_drv_set_frag_threshold)(void *, struct ieee80211_local *, u32);\n\ntypedef void (*btf_trace_drv_set_rts_threshold)(void *, struct ieee80211_local *, u32);\n\ntypedef void (*btf_trace_drv_set_coverage_class)(void *, struct ieee80211_local *, s16);\n\ntypedef void (*btf_trace_drv_sta_notify)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, enum sta_notify_cmd, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_sta_state)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *, enum ieee80211_sta_state, enum ieee80211_sta_state);\n\ntypedef void (*btf_trace_drv_sta_set_txpwr)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_sta_rc_update)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *, u32);\n\ntypedef void (*btf_trace_drv_sta_statistics)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_sta_add)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_sta_remove)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_sta_pre_rcu_remove)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_sync_rx_queues)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_sta_rate_tbl_update)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_conf_tx)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, u16, const struct ieee80211_tx_queue_params *);\n\ntypedef void (*btf_trace_drv_get_tsf)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_set_tsf)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, u64);\n\ntypedef void (*btf_trace_drv_offset_tsf)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, s64);\n\ntypedef void (*btf_trace_drv_reset_tsf)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_tx_last_beacon)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_ampdu_action)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_ampdu_params *);\n\ntypedef void (*btf_trace_drv_get_survey)(void *, struct ieee80211_local *, int, struct survey_info *);\n\ntypedef void (*btf_trace_drv_flush)(void *, struct ieee80211_local *, u32, bool);\n\ntypedef void (*btf_trace_drv_channel_switch)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_channel_switch *);\n\ntypedef void (*btf_trace_drv_set_antenna)(void *, struct ieee80211_local *, u32, u32, int);\n\ntypedef void (*btf_trace_drv_get_antenna)(void *, struct ieee80211_local *, u32, u32, int);\n\ntypedef void (*btf_trace_drv_remain_on_channel)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_channel *, unsigned int, enum ieee80211_roc_type);\n\ntypedef void (*btf_trace_drv_cancel_remain_on_channel)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_set_ringparam)(void *, struct ieee80211_local *, u32, u32);\n\ntypedef void (*btf_trace_drv_get_ringparam)(void *, struct ieee80211_local *, u32 *, u32 *, u32 *, u32 *);\n\ntypedef void (*btf_trace_drv_tx_frames_pending)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_offchannel_tx_cancel_wait)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_set_bitrate_mask)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, const struct cfg80211_bitrate_mask *);\n\ntypedef void (*btf_trace_drv_set_rekey_data)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct cfg80211_gtk_rekey_data *);\n\ntypedef void (*btf_trace_drv_event_callback)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, const struct ieee80211_event *);\n\ntypedef void (*btf_trace_drv_release_buffered_frames)(void *, struct ieee80211_local *, struct ieee80211_sta *, u16, int, enum ieee80211_frame_release_type, bool);\n\ntypedef void (*btf_trace_drv_allow_buffered_frames)(void *, struct ieee80211_local *, struct ieee80211_sta *, u16, int, enum ieee80211_frame_release_type, bool);\n\ntypedef void (*btf_trace_drv_mgd_prepare_tx)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, u16);\n\ntypedef void (*btf_trace_drv_mgd_protect_tdls_discover)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_add_chanctx)(void *, struct ieee80211_local *, struct ieee80211_chanctx *);\n\ntypedef void (*btf_trace_drv_remove_chanctx)(void *, struct ieee80211_local *, struct ieee80211_chanctx *);\n\ntypedef void (*btf_trace_drv_change_chanctx)(void *, struct ieee80211_local *, struct ieee80211_chanctx *, u32);\n\ntypedef void (*btf_trace_drv_switch_vif_chanctx)(void *, struct ieee80211_local *, struct ieee80211_vif_chanctx_switch *, int, enum ieee80211_chanctx_switch_mode);\n\ntypedef void (*btf_trace_drv_assign_vif_chanctx)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_chanctx *);\n\ntypedef void (*btf_trace_drv_unassign_vif_chanctx)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_chanctx *);\n\ntypedef void (*btf_trace_drv_start_ap)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_bss_conf *);\n\ntypedef void (*btf_trace_drv_stop_ap)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_reconfig_complete)(void *, struct ieee80211_local *, enum ieee80211_reconfig_type);\n\ntypedef void (*btf_trace_drv_ipv6_addr_change)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_join_ibss)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_bss_conf *);\n\ntypedef void (*btf_trace_drv_leave_ibss)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_get_expected_throughput)(void *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_start_nan)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct cfg80211_nan_conf *);\n\ntypedef void (*btf_trace_drv_stop_nan)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_nan_change_conf)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct cfg80211_nan_conf *, u32);\n\ntypedef void (*btf_trace_drv_add_nan_func)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, const struct cfg80211_nan_func *);\n\ntypedef void (*btf_trace_drv_del_nan_func)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, u8);\n\ntypedef void (*btf_trace_drv_start_pmsr)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_abort_pmsr)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_api_start_tx_ba_session)(void *, struct ieee80211_sta *, u16);\n\ntypedef void (*btf_trace_api_start_tx_ba_cb)(void *, struct ieee80211_sub_if_data *, const u8 *, u16);\n\ntypedef void (*btf_trace_api_stop_tx_ba_session)(void *, struct ieee80211_sta *, u16);\n\ntypedef void (*btf_trace_api_stop_tx_ba_cb)(void *, struct ieee80211_sub_if_data *, const u8 *, u16);\n\ntypedef void (*btf_trace_api_restart_hw)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_api_beacon_loss)(void *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_api_connection_loss)(void *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_api_cqm_rssi_notify)(void *, struct ieee80211_sub_if_data *, enum nl80211_cqm_rssi_threshold_event, s32);\n\ntypedef void (*btf_trace_api_cqm_beacon_loss_notify)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_api_scan_completed)(void *, struct ieee80211_local *, bool);\n\ntypedef void (*btf_trace_api_sched_scan_results)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_api_sched_scan_stopped)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_api_sta_block_awake)(void *, struct ieee80211_local *, struct ieee80211_sta *, bool);\n\ntypedef void (*btf_trace_api_chswitch_done)(void *, struct ieee80211_sub_if_data *, bool);\n\ntypedef void (*btf_trace_api_ready_on_channel)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_api_remain_on_channel_expired)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_api_gtk_rekey_notify)(void *, struct ieee80211_sub_if_data *, const u8 *, const u8 *);\n\ntypedef void (*btf_trace_api_enable_rssi_reports)(void *, struct ieee80211_sub_if_data *, int, int);\n\ntypedef void (*btf_trace_api_eosp)(void *, struct ieee80211_local *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_api_send_eosp_nullfunc)(void *, struct ieee80211_local *, struct ieee80211_sta *, u8);\n\ntypedef void (*btf_trace_api_sta_set_buffered)(void *, struct ieee80211_local *, struct ieee80211_sta *, u8, bool);\n\ntypedef void (*btf_trace_wake_queue)(void *, struct ieee80211_local *, u16, enum queue_stop_reason);\n\ntypedef void (*btf_trace_stop_queue)(void *, struct ieee80211_local *, u16, enum queue_stop_reason);\n\ntypedef void (*btf_trace_drv_set_default_unicast_key)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, int);\n\ntypedef void (*btf_trace_api_radar_detected)(void *, struct ieee80211_local *);\n\ntypedef void (*btf_trace_drv_channel_switch_beacon)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_drv_pre_channel_switch)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_channel_switch *);\n\ntypedef void (*btf_trace_drv_post_channel_switch)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_abort_channel_switch)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *);\n\ntypedef void (*btf_trace_drv_channel_switch_rx_beacon)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_channel_switch *);\n\ntypedef void (*btf_trace_drv_get_txpower)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, int, int);\n\ntypedef void (*btf_trace_drv_tdls_channel_switch)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *, u8, struct cfg80211_chan_def *);\n\ntypedef void (*btf_trace_drv_tdls_cancel_channel_switch)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_sta *);\n\ntypedef void (*btf_trace_drv_tdls_recv_channel_switch)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct ieee80211_tdls_ch_sw_params *);\n\ntypedef void (*btf_trace_drv_wake_tx_queue)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct txq_info *);\n\ntypedef void (*btf_trace_drv_get_ftm_responder_stats)(void *, struct ieee80211_local *, struct ieee80211_sub_if_data *, struct cfg80211_ftm_responder_stats *);\n\nenum ieee80211_he_mcs_support {\n\tIEEE80211_HE_MCS_SUPPORT_0_7 = 0,\n\tIEEE80211_HE_MCS_SUPPORT_0_9 = 1,\n\tIEEE80211_HE_MCS_SUPPORT_0_11 = 2,\n\tIEEE80211_HE_MCS_NOT_SUPPORTED = 3,\n};\n\nstruct ieee80211_country_ie_triplet {\n\tunion {\n\t\tstruct {\n\t\t\tu8 first_channel;\n\t\t\tu8 num_channels;\n\t\t\ts8 max_power;\n\t\t} chans;\n\t\tstruct {\n\t\t\tu8 reg_extension_id;\n\t\t\tu8 reg_class;\n\t\t\tu8 coverage_class;\n\t\t} ext;\n\t};\n};\n\nenum ieee80211_timeout_interval_type {\n\tWLAN_TIMEOUT_REASSOC_DEADLINE = 1,\n\tWLAN_TIMEOUT_KEY_LIFETIME = 2,\n\tWLAN_TIMEOUT_ASSOC_COMEBACK = 3,\n};\n\nenum ieee80211_idle_options {\n\tWLAN_IDLE_OPTIONS_PROTECTED_KEEP_ALIVE = 1,\n};\n\nstruct ieee80211_wmm_ac_param {\n\tu8 aci_aifsn;\n\tu8 cw;\n\t__le16 txop_limit;\n};\n\nstruct ieee80211_wmm_param_ie {\n\tu8 element_id;\n\tu8 len;\n\tu8 oui[3];\n\tu8 oui_type;\n\tu8 oui_subtype;\n\tu8 version;\n\tu8 qos_info;\n\tu8 reserved;\n\tstruct ieee80211_wmm_ac_param ac[4];\n};\n\nenum ocb_deferred_task_flags {\n\tOCB_WORK_HOUSEKEEPING = 0,\n};\n\nstruct mcs_group {\n\tu8 shift;\n\tu16 duration[12];\n};\n\nstruct minstrel_rate_stats {\n\tu16 attempts;\n\tu16 last_attempts;\n\tu16 success;\n\tu16 last_success;\n\tu32 att_hist;\n\tu32 succ_hist;\n\tu16 prob_avg;\n\tu16 prob_avg_1;\n\tu8 retry_count;\n\tu8 retry_count_rtscts;\n\tu8 sample_skipped;\n\tbool retry_updated;\n};\n\nstruct minstrel_rate {\n\tint bitrate;\n\ts8 rix;\n\tu8 retry_count_cts;\n\tu8 adjusted_retry_count;\n\tunsigned int perfect_tx_time;\n\tunsigned int ack_time;\n\tint sample_limit;\n\tstruct minstrel_rate_stats stats;\n};\n\nstruct minstrel_sta_info {\n\tstruct ieee80211_sta *sta;\n\tlong unsigned int last_stats_update;\n\tunsigned int sp_ack_dur;\n\tunsigned int rate_avg;\n\tunsigned int lowest_rix;\n\tu8 max_tp_rate[4];\n\tu8 max_prob_rate;\n\tunsigned int total_packets;\n\tunsigned int sample_packets;\n\tint sample_deferred;\n\tunsigned int sample_row;\n\tunsigned int sample_column;\n\tint n_rates;\n\tstruct minstrel_rate *r;\n\tbool prev_sample;\n\tu8 *sample_table;\n};\n\nstruct minstrel_priv {\n\tstruct ieee80211_hw *hw;\n\tbool has_mrr;\n\tbool new_avg;\n\tu32 sample_switch;\n\tunsigned int cw_min;\n\tunsigned int cw_max;\n\tunsigned int max_retry;\n\tunsigned int segment_size;\n\tunsigned int update_interval;\n\tunsigned int lookaround_rate;\n\tunsigned int lookaround_rate_mrr;\n\tu8 cck_rates[4];\n};\n\nstruct mcs_group___2 {\n\tu16 flags;\n\tu8 streams;\n\tu8 shift;\n\tu8 bw;\n\tu16 duration[10];\n};\n\nstruct minstrel_mcs_group_data {\n\tu8 index;\n\tu8 column;\n\tu16 max_group_tp_rate[4];\n\tu16 max_group_prob_rate;\n\tstruct minstrel_rate_stats rates[10];\n};\n\nenum minstrel_sample_mode {\n\tMINSTREL_SAMPLE_IDLE = 0,\n\tMINSTREL_SAMPLE_ACTIVE = 1,\n\tMINSTREL_SAMPLE_PENDING = 2,\n};\n\nstruct minstrel_ht_sta {\n\tstruct ieee80211_sta *sta;\n\tunsigned int ampdu_len;\n\tunsigned int ampdu_packets;\n\tunsigned int avg_ampdu_len;\n\tu16 max_tp_rate[4];\n\tu16 max_prob_rate;\n\tlong unsigned int last_stats_update;\n\tunsigned int overhead;\n\tunsigned int overhead_rtscts;\n\tunsigned int total_packets_last;\n\tunsigned int total_packets_cur;\n\tunsigned int total_packets;\n\tunsigned int sample_packets;\n\tu32 tx_flags;\n\tu8 sample_wait;\n\tu8 sample_tries;\n\tu8 sample_count;\n\tu8 sample_slow;\n\tenum minstrel_sample_mode sample_mode;\n\tu16 sample_rate;\n\tu8 sample_group;\n\tu8 cck_supported;\n\tu8 cck_supported_short;\n\tu16 supported[41];\n\tstruct minstrel_mcs_group_data groups[41];\n};\n\nstruct minstrel_ht_sta_priv {\n\tunion {\n\t\tstruct minstrel_ht_sta ht;\n\t\tstruct minstrel_sta_info legacy;\n\t};\n\tvoid *ratelist;\n\tvoid *sample_table;\n\tbool is_ht;\n};\n\nstruct netlbl_af4list {\n\t__be32 addr;\n\t__be32 mask;\n\tu32 valid;\n\tstruct list_head list;\n};\n\nstruct netlbl_af6list {\n\tstruct in6_addr addr;\n\tstruct in6_addr mask;\n\tu32 valid;\n\tstruct list_head list;\n};\n\nstruct netlbl_domaddr_map {\n\tstruct list_head list4;\n\tstruct list_head list6;\n};\n\nstruct netlbl_dommap_def {\n\tu32 type;\n\tunion {\n\t\tstruct netlbl_domaddr_map *addrsel;\n\t\tstruct cipso_v4_doi *cipso;\n\t\tstruct calipso_doi *calipso;\n\t};\n};\n\nstruct netlbl_domaddr4_map {\n\tstruct netlbl_dommap_def def;\n\tstruct netlbl_af4list list;\n};\n\nstruct netlbl_domaddr6_map {\n\tstruct netlbl_dommap_def def;\n\tstruct netlbl_af6list list;\n};\n\nstruct netlbl_dom_map {\n\tchar *domain;\n\tu16 family;\n\tstruct netlbl_dommap_def def;\n\tu32 valid;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct netlbl_domhsh_tbl {\n\tstruct list_head *tbl;\n\tu32 size;\n};\n\nenum {\n\tNLBL_MGMT_C_UNSPEC = 0,\n\tNLBL_MGMT_C_ADD = 1,\n\tNLBL_MGMT_C_REMOVE = 2,\n\tNLBL_MGMT_C_LISTALL = 3,\n\tNLBL_MGMT_C_ADDDEF = 4,\n\tNLBL_MGMT_C_REMOVEDEF = 5,\n\tNLBL_MGMT_C_LISTDEF = 6,\n\tNLBL_MGMT_C_PROTOCOLS = 7,\n\tNLBL_MGMT_C_VERSION = 8,\n\t__NLBL_MGMT_C_MAX = 9,\n};\n\nenum {\n\tNLBL_MGMT_A_UNSPEC = 0,\n\tNLBL_MGMT_A_DOMAIN = 1,\n\tNLBL_MGMT_A_PROTOCOL = 2,\n\tNLBL_MGMT_A_VERSION = 3,\n\tNLBL_MGMT_A_CV4DOI = 4,\n\tNLBL_MGMT_A_IPV6ADDR = 5,\n\tNLBL_MGMT_A_IPV6MASK = 6,\n\tNLBL_MGMT_A_IPV4ADDR = 7,\n\tNLBL_MGMT_A_IPV4MASK = 8,\n\tNLBL_MGMT_A_ADDRSELECTOR = 9,\n\tNLBL_MGMT_A_SELECTORLIST = 10,\n\tNLBL_MGMT_A_FAMILY = 11,\n\tNLBL_MGMT_A_CLPDOI = 12,\n\t__NLBL_MGMT_A_MAX = 13,\n};\n\nstruct netlbl_domhsh_walk_arg {\n\tstruct netlink_callback *nl_cb;\n\tstruct sk_buff *skb;\n\tu32 seq;\n};\n\nenum {\n\tNLBL_UNLABEL_C_UNSPEC = 0,\n\tNLBL_UNLABEL_C_ACCEPT = 1,\n\tNLBL_UNLABEL_C_LIST = 2,\n\tNLBL_UNLABEL_C_STATICADD = 3,\n\tNLBL_UNLABEL_C_STATICREMOVE = 4,\n\tNLBL_UNLABEL_C_STATICLIST = 5,\n\tNLBL_UNLABEL_C_STATICADDDEF = 6,\n\tNLBL_UNLABEL_C_STATICREMOVEDEF = 7,\n\tNLBL_UNLABEL_C_STATICLISTDEF = 8,\n\t__NLBL_UNLABEL_C_MAX = 9,\n};\n\nenum {\n\tNLBL_UNLABEL_A_UNSPEC = 0,\n\tNLBL_UNLABEL_A_ACPTFLG = 1,\n\tNLBL_UNLABEL_A_IPV6ADDR = 2,\n\tNLBL_UNLABEL_A_IPV6MASK = 3,\n\tNLBL_UNLABEL_A_IPV4ADDR = 4,\n\tNLBL_UNLABEL_A_IPV4MASK = 5,\n\tNLBL_UNLABEL_A_IFACE = 6,\n\tNLBL_UNLABEL_A_SECCTX = 7,\n\t__NLBL_UNLABEL_A_MAX = 8,\n};\n\nstruct netlbl_unlhsh_tbl {\n\tstruct list_head *tbl;\n\tu32 size;\n};\n\nstruct netlbl_unlhsh_addr4 {\n\tu32 secid;\n\tstruct netlbl_af4list list;\n\tstruct callback_head rcu;\n};\n\nstruct netlbl_unlhsh_addr6 {\n\tu32 secid;\n\tstruct netlbl_af6list list;\n\tstruct callback_head rcu;\n};\n\nstruct netlbl_unlhsh_iface {\n\tint ifindex;\n\tstruct list_head addr4_list;\n\tstruct list_head addr6_list;\n\tu32 valid;\n\tstruct list_head list;\n\tstruct callback_head rcu;\n};\n\nstruct netlbl_unlhsh_walk_arg {\n\tstruct netlink_callback *nl_cb;\n\tstruct sk_buff *skb;\n\tu32 seq;\n};\n\nenum {\n\tNLBL_CIPSOV4_C_UNSPEC = 0,\n\tNLBL_CIPSOV4_C_ADD = 1,\n\tNLBL_CIPSOV4_C_REMOVE = 2,\n\tNLBL_CIPSOV4_C_LIST = 3,\n\tNLBL_CIPSOV4_C_LISTALL = 4,\n\t__NLBL_CIPSOV4_C_MAX = 5,\n};\n\nenum {\n\tNLBL_CIPSOV4_A_UNSPEC = 0,\n\tNLBL_CIPSOV4_A_DOI = 1,\n\tNLBL_CIPSOV4_A_MTYPE = 2,\n\tNLBL_CIPSOV4_A_TAG = 3,\n\tNLBL_CIPSOV4_A_TAGLST = 4,\n\tNLBL_CIPSOV4_A_MLSLVLLOC = 5,\n\tNLBL_CIPSOV4_A_MLSLVLREM = 6,\n\tNLBL_CIPSOV4_A_MLSLVL = 7,\n\tNLBL_CIPSOV4_A_MLSLVLLST = 8,\n\tNLBL_CIPSOV4_A_MLSCATLOC = 9,\n\tNLBL_CIPSOV4_A_MLSCATREM = 10,\n\tNLBL_CIPSOV4_A_MLSCAT = 11,\n\tNLBL_CIPSOV4_A_MLSCATLST = 12,\n\t__NLBL_CIPSOV4_A_MAX = 13,\n};\n\nstruct netlbl_cipsov4_doiwalk_arg {\n\tstruct netlink_callback *nl_cb;\n\tstruct sk_buff *skb;\n\tu32 seq;\n};\n\nstruct netlbl_domhsh_walk_arg___2 {\n\tstruct netlbl_audit *audit_info;\n\tu32 doi;\n};\n\nenum {\n\tNLBL_CALIPSO_C_UNSPEC = 0,\n\tNLBL_CALIPSO_C_ADD = 1,\n\tNLBL_CALIPSO_C_REMOVE = 2,\n\tNLBL_CALIPSO_C_LIST = 3,\n\tNLBL_CALIPSO_C_LISTALL = 4,\n\t__NLBL_CALIPSO_C_MAX = 5,\n};\n\nenum {\n\tNLBL_CALIPSO_A_UNSPEC = 0,\n\tNLBL_CALIPSO_A_DOI = 1,\n\tNLBL_CALIPSO_A_MTYPE = 2,\n\t__NLBL_CALIPSO_A_MAX = 3,\n};\n\nstruct netlbl_calipso_doiwalk_arg {\n\tstruct netlink_callback *nl_cb;\n\tstruct sk_buff *skb;\n\tu32 seq;\n};\n\nenum rfkill_operation {\n\tRFKILL_OP_ADD = 0,\n\tRFKILL_OP_DEL = 1,\n\tRFKILL_OP_CHANGE = 2,\n\tRFKILL_OP_CHANGE_ALL = 3,\n};\n\nstruct rfkill_event {\n\t__u32 idx;\n\t__u8 type;\n\t__u8 op;\n\t__u8 soft;\n\t__u8 hard;\n};\n\nenum rfkill_user_states {\n\tRFKILL_USER_STATE_SOFT_BLOCKED = 0,\n\tRFKILL_USER_STATE_UNBLOCKED = 1,\n\tRFKILL_USER_STATE_HARD_BLOCKED = 2,\n};\n\nstruct rfkill {\n\tspinlock_t lock;\n\tenum rfkill_type type;\n\tlong unsigned int state;\n\tu32 idx;\n\tbool registered;\n\tbool persistent;\n\tbool polling_paused;\n\tbool suspended;\n\tconst struct rfkill_ops *ops;\n\tvoid *data;\n\tstruct led_trigger led_trigger;\n\tconst char *ledtrigname;\n\tstruct device dev;\n\tstruct list_head node;\n\tstruct delayed_work poll_work;\n\tstruct work_struct uevent_work;\n\tstruct work_struct sync_work;\n\tchar name[0];\n};\n\nstruct rfkill_int_event {\n\tstruct list_head list;\n\tstruct rfkill_event ev;\n};\n\nstruct rfkill_data {\n\tstruct list_head list;\n\tstruct list_head events;\n\tstruct mutex mtx;\n\twait_queue_head_t read_wait;\n\tbool input_handler;\n};\n\nenum rfkill_input_master_mode {\n\tRFKILL_INPUT_MASTER_UNLOCK = 0,\n\tRFKILL_INPUT_MASTER_RESTORE = 1,\n\tRFKILL_INPUT_MASTER_UNBLOCKALL = 2,\n\tNUM_RFKILL_INPUT_MASTER_MODES = 3,\n};\n\nenum rfkill_sched_op {\n\tRFKILL_GLOBAL_OP_EPO = 0,\n\tRFKILL_GLOBAL_OP_RESTORE = 1,\n\tRFKILL_GLOBAL_OP_UNLOCK = 2,\n\tRFKILL_GLOBAL_OP_UNBLOCK = 3,\n};\n\nenum dns_payload_content_type {\n\tDNS_PAYLOAD_IS_SERVER_LIST = 0,\n};\n\nstruct dns_payload_header {\n\t__u8 zero;\n\t__u8 content;\n\t__u8 version;\n};\n\nenum {\n\tdns_key_data = 0,\n\tdns_key_error = 1,\n};\n\nstruct sockaddr_xdp {\n\t__u16 sxdp_family;\n\t__u16 sxdp_flags;\n\t__u32 sxdp_ifindex;\n\t__u32 sxdp_queue_id;\n\t__u32 sxdp_shared_umem_fd;\n};\n\nstruct xdp_ring_offset {\n\t__u64 producer;\n\t__u64 consumer;\n\t__u64 desc;\n\t__u64 flags;\n};\n\nstruct xdp_mmap_offsets {\n\tstruct xdp_ring_offset rx;\n\tstruct xdp_ring_offset tx;\n\tstruct xdp_ring_offset fr;\n\tstruct xdp_ring_offset cr;\n};\n\nstruct xdp_umem_reg {\n\t__u64 addr;\n\t__u64 len;\n\t__u32 chunk_size;\n\t__u32 headroom;\n\t__u32 flags;\n};\n\nstruct xdp_statistics {\n\t__u64 rx_dropped;\n\t__u64 rx_invalid_descs;\n\t__u64 tx_invalid_descs;\n};\n\nstruct xdp_options {\n\t__u32 flags;\n};\n\nstruct xdp_desc {\n\t__u64 addr;\n\t__u32 len;\n\t__u32 options;\n};\n\nstruct xdp_ring;\n\nstruct xsk_queue {\n\tu32 ring_mask;\n\tu32 nentries;\n\tu32 cached_prod;\n\tu32 cached_cons;\n\tstruct xdp_ring *ring;\n\tu64 invalid_descs;\n};\n\nstruct xdp_ring_offset_v1 {\n\t__u64 producer;\n\t__u64 consumer;\n\t__u64 desc;\n};\n\nstruct xdp_mmap_offsets_v1 {\n\tstruct xdp_ring_offset_v1 rx;\n\tstruct xdp_ring_offset_v1 tx;\n\tstruct xdp_ring_offset_v1 fr;\n\tstruct xdp_ring_offset_v1 cr;\n};\n\nstruct xsk_map_node {\n\tstruct list_head node;\n\tstruct xsk_map *map;\n\tstruct xdp_sock **map_entry;\n};\n\nstruct xdp_ring {\n\tu32 producer;\n\tlong: 32;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tu32 consumer;\n\tu32 flags;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n\tlong: 64;\n};\n\nstruct xdp_rxtx_ring {\n\tstruct xdp_ring ptrs;\n\tstruct xdp_desc desc[0];\n};\n\nstruct xdp_umem_ring {\n\tstruct xdp_ring ptrs;\n\tu64 desc[0];\n};\n\nstruct xdp_diag_req {\n\t__u8 sdiag_family;\n\t__u8 sdiag_protocol;\n\t__u16 pad;\n\t__u32 xdiag_ino;\n\t__u32 xdiag_show;\n\t__u32 xdiag_cookie[2];\n};\n\nstruct xdp_diag_msg {\n\t__u8 xdiag_family;\n\t__u8 xdiag_type;\n\t__u16 pad;\n\t__u32 xdiag_ino;\n\t__u32 xdiag_cookie[2];\n};\n\nenum {\n\tXDP_DIAG_NONE = 0,\n\tXDP_DIAG_INFO = 1,\n\tXDP_DIAG_UID = 2,\n\tXDP_DIAG_RX_RING = 3,\n\tXDP_DIAG_TX_RING = 4,\n\tXDP_DIAG_UMEM = 5,\n\tXDP_DIAG_UMEM_FILL_RING = 6,\n\tXDP_DIAG_UMEM_COMPLETION_RING = 7,\n\tXDP_DIAG_MEMINFO = 8,\n\t__XDP_DIAG_MAX = 9,\n};\n\nstruct xdp_diag_info {\n\t__u32 ifindex;\n\t__u32 queue_id;\n};\n\nstruct xdp_diag_ring {\n\t__u32 entries;\n};\n\nstruct xdp_diag_umem {\n\t__u64 size;\n\t__u32 id;\n\t__u32 num_pages;\n\t__u32 chunk_size;\n\t__u32 headroom;\n\t__u32 ifindex;\n\t__u32 queue_id;\n\t__u32 flags;\n\t__u32 refs;\n};\n\nstruct pcibios_fwaddrmap {\n\tstruct list_head list;\n\tstruct pci_dev *dev;\n\tresource_size_t fw_addr[11];\n};\n\nstruct pci_check_idx_range {\n\tint start;\n\tint end;\n};\n\nstruct pci_mmcfg_region {\n\tstruct list_head list;\n\tstruct resource res;\n\tu64 address;\n\tchar *virt;\n\tu16 segment;\n\tu8 start_bus;\n\tu8 end_bus;\n\tchar name[30];\n};\n\nstruct acpi_table_mcfg {\n\tstruct acpi_table_header header;\n\tu8 reserved[8];\n};\n\nstruct acpi_mcfg_allocation {\n\tu64 address;\n\tu16 pci_segment;\n\tu8 start_bus_number;\n\tu8 end_bus_number;\n\tu32 reserved;\n};\n\nstruct pci_mmcfg_hostbridge_probe {\n\tu32 bus;\n\tu32 devfn;\n\tu32 vendor;\n\tu32 device;\n\tconst char * (*probe)();\n};\n\ntypedef bool (*check_reserved_t)(u64, u64, unsigned int);\n\nstruct pci_root_info {\n\tstruct acpi_pci_root_info common;\n\tstruct pci_sysdata sd;\n\tbool mcfg_added;\n\tu8 start_bus;\n\tu8 end_bus;\n};\n\nstruct irq_info___2 {\n\tu8 bus;\n\tu8 devfn;\n\tstruct {\n\t\tu8 link;\n\t\tu16 bitmap;\n\t} __attribute__((packed)) irq[4];\n\tu8 slot;\n\tu8 rfu;\n};\n\nstruct irq_routing_table {\n\tu32 signature;\n\tu16 version;\n\tu16 size;\n\tu8 rtr_bus;\n\tu8 rtr_devfn;\n\tu16 exclusive_irqs;\n\tu16 rtr_vendor;\n\tu16 rtr_device;\n\tu32 miniport_data;\n\tu8 rfu[11];\n\tu8 checksum;\n\tstruct irq_info___2 slots[0];\n};\n\nstruct irq_router {\n\tchar *name;\n\tu16 vendor;\n\tu16 device;\n\tint (*get)(struct pci_dev *, struct pci_dev *, int);\n\tint (*set)(struct pci_dev *, struct pci_dev *, int, int);\n};\n\nstruct irq_router_handler {\n\tu16 vendor;\n\tint (*probe)(struct irq_router *, struct pci_dev *, u16);\n};\n\nstruct pci_setup_rom {\n\tstruct setup_data data;\n\tuint16_t vendor;\n\tuint16_t devid;\n\tuint64_t pcilen;\n\tlong unsigned int segment;\n\tlong unsigned int bus;\n\tlong unsigned int device;\n\tlong unsigned int function;\n\tuint8_t romdata[0];\n};\n\nenum pci_bf_sort_state {\n\tpci_bf_sort_default = 0,\n\tpci_force_nobf = 1,\n\tpci_force_bf = 2,\n\tpci_dmi_bf = 3,\n};\n\nstruct pci_root_res {\n\tstruct list_head list;\n\tstruct resource res;\n};\n\nstruct pci_root_info___2 {\n\tstruct list_head list;\n\tchar name[12];\n\tstruct list_head resources;\n\tstruct resource busn;\n\tint node;\n\tint link;\n};\n\nstruct amd_hostbridge {\n\tu32 bus;\n\tu32 slot;\n\tu32 device;\n};\n\nstruct saved_msr {\n\tbool valid;\n\tstruct msr_info info;\n};\n\nstruct saved_msrs {\n\tunsigned int num;\n\tstruct saved_msr *array;\n};\n\nstruct saved_context {\n\tstruct pt_regs regs;\n\tu16 ds;\n\tu16 es;\n\tu16 fs;\n\tu16 gs;\n\tlong unsigned int kernelmode_gs_base;\n\tlong unsigned int usermode_gs_base;\n\tlong unsigned int fs_base;\n\tlong unsigned int cr0;\n\tlong unsigned int cr2;\n\tlong unsigned int cr3;\n\tlong unsigned int cr4;\n\tu64 misc_enable;\n\tbool misc_enable_saved;\n\tstruct saved_msrs saved_msrs;\n\tlong unsigned int efer;\n\tu16 gdt_pad;\n\tstruct desc_ptr gdt_desc;\n\tu16 idt_pad;\n\tstruct desc_ptr idt;\n\tu16 ldt;\n\tu16 tss;\n\tlong unsigned int tr;\n\tlong unsigned int safety;\n\tlong unsigned int return_address;\n} __attribute__((packed));\n\ntypedef int (*pm_cpu_match_t)(const struct x86_cpu_id *);\n\nstruct restore_data_record {\n\tlong unsigned int jump_address;\n\tlong unsigned int jump_address_phys;\n\tlong unsigned int cr3;\n\tlong unsigned int magic;\n\tu8 e820_digest[16];\n};\n\n#ifndef BPF_NO_PRESERVE_ACCESS_INDEX\n#pragma clang attribute pop\n#endif\n\n#endif /* __VMLINUX_H__ */\n" } ]