[
  {
    "path": "LICENSE",
    "content": "MIT License\n\nCopyright (c) 2021 Emin Fedar\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n"
  },
  {
    "path": "README.md",
    "content": "# Fedar F1\n[![LibreCores](https://www.librecores.org/eminfedar/fedar-f1-rv64im/badge.svg?style=flat)](https://www.librecores.org/eminfedar/fedar-f1-rv64im)\n\nFedar F1 is a 5-Stage Pipelined (Fetch|Decode|Execute|Memory|Writeback) RV64IM RISC-V Core written fully in Verilog.\n\n![Simulated GTKWave output of the CPU](https://raw.githubusercontent.com/eminfedar/fedar-f1-rv64im/main/gtkwave-image.png)\n\n## How to compile?\n\n1. Open a terminal in `testbench` folder.\n2. Run: `run_tests.sh`.\n  - The script automatically compile and create files under the `testbench/output/` folder. \n  - And will create `.vcd` files under the `testbench/vcd` folder.\n3. Done!\n\nCompilation requires `iverilog` verilog compiler.\n\nYou can install iverilog on Debian based distros (like Pardus GNU/Linux or Ubuntu) with this command:\n```\nsudo apt install iverilog\n```\n\n> If you don't want to compile it again, precompiled `.vcd` files are available under the `testbench/vcd`.\n\n## How to open .vcd files?\n- Use [GTKWave](https://github.com/gtkwave/gtkwave).\n\nYou can install GTKWave on Debian based distros (like Pardus GNU/Linux or Ubuntu) with this command:\n```\nsudo apt install gtkwave\n```\nThen double click the files or open with terminal command: `gtkwave file.vcd`.\n"
  },
  {
    "path": "example/Program.s",
    "content": "start:\n    nop\n    addi x1, x0, 1\n    addi x6, x0, 1\n    addi x12, x0, 4\n    sw x6, 0(x1)        # x6 -> R2 Data Dependency (WriteBack)\nloop:\n    lw x6, 0(x1)        # Load Stall\n    addi x6, x6, 1      # x6 -> R1 Data Dependency\n    sw x6, 0(x1)\n    blt x6, x12, loop   # x6 -> R1 Data Dependency (WriteBack) & Control Hazard\ndata_dep_test:\n    addi x8, x0, 55\n    add x8, x0, x8      # x8 -> R2 Data Dependency\n    addi x8, x8, 1      # x8 -> R1 Data Dependency\nfinish:\n    nop"
  },
  {
    "path": "gtkwave/pipeline_type_enums.gtkw",
    "content": "0 REGISTER\n1 LOAD\n2 STORE\n3 IMMEDIATE\n4 UPPERIMMEDIATE\n5 BRANCH"
  },
  {
    "path": "gtkwave/rom_instruction_enums.gtkw",
    "content": "00000013 NOP\n00100093 addi_x1_x0_1\n00100313 addi_x6_x0_1\n00400613 addi_x12_x0_4\n0060A023 sw_x6_0(x1)\n0000A303 lw_x6_0(x1)\n00130313 addi_x6_x6_1\n0060A023 sw_x6_0(x1)\nFEC34AE3 blt_x6_x12_-12\n03700413 addi_x8_x0_55\n00800433 add_x8_x0_x8\n00140413 addi_x8_x8_1"
  },
  {
    "path": "src/ALU.v",
    "content": "module ALU(\n    input [63:0] X,\n    input [63:0] Y,\n    input [3:0] OP,\n\n    output [63:0] OUTPUT,\n    output isEqual\n);\n    reg [127:0] RESULT;\n\n    wire signed [63:0] X_signed = X;\n    wire signed [63:0] Y_signed = Y;\n\n    assign isEqual = X == Y;\n\n    always @(*) begin\n        case (OP)\n            0:  RESULT <= X + Y; // add\n            1:  RESULT <= X - Y; // sub\n            2:  RESULT <= X & Y; // and\n            3:  RESULT <= X | Y; // or\n            4:  RESULT <= X ^ Y; // xor\n            5:  RESULT <= X << Y; // shift left logical\n            6:  RESULT <= X >> Y; // shift right logical\n            7:  RESULT <= X_signed >>> Y; // shift right arithmetic\n            8:  RESULT <= X * Y; // mul\n            9:  RESULT <= X * Y; // mulh\n            10: RESULT <= X / Y; // div\n            11: RESULT <= X % Y; // rem\n            12: RESULT <= (X_signed < Y_signed ? 1 : 0); // set less than (slt)\n            13: RESULT <= (X < Y ? 1 : 0); // set less than (sltu)\n        endcase\n    end\n\n    assign OUTPUT = OP == 9 ? RESULT[127:64] : RESULT[63:0];\n\nendmodule"
  },
  {
    "path": "src/CPU.v",
    "content": "`include \"ALU.v\"\n`include \"RegFile.v\"\n`include \"ImmediateExtractor.v\"\n`include \"Encoders.v\"\n\nmodule CPU (\n    input [63:0] RAM_READ_DATA,\n    input [31:0] INSTRUCTION,\n    input CLK,\n\n    output [9:0] RAM_ADDR,          // 10-bit Size RAM\n    output reg [63:0] RAM_WRITE_DATA,\n    output RAM_WRITE_ENABLE,\n    output [9:0] INSTRUCTION_ADDR   // 10-bit Size ROM\n);\n    // CONSTANTS:\n    // -- OPCODE DEFINES:\n    integer OP_R_TYPE           = 7'h33;\n    integer OP_R_TYPE_64        = 7'h3B;\n    integer OP_I_TYPE_LOAD      = 7'h03;\n    integer OP_I_TYPE_OTHER     = 7'h13;\n    integer OP_I_TYPE_64        = 7'h1B;\n    integer OP_I_TYPE_JUMP      = 7'h6F;\n    integer OP_S_TYPE           = 7'h23;\n    integer OP_B_TYPE           = 7'h63;\n    integer OP_U_TYPE_LOAD      = 7'h37;\n    integer OP_U_TYPE_JUMP      = 7'h67;\n    integer OP_U_TYPE_AUIPC     = 7'h17;\n    // -- PIPELINE HAZARD INSTRUCTION TYPE DEFINES:\n    integer TYPE_REGISTER       = 0;\n    integer TYPE_LOAD           = 1;\n    integer TYPE_STORE          = 2;\n    integer TYPE_IMMEDIATE      = 3;\n    integer TYPE_UPPERIMMEDIATE = 4;\n    integer TYPE_BRANCH         = 5;\n    // -- PIPELINE STAGES\n    integer DECODE      = 0;\n    integer EXECUTE     = 1;\n    integer MEMORY      = 2;\n    integer WRITEBACK   = 3;\n\n\n    // WIRE DEFINITIONS:\n    wire [6:0] OPCODE   = INSTRUCTION_EXECUTE_3[6:0];\n    wire [4:0] RD       = INSTRUCTION_WRITEBACK_5[11:7];\n    wire [2:0] FUNCT3   = INSTRUCTION_EXECUTE_3[14:12];\n    wire [4:0] R1       = INSTRUCTION_EXECUTE_3[19:15];\n    wire [4:0] R2       = INSTRUCTION_EXECUTE_3[24:20];\n    wire [6:0] FUNCT7   = INSTRUCTION_EXECUTE_3[31:25];\n\n    wire R_TYPE         = OPCODE == OP_R_TYPE;\n    wire R_TYPE_64      = OPCODE == OP_R_TYPE_64;\n    wire I_TYPE_LOAD    = OPCODE == OP_I_TYPE_LOAD;\n    wire I_TYPE_OTHER   = OPCODE == OP_I_TYPE_OTHER;\n    wire I_TYPE_64      = OPCODE == OP_I_TYPE_64;\n    wire I_TYPE_JUMP    = OPCODE == OP_I_TYPE_JUMP;\n    wire I_TYPE         = I_TYPE_JUMP || I_TYPE_LOAD || I_TYPE_OTHER || I_TYPE_64;\n    wire S_TYPE         = OPCODE == OP_S_TYPE;\n    wire B_TYPE         = OPCODE == OP_B_TYPE;\n    wire U_TYPE_LOAD    = OPCODE == OP_U_TYPE_LOAD;\n    wire U_TYPE_JUMP    = OPCODE == OP_U_TYPE_JUMP;\n    wire U_TYPE_AUIPC   = OPCODE == OP_U_TYPE_AUIPC;\n    wire U_TYPE         = U_TYPE_JUMP || U_TYPE_LOAD || U_TYPE_AUIPC;\n\n    // -- Register-Register Types (R-Type)    \n    // ---- RV32I:\n    wire R_add      = R_TYPE && FUNCT3 == 3'h0 && FUNCT7 == 7'h00;\n    wire R_sub      = R_TYPE && FUNCT3 == 3'h0 && FUNCT7 == 7'h20;\n    wire R_sll      = R_TYPE && FUNCT3 == 3'h1 && FUNCT7 == 7'h00;\n    wire R_slt      = R_TYPE && FUNCT3 == 3'h2 && FUNCT7 == 7'h00;\n    wire R_sltu     = R_TYPE && FUNCT3 == 3'h3 && FUNCT7 == 7'h00;\n    wire R_xor      = R_TYPE && FUNCT3 == 3'h4 && FUNCT7 == 7'h00;\n    wire R_srl      = R_TYPE && FUNCT3 == 3'h5 && FUNCT7 == 7'h00;\n    wire R_sra      = R_TYPE && FUNCT3 == 3'h5 && FUNCT7 == 7'h20;\n    wire R_or       = R_TYPE && FUNCT3 == 3'h6 && FUNCT7 == 7'h00;\n    wire R_and      = R_TYPE && FUNCT3 == 3'h7 && FUNCT7 == 7'h00;\n    // ---- RV32M:\n    wire R_mul      = R_TYPE && FUNCT3 == 3'h0 && FUNCT7 == 7'h01;\n    wire R_mulh     = R_TYPE && FUNCT3 == 3'h1 && FUNCT7 == 7'h01;\n    wire R_rem      = R_TYPE && FUNCT3 == 3'h6 && FUNCT7 == 7'h01;\n    wire R_div      = R_TYPE && FUNCT3 == 3'h4 && FUNCT7 == 7'h01;\n    // ---- RV64I:\n    wire R_addw     = R_TYPE_64 && FUNCT3 == 3'h0 && FUNCT7 == 7'h00;\n    wire R_subw     = R_TYPE_64 && FUNCT3 == 3'h0 && FUNCT7 == 7'h20;\n    wire R_sllw     = R_TYPE_64 && FUNCT3 == 3'h1 && FUNCT7 == 7'h00;\n    wire R_srlw     = R_TYPE_64 && FUNCT3 == 3'h5 && FUNCT7 == 7'h00;\n    wire R_sraw     = R_TYPE_64 && FUNCT3 == 3'h5 && FUNCT7 == 7'h20;\n    // ---- RV64M:\n    wire R_mulw     = R_TYPE_64 && FUNCT3 == 3'h0 && FUNCT7 == 7'h01;\n    wire R_divw     = R_TYPE_64 && FUNCT3 == 3'h4 && FUNCT7 == 7'h01;\n    wire R_remw     = R_TYPE_64 && FUNCT3 == 3'h6 && FUNCT7 == 7'h01;\n    \n\n    // -- Immediate Types (I-Type)\n    // ---- RV32I:\n    wire I_addi     = I_TYPE_OTHER && FUNCT3 == 3'h0;\n    wire I_slli     = I_TYPE_OTHER && FUNCT3 == 3'h1 && FUNCT7 == 7'h00;\n    wire I_slti     = I_TYPE_OTHER && FUNCT3 == 3'h2;\n    wire I_sltiu    = I_TYPE_OTHER && FUNCT3 == 3'h3;\n    wire I_xori     = I_TYPE_OTHER && FUNCT3 == 3'h4;\n    wire I_srli     = I_TYPE_OTHER && FUNCT3 == 3'h5 && FUNCT7 == 7'h00;\n    wire I_srai     = I_TYPE_OTHER && FUNCT3 == 3'h5 && FUNCT7 == 7'h10;\n    wire I_ori      = I_TYPE_OTHER && FUNCT3 == 3'h6;\n    wire I_andi     = I_TYPE_OTHER && FUNCT3 == 3'h7;\n    // ---- RV64I:\n    wire I_addiw    = I_TYPE_64 && FUNCT3 == 3'h0;\n    wire I_slliw    = I_TYPE_64 && FUNCT3 == 3'h1 && FUNCT7 == 7'h00;\n    wire I_srliw    = I_TYPE_64 && FUNCT3 == 3'h5 && FUNCT7 == 7'h00;\n    wire I_sraiw    = I_TYPE_64 && FUNCT3 == 3'h5 && FUNCT7 == 7'h20;\n    // ---- Load\n    wire I_lb       = INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_LOAD && INSTRUCTION_MEMORY_4[14:12] == 3'h0;\n    wire I_lh       = INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_LOAD && INSTRUCTION_MEMORY_4[14:12] == 3'h1;\n    wire I_lw       = INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_LOAD && INSTRUCTION_MEMORY_4[14:12] == 3'h2;\n    wire I_ld       = INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_LOAD && INSTRUCTION_MEMORY_4[14:12] == 3'h3;\n    // ---- Jump\n    wire I_jalr     = I_TYPE_JUMP;\n\n\n    // -- Upper Immediate Types (U-Type)\n    wire U_lui      = U_TYPE_LOAD;\n    wire U_auipc    = U_TYPE_AUIPC;\n    wire U_jal      = U_TYPE_JUMP;\n\n\n    // -- Store Types (S-Type)\n    wire S_sb       = INSTRUCTION_MEMORY_4[6:0] == OP_S_TYPE && INSTRUCTION_MEMORY_4[14:12] == 3'h0;\n    wire S_sh       = INSTRUCTION_MEMORY_4[6:0] == OP_S_TYPE && INSTRUCTION_MEMORY_4[14:12] == 3'h1;\n    wire S_sw       = INSTRUCTION_MEMORY_4[6:0] == OP_S_TYPE && INSTRUCTION_MEMORY_4[14:12] == 3'h2;\n    wire S_sd       = INSTRUCTION_MEMORY_4[6:0] == OP_S_TYPE && INSTRUCTION_MEMORY_4[14:12] == 3'h3;\n\n\n    // -- Branch Types (B-Type)\n    wire B_beq      = B_TYPE && FUNCT3 == 0;\n    wire B_bne      = B_TYPE && FUNCT3 == 1;\n    wire B_blt      = B_TYPE && FUNCT3 == 4;\n    wire B_bge      = B_TYPE && FUNCT3 == 5;\n    wire B_bltu     = B_TYPE && FUNCT3 == 6;\n    wire B_bgeu     = B_TYPE && FUNCT3 == 7;\n\n    // -- PC Get Data From ALU Switch\n    wire signed [63:0] R1_DATA =    DATA_DEPENDENCY_HAZARD_R1 ? ALU_OUT_MEMORY_4 :\n                                    DATA_DEPENDENCY_HAZARD_R1_WRITEBACK ?\n                                        (REG_WRITEBACK_SELECTION == 3 ? RAM_READ_DATA_WRITEBACK_5 : REG_WRITE_DATA_WRITEBACK_5)\n                                        : R1_DATA_EXECUTE_3;\n    wire signed [63:0] R2_DATA =    DATA_DEPENDENCY_HAZARD_R2 ? ALU_OUT_MEMORY_4 :\n                                    DATA_DEPENDENCY_HAZARD_R2_WRITEBACK ?\n                                        (REG_WRITEBACK_SELECTION == 3 ? RAM_READ_DATA_WRITEBACK_5 : REG_WRITE_DATA_WRITEBACK_5)\n                                        : R2_DATA_EXECUTE_3;\n    \n    wire [63:0] R1_DATA_UNSIGNED = R1_DATA;\n    wire [63:0] R2_DATA_UNSIGNED = R2_DATA;\n\n    wire PC_ALU_SEL =   (B_beq && R1_DATA == R2_DATA)\n                        || (B_bne && R1_DATA != R2_DATA)\n                        || (B_blt && R1_DATA <  R2_DATA)\n                        || (B_bge && R1_DATA >= R2_DATA)\n                        || (B_bltu && R1_DATA_UNSIGNED <  R2_DATA_UNSIGNED)\n                        || (B_bgeu && R1_DATA_UNSIGNED >= R2_DATA_UNSIGNED)\n                        || I_jalr\n                        || U_jal\n                        ;\n    \n    // -- RAM Read & Write Enable Pins\n    assign RAM_WRITE_ENABLE     = INSTRUCTION_MEMORY_4[6:0] == OP_S_TYPE;\n    assign RAM_ADDR             = ALU_OUT_MEMORY_4[9:0];\n\n\n    // -- PIPELINING HAZARDS\n    // ---- DATA HAZARD CONTROL REGISTERS\n    reg [4:0] R1_PIPELINE[3:0];        // R1 Register of the current stage.\n    reg [4:0] R2_PIPELINE[3:0];        // R2 Register of the current stage.\n    reg [4:0] RD_PIPELINE[3:0];        // RD Register of the current stage.\n    reg [2:0] TYPE_PIPELINE[3:0];      // Instruction Types of the current stage. [R-Type=0, Load=1, Store=2, Immediate or UpperImmediate=3, Branch=4]\n\n    // If R1 depends on the previous RD (or R2 if STORE)\n    wire DATA_DEPENDENCY_HAZARD_R1 =\n                        R1_PIPELINE[EXECUTE] != 0\n                    &&  TYPE_PIPELINE[EXECUTE] != TYPE_UPPERIMMEDIATE\n                    &&  R1_PIPELINE[EXECUTE] == RD_PIPELINE[MEMORY];\n    // If R2 depends on the previous RD (or R2 if STORE)\n    wire DATA_DEPENDENCY_HAZARD_R2 =\n                        R2_PIPELINE[EXECUTE] != 0\n                    &&  TYPE_PIPELINE[EXECUTE] != TYPE_UPPERIMMEDIATE\n                    &&  TYPE_PIPELINE[EXECUTE] != TYPE_IMMEDIATE\n                    &&  R2_PIPELINE[EXECUTE] == RD_PIPELINE[MEMORY];\n    \n    // If R1 depends on the 5th stage RD\n    wire DATA_DEPENDENCY_HAZARD_R1_WRITEBACK =\n                        R1_PIPELINE[EXECUTE] != 0\n                    &&  TYPE_PIPELINE[EXECUTE] != TYPE_UPPERIMMEDIATE\n                    &&  R1_PIPELINE[EXECUTE] == RD_PIPELINE[WRITEBACK];\n    // If R2 depends on the 5th stage RD\n    wire DATA_DEPENDENCY_HAZARD_R2_WRITEBACK =\n                        R2_PIPELINE[EXECUTE] != 0\n                    &&  TYPE_PIPELINE[EXECUTE] != TYPE_UPPERIMMEDIATE\n                    &&  TYPE_PIPELINE[EXECUTE] != TYPE_IMMEDIATE\n                    &&  R2_PIPELINE[EXECUTE] == RD_PIPELINE[WRITEBACK];\n    \n\n    // If the next instruction depends on a Load instruction before, stall one clock.\n    wire LOAD_STALL =\n                        TYPE_PIPELINE[EXECUTE] == TYPE_LOAD\n                    &&  (\n                            (\n                                TYPE_PIPELINE[DECODE] != TYPE_UPPERIMMEDIATE\n                            &&  TYPE_PIPELINE[DECODE] != TYPE_IMMEDIATE\n                            &&  (\n                                    (R1_PIPELINE[DECODE] != 0 && R1_PIPELINE[DECODE] == RD_PIPELINE[EXECUTE])\n                                ||  (R2_PIPELINE[DECODE] != 0 && R2_PIPELINE[DECODE] == RD_PIPELINE[EXECUTE])\n                                )\n                            )\n                        ||  (   \n                                TYPE_PIPELINE[DECODE] == TYPE_IMMEDIATE\n                            &&  R1_PIPELINE[DECODE] != 0\n                            &&  R1_PIPELINE[DECODE] == RD_PIPELINE[EXECUTE]\n                            )\n                        );\n    \n    // If there is a branch instruction, stall for 2 clocks.\n    wire CONTROL_HAZARD_STALL = INSTRUCTION_DECODE_2[6:0] == OP_B_TYPE || INSTRUCTION_EXECUTE_3[6:0] == OP_B_TYPE;\n    \n\n\n\n    // COMPONENT DEFINITIONS (IMMEDIATE EXTRACTOR, ALU, REGFILE):\n    // -- Immediate Extractor\n    wire [63:0] IMMEDIATE_VALUE;\n    wire [2:0] IMMEDIATE_SELECTION;\n    wire [7:0] immediateSelectionInputs;\n\n    assign immediateSelectionInputs[0] = 0;\n    assign immediateSelectionInputs[1] = I_TYPE;\n    assign immediateSelectionInputs[2] = U_TYPE_LOAD || U_TYPE_AUIPC;\n    assign immediateSelectionInputs[3] = S_TYPE;\n    assign immediateSelectionInputs[4] = B_TYPE;\n    assign immediateSelectionInputs[5] = U_TYPE_JUMP;\n    assign immediateSelectionInputs[6] = 0;\n    assign immediateSelectionInputs[7] = 0;\n    Encoder_8 immediateSelectionEncoder(immediateSelectionInputs, IMMEDIATE_SELECTION);\n    \n    ImmediateExtractor immediateExtractor(INSTRUCTION_EXECUTE_3, IMMEDIATE_SELECTION, IMMEDIATE_VALUE);\n\n\n\n\n    // -- ALU Operation Selection\n    wire [15:0] aluOpEncoderInputs;\n    wire [3:0] ALU_OP;\n    \n    assign aluOpEncoderInputs[0] = R_add || R_addw || I_addi || I_addiw;\n    assign aluOpEncoderInputs[1] = R_sub || R_subw;\n    assign aluOpEncoderInputs[2] = R_and || I_andi;\n    assign aluOpEncoderInputs[3] = R_or || I_ori;\n    assign aluOpEncoderInputs[4] = R_xor || I_xori;\n    assign aluOpEncoderInputs[5] = R_sll || R_sllw || I_slli || I_slliw;\n    assign aluOpEncoderInputs[6] = R_srl || R_srlw || I_srli || I_srliw;\n    assign aluOpEncoderInputs[7] = R_sra || R_sraw || I_srai || I_sraiw;\n    assign aluOpEncoderInputs[8] = R_mul || R_mulw;\n    assign aluOpEncoderInputs[9] = R_mulh;\n    assign aluOpEncoderInputs[10] = R_div || R_divw;\n    assign aluOpEncoderInputs[11] = R_rem || R_remw;\n    assign aluOpEncoderInputs[12] = R_slt || I_slti;\n    assign aluOpEncoderInputs[13] = R_sltu || I_sltiu;\n    assign aluOpEncoderInputs[14] = 0;\n    assign aluOpEncoderInputs[15] = 0;\n    Encoder_16 aluOpEncoder(aluOpEncoderInputs, ALU_OP);\n\n    // -- ALU Input Selection Encoders\n    wire [3:0] aluX1SelectionInputs;\n    wire [3:0] aluX2SelectionInputs;\n    wire [1:0] ALU_X1_SEL;\n    wire [1:0] ALU_X2_SEL;\n    \n    assign aluX1SelectionInputs[0] = 1;\n    assign aluX1SelectionInputs[1] = B_TYPE || U_TYPE_JUMP || U_TYPE_AUIPC || I_TYPE_JUMP;\n    assign aluX1SelectionInputs[2] = U_TYPE_LOAD;\n    assign aluX1SelectionInputs[3] = 0; //DATA_DEPENDENCY_HAZARD_R1_WRITEBACK && B_TYPE == 0 && I_TYPE_JUMP == 0;\n    //assign aluX1SelectionInputs[4] = 0; //DATA_DEPENDENCY_HAZARD_R1 && B_TYPE == 0 && I_TYPE_JUMP == 0;\n    //assign aluX1SelectionInputs[5] = 0;\n    //assign aluX1SelectionInputs[6] = 0;\n    //assign aluX1SelectionInputs[7] = 0;\n\n    assign aluX2SelectionInputs[0] = 1;\n    assign aluX2SelectionInputs[1] = S_TYPE || I_TYPE || B_TYPE || U_TYPE;    \n    assign aluX2SelectionInputs[2] = 0; //DATA_DEPENDENCY_HAZARD_R2_WRITEBACK && (S_TYPE || B_TYPE || U_TYPE) == 0;\n    assign aluX2SelectionInputs[3] = 0; //DATA_DEPENDENCY_HAZARD_R2 && (S_TYPE || B_TYPE || U_TYPE) == 0;\n    Encoder_4 aluX1SelectionEncoder(aluX1SelectionInputs, ALU_X1_SEL);\n    Encoder_4 aluX2SelectionEncoder(aluX2SelectionInputs, ALU_X2_SEL);\n\n    // -- ALU\n    reg [63:0] ALU_X1;\n    reg [63:0] ALU_X2;\n    wire [63:0] ALU_OUT;\n    wire isALUEqual;\n    ALU alu(ALU_X1, ALU_X2, ALU_OP, ALU_OUT, isALUEqual);\n\n    always @(*) begin\n        case(ALU_X1_SEL)\n            0: ALU_X1 <= R1_DATA;\n            1: ALU_X1 <= PC_EXECUTE_3;\n            //2: ALU_X1 <= 0;\n            //3: ALU_X1 <= REG_WRITE_DATA_WRITEBACK_5; // USE WRITEBACK output directly (Data Hazard fix)\n            //4: ALU_X1 <= ALU_OUT_MEMORY_4; // USE ALU output directly (Data Hazard fix)\n            default: ALU_X1 <= 0;\n        endcase\n\n        case(ALU_X2_SEL)\n            0: ALU_X2 <= R2_DATA;\n            1: ALU_X2 <= IMMEDIATE_VALUE;\n            //2: ALU_X2 <= REG_WRITE_DATA_WRITEBACK_5; // USE WRITEBACK output directly (Data Hazard fix)\n            //3: ALU_X2 <= ALU_OUT_MEMORY_4; // USE ALU output directly (Data Hazard fix)\n            default: ALU_X2 <= 0;\n        endcase\n    end\n\n\n\n\n    // -- RegFile\n    // Decoding OPCODE for 5th stage of pipeline.\n    wire [6:0] OPCODE_WRITEBACK_5 = INSTRUCTION_WRITEBACK_5[6:0];\n    wire WB_R_TYPE         = OPCODE_WRITEBACK_5 == OP_R_TYPE;\n    wire WB_R_TYPE_64      = OPCODE_WRITEBACK_5 == OP_R_TYPE_64;\n    wire WB_I_TYPE_LOAD    = OPCODE_WRITEBACK_5 == OP_I_TYPE_LOAD;\n    wire WB_I_TYPE_OTHER   = OPCODE_WRITEBACK_5 == OP_I_TYPE_OTHER;\n    wire WB_I_TYPE_64      = OPCODE_WRITEBACK_5 == OP_I_TYPE_64;\n    wire WB_I_TYPE_JUMP    = OPCODE_WRITEBACK_5 == OP_I_TYPE_JUMP;\n    wire WB_I_TYPE         = WB_I_TYPE_JUMP || WB_I_TYPE_LOAD || WB_I_TYPE_OTHER || WB_I_TYPE_64;\n    wire WB_U_TYPE_LOAD    = OPCODE_WRITEBACK_5 == OP_U_TYPE_LOAD;\n    wire WB_U_TYPE_JUMP    = OPCODE_WRITEBACK_5 == OP_U_TYPE_JUMP;\n    wire WB_U_TYPE_AUIPC   = OPCODE_WRITEBACK_5 == OP_U_TYPE_AUIPC;\n    wire WB_U_TYPE         = WB_U_TYPE_JUMP || WB_U_TYPE_LOAD || WB_U_TYPE_AUIPC;\n\n    wire REG_WRITE_ENABLE = WB_R_TYPE || WB_R_TYPE_64 || WB_I_TYPE || WB_U_TYPE;\n\n    // -- Register Write Back Selection Encoder\n    wire [3:0] regWritebackSelectionInputs;\n    wire [1:0] REG_WRITEBACK_SELECTION;\n\n    assign regWritebackSelectionInputs[0] = 0;\n    assign regWritebackSelectionInputs[1] = WB_R_TYPE || WB_R_TYPE_64 || WB_U_TYPE_LOAD || WB_I_TYPE_OTHER || WB_I_TYPE_64;\n    assign regWritebackSelectionInputs[2] = WB_U_TYPE_JUMP || WB_I_TYPE_JUMP;\n    assign regWritebackSelectionInputs[3] = WB_I_TYPE_LOAD;\n    \n    Encoder_4 writeBackSelectionEncoder(regWritebackSelectionInputs, REG_WRITEBACK_SELECTION);    \n\n\n    wire signed[63:0] R1_DATA_EXECUTE_3;\n    wire signed [63:0] R2_DATA_EXECUTE_3;\n\n    wire [63:0] REG_WRITE_DATA = REG_WRITEBACK_SELECTION == 3 ? RAM_READ_DATA_WRITEBACK_5 : REG_WRITE_DATA_WRITEBACK_5;\n\n    RegFile regFile(R1, R2, RD, REG_WRITE_DATA, REG_WRITE_ENABLE, R1_DATA_EXECUTE_3, R2_DATA_EXECUTE_3);\n\n\n\n    // == PIPELINING ==================================================    \n    // -- 1. Stage: Fetch\n    reg [9:0] PC = 0;\n    assign INSTRUCTION_ADDR = PC >> 2;\n\n    always @(posedge CLK) begin\n        if (PC_ALU_SEL == 1) begin\n            PC <= ALU_OUT[9:0];\n        end\n        else begin\n            if (LOAD_STALL == 1 || CONTROL_HAZARD_STALL == 1)\n                PC <= PC; \n            else\n                PC <= PC + 4;\n        end        \n\n        // PIPELINE HAZARD DATA REGISTERS\n        if (CONTROL_HAZARD_STALL == 1) begin\n            R1_PIPELINE[DECODE]      <= 0;\n            R2_PIPELINE[DECODE]      <= 0;\n            RD_PIPELINE[DECODE]      <= 0;\n            TYPE_PIPELINE[DECODE]    <= TYPE_IMMEDIATE;\n        end\n        else begin\n            R1_PIPELINE[DECODE] <= INSTRUCTION[19:15];\n            R2_PIPELINE[DECODE] <= INSTRUCTION[24:20];\n            RD_PIPELINE[DECODE] <= INSTRUCTION[11:7];\n\n            if (INSTRUCTION[6:0] == OP_R_TYPE || INSTRUCTION[6:0] == OP_R_TYPE_64) // R-Type\n                TYPE_PIPELINE[DECODE] <= TYPE_REGISTER;\n                \n            else if (INSTRUCTION[6:0] == OP_I_TYPE_LOAD) // Load\n                TYPE_PIPELINE[DECODE] <= TYPE_LOAD;\n\n            else if (INSTRUCTION[6:0] == OP_S_TYPE) // Store\n                TYPE_PIPELINE[DECODE] <= TYPE_STORE;\n\n            else if (INSTRUCTION[6:0] == OP_I_TYPE_OTHER || INSTRUCTION[6:0] == OP_I_TYPE_64 || INSTRUCTION[6:0] == OP_I_TYPE_JUMP) // Immediate\n                TYPE_PIPELINE[DECODE] <= TYPE_IMMEDIATE;\n\n            else if (INSTRUCTION[6:0] == OP_B_TYPE[6:0]) // Branch\n                TYPE_PIPELINE[DECODE] <= TYPE_BRANCH;\n        end\n    end\n\n\n    // -- 2. Stage: Decode\n    reg [9:0] PC_DECODE_2 = 0;\n    reg [31:0] INSTRUCTION_DECODE_2 = 0;\n\n    always @(posedge CLK) begin\n        if (LOAD_STALL == 1) begin\n            INSTRUCTION_DECODE_2 <= INSTRUCTION_DECODE_2;\n            PC_DECODE_2 <= PC_DECODE_2;\n        end\n        else if (CONTROL_HAZARD_STALL == 1) begin\n            INSTRUCTION_DECODE_2 <= 32'h00000013;\n            PC_DECODE_2 <= PC_DECODE_2;\n        end\n        else begin\n            INSTRUCTION_DECODE_2 <= INSTRUCTION;\n            PC_DECODE_2 <= PC;\n        end\n        \n        \n        // Pipeline Type\n        if (INSTRUCTION_DECODE_2[6:0] == OP_R_TYPE || INSTRUCTION_DECODE_2[6:0] == OP_R_TYPE_64) // R-Type\n            TYPE_PIPELINE[EXECUTE] <= TYPE_REGISTER;\n            \n        else if (INSTRUCTION_DECODE_2[6:0] == OP_I_TYPE_LOAD) // Load\n            TYPE_PIPELINE[EXECUTE] <= TYPE_LOAD;\n\n        else if (INSTRUCTION_DECODE_2[6:0] == OP_S_TYPE) // Store\n            TYPE_PIPELINE[EXECUTE] <= TYPE_STORE;\n\n        else if (INSTRUCTION_DECODE_2[6:0] == OP_I_TYPE_OTHER || INSTRUCTION_DECODE_2[6:0] == OP_I_TYPE_64 || INSTRUCTION_DECODE_2[6:0] == OP_I_TYPE_JUMP) // Immediate\n            TYPE_PIPELINE[EXECUTE] <= TYPE_IMMEDIATE;\n\n        else if (INSTRUCTION_DECODE_2[6:0] == OP_B_TYPE[6:0]) // Branch\n            TYPE_PIPELINE[EXECUTE] <= TYPE_BRANCH;\n        \n        R1_PIPELINE[EXECUTE] <= INSTRUCTION_DECODE_2[19:15];\n        R2_PIPELINE[EXECUTE] <= INSTRUCTION_DECODE_2[24:20];\n        RD_PIPELINE[EXECUTE] <= INSTRUCTION_DECODE_2[11:7];\n\n        \n        if (LOAD_STALL == 1) begin\n            R1_PIPELINE[EXECUTE]      <= 0;\n            R2_PIPELINE[EXECUTE]      <= 0;\n            RD_PIPELINE[EXECUTE]      <= 0;\n            TYPE_PIPELINE[EXECUTE]    <= TYPE_IMMEDIATE;\n        end\n    end\n\n\n    // -- 3. Stage: Execute\n    reg [9:0] PC_EXECUTE_3 = 0;\n    reg [31:0] INSTRUCTION_EXECUTE_3 = 0;\n\n    always @(posedge CLK) begin\n        if (LOAD_STALL == 1 ) begin\n            INSTRUCTION_EXECUTE_3 <= 32'h00000013; // NOP for Stall\n            PC_EXECUTE_3 <= PC_EXECUTE_3;\n        end\n        else begin\n            PC_EXECUTE_3 <= PC_DECODE_2;\n            INSTRUCTION_EXECUTE_3 <= INSTRUCTION_DECODE_2;\n        end\n\n        if (INSTRUCTION_EXECUTE_3[6:0] == OP_R_TYPE || INSTRUCTION_EXECUTE_3[6:0] == OP_R_TYPE_64) // R-Type\n            TYPE_PIPELINE[MEMORY] <= TYPE_REGISTER;\n            \n        else if (INSTRUCTION_EXECUTE_3[6:0] == OP_I_TYPE_LOAD) // Load\n            TYPE_PIPELINE[MEMORY] <= TYPE_LOAD;\n\n        else if (INSTRUCTION_EXECUTE_3[6:0] == OP_S_TYPE) // Store\n            TYPE_PIPELINE[MEMORY] <= TYPE_STORE;\n\n        else if (INSTRUCTION_EXECUTE_3[6:0] == OP_I_TYPE_OTHER || INSTRUCTION_EXECUTE_3[6:0] == OP_I_TYPE_64 || INSTRUCTION_EXECUTE_3[6:0] == OP_I_TYPE_JUMP) // Immediate\n            TYPE_PIPELINE[MEMORY] <= TYPE_IMMEDIATE;\n\n        else if (INSTRUCTION_EXECUTE_3[6:0] == OP_B_TYPE[6:0]) // Branch\n            TYPE_PIPELINE[MEMORY] <= TYPE_BRANCH;\n        \n        R1_PIPELINE[MEMORY] <= INSTRUCTION_EXECUTE_3[19:15];\n        R2_PIPELINE[MEMORY] <= INSTRUCTION_EXECUTE_3[24:20];\n        RD_PIPELINE[MEMORY] <= INSTRUCTION_EXECUTE_3[11:7];\n    end    \n\n\n    // -- 4. Stage: Memory\n    reg [9:0] PC_MEMORY_4 = 0;\n    reg [31:0] INSTRUCTION_MEMORY_4 = 0;\n    reg [63:0] ALU_OUT_MEMORY_4 = 0;\n\n    always @(posedge CLK) begin\n        INSTRUCTION_MEMORY_4 <= INSTRUCTION_EXECUTE_3;\n        PC_MEMORY_4 <= PC_EXECUTE_3;\n\n        ALU_OUT_MEMORY_4 <= ALU_OUT;\n        RAM_WRITE_DATA <= R2_DATA;\n        \n\n        if (INSTRUCTION_MEMORY_4[6:0] == OP_R_TYPE || INSTRUCTION_MEMORY_4[6:0] == OP_R_TYPE_64) // R-Type\n            TYPE_PIPELINE[WRITEBACK] <= TYPE_REGISTER;\n            \n        else if (INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_LOAD) // Load\n            TYPE_PIPELINE[WRITEBACK] <= TYPE_LOAD;\n\n        else if (INSTRUCTION_MEMORY_4[6:0] == OP_S_TYPE) // Store\n            TYPE_PIPELINE[WRITEBACK] <= TYPE_STORE;\n\n        else if (INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_OTHER || INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_64 || INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_JUMP) // Immediate\n            TYPE_PIPELINE[WRITEBACK] <= TYPE_IMMEDIATE;\n\n        else if (INSTRUCTION_MEMORY_4[6:0] == OP_B_TYPE[6:0]) // Branch\n            TYPE_PIPELINE[WRITEBACK] <= TYPE_BRANCH;\n        \n        R1_PIPELINE[WRITEBACK] <= INSTRUCTION_MEMORY_4[19:15];\n        R2_PIPELINE[WRITEBACK] <= INSTRUCTION_MEMORY_4[24:20];\n        RD_PIPELINE[WRITEBACK] <= INSTRUCTION_MEMORY_4[11:7];\n    end\n\n\n    // -- 5. Stage: WriteBack\n    reg [31:0] INSTRUCTION_WRITEBACK_5 = 0;\n    reg [63:0] REG_WRITE_DATA_WRITEBACK_5 = 0;\n    reg [63:0] RAM_READ_DATA_WRITEBACK_5 = 0;\n    \n    always @(posedge CLK) begin\n        INSTRUCTION_WRITEBACK_5 <= INSTRUCTION_MEMORY_4;\n        RAM_READ_DATA_WRITEBACK_5 <= RAM_READ_DATA;\n\n        //REG_WRITE_DATA_WRITEBACK_5 <= ALU_OUT_MEMORY_4;\n        case (REG_WRITEBACK_SELECTION)\n            1: REG_WRITE_DATA_WRITEBACK_5 <= ALU_OUT_MEMORY_4;\n            2: REG_WRITE_DATA_WRITEBACK_5 <= PC_MEMORY_4 + 4;\n        endcase\n    end\n\n\n\n\n\n\n    // GTK WAVE trick to show Arrays. NOT NECESSARY:\n    generate\n        genvar idx;\n        for(idx = 0; idx < 4; idx = idx+1) begin: PIPELINE\n            wire [4:0] R1 = R1_PIPELINE[idx];\n            wire [4:0] R2 = R2_PIPELINE[idx];\n            wire [4:0] RD = RD_PIPELINE[idx];\n            wire [2:0] TYPE = TYPE_PIPELINE[idx];\n        end\n    endgenerate\nendmodule\n"
  },
  {
    "path": "src/Encoders.v",
    "content": "module Encoder_4 (\n    input [3:0] in,\n    output reg [1:0] out\n  );\n  initial begin\n    out = 0;\n  end\n\n  always @(in) begin\n    casex (in)\n      4'b1xxx : out = 3;\n      4'b01xx : out = 2;\n      4'b001x : out = 1;\n      4'b0001 : out = 0;\n      4'b0000 : out = 0;\n      default: out = 0;\n    endcase\n  end\nendmodule\n\nmodule Encoder_8 (\n    input [7:0] in,\n    output reg [2:0] out\n  );\n  initial begin\n    out = 0;\n  end\n  \n  always @(in) begin\n    casex (in)\n      8'b1xxxxxxx : out = 7;\n      8'b01xxxxxx : out = 6;\n      8'b001xxxxx : out = 5;\n      8'b0001xxxx : out = 4;\n      8'b00001xxx : out = 3;\n      8'b000001xx : out = 2;\n      8'b0000001x : out = 1;\n      8'b00000001 : out = 0;\n      8'b00000000 : out = 0;\n      default: out = 0;\n    endcase\n  end\n  \nendmodule\n\nmodule Encoder_16 (\n    input [15:0] in,\n    output reg [3:0] out\n  );\n  initial begin\n    out = 0;\n  end\n  \n  always @(in) begin\n    casex (in)\n      16'b1xxxxxxxxxxxxxxx : out = 15;\n      16'b01xxxxxxxxxxxxxx : out = 14;\n      16'b001xxxxxxxxxxxxx : out = 13;\n      16'b0001xxxxxxxxxxxx : out = 12;\n      16'b00001xxxxxxxxxxx : out = 11;\n      16'b000001xxxxxxxxxx : out = 10;\n      16'b0000001xxxxxxxxx : out = 9;\n      16'b00000001xxxxxxxx : out = 8;\n      16'b000000001xxxxxxx : out = 7;\n      16'b0000000001xxxxxx : out = 6;\n      16'b00000000001xxxxx : out = 5;\n      16'b000000000001xxxx : out = 4;\n      16'b0000000000001xxx : out = 3;\n      16'b00000000000001xx : out = 2;\n      16'b000000000000001x : out = 1;\n      16'b0000000000000001 : out = 0;\n      16'b0000000000000000 : out = 0;\n      default: out = 0;\n    endcase\n  end\n  \nendmodule"
  },
  {
    "path": "src/ImmediateExtractor.v",
    "content": "module ImmediateExtractor(\n    input [31:0] INSTRUCTION,\n    input [2:0] SELECTION,\n    output reg signed [63:0] VALUE\n);\n    wire [11:0] IMM_11_0    = INSTRUCTION[31:20];\n    wire [19:0] IMM_31_12   = INSTRUCTION[31:12];\n    wire [4:0] IMM_4_0      = INSTRUCTION[11:7];\n    wire [6:0] IMM_11_5     = INSTRUCTION[31:25];\n    wire IMM_11_B           = INSTRUCTION[7];\n    wire [3:0] IMM_4_1      = INSTRUCTION[11:8];\n    wire [5:0] IMM_10_5     = INSTRUCTION[30:25];\n    wire IMM_12             = INSTRUCTION[31];\n    wire [7:0] IMM_19_12    = INSTRUCTION[19:12];\n    wire IMM_11_J           = INSTRUCTION[20];\n    wire [9:0] IMM_10_1     = INSTRUCTION[30:21];\n    wire IMM_20             = INSTRUCTION[31];\n\n    // Extend bits and get immediate values of types.    \n    wire signed [63:0] Imm_I = { {64{IMM_11_0[11]}}, IMM_11_0 };\n    wire signed [63:0] Imm_U = { {64{IMM_31_12[19]}}, IMM_31_12, 12'h000 };\n    wire signed [63:0] Imm_B = { {64{IMM_12}}, IMM_11_B, IMM_10_5, IMM_4_1, 1'b0 };\n    wire signed [63:0] Imm_S = { {64{IMM_11_5[6]}}, IMM_11_5, IMM_4_0 };\n    wire signed [63:0] Imm_UJ = { {64{IMM_20}}, IMM_19_12, IMM_11_J, IMM_10_1, 1'b0 };\n\n    always @(*) begin\n        case (SELECTION)\n            1: VALUE = Imm_I;\n            2: VALUE = Imm_U;\n            3: VALUE = Imm_S;\n            4: VALUE = Imm_B;\n            5: VALUE = Imm_UJ;\n            default : VALUE = 0;\n        endcase\n    end\nendmodule\n"
  },
  {
    "path": "src/RAM.v",
    "content": "module RAM(\n    input [9:0] ADDRESS,\n    input [63:0] DATA_IN,\n    input WRITE_ENABLE,\n    input CLK,\n    \n    output [63:0] DATA_OUT\n);\n    reg [63:0] memory [1023:0];\n\n    initial begin\n        for(int i=0; i<1024; i=i+1) begin\n            memory[i] <= 0;\n        end\n    end\n\n    assign DATA_OUT = memory[ADDRESS];\n\n    always @(posedge CLK) begin\n        if (WRITE_ENABLE)\n            memory[ADDRESS] <= DATA_IN;\n    end\n\nendmodule"
  },
  {
    "path": "src/ROM.v",
    "content": "module ROM(\n    input [9:0] ADDRESS,    \n    output [31:0] DATA\n);\n    reg [31:0] memory [1023:0]; // 10-bit address. 32-bit cell size.\n\n    assign DATA = memory[ADDRESS];\n\n    initial begin\n        // Example program:\n\n        memory[0] = 32'h00000013; // nop (add x0 x0 0)\n        \n        // start:\n        memory[1] = 32'h00100093; // addi x1 x0 1\n        memory[2] = 32'h00100313; // addi x6 x0 1\n        memory[3] = 32'h00400613; // addi x12 x0 4\n        memory[4] = 32'h0060A023; // sw x6 0(x1)        x6 R2 Dep (WB)\n\n        // loop:\n        memory[5] = 32'h0000A303; // lw x6 0(x1)        \n        memory[6] = 32'h00130313; // addi x6 x6 1       LoadStall and x6 R1 Dep (WB)\n        memory[7] = 32'h0060A023; // sw x6 0(x1)        x6 R2 Dep\n        memory[8] = 32'hFEC34AE3; // blt x6 x12 -12     x6 R1 Dep (WB)\n\n        // data_dep_test:\n        memory[9] = 32'h03700413; // addi x8 x0 55\n        memory[10] = 32'h00800433; // add x8 x0 x8      x8 R2 Dep\n        memory[11] = 32'h00140413; // addi x8 x8 1      x8 R1 Dep\n        \n        // finish:\n        memory[12] = 32'h00000013; // nop (add x0 x0 0)\n    end\nendmodule\n"
  },
  {
    "path": "src/RegFile.v",
    "content": "module RegFile(\n    input [4:0]R1,\n    input [4:0]R2,\n    input [4:0]RD,\n    input [63:0]RD_DATA,\n    input WRITE_ENABLE,\n\n    output [63:0]R1_DATA,\n    output [63:0]R2_DATA\n);\n    reg [63:0] REGISTERS[31:0]; // 64 Bit length, 32 Registers\n\n    integer i = 0;\n    initial begin\n        for (i = 0; i< 32 ; i = i + 1) begin\n            REGISTERS[i] <= 0;\n        end\n    end\n\n    assign R1_DATA = REGISTERS[R1];\n    assign R2_DATA = REGISTERS[R2];\n\n    always @(*) begin\n        if (WRITE_ENABLE == 1 && RD != 0)\n            REGISTERS[RD] <= RD_DATA;\n    end\n    \n\n    // GTK WAVE trick to show Arrays. NOT NECESSARY:\n    generate\n        genvar idx;\n        for(idx = 1; idx < 31; idx = idx+1) begin: REG_DATAS\n            wire [63:0] R_DATA = REGISTERS[idx];\n        end\n    endgenerate\nendmodule\n"
  },
  {
    "path": "testbench/run_main_test.sh",
    "content": "#!/bin/bash\nif [ ! -d \"./output\" ]; then\n    mkdir output;\nfi\n\necho \"== Main Test =============\" &&\niverilog -g2005-sv -I ../src/ -o output/tb_main tb_Main.v && vvp output/tb_main &&\necho \"DONE!\" || echo \"An error occured!\";"
  },
  {
    "path": "testbench/run_tests.sh",
    "content": "#!/bin/bash\nif [ ! -d \"./output\" ]; then\n    mkdir output;\nfi\n\necho \"== Encoders Test ========================\" &&\niverilog -g2005-sv -I ../src/ -o output/tb_encoders tb_Encoders.v && vvp output/tb_encoders &&\necho \"== ALU Test ============================\" &&\niverilog -g2005-sv -I ../src/ -o output/tb_alu tb_ALU.v && vvp output/tb_alu &&\necho \"== RegFile Test=========================\" &&\niverilog -g2005-sv -I ../src/ -o output/tb_regfile tb_RegFile.v && vvp output/tb_regfile && \necho \"== ImmediateExtractor Test =============\" &&\niverilog -g2005-sv -I ../src/ -o output/tb_immediateextractor tb_ImmediateExtractor.v && vvp output/tb_immediateextractor &&\necho \"== RAM Test ============================\" &&\niverilog -g2005-sv -I ../src/ -o output/tb_ram tb_RAM.v && vvp output/tb_ram &&\necho \"== ROM Test ============================\" &&\niverilog -g2005-sv -I ../src/ -o output/tb_rom tb_ROM.v && vvp output/tb_rom &&\necho \"========================================\" &&\necho \"Test finished.\" || echo \"ERROR: One of the modules has been failed to compile!\";"
  },
  {
    "path": "testbench/tb_ALU.v",
    "content": "`include \"ALU.v\"\n`timescale 1ns / 100ps \n\nmodule tb_ALU;\n    reg [63:0] a;\n    reg [63:0] b;\n    reg [3:0]  op;\n\n    wire [63:0] result;\n    wire isEqual;\n\n    ALU alu(a, b, op, result, isEqual);\n\n    initial begin\n        // add\n        a = 5;          b = 5;      op = 0; #20;\n        // sub\n        a = 66;         b = 11;     op = 1; #20;        \n        // and\n        a = 3'b101;     b = 3'b110; op = 2; #20;\n        // or\n        a = 3'b101;     b = 3'b110; op = 3; #20;\n        // xor\n        a = 3'b110;     b = 3'b010; op = 4; #20;\n        // sll (Shift Left Logical)\n        a = 1;          b = 3;      op = 5; #20;\n        // srl (Shift Right Logical)\n        a = 8;          b = 2;      op = 6; #20;\n        // sra (Shift Right Arithmetic)\n        a = -8;         b = 2;      op = 7; #20;\n        // mul\n        a = 6;          b = 5;      op = 8; #20;\n        // mulh\n        a = 64'h8000000000000000;   b = 4;  op = 9; #20; // output will be ...0010 = 2\n        // div\n        a = 66;         b = 11;     op = 10; #20;\n        // rem\n        a = 62;         b = 3;      op = 11; #20;\n        // slt (Set Less Than)\n        a = -1;         b = 9;      op = 12; #20;\n        // sltu (Set Less Than Unsigned)\n        a = -1;         b = 9;      op = 13; #20;\n    end\n\n    initial begin\n        $dumpfile(\"vcd/alu.vcd\");\n        $dumpvars(0, tb_ALU);\n    end\nendmodule"
  },
  {
    "path": "testbench/tb_Encoders.v",
    "content": "`include \"Encoders.v\"\n\n`timescale 1ns / 100ps \n\nmodule tb_Encoders;\n    reg [15:0] in = 0;\n    reg [3:0] out4;\n    reg [2:0] out3;\n    reg [1:0] out2;\n\n    Encoder_16 enc(in, out4);\n    Encoder_8 enc8(in[7:0], out3);\n    Encoder_4 enc4(in[3:0], out2);\n\n    initial begin\n        in = 16'b0000000000000000; #20;\n        in = 16'b0000000000000001; #20;\n        in = 16'b0000000000000010; #20;\n        in = 16'b0000000000000100; #20;\n        in = 16'b0000000000001000; #20;\n        in = 16'b0000000000010000; #20;\n        in = 16'b0000000000100000; #20;\n        in = 16'b0000000001000000; #20;\n        in = 16'b0000000010000000; #20;\n        in = 16'b0000000100000000; #20;\n        in = 16'b0000001000000000; #20;\n        in = 16'b0000010000000000; #20;\n        in = 16'b0000100000000000; #20;\n        in = 16'b0001000000000000; #20;\n        in = 16'b0010000000000000; #20;\n        in = 16'b0100000000000000; #20;\n        in = 16'b1000000000000000; #20;\n        in = 16'b1000000000000001; #20;\n        in = 16'b0000000100000001; #20;\n        in = 16'b0000000000000011; #20;\n        in = 16'b0000000000000000; #20;\n        \n    end\n\n    initial begin\n        $dumpfile(\"vcd/encoders.vcd\");\n        $dumpvars(0, tb_Encoders);\n    end\n\nendmodule"
  },
  {
    "path": "testbench/tb_ImmediateExtractor.v",
    "content": "`include \"ImmediateExtractor.v\"\n`timescale 1ns / 100ps \n\nmodule tb_ImmediateExtractor;\n    reg [31:0] INSTRUCTION;\n    reg [2:0] SELECTION;\n    reg signed [63:0] VALUE;\n\n    ImmediateExtractor ie(INSTRUCTION, SELECTION, VALUE);\n\n    initial begin\n        INSTRUCTION = 32'h00A00613; // addi x12 x0 10  // Expects: 10\n        SELECTION = 1; // I Type\n        #20;\n\n        INSTRUCTION = 32'h00001337; // lui x6 1  // Expects: 4096\n        SELECTION = 2; // U Type\n        #20;\n\n        INSTRUCTION = 32'h00B323A3; // sw x11 7(x6) // Expects: 7\n        SELECTION = 3; // S Type\n        #20;\n\n        INSTRUCTION = 32'hFEC5CAE3; // blt x11 x12 -12 // Expects: -12\n        SELECTION = 4; // B Type\n        #20;\n\n        INSTRUCTION = 32'h4000006F; // jal x0 1024 // Expects: 1024\n        SELECTION = 5; // UJ Type\n        #20;\n    end\n\n    initial begin\n        $dumpfile(\"vcd/immediateextractor.vcd\");\n        $dumpvars(0, tb_ImmediateExtractor);\n    end\nendmodule"
  },
  {
    "path": "testbench/tb_Main.v",
    "content": "`include \"CPU.v\"\n`include \"RAM.v\"\n`include \"ROM.v\"\n`timescale 1ns / 100ps \n\nmodule tb_Main;\n    wire [9:0] RAM_ADDR;\n    wire [63:0] RAM_READ_DATA;\n    wire [63:0] RAM_WRITE_DATA;\n    wire RAM_WRITE_ENABLE;\n\n    wire [9:0] INSTRUCTION_ADDR;\n    wire [31:0] INSTRUCTION;\n    reg CLK = 1;\n    \n    CPU cpu(\n        .RAM_READ_DATA(RAM_READ_DATA),\n        .INSTRUCTION(INSTRUCTION),\n        .CLK(CLK),\n\n        .RAM_ADDR(RAM_ADDR),\n        .RAM_WRITE_DATA(RAM_WRITE_DATA),\n        .RAM_WRITE_ENABLE(RAM_WRITE_ENABLE),\n        .INSTRUCTION_ADDR(INSTRUCTION_ADDR)\n    );\n    \n    ROM rom(\n        .ADDRESS(INSTRUCTION_ADDR),\n\n        .DATA(INSTRUCTION)\n    );\n\n    RAM ram(\n        .ADDRESS(RAM_ADDR),\n        .DATA_IN(RAM_WRITE_DATA),\n        .WRITE_ENABLE(RAM_WRITE_ENABLE),\n        .CLK(CLK),\n\n        .DATA_OUT(RAM_READ_DATA)    \n    );\n\n    initial begin\n        for(int i=0; i<40; i=i+1) begin\n            CLK=1; #20; CLK=0; #20;\n        end\n    end\n\n    initial begin\n        $dumpfile(\"vcd/main.vcd\");\n        $dumpvars(0, tb_Main);\n    end\n    \nendmodule"
  },
  {
    "path": "testbench/tb_RAM.v",
    "content": "`include \"RAM.v\"\n`timescale 1ns / 100ps \n\nmodule tb_RAM;\n    reg [9:0] ADDRESS;\n    reg [63:0] DATA_IN;\n    reg WRITE_ENABLE;\n    reg CLK;\n\n    reg [63:0] DATA_OUT;\n\n    RAM ram(ADDRESS, DATA_IN, WRITE_ENABLE, CLK, DATA_OUT);\n\n    initial begin\n        // Write #1\n        ADDRESS = 1;\n        DATA_IN = 55;\n        WRITE_ENABLE = 1;\n        CLK = 1; #20; CLK = 0; #20;\n\n        // Write #2\n        ADDRESS = 2;\n        DATA_IN = 99;\n        WRITE_ENABLE = 1;\n        CLK = 1; #20; CLK = 0; #20;\n\n        // Read #1\n        ADDRESS = 1;\n        WRITE_ENABLE = 0;\n        DATA_IN = 0;\n        CLK = 1; #20; CLK = 0; #20;\n\n        // Read #2\n        ADDRESS = 2;\n        WRITE_ENABLE = 0;\n        DATA_IN = 0;\n        CLK = 1; #20; CLK = 0; #20;\n    end\n\n    initial begin\n        $dumpfile(\"vcd/ram.vcd\");\n        $dumpvars(0, tb_RAM);\n    end\nendmodule"
  },
  {
    "path": "testbench/tb_ROM.v",
    "content": "`include \"ROM.v\"\n`timescale 1ns / 100ps \n\nmodule tb_ROM;\n    reg [9:0] ADDRESS;\n    reg [31:0] DATA_OUT;\n\n    ROM rom(ADDRESS, DATA_OUT);\n\n    initial begin\n        ADDRESS = 0; #20;\n        ADDRESS = 1; #20;\n        ADDRESS = 2; #20;\n        ADDRESS = 3; #20;\n        ADDRESS = 4; #20;\n        ADDRESS = 5; #20;\n        ADDRESS = 20; #20;\n    end\n\n    initial begin\n        $dumpfile(\"vcd/rom.vcd\");\n        $dumpvars(0, tb_ROM);\n    end\nendmodule"
  },
  {
    "path": "testbench/tb_RegFile.v",
    "content": "`include \"RegFile.v\"\n`timescale 1ns / 100ps \n\nmodule tb_RegFile;\n    reg [4:0]R1;\n    reg [4:0]R2;\n    reg [4:0]RD;\n    reg [63:0]RD_DATA;\n    reg reg_write_enable;\n\n    wire [63:0]R1_data;\n    wire [63:0]R2_data;\n\n    RegFile regfile(R1, R2, RD, RD_DATA, reg_write_enable, R1_data, R2_data );\n\n    initial begin\n        R1 = 0;\n        R2 = 0;\n        RD = 0;\n        RD_DATA = 0;\n        reg_write_enable = 0;\n        #20;\n\n        R1 = 0;\n        R2 = 0;\n        RD = 1;\n        RD_DATA = 5;\n        reg_write_enable = 1;\n        #20;\n\n        R1 = 1;\n        R2 = 0;\n        RD = 2;\n        RD_DATA = 10;\n        reg_write_enable = 1;\n        #20;\n\n        R1 = 1;\n        R2 = 2;\n        RD = 0;\n        RD_DATA = 0;\n        reg_write_enable = 0;\n        #20;\n    end\n\n    initial begin\n        $dumpfile(\"vcd/regfile.vcd\");\n        $dumpvars(0, tb_RegFile);\n    end\nendmodule"
  },
  {
    "path": "testbench/vcd/alu.vcd",
    "content": "$date\n\tTue May 25 21:18:16 2021\n$end\n$version\n\tIcarus Verilog\n$end\n$timescale\n\t100ps\n$end\n$scope module tb_ALU $end\n$var wire 64 ! result [63:0] $end\n$var wire 1 \" isEqual $end\n$var reg 64 # a [63:0] $end\n$var reg 64 $ b [63:0] $end\n$var reg 4 % op [3:0] $end\n$scope module alu $end\n$var wire 4 & OP [3:0] $end\n$var wire 64 ' X [63:0] $end\n$var wire 64 ( X_signed [63:0] $end\n$var wire 64 ) Y [63:0] $end\n$var wire 64 * Y_signed [63:0] $end\n$var wire 1 \" isEqual $end\n$var wire 64 + OUTPUT [63:0] $end\n$var reg 64 , RESULT [63:0] $end\n$var reg 128 - RESULT_MULH [127:0] $end\n$upscope $end\n$upscope $end\n$enddefinitions $end\n#0\n$dumpvars\nbx -\nb1010 ,\nb1010 +\nb101 *\nb101 )\nb101 (\nb101 '\nb0 &\nb0 %\nb101 $\nb101 #\n1\"\nb1010 !\n$end\n#200\nb110111 !\nb110111 +\nb110111 ,\nb1 %\nb1 &\nb1011 *\nb1011 $\nb1011 )\nb1000010 (\n0\"\nb1000010 #\nb1000010 '\n#400\nb100 !\nb100 +\nb100 ,\nb10 %\nb10 &\nb110 *\nb110 $\nb110 )\nb101 (\nb101 #\nb101 '\n#600\nb111 !\nb111 +\nb111 ,\nb11 %\nb11 &\n#800\nb100 !\nb100 +\nb100 ,\nb100 %\nb100 &\nb10 *\nb10 $\nb10 )\nb110 (\n0\"\nb110 #\nb110 '\n#1000\nb1000 !\nb1000 +\nb1000 ,\nb101 %\nb101 &\nb11 *\nb11 $\nb11 )\nb1 (\nb1 #\nb1 '\n#1200\nb10 !\nb10 +\nb10 ,\nb110 %\nb110 &\nb10 *\nb10 $\nb10 )\nb1000 (\nb1000 #\nb1000 '\n#1400\nb1111111111111111111111111111111111111111111111111111111111111110 !\nb1111111111111111111111111111111111111111111111111111111111111110 +\nb1111111111111111111111111111111111111111111111111111111111111110 ,\nb111 %\nb111 &\nb1111111111111111111111111111111111111111111111111111111111111000 (\nb1111111111111111111111111111111111111111111111111111111111111000 #\nb1111111111111111111111111111111111111111111111111111111111111000 '\n#1600\nb11110 !\nb11110 +\nb11110 ,\nb1000 %\nb1000 &\nb101 *\nb101 $\nb101 )\nb110 (\nb110 #\nb110 '\n#1800\nb100000000000000000000000000000000000000000000000000000000000000000 -\nb10 !\nb10 +\nb1001 %\nb1001 &\nb100 *\nb100 $\nb100 )\nb1000000000000000000000000000000000000000000000000000000000000000 (\nb1000000000000000000000000000000000000000000000000000000000000000 #\nb1000000000000000000000000000000000000000000000000000000000000000 '\n#2000\nb110 ,\nb110 !\nb110 +\nb1010 %\nb1010 &\nb1011 *\nb1011 $\nb1011 )\nb1000010 (\nb1000010 #\nb1000010 '\n#2200\nb10 !\nb10 +\nb10 ,\nb1011 %\nb1011 &\nb11 *\nb11 $\nb11 )\nb111110 (\nb111110 #\nb111110 '\n#2400\nb1 !\nb1 +\nb1 ,\nb1100 %\nb1100 &\nb1001 *\nb1001 $\nb1001 )\nb1111111111111111111111111111111111111111111111111111111111111111 (\nb1111111111111111111111111111111111111111111111111111111111111111 #\nb1111111111111111111111111111111111111111111111111111111111111111 '\n#2600\nb0 !\nb0 +\nb0 ,\nb1101 %\nb1101 &\n#2800\n"
  },
  {
    "path": "testbench/vcd/encoders.vcd",
    "content": "$date\n\tMon May 24 15:33:45 2021\n$end\n$version\n\tIcarus Verilog\n$end\n$timescale\n\t100ps\n$end\n$scope module tb_Encoders $end\n$var wire 4 ! out4 [3:0] $end\n$var wire 3 \" out3 [2:0] $end\n$var wire 2 # out2 [1:0] $end\n$var reg 16 $ in [15:0] $end\n$scope module enc $end\n$var wire 16 % in [15:0] $end\n$var reg 4 & out [3:0] $end\n$upscope $end\n$scope module enc4 $end\n$var wire 4 ' in [3:0] $end\n$var reg 2 ( out [1:0] $end\n$upscope $end\n$scope module enc8 $end\n$var wire 8 ) in [7:0] $end\n$var reg 3 * out [2:0] $end\n$upscope $end\n$upscope $end\n$enddefinitions $end\n#0\n$dumpvars\nb0 *\nb0 )\nb0 (\nb0 '\nb0 &\nb0 %\nb0 $\nb0 #\nb0 \"\nb0 !\n$end\n#200\nb1 )\nb1 '\nb1 $\nb1 %\n#400\nb1 \"\nb1 *\nb1 #\nb1 (\nb10 )\nb10 '\nb1 !\nb1 &\nb10 $\nb10 %\n#600\nb10 \"\nb10 *\nb10 #\nb10 (\nb100 )\nb100 '\nb10 !\nb10 &\nb100 $\nb100 %\n#800\nb11 \"\nb11 *\nb11 #\nb11 (\nb1000 )\nb1000 '\nb11 !\nb11 &\nb1000 $\nb1000 %\n#1000\nb100 \"\nb100 *\nb0 #\nb0 (\nb10000 )\nb0 '\nb100 !\nb100 &\nb10000 $\nb10000 %\n#1200\nb101 \"\nb101 *\nb100000 )\nb101 !\nb101 &\nb100000 $\nb100000 %\n#1400\nb110 \"\nb110 *\nb1000000 )\nb110 !\nb110 &\nb1000000 $\nb1000000 %\n#1600\nb111 \"\nb111 *\nb10000000 )\nb111 !\nb111 &\nb10000000 $\nb10000000 %\n#1800\nb0 \"\nb0 *\nb0 )\nb1000 !\nb1000 &\nb100000000 $\nb100000000 %\n#2000\nb1001 !\nb1001 &\nb1000000000 $\nb1000000000 %\n#2200\nb1010 !\nb1010 &\nb10000000000 $\nb10000000000 %\n#2400\nb1011 !\nb1011 &\nb100000000000 $\nb100000000000 %\n#2600\nb1100 !\nb1100 &\nb1000000000000 $\nb1000000000000 %\n#2800\nb1101 !\nb1101 &\nb10000000000000 $\nb10000000000000 %\n#3000\nb1110 !\nb1110 &\nb100000000000000 $\nb100000000000000 %\n#3200\nb1111 !\nb1111 &\nb1000000000000000 $\nb1000000000000000 %\n#3400\nb1 )\nb1 '\nb1000000000000001 $\nb1000000000000001 %\n#3600\nb1000 !\nb1000 &\nb100000001 $\nb100000001 %\n#3800\nb1 \"\nb1 *\nb1 #\nb1 (\nb11 )\nb11 '\nb1 !\nb1 &\nb11 $\nb11 %\n#4000\nb0 \"\nb0 *\nb0 #\nb0 (\nb0 )\nb0 '\nb0 !\nb0 &\nb0 $\nb0 %\n#4200\n"
  },
  {
    "path": "testbench/vcd/immediateextractor.vcd",
    "content": "$date\n\tMon May 24 15:33:45 2021\n$end\n$version\n\tIcarus Verilog\n$end\n$timescale\n\t100ps\n$end\n$scope module tb_ImmediateExtractor $end\n$var wire 64 ! VALUE [63:0] $end\n$var reg 32 \" INSTRUCTION [31:0] $end\n$var reg 3 # SELECTION [2:0] $end\n$scope module ie $end\n$var wire 32 $ INSTRUCTION [31:0] $end\n$var wire 3 % SELECTION [2:0] $end\n$var wire 64 & Imm_UJ [63:0] $end\n$var wire 64 ' Imm_U [63:0] $end\n$var wire 64 ( Imm_S [63:0] $end\n$var wire 64 ) Imm_I [63:0] $end\n$var wire 64 * Imm_B [63:0] $end\n$var wire 4 + IMM_4_1 [3:0] $end\n$var wire 5 , IMM_4_0 [4:0] $end\n$var wire 20 - IMM_31_12 [19:0] $end\n$var wire 1 . IMM_20 $end\n$var wire 8 / IMM_19_12 [7:0] $end\n$var wire 1 0 IMM_12 $end\n$var wire 1 1 IMM_11_J $end\n$var wire 1 2 IMM_11_B $end\n$var wire 7 3 IMM_11_5 [6:0] $end\n$var wire 12 4 IMM_11_0 [11:0] $end\n$var wire 6 5 IMM_10_5 [5:0] $end\n$var wire 10 6 IMM_10_1 [9:0] $end\n$var reg 64 7 VALUE [63:0] $end\n$upscope $end\n$upscope $end\n$enddefinitions $end\n#0\n$dumpvars\nb1010 7\nb101 6\nb0 5\nb1010 4\nb0 3\n02\n01\n00\nb0 /\n0.\nb101000000000 -\nb1100 ,\nb110 +\nb1100 *\nb1010 )\nb1100 (\nb101000000000000000000000 '\nb1010 &\nb1 %\nb101000000000011000010011 $\nb1 #\nb101000000000011000010011 \"\nb1010 !\n$end\n#200\nb0 )\nb1000000000000 '\nb110 (\nb110 *\nb1000000000000 &\nb1000000000000 !\nb1000000000000 7\nb0 4\nb1 -\nb110 ,\nb11 +\nb1 /\nb0 6\nb10 #\nb10 %\nb1001100110111 \"\nb1001100110111 $\n#400\nb1011 )\nb101100110010000000000000 '\nb111 (\nb100000000110 *\nb110010100000001010 &\nb111 !\nb111 7\nb1011 4\nb101100110010 -\nb111 ,\n12\nb110010 /\n11\nb101 6\nb11 #\nb11 %\nb101100110010001110100011 \"\nb101100110010001110100011 $\n#600\nb1111111111111111111111111111111111111111111111111111111111101100 )\nb1111111111111111111111111111111111111110110001011100000000000000 '\nb1111111111111111111111111111111111111111111111111111111111110101 (\nb1111111111111111111111111111111111111111111111111111111111110100 *\nb1111111111111111111111111111111111111111111101011100011111101100 &\nb1111111111111111111111111111111111111111111111111111111111110100 !\nb1111111111111111111111111111111111111111111111111111111111110100 7\nb111111101100 4\nb11111110110001011100 -\nb10101 ,\nb1111111 3\nb1010 +\nb111111 5\n10\nb1011100 /\n01\nb1111110110 6\n1.\nb100 #\nb100 %\nb11111110110001011100101011100011 \"\nb11111110110001011100101011100011 $\n#800\nb10000000000 )\nb1000000000000000000000000000000 '\nb10000000000 (\nb10000000000 *\nb10000000000 &\nb10000000000 !\nb10000000000 7\nb10000000000 4\nb1000000000000000000 -\nb0 ,\nb100000 3\n02\nb0 +\nb100000 5\n00\nb0 /\nb1000000000 6\n0.\nb101 #\nb101 %\nb1000000000000000000000001101111 \"\nb1000000000000000000000001101111 $\n#1000\n"
  },
  {
    "path": "testbench/vcd/main.vcd",
    "content": "$date\n\tMon May 24 15:34:03 2021\n$end\n$version\n\tIcarus Verilog\n$end\n$timescale\n\t100ps\n$end\n$scope module tb_Main $end\n$var wire 1 ! RAM_WRITE_ENABLE $end\n$var wire 64 \" RAM_WRITE_DATA [63:0] $end\n$var wire 64 # RAM_READ_DATA [63:0] $end\n$var wire 10 $ RAM_ADDR [9:0] $end\n$var wire 10 % INSTRUCTION_ADDR [9:0] $end\n$var wire 32 & INSTRUCTION [31:0] $end\n$var reg 1 ' CLK $end\n$scope module cpu $end\n$var wire 1 ( B_beq $end\n$var wire 1 ) B_bge $end\n$var wire 1 * B_bgeu $end\n$var wire 1 + B_blt $end\n$var wire 1 , B_bltu $end\n$var wire 1 - B_bne $end\n$var wire 1 ' CLK $end\n$var wire 1 . CONTROL_HAZARD_STALL $end\n$var wire 1 / DATA_DEPENDENCY_HAZARD_R1 $end\n$var wire 1 0 DATA_DEPENDENCY_HAZARD_R1_WRITEBACK $end\n$var wire 1 1 DATA_DEPENDENCY_HAZARD_R2 $end\n$var wire 1 2 DATA_DEPENDENCY_HAZARD_R2_WRITEBACK $end\n$var wire 1 3 I_TYPE $end\n$var wire 1 4 I_addi $end\n$var wire 1 5 I_addiw $end\n$var wire 1 6 I_andi $end\n$var wire 1 7 I_jalr $end\n$var wire 1 8 I_lb $end\n$var wire 1 9 I_ld $end\n$var wire 1 : I_lh $end\n$var wire 1 ; I_lw $end\n$var wire 1 < I_ori $end\n$var wire 1 = I_slli $end\n$var wire 1 > I_slliw $end\n$var wire 1 ? I_slti $end\n$var wire 1 @ I_sltiu $end\n$var wire 1 A I_srai $end\n$var wire 1 B I_sraiw $end\n$var wire 1 C I_srli $end\n$var wire 1 D I_srliw $end\n$var wire 1 E I_xori $end\n$var wire 1 F LOAD_STALL $end\n$var wire 1 G PC_ALU_SEL $end\n$var wire 64 H R1_DATA_UNSIGNED [63:0] $end\n$var wire 64 I R2_DATA_UNSIGNED [63:0] $end\n$var wire 1 J REG_WRITE_ENABLE $end\n$var wire 1 K R_add $end\n$var wire 1 L R_addw $end\n$var wire 1 M R_and $end\n$var wire 1 N R_div $end\n$var wire 1 O R_divw $end\n$var wire 1 P R_mul $end\n$var wire 1 Q R_mulh $end\n$var wire 1 R R_mulw $end\n$var wire 1 S R_or $end\n$var wire 1 T R_rem $end\n$var wire 1 U R_remw $end\n$var wire 1 V R_sll $end\n$var wire 1 W R_sllw $end\n$var wire 1 X R_slt $end\n$var wire 1 Y R_sltu $end\n$var wire 1 Z R_sra $end\n$var wire 1 [ R_sraw $end\n$var wire 1 \\ R_srl $end\n$var wire 1 ] R_srlw $end\n$var wire 1 ^ R_sub $end\n$var wire 1 _ R_subw $end\n$var wire 1 ` R_xor $end\n$var wire 1 a S_sb $end\n$var wire 1 b S_sd $end\n$var wire 1 c S_sh $end\n$var wire 1 d S_sw $end\n$var wire 1 e U_TYPE $end\n$var wire 1 f U_auipc $end\n$var wire 1 g U_jal $end\n$var wire 1 h U_lui $end\n$var wire 1 i WB_I_TYPE $end\n$var wire 1 j WB_U_TYPE $end\n$var wire 4 k regWritebackSelectionInputs [3:0] $end\n$var wire 1 l isALUEqual $end\n$var wire 8 m immediateSelectionInputs [7:0] $end\n$var wire 4 n aluX2SelectionInputs [3:0] $end\n$var wire 4 o aluX1SelectionInputs [3:0] $end\n$var wire 16 p aluOpEncoderInputs [15:0] $end\n$var wire 1 q WB_U_TYPE_LOAD $end\n$var wire 1 r WB_U_TYPE_JUMP $end\n$var wire 1 s WB_U_TYPE_AUIPC $end\n$var wire 1 t WB_R_TYPE_64 $end\n$var wire 1 u WB_R_TYPE $end\n$var wire 1 v WB_I_TYPE_OTHER $end\n$var wire 1 w WB_I_TYPE_LOAD $end\n$var wire 1 x WB_I_TYPE_JUMP $end\n$var wire 1 y WB_I_TYPE_64 $end\n$var wire 1 z U_TYPE_LOAD $end\n$var wire 1 { U_TYPE_JUMP $end\n$var wire 1 | U_TYPE_AUIPC $end\n$var wire 1 } S_TYPE $end\n$var wire 1 ~ R_TYPE_64 $end\n$var wire 1 !\" R_TYPE $end\n$var wire 64 \"\" REG_WRITE_DATA [63:0] $end\n$var wire 2 #\" REG_WRITEBACK_SELECTION [1:0] $end\n$var wire 5 $\" RD [4:0] $end\n$var wire 1 ! RAM_WRITE_ENABLE $end\n$var wire 64 %\" RAM_READ_DATA [63:0] $end\n$var wire 10 &\" RAM_ADDR [9:0] $end\n$var wire 64 '\" R2_DATA_EXECUTE_3 [63:0] $end\n$var wire 64 (\" R2_DATA [63:0] $end\n$var wire 5 )\" R2 [4:0] $end\n$var wire 64 *\" R1_DATA_EXECUTE_3 [63:0] $end\n$var wire 64 +\" R1_DATA [63:0] $end\n$var wire 5 ,\" R1 [4:0] $end\n$var wire 7 -\" OPCODE_WRITEBACK_5 [6:0] $end\n$var wire 7 .\" OPCODE [6:0] $end\n$var wire 1 /\" I_TYPE_OTHER $end\n$var wire 1 0\" I_TYPE_LOAD $end\n$var wire 1 1\" I_TYPE_JUMP $end\n$var wire 1 2\" I_TYPE_64 $end\n$var wire 10 3\" INSTRUCTION_ADDR [9:0] $end\n$var wire 32 4\" INSTRUCTION [31:0] $end\n$var wire 64 5\" IMMEDIATE_VALUE [63:0] $end\n$var wire 3 6\" IMMEDIATE_SELECTION [2:0] $end\n$var wire 7 7\" FUNCT7 [6:0] $end\n$var wire 3 8\" FUNCT3 [2:0] $end\n$var wire 1 9\" B_TYPE $end\n$var wire 2 :\" ALU_X2_SEL [1:0] $end\n$var wire 2 ;\" ALU_X1_SEL [1:0] $end\n$var wire 64 <\" ALU_OUT [63:0] $end\n$var wire 4 =\" ALU_OP [3:0] $end\n$var reg 64 >\" ALU_OUT_MEMORY_4 [63:0] $end\n$var reg 64 ?\" ALU_X1 [63:0] $end\n$var reg 64 @\" ALU_X2 [63:0] $end\n$var reg 32 A\" INSTRUCTION_DECODE_2 [31:0] $end\n$var reg 32 B\" INSTRUCTION_EXECUTE_3 [31:0] $end\n$var reg 32 C\" INSTRUCTION_MEMORY_4 [31:0] $end\n$var reg 32 D\" INSTRUCTION_WRITEBACK_5 [31:0] $end\n$var reg 10 E\" PC [9:0] $end\n$var reg 10 F\" PC_DECODE_2 [9:0] $end\n$var reg 10 G\" PC_EXECUTE_3 [9:0] $end\n$var reg 10 H\" PC_MEMORY_4 [9:0] $end\n$var reg 64 I\" RAM_READ_DATA_WRITEBACK_5 [63:0] $end\n$var reg 64 J\" RAM_WRITE_DATA [63:0] $end\n$var reg 64 K\" REG_WRITE_DATA_WRITEBACK_5 [63:0] $end\n$var integer 32 L\" DECODE [31:0] $end\n$var integer 32 M\" EXECUTE [31:0] $end\n$var integer 32 N\" MEMORY [31:0] $end\n$var integer 32 O\" OP_B_TYPE [31:0] $end\n$var integer 32 P\" OP_I_TYPE_64 [31:0] $end\n$var integer 32 Q\" OP_I_TYPE_JUMP [31:0] $end\n$var integer 32 R\" OP_I_TYPE_LOAD [31:0] $end\n$var integer 32 S\" OP_I_TYPE_OTHER [31:0] $end\n$var integer 32 T\" OP_R_TYPE [31:0] $end\n$var integer 32 U\" OP_R_TYPE_64 [31:0] $end\n$var integer 32 V\" OP_S_TYPE [31:0] $end\n$var integer 32 W\" OP_U_TYPE_AUIPC [31:0] $end\n$var integer 32 X\" OP_U_TYPE_JUMP [31:0] $end\n$var integer 32 Y\" OP_U_TYPE_LOAD [31:0] $end\n$var integer 32 Z\" TYPE_BRANCH [31:0] $end\n$var integer 32 [\" TYPE_IMMEDIATE [31:0] $end\n$var integer 32 \\\" TYPE_LOAD [31:0] $end\n$var integer 32 ]\" TYPE_REGISTER [31:0] $end\n$var integer 32 ^\" TYPE_STORE [31:0] $end\n$var integer 32 _\" TYPE_UPPERIMMEDIATE [31:0] $end\n$var integer 32 `\" WRITEBACK [31:0] $end\n$scope begin PIPELINE[0] $end\n$var wire 5 a\" R1 [4:0] $end\n$var wire 5 b\" R2 [4:0] $end\n$var wire 5 c\" RD [4:0] $end\n$var wire 3 d\" TYPE [2:0] $end\n$upscope $end\n$scope begin PIPELINE[1] $end\n$var wire 5 e\" R1 [4:0] $end\n$var wire 5 f\" R2 [4:0] $end\n$var wire 5 g\" RD [4:0] $end\n$var wire 3 h\" TYPE [2:0] $end\n$upscope $end\n$scope begin PIPELINE[2] $end\n$var wire 5 i\" R1 [4:0] $end\n$var wire 5 j\" R2 [4:0] $end\n$var wire 5 k\" RD [4:0] $end\n$var wire 3 l\" TYPE [2:0] $end\n$upscope $end\n$scope begin PIPELINE[3] $end\n$var wire 5 m\" R1 [4:0] $end\n$var wire 5 n\" R2 [4:0] $end\n$var wire 5 o\" RD [4:0] $end\n$var wire 3 p\" TYPE [2:0] $end\n$upscope $end\n$scope module alu $end\n$var wire 64 q\" X [63:0] $end\n$var wire 64 r\" X_signed [63:0] $end\n$var wire 64 s\" Y [63:0] $end\n$var wire 64 t\" Y_signed [63:0] $end\n$var wire 1 l isEqual $end\n$var wire 4 u\" OP [3:0] $end\n$var reg 64 v\" result_reg [63:0] $end\n$upscope $end\n$scope module aluOpEncoder $end\n$var wire 16 w\" in [15:0] $end\n$var reg 4 x\" out [3:0] $end\n$upscope $end\n$scope module aluX1SelectionEncoder $end\n$var wire 4 y\" in [3:0] $end\n$var reg 2 z\" out [1:0] $end\n$upscope $end\n$scope module aluX2SelectionEncoder $end\n$var wire 4 {\" in [3:0] $end\n$var reg 2 |\" out [1:0] $end\n$upscope $end\n$scope module immediateExtractor $end\n$var wire 32 }\" INSTRUCTION [31:0] $end\n$var wire 3 ~\" SELECTION [2:0] $end\n$var wire 64 !# Imm_UJ [63:0] $end\n$var wire 64 \"# Imm_U [63:0] $end\n$var wire 64 ## Imm_S [63:0] $end\n$var wire 64 $# Imm_I [63:0] $end\n$var wire 64 %# Imm_B [63:0] $end\n$var wire 4 &# IMM_4_1 [3:0] $end\n$var wire 5 '# IMM_4_0 [4:0] $end\n$var wire 20 (# IMM_31_12 [19:0] $end\n$var wire 1 )# IMM_20 $end\n$var wire 8 *# IMM_19_12 [7:0] $end\n$var wire 1 +# IMM_12 $end\n$var wire 1 ,# IMM_11_J $end\n$var wire 1 -# IMM_11_B $end\n$var wire 7 .# IMM_11_5 [6:0] $end\n$var wire 12 /# IMM_11_0 [11:0] $end\n$var wire 6 0# IMM_10_5 [5:0] $end\n$var wire 10 1# IMM_10_1 [9:0] $end\n$var reg 64 2# VALUE [63:0] $end\n$upscope $end\n$scope module immediateSelectionEncoder $end\n$var wire 8 3# in [7:0] $end\n$var reg 3 4# out [2:0] $end\n$upscope $end\n$scope module regFile $end\n$var wire 5 5# R1 [4:0] $end\n$var wire 64 6# R1_DATA [63:0] $end\n$var wire 5 7# R2 [4:0] $end\n$var wire 64 8# R2_DATA [63:0] $end\n$var wire 5 9# RD [4:0] $end\n$var wire 64 :# RD_DATA [63:0] $end\n$var wire 1 J WRITE_ENABLE $end\n$var integer 32 ;# i [31:0] $end\n$scope begin REG_DATAS[1] $end\n$var wire 64 <# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[2] $end\n$var wire 64 =# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[3] $end\n$var wire 64 ># R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[4] $end\n$var wire 64 ?# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[5] $end\n$var wire 64 @# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[6] $end\n$var wire 64 A# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[7] $end\n$var wire 64 B# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[8] $end\n$var wire 64 C# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[9] $end\n$var wire 64 D# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[10] $end\n$var wire 64 E# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[11] $end\n$var wire 64 F# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[12] $end\n$var wire 64 G# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[13] $end\n$var wire 64 H# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[14] $end\n$var wire 64 I# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[15] $end\n$var wire 64 J# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[16] $end\n$var wire 64 K# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[17] $end\n$var wire 64 L# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[18] $end\n$var wire 64 M# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[19] $end\n$var wire 64 N# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[20] $end\n$var wire 64 O# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[21] $end\n$var wire 64 P# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[22] $end\n$var wire 64 Q# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[23] $end\n$var wire 64 R# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[24] $end\n$var wire 64 S# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[25] $end\n$var wire 64 T# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[26] $end\n$var wire 64 U# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[27] $end\n$var wire 64 V# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[28] $end\n$var wire 64 W# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[29] $end\n$var wire 64 X# R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[30] $end\n$var wire 64 Y# R_DATA [63:0] $end\n$upscope $end\n$upscope $end\n$scope module writeBackSelectionEncoder $end\n$var wire 4 Z# in [3:0] $end\n$var reg 2 [# out [1:0] $end\n$upscope $end\n$upscope $end\n$scope module ram $end\n$var wire 10 \\# ADDRESS [9:0] $end\n$var wire 1 ' CLK $end\n$var wire 64 ]# DATA_IN [63:0] $end\n$var wire 64 ^# DATA_OUT [63:0] $end\n$var wire 1 ! WRITE_ENABLE $end\n$scope begin $ivl_for_loop0 $end\n$var integer 32 _# i [31:0] $end\n$upscope $end\n$upscope $end\n$scope module rom $end\n$var wire 10 `# ADDRESS [9:0] $end\n$var wire 32 a# DATA [31:0] $end\n$upscope $end\n$scope begin $ivl_for_loop1 $end\n$var integer 32 b# i [31:0] $end\n$upscope $end\n$upscope $end\n$enddefinitions $end\n#0\n$dumpvars\nb0 b#\nb10011 a#\nb0 `#\nb10000000000 _#\nb0 ^#\nbx ]#\nb0 \\#\nb0 [#\nb0 Z#\nb0 Y#\nb0 X#\nb0 W#\nb0 V#\nb0 U#\nb0 T#\nb0 S#\nb0 R#\nb0 Q#\nb0 P#\nb0 O#\nb0 N#\nb0 M#\nb0 L#\nb0 K#\nb0 J#\nb0 I#\nb0 H#\nb0 G#\nb0 F#\nb0 E#\nb0 D#\nb0 C#\nb0 B#\nb0 A#\nb0 @#\nb0 ?#\nb0 >#\nb0 =#\nb0 <#\nb100000 ;#\nb0 :#\nb0 9#\nb0 8#\nb0 7#\nb0 6#\nb0 5#\nb0 4#\nb0 3#\nb0 2#\nb0 1#\nb0 0#\nb0 /#\nb0 .#\n0-#\n0,#\n0+#\nb0 *#\n0)#\nb0 (#\nb0 '#\nb0 &#\nb0 %#\nb0 $#\nb0 ##\nb0 \"#\nb0 !#\nb0 ~\"\nb0 }\"\nb0 |\"\nb1 {\"\nb0 z\"\nb1 y\"\nb0 x\"\nb0 w\"\nb0 v\"\nb0 u\"\nb0 t\"\nb0 s\"\nb0 r\"\nb0 q\"\nbx p\"\nbx o\"\nbx n\"\nbx m\"\nbx l\"\nbx k\"\nbx j\"\nbx i\"\nbx h\"\nbx g\"\nbx f\"\nbx e\"\nbx d\"\nbx c\"\nbx b\"\nbx a\"\nb11 `\"\nb100 _\"\nb10 ^\"\nb0 ]\"\nb1 \\\"\nb11 [\"\nb101 Z\"\nb110111 Y\"\nb1100111 X\"\nb10111 W\"\nb100011 V\"\nb111011 U\"\nb110011 T\"\nb10011 S\"\nb11 R\"\nb1101111 Q\"\nb11011 P\"\nb1100011 O\"\nb10 N\"\nb1 M\"\nb0 L\"\nb0 K\"\nbx J\"\nb0 I\"\nb0 H\"\nb0 G\"\nb0 F\"\nb0 E\"\nb0 D\"\nb0 C\"\nb0 B\"\nb0 A\"\nb0 @\"\nb0 ?\"\nb0 >\"\nb0 =\"\nb0 <\"\nb0 ;\"\nb0 :\"\n09\"\nb0 8\"\nb0 7\"\nb0 6\"\nb0 5\"\nb10011 4\"\nb0 3\"\n02\"\n01\"\n00\"\n0/\"\nb0 .\"\nb0 -\"\nb0 ,\"\nb0 +\"\nb0 *\"\nb0 )\"\nb0 (\"\nb0 '\"\nb0 &\"\nb0 %\"\nb0 $\"\nb0 #\"\nb0 \"\"\n0!\"\n0~\n0}\n0|\n0{\n0z\n0y\n0x\n0w\n0v\n0u\n0t\n0s\n0r\n0q\nb0 p\nb1 o\nb1 n\nb0 m\n1l\nb0 k\n0j\n0i\n0h\n0g\n0f\n0e\n0d\n0c\n0b\n0a\n0`\n0_\n0^\n0]\n0\\\n0[\n0Z\n0Y\n0X\n0W\n0V\n0U\n0T\n0S\n0R\n0Q\n0P\n0O\n0N\n0M\n0L\n0K\n0J\nb0 I\nb0 H\n0G\nxF\n0E\n0D\n0C\n0B\n0A\n0@\n0?\n0>\n0=\n0<\n0;\n0:\n09\n08\n07\n06\n05\n04\n03\nx2\nx1\nx0\nx/\n0.\n0-\n0,\n0+\n0*\n0)\n0(\n1'\nb10011 &\nb0 %\nb0 $\nb0 #\nbx \"\n0!\n$end\n#200\n0'\n#400\n0F\n01\n02\n0/\n00\nb100000000000010010011 &\nb100000000000010010011 4\"\nb100000000000010010011 a#\nb1 %\nb1 3\"\nb1 `#\nb11 d\"\nb0 c\"\nb0 b\"\nb0 a\"\nb100 E\"\nb0 g\"\nb0 f\"\nb0 e\"\nb10011 A\"\nb0 k\"\nb0 j\"\nb0 i\"\nb0 o\"\nb0 n\"\nb0 m\"\nb0 \"\nb0 J\"\nb0 ]#\n1'\nb1 b#\n#600\n0'\n#800\nb1 :\"\nb1 |\"\nb11 n\nb11 {\"\nb1 p\nb1 w\"\nb1 6\"\nb1 ~\"\nb1 4#\nb10 m\nb10 3#\n13\n14\n1/\"\nb10011 .\"\nb100000000001100010011 &\nb100000000001100010011 4\"\nb100000000001100010011 a#\nb10 %\nb10 3\"\nb10 `#\nb10011 B\"\nb10011 }\"\nb11 h\"\nb100 F\"\nb100000000000010010011 A\"\nb1 c\"\nb1 b\"\nb1000 E\"\n1'\nb10 b#\n#1000\n0'\n#1200\nb1 <\"\nb1 v\"\nb1 t\"\n0l\nb1 @\"\nb1 s\"\nb1 5\"\nb1 2#\nb1 $#\nb100000000000000000000 \"#\nb1 ##\nb100000000000 %#\nb100000000000 !#\nb10000000000011000010011 &\nb10000000000011000010011 4\"\nb10000000000011000010011 a#\nb11 %\nb11 3\"\nb11 `#\nb1 )\"\nb1 7#\nb1 /#\nb100000000 (#\nb1 '#\n1-#\n1,#\nb110 c\"\nb1100 E\"\nb1 g\"\nb1 f\"\nb1000 F\"\nb100000000001100010011 A\"\nb11 l\"\nb100000000000010010011 B\"\nb100000000000010010011 }\"\nb100 G\"\nb10011 C\"\n1'\nb11 b#\n#1400\n0'\n#1600\n1J\nb1 #\"\nb1 [#\nb10 k\nb10 Z#\n1i\nb110 ##\nb110 %#\n1v\nb10011 -\"\nb1 $\nb1 &\"\nb1 \\#\nb110 '#\n0-#\nb11 &#\nb11000001010000000100011 &\nb11000001010000000100011 4\"\nb11000001010000000100011 a#\nb100 %\nb100 3\"\nb100 `#\nb10011 D\"\nb11 p\"\nb1 >\"\nb100 H\"\nb100000000000010010011 C\"\nb1 k\"\nb1 j\"\nb100000000001100010011 B\"\nb100000000001100010011 }\"\nb1000 G\"\nb110 g\"\nb1100 F\"\nb10000000000011000010011 A\"\nb1100 c\"\nb100 b\"\nb10000 E\"\n1'\nb100 b#\n#1800\n0'\n#2000\nb100 <\"\nb100 v\"\nb100 t\"\nb100 @\"\nb100 s\"\nb1 <#\nb100 5\"\nb100 2#\nb100 $#\nb10000000000000000000000 \"#\nb1100 ##\nb1100 %#\nb100 !#\nb1010001100000011 &\nb1010001100000011 4\"\nb1010001100000011 a#\nb101 %\nb101 3\"\nb101 `#\nb100 )\"\nb100 7#\nb100 /#\nb10000000000 (#\nb1100 '#\nb110 &#\n0,#\nb10 1#\nb1 \"\"\nb1 :#\nb1 $\"\nb1 9#\nb10 d\"\nb0 c\"\nb110 b\"\nb1 a\"\nb10100 E\"\nb1100 g\"\nb100 f\"\nb10000 F\"\nb11000001010000000100011 A\"\nb110 k\"\nb10000000000011000010011 B\"\nb10000000000011000010011 }\"\nb1100 G\"\nb1 o\"\nb1 n\"\nb1000 H\"\nb100000000001100010011 C\"\nb1 K\"\nb100000000000010010011 D\"\n1'\nb101 b#\n#2200\n0'\n#2400\nb1 <\"\nb1 v\"\nb0 t\"\nb0 @\"\nb0 s\"\nb1 r\"\nb1 ?\"\nb1 q\"\nb1 '\"\nb1 8#\nb1 A#\nb0 p\nb0 w\"\nb1 I\nb1 (\"\n03\nb1 H\nb1 +\"\nb0 5\"\nb0 2#\nb11 6\"\nb11 ~\"\nb11 4#\n04\nb110 $#\nb11000001010000000000000 \"#\nb0 ##\nb0 %#\nb1010000000000110 !#\nb110 $\"\nb110 9#\n12\nb100 $\nb100 &\"\nb100 \\#\n0/\"\nb1000 m\nb1000 3#\n1}\nb100011 .\"\nb10 8\"\nb1 *\"\nb1 6#\nb1 ,\"\nb1 5#\nb110 )\"\nb110 7#\nb110 /#\nb11000001010 (#\nb0 '#\nb0 &#\nb1010 *#\nb11 1#\nb100110000001100010011 &\nb100110000001100010011 4\"\nb100110000001100010011 a#\nb110 %\nb110 3\"\nb110 `#\nb100000000001100010011 D\"\nb110 o\"\nb100 >\"\nb1100 H\"\nb10000000000011000010011 C\"\nb1100 k\"\nb100 j\"\nb11000001010000000100011 B\"\nb11000001010000000100011 }\"\nb10000 G\"\nb0 g\"\nb110 f\"\nb1 e\"\nb10 h\"\nb10100 F\"\nb1010001100000011 A\"\nb1 d\"\nb110 c\"\nb0 b\"\nb11000 E\"\n1'\nb110 b#\n#2600\n0'\n#2800\nb100 G#\nb1 :\"\nb1 |\"\n1F\nb0 I\nb0 (\"\n13\nb11 n\nb11 {\"\nb1 6\"\nb1 ~\"\nb1 4#\nb0 $#\nb1010000000000000 \"#\nb110 ##\nb110 %#\nb1010000000000000 !#\n1d\nb11000001010000000100011 &\nb11000001010000000100011 4\"\nb11000001010000000100011 a#\nb111 %\nb111 3\"\nb111 `#\n01\n10\"\nb10 m\nb10 3#\n0}\nb11 .\"\nb0 '\"\nb0 8#\nb0 )\"\nb0 7#\nb0 /#\nb1010 (#\nb110 '#\nb11 &#\nb0 1#\n02\nb1 $\nb1 &\"\nb1 \\#\n1!\nb100 \"\"\nb100 :#\nb1100 $\"\nb1100 9#\nb11 d\"\nb1 b\"\nb110 a\"\nb11100 E\"\nb110 g\"\nb0 f\"\nb1 h\"\nb11000 F\"\nb100110000001100010011 A\"\nb0 k\"\nb110 j\"\nb1 i\"\nb10 l\"\nb1010001100000011 B\"\nb1010001100000011 }\"\nb10100 G\"\nb1100 o\"\nb100 n\"\nb1 \"\nb1 J\"\nb1 ]#\nb1 >\"\nb10000 H\"\nb11000001010000000100011 C\"\nb100 K\"\nb10000000000011000010011 D\"\n1'\nb111 b#\n#3000\n0'\n#3200\nb0 <\"\nb0 v\"\nb0 r\"\n1l\nb0 ?\"\nb0 q\"\n0J\nb0 #\"\nb0 [#\nb1 p\nb1 w\"\nb0 k\nb0 Z#\n0i\nb0 H\nb0 +\"\n1;\n0d\n14\nb0 \"#\nb0 ##\nb0 %#\nb0 !#\nb1 \"\"\nb1 :#\nb0 $\"\nb0 9#\n0v\nb100011 -\"\n0!\n00\"\n1/\"\nb10011 .\"\nb0 8\"\nb0 *\"\nb0 6#\nb0 ,\"\nb0 5#\nb0 (#\nb0 '#\nb0 &#\nb0 *#\n0F\nb1 #\nb1 %\"\nb1 ^#\nb1 K\"\nb11000001010000000100011 D\"\nb0 o\"\nb110 n\"\nb1 m\"\nb10 p\"\nb0 \"\nb0 J\"\nb0 ]#\nb10100 H\"\nb1010001100000011 C\"\nb110 k\"\nb0 j\"\nb1 l\"\nb10011 B\"\nb10011 }\"\nb0 g\"\nb0 f\"\nb0 e\"\nb11 h\"\nb10 d\"\nb0 c\"\nb110 b\"\nb1 a\"\n1'\nb1000 b#\n#3400\n0'\n#3600\nb10 <\"\nb10 v\"\nb1 t\"\nb1 @\"\nb1 s\"\nb1 r\"\n1l\nb1 ?\"\nb1 q\"\n1J\n1i\nb1 H\nb1 +\"\nb1 I\nb1 (\"\nb1 5\"\nb1 2#\n10\nb1 $#\nb100110000000000000000 \"#\nb110 ##\nb110 %#\nb110000100000000000 !#\n0;\nb11 #\"\nb11 [#\nb11111110110000110100101011100011 &\nb11111110110000110100101011100011 4\"\nb11111110110000110100101011100011 a#\nb1000 %\nb1000 3\"\nb1000 `#\nb1 *\"\nb1 6#\nb110 ,\"\nb110 5#\nb1 '\"\nb1 8#\nb1 )\"\nb1 7#\nb1 /#\nb100110000 (#\nb110 '#\nb11 &#\nb110000 *#\n1,#\nb0 #\nb0 %\"\nb0 ^#\nb0 $\nb0 &\"\nb0 \\#\nb110 $\"\nb110 9#\nb1000 k\nb1000 Z#\n1w\nb11 -\"\nb100000 E\"\nb110 g\"\nb1 f\"\nb110 e\"\nb11100 F\"\nb11000001010000000100011 A\"\nb0 k\"\nb0 i\"\nb11 l\"\nb100110000001100010011 B\"\nb100110000001100010011 }\"\nb11000 G\"\nb110 o\"\nb0 n\"\nb1 p\"\nb0 >\"\nb10011 C\"\nb1 I\"\nb1010001100000011 D\"\n1'\nb1001 b#\n#3800\n0'\n#4000\nb1 <\"\nb1 v\"\nb0 t\"\n0l\nb0 @\"\nb0 s\"\nb0 p\nb0 w\"\n03\nb0 5\"\nb0 2#\nb1 #\"\nb1 [#\nb10 I\nb10 (\"\nb11 6\"\nb11 ~\"\nb11 4#\n04\nb110 $#\nb11000001010000000000000 \"#\nb0 ##\nb0 %#\nb1010000000000110 !#\n1.\nb1 \"\"\nb1 :#\nb0 $\"\nb0 9#\nb10 k\nb10 Z#\n0w\n1v\nb10011 -\"\nb10 $\nb10 &\"\nb10 \\#\n11\n0/\"\nb1000 m\nb1000 3#\n1}\nb100011 .\"\nb10 8\"\nb1 ,\"\nb1 5#\nb110 )\"\nb110 7#\nb110 /#\nb11000001010 (#\nb0 '#\nb0 &#\nb1010 *#\n0,#\nb11 1#\n00\nb11011100000000010000010011 &\nb11011100000000010000010011 4\"\nb11011100000000010000010011 a#\nb1001 %\nb1001 3\"\nb1001 `#\nb0 I\"\nb10011 D\"\nb0 o\"\nb0 m\"\nb11 p\"\nb1 \"\nb1 J\"\nb1 ]#\nb10 >\"\nb11000 H\"\nb100110000001100010011 C\"\nb110 k\"\nb1 j\"\nb110 i\"\nb11000001010000000100011 B\"\nb11000001010000000100011 }\"\nb11100 G\"\nb0 g\"\nb110 f\"\nb1 e\"\nb10 h\"\nb100000 F\"\nb11111110110000110100101011100011 A\"\nb101 d\"\nb10101 c\"\nb1100 b\"\nb110 a\"\nb100100 E\"\n1'\nb1010 b#\n#4200\n0'\n#4400\nb10100 <\"\nb10100 v\"\nb100000 r\"\nb100000 ?\"\nb100000 q\"\nb1111111111111111111111111111111111111111111111111111111111110100 t\"\nb1111111111111111111111111111111111111111111111111111111111110100 @\"\nb1111111111111111111111111111111111111111111111111111111111110100 s\"\nb10 *\"\nb10 6#\nb10 A#\n1G\nb1 ;\"\nb1 z\"\nb11 o\nb11 y\"\nb10 H\nb10 +\"\nb1111111111111111111111111111111111111111111111111111111111110100 5\"\nb1111111111111111111111111111111111111111111111111111111111110100 2#\nb100 6\"\nb100 ~\"\nb100 4#\n1+\nb1111111111111111111111111111111111111111111111111111111111101100 $#\nb1111111111111111111111111111111111111110110000110100000000000000 \"#\nb1111111111111111111111111111111111111111111111111111111111110101 ##\nb1111111111111111111111111111111111111111111111111111111111110100 %#\nb1111111111111111111111111111111111111111111100110100011111101100 !#\n1d\n10\n01\n0}\nb10000 m\nb10000 3#\n19\"\nb1100011 .\"\nb100 8\"\nb110 ,\"\nb110 5#\nb100 '\"\nb100 8#\nb1100 )\"\nb1100 7#\nb1111111 7\"\nb111111101100 /#\nb11111110110000110100 (#\nb10101 '#\nb1111111 .#\n1-#\nb1010 &#\nb111111 0#\n1+#\nb110100 *#\nb1111110110 1#\n1)#\nb100 I\nb100 (\"\nb1 #\nb1 %\"\nb1 ^#\nb1 $\nb1 &\"\nb1 \\#\n1!\nb10 \"\"\nb10 :#\nb110 $\"\nb110 9#\nb11 d\"\nb0 c\"\nb0 b\"\nb0 a\"\nb10101 g\"\nb1100 f\"\nb110 e\"\nb101 h\"\nb10011 A\"\nb0 k\"\nb110 j\"\nb1 i\"\nb10 l\"\nb11111110110000110100101011100011 B\"\nb11111110110000110100101011100011 }\"\nb100000 G\"\nb110 o\"\nb1 n\"\nb110 m\"\nb10 \"\nb10 J\"\nb10 ]#\nb1 >\"\nb11100 H\"\nb11000001010000000100011 C\"\nb10 K\"\nb100110000001100010011 D\"\n1'\nb1011 b#\n#4600\n0'\n#4800\nb0 <\"\nb0 v\"\nb0 r\"\n1l\nb0 ?\"\nb0 q\"\nb0 t\"\nb0 @\"\nb0 s\"\n0G\n0J\nb0 ;\"\nb0 z\"\nb0 #\"\nb0 [#\nb1 :\"\nb1 |\"\nb1 o\nb1 y\"\nb1 p\nb1 w\"\nb0 H\nb0 +\"\nb0 k\nb0 Z#\n0i\n13\nb11 n\nb11 {\"\nb0 I\nb0 (\"\nb0 5\"\nb0 2#\n0d\nb1 6\"\nb1 ~\"\nb1 4#\n14\n0+\n0.\nb0 $#\nb0 \"#\nb0 ##\nb0 %#\nb0 !#\n00\nb1 \"\"\nb1 :#\nb0 $\"\nb0 9#\n0v\nb100011 -\"\nb10100 $\nb10100 &\"\nb10100 \\#\n0!\n1/\"\nb10 m\nb10 3#\n09\"\nb10011 .\"\nb0 8\"\nb0 *\"\nb0 6#\nb0 ,\"\nb0 5#\nb0 '\"\nb0 8#\nb0 )\"\nb0 7#\nb0 7\"\nb0 /#\nb0 (#\nb0 '#\nb0 .#\n0-#\nb0 &#\nb0 0#\n0+#\nb0 *#\nb0 1#\n0)#\nb1010001100000011 &\nb1010001100000011 4\"\nb1010001100000011 a#\nb101 %\nb101 3\"\nb101 `#\nb0 #\nb0 %\"\nb0 ^#\nb1 K\"\nb1 I\"\nb11000001010000000100011 D\"\nb0 o\"\nb110 n\"\nb1 m\"\nb10 p\"\nb100 \"\nb100 J\"\nb100 ]#\nb10100 >\"\nb100000 H\"\nb11111110110000110100101011100011 C\"\nb10101 k\"\nb1100 j\"\nb110 i\"\nb101 l\"\nb10011 B\"\nb10011 }\"\nb0 g\"\nb0 f\"\nb0 e\"\nb11 h\"\nb10100 E\"\n1'\nb1100 b#\n#5000\n0'\n#5200\nb100110000001100010011 &\nb100110000001100010011 4\"\nb100110000001100010011 a#\nb110 %\nb110 3\"\nb110 `#\nb0 $\nb0 &\"\nb0 \\#\nb10101 $\"\nb10101 9#\nb1100011 -\"\nb1 d\"\nb110 c\"\nb1 a\"\nb11000 E\"\nb10100 F\"\nb1010001100000011 A\"\nb0 k\"\nb0 j\"\nb0 i\"\nb11 l\"\nb10101 o\"\nb1100 n\"\nb110 m\"\nb101 p\"\nb0 \"\nb0 J\"\nb0 ]#\nb0 >\"\nb10011 C\"\nb0 I\"\nb11111110110000110100101011100011 D\"\n1'\nb1101 b#\n#5400\n0'\n#5600\nb1 <\"\nb1 v\"\nb1 r\"\n0l\nb1 ?\"\nb1 q\"\nb1 :\"\nb1 |\"\nb11 n\nb11 {\"\n1J\nb1 #\"\nb1 [#\nb1 6\"\nb1 ~\"\nb1 4#\nb0 p\nb0 w\"\nb10 k\nb10 Z#\n1i\nb10 m\nb10 3#\n13\nb1 H\nb1 +\"\n1F\n04\nb1010000000000000 \"#\nb110 ##\nb110 %#\nb1010000000000000 !#\nb0 $\"\nb0 9#\n1v\nb10011 -\"\n10\"\n0/\"\nb11 .\"\nb10 8\"\nb1 *\"\nb1 6#\nb1 ,\"\nb1 5#\nb1010 (#\nb110 '#\nb11 &#\nb1010 *#\nb11000001010000000100011 &\nb11000001010000000100011 4\"\nb11000001010000000100011 a#\nb111 %\nb111 3\"\nb111 `#\nb10011 D\"\nb0 o\"\nb0 n\"\nb0 m\"\nb11 p\"\nb1010001100000011 B\"\nb1010001100000011 }\"\nb10100 G\"\nb110 g\"\nb1 e\"\nb1 h\"\nb11000 F\"\nb100110000001100010011 A\"\nb11 d\"\nb1 b\"\nb110 a\"\nb11100 E\"\n1'\nb1110 b#\n#5800\n0'\n#6000\nb0 <\"\nb0 v\"\nb0 r\"\n1l\nb0 ?\"\nb0 q\"\nb1 p\nb1 w\"\nb0 H\nb0 +\"\n14\nb0 \"#\nb0 ##\nb0 %#\nb0 !#\n1;\n00\n0F\n00\"\n1/\"\nb10011 .\"\nb0 8\"\nb0 *\"\nb0 6#\nb0 ,\"\nb0 5#\nb0 (#\nb0 '#\nb0 &#\nb0 *#\nb10 #\nb10 %\"\nb10 ^#\nb1 $\nb1 &\"\nb1 \\#\nb0 \"\"\nb0 :#\nb10 d\"\nb0 c\"\nb110 b\"\nb1 a\"\nb0 g\"\nb0 f\"\nb0 e\"\nb11 h\"\nb110 k\"\nb1 i\"\nb1 l\"\nb10011 B\"\nb10011 }\"\nb1 >\"\nb10100 H\"\nb1010001100000011 C\"\nb0 K\"\n1'\nb1111 b#\n#6200\n0'\n#6400\nb11 <\"\nb11 v\"\nb1 t\"\nb1 @\"\nb1 s\"\nb10 r\"\n0l\nb10 ?\"\nb10 q\"\nb10 A#\n1J\n1i\nb10 H\nb10 +\"\nb1 I\nb1 (\"\nb1 5\"\nb1 2#\nb11 #\"\nb11 [#\n0;\nb1 $#\nb100110000000000000000 \"#\nb110 ##\nb110 %#\nb110000100000000000 !#\n10\nb10 \"\"\nb10 :#\nb110 $\"\nb110 9#\nb1000 k\nb1000 Z#\n1w\n0v\nb11 -\"\nb0 #\nb0 %\"\nb0 ^#\nb0 $\nb0 &\"\nb0 \\#\nb10 *\"\nb10 6#\nb110 ,\"\nb110 5#\nb1 '\"\nb1 8#\nb1 )\"\nb1 7#\nb1 /#\nb100110000 (#\nb110 '#\nb11 &#\nb110000 *#\n1,#\nb11111110110000110100101011100011 &\nb11111110110000110100101011100011 4\"\nb11111110110000110100101011100011 a#\nb1000 %\nb1000 3\"\nb1000 `#\nb1 K\"\nb10 I\"\nb1010001100000011 D\"\nb110 o\"\nb1 m\"\nb1 p\"\nb0 >\"\nb10011 C\"\nb0 k\"\nb0 i\"\nb11 l\"\nb100110000001100010011 B\"\nb100110000001100010011 }\"\nb11000 G\"\nb110 g\"\nb1 f\"\nb110 e\"\nb11100 F\"\nb11000001010000000100011 A\"\nb100000 E\"\n1'\nb10000 b#\n#6600\n0'\n#6800\nb1 <\"\nb1 v\"\nb0 t\"\nb0 @\"\nb0 s\"\nb1 r\"\n0l\nb1 ?\"\nb1 q\"\nb0 p\nb0 w\"\n03\nb0 5\"\nb0 2#\nb1 H\nb1 +\"\nb11 I\nb11 (\"\n1.\nb11 6\"\nb11 ~\"\nb11 4#\n04\nb110 $#\nb11000001010000000000000 \"#\nb0 ##\nb0 %#\nb1010000000000110 !#\nb1 #\"\nb1 [#\nb11011100000000010000010011 &\nb11011100000000010000010011 4\"\nb11011100000000010000010011 a#\nb1001 %\nb1001 3\"\nb1001 `#\n11\n0/\"\nb1000 m\nb1000 3#\n1}\nb100011 .\"\nb10 8\"\nb1 *\"\nb1 6#\nb1 ,\"\nb1 5#\nb10 '\"\nb10 8#\nb110 )\"\nb110 7#\nb110 /#\nb11000001010 (#\nb0 '#\nb0 &#\nb1010 *#\n0,#\nb11 1#\n00\nb11 $\nb11 &\"\nb11 \\#\nb1 \"\"\nb1 :#\nb0 $\"\nb0 9#\nb10 k\nb10 Z#\n0w\n1v\nb10011 -\"\nb101 d\"\nb10101 c\"\nb1100 b\"\nb110 a\"\nb100100 E\"\nb0 g\"\nb110 f\"\nb1 e\"\nb10 h\"\nb100000 F\"\nb11111110110000110100101011100011 A\"\nb110 k\"\nb1 j\"\nb110 i\"\nb11000001010000000100011 B\"\nb11000001010000000100011 }\"\nb11100 G\"\nb0 o\"\nb0 m\"\nb11 p\"\nb1 \"\nb1 J\"\nb1 ]#\nb11 >\"\nb11000 H\"\nb100110000001100010011 C\"\nb0 I\"\nb10011 D\"\n1'\nb10001 b#\n#7000\n0'\n#7200\nb10100 <\"\nb10100 v\"\nb1111111111111111111111111111111111111111111111111111111111110100 t\"\nb1111111111111111111111111111111111111111111111111111111111110100 @\"\nb1111111111111111111111111111111111111111111111111111111111110100 s\"\nb100000 r\"\nb100000 ?\"\nb100000 q\"\nb11 A#\n1G\nb1 ;\"\nb1 z\"\nb11 o\nb11 y\"\nb11 H\nb11 +\"\nb1111111111111111111111111111111111111111111111111111111111110100 5\"\nb1111111111111111111111111111111111111111111111111111111111110100 2#\n1d\nb100 6\"\nb100 ~\"\nb100 4#\n1+\nb1111111111111111111111111111111111111111111111111111111111101100 $#\nb1111111111111111111111111111111111111110110000110100000000000000 \"#\nb1111111111111111111111111111111111111111111111111111111111110101 ##\nb1111111111111111111111111111111111111111111111111111111111110100 %#\nb1111111111111111111111111111111111111111111100110100011111101100 !#\nb11 \"\"\nb11 :#\nb110 $\"\nb110 9#\n10\nb100 I\nb100 (\"\nb10 #\nb10 %\"\nb10 ^#\nb1 $\nb1 &\"\nb1 \\#\n1!\n0}\nb10000 m\nb10000 3#\n19\"\nb1100011 .\"\nb100 8\"\nb11 *\"\nb11 6#\nb110 ,\"\nb110 5#\nb100 '\"\nb100 8#\nb1100 )\"\nb1100 7#\nb1111111 7\"\nb111111101100 /#\nb11111110110000110100 (#\nb10101 '#\nb1111111 .#\n1-#\nb1010 &#\nb111111 0#\n1+#\nb110100 *#\nb1111110110 1#\n1)#\n01\nb11 K\"\nb100110000001100010011 D\"\nb110 o\"\nb1 n\"\nb110 m\"\nb11 \"\nb11 J\"\nb11 ]#\nb1 >\"\nb11100 H\"\nb11000001010000000100011 C\"\nb0 k\"\nb110 j\"\nb1 i\"\nb10 l\"\nb11111110110000110100101011100011 B\"\nb11111110110000110100101011100011 }\"\nb100000 G\"\nb10101 g\"\nb1100 f\"\nb110 e\"\nb101 h\"\nb10011 A\"\nb11 d\"\nb0 c\"\nb0 b\"\nb0 a\"\n1'\nb10010 b#\n#7400\n0'\n#7600\nb0 <\"\nb0 v\"\nb0 r\"\n1l\nb0 ?\"\nb0 q\"\nb0 t\"\nb0 @\"\nb0 s\"\n0G\nb0 ;\"\nb0 z\"\n0J\nb1 :\"\nb1 |\"\nb1 o\nb1 y\"\nb1 p\nb1 w\"\nb0 #\"\nb0 [#\n13\nb11 n\nb11 {\"\nb0 I\nb0 (\"\nb0 5\"\nb0 2#\nb0 H\nb0 +\"\nb0 k\nb0 Z#\n0i\n00\nb1 6\"\nb1 ~\"\nb1 4#\n14\n0+\n0.\nb0 $#\nb0 \"#\nb0 ##\nb0 %#\nb0 !#\n0d\nb1010001100000011 &\nb1010001100000011 4\"\nb1010001100000011 a#\nb101 %\nb101 3\"\nb101 `#\n1/\"\nb10 m\nb10 3#\n09\"\nb10011 .\"\nb0 8\"\nb0 *\"\nb0 6#\nb0 ,\"\nb0 5#\nb0 '\"\nb0 8#\nb0 )\"\nb0 7#\nb0 7\"\nb0 /#\nb0 (#\nb0 '#\nb0 .#\n0-#\nb0 &#\nb0 0#\n0+#\nb0 *#\nb0 1#\n0)#\nb10100 $\nb10100 &\"\nb10100 \\#\n0!\nb1 \"\"\nb1 :#\nb0 $\"\nb0 9#\n0v\nb100011 -\"\nb10100 E\"\nb0 g\"\nb0 f\"\nb0 e\"\nb11 h\"\nb10101 k\"\nb1100 j\"\nb110 i\"\nb101 l\"\nb10011 B\"\nb10011 }\"\nb0 o\"\nb110 n\"\nb1 m\"\nb10 p\"\nb100 \"\nb100 J\"\nb100 ]#\nb10100 >\"\nb100000 H\"\nb11111110110000110100101011100011 C\"\nb1 K\"\nb10 I\"\nb11000001010000000100011 D\"\nb0 #\nb0 %\"\nb0 ^#\n1'\nb10011 b#\n#7800\n0'\n#8000\nb10101 $\"\nb10101 9#\nb1100011 -\"\nb0 $\nb0 &\"\nb0 \\#\nb100110000001100010011 &\nb100110000001100010011 4\"\nb100110000001100010011 a#\nb110 %\nb110 3\"\nb110 `#\nb0 I\"\nb11111110110000110100101011100011 D\"\nb10101 o\"\nb1100 n\"\nb110 m\"\nb101 p\"\nb0 \"\nb0 J\"\nb0 ]#\nb0 >\"\nb10011 C\"\nb0 k\"\nb0 j\"\nb0 i\"\nb11 l\"\nb10100 F\"\nb1010001100000011 A\"\nb1 d\"\nb110 c\"\nb1 a\"\nb11000 E\"\n1'\nb10100 b#\n#8200\n0'\n#8400\nb1 <\"\nb1 v\"\nb1 r\"\n0l\nb1 ?\"\nb1 q\"\nb1 :\"\nb1 |\"\nb11 n\nb11 {\"\n1J\n1F\nb1 6\"\nb1 ~\"\nb1 4#\nb0 p\nb0 w\"\nb1 #\"\nb1 [#\nb10 m\nb10 3#\n13\nb1 H\nb1 +\"\nb10 k\nb10 Z#\n1i\n04\nb1010000000000000 \"#\nb110 ##\nb110 %#\nb1010000000000000 !#\nb11000001010000000100011 &\nb11000001010000000100011 4\"\nb11000001010000000100011 a#\nb111 %\nb111 3\"\nb111 `#\n10\"\n0/\"\nb11 .\"\nb10 8\"\nb1 *\"\nb1 6#\nb1 ,\"\nb1 5#\nb1010 (#\nb110 '#\nb11 &#\nb1010 *#\nb0 $\"\nb0 9#\n1v\nb10011 -\"\nb11 d\"\nb1 b\"\nb110 a\"\nb11100 E\"\nb110 g\"\nb1 e\"\nb1 h\"\nb11000 F\"\nb100110000001100010011 A\"\nb1010001100000011 B\"\nb1010001100000011 }\"\nb10100 G\"\nb0 o\"\nb0 n\"\nb0 m\"\nb11 p\"\nb10011 D\"\n1'\nb10101 b#\n#8600\n0'\n#8800\nb0 <\"\nb0 v\"\nb0 r\"\n1l\nb0 ?\"\nb0 q\"\nb1 p\nb1 w\"\nb0 H\nb0 +\"\n1;\n14\nb0 \"#\nb0 ##\nb0 %#\nb0 !#\nb0 \"\"\nb0 :#\nb11 #\nb11 %\"\nb11 ^#\nb1 $\nb1 &\"\nb1 \\#\n00\"\n1/\"\nb10011 .\"\nb0 8\"\nb0 *\"\nb0 6#\nb0 ,\"\nb0 5#\nb0 (#\nb0 '#\nb0 &#\nb0 *#\n00\n0F\nb0 K\"\nb1 >\"\nb10100 H\"\nb1010001100000011 C\"\nb110 k\"\nb1 i\"\nb1 l\"\nb10011 B\"\nb10011 }\"\nb0 g\"\nb0 f\"\nb0 e\"\nb11 h\"\nb10 d\"\nb0 c\"\nb110 b\"\nb1 a\"\n1'\nb10110 b#\n#9000\n0'\n#9200\nb100 <\"\nb100 v\"\nb1 t\"\nb1 @\"\nb1 s\"\nb11 r\"\n0l\nb11 ?\"\nb11 q\"\nb11 A#\n1J\nb11 H\nb11 +\"\nb1 I\nb1 (\"\nb1 5\"\nb1 2#\n1i\n10\nb1 $#\nb100110000000000000000 \"#\nb110 ##\nb110 %#\nb110000100000000000 !#\n0;\nb11 #\"\nb11 [#\nb11111110110000110100101011100011 &\nb11111110110000110100101011100011 4\"\nb11111110110000110100101011100011 a#\nb1000 %\nb1000 3\"\nb1000 `#\nb11 *\"\nb11 6#\nb110 ,\"\nb110 5#\nb1 '\"\nb1 8#\nb1 )\"\nb1 7#\nb1 /#\nb100110000 (#\nb110 '#\nb11 &#\nb110000 *#\n1,#\nb0 #\nb0 %\"\nb0 ^#\nb0 $\nb0 &\"\nb0 \\#\nb11 \"\"\nb11 :#\nb110 $\"\nb110 9#\nb1000 k\nb1000 Z#\n1w\n0v\nb11 -\"\nb100000 E\"\nb110 g\"\nb1 f\"\nb110 e\"\nb11100 F\"\nb11000001010000000100011 A\"\nb0 k\"\nb0 i\"\nb11 l\"\nb100110000001100010011 B\"\nb100110000001100010011 }\"\nb11000 G\"\nb110 o\"\nb1 m\"\nb1 p\"\nb0 >\"\nb10011 C\"\nb1 K\"\nb11 I\"\nb1010001100000011 D\"\n1'\nb10111 b#\n#9400\n0'\n#9600\nb1 <\"\nb1 v\"\nb0 t\"\nb0 @\"\nb0 s\"\nb1 r\"\n0l\nb1 ?\"\nb1 q\"\nb0 p\nb0 w\"\n03\nb0 5\"\nb0 2#\nb1 H\nb1 +\"\nb1 #\"\nb1 [#\nb100 I\nb100 (\"\nb11 6\"\nb11 ~\"\nb11 4#\n04\nb110 $#\nb11000001010000000000000 \"#\nb0 ##\nb0 %#\nb1010000000000110 !#\n1.\nb1 \"\"\nb1 :#\nb0 $\"\nb0 9#\nb10 k\nb10 Z#\n0w\n1v\nb10011 -\"\nb100 $\nb100 &\"\nb100 \\#\n11\n0/\"\nb1000 m\nb1000 3#\n1}\nb100011 .\"\nb10 8\"\nb1 *\"\nb1 6#\nb1 ,\"\nb1 5#\nb11 '\"\nb11 8#\nb110 )\"\nb110 7#\nb110 /#\nb11000001010 (#\nb0 '#\nb0 &#\nb1010 *#\n0,#\nb11 1#\n00\nb11011100000000010000010011 &\nb11011100000000010000010011 4\"\nb11011100000000010000010011 a#\nb1001 %\nb1001 3\"\nb1001 `#\nb0 I\"\nb10011 D\"\nb0 o\"\nb0 m\"\nb11 p\"\nb1 \"\nb1 J\"\nb1 ]#\nb100 >\"\nb11000 H\"\nb100110000001100010011 C\"\nb110 k\"\nb1 j\"\nb110 i\"\nb11000001010000000100011 B\"\nb11000001010000000100011 }\"\nb11100 G\"\nb0 g\"\nb110 f\"\nb1 e\"\nb10 h\"\nb100000 F\"\nb11111110110000110100101011100011 A\"\nb101 d\"\nb10101 c\"\nb1100 b\"\nb110 a\"\nb100100 E\"\n1'\nb11000 b#\n#9800\n0'\n#10000\nb10100 <\"\nb10100 v\"\nb1111111111111111111111111111111111111111111111111111111111110100 t\"\nb1111111111111111111111111111111111111111111111111111111111110100 @\"\nb1111111111111111111111111111111111111111111111111111111111110100 s\"\nb100000 r\"\nb100000 ?\"\nb100000 q\"\nb100 A#\nb1 ;\"\nb1 z\"\nb11 o\nb11 y\"\nb100 H\nb100 +\"\nb1111111111111111111111111111111111111111111111111111111111110100 5\"\nb1111111111111111111111111111111111111111111111111111111111110100 2#\nb100 6\"\nb100 ~\"\nb100 4#\n1+\nb1111111111111111111111111111111111111111111111111111111111101100 $#\nb1111111111111111111111111111111111111110110000110100000000000000 \"#\nb1111111111111111111111111111111111111111111111111111111111110101 ##\nb1111111111111111111111111111111111111111111111111111111111110100 %#\nb1111111111111111111111111111111111111111111100110100011111101100 !#\n1d\n10\n01\n0}\nb10000 m\nb10000 3#\n19\"\nb1100011 .\"\nb100 8\"\nb100 *\"\nb100 6#\nb110 ,\"\nb110 5#\nb100 '\"\nb100 8#\nb1100 )\"\nb1100 7#\nb1111111 7\"\nb111111101100 /#\nb11111110110000110100 (#\nb10101 '#\nb1111111 .#\n1-#\nb1010 &#\nb111111 0#\n1+#\nb110100 *#\nb1111110110 1#\n1)#\nb100 I\nb100 (\"\nb11 #\nb11 %\"\nb11 ^#\nb1 $\nb1 &\"\nb1 \\#\n1!\nb100 \"\"\nb100 :#\nb110 $\"\nb110 9#\nb11 d\"\nb0 c\"\nb0 b\"\nb0 a\"\nb10101 g\"\nb1100 f\"\nb110 e\"\nb101 h\"\nb10011 A\"\nb0 k\"\nb110 j\"\nb1 i\"\nb10 l\"\nb11111110110000110100101011100011 B\"\nb11111110110000110100101011100011 }\"\nb100000 G\"\nb110 o\"\nb1 n\"\nb110 m\"\nb100 \"\nb100 J\"\nb100 ]#\nb1 >\"\nb11100 H\"\nb11000001010000000100011 C\"\nb100 K\"\nb100110000001100010011 D\"\n1'\nb11001 b#\n#10200\n0'\n#10400\nb0 <\"\nb0 v\"\nb0 r\"\n1l\nb0 ?\"\nb0 q\"\nb0 t\"\nb0 @\"\nb0 s\"\n0J\nb0 ;\"\nb0 z\"\nb0 #\"\nb0 [#\nb1 :\"\nb1 |\"\nb1 o\nb1 y\"\nb1 p\nb1 w\"\nb0 H\nb0 +\"\nb0 k\nb0 Z#\n0i\n13\nb11 n\nb11 {\"\nb0 I\nb0 (\"\nb0 5\"\nb0 2#\n0d\nb1 6\"\nb1 ~\"\nb1 4#\n14\n0+\n0.\nb0 $#\nb0 \"#\nb0 ##\nb0 %#\nb0 !#\n00\nb1 \"\"\nb1 :#\nb0 $\"\nb0 9#\n0v\nb100011 -\"\nb10100 $\nb10100 &\"\nb10100 \\#\n0!\n1/\"\nb10 m\nb10 3#\n09\"\nb10011 .\"\nb0 8\"\nb0 *\"\nb0 6#\nb0 ,\"\nb0 5#\nb0 '\"\nb0 8#\nb0 )\"\nb0 7#\nb0 7\"\nb0 /#\nb0 (#\nb0 '#\nb0 .#\n0-#\nb0 &#\nb0 0#\n0+#\nb0 *#\nb0 1#\n0)#\nb0 #\nb0 %\"\nb0 ^#\nb1 K\"\nb11 I\"\nb11000001010000000100011 D\"\nb0 o\"\nb110 n\"\nb1 m\"\nb10 p\"\nb10100 >\"\nb100000 H\"\nb11111110110000110100101011100011 C\"\nb10101 k\"\nb1100 j\"\nb110 i\"\nb101 l\"\nb10011 B\"\nb10011 }\"\nb0 g\"\nb0 f\"\nb0 e\"\nb11 h\"\n1'\nb11010 b#\n#10600\n0'\n#10800\nb100000000000010000110011 &\nb100000000000010000110011 4\"\nb100000000000010000110011 a#\nb1010 %\nb1010 3\"\nb1010 `#\nb0 $\nb0 &\"\nb0 \\#\nb10101 $\"\nb10101 9#\nb1100011 -\"\nb1000 c\"\nb10111 b\"\nb101000 E\"\nb100100 F\"\nb11011100000000010000010011 A\"\nb0 k\"\nb0 j\"\nb0 i\"\nb11 l\"\nb10101 o\"\nb1100 n\"\nb110 m\"\nb101 p\"\nb0 \"\nb0 J\"\nb0 ]#\nb0 >\"\nb10011 C\"\nb0 I\"\nb11111110110000110100101011100011 D\"\n1'\nb11011 b#\n#11000\n0'\n#11200\nb110111 <\"\nb110111 v\"\nb110111 t\"\n0l\nb110111 @\"\nb110111 s\"\n1J\nb1 #\"\nb1 [#\nb10 k\nb10 Z#\n1i\nb110111 5\"\nb110111 2#\nb110111 $#\nb11011100000000000000000000 \"#\nb101000 ##\nb101000 %#\nb100000110110 !#\nb0 $\"\nb0 9#\n1v\nb10011 -\"\nb10111 )\"\nb10111 7#\nb1 7\"\nb110111 /#\nb11011100000000 (#\nb1000 '#\nb1 .#\nb100 &#\nb1 0#\n1,#\nb11011 1#\nb101000000010000010011 &\nb101000000010000010011 4\"\nb101000000010000010011 a#\nb1011 %\nb1011 3\"\nb1011 `#\nb10011 D\"\nb0 o\"\nb0 n\"\nb0 m\"\nb11 p\"\nb11011100000000010000010011 B\"\nb11011100000000010000010011 }\"\nb100100 G\"\nb1000 g\"\nb10111 f\"\nb101000 F\"\nb100000000000010000110011 A\"\nb0 d\"\nb1000 b\"\nb101100 E\"\n1'\nb11100 b#\n#11400\n0'\n#11600\n0l\nb110111 t\"\nb110111 @\"\nb110111 s\"\nb0 :\"\nb0 |\"\nb1 n\nb1 {\"\nb1 p\nb1 w\"\nb0 6\"\nb0 ~\"\nb0 4#\n1K\nb0 m\nb0 3#\n03\nb0 5\"\nb0 2#\nb110111 I\nb110111 (\"\n04\nb1000 $#\nb100000000000000000000000 \"#\nb1000 ##\nb1000 %#\nb1000 !#\nb10011 &\nb10011 4\"\nb10011 a#\nb1100 %\nb1100 3\"\nb1100 `#\n11\n1!\"\n0/\"\nb110011 .\"\nb1000 )\"\nb1000 7#\nb0 7\"\nb1000 /#\nb100000000000 (#\nb0 .#\nb0 0#\n0,#\nb100 1#\nb110111 $\nb110111 &\"\nb110111 \\#\nb0 \"\"\nb0 :#\nb11 d\"\nb1 b\"\nb1000 a\"\nb110000 E\"\nb1000 f\"\nb0 h\"\nb101100 F\"\nb101000000010000010011 A\"\nb1000 k\"\nb10111 j\"\nb100000000000010000110011 B\"\nb100000000000010000110011 }\"\nb101000 G\"\nb110111 >\"\nb100100 H\"\nb11011100000000010000010011 C\"\nb0 K\"\n1'\nb11101 b#\n#11800\n0'\n#12000\nb111000 <\"\nb111000 v\"\nb1 t\"\nb1 @\"\nb1 s\"\nb110111 r\"\n0l\nb110111 ?\"\nb110111 q\"\nb110111 *\"\nb110111 6#\nb110111 C#\nb1 :\"\nb1 |\"\nb11 n\nb11 {\"\nb1 5\"\nb1 2#\nb1 6\"\nb1 ~\"\nb1 4#\n0K\nb10 m\nb10 3#\n13\nb110111 H\nb110111 +\"\n14\nb1 $#\nb101000000000000000000 \"#\nb1000000100000000000 !#\nb1 I\nb1 (\"\n1/\n10\nb110111 \"\"\nb110111 :#\nb1000 $\"\nb1000 9#\n0!\"\n1/\"\nb10011 .\"\nb1000 ,\"\nb1000 5#\nb1 '\"\nb1 8#\nb1 )\"\nb1 7#\nb1 /#\nb101000000 (#\nb1000000 *#\n1,#\nb0 1#\n01\nbx &\nbx 4\"\nbx a#\nb1101 %\nb1101 3\"\nb1101 `#\nb110111 K\"\nb11011100000000010000010011 D\"\nb1000 o\"\nb10111 n\"\nb110111 \"\nb110111 J\"\nb110111 ]#\nb101000 H\"\nb100000000000010000110011 C\"\nb1000 j\"\nb0 l\"\nb101000000010000010011 B\"\nb101000000010000010011 }\"\nb101100 G\"\nb1 f\"\nb1000 e\"\nb11 h\"\nb110000 F\"\nb10011 A\"\nb0 c\"\nb0 b\"\nb0 a\"\nb110100 E\"\n1'\nb11110 b#\n#12200\n0'\n#12400\nb0 <\"\nb0 v\"\nb0 t\"\n1l\nb0 @\"\nb0 s\"\nb0 r\"\nb0 ?\"\nb0 q\"\nb1 #\"\nb1 [#\nb0 I\nb0 (\"\nb0 5\"\nb0 2#\nb10 k\nb10 Z#\n0i\nx.\nb0 $#\nb0 \"#\nb0 ##\nb0 %#\nb0 !#\nb1110 %\nb1110 3\"\nb1110 `#\n0/\n00\nb0 *\"\nb0 6#\nb0 ,\"\nb0 5#\nb0 '\"\nb0 8#\nb0 )\"\nb0 7#\nb0 /#\nb0 (#\nb0 '#\nb0 &#\nb0 *#\n0,#\nb0 H\nb0 +\"\nb111000 $\nb111000 &\"\nb111000 \\#\n1u\n0v\nb110011 -\"\nbx c\"\nbx b\"\nbx a\"\nb111000 E\"\nb0 g\"\nb0 f\"\nb0 e\"\nb110100 F\"\nbx A\"\nb1 j\"\nb1000 i\"\nb11 l\"\nb10011 B\"\nb10011 }\"\nb110000 G\"\nb1000 n\"\nb0 p\"\nb1 \"\nb1 J\"\nb1 ]#\nb111000 >\"\nb101100 H\"\nb101000000010000010011 C\"\nb100000000000010000110011 D\"\n1'\nb11111 b#\n#12600\n0'\n#12800\nb0x <\"\nb0x v\"\nbx0 t\"\nxl\nbx0 @\"\nbx0 s\"\nb111000 C#\nb0x1 n\nb0x1 {\"\nb1101 =\"\nb1101 u\"\nb1101 x\"\n1i\nx3\nxK\nx^\nxV\nxX\nxY\nx`\nx\\\nxZ\nxS\nxM\nxP\nxQ\nxT\nxN\nxL\nx_\nxW\nx]\nx[\nxR\nxO\nxU\nx=\nxC\nxA\nb0xxxxxxxxxxxxxx p\nb0xxxxxxxxxxxxxx w\"\nx>\nxD\nxB\nbx I\nbx (\"\nbx0 5\"\nbx0 2#\nbx H\nbx +\"\nb10 ;\"\nb10 z\"\nb101 6\"\nb101 ~\"\nb101 4#\nxG\nxe\nx4\nx?\nx@\nxE\nx<\nx6\nx5\nx(\nx-\nx+\nx)\nx,\nx*\nbx $#\nbx000000000000 \"#\nbx ##\nbx0 %#\nbx0 !#\nx/\nx0\nb111000 \"\"\nb111000 :#\n0u\n1v\nb10011 -\"\nb0 $\nb0 &\"\nb0 \\#\nx!\"\nx~\nx0\"\nx/\"\nx2\"\nx7\nx1\"\nx}\nx9\"\nb0xx1 o\nb0xx1 y\"\nxh\nxz\nb0xxxxx0 m\nb0xxxxx0 3#\nxg\nx{\nxf\nx|\nbx .\"\nbx 8\"\nbx *\"\nbx 6#\nbx ,\"\nbx 5#\nbx '\"\nbx 8#\nbx )\"\nbx 7#\nbx 7\"\nbx /#\nbx (#\nbx '#\nbx .#\nx-#\nbx &#\nbx 0#\nx+#\nbx *#\nx,#\nbx 1#\nx)#\nb1111 %\nb1111 3\"\nb1111 `#\nb111000 K\"\nb101000000010000010011 D\"\nb1 n\"\nb1000 m\"\nb11 p\"\nb0 \"\nb0 J\"\nb0 ]#\nb0 >\"\nb110000 H\"\nb10011 C\"\nb0 k\"\nb0 j\"\nb0 i\"\nbx B\"\nbx }\"\nb110100 G\"\nbx g\"\nbx f\"\nbx e\"\nb111000 F\"\nb111100 E\"\n1'\nb100000 b#\n#13000\n0'\n#13200\nx8\nx:\nx;\nx9\nxa\nxc\nxd\nxb\nb10000 %\nb10000 3\"\nb10000 `#\nbx #\nbx %\"\nbx ^#\nb0x $\nb0x &\"\nb0x \\#\nx!\nb0 \"\"\nb0 :#\nb0 $\"\nb0 9#\nb1000000 E\"\nb111100 F\"\nbx k\"\nbx j\"\nbx i\"\nb111000 G\"\nb0 o\"\nb0 n\"\nb0 m\"\nbx \"\nbx J\"\nbx ]#\nb0x >\"\nb110100 H\"\nbx C\"\nb0 K\"\nb10011 D\"\n1'\nb100001 b#\n#13400\n0'\n#13600\nxJ\nxi\nb11 #\"\nb11 [#\nxj\nbx \"\"\nbx :#\nbx $\"\nbx 9#\nxu\nxt\nbx0 k\nbx0 Z#\nxw\nxv\nxy\nxx\nxq\nxr\nxs\nbx -\"\nb10001 %\nb10001 3\"\nb10001 `#\nb0x K\"\nbx I\"\nbx D\"\nbx o\"\nbx n\"\nbx m\"\nb111000 H\"\nb111100 G\"\nb1000000 F\"\nb1000100 E\"\n1'\nb100010 b#\n#13800\n0'\n#14000\nb10010 %\nb10010 3\"\nb10010 `#\nb1001000 E\"\nb1000100 F\"\nb1000000 G\"\nb111100 H\"\n1'\nb100011 b#\n#14200\n0'\n#14400\nb10011 %\nb10011 3\"\nb10011 `#\nb1000000 H\"\nb1000100 G\"\nb1001000 F\"\nb1001100 E\"\n1'\nb100100 b#\n#14600\n0'\n#14800\nb10100 %\nb10100 3\"\nb10100 `#\nb1010000 E\"\nb1001100 F\"\nb1001000 G\"\nb1000100 H\"\n1'\nb100101 b#\n#15000\n0'\n#15200\nb10101 %\nb10101 3\"\nb10101 `#\nb1001000 H\"\nb1001100 G\"\nb1010000 F\"\nb1010100 E\"\n1'\nb100110 b#\n#15400\n0'\n#15600\nb10110 %\nb10110 3\"\nb10110 `#\nb1011000 E\"\nb1010100 F\"\nb1010000 G\"\nb1001100 H\"\n1'\nb100111 b#\n#15800\n0'\n#16000\nb101000 b#\n"
  },
  {
    "path": "testbench/vcd/ram.vcd",
    "content": "$date\n\tMon May 24 15:33:45 2021\n$end\n$version\n\tIcarus Verilog\n$end\n$timescale\n\t100ps\n$end\n$scope module tb_RAM $end\n$var wire 64 ! DATA_OUT [63:0] $end\n$var reg 10 \" ADDRESS [9:0] $end\n$var reg 1 # CLK $end\n$var reg 64 $ DATA_IN [63:0] $end\n$var reg 1 % WRITE_ENABLE $end\n$scope module ram $end\n$var wire 10 & ADDRESS [9:0] $end\n$var wire 1 # CLK $end\n$var wire 64 ' DATA_IN [63:0] $end\n$var wire 64 ( DATA_OUT [63:0] $end\n$var wire 1 % WRITE_ENABLE $end\n$scope begin $ivl_for_loop0 $end\n$var integer 32 ) i [31:0] $end\n$upscope $end\n$upscope $end\n$upscope $end\n$enddefinitions $end\n#0\n$dumpvars\nb10000000000 )\nb110111 (\nb110111 '\nb1 &\n1%\nb110111 $\n1#\nb1 \"\nb110111 !\n$end\n#200\n0#\n#400\n1#\nb1100011 $\nb1100011 '\nb1100011 !\nb1100011 (\nb10 \"\nb10 &\n#600\n0#\n#800\n1#\nb0 $\nb0 '\n0%\nb110111 !\nb110111 (\nb1 \"\nb1 &\n#1000\n0#\n#1200\n1#\nb1100011 !\nb1100011 (\nb10 \"\nb10 &\n#1400\n0#\n#1600\n"
  },
  {
    "path": "testbench/vcd/regfile.vcd",
    "content": "$date\n\tMon May 24 15:33:45 2021\n$end\n$version\n\tIcarus Verilog\n$end\n$timescale\n\t100ps\n$end\n$scope module tb_RegFile $end\n$var wire 64 ! R2_data [63:0] $end\n$var wire 64 \" R1_data [63:0] $end\n$var reg 5 # R1 [4:0] $end\n$var reg 5 $ R2 [4:0] $end\n$var reg 5 % RD [4:0] $end\n$var reg 64 & RD_DATA [63:0] $end\n$var reg 1 ' reg_write_enable $end\n$scope module regfile $end\n$var wire 5 ( R1 [4:0] $end\n$var wire 64 ) R1_DATA [63:0] $end\n$var wire 5 * R2 [4:0] $end\n$var wire 64 + R2_DATA [63:0] $end\n$var wire 5 , RD [4:0] $end\n$var wire 64 - RD_DATA [63:0] $end\n$var wire 1 ' WRITE_ENABLE $end\n$var integer 32 . i [31:0] $end\n$scope begin REG_DATAS[1] $end\n$var wire 64 / R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[2] $end\n$var wire 64 0 R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[3] $end\n$var wire 64 1 R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[4] $end\n$var wire 64 2 R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[5] $end\n$var wire 64 3 R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[6] $end\n$var wire 64 4 R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[7] $end\n$var wire 64 5 R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[8] $end\n$var wire 64 6 R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[9] $end\n$var wire 64 7 R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[10] $end\n$var wire 64 8 R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[11] $end\n$var wire 64 9 R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[12] $end\n$var wire 64 : R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[13] $end\n$var wire 64 ; R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[14] $end\n$var wire 64 < R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[15] $end\n$var wire 64 = R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[16] $end\n$var wire 64 > R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[17] $end\n$var wire 64 ? R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[18] $end\n$var wire 64 @ R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[19] $end\n$var wire 64 A R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[20] $end\n$var wire 64 B R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[21] $end\n$var wire 64 C R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[22] $end\n$var wire 64 D R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[23] $end\n$var wire 64 E R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[24] $end\n$var wire 64 F R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[25] $end\n$var wire 64 G R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[26] $end\n$var wire 64 H R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[27] $end\n$var wire 64 I R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[28] $end\n$var wire 64 J R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[29] $end\n$var wire 64 K R_DATA [63:0] $end\n$upscope $end\n$scope begin REG_DATAS[30] $end\n$var wire 64 L R_DATA [63:0] $end\n$upscope $end\n$upscope $end\n$upscope $end\n$enddefinitions $end\n#0\n$dumpvars\nb0 L\nb0 K\nb0 J\nb0 I\nb0 H\nb0 G\nb0 F\nb0 E\nb0 D\nb0 C\nb0 B\nb0 A\nb0 @\nb0 ?\nb0 >\nb0 =\nb0 <\nb0 ;\nb0 :\nb0 9\nb0 8\nb0 7\nb0 6\nb0 5\nb0 4\nb0 3\nb0 2\nb0 1\nb0 0\nb0 /\nb100000 .\nb0 -\nb0 ,\nb0 +\nb0 *\nb0 )\nb0 (\n0'\nb0 &\nb0 %\nb0 $\nb0 #\nb0 \"\nb0 !\n$end\n#200\nb101 /\n1'\nb101 &\nb101 -\nb1 %\nb1 ,\n#400\nb1010 0\nb1010 &\nb1010 -\nb10 %\nb10 ,\nb101 \"\nb101 )\nb1 #\nb1 (\n#600\n0'\nb0 &\nb0 -\nb0 %\nb0 ,\nb1010 !\nb1010 +\nb10 $\nb10 *\n#800\n"
  },
  {
    "path": "testbench/vcd/rom.vcd",
    "content": "$date\n\tMon May 24 15:33:45 2021\n$end\n$version\n\tIcarus Verilog\n$end\n$timescale\n\t100ps\n$end\n$scope module tb_ROM $end\n$var wire 32 ! DATA_OUT [31:0] $end\n$var reg 10 \" ADDRESS [9:0] $end\n$scope module rom $end\n$var wire 10 # ADDRESS [9:0] $end\n$var wire 32 $ DATA [31:0] $end\n$upscope $end\n$upscope $end\n$enddefinitions $end\n#0\n$dumpvars\nb10011 $\nb0 #\nb0 \"\nb10011 !\n$end\n#200\nb100000000000010010011 !\nb100000000000010010011 $\nb1 \"\nb1 #\n#400\nb100000000001100010011 !\nb100000000001100010011 $\nb10 \"\nb10 #\n#600\nb10000000000011000010011 !\nb10000000000011000010011 $\nb11 \"\nb11 #\n#800\nb11000001010000000100011 !\nb11000001010000000100011 $\nb100 \"\nb100 #\n#1000\nb1010001100000011 !\nb1010001100000011 $\nb101 \"\nb101 #\n#1200\nbx !\nbx $\nb10100 \"\nb10100 #\n#1400\n"
  }
]