Repository: eminfedar/fedar-f1-rv64im Branch: main Commit: 05c9dad274ac Files: 28 Total size: 87.0 KB Directory structure: gitextract_9lnfhkcl/ ├── LICENSE ├── README.md ├── example/ │ └── Program.s ├── gtkwave/ │ ├── pipeline_type_enums.gtkw │ └── rom_instruction_enums.gtkw ├── src/ │ ├── ALU.v │ ├── CPU.v │ ├── Encoders.v │ ├── ImmediateExtractor.v │ ├── RAM.v │ ├── ROM.v │ └── RegFile.v └── testbench/ ├── run_main_test.sh ├── run_tests.sh ├── tb_ALU.v ├── tb_Encoders.v ├── tb_ImmediateExtractor.v ├── tb_Main.v ├── tb_RAM.v ├── tb_ROM.v ├── tb_RegFile.v └── vcd/ ├── alu.vcd ├── encoders.vcd ├── immediateextractor.vcd ├── main.vcd ├── ram.vcd ├── regfile.vcd └── rom.vcd ================================================ FILE CONTENTS ================================================ ================================================ FILE: LICENSE ================================================ MIT License Copyright (c) 2021 Emin Fedar Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ================================================ FILE: README.md ================================================ # Fedar F1 [![LibreCores](https://www.librecores.org/eminfedar/fedar-f1-rv64im/badge.svg?style=flat)](https://www.librecores.org/eminfedar/fedar-f1-rv64im) Fedar F1 is a 5-Stage Pipelined (Fetch|Decode|Execute|Memory|Writeback) RV64IM RISC-V Core written fully in Verilog. ![Simulated GTKWave output of the CPU](https://raw.githubusercontent.com/eminfedar/fedar-f1-rv64im/main/gtkwave-image.png) ## How to compile? 1. Open a terminal in `testbench` folder. 2. Run: `run_tests.sh`. - The script automatically compile and create files under the `testbench/output/` folder. - And will create `.vcd` files under the `testbench/vcd` folder. 3. Done! Compilation requires `iverilog` verilog compiler. You can install iverilog on Debian based distros (like Pardus GNU/Linux or Ubuntu) with this command: ``` sudo apt install iverilog ``` > If you don't want to compile it again, precompiled `.vcd` files are available under the `testbench/vcd`. ## How to open .vcd files? - Use [GTKWave](https://github.com/gtkwave/gtkwave). You can install GTKWave on Debian based distros (like Pardus GNU/Linux or Ubuntu) with this command: ``` sudo apt install gtkwave ``` Then double click the files or open with terminal command: `gtkwave file.vcd`. ================================================ FILE: example/Program.s ================================================ start: nop addi x1, x0, 1 addi x6, x0, 1 addi x12, x0, 4 sw x6, 0(x1) # x6 -> R2 Data Dependency (WriteBack) loop: lw x6, 0(x1) # Load Stall addi x6, x6, 1 # x6 -> R1 Data Dependency sw x6, 0(x1) blt x6, x12, loop # x6 -> R1 Data Dependency (WriteBack) & Control Hazard data_dep_test: addi x8, x0, 55 add x8, x0, x8 # x8 -> R2 Data Dependency addi x8, x8, 1 # x8 -> R1 Data Dependency finish: nop ================================================ FILE: gtkwave/pipeline_type_enums.gtkw ================================================ 0 REGISTER 1 LOAD 2 STORE 3 IMMEDIATE 4 UPPERIMMEDIATE 5 BRANCH ================================================ FILE: gtkwave/rom_instruction_enums.gtkw ================================================ 00000013 NOP 00100093 addi_x1_x0_1 00100313 addi_x6_x0_1 00400613 addi_x12_x0_4 0060A023 sw_x6_0(x1) 0000A303 lw_x6_0(x1) 00130313 addi_x6_x6_1 0060A023 sw_x6_0(x1) FEC34AE3 blt_x6_x12_-12 03700413 addi_x8_x0_55 00800433 add_x8_x0_x8 00140413 addi_x8_x8_1 ================================================ FILE: src/ALU.v ================================================ module ALU( input [63:0] X, input [63:0] Y, input [3:0] OP, output [63:0] OUTPUT, output isEqual ); reg [127:0] RESULT; wire signed [63:0] X_signed = X; wire signed [63:0] Y_signed = Y; assign isEqual = X == Y; always @(*) begin case (OP) 0: RESULT <= X + Y; // add 1: RESULT <= X - Y; // sub 2: RESULT <= X & Y; // and 3: RESULT <= X | Y; // or 4: RESULT <= X ^ Y; // xor 5: RESULT <= X << Y; // shift left logical 6: RESULT <= X >> Y; // shift right logical 7: RESULT <= X_signed >>> Y; // shift right arithmetic 8: RESULT <= X * Y; // mul 9: RESULT <= X * Y; // mulh 10: RESULT <= X / Y; // div 11: RESULT <= X % Y; // rem 12: RESULT <= (X_signed < Y_signed ? 1 : 0); // set less than (slt) 13: RESULT <= (X < Y ? 1 : 0); // set less than (sltu) endcase end assign OUTPUT = OP == 9 ? RESULT[127:64] : RESULT[63:0]; endmodule ================================================ FILE: src/CPU.v ================================================ `include "ALU.v" `include "RegFile.v" `include "ImmediateExtractor.v" `include "Encoders.v" module CPU ( input [63:0] RAM_READ_DATA, input [31:0] INSTRUCTION, input CLK, output [9:0] RAM_ADDR, // 10-bit Size RAM output reg [63:0] RAM_WRITE_DATA, output RAM_WRITE_ENABLE, output [9:0] INSTRUCTION_ADDR // 10-bit Size ROM ); // CONSTANTS: // -- OPCODE DEFINES: integer OP_R_TYPE = 7'h33; integer OP_R_TYPE_64 = 7'h3B; integer OP_I_TYPE_LOAD = 7'h03; integer OP_I_TYPE_OTHER = 7'h13; integer OP_I_TYPE_64 = 7'h1B; integer OP_I_TYPE_JUMP = 7'h6F; integer OP_S_TYPE = 7'h23; integer OP_B_TYPE = 7'h63; integer OP_U_TYPE_LOAD = 7'h37; integer OP_U_TYPE_JUMP = 7'h67; integer OP_U_TYPE_AUIPC = 7'h17; // -- PIPELINE HAZARD INSTRUCTION TYPE DEFINES: integer TYPE_REGISTER = 0; integer TYPE_LOAD = 1; integer TYPE_STORE = 2; integer TYPE_IMMEDIATE = 3; integer TYPE_UPPERIMMEDIATE = 4; integer TYPE_BRANCH = 5; // -- PIPELINE STAGES integer DECODE = 0; integer EXECUTE = 1; integer MEMORY = 2; integer WRITEBACK = 3; // WIRE DEFINITIONS: wire [6:0] OPCODE = INSTRUCTION_EXECUTE_3[6:0]; wire [4:0] RD = INSTRUCTION_WRITEBACK_5[11:7]; wire [2:0] FUNCT3 = INSTRUCTION_EXECUTE_3[14:12]; wire [4:0] R1 = INSTRUCTION_EXECUTE_3[19:15]; wire [4:0] R2 = INSTRUCTION_EXECUTE_3[24:20]; wire [6:0] FUNCT7 = INSTRUCTION_EXECUTE_3[31:25]; wire R_TYPE = OPCODE == OP_R_TYPE; wire R_TYPE_64 = OPCODE == OP_R_TYPE_64; wire I_TYPE_LOAD = OPCODE == OP_I_TYPE_LOAD; wire I_TYPE_OTHER = OPCODE == OP_I_TYPE_OTHER; wire I_TYPE_64 = OPCODE == OP_I_TYPE_64; wire I_TYPE_JUMP = OPCODE == OP_I_TYPE_JUMP; wire I_TYPE = I_TYPE_JUMP || I_TYPE_LOAD || I_TYPE_OTHER || I_TYPE_64; wire S_TYPE = OPCODE == OP_S_TYPE; wire B_TYPE = OPCODE == OP_B_TYPE; wire U_TYPE_LOAD = OPCODE == OP_U_TYPE_LOAD; wire U_TYPE_JUMP = OPCODE == OP_U_TYPE_JUMP; wire U_TYPE_AUIPC = OPCODE == OP_U_TYPE_AUIPC; wire U_TYPE = U_TYPE_JUMP || U_TYPE_LOAD || U_TYPE_AUIPC; // -- Register-Register Types (R-Type) // ---- RV32I: wire R_add = R_TYPE && FUNCT3 == 3'h0 && FUNCT7 == 7'h00; wire R_sub = R_TYPE && FUNCT3 == 3'h0 && FUNCT7 == 7'h20; wire R_sll = R_TYPE && FUNCT3 == 3'h1 && FUNCT7 == 7'h00; wire R_slt = R_TYPE && FUNCT3 == 3'h2 && FUNCT7 == 7'h00; wire R_sltu = R_TYPE && FUNCT3 == 3'h3 && FUNCT7 == 7'h00; wire R_xor = R_TYPE && FUNCT3 == 3'h4 && FUNCT7 == 7'h00; wire R_srl = R_TYPE && FUNCT3 == 3'h5 && FUNCT7 == 7'h00; wire R_sra = R_TYPE && FUNCT3 == 3'h5 && FUNCT7 == 7'h20; wire R_or = R_TYPE && FUNCT3 == 3'h6 && FUNCT7 == 7'h00; wire R_and = R_TYPE && FUNCT3 == 3'h7 && FUNCT7 == 7'h00; // ---- RV32M: wire R_mul = R_TYPE && FUNCT3 == 3'h0 && FUNCT7 == 7'h01; wire R_mulh = R_TYPE && FUNCT3 == 3'h1 && FUNCT7 == 7'h01; wire R_rem = R_TYPE && FUNCT3 == 3'h6 && FUNCT7 == 7'h01; wire R_div = R_TYPE && FUNCT3 == 3'h4 && FUNCT7 == 7'h01; // ---- RV64I: wire R_addw = R_TYPE_64 && FUNCT3 == 3'h0 && FUNCT7 == 7'h00; wire R_subw = R_TYPE_64 && FUNCT3 == 3'h0 && FUNCT7 == 7'h20; wire R_sllw = R_TYPE_64 && FUNCT3 == 3'h1 && FUNCT7 == 7'h00; wire R_srlw = R_TYPE_64 && FUNCT3 == 3'h5 && FUNCT7 == 7'h00; wire R_sraw = R_TYPE_64 && FUNCT3 == 3'h5 && FUNCT7 == 7'h20; // ---- RV64M: wire R_mulw = R_TYPE_64 && FUNCT3 == 3'h0 && FUNCT7 == 7'h01; wire R_divw = R_TYPE_64 && FUNCT3 == 3'h4 && FUNCT7 == 7'h01; wire R_remw = R_TYPE_64 && FUNCT3 == 3'h6 && FUNCT7 == 7'h01; // -- Immediate Types (I-Type) // ---- RV32I: wire I_addi = I_TYPE_OTHER && FUNCT3 == 3'h0; wire I_slli = I_TYPE_OTHER && FUNCT3 == 3'h1 && FUNCT7 == 7'h00; wire I_slti = I_TYPE_OTHER && FUNCT3 == 3'h2; wire I_sltiu = I_TYPE_OTHER && FUNCT3 == 3'h3; wire I_xori = I_TYPE_OTHER && FUNCT3 == 3'h4; wire I_srli = I_TYPE_OTHER && FUNCT3 == 3'h5 && FUNCT7 == 7'h00; wire I_srai = I_TYPE_OTHER && FUNCT3 == 3'h5 && FUNCT7 == 7'h10; wire I_ori = I_TYPE_OTHER && FUNCT3 == 3'h6; wire I_andi = I_TYPE_OTHER && FUNCT3 == 3'h7; // ---- RV64I: wire I_addiw = I_TYPE_64 && FUNCT3 == 3'h0; wire I_slliw = I_TYPE_64 && FUNCT3 == 3'h1 && FUNCT7 == 7'h00; wire I_srliw = I_TYPE_64 && FUNCT3 == 3'h5 && FUNCT7 == 7'h00; wire I_sraiw = I_TYPE_64 && FUNCT3 == 3'h5 && FUNCT7 == 7'h20; // ---- Load wire I_lb = INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_LOAD && INSTRUCTION_MEMORY_4[14:12] == 3'h0; wire I_lh = INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_LOAD && INSTRUCTION_MEMORY_4[14:12] == 3'h1; wire I_lw = INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_LOAD && INSTRUCTION_MEMORY_4[14:12] == 3'h2; wire I_ld = INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_LOAD && INSTRUCTION_MEMORY_4[14:12] == 3'h3; // ---- Jump wire I_jalr = I_TYPE_JUMP; // -- Upper Immediate Types (U-Type) wire U_lui = U_TYPE_LOAD; wire U_auipc = U_TYPE_AUIPC; wire U_jal = U_TYPE_JUMP; // -- Store Types (S-Type) wire S_sb = INSTRUCTION_MEMORY_4[6:0] == OP_S_TYPE && INSTRUCTION_MEMORY_4[14:12] == 3'h0; wire S_sh = INSTRUCTION_MEMORY_4[6:0] == OP_S_TYPE && INSTRUCTION_MEMORY_4[14:12] == 3'h1; wire S_sw = INSTRUCTION_MEMORY_4[6:0] == OP_S_TYPE && INSTRUCTION_MEMORY_4[14:12] == 3'h2; wire S_sd = INSTRUCTION_MEMORY_4[6:0] == OP_S_TYPE && INSTRUCTION_MEMORY_4[14:12] == 3'h3; // -- Branch Types (B-Type) wire B_beq = B_TYPE && FUNCT3 == 0; wire B_bne = B_TYPE && FUNCT3 == 1; wire B_blt = B_TYPE && FUNCT3 == 4; wire B_bge = B_TYPE && FUNCT3 == 5; wire B_bltu = B_TYPE && FUNCT3 == 6; wire B_bgeu = B_TYPE && FUNCT3 == 7; // -- PC Get Data From ALU Switch wire signed [63:0] R1_DATA = DATA_DEPENDENCY_HAZARD_R1 ? ALU_OUT_MEMORY_4 : DATA_DEPENDENCY_HAZARD_R1_WRITEBACK ? (REG_WRITEBACK_SELECTION == 3 ? RAM_READ_DATA_WRITEBACK_5 : REG_WRITE_DATA_WRITEBACK_5) : R1_DATA_EXECUTE_3; wire signed [63:0] R2_DATA = DATA_DEPENDENCY_HAZARD_R2 ? ALU_OUT_MEMORY_4 : DATA_DEPENDENCY_HAZARD_R2_WRITEBACK ? (REG_WRITEBACK_SELECTION == 3 ? RAM_READ_DATA_WRITEBACK_5 : REG_WRITE_DATA_WRITEBACK_5) : R2_DATA_EXECUTE_3; wire [63:0] R1_DATA_UNSIGNED = R1_DATA; wire [63:0] R2_DATA_UNSIGNED = R2_DATA; wire PC_ALU_SEL = (B_beq && R1_DATA == R2_DATA) || (B_bne && R1_DATA != R2_DATA) || (B_blt && R1_DATA < R2_DATA) || (B_bge && R1_DATA >= R2_DATA) || (B_bltu && R1_DATA_UNSIGNED < R2_DATA_UNSIGNED) || (B_bgeu && R1_DATA_UNSIGNED >= R2_DATA_UNSIGNED) || I_jalr || U_jal ; // -- RAM Read & Write Enable Pins assign RAM_WRITE_ENABLE = INSTRUCTION_MEMORY_4[6:0] == OP_S_TYPE; assign RAM_ADDR = ALU_OUT_MEMORY_4[9:0]; // -- PIPELINING HAZARDS // ---- DATA HAZARD CONTROL REGISTERS reg [4:0] R1_PIPELINE[3:0]; // R1 Register of the current stage. reg [4:0] R2_PIPELINE[3:0]; // R2 Register of the current stage. reg [4:0] RD_PIPELINE[3:0]; // RD Register of the current stage. reg [2:0] TYPE_PIPELINE[3:0]; // Instruction Types of the current stage. [R-Type=0, Load=1, Store=2, Immediate or UpperImmediate=3, Branch=4] // If R1 depends on the previous RD (or R2 if STORE) wire DATA_DEPENDENCY_HAZARD_R1 = R1_PIPELINE[EXECUTE] != 0 && TYPE_PIPELINE[EXECUTE] != TYPE_UPPERIMMEDIATE && R1_PIPELINE[EXECUTE] == RD_PIPELINE[MEMORY]; // If R2 depends on the previous RD (or R2 if STORE) wire DATA_DEPENDENCY_HAZARD_R2 = R2_PIPELINE[EXECUTE] != 0 && TYPE_PIPELINE[EXECUTE] != TYPE_UPPERIMMEDIATE && TYPE_PIPELINE[EXECUTE] != TYPE_IMMEDIATE && R2_PIPELINE[EXECUTE] == RD_PIPELINE[MEMORY]; // If R1 depends on the 5th stage RD wire DATA_DEPENDENCY_HAZARD_R1_WRITEBACK = R1_PIPELINE[EXECUTE] != 0 && TYPE_PIPELINE[EXECUTE] != TYPE_UPPERIMMEDIATE && R1_PIPELINE[EXECUTE] == RD_PIPELINE[WRITEBACK]; // If R2 depends on the 5th stage RD wire DATA_DEPENDENCY_HAZARD_R2_WRITEBACK = R2_PIPELINE[EXECUTE] != 0 && TYPE_PIPELINE[EXECUTE] != TYPE_UPPERIMMEDIATE && TYPE_PIPELINE[EXECUTE] != TYPE_IMMEDIATE && R2_PIPELINE[EXECUTE] == RD_PIPELINE[WRITEBACK]; // If the next instruction depends on a Load instruction before, stall one clock. wire LOAD_STALL = TYPE_PIPELINE[EXECUTE] == TYPE_LOAD && ( ( TYPE_PIPELINE[DECODE] != TYPE_UPPERIMMEDIATE && TYPE_PIPELINE[DECODE] != TYPE_IMMEDIATE && ( (R1_PIPELINE[DECODE] != 0 && R1_PIPELINE[DECODE] == RD_PIPELINE[EXECUTE]) || (R2_PIPELINE[DECODE] != 0 && R2_PIPELINE[DECODE] == RD_PIPELINE[EXECUTE]) ) ) || ( TYPE_PIPELINE[DECODE] == TYPE_IMMEDIATE && R1_PIPELINE[DECODE] != 0 && R1_PIPELINE[DECODE] == RD_PIPELINE[EXECUTE] ) ); // If there is a branch instruction, stall for 2 clocks. wire CONTROL_HAZARD_STALL = INSTRUCTION_DECODE_2[6:0] == OP_B_TYPE || INSTRUCTION_EXECUTE_3[6:0] == OP_B_TYPE; // COMPONENT DEFINITIONS (IMMEDIATE EXTRACTOR, ALU, REGFILE): // -- Immediate Extractor wire [63:0] IMMEDIATE_VALUE; wire [2:0] IMMEDIATE_SELECTION; wire [7:0] immediateSelectionInputs; assign immediateSelectionInputs[0] = 0; assign immediateSelectionInputs[1] = I_TYPE; assign immediateSelectionInputs[2] = U_TYPE_LOAD || U_TYPE_AUIPC; assign immediateSelectionInputs[3] = S_TYPE; assign immediateSelectionInputs[4] = B_TYPE; assign immediateSelectionInputs[5] = U_TYPE_JUMP; assign immediateSelectionInputs[6] = 0; assign immediateSelectionInputs[7] = 0; Encoder_8 immediateSelectionEncoder(immediateSelectionInputs, IMMEDIATE_SELECTION); ImmediateExtractor immediateExtractor(INSTRUCTION_EXECUTE_3, IMMEDIATE_SELECTION, IMMEDIATE_VALUE); // -- ALU Operation Selection wire [15:0] aluOpEncoderInputs; wire [3:0] ALU_OP; assign aluOpEncoderInputs[0] = R_add || R_addw || I_addi || I_addiw; assign aluOpEncoderInputs[1] = R_sub || R_subw; assign aluOpEncoderInputs[2] = R_and || I_andi; assign aluOpEncoderInputs[3] = R_or || I_ori; assign aluOpEncoderInputs[4] = R_xor || I_xori; assign aluOpEncoderInputs[5] = R_sll || R_sllw || I_slli || I_slliw; assign aluOpEncoderInputs[6] = R_srl || R_srlw || I_srli || I_srliw; assign aluOpEncoderInputs[7] = R_sra || R_sraw || I_srai || I_sraiw; assign aluOpEncoderInputs[8] = R_mul || R_mulw; assign aluOpEncoderInputs[9] = R_mulh; assign aluOpEncoderInputs[10] = R_div || R_divw; assign aluOpEncoderInputs[11] = R_rem || R_remw; assign aluOpEncoderInputs[12] = R_slt || I_slti; assign aluOpEncoderInputs[13] = R_sltu || I_sltiu; assign aluOpEncoderInputs[14] = 0; assign aluOpEncoderInputs[15] = 0; Encoder_16 aluOpEncoder(aluOpEncoderInputs, ALU_OP); // -- ALU Input Selection Encoders wire [3:0] aluX1SelectionInputs; wire [3:0] aluX2SelectionInputs; wire [1:0] ALU_X1_SEL; wire [1:0] ALU_X2_SEL; assign aluX1SelectionInputs[0] = 1; assign aluX1SelectionInputs[1] = B_TYPE || U_TYPE_JUMP || U_TYPE_AUIPC || I_TYPE_JUMP; assign aluX1SelectionInputs[2] = U_TYPE_LOAD; assign aluX1SelectionInputs[3] = 0; //DATA_DEPENDENCY_HAZARD_R1_WRITEBACK && B_TYPE == 0 && I_TYPE_JUMP == 0; //assign aluX1SelectionInputs[4] = 0; //DATA_DEPENDENCY_HAZARD_R1 && B_TYPE == 0 && I_TYPE_JUMP == 0; //assign aluX1SelectionInputs[5] = 0; //assign aluX1SelectionInputs[6] = 0; //assign aluX1SelectionInputs[7] = 0; assign aluX2SelectionInputs[0] = 1; assign aluX2SelectionInputs[1] = S_TYPE || I_TYPE || B_TYPE || U_TYPE; assign aluX2SelectionInputs[2] = 0; //DATA_DEPENDENCY_HAZARD_R2_WRITEBACK && (S_TYPE || B_TYPE || U_TYPE) == 0; assign aluX2SelectionInputs[3] = 0; //DATA_DEPENDENCY_HAZARD_R2 && (S_TYPE || B_TYPE || U_TYPE) == 0; Encoder_4 aluX1SelectionEncoder(aluX1SelectionInputs, ALU_X1_SEL); Encoder_4 aluX2SelectionEncoder(aluX2SelectionInputs, ALU_X2_SEL); // -- ALU reg [63:0] ALU_X1; reg [63:0] ALU_X2; wire [63:0] ALU_OUT; wire isALUEqual; ALU alu(ALU_X1, ALU_X2, ALU_OP, ALU_OUT, isALUEqual); always @(*) begin case(ALU_X1_SEL) 0: ALU_X1 <= R1_DATA; 1: ALU_X1 <= PC_EXECUTE_3; //2: ALU_X1 <= 0; //3: ALU_X1 <= REG_WRITE_DATA_WRITEBACK_5; // USE WRITEBACK output directly (Data Hazard fix) //4: ALU_X1 <= ALU_OUT_MEMORY_4; // USE ALU output directly (Data Hazard fix) default: ALU_X1 <= 0; endcase case(ALU_X2_SEL) 0: ALU_X2 <= R2_DATA; 1: ALU_X2 <= IMMEDIATE_VALUE; //2: ALU_X2 <= REG_WRITE_DATA_WRITEBACK_5; // USE WRITEBACK output directly (Data Hazard fix) //3: ALU_X2 <= ALU_OUT_MEMORY_4; // USE ALU output directly (Data Hazard fix) default: ALU_X2 <= 0; endcase end // -- RegFile // Decoding OPCODE for 5th stage of pipeline. wire [6:0] OPCODE_WRITEBACK_5 = INSTRUCTION_WRITEBACK_5[6:0]; wire WB_R_TYPE = OPCODE_WRITEBACK_5 == OP_R_TYPE; wire WB_R_TYPE_64 = OPCODE_WRITEBACK_5 == OP_R_TYPE_64; wire WB_I_TYPE_LOAD = OPCODE_WRITEBACK_5 == OP_I_TYPE_LOAD; wire WB_I_TYPE_OTHER = OPCODE_WRITEBACK_5 == OP_I_TYPE_OTHER; wire WB_I_TYPE_64 = OPCODE_WRITEBACK_5 == OP_I_TYPE_64; wire WB_I_TYPE_JUMP = OPCODE_WRITEBACK_5 == OP_I_TYPE_JUMP; wire WB_I_TYPE = WB_I_TYPE_JUMP || WB_I_TYPE_LOAD || WB_I_TYPE_OTHER || WB_I_TYPE_64; wire WB_U_TYPE_LOAD = OPCODE_WRITEBACK_5 == OP_U_TYPE_LOAD; wire WB_U_TYPE_JUMP = OPCODE_WRITEBACK_5 == OP_U_TYPE_JUMP; wire WB_U_TYPE_AUIPC = OPCODE_WRITEBACK_5 == OP_U_TYPE_AUIPC; wire WB_U_TYPE = WB_U_TYPE_JUMP || WB_U_TYPE_LOAD || WB_U_TYPE_AUIPC; wire REG_WRITE_ENABLE = WB_R_TYPE || WB_R_TYPE_64 || WB_I_TYPE || WB_U_TYPE; // -- Register Write Back Selection Encoder wire [3:0] regWritebackSelectionInputs; wire [1:0] REG_WRITEBACK_SELECTION; assign regWritebackSelectionInputs[0] = 0; assign regWritebackSelectionInputs[1] = WB_R_TYPE || WB_R_TYPE_64 || WB_U_TYPE_LOAD || WB_I_TYPE_OTHER || WB_I_TYPE_64; assign regWritebackSelectionInputs[2] = WB_U_TYPE_JUMP || WB_I_TYPE_JUMP; assign regWritebackSelectionInputs[3] = WB_I_TYPE_LOAD; Encoder_4 writeBackSelectionEncoder(regWritebackSelectionInputs, REG_WRITEBACK_SELECTION); wire signed[63:0] R1_DATA_EXECUTE_3; wire signed [63:0] R2_DATA_EXECUTE_3; wire [63:0] REG_WRITE_DATA = REG_WRITEBACK_SELECTION == 3 ? RAM_READ_DATA_WRITEBACK_5 : REG_WRITE_DATA_WRITEBACK_5; RegFile regFile(R1, R2, RD, REG_WRITE_DATA, REG_WRITE_ENABLE, R1_DATA_EXECUTE_3, R2_DATA_EXECUTE_3); // == PIPELINING ================================================== // -- 1. Stage: Fetch reg [9:0] PC = 0; assign INSTRUCTION_ADDR = PC >> 2; always @(posedge CLK) begin if (PC_ALU_SEL == 1) begin PC <= ALU_OUT[9:0]; end else begin if (LOAD_STALL == 1 || CONTROL_HAZARD_STALL == 1) PC <= PC; else PC <= PC + 4; end // PIPELINE HAZARD DATA REGISTERS if (CONTROL_HAZARD_STALL == 1) begin R1_PIPELINE[DECODE] <= 0; R2_PIPELINE[DECODE] <= 0; RD_PIPELINE[DECODE] <= 0; TYPE_PIPELINE[DECODE] <= TYPE_IMMEDIATE; end else begin R1_PIPELINE[DECODE] <= INSTRUCTION[19:15]; R2_PIPELINE[DECODE] <= INSTRUCTION[24:20]; RD_PIPELINE[DECODE] <= INSTRUCTION[11:7]; if (INSTRUCTION[6:0] == OP_R_TYPE || INSTRUCTION[6:0] == OP_R_TYPE_64) // R-Type TYPE_PIPELINE[DECODE] <= TYPE_REGISTER; else if (INSTRUCTION[6:0] == OP_I_TYPE_LOAD) // Load TYPE_PIPELINE[DECODE] <= TYPE_LOAD; else if (INSTRUCTION[6:0] == OP_S_TYPE) // Store TYPE_PIPELINE[DECODE] <= TYPE_STORE; else if (INSTRUCTION[6:0] == OP_I_TYPE_OTHER || INSTRUCTION[6:0] == OP_I_TYPE_64 || INSTRUCTION[6:0] == OP_I_TYPE_JUMP) // Immediate TYPE_PIPELINE[DECODE] <= TYPE_IMMEDIATE; else if (INSTRUCTION[6:0] == OP_B_TYPE[6:0]) // Branch TYPE_PIPELINE[DECODE] <= TYPE_BRANCH; end end // -- 2. Stage: Decode reg [9:0] PC_DECODE_2 = 0; reg [31:0] INSTRUCTION_DECODE_2 = 0; always @(posedge CLK) begin if (LOAD_STALL == 1) begin INSTRUCTION_DECODE_2 <= INSTRUCTION_DECODE_2; PC_DECODE_2 <= PC_DECODE_2; end else if (CONTROL_HAZARD_STALL == 1) begin INSTRUCTION_DECODE_2 <= 32'h00000013; PC_DECODE_2 <= PC_DECODE_2; end else begin INSTRUCTION_DECODE_2 <= INSTRUCTION; PC_DECODE_2 <= PC; end // Pipeline Type if (INSTRUCTION_DECODE_2[6:0] == OP_R_TYPE || INSTRUCTION_DECODE_2[6:0] == OP_R_TYPE_64) // R-Type TYPE_PIPELINE[EXECUTE] <= TYPE_REGISTER; else if (INSTRUCTION_DECODE_2[6:0] == OP_I_TYPE_LOAD) // Load TYPE_PIPELINE[EXECUTE] <= TYPE_LOAD; else if (INSTRUCTION_DECODE_2[6:0] == OP_S_TYPE) // Store TYPE_PIPELINE[EXECUTE] <= TYPE_STORE; else if (INSTRUCTION_DECODE_2[6:0] == OP_I_TYPE_OTHER || INSTRUCTION_DECODE_2[6:0] == OP_I_TYPE_64 || INSTRUCTION_DECODE_2[6:0] == OP_I_TYPE_JUMP) // Immediate TYPE_PIPELINE[EXECUTE] <= TYPE_IMMEDIATE; else if (INSTRUCTION_DECODE_2[6:0] == OP_B_TYPE[6:0]) // Branch TYPE_PIPELINE[EXECUTE] <= TYPE_BRANCH; R1_PIPELINE[EXECUTE] <= INSTRUCTION_DECODE_2[19:15]; R2_PIPELINE[EXECUTE] <= INSTRUCTION_DECODE_2[24:20]; RD_PIPELINE[EXECUTE] <= INSTRUCTION_DECODE_2[11:7]; if (LOAD_STALL == 1) begin R1_PIPELINE[EXECUTE] <= 0; R2_PIPELINE[EXECUTE] <= 0; RD_PIPELINE[EXECUTE] <= 0; TYPE_PIPELINE[EXECUTE] <= TYPE_IMMEDIATE; end end // -- 3. Stage: Execute reg [9:0] PC_EXECUTE_3 = 0; reg [31:0] INSTRUCTION_EXECUTE_3 = 0; always @(posedge CLK) begin if (LOAD_STALL == 1 ) begin INSTRUCTION_EXECUTE_3 <= 32'h00000013; // NOP for Stall PC_EXECUTE_3 <= PC_EXECUTE_3; end else begin PC_EXECUTE_3 <= PC_DECODE_2; INSTRUCTION_EXECUTE_3 <= INSTRUCTION_DECODE_2; end if (INSTRUCTION_EXECUTE_3[6:0] == OP_R_TYPE || INSTRUCTION_EXECUTE_3[6:0] == OP_R_TYPE_64) // R-Type TYPE_PIPELINE[MEMORY] <= TYPE_REGISTER; else if (INSTRUCTION_EXECUTE_3[6:0] == OP_I_TYPE_LOAD) // Load TYPE_PIPELINE[MEMORY] <= TYPE_LOAD; else if (INSTRUCTION_EXECUTE_3[6:0] == OP_S_TYPE) // Store TYPE_PIPELINE[MEMORY] <= TYPE_STORE; else if (INSTRUCTION_EXECUTE_3[6:0] == OP_I_TYPE_OTHER || INSTRUCTION_EXECUTE_3[6:0] == OP_I_TYPE_64 || INSTRUCTION_EXECUTE_3[6:0] == OP_I_TYPE_JUMP) // Immediate TYPE_PIPELINE[MEMORY] <= TYPE_IMMEDIATE; else if (INSTRUCTION_EXECUTE_3[6:0] == OP_B_TYPE[6:0]) // Branch TYPE_PIPELINE[MEMORY] <= TYPE_BRANCH; R1_PIPELINE[MEMORY] <= INSTRUCTION_EXECUTE_3[19:15]; R2_PIPELINE[MEMORY] <= INSTRUCTION_EXECUTE_3[24:20]; RD_PIPELINE[MEMORY] <= INSTRUCTION_EXECUTE_3[11:7]; end // -- 4. Stage: Memory reg [9:0] PC_MEMORY_4 = 0; reg [31:0] INSTRUCTION_MEMORY_4 = 0; reg [63:0] ALU_OUT_MEMORY_4 = 0; always @(posedge CLK) begin INSTRUCTION_MEMORY_4 <= INSTRUCTION_EXECUTE_3; PC_MEMORY_4 <= PC_EXECUTE_3; ALU_OUT_MEMORY_4 <= ALU_OUT; RAM_WRITE_DATA <= R2_DATA; if (INSTRUCTION_MEMORY_4[6:0] == OP_R_TYPE || INSTRUCTION_MEMORY_4[6:0] == OP_R_TYPE_64) // R-Type TYPE_PIPELINE[WRITEBACK] <= TYPE_REGISTER; else if (INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_LOAD) // Load TYPE_PIPELINE[WRITEBACK] <= TYPE_LOAD; else if (INSTRUCTION_MEMORY_4[6:0] == OP_S_TYPE) // Store TYPE_PIPELINE[WRITEBACK] <= TYPE_STORE; else if (INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_OTHER || INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_64 || INSTRUCTION_MEMORY_4[6:0] == OP_I_TYPE_JUMP) // Immediate TYPE_PIPELINE[WRITEBACK] <= TYPE_IMMEDIATE; else if (INSTRUCTION_MEMORY_4[6:0] == OP_B_TYPE[6:0]) // Branch TYPE_PIPELINE[WRITEBACK] <= TYPE_BRANCH; R1_PIPELINE[WRITEBACK] <= INSTRUCTION_MEMORY_4[19:15]; R2_PIPELINE[WRITEBACK] <= INSTRUCTION_MEMORY_4[24:20]; RD_PIPELINE[WRITEBACK] <= INSTRUCTION_MEMORY_4[11:7]; end // -- 5. Stage: WriteBack reg [31:0] INSTRUCTION_WRITEBACK_5 = 0; reg [63:0] REG_WRITE_DATA_WRITEBACK_5 = 0; reg [63:0] RAM_READ_DATA_WRITEBACK_5 = 0; always @(posedge CLK) begin INSTRUCTION_WRITEBACK_5 <= INSTRUCTION_MEMORY_4; RAM_READ_DATA_WRITEBACK_5 <= RAM_READ_DATA; //REG_WRITE_DATA_WRITEBACK_5 <= ALU_OUT_MEMORY_4; case (REG_WRITEBACK_SELECTION) 1: REG_WRITE_DATA_WRITEBACK_5 <= ALU_OUT_MEMORY_4; 2: REG_WRITE_DATA_WRITEBACK_5 <= PC_MEMORY_4 + 4; endcase end // GTK WAVE trick to show Arrays. NOT NECESSARY: generate genvar idx; for(idx = 0; idx < 4; idx = idx+1) begin: PIPELINE wire [4:0] R1 = R1_PIPELINE[idx]; wire [4:0] R2 = R2_PIPELINE[idx]; wire [4:0] RD = RD_PIPELINE[idx]; wire [2:0] TYPE = TYPE_PIPELINE[idx]; end endgenerate endmodule ================================================ FILE: src/Encoders.v ================================================ module Encoder_4 ( input [3:0] in, output reg [1:0] out ); initial begin out = 0; end always @(in) begin casex (in) 4'b1xxx : out = 3; 4'b01xx : out = 2; 4'b001x : out = 1; 4'b0001 : out = 0; 4'b0000 : out = 0; default: out = 0; endcase end endmodule module Encoder_8 ( input [7:0] in, output reg [2:0] out ); initial begin out = 0; end always @(in) begin casex (in) 8'b1xxxxxxx : out = 7; 8'b01xxxxxx : out = 6; 8'b001xxxxx : out = 5; 8'b0001xxxx : out = 4; 8'b00001xxx : out = 3; 8'b000001xx : out = 2; 8'b0000001x : out = 1; 8'b00000001 : out = 0; 8'b00000000 : out = 0; default: out = 0; endcase end endmodule module Encoder_16 ( input [15:0] in, output reg [3:0] out ); initial begin out = 0; end always @(in) begin casex (in) 16'b1xxxxxxxxxxxxxxx : out = 15; 16'b01xxxxxxxxxxxxxx : out = 14; 16'b001xxxxxxxxxxxxx : out = 13; 16'b0001xxxxxxxxxxxx : out = 12; 16'b00001xxxxxxxxxxx : out = 11; 16'b000001xxxxxxxxxx : out = 10; 16'b0000001xxxxxxxxx : out = 9; 16'b00000001xxxxxxxx : out = 8; 16'b000000001xxxxxxx : out = 7; 16'b0000000001xxxxxx : out = 6; 16'b00000000001xxxxx : out = 5; 16'b000000000001xxxx : out = 4; 16'b0000000000001xxx : out = 3; 16'b00000000000001xx : out = 2; 16'b000000000000001x : out = 1; 16'b0000000000000001 : out = 0; 16'b0000000000000000 : out = 0; default: out = 0; endcase end endmodule ================================================ FILE: src/ImmediateExtractor.v ================================================ module ImmediateExtractor( input [31:0] INSTRUCTION, input [2:0] SELECTION, output reg signed [63:0] VALUE ); wire [11:0] IMM_11_0 = INSTRUCTION[31:20]; wire [19:0] IMM_31_12 = INSTRUCTION[31:12]; wire [4:0] IMM_4_0 = INSTRUCTION[11:7]; wire [6:0] IMM_11_5 = INSTRUCTION[31:25]; wire IMM_11_B = INSTRUCTION[7]; wire [3:0] IMM_4_1 = INSTRUCTION[11:8]; wire [5:0] IMM_10_5 = INSTRUCTION[30:25]; wire IMM_12 = INSTRUCTION[31]; wire [7:0] IMM_19_12 = INSTRUCTION[19:12]; wire IMM_11_J = INSTRUCTION[20]; wire [9:0] IMM_10_1 = INSTRUCTION[30:21]; wire IMM_20 = INSTRUCTION[31]; // Extend bits and get immediate values of types. wire signed [63:0] Imm_I = { {64{IMM_11_0[11]}}, IMM_11_0 }; wire signed [63:0] Imm_U = { {64{IMM_31_12[19]}}, IMM_31_12, 12'h000 }; wire signed [63:0] Imm_B = { {64{IMM_12}}, IMM_11_B, IMM_10_5, IMM_4_1, 1'b0 }; wire signed [63:0] Imm_S = { {64{IMM_11_5[6]}}, IMM_11_5, IMM_4_0 }; wire signed [63:0] Imm_UJ = { {64{IMM_20}}, IMM_19_12, IMM_11_J, IMM_10_1, 1'b0 }; always @(*) begin case (SELECTION) 1: VALUE = Imm_I; 2: VALUE = Imm_U; 3: VALUE = Imm_S; 4: VALUE = Imm_B; 5: VALUE = Imm_UJ; default : VALUE = 0; endcase end endmodule ================================================ FILE: src/RAM.v ================================================ module RAM( input [9:0] ADDRESS, input [63:0] DATA_IN, input WRITE_ENABLE, input CLK, output [63:0] DATA_OUT ); reg [63:0] memory [1023:0]; initial begin for(int i=0; i<1024; i=i+1) begin memory[i] <= 0; end end assign DATA_OUT = memory[ADDRESS]; always @(posedge CLK) begin if (WRITE_ENABLE) memory[ADDRESS] <= DATA_IN; end endmodule ================================================ FILE: src/ROM.v ================================================ module ROM( input [9:0] ADDRESS, output [31:0] DATA ); reg [31:0] memory [1023:0]; // 10-bit address. 32-bit cell size. assign DATA = memory[ADDRESS]; initial begin // Example program: memory[0] = 32'h00000013; // nop (add x0 x0 0) // start: memory[1] = 32'h00100093; // addi x1 x0 1 memory[2] = 32'h00100313; // addi x6 x0 1 memory[3] = 32'h00400613; // addi x12 x0 4 memory[4] = 32'h0060A023; // sw x6 0(x1) x6 R2 Dep (WB) // loop: memory[5] = 32'h0000A303; // lw x6 0(x1) memory[6] = 32'h00130313; // addi x6 x6 1 LoadStall and x6 R1 Dep (WB) memory[7] = 32'h0060A023; // sw x6 0(x1) x6 R2 Dep memory[8] = 32'hFEC34AE3; // blt x6 x12 -12 x6 R1 Dep (WB) // data_dep_test: memory[9] = 32'h03700413; // addi x8 x0 55 memory[10] = 32'h00800433; // add x8 x0 x8 x8 R2 Dep memory[11] = 32'h00140413; // addi x8 x8 1 x8 R1 Dep // finish: memory[12] = 32'h00000013; // nop (add x0 x0 0) end endmodule ================================================ FILE: src/RegFile.v ================================================ module RegFile( input [4:0]R1, input [4:0]R2, input [4:0]RD, input [63:0]RD_DATA, input WRITE_ENABLE, output [63:0]R1_DATA, output [63:0]R2_DATA ); reg [63:0] REGISTERS[31:0]; // 64 Bit length, 32 Registers integer i = 0; initial begin for (i = 0; i< 32 ; i = i + 1) begin REGISTERS[i] <= 0; end end assign R1_DATA = REGISTERS[R1]; assign R2_DATA = REGISTERS[R2]; always @(*) begin if (WRITE_ENABLE == 1 && RD != 0) REGISTERS[RD] <= RD_DATA; end // GTK WAVE trick to show Arrays. NOT NECESSARY: generate genvar idx; for(idx = 1; idx < 31; idx = idx+1) begin: REG_DATAS wire [63:0] R_DATA = REGISTERS[idx]; end endgenerate endmodule ================================================ FILE: testbench/run_main_test.sh ================================================ #!/bin/bash if [ ! -d "./output" ]; then mkdir output; fi echo "== Main Test =============" && iverilog -g2005-sv -I ../src/ -o output/tb_main tb_Main.v && vvp output/tb_main && echo "DONE!" || echo "An error occured!"; ================================================ FILE: testbench/run_tests.sh ================================================ #!/bin/bash if [ ! -d "./output" ]; then mkdir output; fi echo "== Encoders Test ========================" && iverilog -g2005-sv -I ../src/ -o output/tb_encoders tb_Encoders.v && vvp output/tb_encoders && echo "== ALU Test ============================" && iverilog -g2005-sv -I ../src/ -o output/tb_alu tb_ALU.v && vvp output/tb_alu && echo "== RegFile Test=========================" && iverilog -g2005-sv -I ../src/ -o output/tb_regfile tb_RegFile.v && vvp output/tb_regfile && echo "== ImmediateExtractor Test =============" && iverilog -g2005-sv -I ../src/ -o output/tb_immediateextractor tb_ImmediateExtractor.v && vvp output/tb_immediateextractor && echo "== RAM Test ============================" && iverilog -g2005-sv -I ../src/ -o output/tb_ram tb_RAM.v && vvp output/tb_ram && echo "== ROM Test ============================" && iverilog -g2005-sv -I ../src/ -o output/tb_rom tb_ROM.v && vvp output/tb_rom && echo "========================================" && echo "Test finished." || echo "ERROR: One of the modules has been failed to compile!"; ================================================ FILE: testbench/tb_ALU.v ================================================ `include "ALU.v" `timescale 1ns / 100ps module tb_ALU; reg [63:0] a; reg [63:0] b; reg [3:0] op; wire [63:0] result; wire isEqual; ALU alu(a, b, op, result, isEqual); initial begin // add a = 5; b = 5; op = 0; #20; // sub a = 66; b = 11; op = 1; #20; // and a = 3'b101; b = 3'b110; op = 2; #20; // or a = 3'b101; b = 3'b110; op = 3; #20; // xor a = 3'b110; b = 3'b010; op = 4; #20; // sll (Shift Left Logical) a = 1; b = 3; op = 5; #20; // srl (Shift Right Logical) a = 8; b = 2; op = 6; #20; // sra (Shift Right Arithmetic) a = -8; b = 2; op = 7; #20; // mul a = 6; b = 5; op = 8; #20; // mulh a = 64'h8000000000000000; b = 4; op = 9; #20; // output will be ...0010 = 2 // div a = 66; b = 11; op = 10; #20; // rem a = 62; b = 3; op = 11; #20; // slt (Set Less Than) a = -1; b = 9; op = 12; #20; // sltu (Set Less Than Unsigned) a = -1; b = 9; op = 13; #20; end initial begin $dumpfile("vcd/alu.vcd"); $dumpvars(0, tb_ALU); end endmodule ================================================ FILE: testbench/tb_Encoders.v ================================================ `include "Encoders.v" `timescale 1ns / 100ps module tb_Encoders; reg [15:0] in = 0; reg [3:0] out4; reg [2:0] out3; reg [1:0] out2; Encoder_16 enc(in, out4); Encoder_8 enc8(in[7:0], out3); Encoder_4 enc4(in[3:0], out2); initial begin in = 16'b0000000000000000; #20; in = 16'b0000000000000001; #20; in = 16'b0000000000000010; #20; in = 16'b0000000000000100; #20; in = 16'b0000000000001000; #20; in = 16'b0000000000010000; #20; in = 16'b0000000000100000; #20; in = 16'b0000000001000000; #20; in = 16'b0000000010000000; #20; in = 16'b0000000100000000; #20; in = 16'b0000001000000000; #20; in = 16'b0000010000000000; #20; in = 16'b0000100000000000; #20; in = 16'b0001000000000000; #20; in = 16'b0010000000000000; #20; in = 16'b0100000000000000; #20; in = 16'b1000000000000000; #20; in = 16'b1000000000000001; #20; in = 16'b0000000100000001; #20; in = 16'b0000000000000011; #20; in = 16'b0000000000000000; #20; end initial begin $dumpfile("vcd/encoders.vcd"); $dumpvars(0, tb_Encoders); end endmodule ================================================ FILE: testbench/tb_ImmediateExtractor.v ================================================ `include "ImmediateExtractor.v" `timescale 1ns / 100ps module tb_ImmediateExtractor; reg [31:0] INSTRUCTION; reg [2:0] SELECTION; reg signed [63:0] VALUE; ImmediateExtractor ie(INSTRUCTION, SELECTION, VALUE); initial begin INSTRUCTION = 32'h00A00613; // addi x12 x0 10 // Expects: 10 SELECTION = 1; // I Type #20; INSTRUCTION = 32'h00001337; // lui x6 1 // Expects: 4096 SELECTION = 2; // U Type #20; INSTRUCTION = 32'h00B323A3; // sw x11 7(x6) // Expects: 7 SELECTION = 3; // S Type #20; INSTRUCTION = 32'hFEC5CAE3; // blt x11 x12 -12 // Expects: -12 SELECTION = 4; // B Type #20; INSTRUCTION = 32'h4000006F; // jal x0 1024 // Expects: 1024 SELECTION = 5; // UJ Type #20; end initial begin $dumpfile("vcd/immediateextractor.vcd"); $dumpvars(0, tb_ImmediateExtractor); end endmodule ================================================ FILE: testbench/tb_Main.v ================================================ `include "CPU.v" `include "RAM.v" `include "ROM.v" `timescale 1ns / 100ps module tb_Main; wire [9:0] RAM_ADDR; wire [63:0] RAM_READ_DATA; wire [63:0] RAM_WRITE_DATA; wire RAM_WRITE_ENABLE; wire [9:0] INSTRUCTION_ADDR; wire [31:0] INSTRUCTION; reg CLK = 1; CPU cpu( .RAM_READ_DATA(RAM_READ_DATA), .INSTRUCTION(INSTRUCTION), .CLK(CLK), .RAM_ADDR(RAM_ADDR), .RAM_WRITE_DATA(RAM_WRITE_DATA), .RAM_WRITE_ENABLE(RAM_WRITE_ENABLE), .INSTRUCTION_ADDR(INSTRUCTION_ADDR) ); ROM rom( .ADDRESS(INSTRUCTION_ADDR), .DATA(INSTRUCTION) ); RAM ram( .ADDRESS(RAM_ADDR), .DATA_IN(RAM_WRITE_DATA), .WRITE_ENABLE(RAM_WRITE_ENABLE), .CLK(CLK), .DATA_OUT(RAM_READ_DATA) ); initial begin for(int i=0; i<40; i=i+1) begin CLK=1; #20; CLK=0; #20; end end initial begin $dumpfile("vcd/main.vcd"); $dumpvars(0, tb_Main); end endmodule ================================================ FILE: testbench/tb_RAM.v ================================================ `include "RAM.v" `timescale 1ns / 100ps module tb_RAM; reg [9:0] ADDRESS; reg [63:0] DATA_IN; reg WRITE_ENABLE; reg CLK; reg [63:0] DATA_OUT; RAM ram(ADDRESS, DATA_IN, WRITE_ENABLE, CLK, DATA_OUT); initial begin // Write #1 ADDRESS = 1; DATA_IN = 55; WRITE_ENABLE = 1; CLK = 1; #20; CLK = 0; #20; // Write #2 ADDRESS = 2; DATA_IN = 99; WRITE_ENABLE = 1; CLK = 1; #20; CLK = 0; #20; // Read #1 ADDRESS = 1; WRITE_ENABLE = 0; DATA_IN = 0; CLK = 1; #20; CLK = 0; #20; // Read #2 ADDRESS = 2; WRITE_ENABLE = 0; DATA_IN = 0; CLK = 1; #20; CLK = 0; #20; end initial begin $dumpfile("vcd/ram.vcd"); $dumpvars(0, tb_RAM); end endmodule ================================================ FILE: testbench/tb_ROM.v ================================================ `include "ROM.v" `timescale 1ns / 100ps module tb_ROM; reg [9:0] ADDRESS; reg [31:0] DATA_OUT; ROM rom(ADDRESS, DATA_OUT); initial begin ADDRESS = 0; #20; ADDRESS = 1; #20; ADDRESS = 2; #20; ADDRESS = 3; #20; ADDRESS = 4; #20; ADDRESS = 5; #20; ADDRESS = 20; #20; end initial begin $dumpfile("vcd/rom.vcd"); $dumpvars(0, tb_ROM); end endmodule ================================================ FILE: testbench/tb_RegFile.v ================================================ `include "RegFile.v" `timescale 1ns / 100ps module tb_RegFile; reg [4:0]R1; reg [4:0]R2; reg [4:0]RD; reg [63:0]RD_DATA; reg reg_write_enable; wire [63:0]R1_data; wire [63:0]R2_data; RegFile regfile(R1, R2, RD, RD_DATA, reg_write_enable, R1_data, R2_data ); initial begin R1 = 0; R2 = 0; RD = 0; RD_DATA = 0; reg_write_enable = 0; #20; R1 = 0; R2 = 0; RD = 1; RD_DATA = 5; reg_write_enable = 1; #20; R1 = 1; R2 = 0; RD = 2; RD_DATA = 10; reg_write_enable = 1; #20; R1 = 1; R2 = 2; RD = 0; RD_DATA = 0; reg_write_enable = 0; #20; end initial begin $dumpfile("vcd/regfile.vcd"); $dumpvars(0, tb_RegFile); end endmodule ================================================ FILE: testbench/vcd/alu.vcd ================================================ $date Tue May 25 21:18:16 2021 $end $version Icarus Verilog $end $timescale 100ps $end $scope module tb_ALU $end $var wire 64 ! result [63:0] $end $var wire 1 " isEqual $end $var reg 64 # a [63:0] $end $var reg 64 $ b [63:0] $end $var reg 4 % op [3:0] $end $scope module alu $end $var wire 4 & OP [3:0] $end $var wire 64 ' X [63:0] $end $var wire 64 ( X_signed [63:0] $end $var wire 64 ) Y [63:0] $end $var wire 64 * Y_signed [63:0] $end $var wire 1 " isEqual $end $var wire 64 + OUTPUT [63:0] $end $var reg 64 , RESULT [63:0] $end $var reg 128 - RESULT_MULH [127:0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars bx - b1010 , b1010 + b101 * b101 ) b101 ( b101 ' b0 & b0 % b101 $ b101 # 1" b1010 ! $end #200 b110111 ! b110111 + b110111 , b1 % b1 & b1011 * b1011 $ b1011 ) b1000010 ( 0" b1000010 # b1000010 ' #400 b100 ! b100 + b100 , b10 % b10 & b110 * b110 $ b110 ) b101 ( b101 # b101 ' #600 b111 ! b111 + b111 , b11 % b11 & #800 b100 ! b100 + b100 , b100 % b100 & b10 * b10 $ b10 ) b110 ( 0" b110 # b110 ' #1000 b1000 ! b1000 + b1000 , b101 % b101 & b11 * b11 $ b11 ) b1 ( b1 # b1 ' #1200 b10 ! b10 + b10 , b110 % b110 & b10 * b10 $ b10 ) b1000 ( b1000 # b1000 ' #1400 b1111111111111111111111111111111111111111111111111111111111111110 ! b1111111111111111111111111111111111111111111111111111111111111110 + b1111111111111111111111111111111111111111111111111111111111111110 , b111 % b111 & b1111111111111111111111111111111111111111111111111111111111111000 ( b1111111111111111111111111111111111111111111111111111111111111000 # b1111111111111111111111111111111111111111111111111111111111111000 ' #1600 b11110 ! b11110 + b11110 , b1000 % b1000 & b101 * b101 $ b101 ) b110 ( b110 # b110 ' #1800 b100000000000000000000000000000000000000000000000000000000000000000 - b10 ! b10 + b1001 % b1001 & b100 * b100 $ b100 ) b1000000000000000000000000000000000000000000000000000000000000000 ( b1000000000000000000000000000000000000000000000000000000000000000 # b1000000000000000000000000000000000000000000000000000000000000000 ' #2000 b110 , b110 ! b110 + b1010 % b1010 & b1011 * b1011 $ b1011 ) b1000010 ( b1000010 # b1000010 ' #2200 b10 ! b10 + b10 , b1011 % b1011 & b11 * b11 $ b11 ) b111110 ( b111110 # b111110 ' #2400 b1 ! b1 + b1 , b1100 % b1100 & b1001 * b1001 $ b1001 ) b1111111111111111111111111111111111111111111111111111111111111111 ( b1111111111111111111111111111111111111111111111111111111111111111 # b1111111111111111111111111111111111111111111111111111111111111111 ' #2600 b0 ! b0 + b0 , b1101 % b1101 & #2800 ================================================ FILE: testbench/vcd/encoders.vcd ================================================ $date Mon May 24 15:33:45 2021 $end $version Icarus Verilog $end $timescale 100ps $end $scope module tb_Encoders $end $var wire 4 ! out4 [3:0] $end $var wire 3 " out3 [2:0] $end $var wire 2 # out2 [1:0] $end $var reg 16 $ in [15:0] $end $scope module enc $end $var wire 16 % in [15:0] $end $var reg 4 & out [3:0] $end $upscope $end $scope module enc4 $end $var wire 4 ' in [3:0] $end $var reg 2 ( out [1:0] $end $upscope $end $scope module enc8 $end $var wire 8 ) in [7:0] $end $var reg 3 * out [2:0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b0 * b0 ) b0 ( b0 ' b0 & b0 % b0 $ b0 # b0 " b0 ! $end #200 b1 ) b1 ' b1 $ b1 % #400 b1 " b1 * b1 # b1 ( b10 ) b10 ' b1 ! b1 & b10 $ b10 % #600 b10 " b10 * b10 # b10 ( b100 ) b100 ' b10 ! b10 & b100 $ b100 % #800 b11 " b11 * b11 # b11 ( b1000 ) b1000 ' b11 ! b11 & b1000 $ b1000 % #1000 b100 " b100 * b0 # b0 ( b10000 ) b0 ' b100 ! b100 & b10000 $ b10000 % #1200 b101 " b101 * b100000 ) b101 ! b101 & b100000 $ b100000 % #1400 b110 " b110 * b1000000 ) b110 ! b110 & b1000000 $ b1000000 % #1600 b111 " b111 * b10000000 ) b111 ! b111 & b10000000 $ b10000000 % #1800 b0 " b0 * b0 ) b1000 ! b1000 & b100000000 $ b100000000 % #2000 b1001 ! b1001 & b1000000000 $ b1000000000 % #2200 b1010 ! b1010 & b10000000000 $ b10000000000 % #2400 b1011 ! b1011 & b100000000000 $ b100000000000 % #2600 b1100 ! b1100 & b1000000000000 $ b1000000000000 % #2800 b1101 ! b1101 & b10000000000000 $ b10000000000000 % #3000 b1110 ! b1110 & b100000000000000 $ b100000000000000 % #3200 b1111 ! b1111 & b1000000000000000 $ b1000000000000000 % #3400 b1 ) b1 ' b1000000000000001 $ b1000000000000001 % #3600 b1000 ! b1000 & b100000001 $ b100000001 % #3800 b1 " b1 * b1 # b1 ( b11 ) b11 ' b1 ! b1 & b11 $ b11 % #4000 b0 " b0 * b0 # b0 ( b0 ) b0 ' b0 ! b0 & b0 $ b0 % #4200 ================================================ FILE: testbench/vcd/immediateextractor.vcd ================================================ $date Mon May 24 15:33:45 2021 $end $version Icarus Verilog $end $timescale 100ps $end $scope module tb_ImmediateExtractor $end $var wire 64 ! VALUE [63:0] $end $var reg 32 " INSTRUCTION [31:0] $end $var reg 3 # SELECTION [2:0] $end $scope module ie $end $var wire 32 $ INSTRUCTION [31:0] $end $var wire 3 % SELECTION [2:0] $end $var wire 64 & Imm_UJ [63:0] $end $var wire 64 ' Imm_U [63:0] $end $var wire 64 ( Imm_S [63:0] $end $var wire 64 ) Imm_I [63:0] $end $var wire 64 * Imm_B [63:0] $end $var wire 4 + IMM_4_1 [3:0] $end $var wire 5 , IMM_4_0 [4:0] $end $var wire 20 - IMM_31_12 [19:0] $end $var wire 1 . IMM_20 $end $var wire 8 / IMM_19_12 [7:0] $end $var wire 1 0 IMM_12 $end $var wire 1 1 IMM_11_J $end $var wire 1 2 IMM_11_B $end $var wire 7 3 IMM_11_5 [6:0] $end $var wire 12 4 IMM_11_0 [11:0] $end $var wire 6 5 IMM_10_5 [5:0] $end $var wire 10 6 IMM_10_1 [9:0] $end $var reg 64 7 VALUE [63:0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b1010 7 b101 6 b0 5 b1010 4 b0 3 02 01 00 b0 / 0. b101000000000 - b1100 , b110 + b1100 * b1010 ) b1100 ( b101000000000000000000000 ' b1010 & b1 % b101000000000011000010011 $ b1 # b101000000000011000010011 " b1010 ! $end #200 b0 ) b1000000000000 ' b110 ( b110 * b1000000000000 & b1000000000000 ! b1000000000000 7 b0 4 b1 - b110 , b11 + b1 / b0 6 b10 # b10 % b1001100110111 " b1001100110111 $ #400 b1011 ) b101100110010000000000000 ' b111 ( b100000000110 * b110010100000001010 & b111 ! b111 7 b1011 4 b101100110010 - b111 , 12 b110010 / 11 b101 6 b11 # b11 % b101100110010001110100011 " b101100110010001110100011 $ #600 b1111111111111111111111111111111111111111111111111111111111101100 ) b1111111111111111111111111111111111111110110001011100000000000000 ' b1111111111111111111111111111111111111111111111111111111111110101 ( b1111111111111111111111111111111111111111111111111111111111110100 * b1111111111111111111111111111111111111111111101011100011111101100 & b1111111111111111111111111111111111111111111111111111111111110100 ! b1111111111111111111111111111111111111111111111111111111111110100 7 b111111101100 4 b11111110110001011100 - b10101 , b1111111 3 b1010 + b111111 5 10 b1011100 / 01 b1111110110 6 1. b100 # b100 % b11111110110001011100101011100011 " b11111110110001011100101011100011 $ #800 b10000000000 ) b1000000000000000000000000000000 ' b10000000000 ( b10000000000 * b10000000000 & b10000000000 ! b10000000000 7 b10000000000 4 b1000000000000000000 - b0 , b100000 3 02 b0 + b100000 5 00 b0 / b1000000000 6 0. b101 # b101 % b1000000000000000000000001101111 " b1000000000000000000000001101111 $ #1000 ================================================ FILE: testbench/vcd/main.vcd ================================================ $date Mon May 24 15:34:03 2021 $end $version Icarus Verilog $end $timescale 100ps $end $scope module tb_Main $end $var wire 1 ! RAM_WRITE_ENABLE $end $var wire 64 " RAM_WRITE_DATA [63:0] $end $var wire 64 # RAM_READ_DATA [63:0] $end $var wire 10 $ RAM_ADDR [9:0] $end $var wire 10 % INSTRUCTION_ADDR [9:0] $end $var wire 32 & INSTRUCTION [31:0] $end $var reg 1 ' CLK $end $scope module cpu $end $var wire 1 ( B_beq $end $var wire 1 ) B_bge $end $var wire 1 * B_bgeu $end $var wire 1 + B_blt $end $var wire 1 , B_bltu $end $var wire 1 - B_bne $end $var wire 1 ' CLK $end $var wire 1 . CONTROL_HAZARD_STALL $end $var wire 1 / DATA_DEPENDENCY_HAZARD_R1 $end $var wire 1 0 DATA_DEPENDENCY_HAZARD_R1_WRITEBACK $end $var wire 1 1 DATA_DEPENDENCY_HAZARD_R2 $end $var wire 1 2 DATA_DEPENDENCY_HAZARD_R2_WRITEBACK $end $var wire 1 3 I_TYPE $end $var wire 1 4 I_addi $end $var wire 1 5 I_addiw $end $var wire 1 6 I_andi $end $var wire 1 7 I_jalr $end $var wire 1 8 I_lb $end $var wire 1 9 I_ld $end $var wire 1 : I_lh $end $var wire 1 ; I_lw $end $var wire 1 < I_ori $end $var wire 1 = I_slli $end $var wire 1 > I_slliw $end $var wire 1 ? I_slti $end $var wire 1 @ I_sltiu $end $var wire 1 A I_srai $end $var wire 1 B I_sraiw $end $var wire 1 C I_srli $end $var wire 1 D I_srliw $end $var wire 1 E I_xori $end $var wire 1 F LOAD_STALL $end $var wire 1 G PC_ALU_SEL $end $var wire 64 H R1_DATA_UNSIGNED [63:0] $end $var wire 64 I R2_DATA_UNSIGNED [63:0] $end $var wire 1 J REG_WRITE_ENABLE $end $var wire 1 K R_add $end $var wire 1 L R_addw $end $var wire 1 M R_and $end $var wire 1 N R_div $end $var wire 1 O R_divw $end $var wire 1 P R_mul $end $var wire 1 Q R_mulh $end $var wire 1 R R_mulw $end $var wire 1 S R_or $end $var wire 1 T R_rem $end $var wire 1 U R_remw $end $var wire 1 V R_sll $end $var wire 1 W R_sllw $end $var wire 1 X R_slt $end $var wire 1 Y R_sltu $end $var wire 1 Z R_sra $end $var wire 1 [ R_sraw $end $var wire 1 \ R_srl $end $var wire 1 ] R_srlw $end $var wire 1 ^ R_sub $end $var wire 1 _ R_subw $end $var wire 1 ` R_xor $end $var wire 1 a S_sb $end $var wire 1 b S_sd $end $var wire 1 c S_sh $end $var wire 1 d S_sw $end $var wire 1 e U_TYPE $end $var wire 1 f U_auipc $end $var wire 1 g U_jal $end $var wire 1 h U_lui $end $var wire 1 i WB_I_TYPE $end $var wire 1 j WB_U_TYPE $end $var wire 4 k regWritebackSelectionInputs [3:0] $end $var wire 1 l isALUEqual $end $var wire 8 m immediateSelectionInputs [7:0] $end $var wire 4 n aluX2SelectionInputs [3:0] $end $var wire 4 o aluX1SelectionInputs [3:0] $end $var wire 16 p aluOpEncoderInputs [15:0] $end $var wire 1 q WB_U_TYPE_LOAD $end $var wire 1 r WB_U_TYPE_JUMP $end $var wire 1 s WB_U_TYPE_AUIPC $end $var wire 1 t WB_R_TYPE_64 $end $var wire 1 u WB_R_TYPE $end $var wire 1 v WB_I_TYPE_OTHER $end $var wire 1 w WB_I_TYPE_LOAD $end $var wire 1 x WB_I_TYPE_JUMP $end $var wire 1 y WB_I_TYPE_64 $end $var wire 1 z U_TYPE_LOAD $end $var wire 1 { U_TYPE_JUMP $end $var wire 1 | U_TYPE_AUIPC $end $var wire 1 } S_TYPE $end $var wire 1 ~ R_TYPE_64 $end $var wire 1 !" R_TYPE $end $var wire 64 "" REG_WRITE_DATA [63:0] $end $var wire 2 #" REG_WRITEBACK_SELECTION [1:0] $end $var wire 5 $" RD [4:0] $end $var wire 1 ! RAM_WRITE_ENABLE $end $var wire 64 %" RAM_READ_DATA [63:0] $end $var wire 10 &" RAM_ADDR [9:0] $end $var wire 64 '" R2_DATA_EXECUTE_3 [63:0] $end $var wire 64 (" R2_DATA [63:0] $end $var wire 5 )" R2 [4:0] $end $var wire 64 *" R1_DATA_EXECUTE_3 [63:0] $end $var wire 64 +" R1_DATA [63:0] $end $var wire 5 ," R1 [4:0] $end $var wire 7 -" OPCODE_WRITEBACK_5 [6:0] $end $var wire 7 ." OPCODE [6:0] $end $var wire 1 /" I_TYPE_OTHER $end $var wire 1 0" I_TYPE_LOAD $end $var wire 1 1" I_TYPE_JUMP $end $var wire 1 2" I_TYPE_64 $end $var wire 10 3" INSTRUCTION_ADDR [9:0] $end $var wire 32 4" INSTRUCTION [31:0] $end $var wire 64 5" IMMEDIATE_VALUE [63:0] $end $var wire 3 6" IMMEDIATE_SELECTION [2:0] $end $var wire 7 7" FUNCT7 [6:0] $end $var wire 3 8" FUNCT3 [2:0] $end $var wire 1 9" B_TYPE $end $var wire 2 :" ALU_X2_SEL [1:0] $end $var wire 2 ;" ALU_X1_SEL [1:0] $end $var wire 64 <" ALU_OUT [63:0] $end $var wire 4 =" ALU_OP [3:0] $end $var reg 64 >" ALU_OUT_MEMORY_4 [63:0] $end $var reg 64 ?" ALU_X1 [63:0] $end $var reg 64 @" ALU_X2 [63:0] $end $var reg 32 A" INSTRUCTION_DECODE_2 [31:0] $end $var reg 32 B" INSTRUCTION_EXECUTE_3 [31:0] $end $var reg 32 C" INSTRUCTION_MEMORY_4 [31:0] $end $var reg 32 D" INSTRUCTION_WRITEBACK_5 [31:0] $end $var reg 10 E" PC [9:0] $end $var reg 10 F" PC_DECODE_2 [9:0] $end $var reg 10 G" PC_EXECUTE_3 [9:0] $end $var reg 10 H" PC_MEMORY_4 [9:0] $end $var reg 64 I" RAM_READ_DATA_WRITEBACK_5 [63:0] $end $var reg 64 J" RAM_WRITE_DATA [63:0] $end $var reg 64 K" REG_WRITE_DATA_WRITEBACK_5 [63:0] $end $var integer 32 L" DECODE [31:0] $end $var integer 32 M" EXECUTE [31:0] $end $var integer 32 N" MEMORY [31:0] $end $var integer 32 O" OP_B_TYPE [31:0] $end $var integer 32 P" OP_I_TYPE_64 [31:0] $end $var integer 32 Q" OP_I_TYPE_JUMP [31:0] $end $var integer 32 R" OP_I_TYPE_LOAD [31:0] $end $var integer 32 S" OP_I_TYPE_OTHER [31:0] $end $var integer 32 T" OP_R_TYPE [31:0] $end $var integer 32 U" OP_R_TYPE_64 [31:0] $end $var integer 32 V" OP_S_TYPE [31:0] $end $var integer 32 W" OP_U_TYPE_AUIPC [31:0] $end $var integer 32 X" OP_U_TYPE_JUMP [31:0] $end $var integer 32 Y" OP_U_TYPE_LOAD [31:0] $end $var integer 32 Z" TYPE_BRANCH [31:0] $end $var integer 32 [" TYPE_IMMEDIATE [31:0] $end $var integer 32 \" TYPE_LOAD [31:0] $end $var integer 32 ]" TYPE_REGISTER [31:0] $end $var integer 32 ^" TYPE_STORE [31:0] $end $var integer 32 _" TYPE_UPPERIMMEDIATE [31:0] $end $var integer 32 `" WRITEBACK [31:0] $end $scope begin PIPELINE[0] $end $var wire 5 a" R1 [4:0] $end $var wire 5 b" R2 [4:0] $end $var wire 5 c" RD [4:0] $end $var wire 3 d" TYPE [2:0] $end $upscope $end $scope begin PIPELINE[1] $end $var wire 5 e" R1 [4:0] $end $var wire 5 f" R2 [4:0] $end $var wire 5 g" RD [4:0] $end $var wire 3 h" TYPE [2:0] $end $upscope $end $scope begin PIPELINE[2] $end $var wire 5 i" R1 [4:0] $end $var wire 5 j" R2 [4:0] $end $var wire 5 k" RD [4:0] $end $var wire 3 l" TYPE [2:0] $end $upscope $end $scope begin PIPELINE[3] $end $var wire 5 m" R1 [4:0] $end $var wire 5 n" R2 [4:0] $end $var wire 5 o" RD [4:0] $end $var wire 3 p" TYPE [2:0] $end $upscope $end $scope module alu $end $var wire 64 q" X [63:0] $end $var wire 64 r" X_signed [63:0] $end $var wire 64 s" Y [63:0] $end $var wire 64 t" Y_signed [63:0] $end $var wire 1 l isEqual $end $var wire 4 u" OP [3:0] $end $var reg 64 v" result_reg [63:0] $end $upscope $end $scope module aluOpEncoder $end $var wire 16 w" in [15:0] $end $var reg 4 x" out [3:0] $end $upscope $end $scope module aluX1SelectionEncoder $end $var wire 4 y" in [3:0] $end $var reg 2 z" out [1:0] $end $upscope $end $scope module aluX2SelectionEncoder $end $var wire 4 {" in [3:0] $end $var reg 2 |" out [1:0] $end $upscope $end $scope module immediateExtractor $end $var wire 32 }" INSTRUCTION [31:0] $end $var wire 3 ~" SELECTION [2:0] $end $var wire 64 !# Imm_UJ [63:0] $end $var wire 64 "# Imm_U [63:0] $end $var wire 64 ## Imm_S [63:0] $end $var wire 64 $# Imm_I [63:0] $end $var wire 64 %# Imm_B [63:0] $end $var wire 4 &# IMM_4_1 [3:0] $end $var wire 5 '# IMM_4_0 [4:0] $end $var wire 20 (# IMM_31_12 [19:0] $end $var wire 1 )# IMM_20 $end $var wire 8 *# IMM_19_12 [7:0] $end $var wire 1 +# IMM_12 $end $var wire 1 ,# IMM_11_J $end $var wire 1 -# IMM_11_B $end $var wire 7 .# IMM_11_5 [6:0] $end $var wire 12 /# IMM_11_0 [11:0] $end $var wire 6 0# IMM_10_5 [5:0] $end $var wire 10 1# IMM_10_1 [9:0] $end $var reg 64 2# VALUE [63:0] $end $upscope $end $scope module immediateSelectionEncoder $end $var wire 8 3# in [7:0] $end $var reg 3 4# out [2:0] $end $upscope $end $scope module regFile $end $var wire 5 5# R1 [4:0] $end $var wire 64 6# R1_DATA [63:0] $end $var wire 5 7# R2 [4:0] $end $var wire 64 8# R2_DATA [63:0] $end $var wire 5 9# RD [4:0] $end $var wire 64 :# RD_DATA [63:0] $end $var wire 1 J WRITE_ENABLE $end $var integer 32 ;# i [31:0] $end $scope begin REG_DATAS[1] $end $var wire 64 <# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[2] $end $var wire 64 =# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[3] $end $var wire 64 ># R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[4] $end $var wire 64 ?# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[5] $end $var wire 64 @# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[6] $end $var wire 64 A# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[7] $end $var wire 64 B# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[8] $end $var wire 64 C# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[9] $end $var wire 64 D# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[10] $end $var wire 64 E# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[11] $end $var wire 64 F# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[12] $end $var wire 64 G# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[13] $end $var wire 64 H# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[14] $end $var wire 64 I# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[15] $end $var wire 64 J# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[16] $end $var wire 64 K# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[17] $end $var wire 64 L# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[18] $end $var wire 64 M# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[19] $end $var wire 64 N# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[20] $end $var wire 64 O# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[21] $end $var wire 64 P# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[22] $end $var wire 64 Q# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[23] $end $var wire 64 R# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[24] $end $var wire 64 S# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[25] $end $var wire 64 T# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[26] $end $var wire 64 U# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[27] $end $var wire 64 V# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[28] $end $var wire 64 W# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[29] $end $var wire 64 X# R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[30] $end $var wire 64 Y# R_DATA [63:0] $end $upscope $end $upscope $end $scope module writeBackSelectionEncoder $end $var wire 4 Z# in [3:0] $end $var reg 2 [# out [1:0] $end $upscope $end $upscope $end $scope module ram $end $var wire 10 \# ADDRESS [9:0] $end $var wire 1 ' CLK $end $var wire 64 ]# DATA_IN [63:0] $end $var wire 64 ^# DATA_OUT [63:0] $end $var wire 1 ! WRITE_ENABLE $end $scope begin $ivl_for_loop0 $end $var integer 32 _# i [31:0] $end $upscope $end $upscope $end $scope module rom $end $var wire 10 `# ADDRESS [9:0] $end $var wire 32 a# DATA [31:0] $end $upscope $end $scope begin $ivl_for_loop1 $end $var integer 32 b# i [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b0 b# b10011 a# b0 `# b10000000000 _# b0 ^# bx ]# b0 \# b0 [# b0 Z# b0 Y# b0 X# b0 W# b0 V# b0 U# b0 T# b0 S# b0 R# b0 Q# b0 P# b0 O# b0 N# b0 M# b0 L# b0 K# b0 J# b0 I# b0 H# b0 G# b0 F# b0 E# b0 D# b0 C# b0 B# b0 A# b0 @# b0 ?# b0 ># b0 =# b0 <# b100000 ;# b0 :# b0 9# b0 8# b0 7# b0 6# b0 5# b0 4# b0 3# b0 2# b0 1# b0 0# b0 /# b0 .# 0-# 0,# 0+# b0 *# 0)# b0 (# b0 '# b0 &# b0 %# b0 $# b0 ## b0 "# b0 !# b0 ~" b0 }" b0 |" b1 {" b0 z" b1 y" b0 x" b0 w" b0 v" b0 u" b0 t" b0 s" b0 r" b0 q" bx p" bx o" bx n" bx m" bx l" bx k" bx j" bx i" bx h" bx g" bx f" bx e" bx d" bx c" bx b" bx a" b11 `" b100 _" b10 ^" b0 ]" b1 \" b11 [" b101 Z" b110111 Y" b1100111 X" b10111 W" b100011 V" b111011 U" b110011 T" b10011 S" b11 R" b1101111 Q" b11011 P" b1100011 O" b10 N" b1 M" b0 L" b0 K" bx J" b0 I" b0 H" b0 G" b0 F" b0 E" b0 D" b0 C" b0 B" b0 A" b0 @" b0 ?" b0 >" b0 =" b0 <" b0 ;" b0 :" 09" b0 8" b0 7" b0 6" b0 5" b10011 4" b0 3" 02" 01" 00" 0/" b0 ." b0 -" b0 ," b0 +" b0 *" b0 )" b0 (" b0 '" b0 &" b0 %" b0 $" b0 #" b0 "" 0!" 0~ 0} 0| 0{ 0z 0y 0x 0w 0v 0u 0t 0s 0r 0q b0 p b1 o b1 n b0 m 1l b0 k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P 0O 0N 0M 0L 0K 0J b0 I b0 H 0G xF 0E 0D 0C 0B 0A 0@ 0? 0> 0= 0< 0; 0: 09 08 07 06 05 04 03 x2 x1 x0 x/ 0. 0- 0, 0+ 0* 0) 0( 1' b10011 & b0 % b0 $ b0 # bx " 0! $end #200 0' #400 0F 01 02 0/ 00 b100000000000010010011 & b100000000000010010011 4" b100000000000010010011 a# b1 % b1 3" b1 `# b11 d" b0 c" b0 b" b0 a" b100 E" b0 g" b0 f" b0 e" b10011 A" b0 k" b0 j" b0 i" b0 o" b0 n" b0 m" b0 " b0 J" b0 ]# 1' b1 b# #600 0' #800 b1 :" b1 |" b11 n b11 {" b1 p b1 w" b1 6" b1 ~" b1 4# b10 m b10 3# 13 14 1/" b10011 ." b100000000001100010011 & b100000000001100010011 4" b100000000001100010011 a# b10 % b10 3" b10 `# b10011 B" b10011 }" b11 h" b100 F" b100000000000010010011 A" b1 c" b1 b" b1000 E" 1' b10 b# #1000 0' #1200 b1 <" b1 v" b1 t" 0l b1 @" b1 s" b1 5" b1 2# b1 $# b100000000000000000000 "# b1 ## b100000000000 %# b100000000000 !# b10000000000011000010011 & b10000000000011000010011 4" b10000000000011000010011 a# b11 % b11 3" b11 `# b1 )" b1 7# b1 /# b100000000 (# b1 '# 1-# 1,# b110 c" b1100 E" b1 g" b1 f" b1000 F" b100000000001100010011 A" b11 l" b100000000000010010011 B" b100000000000010010011 }" b100 G" b10011 C" 1' b11 b# #1400 0' #1600 1J b1 #" b1 [# b10 k b10 Z# 1i b110 ## b110 %# 1v b10011 -" b1 $ b1 &" b1 \# b110 '# 0-# b11 &# b11000001010000000100011 & b11000001010000000100011 4" b11000001010000000100011 a# b100 % b100 3" b100 `# b10011 D" b11 p" b1 >" b100 H" b100000000000010010011 C" b1 k" b1 j" b100000000001100010011 B" b100000000001100010011 }" b1000 G" b110 g" b1100 F" b10000000000011000010011 A" b1100 c" b100 b" b10000 E" 1' b100 b# #1800 0' #2000 b100 <" b100 v" b100 t" b100 @" b100 s" b1 <# b100 5" b100 2# b100 $# b10000000000000000000000 "# b1100 ## b1100 %# b100 !# b1010001100000011 & b1010001100000011 4" b1010001100000011 a# b101 % b101 3" b101 `# b100 )" b100 7# b100 /# b10000000000 (# b1100 '# b110 &# 0,# b10 1# b1 "" b1 :# b1 $" b1 9# b10 d" b0 c" b110 b" b1 a" b10100 E" b1100 g" b100 f" b10000 F" b11000001010000000100011 A" b110 k" b10000000000011000010011 B" b10000000000011000010011 }" b1100 G" b1 o" b1 n" b1000 H" b100000000001100010011 C" b1 K" b100000000000010010011 D" 1' b101 b# #2200 0' #2400 b1 <" b1 v" b0 t" b0 @" b0 s" b1 r" b1 ?" b1 q" b1 '" b1 8# b1 A# b0 p b0 w" b1 I b1 (" 03 b1 H b1 +" b0 5" b0 2# b11 6" b11 ~" b11 4# 04 b110 $# b11000001010000000000000 "# b0 ## b0 %# b1010000000000110 !# b110 $" b110 9# 12 b100 $ b100 &" b100 \# 0/" b1000 m b1000 3# 1} b100011 ." b10 8" b1 *" b1 6# b1 ," b1 5# b110 )" b110 7# b110 /# b11000001010 (# b0 '# b0 &# b1010 *# b11 1# b100110000001100010011 & b100110000001100010011 4" b100110000001100010011 a# b110 % b110 3" b110 `# b100000000001100010011 D" b110 o" b100 >" b1100 H" b10000000000011000010011 C" b1100 k" b100 j" b11000001010000000100011 B" b11000001010000000100011 }" b10000 G" b0 g" b110 f" b1 e" b10 h" b10100 F" b1010001100000011 A" b1 d" b110 c" b0 b" b11000 E" 1' b110 b# #2600 0' #2800 b100 G# b1 :" b1 |" 1F b0 I b0 (" 13 b11 n b11 {" b1 6" b1 ~" b1 4# b0 $# b1010000000000000 "# b110 ## b110 %# b1010000000000000 !# 1d b11000001010000000100011 & b11000001010000000100011 4" b11000001010000000100011 a# b111 % b111 3" b111 `# 01 10" b10 m b10 3# 0} b11 ." b0 '" b0 8# b0 )" b0 7# b0 /# b1010 (# b110 '# b11 &# b0 1# 02 b1 $ b1 &" b1 \# 1! b100 "" b100 :# b1100 $" b1100 9# b11 d" b1 b" b110 a" b11100 E" b110 g" b0 f" b1 h" b11000 F" b100110000001100010011 A" b0 k" b110 j" b1 i" b10 l" b1010001100000011 B" b1010001100000011 }" b10100 G" b1100 o" b100 n" b1 " b1 J" b1 ]# b1 >" b10000 H" b11000001010000000100011 C" b100 K" b10000000000011000010011 D" 1' b111 b# #3000 0' #3200 b0 <" b0 v" b0 r" 1l b0 ?" b0 q" 0J b0 #" b0 [# b1 p b1 w" b0 k b0 Z# 0i b0 H b0 +" 1; 0d 14 b0 "# b0 ## b0 %# b0 !# b1 "" b1 :# b0 $" b0 9# 0v b100011 -" 0! 00" 1/" b10011 ." b0 8" b0 *" b0 6# b0 ," b0 5# b0 (# b0 '# b0 &# b0 *# 0F b1 # b1 %" b1 ^# b1 K" b11000001010000000100011 D" b0 o" b110 n" b1 m" b10 p" b0 " b0 J" b0 ]# b10100 H" b1010001100000011 C" b110 k" b0 j" b1 l" b10011 B" b10011 }" b0 g" b0 f" b0 e" b11 h" b10 d" b0 c" b110 b" b1 a" 1' b1000 b# #3400 0' #3600 b10 <" b10 v" b1 t" b1 @" b1 s" b1 r" 1l b1 ?" b1 q" 1J 1i b1 H b1 +" b1 I b1 (" b1 5" b1 2# 10 b1 $# b100110000000000000000 "# b110 ## b110 %# b110000100000000000 !# 0; b11 #" b11 [# b11111110110000110100101011100011 & b11111110110000110100101011100011 4" b11111110110000110100101011100011 a# b1000 % b1000 3" b1000 `# b1 *" b1 6# b110 ," b110 5# b1 '" b1 8# b1 )" b1 7# b1 /# b100110000 (# b110 '# b11 &# b110000 *# 1,# b0 # b0 %" b0 ^# b0 $ b0 &" b0 \# b110 $" b110 9# b1000 k b1000 Z# 1w b11 -" b100000 E" b110 g" b1 f" b110 e" b11100 F" b11000001010000000100011 A" b0 k" b0 i" b11 l" b100110000001100010011 B" b100110000001100010011 }" b11000 G" b110 o" b0 n" b1 p" b0 >" b10011 C" b1 I" b1010001100000011 D" 1' b1001 b# #3800 0' #4000 b1 <" b1 v" b0 t" 0l b0 @" b0 s" b0 p b0 w" 03 b0 5" b0 2# b1 #" b1 [# b10 I b10 (" b11 6" b11 ~" b11 4# 04 b110 $# b11000001010000000000000 "# b0 ## b0 %# b1010000000000110 !# 1. b1 "" b1 :# b0 $" b0 9# b10 k b10 Z# 0w 1v b10011 -" b10 $ b10 &" b10 \# 11 0/" b1000 m b1000 3# 1} b100011 ." b10 8" b1 ," b1 5# b110 )" b110 7# b110 /# b11000001010 (# b0 '# b0 &# b1010 *# 0,# b11 1# 00 b11011100000000010000010011 & b11011100000000010000010011 4" b11011100000000010000010011 a# b1001 % b1001 3" b1001 `# b0 I" b10011 D" b0 o" b0 m" b11 p" b1 " b1 J" b1 ]# b10 >" b11000 H" b100110000001100010011 C" b110 k" b1 j" b110 i" b11000001010000000100011 B" b11000001010000000100011 }" b11100 G" b0 g" b110 f" b1 e" b10 h" b100000 F" b11111110110000110100101011100011 A" b101 d" b10101 c" b1100 b" b110 a" b100100 E" 1' b1010 b# #4200 0' #4400 b10100 <" b10100 v" b100000 r" b100000 ?" b100000 q" b1111111111111111111111111111111111111111111111111111111111110100 t" b1111111111111111111111111111111111111111111111111111111111110100 @" b1111111111111111111111111111111111111111111111111111111111110100 s" b10 *" b10 6# b10 A# 1G b1 ;" b1 z" b11 o b11 y" b10 H b10 +" b1111111111111111111111111111111111111111111111111111111111110100 5" b1111111111111111111111111111111111111111111111111111111111110100 2# b100 6" b100 ~" b100 4# 1+ b1111111111111111111111111111111111111111111111111111111111101100 $# b1111111111111111111111111111111111111110110000110100000000000000 "# b1111111111111111111111111111111111111111111111111111111111110101 ## b1111111111111111111111111111111111111111111111111111111111110100 %# b1111111111111111111111111111111111111111111100110100011111101100 !# 1d 10 01 0} b10000 m b10000 3# 19" b1100011 ." b100 8" b110 ," b110 5# b100 '" b100 8# b1100 )" b1100 7# b1111111 7" b111111101100 /# b11111110110000110100 (# b10101 '# b1111111 .# 1-# b1010 &# b111111 0# 1+# b110100 *# b1111110110 1# 1)# b100 I b100 (" b1 # b1 %" b1 ^# b1 $ b1 &" b1 \# 1! b10 "" b10 :# b110 $" b110 9# b11 d" b0 c" b0 b" b0 a" b10101 g" b1100 f" b110 e" b101 h" b10011 A" b0 k" b110 j" b1 i" b10 l" b11111110110000110100101011100011 B" b11111110110000110100101011100011 }" b100000 G" b110 o" b1 n" b110 m" b10 " b10 J" b10 ]# b1 >" b11100 H" b11000001010000000100011 C" b10 K" b100110000001100010011 D" 1' b1011 b# #4600 0' #4800 b0 <" b0 v" b0 r" 1l b0 ?" b0 q" b0 t" b0 @" b0 s" 0G 0J b0 ;" b0 z" b0 #" b0 [# b1 :" b1 |" b1 o b1 y" b1 p b1 w" b0 H b0 +" b0 k b0 Z# 0i 13 b11 n b11 {" b0 I b0 (" b0 5" b0 2# 0d b1 6" b1 ~" b1 4# 14 0+ 0. b0 $# b0 "# b0 ## b0 %# b0 !# 00 b1 "" b1 :# b0 $" b0 9# 0v b100011 -" b10100 $ b10100 &" b10100 \# 0! 1/" b10 m b10 3# 09" b10011 ." b0 8" b0 *" b0 6# b0 ," b0 5# b0 '" b0 8# b0 )" b0 7# b0 7" b0 /# b0 (# b0 '# b0 .# 0-# b0 &# b0 0# 0+# b0 *# b0 1# 0)# b1010001100000011 & b1010001100000011 4" b1010001100000011 a# b101 % b101 3" b101 `# b0 # b0 %" b0 ^# b1 K" b1 I" b11000001010000000100011 D" b0 o" b110 n" b1 m" b10 p" b100 " b100 J" b100 ]# b10100 >" b100000 H" b11111110110000110100101011100011 C" b10101 k" b1100 j" b110 i" b101 l" b10011 B" b10011 }" b0 g" b0 f" b0 e" b11 h" b10100 E" 1' b1100 b# #5000 0' #5200 b100110000001100010011 & b100110000001100010011 4" b100110000001100010011 a# b110 % b110 3" b110 `# b0 $ b0 &" b0 \# b10101 $" b10101 9# b1100011 -" b1 d" b110 c" b1 a" b11000 E" b10100 F" b1010001100000011 A" b0 k" b0 j" b0 i" b11 l" b10101 o" b1100 n" b110 m" b101 p" b0 " b0 J" b0 ]# b0 >" b10011 C" b0 I" b11111110110000110100101011100011 D" 1' b1101 b# #5400 0' #5600 b1 <" b1 v" b1 r" 0l b1 ?" b1 q" b1 :" b1 |" b11 n b11 {" 1J b1 #" b1 [# b1 6" b1 ~" b1 4# b0 p b0 w" b10 k b10 Z# 1i b10 m b10 3# 13 b1 H b1 +" 1F 04 b1010000000000000 "# b110 ## b110 %# b1010000000000000 !# b0 $" b0 9# 1v b10011 -" 10" 0/" b11 ." b10 8" b1 *" b1 6# b1 ," b1 5# b1010 (# b110 '# b11 &# b1010 *# b11000001010000000100011 & b11000001010000000100011 4" b11000001010000000100011 a# b111 % b111 3" b111 `# b10011 D" b0 o" b0 n" b0 m" b11 p" b1010001100000011 B" b1010001100000011 }" b10100 G" b110 g" b1 e" b1 h" b11000 F" b100110000001100010011 A" b11 d" b1 b" b110 a" b11100 E" 1' b1110 b# #5800 0' #6000 b0 <" b0 v" b0 r" 1l b0 ?" b0 q" b1 p b1 w" b0 H b0 +" 14 b0 "# b0 ## b0 %# b0 !# 1; 00 0F 00" 1/" b10011 ." b0 8" b0 *" b0 6# b0 ," b0 5# b0 (# b0 '# b0 &# b0 *# b10 # b10 %" b10 ^# b1 $ b1 &" b1 \# b0 "" b0 :# b10 d" b0 c" b110 b" b1 a" b0 g" b0 f" b0 e" b11 h" b110 k" b1 i" b1 l" b10011 B" b10011 }" b1 >" b10100 H" b1010001100000011 C" b0 K" 1' b1111 b# #6200 0' #6400 b11 <" b11 v" b1 t" b1 @" b1 s" b10 r" 0l b10 ?" b10 q" b10 A# 1J 1i b10 H b10 +" b1 I b1 (" b1 5" b1 2# b11 #" b11 [# 0; b1 $# b100110000000000000000 "# b110 ## b110 %# b110000100000000000 !# 10 b10 "" b10 :# b110 $" b110 9# b1000 k b1000 Z# 1w 0v b11 -" b0 # b0 %" b0 ^# b0 $ b0 &" b0 \# b10 *" b10 6# b110 ," b110 5# b1 '" b1 8# b1 )" b1 7# b1 /# b100110000 (# b110 '# b11 &# b110000 *# 1,# b11111110110000110100101011100011 & b11111110110000110100101011100011 4" b11111110110000110100101011100011 a# b1000 % b1000 3" b1000 `# b1 K" b10 I" b1010001100000011 D" b110 o" b1 m" b1 p" b0 >" b10011 C" b0 k" b0 i" b11 l" b100110000001100010011 B" b100110000001100010011 }" b11000 G" b110 g" b1 f" b110 e" b11100 F" b11000001010000000100011 A" b100000 E" 1' b10000 b# #6600 0' #6800 b1 <" b1 v" b0 t" b0 @" b0 s" b1 r" 0l b1 ?" b1 q" b0 p b0 w" 03 b0 5" b0 2# b1 H b1 +" b11 I b11 (" 1. b11 6" b11 ~" b11 4# 04 b110 $# b11000001010000000000000 "# b0 ## b0 %# b1010000000000110 !# b1 #" b1 [# b11011100000000010000010011 & b11011100000000010000010011 4" b11011100000000010000010011 a# b1001 % b1001 3" b1001 `# 11 0/" b1000 m b1000 3# 1} b100011 ." b10 8" b1 *" b1 6# b1 ," b1 5# b10 '" b10 8# b110 )" b110 7# b110 /# b11000001010 (# b0 '# b0 &# b1010 *# 0,# b11 1# 00 b11 $ b11 &" b11 \# b1 "" b1 :# b0 $" b0 9# b10 k b10 Z# 0w 1v b10011 -" b101 d" b10101 c" b1100 b" b110 a" b100100 E" b0 g" b110 f" b1 e" b10 h" b100000 F" b11111110110000110100101011100011 A" b110 k" b1 j" b110 i" b11000001010000000100011 B" b11000001010000000100011 }" b11100 G" b0 o" b0 m" b11 p" b1 " b1 J" b1 ]# b11 >" b11000 H" b100110000001100010011 C" b0 I" b10011 D" 1' b10001 b# #7000 0' #7200 b10100 <" b10100 v" b1111111111111111111111111111111111111111111111111111111111110100 t" b1111111111111111111111111111111111111111111111111111111111110100 @" b1111111111111111111111111111111111111111111111111111111111110100 s" b100000 r" b100000 ?" b100000 q" b11 A# 1G b1 ;" b1 z" b11 o b11 y" b11 H b11 +" b1111111111111111111111111111111111111111111111111111111111110100 5" b1111111111111111111111111111111111111111111111111111111111110100 2# 1d b100 6" b100 ~" b100 4# 1+ b1111111111111111111111111111111111111111111111111111111111101100 $# b1111111111111111111111111111111111111110110000110100000000000000 "# b1111111111111111111111111111111111111111111111111111111111110101 ## b1111111111111111111111111111111111111111111111111111111111110100 %# b1111111111111111111111111111111111111111111100110100011111101100 !# b11 "" b11 :# b110 $" b110 9# 10 b100 I b100 (" b10 # b10 %" b10 ^# b1 $ b1 &" b1 \# 1! 0} b10000 m b10000 3# 19" b1100011 ." b100 8" b11 *" b11 6# b110 ," b110 5# b100 '" b100 8# b1100 )" b1100 7# b1111111 7" b111111101100 /# b11111110110000110100 (# b10101 '# b1111111 .# 1-# b1010 &# b111111 0# 1+# b110100 *# b1111110110 1# 1)# 01 b11 K" b100110000001100010011 D" b110 o" b1 n" b110 m" b11 " b11 J" b11 ]# b1 >" b11100 H" b11000001010000000100011 C" b0 k" b110 j" b1 i" b10 l" b11111110110000110100101011100011 B" b11111110110000110100101011100011 }" b100000 G" b10101 g" b1100 f" b110 e" b101 h" b10011 A" b11 d" b0 c" b0 b" b0 a" 1' b10010 b# #7400 0' #7600 b0 <" b0 v" b0 r" 1l b0 ?" b0 q" b0 t" b0 @" b0 s" 0G b0 ;" b0 z" 0J b1 :" b1 |" b1 o b1 y" b1 p b1 w" b0 #" b0 [# 13 b11 n b11 {" b0 I b0 (" b0 5" b0 2# b0 H b0 +" b0 k b0 Z# 0i 00 b1 6" b1 ~" b1 4# 14 0+ 0. b0 $# b0 "# b0 ## b0 %# b0 !# 0d b1010001100000011 & b1010001100000011 4" b1010001100000011 a# b101 % b101 3" b101 `# 1/" b10 m b10 3# 09" b10011 ." b0 8" b0 *" b0 6# b0 ," b0 5# b0 '" b0 8# b0 )" b0 7# b0 7" b0 /# b0 (# b0 '# b0 .# 0-# b0 &# b0 0# 0+# b0 *# b0 1# 0)# b10100 $ b10100 &" b10100 \# 0! b1 "" b1 :# b0 $" b0 9# 0v b100011 -" b10100 E" b0 g" b0 f" b0 e" b11 h" b10101 k" b1100 j" b110 i" b101 l" b10011 B" b10011 }" b0 o" b110 n" b1 m" b10 p" b100 " b100 J" b100 ]# b10100 >" b100000 H" b11111110110000110100101011100011 C" b1 K" b10 I" b11000001010000000100011 D" b0 # b0 %" b0 ^# 1' b10011 b# #7800 0' #8000 b10101 $" b10101 9# b1100011 -" b0 $ b0 &" b0 \# b100110000001100010011 & b100110000001100010011 4" b100110000001100010011 a# b110 % b110 3" b110 `# b0 I" b11111110110000110100101011100011 D" b10101 o" b1100 n" b110 m" b101 p" b0 " b0 J" b0 ]# b0 >" b10011 C" b0 k" b0 j" b0 i" b11 l" b10100 F" b1010001100000011 A" b1 d" b110 c" b1 a" b11000 E" 1' b10100 b# #8200 0' #8400 b1 <" b1 v" b1 r" 0l b1 ?" b1 q" b1 :" b1 |" b11 n b11 {" 1J 1F b1 6" b1 ~" b1 4# b0 p b0 w" b1 #" b1 [# b10 m b10 3# 13 b1 H b1 +" b10 k b10 Z# 1i 04 b1010000000000000 "# b110 ## b110 %# b1010000000000000 !# b11000001010000000100011 & b11000001010000000100011 4" b11000001010000000100011 a# b111 % b111 3" b111 `# 10" 0/" b11 ." b10 8" b1 *" b1 6# b1 ," b1 5# b1010 (# b110 '# b11 &# b1010 *# b0 $" b0 9# 1v b10011 -" b11 d" b1 b" b110 a" b11100 E" b110 g" b1 e" b1 h" b11000 F" b100110000001100010011 A" b1010001100000011 B" b1010001100000011 }" b10100 G" b0 o" b0 n" b0 m" b11 p" b10011 D" 1' b10101 b# #8600 0' #8800 b0 <" b0 v" b0 r" 1l b0 ?" b0 q" b1 p b1 w" b0 H b0 +" 1; 14 b0 "# b0 ## b0 %# b0 !# b0 "" b0 :# b11 # b11 %" b11 ^# b1 $ b1 &" b1 \# 00" 1/" b10011 ." b0 8" b0 *" b0 6# b0 ," b0 5# b0 (# b0 '# b0 &# b0 *# 00 0F b0 K" b1 >" b10100 H" b1010001100000011 C" b110 k" b1 i" b1 l" b10011 B" b10011 }" b0 g" b0 f" b0 e" b11 h" b10 d" b0 c" b110 b" b1 a" 1' b10110 b# #9000 0' #9200 b100 <" b100 v" b1 t" b1 @" b1 s" b11 r" 0l b11 ?" b11 q" b11 A# 1J b11 H b11 +" b1 I b1 (" b1 5" b1 2# 1i 10 b1 $# b100110000000000000000 "# b110 ## b110 %# b110000100000000000 !# 0; b11 #" b11 [# b11111110110000110100101011100011 & b11111110110000110100101011100011 4" b11111110110000110100101011100011 a# b1000 % b1000 3" b1000 `# b11 *" b11 6# b110 ," b110 5# b1 '" b1 8# b1 )" b1 7# b1 /# b100110000 (# b110 '# b11 &# b110000 *# 1,# b0 # b0 %" b0 ^# b0 $ b0 &" b0 \# b11 "" b11 :# b110 $" b110 9# b1000 k b1000 Z# 1w 0v b11 -" b100000 E" b110 g" b1 f" b110 e" b11100 F" b11000001010000000100011 A" b0 k" b0 i" b11 l" b100110000001100010011 B" b100110000001100010011 }" b11000 G" b110 o" b1 m" b1 p" b0 >" b10011 C" b1 K" b11 I" b1010001100000011 D" 1' b10111 b# #9400 0' #9600 b1 <" b1 v" b0 t" b0 @" b0 s" b1 r" 0l b1 ?" b1 q" b0 p b0 w" 03 b0 5" b0 2# b1 H b1 +" b1 #" b1 [# b100 I b100 (" b11 6" b11 ~" b11 4# 04 b110 $# b11000001010000000000000 "# b0 ## b0 %# b1010000000000110 !# 1. b1 "" b1 :# b0 $" b0 9# b10 k b10 Z# 0w 1v b10011 -" b100 $ b100 &" b100 \# 11 0/" b1000 m b1000 3# 1} b100011 ." b10 8" b1 *" b1 6# b1 ," b1 5# b11 '" b11 8# b110 )" b110 7# b110 /# b11000001010 (# b0 '# b0 &# b1010 *# 0,# b11 1# 00 b11011100000000010000010011 & b11011100000000010000010011 4" b11011100000000010000010011 a# b1001 % b1001 3" b1001 `# b0 I" b10011 D" b0 o" b0 m" b11 p" b1 " b1 J" b1 ]# b100 >" b11000 H" b100110000001100010011 C" b110 k" b1 j" b110 i" b11000001010000000100011 B" b11000001010000000100011 }" b11100 G" b0 g" b110 f" b1 e" b10 h" b100000 F" b11111110110000110100101011100011 A" b101 d" b10101 c" b1100 b" b110 a" b100100 E" 1' b11000 b# #9800 0' #10000 b10100 <" b10100 v" b1111111111111111111111111111111111111111111111111111111111110100 t" b1111111111111111111111111111111111111111111111111111111111110100 @" b1111111111111111111111111111111111111111111111111111111111110100 s" b100000 r" b100000 ?" b100000 q" b100 A# b1 ;" b1 z" b11 o b11 y" b100 H b100 +" b1111111111111111111111111111111111111111111111111111111111110100 5" b1111111111111111111111111111111111111111111111111111111111110100 2# b100 6" b100 ~" b100 4# 1+ b1111111111111111111111111111111111111111111111111111111111101100 $# b1111111111111111111111111111111111111110110000110100000000000000 "# b1111111111111111111111111111111111111111111111111111111111110101 ## b1111111111111111111111111111111111111111111111111111111111110100 %# b1111111111111111111111111111111111111111111100110100011111101100 !# 1d 10 01 0} b10000 m b10000 3# 19" b1100011 ." b100 8" b100 *" b100 6# b110 ," b110 5# b100 '" b100 8# b1100 )" b1100 7# b1111111 7" b111111101100 /# b11111110110000110100 (# b10101 '# b1111111 .# 1-# b1010 &# b111111 0# 1+# b110100 *# b1111110110 1# 1)# b100 I b100 (" b11 # b11 %" b11 ^# b1 $ b1 &" b1 \# 1! b100 "" b100 :# b110 $" b110 9# b11 d" b0 c" b0 b" b0 a" b10101 g" b1100 f" b110 e" b101 h" b10011 A" b0 k" b110 j" b1 i" b10 l" b11111110110000110100101011100011 B" b11111110110000110100101011100011 }" b100000 G" b110 o" b1 n" b110 m" b100 " b100 J" b100 ]# b1 >" b11100 H" b11000001010000000100011 C" b100 K" b100110000001100010011 D" 1' b11001 b# #10200 0' #10400 b0 <" b0 v" b0 r" 1l b0 ?" b0 q" b0 t" b0 @" b0 s" 0J b0 ;" b0 z" b0 #" b0 [# b1 :" b1 |" b1 o b1 y" b1 p b1 w" b0 H b0 +" b0 k b0 Z# 0i 13 b11 n b11 {" b0 I b0 (" b0 5" b0 2# 0d b1 6" b1 ~" b1 4# 14 0+ 0. b0 $# b0 "# b0 ## b0 %# b0 !# 00 b1 "" b1 :# b0 $" b0 9# 0v b100011 -" b10100 $ b10100 &" b10100 \# 0! 1/" b10 m b10 3# 09" b10011 ." b0 8" b0 *" b0 6# b0 ," b0 5# b0 '" b0 8# b0 )" b0 7# b0 7" b0 /# b0 (# b0 '# b0 .# 0-# b0 &# b0 0# 0+# b0 *# b0 1# 0)# b0 # b0 %" b0 ^# b1 K" b11 I" b11000001010000000100011 D" b0 o" b110 n" b1 m" b10 p" b10100 >" b100000 H" b11111110110000110100101011100011 C" b10101 k" b1100 j" b110 i" b101 l" b10011 B" b10011 }" b0 g" b0 f" b0 e" b11 h" 1' b11010 b# #10600 0' #10800 b100000000000010000110011 & b100000000000010000110011 4" b100000000000010000110011 a# b1010 % b1010 3" b1010 `# b0 $ b0 &" b0 \# b10101 $" b10101 9# b1100011 -" b1000 c" b10111 b" b101000 E" b100100 F" b11011100000000010000010011 A" b0 k" b0 j" b0 i" b11 l" b10101 o" b1100 n" b110 m" b101 p" b0 " b0 J" b0 ]# b0 >" b10011 C" b0 I" b11111110110000110100101011100011 D" 1' b11011 b# #11000 0' #11200 b110111 <" b110111 v" b110111 t" 0l b110111 @" b110111 s" 1J b1 #" b1 [# b10 k b10 Z# 1i b110111 5" b110111 2# b110111 $# b11011100000000000000000000 "# b101000 ## b101000 %# b100000110110 !# b0 $" b0 9# 1v b10011 -" b10111 )" b10111 7# b1 7" b110111 /# b11011100000000 (# b1000 '# b1 .# b100 &# b1 0# 1,# b11011 1# b101000000010000010011 & b101000000010000010011 4" b101000000010000010011 a# b1011 % b1011 3" b1011 `# b10011 D" b0 o" b0 n" b0 m" b11 p" b11011100000000010000010011 B" b11011100000000010000010011 }" b100100 G" b1000 g" b10111 f" b101000 F" b100000000000010000110011 A" b0 d" b1000 b" b101100 E" 1' b11100 b# #11400 0' #11600 0l b110111 t" b110111 @" b110111 s" b0 :" b0 |" b1 n b1 {" b1 p b1 w" b0 6" b0 ~" b0 4# 1K b0 m b0 3# 03 b0 5" b0 2# b110111 I b110111 (" 04 b1000 $# b100000000000000000000000 "# b1000 ## b1000 %# b1000 !# b10011 & b10011 4" b10011 a# b1100 % b1100 3" b1100 `# 11 1!" 0/" b110011 ." b1000 )" b1000 7# b0 7" b1000 /# b100000000000 (# b0 .# b0 0# 0,# b100 1# b110111 $ b110111 &" b110111 \# b0 "" b0 :# b11 d" b1 b" b1000 a" b110000 E" b1000 f" b0 h" b101100 F" b101000000010000010011 A" b1000 k" b10111 j" b100000000000010000110011 B" b100000000000010000110011 }" b101000 G" b110111 >" b100100 H" b11011100000000010000010011 C" b0 K" 1' b11101 b# #11800 0' #12000 b111000 <" b111000 v" b1 t" b1 @" b1 s" b110111 r" 0l b110111 ?" b110111 q" b110111 *" b110111 6# b110111 C# b1 :" b1 |" b11 n b11 {" b1 5" b1 2# b1 6" b1 ~" b1 4# 0K b10 m b10 3# 13 b110111 H b110111 +" 14 b1 $# b101000000000000000000 "# b1000000100000000000 !# b1 I b1 (" 1/ 10 b110111 "" b110111 :# b1000 $" b1000 9# 0!" 1/" b10011 ." b1000 ," b1000 5# b1 '" b1 8# b1 )" b1 7# b1 /# b101000000 (# b1000000 *# 1,# b0 1# 01 bx & bx 4" bx a# b1101 % b1101 3" b1101 `# b110111 K" b11011100000000010000010011 D" b1000 o" b10111 n" b110111 " b110111 J" b110111 ]# b101000 H" b100000000000010000110011 C" b1000 j" b0 l" b101000000010000010011 B" b101000000010000010011 }" b101100 G" b1 f" b1000 e" b11 h" b110000 F" b10011 A" b0 c" b0 b" b0 a" b110100 E" 1' b11110 b# #12200 0' #12400 b0 <" b0 v" b0 t" 1l b0 @" b0 s" b0 r" b0 ?" b0 q" b1 #" b1 [# b0 I b0 (" b0 5" b0 2# b10 k b10 Z# 0i x. b0 $# b0 "# b0 ## b0 %# b0 !# b1110 % b1110 3" b1110 `# 0/ 00 b0 *" b0 6# b0 ," b0 5# b0 '" b0 8# b0 )" b0 7# b0 /# b0 (# b0 '# b0 &# b0 *# 0,# b0 H b0 +" b111000 $ b111000 &" b111000 \# 1u 0v b110011 -" bx c" bx b" bx a" b111000 E" b0 g" b0 f" b0 e" b110100 F" bx A" b1 j" b1000 i" b11 l" b10011 B" b10011 }" b110000 G" b1000 n" b0 p" b1 " b1 J" b1 ]# b111000 >" b101100 H" b101000000010000010011 C" b100000000000010000110011 D" 1' b11111 b# #12600 0' #12800 b0x <" b0x v" bx0 t" xl bx0 @" bx0 s" b111000 C# b0x1 n b0x1 {" b1101 =" b1101 u" b1101 x" 1i x3 xK x^ xV xX xY x` x\ xZ xS xM xP xQ xT xN xL x_ xW x] x[ xR xO xU x= xC xA b0xxxxxxxxxxxxxx p b0xxxxxxxxxxxxxx w" x> xD xB bx I bx (" bx0 5" bx0 2# bx H bx +" b10 ;" b10 z" b101 6" b101 ~" b101 4# xG xe x4 x? x@ xE x< x6 x5 x( x- x+ x) x, x* bx $# bx000000000000 "# bx ## bx0 %# bx0 !# x/ x0 b111000 "" b111000 :# 0u 1v b10011 -" b0 $ b0 &" b0 \# x!" x~ x0" x/" x2" x7 x1" x} x9" b0xx1 o b0xx1 y" xh xz b0xxxxx0 m b0xxxxx0 3# xg x{ xf x| bx ." bx 8" bx *" bx 6# bx ," bx 5# bx '" bx 8# bx )" bx 7# bx 7" bx /# bx (# bx '# bx .# x-# bx &# bx 0# x+# bx *# x,# bx 1# x)# b1111 % b1111 3" b1111 `# b111000 K" b101000000010000010011 D" b1 n" b1000 m" b11 p" b0 " b0 J" b0 ]# b0 >" b110000 H" b10011 C" b0 k" b0 j" b0 i" bx B" bx }" b110100 G" bx g" bx f" bx e" b111000 F" b111100 E" 1' b100000 b# #13000 0' #13200 x8 x: x; x9 xa xc xd xb b10000 % b10000 3" b10000 `# bx # bx %" bx ^# b0x $ b0x &" b0x \# x! b0 "" b0 :# b0 $" b0 9# b1000000 E" b111100 F" bx k" bx j" bx i" b111000 G" b0 o" b0 n" b0 m" bx " bx J" bx ]# b0x >" b110100 H" bx C" b0 K" b10011 D" 1' b100001 b# #13400 0' #13600 xJ xi b11 #" b11 [# xj bx "" bx :# bx $" bx 9# xu xt bx0 k bx0 Z# xw xv xy xx xq xr xs bx -" b10001 % b10001 3" b10001 `# b0x K" bx I" bx D" bx o" bx n" bx m" b111000 H" b111100 G" b1000000 F" b1000100 E" 1' b100010 b# #13800 0' #14000 b10010 % b10010 3" b10010 `# b1001000 E" b1000100 F" b1000000 G" b111100 H" 1' b100011 b# #14200 0' #14400 b10011 % b10011 3" b10011 `# b1000000 H" b1000100 G" b1001000 F" b1001100 E" 1' b100100 b# #14600 0' #14800 b10100 % b10100 3" b10100 `# b1010000 E" b1001100 F" b1001000 G" b1000100 H" 1' b100101 b# #15000 0' #15200 b10101 % b10101 3" b10101 `# b1001000 H" b1001100 G" b1010000 F" b1010100 E" 1' b100110 b# #15400 0' #15600 b10110 % b10110 3" b10110 `# b1011000 E" b1010100 F" b1010000 G" b1001100 H" 1' b100111 b# #15800 0' #16000 b101000 b# ================================================ FILE: testbench/vcd/ram.vcd ================================================ $date Mon May 24 15:33:45 2021 $end $version Icarus Verilog $end $timescale 100ps $end $scope module tb_RAM $end $var wire 64 ! DATA_OUT [63:0] $end $var reg 10 " ADDRESS [9:0] $end $var reg 1 # CLK $end $var reg 64 $ DATA_IN [63:0] $end $var reg 1 % WRITE_ENABLE $end $scope module ram $end $var wire 10 & ADDRESS [9:0] $end $var wire 1 # CLK $end $var wire 64 ' DATA_IN [63:0] $end $var wire 64 ( DATA_OUT [63:0] $end $var wire 1 % WRITE_ENABLE $end $scope begin $ivl_for_loop0 $end $var integer 32 ) i [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b10000000000 ) b110111 ( b110111 ' b1 & 1% b110111 $ 1# b1 " b110111 ! $end #200 0# #400 1# b1100011 $ b1100011 ' b1100011 ! b1100011 ( b10 " b10 & #600 0# #800 1# b0 $ b0 ' 0% b110111 ! b110111 ( b1 " b1 & #1000 0# #1200 1# b1100011 ! b1100011 ( b10 " b10 & #1400 0# #1600 ================================================ FILE: testbench/vcd/regfile.vcd ================================================ $date Mon May 24 15:33:45 2021 $end $version Icarus Verilog $end $timescale 100ps $end $scope module tb_RegFile $end $var wire 64 ! R2_data [63:0] $end $var wire 64 " R1_data [63:0] $end $var reg 5 # R1 [4:0] $end $var reg 5 $ R2 [4:0] $end $var reg 5 % RD [4:0] $end $var reg 64 & RD_DATA [63:0] $end $var reg 1 ' reg_write_enable $end $scope module regfile $end $var wire 5 ( R1 [4:0] $end $var wire 64 ) R1_DATA [63:0] $end $var wire 5 * R2 [4:0] $end $var wire 64 + R2_DATA [63:0] $end $var wire 5 , RD [4:0] $end $var wire 64 - RD_DATA [63:0] $end $var wire 1 ' WRITE_ENABLE $end $var integer 32 . i [31:0] $end $scope begin REG_DATAS[1] $end $var wire 64 / R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[2] $end $var wire 64 0 R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[3] $end $var wire 64 1 R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[4] $end $var wire 64 2 R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[5] $end $var wire 64 3 R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[6] $end $var wire 64 4 R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[7] $end $var wire 64 5 R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[8] $end $var wire 64 6 R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[9] $end $var wire 64 7 R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[10] $end $var wire 64 8 R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[11] $end $var wire 64 9 R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[12] $end $var wire 64 : R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[13] $end $var wire 64 ; R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[14] $end $var wire 64 < R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[15] $end $var wire 64 = R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[16] $end $var wire 64 > R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[17] $end $var wire 64 ? R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[18] $end $var wire 64 @ R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[19] $end $var wire 64 A R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[20] $end $var wire 64 B R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[21] $end $var wire 64 C R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[22] $end $var wire 64 D R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[23] $end $var wire 64 E R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[24] $end $var wire 64 F R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[25] $end $var wire 64 G R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[26] $end $var wire 64 H R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[27] $end $var wire 64 I R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[28] $end $var wire 64 J R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[29] $end $var wire 64 K R_DATA [63:0] $end $upscope $end $scope begin REG_DATAS[30] $end $var wire 64 L R_DATA [63:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b0 L b0 K b0 J b0 I b0 H b0 G b0 F b0 E b0 D b0 C b0 B b0 A b0 @ b0 ? b0 > b0 = b0 < b0 ; b0 : b0 9 b0 8 b0 7 b0 6 b0 5 b0 4 b0 3 b0 2 b0 1 b0 0 b0 / b100000 . b0 - b0 , b0 + b0 * b0 ) b0 ( 0' b0 & b0 % b0 $ b0 # b0 " b0 ! $end #200 b101 / 1' b101 & b101 - b1 % b1 , #400 b1010 0 b1010 & b1010 - b10 % b10 , b101 " b101 ) b1 # b1 ( #600 0' b0 & b0 - b0 % b0 , b1010 ! b1010 + b10 $ b10 * #800 ================================================ FILE: testbench/vcd/rom.vcd ================================================ $date Mon May 24 15:33:45 2021 $end $version Icarus Verilog $end $timescale 100ps $end $scope module tb_ROM $end $var wire 32 ! DATA_OUT [31:0] $end $var reg 10 " ADDRESS [9:0] $end $scope module rom $end $var wire 10 # ADDRESS [9:0] $end $var wire 32 $ DATA [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b10011 $ b0 # b0 " b10011 ! $end #200 b100000000000010010011 ! b100000000000010010011 $ b1 " b1 # #400 b100000000001100010011 ! b100000000001100010011 $ b10 " b10 # #600 b10000000000011000010011 ! b10000000000011000010011 $ b11 " b11 # #800 b11000001010000000100011 ! b11000001010000000100011 $ b100 " b100 # #1000 b1010001100000011 ! b1010001100000011 $ b101 " b101 # #1200 bx ! bx $ b10100 " b10100 # #1400